, q : UInt<1>} \n\n\n node _output_T = asAsyncReset(reset) \n node _output_T_1 = bits(io.d, 0, 0) \n inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_14 \n connect output_chain.clock, clock\n\n connect output_chain.reset, _output_T\n\n connect output_chain.io.d, _output_T_1 \n wire output_0 : UInt<1> \n connect output_0, output_chain.io.q \n connect io.q, output_0"},"response":{"kind":"string","value":"module AsyncResetSynchronizerShiftReg_w1_d3_i0_14(\t// @[SynchronizerReg.scala:80:7]\n input clock,\t// @[SynchronizerReg.scala:80:7]\n input reset,\t// @[SynchronizerReg.scala:80:7]\n input io_d,\t// @[ShiftReg.scala:36:14]\n output io_q\t// @[ShiftReg.scala:36:14]\n);\n\n wire io_d_0 = io_d;\t// @[SynchronizerReg.scala:80:7]\n wire _output_T = reset;\t// @[SynchronizerReg.scala:86:21]\n wire _output_T_1 = io_d_0;\t// @[SynchronizerReg.scala:80:7, :87:41]\n wire output_0;\t// @[ShiftReg.scala:48:24]\n wire io_q_0;\t// @[SynchronizerReg.scala:80:7]\n assign io_q_0 = output_0;\t// @[SynchronizerReg.scala:80:7]\n AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_14 output_chain (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (_output_T),\t// @[SynchronizerReg.scala:86:21]\n .io_d (_output_T_1),\t// @[SynchronizerReg.scala:87:41]\n .io_q (output_0)\n );\t// @[ShiftReg.scala:45:23]\n assign io_q = io_q_0;\t// @[SynchronizerReg.scala:80:7]\nendmodule"}}},{"rowIdx":34184,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module TLSlaveBEToNoC : \n input clock : Clock \n input reset : Reset \n output io : { tilelink : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flits : { b : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}, flip e : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}} \n\n\n invalidate io.tilelink.e.bits.sink \n invalidate io.tilelink.e.valid \n invalidate io.tilelink.e.ready \n invalidate io.tilelink.d.bits.corrupt \n invalidate io.tilelink.d.bits.data \n invalidate io.tilelink.d.bits.denied \n invalidate io.tilelink.d.bits.sink \n invalidate io.tilelink.d.bits.source \n invalidate io.tilelink.d.bits.size \n invalidate io.tilelink.d.bits.param \n invalidate io.tilelink.d.bits.opcode \n invalidate io.tilelink.d.valid \n invalidate io.tilelink.d.ready \n invalidate io.tilelink.c.bits.corrupt \n invalidate io.tilelink.c.bits.data \n invalidate io.tilelink.c.bits.address \n invalidate io.tilelink.c.bits.source \n invalidate io.tilelink.c.bits.size \n invalidate io.tilelink.c.bits.param \n invalidate io.tilelink.c.bits.opcode \n invalidate io.tilelink.c.valid \n invalidate io.tilelink.c.ready \n invalidate io.tilelink.b.bits.corrupt \n invalidate io.tilelink.b.bits.data \n invalidate io.tilelink.b.bits.mask \n invalidate io.tilelink.b.bits.address \n invalidate io.tilelink.b.bits.source \n invalidate io.tilelink.b.bits.size \n invalidate io.tilelink.b.bits.param \n invalidate io.tilelink.b.bits.opcode \n invalidate io.tilelink.b.valid \n invalidate io.tilelink.b.ready \n invalidate io.tilelink.a.bits.corrupt \n invalidate io.tilelink.a.bits.data \n invalidate io.tilelink.a.bits.mask \n invalidate io.tilelink.a.bits.address \n invalidate io.tilelink.a.bits.source \n invalidate io.tilelink.a.bits.size \n invalidate io.tilelink.a.bits.param \n invalidate io.tilelink.a.bits.opcode \n invalidate io.tilelink.a.valid \n invalidate io.tilelink.a.ready \n inst b of TLBToNoC \n connect b.clock, clock\n\n connect b.reset, reset\n\n inst e of TLEFromNoC \n connect e.clock, clock\n\n connect e.reset, reset\n\n connect b.io.protocol, io.tilelink.b \n connect io.tilelink.e.bits, e.io.protocol.bits \n connect io.tilelink.e.valid, e.io.protocol.valid \n connect e.io.protocol.ready, io.tilelink.e.ready \n connect io.flits.b.bits, b.io.flit.bits \n connect io.flits.b.valid, b.io.flit.valid \n connect b.io.flit.ready, io.flits.b.ready \n connect e.io.flit, io.flits.e"},"response":{"kind":"string","value":"module TLSlaveBEToNoC(\t// @[Tilelink.scala:189:7]\n input clock,\t// @[Tilelink.scala:189:7]\n input reset,\t// @[Tilelink.scala:189:7]\n input io_flits_b_ready,\t// @[Tilelink.scala:196:14]\n output io_flits_b_valid,\t// @[Tilelink.scala:196:14]\n output io_flits_b_bits_head,\t// @[Tilelink.scala:196:14]\n output io_flits_b_bits_tail,\t// @[Tilelink.scala:196:14]\n output [72:0] io_flits_b_bits_payload,\t// @[Tilelink.scala:196:14]\n output [3:0] io_flits_b_bits_egress_id,\t// @[Tilelink.scala:196:14]\n output io_flits_e_ready,\t// @[Tilelink.scala:196:14]\n input io_flits_e_valid,\t// @[Tilelink.scala:196:14]\n input io_flits_e_bits_head,\t// @[Tilelink.scala:196:14]\n input io_flits_e_bits_tail\t// @[Tilelink.scala:196:14]\n);\n\n TLBToNoC b (\t// @[Tilelink.scala:204:17]\n .clock (clock),\n .reset (reset),\n .io_flit_ready (io_flits_b_ready),\n .io_flit_valid (io_flits_b_valid),\n .io_flit_bits_head (io_flits_b_bits_head),\n .io_flit_bits_tail (io_flits_b_bits_tail),\n .io_flit_bits_payload (io_flits_b_bits_payload),\n .io_flit_bits_egress_id (io_flits_b_bits_egress_id)\n );\t// @[Tilelink.scala:204:17]\n TLEFromNoC e (\t// @[Tilelink.scala:205:17]\n .clock (clock),\n .reset (reset),\n .io_flit_ready (io_flits_e_ready),\n .io_flit_valid (io_flits_e_valid),\n .io_flit_bits_head (io_flits_e_bits_head),\n .io_flit_bits_tail (io_flits_e_bits_tail)\n );\t// @[Tilelink.scala:205:17]\nendmodule"}}},{"rowIdx":34185,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module Router : \n input clock : Clock \n input reset : Reset \n output auto : { debug_out : { va_stall : UInt[3], sa_stall : UInt[3]}, egress_nodes_out : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, flip ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<6>, flip vc_free : UInt<6>}, flip dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<6>, flip vc_free : UInt<6>}} \n\n\n wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<6>, flip vc_free : UInt<6>} \n invalidate destNodesIn.vc_free \n invalidate destNodesIn.credit_return \n invalidate destNodesIn.flit[0].bits.virt_channel_id \n invalidate destNodesIn.flit[0].bits.flow.egress_node_id \n invalidate destNodesIn.flit[0].bits.flow.egress_node \n invalidate destNodesIn.flit[0].bits.flow.ingress_node_id \n invalidate destNodesIn.flit[0].bits.flow.ingress_node \n invalidate destNodesIn.flit[0].bits.flow.vnet_id \n invalidate destNodesIn.flit[0].bits.payload \n invalidate destNodesIn.flit[0].bits.tail \n invalidate destNodesIn.flit[0].bits.head \n invalidate destNodesIn.flit[0].valid \n inst monitor of NoCMonitor \n connect monitor.clock, clock\n\n connect monitor.reset, reset\n\n connect monitor.io.in.vc_free, destNodesIn.vc_free \n connect monitor.io.in.credit_return, destNodesIn.credit_return \n connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id \n connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id \n connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node \n connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id \n connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node \n connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id \n connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload \n connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail \n connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head \n connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid \n wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<6>, flip vc_free : UInt<6>} \n invalidate sourceNodesOut.vc_free \n invalidate sourceNodesOut.credit_return \n invalidate sourceNodesOut.flit[0].bits.virt_channel_id \n invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id \n invalidate sourceNodesOut.flit[0].bits.flow.egress_node \n invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id \n invalidate sourceNodesOut.flit[0].bits.flow.ingress_node \n invalidate sourceNodesOut.flit[0].bits.flow.vnet_id \n invalidate sourceNodesOut.flit[0].bits.payload \n invalidate sourceNodesOut.flit[0].bits.tail \n invalidate sourceNodesOut.flit[0].bits.head \n invalidate sourceNodesOut.flit[0].valid \n wire ingressNodesIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} \n invalidate ingressNodesIn.flit.bits.egress_id \n invalidate ingressNodesIn.flit.bits.payload \n invalidate ingressNodesIn.flit.bits.tail \n invalidate ingressNodesIn.flit.bits.head \n invalidate ingressNodesIn.flit.valid \n invalidate ingressNodesIn.flit.ready \n wire ingressNodesIn_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} \n invalidate ingressNodesIn_1.flit.bits.egress_id \n invalidate ingressNodesIn_1.flit.bits.payload \n invalidate ingressNodesIn_1.flit.bits.tail \n invalidate ingressNodesIn_1.flit.bits.head \n invalidate ingressNodesIn_1.flit.valid \n invalidate ingressNodesIn_1.flit.ready \n wire egressNodesOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} \n invalidate egressNodesOut.flit.bits.ingress_id \n invalidate egressNodesOut.flit.bits.payload \n invalidate egressNodesOut.flit.bits.tail \n invalidate egressNodesOut.flit.bits.head \n invalidate egressNodesOut.flit.valid \n invalidate egressNodesOut.flit.ready \n wire debugNodeOut : { va_stall : UInt[3], sa_stall : UInt[3]} \n invalidate debugNodeOut.sa_stall[0] \n invalidate debugNodeOut.sa_stall[1] \n invalidate debugNodeOut.sa_stall[2] \n invalidate debugNodeOut.va_stall[0] \n invalidate debugNodeOut.va_stall[1] \n invalidate debugNodeOut.va_stall[2] \n connect destNodesIn, auto.dest_nodes_in \n connect auto.source_nodes_out, sourceNodesOut \n connect ingressNodesIn, auto.ingress_nodes_in_0 \n connect ingressNodesIn_1, auto.ingress_nodes_in_1 \n connect auto.egress_nodes_out, egressNodesOut \n connect auto.debug_out, debugNodeOut \n inst input_unit_0_from_12 of InputUnit \n connect input_unit_0_from_12.clock, clock\n\n connect input_unit_0_from_12.reset, reset\n\n inst ingress_unit_1_from_2 of IngressUnit \n connect ingress_unit_1_from_2.clock, clock\n\n connect ingress_unit_1_from_2.reset, reset\n\n inst ingress_unit_2_from_3 of IngressUnit_1 \n connect ingress_unit_2_from_3.clock, clock\n\n connect ingress_unit_2_from_3.reset, reset\n\n inst output_unit_0_to_1 of OutputUnit \n connect output_unit_0_to_1.clock, clock\n\n connect output_unit_0_to_1.reset, reset\n\n inst egress_unit_1_to_1 of EgressUnit \n connect egress_unit_1_to_1.clock, clock\n\n connect egress_unit_1_to_1.reset, reset\n\n inst switch of Switch \n connect switch.clock, clock\n\n connect switch.reset, reset\n\n inst switch_allocator of SwitchAllocator \n connect switch_allocator.clock, clock\n\n connect switch_allocator.reset, reset\n\n inst vc_allocator of RotatingSingleVCAllocator \n connect vc_allocator.clock, clock\n\n connect vc_allocator.reset, reset\n\n inst route_computer of RouteComputer \n connect route_computer.clock, clock\n\n connect route_computer.reset, reset\n\n node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid) \n node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid) \n node _fires_count_T_2 = and(vc_allocator.io.req.`2`.ready, vc_allocator.io.req.`2`.valid) \n node _fires_count_T_3 = add(_fires_count_T_1, _fires_count_T_2) \n node _fires_count_T_4 = bits(_fires_count_T_3, 1, 0) \n node _fires_count_T_5 = add(_fires_count_T, _fires_count_T_4) \n node _fires_count_T_6 = bits(_fires_count_T_5, 1, 0) \n wire fires_count : UInt \n connect fires_count, _fires_count_T_6 \n connect input_unit_0_from_12.io.in, destNodesIn \n connect ingress_unit_1_from_2.io.in, ingressNodesIn.flit \n connect ingress_unit_2_from_3.io.in, ingressNodesIn_1.flit \n connect output_unit_0_to_1.io.out.vc_free, sourceNodesOut.vc_free \n connect output_unit_0_to_1.io.out.credit_return, sourceNodesOut.credit_return \n connect sourceNodesOut.flit, output_unit_0_to_1.io.out.flit \n connect egressNodesOut.flit.bits, egress_unit_1_to_1.io.out.bits \n connect egressNodesOut.flit.valid, egress_unit_1_to_1.io.out.valid \n connect egress_unit_1_to_1.io.out.ready, egressNodesOut.flit.ready \n connect route_computer.io.req.`0`, input_unit_0_from_12.io.router_req \n connect route_computer.io.req.`1`, ingress_unit_1_from_2.io.router_req \n connect route_computer.io.req.`2`, ingress_unit_2_from_3.io.router_req \n connect input_unit_0_from_12.io.router_resp, route_computer.io.resp.`0` \n connect ingress_unit_1_from_2.io.router_resp, route_computer.io.resp.`1` \n connect ingress_unit_2_from_3.io.router_resp, route_computer.io.resp.`2` \n connect vc_allocator.io.req.`0`, input_unit_0_from_12.io.vcalloc_req \n connect vc_allocator.io.req.`1`, ingress_unit_1_from_2.io.vcalloc_req \n connect vc_allocator.io.req.`2`, ingress_unit_2_from_3.io.vcalloc_req \n connect input_unit_0_from_12.io.vcalloc_resp, vc_allocator.io.resp.`0` \n connect ingress_unit_1_from_2.io.vcalloc_resp, vc_allocator.io.resp.`1` \n connect ingress_unit_2_from_3.io.vcalloc_resp, vc_allocator.io.resp.`2` \n connect output_unit_0_to_1.io.allocs, vc_allocator.io.out_allocs.`0` \n connect egress_unit_1_to_1.io.allocs, vc_allocator.io.out_allocs.`1` \n connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_1.io.channel_status[0].flow.egress_node_id \n connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_1.io.channel_status[0].flow.egress_node \n connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_1.io.channel_status[0].flow.ingress_node_id \n connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_1.io.channel_status[0].flow.ingress_node \n connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_1.io.channel_status[0].flow.vnet_id \n connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_1.io.channel_status[0].occupied \n connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_1.io.channel_status[1].flow.egress_node_id \n connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_1.io.channel_status[1].flow.egress_node \n connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_1.io.channel_status[1].flow.ingress_node_id \n connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_1.io.channel_status[1].flow.ingress_node \n connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_1.io.channel_status[1].flow.vnet_id \n connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_1.io.channel_status[1].occupied \n connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_1.io.channel_status[2].flow.egress_node_id \n connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_1.io.channel_status[2].flow.egress_node \n connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_1.io.channel_status[2].flow.ingress_node_id \n connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_1.io.channel_status[2].flow.ingress_node \n connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_1.io.channel_status[2].flow.vnet_id \n connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_1.io.channel_status[2].occupied \n connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_1.io.channel_status[3].flow.egress_node_id \n connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_1.io.channel_status[3].flow.egress_node \n connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_1.io.channel_status[3].flow.ingress_node_id \n connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_1.io.channel_status[3].flow.ingress_node \n connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_1.io.channel_status[3].flow.vnet_id \n connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_1.io.channel_status[3].occupied \n connect vc_allocator.io.channel_status.`0`[4].flow.egress_node_id, output_unit_0_to_1.io.channel_status[4].flow.egress_node_id \n connect vc_allocator.io.channel_status.`0`[4].flow.egress_node, output_unit_0_to_1.io.channel_status[4].flow.egress_node \n connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node_id, output_unit_0_to_1.io.channel_status[4].flow.ingress_node_id \n connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node, output_unit_0_to_1.io.channel_status[4].flow.ingress_node \n connect vc_allocator.io.channel_status.`0`[4].flow.vnet_id, output_unit_0_to_1.io.channel_status[4].flow.vnet_id \n connect vc_allocator.io.channel_status.`0`[4].occupied, output_unit_0_to_1.io.channel_status[4].occupied \n connect vc_allocator.io.channel_status.`0`[5].flow.egress_node_id, output_unit_0_to_1.io.channel_status[5].flow.egress_node_id \n connect vc_allocator.io.channel_status.`0`[5].flow.egress_node, output_unit_0_to_1.io.channel_status[5].flow.egress_node \n connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node_id, output_unit_0_to_1.io.channel_status[5].flow.ingress_node_id \n connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node, output_unit_0_to_1.io.channel_status[5].flow.ingress_node \n connect vc_allocator.io.channel_status.`0`[5].flow.vnet_id, output_unit_0_to_1.io.channel_status[5].flow.vnet_id \n connect vc_allocator.io.channel_status.`0`[5].occupied, output_unit_0_to_1.io.channel_status[5].occupied \n connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, egress_unit_1_to_1.io.channel_status[0].flow.egress_node_id \n connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, egress_unit_1_to_1.io.channel_status[0].flow.egress_node \n connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, egress_unit_1_to_1.io.channel_status[0].flow.ingress_node_id \n connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, egress_unit_1_to_1.io.channel_status[0].flow.ingress_node \n connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, egress_unit_1_to_1.io.channel_status[0].flow.vnet_id \n connect vc_allocator.io.channel_status.`1`[0].occupied, egress_unit_1_to_1.io.channel_status[0].occupied \n connect input_unit_0_from_12.io.out_credit_available.`0`[0], output_unit_0_to_1.io.credit_available[0] \n connect input_unit_0_from_12.io.out_credit_available.`0`[1], output_unit_0_to_1.io.credit_available[1] \n connect input_unit_0_from_12.io.out_credit_available.`0`[2], output_unit_0_to_1.io.credit_available[2] \n connect input_unit_0_from_12.io.out_credit_available.`0`[3], output_unit_0_to_1.io.credit_available[3] \n connect input_unit_0_from_12.io.out_credit_available.`0`[4], output_unit_0_to_1.io.credit_available[4] \n connect input_unit_0_from_12.io.out_credit_available.`0`[5], output_unit_0_to_1.io.credit_available[5] \n connect input_unit_0_from_12.io.out_credit_available.`1`[0], egress_unit_1_to_1.io.credit_available[0] \n connect ingress_unit_1_from_2.io.out_credit_available.`0`[0], output_unit_0_to_1.io.credit_available[0] \n connect ingress_unit_1_from_2.io.out_credit_available.`0`[1], output_unit_0_to_1.io.credit_available[1] \n connect ingress_unit_1_from_2.io.out_credit_available.`0`[2], output_unit_0_to_1.io.credit_available[2] \n connect ingress_unit_1_from_2.io.out_credit_available.`0`[3], output_unit_0_to_1.io.credit_available[3] \n connect ingress_unit_1_from_2.io.out_credit_available.`0`[4], output_unit_0_to_1.io.credit_available[4] \n connect ingress_unit_1_from_2.io.out_credit_available.`0`[5], output_unit_0_to_1.io.credit_available[5] \n connect ingress_unit_1_from_2.io.out_credit_available.`1`[0], egress_unit_1_to_1.io.credit_available[0] \n connect ingress_unit_2_from_3.io.out_credit_available.`0`[0], output_unit_0_to_1.io.credit_available[0] \n connect ingress_unit_2_from_3.io.out_credit_available.`0`[1], output_unit_0_to_1.io.credit_available[1] \n connect ingress_unit_2_from_3.io.out_credit_available.`0`[2], output_unit_0_to_1.io.credit_available[2] \n connect ingress_unit_2_from_3.io.out_credit_available.`0`[3], output_unit_0_to_1.io.credit_available[3] \n connect ingress_unit_2_from_3.io.out_credit_available.`0`[4], output_unit_0_to_1.io.credit_available[4] \n connect ingress_unit_2_from_3.io.out_credit_available.`0`[5], output_unit_0_to_1.io.credit_available[5] \n connect ingress_unit_2_from_3.io.out_credit_available.`1`[0], egress_unit_1_to_1.io.credit_available[0] \n connect switch_allocator.io.req.`0`[0], input_unit_0_from_12.io.salloc_req[0] \n connect switch_allocator.io.req.`1`[0], ingress_unit_1_from_2.io.salloc_req[0] \n connect switch_allocator.io.req.`2`[0], ingress_unit_2_from_3.io.salloc_req[0] \n connect output_unit_0_to_1.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail \n connect output_unit_0_to_1.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc \n connect output_unit_0_to_1.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail \n connect output_unit_0_to_1.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc \n connect output_unit_0_to_1.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail \n connect output_unit_0_to_1.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc \n connect output_unit_0_to_1.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail \n connect output_unit_0_to_1.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc \n connect output_unit_0_to_1.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`0`[4].tail \n connect output_unit_0_to_1.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`0`[4].alloc \n connect output_unit_0_to_1.io.credit_alloc[5].tail, switch_allocator.io.credit_alloc.`0`[5].tail \n connect output_unit_0_to_1.io.credit_alloc[5].alloc, switch_allocator.io.credit_alloc.`0`[5].alloc \n connect egress_unit_1_to_1.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail \n connect egress_unit_1_to_1.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc \n connect switch.io.in.`0`[0], input_unit_0_from_12.io.out[0] \n connect switch.io.in.`1`[0], ingress_unit_1_from_2.io.out[0] \n connect switch.io.in.`2`[0], ingress_unit_2_from_3.io.out[0] \n connect output_unit_0_to_1.io.in, switch.io.out.`0` \n connect egress_unit_1_to_1.io.in, switch.io.out.`1` \n reg REG : { `1` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock \n connect REG, switch_allocator.io.switch_sel \n connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0] \n connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0] \n connect switch.io.sel.`0`[0].`2`[0], REG.`0`[0].`2`[0] \n connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0] \n connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0] \n connect switch.io.sel.`1`[0].`2`[0], REG.`1`[0].`2`[0] \n connect input_unit_0_from_12.io.block, UInt<1>(0h0) \n connect ingress_unit_1_from_2.io.block, UInt<1>(0h0) \n connect ingress_unit_2_from_3.io.block, UInt<1>(0h0) \n connect debugNodeOut.va_stall[0], input_unit_0_from_12.io.debug.va_stall \n connect debugNodeOut.va_stall[1], ingress_unit_1_from_2.io.debug.va_stall \n connect debugNodeOut.va_stall[2], ingress_unit_2_from_3.io.debug.va_stall \n connect debugNodeOut.sa_stall[0], input_unit_0_from_12.io.debug.sa_stall \n connect debugNodeOut.sa_stall[1], ingress_unit_1_from_2.io.debug.sa_stall \n connect debugNodeOut.sa_stall[2], ingress_unit_2_from_3.io.debug.sa_stall \n regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0) \n node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1)) \n node _debug_tsc_T_1 = tail(_debug_tsc_T, 1) \n connect debug_tsc, _debug_tsc_T_1 \n regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0) \n node _debug_sample_T = add(debug_sample, UInt<1>(0h1)) \n node _debug_sample_T_1 = tail(_debug_sample_T, 1) \n connect debug_sample, _debug_sample_T_1 \n inst plusarg_reader of plusarg_reader_18 \n node _T = sub(plusarg_reader.out, UInt<1>(0h1)) \n node _T_1 = tail(_T, 1) \n node _T_2 = eq(debug_sample, _T_1) \n when _T_2 : \n connect debug_sample, UInt<1>(0h0) \n regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0) \n regreset fired : UInt<1>, clock, reset, UInt<1>(0h0) \n node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid) \n node _util_ctr_T_1 = tail(_util_ctr_T, 1) \n connect util_ctr, _util_ctr_T_1 \n node _fired_T = or(fired, destNodesIn.flit[0].valid) \n connect fired, _fired_T \n node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0)) \n node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1)) \n node _T_5 = tail(_T_4, 1) \n node _T_6 = eq(debug_sample, _T_5) \n node _T_7 = and(_T_3, _T_6) \n node _T_8 = and(_T_7, fired) \n when _T_8 : \n node _T_9 = asUInt(reset) \n node _T_10 = eq(_T_9, UInt<1>(0h0)) \n when _T_10 : \n printf(clock, UInt<1>(0h1), \"nocsample %d 12 0 %d\\n\", debug_tsc, util_ctr) : printf \n connect fired, destNodesIn.flit[0].valid \n node _T_11 = and(ingressNodesIn.flit.ready, ingressNodesIn.flit.valid) \n regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0) \n regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _util_ctr_T_2 = add(util_ctr_1, _T_11) \n node _util_ctr_T_3 = tail(_util_ctr_T_2, 1) \n connect util_ctr_1, _util_ctr_T_3 \n node _fired_T_1 = or(fired_1, _T_11) \n connect fired_1, _fired_T_1 \n node _T_12 = neq(plusarg_reader.out, UInt<1>(0h0)) \n node _T_13 = sub(plusarg_reader.out, UInt<1>(0h1)) \n node _T_14 = tail(_T_13, 1) \n node _T_15 = eq(debug_sample, _T_14) \n node _T_16 = and(_T_12, _T_15) \n node _T_17 = and(_T_16, fired_1) \n when _T_17 : \n node _T_18 = asUInt(reset) \n node _T_19 = eq(_T_18, UInt<1>(0h0)) \n when _T_19 : \n printf(clock, UInt<1>(0h1), \"nocsample %d i2 0 %d\\n\", debug_tsc, util_ctr_1) : printf_1 \n connect fired_1, _T_11 \n node _T_20 = and(ingressNodesIn_1.flit.ready, ingressNodesIn_1.flit.valid) \n regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0) \n regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _util_ctr_T_4 = add(util_ctr_2, _T_20) \n node _util_ctr_T_5 = tail(_util_ctr_T_4, 1) \n connect util_ctr_2, _util_ctr_T_5 \n node _fired_T_2 = or(fired_2, _T_20) \n connect fired_2, _fired_T_2 \n node _T_21 = neq(plusarg_reader.out, UInt<1>(0h0)) \n node _T_22 = sub(plusarg_reader.out, UInt<1>(0h1)) \n node _T_23 = tail(_T_22, 1) \n node _T_24 = eq(debug_sample, _T_23) \n node _T_25 = and(_T_21, _T_24) \n node _T_26 = and(_T_25, fired_2) \n when _T_26 : \n node _T_27 = asUInt(reset) \n node _T_28 = eq(_T_27, UInt<1>(0h0)) \n when _T_28 : \n printf(clock, UInt<1>(0h1), \"nocsample %d i3 0 %d\\n\", debug_tsc, util_ctr_2) : printf_2 \n connect fired_2, _T_20 \n node _T_29 = and(egressNodesOut.flit.ready, egressNodesOut.flit.valid) \n regreset util_ctr_3 : UInt<64>, clock, reset, UInt<64>(0h0) \n regreset fired_3 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _util_ctr_T_6 = add(util_ctr_3, _T_29) \n node _util_ctr_T_7 = tail(_util_ctr_T_6, 1) \n connect util_ctr_3, _util_ctr_T_7 \n node _fired_T_3 = or(fired_3, _T_29) \n connect fired_3, _fired_T_3 \n node _T_30 = neq(plusarg_reader.out, UInt<1>(0h0)) \n node _T_31 = sub(plusarg_reader.out, UInt<1>(0h1)) \n node _T_32 = tail(_T_31, 1) \n node _T_33 = eq(debug_sample, _T_32) \n node _T_34 = and(_T_30, _T_33) \n node _T_35 = and(_T_34, fired_3) \n when _T_35 : \n node _T_36 = asUInt(reset) \n node _T_37 = eq(_T_36, UInt<1>(0h0)) \n when _T_37 : \n printf(clock, UInt<1>(0h1), \"nocsample %d 0 e1 %d\\n\", debug_tsc, util_ctr_3) : printf_3 \n connect fired_3, _T_29"},"response":{"kind":"string","value":"module Router(\t// @[Router.scala:89:25]\n input clock,\t// @[Router.scala:89:25]\n input reset,\t// @[Router.scala:89:25]\n output [2:0] auto_debug_out_va_stall_0,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_debug_out_va_stall_1,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_debug_out_va_stall_2,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_debug_out_sa_stall_0,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_debug_out_sa_stall_1,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_debug_out_sa_stall_2,\t// @[LazyModuleImp.scala:107:25]\n input auto_egress_nodes_out_flit_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_egress_nodes_out_flit_valid,\t// @[LazyModuleImp.scala:107:25]\n output auto_egress_nodes_out_flit_bits_head,\t// @[LazyModuleImp.scala:107:25]\n output auto_egress_nodes_out_flit_bits_tail,\t// @[LazyModuleImp.scala:107:25]\n output [72:0] auto_egress_nodes_out_flit_bits_payload,\t// @[LazyModuleImp.scala:107:25]\n output auto_ingress_nodes_in_1_flit_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_ingress_nodes_in_1_flit_valid,\t// @[LazyModuleImp.scala:107:25]\n input auto_ingress_nodes_in_1_flit_bits_head,\t// @[LazyModuleImp.scala:107:25]\n input auto_ingress_nodes_in_1_flit_bits_tail,\t// @[LazyModuleImp.scala:107:25]\n input [72:0] auto_ingress_nodes_in_1_flit_bits_payload,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_ingress_nodes_in_1_flit_bits_egress_id,\t// @[LazyModuleImp.scala:107:25]\n output auto_ingress_nodes_in_0_flit_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_ingress_nodes_in_0_flit_valid,\t// @[LazyModuleImp.scala:107:25]\n input auto_ingress_nodes_in_0_flit_bits_head,\t// @[LazyModuleImp.scala:107:25]\n input auto_ingress_nodes_in_0_flit_bits_tail,\t// @[LazyModuleImp.scala:107:25]\n input [72:0] auto_ingress_nodes_in_0_flit_bits_payload,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_ingress_nodes_in_0_flit_bits_egress_id,\t// @[LazyModuleImp.scala:107:25]\n output auto_source_nodes_out_flit_0_valid,\t// @[LazyModuleImp.scala:107:25]\n output auto_source_nodes_out_flit_0_bits_head,\t// @[LazyModuleImp.scala:107:25]\n output auto_source_nodes_out_flit_0_bits_tail,\t// @[LazyModuleImp.scala:107:25]\n output [72:0] auto_source_nodes_out_flit_0_bits_payload,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_source_nodes_out_flit_0_bits_flow_vnet_id,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node_id,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_source_nodes_out_flit_0_bits_flow_egress_node,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_source_nodes_out_flit_0_bits_flow_egress_node_id,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_source_nodes_out_flit_0_bits_virt_channel_id,\t// @[LazyModuleImp.scala:107:25]\n input [5:0] auto_source_nodes_out_credit_return,\t// @[LazyModuleImp.scala:107:25]\n input [5:0] auto_source_nodes_out_vc_free,\t// @[LazyModuleImp.scala:107:25]\n input auto_dest_nodes_in_flit_0_valid,\t// @[LazyModuleImp.scala:107:25]\n input auto_dest_nodes_in_flit_0_bits_head,\t// @[LazyModuleImp.scala:107:25]\n input auto_dest_nodes_in_flit_0_bits_tail,\t// @[LazyModuleImp.scala:107:25]\n input [72:0] auto_dest_nodes_in_flit_0_bits_payload,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_dest_nodes_in_flit_0_bits_flow_vnet_id,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node_id,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_dest_nodes_in_flit_0_bits_virt_channel_id,\t// @[LazyModuleImp.scala:107:25]\n output [5:0] auto_dest_nodes_in_credit_return,\t// @[LazyModuleImp.scala:107:25]\n output [5:0] auto_dest_nodes_in_vc_free\t// @[LazyModuleImp.scala:107:25]\n);\n\n wire [19:0] _plusarg_reader_out;\t// @[PlusArg.scala:80:11]\n wire _route_computer_io_resp_1_vc_sel_0_0;\t// @[Router.scala:136:32]\n wire _route_computer_io_resp_1_vc_sel_0_1;\t// @[Router.scala:136:32]\n wire _route_computer_io_resp_1_vc_sel_0_2;\t// @[Router.scala:136:32]\n wire _route_computer_io_resp_1_vc_sel_0_3;\t// @[Router.scala:136:32]\n wire _route_computer_io_resp_1_vc_sel_0_4;\t// @[Router.scala:136:32]\n wire _route_computer_io_resp_1_vc_sel_0_5;\t// @[Router.scala:136:32]\n wire _route_computer_io_resp_0_vc_sel_0_0;\t// @[Router.scala:136:32]\n wire _route_computer_io_resp_0_vc_sel_0_1;\t// @[Router.scala:136:32]\n wire _vc_allocator_io_req_2_ready;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_req_1_ready;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_req_0_ready;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_2_vc_sel_1_0;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_2_vc_sel_0_0;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_2_vc_sel_0_1;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_2_vc_sel_0_2;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_2_vc_sel_0_3;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_2_vc_sel_0_4;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_2_vc_sel_0_5;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_1_vc_sel_1_0;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_1_vc_sel_0_0;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_1_vc_sel_0_1;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_1_vc_sel_0_2;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_1_vc_sel_0_3;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_1_vc_sel_0_4;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_1_vc_sel_0_5;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_0_vc_sel_1_0;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_0_vc_sel_0_0;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_0_vc_sel_0_1;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_out_allocs_1_0_alloc;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_out_allocs_0_0_alloc;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_out_allocs_0_1_alloc;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_out_allocs_0_3_alloc;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_out_allocs_0_5_alloc;\t// @[Router.scala:133:30]\n wire _switch_allocator_io_req_2_0_ready;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_req_1_0_ready;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_req_0_0_ready;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_credit_alloc_1_0_alloc;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_credit_alloc_1_0_tail;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_credit_alloc_0_0_alloc;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_credit_alloc_0_1_alloc;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_credit_alloc_0_3_alloc;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_credit_alloc_0_5_alloc;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_switch_sel_1_0_2_0;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_switch_sel_1_0_1_0;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_switch_sel_1_0_0_0;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_switch_sel_0_0_2_0;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_switch_sel_0_0_1_0;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_switch_sel_0_0_0_0;\t// @[Router.scala:132:34]\n wire _switch_io_out_1_0_valid;\t// @[Router.scala:131:24]\n wire _switch_io_out_1_0_bits_head;\t// @[Router.scala:131:24]\n wire _switch_io_out_1_0_bits_tail;\t// @[Router.scala:131:24]\n wire [72:0] _switch_io_out_1_0_bits_payload;\t// @[Router.scala:131:24]\n wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node;\t// @[Router.scala:131:24]\n wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id;\t// @[Router.scala:131:24]\n wire _switch_io_out_0_0_valid;\t// @[Router.scala:131:24]\n wire _switch_io_out_0_0_bits_head;\t// @[Router.scala:131:24]\n wire _switch_io_out_0_0_bits_tail;\t// @[Router.scala:131:24]\n wire [72:0] _switch_io_out_0_0_bits_payload;\t// @[Router.scala:131:24]\n wire [1:0] _switch_io_out_0_0_bits_flow_vnet_id;\t// @[Router.scala:131:24]\n wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node;\t// @[Router.scala:131:24]\n wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id;\t// @[Router.scala:131:24]\n wire [3:0] _switch_io_out_0_0_bits_flow_egress_node;\t// @[Router.scala:131:24]\n wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id;\t// @[Router.scala:131:24]\n wire [2:0] _switch_io_out_0_0_bits_virt_channel_id;\t// @[Router.scala:131:24]\n wire _egress_unit_1_to_1_io_credit_available_0;\t// @[Router.scala:125:13]\n wire _egress_unit_1_to_1_io_channel_status_0_occupied;\t// @[Router.scala:125:13]\n wire _egress_unit_1_to_1_io_out_valid;\t// @[Router.scala:125:13]\n wire _output_unit_0_to_1_io_credit_available_0;\t// @[Router.scala:122:13]\n wire _output_unit_0_to_1_io_credit_available_1;\t// @[Router.scala:122:13]\n wire _output_unit_0_to_1_io_credit_available_3;\t// @[Router.scala:122:13]\n wire _output_unit_0_to_1_io_credit_available_5;\t// @[Router.scala:122:13]\n wire _output_unit_0_to_1_io_channel_status_0_occupied;\t// @[Router.scala:122:13]\n wire _output_unit_0_to_1_io_channel_status_1_occupied;\t// @[Router.scala:122:13]\n wire _output_unit_0_to_1_io_channel_status_3_occupied;\t// @[Router.scala:122:13]\n wire _output_unit_0_to_1_io_channel_status_5_occupied;\t// @[Router.scala:122:13]\n wire _ingress_unit_2_from_3_io_vcalloc_req_valid;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_3_io_vcalloc_req_bits_vc_sel_1_0;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_3_io_vcalloc_req_bits_vc_sel_0_0;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_3_io_vcalloc_req_bits_vc_sel_0_1;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_3_io_vcalloc_req_bits_vc_sel_0_2;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_3_io_vcalloc_req_bits_vc_sel_0_3;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_3_io_vcalloc_req_bits_vc_sel_0_4;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_3_io_vcalloc_req_bits_vc_sel_0_5;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_3_io_salloc_req_0_valid;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_3_io_salloc_req_0_bits_vc_sel_1_0;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_3_io_salloc_req_0_bits_vc_sel_0_0;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_3_io_salloc_req_0_bits_vc_sel_0_1;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_3_io_salloc_req_0_bits_vc_sel_0_2;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_3_io_salloc_req_0_bits_vc_sel_0_3;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_3_io_salloc_req_0_bits_vc_sel_0_4;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_3_io_salloc_req_0_bits_vc_sel_0_5;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_3_io_salloc_req_0_bits_tail;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_3_io_out_0_valid;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_3_io_out_0_bits_flit_head;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_3_io_out_0_bits_flit_tail;\t// @[Router.scala:116:13]\n wire [72:0] _ingress_unit_2_from_3_io_out_0_bits_flit_payload;\t// @[Router.scala:116:13]\n wire [1:0] _ingress_unit_2_from_3_io_out_0_bits_flit_flow_vnet_id;\t// @[Router.scala:116:13]\n wire [3:0] _ingress_unit_2_from_3_io_out_0_bits_flit_flow_ingress_node;\t// @[Router.scala:116:13]\n wire [1:0] _ingress_unit_2_from_3_io_out_0_bits_flit_flow_ingress_node_id;\t// @[Router.scala:116:13]\n wire [3:0] _ingress_unit_2_from_3_io_out_0_bits_flit_flow_egress_node;\t// @[Router.scala:116:13]\n wire [1:0] _ingress_unit_2_from_3_io_out_0_bits_flit_flow_egress_node_id;\t// @[Router.scala:116:13]\n wire [2:0] _ingress_unit_2_from_3_io_out_0_bits_out_virt_channel;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_3_io_in_ready;\t// @[Router.scala:116:13]\n wire [3:0] _ingress_unit_1_from_2_io_router_req_bits_flow_egress_node;\t// @[Router.scala:116:13]\n wire [1:0] _ingress_unit_1_from_2_io_router_req_bits_flow_egress_node_id;\t// @[Router.scala:116:13]\n wire _ingress_unit_1_from_2_io_vcalloc_req_valid;\t// @[Router.scala:116:13]\n wire _ingress_unit_1_from_2_io_vcalloc_req_bits_vc_sel_1_0;\t// @[Router.scala:116:13]\n wire _ingress_unit_1_from_2_io_vcalloc_req_bits_vc_sel_0_0;\t// @[Router.scala:116:13]\n wire _ingress_unit_1_from_2_io_vcalloc_req_bits_vc_sel_0_1;\t// @[Router.scala:116:13]\n wire _ingress_unit_1_from_2_io_vcalloc_req_bits_vc_sel_0_2;\t// @[Router.scala:116:13]\n wire _ingress_unit_1_from_2_io_vcalloc_req_bits_vc_sel_0_3;\t// @[Router.scala:116:13]\n wire _ingress_unit_1_from_2_io_vcalloc_req_bits_vc_sel_0_4;\t// @[Router.scala:116:13]\n wire _ingress_unit_1_from_2_io_vcalloc_req_bits_vc_sel_0_5;\t// @[Router.scala:116:13]\n wire _ingress_unit_1_from_2_io_salloc_req_0_valid;\t// @[Router.scala:116:13]\n wire _ingress_unit_1_from_2_io_salloc_req_0_bits_vc_sel_1_0;\t// @[Router.scala:116:13]\n wire _ingress_unit_1_from_2_io_salloc_req_0_bits_vc_sel_0_0;\t// @[Router.scala:116:13]\n wire _ingress_unit_1_from_2_io_salloc_req_0_bits_vc_sel_0_1;\t// @[Router.scala:116:13]\n wire _ingress_unit_1_from_2_io_salloc_req_0_bits_vc_sel_0_2;\t// @[Router.scala:116:13]\n wire _ingress_unit_1_from_2_io_salloc_req_0_bits_vc_sel_0_3;\t// @[Router.scala:116:13]\n wire _ingress_unit_1_from_2_io_salloc_req_0_bits_vc_sel_0_4;\t// @[Router.scala:116:13]\n wire _ingress_unit_1_from_2_io_salloc_req_0_bits_vc_sel_0_5;\t// @[Router.scala:116:13]\n wire _ingress_unit_1_from_2_io_salloc_req_0_bits_tail;\t// @[Router.scala:116:13]\n wire _ingress_unit_1_from_2_io_out_0_valid;\t// @[Router.scala:116:13]\n wire _ingress_unit_1_from_2_io_out_0_bits_flit_head;\t// @[Router.scala:116:13]\n wire _ingress_unit_1_from_2_io_out_0_bits_flit_tail;\t// @[Router.scala:116:13]\n wire [72:0] _ingress_unit_1_from_2_io_out_0_bits_flit_payload;\t// @[Router.scala:116:13]\n wire [1:0] _ingress_unit_1_from_2_io_out_0_bits_flit_flow_vnet_id;\t// @[Router.scala:116:13]\n wire [3:0] _ingress_unit_1_from_2_io_out_0_bits_flit_flow_ingress_node;\t// @[Router.scala:116:13]\n wire [1:0] _ingress_unit_1_from_2_io_out_0_bits_flit_flow_ingress_node_id;\t// @[Router.scala:116:13]\n wire [3:0] _ingress_unit_1_from_2_io_out_0_bits_flit_flow_egress_node;\t// @[Router.scala:116:13]\n wire [1:0] _ingress_unit_1_from_2_io_out_0_bits_flit_flow_egress_node_id;\t// @[Router.scala:116:13]\n wire [2:0] _ingress_unit_1_from_2_io_out_0_bits_out_virt_channel;\t// @[Router.scala:116:13]\n wire _ingress_unit_1_from_2_io_in_ready;\t// @[Router.scala:116:13]\n wire [2:0] _input_unit_0_from_12_io_router_req_bits_src_virt_id;\t// @[Router.scala:112:13]\n wire [1:0] _input_unit_0_from_12_io_router_req_bits_flow_vnet_id;\t// @[Router.scala:112:13]\n wire [3:0] _input_unit_0_from_12_io_router_req_bits_flow_ingress_node;\t// @[Router.scala:112:13]\n wire [1:0] _input_unit_0_from_12_io_router_req_bits_flow_ingress_node_id;\t// @[Router.scala:112:13]\n wire [3:0] _input_unit_0_from_12_io_router_req_bits_flow_egress_node;\t// @[Router.scala:112:13]\n wire [1:0] _input_unit_0_from_12_io_router_req_bits_flow_egress_node_id;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_12_io_vcalloc_req_valid;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_12_io_vcalloc_req_bits_vc_sel_1_0;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_12_io_vcalloc_req_bits_vc_sel_0_0;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_12_io_vcalloc_req_bits_vc_sel_0_1;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_12_io_salloc_req_0_valid;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_12_io_salloc_req_0_bits_vc_sel_1_0;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_12_io_salloc_req_0_bits_vc_sel_0_0;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_12_io_salloc_req_0_bits_vc_sel_0_1;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_12_io_salloc_req_0_bits_vc_sel_0_2;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_12_io_salloc_req_0_bits_vc_sel_0_3;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_12_io_salloc_req_0_bits_vc_sel_0_4;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_12_io_salloc_req_0_bits_vc_sel_0_5;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_12_io_salloc_req_0_bits_tail;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_12_io_out_0_valid;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_12_io_out_0_bits_flit_head;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_12_io_out_0_bits_flit_tail;\t// @[Router.scala:112:13]\n wire [72:0] _input_unit_0_from_12_io_out_0_bits_flit_payload;\t// @[Router.scala:112:13]\n wire [1:0] _input_unit_0_from_12_io_out_0_bits_flit_flow_vnet_id;\t// @[Router.scala:112:13]\n wire [3:0] _input_unit_0_from_12_io_out_0_bits_flit_flow_ingress_node;\t// @[Router.scala:112:13]\n wire [1:0] _input_unit_0_from_12_io_out_0_bits_flit_flow_ingress_node_id;\t// @[Router.scala:112:13]\n wire [3:0] _input_unit_0_from_12_io_out_0_bits_flit_flow_egress_node;\t// @[Router.scala:112:13]\n wire [1:0] _input_unit_0_from_12_io_out_0_bits_flit_flow_egress_node_id;\t// @[Router.scala:112:13]\n wire [2:0] _input_unit_0_from_12_io_out_0_bits_out_virt_channel;\t// @[Router.scala:112:13]\n wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_12_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _ingress_unit_1_from_2_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_2_ready & _ingress_unit_2_from_3_io_vcalloc_req_valid};\t// @[Decoupled.scala:51:35]\n reg REG_1_0_2_0;\t// @[Router.scala:178:14]\n reg REG_1_0_1_0;\t// @[Router.scala:178:14]\n reg REG_1_0_0_0;\t// @[Router.scala:178:14]\n reg REG_0_0_2_0;\t// @[Router.scala:178:14]\n reg REG_0_0_1_0;\t// @[Router.scala:178:14]\n reg REG_0_0_0_0;\t// @[Router.scala:178:14]\n reg [63:0] debug_tsc;\t// @[Router.scala:195:28]\n reg [63:0] debug_sample;\t// @[Router.scala:197:31]\n wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1};\t// @[PlusArg.scala:80:11]\n reg [63:0] util_ctr;\t// @[Router.scala:203:29]\n reg fired;\t// @[Router.scala:204:26]\n wire _GEN_0 = (|_plusarg_reader_out) & _GEN;\t// @[PlusArg.scala:80:11]\n wire _GEN_1 = _GEN_0 & fired;\t// @[Router.scala:204:26, :207:{33,71}]\n reg [63:0] util_ctr_1;\t// @[Router.scala:203:29]\n reg fired_1;\t// @[Router.scala:204:26]\n wire _GEN_2 = _GEN_0 & fired_1;\t// @[Router.scala:204:26, :207:{33,71}]\n reg [63:0] util_ctr_2;\t// @[Router.scala:203:29]\n reg fired_2;\t// @[Router.scala:204:26]\n wire _GEN_3 = _GEN_0 & fired_2;\t// @[Router.scala:204:26, :207:{33,71}]\n reg [63:0] util_ctr_3;\t// @[Router.scala:203:29]\n reg fired_3;\t// @[Router.scala:204:26]\n wire _GEN_4 = _GEN_0 & fired_3;\t// @[Router.scala:204:26, :207:{33,71}]"}}},{"rowIdx":34186,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module Router_32 : \n input clock : Clock \n input reset : Reset \n output auto : { debug_out : { va_stall : UInt[3], sa_stall : UInt[3]}, egress_nodes_out_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, egress_nodes_out_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, egress_nodes_out_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, flip ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}} \n\n\n wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>} \n invalidate destNodesIn.vc_free \n invalidate destNodesIn.credit_return \n invalidate destNodesIn.flit[0].bits.virt_channel_id \n invalidate destNodesIn.flit[0].bits.flow.egress_node_id \n invalidate destNodesIn.flit[0].bits.flow.egress_node \n invalidate destNodesIn.flit[0].bits.flow.ingress_node_id \n invalidate destNodesIn.flit[0].bits.flow.ingress_node \n invalidate destNodesIn.flit[0].bits.flow.vnet_id \n invalidate destNodesIn.flit[0].bits.payload \n invalidate destNodesIn.flit[0].bits.tail \n invalidate destNodesIn.flit[0].bits.head \n invalidate destNodesIn.flit[0].valid \n inst monitor of NoCMonitor_75 \n connect monitor.clock, clock\n\n connect monitor.reset, reset\n\n connect monitor.io.in.vc_free, destNodesIn.vc_free \n connect monitor.io.in.credit_return, destNodesIn.credit_return \n connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id \n connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id \n connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node \n connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id \n connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node \n connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id \n connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload \n connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail \n connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head \n connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid \n wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>} \n invalidate sourceNodesOut.vc_free \n invalidate sourceNodesOut.credit_return \n invalidate sourceNodesOut.flit[0].bits.virt_channel_id \n invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id \n invalidate sourceNodesOut.flit[0].bits.flow.egress_node \n invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id \n invalidate sourceNodesOut.flit[0].bits.flow.ingress_node \n invalidate sourceNodesOut.flit[0].bits.flow.vnet_id \n invalidate sourceNodesOut.flit[0].bits.payload \n invalidate sourceNodesOut.flit[0].bits.tail \n invalidate sourceNodesOut.flit[0].bits.head \n invalidate sourceNodesOut.flit[0].valid \n wire ingressNodesIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} \n invalidate ingressNodesIn.flit.bits.egress_id \n invalidate ingressNodesIn.flit.bits.payload \n invalidate ingressNodesIn.flit.bits.tail \n invalidate ingressNodesIn.flit.bits.head \n invalidate ingressNodesIn.flit.valid \n invalidate ingressNodesIn.flit.ready \n wire ingressNodesIn_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}} \n invalidate ingressNodesIn_1.flit.bits.egress_id \n invalidate ingressNodesIn_1.flit.bits.payload \n invalidate ingressNodesIn_1.flit.bits.tail \n invalidate ingressNodesIn_1.flit.bits.head \n invalidate ingressNodesIn_1.flit.valid \n invalidate ingressNodesIn_1.flit.ready \n wire egressNodesOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} \n invalidate egressNodesOut.flit.bits.ingress_id \n invalidate egressNodesOut.flit.bits.payload \n invalidate egressNodesOut.flit.bits.tail \n invalidate egressNodesOut.flit.bits.head \n invalidate egressNodesOut.flit.valid \n invalidate egressNodesOut.flit.ready \n wire egressNodesOut_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} \n invalidate egressNodesOut_1.flit.bits.ingress_id \n invalidate egressNodesOut_1.flit.bits.payload \n invalidate egressNodesOut_1.flit.bits.tail \n invalidate egressNodesOut_1.flit.bits.head \n invalidate egressNodesOut_1.flit.valid \n invalidate egressNodesOut_1.flit.ready \n wire egressNodesOut_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}} \n invalidate egressNodesOut_2.flit.bits.ingress_id \n invalidate egressNodesOut_2.flit.bits.payload \n invalidate egressNodesOut_2.flit.bits.tail \n invalidate egressNodesOut_2.flit.bits.head \n invalidate egressNodesOut_2.flit.valid \n invalidate egressNodesOut_2.flit.ready \n wire debugNodeOut : { va_stall : UInt[3], sa_stall : UInt[3]} \n invalidate debugNodeOut.sa_stall[0] \n invalidate debugNodeOut.sa_stall[1] \n invalidate debugNodeOut.sa_stall[2] \n invalidate debugNodeOut.va_stall[0] \n invalidate debugNodeOut.va_stall[1] \n invalidate debugNodeOut.va_stall[2] \n connect destNodesIn, auto.dest_nodes_in \n connect auto.source_nodes_out, sourceNodesOut \n connect ingressNodesIn, auto.ingress_nodes_in_0 \n connect ingressNodesIn_1, auto.ingress_nodes_in_1 \n connect auto.egress_nodes_out_0, egressNodesOut \n connect auto.egress_nodes_out_1, egressNodesOut_1 \n connect auto.egress_nodes_out_2, egressNodesOut_2 \n connect auto.debug_out, debugNodeOut \n inst input_unit_0_from_12 of InputUnit_75 \n connect input_unit_0_from_12.clock, clock\n\n connect input_unit_0_from_12.reset, reset\n\n inst ingress_unit_1_from_7 of IngressUnit_44 \n connect ingress_unit_1_from_7.clock, clock\n\n connect ingress_unit_1_from_7.reset, reset\n\n inst ingress_unit_2_from_8 of IngressUnit_45 \n connect ingress_unit_2_from_8.clock, clock\n\n connect ingress_unit_2_from_8.reset, reset\n\n inst output_unit_0_to_12 of OutputUnit_75 \n connect output_unit_0_to_12.clock, clock\n\n connect output_unit_0_to_12.reset, reset\n\n inst egress_unit_1_to_8 of EgressUnit_41 \n connect egress_unit_1_to_8.clock, clock\n\n connect egress_unit_1_to_8.reset, reset\n\n inst egress_unit_2_to_9 of EgressUnit_42 \n connect egress_unit_2_to_9.clock, clock\n\n connect egress_unit_2_to_9.reset, reset\n\n inst egress_unit_3_to_10 of EgressUnit_43 \n connect egress_unit_3_to_10.clock, clock\n\n connect egress_unit_3_to_10.reset, reset\n\n inst switch of Switch_32 \n connect switch.clock, clock\n\n connect switch.reset, reset\n\n inst switch_allocator of SwitchAllocator_32 \n connect switch_allocator.clock, clock\n\n connect switch_allocator.reset, reset\n\n inst vc_allocator of RotatingSingleVCAllocator_32 \n connect vc_allocator.clock, clock\n\n connect vc_allocator.reset, reset\n\n inst route_computer of RouteComputer_32 \n connect route_computer.clock, clock\n\n connect route_computer.reset, reset\n\n node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid) \n node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid) \n node _fires_count_T_2 = and(vc_allocator.io.req.`2`.ready, vc_allocator.io.req.`2`.valid) \n node _fires_count_T_3 = add(_fires_count_T_1, _fires_count_T_2) \n node _fires_count_T_4 = bits(_fires_count_T_3, 1, 0) \n node _fires_count_T_5 = add(_fires_count_T, _fires_count_T_4) \n node _fires_count_T_6 = bits(_fires_count_T_5, 1, 0) \n wire fires_count : UInt \n connect fires_count, _fires_count_T_6 \n connect input_unit_0_from_12.io.in, destNodesIn \n connect ingress_unit_1_from_7.io.in, ingressNodesIn.flit \n connect ingress_unit_2_from_8.io.in, ingressNodesIn_1.flit \n connect output_unit_0_to_12.io.out.vc_free, sourceNodesOut.vc_free \n connect output_unit_0_to_12.io.out.credit_return, sourceNodesOut.credit_return \n connect sourceNodesOut.flit, output_unit_0_to_12.io.out.flit \n connect egressNodesOut.flit.bits, egress_unit_1_to_8.io.out.bits \n connect egressNodesOut.flit.valid, egress_unit_1_to_8.io.out.valid \n connect egress_unit_1_to_8.io.out.ready, egressNodesOut.flit.ready \n connect egressNodesOut_1.flit.bits, egress_unit_2_to_9.io.out.bits \n connect egressNodesOut_1.flit.valid, egress_unit_2_to_9.io.out.valid \n connect egress_unit_2_to_9.io.out.ready, egressNodesOut_1.flit.ready \n connect egressNodesOut_2.flit.bits, egress_unit_3_to_10.io.out.bits \n connect egressNodesOut_2.flit.valid, egress_unit_3_to_10.io.out.valid \n connect egress_unit_3_to_10.io.out.ready, egressNodesOut_2.flit.ready \n connect route_computer.io.req.`0`, input_unit_0_from_12.io.router_req \n connect route_computer.io.req.`1`, ingress_unit_1_from_7.io.router_req \n connect route_computer.io.req.`2`, ingress_unit_2_from_8.io.router_req \n connect input_unit_0_from_12.io.router_resp, route_computer.io.resp.`0` \n connect ingress_unit_1_from_7.io.router_resp, route_computer.io.resp.`1` \n connect ingress_unit_2_from_8.io.router_resp, route_computer.io.resp.`2` \n connect vc_allocator.io.req.`0`, input_unit_0_from_12.io.vcalloc_req \n connect vc_allocator.io.req.`1`, ingress_unit_1_from_7.io.vcalloc_req \n connect vc_allocator.io.req.`2`, ingress_unit_2_from_8.io.vcalloc_req \n connect input_unit_0_from_12.io.vcalloc_resp, vc_allocator.io.resp.`0` \n connect ingress_unit_1_from_7.io.vcalloc_resp, vc_allocator.io.resp.`1` \n connect ingress_unit_2_from_8.io.vcalloc_resp, vc_allocator.io.resp.`2` \n connect output_unit_0_to_12.io.allocs, vc_allocator.io.out_allocs.`0` \n connect egress_unit_1_to_8.io.allocs, vc_allocator.io.out_allocs.`1` \n connect egress_unit_2_to_9.io.allocs, vc_allocator.io.out_allocs.`2` \n connect egress_unit_3_to_10.io.allocs, vc_allocator.io.out_allocs.`3` \n connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_12.io.channel_status[0].flow.egress_node_id \n connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_12.io.channel_status[0].flow.egress_node \n connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_12.io.channel_status[0].flow.ingress_node_id \n connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_12.io.channel_status[0].flow.ingress_node \n connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_12.io.channel_status[0].flow.vnet_id \n connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_12.io.channel_status[0].occupied \n connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_12.io.channel_status[1].flow.egress_node_id \n connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_12.io.channel_status[1].flow.egress_node \n connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_12.io.channel_status[1].flow.ingress_node_id \n connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_12.io.channel_status[1].flow.ingress_node \n connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_12.io.channel_status[1].flow.vnet_id \n connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_12.io.channel_status[1].occupied \n connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_12.io.channel_status[2].flow.egress_node_id \n connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_12.io.channel_status[2].flow.egress_node \n connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_12.io.channel_status[2].flow.ingress_node_id \n connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_12.io.channel_status[2].flow.ingress_node \n connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_12.io.channel_status[2].flow.vnet_id \n connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_12.io.channel_status[2].occupied \n connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_12.io.channel_status[3].flow.egress_node_id \n connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_12.io.channel_status[3].flow.egress_node \n connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_12.io.channel_status[3].flow.ingress_node_id \n connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_12.io.channel_status[3].flow.ingress_node \n connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_12.io.channel_status[3].flow.vnet_id \n connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_12.io.channel_status[3].occupied \n connect vc_allocator.io.channel_status.`0`[4].flow.egress_node_id, output_unit_0_to_12.io.channel_status[4].flow.egress_node_id \n connect vc_allocator.io.channel_status.`0`[4].flow.egress_node, output_unit_0_to_12.io.channel_status[4].flow.egress_node \n connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node_id, output_unit_0_to_12.io.channel_status[4].flow.ingress_node_id \n connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node, output_unit_0_to_12.io.channel_status[4].flow.ingress_node \n connect vc_allocator.io.channel_status.`0`[4].flow.vnet_id, output_unit_0_to_12.io.channel_status[4].flow.vnet_id \n connect vc_allocator.io.channel_status.`0`[4].occupied, output_unit_0_to_12.io.channel_status[4].occupied \n connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, egress_unit_1_to_8.io.channel_status[0].flow.egress_node_id \n connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, egress_unit_1_to_8.io.channel_status[0].flow.egress_node \n connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, egress_unit_1_to_8.io.channel_status[0].flow.ingress_node_id \n connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, egress_unit_1_to_8.io.channel_status[0].flow.ingress_node \n connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, egress_unit_1_to_8.io.channel_status[0].flow.vnet_id \n connect vc_allocator.io.channel_status.`1`[0].occupied, egress_unit_1_to_8.io.channel_status[0].occupied \n connect vc_allocator.io.channel_status.`2`[0].flow.egress_node_id, egress_unit_2_to_9.io.channel_status[0].flow.egress_node_id \n connect vc_allocator.io.channel_status.`2`[0].flow.egress_node, egress_unit_2_to_9.io.channel_status[0].flow.egress_node \n connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node_id, egress_unit_2_to_9.io.channel_status[0].flow.ingress_node_id \n connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node, egress_unit_2_to_9.io.channel_status[0].flow.ingress_node \n connect vc_allocator.io.channel_status.`2`[0].flow.vnet_id, egress_unit_2_to_9.io.channel_status[0].flow.vnet_id \n connect vc_allocator.io.channel_status.`2`[0].occupied, egress_unit_2_to_9.io.channel_status[0].occupied \n connect vc_allocator.io.channel_status.`3`[0].flow.egress_node_id, egress_unit_3_to_10.io.channel_status[0].flow.egress_node_id \n connect vc_allocator.io.channel_status.`3`[0].flow.egress_node, egress_unit_3_to_10.io.channel_status[0].flow.egress_node \n connect vc_allocator.io.channel_status.`3`[0].flow.ingress_node_id, egress_unit_3_to_10.io.channel_status[0].flow.ingress_node_id \n connect vc_allocator.io.channel_status.`3`[0].flow.ingress_node, egress_unit_3_to_10.io.channel_status[0].flow.ingress_node \n connect vc_allocator.io.channel_status.`3`[0].flow.vnet_id, egress_unit_3_to_10.io.channel_status[0].flow.vnet_id \n connect vc_allocator.io.channel_status.`3`[0].occupied, egress_unit_3_to_10.io.channel_status[0].occupied \n connect input_unit_0_from_12.io.out_credit_available.`0`[0], output_unit_0_to_12.io.credit_available[0] \n connect input_unit_0_from_12.io.out_credit_available.`0`[1], output_unit_0_to_12.io.credit_available[1] \n connect input_unit_0_from_12.io.out_credit_available.`0`[2], output_unit_0_to_12.io.credit_available[2] \n connect input_unit_0_from_12.io.out_credit_available.`0`[3], output_unit_0_to_12.io.credit_available[3] \n connect input_unit_0_from_12.io.out_credit_available.`0`[4], output_unit_0_to_12.io.credit_available[4] \n connect input_unit_0_from_12.io.out_credit_available.`1`[0], egress_unit_1_to_8.io.credit_available[0] \n connect input_unit_0_from_12.io.out_credit_available.`2`[0], egress_unit_2_to_9.io.credit_available[0] \n connect input_unit_0_from_12.io.out_credit_available.`3`[0], egress_unit_3_to_10.io.credit_available[0] \n connect ingress_unit_1_from_7.io.out_credit_available.`0`[0], output_unit_0_to_12.io.credit_available[0] \n connect ingress_unit_1_from_7.io.out_credit_available.`0`[1], output_unit_0_to_12.io.credit_available[1] \n connect ingress_unit_1_from_7.io.out_credit_available.`0`[2], output_unit_0_to_12.io.credit_available[2] \n connect ingress_unit_1_from_7.io.out_credit_available.`0`[3], output_unit_0_to_12.io.credit_available[3] \n connect ingress_unit_1_from_7.io.out_credit_available.`0`[4], output_unit_0_to_12.io.credit_available[4] \n connect ingress_unit_1_from_7.io.out_credit_available.`1`[0], egress_unit_1_to_8.io.credit_available[0] \n connect ingress_unit_1_from_7.io.out_credit_available.`2`[0], egress_unit_2_to_9.io.credit_available[0] \n connect ingress_unit_1_from_7.io.out_credit_available.`3`[0], egress_unit_3_to_10.io.credit_available[0] \n connect ingress_unit_2_from_8.io.out_credit_available.`0`[0], output_unit_0_to_12.io.credit_available[0] \n connect ingress_unit_2_from_8.io.out_credit_available.`0`[1], output_unit_0_to_12.io.credit_available[1] \n connect ingress_unit_2_from_8.io.out_credit_available.`0`[2], output_unit_0_to_12.io.credit_available[2] \n connect ingress_unit_2_from_8.io.out_credit_available.`0`[3], output_unit_0_to_12.io.credit_available[3] \n connect ingress_unit_2_from_8.io.out_credit_available.`0`[4], output_unit_0_to_12.io.credit_available[4] \n connect ingress_unit_2_from_8.io.out_credit_available.`1`[0], egress_unit_1_to_8.io.credit_available[0] \n connect ingress_unit_2_from_8.io.out_credit_available.`2`[0], egress_unit_2_to_9.io.credit_available[0] \n connect ingress_unit_2_from_8.io.out_credit_available.`3`[0], egress_unit_3_to_10.io.credit_available[0] \n connect switch_allocator.io.req.`0`[0], input_unit_0_from_12.io.salloc_req[0] \n connect switch_allocator.io.req.`1`[0], ingress_unit_1_from_7.io.salloc_req[0] \n connect switch_allocator.io.req.`2`[0], ingress_unit_2_from_8.io.salloc_req[0] \n connect output_unit_0_to_12.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail \n connect output_unit_0_to_12.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc \n connect output_unit_0_to_12.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail \n connect output_unit_0_to_12.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc \n connect output_unit_0_to_12.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail \n connect output_unit_0_to_12.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc \n connect output_unit_0_to_12.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail \n connect output_unit_0_to_12.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc \n connect output_unit_0_to_12.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`0`[4].tail \n connect output_unit_0_to_12.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`0`[4].alloc \n connect egress_unit_1_to_8.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail \n connect egress_unit_1_to_8.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc \n connect egress_unit_2_to_9.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`2`[0].tail \n connect egress_unit_2_to_9.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`2`[0].alloc \n connect egress_unit_3_to_10.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`3`[0].tail \n connect egress_unit_3_to_10.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`3`[0].alloc \n connect switch.io.in.`0`[0], input_unit_0_from_12.io.out[0] \n connect switch.io.in.`1`[0], ingress_unit_1_from_7.io.out[0] \n connect switch.io.in.`2`[0], ingress_unit_2_from_8.io.out[0] \n connect output_unit_0_to_12.io.in, switch.io.out.`0` \n connect egress_unit_1_to_8.io.in, switch.io.out.`1` \n connect egress_unit_2_to_9.io.in, switch.io.out.`2` \n connect egress_unit_3_to_10.io.in, switch.io.out.`3` \n reg REG : { `3` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `2` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock \n connect REG, switch_allocator.io.switch_sel \n connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0] \n connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0] \n connect switch.io.sel.`0`[0].`2`[0], REG.`0`[0].`2`[0] \n connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0] \n connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0] \n connect switch.io.sel.`1`[0].`2`[0], REG.`1`[0].`2`[0] \n connect switch.io.sel.`2`[0].`0`[0], REG.`2`[0].`0`[0] \n connect switch.io.sel.`2`[0].`1`[0], REG.`2`[0].`1`[0] \n connect switch.io.sel.`2`[0].`2`[0], REG.`2`[0].`2`[0] \n connect switch.io.sel.`3`[0].`0`[0], REG.`3`[0].`0`[0] \n connect switch.io.sel.`3`[0].`1`[0], REG.`3`[0].`1`[0] \n connect switch.io.sel.`3`[0].`2`[0], REG.`3`[0].`2`[0] \n connect input_unit_0_from_12.io.block, UInt<1>(0h0) \n connect ingress_unit_1_from_7.io.block, UInt<1>(0h0) \n connect ingress_unit_2_from_8.io.block, UInt<1>(0h0) \n connect debugNodeOut.va_stall[0], input_unit_0_from_12.io.debug.va_stall \n connect debugNodeOut.va_stall[1], ingress_unit_1_from_7.io.debug.va_stall \n connect debugNodeOut.va_stall[2], ingress_unit_2_from_8.io.debug.va_stall \n connect debugNodeOut.sa_stall[0], input_unit_0_from_12.io.debug.sa_stall \n connect debugNodeOut.sa_stall[1], ingress_unit_1_from_7.io.debug.sa_stall \n connect debugNodeOut.sa_stall[2], ingress_unit_2_from_8.io.debug.sa_stall \n regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0) \n node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1)) \n node _debug_tsc_T_1 = tail(_debug_tsc_T, 1) \n connect debug_tsc, _debug_tsc_T_1 \n regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0) \n node _debug_sample_T = add(debug_sample, UInt<1>(0h1)) \n node _debug_sample_T_1 = tail(_debug_sample_T, 1) \n connect debug_sample, _debug_sample_T_1 \n inst plusarg_reader of plusarg_reader_80 \n node _T = sub(plusarg_reader.out, UInt<1>(0h1)) \n node _T_1 = tail(_T, 1) \n node _T_2 = eq(debug_sample, _T_1) \n when _T_2 : \n connect debug_sample, UInt<1>(0h0) \n regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0) \n regreset fired : UInt<1>, clock, reset, UInt<1>(0h0) \n node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid) \n node _util_ctr_T_1 = tail(_util_ctr_T, 1) \n connect util_ctr, _util_ctr_T_1 \n node _fired_T = or(fired, destNodesIn.flit[0].valid) \n connect fired, _fired_T \n node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0)) \n node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1)) \n node _T_5 = tail(_T_4, 1) \n node _T_6 = eq(debug_sample, _T_5) \n node _T_7 = and(_T_3, _T_6) \n node _T_8 = and(_T_7, fired) \n when _T_8 : \n node _T_9 = asUInt(reset) \n node _T_10 = eq(_T_9, UInt<1>(0h0)) \n when _T_10 : \n printf(clock, UInt<1>(0h1), \"nocsample %d 12 3 %d\\n\", debug_tsc, util_ctr) : printf \n connect fired, destNodesIn.flit[0].valid \n node _T_11 = and(ingressNodesIn.flit.ready, ingressNodesIn.flit.valid) \n regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0) \n regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _util_ctr_T_2 = add(util_ctr_1, _T_11) \n node _util_ctr_T_3 = tail(_util_ctr_T_2, 1) \n connect util_ctr_1, _util_ctr_T_3 \n node _fired_T_1 = or(fired_1, _T_11) \n connect fired_1, _fired_T_1 \n node _T_12 = neq(plusarg_reader.out, UInt<1>(0h0)) \n node _T_13 = sub(plusarg_reader.out, UInt<1>(0h1)) \n node _T_14 = tail(_T_13, 1) \n node _T_15 = eq(debug_sample, _T_14) \n node _T_16 = and(_T_12, _T_15) \n node _T_17 = and(_T_16, fired_1) \n when _T_17 : \n node _T_18 = asUInt(reset) \n node _T_19 = eq(_T_18, UInt<1>(0h0)) \n when _T_19 : \n printf(clock, UInt<1>(0h1), \"nocsample %d i7 3 %d\\n\", debug_tsc, util_ctr_1) : printf_1 \n connect fired_1, _T_11 \n node _T_20 = and(ingressNodesIn_1.flit.ready, ingressNodesIn_1.flit.valid) \n regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0) \n regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _util_ctr_T_4 = add(util_ctr_2, _T_20) \n node _util_ctr_T_5 = tail(_util_ctr_T_4, 1) \n connect util_ctr_2, _util_ctr_T_5 \n node _fired_T_2 = or(fired_2, _T_20) \n connect fired_2, _fired_T_2 \n node _T_21 = neq(plusarg_reader.out, UInt<1>(0h0)) \n node _T_22 = sub(plusarg_reader.out, UInt<1>(0h1)) \n node _T_23 = tail(_T_22, 1) \n node _T_24 = eq(debug_sample, _T_23) \n node _T_25 = and(_T_21, _T_24) \n node _T_26 = and(_T_25, fired_2) \n when _T_26 : \n node _T_27 = asUInt(reset) \n node _T_28 = eq(_T_27, UInt<1>(0h0)) \n when _T_28 : \n printf(clock, UInt<1>(0h1), \"nocsample %d i8 3 %d\\n\", debug_tsc, util_ctr_2) : printf_2 \n connect fired_2, _T_20 \n node _T_29 = and(egressNodesOut.flit.ready, egressNodesOut.flit.valid) \n regreset util_ctr_3 : UInt<64>, clock, reset, UInt<64>(0h0) \n regreset fired_3 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _util_ctr_T_6 = add(util_ctr_3, _T_29) \n node _util_ctr_T_7 = tail(_util_ctr_T_6, 1) \n connect util_ctr_3, _util_ctr_T_7 \n node _fired_T_3 = or(fired_3, _T_29) \n connect fired_3, _fired_T_3 \n node _T_30 = neq(plusarg_reader.out, UInt<1>(0h0)) \n node _T_31 = sub(plusarg_reader.out, UInt<1>(0h1)) \n node _T_32 = tail(_T_31, 1) \n node _T_33 = eq(debug_sample, _T_32) \n node _T_34 = and(_T_30, _T_33) \n node _T_35 = and(_T_34, fired_3) \n when _T_35 : \n node _T_36 = asUInt(reset) \n node _T_37 = eq(_T_36, UInt<1>(0h0)) \n when _T_37 : \n printf(clock, UInt<1>(0h1), \"nocsample %d 3 e8 %d\\n\", debug_tsc, util_ctr_3) : printf_3 \n connect fired_3, _T_29 \n node _T_38 = and(egressNodesOut_1.flit.ready, egressNodesOut_1.flit.valid) \n regreset util_ctr_4 : UInt<64>, clock, reset, UInt<64>(0h0) \n regreset fired_4 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _util_ctr_T_8 = add(util_ctr_4, _T_38) \n node _util_ctr_T_9 = tail(_util_ctr_T_8, 1) \n connect util_ctr_4, _util_ctr_T_9 \n node _fired_T_4 = or(fired_4, _T_38) \n connect fired_4, _fired_T_4 \n node _T_39 = neq(plusarg_reader.out, UInt<1>(0h0)) \n node _T_40 = sub(plusarg_reader.out, UInt<1>(0h1)) \n node _T_41 = tail(_T_40, 1) \n node _T_42 = eq(debug_sample, _T_41) \n node _T_43 = and(_T_39, _T_42) \n node _T_44 = and(_T_43, fired_4) \n when _T_44 : \n node _T_45 = asUInt(reset) \n node _T_46 = eq(_T_45, UInt<1>(0h0)) \n when _T_46 : \n printf(clock, UInt<1>(0h1), \"nocsample %d 3 e9 %d\\n\", debug_tsc, util_ctr_4) : printf_4 \n connect fired_4, _T_38 \n node _T_47 = and(egressNodesOut_2.flit.ready, egressNodesOut_2.flit.valid) \n regreset util_ctr_5 : UInt<64>, clock, reset, UInt<64>(0h0) \n regreset fired_5 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _util_ctr_T_10 = add(util_ctr_5, _T_47) \n node _util_ctr_T_11 = tail(_util_ctr_T_10, 1) \n connect util_ctr_5, _util_ctr_T_11 \n node _fired_T_5 = or(fired_5, _T_47) \n connect fired_5, _fired_T_5 \n node _T_48 = neq(plusarg_reader.out, UInt<1>(0h0)) \n node _T_49 = sub(plusarg_reader.out, UInt<1>(0h1)) \n node _T_50 = tail(_T_49, 1) \n node _T_51 = eq(debug_sample, _T_50) \n node _T_52 = and(_T_48, _T_51) \n node _T_53 = and(_T_52, fired_5) \n when _T_53 : \n node _T_54 = asUInt(reset) \n node _T_55 = eq(_T_54, UInt<1>(0h0)) \n when _T_55 : \n printf(clock, UInt<1>(0h1), \"nocsample %d 3 e10 %d\\n\", debug_tsc, util_ctr_5) : printf_5 \n connect fired_5, _T_47"},"response":{"kind":"string","value":"module Router_32(\t// @[Router.scala:89:25]\n input clock,\t// @[Router.scala:89:25]\n input reset,\t// @[Router.scala:89:25]\n output [2:0] auto_debug_out_va_stall_0,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_debug_out_va_stall_2,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_debug_out_sa_stall_0,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_debug_out_sa_stall_2,\t// @[LazyModuleImp.scala:107:25]\n input auto_egress_nodes_out_2_flit_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_egress_nodes_out_2_flit_valid,\t// @[LazyModuleImp.scala:107:25]\n output auto_egress_nodes_out_2_flit_bits_head,\t// @[LazyModuleImp.scala:107:25]\n output auto_egress_nodes_out_2_flit_bits_tail,\t// @[LazyModuleImp.scala:107:25]\n input auto_egress_nodes_out_1_flit_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_egress_nodes_out_1_flit_valid,\t// @[LazyModuleImp.scala:107:25]\n output auto_egress_nodes_out_1_flit_bits_head,\t// @[LazyModuleImp.scala:107:25]\n output auto_egress_nodes_out_1_flit_bits_tail,\t// @[LazyModuleImp.scala:107:25]\n input auto_egress_nodes_out_0_flit_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_egress_nodes_out_0_flit_valid,\t// @[LazyModuleImp.scala:107:25]\n output auto_egress_nodes_out_0_flit_bits_head,\t// @[LazyModuleImp.scala:107:25]\n output auto_egress_nodes_out_0_flit_bits_tail,\t// @[LazyModuleImp.scala:107:25]\n output [72:0] auto_egress_nodes_out_0_flit_bits_payload,\t// @[LazyModuleImp.scala:107:25]\n output auto_ingress_nodes_in_1_flit_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_ingress_nodes_in_1_flit_valid,\t// @[LazyModuleImp.scala:107:25]\n input auto_ingress_nodes_in_1_flit_bits_head,\t// @[LazyModuleImp.scala:107:25]\n input auto_ingress_nodes_in_1_flit_bits_tail,\t// @[LazyModuleImp.scala:107:25]\n input [72:0] auto_ingress_nodes_in_1_flit_bits_payload,\t// @[LazyModuleImp.scala:107:25]\n output auto_source_nodes_out_flit_0_valid,\t// @[LazyModuleImp.scala:107:25]\n output auto_source_nodes_out_flit_0_bits_head,\t// @[LazyModuleImp.scala:107:25]\n output auto_source_nodes_out_flit_0_bits_tail,\t// @[LazyModuleImp.scala:107:25]\n output [72:0] auto_source_nodes_out_flit_0_bits_payload,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_source_nodes_out_flit_0_bits_flow_vnet_id,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node_id,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_source_nodes_out_flit_0_bits_flow_egress_node,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_source_nodes_out_flit_0_bits_flow_egress_node_id,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_source_nodes_out_flit_0_bits_virt_channel_id,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_source_nodes_out_credit_return,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_source_nodes_out_vc_free,\t// @[LazyModuleImp.scala:107:25]\n input auto_dest_nodes_in_flit_0_valid,\t// @[LazyModuleImp.scala:107:25]\n input auto_dest_nodes_in_flit_0_bits_head,\t// @[LazyModuleImp.scala:107:25]\n input auto_dest_nodes_in_flit_0_bits_tail,\t// @[LazyModuleImp.scala:107:25]\n input [72:0] auto_dest_nodes_in_flit_0_bits_payload,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_dest_nodes_in_flit_0_bits_flow_vnet_id,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node_id,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_dest_nodes_in_flit_0_bits_virt_channel_id,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_dest_nodes_in_credit_return,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_dest_nodes_in_vc_free\t// @[LazyModuleImp.scala:107:25]\n);\n\n wire [19:0] _plusarg_reader_out;\t// @[PlusArg.scala:80:11]\n wire _vc_allocator_io_req_2_ready;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_req_0_ready;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_2_vc_sel_3_0;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_2_vc_sel_2_0;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_2_vc_sel_1_0;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_2_vc_sel_0_0;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_2_vc_sel_0_1;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_2_vc_sel_0_2;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_2_vc_sel_0_3;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_2_vc_sel_0_4;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_0_vc_sel_3_0;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_0_vc_sel_2_0;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_resp_0_vc_sel_1_0;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_out_allocs_3_0_alloc;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_out_allocs_2_0_alloc;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_out_allocs_1_0_alloc;\t// @[Router.scala:133:30]\n wire _vc_allocator_io_out_allocs_0_1_alloc;\t// @[Router.scala:133:30]\n wire _switch_allocator_io_req_2_0_ready;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_req_0_0_ready;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_credit_alloc_3_0_alloc;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_credit_alloc_3_0_tail;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_credit_alloc_2_0_alloc;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_credit_alloc_2_0_tail;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_credit_alloc_1_0_alloc;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_credit_alloc_1_0_tail;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_credit_alloc_0_1_alloc;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_switch_sel_3_0_2_0;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_switch_sel_3_0_0_0;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_switch_sel_2_0_2_0;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_switch_sel_2_0_0_0;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_switch_sel_1_0_2_0;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_switch_sel_1_0_0_0;\t// @[Router.scala:132:34]\n wire _switch_allocator_io_switch_sel_0_0_2_0;\t// @[Router.scala:132:34]\n wire _switch_io_out_3_0_valid;\t// @[Router.scala:131:24]\n wire _switch_io_out_3_0_bits_head;\t// @[Router.scala:131:24]\n wire _switch_io_out_3_0_bits_tail;\t// @[Router.scala:131:24]\n wire [72:0] _switch_io_out_3_0_bits_payload;\t// @[Router.scala:131:24]\n wire _switch_io_out_2_0_valid;\t// @[Router.scala:131:24]\n wire _switch_io_out_2_0_bits_head;\t// @[Router.scala:131:24]\n wire _switch_io_out_2_0_bits_tail;\t// @[Router.scala:131:24]\n wire [72:0] _switch_io_out_2_0_bits_payload;\t// @[Router.scala:131:24]\n wire _switch_io_out_1_0_valid;\t// @[Router.scala:131:24]\n wire _switch_io_out_1_0_bits_head;\t// @[Router.scala:131:24]\n wire _switch_io_out_1_0_bits_tail;\t// @[Router.scala:131:24]\n wire [72:0] _switch_io_out_1_0_bits_payload;\t// @[Router.scala:131:24]\n wire _switch_io_out_0_0_valid;\t// @[Router.scala:131:24]\n wire _switch_io_out_0_0_bits_head;\t// @[Router.scala:131:24]\n wire _switch_io_out_0_0_bits_tail;\t// @[Router.scala:131:24]\n wire [72:0] _switch_io_out_0_0_bits_payload;\t// @[Router.scala:131:24]\n wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id;\t// @[Router.scala:131:24]\n wire [4:0] _switch_io_out_0_0_bits_flow_ingress_node;\t// @[Router.scala:131:24]\n wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id;\t// @[Router.scala:131:24]\n wire [4:0] _switch_io_out_0_0_bits_flow_egress_node;\t// @[Router.scala:131:24]\n wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id;\t// @[Router.scala:131:24]\n wire [2:0] _switch_io_out_0_0_bits_virt_channel_id;\t// @[Router.scala:131:24]\n wire _egress_unit_3_to_10_io_credit_available_0;\t// @[Router.scala:125:13]\n wire _egress_unit_3_to_10_io_channel_status_0_occupied;\t// @[Router.scala:125:13]\n wire _egress_unit_3_to_10_io_out_valid;\t// @[Router.scala:125:13]\n wire _egress_unit_2_to_9_io_credit_available_0;\t// @[Router.scala:125:13]\n wire _egress_unit_2_to_9_io_channel_status_0_occupied;\t// @[Router.scala:125:13]\n wire _egress_unit_2_to_9_io_out_valid;\t// @[Router.scala:125:13]\n wire _egress_unit_1_to_8_io_credit_available_0;\t// @[Router.scala:125:13]\n wire _egress_unit_1_to_8_io_channel_status_0_occupied;\t// @[Router.scala:125:13]\n wire _egress_unit_1_to_8_io_out_valid;\t// @[Router.scala:125:13]\n wire _output_unit_0_to_12_io_credit_available_1;\t// @[Router.scala:122:13]\n wire _output_unit_0_to_12_io_channel_status_1_occupied;\t// @[Router.scala:122:13]\n wire _ingress_unit_2_from_8_io_vcalloc_req_valid;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_8_io_vcalloc_req_bits_vc_sel_3_0;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_8_io_vcalloc_req_bits_vc_sel_2_0;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_8_io_vcalloc_req_bits_vc_sel_1_0;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_8_io_vcalloc_req_bits_vc_sel_0_0;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_8_io_vcalloc_req_bits_vc_sel_0_1;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_8_io_vcalloc_req_bits_vc_sel_0_2;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_8_io_vcalloc_req_bits_vc_sel_0_3;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_8_io_vcalloc_req_bits_vc_sel_0_4;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_8_io_salloc_req_0_valid;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_8_io_salloc_req_0_bits_vc_sel_3_0;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_8_io_salloc_req_0_bits_vc_sel_2_0;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_8_io_salloc_req_0_bits_vc_sel_1_0;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_8_io_salloc_req_0_bits_vc_sel_0_0;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_8_io_salloc_req_0_bits_vc_sel_0_1;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_8_io_salloc_req_0_bits_vc_sel_0_2;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_8_io_salloc_req_0_bits_vc_sel_0_3;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_8_io_salloc_req_0_bits_vc_sel_0_4;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_8_io_salloc_req_0_bits_tail;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_8_io_out_0_valid;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_8_io_out_0_bits_flit_head;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_8_io_out_0_bits_flit_tail;\t// @[Router.scala:116:13]\n wire [72:0] _ingress_unit_2_from_8_io_out_0_bits_flit_payload;\t// @[Router.scala:116:13]\n wire [2:0] _ingress_unit_2_from_8_io_out_0_bits_flit_flow_vnet_id;\t// @[Router.scala:116:13]\n wire [4:0] _ingress_unit_2_from_8_io_out_0_bits_flit_flow_ingress_node;\t// @[Router.scala:116:13]\n wire [1:0] _ingress_unit_2_from_8_io_out_0_bits_flit_flow_ingress_node_id;\t// @[Router.scala:116:13]\n wire [4:0] _ingress_unit_2_from_8_io_out_0_bits_flit_flow_egress_node;\t// @[Router.scala:116:13]\n wire [1:0] _ingress_unit_2_from_8_io_out_0_bits_flit_flow_egress_node_id;\t// @[Router.scala:116:13]\n wire [2:0] _ingress_unit_2_from_8_io_out_0_bits_out_virt_channel;\t// @[Router.scala:116:13]\n wire _ingress_unit_2_from_8_io_in_ready;\t// @[Router.scala:116:13]\n wire _input_unit_0_from_12_io_vcalloc_req_valid;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_12_io_vcalloc_req_bits_vc_sel_3_0;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_12_io_vcalloc_req_bits_vc_sel_2_0;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_12_io_vcalloc_req_bits_vc_sel_1_0;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_12_io_salloc_req_0_valid;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_12_io_salloc_req_0_bits_vc_sel_3_0;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_12_io_salloc_req_0_bits_vc_sel_2_0;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_12_io_salloc_req_0_bits_vc_sel_1_0;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_12_io_salloc_req_0_bits_tail;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_12_io_out_0_valid;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_12_io_out_0_bits_flit_head;\t// @[Router.scala:112:13]\n wire _input_unit_0_from_12_io_out_0_bits_flit_tail;\t// @[Router.scala:112:13]\n wire [72:0] _input_unit_0_from_12_io_out_0_bits_flit_payload;\t// @[Router.scala:112:13]\n wire [2:0] _input_unit_0_from_12_io_out_0_bits_flit_flow_vnet_id;\t// @[Router.scala:112:13]\n wire [4:0] _input_unit_0_from_12_io_out_0_bits_flit_flow_ingress_node;\t// @[Router.scala:112:13]\n wire [1:0] _input_unit_0_from_12_io_out_0_bits_flit_flow_ingress_node_id;\t// @[Router.scala:112:13]\n wire [4:0] _input_unit_0_from_12_io_out_0_bits_flit_flow_egress_node;\t// @[Router.scala:112:13]\n wire [1:0] _input_unit_0_from_12_io_out_0_bits_flit_flow_egress_node_id;\t// @[Router.scala:112:13]\n wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_2_ready & _ingress_unit_2_from_8_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_12_io_vcalloc_req_valid};\t// @[Decoupled.scala:51:35]\n reg REG_3_0_2_0;\t// @[Router.scala:178:14]\n reg REG_3_0_0_0;\t// @[Router.scala:178:14]\n reg REG_2_0_2_0;\t// @[Router.scala:178:14]\n reg REG_2_0_0_0;\t// @[Router.scala:178:14]\n reg REG_1_0_2_0;\t// @[Router.scala:178:14]\n reg REG_1_0_0_0;\t// @[Router.scala:178:14]\n reg REG_0_0_2_0;\t// @[Router.scala:178:14]\n reg [63:0] debug_tsc;\t// @[Router.scala:195:28]\n reg [63:0] debug_sample;\t// @[Router.scala:197:31]\n wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1};\t// @[PlusArg.scala:80:11]\n reg [63:0] util_ctr;\t// @[Router.scala:203:29]\n reg fired;\t// @[Router.scala:204:26]\n wire _GEN_0 = (|_plusarg_reader_out) & _GEN;\t// @[PlusArg.scala:80:11]\n wire _GEN_1 = _GEN_0 & fired;\t// @[Router.scala:204:26, :207:{33,71}]\n reg [63:0] util_ctr_2;\t// @[Router.scala:203:29]\n reg fired_2;\t// @[Router.scala:204:26]\n wire _GEN_2 = _GEN_0 & fired_2;\t// @[Router.scala:204:26, :207:{33,71}]\n reg [63:0] util_ctr_3;\t// @[Router.scala:203:29]\n reg fired_3;\t// @[Router.scala:204:26]\n wire _GEN_3 = _GEN_0 & fired_3;\t// @[Router.scala:204:26, :207:{33,71}]\n reg [63:0] util_ctr_4;\t// @[Router.scala:203:29]\n reg fired_4;\t// @[Router.scala:204:26]\n wire _GEN_4 = _GEN_0 & fired_4;\t// @[Router.scala:204:26, :207:{33,71}]\n reg [63:0] util_ctr_5;\t// @[Router.scala:203:29]\n reg fired_5;\t// @[Router.scala:204:26]\n wire _GEN_5 = _GEN_0 & fired_5;\t// @[Router.scala:204:26, :207:{33,71}]"}}},{"rowIdx":34187,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module PE_261 : \n input clock : Clock \n input reset : Reset \n output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} \n\n\n inst mac_unit of MacUnit_5 \n connect mac_unit.clock, clock\n\n connect mac_unit.reset, reset\n\n reg c1 : SInt<8>, clock \n reg c2 : SInt<8>, clock \n connect io.out_a, io.in_a \n connect io.out_control.dataflow, io.in_control.dataflow \n connect io.out_control.propagate, io.in_control.propagate \n connect io.out_control.shift, io.in_control.shift \n connect io.out_id, io.in_id \n connect io.out_last, io.in_last \n connect io.out_valid, io.in_valid \n connect mac_unit.io.in_a, io.in_a \n reg last_s : UInt<1>, clock \n when io.in_valid : \n connect last_s, io.in_control.propagate \n node flip = neq(last_s, io.in_control.propagate) \n node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) \n connect io.bad_dataflow, UInt<1>(0h0) \n node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) \n node _T_1 = and(UInt<1>(0h0), _T) \n node _T_2 = or(UInt<1>(0h0), _T_1) \n when _T_2 : \n node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) \n when _T_3 : \n node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) \n node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) \n node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) \n node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) \n node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) \n node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) \n node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) \n node _io_out_c_zeros_T_1 = asUInt(c1) \n node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) \n node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) \n node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) \n node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) \n node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) \n node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) \n node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) \n node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) \n node _io_out_c_ones_digit_T = dshr(c1, shift_offset) \n node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) \n node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) \n node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) \n node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) \n node _io_out_c_T = dshr(c1, shift_offset) \n node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) \n node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) \n node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) \n node _io_out_c_T_4 = asSInt(_io_out_c_T_3) \n node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) \n node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) \n node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) \n node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) \n node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) \n node _io_out_c_T_10 = asSInt(_io_out_c_T_9) \n connect io.out_c, _io_out_c_T_10 \n connect io.out_b, io.in_b \n wire _mac_unit_io_in_b_WIRE : SInt<8> \n node _mac_unit_io_in_b_T = asUInt(io.in_b) \n node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) \n connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 \n connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE \n connect mac_unit.io.in_c, c2 \n connect c2, mac_unit.io.out_d \n node _c1_T = bits(io.in_d, 7, 0) \n node _c1_T_1 = asSInt(_c1_T) \n connect c1, _c1_T_1 \n else :\n\n node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) \n node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) \n node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) \n node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) \n node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) \n node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) \n node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) \n node _io_out_c_zeros_T_10 = asUInt(c2) \n node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) \n node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) \n node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) \n node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) \n node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) \n node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) \n node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) \n node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) \n node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) \n node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) \n node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) \n node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) \n node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) \n node _io_out_c_T_11 = dshr(c2, shift_offset) \n node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) \n node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) \n node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) \n node _io_out_c_T_15 = asSInt(_io_out_c_T_14) \n node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) \n node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) \n node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) \n node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) \n node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) \n node _io_out_c_T_21 = asSInt(_io_out_c_T_20) \n connect io.out_c, _io_out_c_T_21 \n connect io.out_b, io.in_b \n wire _mac_unit_io_in_b_WIRE_1 : SInt<8> \n node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) \n node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) \n connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 \n connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 \n connect mac_unit.io.in_c, c1 \n connect c1, mac_unit.io.out_d \n node _c2_T = bits(io.in_d, 7, 0) \n node _c2_T_1 = asSInt(_c2_T) \n connect c2, _c2_T_1 \n else :\n\n node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) \n node _T_5 = and(UInt<1>(0h0), _T_4) \n node _T_6 = or(UInt<1>(0h1), _T_5) \n when _T_6 : \n node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) \n when _T_7 : \n connect io.out_c, c1 \n wire _mac_unit_io_in_b_WIRE_2 : SInt<8> \n node _mac_unit_io_in_b_T_4 = asUInt(c2) \n node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) \n connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 \n connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 \n connect mac_unit.io.in_c, io.in_b \n connect io.out_b, mac_unit.io.out_d \n connect c1, io.in_d \n else :\n\n connect io.out_c, c2 \n wire _mac_unit_io_in_b_WIRE_3 : SInt<8> \n node _mac_unit_io_in_b_T_6 = asUInt(c1) \n node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) \n connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 \n connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 \n connect mac_unit.io.in_c, io.in_b \n connect io.out_b, mac_unit.io.out_d \n connect c2, io.in_d \n else :\n\n connect io.bad_dataflow, UInt<1>(0h1) \n invalidate io.out_c \n invalidate io.out_b \n wire _mac_unit_io_in_b_WIRE_4 : SInt<8> \n node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) \n node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) \n connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 \n connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 \n connect mac_unit.io.in_c, c2 \n node _T_8 = eq(io.in_valid, UInt<1>(0h0)) \n when _T_8 : \n connect c1, c1 \n connect c2, c2 \n invalidate mac_unit.io.in_b \n invalidate mac_unit.io.in_c"},"response":{"kind":"string","value":"module PE_261(\t// @[PE.scala:31:7]\n input clock,\t// @[PE.scala:31:7]\n input reset,\t// @[PE.scala:31:7]\n input [7:0] io_in_a,\t// @[PE.scala:35:14]\n input [19:0] io_in_b,\t// @[PE.scala:35:14]\n input [19:0] io_in_d,\t// @[PE.scala:35:14]\n output [7:0] io_out_a,\t// @[PE.scala:35:14]\n output [19:0] io_out_b,\t// @[PE.scala:35:14]\n output [19:0] io_out_c,\t// @[PE.scala:35:14]\n input io_in_control_dataflow,\t// @[PE.scala:35:14]\n input io_in_control_propagate,\t// @[PE.scala:35:14]\n input [4:0] io_in_control_shift,\t// @[PE.scala:35:14]\n output io_out_control_dataflow,\t// @[PE.scala:35:14]\n output io_out_control_propagate,\t// @[PE.scala:35:14]\n output [4:0] io_out_control_shift,\t// @[PE.scala:35:14]\n input [2:0] io_in_id,\t// @[PE.scala:35:14]\n output [2:0] io_out_id,\t// @[PE.scala:35:14]\n input io_in_last,\t// @[PE.scala:35:14]\n output io_out_last,\t// @[PE.scala:35:14]\n input io_in_valid,\t// @[PE.scala:35:14]\n output io_out_valid\t// @[PE.scala:35:14]\n);\n\n wire [7:0] io_in_a_0 = io_in_a;\t// @[PE.scala:31:7]\n wire [19:0] io_in_b_0 = io_in_b;\t// @[PE.scala:31:7]\n wire [19:0] io_in_d_0 = io_in_d;\t// @[PE.scala:31:7]\n wire io_in_control_dataflow_0 = io_in_control_dataflow;\t// @[PE.scala:31:7]\n wire io_in_control_propagate_0 = io_in_control_propagate;\t// @[PE.scala:31:7]\n wire [4:0] io_in_control_shift_0 = io_in_control_shift;\t// @[PE.scala:31:7]\n wire [2:0] io_in_id_0 = io_in_id;\t// @[PE.scala:31:7]\n wire io_in_last_0 = io_in_last;\t// @[PE.scala:31:7]\n wire io_in_valid_0 = io_in_valid;\t// @[PE.scala:31:7]\n wire io_bad_dataflow = 1'h0;\t// @[PE.scala:31:7]\n wire _io_out_c_T_5 = 1'h0;\t// @[Arithmetic.scala:125:33]\n wire _io_out_c_T_6 = 1'h0;\t// @[Arithmetic.scala:125:60]\n wire _io_out_c_T_16 = 1'h0;\t// @[Arithmetic.scala:125:33]\n wire _io_out_c_T_17 = 1'h0;\t// @[Arithmetic.scala:125:60]\n wire [7:0] io_out_a_0 = io_in_a_0;\t// @[PE.scala:31:7]\n wire [19:0] _mac_unit_io_in_b_T = io_in_b_0;\t// @[PE.scala:31:7, :106:37]\n wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0;\t// @[PE.scala:31:7, :113:37]\n wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0;\t// @[PE.scala:31:7, :137:35]\n wire io_out_control_dataflow_0 = io_in_control_dataflow_0;\t// @[PE.scala:31:7]\n wire io_out_control_propagate_0 = io_in_control_propagate_0;\t// @[PE.scala:31:7]\n wire [4:0] io_out_control_shift_0 = io_in_control_shift_0;\t// @[PE.scala:31:7]\n wire [2:0] io_out_id_0 = io_in_id_0;\t// @[PE.scala:31:7]\n wire io_out_last_0 = io_in_last_0;\t// @[PE.scala:31:7]\n wire io_out_valid_0 = io_in_valid_0;\t// @[PE.scala:31:7]\n wire [19:0] io_out_b_0;\t// @[PE.scala:31:7]\n wire [19:0] io_out_c_0;\t// @[PE.scala:31:7]\n reg [7:0] c1;\t// @[PE.scala:70:15]\n wire [7:0] _io_out_c_zeros_T_1 = c1;\t// @[PE.scala:70:15]\n wire [7:0] _mac_unit_io_in_b_T_6 = c1;\t// @[PE.scala:70:15, :127:38]\n reg [7:0] c2;\t// @[PE.scala:71:15]\n wire [7:0] _io_out_c_zeros_T_10 = c2;\t// @[PE.scala:71:15]\n wire [7:0] _mac_unit_io_in_b_T_4 = c2;\t// @[PE.scala:71:15, :121:38]\n reg last_s;\t// @[PE.scala:89:25]\n wire flip = last_s != io_in_control_propagate_0;\t// @[PE.scala:31:7, :89:25, :90:21]\n wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0;\t// @[PE.scala:31:7, :90:21, :91:25]\n wire _GEN = shift_offset == 5'h0;\t// @[PE.scala:91:25]\n wire _io_out_c_point_five_T;\t// @[Arithmetic.scala:101:32]\n assign _io_out_c_point_five_T = _GEN;\t// @[Arithmetic.scala:101:32]\n wire _io_out_c_point_five_T_5;\t// @[Arithmetic.scala:101:32]\n assign _io_out_c_point_five_T_5 = _GEN;\t// @[Arithmetic.scala:101:32]\n wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1;\t// @[PE.scala:91:25]\n wire [5:0] _io_out_c_point_five_T_1;\t// @[Arithmetic.scala:101:53]\n assign _io_out_c_point_five_T_1 = _GEN_0;\t// @[Arithmetic.scala:101:53]\n wire [5:0] _io_out_c_zeros_T_2;\t// @[Arithmetic.scala:102:66]\n assign _io_out_c_zeros_T_2 = _GEN_0;\t// @[Arithmetic.scala:101:53, :102:66]\n wire [5:0] _io_out_c_point_five_T_6;\t// @[Arithmetic.scala:101:53]\n assign _io_out_c_point_five_T_6 = _GEN_0;\t// @[Arithmetic.scala:101:53]\n wire [5:0] _io_out_c_zeros_T_11;\t// @[Arithmetic.scala:102:66]\n assign _io_out_c_zeros_T_11 = _GEN_0;\t// @[Arithmetic.scala:101:53, :102:66]\n wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0];\t// @[Arithmetic.scala:101:53]\n wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2);\t// @[PE.scala:70:15]\n wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0];\t// @[Arithmetic.scala:101:50]\n wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4;\t// @[Arithmetic.scala:101:{29,32,50}]\n wire _GEN_1 = shift_offset < 5'h2;\t// @[PE.scala:91:25]\n wire _io_out_c_zeros_T;\t// @[Arithmetic.scala:102:27]\n assign _io_out_c_zeros_T = _GEN_1;\t// @[Arithmetic.scala:102:27]\n wire _io_out_c_zeros_T_9;\t// @[Arithmetic.scala:102:27]\n assign _io_out_c_zeros_T_9 = _GEN_1;\t// @[Arithmetic.scala:102:27]\n wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0];\t// @[Arithmetic.scala:102:66]\n wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3;\t// @[Arithmetic.scala:102:{60,66}]\n wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1;\t// @[Arithmetic.scala:102:{60,81}]\n wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0];\t// @[Arithmetic.scala:102:81]\n wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1};\t// @[Arithmetic.scala:102:{45,52,81}]\n wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7;\t// @[Arithmetic.scala:102:{24,27,52}]\n wire io_out_c_zeros = |_io_out_c_zeros_T_8;\t// @[Arithmetic.scala:102:{24,89}]\n wire [7:0] _GEN_2 = {3'h0, shift_offset};\t// @[PE.scala:91:25]\n wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2);\t// @[PE.scala:70:15]\n wire [7:0] _io_out_c_ones_digit_T;\t// @[Arithmetic.scala:103:30]\n assign _io_out_c_ones_digit_T = _GEN_3;\t// @[Arithmetic.scala:103:30]\n wire [7:0] _io_out_c_T;\t// @[Arithmetic.scala:107:15]\n assign _io_out_c_T = _GEN_3;\t// @[Arithmetic.scala:103:30, :107:15]\n wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0];\t// @[Arithmetic.scala:103:30]\n wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit;\t// @[Arithmetic.scala:102:89, :103:30, :105:38]\n wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T;\t// @[Arithmetic.scala:101:29, :105:{29,38}]\n wire io_out_c_r = _io_out_c_r_T_1;\t// @[Arithmetic.scala:105:{29,53}]\n wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r};\t// @[Arithmetic.scala:105:53, :107:33]\n wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1};\t// @[Arithmetic.scala:107:{15,28,33}]\n wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0];\t// @[Arithmetic.scala:107:28]\n wire [7:0] _io_out_c_T_4 = _io_out_c_T_3;\t// @[Arithmetic.scala:107:28]\n wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4};\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_8 = _io_out_c_T_7;\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_9 = _io_out_c_T_8;\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_10 = _io_out_c_T_9;\t// @[Arithmetic.scala:125:{81,99}]\n wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T;\t// @[PE.scala:106:37]\n wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0];\t// @[PE.scala:106:37]\n wire [7:0] _c1_T = io_in_d_0[7:0];\t// @[PE.scala:31:7]\n wire [7:0] _c2_T = io_in_d_0[7:0];\t// @[PE.scala:31:7]\n wire [7:0] _c1_T_1 = _c1_T;\t// @[Arithmetic.scala:114:{15,33}]\n wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0];\t// @[Arithmetic.scala:101:53]\n wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7);\t// @[PE.scala:71:15]\n wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0];\t// @[Arithmetic.scala:101:50]\n wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9;\t// @[Arithmetic.scala:101:{29,32,50}]\n wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0];\t// @[Arithmetic.scala:102:66]\n wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12;\t// @[Arithmetic.scala:102:{60,66}]\n wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1;\t// @[Arithmetic.scala:102:{60,81}]\n wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0];\t// @[Arithmetic.scala:102:81]\n wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10};\t// @[Arithmetic.scala:102:{45,52,81}]\n wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16;\t// @[Arithmetic.scala:102:{24,27,52}]\n wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17;\t// @[Arithmetic.scala:102:{24,89}]\n wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2);\t// @[PE.scala:71:15]\n wire [7:0] _io_out_c_ones_digit_T_1;\t// @[Arithmetic.scala:103:30]\n assign _io_out_c_ones_digit_T_1 = _GEN_4;\t// @[Arithmetic.scala:103:30]\n wire [7:0] _io_out_c_T_11;\t// @[Arithmetic.scala:107:15]\n assign _io_out_c_T_11 = _GEN_4;\t// @[Arithmetic.scala:103:30, :107:15]\n wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0];\t// @[Arithmetic.scala:103:30]\n wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1;\t// @[Arithmetic.scala:102:89, :103:30, :105:38]\n wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2;\t// @[Arithmetic.scala:101:29, :105:{29,38}]\n wire io_out_c_r_1 = _io_out_c_r_T_3;\t// @[Arithmetic.scala:105:{29,53}]\n wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1};\t// @[Arithmetic.scala:105:53, :107:33]\n wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12};\t// @[Arithmetic.scala:107:{15,28,33}]\n wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0];\t// @[Arithmetic.scala:107:28]\n wire [7:0] _io_out_c_T_15 = _io_out_c_T_14;\t// @[Arithmetic.scala:107:28]\n wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15};\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_19 = _io_out_c_T_18;\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_20 = _io_out_c_T_19;\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_21 = _io_out_c_T_20;\t// @[Arithmetic.scala:125:{81,99}]\n wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2;\t// @[PE.scala:113:37]\n wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0];\t// @[PE.scala:113:37]\n wire [7:0] _c2_T_1 = _c2_T;\t// @[Arithmetic.scala:114:{15,33}]\n wire [7:0] _mac_unit_io_in_b_T_5;\t// @[PE.scala:121:38]\n assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4;\t// @[PE.scala:121:38]\n wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5;\t// @[PE.scala:121:38]\n assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2};\t// @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]\n wire [7:0] _mac_unit_io_in_b_T_7;\t// @[PE.scala:127:38]\n assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6;\t// @[PE.scala:127:38]\n wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7;\t// @[PE.scala:127:38]\n wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8;\t// @[PE.scala:137:35]\n wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0];\t// @[PE.scala:137:35]\n always @(posedge clock) begin\t// @[PE.scala:31:7]\n if (io_in_valid_0 & io_in_control_propagate_0)\t// @[PE.scala:31:7, :102:95, :141:17, :142:8]\n c1 <= io_in_d_0[7:0];\t// @[PE.scala:31:7, :70:15]\n if (~(~io_in_valid_0 | io_in_control_propagate_0))\t// @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]\n c2 <= io_in_d_0[7:0];\t// @[PE.scala:31:7, :71:15]\n if (io_in_valid_0)\t// @[PE.scala:31:7]\n last_s <= io_in_control_propagate_0;\t// @[PE.scala:31:7, :89:25]\n always @(posedge)\n MacUnit_5 mac_unit (\t// @[PE.scala:64:24]\n .clock (clock),\n .reset (reset),\n .io_in_a (io_in_a_0),\t// @[PE.scala:31:7]\n .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3),\t// @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]\n .io_in_c (io_in_b_0),\t// @[PE.scala:31:7]\n .io_out_d (io_out_b_0)\n );\t// @[PE.scala:64:24]\n assign io_out_a = io_out_a_0;\t// @[PE.scala:31:7]\n assign io_out_b = io_out_b_0;\t// @[PE.scala:31:7]\n assign io_out_c = io_out_c_0;\t// @[PE.scala:31:7]\n assign io_out_control_dataflow = io_out_control_dataflow_0;\t// @[PE.scala:31:7]\n assign io_out_control_propagate = io_out_control_propagate_0;\t// @[PE.scala:31:7]\n assign io_out_control_shift = io_out_control_shift_0;\t// @[PE.scala:31:7]\n assign io_out_id = io_out_id_0;\t// @[PE.scala:31:7]\n assign io_out_last = io_out_last_0;\t// @[PE.scala:31:7]\n assign io_out_valid = io_out_valid_0;\t// @[PE.scala:31:7]\nendmodule"}}},{"rowIdx":34188,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_342 : \n input clock : Clock \n input reset : AsyncReset \n output io : { flip d : UInt<1>, q : UInt<1>} \n\n\n regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) \n regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) \n regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _sync_2_T = bits(io.d, 0, 0) \n connect sync_2, _sync_2_T \n connect sync_0, sync_1 \n connect sync_1, sync_2 \n connect io.q, sync_0"},"response":{"kind":"string","value":"module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_342(\t// @[SynchronizerReg.scala:68:19]\n input clock,\t// @[SynchronizerReg.scala:68:19]\n input reset,\t// @[SynchronizerReg.scala:68:19]\n output io_q\t// @[ShiftReg.scala:36:14]\n);\n\n wire io_d = 1'h1;\t// @[SynchronizerReg.scala:54:22, :68:19]\n wire _sync_2_T = 1'h1;\t// @[SynchronizerReg.scala:54:22, :68:19]\n wire io_q_0;\t// @[SynchronizerReg.scala:68:19]\n reg sync_0;\t// @[SynchronizerReg.scala:51:87]\n assign io_q_0 = sync_0;\t// @[SynchronizerReg.scala:51:87, :68:19]\n reg sync_1;\t// @[SynchronizerReg.scala:51:87]\n reg sync_2;\t// @[SynchronizerReg.scala:51:87]\n always @(posedge clock or posedge reset) begin\t// @[SynchronizerReg.scala:68:19]\n if (reset) begin\t// @[SynchronizerReg.scala:68:19]\n sync_0 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n sync_1 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n sync_2 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n end\n else begin\t// @[SynchronizerReg.scala:68:19]\n sync_0 <= sync_1;\t// @[SynchronizerReg.scala:51:87]\n sync_1 <= sync_2;\t// @[SynchronizerReg.scala:51:87]\n sync_2 <= 1'h1;\t// @[SynchronizerReg.scala:51:87, :54:22, :68:19]\n end\n always @(posedge, posedge)"}}},{"rowIdx":34189,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i64_e11_s53_2 : \n output io : { flip signedIn : UInt<1>, flip in : UInt<64>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>} \n\n\n node _intAsRawFloat_sign_T = bits(io.in, 63, 63) \n node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T) \n node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in) \n node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1) \n node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in) \n node _intAsRawFloat_extAbsIn_T = cat(UInt<64>(0h0), intAsRawFloat_absIn) \n node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 63, 0) \n node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0) \n node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1) \n node _intAsRawFloat_adjustedNormDist_T_2 = bits(intAsRawFloat_extAbsIn, 2, 2) \n node _intAsRawFloat_adjustedNormDist_T_3 = bits(intAsRawFloat_extAbsIn, 3, 3) \n node _intAsRawFloat_adjustedNormDist_T_4 = bits(intAsRawFloat_extAbsIn, 4, 4) \n node _intAsRawFloat_adjustedNormDist_T_5 = bits(intAsRawFloat_extAbsIn, 5, 5) \n node _intAsRawFloat_adjustedNormDist_T_6 = bits(intAsRawFloat_extAbsIn, 6, 6) \n node _intAsRawFloat_adjustedNormDist_T_7 = bits(intAsRawFloat_extAbsIn, 7, 7) \n node _intAsRawFloat_adjustedNormDist_T_8 = bits(intAsRawFloat_extAbsIn, 8, 8) \n node _intAsRawFloat_adjustedNormDist_T_9 = bits(intAsRawFloat_extAbsIn, 9, 9) \n node _intAsRawFloat_adjustedNormDist_T_10 = bits(intAsRawFloat_extAbsIn, 10, 10) \n node _intAsRawFloat_adjustedNormDist_T_11 = bits(intAsRawFloat_extAbsIn, 11, 11) \n node _intAsRawFloat_adjustedNormDist_T_12 = bits(intAsRawFloat_extAbsIn, 12, 12) \n node _intAsRawFloat_adjustedNormDist_T_13 = bits(intAsRawFloat_extAbsIn, 13, 13) \n node _intAsRawFloat_adjustedNormDist_T_14 = bits(intAsRawFloat_extAbsIn, 14, 14) \n node _intAsRawFloat_adjustedNormDist_T_15 = bits(intAsRawFloat_extAbsIn, 15, 15) \n node _intAsRawFloat_adjustedNormDist_T_16 = bits(intAsRawFloat_extAbsIn, 16, 16) \n node _intAsRawFloat_adjustedNormDist_T_17 = bits(intAsRawFloat_extAbsIn, 17, 17) \n node _intAsRawFloat_adjustedNormDist_T_18 = bits(intAsRawFloat_extAbsIn, 18, 18) \n node _intAsRawFloat_adjustedNormDist_T_19 = bits(intAsRawFloat_extAbsIn, 19, 19) \n node _intAsRawFloat_adjustedNormDist_T_20 = bits(intAsRawFloat_extAbsIn, 20, 20) \n node _intAsRawFloat_adjustedNormDist_T_21 = bits(intAsRawFloat_extAbsIn, 21, 21) \n node _intAsRawFloat_adjustedNormDist_T_22 = bits(intAsRawFloat_extAbsIn, 22, 22) \n node _intAsRawFloat_adjustedNormDist_T_23 = bits(intAsRawFloat_extAbsIn, 23, 23) \n node _intAsRawFloat_adjustedNormDist_T_24 = bits(intAsRawFloat_extAbsIn, 24, 24) \n node _intAsRawFloat_adjustedNormDist_T_25 = bits(intAsRawFloat_extAbsIn, 25, 25) \n node _intAsRawFloat_adjustedNormDist_T_26 = bits(intAsRawFloat_extAbsIn, 26, 26) \n node _intAsRawFloat_adjustedNormDist_T_27 = bits(intAsRawFloat_extAbsIn, 27, 27) \n node _intAsRawFloat_adjustedNormDist_T_28 = bits(intAsRawFloat_extAbsIn, 28, 28) \n node _intAsRawFloat_adjustedNormDist_T_29 = bits(intAsRawFloat_extAbsIn, 29, 29) \n node _intAsRawFloat_adjustedNormDist_T_30 = bits(intAsRawFloat_extAbsIn, 30, 30) \n node _intAsRawFloat_adjustedNormDist_T_31 = bits(intAsRawFloat_extAbsIn, 31, 31) \n node _intAsRawFloat_adjustedNormDist_T_32 = bits(intAsRawFloat_extAbsIn, 32, 32) \n node _intAsRawFloat_adjustedNormDist_T_33 = bits(intAsRawFloat_extAbsIn, 33, 33) \n node _intAsRawFloat_adjustedNormDist_T_34 = bits(intAsRawFloat_extAbsIn, 34, 34) \n node _intAsRawFloat_adjustedNormDist_T_35 = bits(intAsRawFloat_extAbsIn, 35, 35) \n node _intAsRawFloat_adjustedNormDist_T_36 = bits(intAsRawFloat_extAbsIn, 36, 36) \n node _intAsRawFloat_adjustedNormDist_T_37 = bits(intAsRawFloat_extAbsIn, 37, 37) \n node _intAsRawFloat_adjustedNormDist_T_38 = bits(intAsRawFloat_extAbsIn, 38, 38) \n node _intAsRawFloat_adjustedNormDist_T_39 = bits(intAsRawFloat_extAbsIn, 39, 39) \n node _intAsRawFloat_adjustedNormDist_T_40 = bits(intAsRawFloat_extAbsIn, 40, 40) \n node _intAsRawFloat_adjustedNormDist_T_41 = bits(intAsRawFloat_extAbsIn, 41, 41) \n node _intAsRawFloat_adjustedNormDist_T_42 = bits(intAsRawFloat_extAbsIn, 42, 42) \n node _intAsRawFloat_adjustedNormDist_T_43 = bits(intAsRawFloat_extAbsIn, 43, 43) \n node _intAsRawFloat_adjustedNormDist_T_44 = bits(intAsRawFloat_extAbsIn, 44, 44) \n node _intAsRawFloat_adjustedNormDist_T_45 = bits(intAsRawFloat_extAbsIn, 45, 45) \n node _intAsRawFloat_adjustedNormDist_T_46 = bits(intAsRawFloat_extAbsIn, 46, 46) \n node _intAsRawFloat_adjustedNormDist_T_47 = bits(intAsRawFloat_extAbsIn, 47, 47) \n node _intAsRawFloat_adjustedNormDist_T_48 = bits(intAsRawFloat_extAbsIn, 48, 48) \n node _intAsRawFloat_adjustedNormDist_T_49 = bits(intAsRawFloat_extAbsIn, 49, 49) \n node _intAsRawFloat_adjustedNormDist_T_50 = bits(intAsRawFloat_extAbsIn, 50, 50) \n node _intAsRawFloat_adjustedNormDist_T_51 = bits(intAsRawFloat_extAbsIn, 51, 51) \n node _intAsRawFloat_adjustedNormDist_T_52 = bits(intAsRawFloat_extAbsIn, 52, 52) \n node _intAsRawFloat_adjustedNormDist_T_53 = bits(intAsRawFloat_extAbsIn, 53, 53) \n node _intAsRawFloat_adjustedNormDist_T_54 = bits(intAsRawFloat_extAbsIn, 54, 54) \n node _intAsRawFloat_adjustedNormDist_T_55 = bits(intAsRawFloat_extAbsIn, 55, 55) \n node _intAsRawFloat_adjustedNormDist_T_56 = bits(intAsRawFloat_extAbsIn, 56, 56) \n node _intAsRawFloat_adjustedNormDist_T_57 = bits(intAsRawFloat_extAbsIn, 57, 57) \n node _intAsRawFloat_adjustedNormDist_T_58 = bits(intAsRawFloat_extAbsIn, 58, 58) \n node _intAsRawFloat_adjustedNormDist_T_59 = bits(intAsRawFloat_extAbsIn, 59, 59) \n node _intAsRawFloat_adjustedNormDist_T_60 = bits(intAsRawFloat_extAbsIn, 60, 60) \n node _intAsRawFloat_adjustedNormDist_T_61 = bits(intAsRawFloat_extAbsIn, 61, 61) \n node _intAsRawFloat_adjustedNormDist_T_62 = bits(intAsRawFloat_extAbsIn, 62, 62) \n node _intAsRawFloat_adjustedNormDist_T_63 = bits(intAsRawFloat_extAbsIn, 63, 63) \n node _intAsRawFloat_adjustedNormDist_T_64 = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<6>(0h3e), UInt<6>(0h3f)) \n node _intAsRawFloat_adjustedNormDist_T_65 = mux(_intAsRawFloat_adjustedNormDist_T_2, UInt<6>(0h3d), _intAsRawFloat_adjustedNormDist_T_64) \n node _intAsRawFloat_adjustedNormDist_T_66 = mux(_intAsRawFloat_adjustedNormDist_T_3, UInt<6>(0h3c), _intAsRawFloat_adjustedNormDist_T_65) \n node _intAsRawFloat_adjustedNormDist_T_67 = mux(_intAsRawFloat_adjustedNormDist_T_4, UInt<6>(0h3b), _intAsRawFloat_adjustedNormDist_T_66) \n node _intAsRawFloat_adjustedNormDist_T_68 = mux(_intAsRawFloat_adjustedNormDist_T_5, UInt<6>(0h3a), _intAsRawFloat_adjustedNormDist_T_67) \n node _intAsRawFloat_adjustedNormDist_T_69 = mux(_intAsRawFloat_adjustedNormDist_T_6, UInt<6>(0h39), _intAsRawFloat_adjustedNormDist_T_68) \n node _intAsRawFloat_adjustedNormDist_T_70 = mux(_intAsRawFloat_adjustedNormDist_T_7, UInt<6>(0h38), _intAsRawFloat_adjustedNormDist_T_69) \n node _intAsRawFloat_adjustedNormDist_T_71 = mux(_intAsRawFloat_adjustedNormDist_T_8, UInt<6>(0h37), _intAsRawFloat_adjustedNormDist_T_70) \n node _intAsRawFloat_adjustedNormDist_T_72 = mux(_intAsRawFloat_adjustedNormDist_T_9, UInt<6>(0h36), _intAsRawFloat_adjustedNormDist_T_71) \n node _intAsRawFloat_adjustedNormDist_T_73 = mux(_intAsRawFloat_adjustedNormDist_T_10, UInt<6>(0h35), _intAsRawFloat_adjustedNormDist_T_72) \n node _intAsRawFloat_adjustedNormDist_T_74 = mux(_intAsRawFloat_adjustedNormDist_T_11, UInt<6>(0h34), _intAsRawFloat_adjustedNormDist_T_73) \n node _intAsRawFloat_adjustedNormDist_T_75 = mux(_intAsRawFloat_adjustedNormDist_T_12, UInt<6>(0h33), _intAsRawFloat_adjustedNormDist_T_74) \n node _intAsRawFloat_adjustedNormDist_T_76 = mux(_intAsRawFloat_adjustedNormDist_T_13, UInt<6>(0h32), _intAsRawFloat_adjustedNormDist_T_75) \n node _intAsRawFloat_adjustedNormDist_T_77 = mux(_intAsRawFloat_adjustedNormDist_T_14, UInt<6>(0h31), _intAsRawFloat_adjustedNormDist_T_76) \n node _intAsRawFloat_adjustedNormDist_T_78 = mux(_intAsRawFloat_adjustedNormDist_T_15, UInt<6>(0h30), _intAsRawFloat_adjustedNormDist_T_77) \n node _intAsRawFloat_adjustedNormDist_T_79 = mux(_intAsRawFloat_adjustedNormDist_T_16, UInt<6>(0h2f), _intAsRawFloat_adjustedNormDist_T_78) \n node _intAsRawFloat_adjustedNormDist_T_80 = mux(_intAsRawFloat_adjustedNormDist_T_17, UInt<6>(0h2e), _intAsRawFloat_adjustedNormDist_T_79) \n node _intAsRawFloat_adjustedNormDist_T_81 = mux(_intAsRawFloat_adjustedNormDist_T_18, UInt<6>(0h2d), _intAsRawFloat_adjustedNormDist_T_80) \n node _intAsRawFloat_adjustedNormDist_T_82 = mux(_intAsRawFloat_adjustedNormDist_T_19, UInt<6>(0h2c), _intAsRawFloat_adjustedNormDist_T_81) \n node _intAsRawFloat_adjustedNormDist_T_83 = mux(_intAsRawFloat_adjustedNormDist_T_20, UInt<6>(0h2b), _intAsRawFloat_adjustedNormDist_T_82) \n node _intAsRawFloat_adjustedNormDist_T_84 = mux(_intAsRawFloat_adjustedNormDist_T_21, UInt<6>(0h2a), _intAsRawFloat_adjustedNormDist_T_83) \n node _intAsRawFloat_adjustedNormDist_T_85 = mux(_intAsRawFloat_adjustedNormDist_T_22, UInt<6>(0h29), _intAsRawFloat_adjustedNormDist_T_84) \n node _intAsRawFloat_adjustedNormDist_T_86 = mux(_intAsRawFloat_adjustedNormDist_T_23, UInt<6>(0h28), _intAsRawFloat_adjustedNormDist_T_85) \n node _intAsRawFloat_adjustedNormDist_T_87 = mux(_intAsRawFloat_adjustedNormDist_T_24, UInt<6>(0h27), _intAsRawFloat_adjustedNormDist_T_86) \n node _intAsRawFloat_adjustedNormDist_T_88 = mux(_intAsRawFloat_adjustedNormDist_T_25, UInt<6>(0h26), _intAsRawFloat_adjustedNormDist_T_87) \n node _intAsRawFloat_adjustedNormDist_T_89 = mux(_intAsRawFloat_adjustedNormDist_T_26, UInt<6>(0h25), _intAsRawFloat_adjustedNormDist_T_88) \n node _intAsRawFloat_adjustedNormDist_T_90 = mux(_intAsRawFloat_adjustedNormDist_T_27, UInt<6>(0h24), _intAsRawFloat_adjustedNormDist_T_89) \n node _intAsRawFloat_adjustedNormDist_T_91 = mux(_intAsRawFloat_adjustedNormDist_T_28, UInt<6>(0h23), _intAsRawFloat_adjustedNormDist_T_90) \n node _intAsRawFloat_adjustedNormDist_T_92 = mux(_intAsRawFloat_adjustedNormDist_T_29, UInt<6>(0h22), _intAsRawFloat_adjustedNormDist_T_91) \n node _intAsRawFloat_adjustedNormDist_T_93 = mux(_intAsRawFloat_adjustedNormDist_T_30, UInt<6>(0h21), _intAsRawFloat_adjustedNormDist_T_92) \n node _intAsRawFloat_adjustedNormDist_T_94 = mux(_intAsRawFloat_adjustedNormDist_T_31, UInt<6>(0h20), _intAsRawFloat_adjustedNormDist_T_93) \n node _intAsRawFloat_adjustedNormDist_T_95 = mux(_intAsRawFloat_adjustedNormDist_T_32, UInt<5>(0h1f), _intAsRawFloat_adjustedNormDist_T_94) \n node _intAsRawFloat_adjustedNormDist_T_96 = mux(_intAsRawFloat_adjustedNormDist_T_33, UInt<5>(0h1e), _intAsRawFloat_adjustedNormDist_T_95) \n node _intAsRawFloat_adjustedNormDist_T_97 = mux(_intAsRawFloat_adjustedNormDist_T_34, UInt<5>(0h1d), _intAsRawFloat_adjustedNormDist_T_96) \n node _intAsRawFloat_adjustedNormDist_T_98 = mux(_intAsRawFloat_adjustedNormDist_T_35, UInt<5>(0h1c), _intAsRawFloat_adjustedNormDist_T_97) \n node _intAsRawFloat_adjustedNormDist_T_99 = mux(_intAsRawFloat_adjustedNormDist_T_36, UInt<5>(0h1b), _intAsRawFloat_adjustedNormDist_T_98) \n node _intAsRawFloat_adjustedNormDist_T_100 = mux(_intAsRawFloat_adjustedNormDist_T_37, UInt<5>(0h1a), _intAsRawFloat_adjustedNormDist_T_99) \n node _intAsRawFloat_adjustedNormDist_T_101 = mux(_intAsRawFloat_adjustedNormDist_T_38, UInt<5>(0h19), _intAsRawFloat_adjustedNormDist_T_100) \n node _intAsRawFloat_adjustedNormDist_T_102 = mux(_intAsRawFloat_adjustedNormDist_T_39, UInt<5>(0h18), _intAsRawFloat_adjustedNormDist_T_101) \n node _intAsRawFloat_adjustedNormDist_T_103 = mux(_intAsRawFloat_adjustedNormDist_T_40, UInt<5>(0h17), _intAsRawFloat_adjustedNormDist_T_102) \n node _intAsRawFloat_adjustedNormDist_T_104 = mux(_intAsRawFloat_adjustedNormDist_T_41, UInt<5>(0h16), _intAsRawFloat_adjustedNormDist_T_103) \n node _intAsRawFloat_adjustedNormDist_T_105 = mux(_intAsRawFloat_adjustedNormDist_T_42, UInt<5>(0h15), _intAsRawFloat_adjustedNormDist_T_104) \n node _intAsRawFloat_adjustedNormDist_T_106 = mux(_intAsRawFloat_adjustedNormDist_T_43, UInt<5>(0h14), _intAsRawFloat_adjustedNormDist_T_105) \n node _intAsRawFloat_adjustedNormDist_T_107 = mux(_intAsRawFloat_adjustedNormDist_T_44, UInt<5>(0h13), _intAsRawFloat_adjustedNormDist_T_106) \n node _intAsRawFloat_adjustedNormDist_T_108 = mux(_intAsRawFloat_adjustedNormDist_T_45, UInt<5>(0h12), _intAsRawFloat_adjustedNormDist_T_107) \n node _intAsRawFloat_adjustedNormDist_T_109 = mux(_intAsRawFloat_adjustedNormDist_T_46, UInt<5>(0h11), _intAsRawFloat_adjustedNormDist_T_108) \n node _intAsRawFloat_adjustedNormDist_T_110 = mux(_intAsRawFloat_adjustedNormDist_T_47, UInt<5>(0h10), _intAsRawFloat_adjustedNormDist_T_109) \n node _intAsRawFloat_adjustedNormDist_T_111 = mux(_intAsRawFloat_adjustedNormDist_T_48, UInt<4>(0hf), _intAsRawFloat_adjustedNormDist_T_110) \n node _intAsRawFloat_adjustedNormDist_T_112 = mux(_intAsRawFloat_adjustedNormDist_T_49, UInt<4>(0he), _intAsRawFloat_adjustedNormDist_T_111) \n node _intAsRawFloat_adjustedNormDist_T_113 = mux(_intAsRawFloat_adjustedNormDist_T_50, UInt<4>(0hd), _intAsRawFloat_adjustedNormDist_T_112) \n node _intAsRawFloat_adjustedNormDist_T_114 = mux(_intAsRawFloat_adjustedNormDist_T_51, UInt<4>(0hc), _intAsRawFloat_adjustedNormDist_T_113) \n node _intAsRawFloat_adjustedNormDist_T_115 = mux(_intAsRawFloat_adjustedNormDist_T_52, UInt<4>(0hb), _intAsRawFloat_adjustedNormDist_T_114) \n node _intAsRawFloat_adjustedNormDist_T_116 = mux(_intAsRawFloat_adjustedNormDist_T_53, UInt<4>(0ha), _intAsRawFloat_adjustedNormDist_T_115) \n node _intAsRawFloat_adjustedNormDist_T_117 = mux(_intAsRawFloat_adjustedNormDist_T_54, UInt<4>(0h9), _intAsRawFloat_adjustedNormDist_T_116) \n node _intAsRawFloat_adjustedNormDist_T_118 = mux(_intAsRawFloat_adjustedNormDist_T_55, UInt<4>(0h8), _intAsRawFloat_adjustedNormDist_T_117) \n node _intAsRawFloat_adjustedNormDist_T_119 = mux(_intAsRawFloat_adjustedNormDist_T_56, UInt<3>(0h7), _intAsRawFloat_adjustedNormDist_T_118) \n node _intAsRawFloat_adjustedNormDist_T_120 = mux(_intAsRawFloat_adjustedNormDist_T_57, UInt<3>(0h6), _intAsRawFloat_adjustedNormDist_T_119) \n node _intAsRawFloat_adjustedNormDist_T_121 = mux(_intAsRawFloat_adjustedNormDist_T_58, UInt<3>(0h5), _intAsRawFloat_adjustedNormDist_T_120) \n node _intAsRawFloat_adjustedNormDist_T_122 = mux(_intAsRawFloat_adjustedNormDist_T_59, UInt<3>(0h4), _intAsRawFloat_adjustedNormDist_T_121) \n node _intAsRawFloat_adjustedNormDist_T_123 = mux(_intAsRawFloat_adjustedNormDist_T_60, UInt<2>(0h3), _intAsRawFloat_adjustedNormDist_T_122) \n node _intAsRawFloat_adjustedNormDist_T_124 = mux(_intAsRawFloat_adjustedNormDist_T_61, UInt<2>(0h2), _intAsRawFloat_adjustedNormDist_T_123) \n node _intAsRawFloat_adjustedNormDist_T_125 = mux(_intAsRawFloat_adjustedNormDist_T_62, UInt<1>(0h1), _intAsRawFloat_adjustedNormDist_T_124) \n node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_63, UInt<1>(0h0), _intAsRawFloat_adjustedNormDist_T_125) \n node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist) \n node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 63, 0) \n wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<9>, sig : UInt<65>} \n connect intAsRawFloat.isNaN, UInt<1>(0h0) \n connect intAsRawFloat.isInf, UInt<1>(0h0) \n node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 63, 63) \n node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0)) \n connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1 \n connect intAsRawFloat.sign, intAsRawFloat_sign \n node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 5, 0) \n node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T) \n node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1) \n node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2) \n connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3 \n connect intAsRawFloat.sig, intAsRawFloat_sig \n inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie7_is64_oe11_os53_2 \n connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0) \n connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0) \n connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig \n connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp \n connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign \n connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero \n connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf \n connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN \n connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode \n connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess \n connect io.out, roundAnyRawFNToRecFN.io.out \n connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags"},"response":{"kind":"string","value":"module INToRecFN_i64_e11_s53_2(\t// @[INToRecFN.scala:43:7]\n input io_signedIn,\t// @[INToRecFN.scala:46:16]\n input [63:0] io_in,\t// @[INToRecFN.scala:46:16]\n input [2:0] io_roundingMode,\t// @[INToRecFN.scala:46:16]\n output [64:0] io_out,\t// @[INToRecFN.scala:46:16]\n output [4:0] io_exceptionFlags\t// @[INToRecFN.scala:46:16]\n);\n\n wire io_signedIn_0 = io_signedIn;\t// @[INToRecFN.scala:43:7]\n wire [63:0] io_in_0 = io_in;\t// @[INToRecFN.scala:43:7]\n wire [2:0] io_roundingMode_0 = io_roundingMode;\t// @[INToRecFN.scala:43:7]\n wire intAsRawFloat_isNaN = 1'h0;\t// @[rawFloatFromIN.scala:59:23]\n wire intAsRawFloat_isInf = 1'h0;\t// @[rawFloatFromIN.scala:59:23]\n wire io_detectTininess = 1'h1;\t// @[INToRecFN.scala:43:7]\n wire [64:0] io_out_0;\t// @[INToRecFN.scala:43:7]\n wire [4:0] io_exceptionFlags_0;\t// @[INToRecFN.scala:43:7]\n wire _intAsRawFloat_sign_T = io_in_0[63];\t// @[rawFloatFromIN.scala:51:34]\n wire intAsRawFloat_sign = io_signedIn_0 & _intAsRawFloat_sign_T;\t// @[rawFloatFromIN.scala:51:{29,34}]\n wire intAsRawFloat_sign_0 = intAsRawFloat_sign;\t// @[rawFloatFromIN.scala:51:29, :59:23]\n wire [64:0] _intAsRawFloat_absIn_T = 65'h0 - {1'h0, io_in_0};\t// @[rawFloatFromIN.scala:52:31]\n wire [63:0] _intAsRawFloat_absIn_T_1 = _intAsRawFloat_absIn_T[63:0];\t// @[rawFloatFromIN.scala:52:31]\n wire [63:0] intAsRawFloat_absIn = intAsRawFloat_sign ? _intAsRawFloat_absIn_T_1 : io_in_0;\t// @[rawFloatFromIN.scala:51:29, :52:{24,31}]\n wire [127:0] _intAsRawFloat_extAbsIn_T = {64'h0, intAsRawFloat_absIn};\t// @[rawFloatFromIN.scala:52:24, :53:44]\n wire [63:0] intAsRawFloat_extAbsIn = _intAsRawFloat_extAbsIn_T[63:0];\t// @[rawFloatFromIN.scala:53:{44,53}]\n wire _intAsRawFloat_adjustedNormDist_T = intAsRawFloat_extAbsIn[0];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_1 = intAsRawFloat_extAbsIn[1];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_2 = intAsRawFloat_extAbsIn[2];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_3 = intAsRawFloat_extAbsIn[3];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_4 = intAsRawFloat_extAbsIn[4];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_5 = intAsRawFloat_extAbsIn[5];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_6 = intAsRawFloat_extAbsIn[6];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_7 = intAsRawFloat_extAbsIn[7];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_8 = intAsRawFloat_extAbsIn[8];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_9 = intAsRawFloat_extAbsIn[9];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_10 = intAsRawFloat_extAbsIn[10];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_11 = intAsRawFloat_extAbsIn[11];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_12 = intAsRawFloat_extAbsIn[12];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_13 = intAsRawFloat_extAbsIn[13];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_14 = intAsRawFloat_extAbsIn[14];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_15 = intAsRawFloat_extAbsIn[15];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_16 = intAsRawFloat_extAbsIn[16];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_17 = intAsRawFloat_extAbsIn[17];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_18 = intAsRawFloat_extAbsIn[18];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_19 = intAsRawFloat_extAbsIn[19];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_20 = intAsRawFloat_extAbsIn[20];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_21 = intAsRawFloat_extAbsIn[21];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_22 = intAsRawFloat_extAbsIn[22];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_23 = intAsRawFloat_extAbsIn[23];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_24 = intAsRawFloat_extAbsIn[24];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_25 = intAsRawFloat_extAbsIn[25];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_26 = intAsRawFloat_extAbsIn[26];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_27 = intAsRawFloat_extAbsIn[27];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_28 = intAsRawFloat_extAbsIn[28];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_29 = intAsRawFloat_extAbsIn[29];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_30 = intAsRawFloat_extAbsIn[30];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_31 = intAsRawFloat_extAbsIn[31];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_32 = intAsRawFloat_extAbsIn[32];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_33 = intAsRawFloat_extAbsIn[33];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_34 = intAsRawFloat_extAbsIn[34];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_35 = intAsRawFloat_extAbsIn[35];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_36 = intAsRawFloat_extAbsIn[36];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_37 = intAsRawFloat_extAbsIn[37];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_38 = intAsRawFloat_extAbsIn[38];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_39 = intAsRawFloat_extAbsIn[39];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_40 = intAsRawFloat_extAbsIn[40];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_41 = intAsRawFloat_extAbsIn[41];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_42 = intAsRawFloat_extAbsIn[42];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_43 = intAsRawFloat_extAbsIn[43];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_44 = intAsRawFloat_extAbsIn[44];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_45 = intAsRawFloat_extAbsIn[45];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_46 = intAsRawFloat_extAbsIn[46];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_47 = intAsRawFloat_extAbsIn[47];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_48 = intAsRawFloat_extAbsIn[48];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_49 = intAsRawFloat_extAbsIn[49];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_50 = intAsRawFloat_extAbsIn[50];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_51 = intAsRawFloat_extAbsIn[51];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_52 = intAsRawFloat_extAbsIn[52];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_53 = intAsRawFloat_extAbsIn[53];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_54 = intAsRawFloat_extAbsIn[54];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_55 = intAsRawFloat_extAbsIn[55];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_56 = intAsRawFloat_extAbsIn[56];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_57 = intAsRawFloat_extAbsIn[57];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_58 = intAsRawFloat_extAbsIn[58];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_59 = intAsRawFloat_extAbsIn[59];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_60 = intAsRawFloat_extAbsIn[60];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_61 = intAsRawFloat_extAbsIn[61];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_62 = intAsRawFloat_extAbsIn[62];\t// @[rawFloatFromIN.scala:53:53]\n wire _intAsRawFloat_adjustedNormDist_T_63 = intAsRawFloat_extAbsIn[63];\t// @[rawFloatFromIN.scala:53:53]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_64 = {5'h1F, ~_intAsRawFloat_adjustedNormDist_T_1};\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_65 = _intAsRawFloat_adjustedNormDist_T_2 ? 6'h3D : _intAsRawFloat_adjustedNormDist_T_64;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_66 = _intAsRawFloat_adjustedNormDist_T_3 ? 6'h3C : _intAsRawFloat_adjustedNormDist_T_65;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_67 = _intAsRawFloat_adjustedNormDist_T_4 ? 6'h3B : _intAsRawFloat_adjustedNormDist_T_66;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_68 = _intAsRawFloat_adjustedNormDist_T_5 ? 6'h3A : _intAsRawFloat_adjustedNormDist_T_67;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_69 = _intAsRawFloat_adjustedNormDist_T_6 ? 6'h39 : _intAsRawFloat_adjustedNormDist_T_68;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_70 = _intAsRawFloat_adjustedNormDist_T_7 ? 6'h38 : _intAsRawFloat_adjustedNormDist_T_69;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_71 = _intAsRawFloat_adjustedNormDist_T_8 ? 6'h37 : _intAsRawFloat_adjustedNormDist_T_70;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_72 = _intAsRawFloat_adjustedNormDist_T_9 ? 6'h36 : _intAsRawFloat_adjustedNormDist_T_71;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_73 = _intAsRawFloat_adjustedNormDist_T_10 ? 6'h35 : _intAsRawFloat_adjustedNormDist_T_72;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_74 = _intAsRawFloat_adjustedNormDist_T_11 ? 6'h34 : _intAsRawFloat_adjustedNormDist_T_73;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_75 = _intAsRawFloat_adjustedNormDist_T_12 ? 6'h33 : _intAsRawFloat_adjustedNormDist_T_74;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_76 = _intAsRawFloat_adjustedNormDist_T_13 ? 6'h32 : _intAsRawFloat_adjustedNormDist_T_75;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_77 = _intAsRawFloat_adjustedNormDist_T_14 ? 6'h31 : _intAsRawFloat_adjustedNormDist_T_76;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_78 = _intAsRawFloat_adjustedNormDist_T_15 ? 6'h30 : _intAsRawFloat_adjustedNormDist_T_77;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_79 = _intAsRawFloat_adjustedNormDist_T_16 ? 6'h2F : _intAsRawFloat_adjustedNormDist_T_78;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_80 = _intAsRawFloat_adjustedNormDist_T_17 ? 6'h2E : _intAsRawFloat_adjustedNormDist_T_79;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_81 = _intAsRawFloat_adjustedNormDist_T_18 ? 6'h2D : _intAsRawFloat_adjustedNormDist_T_80;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_82 = _intAsRawFloat_adjustedNormDist_T_19 ? 6'h2C : _intAsRawFloat_adjustedNormDist_T_81;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_83 = _intAsRawFloat_adjustedNormDist_T_20 ? 6'h2B : _intAsRawFloat_adjustedNormDist_T_82;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_84 = _intAsRawFloat_adjustedNormDist_T_21 ? 6'h2A : _intAsRawFloat_adjustedNormDist_T_83;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_85 = _intAsRawFloat_adjustedNormDist_T_22 ? 6'h29 : _intAsRawFloat_adjustedNormDist_T_84;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_86 = _intAsRawFloat_adjustedNormDist_T_23 ? 6'h28 : _intAsRawFloat_adjustedNormDist_T_85;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_87 = _intAsRawFloat_adjustedNormDist_T_24 ? 6'h27 : _intAsRawFloat_adjustedNormDist_T_86;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_88 = _intAsRawFloat_adjustedNormDist_T_25 ? 6'h26 : _intAsRawFloat_adjustedNormDist_T_87;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_89 = _intAsRawFloat_adjustedNormDist_T_26 ? 6'h25 : _intAsRawFloat_adjustedNormDist_T_88;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_90 = _intAsRawFloat_adjustedNormDist_T_27 ? 6'h24 : _intAsRawFloat_adjustedNormDist_T_89;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_91 = _intAsRawFloat_adjustedNormDist_T_28 ? 6'h23 : _intAsRawFloat_adjustedNormDist_T_90;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_92 = _intAsRawFloat_adjustedNormDist_T_29 ? 6'h22 : _intAsRawFloat_adjustedNormDist_T_91;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_93 = _intAsRawFloat_adjustedNormDist_T_30 ? 6'h21 : _intAsRawFloat_adjustedNormDist_T_92;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_94 = _intAsRawFloat_adjustedNormDist_T_31 ? 6'h20 : _intAsRawFloat_adjustedNormDist_T_93;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_95 = _intAsRawFloat_adjustedNormDist_T_32 ? 6'h1F : _intAsRawFloat_adjustedNormDist_T_94;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_96 = _intAsRawFloat_adjustedNormDist_T_33 ? 6'h1E : _intAsRawFloat_adjustedNormDist_T_95;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_97 = _intAsRawFloat_adjustedNormDist_T_34 ? 6'h1D : _intAsRawFloat_adjustedNormDist_T_96;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_98 = _intAsRawFloat_adjustedNormDist_T_35 ? 6'h1C : _intAsRawFloat_adjustedNormDist_T_97;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_99 = _intAsRawFloat_adjustedNormDist_T_36 ? 6'h1B : _intAsRawFloat_adjustedNormDist_T_98;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_100 = _intAsRawFloat_adjustedNormDist_T_37 ? 6'h1A : _intAsRawFloat_adjustedNormDist_T_99;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_101 = _intAsRawFloat_adjustedNormDist_T_38 ? 6'h19 : _intAsRawFloat_adjustedNormDist_T_100;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_102 = _intAsRawFloat_adjustedNormDist_T_39 ? 6'h18 : _intAsRawFloat_adjustedNormDist_T_101;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_103 = _intAsRawFloat_adjustedNormDist_T_40 ? 6'h17 : _intAsRawFloat_adjustedNormDist_T_102;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_104 = _intAsRawFloat_adjustedNormDist_T_41 ? 6'h16 : _intAsRawFloat_adjustedNormDist_T_103;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_105 = _intAsRawFloat_adjustedNormDist_T_42 ? 6'h15 : _intAsRawFloat_adjustedNormDist_T_104;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_106 = _intAsRawFloat_adjustedNormDist_T_43 ? 6'h14 : _intAsRawFloat_adjustedNormDist_T_105;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_107 = _intAsRawFloat_adjustedNormDist_T_44 ? 6'h13 : _intAsRawFloat_adjustedNormDist_T_106;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_108 = _intAsRawFloat_adjustedNormDist_T_45 ? 6'h12 : _intAsRawFloat_adjustedNormDist_T_107;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_109 = _intAsRawFloat_adjustedNormDist_T_46 ? 6'h11 : _intAsRawFloat_adjustedNormDist_T_108;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_110 = _intAsRawFloat_adjustedNormDist_T_47 ? 6'h10 : _intAsRawFloat_adjustedNormDist_T_109;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_111 = _intAsRawFloat_adjustedNormDist_T_48 ? 6'hF : _intAsRawFloat_adjustedNormDist_T_110;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_112 = _intAsRawFloat_adjustedNormDist_T_49 ? 6'hE : _intAsRawFloat_adjustedNormDist_T_111;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_113 = _intAsRawFloat_adjustedNormDist_T_50 ? 6'hD : _intAsRawFloat_adjustedNormDist_T_112;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_114 = _intAsRawFloat_adjustedNormDist_T_51 ? 6'hC : _intAsRawFloat_adjustedNormDist_T_113;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_115 = _intAsRawFloat_adjustedNormDist_T_52 ? 6'hB : _intAsRawFloat_adjustedNormDist_T_114;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_116 = _intAsRawFloat_adjustedNormDist_T_53 ? 6'hA : _intAsRawFloat_adjustedNormDist_T_115;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_117 = _intAsRawFloat_adjustedNormDist_T_54 ? 6'h9 : _intAsRawFloat_adjustedNormDist_T_116;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_118 = _intAsRawFloat_adjustedNormDist_T_55 ? 6'h8 : _intAsRawFloat_adjustedNormDist_T_117;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_119 = _intAsRawFloat_adjustedNormDist_T_56 ? 6'h7 : _intAsRawFloat_adjustedNormDist_T_118;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_120 = _intAsRawFloat_adjustedNormDist_T_57 ? 6'h6 : _intAsRawFloat_adjustedNormDist_T_119;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_121 = _intAsRawFloat_adjustedNormDist_T_58 ? 6'h5 : _intAsRawFloat_adjustedNormDist_T_120;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_122 = _intAsRawFloat_adjustedNormDist_T_59 ? 6'h4 : _intAsRawFloat_adjustedNormDist_T_121;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_123 = _intAsRawFloat_adjustedNormDist_T_60 ? 6'h3 : _intAsRawFloat_adjustedNormDist_T_122;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_124 = _intAsRawFloat_adjustedNormDist_T_61 ? 6'h2 : _intAsRawFloat_adjustedNormDist_T_123;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_adjustedNormDist_T_125 = _intAsRawFloat_adjustedNormDist_T_62 ? 6'h1 : _intAsRawFloat_adjustedNormDist_T_124;\t// @[Mux.scala:50:70]\n wire [5:0] intAsRawFloat_adjustedNormDist = _intAsRawFloat_adjustedNormDist_T_63 ? 6'h0 : _intAsRawFloat_adjustedNormDist_T_125;\t// @[Mux.scala:50:70]\n wire [5:0] _intAsRawFloat_out_sExp_T = intAsRawFloat_adjustedNormDist;\t// @[Mux.scala:50:70]\n wire [126:0] _intAsRawFloat_sig_T = {63'h0, intAsRawFloat_extAbsIn} << intAsRawFloat_adjustedNormDist;\t// @[Mux.scala:50:70]\n wire [63:0] intAsRawFloat_sig = _intAsRawFloat_sig_T[63:0];\t// @[rawFloatFromIN.scala:56:{22,41}]\n wire _intAsRawFloat_out_isZero_T_1;\t// @[rawFloatFromIN.scala:62:23]\n wire [8:0] _intAsRawFloat_out_sExp_T_3;\t// @[rawFloatFromIN.scala:64:72]\n wire intAsRawFloat_isZero;\t// @[rawFloatFromIN.scala:59:23]\n wire [8:0] intAsRawFloat_sExp;\t// @[rawFloatFromIN.scala:59:23]\n wire [64:0] intAsRawFloat_sig_0;\t// @[rawFloatFromIN.scala:59:23]\n wire _intAsRawFloat_out_isZero_T = intAsRawFloat_sig[63];\t// @[rawFloatFromIN.scala:56:41, :62:28]\n assign _intAsRawFloat_out_isZero_T_1 = ~_intAsRawFloat_out_isZero_T;\t// @[rawFloatFromIN.scala:62:{23,28}]\n assign intAsRawFloat_isZero = _intAsRawFloat_out_isZero_T_1;\t// @[rawFloatFromIN.scala:59:23, :62:23]\n wire [5:0] _intAsRawFloat_out_sExp_T_1 = ~_intAsRawFloat_out_sExp_T;\t// @[rawFloatFromIN.scala:64:{36,53}]\n wire [7:0] _intAsRawFloat_out_sExp_T_2 = {2'h2, _intAsRawFloat_out_sExp_T_1};\t// @[rawFloatFromIN.scala:64:{33,36}]\n assign _intAsRawFloat_out_sExp_T_3 = {1'h0, _intAsRawFloat_out_sExp_T_2};\t// @[rawFloatFromIN.scala:64:{33,72}]\n assign intAsRawFloat_sExp = _intAsRawFloat_out_sExp_T_3;\t// @[rawFloatFromIN.scala:59:23, :64:72]\n assign intAsRawFloat_sig_0 = {1'h0, intAsRawFloat_sig};\t// @[rawFloatFromIN.scala:56:41, :59:23, :65:20]\n RoundAnyRawFNToRecFN_ie7_is64_oe11_os53_2 roundAnyRawFNToRecFN (\t// @[INToRecFN.scala:60:15]\n .io_in_isZero (intAsRawFloat_isZero),\t// @[rawFloatFromIN.scala:59:23]\n .io_in_sign (intAsRawFloat_sign_0),\t// @[rawFloatFromIN.scala:59:23]\n .io_in_sExp (intAsRawFloat_sExp),\t// @[rawFloatFromIN.scala:59:23]\n .io_in_sig (intAsRawFloat_sig_0),\t// @[rawFloatFromIN.scala:59:23]\n .io_roundingMode (io_roundingMode_0),\t// @[INToRecFN.scala:43:7]\n .io_out (io_out_0),\n .io_exceptionFlags (io_exceptionFlags_0)\n );\t// @[INToRecFN.scala:60:15]\n assign io_out = io_out_0;\t// @[INToRecFN.scala:43:7]\n assign io_exceptionFlags = io_exceptionFlags_0;\t// @[INToRecFN.scala:43:7]\nendmodule"}}},{"rowIdx":34190,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_53 : \n input clock : Clock \n input reset : Reset \n output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} \n\n\n when io.in.a.valid : \n node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) \n node _T_1 = asUInt(reset) \n node _T_2 = eq(_T_1, UInt<1>(0h0)) \n when _T_2 : \n node _T_3 = eq(_T, UInt<1>(0h0)) \n when _T_3 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf \n assert(clock, _T, UInt<1>(0h1), \"\") : assert \n node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) \n wire _source_ok_WIRE : UInt<1>[1] \n connect _source_ok_WIRE[0], _source_ok_T \n node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) \n node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) \n node is_aligned_mask = not(_is_aligned_mask_T_1) \n node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) \n node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) \n node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) \n node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) \n node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) \n node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) \n node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) \n node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) \n node mask_sub_size = bits(mask_sizeOH, 1, 1) \n node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) \n node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) \n node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) \n node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) \n node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) \n node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) \n node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) \n node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) \n node mask_size = bits(mask_sizeOH, 0, 0) \n node mask_bit = bits(io.in.a.bits.address, 0, 0) \n node mask_nbit = eq(mask_bit, UInt<1>(0h0)) \n node mask_eq = and(mask_sub_0_2, mask_nbit) \n node _mask_acc_T = and(mask_size, mask_eq) \n node mask_acc = or(mask_sub_0_1, _mask_acc_T) \n node mask_eq_1 = and(mask_sub_0_2, mask_bit) \n node _mask_acc_T_1 = and(mask_size, mask_eq_1) \n node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) \n node mask_eq_2 = and(mask_sub_1_2, mask_nbit) \n node _mask_acc_T_2 = and(mask_size, mask_eq_2) \n node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) \n node mask_eq_3 = and(mask_sub_1_2, mask_bit) \n node _mask_acc_T_3 = and(mask_size, mask_eq_3) \n node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) \n node mask_lo = cat(mask_acc_1, mask_acc) \n node mask_hi = cat(mask_acc_3, mask_acc_2) \n node mask = cat(mask_hi, mask_lo) \n node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) \n node _T_5 = eq(_T_4, UInt<1>(0h0)) \n node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_7 = cvt(_T_6) \n node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) \n node _T_9 = asSInt(_T_8) \n node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) \n node _T_11 = or(_T_5, _T_10) \n node _T_12 = asUInt(reset) \n node _T_13 = eq(_T_12, UInt<1>(0h0)) \n when _T_13 : \n node _T_14 = eq(_T_11, UInt<1>(0h0)) \n when _T_14 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_1 \n assert(clock, _T_11, UInt<1>(0h1), \"\") : assert_1 \n node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) \n when _T_15 : \n node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) \n node _T_17 = and(UInt<1>(0h0), _T_16) \n node _T_18 = or(UInt<1>(0h0), _T_17) \n node _T_19 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_20 = leq(io.in.a.bits.size, UInt<2>(0h2)) \n node _T_21 = and(_T_19, _T_20) \n node _T_22 = or(UInt<1>(0h0), _T_21) \n node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_24 = cvt(_T_23) \n node _T_25 = and(_T_24, asSInt(UInt<129>(0h100000000000000000000000000000000))) \n node _T_26 = asSInt(_T_25) \n node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) \n node _T_28 = and(_T_22, _T_27) \n node _T_29 = or(UInt<1>(0h0), _T_28) \n node _T_30 = and(_T_18, _T_29) \n node _T_31 = asUInt(reset) \n node _T_32 = eq(_T_31, UInt<1>(0h0)) \n when _T_32 : \n node _T_33 = eq(_T_30, UInt<1>(0h0)) \n when _T_33 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_2 \n assert(clock, _T_30, UInt<1>(0h1), \"\") : assert_2 \n node _T_34 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_35 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_36 = and(_T_34, _T_35) \n node _T_37 = or(UInt<1>(0h0), _T_36) \n node _T_38 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_39 = cvt(_T_38) \n node _T_40 = and(_T_39, asSInt(UInt<129>(0h100000000000000000000000000000000))) \n node _T_41 = asSInt(_T_40) \n node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) \n node _T_43 = and(_T_37, _T_42) \n node _T_44 = or(UInt<1>(0h0), _T_43) \n node _T_45 = and(UInt<1>(0h0), _T_44) \n node _T_46 = asUInt(reset) \n node _T_47 = eq(_T_46, UInt<1>(0h0)) \n when _T_47 : \n node _T_48 = eq(_T_45, UInt<1>(0h0)) \n when _T_48 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_3 \n assert(clock, _T_45, UInt<1>(0h1), \"\") : assert_3 \n node _T_49 = asUInt(reset) \n node _T_50 = eq(_T_49, UInt<1>(0h0)) \n when _T_50 : \n node _T_51 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_51 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_4 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_4 \n node _T_52 = geq(io.in.a.bits.size, UInt<2>(0h2)) \n node _T_53 = asUInt(reset) \n node _T_54 = eq(_T_53, UInt<1>(0h0)) \n when _T_54 : \n node _T_55 = eq(_T_52, UInt<1>(0h0)) \n when _T_55 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_5 \n assert(clock, _T_52, UInt<1>(0h1), \"\") : assert_5 \n node _T_56 = asUInt(reset) \n node _T_57 = eq(_T_56, UInt<1>(0h0)) \n when _T_57 : \n node _T_58 = eq(is_aligned, UInt<1>(0h0)) \n when _T_58 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_6 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_6 \n node _T_59 = leq(io.in.a.bits.param, UInt<2>(0h2)) \n node _T_60 = asUInt(reset) \n node _T_61 = eq(_T_60, UInt<1>(0h0)) \n when _T_61 : \n node _T_62 = eq(_T_59, UInt<1>(0h0)) \n when _T_62 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_7 \n assert(clock, _T_59, UInt<1>(0h1), \"\") : assert_7 \n node _T_63 = not(io.in.a.bits.mask) \n node _T_64 = eq(_T_63, UInt<1>(0h0)) \n node _T_65 = asUInt(reset) \n node _T_66 = eq(_T_65, UInt<1>(0h0)) \n when _T_66 : \n node _T_67 = eq(_T_64, UInt<1>(0h0)) \n when _T_67 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_8 \n assert(clock, _T_64, UInt<1>(0h1), \"\") : assert_8 \n node _T_68 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_69 = asUInt(reset) \n node _T_70 = eq(_T_69, UInt<1>(0h0)) \n when _T_70 : \n node _T_71 = eq(_T_68, UInt<1>(0h0)) \n when _T_71 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_9 \n assert(clock, _T_68, UInt<1>(0h1), \"\") : assert_9 \n node _T_72 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) \n when _T_72 : \n node _T_73 = eq(io.in.a.bits.source, UInt<1>(0h0)) \n node _T_74 = and(UInt<1>(0h0), _T_73) \n node _T_75 = or(UInt<1>(0h0), _T_74) \n node _T_76 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_77 = leq(io.in.a.bits.size, UInt<2>(0h2)) \n node _T_78 = and(_T_76, _T_77) \n node _T_79 = or(UInt<1>(0h0), _T_78) \n node _T_80 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_81 = cvt(_T_80) \n node _T_82 = and(_T_81, asSInt(UInt<129>(0h100000000000000000000000000000000))) \n node _T_83 = asSInt(_T_82) \n node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) \n node _T_85 = and(_T_79, _T_84) \n node _T_86 = or(UInt<1>(0h0), _T_85) \n node _T_87 = and(_T_75, _T_86) \n node _T_88 = asUInt(reset) \n node _T_89 = eq(_T_88, UInt<1>(0h0)) \n when _T_89 : \n node _T_90 = eq(_T_87, UInt<1>(0h0)) \n when _T_90 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_10 \n assert(clock, _T_87, UInt<1>(0h1), \"\") : assert_10 \n node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) \n node _T_93 = and(_T_91, _T_92) \n node _T_94 = or(UInt<1>(0h0), _T_93) \n node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_96 = cvt(_T_95) \n node _T_97 = and(_T_96, asSInt(UInt<129>(0h100000000000000000000000000000000))) \n node _T_98 = asSInt(_T_97) \n node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) \n node _T_100 = and(_T_94, _T_99) \n node _T_101 = or(UInt<1>(0h0), _T_100) \n node _T_102 = and(UInt<1>(0h0), _T_101) \n node _T_103 = asUInt(reset) \n node _T_104 = eq(_T_103, UInt<1>(0h0)) \n when _T_104 : \n node _T_105 = eq(_T_102, UInt<1>(0h0)) \n when _T_105 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_11 \n assert(clock, _T_102, UInt<1>(0h1), \"\") : assert_11 \n node _T_106 = asUInt(reset) \n node _T_107 = eq(_T_106, UInt<1>(0h0)) \n when _T_107 : \n node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_108 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_12 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_12 \n node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2)) \n node _T_110 = asUInt(reset) \n node _T_111 = eq(_T_110, UInt<1>(0h0)) \n when _T_111 : \n node _T_112 = eq(_T_109, UInt<1>(0h0)) \n when _T_112 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_13 \n assert(clock, _T_109, UInt<1>(0h1), \"\") : assert_13 \n node _T_113 = asUInt(reset) \n node _T_114 = eq(_T_113, UInt<1>(0h0)) \n when _T_114 : \n node _T_115 = eq(is_aligned, UInt<1>(0h0)) \n when _T_115 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_14 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_14 \n node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2)) \n node _T_117 = asUInt(reset) \n node _T_118 = eq(_T_117, UInt<1>(0h0)) \n when _T_118 : \n node _T_119 = eq(_T_116, UInt<1>(0h0)) \n when _T_119 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_15 \n assert(clock, _T_116, UInt<1>(0h1), \"\") : assert_15 \n node _T_120 = neq(io.in.a.bits.param, UInt<2>(0h0)) \n node _T_121 = asUInt(reset) \n node _T_122 = eq(_T_121, UInt<1>(0h0)) \n when _T_122 : \n node _T_123 = eq(_T_120, UInt<1>(0h0)) \n when _T_123 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_16 \n assert(clock, _T_120, UInt<1>(0h1), \"\") : assert_16 \n node _T_124 = not(io.in.a.bits.mask) \n node _T_125 = eq(_T_124, UInt<1>(0h0)) \n node _T_126 = asUInt(reset) \n node _T_127 = eq(_T_126, UInt<1>(0h0)) \n when _T_127 : \n node _T_128 = eq(_T_125, UInt<1>(0h0)) \n when _T_128 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_17 \n assert(clock, _T_125, UInt<1>(0h1), \"\") : assert_17 \n node _T_129 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_130 = asUInt(reset) \n node _T_131 = eq(_T_130, UInt<1>(0h0)) \n when _T_131 : \n node _T_132 = eq(_T_129, UInt<1>(0h0)) \n when _T_132 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_18 \n assert(clock, _T_129, UInt<1>(0h1), \"\") : assert_18 \n node _T_133 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) \n when _T_133 : \n node _T_134 = eq(UInt<2>(0h2), io.in.a.bits.size) \n node _T_135 = eq(io.in.a.bits.source, UInt<1>(0h0)) \n node _T_136 = and(_T_134, _T_135) \n node _T_137 = or(UInt<1>(0h0), _T_136) \n node _T_138 = asUInt(reset) \n node _T_139 = eq(_T_138, UInt<1>(0h0)) \n when _T_139 : \n node _T_140 = eq(_T_137, UInt<1>(0h0)) \n when _T_140 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_19 \n assert(clock, _T_137, UInt<1>(0h1), \"\") : assert_19 \n node _T_141 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_142 = leq(io.in.a.bits.size, UInt<2>(0h2)) \n node _T_143 = and(_T_141, _T_142) \n node _T_144 = or(UInt<1>(0h0), _T_143) \n node _T_145 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_146 = cvt(_T_145) \n node _T_147 = and(_T_146, asSInt(UInt<129>(0h100000000000000000000000000000000))) \n node _T_148 = asSInt(_T_147) \n node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) \n node _T_150 = and(_T_144, _T_149) \n node _T_151 = or(UInt<1>(0h0), _T_150) \n node _T_152 = asUInt(reset) \n node _T_153 = eq(_T_152, UInt<1>(0h0)) \n when _T_153 : \n node _T_154 = eq(_T_151, UInt<1>(0h0)) \n when _T_154 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_20 \n assert(clock, _T_151, UInt<1>(0h1), \"\") : assert_20 \n node _T_155 = asUInt(reset) \n node _T_156 = eq(_T_155, UInt<1>(0h0)) \n when _T_156 : \n node _T_157 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_157 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_21 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_21 \n node _T_158 = asUInt(reset) \n node _T_159 = eq(_T_158, UInt<1>(0h0)) \n when _T_159 : \n node _T_160 = eq(is_aligned, UInt<1>(0h0)) \n when _T_160 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_22 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_22 \n node _T_161 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_162 = asUInt(reset) \n node _T_163 = eq(_T_162, UInt<1>(0h0)) \n when _T_163 : \n node _T_164 = eq(_T_161, UInt<1>(0h0)) \n when _T_164 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_23 \n assert(clock, _T_161, UInt<1>(0h1), \"\") : assert_23 \n node _T_165 = eq(io.in.a.bits.mask, mask) \n node _T_166 = asUInt(reset) \n node _T_167 = eq(_T_166, UInt<1>(0h0)) \n when _T_167 : \n node _T_168 = eq(_T_165, UInt<1>(0h0)) \n when _T_168 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_24 \n assert(clock, _T_165, UInt<1>(0h1), \"\") : assert_24 \n node _T_169 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_170 = asUInt(reset) \n node _T_171 = eq(_T_170, UInt<1>(0h0)) \n when _T_171 : \n node _T_172 = eq(_T_169, UInt<1>(0h0)) \n when _T_172 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_25 \n assert(clock, _T_169, UInt<1>(0h1), \"\") : assert_25 \n node _T_173 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) \n when _T_173 : \n node _T_174 = eq(UInt<2>(0h2), io.in.a.bits.size) \n node _T_175 = eq(io.in.a.bits.source, UInt<1>(0h0)) \n node _T_176 = and(_T_174, _T_175) \n node _T_177 = or(UInt<1>(0h0), _T_176) \n node _T_178 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_179 = leq(io.in.a.bits.size, UInt<2>(0h2)) \n node _T_180 = and(_T_178, _T_179) \n node _T_181 = or(UInt<1>(0h0), _T_180) \n node _T_182 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_183 = cvt(_T_182) \n node _T_184 = and(_T_183, asSInt(UInt<129>(0h100000000000000000000000000000000))) \n node _T_185 = asSInt(_T_184) \n node _T_186 = eq(_T_185, asSInt(UInt<1>(0h0))) \n node _T_187 = and(_T_181, _T_186) \n node _T_188 = or(UInt<1>(0h0), _T_187) \n node _T_189 = and(_T_177, _T_188) \n node _T_190 = asUInt(reset) \n node _T_191 = eq(_T_190, UInt<1>(0h0)) \n when _T_191 : \n node _T_192 = eq(_T_189, UInt<1>(0h0)) \n when _T_192 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_26 \n assert(clock, _T_189, UInt<1>(0h1), \"\") : assert_26 \n node _T_193 = asUInt(reset) \n node _T_194 = eq(_T_193, UInt<1>(0h0)) \n when _T_194 : \n node _T_195 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_195 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_27 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_27 \n node _T_196 = asUInt(reset) \n node _T_197 = eq(_T_196, UInt<1>(0h0)) \n when _T_197 : \n node _T_198 = eq(is_aligned, UInt<1>(0h0)) \n when _T_198 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_28 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_28 \n node _T_199 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_200 = asUInt(reset) \n node _T_201 = eq(_T_200, UInt<1>(0h0)) \n when _T_201 : \n node _T_202 = eq(_T_199, UInt<1>(0h0)) \n when _T_202 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_29 \n assert(clock, _T_199, UInt<1>(0h1), \"\") : assert_29 \n node _T_203 = eq(io.in.a.bits.mask, mask) \n node _T_204 = asUInt(reset) \n node _T_205 = eq(_T_204, UInt<1>(0h0)) \n when _T_205 : \n node _T_206 = eq(_T_203, UInt<1>(0h0)) \n when _T_206 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_30 \n assert(clock, _T_203, UInt<1>(0h1), \"\") : assert_30 \n node _T_207 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) \n when _T_207 : \n node _T_208 = eq(io.in.a.bits.source, UInt<1>(0h0)) \n node _T_209 = and(UInt<1>(0h0), _T_208) \n node _T_210 = or(UInt<1>(0h0), _T_209) \n node _T_211 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_212 = leq(io.in.a.bits.size, UInt<2>(0h2)) \n node _T_213 = and(_T_211, _T_212) \n node _T_214 = or(UInt<1>(0h0), _T_213) \n node _T_215 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_216 = cvt(_T_215) \n node _T_217 = and(_T_216, asSInt(UInt<129>(0h100000000000000000000000000000000))) \n node _T_218 = asSInt(_T_217) \n node _T_219 = eq(_T_218, asSInt(UInt<1>(0h0))) \n node _T_220 = and(_T_214, _T_219) \n node _T_221 = or(UInt<1>(0h0), _T_220) \n node _T_222 = and(_T_210, _T_221) \n node _T_223 = asUInt(reset) \n node _T_224 = eq(_T_223, UInt<1>(0h0)) \n when _T_224 : \n node _T_225 = eq(_T_222, UInt<1>(0h0)) \n when _T_225 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_31 \n assert(clock, _T_222, UInt<1>(0h1), \"\") : assert_31 \n node _T_226 = asUInt(reset) \n node _T_227 = eq(_T_226, UInt<1>(0h0)) \n when _T_227 : \n node _T_228 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_228 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_32 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_32 \n node _T_229 = asUInt(reset) \n node _T_230 = eq(_T_229, UInt<1>(0h0)) \n when _T_230 : \n node _T_231 = eq(is_aligned, UInt<1>(0h0)) \n when _T_231 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_33 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_33 \n node _T_232 = eq(io.in.a.bits.param, UInt<1>(0h0)) \n node _T_233 = asUInt(reset) \n node _T_234 = eq(_T_233, UInt<1>(0h0)) \n when _T_234 : \n node _T_235 = eq(_T_232, UInt<1>(0h0)) \n when _T_235 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_34 \n assert(clock, _T_232, UInt<1>(0h1), \"\") : assert_34 \n node _T_236 = not(mask) \n node _T_237 = and(io.in.a.bits.mask, _T_236) \n node _T_238 = eq(_T_237, UInt<1>(0h0)) \n node _T_239 = asUInt(reset) \n node _T_240 = eq(_T_239, UInt<1>(0h0)) \n when _T_240 : \n node _T_241 = eq(_T_238, UInt<1>(0h0)) \n when _T_241 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_35 \n assert(clock, _T_238, UInt<1>(0h1), \"\") : assert_35 \n node _T_242 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) \n when _T_242 : \n node _T_243 = eq(io.in.a.bits.source, UInt<1>(0h0)) \n node _T_244 = and(UInt<1>(0h0), _T_243) \n node _T_245 = or(UInt<1>(0h0), _T_244) \n node _T_246 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_247 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_248 = cvt(_T_247) \n node _T_249 = and(_T_248, asSInt(UInt<129>(0h100000000000000000000000000000000))) \n node _T_250 = asSInt(_T_249) \n node _T_251 = eq(_T_250, asSInt(UInt<1>(0h0))) \n node _T_252 = and(_T_246, _T_251) \n node _T_253 = or(UInt<1>(0h0), _T_252) \n node _T_254 = and(_T_245, _T_253) \n node _T_255 = asUInt(reset) \n node _T_256 = eq(_T_255, UInt<1>(0h0)) \n when _T_256 : \n node _T_257 = eq(_T_254, UInt<1>(0h0)) \n when _T_257 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_36 \n assert(clock, _T_254, UInt<1>(0h1), \"\") : assert_36 \n node _T_258 = asUInt(reset) \n node _T_259 = eq(_T_258, UInt<1>(0h0)) \n when _T_259 : \n node _T_260 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_260 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_37 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_37 \n node _T_261 = asUInt(reset) \n node _T_262 = eq(_T_261, UInt<1>(0h0)) \n when _T_262 : \n node _T_263 = eq(is_aligned, UInt<1>(0h0)) \n when _T_263 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_38 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_38 \n node _T_264 = leq(io.in.a.bits.param, UInt<3>(0h4)) \n node _T_265 = asUInt(reset) \n node _T_266 = eq(_T_265, UInt<1>(0h0)) \n when _T_266 : \n node _T_267 = eq(_T_264, UInt<1>(0h0)) \n when _T_267 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_39 \n assert(clock, _T_264, UInt<1>(0h1), \"\") : assert_39 \n node _T_268 = eq(io.in.a.bits.mask, mask) \n node _T_269 = asUInt(reset) \n node _T_270 = eq(_T_269, UInt<1>(0h0)) \n when _T_270 : \n node _T_271 = eq(_T_268, UInt<1>(0h0)) \n when _T_271 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_40 \n assert(clock, _T_268, UInt<1>(0h1), \"\") : assert_40 \n node _T_272 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) \n when _T_272 : \n node _T_273 = eq(io.in.a.bits.source, UInt<1>(0h0)) \n node _T_274 = and(UInt<1>(0h0), _T_273) \n node _T_275 = or(UInt<1>(0h0), _T_274) \n node _T_276 = or(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_277 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_278 = cvt(_T_277) \n node _T_279 = and(_T_278, asSInt(UInt<129>(0h100000000000000000000000000000000))) \n node _T_280 = asSInt(_T_279) \n node _T_281 = eq(_T_280, asSInt(UInt<1>(0h0))) \n node _T_282 = and(_T_276, _T_281) \n node _T_283 = or(UInt<1>(0h0), _T_282) \n node _T_284 = and(_T_275, _T_283) \n node _T_285 = asUInt(reset) \n node _T_286 = eq(_T_285, UInt<1>(0h0)) \n when _T_286 : \n node _T_287 = eq(_T_284, UInt<1>(0h0)) \n when _T_287 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_41 \n assert(clock, _T_284, UInt<1>(0h1), \"\") : assert_41 \n node _T_288 = asUInt(reset) \n node _T_289 = eq(_T_288, UInt<1>(0h0)) \n when _T_289 : \n node _T_290 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_290 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_42 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_42 \n node _T_291 = asUInt(reset) \n node _T_292 = eq(_T_291, UInt<1>(0h0)) \n when _T_292 : \n node _T_293 = eq(is_aligned, UInt<1>(0h0)) \n when _T_293 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_43 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_43 \n node _T_294 = leq(io.in.a.bits.param, UInt<3>(0h3)) \n node _T_295 = asUInt(reset) \n node _T_296 = eq(_T_295, UInt<1>(0h0)) \n when _T_296 : \n node _T_297 = eq(_T_294, UInt<1>(0h0)) \n when _T_297 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_44 \n assert(clock, _T_294, UInt<1>(0h1), \"\") : assert_44 \n node _T_298 = eq(io.in.a.bits.mask, mask) \n node _T_299 = asUInt(reset) \n node _T_300 = eq(_T_299, UInt<1>(0h0)) \n when _T_300 : \n node _T_301 = eq(_T_298, UInt<1>(0h0)) \n when _T_301 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_45 \n assert(clock, _T_298, UInt<1>(0h1), \"\") : assert_45 \n node _T_302 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) \n when _T_302 : \n node _T_303 = eq(io.in.a.bits.source, UInt<1>(0h0)) \n node _T_304 = and(UInt<1>(0h0), _T_303) \n node _T_305 = or(UInt<1>(0h0), _T_304) \n node _T_306 = leq(UInt<1>(0h0), io.in.a.bits.size) \n node _T_307 = leq(io.in.a.bits.size, UInt<2>(0h2)) \n node _T_308 = and(_T_306, _T_307) \n node _T_309 = or(UInt<1>(0h0), _T_308) \n node _T_310 = xor(io.in.a.bits.address, UInt<1>(0h0)) \n node _T_311 = cvt(_T_310) \n node _T_312 = and(_T_311, asSInt(UInt<129>(0h100000000000000000000000000000000))) \n node _T_313 = asSInt(_T_312) \n node _T_314 = eq(_T_313, asSInt(UInt<1>(0h0))) \n node _T_315 = and(_T_309, _T_314) \n node _T_316 = or(UInt<1>(0h0), _T_315) \n node _T_317 = and(_T_305, _T_316) \n node _T_318 = asUInt(reset) \n node _T_319 = eq(_T_318, UInt<1>(0h0)) \n when _T_319 : \n node _T_320 = eq(_T_317, UInt<1>(0h0)) \n when _T_320 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_46 \n assert(clock, _T_317, UInt<1>(0h1), \"\") : assert_46 \n node _T_321 = asUInt(reset) \n node _T_322 = eq(_T_321, UInt<1>(0h0)) \n when _T_322 : \n node _T_323 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) \n when _T_323 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_47 \n assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), \"\") : assert_47 \n node _T_324 = asUInt(reset) \n node _T_325 = eq(_T_324, UInt<1>(0h0)) \n when _T_325 : \n node _T_326 = eq(is_aligned, UInt<1>(0h0)) \n when _T_326 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_48 \n assert(clock, is_aligned, UInt<1>(0h1), \"\") : assert_48 \n node _T_327 = leq(io.in.a.bits.param, UInt<1>(0h1)) \n node _T_328 = asUInt(reset) \n node _T_329 = eq(_T_328, UInt<1>(0h0)) \n when _T_329 : \n node _T_330 = eq(_T_327, UInt<1>(0h0)) \n when _T_330 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_49 \n assert(clock, _T_327, UInt<1>(0h1), \"\") : assert_49 \n node _T_331 = eq(io.in.a.bits.mask, mask) \n node _T_332 = asUInt(reset) \n node _T_333 = eq(_T_332, UInt<1>(0h0)) \n when _T_333 : \n node _T_334 = eq(_T_331, UInt<1>(0h0)) \n when _T_334 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_50 \n assert(clock, _T_331, UInt<1>(0h1), \"\") : assert_50 \n node _T_335 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) \n node _T_336 = asUInt(reset) \n node _T_337 = eq(_T_336, UInt<1>(0h0)) \n when _T_337 : \n node _T_338 = eq(_T_335, UInt<1>(0h0)) \n when _T_338 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_51 \n assert(clock, _T_335, UInt<1>(0h1), \"\") : assert_51 \n when io.in.d.valid : \n node _T_339 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_340 = asUInt(reset) \n node _T_341 = eq(_T_340, UInt<1>(0h0)) \n when _T_341 : \n node _T_342 = eq(_T_339, UInt<1>(0h0)) \n when _T_342 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_52 \n assert(clock, _T_339, UInt<1>(0h1), \"\") : assert_52 \n node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) \n wire _source_ok_WIRE_1 : UInt<1>[1] \n connect _source_ok_WIRE_1[0], _source_ok_T_1 \n node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h1)) \n node _T_343 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n when _T_343 : \n node _T_344 = asUInt(reset) \n node _T_345 = eq(_T_344, UInt<1>(0h0)) \n when _T_345 : \n node _T_346 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_346 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_53 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_53 \n node _T_347 = geq(io.in.d.bits.size, UInt<2>(0h2)) \n node _T_348 = asUInt(reset) \n node _T_349 = eq(_T_348, UInt<1>(0h0)) \n when _T_349 : \n node _T_350 = eq(_T_347, UInt<1>(0h0)) \n when _T_350 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_54 \n assert(clock, _T_347, UInt<1>(0h1), \"\") : assert_54 \n node _T_351 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_352 = asUInt(reset) \n node _T_353 = eq(_T_352, UInt<1>(0h0)) \n when _T_353 : \n node _T_354 = eq(_T_351, UInt<1>(0h0)) \n when _T_354 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_55 \n assert(clock, _T_351, UInt<1>(0h1), \"\") : assert_55 \n node _T_355 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_356 = asUInt(reset) \n node _T_357 = eq(_T_356, UInt<1>(0h0)) \n when _T_357 : \n node _T_358 = eq(_T_355, UInt<1>(0h0)) \n when _T_358 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_56 \n assert(clock, _T_355, UInt<1>(0h1), \"\") : assert_56 \n node _T_359 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_360 = asUInt(reset) \n node _T_361 = eq(_T_360, UInt<1>(0h0)) \n when _T_361 : \n node _T_362 = eq(_T_359, UInt<1>(0h0)) \n when _T_362 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_57 \n assert(clock, _T_359, UInt<1>(0h1), \"\") : assert_57 \n node _T_363 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) \n when _T_363 : \n node _T_364 = asUInt(reset) \n node _T_365 = eq(_T_364, UInt<1>(0h0)) \n when _T_365 : \n node _T_366 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_366 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_58 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_58 \n node _T_367 = asUInt(reset) \n node _T_368 = eq(_T_367, UInt<1>(0h0)) \n when _T_368 : \n node _T_369 = eq(sink_ok, UInt<1>(0h0)) \n when _T_369 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_59 \n assert(clock, sink_ok, UInt<1>(0h1), \"\") : assert_59 \n node _T_370 = geq(io.in.d.bits.size, UInt<2>(0h2)) \n node _T_371 = asUInt(reset) \n node _T_372 = eq(_T_371, UInt<1>(0h0)) \n when _T_372 : \n node _T_373 = eq(_T_370, UInt<1>(0h0)) \n when _T_373 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_60 \n assert(clock, _T_370, UInt<1>(0h1), \"\") : assert_60 \n node _T_374 = leq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_375 = asUInt(reset) \n node _T_376 = eq(_T_375, UInt<1>(0h0)) \n when _T_376 : \n node _T_377 = eq(_T_374, UInt<1>(0h0)) \n when _T_377 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_61 \n assert(clock, _T_374, UInt<1>(0h1), \"\") : assert_61 \n node _T_378 = neq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_379 = asUInt(reset) \n node _T_380 = eq(_T_379, UInt<1>(0h0)) \n when _T_380 : \n node _T_381 = eq(_T_378, UInt<1>(0h0)) \n when _T_381 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_62 \n assert(clock, _T_378, UInt<1>(0h1), \"\") : assert_62 \n node _T_382 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_383 = asUInt(reset) \n node _T_384 = eq(_T_383, UInt<1>(0h0)) \n when _T_384 : \n node _T_385 = eq(_T_382, UInt<1>(0h0)) \n when _T_385 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_63 \n assert(clock, _T_382, UInt<1>(0h1), \"\") : assert_63 \n node _T_386 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_387 = or(UInt<1>(0h1), _T_386) \n node _T_388 = asUInt(reset) \n node _T_389 = eq(_T_388, UInt<1>(0h0)) \n when _T_389 : \n node _T_390 = eq(_T_387, UInt<1>(0h0)) \n when _T_390 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_64 \n assert(clock, _T_387, UInt<1>(0h1), \"\") : assert_64 \n node _T_391 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) \n when _T_391 : \n node _T_392 = asUInt(reset) \n node _T_393 = eq(_T_392, UInt<1>(0h0)) \n when _T_393 : \n node _T_394 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_394 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_65 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_65 \n node _T_395 = asUInt(reset) \n node _T_396 = eq(_T_395, UInt<1>(0h0)) \n when _T_396 : \n node _T_397 = eq(sink_ok, UInt<1>(0h0)) \n when _T_397 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_66 \n assert(clock, sink_ok, UInt<1>(0h1), \"\") : assert_66 \n node _T_398 = geq(io.in.d.bits.size, UInt<2>(0h2)) \n node _T_399 = asUInt(reset) \n node _T_400 = eq(_T_399, UInt<1>(0h0)) \n when _T_400 : \n node _T_401 = eq(_T_398, UInt<1>(0h0)) \n when _T_401 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_67 \n assert(clock, _T_398, UInt<1>(0h1), \"\") : assert_67 \n node _T_402 = leq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_403 = asUInt(reset) \n node _T_404 = eq(_T_403, UInt<1>(0h0)) \n when _T_404 : \n node _T_405 = eq(_T_402, UInt<1>(0h0)) \n when _T_405 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_68 \n assert(clock, _T_402, UInt<1>(0h1), \"\") : assert_68 \n node _T_406 = neq(io.in.d.bits.param, UInt<2>(0h2)) \n node _T_407 = asUInt(reset) \n node _T_408 = eq(_T_407, UInt<1>(0h0)) \n when _T_408 : \n node _T_409 = eq(_T_406, UInt<1>(0h0)) \n when _T_409 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_69 \n assert(clock, _T_406, UInt<1>(0h1), \"\") : assert_69 \n node _T_410 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_411 = or(_T_410, io.in.d.bits.corrupt) \n node _T_412 = asUInt(reset) \n node _T_413 = eq(_T_412, UInt<1>(0h0)) \n when _T_413 : \n node _T_414 = eq(_T_411, UInt<1>(0h0)) \n when _T_414 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_70 \n assert(clock, _T_411, UInt<1>(0h1), \"\") : assert_70 \n node _T_415 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_416 = or(UInt<1>(0h1), _T_415) \n node _T_417 = asUInt(reset) \n node _T_418 = eq(_T_417, UInt<1>(0h0)) \n when _T_418 : \n node _T_419 = eq(_T_416, UInt<1>(0h0)) \n when _T_419 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_71 \n assert(clock, _T_416, UInt<1>(0h1), \"\") : assert_71 \n node _T_420 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) \n when _T_420 : \n node _T_421 = asUInt(reset) \n node _T_422 = eq(_T_421, UInt<1>(0h0)) \n when _T_422 : \n node _T_423 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_423 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_72 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_72 \n node _T_424 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_425 = asUInt(reset) \n node _T_426 = eq(_T_425, UInt<1>(0h0)) \n when _T_426 : \n node _T_427 = eq(_T_424, UInt<1>(0h0)) \n when _T_427 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_73 \n assert(clock, _T_424, UInt<1>(0h1), \"\") : assert_73 \n node _T_428 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_429 = asUInt(reset) \n node _T_430 = eq(_T_429, UInt<1>(0h0)) \n when _T_430 : \n node _T_431 = eq(_T_428, UInt<1>(0h0)) \n when _T_431 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_74 \n assert(clock, _T_428, UInt<1>(0h1), \"\") : assert_74 \n node _T_432 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_433 = or(UInt<1>(0h1), _T_432) \n node _T_434 = asUInt(reset) \n node _T_435 = eq(_T_434, UInt<1>(0h0)) \n when _T_435 : \n node _T_436 = eq(_T_433, UInt<1>(0h0)) \n when _T_436 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_75 \n assert(clock, _T_433, UInt<1>(0h1), \"\") : assert_75 \n node _T_437 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) \n when _T_437 : \n node _T_438 = asUInt(reset) \n node _T_439 = eq(_T_438, UInt<1>(0h0)) \n when _T_439 : \n node _T_440 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_440 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_76 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_76 \n node _T_441 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_442 = asUInt(reset) \n node _T_443 = eq(_T_442, UInt<1>(0h0)) \n when _T_443 : \n node _T_444 = eq(_T_441, UInt<1>(0h0)) \n when _T_444 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_77 \n assert(clock, _T_441, UInt<1>(0h1), \"\") : assert_77 \n node _T_445 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_446 = or(_T_445, io.in.d.bits.corrupt) \n node _T_447 = asUInt(reset) \n node _T_448 = eq(_T_447, UInt<1>(0h0)) \n when _T_448 : \n node _T_449 = eq(_T_446, UInt<1>(0h0)) \n when _T_449 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_78 \n assert(clock, _T_446, UInt<1>(0h1), \"\") : assert_78 \n node _T_450 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_451 = or(UInt<1>(0h1), _T_450) \n node _T_452 = asUInt(reset) \n node _T_453 = eq(_T_452, UInt<1>(0h0)) \n when _T_453 : \n node _T_454 = eq(_T_451, UInt<1>(0h0)) \n when _T_454 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_79 \n assert(clock, _T_451, UInt<1>(0h1), \"\") : assert_79 \n node _T_455 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) \n when _T_455 : \n node _T_456 = asUInt(reset) \n node _T_457 = eq(_T_456, UInt<1>(0h0)) \n when _T_457 : \n node _T_458 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) \n when _T_458 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_80 \n assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), \"\") : assert_80 \n node _T_459 = eq(io.in.d.bits.param, UInt<1>(0h0)) \n node _T_460 = asUInt(reset) \n node _T_461 = eq(_T_460, UInt<1>(0h0)) \n when _T_461 : \n node _T_462 = eq(_T_459, UInt<1>(0h0)) \n when _T_462 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_81 \n assert(clock, _T_459, UInt<1>(0h1), \"\") : assert_81 \n node _T_463 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) \n node _T_464 = asUInt(reset) \n node _T_465 = eq(_T_464, UInt<1>(0h0)) \n when _T_465 : \n node _T_466 = eq(_T_463, UInt<1>(0h0)) \n when _T_466 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_82 \n assert(clock, _T_463, UInt<1>(0h1), \"\") : assert_82 \n node _T_467 = eq(io.in.d.bits.denied, UInt<1>(0h0)) \n node _T_468 = or(UInt<1>(0h1), _T_467) \n node _T_469 = asUInt(reset) \n node _T_470 = eq(_T_469, UInt<1>(0h0)) \n when _T_470 : \n node _T_471 = eq(_T_468, UInt<1>(0h0)) \n when _T_471 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_83 \n assert(clock, _T_468, UInt<1>(0h1), \"\") : assert_83 \n wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE.bits.corrupt, UInt<1>(0h0) \n connect _WIRE.bits.data, UInt<32>(0h0) \n connect _WIRE.bits.mask, UInt<4>(0h0) \n connect _WIRE.bits.address, UInt<128>(0h0) \n connect _WIRE.bits.source, UInt<1>(0h0) \n connect _WIRE.bits.size, UInt<2>(0h0) \n connect _WIRE.bits.param, UInt<2>(0h0) \n connect _WIRE.bits.opcode, UInt<3>(0h0) \n connect _WIRE.valid, UInt<1>(0h0) \n connect _WIRE.ready, UInt<1>(0h0) \n wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_1.bits, _WIRE.bits \n connect _WIRE_1.valid, _WIRE.valid \n connect _WIRE_1.ready, _WIRE.ready \n node _T_472 = eq(_WIRE_1.valid, UInt<1>(0h0)) \n node _T_473 = asUInt(reset) \n node _T_474 = eq(_T_473, UInt<1>(0h0)) \n when _T_474 : \n node _T_475 = eq(_T_472, UInt<1>(0h0)) \n when _T_475 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_84 \n assert(clock, _T_472, UInt<1>(0h1), \"\") : assert_84 \n wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_2.bits.data, UInt<32>(0h0) \n connect _WIRE_2.bits.address, UInt<128>(0h0) \n connect _WIRE_2.bits.source, UInt<1>(0h0) \n connect _WIRE_2.bits.size, UInt<2>(0h0) \n connect _WIRE_2.bits.param, UInt<3>(0h0) \n connect _WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _WIRE_2.valid, UInt<1>(0h0) \n connect _WIRE_2.ready, UInt<1>(0h0) \n wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_3.bits, _WIRE_2.bits \n connect _WIRE_3.valid, _WIRE_2.valid \n connect _WIRE_3.ready, _WIRE_2.ready \n node _T_476 = eq(_WIRE_3.valid, UInt<1>(0h0)) \n node _T_477 = asUInt(reset) \n node _T_478 = eq(_T_477, UInt<1>(0h0)) \n when _T_478 : \n node _T_479 = eq(_T_476, UInt<1>(0h0)) \n when _T_479 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_85 \n assert(clock, _T_476, UInt<1>(0h1), \"\") : assert_85 \n wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_4.bits.sink, UInt<1>(0h0) \n connect _WIRE_4.valid, UInt<1>(0h0) \n connect _WIRE_4.ready, UInt<1>(0h0) \n wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} \n connect _WIRE_5.bits, _WIRE_4.bits \n connect _WIRE_5.valid, _WIRE_4.valid \n connect _WIRE_5.ready, _WIRE_4.ready \n node _T_480 = eq(_WIRE_5.valid, UInt<1>(0h0)) \n node _T_481 = asUInt(reset) \n node _T_482 = eq(_T_481, UInt<1>(0h0)) \n when _T_482 : \n node _T_483 = eq(_T_480, UInt<1>(0h0)) \n when _T_483 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_86 \n assert(clock, _T_480, UInt<1>(0h1), \"\") : assert_86 \n node _a_first_T = and(io.in.a.ready, io.in.a.valid) \n node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) \n node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) \n node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) \n node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) \n node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) \n node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) \n node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) \n regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) \n node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) \n node a_first_counter1 = tail(_a_first_counter1_T, 1) \n node a_first = eq(a_first_counter, UInt<1>(0h0)) \n node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) \n node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) \n node a_first_last = or(_a_first_last_T, _a_first_last_T_1) \n node a_first_done = and(a_first_last, _a_first_T) \n node _a_first_count_T = not(a_first_counter1) \n node a_first_count = and(a_first_beats1, _a_first_count_T) \n when _a_first_T : \n node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) \n connect a_first_counter, _a_first_counter_T \n reg opcode : UInt, clock \n reg param : UInt, clock \n reg size : UInt, clock \n reg source : UInt, clock \n reg address : UInt, clock \n node _T_484 = eq(a_first, UInt<1>(0h0)) \n node _T_485 = and(io.in.a.valid, _T_484) \n when _T_485 : \n node _T_486 = eq(io.in.a.bits.opcode, opcode) \n node _T_487 = asUInt(reset) \n node _T_488 = eq(_T_487, UInt<1>(0h0)) \n when _T_488 : \n node _T_489 = eq(_T_486, UInt<1>(0h0)) \n when _T_489 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_87 \n assert(clock, _T_486, UInt<1>(0h1), \"\") : assert_87 \n node _T_490 = eq(io.in.a.bits.param, param) \n node _T_491 = asUInt(reset) \n node _T_492 = eq(_T_491, UInt<1>(0h0)) \n when _T_492 : \n node _T_493 = eq(_T_490, UInt<1>(0h0)) \n when _T_493 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_88 \n assert(clock, _T_490, UInt<1>(0h1), \"\") : assert_88 \n node _T_494 = eq(io.in.a.bits.size, size) \n node _T_495 = asUInt(reset) \n node _T_496 = eq(_T_495, UInt<1>(0h0)) \n when _T_496 : \n node _T_497 = eq(_T_494, UInt<1>(0h0)) \n when _T_497 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_89 \n assert(clock, _T_494, UInt<1>(0h1), \"\") : assert_89 \n node _T_498 = eq(io.in.a.bits.source, source) \n node _T_499 = asUInt(reset) \n node _T_500 = eq(_T_499, UInt<1>(0h0)) \n when _T_500 : \n node _T_501 = eq(_T_498, UInt<1>(0h0)) \n when _T_501 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_90 \n assert(clock, _T_498, UInt<1>(0h1), \"\") : assert_90 \n node _T_502 = eq(io.in.a.bits.address, address) \n node _T_503 = asUInt(reset) \n node _T_504 = eq(_T_503, UInt<1>(0h0)) \n when _T_504 : \n node _T_505 = eq(_T_502, UInt<1>(0h0)) \n when _T_505 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_91 \n assert(clock, _T_502, UInt<1>(0h1), \"\") : assert_91 \n node _T_506 = and(io.in.a.ready, io.in.a.valid) \n node _T_507 = and(_T_506, a_first) \n when _T_507 : \n connect opcode, io.in.a.bits.opcode \n connect param, io.in.a.bits.param \n connect size, io.in.a.bits.size \n connect source, io.in.a.bits.source \n connect address, io.in.a.bits.address \n node _d_first_T = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) \n node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) \n node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) \n node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) \n node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) \n regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) \n node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) \n node d_first_counter1 = tail(_d_first_counter1_T, 1) \n node d_first = eq(d_first_counter, UInt<1>(0h0)) \n node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) \n node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) \n node d_first_last = or(_d_first_last_T, _d_first_last_T_1) \n node d_first_done = and(d_first_last, _d_first_T) \n node _d_first_count_T = not(d_first_counter1) \n node d_first_count = and(d_first_beats1, _d_first_count_T) \n when _d_first_T : \n node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) \n connect d_first_counter, _d_first_counter_T \n reg opcode_1 : UInt, clock \n reg param_1 : UInt, clock \n reg size_1 : UInt, clock \n reg source_1 : UInt, clock \n reg sink : UInt, clock \n reg denied : UInt<1>, clock \n node _T_508 = eq(d_first, UInt<1>(0h0)) \n node _T_509 = and(io.in.d.valid, _T_508) \n when _T_509 : \n node _T_510 = eq(io.in.d.bits.opcode, opcode_1) \n node _T_511 = asUInt(reset) \n node _T_512 = eq(_T_511, UInt<1>(0h0)) \n when _T_512 : \n node _T_513 = eq(_T_510, UInt<1>(0h0)) \n when _T_513 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_92 \n assert(clock, _T_510, UInt<1>(0h1), \"\") : assert_92 \n node _T_514 = eq(io.in.d.bits.param, param_1) \n node _T_515 = asUInt(reset) \n node _T_516 = eq(_T_515, UInt<1>(0h0)) \n when _T_516 : \n node _T_517 = eq(_T_514, UInt<1>(0h0)) \n when _T_517 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_93 \n assert(clock, _T_514, UInt<1>(0h1), \"\") : assert_93 \n node _T_518 = eq(io.in.d.bits.size, size_1) \n node _T_519 = asUInt(reset) \n node _T_520 = eq(_T_519, UInt<1>(0h0)) \n when _T_520 : \n node _T_521 = eq(_T_518, UInt<1>(0h0)) \n when _T_521 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_94 \n assert(clock, _T_518, UInt<1>(0h1), \"\") : assert_94 \n node _T_522 = eq(io.in.d.bits.source, source_1) \n node _T_523 = asUInt(reset) \n node _T_524 = eq(_T_523, UInt<1>(0h0)) \n when _T_524 : \n node _T_525 = eq(_T_522, UInt<1>(0h0)) \n when _T_525 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_95 \n assert(clock, _T_522, UInt<1>(0h1), \"\") : assert_95 \n node _T_526 = eq(io.in.d.bits.sink, sink) \n node _T_527 = asUInt(reset) \n node _T_528 = eq(_T_527, UInt<1>(0h0)) \n when _T_528 : \n node _T_529 = eq(_T_526, UInt<1>(0h0)) \n when _T_529 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_96 \n assert(clock, _T_526, UInt<1>(0h1), \"\") : assert_96 \n node _T_530 = eq(io.in.d.bits.denied, denied) \n node _T_531 = asUInt(reset) \n node _T_532 = eq(_T_531, UInt<1>(0h0)) \n when _T_532 : \n node _T_533 = eq(_T_530, UInt<1>(0h0)) \n when _T_533 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_97 \n assert(clock, _T_530, UInt<1>(0h1), \"\") : assert_97 \n node _T_534 = and(io.in.d.ready, io.in.d.valid) \n node _T_535 = and(_T_534, d_first) \n when _T_535 : \n connect opcode_1, io.in.d.bits.opcode \n connect param_1, io.in.d.bits.param \n connect size_1, io.in.d.bits.size \n connect source_1, io.in.d.bits.source \n connect sink, io.in.d.bits.sink \n connect denied, io.in.d.bits.denied \n regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) \n regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) \n regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) \n node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) \n node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) \n node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) \n node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) \n node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) \n node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) \n node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) \n node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) \n regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) \n node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) \n node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) \n node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) \n node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) \n node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) \n node a_first_done_1 = and(a_first_last_1, _a_first_T_1) \n node _a_first_count_T_1 = not(a_first_counter1_1) \n node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) \n when _a_first_T_1 : \n node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) \n connect a_first_counter_1, _a_first_counter_T_1 \n node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) \n node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) \n node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) \n node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) \n node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) \n regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) \n node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) \n node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) \n node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) \n node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) \n node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) \n node d_first_done_1 = and(d_first_last_1, _d_first_T_1) \n node _d_first_count_T_1 = not(d_first_counter1_1) \n node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) \n when _d_first_T_1 : \n node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) \n connect d_first_counter_1, _d_first_counter_T_1 \n wire a_set : UInt<1> \n connect a_set, UInt<1>(0h0) \n wire a_set_wo_ready : UInt<1> \n connect a_set_wo_ready, UInt<1>(0h0) \n wire a_opcodes_set : UInt<4> \n connect a_opcodes_set, UInt<4>(0h0) \n wire a_sizes_set : UInt<4> \n connect a_sizes_set, UInt<4>(0h0) \n wire a_opcode_lookup : UInt<3> \n connect a_opcode_lookup, UInt<3>(0h0) \n node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) \n node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) \n node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) \n node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) \n node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) \n node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) \n connect a_opcode_lookup, _a_opcode_lookup_T_7 \n wire a_size_lookup : UInt<4> \n connect a_size_lookup, UInt<4>(0h0) \n node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) \n node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) \n node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) \n node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) \n node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) \n node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) \n connect a_size_lookup, _a_size_lookup_T_7 \n wire responseMap : UInt<3>[8] \n connect responseMap[0], UInt<1>(0h0) \n connect responseMap[1], UInt<1>(0h0) \n connect responseMap[2], UInt<1>(0h1) \n connect responseMap[3], UInt<1>(0h1) \n connect responseMap[4], UInt<1>(0h1) \n connect responseMap[5], UInt<2>(0h2) \n connect responseMap[6], UInt<3>(0h4) \n connect responseMap[7], UInt<3>(0h4) \n wire responseMapSecondOption : UInt<3>[8] \n connect responseMapSecondOption[0], UInt<1>(0h0) \n connect responseMapSecondOption[1], UInt<1>(0h0) \n connect responseMapSecondOption[2], UInt<1>(0h1) \n connect responseMapSecondOption[3], UInt<1>(0h1) \n connect responseMapSecondOption[4], UInt<1>(0h1) \n connect responseMapSecondOption[5], UInt<2>(0h2) \n connect responseMapSecondOption[6], UInt<3>(0h5) \n connect responseMapSecondOption[7], UInt<3>(0h4) \n wire a_opcodes_set_interm : UInt<4> \n connect a_opcodes_set_interm, UInt<4>(0h0) \n wire a_sizes_set_interm : UInt<3> \n connect a_sizes_set_interm, UInt<3>(0h0) \n node _T_536 = and(io.in.a.valid, a_first_1) \n node _T_537 = and(_T_536, UInt<1>(0h1)) \n when _T_537 : \n node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) \n connect a_set_wo_ready, _a_set_wo_ready_T \n node _T_538 = and(io.in.a.ready, io.in.a.valid) \n node _T_539 = and(_T_538, a_first_1) \n node _T_540 = and(_T_539, UInt<1>(0h1)) \n when _T_540 : \n node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) \n connect a_set, _a_set_T \n node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) \n node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) \n connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 \n node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) \n node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) \n connect a_sizes_set_interm, _a_sizes_set_interm_T_1 \n node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) \n node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) \n connect a_opcodes_set, _a_opcodes_set_T_1 \n node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) \n node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) \n connect a_sizes_set, _a_sizes_set_T_1 \n node _T_541 = dshr(inflight, io.in.a.bits.source) \n node _T_542 = bits(_T_541, 0, 0) \n node _T_543 = eq(_T_542, UInt<1>(0h0)) \n node _T_544 = asUInt(reset) \n node _T_545 = eq(_T_544, UInt<1>(0h0)) \n when _T_545 : \n node _T_546 = eq(_T_543, UInt<1>(0h0)) \n when _T_546 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_98 \n assert(clock, _T_543, UInt<1>(0h1), \"\") : assert_98 \n wire d_clr : UInt<1> \n connect d_clr, UInt<1>(0h0) \n wire d_clr_wo_ready : UInt<1> \n connect d_clr_wo_ready, UInt<1>(0h0) \n wire d_opcodes_clr : UInt<4> \n connect d_opcodes_clr, UInt<4>(0h0) \n wire d_sizes_clr : UInt<4> \n connect d_sizes_clr, UInt<4>(0h0) \n node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_547 = and(io.in.d.valid, d_first_1) \n node _T_548 = and(_T_547, UInt<1>(0h1)) \n node _T_549 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_550 = and(_T_548, _T_549) \n when _T_550 : \n node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_wo_ready, _d_clr_wo_ready_T \n node _T_551 = and(io.in.d.ready, io.in.d.valid) \n node _T_552 = and(_T_551, d_first_1) \n node _T_553 = and(_T_552, UInt<1>(0h1)) \n node _T_554 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_555 = and(_T_553, _T_554) \n when _T_555 : \n node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr, _d_clr_T \n node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) \n node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) \n node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) \n node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) \n connect d_opcodes_clr, _d_opcodes_clr_T_5 \n node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) \n node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) \n node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) \n node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) \n connect d_sizes_clr, _d_sizes_clr_T_5 \n node _T_556 = and(io.in.d.valid, d_first_1) \n node _T_557 = and(_T_556, UInt<1>(0h1)) \n node _T_558 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_559 = and(_T_557, _T_558) \n when _T_559 : \n node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) \n node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) \n node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) \n node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) \n node _T_560 = dshr(inflight, io.in.d.bits.source) \n node _T_561 = bits(_T_560, 0, 0) \n node _T_562 = or(_T_561, same_cycle_resp) \n node _T_563 = asUInt(reset) \n node _T_564 = eq(_T_563, UInt<1>(0h0)) \n when _T_564 : \n node _T_565 = eq(_T_562, UInt<1>(0h0)) \n when _T_565 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_99 \n assert(clock, _T_562, UInt<1>(0h1), \"\") : assert_99 \n when same_cycle_resp : \n node _T_566 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) \n node _T_567 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) \n node _T_568 = or(_T_566, _T_567) \n node _T_569 = asUInt(reset) \n node _T_570 = eq(_T_569, UInt<1>(0h0)) \n when _T_570 : \n node _T_571 = eq(_T_568, UInt<1>(0h0)) \n when _T_571 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_100 \n assert(clock, _T_568, UInt<1>(0h1), \"\") : assert_100 \n node _T_572 = eq(io.in.a.bits.size, io.in.d.bits.size) \n node _T_573 = asUInt(reset) \n node _T_574 = eq(_T_573, UInt<1>(0h0)) \n when _T_574 : \n node _T_575 = eq(_T_572, UInt<1>(0h0)) \n when _T_575 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_101 \n assert(clock, _T_572, UInt<1>(0h1), \"\") : assert_101 \n else :\n\n node _T_576 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) \n node _T_577 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) \n node _T_578 = or(_T_576, _T_577) \n node _T_579 = asUInt(reset) \n node _T_580 = eq(_T_579, UInt<1>(0h0)) \n when _T_580 : \n node _T_581 = eq(_T_578, UInt<1>(0h0)) \n when _T_581 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_102 \n assert(clock, _T_578, UInt<1>(0h1), \"\") : assert_102 \n node _T_582 = eq(io.in.d.bits.size, a_size_lookup) \n node _T_583 = asUInt(reset) \n node _T_584 = eq(_T_583, UInt<1>(0h0)) \n when _T_584 : \n node _T_585 = eq(_T_582, UInt<1>(0h0)) \n when _T_585 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_103 \n assert(clock, _T_582, UInt<1>(0h1), \"\") : assert_103 \n node _T_586 = and(io.in.d.valid, d_first_1) \n node _T_587 = and(_T_586, a_first_1) \n node _T_588 = and(_T_587, io.in.a.valid) \n node _T_589 = eq(io.in.a.bits.source, io.in.d.bits.source) \n node _T_590 = and(_T_588, _T_589) \n node _T_591 = eq(d_release_ack, UInt<1>(0h0)) \n node _T_592 = and(_T_590, _T_591) \n when _T_592 : \n node _T_593 = eq(io.in.d.ready, UInt<1>(0h0)) \n node _T_594 = or(_T_593, io.in.a.ready) \n node _T_595 = asUInt(reset) \n node _T_596 = eq(_T_595, UInt<1>(0h0)) \n when _T_596 : \n node _T_597 = eq(_T_594, UInt<1>(0h0)) \n when _T_597 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ready check\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_104 \n assert(clock, _T_594, UInt<1>(0h1), \"\") : assert_104 \n node _inflight_T = or(inflight, a_set) \n node _inflight_T_1 = not(d_clr) \n node _inflight_T_2 = and(_inflight_T, _inflight_T_1) \n connect inflight, _inflight_T_2 \n node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) \n node _inflight_opcodes_T_1 = not(d_opcodes_clr) \n node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) \n connect inflight_opcodes, _inflight_opcodes_T_2 \n node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) \n node _inflight_sizes_T_1 = not(d_sizes_clr) \n node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) \n connect inflight_sizes, _inflight_sizes_T_2 \n regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) \n inst plusarg_reader of plusarg_reader_107 \n node _T_598 = orr(inflight) \n node _T_599 = eq(_T_598, UInt<1>(0h0)) \n node _T_600 = eq(plusarg_reader.out, UInt<1>(0h0)) \n node _T_601 = or(_T_599, _T_600) \n node _T_602 = lt(watchdog, plusarg_reader.out) \n node _T_603 = or(_T_601, _T_602) \n node _T_604 = asUInt(reset) \n node _T_605 = eq(_T_604, UInt<1>(0h0)) \n when _T_605 : \n node _T_606 = eq(_T_603, UInt<1>(0h0)) \n when _T_606 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_105 \n assert(clock, _T_603, UInt<1>(0h1), \"\") : assert_105 \n node _watchdog_T = add(watchdog, UInt<1>(0h1)) \n node _watchdog_T_1 = tail(_watchdog_T, 1) \n connect watchdog, _watchdog_T_1 \n node _T_607 = and(io.in.a.ready, io.in.a.valid) \n node _T_608 = and(io.in.d.ready, io.in.d.valid) \n node _T_609 = or(_T_607, _T_608) \n when _T_609 : \n connect watchdog, UInt<1>(0h0) \n regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) \n regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) \n regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) \n wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_first_WIRE.bits.data, UInt<32>(0h0) \n connect _c_first_WIRE.bits.address, UInt<128>(0h0) \n connect _c_first_WIRE.bits.source, UInt<1>(0h0) \n connect _c_first_WIRE.bits.size, UInt<2>(0h0) \n connect _c_first_WIRE.bits.param, UInt<3>(0h0) \n connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_first_WIRE.valid, UInt<1>(0h0) \n connect _c_first_WIRE.ready, UInt<1>(0h0) \n wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_first_WIRE_1.bits, _c_first_WIRE.bits \n connect _c_first_WIRE_1.valid, _c_first_WIRE.valid \n connect _c_first_WIRE_1.ready, _c_first_WIRE.ready \n wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) \n connect _c_first_WIRE_2.bits.address, UInt<128>(0h0) \n connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) \n connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) \n connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) \n connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _c_first_WIRE_2.valid, UInt<1>(0h0) \n connect _c_first_WIRE_2.ready, UInt<1>(0h0) \n wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits \n connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid \n connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready \n node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) \n node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) \n node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) \n node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) \n node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) \n node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) \n node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) \n regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) \n node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) \n node c_first_counter1 = tail(_c_first_counter1_T, 1) \n node c_first = eq(c_first_counter, UInt<1>(0h0)) \n node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) \n node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) \n node c_first_last = or(_c_first_last_T, _c_first_last_T_1) \n node c_first_done = and(c_first_last, _c_first_T) \n node _c_first_count_T = not(c_first_counter1) \n node c_first_count = and(c_first_beats1, _c_first_count_T) \n when _c_first_T : \n node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) \n connect c_first_counter, _c_first_counter_T \n node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) \n node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) \n node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) \n node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) \n node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) \n node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) \n node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) \n regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) \n node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) \n node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) \n node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) \n node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) \n node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) \n node d_first_done_2 = and(d_first_last_2, _d_first_T_2) \n node _d_first_count_T_2 = not(d_first_counter1_2) \n node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) \n when _d_first_T_2 : \n node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) \n connect d_first_counter_2, _d_first_counter_T_2 \n wire c_set : UInt<1> \n connect c_set, UInt<1>(0h0) \n wire c_set_wo_ready : UInt<1> \n connect c_set_wo_ready, UInt<1>(0h0) \n wire c_opcodes_set : UInt<4> \n connect c_opcodes_set, UInt<4>(0h0) \n wire c_sizes_set : UInt<4> \n connect c_sizes_set, UInt<4>(0h0) \n wire c_opcode_lookup : UInt<4> \n connect c_opcode_lookup, UInt<4>(0h0) \n wire c_size_lookup : UInt<4> \n connect c_size_lookup, UInt<4>(0h0) \n node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) \n node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) \n node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) \n node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) \n node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) \n node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) \n connect c_opcode_lookup, _c_opcode_lookup_T_7 \n node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) \n node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) \n node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) \n node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) \n node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) \n node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) \n connect c_size_lookup, _c_size_lookup_T_7 \n wire c_opcodes_set_interm : UInt<4> \n connect c_opcodes_set_interm, UInt<4>(0h0) \n wire c_sizes_set_interm : UInt<3> \n connect c_sizes_set_interm, UInt<3>(0h0) \n wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_6.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_6.bits.data, UInt<32>(0h0) \n connect _WIRE_6.bits.address, UInt<128>(0h0) \n connect _WIRE_6.bits.source, UInt<1>(0h0) \n connect _WIRE_6.bits.size, UInt<2>(0h0) \n connect _WIRE_6.bits.param, UInt<3>(0h0) \n connect _WIRE_6.bits.opcode, UInt<3>(0h0) \n connect _WIRE_6.valid, UInt<1>(0h0) \n connect _WIRE_6.ready, UInt<1>(0h0) \n wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_7.bits, _WIRE_6.bits \n connect _WIRE_7.valid, _WIRE_6.valid \n connect _WIRE_7.ready, _WIRE_6.ready \n node _T_610 = and(_WIRE_7.valid, c_first) \n wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_8.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_8.bits.data, UInt<32>(0h0) \n connect _WIRE_8.bits.address, UInt<128>(0h0) \n connect _WIRE_8.bits.source, UInt<1>(0h0) \n connect _WIRE_8.bits.size, UInt<2>(0h0) \n connect _WIRE_8.bits.param, UInt<3>(0h0) \n connect _WIRE_8.bits.opcode, UInt<3>(0h0) \n connect _WIRE_8.valid, UInt<1>(0h0) \n connect _WIRE_8.ready, UInt<1>(0h0) \n wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_9.bits, _WIRE_8.bits \n connect _WIRE_9.valid, _WIRE_8.valid \n connect _WIRE_9.ready, _WIRE_8.ready \n node _T_611 = bits(_WIRE_9.bits.opcode, 2, 2) \n node _T_612 = bits(_WIRE_9.bits.opcode, 1, 1) \n node _T_613 = and(_T_611, _T_612) \n node _T_614 = and(_T_610, _T_613) \n when _T_614 : \n wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) \n connect _c_set_wo_ready_WIRE.bits.address, UInt<128>(0h0) \n connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) \n connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) \n connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) \n connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) \n wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits \n connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid \n connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready \n node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) \n connect c_set_wo_ready, _c_set_wo_ready_T \n wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_10.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_10.bits.data, UInt<32>(0h0) \n connect _WIRE_10.bits.address, UInt<128>(0h0) \n connect _WIRE_10.bits.source, UInt<1>(0h0) \n connect _WIRE_10.bits.size, UInt<2>(0h0) \n connect _WIRE_10.bits.param, UInt<3>(0h0) \n connect _WIRE_10.bits.opcode, UInt<3>(0h0) \n connect _WIRE_10.valid, UInt<1>(0h0) \n connect _WIRE_10.ready, UInt<1>(0h0) \n wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_11.bits, _WIRE_10.bits \n connect _WIRE_11.valid, _WIRE_10.valid \n connect _WIRE_11.ready, _WIRE_10.ready \n node _T_615 = and(_WIRE_11.ready, _WIRE_11.valid) \n node _T_616 = and(_T_615, c_first) \n wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_12.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_12.bits.data, UInt<32>(0h0) \n connect _WIRE_12.bits.address, UInt<128>(0h0) \n connect _WIRE_12.bits.source, UInt<1>(0h0) \n connect _WIRE_12.bits.size, UInt<2>(0h0) \n connect _WIRE_12.bits.param, UInt<3>(0h0) \n connect _WIRE_12.bits.opcode, UInt<3>(0h0) \n connect _WIRE_12.valid, UInt<1>(0h0) \n connect _WIRE_12.ready, UInt<1>(0h0) \n wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_13.bits, _WIRE_12.bits \n connect _WIRE_13.valid, _WIRE_12.valid \n connect _WIRE_13.ready, _WIRE_12.ready \n node _T_617 = bits(_WIRE_13.bits.opcode, 2, 2) \n node _T_618 = bits(_WIRE_13.bits.opcode, 1, 1) \n node _T_619 = and(_T_617, _T_618) \n node _T_620 = and(_T_616, _T_619) \n when _T_620 : \n wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_set_WIRE.bits.data, UInt<32>(0h0) \n connect _c_set_WIRE.bits.address, UInt<128>(0h0) \n connect _c_set_WIRE.bits.source, UInt<1>(0h0) \n connect _c_set_WIRE.bits.size, UInt<2>(0h0) \n connect _c_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_set_WIRE.valid, UInt<1>(0h0) \n connect _c_set_WIRE.ready, UInt<1>(0h0) \n wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_set_WIRE_1.bits, _c_set_WIRE.bits \n connect _c_set_WIRE_1.valid, _c_set_WIRE.valid \n connect _c_set_WIRE_1.ready, _c_set_WIRE.ready \n node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) \n connect c_set, _c_set_T \n wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.address, UInt<128>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) \n connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) \n wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits \n connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid \n connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready \n node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) \n node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) \n connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 \n wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.address, UInt<128>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) \n connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) \n wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits \n connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid \n connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready \n node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) \n node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) \n connect c_sizes_set_interm, _c_sizes_set_interm_T_1 \n wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) \n connect _c_opcodes_set_WIRE.bits.address, UInt<128>(0h0) \n connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) \n connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) \n connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) \n connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) \n wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits \n connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid \n connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready \n node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) \n node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) \n connect c_opcodes_set, _c_opcodes_set_T_1 \n wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) \n connect _c_sizes_set_WIRE.bits.address, UInt<128>(0h0) \n connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) \n connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) \n connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) \n connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) \n wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits \n connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid \n connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready \n node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) \n node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) \n connect c_sizes_set, _c_sizes_set_T_1 \n wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_14.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_14.bits.data, UInt<32>(0h0) \n connect _WIRE_14.bits.address, UInt<128>(0h0) \n connect _WIRE_14.bits.source, UInt<1>(0h0) \n connect _WIRE_14.bits.size, UInt<2>(0h0) \n connect _WIRE_14.bits.param, UInt<3>(0h0) \n connect _WIRE_14.bits.opcode, UInt<3>(0h0) \n connect _WIRE_14.valid, UInt<1>(0h0) \n connect _WIRE_14.ready, UInt<1>(0h0) \n wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_15.bits, _WIRE_14.bits \n connect _WIRE_15.valid, _WIRE_14.valid \n connect _WIRE_15.ready, _WIRE_14.ready \n node _T_621 = dshr(inflight_1, _WIRE_15.bits.source) \n node _T_622 = bits(_T_621, 0, 0) \n node _T_623 = eq(_T_622, UInt<1>(0h0)) \n node _T_624 = asUInt(reset) \n node _T_625 = eq(_T_624, UInt<1>(0h0)) \n when _T_625 : \n node _T_626 = eq(_T_623, UInt<1>(0h0)) \n when _T_626 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_106 \n assert(clock, _T_623, UInt<1>(0h1), \"\") : assert_106 \n wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) \n connect _c_probe_ack_WIRE.bits.address, UInt<128>(0h0) \n connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) \n connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) \n connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) \n connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) \n connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) \n wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits \n connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid \n connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready \n node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) \n wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) \n connect _c_probe_ack_WIRE_2.bits.address, UInt<128>(0h0) \n connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) \n connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) \n connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) \n connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) \n wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits \n connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid \n connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready \n node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) \n node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) \n wire d_clr_1 : UInt<1> \n connect d_clr_1, UInt<1>(0h0) \n wire d_clr_wo_ready_1 : UInt<1> \n connect d_clr_wo_ready_1, UInt<1>(0h0) \n wire d_opcodes_clr_1 : UInt<4> \n connect d_opcodes_clr_1, UInt<4>(0h0) \n wire d_sizes_clr_1 : UInt<4> \n connect d_sizes_clr_1, UInt<4>(0h0) \n node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) \n node _T_627 = and(io.in.d.valid, d_first_2) \n node _T_628 = and(_T_627, UInt<1>(0h1)) \n node _T_629 = and(_T_628, d_release_ack_1) \n when _T_629 : \n node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 \n node _T_630 = and(io.in.d.ready, io.in.d.valid) \n node _T_631 = and(_T_630, d_first_2) \n node _T_632 = and(_T_631, UInt<1>(0h1)) \n node _T_633 = and(_T_632, d_release_ack_1) \n when _T_633 : \n node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) \n connect d_clr_1, _d_clr_T_1 \n node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) \n node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) \n node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) \n node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) \n connect d_opcodes_clr_1, _d_opcodes_clr_T_11 \n node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) \n node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) \n node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) \n node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) \n node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) \n node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) \n connect d_sizes_clr_1, _d_sizes_clr_T_11 \n node _T_634 = and(io.in.d.valid, d_first_2) \n node _T_635 = and(_T_634, UInt<1>(0h1)) \n node _T_636 = and(_T_635, d_release_ack_1) \n when _T_636 : \n wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) \n connect _same_cycle_resp_WIRE.bits.address, UInt<128>(0h0) \n connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) \n connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits \n connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid \n connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready \n node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) \n wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.address, UInt<128>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits \n connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid \n connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready \n node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) \n node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) \n node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) \n node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) \n wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.address, UInt<128>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) \n connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) \n connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) \n wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits \n connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid \n connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready \n node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) \n node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) \n node _T_637 = dshr(inflight_1, io.in.d.bits.source) \n node _T_638 = bits(_T_637, 0, 0) \n node _T_639 = or(_T_638, same_cycle_resp_1) \n node _T_640 = asUInt(reset) \n node _T_641 = eq(_T_640, UInt<1>(0h0)) \n when _T_641 : \n node _T_642 = eq(_T_639, UInt<1>(0h0)) \n when _T_642 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_107 \n assert(clock, _T_639, UInt<1>(0h1), \"\") : assert_107 \n when same_cycle_resp_1 : \n wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_16.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_16.bits.data, UInt<32>(0h0) \n connect _WIRE_16.bits.address, UInt<128>(0h0) \n connect _WIRE_16.bits.source, UInt<1>(0h0) \n connect _WIRE_16.bits.size, UInt<2>(0h0) \n connect _WIRE_16.bits.param, UInt<3>(0h0) \n connect _WIRE_16.bits.opcode, UInt<3>(0h0) \n connect _WIRE_16.valid, UInt<1>(0h0) \n connect _WIRE_16.ready, UInt<1>(0h0) \n wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_17.bits, _WIRE_16.bits \n connect _WIRE_17.valid, _WIRE_16.valid \n connect _WIRE_17.ready, _WIRE_16.ready \n node _T_643 = eq(io.in.d.bits.size, _WIRE_17.bits.size) \n node _T_644 = asUInt(reset) \n node _T_645 = eq(_T_644, UInt<1>(0h0)) \n when _T_645 : \n node _T_646 = eq(_T_643, UInt<1>(0h0)) \n when _T_646 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_108 \n assert(clock, _T_643, UInt<1>(0h1), \"\") : assert_108 \n else :\n\n node _T_647 = eq(io.in.d.bits.size, c_size_lookup) \n node _T_648 = asUInt(reset) \n node _T_649 = eq(_T_648, UInt<1>(0h0)) \n when _T_649 : \n node _T_650 = eq(_T_647, UInt<1>(0h0)) \n when _T_650 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_109 \n assert(clock, _T_647, UInt<1>(0h1), \"\") : assert_109 \n node _T_651 = and(io.in.d.valid, d_first_2) \n node _T_652 = and(_T_651, c_first) \n wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_18.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_18.bits.data, UInt<32>(0h0) \n connect _WIRE_18.bits.address, UInt<128>(0h0) \n connect _WIRE_18.bits.source, UInt<1>(0h0) \n connect _WIRE_18.bits.size, UInt<2>(0h0) \n connect _WIRE_18.bits.param, UInt<3>(0h0) \n connect _WIRE_18.bits.opcode, UInt<3>(0h0) \n connect _WIRE_18.valid, UInt<1>(0h0) \n connect _WIRE_18.ready, UInt<1>(0h0) \n wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_19.bits, _WIRE_18.bits \n connect _WIRE_19.valid, _WIRE_18.valid \n connect _WIRE_19.ready, _WIRE_18.ready \n node _T_653 = and(_T_652, _WIRE_19.valid) \n wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_20.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_20.bits.data, UInt<32>(0h0) \n connect _WIRE_20.bits.address, UInt<128>(0h0) \n connect _WIRE_20.bits.source, UInt<1>(0h0) \n connect _WIRE_20.bits.size, UInt<2>(0h0) \n connect _WIRE_20.bits.param, UInt<3>(0h0) \n connect _WIRE_20.bits.opcode, UInt<3>(0h0) \n connect _WIRE_20.valid, UInt<1>(0h0) \n connect _WIRE_20.ready, UInt<1>(0h0) \n wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_21.bits, _WIRE_20.bits \n connect _WIRE_21.valid, _WIRE_20.valid \n connect _WIRE_21.ready, _WIRE_20.ready \n node _T_654 = eq(_WIRE_21.bits.source, io.in.d.bits.source) \n node _T_655 = and(_T_653, _T_654) \n node _T_656 = and(_T_655, d_release_ack_1) \n node _T_657 = eq(c_probe_ack, UInt<1>(0h0)) \n node _T_658 = and(_T_656, _T_657) \n when _T_658 : \n node _T_659 = eq(io.in.d.ready, UInt<1>(0h0)) \n wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_22.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_22.bits.data, UInt<32>(0h0) \n connect _WIRE_22.bits.address, UInt<128>(0h0) \n connect _WIRE_22.bits.source, UInt<1>(0h0) \n connect _WIRE_22.bits.size, UInt<2>(0h0) \n connect _WIRE_22.bits.param, UInt<3>(0h0) \n connect _WIRE_22.bits.opcode, UInt<3>(0h0) \n connect _WIRE_22.valid, UInt<1>(0h0) \n connect _WIRE_22.ready, UInt<1>(0h0) \n wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_23.bits, _WIRE_22.bits \n connect _WIRE_23.valid, _WIRE_22.valid \n connect _WIRE_23.ready, _WIRE_22.ready \n node _T_660 = or(_T_659, _WIRE_23.ready) \n node _T_661 = asUInt(reset) \n node _T_662 = eq(_T_661, UInt<1>(0h0)) \n when _T_662 : \n node _T_663 = eq(_T_660, UInt<1>(0h0)) \n when _T_663 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: ready check\\n at Monitor.scala:52 assert(cond, message)\\n\") : printf_110 \n assert(clock, _T_660, UInt<1>(0h1), \"\") : assert_110 \n node _inflight_T_3 = or(inflight_1, c_set) \n node _inflight_T_4 = not(d_clr_1) \n node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) \n connect inflight_1, _inflight_T_5 \n node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) \n node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) \n node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) \n connect inflight_opcodes_1, _inflight_opcodes_T_5 \n node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) \n node _inflight_sizes_T_4 = not(d_sizes_clr_1) \n node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) \n connect inflight_sizes_1, _inflight_sizes_T_5 \n regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) \n inst plusarg_reader_1 of plusarg_reader_108 \n node _T_664 = orr(inflight_1) \n node _T_665 = eq(_T_664, UInt<1>(0h0)) \n node _T_666 = eq(plusarg_reader_1.out, UInt<1>(0h0)) \n node _T_667 = or(_T_665, _T_666) \n node _T_668 = lt(watchdog_1, plusarg_reader_1.out) \n node _T_669 = or(_T_667, _T_668) \n node _T_670 = asUInt(reset) \n node _T_671 = eq(_T_670, UInt<1>(0h0)) \n when _T_671 : \n node _T_672 = eq(_T_669, UInt<1>(0h0)) \n when _T_672 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\\n at Monitor.scala:45 assert(cond, message)\\n\") : printf_111 \n assert(clock, _T_669, UInt<1>(0h1), \"\") : assert_111 \n node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) \n node _watchdog_T_3 = tail(_watchdog_T_2, 1) \n connect watchdog_1, _watchdog_T_3 \n wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_24.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_24.bits.data, UInt<32>(0h0) \n connect _WIRE_24.bits.address, UInt<128>(0h0) \n connect _WIRE_24.bits.source, UInt<1>(0h0) \n connect _WIRE_24.bits.size, UInt<2>(0h0) \n connect _WIRE_24.bits.param, UInt<3>(0h0) \n connect _WIRE_24.bits.opcode, UInt<3>(0h0) \n connect _WIRE_24.valid, UInt<1>(0h0) \n connect _WIRE_24.ready, UInt<1>(0h0) \n wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} \n connect _WIRE_25.bits, _WIRE_24.bits \n connect _WIRE_25.valid, _WIRE_24.valid \n connect _WIRE_25.ready, _WIRE_24.ready \n node _T_673 = and(_WIRE_25.ready, _WIRE_25.valid) \n node _T_674 = and(io.in.d.ready, io.in.d.valid) \n node _T_675 = or(_T_673, _T_674) \n when _T_675 : \n connect watchdog_1, UInt<1>(0h0)"},"response":{"kind":"string","value":"module TLMonitor_53(\t// @[Monitor.scala:36:7]\n input clock,\t// @[Monitor.scala:36:7]\n input reset,\t// @[Monitor.scala:36:7]\n input io_in_a_ready,\t// @[Monitor.scala:20:14]\n input io_in_a_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_a_bits_opcode,\t// @[Monitor.scala:20:14]\n input [127:0] io_in_a_bits_address,\t// @[Monitor.scala:20:14]\n input [31:0] io_in_a_bits_data,\t// @[Monitor.scala:20:14]\n input io_in_d_ready,\t// @[Monitor.scala:20:14]\n input io_in_d_valid,\t// @[Monitor.scala:20:14]\n input [2:0] io_in_d_bits_opcode,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_d_bits_param,\t// @[Monitor.scala:20:14]\n input [1:0] io_in_d_bits_size,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_denied,\t// @[Monitor.scala:20:14]\n input io_in_d_bits_corrupt\t// @[Monitor.scala:20:14]\n);\n\n wire [31:0] _plusarg_reader_1_out;\t// @[PlusArg.scala:80:11]\n wire [31:0] _plusarg_reader_out;\t// @[PlusArg.scala:80:11]\n wire io_in_a_ready_0 = io_in_a_ready;\t// @[Monitor.scala:36:7]\n wire io_in_a_valid_0 = io_in_a_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [127:0] io_in_a_bits_address_0 = io_in_a_bits_address;\t// @[Monitor.scala:36:7]\n wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data;\t// @[Monitor.scala:36:7]\n wire io_in_d_ready_0 = io_in_d_ready;\t// @[Monitor.scala:36:7]\n wire io_in_d_valid_0 = io_in_d_valid;\t// @[Monitor.scala:36:7]\n wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode;\t// @[Monitor.scala:36:7]\n wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param;\t// @[Monitor.scala:36:7]\n wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_denied_0 = io_in_d_bits_denied;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt;\t// @[Monitor.scala:36:7]\n wire io_in_a_bits_source = 1'h0;\t// @[Monitor.scala:36:7]\n wire io_in_a_bits_corrupt = 1'h0;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_source = 1'h0;\t// @[Monitor.scala:36:7]\n wire io_in_d_bits_sink = 1'h0;\t// @[Monitor.scala:36:7]\n wire mask_sizeOH_shiftAmount = 1'h0;\t// @[OneHot.scala:64:49]\n wire mask_sub_size = 1'h0;\t// @[Misc.scala:209:26]\n wire _mask_sub_acc_T = 1'h0;\t// @[Misc.scala:215:38]\n wire _mask_sub_acc_T_1 = 1'h0;\t// @[Misc.scala:215:38]\n wire a_first_beats1_decode = 1'h0;\t// @[Edges.scala:220:59]\n wire a_first_beats1 = 1'h0;\t// @[Edges.scala:221:14]\n wire a_first_count = 1'h0;\t// @[Edges.scala:234:25]\n wire d_first_beats1_decode = 1'h0;\t// @[Edges.scala:220:59]\n wire d_first_beats1 = 1'h0;\t// @[Edges.scala:221:14]\n wire d_first_count = 1'h0;\t// @[Edges.scala:234:25]\n wire a_first_beats1_decode_1 = 1'h0;\t// @[Edges.scala:220:59]\n wire a_first_beats1_1 = 1'h0;\t// @[Edges.scala:221:14]\n wire a_first_count_1 = 1'h0;\t// @[Edges.scala:234:25]\n wire d_first_beats1_decode_1 = 1'h0;\t// @[Edges.scala:220:59]\n wire d_first_beats1_1 = 1'h0;\t// @[Edges.scala:221:14]\n wire d_first_count_1 = 1'h0;\t// @[Edges.scala:234:25]\n wire _c_first_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_first_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_first_T = 1'h0;\t// @[Decoupled.scala:51:35]\n wire c_first_beats1_decode = 1'h0;\t// @[Edges.scala:220:59]\n wire c_first_beats1_opdata = 1'h0;\t// @[Edges.scala:102:36]\n wire c_first_beats1 = 1'h0;\t// @[Edges.scala:221:14]\n wire _c_first_last_T = 1'h0;\t// @[Edges.scala:232:25]\n wire c_first_done = 1'h0;\t// @[Edges.scala:233:22]\n wire _c_first_count_T = 1'h0;\t// @[Edges.scala:234:27]\n wire c_first_count = 1'h0;\t// @[Edges.scala:234:25]\n wire _c_first_counter_T = 1'h0;\t// @[Edges.scala:236:21]\n wire d_first_beats1_decode_2 = 1'h0;\t// @[Edges.scala:220:59]\n wire d_first_beats1_2 = 1'h0;\t// @[Edges.scala:221:14]\n wire d_first_count_2 = 1'h0;\t// @[Edges.scala:234:25]\n wire c_set = 1'h0;\t// @[Monitor.scala:738:34]\n wire c_set_wo_ready = 1'h0;\t// @[Monitor.scala:739:34]\n wire _c_set_wo_ready_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_wo_ready_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_interm_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_opcodes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_sizes_set_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T = 1'h0;\t// @[Monitor.scala:772:47]\n wire _c_probe_ack_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _c_probe_ack_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _c_probe_ack_T_1 = 1'h0;\t// @[Monitor.scala:772:95]\n wire c_probe_ack = 1'h0;\t// @[Monitor.scala:772:71]\n wire _same_cycle_resp_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_3 = 1'h0;\t// @[Monitor.scala:795:44]\n wire _same_cycle_resp_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_T_4 = 1'h0;\t// @[Edges.scala:68:36]\n wire _same_cycle_resp_T_5 = 1'h0;\t// @[Edges.scala:68:51]\n wire _same_cycle_resp_T_6 = 1'h0;\t// @[Edges.scala:68:40]\n wire _same_cycle_resp_T_7 = 1'h0;\t// @[Monitor.scala:795:55]\n wire _same_cycle_resp_WIRE_4_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_bits_source = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _same_cycle_resp_WIRE_5_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_bits_source = 1'h0;\t// @[Bundles.scala:265:61]\n wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire same_cycle_resp_1 = 1'h0;\t// @[Monitor.scala:795:88]\n wire _source_ok_T = 1'h1;\t// @[Parameters.scala:46:9]\n wire _source_ok_WIRE_0 = 1'h1;\t// @[Parameters.scala:1138:31]\n wire mask_sub_sub_0_1 = 1'h1;\t// @[Misc.scala:206:21]\n wire mask_sub_0_1 = 1'h1;\t// @[Misc.scala:215:29]\n wire mask_sub_1_1 = 1'h1;\t// @[Misc.scala:215:29]\n wire mask_size = 1'h1;\t// @[Misc.scala:209:26]\n wire mask_acc = 1'h1;\t// @[Misc.scala:215:29]\n wire mask_acc_1 = 1'h1;\t// @[Misc.scala:215:29]\n wire mask_acc_2 = 1'h1;\t// @[Misc.scala:215:29]\n wire mask_acc_3 = 1'h1;\t// @[Misc.scala:215:29]\n wire _source_ok_T_1 = 1'h1;\t// @[Parameters.scala:46:9]\n wire _source_ok_WIRE_1_0 = 1'h1;\t// @[Parameters.scala:1138:31]\n wire sink_ok = 1'h1;\t// @[Monitor.scala:309:31]\n wire _a_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire a_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire _d_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire d_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire _a_first_last_T_3 = 1'h1;\t// @[Edges.scala:232:43]\n wire a_first_last_1 = 1'h1;\t// @[Edges.scala:232:33]\n wire _d_first_last_T_3 = 1'h1;\t// @[Edges.scala:232:43]\n wire d_first_last_1 = 1'h1;\t// @[Edges.scala:232:33]\n wire _same_cycle_resp_T_2 = 1'h1;\t// @[Monitor.scala:684:113]\n wire c_first_counter1 = 1'h1;\t// @[Edges.scala:230:28]\n wire c_first = 1'h1;\t// @[Edges.scala:231:25]\n wire _c_first_last_T_1 = 1'h1;\t// @[Edges.scala:232:43]\n wire c_first_last = 1'h1;\t// @[Edges.scala:232:33]\n wire _d_first_last_T_5 = 1'h1;\t// @[Edges.scala:232:43]\n wire d_first_last_2 = 1'h1;\t// @[Edges.scala:232:33]\n wire _same_cycle_resp_T_8 = 1'h1;\t// @[Monitor.scala:795:113]\n wire [1:0] is_aligned_mask = 2'h3;\t// @[package.scala:243:46]\n wire [1:0] mask_lo = 2'h3;\t// @[Misc.scala:222:10]\n wire [1:0] mask_hi = 2'h3;\t// @[Misc.scala:222:10]\n wire [1:0] _a_first_beats1_decode_T_2 = 2'h3;\t// @[package.scala:243:46]\n wire [1:0] _a_first_beats1_decode_T_5 = 2'h3;\t// @[package.scala:243:46]\n wire [1:0] _c_first_beats1_decode_T_1 = 2'h3;\t// @[package.scala:243:76]\n wire [1:0] _c_first_counter1_T = 2'h3;\t// @[Edges.scala:230:28]\n wire [1:0] io_in_a_bits_size = 2'h2;\t// @[Monitor.scala:36:7]\n wire [1:0] _mask_sizeOH_T = 2'h2;\t// @[Misc.scala:202:34]\n wire [2:0] io_in_a_bits_param = 3'h0;\t// @[Monitor.scala:36:7]\n wire [2:0] responseMap_0 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_1 = 3'h0;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_0 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_1 = 3'h0;\t// @[Monitor.scala:644:42]\n wire [2:0] _c_first_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_first_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] c_sizes_set_interm = 3'h0;\t// @[Monitor.scala:755:40]\n wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_interm_T = 3'h0;\t// @[Monitor.scala:766:51]\n wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] io_in_a_bits_mask = 4'hF;\t// @[Monitor.scala:36:7]\n wire [3:0] mask = 4'hF;\t// @[Misc.scala:222:10]\n wire [31:0] io_in_d_bits_data = 32'h0;\t// @[Monitor.scala:36:7]\n wire [31:0] _c_first_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_first_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_first_WIRE_2_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_first_WIRE_3_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_set_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_set_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0;\t// @[Bundles.scala:265:61]\n wire [127:0] _c_first_WIRE_bits_address = 128'h0;\t// @[Bundles.scala:265:74]\n wire [127:0] _c_first_WIRE_1_bits_address = 128'h0;\t// @[Bundles.scala:265:61]\n wire [127:0] _c_first_WIRE_2_bits_address = 128'h0;\t// @[Bundles.scala:265:74]\n wire [127:0] _c_first_WIRE_3_bits_address = 128'h0;\t// @[Bundles.scala:265:61]\n wire [127:0] _c_set_wo_ready_WIRE_bits_address = 128'h0;\t// @[Bundles.scala:265:74]\n wire [127:0] _c_set_wo_ready_WIRE_1_bits_address = 128'h0;\t// @[Bundles.scala:265:61]\n wire [127:0] _c_set_WIRE_bits_address = 128'h0;\t// @[Bundles.scala:265:74]\n wire [127:0] _c_set_WIRE_1_bits_address = 128'h0;\t// @[Bundles.scala:265:61]\n wire [127:0] _c_opcodes_set_interm_WIRE_bits_address = 128'h0;\t// @[Bundles.scala:265:74]\n wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_address = 128'h0;\t// @[Bundles.scala:265:61]\n wire [127:0] _c_sizes_set_interm_WIRE_bits_address = 128'h0;\t// @[Bundles.scala:265:74]\n wire [127:0] _c_sizes_set_interm_WIRE_1_bits_address = 128'h0;\t// @[Bundles.scala:265:61]\n wire [127:0] _c_opcodes_set_WIRE_bits_address = 128'h0;\t// @[Bundles.scala:265:74]\n wire [127:0] _c_opcodes_set_WIRE_1_bits_address = 128'h0;\t// @[Bundles.scala:265:61]\n wire [127:0] _c_sizes_set_WIRE_bits_address = 128'h0;\t// @[Bundles.scala:265:74]\n wire [127:0] _c_sizes_set_WIRE_1_bits_address = 128'h0;\t// @[Bundles.scala:265:61]\n wire [127:0] _c_probe_ack_WIRE_bits_address = 128'h0;\t// @[Bundles.scala:265:74]\n wire [127:0] _c_probe_ack_WIRE_1_bits_address = 128'h0;\t// @[Bundles.scala:265:61]\n wire [127:0] _c_probe_ack_WIRE_2_bits_address = 128'h0;\t// @[Bundles.scala:265:74]\n wire [127:0] _c_probe_ack_WIRE_3_bits_address = 128'h0;\t// @[Bundles.scala:265:61]\n wire [127:0] _same_cycle_resp_WIRE_bits_address = 128'h0;\t// @[Bundles.scala:265:74]\n wire [127:0] _same_cycle_resp_WIRE_1_bits_address = 128'h0;\t// @[Bundles.scala:265:61]\n wire [127:0] _same_cycle_resp_WIRE_2_bits_address = 128'h0;\t// @[Bundles.scala:265:74]\n wire [127:0] _same_cycle_resp_WIRE_3_bits_address = 128'h0;\t// @[Bundles.scala:265:61]\n wire [127:0] _same_cycle_resp_WIRE_4_bits_address = 128'h0;\t// @[Bundles.scala:265:74]\n wire [127:0] _same_cycle_resp_WIRE_5_bits_address = 128'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _is_aligned_mask_T_1 = 2'h0;\t// @[package.scala:243:76]\n wire [1:0] _a_first_beats1_decode_T_1 = 2'h0;\t// @[package.scala:243:76]\n wire [1:0] _a_first_beats1_decode_T_4 = 2'h0;\t// @[package.scala:243:76]\n wire [1:0] _c_first_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_first_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_first_WIRE_2_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_first_WIRE_3_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_first_beats1_decode_T_2 = 2'h0;\t// @[package.scala:243:46]\n wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_set_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_set_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0;\t// @[Bundles.scala:265:74]\n wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0;\t// @[Bundles.scala:265:61]\n wire [30:0] _d_opcodes_clr_T_5 = 31'hF;\t// @[Monitor.scala:680:76]\n wire [30:0] _d_sizes_clr_T_5 = 31'hF;\t// @[Monitor.scala:681:74]\n wire [30:0] _d_opcodes_clr_T_11 = 31'hF;\t// @[Monitor.scala:790:76]\n wire [30:0] _d_sizes_clr_T_11 = 31'hF;\t// @[Monitor.scala:791:74]\n wire [3:0] _a_opcode_lookup_T = 4'h0;\t// @[Monitor.scala:637:69]\n wire [3:0] _a_size_lookup_T = 4'h0;\t// @[Monitor.scala:641:65]\n wire [3:0] _a_opcodes_set_T = 4'h0;\t// @[Monitor.scala:659:79]\n wire [3:0] _a_sizes_set_T = 4'h0;\t// @[Monitor.scala:660:77]\n wire [3:0] _d_opcodes_clr_T_4 = 4'h0;\t// @[Monitor.scala:680:101]\n wire [3:0] _d_sizes_clr_T_4 = 4'h0;\t// @[Monitor.scala:681:99]\n wire [3:0] c_opcodes_set = 4'h0;\t// @[Monitor.scala:740:34]\n wire [3:0] c_sizes_set = 4'h0;\t// @[Monitor.scala:741:34]\n wire [3:0] _c_opcode_lookup_T = 4'h0;\t// @[Monitor.scala:749:69]\n wire [3:0] _c_size_lookup_T = 4'h0;\t// @[Monitor.scala:750:67]\n wire [3:0] c_opcodes_set_interm = 4'h0;\t// @[Monitor.scala:754:40]\n wire [3:0] _c_opcodes_set_interm_T = 4'h0;\t// @[Monitor.scala:765:53]\n wire [3:0] _c_opcodes_set_T = 4'h0;\t// @[Monitor.scala:767:79]\n wire [3:0] _c_sizes_set_T = 4'h0;\t// @[Monitor.scala:768:77]\n wire [3:0] _d_opcodes_clr_T_10 = 4'h0;\t// @[Monitor.scala:790:101]\n wire [3:0] _d_sizes_clr_T_10 = 4'h0;\t// @[Monitor.scala:791:99]\n wire [15:0] _a_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _a_size_lookup_T_5 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_opcodes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _d_sizes_clr_T_3 = 16'hF;\t// @[Monitor.scala:612:57]\n wire [15:0] _c_opcode_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _c_size_lookup_T_5 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_opcodes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _d_sizes_clr_T_9 = 16'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _a_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _a_size_lookup_T_4 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_opcodes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _d_sizes_clr_T_2 = 17'hF;\t// @[Monitor.scala:612:57]\n wire [16:0] _c_opcode_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _c_size_lookup_T_4 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_opcodes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [16:0] _d_sizes_clr_T_8 = 17'hF;\t// @[Monitor.scala:724:57]\n wire [15:0] _a_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _a_size_lookup_T_3 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_opcodes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _d_sizes_clr_T_1 = 16'h10;\t// @[Monitor.scala:612:51]\n wire [15:0] _c_opcode_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _c_size_lookup_T_3 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_opcodes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [15:0] _d_sizes_clr_T_7 = 16'h10;\t// @[Monitor.scala:724:51]\n wire [1:0] _mask_sizeOH_T_1 = 2'h1;\t// @[OneHot.scala:65:12]\n wire [1:0] _mask_sizeOH_T_2 = 2'h1;\t// @[OneHot.scala:65:27]\n wire [1:0] mask_sizeOH = 2'h1;\t// @[Misc.scala:202:81]\n wire [1:0] _a_set_wo_ready_T = 2'h1;\t// @[OneHot.scala:58:35]\n wire [1:0] _a_set_T = 2'h1;\t// @[OneHot.scala:58:35]\n wire [1:0] _d_clr_wo_ready_T = 2'h1;\t// @[OneHot.scala:58:35]\n wire [1:0] _d_clr_T = 2'h1;\t// @[OneHot.scala:58:35]\n wire [1:0] _c_set_wo_ready_T = 2'h1;\t// @[OneHot.scala:58:35]\n wire [1:0] _c_set_T = 2'h1;\t// @[OneHot.scala:58:35]\n wire [1:0] _d_clr_wo_ready_T_1 = 2'h1;\t// @[OneHot.scala:58:35]\n wire [1:0] _d_clr_T_1 = 2'h1;\t// @[OneHot.scala:58:35]\n wire [17:0] _c_sizes_set_T_1 = 18'h0;\t// @[Monitor.scala:768:52]\n wire [18:0] _c_opcodes_set_T_1 = 19'h0;\t// @[Monitor.scala:767:54]\n wire [2:0] responseMap_2 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_3 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_4 = 3'h1;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_2 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_3 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] responseMapSecondOption_4 = 3'h1;\t// @[Monitor.scala:644:42]\n wire [2:0] _c_sizes_set_interm_T_1 = 3'h1;\t// @[Monitor.scala:766:59]\n wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1;\t// @[Monitor.scala:765:61]\n wire [4:0] _c_first_beats1_decode_T = 5'h3;\t// @[package.scala:243:71]\n wire [2:0] responseMapSecondOption_6 = 3'h5;\t// @[Monitor.scala:644:42]\n wire [2:0] _a_sizes_set_interm_T_1 = 3'h5;\t// @[Monitor.scala:658:59]\n wire [2:0] responseMap_6 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMap_7 = 3'h4;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_7 = 3'h4;\t// @[Monitor.scala:644:42]\n wire [2:0] _a_sizes_set_interm_T = 3'h4;\t// @[Monitor.scala:658:51]\n wire [2:0] responseMap_5 = 3'h2;\t// @[Monitor.scala:643:42]\n wire [2:0] responseMapSecondOption_5 = 3'h2;\t// @[Monitor.scala:644:42]\n wire [4:0] _is_aligned_mask_T = 5'hC;\t// @[package.scala:243:71]\n wire [4:0] _a_first_beats1_decode_T = 5'hC;\t// @[package.scala:243:71]\n wire [4:0] _a_first_beats1_decode_T_3 = 5'hC;\t// @[package.scala:243:71]\n wire [3:0] _a_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:637:123]\n wire [3:0] _a_size_lookup_T_2 = 4'h4;\t// @[Monitor.scala:641:117]\n wire [3:0] _d_opcodes_clr_T = 4'h4;\t// @[Monitor.scala:680:48]\n wire [3:0] _d_sizes_clr_T = 4'h4;\t// @[Monitor.scala:681:48]\n wire [3:0] _c_opcode_lookup_T_2 = 4'h4;\t// @[Monitor.scala:749:123]\n wire [3:0] _c_size_lookup_T_2 = 4'h4;\t// @[Monitor.scala:750:119]\n wire [3:0] _d_opcodes_clr_T_6 = 4'h4;\t// @[Monitor.scala:790:48]\n wire [3:0] _d_sizes_clr_T_6 = 4'h4;\t// @[Monitor.scala:791:48]\n wire [127:0] _is_aligned_T = {126'h0, io_in_a_bits_address_0[1:0]};\t// @[Monitor.scala:36:7]\n wire is_aligned = _is_aligned_T == 128'h0;\t// @[Edges.scala:21:{16,24}]\n wire mask_sub_bit = io_in_a_bits_address_0[1];\t// @[Misc.scala:210:26]\n wire mask_sub_1_2 = mask_sub_bit;\t// @[Misc.scala:210:26, :214:27]\n wire mask_sub_nbit = ~mask_sub_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_sub_0_2 = mask_sub_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire mask_bit = io_in_a_bits_address_0[0];\t// @[Misc.scala:210:26]\n wire mask_nbit = ~mask_bit;\t// @[Misc.scala:210:26, :211:20]\n wire mask_eq = mask_sub_0_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T = mask_eq;\t// @[Misc.scala:214:27, :215:38]\n wire mask_eq_1 = mask_sub_0_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_1 = mask_eq_1;\t// @[Misc.scala:214:27, :215:38]\n wire mask_eq_2 = mask_sub_1_2 & mask_nbit;\t// @[Misc.scala:211:20, :214:27]\n wire _mask_acc_T_2 = mask_eq_2;\t// @[Misc.scala:214:27, :215:38]\n wire mask_eq_3 = mask_sub_1_2 & mask_bit;\t// @[Misc.scala:210:26, :214:27]\n wire _mask_acc_T_3 = mask_eq_3;\t// @[Misc.scala:214:27, :215:38]\n wire _T_607 = io_in_a_ready_0 & io_in_a_valid_0;\t// @[Decoupled.scala:51:35]\n wire _a_first_T;\t// @[Decoupled.scala:51:35]\n assign _a_first_T = _T_607;\t// @[Decoupled.scala:51:35]\n wire _a_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _a_first_T_1 = _T_607;\t// @[Decoupled.scala:51:35]\n wire a_first_done = _a_first_T;\t// @[Decoupled.scala:51:35]\n wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2];\t// @[Monitor.scala:36:7]\n wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T;\t// @[Edges.scala:92:{28,37}]\n reg a_first_counter;\t// @[Edges.scala:229:27]\n wire _a_first_last_T = a_first_counter;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire a_first_counter1 = _a_first_counter1_T[0];\t// @[Edges.scala:230:28]\n wire a_first = ~a_first_counter;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_count_T = ~a_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire _a_first_counter_T = ~a_first & a_first_counter1;\t// @[Edges.scala:230:28, :231:25, :236:21]\n reg [2:0] opcode;\t// @[Monitor.scala:387:22]\n reg [127:0] address;\t// @[Monitor.scala:391:22]\n wire _T_675 = io_in_d_ready_0 & io_in_d_valid_0;\t// @[Decoupled.scala:51:35]\n wire _d_first_T;\t// @[Decoupled.scala:51:35]\n assign _d_first_T = _T_675;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_1;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_1 = _T_675;\t// @[Decoupled.scala:51:35]\n wire _d_first_T_2;\t// @[Decoupled.scala:51:35]\n assign _d_first_T_2 = _T_675;\t// @[Decoupled.scala:51:35]\n wire d_first_done = _d_first_T;\t// @[Decoupled.scala:51:35]\n wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0;\t// @[package.scala:243:71]\n wire [4:0] _d_first_beats1_decode_T;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T = _GEN;\t// @[package.scala:243:71]\n wire [4:0] _d_first_beats1_decode_T_3;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_3 = _GEN;\t// @[package.scala:243:71]\n wire [4:0] _d_first_beats1_decode_T_6;\t// @[package.scala:243:71]\n assign _d_first_beats1_decode_T_6 = _GEN;\t// @[package.scala:243:71]\n wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0];\t// @[package.scala:243:{71,76}]\n wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0];\t// @[Monitor.scala:36:7]\n reg d_first_counter;\t// @[Edges.scala:229:27]\n wire _d_first_last_T = d_first_counter;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire d_first_counter1 = _d_first_counter1_T[0];\t// @[Edges.scala:230:28]\n wire d_first = ~d_first_counter;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_count_T = ~d_first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire _d_first_counter_T = ~d_first & d_first_counter1;\t// @[Edges.scala:230:28, :231:25, :236:21]\n reg [2:0] opcode_1;\t// @[Monitor.scala:538:22]\n reg [1:0] param_1;\t// @[Monitor.scala:539:22]\n reg [1:0] size_1;\t// @[Monitor.scala:540:22]\n reg denied;\t// @[Monitor.scala:543:22]\n reg [1:0] inflight;\t// @[Monitor.scala:614:27]\n reg [3:0] inflight_opcodes;\t// @[Monitor.scala:616:35]\n wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes;\t// @[Monitor.scala:616:35, :637:44]\n reg [3:0] inflight_sizes;\t// @[Monitor.scala:618:33]\n wire [3:0] _a_size_lookup_T_1 = inflight_sizes;\t// @[Monitor.scala:618:33, :641:40]\n wire a_first_done_1 = _a_first_T_1;\t// @[Decoupled.scala:51:35]\n wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1;\t// @[Edges.scala:92:{28,37}]\n reg a_first_counter_1;\t// @[Edges.scala:229:27]\n wire _a_first_last_T_2 = a_first_counter_1;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire a_first_counter1_1 = _a_first_counter1_T_1[0];\t// @[Edges.scala:230:28]\n wire a_first_1 = ~a_first_counter_1;\t// @[Edges.scala:229:27, :231:25]\n wire _a_first_count_T_1 = ~a_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1;\t// @[Edges.scala:230:28, :231:25, :236:21]\n wire d_first_done_1 = _d_first_T_1;\t// @[Decoupled.scala:51:35]\n wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0];\t// @[package.scala:243:{71,76}]\n wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4;\t// @[package.scala:243:{46,76}]\n reg d_first_counter_1;\t// @[Edges.scala:229:27]\n wire _d_first_last_T_2 = d_first_counter_1;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire d_first_counter1_1 = _d_first_counter1_T_1[0];\t// @[Edges.scala:230:28]\n wire d_first_1 = ~d_first_counter_1;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_count_T_1 = ~d_first_counter1_1;\t// @[Edges.scala:230:28, :234:27]\n wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1;\t// @[Edges.scala:230:28, :231:25, :236:21]\n wire a_set;\t// @[Monitor.scala:626:34]\n wire a_set_wo_ready;\t// @[Monitor.scala:627:34]\n wire [3:0] a_opcodes_set;\t// @[Monitor.scala:630:33]\n wire [3:0] a_sizes_set;\t// @[Monitor.scala:632:31]\n wire [2:0] a_opcode_lookup;\t// @[Monitor.scala:635:35]\n wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1};\t// @[Monitor.scala:637:{44,97}]\n wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]};\t// @[Monitor.scala:637:{97,152}]\n assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0];\t// @[Monitor.scala:635:35, :637:{21,152}]\n wire [3:0] a_size_lookup;\t// @[Monitor.scala:639:33]\n wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1};\t// @[Monitor.scala:637:97, :641:{40,91}]\n wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]};\t// @[Monitor.scala:641:{91,144}]\n assign a_size_lookup = _a_size_lookup_T_7[3:0];\t// @[Monitor.scala:639:33, :641:{19,144}]\n wire [3:0] a_opcodes_set_interm;\t// @[Monitor.scala:646:40]\n wire [2:0] a_sizes_set_interm;\t// @[Monitor.scala:648:38]\n wire _T_537 = io_in_a_valid_0 & a_first_1;\t// @[Monitor.scala:36:7, :651:26]\n assign a_set_wo_ready = _T_537;\t// @[Monitor.scala:627:34, :651:26]\n wire _same_cycle_resp_T;\t// @[Monitor.scala:684:44]\n assign _same_cycle_resp_T = _T_537;\t// @[Monitor.scala:651:26, :684:44]\n assign a_set = _T_607 & a_first_1;\t// @[Decoupled.scala:51:35]\n wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0};\t// @[Monitor.scala:36:7, :657:53]\n wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1};\t// @[Monitor.scala:657:{53,61}]\n assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0;\t// @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}]\n assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0;\t// @[Monitor.scala:626:34, :648:38, :655:70, :658:28]\n wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm};\t// @[Monitor.scala:646:40, :659:54]\n assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0;\t// @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}]\n wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm};\t// @[Monitor.scala:648:38, :659:54, :660:52]\n assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0;\t// @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}]\n wire d_clr;\t// @[Monitor.scala:664:34]\n wire d_clr_wo_ready;\t// @[Monitor.scala:665:34]\n wire [3:0] d_opcodes_clr;\t// @[Monitor.scala:668:33]\n wire [3:0] d_sizes_clr;\t// @[Monitor.scala:670:31]\n wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6;\t// @[Monitor.scala:36:7, :673:46]\n wire d_release_ack;\t// @[Monitor.scala:673:46]\n assign d_release_ack = _GEN_0;\t// @[Monitor.scala:673:46]\n wire d_release_ack_1;\t// @[Monitor.scala:783:46]\n assign d_release_ack_1 = _GEN_0;\t// @[Monitor.scala:673:46, :783:46]\n wire _T_586 = io_in_d_valid_0 & d_first_1;\t// @[Monitor.scala:36:7, :674:26]\n assign d_clr_wo_ready = _T_586 & ~d_release_ack;\t// @[Monitor.scala:665:34, :673:46, :674:{26,71,74}]\n assign d_clr = _T_675 & d_first_1 & ~d_release_ack;\t// @[Decoupled.scala:51:35]\n wire [3:0] _GEN_1 = {4{d_clr}};\t// @[Monitor.scala:664:34, :668:33, :678:89, :680:21]\n assign d_opcodes_clr = _GEN_1;\t// @[Monitor.scala:668:33, :678:89, :680:21]\n assign d_sizes_clr = _GEN_1;\t// @[Monitor.scala:668:33, :670:31, :678:89, :680:21]\n wire _same_cycle_resp_T_1 = _same_cycle_resp_T;\t// @[Monitor.scala:684:{44,55}]\n wire same_cycle_resp = _same_cycle_resp_T_1;\t// @[Monitor.scala:684:{55,88}]\n wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set};\t// @[Monitor.scala:614:27, :626:34, :705:27]\n wire _inflight_T_1 = ~d_clr;\t// @[Monitor.scala:664:34, :705:38]\n wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1};\t// @[Monitor.scala:705:{27,36,38}]\n wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set;\t// @[Monitor.scala:616:35, :630:33, :706:43]\n wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr;\t// @[Monitor.scala:668:33, :706:62]\n wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1;\t// @[Monitor.scala:706:{43,60,62}]\n wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set;\t// @[Monitor.scala:618:33, :632:31, :707:39]\n wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr;\t// @[Monitor.scala:670:31, :707:56]\n wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1;\t// @[Monitor.scala:707:{39,54,56}]\n reg [31:0] watchdog;\t// @[Monitor.scala:709:27]\n wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1;\t// @[Monitor.scala:709:27, :714:26]\n wire [31:0] _watchdog_T_1 = _watchdog_T[31:0];\t// @[Monitor.scala:714:26]\n reg [1:0] inflight_1;\t// @[Monitor.scala:726:35]\n wire [1:0] _inflight_T_3 = inflight_1;\t// @[Monitor.scala:726:35, :814:35]\n reg [3:0] inflight_opcodes_1;\t// @[Monitor.scala:727:35]\n wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1;\t// @[Monitor.scala:727:35, :749:44]\n wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1;\t// @[Monitor.scala:727:35, :815:43]\n reg [3:0] inflight_sizes_1;\t// @[Monitor.scala:728:35]\n wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1;\t// @[Monitor.scala:728:35, :750:42]\n wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1;\t// @[Monitor.scala:728:35, :816:41]\n wire d_first_done_2 = _d_first_T_2;\t// @[Decoupled.scala:51:35]\n wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0];\t// @[package.scala:243:{71,76}]\n wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7;\t// @[package.scala:243:{46,76}]\n reg d_first_counter_2;\t// @[Edges.scala:229:27]\n wire _d_first_last_T_4 = d_first_counter_2;\t// @[Edges.scala:229:27, :232:25]\n wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1;\t// @[Edges.scala:229:27, :230:28]\n wire d_first_counter1_2 = _d_first_counter1_T_2[0];\t// @[Edges.scala:230:28]\n wire d_first_2 = ~d_first_counter_2;\t// @[Edges.scala:229:27, :231:25]\n wire _d_first_count_T_2 = ~d_first_counter1_2;\t// @[Edges.scala:230:28, :234:27]\n wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2;\t// @[Edges.scala:230:28, :231:25, :236:21]\n wire [3:0] c_opcode_lookup;\t// @[Monitor.scala:747:35]\n wire [3:0] c_size_lookup;\t// @[Monitor.scala:748:35]\n wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1};\t// @[Monitor.scala:637:97, :749:{44,97}]\n wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]};\t// @[Monitor.scala:749:{97,152}]\n assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0];\t// @[Monitor.scala:747:35, :749:{21,152}]\n wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1};\t// @[Monitor.scala:637:97, :750:{42,93}]\n wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]};\t// @[Monitor.scala:750:{93,146}]\n assign c_size_lookup = _c_size_lookup_T_7[3:0];\t// @[Monitor.scala:748:35, :750:{21,146}]\n wire d_clr_1;\t// @[Monitor.scala:774:34]\n wire d_clr_wo_ready_1;\t// @[Monitor.scala:775:34]\n wire [3:0] d_opcodes_clr_1;\t// @[Monitor.scala:776:34]\n wire [3:0] d_sizes_clr_1;\t// @[Monitor.scala:777:34]\n wire _T_651 = io_in_d_valid_0 & d_first_2;\t// @[Monitor.scala:36:7, :784:26]\n assign d_clr_wo_ready_1 = _T_651 & d_release_ack_1;\t// @[Monitor.scala:775:34, :783:46, :784:{26,71}]\n assign d_clr_1 = _T_675 & d_first_2 & d_release_ack_1;\t// @[Decoupled.scala:51:35]\n wire [3:0] _GEN_2 = {4{d_clr_1}};\t// @[Monitor.scala:774:34, :776:34, :788:88, :790:21]\n assign d_opcodes_clr_1 = _GEN_2;\t// @[Monitor.scala:776:34, :788:88, :790:21]\n assign d_sizes_clr_1 = _GEN_2;\t// @[Monitor.scala:776:34, :777:34, :788:88, :790:21]\n wire _inflight_T_4 = ~d_clr_1;\t// @[Monitor.scala:774:34, :814:46]\n wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4};\t// @[Monitor.scala:814:{35,44,46}]\n wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1;\t// @[Monitor.scala:776:34, :815:62]\n wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4;\t// @[Monitor.scala:815:{43,60,62}]\n wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1;\t// @[Monitor.scala:777:34, :816:58]\n wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4;\t// @[Monitor.scala:816:{41,56,58}]\n reg [31:0] watchdog_1;\t// @[Monitor.scala:818:27]"}}},{"rowIdx":34191,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module ALUExeUnit_2 : \n input clock : Clock \n input reset : Reset \n output io : { fu_types : UInt<10>, flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, rs1_data : UInt<65>, rs2_data : UInt<65>, rs3_data : UInt<65>, pred_data : UInt<1>, kill : UInt<1>}}, ll_iresp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}, ll_fresp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}, bypass : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}[0], flip brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip lsu_io : { flip req : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, predicated : UInt<1>, data : UInt<64>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}, addr : UInt<40>, mxcpt : { valid : UInt<1>, bits : UInt<25>}, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}}}, iresp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}, fresp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}}, flip bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[0], flip mcontext : UInt<0>, flip scontext : UInt<0>, flip com_exception : UInt<1>} \n\n\n connect io.req.ready, UInt<1>(0h0) \n connect io.ll_iresp.valid, UInt<1>(0h0) \n invalidate io.ll_iresp.bits.fflags.bits.flags \n invalidate io.ll_iresp.bits.fflags.bits.uop.debug_tsrc \n invalidate io.ll_iresp.bits.fflags.bits.uop.debug_fsrc \n invalidate io.ll_iresp.bits.fflags.bits.uop.bp_xcpt_if \n invalidate io.ll_iresp.bits.fflags.bits.uop.bp_debug_if \n invalidate io.ll_iresp.bits.fflags.bits.uop.xcpt_ma_if \n invalidate io.ll_iresp.bits.fflags.bits.uop.xcpt_ae_if \n invalidate io.ll_iresp.bits.fflags.bits.uop.xcpt_pf_if \n invalidate io.ll_iresp.bits.fflags.bits.uop.fp_single \n invalidate io.ll_iresp.bits.fflags.bits.uop.fp_val \n invalidate io.ll_iresp.bits.fflags.bits.uop.frs3_en \n invalidate io.ll_iresp.bits.fflags.bits.uop.lrs2_rtype \n invalidate io.ll_iresp.bits.fflags.bits.uop.lrs1_rtype \n invalidate io.ll_iresp.bits.fflags.bits.uop.dst_rtype \n invalidate io.ll_iresp.bits.fflags.bits.uop.ldst_val \n invalidate io.ll_iresp.bits.fflags.bits.uop.lrs3 \n invalidate io.ll_iresp.bits.fflags.bits.uop.lrs2 \n invalidate io.ll_iresp.bits.fflags.bits.uop.lrs1 \n invalidate io.ll_iresp.bits.fflags.bits.uop.ldst \n invalidate io.ll_iresp.bits.fflags.bits.uop.ldst_is_rs1 \n invalidate io.ll_iresp.bits.fflags.bits.uop.flush_on_commit \n invalidate io.ll_iresp.bits.fflags.bits.uop.is_unique \n invalidate io.ll_iresp.bits.fflags.bits.uop.is_sys_pc2epc \n invalidate io.ll_iresp.bits.fflags.bits.uop.uses_stq \n invalidate io.ll_iresp.bits.fflags.bits.uop.uses_ldq \n invalidate io.ll_iresp.bits.fflags.bits.uop.is_amo \n invalidate io.ll_iresp.bits.fflags.bits.uop.is_fencei \n invalidate io.ll_iresp.bits.fflags.bits.uop.is_fence \n invalidate io.ll_iresp.bits.fflags.bits.uop.mem_signed \n invalidate io.ll_iresp.bits.fflags.bits.uop.mem_size \n invalidate io.ll_iresp.bits.fflags.bits.uop.mem_cmd \n invalidate io.ll_iresp.bits.fflags.bits.uop.bypassable \n invalidate io.ll_iresp.bits.fflags.bits.uop.exc_cause \n invalidate io.ll_iresp.bits.fflags.bits.uop.exception \n invalidate io.ll_iresp.bits.fflags.bits.uop.stale_pdst \n invalidate io.ll_iresp.bits.fflags.bits.uop.ppred_busy \n invalidate io.ll_iresp.bits.fflags.bits.uop.prs3_busy \n invalidate io.ll_iresp.bits.fflags.bits.uop.prs2_busy \n invalidate io.ll_iresp.bits.fflags.bits.uop.prs1_busy \n invalidate io.ll_iresp.bits.fflags.bits.uop.ppred \n invalidate io.ll_iresp.bits.fflags.bits.uop.prs3 \n invalidate io.ll_iresp.bits.fflags.bits.uop.prs2 \n invalidate io.ll_iresp.bits.fflags.bits.uop.prs1 \n invalidate io.ll_iresp.bits.fflags.bits.uop.pdst \n invalidate io.ll_iresp.bits.fflags.bits.uop.rxq_idx \n invalidate io.ll_iresp.bits.fflags.bits.uop.stq_idx \n invalidate io.ll_iresp.bits.fflags.bits.uop.ldq_idx \n invalidate io.ll_iresp.bits.fflags.bits.uop.rob_idx \n invalidate io.ll_iresp.bits.fflags.bits.uop.csr_addr \n invalidate io.ll_iresp.bits.fflags.bits.uop.imm_packed \n invalidate io.ll_iresp.bits.fflags.bits.uop.taken \n invalidate io.ll_iresp.bits.fflags.bits.uop.pc_lob \n invalidate io.ll_iresp.bits.fflags.bits.uop.edge_inst \n invalidate io.ll_iresp.bits.fflags.bits.uop.ftq_idx \n invalidate io.ll_iresp.bits.fflags.bits.uop.br_tag \n invalidate io.ll_iresp.bits.fflags.bits.uop.br_mask \n invalidate io.ll_iresp.bits.fflags.bits.uop.is_sfb \n invalidate io.ll_iresp.bits.fflags.bits.uop.is_jal \n invalidate io.ll_iresp.bits.fflags.bits.uop.is_jalr \n invalidate io.ll_iresp.bits.fflags.bits.uop.is_br \n invalidate io.ll_iresp.bits.fflags.bits.uop.iw_p2_poisoned \n invalidate io.ll_iresp.bits.fflags.bits.uop.iw_p1_poisoned \n invalidate io.ll_iresp.bits.fflags.bits.uop.iw_state \n invalidate io.ll_iresp.bits.fflags.bits.uop.ctrl.is_std \n invalidate io.ll_iresp.bits.fflags.bits.uop.ctrl.is_sta \n invalidate io.ll_iresp.bits.fflags.bits.uop.ctrl.is_load \n invalidate io.ll_iresp.bits.fflags.bits.uop.ctrl.csr_cmd \n invalidate io.ll_iresp.bits.fflags.bits.uop.ctrl.fcn_dw \n invalidate io.ll_iresp.bits.fflags.bits.uop.ctrl.op_fcn \n invalidate io.ll_iresp.bits.fflags.bits.uop.ctrl.imm_sel \n invalidate io.ll_iresp.bits.fflags.bits.uop.ctrl.op2_sel \n invalidate io.ll_iresp.bits.fflags.bits.uop.ctrl.op1_sel \n invalidate io.ll_iresp.bits.fflags.bits.uop.ctrl.br_type \n invalidate io.ll_iresp.bits.fflags.bits.uop.fu_code \n invalidate io.ll_iresp.bits.fflags.bits.uop.iq_type \n invalidate io.ll_iresp.bits.fflags.bits.uop.debug_pc \n invalidate io.ll_iresp.bits.fflags.bits.uop.is_rvc \n invalidate io.ll_iresp.bits.fflags.bits.uop.debug_inst \n invalidate io.ll_iresp.bits.fflags.bits.uop.inst \n invalidate io.ll_iresp.bits.fflags.bits.uop.uopc \n invalidate io.ll_iresp.bits.fflags.valid \n invalidate io.ll_iresp.bits.predicated \n invalidate io.ll_iresp.bits.data \n invalidate io.ll_iresp.bits.uop.debug_tsrc \n invalidate io.ll_iresp.bits.uop.debug_fsrc \n invalidate io.ll_iresp.bits.uop.bp_xcpt_if \n invalidate io.ll_iresp.bits.uop.bp_debug_if \n invalidate io.ll_iresp.bits.uop.xcpt_ma_if \n invalidate io.ll_iresp.bits.uop.xcpt_ae_if \n invalidate io.ll_iresp.bits.uop.xcpt_pf_if \n invalidate io.ll_iresp.bits.uop.fp_single \n invalidate io.ll_iresp.bits.uop.fp_val \n invalidate io.ll_iresp.bits.uop.frs3_en \n invalidate io.ll_iresp.bits.uop.lrs2_rtype \n invalidate io.ll_iresp.bits.uop.lrs1_rtype \n invalidate io.ll_iresp.bits.uop.dst_rtype \n invalidate io.ll_iresp.bits.uop.ldst_val \n invalidate io.ll_iresp.bits.uop.lrs3 \n invalidate io.ll_iresp.bits.uop.lrs2 \n invalidate io.ll_iresp.bits.uop.lrs1 \n invalidate io.ll_iresp.bits.uop.ldst \n invalidate io.ll_iresp.bits.uop.ldst_is_rs1 \n invalidate io.ll_iresp.bits.uop.flush_on_commit \n invalidate io.ll_iresp.bits.uop.is_unique \n invalidate io.ll_iresp.bits.uop.is_sys_pc2epc \n invalidate io.ll_iresp.bits.uop.uses_stq \n invalidate io.ll_iresp.bits.uop.uses_ldq \n invalidate io.ll_iresp.bits.uop.is_amo \n invalidate io.ll_iresp.bits.uop.is_fencei \n invalidate io.ll_iresp.bits.uop.is_fence \n invalidate io.ll_iresp.bits.uop.mem_signed \n invalidate io.ll_iresp.bits.uop.mem_size \n invalidate io.ll_iresp.bits.uop.mem_cmd \n invalidate io.ll_iresp.bits.uop.bypassable \n invalidate io.ll_iresp.bits.uop.exc_cause \n invalidate io.ll_iresp.bits.uop.exception \n invalidate io.ll_iresp.bits.uop.stale_pdst \n invalidate io.ll_iresp.bits.uop.ppred_busy \n invalidate io.ll_iresp.bits.uop.prs3_busy \n invalidate io.ll_iresp.bits.uop.prs2_busy \n invalidate io.ll_iresp.bits.uop.prs1_busy \n invalidate io.ll_iresp.bits.uop.ppred \n invalidate io.ll_iresp.bits.uop.prs3 \n invalidate io.ll_iresp.bits.uop.prs2 \n invalidate io.ll_iresp.bits.uop.prs1 \n invalidate io.ll_iresp.bits.uop.pdst \n invalidate io.ll_iresp.bits.uop.rxq_idx \n invalidate io.ll_iresp.bits.uop.stq_idx \n invalidate io.ll_iresp.bits.uop.ldq_idx \n invalidate io.ll_iresp.bits.uop.rob_idx \n invalidate io.ll_iresp.bits.uop.csr_addr \n invalidate io.ll_iresp.bits.uop.imm_packed \n invalidate io.ll_iresp.bits.uop.taken \n invalidate io.ll_iresp.bits.uop.pc_lob \n invalidate io.ll_iresp.bits.uop.edge_inst \n invalidate io.ll_iresp.bits.uop.ftq_idx \n invalidate io.ll_iresp.bits.uop.br_tag \n invalidate io.ll_iresp.bits.uop.br_mask \n invalidate io.ll_iresp.bits.uop.is_sfb \n invalidate io.ll_iresp.bits.uop.is_jal \n invalidate io.ll_iresp.bits.uop.is_jalr \n invalidate io.ll_iresp.bits.uop.is_br \n invalidate io.ll_iresp.bits.uop.iw_p2_poisoned \n invalidate io.ll_iresp.bits.uop.iw_p1_poisoned \n invalidate io.ll_iresp.bits.uop.iw_state \n invalidate io.ll_iresp.bits.uop.ctrl.is_std \n invalidate io.ll_iresp.bits.uop.ctrl.is_sta \n invalidate io.ll_iresp.bits.uop.ctrl.is_load \n invalidate io.ll_iresp.bits.uop.ctrl.csr_cmd \n invalidate io.ll_iresp.bits.uop.ctrl.fcn_dw \n invalidate io.ll_iresp.bits.uop.ctrl.op_fcn \n invalidate io.ll_iresp.bits.uop.ctrl.imm_sel \n invalidate io.ll_iresp.bits.uop.ctrl.op2_sel \n invalidate io.ll_iresp.bits.uop.ctrl.op1_sel \n invalidate io.ll_iresp.bits.uop.ctrl.br_type \n invalidate io.ll_iresp.bits.uop.fu_code \n invalidate io.ll_iresp.bits.uop.iq_type \n invalidate io.ll_iresp.bits.uop.debug_pc \n invalidate io.ll_iresp.bits.uop.is_rvc \n invalidate io.ll_iresp.bits.uop.debug_inst \n invalidate io.ll_iresp.bits.uop.inst \n invalidate io.ll_iresp.bits.uop.uopc \n connect io.ll_iresp.bits.fflags.valid, UInt<1>(0h0) \n connect io.ll_iresp.bits.predicated, UInt<1>(0h0) \n connect io.ll_fresp.valid, UInt<1>(0h0) \n invalidate io.ll_fresp.bits.fflags.bits.flags \n invalidate io.ll_fresp.bits.fflags.bits.uop.debug_tsrc \n invalidate io.ll_fresp.bits.fflags.bits.uop.debug_fsrc \n invalidate io.ll_fresp.bits.fflags.bits.uop.bp_xcpt_if \n invalidate io.ll_fresp.bits.fflags.bits.uop.bp_debug_if \n invalidate io.ll_fresp.bits.fflags.bits.uop.xcpt_ma_if \n invalidate io.ll_fresp.bits.fflags.bits.uop.xcpt_ae_if \n invalidate io.ll_fresp.bits.fflags.bits.uop.xcpt_pf_if \n invalidate io.ll_fresp.bits.fflags.bits.uop.fp_single \n invalidate io.ll_fresp.bits.fflags.bits.uop.fp_val \n invalidate io.ll_fresp.bits.fflags.bits.uop.frs3_en \n invalidate io.ll_fresp.bits.fflags.bits.uop.lrs2_rtype \n invalidate io.ll_fresp.bits.fflags.bits.uop.lrs1_rtype \n invalidate io.ll_fresp.bits.fflags.bits.uop.dst_rtype \n invalidate io.ll_fresp.bits.fflags.bits.uop.ldst_val \n invalidate io.ll_fresp.bits.fflags.bits.uop.lrs3 \n invalidate io.ll_fresp.bits.fflags.bits.uop.lrs2 \n invalidate io.ll_fresp.bits.fflags.bits.uop.lrs1 \n invalidate io.ll_fresp.bits.fflags.bits.uop.ldst \n invalidate io.ll_fresp.bits.fflags.bits.uop.ldst_is_rs1 \n invalidate io.ll_fresp.bits.fflags.bits.uop.flush_on_commit \n invalidate io.ll_fresp.bits.fflags.bits.uop.is_unique \n invalidate io.ll_fresp.bits.fflags.bits.uop.is_sys_pc2epc \n invalidate io.ll_fresp.bits.fflags.bits.uop.uses_stq \n invalidate io.ll_fresp.bits.fflags.bits.uop.uses_ldq \n invalidate io.ll_fresp.bits.fflags.bits.uop.is_amo \n invalidate io.ll_fresp.bits.fflags.bits.uop.is_fencei \n invalidate io.ll_fresp.bits.fflags.bits.uop.is_fence \n invalidate io.ll_fresp.bits.fflags.bits.uop.mem_signed \n invalidate io.ll_fresp.bits.fflags.bits.uop.mem_size \n invalidate io.ll_fresp.bits.fflags.bits.uop.mem_cmd \n invalidate io.ll_fresp.bits.fflags.bits.uop.bypassable \n invalidate io.ll_fresp.bits.fflags.bits.uop.exc_cause \n invalidate io.ll_fresp.bits.fflags.bits.uop.exception \n invalidate io.ll_fresp.bits.fflags.bits.uop.stale_pdst \n invalidate io.ll_fresp.bits.fflags.bits.uop.ppred_busy \n invalidate io.ll_fresp.bits.fflags.bits.uop.prs3_busy \n invalidate io.ll_fresp.bits.fflags.bits.uop.prs2_busy \n invalidate io.ll_fresp.bits.fflags.bits.uop.prs1_busy \n invalidate io.ll_fresp.bits.fflags.bits.uop.ppred \n invalidate io.ll_fresp.bits.fflags.bits.uop.prs3 \n invalidate io.ll_fresp.bits.fflags.bits.uop.prs2 \n invalidate io.ll_fresp.bits.fflags.bits.uop.prs1 \n invalidate io.ll_fresp.bits.fflags.bits.uop.pdst \n invalidate io.ll_fresp.bits.fflags.bits.uop.rxq_idx \n invalidate io.ll_fresp.bits.fflags.bits.uop.stq_idx \n invalidate io.ll_fresp.bits.fflags.bits.uop.ldq_idx \n invalidate io.ll_fresp.bits.fflags.bits.uop.rob_idx \n invalidate io.ll_fresp.bits.fflags.bits.uop.csr_addr \n invalidate io.ll_fresp.bits.fflags.bits.uop.imm_packed \n invalidate io.ll_fresp.bits.fflags.bits.uop.taken \n invalidate io.ll_fresp.bits.fflags.bits.uop.pc_lob \n invalidate io.ll_fresp.bits.fflags.bits.uop.edge_inst \n invalidate io.ll_fresp.bits.fflags.bits.uop.ftq_idx \n invalidate io.ll_fresp.bits.fflags.bits.uop.br_tag \n invalidate io.ll_fresp.bits.fflags.bits.uop.br_mask \n invalidate io.ll_fresp.bits.fflags.bits.uop.is_sfb \n invalidate io.ll_fresp.bits.fflags.bits.uop.is_jal \n invalidate io.ll_fresp.bits.fflags.bits.uop.is_jalr \n invalidate io.ll_fresp.bits.fflags.bits.uop.is_br \n invalidate io.ll_fresp.bits.fflags.bits.uop.iw_p2_poisoned \n invalidate io.ll_fresp.bits.fflags.bits.uop.iw_p1_poisoned \n invalidate io.ll_fresp.bits.fflags.bits.uop.iw_state \n invalidate io.ll_fresp.bits.fflags.bits.uop.ctrl.is_std \n invalidate io.ll_fresp.bits.fflags.bits.uop.ctrl.is_sta \n invalidate io.ll_fresp.bits.fflags.bits.uop.ctrl.is_load \n invalidate io.ll_fresp.bits.fflags.bits.uop.ctrl.csr_cmd \n invalidate io.ll_fresp.bits.fflags.bits.uop.ctrl.fcn_dw \n invalidate io.ll_fresp.bits.fflags.bits.uop.ctrl.op_fcn \n invalidate io.ll_fresp.bits.fflags.bits.uop.ctrl.imm_sel \n invalidate io.ll_fresp.bits.fflags.bits.uop.ctrl.op2_sel \n invalidate io.ll_fresp.bits.fflags.bits.uop.ctrl.op1_sel \n invalidate io.ll_fresp.bits.fflags.bits.uop.ctrl.br_type \n invalidate io.ll_fresp.bits.fflags.bits.uop.fu_code \n invalidate io.ll_fresp.bits.fflags.bits.uop.iq_type \n invalidate io.ll_fresp.bits.fflags.bits.uop.debug_pc \n invalidate io.ll_fresp.bits.fflags.bits.uop.is_rvc \n invalidate io.ll_fresp.bits.fflags.bits.uop.debug_inst \n invalidate io.ll_fresp.bits.fflags.bits.uop.inst \n invalidate io.ll_fresp.bits.fflags.bits.uop.uopc \n invalidate io.ll_fresp.bits.fflags.valid \n invalidate io.ll_fresp.bits.predicated \n invalidate io.ll_fresp.bits.data \n invalidate io.ll_fresp.bits.uop.debug_tsrc \n invalidate io.ll_fresp.bits.uop.debug_fsrc \n invalidate io.ll_fresp.bits.uop.bp_xcpt_if \n invalidate io.ll_fresp.bits.uop.bp_debug_if \n invalidate io.ll_fresp.bits.uop.xcpt_ma_if \n invalidate io.ll_fresp.bits.uop.xcpt_ae_if \n invalidate io.ll_fresp.bits.uop.xcpt_pf_if \n invalidate io.ll_fresp.bits.uop.fp_single \n invalidate io.ll_fresp.bits.uop.fp_val \n invalidate io.ll_fresp.bits.uop.frs3_en \n invalidate io.ll_fresp.bits.uop.lrs2_rtype \n invalidate io.ll_fresp.bits.uop.lrs1_rtype \n invalidate io.ll_fresp.bits.uop.dst_rtype \n invalidate io.ll_fresp.bits.uop.ldst_val \n invalidate io.ll_fresp.bits.uop.lrs3 \n invalidate io.ll_fresp.bits.uop.lrs2 \n invalidate io.ll_fresp.bits.uop.lrs1 \n invalidate io.ll_fresp.bits.uop.ldst \n invalidate io.ll_fresp.bits.uop.ldst_is_rs1 \n invalidate io.ll_fresp.bits.uop.flush_on_commit \n invalidate io.ll_fresp.bits.uop.is_unique \n invalidate io.ll_fresp.bits.uop.is_sys_pc2epc \n invalidate io.ll_fresp.bits.uop.uses_stq \n invalidate io.ll_fresp.bits.uop.uses_ldq \n invalidate io.ll_fresp.bits.uop.is_amo \n invalidate io.ll_fresp.bits.uop.is_fencei \n invalidate io.ll_fresp.bits.uop.is_fence \n invalidate io.ll_fresp.bits.uop.mem_signed \n invalidate io.ll_fresp.bits.uop.mem_size \n invalidate io.ll_fresp.bits.uop.mem_cmd \n invalidate io.ll_fresp.bits.uop.bypassable \n invalidate io.ll_fresp.bits.uop.exc_cause \n invalidate io.ll_fresp.bits.uop.exception \n invalidate io.ll_fresp.bits.uop.stale_pdst \n invalidate io.ll_fresp.bits.uop.ppred_busy \n invalidate io.ll_fresp.bits.uop.prs3_busy \n invalidate io.ll_fresp.bits.uop.prs2_busy \n invalidate io.ll_fresp.bits.uop.prs1_busy \n invalidate io.ll_fresp.bits.uop.ppred \n invalidate io.ll_fresp.bits.uop.prs3 \n invalidate io.ll_fresp.bits.uop.prs2 \n invalidate io.ll_fresp.bits.uop.prs1 \n invalidate io.ll_fresp.bits.uop.pdst \n invalidate io.ll_fresp.bits.uop.rxq_idx \n invalidate io.ll_fresp.bits.uop.stq_idx \n invalidate io.ll_fresp.bits.uop.ldq_idx \n invalidate io.ll_fresp.bits.uop.rob_idx \n invalidate io.ll_fresp.bits.uop.csr_addr \n invalidate io.ll_fresp.bits.uop.imm_packed \n invalidate io.ll_fresp.bits.uop.taken \n invalidate io.ll_fresp.bits.uop.pc_lob \n invalidate io.ll_fresp.bits.uop.edge_inst \n invalidate io.ll_fresp.bits.uop.ftq_idx \n invalidate io.ll_fresp.bits.uop.br_tag \n invalidate io.ll_fresp.bits.uop.br_mask \n invalidate io.ll_fresp.bits.uop.is_sfb \n invalidate io.ll_fresp.bits.uop.is_jal \n invalidate io.ll_fresp.bits.uop.is_jalr \n invalidate io.ll_fresp.bits.uop.is_br \n invalidate io.ll_fresp.bits.uop.iw_p2_poisoned \n invalidate io.ll_fresp.bits.uop.iw_p1_poisoned \n invalidate io.ll_fresp.bits.uop.iw_state \n invalidate io.ll_fresp.bits.uop.ctrl.is_std \n invalidate io.ll_fresp.bits.uop.ctrl.is_sta \n invalidate io.ll_fresp.bits.uop.ctrl.is_load \n invalidate io.ll_fresp.bits.uop.ctrl.csr_cmd \n invalidate io.ll_fresp.bits.uop.ctrl.fcn_dw \n invalidate io.ll_fresp.bits.uop.ctrl.op_fcn \n invalidate io.ll_fresp.bits.uop.ctrl.imm_sel \n invalidate io.ll_fresp.bits.uop.ctrl.op2_sel \n invalidate io.ll_fresp.bits.uop.ctrl.op1_sel \n invalidate io.ll_fresp.bits.uop.ctrl.br_type \n invalidate io.ll_fresp.bits.uop.fu_code \n invalidate io.ll_fresp.bits.uop.iq_type \n invalidate io.ll_fresp.bits.uop.debug_pc \n invalidate io.ll_fresp.bits.uop.is_rvc \n invalidate io.ll_fresp.bits.uop.debug_inst \n invalidate io.ll_fresp.bits.uop.inst \n invalidate io.ll_fresp.bits.uop.uopc \n connect io.ll_fresp.bits.fflags.valid, UInt<1>(0h0) \n connect io.ll_fresp.bits.predicated, UInt<1>(0h0) \n wire div_busy : UInt<1> \n connect div_busy, UInt<1>(0h0) \n wire ifpu_busy : UInt<1> \n connect ifpu_busy, UInt<1>(0h0) \n node _io_fu_types_T = mux(UInt<1>(0h0), UInt<10>(0h1), UInt<1>(0h0)) \n node _io_fu_types_T_1 = mux(UInt<1>(0h0), UInt<10>(0h8), UInt<1>(0h0)) \n node _io_fu_types_T_2 = or(_io_fu_types_T, _io_fu_types_T_1) \n node _io_fu_types_T_3 = eq(div_busy, UInt<1>(0h0)) \n node _io_fu_types_T_4 = and(_io_fu_types_T_3, UInt<1>(0h0)) \n node _io_fu_types_T_5 = mux(_io_fu_types_T_4, UInt<10>(0h10), UInt<1>(0h0)) \n node _io_fu_types_T_6 = or(_io_fu_types_T_2, _io_fu_types_T_5) \n node _io_fu_types_T_7 = mux(UInt<1>(0h0), UInt<10>(0h20), UInt<1>(0h0)) \n node _io_fu_types_T_8 = or(_io_fu_types_T_6, _io_fu_types_T_7) \n node _io_fu_types_T_9 = mux(UInt<1>(0h0), UInt<10>(0h2), UInt<1>(0h0)) \n node _io_fu_types_T_10 = or(_io_fu_types_T_8, _io_fu_types_T_9) \n node _io_fu_types_T_11 = eq(ifpu_busy, UInt<1>(0h0)) \n node _io_fu_types_T_12 = and(_io_fu_types_T_11, UInt<1>(0h0)) \n node _io_fu_types_T_13 = mux(_io_fu_types_T_12, UInt<10>(0h100), UInt<1>(0h0)) \n node _io_fu_types_T_14 = or(_io_fu_types_T_10, _io_fu_types_T_13) \n node _io_fu_types_T_15 = mux(UInt<1>(0h1), UInt<10>(0h4), UInt<1>(0h0)) \n node _io_fu_types_T_16 = or(_io_fu_types_T_14, _io_fu_types_T_15) \n connect io.fu_types, _io_fu_types_T_16 \n wire div_resp_val : UInt<1> \n connect div_resp_val, UInt<1>(0h0) \n inst maddrcalc of MemAddrCalcUnit_1 \n connect maddrcalc.clock, clock\n\n connect maddrcalc.reset, reset\n\n connect maddrcalc.io.req, io.req \n node _maddrcalc_io_req_valid_T = and(io.req.bits.uop.fu_code, UInt<10>(0h4)) \n node _maddrcalc_io_req_valid_T_1 = neq(_maddrcalc_io_req_valid_T, UInt<1>(0h0)) \n node _maddrcalc_io_req_valid_T_2 = and(io.req.valid, _maddrcalc_io_req_valid_T_1) \n connect maddrcalc.io.req.valid, _maddrcalc_io_req_valid_T_2 \n connect maddrcalc.io.brupdate, io.brupdate \n connect maddrcalc.io.status.uie, io.status.uie \n connect maddrcalc.io.status.sie, io.status.sie \n connect maddrcalc.io.status.hie, io.status.hie \n connect maddrcalc.io.status.mie, io.status.mie \n connect maddrcalc.io.status.upie, io.status.upie \n connect maddrcalc.io.status.spie, io.status.spie \n connect maddrcalc.io.status.ube, io.status.ube \n connect maddrcalc.io.status.mpie, io.status.mpie \n connect maddrcalc.io.status.spp, io.status.spp \n connect maddrcalc.io.status.vs, io.status.vs \n connect maddrcalc.io.status.mpp, io.status.mpp \n connect maddrcalc.io.status.fs, io.status.fs \n connect maddrcalc.io.status.xs, io.status.xs \n connect maddrcalc.io.status.mprv, io.status.mprv \n connect maddrcalc.io.status.sum, io.status.sum \n connect maddrcalc.io.status.mxr, io.status.mxr \n connect maddrcalc.io.status.tvm, io.status.tvm \n connect maddrcalc.io.status.tw, io.status.tw \n connect maddrcalc.io.status.tsr, io.status.tsr \n connect maddrcalc.io.status.zero1, io.status.zero1 \n connect maddrcalc.io.status.sd_rv32, io.status.sd_rv32 \n connect maddrcalc.io.status.uxl, io.status.uxl \n connect maddrcalc.io.status.sxl, io.status.sxl \n connect maddrcalc.io.status.sbe, io.status.sbe \n connect maddrcalc.io.status.mbe, io.status.mbe \n connect maddrcalc.io.status.gva, io.status.gva \n connect maddrcalc.io.status.mpv, io.status.mpv \n connect maddrcalc.io.status.zero2, io.status.zero2 \n connect maddrcalc.io.status.sd, io.status.sd \n connect maddrcalc.io.status.v, io.status.v \n connect maddrcalc.io.status.prv, io.status.prv \n connect maddrcalc.io.status.dv, io.status.dv \n connect maddrcalc.io.status.dprv, io.status.dprv \n connect maddrcalc.io.status.isa, io.status.isa \n connect maddrcalc.io.status.wfi, io.status.wfi \n connect maddrcalc.io.status.cease, io.status.cease \n connect maddrcalc.io.status.debug, io.status.debug \n connect maddrcalc.io.mcontext, io.mcontext \n connect maddrcalc.io.scontext, io.scontext \n invalidate maddrcalc.io.resp.ready \n connect io.lsu_io.req.bits, maddrcalc.io.resp.bits \n connect io.lsu_io.req.valid, maddrcalc.io.resp.valid \n connect io.ll_iresp, io.lsu_io.iresp \n connect io.ll_fresp, io.lsu_io.fresp \n node _T = leq(UInt<1>(0h0), UInt<1>(0h1)) \n node _T_1 = eq(div_resp_val, UInt<1>(0h0)) \n node _T_2 = and(_T, _T_1) \n node _T_3 = leq(UInt<1>(0h0), UInt<2>(0h2)) \n node _T_4 = and(_T_3, div_resp_val) \n node _T_5 = or(_T_2, _T_4) \n node _T_6 = asUInt(reset) \n node _T_7 = eq(_T_6, UInt<1>(0h0)) \n when _T_7 : \n node _T_8 = eq(_T_5, UInt<1>(0h0)) \n when _T_8 : \n printf(clock, UInt<1>(0h1), \"Assertion failed: Multiple functional units are fighting over the write port.\\n at execution-unit.scala:425 assert ((PopCount(iresp_fu_units.map(_.io.resp.valid)) <= 1.U && !div_resp_val) ||\\n\") : printf \n assert(clock, _T_5, UInt<1>(0h1), \"\") : assert"},"response":{"kind":"string","value":"module ALUExeUnit_2(\t// @[execution-unit.scala:204:7]\n input clock,\t// @[execution-unit.scala:204:7]\n input reset,\t// @[execution-unit.scala:204:7]\n input io_req_valid,\t// @[execution-unit.scala:104:14]\n input [6:0] io_req_bits_uop_uopc,\t// @[execution-unit.scala:104:14]\n input [31:0] io_req_bits_uop_inst,\t// @[execution-unit.scala:104:14]\n input [31:0] io_req_bits_uop_debug_inst,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_is_rvc,\t// @[execution-unit.scala:104:14]\n input [39:0] io_req_bits_uop_debug_pc,\t// @[execution-unit.scala:104:14]\n input [2:0] io_req_bits_uop_iq_type,\t// @[execution-unit.scala:104:14]\n input [9:0] io_req_bits_uop_fu_code,\t// @[execution-unit.scala:104:14]\n input [3:0] io_req_bits_uop_ctrl_br_type,\t// @[execution-unit.scala:104:14]\n input [1:0] io_req_bits_uop_ctrl_op1_sel,\t// @[execution-unit.scala:104:14]\n input [2:0] io_req_bits_uop_ctrl_op2_sel,\t// @[execution-unit.scala:104:14]\n input [2:0] io_req_bits_uop_ctrl_imm_sel,\t// @[execution-unit.scala:104:14]\n input [4:0] io_req_bits_uop_ctrl_op_fcn,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_ctrl_fcn_dw,\t// @[execution-unit.scala:104:14]\n input [2:0] io_req_bits_uop_ctrl_csr_cmd,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_ctrl_is_load,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_ctrl_is_sta,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_ctrl_is_std,\t// @[execution-unit.scala:104:14]\n input [1:0] io_req_bits_uop_iw_state,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_iw_p1_poisoned,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_iw_p2_poisoned,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_is_br,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_is_jalr,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_is_jal,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_is_sfb,\t// @[execution-unit.scala:104:14]\n input [7:0] io_req_bits_uop_br_mask,\t// @[execution-unit.scala:104:14]\n input [2:0] io_req_bits_uop_br_tag,\t// @[execution-unit.scala:104:14]\n input [3:0] io_req_bits_uop_ftq_idx,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_edge_inst,\t// @[execution-unit.scala:104:14]\n input [5:0] io_req_bits_uop_pc_lob,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_taken,\t// @[execution-unit.scala:104:14]\n input [19:0] io_req_bits_uop_imm_packed,\t// @[execution-unit.scala:104:14]\n input [11:0] io_req_bits_uop_csr_addr,\t// @[execution-unit.scala:104:14]\n input [4:0] io_req_bits_uop_rob_idx,\t// @[execution-unit.scala:104:14]\n input [2:0] io_req_bits_uop_ldq_idx,\t// @[execution-unit.scala:104:14]\n input [2:0] io_req_bits_uop_stq_idx,\t// @[execution-unit.scala:104:14]\n input [1:0] io_req_bits_uop_rxq_idx,\t// @[execution-unit.scala:104:14]\n input [5:0] io_req_bits_uop_pdst,\t// @[execution-unit.scala:104:14]\n input [5:0] io_req_bits_uop_prs1,\t// @[execution-unit.scala:104:14]\n input [5:0] io_req_bits_uop_prs2,\t// @[execution-unit.scala:104:14]\n input [5:0] io_req_bits_uop_prs3,\t// @[execution-unit.scala:104:14]\n input [3:0] io_req_bits_uop_ppred,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_prs1_busy,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_prs2_busy,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_prs3_busy,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_ppred_busy,\t// @[execution-unit.scala:104:14]\n input [5:0] io_req_bits_uop_stale_pdst,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_exception,\t// @[execution-unit.scala:104:14]\n input [63:0] io_req_bits_uop_exc_cause,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_bypassable,\t// @[execution-unit.scala:104:14]\n input [4:0] io_req_bits_uop_mem_cmd,\t// @[execution-unit.scala:104:14]\n input [1:0] io_req_bits_uop_mem_size,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_mem_signed,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_is_fence,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_is_fencei,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_is_amo,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_uses_ldq,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_uses_stq,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_is_sys_pc2epc,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_is_unique,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_flush_on_commit,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_ldst_is_rs1,\t// @[execution-unit.scala:104:14]\n input [5:0] io_req_bits_uop_ldst,\t// @[execution-unit.scala:104:14]\n input [5:0] io_req_bits_uop_lrs1,\t// @[execution-unit.scala:104:14]\n input [5:0] io_req_bits_uop_lrs2,\t// @[execution-unit.scala:104:14]\n input [5:0] io_req_bits_uop_lrs3,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_ldst_val,\t// @[execution-unit.scala:104:14]\n input [1:0] io_req_bits_uop_dst_rtype,\t// @[execution-unit.scala:104:14]\n input [1:0] io_req_bits_uop_lrs1_rtype,\t// @[execution-unit.scala:104:14]\n input [1:0] io_req_bits_uop_lrs2_rtype,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_frs3_en,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_fp_val,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_fp_single,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_xcpt_pf_if,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_xcpt_ae_if,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_xcpt_ma_if,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_bp_debug_if,\t// @[execution-unit.scala:104:14]\n input io_req_bits_uop_bp_xcpt_if,\t// @[execution-unit.scala:104:14]\n input [1:0] io_req_bits_uop_debug_fsrc,\t// @[execution-unit.scala:104:14]\n input [1:0] io_req_bits_uop_debug_tsrc,\t// @[execution-unit.scala:104:14]\n input [64:0] io_req_bits_rs1_data,\t// @[execution-unit.scala:104:14]\n input [64:0] io_req_bits_rs2_data,\t// @[execution-unit.scala:104:14]\n input io_req_bits_kill,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_valid,\t// @[execution-unit.scala:104:14]\n output [6:0] io_ll_iresp_bits_uop_uopc,\t// @[execution-unit.scala:104:14]\n output [31:0] io_ll_iresp_bits_uop_inst,\t// @[execution-unit.scala:104:14]\n output [31:0] io_ll_iresp_bits_uop_debug_inst,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_is_rvc,\t// @[execution-unit.scala:104:14]\n output [39:0] io_ll_iresp_bits_uop_debug_pc,\t// @[execution-unit.scala:104:14]\n output [2:0] io_ll_iresp_bits_uop_iq_type,\t// @[execution-unit.scala:104:14]\n output [9:0] io_ll_iresp_bits_uop_fu_code,\t// @[execution-unit.scala:104:14]\n output [3:0] io_ll_iresp_bits_uop_ctrl_br_type,\t// @[execution-unit.scala:104:14]\n output [1:0] io_ll_iresp_bits_uop_ctrl_op1_sel,\t// @[execution-unit.scala:104:14]\n output [2:0] io_ll_iresp_bits_uop_ctrl_op2_sel,\t// @[execution-unit.scala:104:14]\n output [2:0] io_ll_iresp_bits_uop_ctrl_imm_sel,\t// @[execution-unit.scala:104:14]\n output [4:0] io_ll_iresp_bits_uop_ctrl_op_fcn,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_ctrl_fcn_dw,\t// @[execution-unit.scala:104:14]\n output [2:0] io_ll_iresp_bits_uop_ctrl_csr_cmd,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_ctrl_is_load,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_ctrl_is_sta,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_ctrl_is_std,\t// @[execution-unit.scala:104:14]\n output [1:0] io_ll_iresp_bits_uop_iw_state,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_iw_p1_poisoned,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_iw_p2_poisoned,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_is_br,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_is_jalr,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_is_jal,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_is_sfb,\t// @[execution-unit.scala:104:14]\n output [7:0] io_ll_iresp_bits_uop_br_mask,\t// @[execution-unit.scala:104:14]\n output [2:0] io_ll_iresp_bits_uop_br_tag,\t// @[execution-unit.scala:104:14]\n output [3:0] io_ll_iresp_bits_uop_ftq_idx,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_edge_inst,\t// @[execution-unit.scala:104:14]\n output [5:0] io_ll_iresp_bits_uop_pc_lob,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_taken,\t// @[execution-unit.scala:104:14]\n output [19:0] io_ll_iresp_bits_uop_imm_packed,\t// @[execution-unit.scala:104:14]\n output [11:0] io_ll_iresp_bits_uop_csr_addr,\t// @[execution-unit.scala:104:14]\n output [4:0] io_ll_iresp_bits_uop_rob_idx,\t// @[execution-unit.scala:104:14]\n output [2:0] io_ll_iresp_bits_uop_ldq_idx,\t// @[execution-unit.scala:104:14]\n output [2:0] io_ll_iresp_bits_uop_stq_idx,\t// @[execution-unit.scala:104:14]\n output [1:0] io_ll_iresp_bits_uop_rxq_idx,\t// @[execution-unit.scala:104:14]\n output [5:0] io_ll_iresp_bits_uop_pdst,\t// @[execution-unit.scala:104:14]\n output [5:0] io_ll_iresp_bits_uop_prs1,\t// @[execution-unit.scala:104:14]\n output [5:0] io_ll_iresp_bits_uop_prs2,\t// @[execution-unit.scala:104:14]\n output [5:0] io_ll_iresp_bits_uop_prs3,\t// @[execution-unit.scala:104:14]\n output [3:0] io_ll_iresp_bits_uop_ppred,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_prs1_busy,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_prs2_busy,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_prs3_busy,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_ppred_busy,\t// @[execution-unit.scala:104:14]\n output [5:0] io_ll_iresp_bits_uop_stale_pdst,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_exception,\t// @[execution-unit.scala:104:14]\n output [63:0] io_ll_iresp_bits_uop_exc_cause,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_bypassable,\t// @[execution-unit.scala:104:14]\n output [4:0] io_ll_iresp_bits_uop_mem_cmd,\t// @[execution-unit.scala:104:14]\n output [1:0] io_ll_iresp_bits_uop_mem_size,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_mem_signed,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_is_fence,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_is_fencei,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_is_amo,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_uses_ldq,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_uses_stq,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_is_sys_pc2epc,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_is_unique,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_flush_on_commit,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_ldst_is_rs1,\t// @[execution-unit.scala:104:14]\n output [5:0] io_ll_iresp_bits_uop_ldst,\t// @[execution-unit.scala:104:14]\n output [5:0] io_ll_iresp_bits_uop_lrs1,\t// @[execution-unit.scala:104:14]\n output [5:0] io_ll_iresp_bits_uop_lrs2,\t// @[execution-unit.scala:104:14]\n output [5:0] io_ll_iresp_bits_uop_lrs3,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_ldst_val,\t// @[execution-unit.scala:104:14]\n output [1:0] io_ll_iresp_bits_uop_dst_rtype,\t// @[execution-unit.scala:104:14]\n output [1:0] io_ll_iresp_bits_uop_lrs1_rtype,\t// @[execution-unit.scala:104:14]\n output [1:0] io_ll_iresp_bits_uop_lrs2_rtype,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_frs3_en,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_fp_val,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_fp_single,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_xcpt_pf_if,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_xcpt_ae_if,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_xcpt_ma_if,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_bp_debug_if,\t// @[execution-unit.scala:104:14]\n output io_ll_iresp_bits_uop_bp_xcpt_if,\t// @[execution-unit.scala:104:14]\n output [1:0] io_ll_iresp_bits_uop_debug_fsrc,\t// @[execution-unit.scala:104:14]\n output [1:0] io_ll_iresp_bits_uop_debug_tsrc,\t// @[execution-unit.scala:104:14]\n output [64:0] io_ll_iresp_bits_data,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_valid,\t// @[execution-unit.scala:104:14]\n output [6:0] io_ll_fresp_bits_uop_uopc,\t// @[execution-unit.scala:104:14]\n output [31:0] io_ll_fresp_bits_uop_inst,\t// @[execution-unit.scala:104:14]\n output [31:0] io_ll_fresp_bits_uop_debug_inst,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_is_rvc,\t// @[execution-unit.scala:104:14]\n output [39:0] io_ll_fresp_bits_uop_debug_pc,\t// @[execution-unit.scala:104:14]\n output [2:0] io_ll_fresp_bits_uop_iq_type,\t// @[execution-unit.scala:104:14]\n output [9:0] io_ll_fresp_bits_uop_fu_code,\t// @[execution-unit.scala:104:14]\n output [3:0] io_ll_fresp_bits_uop_ctrl_br_type,\t// @[execution-unit.scala:104:14]\n output [1:0] io_ll_fresp_bits_uop_ctrl_op1_sel,\t// @[execution-unit.scala:104:14]\n output [2:0] io_ll_fresp_bits_uop_ctrl_op2_sel,\t// @[execution-unit.scala:104:14]\n output [2:0] io_ll_fresp_bits_uop_ctrl_imm_sel,\t// @[execution-unit.scala:104:14]\n output [4:0] io_ll_fresp_bits_uop_ctrl_op_fcn,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_ctrl_fcn_dw,\t// @[execution-unit.scala:104:14]\n output [2:0] io_ll_fresp_bits_uop_ctrl_csr_cmd,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_ctrl_is_load,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_ctrl_is_sta,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_ctrl_is_std,\t// @[execution-unit.scala:104:14]\n output [1:0] io_ll_fresp_bits_uop_iw_state,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_iw_p1_poisoned,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_iw_p2_poisoned,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_is_br,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_is_jalr,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_is_jal,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_is_sfb,\t// @[execution-unit.scala:104:14]\n output [7:0] io_ll_fresp_bits_uop_br_mask,\t// @[execution-unit.scala:104:14]\n output [2:0] io_ll_fresp_bits_uop_br_tag,\t// @[execution-unit.scala:104:14]\n output [3:0] io_ll_fresp_bits_uop_ftq_idx,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_edge_inst,\t// @[execution-unit.scala:104:14]\n output [5:0] io_ll_fresp_bits_uop_pc_lob,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_taken,\t// @[execution-unit.scala:104:14]\n output [19:0] io_ll_fresp_bits_uop_imm_packed,\t// @[execution-unit.scala:104:14]\n output [11:0] io_ll_fresp_bits_uop_csr_addr,\t// @[execution-unit.scala:104:14]\n output [4:0] io_ll_fresp_bits_uop_rob_idx,\t// @[execution-unit.scala:104:14]\n output [2:0] io_ll_fresp_bits_uop_ldq_idx,\t// @[execution-unit.scala:104:14]\n output [2:0] io_ll_fresp_bits_uop_stq_idx,\t// @[execution-unit.scala:104:14]\n output [1:0] io_ll_fresp_bits_uop_rxq_idx,\t// @[execution-unit.scala:104:14]\n output [5:0] io_ll_fresp_bits_uop_pdst,\t// @[execution-unit.scala:104:14]\n output [5:0] io_ll_fresp_bits_uop_prs1,\t// @[execution-unit.scala:104:14]\n output [5:0] io_ll_fresp_bits_uop_prs2,\t// @[execution-unit.scala:104:14]\n output [5:0] io_ll_fresp_bits_uop_prs3,\t// @[execution-unit.scala:104:14]\n output [3:0] io_ll_fresp_bits_uop_ppred,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_prs1_busy,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_prs2_busy,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_prs3_busy,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_ppred_busy,\t// @[execution-unit.scala:104:14]\n output [5:0] io_ll_fresp_bits_uop_stale_pdst,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_exception,\t// @[execution-unit.scala:104:14]\n output [63:0] io_ll_fresp_bits_uop_exc_cause,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_bypassable,\t// @[execution-unit.scala:104:14]\n output [4:0] io_ll_fresp_bits_uop_mem_cmd,\t// @[execution-unit.scala:104:14]\n output [1:0] io_ll_fresp_bits_uop_mem_size,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_mem_signed,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_is_fence,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_is_fencei,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_is_amo,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_uses_ldq,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_uses_stq,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_is_sys_pc2epc,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_is_unique,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_flush_on_commit,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_ldst_is_rs1,\t// @[execution-unit.scala:104:14]\n output [5:0] io_ll_fresp_bits_uop_ldst,\t// @[execution-unit.scala:104:14]\n output [5:0] io_ll_fresp_bits_uop_lrs1,\t// @[execution-unit.scala:104:14]\n output [5:0] io_ll_fresp_bits_uop_lrs2,\t// @[execution-unit.scala:104:14]\n output [5:0] io_ll_fresp_bits_uop_lrs3,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_ldst_val,\t// @[execution-unit.scala:104:14]\n output [1:0] io_ll_fresp_bits_uop_dst_rtype,\t// @[execution-unit.scala:104:14]\n output [1:0] io_ll_fresp_bits_uop_lrs1_rtype,\t// @[execution-unit.scala:104:14]\n output [1:0] io_ll_fresp_bits_uop_lrs2_rtype,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_frs3_en,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_fp_val,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_fp_single,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_xcpt_pf_if,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_xcpt_ae_if,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_xcpt_ma_if,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_bp_debug_if,\t// @[execution-unit.scala:104:14]\n output io_ll_fresp_bits_uop_bp_xcpt_if,\t// @[execution-unit.scala:104:14]\n output [1:0] io_ll_fresp_bits_uop_debug_fsrc,\t// @[execution-unit.scala:104:14]\n output [1:0] io_ll_fresp_bits_uop_debug_tsrc,\t// @[execution-unit.scala:104:14]\n output [64:0] io_ll_fresp_bits_data,\t// @[execution-unit.scala:104:14]\n input [7:0] io_brupdate_b1_resolve_mask,\t// @[execution-unit.scala:104:14]\n input [7:0] io_brupdate_b1_mispredict_mask,\t// @[execution-unit.scala:104:14]\n input [6:0] io_brupdate_b2_uop_uopc,\t// @[execution-unit.scala:104:14]\n input [31:0] io_brupdate_b2_uop_inst,\t// @[execution-unit.scala:104:14]\n input [31:0] io_brupdate_b2_uop_debug_inst,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_is_rvc,\t// @[execution-unit.scala:104:14]\n input [39:0] io_brupdate_b2_uop_debug_pc,\t// @[execution-unit.scala:104:14]\n input [2:0] io_brupdate_b2_uop_iq_type,\t// @[execution-unit.scala:104:14]\n input [9:0] io_brupdate_b2_uop_fu_code,\t// @[execution-unit.scala:104:14]\n input [3:0] io_brupdate_b2_uop_ctrl_br_type,\t// @[execution-unit.scala:104:14]\n input [1:0] io_brupdate_b2_uop_ctrl_op1_sel,\t// @[execution-unit.scala:104:14]\n input [2:0] io_brupdate_b2_uop_ctrl_op2_sel,\t// @[execution-unit.scala:104:14]\n input [2:0] io_brupdate_b2_uop_ctrl_imm_sel,\t// @[execution-unit.scala:104:14]\n input [4:0] io_brupdate_b2_uop_ctrl_op_fcn,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_ctrl_fcn_dw,\t// @[execution-unit.scala:104:14]\n input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_ctrl_is_load,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_ctrl_is_sta,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_ctrl_is_std,\t// @[execution-unit.scala:104:14]\n input [1:0] io_brupdate_b2_uop_iw_state,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_iw_p1_poisoned,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_iw_p2_poisoned,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_is_br,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_is_jalr,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_is_jal,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_is_sfb,\t// @[execution-unit.scala:104:14]\n input [7:0] io_brupdate_b2_uop_br_mask,\t// @[execution-unit.scala:104:14]\n input [2:0] io_brupdate_b2_uop_br_tag,\t// @[execution-unit.scala:104:14]\n input [3:0] io_brupdate_b2_uop_ftq_idx,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_edge_inst,\t// @[execution-unit.scala:104:14]\n input [5:0] io_brupdate_b2_uop_pc_lob,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_taken,\t// @[execution-unit.scala:104:14]\n input [19:0] io_brupdate_b2_uop_imm_packed,\t// @[execution-unit.scala:104:14]\n input [11:0] io_brupdate_b2_uop_csr_addr,\t// @[execution-unit.scala:104:14]\n input [4:0] io_brupdate_b2_uop_rob_idx,\t// @[execution-unit.scala:104:14]\n input [2:0] io_brupdate_b2_uop_ldq_idx,\t// @[execution-unit.scala:104:14]\n input [2:0] io_brupdate_b2_uop_stq_idx,\t// @[execution-unit.scala:104:14]\n input [1:0] io_brupdate_b2_uop_rxq_idx,\t// @[execution-unit.scala:104:14]\n input [5:0] io_brupdate_b2_uop_pdst,\t// @[execution-unit.scala:104:14]\n input [5:0] io_brupdate_b2_uop_prs1,\t// @[execution-unit.scala:104:14]\n input [5:0] io_brupdate_b2_uop_prs2,\t// @[execution-unit.scala:104:14]\n input [5:0] io_brupdate_b2_uop_prs3,\t// @[execution-unit.scala:104:14]\n input [3:0] io_brupdate_b2_uop_ppred,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_prs1_busy,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_prs2_busy,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_prs3_busy,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_ppred_busy,\t// @[execution-unit.scala:104:14]\n input [5:0] io_brupdate_b2_uop_stale_pdst,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_exception,\t// @[execution-unit.scala:104:14]\n input [63:0] io_brupdate_b2_uop_exc_cause,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_bypassable,\t// @[execution-unit.scala:104:14]\n input [4:0] io_brupdate_b2_uop_mem_cmd,\t// @[execution-unit.scala:104:14]\n input [1:0] io_brupdate_b2_uop_mem_size,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_mem_signed,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_is_fence,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_is_fencei,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_is_amo,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_uses_ldq,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_uses_stq,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_is_sys_pc2epc,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_is_unique,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_flush_on_commit,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_ldst_is_rs1,\t// @[execution-unit.scala:104:14]\n input [5:0] io_brupdate_b2_uop_ldst,\t// @[execution-unit.scala:104:14]\n input [5:0] io_brupdate_b2_uop_lrs1,\t// @[execution-unit.scala:104:14]\n input [5:0] io_brupdate_b2_uop_lrs2,\t// @[execution-unit.scala:104:14]\n input [5:0] io_brupdate_b2_uop_lrs3,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_ldst_val,\t// @[execution-unit.scala:104:14]\n input [1:0] io_brupdate_b2_uop_dst_rtype,\t// @[execution-unit.scala:104:14]\n input [1:0] io_brupdate_b2_uop_lrs1_rtype,\t// @[execution-unit.scala:104:14]\n input [1:0] io_brupdate_b2_uop_lrs2_rtype,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_frs3_en,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_fp_val,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_fp_single,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_xcpt_pf_if,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_xcpt_ae_if,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_xcpt_ma_if,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_bp_debug_if,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_uop_bp_xcpt_if,\t// @[execution-unit.scala:104:14]\n input [1:0] io_brupdate_b2_uop_debug_fsrc,\t// @[execution-unit.scala:104:14]\n input [1:0] io_brupdate_b2_uop_debug_tsrc,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_valid,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_mispredict,\t// @[execution-unit.scala:104:14]\n input io_brupdate_b2_taken,\t// @[execution-unit.scala:104:14]\n input [2:0] io_brupdate_b2_cfi_type,\t// @[execution-unit.scala:104:14]\n input [1:0] io_brupdate_b2_pc_sel,\t// @[execution-unit.scala:104:14]\n input [39:0] io_brupdate_b2_jalr_target,\t// @[execution-unit.scala:104:14]\n input [20:0] io_brupdate_b2_target_offset,\t// @[execution-unit.scala:104:14]\n input io_status_debug,\t// @[execution-unit.scala:104:14]\n input io_status_cease,\t// @[execution-unit.scala:104:14]\n input io_status_wfi,\t// @[execution-unit.scala:104:14]\n input [1:0] io_status_dprv,\t// @[execution-unit.scala:104:14]\n input io_status_dv,\t// @[execution-unit.scala:104:14]\n input [1:0] io_status_prv,\t// @[execution-unit.scala:104:14]\n input io_status_v,\t// @[execution-unit.scala:104:14]\n input io_status_sd,\t// @[execution-unit.scala:104:14]\n input io_status_mpv,\t// @[execution-unit.scala:104:14]\n input io_status_gva,\t// @[execution-unit.scala:104:14]\n input io_status_tsr,\t// @[execution-unit.scala:104:14]\n input io_status_tw,\t// @[execution-unit.scala:104:14]\n input io_status_tvm,\t// @[execution-unit.scala:104:14]\n input io_status_mxr,\t// @[execution-unit.scala:104:14]\n input io_status_sum,\t// @[execution-unit.scala:104:14]\n input io_status_mprv,\t// @[execution-unit.scala:104:14]\n input [1:0] io_status_fs,\t// @[execution-unit.scala:104:14]\n input [1:0] io_status_mpp,\t// @[execution-unit.scala:104:14]\n input io_status_spp,\t// @[execution-unit.scala:104:14]\n input io_status_mpie,\t// @[execution-unit.scala:104:14]\n input io_status_spie,\t// @[execution-unit.scala:104:14]\n input io_status_mie,\t// @[execution-unit.scala:104:14]\n input io_status_sie,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_valid,\t// @[execution-unit.scala:104:14]\n output [6:0] io_lsu_io_req_bits_uop_uopc,\t// @[execution-unit.scala:104:14]\n output [31:0] io_lsu_io_req_bits_uop_inst,\t// @[execution-unit.scala:104:14]\n output [31:0] io_lsu_io_req_bits_uop_debug_inst,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_is_rvc,\t// @[execution-unit.scala:104:14]\n output [39:0] io_lsu_io_req_bits_uop_debug_pc,\t// @[execution-unit.scala:104:14]\n output [2:0] io_lsu_io_req_bits_uop_iq_type,\t// @[execution-unit.scala:104:14]\n output [9:0] io_lsu_io_req_bits_uop_fu_code,\t// @[execution-unit.scala:104:14]\n output [3:0] io_lsu_io_req_bits_uop_ctrl_br_type,\t// @[execution-unit.scala:104:14]\n output [1:0] io_lsu_io_req_bits_uop_ctrl_op1_sel,\t// @[execution-unit.scala:104:14]\n output [2:0] io_lsu_io_req_bits_uop_ctrl_op2_sel,\t// @[execution-unit.scala:104:14]\n output [2:0] io_lsu_io_req_bits_uop_ctrl_imm_sel,\t// @[execution-unit.scala:104:14]\n output [4:0] io_lsu_io_req_bits_uop_ctrl_op_fcn,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_ctrl_fcn_dw,\t// @[execution-unit.scala:104:14]\n output [2:0] io_lsu_io_req_bits_uop_ctrl_csr_cmd,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_ctrl_is_load,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_ctrl_is_sta,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_ctrl_is_std,\t// @[execution-unit.scala:104:14]\n output [1:0] io_lsu_io_req_bits_uop_iw_state,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_iw_p1_poisoned,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_iw_p2_poisoned,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_is_br,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_is_jalr,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_is_jal,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_is_sfb,\t// @[execution-unit.scala:104:14]\n output [7:0] io_lsu_io_req_bits_uop_br_mask,\t// @[execution-unit.scala:104:14]\n output [2:0] io_lsu_io_req_bits_uop_br_tag,\t// @[execution-unit.scala:104:14]\n output [3:0] io_lsu_io_req_bits_uop_ftq_idx,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_edge_inst,\t// @[execution-unit.scala:104:14]\n output [5:0] io_lsu_io_req_bits_uop_pc_lob,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_taken,\t// @[execution-unit.scala:104:14]\n output [19:0] io_lsu_io_req_bits_uop_imm_packed,\t// @[execution-unit.scala:104:14]\n output [11:0] io_lsu_io_req_bits_uop_csr_addr,\t// @[execution-unit.scala:104:14]\n output [4:0] io_lsu_io_req_bits_uop_rob_idx,\t// @[execution-unit.scala:104:14]\n output [2:0] io_lsu_io_req_bits_uop_ldq_idx,\t// @[execution-unit.scala:104:14]\n output [2:0] io_lsu_io_req_bits_uop_stq_idx,\t// @[execution-unit.scala:104:14]\n output [1:0] io_lsu_io_req_bits_uop_rxq_idx,\t// @[execution-unit.scala:104:14]\n output [5:0] io_lsu_io_req_bits_uop_pdst,\t// @[execution-unit.scala:104:14]\n output [5:0] io_lsu_io_req_bits_uop_prs1,\t// @[execution-unit.scala:104:14]\n output [5:0] io_lsu_io_req_bits_uop_prs2,\t// @[execution-unit.scala:104:14]\n output [5:0] io_lsu_io_req_bits_uop_prs3,\t// @[execution-unit.scala:104:14]\n output [3:0] io_lsu_io_req_bits_uop_ppred,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_prs1_busy,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_prs2_busy,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_prs3_busy,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_ppred_busy,\t// @[execution-unit.scala:104:14]\n output [5:0] io_lsu_io_req_bits_uop_stale_pdst,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_exception,\t// @[execution-unit.scala:104:14]\n output [63:0] io_lsu_io_req_bits_uop_exc_cause,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_bypassable,\t// @[execution-unit.scala:104:14]\n output [4:0] io_lsu_io_req_bits_uop_mem_cmd,\t// @[execution-unit.scala:104:14]\n output [1:0] io_lsu_io_req_bits_uop_mem_size,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_mem_signed,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_is_fence,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_is_fencei,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_is_amo,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_uses_ldq,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_uses_stq,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_is_sys_pc2epc,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_is_unique,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_flush_on_commit,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_ldst_is_rs1,\t// @[execution-unit.scala:104:14]\n output [5:0] io_lsu_io_req_bits_uop_ldst,\t// @[execution-unit.scala:104:14]\n output [5:0] io_lsu_io_req_bits_uop_lrs1,\t// @[execution-unit.scala:104:14]\n output [5:0] io_lsu_io_req_bits_uop_lrs2,\t// @[execution-unit.scala:104:14]\n output [5:0] io_lsu_io_req_bits_uop_lrs3,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_ldst_val,\t// @[execution-unit.scala:104:14]\n output [1:0] io_lsu_io_req_bits_uop_dst_rtype,\t// @[execution-unit.scala:104:14]\n output [1:0] io_lsu_io_req_bits_uop_lrs1_rtype,\t// @[execution-unit.scala:104:14]\n output [1:0] io_lsu_io_req_bits_uop_lrs2_rtype,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_frs3_en,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_fp_val,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_fp_single,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_xcpt_pf_if,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_xcpt_ae_if,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_xcpt_ma_if,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_bp_debug_if,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_uop_bp_xcpt_if,\t// @[execution-unit.scala:104:14]\n output [1:0] io_lsu_io_req_bits_uop_debug_fsrc,\t// @[execution-unit.scala:104:14]\n output [1:0] io_lsu_io_req_bits_uop_debug_tsrc,\t// @[execution-unit.scala:104:14]\n output [63:0] io_lsu_io_req_bits_data,\t// @[execution-unit.scala:104:14]\n output [39:0] io_lsu_io_req_bits_addr,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_mxcpt_valid,\t// @[execution-unit.scala:104:14]\n output [24:0] io_lsu_io_req_bits_mxcpt_bits,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_sfence_valid,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_sfence_bits_rs1,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_sfence_bits_rs2,\t// @[execution-unit.scala:104:14]\n output [38:0] io_lsu_io_req_bits_sfence_bits_addr,\t// @[execution-unit.scala:104:14]\n output io_lsu_io_req_bits_sfence_bits_asid,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_valid,\t// @[execution-unit.scala:104:14]\n input [6:0] io_lsu_io_iresp_bits_uop_uopc,\t// @[execution-unit.scala:104:14]\n input [31:0] io_lsu_io_iresp_bits_uop_inst,\t// @[execution-unit.scala:104:14]\n input [31:0] io_lsu_io_iresp_bits_uop_debug_inst,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_is_rvc,\t// @[execution-unit.scala:104:14]\n input [39:0] io_lsu_io_iresp_bits_uop_debug_pc,\t// @[execution-unit.scala:104:14]\n input [2:0] io_lsu_io_iresp_bits_uop_iq_type,\t// @[execution-unit.scala:104:14]\n input [9:0] io_lsu_io_iresp_bits_uop_fu_code,\t// @[execution-unit.scala:104:14]\n input [3:0] io_lsu_io_iresp_bits_uop_ctrl_br_type,\t// @[execution-unit.scala:104:14]\n input [1:0] io_lsu_io_iresp_bits_uop_ctrl_op1_sel,\t// @[execution-unit.scala:104:14]\n input [2:0] io_lsu_io_iresp_bits_uop_ctrl_op2_sel,\t// @[execution-unit.scala:104:14]\n input [2:0] io_lsu_io_iresp_bits_uop_ctrl_imm_sel,\t// @[execution-unit.scala:104:14]\n input [4:0] io_lsu_io_iresp_bits_uop_ctrl_op_fcn,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_ctrl_fcn_dw,\t// @[execution-unit.scala:104:14]\n input [2:0] io_lsu_io_iresp_bits_uop_ctrl_csr_cmd,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_ctrl_is_load,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_ctrl_is_sta,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_ctrl_is_std,\t// @[execution-unit.scala:104:14]\n input [1:0] io_lsu_io_iresp_bits_uop_iw_state,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_iw_p1_poisoned,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_iw_p2_poisoned,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_is_br,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_is_jalr,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_is_jal,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_is_sfb,\t// @[execution-unit.scala:104:14]\n input [7:0] io_lsu_io_iresp_bits_uop_br_mask,\t// @[execution-unit.scala:104:14]\n input [2:0] io_lsu_io_iresp_bits_uop_br_tag,\t// @[execution-unit.scala:104:14]\n input [3:0] io_lsu_io_iresp_bits_uop_ftq_idx,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_edge_inst,\t// @[execution-unit.scala:104:14]\n input [5:0] io_lsu_io_iresp_bits_uop_pc_lob,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_taken,\t// @[execution-unit.scala:104:14]\n input [19:0] io_lsu_io_iresp_bits_uop_imm_packed,\t// @[execution-unit.scala:104:14]\n input [11:0] io_lsu_io_iresp_bits_uop_csr_addr,\t// @[execution-unit.scala:104:14]\n input [4:0] io_lsu_io_iresp_bits_uop_rob_idx,\t// @[execution-unit.scala:104:14]\n input [2:0] io_lsu_io_iresp_bits_uop_ldq_idx,\t// @[execution-unit.scala:104:14]\n input [2:0] io_lsu_io_iresp_bits_uop_stq_idx,\t// @[execution-unit.scala:104:14]\n input [1:0] io_lsu_io_iresp_bits_uop_rxq_idx,\t// @[execution-unit.scala:104:14]\n input [5:0] io_lsu_io_iresp_bits_uop_pdst,\t// @[execution-unit.scala:104:14]\n input [5:0] io_lsu_io_iresp_bits_uop_prs1,\t// @[execution-unit.scala:104:14]\n input [5:0] io_lsu_io_iresp_bits_uop_prs2,\t// @[execution-unit.scala:104:14]\n input [5:0] io_lsu_io_iresp_bits_uop_prs3,\t// @[execution-unit.scala:104:14]\n input [3:0] io_lsu_io_iresp_bits_uop_ppred,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_prs1_busy,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_prs2_busy,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_prs3_busy,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_ppred_busy,\t// @[execution-unit.scala:104:14]\n input [5:0] io_lsu_io_iresp_bits_uop_stale_pdst,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_exception,\t// @[execution-unit.scala:104:14]\n input [63:0] io_lsu_io_iresp_bits_uop_exc_cause,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_bypassable,\t// @[execution-unit.scala:104:14]\n input [4:0] io_lsu_io_iresp_bits_uop_mem_cmd,\t// @[execution-unit.scala:104:14]\n input [1:0] io_lsu_io_iresp_bits_uop_mem_size,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_mem_signed,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_is_fence,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_is_fencei,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_is_amo,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_uses_ldq,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_uses_stq,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_is_sys_pc2epc,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_is_unique,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_flush_on_commit,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_ldst_is_rs1,\t// @[execution-unit.scala:104:14]\n input [5:0] io_lsu_io_iresp_bits_uop_ldst,\t// @[execution-unit.scala:104:14]\n input [5:0] io_lsu_io_iresp_bits_uop_lrs1,\t// @[execution-unit.scala:104:14]\n input [5:0] io_lsu_io_iresp_bits_uop_lrs2,\t// @[execution-unit.scala:104:14]\n input [5:0] io_lsu_io_iresp_bits_uop_lrs3,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_ldst_val,\t// @[execution-unit.scala:104:14]\n input [1:0] io_lsu_io_iresp_bits_uop_dst_rtype,\t// @[execution-unit.scala:104:14]\n input [1:0] io_lsu_io_iresp_bits_uop_lrs1_rtype,\t// @[execution-unit.scala:104:14]\n input [1:0] io_lsu_io_iresp_bits_uop_lrs2_rtype,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_frs3_en,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_fp_val,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_fp_single,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_xcpt_pf_if,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_xcpt_ae_if,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_xcpt_ma_if,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_bp_debug_if,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_iresp_bits_uop_bp_xcpt_if,\t// @[execution-unit.scala:104:14]\n input [1:0] io_lsu_io_iresp_bits_uop_debug_fsrc,\t// @[execution-unit.scala:104:14]\n input [1:0] io_lsu_io_iresp_bits_uop_debug_tsrc,\t// @[execution-unit.scala:104:14]\n input [63:0] io_lsu_io_iresp_bits_data,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_valid,\t// @[execution-unit.scala:104:14]\n input [6:0] io_lsu_io_fresp_bits_uop_uopc,\t// @[execution-unit.scala:104:14]\n input [31:0] io_lsu_io_fresp_bits_uop_inst,\t// @[execution-unit.scala:104:14]\n input [31:0] io_lsu_io_fresp_bits_uop_debug_inst,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_is_rvc,\t// @[execution-unit.scala:104:14]\n input [39:0] io_lsu_io_fresp_bits_uop_debug_pc,\t// @[execution-unit.scala:104:14]\n input [2:0] io_lsu_io_fresp_bits_uop_iq_type,\t// @[execution-unit.scala:104:14]\n input [9:0] io_lsu_io_fresp_bits_uop_fu_code,\t// @[execution-unit.scala:104:14]\n input [3:0] io_lsu_io_fresp_bits_uop_ctrl_br_type,\t// @[execution-unit.scala:104:14]\n input [1:0] io_lsu_io_fresp_bits_uop_ctrl_op1_sel,\t// @[execution-unit.scala:104:14]\n input [2:0] io_lsu_io_fresp_bits_uop_ctrl_op2_sel,\t// @[execution-unit.scala:104:14]\n input [2:0] io_lsu_io_fresp_bits_uop_ctrl_imm_sel,\t// @[execution-unit.scala:104:14]\n input [4:0] io_lsu_io_fresp_bits_uop_ctrl_op_fcn,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_ctrl_fcn_dw,\t// @[execution-unit.scala:104:14]\n input [2:0] io_lsu_io_fresp_bits_uop_ctrl_csr_cmd,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_ctrl_is_load,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_ctrl_is_sta,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_ctrl_is_std,\t// @[execution-unit.scala:104:14]\n input [1:0] io_lsu_io_fresp_bits_uop_iw_state,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_iw_p1_poisoned,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_iw_p2_poisoned,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_is_br,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_is_jalr,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_is_jal,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_is_sfb,\t// @[execution-unit.scala:104:14]\n input [7:0] io_lsu_io_fresp_bits_uop_br_mask,\t// @[execution-unit.scala:104:14]\n input [2:0] io_lsu_io_fresp_bits_uop_br_tag,\t// @[execution-unit.scala:104:14]\n input [3:0] io_lsu_io_fresp_bits_uop_ftq_idx,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_edge_inst,\t// @[execution-unit.scala:104:14]\n input [5:0] io_lsu_io_fresp_bits_uop_pc_lob,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_taken,\t// @[execution-unit.scala:104:14]\n input [19:0] io_lsu_io_fresp_bits_uop_imm_packed,\t// @[execution-unit.scala:104:14]\n input [11:0] io_lsu_io_fresp_bits_uop_csr_addr,\t// @[execution-unit.scala:104:14]\n input [4:0] io_lsu_io_fresp_bits_uop_rob_idx,\t// @[execution-unit.scala:104:14]\n input [2:0] io_lsu_io_fresp_bits_uop_ldq_idx,\t// @[execution-unit.scala:104:14]\n input [2:0] io_lsu_io_fresp_bits_uop_stq_idx,\t// @[execution-unit.scala:104:14]\n input [1:0] io_lsu_io_fresp_bits_uop_rxq_idx,\t// @[execution-unit.scala:104:14]\n input [5:0] io_lsu_io_fresp_bits_uop_pdst,\t// @[execution-unit.scala:104:14]\n input [5:0] io_lsu_io_fresp_bits_uop_prs1,\t// @[execution-unit.scala:104:14]\n input [5:0] io_lsu_io_fresp_bits_uop_prs2,\t// @[execution-unit.scala:104:14]\n input [5:0] io_lsu_io_fresp_bits_uop_prs3,\t// @[execution-unit.scala:104:14]\n input [3:0] io_lsu_io_fresp_bits_uop_ppred,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_prs1_busy,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_prs2_busy,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_prs3_busy,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_ppred_busy,\t// @[execution-unit.scala:104:14]\n input [5:0] io_lsu_io_fresp_bits_uop_stale_pdst,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_exception,\t// @[execution-unit.scala:104:14]\n input [63:0] io_lsu_io_fresp_bits_uop_exc_cause,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_bypassable,\t// @[execution-unit.scala:104:14]\n input [4:0] io_lsu_io_fresp_bits_uop_mem_cmd,\t// @[execution-unit.scala:104:14]\n input [1:0] io_lsu_io_fresp_bits_uop_mem_size,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_mem_signed,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_is_fence,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_is_fencei,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_is_amo,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_uses_ldq,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_uses_stq,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_is_sys_pc2epc,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_is_unique,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_flush_on_commit,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_ldst_is_rs1,\t// @[execution-unit.scala:104:14]\n input [5:0] io_lsu_io_fresp_bits_uop_ldst,\t// @[execution-unit.scala:104:14]\n input [5:0] io_lsu_io_fresp_bits_uop_lrs1,\t// @[execution-unit.scala:104:14]\n input [5:0] io_lsu_io_fresp_bits_uop_lrs2,\t// @[execution-unit.scala:104:14]\n input [5:0] io_lsu_io_fresp_bits_uop_lrs3,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_ldst_val,\t// @[execution-unit.scala:104:14]\n input [1:0] io_lsu_io_fresp_bits_uop_dst_rtype,\t// @[execution-unit.scala:104:14]\n input [1:0] io_lsu_io_fresp_bits_uop_lrs1_rtype,\t// @[execution-unit.scala:104:14]\n input [1:0] io_lsu_io_fresp_bits_uop_lrs2_rtype,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_frs3_en,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_fp_val,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_fp_single,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_xcpt_pf_if,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_xcpt_ae_if,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_xcpt_ma_if,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_bp_debug_if,\t// @[execution-unit.scala:104:14]\n input io_lsu_io_fresp_bits_uop_bp_xcpt_if,\t// @[execution-unit.scala:104:14]\n input [1:0] io_lsu_io_fresp_bits_uop_debug_fsrc,\t// @[execution-unit.scala:104:14]\n input [1:0] io_lsu_io_fresp_bits_uop_debug_tsrc,\t// @[execution-unit.scala:104:14]\n input [64:0] io_lsu_io_fresp_bits_data,\t// @[execution-unit.scala:104:14]\n input io_com_exception\t// @[execution-unit.scala:104:14]\n);\n\n wire [64:0] _maddrcalc_io_resp_bits_data;\t// @[execution-unit.scala:388:27]\n wire io_req_valid_0 = io_req_valid;\t// @[execution-unit.scala:204:7]\n wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc;\t// @[execution-unit.scala:204:7]\n wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst;\t// @[execution-unit.scala:204:7]\n wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc;\t// @[execution-unit.scala:204:7]\n wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type;\t// @[execution-unit.scala:204:7]\n wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code;\t// @[execution-unit.scala:204:7]\n wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel;\t// @[execution-unit.scala:204:7]\n wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb;\t// @[execution-unit.scala:204:7]\n wire [7:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag;\t// @[execution-unit.scala:204:7]\n wire [3:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken;\t// @[execution-unit.scala:204:7]\n wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed;\t// @[execution-unit.scala:204:7]\n wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr;\t// @[execution-unit.scala:204:7]\n wire [4:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3;\t// @[execution-unit.scala:204:7]\n wire [3:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception;\t// @[execution-unit.scala:204:7]\n wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable;\t// @[execution-unit.scala:204:7]\n wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc;\t// @[execution-unit.scala:204:7]\n wire [64:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data;\t// @[execution-unit.scala:204:7]\n wire [64:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_kill_0 = io_req_bits_kill;\t// @[execution-unit.scala:204:7]\n wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask;\t// @[execution-unit.scala:204:7]\n wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask;\t// @[execution-unit.scala:204:7]\n wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc;\t// @[execution-unit.scala:204:7]\n wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst;\t// @[execution-unit.scala:204:7]\n wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc;\t// @[execution-unit.scala:204:7]\n wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type;\t// @[execution-unit.scala:204:7]\n wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code;\t// @[execution-unit.scala:204:7]\n wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel;\t// @[execution-unit.scala:204:7]\n wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb;\t// @[execution-unit.scala:204:7]\n wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag;\t// @[execution-unit.scala:204:7]\n wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken;\t// @[execution-unit.scala:204:7]\n wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed;\t// @[execution-unit.scala:204:7]\n wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr;\t// @[execution-unit.scala:204:7]\n wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3;\t// @[execution-unit.scala:204:7]\n wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception;\t// @[execution-unit.scala:204:7]\n wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable;\t// @[execution-unit.scala:204:7]\n wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict;\t// @[execution-unit.scala:204:7]\n wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel;\t// @[execution-unit.scala:204:7]\n wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target;\t// @[execution-unit.scala:204:7]\n wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset;\t// @[execution-unit.scala:204:7]\n wire io_status_debug_0 = io_status_debug;\t// @[execution-unit.scala:204:7]\n wire io_status_cease_0 = io_status_cease;\t// @[execution-unit.scala:204:7]\n wire io_status_wfi_0 = io_status_wfi;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_status_dprv_0 = io_status_dprv;\t// @[execution-unit.scala:204:7]\n wire io_status_dv_0 = io_status_dv;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_status_prv_0 = io_status_prv;\t// @[execution-unit.scala:204:7]\n wire io_status_v_0 = io_status_v;\t// @[execution-unit.scala:204:7]\n wire io_status_sd_0 = io_status_sd;\t// @[execution-unit.scala:204:7]\n wire io_status_mpv_0 = io_status_mpv;\t// @[execution-unit.scala:204:7]\n wire io_status_gva_0 = io_status_gva;\t// @[execution-unit.scala:204:7]\n wire io_status_tsr_0 = io_status_tsr;\t// @[execution-unit.scala:204:7]\n wire io_status_tw_0 = io_status_tw;\t// @[execution-unit.scala:204:7]\n wire io_status_tvm_0 = io_status_tvm;\t// @[execution-unit.scala:204:7]\n wire io_status_mxr_0 = io_status_mxr;\t// @[execution-unit.scala:204:7]\n wire io_status_sum_0 = io_status_sum;\t// @[execution-unit.scala:204:7]\n wire io_status_mprv_0 = io_status_mprv;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_status_fs_0 = io_status_fs;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_status_mpp_0 = io_status_mpp;\t// @[execution-unit.scala:204:7]\n wire io_status_spp_0 = io_status_spp;\t// @[execution-unit.scala:204:7]\n wire io_status_mpie_0 = io_status_mpie;\t// @[execution-unit.scala:204:7]\n wire io_status_spie_0 = io_status_spie;\t// @[execution-unit.scala:204:7]\n wire io_status_mie_0 = io_status_mie;\t// @[execution-unit.scala:204:7]\n wire io_status_sie_0 = io_status_sie;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_valid_0 = io_lsu_io_iresp_valid;\t// @[execution-unit.scala:204:7]\n wire [6:0] io_lsu_io_iresp_bits_uop_uopc_0 = io_lsu_io_iresp_bits_uop_uopc;\t// @[execution-unit.scala:204:7]\n wire [31:0] io_lsu_io_iresp_bits_uop_inst_0 = io_lsu_io_iresp_bits_uop_inst;\t// @[execution-unit.scala:204:7]\n wire [31:0] io_lsu_io_iresp_bits_uop_debug_inst_0 = io_lsu_io_iresp_bits_uop_debug_inst;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_is_rvc_0 = io_lsu_io_iresp_bits_uop_is_rvc;\t// @[execution-unit.scala:204:7]\n wire [39:0] io_lsu_io_iresp_bits_uop_debug_pc_0 = io_lsu_io_iresp_bits_uop_debug_pc;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_lsu_io_iresp_bits_uop_iq_type_0 = io_lsu_io_iresp_bits_uop_iq_type;\t// @[execution-unit.scala:204:7]\n wire [9:0] io_lsu_io_iresp_bits_uop_fu_code_0 = io_lsu_io_iresp_bits_uop_fu_code;\t// @[execution-unit.scala:204:7]\n wire [3:0] io_lsu_io_iresp_bits_uop_ctrl_br_type_0 = io_lsu_io_iresp_bits_uop_ctrl_br_type;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_iresp_bits_uop_ctrl_op1_sel_0 = io_lsu_io_iresp_bits_uop_ctrl_op1_sel;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_lsu_io_iresp_bits_uop_ctrl_op2_sel_0 = io_lsu_io_iresp_bits_uop_ctrl_op2_sel;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_lsu_io_iresp_bits_uop_ctrl_imm_sel_0 = io_lsu_io_iresp_bits_uop_ctrl_imm_sel;\t// @[execution-unit.scala:204:7]\n wire [4:0] io_lsu_io_iresp_bits_uop_ctrl_op_fcn_0 = io_lsu_io_iresp_bits_uop_ctrl_op_fcn;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_ctrl_fcn_dw_0 = io_lsu_io_iresp_bits_uop_ctrl_fcn_dw;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_lsu_io_iresp_bits_uop_ctrl_csr_cmd_0 = io_lsu_io_iresp_bits_uop_ctrl_csr_cmd;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_ctrl_is_load_0 = io_lsu_io_iresp_bits_uop_ctrl_is_load;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_ctrl_is_sta_0 = io_lsu_io_iresp_bits_uop_ctrl_is_sta;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_ctrl_is_std_0 = io_lsu_io_iresp_bits_uop_ctrl_is_std;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_iresp_bits_uop_iw_state_0 = io_lsu_io_iresp_bits_uop_iw_state;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_iw_p1_poisoned_0 = io_lsu_io_iresp_bits_uop_iw_p1_poisoned;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_iw_p2_poisoned_0 = io_lsu_io_iresp_bits_uop_iw_p2_poisoned;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_is_br_0 = io_lsu_io_iresp_bits_uop_is_br;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_is_jalr_0 = io_lsu_io_iresp_bits_uop_is_jalr;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_is_jal_0 = io_lsu_io_iresp_bits_uop_is_jal;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_is_sfb_0 = io_lsu_io_iresp_bits_uop_is_sfb;\t// @[execution-unit.scala:204:7]\n wire [7:0] io_lsu_io_iresp_bits_uop_br_mask_0 = io_lsu_io_iresp_bits_uop_br_mask;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_lsu_io_iresp_bits_uop_br_tag_0 = io_lsu_io_iresp_bits_uop_br_tag;\t// @[execution-unit.scala:204:7]\n wire [3:0] io_lsu_io_iresp_bits_uop_ftq_idx_0 = io_lsu_io_iresp_bits_uop_ftq_idx;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_edge_inst_0 = io_lsu_io_iresp_bits_uop_edge_inst;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_lsu_io_iresp_bits_uop_pc_lob_0 = io_lsu_io_iresp_bits_uop_pc_lob;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_taken_0 = io_lsu_io_iresp_bits_uop_taken;\t// @[execution-unit.scala:204:7]\n wire [19:0] io_lsu_io_iresp_bits_uop_imm_packed_0 = io_lsu_io_iresp_bits_uop_imm_packed;\t// @[execution-unit.scala:204:7]\n wire [11:0] io_lsu_io_iresp_bits_uop_csr_addr_0 = io_lsu_io_iresp_bits_uop_csr_addr;\t// @[execution-unit.scala:204:7]\n wire [4:0] io_lsu_io_iresp_bits_uop_rob_idx_0 = io_lsu_io_iresp_bits_uop_rob_idx;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_lsu_io_iresp_bits_uop_ldq_idx_0 = io_lsu_io_iresp_bits_uop_ldq_idx;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_lsu_io_iresp_bits_uop_stq_idx_0 = io_lsu_io_iresp_bits_uop_stq_idx;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_iresp_bits_uop_rxq_idx_0 = io_lsu_io_iresp_bits_uop_rxq_idx;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_lsu_io_iresp_bits_uop_pdst_0 = io_lsu_io_iresp_bits_uop_pdst;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_lsu_io_iresp_bits_uop_prs1_0 = io_lsu_io_iresp_bits_uop_prs1;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_lsu_io_iresp_bits_uop_prs2_0 = io_lsu_io_iresp_bits_uop_prs2;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_lsu_io_iresp_bits_uop_prs3_0 = io_lsu_io_iresp_bits_uop_prs3;\t// @[execution-unit.scala:204:7]\n wire [3:0] io_lsu_io_iresp_bits_uop_ppred_0 = io_lsu_io_iresp_bits_uop_ppred;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_prs1_busy_0 = io_lsu_io_iresp_bits_uop_prs1_busy;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_prs2_busy_0 = io_lsu_io_iresp_bits_uop_prs2_busy;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_prs3_busy_0 = io_lsu_io_iresp_bits_uop_prs3_busy;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_ppred_busy_0 = io_lsu_io_iresp_bits_uop_ppred_busy;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_lsu_io_iresp_bits_uop_stale_pdst_0 = io_lsu_io_iresp_bits_uop_stale_pdst;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_exception_0 = io_lsu_io_iresp_bits_uop_exception;\t// @[execution-unit.scala:204:7]\n wire [63:0] io_lsu_io_iresp_bits_uop_exc_cause_0 = io_lsu_io_iresp_bits_uop_exc_cause;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_bypassable_0 = io_lsu_io_iresp_bits_uop_bypassable;\t// @[execution-unit.scala:204:7]\n wire [4:0] io_lsu_io_iresp_bits_uop_mem_cmd_0 = io_lsu_io_iresp_bits_uop_mem_cmd;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_iresp_bits_uop_mem_size_0 = io_lsu_io_iresp_bits_uop_mem_size;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_mem_signed_0 = io_lsu_io_iresp_bits_uop_mem_signed;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_is_fence_0 = io_lsu_io_iresp_bits_uop_is_fence;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_is_fencei_0 = io_lsu_io_iresp_bits_uop_is_fencei;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_is_amo_0 = io_lsu_io_iresp_bits_uop_is_amo;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_uses_ldq_0 = io_lsu_io_iresp_bits_uop_uses_ldq;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_uses_stq_0 = io_lsu_io_iresp_bits_uop_uses_stq;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_is_sys_pc2epc_0 = io_lsu_io_iresp_bits_uop_is_sys_pc2epc;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_is_unique_0 = io_lsu_io_iresp_bits_uop_is_unique;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_flush_on_commit_0 = io_lsu_io_iresp_bits_uop_flush_on_commit;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_ldst_is_rs1_0 = io_lsu_io_iresp_bits_uop_ldst_is_rs1;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_lsu_io_iresp_bits_uop_ldst_0 = io_lsu_io_iresp_bits_uop_ldst;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_lsu_io_iresp_bits_uop_lrs1_0 = io_lsu_io_iresp_bits_uop_lrs1;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_lsu_io_iresp_bits_uop_lrs2_0 = io_lsu_io_iresp_bits_uop_lrs2;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_lsu_io_iresp_bits_uop_lrs3_0 = io_lsu_io_iresp_bits_uop_lrs3;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_ldst_val_0 = io_lsu_io_iresp_bits_uop_ldst_val;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_iresp_bits_uop_dst_rtype_0 = io_lsu_io_iresp_bits_uop_dst_rtype;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_iresp_bits_uop_lrs1_rtype_0 = io_lsu_io_iresp_bits_uop_lrs1_rtype;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_iresp_bits_uop_lrs2_rtype_0 = io_lsu_io_iresp_bits_uop_lrs2_rtype;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_frs3_en_0 = io_lsu_io_iresp_bits_uop_frs3_en;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_fp_val_0 = io_lsu_io_iresp_bits_uop_fp_val;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_fp_single_0 = io_lsu_io_iresp_bits_uop_fp_single;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_xcpt_pf_if_0 = io_lsu_io_iresp_bits_uop_xcpt_pf_if;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_xcpt_ae_if_0 = io_lsu_io_iresp_bits_uop_xcpt_ae_if;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_xcpt_ma_if_0 = io_lsu_io_iresp_bits_uop_xcpt_ma_if;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_bp_debug_if_0 = io_lsu_io_iresp_bits_uop_bp_debug_if;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_uop_bp_xcpt_if_0 = io_lsu_io_iresp_bits_uop_bp_xcpt_if;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_iresp_bits_uop_debug_fsrc_0 = io_lsu_io_iresp_bits_uop_debug_fsrc;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_iresp_bits_uop_debug_tsrc_0 = io_lsu_io_iresp_bits_uop_debug_tsrc;\t// @[execution-unit.scala:204:7]\n wire [63:0] io_lsu_io_iresp_bits_data_0 = io_lsu_io_iresp_bits_data;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_valid_0 = io_lsu_io_fresp_valid;\t// @[execution-unit.scala:204:7]\n wire [6:0] io_lsu_io_fresp_bits_uop_uopc_0 = io_lsu_io_fresp_bits_uop_uopc;\t// @[execution-unit.scala:204:7]\n wire [31:0] io_lsu_io_fresp_bits_uop_inst_0 = io_lsu_io_fresp_bits_uop_inst;\t// @[execution-unit.scala:204:7]\n wire [31:0] io_lsu_io_fresp_bits_uop_debug_inst_0 = io_lsu_io_fresp_bits_uop_debug_inst;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_is_rvc_0 = io_lsu_io_fresp_bits_uop_is_rvc;\t// @[execution-unit.scala:204:7]\n wire [39:0] io_lsu_io_fresp_bits_uop_debug_pc_0 = io_lsu_io_fresp_bits_uop_debug_pc;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_lsu_io_fresp_bits_uop_iq_type_0 = io_lsu_io_fresp_bits_uop_iq_type;\t// @[execution-unit.scala:204:7]\n wire [9:0] io_lsu_io_fresp_bits_uop_fu_code_0 = io_lsu_io_fresp_bits_uop_fu_code;\t// @[execution-unit.scala:204:7]\n wire [3:0] io_lsu_io_fresp_bits_uop_ctrl_br_type_0 = io_lsu_io_fresp_bits_uop_ctrl_br_type;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_fresp_bits_uop_ctrl_op1_sel_0 = io_lsu_io_fresp_bits_uop_ctrl_op1_sel;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_lsu_io_fresp_bits_uop_ctrl_op2_sel_0 = io_lsu_io_fresp_bits_uop_ctrl_op2_sel;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_lsu_io_fresp_bits_uop_ctrl_imm_sel_0 = io_lsu_io_fresp_bits_uop_ctrl_imm_sel;\t// @[execution-unit.scala:204:7]\n wire [4:0] io_lsu_io_fresp_bits_uop_ctrl_op_fcn_0 = io_lsu_io_fresp_bits_uop_ctrl_op_fcn;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_ctrl_fcn_dw_0 = io_lsu_io_fresp_bits_uop_ctrl_fcn_dw;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_lsu_io_fresp_bits_uop_ctrl_csr_cmd_0 = io_lsu_io_fresp_bits_uop_ctrl_csr_cmd;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_ctrl_is_load_0 = io_lsu_io_fresp_bits_uop_ctrl_is_load;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_ctrl_is_sta_0 = io_lsu_io_fresp_bits_uop_ctrl_is_sta;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_ctrl_is_std_0 = io_lsu_io_fresp_bits_uop_ctrl_is_std;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_fresp_bits_uop_iw_state_0 = io_lsu_io_fresp_bits_uop_iw_state;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_iw_p1_poisoned_0 = io_lsu_io_fresp_bits_uop_iw_p1_poisoned;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_iw_p2_poisoned_0 = io_lsu_io_fresp_bits_uop_iw_p2_poisoned;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_is_br_0 = io_lsu_io_fresp_bits_uop_is_br;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_is_jalr_0 = io_lsu_io_fresp_bits_uop_is_jalr;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_is_jal_0 = io_lsu_io_fresp_bits_uop_is_jal;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_is_sfb_0 = io_lsu_io_fresp_bits_uop_is_sfb;\t// @[execution-unit.scala:204:7]\n wire [7:0] io_lsu_io_fresp_bits_uop_br_mask_0 = io_lsu_io_fresp_bits_uop_br_mask;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_lsu_io_fresp_bits_uop_br_tag_0 = io_lsu_io_fresp_bits_uop_br_tag;\t// @[execution-unit.scala:204:7]\n wire [3:0] io_lsu_io_fresp_bits_uop_ftq_idx_0 = io_lsu_io_fresp_bits_uop_ftq_idx;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_edge_inst_0 = io_lsu_io_fresp_bits_uop_edge_inst;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_lsu_io_fresp_bits_uop_pc_lob_0 = io_lsu_io_fresp_bits_uop_pc_lob;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_taken_0 = io_lsu_io_fresp_bits_uop_taken;\t// @[execution-unit.scala:204:7]\n wire [19:0] io_lsu_io_fresp_bits_uop_imm_packed_0 = io_lsu_io_fresp_bits_uop_imm_packed;\t// @[execution-unit.scala:204:7]\n wire [11:0] io_lsu_io_fresp_bits_uop_csr_addr_0 = io_lsu_io_fresp_bits_uop_csr_addr;\t// @[execution-unit.scala:204:7]\n wire [4:0] io_lsu_io_fresp_bits_uop_rob_idx_0 = io_lsu_io_fresp_bits_uop_rob_idx;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_lsu_io_fresp_bits_uop_ldq_idx_0 = io_lsu_io_fresp_bits_uop_ldq_idx;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_lsu_io_fresp_bits_uop_stq_idx_0 = io_lsu_io_fresp_bits_uop_stq_idx;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_fresp_bits_uop_rxq_idx_0 = io_lsu_io_fresp_bits_uop_rxq_idx;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_lsu_io_fresp_bits_uop_pdst_0 = io_lsu_io_fresp_bits_uop_pdst;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_lsu_io_fresp_bits_uop_prs1_0 = io_lsu_io_fresp_bits_uop_prs1;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_lsu_io_fresp_bits_uop_prs2_0 = io_lsu_io_fresp_bits_uop_prs2;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_lsu_io_fresp_bits_uop_prs3_0 = io_lsu_io_fresp_bits_uop_prs3;\t// @[execution-unit.scala:204:7]\n wire [3:0] io_lsu_io_fresp_bits_uop_ppred_0 = io_lsu_io_fresp_bits_uop_ppred;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_prs1_busy_0 = io_lsu_io_fresp_bits_uop_prs1_busy;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_prs2_busy_0 = io_lsu_io_fresp_bits_uop_prs2_busy;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_prs3_busy_0 = io_lsu_io_fresp_bits_uop_prs3_busy;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_ppred_busy_0 = io_lsu_io_fresp_bits_uop_ppred_busy;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_lsu_io_fresp_bits_uop_stale_pdst_0 = io_lsu_io_fresp_bits_uop_stale_pdst;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_exception_0 = io_lsu_io_fresp_bits_uop_exception;\t// @[execution-unit.scala:204:7]\n wire [63:0] io_lsu_io_fresp_bits_uop_exc_cause_0 = io_lsu_io_fresp_bits_uop_exc_cause;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_bypassable_0 = io_lsu_io_fresp_bits_uop_bypassable;\t// @[execution-unit.scala:204:7]\n wire [4:0] io_lsu_io_fresp_bits_uop_mem_cmd_0 = io_lsu_io_fresp_bits_uop_mem_cmd;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_fresp_bits_uop_mem_size_0 = io_lsu_io_fresp_bits_uop_mem_size;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_mem_signed_0 = io_lsu_io_fresp_bits_uop_mem_signed;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_is_fence_0 = io_lsu_io_fresp_bits_uop_is_fence;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_is_fencei_0 = io_lsu_io_fresp_bits_uop_is_fencei;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_is_amo_0 = io_lsu_io_fresp_bits_uop_is_amo;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_uses_ldq_0 = io_lsu_io_fresp_bits_uop_uses_ldq;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_uses_stq_0 = io_lsu_io_fresp_bits_uop_uses_stq;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_is_sys_pc2epc_0 = io_lsu_io_fresp_bits_uop_is_sys_pc2epc;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_is_unique_0 = io_lsu_io_fresp_bits_uop_is_unique;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_flush_on_commit_0 = io_lsu_io_fresp_bits_uop_flush_on_commit;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_ldst_is_rs1_0 = io_lsu_io_fresp_bits_uop_ldst_is_rs1;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_lsu_io_fresp_bits_uop_ldst_0 = io_lsu_io_fresp_bits_uop_ldst;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_lsu_io_fresp_bits_uop_lrs1_0 = io_lsu_io_fresp_bits_uop_lrs1;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_lsu_io_fresp_bits_uop_lrs2_0 = io_lsu_io_fresp_bits_uop_lrs2;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_lsu_io_fresp_bits_uop_lrs3_0 = io_lsu_io_fresp_bits_uop_lrs3;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_ldst_val_0 = io_lsu_io_fresp_bits_uop_ldst_val;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_fresp_bits_uop_dst_rtype_0 = io_lsu_io_fresp_bits_uop_dst_rtype;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_fresp_bits_uop_lrs1_rtype_0 = io_lsu_io_fresp_bits_uop_lrs1_rtype;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_fresp_bits_uop_lrs2_rtype_0 = io_lsu_io_fresp_bits_uop_lrs2_rtype;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_frs3_en_0 = io_lsu_io_fresp_bits_uop_frs3_en;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_fp_val_0 = io_lsu_io_fresp_bits_uop_fp_val;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_fp_single_0 = io_lsu_io_fresp_bits_uop_fp_single;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_xcpt_pf_if_0 = io_lsu_io_fresp_bits_uop_xcpt_pf_if;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_xcpt_ae_if_0 = io_lsu_io_fresp_bits_uop_xcpt_ae_if;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_xcpt_ma_if_0 = io_lsu_io_fresp_bits_uop_xcpt_ma_if;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_bp_debug_if_0 = io_lsu_io_fresp_bits_uop_bp_debug_if;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_uop_bp_xcpt_if_0 = io_lsu_io_fresp_bits_uop_bp_xcpt_if;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_fresp_bits_uop_debug_fsrc_0 = io_lsu_io_fresp_bits_uop_debug_fsrc;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_fresp_bits_uop_debug_tsrc_0 = io_lsu_io_fresp_bits_uop_debug_tsrc;\t// @[execution-unit.scala:204:7]\n wire [64:0] io_lsu_io_fresp_bits_data_0 = io_lsu_io_fresp_bits_data;\t// @[execution-unit.scala:204:7]\n wire io_com_exception_0 = io_com_exception;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_status_sxl = 2'h2;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [1:0] io_status_uxl = 2'h2;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [63:0] io_ll_iresp_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [63:0] io_ll_fresp_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [63:0] io_lsu_io_req_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [63:0] io_lsu_io_iresp_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [63:0] io_lsu_io_fresp_bits_fflags_bits_uop_exc_cause = 64'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [11:0] io_ll_iresp_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [11:0] io_ll_fresp_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [11:0] io_lsu_io_req_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [11:0] io_lsu_io_iresp_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [11:0] io_lsu_io_fresp_bits_fflags_bits_uop_csr_addr = 12'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [19:0] io_ll_iresp_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [19:0] io_ll_fresp_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [19:0] io_lsu_io_req_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [19:0] io_lsu_io_iresp_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [19:0] io_lsu_io_fresp_bits_fflags_bits_uop_imm_packed = 20'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_ll_iresp_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_ll_iresp_bits_fflags_bits_uop_pdst = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_ll_iresp_bits_fflags_bits_uop_prs1 = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_ll_iresp_bits_fflags_bits_uop_prs2 = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_ll_iresp_bits_fflags_bits_uop_prs3 = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_ll_iresp_bits_fflags_bits_uop_stale_pdst = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_ll_iresp_bits_fflags_bits_uop_ldst = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_ll_iresp_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_ll_iresp_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_ll_iresp_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_ll_fresp_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_ll_fresp_bits_fflags_bits_uop_pdst = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_ll_fresp_bits_fflags_bits_uop_prs1 = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_ll_fresp_bits_fflags_bits_uop_prs2 = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_ll_fresp_bits_fflags_bits_uop_prs3 = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_ll_fresp_bits_fflags_bits_uop_stale_pdst = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_ll_fresp_bits_fflags_bits_uop_ldst = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_ll_fresp_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_ll_fresp_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_ll_fresp_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_lsu_io_req_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_lsu_io_req_bits_fflags_bits_uop_pdst = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_lsu_io_req_bits_fflags_bits_uop_prs1 = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_lsu_io_req_bits_fflags_bits_uop_prs2 = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_lsu_io_req_bits_fflags_bits_uop_prs3 = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_lsu_io_req_bits_fflags_bits_uop_stale_pdst = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_lsu_io_req_bits_fflags_bits_uop_ldst = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_lsu_io_req_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_lsu_io_req_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_lsu_io_req_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_lsu_io_iresp_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_lsu_io_iresp_bits_fflags_bits_uop_pdst = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_lsu_io_iresp_bits_fflags_bits_uop_prs1 = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_lsu_io_iresp_bits_fflags_bits_uop_prs2 = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_lsu_io_iresp_bits_fflags_bits_uop_prs3 = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_lsu_io_iresp_bits_fflags_bits_uop_stale_pdst = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_lsu_io_iresp_bits_fflags_bits_uop_ldst = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_lsu_io_iresp_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_lsu_io_iresp_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_lsu_io_iresp_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_lsu_io_fresp_bits_fflags_bits_uop_pc_lob = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_lsu_io_fresp_bits_fflags_bits_uop_pdst = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_lsu_io_fresp_bits_fflags_bits_uop_prs1 = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_lsu_io_fresp_bits_fflags_bits_uop_prs2 = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_lsu_io_fresp_bits_fflags_bits_uop_prs3 = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_lsu_io_fresp_bits_fflags_bits_uop_stale_pdst = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_lsu_io_fresp_bits_fflags_bits_uop_ldst = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_lsu_io_fresp_bits_fflags_bits_uop_lrs1 = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_lsu_io_fresp_bits_fflags_bits_uop_lrs2 = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [5:0] io_lsu_io_fresp_bits_fflags_bits_uop_lrs3 = 6'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [4:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [4:0] io_ll_iresp_bits_fflags_bits_uop_rob_idx = 5'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [4:0] io_ll_iresp_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [4:0] io_ll_iresp_bits_fflags_bits_flags = 5'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [4:0] io_ll_fresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [4:0] io_ll_fresp_bits_fflags_bits_uop_rob_idx = 5'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [4:0] io_ll_fresp_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [4:0] io_ll_fresp_bits_fflags_bits_flags = 5'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [4:0] io_lsu_io_req_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [4:0] io_lsu_io_req_bits_fflags_bits_uop_rob_idx = 5'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [4:0] io_lsu_io_req_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [4:0] io_lsu_io_req_bits_fflags_bits_flags = 5'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [4:0] io_lsu_io_iresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [4:0] io_lsu_io_iresp_bits_fflags_bits_uop_rob_idx = 5'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [4:0] io_lsu_io_iresp_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [4:0] io_lsu_io_iresp_bits_fflags_bits_flags = 5'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [4:0] io_lsu_io_fresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [4:0] io_lsu_io_fresp_bits_fflags_bits_uop_rob_idx = 5'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [4:0] io_lsu_io_fresp_bits_fflags_bits_uop_mem_cmd = 5'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [4:0] io_lsu_io_fresp_bits_fflags_bits_flags = 5'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [3:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [3:0] io_ll_iresp_bits_fflags_bits_uop_ftq_idx = 4'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [3:0] io_ll_iresp_bits_fflags_bits_uop_ppred = 4'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [3:0] io_ll_fresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [3:0] io_ll_fresp_bits_fflags_bits_uop_ftq_idx = 4'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [3:0] io_ll_fresp_bits_fflags_bits_uop_ppred = 4'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [3:0] io_lsu_io_req_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [3:0] io_lsu_io_req_bits_fflags_bits_uop_ftq_idx = 4'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [3:0] io_lsu_io_req_bits_fflags_bits_uop_ppred = 4'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [3:0] io_lsu_io_iresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [3:0] io_lsu_io_iresp_bits_fflags_bits_uop_ftq_idx = 4'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [3:0] io_lsu_io_iresp_bits_fflags_bits_uop_ppred = 4'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [3:0] io_lsu_io_fresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [3:0] io_lsu_io_fresp_bits_fflags_bits_uop_ftq_idx = 4'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [3:0] io_lsu_io_fresp_bits_fflags_bits_uop_ppred = 4'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [9:0] io_ll_iresp_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[execution-unit.scala:204:7]\n wire [9:0] io_ll_fresp_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[execution-unit.scala:204:7]\n wire [9:0] io_lsu_io_req_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[execution-unit.scala:204:7]\n wire [9:0] io_lsu_io_iresp_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[execution-unit.scala:204:7]\n wire [9:0] io_lsu_io_fresp_bits_fflags_bits_uop_fu_code = 10'h0;\t// @[execution-unit.scala:204:7]\n wire [9:0] _io_fu_types_T = 10'h0;\t// @[execution-unit.scala:260:21]\n wire [9:0] _io_fu_types_T_1 = 10'h0;\t// @[execution-unit.scala:261:21]\n wire [9:0] _io_fu_types_T_2 = 10'h0;\t// @[execution-unit.scala:260:45]\n wire [9:0] _io_fu_types_T_5 = 10'h0;\t// @[execution-unit.scala:262:21]\n wire [9:0] _io_fu_types_T_6 = 10'h0;\t// @[execution-unit.scala:261:45]\n wire [9:0] _io_fu_types_T_7 = 10'h0;\t// @[execution-unit.scala:263:21]\n wire [9:0] _io_fu_types_T_8 = 10'h0;\t// @[execution-unit.scala:262:58]\n wire [9:0] _io_fu_types_T_9 = 10'h0;\t// @[execution-unit.scala:264:21]\n wire [9:0] _io_fu_types_T_10 = 10'h0;\t// @[execution-unit.scala:263:45]\n wire [9:0] _io_fu_types_T_13 = 10'h0;\t// @[execution-unit.scala:265:21]\n wire [9:0] _io_fu_types_T_14 = 10'h0;\t// @[execution-unit.scala:264:49]\n wire [2:0] io_ll_iresp_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_ll_iresp_bits_fflags_bits_uop_br_tag = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_ll_iresp_bits_fflags_bits_uop_ldq_idx = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_ll_iresp_bits_fflags_bits_uop_stq_idx = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_ll_fresp_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_ll_fresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_ll_fresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_ll_fresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_ll_fresp_bits_fflags_bits_uop_br_tag = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_ll_fresp_bits_fflags_bits_uop_ldq_idx = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_ll_fresp_bits_fflags_bits_uop_stq_idx = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_lsu_io_req_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_lsu_io_req_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_lsu_io_req_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_lsu_io_req_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_lsu_io_req_bits_fflags_bits_uop_br_tag = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_lsu_io_req_bits_fflags_bits_uop_ldq_idx = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_lsu_io_req_bits_fflags_bits_uop_stq_idx = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_lsu_io_iresp_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_lsu_io_iresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_lsu_io_iresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_lsu_io_iresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_lsu_io_iresp_bits_fflags_bits_uop_br_tag = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_lsu_io_iresp_bits_fflags_bits_uop_ldq_idx = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_lsu_io_iresp_bits_fflags_bits_uop_stq_idx = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_lsu_io_fresp_bits_fflags_bits_uop_iq_type = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_lsu_io_fresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_lsu_io_fresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_lsu_io_fresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_lsu_io_fresp_bits_fflags_bits_uop_br_tag = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_lsu_io_fresp_bits_fflags_bits_uop_ldq_idx = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [2:0] io_lsu_io_fresp_bits_fflags_bits_uop_stq_idx = 3'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [39:0] io_ll_iresp_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [39:0] io_ll_fresp_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [39:0] io_lsu_io_req_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [39:0] io_lsu_io_iresp_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [39:0] io_lsu_io_fresp_bits_fflags_bits_uop_debug_pc = 40'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [31:0] io_ll_iresp_bits_fflags_bits_uop_inst = 32'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [31:0] io_ll_iresp_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [31:0] io_ll_fresp_bits_fflags_bits_uop_inst = 32'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [31:0] io_ll_fresp_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [31:0] io_lsu_io_req_bits_fflags_bits_uop_inst = 32'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [31:0] io_lsu_io_req_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [31:0] io_lsu_io_iresp_bits_fflags_bits_uop_inst = 32'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [31:0] io_lsu_io_iresp_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [31:0] io_lsu_io_fresp_bits_fflags_bits_uop_inst = 32'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [31:0] io_lsu_io_fresp_bits_fflags_bits_uop_debug_inst = 32'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [6:0] io_ll_iresp_bits_fflags_bits_uop_uopc = 7'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [6:0] io_ll_fresp_bits_fflags_bits_uop_uopc = 7'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [6:0] io_lsu_io_req_bits_fflags_bits_uop_uopc = 7'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [6:0] io_lsu_io_iresp_bits_fflags_bits_uop_uopc = 7'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [6:0] io_lsu_io_fresp_bits_fflags_bits_uop_uopc = 7'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [64:0] io_req_bits_rs3_data = 65'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire io_req_ready = 1'h1;\t// @[execution-unit.scala:104:14, :204:7, :262:22, :265:22, :388:27, :425:83]\n wire io_ll_iresp_ready = 1'h1;\t// @[execution-unit.scala:104:14, :204:7, :262:22, :265:22, :388:27, :425:83]\n wire io_ll_fresp_ready = 1'h1;\t// @[execution-unit.scala:104:14, :204:7, :262:22, :265:22, :388:27, :425:83]\n wire io_lsu_io_iresp_ready = 1'h1;\t// @[execution-unit.scala:104:14, :204:7, :262:22, :265:22, :388:27, :425:83]\n wire io_lsu_io_fresp_ready = 1'h1;\t// @[execution-unit.scala:104:14, :204:7, :262:22, :265:22, :388:27, :425:83]\n wire _io_fu_types_T_3 = 1'h1;\t// @[execution-unit.scala:104:14, :204:7, :262:22, :265:22, :388:27, :425:83]\n wire _io_fu_types_T_11 = 1'h1;\t// @[execution-unit.scala:104:14, :204:7, :262:22, :265:22, :388:27, :425:83]\n wire [9:0] io_fu_types = 10'h4;\t// @[execution-unit.scala:204:7]\n wire [9:0] _io_fu_types_T_15 = 10'h4;\t// @[execution-unit.scala:266:21]\n wire [9:0] _io_fu_types_T_16 = 10'h4;\t// @[execution-unit.scala:265:60]\n wire [1:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_iresp_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_iresp_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_iresp_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_iresp_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_iresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_iresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_iresp_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_iresp_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_fresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_fresp_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_fresp_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_fresp_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_fresp_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_fresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_fresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_fresp_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_fresp_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_status_xs = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_status_vs = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_req_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_req_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_req_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_req_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_req_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_req_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_req_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_req_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_req_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_iresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_iresp_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_iresp_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_iresp_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_iresp_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_iresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_iresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_iresp_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_iresp_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_fresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_fresp_bits_fflags_bits_uop_iw_state = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_fresp_bits_fflags_bits_uop_rxq_idx = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_fresp_bits_fflags_bits_uop_mem_size = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_fresp_bits_fflags_bits_uop_dst_rtype = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_fresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_fresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_fresp_bits_fflags_bits_uop_debug_fsrc = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_fresp_bits_fflags_bits_uop_debug_tsrc = 2'h0;\t// @[execution-unit.scala:204:7]\n wire [7:0] io_ll_iresp_bits_fflags_bits_uop_br_mask = 8'h0;\t// @[execution-unit.scala:204:7]\n wire [7:0] io_ll_fresp_bits_fflags_bits_uop_br_mask = 8'h0;\t// @[execution-unit.scala:204:7]\n wire [7:0] io_status_zero1 = 8'h0;\t// @[execution-unit.scala:204:7]\n wire [7:0] io_lsu_io_req_bits_fflags_bits_uop_br_mask = 8'h0;\t// @[execution-unit.scala:204:7]\n wire [7:0] io_lsu_io_iresp_bits_fflags_bits_uop_br_mask = 8'h0;\t// @[execution-unit.scala:204:7]\n wire [7:0] io_lsu_io_fresp_bits_fflags_bits_uop_br_mask = 8'h0;\t// @[execution-unit.scala:204:7]\n wire io_req_bits_pred_data = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_predicated = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_valid = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_is_br = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_taken = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_exception = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_predicated = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_valid = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_is_br = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_taken = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_exception = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_status_mbe = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_status_sbe = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_status_sd_rv32 = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_status_ube = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_status_upie = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_status_hie = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_status_uie = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_predicated = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_valid = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_is_br = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_taken = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_exception = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_sfence_bits_hv = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_sfence_bits_hg = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_predicated = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_valid = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_is_br = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_taken = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_exception = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_iresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_predicated = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_valid = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_is_rvc = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_is_br = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_is_jalr = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_is_jal = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_is_sfb = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_edge_inst = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_taken = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_prs1_busy = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_prs2_busy = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_prs3_busy = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_ppred_busy = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_exception = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_bypassable = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_mem_signed = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_is_fence = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_is_fencei = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_is_amo = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_uses_ldq = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_uses_stq = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_is_unique = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_flush_on_commit = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_ldst_val = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_frs3_en = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_fp_val = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_fp_single = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_bp_debug_if = 1'h0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_fresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0;\t// @[execution-unit.scala:204:7]\n wire div_busy = 1'h0;\t// @[execution-unit.scala:253:27]\n wire ifpu_busy = 1'h0;\t// @[execution-unit.scala:254:27]\n wire _io_fu_types_T_4 = 1'h0;\t// @[execution-unit.scala:262:32]\n wire _io_fu_types_T_12 = 1'h0;\t// @[execution-unit.scala:265:33]\n wire div_resp_val = 1'h0;\t// @[execution-unit.scala:364:30]\n wire [22:0] io_status_zero2 = 23'h0;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire [31:0] io_status_isa = 32'h14112D;\t// @[execution-unit.scala:104:14, :204:7, :388:27]\n wire io_ll_iresp_valid_0 = io_lsu_io_iresp_valid_0;\t// @[execution-unit.scala:204:7]\n wire [6:0] io_ll_iresp_bits_uop_uopc_0 = io_lsu_io_iresp_bits_uop_uopc_0;\t// @[execution-unit.scala:204:7]\n wire [31:0] io_ll_iresp_bits_uop_inst_0 = io_lsu_io_iresp_bits_uop_inst_0;\t// @[execution-unit.scala:204:7]\n wire [31:0] io_ll_iresp_bits_uop_debug_inst_0 = io_lsu_io_iresp_bits_uop_debug_inst_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_is_rvc_0 = io_lsu_io_iresp_bits_uop_is_rvc_0;\t// @[execution-unit.scala:204:7]\n wire [39:0] io_ll_iresp_bits_uop_debug_pc_0 = io_lsu_io_iresp_bits_uop_debug_pc_0;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_ll_iresp_bits_uop_iq_type_0 = io_lsu_io_iresp_bits_uop_iq_type_0;\t// @[execution-unit.scala:204:7]\n wire [9:0] io_ll_iresp_bits_uop_fu_code_0 = io_lsu_io_iresp_bits_uop_fu_code_0;\t// @[execution-unit.scala:204:7]\n wire [3:0] io_ll_iresp_bits_uop_ctrl_br_type_0 = io_lsu_io_iresp_bits_uop_ctrl_br_type_0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_iresp_bits_uop_ctrl_op1_sel_0 = io_lsu_io_iresp_bits_uop_ctrl_op1_sel_0;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_ll_iresp_bits_uop_ctrl_op2_sel_0 = io_lsu_io_iresp_bits_uop_ctrl_op2_sel_0;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_ll_iresp_bits_uop_ctrl_imm_sel_0 = io_lsu_io_iresp_bits_uop_ctrl_imm_sel_0;\t// @[execution-unit.scala:204:7]\n wire [4:0] io_ll_iresp_bits_uop_ctrl_op_fcn_0 = io_lsu_io_iresp_bits_uop_ctrl_op_fcn_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_ctrl_fcn_dw_0 = io_lsu_io_iresp_bits_uop_ctrl_fcn_dw_0;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_ll_iresp_bits_uop_ctrl_csr_cmd_0 = io_lsu_io_iresp_bits_uop_ctrl_csr_cmd_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_ctrl_is_load_0 = io_lsu_io_iresp_bits_uop_ctrl_is_load_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_ctrl_is_sta_0 = io_lsu_io_iresp_bits_uop_ctrl_is_sta_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_ctrl_is_std_0 = io_lsu_io_iresp_bits_uop_ctrl_is_std_0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_iresp_bits_uop_iw_state_0 = io_lsu_io_iresp_bits_uop_iw_state_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_iw_p1_poisoned_0 = io_lsu_io_iresp_bits_uop_iw_p1_poisoned_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_iw_p2_poisoned_0 = io_lsu_io_iresp_bits_uop_iw_p2_poisoned_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_is_br_0 = io_lsu_io_iresp_bits_uop_is_br_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_is_jalr_0 = io_lsu_io_iresp_bits_uop_is_jalr_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_is_jal_0 = io_lsu_io_iresp_bits_uop_is_jal_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_is_sfb_0 = io_lsu_io_iresp_bits_uop_is_sfb_0;\t// @[execution-unit.scala:204:7]\n wire [7:0] io_ll_iresp_bits_uop_br_mask_0 = io_lsu_io_iresp_bits_uop_br_mask_0;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_ll_iresp_bits_uop_br_tag_0 = io_lsu_io_iresp_bits_uop_br_tag_0;\t// @[execution-unit.scala:204:7]\n wire [3:0] io_ll_iresp_bits_uop_ftq_idx_0 = io_lsu_io_iresp_bits_uop_ftq_idx_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_edge_inst_0 = io_lsu_io_iresp_bits_uop_edge_inst_0;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_ll_iresp_bits_uop_pc_lob_0 = io_lsu_io_iresp_bits_uop_pc_lob_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_taken_0 = io_lsu_io_iresp_bits_uop_taken_0;\t// @[execution-unit.scala:204:7]\n wire [19:0] io_ll_iresp_bits_uop_imm_packed_0 = io_lsu_io_iresp_bits_uop_imm_packed_0;\t// @[execution-unit.scala:204:7]\n wire [11:0] io_ll_iresp_bits_uop_csr_addr_0 = io_lsu_io_iresp_bits_uop_csr_addr_0;\t// @[execution-unit.scala:204:7]\n wire [4:0] io_ll_iresp_bits_uop_rob_idx_0 = io_lsu_io_iresp_bits_uop_rob_idx_0;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_ll_iresp_bits_uop_ldq_idx_0 = io_lsu_io_iresp_bits_uop_ldq_idx_0;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_ll_iresp_bits_uop_stq_idx_0 = io_lsu_io_iresp_bits_uop_stq_idx_0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_iresp_bits_uop_rxq_idx_0 = io_lsu_io_iresp_bits_uop_rxq_idx_0;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_ll_iresp_bits_uop_pdst_0 = io_lsu_io_iresp_bits_uop_pdst_0;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_ll_iresp_bits_uop_prs1_0 = io_lsu_io_iresp_bits_uop_prs1_0;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_ll_iresp_bits_uop_prs2_0 = io_lsu_io_iresp_bits_uop_prs2_0;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_ll_iresp_bits_uop_prs3_0 = io_lsu_io_iresp_bits_uop_prs3_0;\t// @[execution-unit.scala:204:7]\n wire [3:0] io_ll_iresp_bits_uop_ppred_0 = io_lsu_io_iresp_bits_uop_ppred_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_prs1_busy_0 = io_lsu_io_iresp_bits_uop_prs1_busy_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_prs2_busy_0 = io_lsu_io_iresp_bits_uop_prs2_busy_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_prs3_busy_0 = io_lsu_io_iresp_bits_uop_prs3_busy_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_ppred_busy_0 = io_lsu_io_iresp_bits_uop_ppred_busy_0;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_ll_iresp_bits_uop_stale_pdst_0 = io_lsu_io_iresp_bits_uop_stale_pdst_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_exception_0 = io_lsu_io_iresp_bits_uop_exception_0;\t// @[execution-unit.scala:204:7]\n wire [63:0] io_ll_iresp_bits_uop_exc_cause_0 = io_lsu_io_iresp_bits_uop_exc_cause_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_bypassable_0 = io_lsu_io_iresp_bits_uop_bypassable_0;\t// @[execution-unit.scala:204:7]\n wire [4:0] io_ll_iresp_bits_uop_mem_cmd_0 = io_lsu_io_iresp_bits_uop_mem_cmd_0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_iresp_bits_uop_mem_size_0 = io_lsu_io_iresp_bits_uop_mem_size_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_mem_signed_0 = io_lsu_io_iresp_bits_uop_mem_signed_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_is_fence_0 = io_lsu_io_iresp_bits_uop_is_fence_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_is_fencei_0 = io_lsu_io_iresp_bits_uop_is_fencei_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_is_amo_0 = io_lsu_io_iresp_bits_uop_is_amo_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_uses_ldq_0 = io_lsu_io_iresp_bits_uop_uses_ldq_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_uses_stq_0 = io_lsu_io_iresp_bits_uop_uses_stq_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_is_sys_pc2epc_0 = io_lsu_io_iresp_bits_uop_is_sys_pc2epc_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_is_unique_0 = io_lsu_io_iresp_bits_uop_is_unique_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_flush_on_commit_0 = io_lsu_io_iresp_bits_uop_flush_on_commit_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_ldst_is_rs1_0 = io_lsu_io_iresp_bits_uop_ldst_is_rs1_0;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_ll_iresp_bits_uop_ldst_0 = io_lsu_io_iresp_bits_uop_ldst_0;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_ll_iresp_bits_uop_lrs1_0 = io_lsu_io_iresp_bits_uop_lrs1_0;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_ll_iresp_bits_uop_lrs2_0 = io_lsu_io_iresp_bits_uop_lrs2_0;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_ll_iresp_bits_uop_lrs3_0 = io_lsu_io_iresp_bits_uop_lrs3_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_ldst_val_0 = io_lsu_io_iresp_bits_uop_ldst_val_0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_iresp_bits_uop_dst_rtype_0 = io_lsu_io_iresp_bits_uop_dst_rtype_0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_iresp_bits_uop_lrs1_rtype_0 = io_lsu_io_iresp_bits_uop_lrs1_rtype_0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_iresp_bits_uop_lrs2_rtype_0 = io_lsu_io_iresp_bits_uop_lrs2_rtype_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_frs3_en_0 = io_lsu_io_iresp_bits_uop_frs3_en_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_fp_val_0 = io_lsu_io_iresp_bits_uop_fp_val_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_fp_single_0 = io_lsu_io_iresp_bits_uop_fp_single_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_xcpt_pf_if_0 = io_lsu_io_iresp_bits_uop_xcpt_pf_if_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_xcpt_ae_if_0 = io_lsu_io_iresp_bits_uop_xcpt_ae_if_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_xcpt_ma_if_0 = io_lsu_io_iresp_bits_uop_xcpt_ma_if_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_bp_debug_if_0 = io_lsu_io_iresp_bits_uop_bp_debug_if_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_iresp_bits_uop_bp_xcpt_if_0 = io_lsu_io_iresp_bits_uop_bp_xcpt_if_0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_iresp_bits_uop_debug_fsrc_0 = io_lsu_io_iresp_bits_uop_debug_fsrc_0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_iresp_bits_uop_debug_tsrc_0 = io_lsu_io_iresp_bits_uop_debug_tsrc_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_valid_0 = io_lsu_io_fresp_valid_0;\t// @[execution-unit.scala:204:7]\n wire [6:0] io_ll_fresp_bits_uop_uopc_0 = io_lsu_io_fresp_bits_uop_uopc_0;\t// @[execution-unit.scala:204:7]\n wire [31:0] io_ll_fresp_bits_uop_inst_0 = io_lsu_io_fresp_bits_uop_inst_0;\t// @[execution-unit.scala:204:7]\n wire [31:0] io_ll_fresp_bits_uop_debug_inst_0 = io_lsu_io_fresp_bits_uop_debug_inst_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_is_rvc_0 = io_lsu_io_fresp_bits_uop_is_rvc_0;\t// @[execution-unit.scala:204:7]\n wire [39:0] io_ll_fresp_bits_uop_debug_pc_0 = io_lsu_io_fresp_bits_uop_debug_pc_0;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_ll_fresp_bits_uop_iq_type_0 = io_lsu_io_fresp_bits_uop_iq_type_0;\t// @[execution-unit.scala:204:7]\n wire [9:0] io_ll_fresp_bits_uop_fu_code_0 = io_lsu_io_fresp_bits_uop_fu_code_0;\t// @[execution-unit.scala:204:7]\n wire [3:0] io_ll_fresp_bits_uop_ctrl_br_type_0 = io_lsu_io_fresp_bits_uop_ctrl_br_type_0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_fresp_bits_uop_ctrl_op1_sel_0 = io_lsu_io_fresp_bits_uop_ctrl_op1_sel_0;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_ll_fresp_bits_uop_ctrl_op2_sel_0 = io_lsu_io_fresp_bits_uop_ctrl_op2_sel_0;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_ll_fresp_bits_uop_ctrl_imm_sel_0 = io_lsu_io_fresp_bits_uop_ctrl_imm_sel_0;\t// @[execution-unit.scala:204:7]\n wire [4:0] io_ll_fresp_bits_uop_ctrl_op_fcn_0 = io_lsu_io_fresp_bits_uop_ctrl_op_fcn_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_ctrl_fcn_dw_0 = io_lsu_io_fresp_bits_uop_ctrl_fcn_dw_0;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_ll_fresp_bits_uop_ctrl_csr_cmd_0 = io_lsu_io_fresp_bits_uop_ctrl_csr_cmd_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_ctrl_is_load_0 = io_lsu_io_fresp_bits_uop_ctrl_is_load_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_ctrl_is_sta_0 = io_lsu_io_fresp_bits_uop_ctrl_is_sta_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_ctrl_is_std_0 = io_lsu_io_fresp_bits_uop_ctrl_is_std_0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_fresp_bits_uop_iw_state_0 = io_lsu_io_fresp_bits_uop_iw_state_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_iw_p1_poisoned_0 = io_lsu_io_fresp_bits_uop_iw_p1_poisoned_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_iw_p2_poisoned_0 = io_lsu_io_fresp_bits_uop_iw_p2_poisoned_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_is_br_0 = io_lsu_io_fresp_bits_uop_is_br_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_is_jalr_0 = io_lsu_io_fresp_bits_uop_is_jalr_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_is_jal_0 = io_lsu_io_fresp_bits_uop_is_jal_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_is_sfb_0 = io_lsu_io_fresp_bits_uop_is_sfb_0;\t// @[execution-unit.scala:204:7]\n wire [7:0] io_ll_fresp_bits_uop_br_mask_0 = io_lsu_io_fresp_bits_uop_br_mask_0;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_ll_fresp_bits_uop_br_tag_0 = io_lsu_io_fresp_bits_uop_br_tag_0;\t// @[execution-unit.scala:204:7]\n wire [3:0] io_ll_fresp_bits_uop_ftq_idx_0 = io_lsu_io_fresp_bits_uop_ftq_idx_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_edge_inst_0 = io_lsu_io_fresp_bits_uop_edge_inst_0;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_ll_fresp_bits_uop_pc_lob_0 = io_lsu_io_fresp_bits_uop_pc_lob_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_taken_0 = io_lsu_io_fresp_bits_uop_taken_0;\t// @[execution-unit.scala:204:7]\n wire [19:0] io_ll_fresp_bits_uop_imm_packed_0 = io_lsu_io_fresp_bits_uop_imm_packed_0;\t// @[execution-unit.scala:204:7]\n wire [11:0] io_ll_fresp_bits_uop_csr_addr_0 = io_lsu_io_fresp_bits_uop_csr_addr_0;\t// @[execution-unit.scala:204:7]\n wire [4:0] io_ll_fresp_bits_uop_rob_idx_0 = io_lsu_io_fresp_bits_uop_rob_idx_0;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_ll_fresp_bits_uop_ldq_idx_0 = io_lsu_io_fresp_bits_uop_ldq_idx_0;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_ll_fresp_bits_uop_stq_idx_0 = io_lsu_io_fresp_bits_uop_stq_idx_0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_fresp_bits_uop_rxq_idx_0 = io_lsu_io_fresp_bits_uop_rxq_idx_0;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_ll_fresp_bits_uop_pdst_0 = io_lsu_io_fresp_bits_uop_pdst_0;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_ll_fresp_bits_uop_prs1_0 = io_lsu_io_fresp_bits_uop_prs1_0;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_ll_fresp_bits_uop_prs2_0 = io_lsu_io_fresp_bits_uop_prs2_0;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_ll_fresp_bits_uop_prs3_0 = io_lsu_io_fresp_bits_uop_prs3_0;\t// @[execution-unit.scala:204:7]\n wire [3:0] io_ll_fresp_bits_uop_ppred_0 = io_lsu_io_fresp_bits_uop_ppred_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_prs1_busy_0 = io_lsu_io_fresp_bits_uop_prs1_busy_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_prs2_busy_0 = io_lsu_io_fresp_bits_uop_prs2_busy_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_prs3_busy_0 = io_lsu_io_fresp_bits_uop_prs3_busy_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_ppred_busy_0 = io_lsu_io_fresp_bits_uop_ppred_busy_0;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_ll_fresp_bits_uop_stale_pdst_0 = io_lsu_io_fresp_bits_uop_stale_pdst_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_exception_0 = io_lsu_io_fresp_bits_uop_exception_0;\t// @[execution-unit.scala:204:7]\n wire [63:0] io_ll_fresp_bits_uop_exc_cause_0 = io_lsu_io_fresp_bits_uop_exc_cause_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_bypassable_0 = io_lsu_io_fresp_bits_uop_bypassable_0;\t// @[execution-unit.scala:204:7]\n wire [4:0] io_ll_fresp_bits_uop_mem_cmd_0 = io_lsu_io_fresp_bits_uop_mem_cmd_0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_fresp_bits_uop_mem_size_0 = io_lsu_io_fresp_bits_uop_mem_size_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_mem_signed_0 = io_lsu_io_fresp_bits_uop_mem_signed_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_is_fence_0 = io_lsu_io_fresp_bits_uop_is_fence_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_is_fencei_0 = io_lsu_io_fresp_bits_uop_is_fencei_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_is_amo_0 = io_lsu_io_fresp_bits_uop_is_amo_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_uses_ldq_0 = io_lsu_io_fresp_bits_uop_uses_ldq_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_uses_stq_0 = io_lsu_io_fresp_bits_uop_uses_stq_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_is_sys_pc2epc_0 = io_lsu_io_fresp_bits_uop_is_sys_pc2epc_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_is_unique_0 = io_lsu_io_fresp_bits_uop_is_unique_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_flush_on_commit_0 = io_lsu_io_fresp_bits_uop_flush_on_commit_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_ldst_is_rs1_0 = io_lsu_io_fresp_bits_uop_ldst_is_rs1_0;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_ll_fresp_bits_uop_ldst_0 = io_lsu_io_fresp_bits_uop_ldst_0;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_ll_fresp_bits_uop_lrs1_0 = io_lsu_io_fresp_bits_uop_lrs1_0;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_ll_fresp_bits_uop_lrs2_0 = io_lsu_io_fresp_bits_uop_lrs2_0;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_ll_fresp_bits_uop_lrs3_0 = io_lsu_io_fresp_bits_uop_lrs3_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_ldst_val_0 = io_lsu_io_fresp_bits_uop_ldst_val_0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_fresp_bits_uop_dst_rtype_0 = io_lsu_io_fresp_bits_uop_dst_rtype_0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_fresp_bits_uop_lrs1_rtype_0 = io_lsu_io_fresp_bits_uop_lrs1_rtype_0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_fresp_bits_uop_lrs2_rtype_0 = io_lsu_io_fresp_bits_uop_lrs2_rtype_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_frs3_en_0 = io_lsu_io_fresp_bits_uop_frs3_en_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_fp_val_0 = io_lsu_io_fresp_bits_uop_fp_val_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_fp_single_0 = io_lsu_io_fresp_bits_uop_fp_single_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_xcpt_pf_if_0 = io_lsu_io_fresp_bits_uop_xcpt_pf_if_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_xcpt_ae_if_0 = io_lsu_io_fresp_bits_uop_xcpt_ae_if_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_xcpt_ma_if_0 = io_lsu_io_fresp_bits_uop_xcpt_ma_if_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_bp_debug_if_0 = io_lsu_io_fresp_bits_uop_bp_debug_if_0;\t// @[execution-unit.scala:204:7]\n wire io_ll_fresp_bits_uop_bp_xcpt_if_0 = io_lsu_io_fresp_bits_uop_bp_xcpt_if_0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_fresp_bits_uop_debug_fsrc_0 = io_lsu_io_fresp_bits_uop_debug_fsrc_0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_ll_fresp_bits_uop_debug_tsrc_0 = io_lsu_io_fresp_bits_uop_debug_tsrc_0;\t// @[execution-unit.scala:204:7]\n wire [64:0] io_ll_fresp_bits_data_0 = io_lsu_io_fresp_bits_data_0;\t// @[execution-unit.scala:204:7]\n wire [64:0] io_ll_iresp_bits_data_0;\t// @[execution-unit.scala:204:7]\n wire [3:0] io_lsu_io_req_bits_uop_ctrl_br_type_0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_req_bits_uop_ctrl_op1_sel_0;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_lsu_io_req_bits_uop_ctrl_op2_sel_0;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_lsu_io_req_bits_uop_ctrl_imm_sel_0;\t// @[execution-unit.scala:204:7]\n wire [4:0] io_lsu_io_req_bits_uop_ctrl_op_fcn_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_ctrl_fcn_dw_0;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_lsu_io_req_bits_uop_ctrl_csr_cmd_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_ctrl_is_load_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_ctrl_is_sta_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_ctrl_is_std_0;\t// @[execution-unit.scala:204:7]\n wire [6:0] io_lsu_io_req_bits_uop_uopc_0;\t// @[execution-unit.scala:204:7]\n wire [31:0] io_lsu_io_req_bits_uop_inst_0;\t// @[execution-unit.scala:204:7]\n wire [31:0] io_lsu_io_req_bits_uop_debug_inst_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_is_rvc_0;\t// @[execution-unit.scala:204:7]\n wire [39:0] io_lsu_io_req_bits_uop_debug_pc_0;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_lsu_io_req_bits_uop_iq_type_0;\t// @[execution-unit.scala:204:7]\n wire [9:0] io_lsu_io_req_bits_uop_fu_code_0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_req_bits_uop_iw_state_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_iw_p1_poisoned_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_iw_p2_poisoned_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_is_br_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_is_jalr_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_is_jal_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_is_sfb_0;\t// @[execution-unit.scala:204:7]\n wire [7:0] io_lsu_io_req_bits_uop_br_mask_0;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_lsu_io_req_bits_uop_br_tag_0;\t// @[execution-unit.scala:204:7]\n wire [3:0] io_lsu_io_req_bits_uop_ftq_idx_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_edge_inst_0;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_lsu_io_req_bits_uop_pc_lob_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_taken_0;\t// @[execution-unit.scala:204:7]\n wire [19:0] io_lsu_io_req_bits_uop_imm_packed_0;\t// @[execution-unit.scala:204:7]\n wire [11:0] io_lsu_io_req_bits_uop_csr_addr_0;\t// @[execution-unit.scala:204:7]\n wire [4:0] io_lsu_io_req_bits_uop_rob_idx_0;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_lsu_io_req_bits_uop_ldq_idx_0;\t// @[execution-unit.scala:204:7]\n wire [2:0] io_lsu_io_req_bits_uop_stq_idx_0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_req_bits_uop_rxq_idx_0;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_lsu_io_req_bits_uop_pdst_0;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_lsu_io_req_bits_uop_prs1_0;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_lsu_io_req_bits_uop_prs2_0;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_lsu_io_req_bits_uop_prs3_0;\t// @[execution-unit.scala:204:7]\n wire [3:0] io_lsu_io_req_bits_uop_ppred_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_prs1_busy_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_prs2_busy_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_prs3_busy_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_ppred_busy_0;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_lsu_io_req_bits_uop_stale_pdst_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_exception_0;\t// @[execution-unit.scala:204:7]\n wire [63:0] io_lsu_io_req_bits_uop_exc_cause_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_bypassable_0;\t// @[execution-unit.scala:204:7]\n wire [4:0] io_lsu_io_req_bits_uop_mem_cmd_0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_req_bits_uop_mem_size_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_mem_signed_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_is_fence_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_is_fencei_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_is_amo_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_uses_ldq_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_uses_stq_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_is_sys_pc2epc_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_is_unique_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_flush_on_commit_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_ldst_is_rs1_0;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_lsu_io_req_bits_uop_ldst_0;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_lsu_io_req_bits_uop_lrs1_0;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_lsu_io_req_bits_uop_lrs2_0;\t// @[execution-unit.scala:204:7]\n wire [5:0] io_lsu_io_req_bits_uop_lrs3_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_ldst_val_0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_req_bits_uop_dst_rtype_0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_req_bits_uop_lrs1_rtype_0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_req_bits_uop_lrs2_rtype_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_frs3_en_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_fp_val_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_fp_single_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_xcpt_pf_if_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_xcpt_ae_if_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_xcpt_ma_if_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_bp_debug_if_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_uop_bp_xcpt_if_0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_req_bits_uop_debug_fsrc_0;\t// @[execution-unit.scala:204:7]\n wire [1:0] io_lsu_io_req_bits_uop_debug_tsrc_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_mxcpt_valid_0;\t// @[execution-unit.scala:204:7]\n wire [24:0] io_lsu_io_req_bits_mxcpt_bits_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_sfence_bits_rs1_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_sfence_bits_rs2_0;\t// @[execution-unit.scala:204:7]\n wire [38:0] io_lsu_io_req_bits_sfence_bits_addr_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_sfence_bits_asid_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_bits_sfence_valid_0;\t// @[execution-unit.scala:204:7]\n wire [63:0] io_lsu_io_req_bits_data_0;\t// @[execution-unit.scala:204:7]\n wire [39:0] io_lsu_io_req_bits_addr_0;\t// @[execution-unit.scala:204:7]\n wire io_lsu_io_req_valid_0;\t// @[execution-unit.scala:204:7]\n wire [9:0] _maddrcalc_io_req_valid_T = io_req_bits_uop_fu_code_0 & 10'h4;\t// @[execution-unit.scala:204:7]\n wire _maddrcalc_io_req_valid_T_1 = |_maddrcalc_io_req_valid_T;\t// @[micro-op.scala:154:{40,47}]\n wire _maddrcalc_io_req_valid_T_2 = io_req_valid_0 & _maddrcalc_io_req_valid_T_1;\t// @[execution-unit.scala:204:7, :390:45]\n assign io_lsu_io_req_bits_data_0 = _maddrcalc_io_resp_bits_data[63:0];\t// @[execution-unit.scala:204:7, :388:27, :399:19]\n assign io_ll_iresp_bits_data_0 = {1'h0, io_lsu_io_iresp_bits_data_0};\t// @[execution-unit.scala:204:7, :401:17]\n MemAddrCalcUnit_1 maddrcalc (\t// @[execution-unit.scala:388:27]\n .clock (clock),\n .reset (reset),\n .io_req_valid (_maddrcalc_io_req_valid_T_2),\t// @[execution-unit.scala:390:45]\n .io_req_bits_uop_uopc (io_req_bits_uop_uopc_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_inst (io_req_bits_uop_inst_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_debug_inst (io_req_bits_uop_debug_inst_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_is_rvc (io_req_bits_uop_is_rvc_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_debug_pc (io_req_bits_uop_debug_pc_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_iq_type (io_req_bits_uop_iq_type_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_fu_code (io_req_bits_uop_fu_code_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_ctrl_br_type (io_req_bits_uop_ctrl_br_type_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_ctrl_op1_sel (io_req_bits_uop_ctrl_op1_sel_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_ctrl_op2_sel (io_req_bits_uop_ctrl_op2_sel_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_ctrl_imm_sel (io_req_bits_uop_ctrl_imm_sel_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_ctrl_op_fcn (io_req_bits_uop_ctrl_op_fcn_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_ctrl_fcn_dw (io_req_bits_uop_ctrl_fcn_dw_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_ctrl_csr_cmd (io_req_bits_uop_ctrl_csr_cmd_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_ctrl_is_load (io_req_bits_uop_ctrl_is_load_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_ctrl_is_sta (io_req_bits_uop_ctrl_is_sta_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_ctrl_is_std (io_req_bits_uop_ctrl_is_std_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_iw_state (io_req_bits_uop_iw_state_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_iw_p1_poisoned (io_req_bits_uop_iw_p1_poisoned_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_iw_p2_poisoned (io_req_bits_uop_iw_p2_poisoned_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_is_br (io_req_bits_uop_is_br_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_is_jalr (io_req_bits_uop_is_jalr_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_is_jal (io_req_bits_uop_is_jal_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_is_sfb (io_req_bits_uop_is_sfb_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_br_mask (io_req_bits_uop_br_mask_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_br_tag (io_req_bits_uop_br_tag_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_ftq_idx (io_req_bits_uop_ftq_idx_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_edge_inst (io_req_bits_uop_edge_inst_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_pc_lob (io_req_bits_uop_pc_lob_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_taken (io_req_bits_uop_taken_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_imm_packed (io_req_bits_uop_imm_packed_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_csr_addr (io_req_bits_uop_csr_addr_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_rob_idx (io_req_bits_uop_rob_idx_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_ldq_idx (io_req_bits_uop_ldq_idx_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_stq_idx (io_req_bits_uop_stq_idx_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_rxq_idx (io_req_bits_uop_rxq_idx_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_pdst (io_req_bits_uop_pdst_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_prs1 (io_req_bits_uop_prs1_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_prs2 (io_req_bits_uop_prs2_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_prs3 (io_req_bits_uop_prs3_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_ppred (io_req_bits_uop_ppred_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_prs1_busy (io_req_bits_uop_prs1_busy_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_prs2_busy (io_req_bits_uop_prs2_busy_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_prs3_busy (io_req_bits_uop_prs3_busy_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_ppred_busy (io_req_bits_uop_ppred_busy_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_stale_pdst (io_req_bits_uop_stale_pdst_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_exception (io_req_bits_uop_exception_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_exc_cause (io_req_bits_uop_exc_cause_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_bypassable (io_req_bits_uop_bypassable_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_mem_cmd (io_req_bits_uop_mem_cmd_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_mem_size (io_req_bits_uop_mem_size_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_mem_signed (io_req_bits_uop_mem_signed_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_is_fence (io_req_bits_uop_is_fence_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_is_fencei (io_req_bits_uop_is_fencei_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_is_amo (io_req_bits_uop_is_amo_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_uses_ldq (io_req_bits_uop_uses_ldq_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_uses_stq (io_req_bits_uop_uses_stq_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_is_sys_pc2epc (io_req_bits_uop_is_sys_pc2epc_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_is_unique (io_req_bits_uop_is_unique_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_flush_on_commit (io_req_bits_uop_flush_on_commit_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_ldst_is_rs1 (io_req_bits_uop_ldst_is_rs1_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_ldst (io_req_bits_uop_ldst_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_lrs1 (io_req_bits_uop_lrs1_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_lrs2 (io_req_bits_uop_lrs2_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_lrs3 (io_req_bits_uop_lrs3_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_ldst_val (io_req_bits_uop_ldst_val_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_dst_rtype (io_req_bits_uop_dst_rtype_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_lrs1_rtype (io_req_bits_uop_lrs1_rtype_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_lrs2_rtype (io_req_bits_uop_lrs2_rtype_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_frs3_en (io_req_bits_uop_frs3_en_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_fp_val (io_req_bits_uop_fp_val_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_fp_single (io_req_bits_uop_fp_single_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_xcpt_pf_if (io_req_bits_uop_xcpt_pf_if_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_xcpt_ae_if (io_req_bits_uop_xcpt_ae_if_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_xcpt_ma_if (io_req_bits_uop_xcpt_ma_if_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_bp_debug_if (io_req_bits_uop_bp_debug_if_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_bp_xcpt_if (io_req_bits_uop_bp_xcpt_if_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_debug_fsrc (io_req_bits_uop_debug_fsrc_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_uop_debug_tsrc (io_req_bits_uop_debug_tsrc_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_rs1_data (io_req_bits_rs1_data_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_rs2_data (io_req_bits_rs2_data_0),\t// @[execution-unit.scala:204:7]\n .io_req_bits_kill (io_req_bits_kill_0),\t// @[execution-unit.scala:204:7]\n .io_resp_valid (io_lsu_io_req_valid_0),\n .io_resp_bits_uop_uopc (io_lsu_io_req_bits_uop_uopc_0),\n .io_resp_bits_uop_inst (io_lsu_io_req_bits_uop_inst_0),\n .io_resp_bits_uop_debug_inst (io_lsu_io_req_bits_uop_debug_inst_0),\n .io_resp_bits_uop_is_rvc (io_lsu_io_req_bits_uop_is_rvc_0),\n .io_resp_bits_uop_debug_pc (io_lsu_io_req_bits_uop_debug_pc_0),\n .io_resp_bits_uop_iq_type (io_lsu_io_req_bits_uop_iq_type_0),\n .io_resp_bits_uop_fu_code (io_lsu_io_req_bits_uop_fu_code_0),\n .io_resp_bits_uop_ctrl_br_type (io_lsu_io_req_bits_uop_ctrl_br_type_0),\n .io_resp_bits_uop_ctrl_op1_sel (io_lsu_io_req_bits_uop_ctrl_op1_sel_0),\n .io_resp_bits_uop_ctrl_op2_sel (io_lsu_io_req_bits_uop_ctrl_op2_sel_0),\n .io_resp_bits_uop_ctrl_imm_sel (io_lsu_io_req_bits_uop_ctrl_imm_sel_0),\n .io_resp_bits_uop_ctrl_op_fcn (io_lsu_io_req_bits_uop_ctrl_op_fcn_0),\n .io_resp_bits_uop_ctrl_fcn_dw (io_lsu_io_req_bits_uop_ctrl_fcn_dw_0),\n .io_resp_bits_uop_ctrl_csr_cmd (io_lsu_io_req_bits_uop_ctrl_csr_cmd_0),\n .io_resp_bits_uop_ctrl_is_load (io_lsu_io_req_bits_uop_ctrl_is_load_0),\n .io_resp_bits_uop_ctrl_is_sta (io_lsu_io_req_bits_uop_ctrl_is_sta_0),\n .io_resp_bits_uop_ctrl_is_std (io_lsu_io_req_bits_uop_ctrl_is_std_0),\n .io_resp_bits_uop_iw_state (io_lsu_io_req_bits_uop_iw_state_0),\n .io_resp_bits_uop_iw_p1_poisoned (io_lsu_io_req_bits_uop_iw_p1_poisoned_0),\n .io_resp_bits_uop_iw_p2_poisoned (io_lsu_io_req_bits_uop_iw_p2_poisoned_0),\n .io_resp_bits_uop_is_br (io_lsu_io_req_bits_uop_is_br_0),\n .io_resp_bits_uop_is_jalr (io_lsu_io_req_bits_uop_is_jalr_0),\n .io_resp_bits_uop_is_jal (io_lsu_io_req_bits_uop_is_jal_0),\n .io_resp_bits_uop_is_sfb (io_lsu_io_req_bits_uop_is_sfb_0),\n .io_resp_bits_uop_br_mask (io_lsu_io_req_bits_uop_br_mask_0),\n .io_resp_bits_uop_br_tag (io_lsu_io_req_bits_uop_br_tag_0),\n .io_resp_bits_uop_ftq_idx (io_lsu_io_req_bits_uop_ftq_idx_0),\n .io_resp_bits_uop_edge_inst (io_lsu_io_req_bits_uop_edge_inst_0),\n .io_resp_bits_uop_pc_lob (io_lsu_io_req_bits_uop_pc_lob_0),\n .io_resp_bits_uop_taken (io_lsu_io_req_bits_uop_taken_0),\n .io_resp_bits_uop_imm_packed (io_lsu_io_req_bits_uop_imm_packed_0),\n .io_resp_bits_uop_csr_addr (io_lsu_io_req_bits_uop_csr_addr_0),\n .io_resp_bits_uop_rob_idx (io_lsu_io_req_bits_uop_rob_idx_0),\n .io_resp_bits_uop_ldq_idx (io_lsu_io_req_bits_uop_ldq_idx_0),\n .io_resp_bits_uop_stq_idx (io_lsu_io_req_bits_uop_stq_idx_0),\n .io_resp_bits_uop_rxq_idx (io_lsu_io_req_bits_uop_rxq_idx_0),\n .io_resp_bits_uop_pdst (io_lsu_io_req_bits_uop_pdst_0),\n .io_resp_bits_uop_prs1 (io_lsu_io_req_bits_uop_prs1_0),\n .io_resp_bits_uop_prs2 (io_lsu_io_req_bits_uop_prs2_0),\n .io_resp_bits_uop_prs3 (io_lsu_io_req_bits_uop_prs3_0),\n .io_resp_bits_uop_ppred (io_lsu_io_req_bits_uop_ppred_0),\n .io_resp_bits_uop_prs1_busy (io_lsu_io_req_bits_uop_prs1_busy_0),\n .io_resp_bits_uop_prs2_busy (io_lsu_io_req_bits_uop_prs2_busy_0),\n .io_resp_bits_uop_prs3_busy (io_lsu_io_req_bits_uop_prs3_busy_0),\n .io_resp_bits_uop_ppred_busy (io_lsu_io_req_bits_uop_ppred_busy_0),\n .io_resp_bits_uop_stale_pdst (io_lsu_io_req_bits_uop_stale_pdst_0),\n .io_resp_bits_uop_exception (io_lsu_io_req_bits_uop_exception_0),\n .io_resp_bits_uop_exc_cause (io_lsu_io_req_bits_uop_exc_cause_0),\n .io_resp_bits_uop_bypassable (io_lsu_io_req_bits_uop_bypassable_0),\n .io_resp_bits_uop_mem_cmd (io_lsu_io_req_bits_uop_mem_cmd_0),\n .io_resp_bits_uop_mem_size (io_lsu_io_req_bits_uop_mem_size_0),\n .io_resp_bits_uop_mem_signed (io_lsu_io_req_bits_uop_mem_signed_0),\n .io_resp_bits_uop_is_fence (io_lsu_io_req_bits_uop_is_fence_0),\n .io_resp_bits_uop_is_fencei (io_lsu_io_req_bits_uop_is_fencei_0),\n .io_resp_bits_uop_is_amo (io_lsu_io_req_bits_uop_is_amo_0),\n .io_resp_bits_uop_uses_ldq (io_lsu_io_req_bits_uop_uses_ldq_0),\n .io_resp_bits_uop_uses_stq (io_lsu_io_req_bits_uop_uses_stq_0),\n .io_resp_bits_uop_is_sys_pc2epc (io_lsu_io_req_bits_uop_is_sys_pc2epc_0),\n .io_resp_bits_uop_is_unique (io_lsu_io_req_bits_uop_is_unique_0),\n .io_resp_bits_uop_flush_on_commit (io_lsu_io_req_bits_uop_flush_on_commit_0),\n .io_resp_bits_uop_ldst_is_rs1 (io_lsu_io_req_bits_uop_ldst_is_rs1_0),\n .io_resp_bits_uop_ldst (io_lsu_io_req_bits_uop_ldst_0),\n .io_resp_bits_uop_lrs1 (io_lsu_io_req_bits_uop_lrs1_0),\n .io_resp_bits_uop_lrs2 (io_lsu_io_req_bits_uop_lrs2_0),\n .io_resp_bits_uop_lrs3 (io_lsu_io_req_bits_uop_lrs3_0),\n .io_resp_bits_uop_ldst_val (io_lsu_io_req_bits_uop_ldst_val_0),\n .io_resp_bits_uop_dst_rtype (io_lsu_io_req_bits_uop_dst_rtype_0),\n .io_resp_bits_uop_lrs1_rtype (io_lsu_io_req_bits_uop_lrs1_rtype_0),\n .io_resp_bits_uop_lrs2_rtype (io_lsu_io_req_bits_uop_lrs2_rtype_0),\n .io_resp_bits_uop_frs3_en (io_lsu_io_req_bits_uop_frs3_en_0),\n .io_resp_bits_uop_fp_val (io_lsu_io_req_bits_uop_fp_val_0),\n .io_resp_bits_uop_fp_single (io_lsu_io_req_bits_uop_fp_single_0),\n .io_resp_bits_uop_xcpt_pf_if (io_lsu_io_req_bits_uop_xcpt_pf_if_0),\n .io_resp_bits_uop_xcpt_ae_if (io_lsu_io_req_bits_uop_xcpt_ae_if_0),\n .io_resp_bits_uop_xcpt_ma_if (io_lsu_io_req_bits_uop_xcpt_ma_if_0),\n .io_resp_bits_uop_bp_debug_if (io_lsu_io_req_bits_uop_bp_debug_if_0),\n .io_resp_bits_uop_bp_xcpt_if (io_lsu_io_req_bits_uop_bp_xcpt_if_0),\n .io_resp_bits_uop_debug_fsrc (io_lsu_io_req_bits_uop_debug_fsrc_0),\n .io_resp_bits_uop_debug_tsrc (io_lsu_io_req_bits_uop_debug_tsrc_0),\n .io_resp_bits_data (_maddrcalc_io_resp_bits_data),\n .io_resp_bits_addr (io_lsu_io_req_bits_addr_0),\n .io_resp_bits_mxcpt_valid (io_lsu_io_req_bits_mxcpt_valid_0),\n .io_resp_bits_mxcpt_bits (io_lsu_io_req_bits_mxcpt_bits_0),\n .io_resp_bits_sfence_valid (io_lsu_io_req_bits_sfence_valid_0),\n .io_resp_bits_sfence_bits_rs1 (io_lsu_io_req_bits_sfence_bits_rs1_0),\n .io_resp_bits_sfence_bits_rs2 (io_lsu_io_req_bits_sfence_bits_rs2_0),\n .io_resp_bits_sfence_bits_addr (io_lsu_io_req_bits_sfence_bits_addr_0),\n .io_resp_bits_sfence_bits_asid (io_lsu_io_req_bits_sfence_bits_asid_0),\n .io_brupdate_b1_resolve_mask (io_brupdate_b1_resolve_mask_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b1_mispredict_mask (io_brupdate_b1_mispredict_mask_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_uopc (io_brupdate_b2_uop_uopc_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_inst (io_brupdate_b2_uop_inst_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_debug_inst (io_brupdate_b2_uop_debug_inst_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_is_rvc (io_brupdate_b2_uop_is_rvc_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_debug_pc (io_brupdate_b2_uop_debug_pc_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_iq_type (io_brupdate_b2_uop_iq_type_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_fu_code (io_brupdate_b2_uop_fu_code_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_ctrl_br_type (io_brupdate_b2_uop_ctrl_br_type_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_ctrl_op1_sel (io_brupdate_b2_uop_ctrl_op1_sel_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_ctrl_op2_sel (io_brupdate_b2_uop_ctrl_op2_sel_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_ctrl_imm_sel (io_brupdate_b2_uop_ctrl_imm_sel_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_ctrl_op_fcn (io_brupdate_b2_uop_ctrl_op_fcn_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_ctrl_fcn_dw (io_brupdate_b2_uop_ctrl_fcn_dw_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_ctrl_csr_cmd (io_brupdate_b2_uop_ctrl_csr_cmd_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_ctrl_is_load (io_brupdate_b2_uop_ctrl_is_load_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_ctrl_is_sta (io_brupdate_b2_uop_ctrl_is_sta_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_ctrl_is_std (io_brupdate_b2_uop_ctrl_is_std_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_iw_state (io_brupdate_b2_uop_iw_state_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_iw_p1_poisoned (io_brupdate_b2_uop_iw_p1_poisoned_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_iw_p2_poisoned (io_brupdate_b2_uop_iw_p2_poisoned_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_is_br (io_brupdate_b2_uop_is_br_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_is_jalr (io_brupdate_b2_uop_is_jalr_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_is_jal (io_brupdate_b2_uop_is_jal_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_is_sfb (io_brupdate_b2_uop_is_sfb_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_br_mask (io_brupdate_b2_uop_br_mask_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_br_tag (io_brupdate_b2_uop_br_tag_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_ftq_idx (io_brupdate_b2_uop_ftq_idx_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_edge_inst (io_brupdate_b2_uop_edge_inst_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_pc_lob (io_brupdate_b2_uop_pc_lob_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_taken (io_brupdate_b2_uop_taken_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_imm_packed (io_brupdate_b2_uop_imm_packed_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_csr_addr (io_brupdate_b2_uop_csr_addr_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_rob_idx (io_brupdate_b2_uop_rob_idx_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_ldq_idx (io_brupdate_b2_uop_ldq_idx_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_stq_idx (io_brupdate_b2_uop_stq_idx_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_rxq_idx (io_brupdate_b2_uop_rxq_idx_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_pdst (io_brupdate_b2_uop_pdst_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_prs1 (io_brupdate_b2_uop_prs1_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_prs2 (io_brupdate_b2_uop_prs2_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_prs3 (io_brupdate_b2_uop_prs3_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_ppred (io_brupdate_b2_uop_ppred_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_prs1_busy (io_brupdate_b2_uop_prs1_busy_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_prs2_busy (io_brupdate_b2_uop_prs2_busy_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_prs3_busy (io_brupdate_b2_uop_prs3_busy_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_ppred_busy (io_brupdate_b2_uop_ppred_busy_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_stale_pdst (io_brupdate_b2_uop_stale_pdst_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_exception (io_brupdate_b2_uop_exception_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_exc_cause (io_brupdate_b2_uop_exc_cause_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_bypassable (io_brupdate_b2_uop_bypassable_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_mem_cmd (io_brupdate_b2_uop_mem_cmd_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_mem_size (io_brupdate_b2_uop_mem_size_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_mem_signed (io_brupdate_b2_uop_mem_signed_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_is_fence (io_brupdate_b2_uop_is_fence_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_is_fencei (io_brupdate_b2_uop_is_fencei_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_is_amo (io_brupdate_b2_uop_is_amo_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_uses_ldq (io_brupdate_b2_uop_uses_ldq_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_uses_stq (io_brupdate_b2_uop_uses_stq_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_is_sys_pc2epc (io_brupdate_b2_uop_is_sys_pc2epc_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_is_unique (io_brupdate_b2_uop_is_unique_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_flush_on_commit (io_brupdate_b2_uop_flush_on_commit_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_ldst_is_rs1 (io_brupdate_b2_uop_ldst_is_rs1_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_ldst (io_brupdate_b2_uop_ldst_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_lrs1 (io_brupdate_b2_uop_lrs1_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_lrs2 (io_brupdate_b2_uop_lrs2_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_lrs3 (io_brupdate_b2_uop_lrs3_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_ldst_val (io_brupdate_b2_uop_ldst_val_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_dst_rtype (io_brupdate_b2_uop_dst_rtype_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_lrs1_rtype (io_brupdate_b2_uop_lrs1_rtype_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_lrs2_rtype (io_brupdate_b2_uop_lrs2_rtype_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_frs3_en (io_brupdate_b2_uop_frs3_en_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_fp_val (io_brupdate_b2_uop_fp_val_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_fp_single (io_brupdate_b2_uop_fp_single_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_xcpt_pf_if (io_brupdate_b2_uop_xcpt_pf_if_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_xcpt_ae_if (io_brupdate_b2_uop_xcpt_ae_if_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_xcpt_ma_if (io_brupdate_b2_uop_xcpt_ma_if_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_bp_debug_if (io_brupdate_b2_uop_bp_debug_if_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_bp_xcpt_if (io_brupdate_b2_uop_bp_xcpt_if_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_debug_fsrc (io_brupdate_b2_uop_debug_fsrc_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_uop_debug_tsrc (io_brupdate_b2_uop_debug_tsrc_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_valid (io_brupdate_b2_valid_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_mispredict (io_brupdate_b2_mispredict_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_taken (io_brupdate_b2_taken_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_cfi_type (io_brupdate_b2_cfi_type_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_pc_sel (io_brupdate_b2_pc_sel_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_jalr_target (io_brupdate_b2_jalr_target_0),\t// @[execution-unit.scala:204:7]\n .io_brupdate_b2_target_offset (io_brupdate_b2_target_offset_0),\t// @[execution-unit.scala:204:7]\n .io_status_debug (io_status_debug_0),\t// @[execution-unit.scala:204:7]\n .io_status_cease (io_status_cease_0),\t// @[execution-unit.scala:204:7]\n .io_status_wfi (io_status_wfi_0),\t// @[execution-unit.scala:204:7]\n .io_status_dprv (io_status_dprv_0),\t// @[execution-unit.scala:204:7]\n .io_status_dv (io_status_dv_0),\t// @[execution-unit.scala:204:7]\n .io_status_prv (io_status_prv_0),\t// @[execution-unit.scala:204:7]\n .io_status_v (io_status_v_0),\t// @[execution-unit.scala:204:7]\n .io_status_sd (io_status_sd_0),\t// @[execution-unit.scala:204:7]\n .io_status_mpv (io_status_mpv_0),\t// @[execution-unit.scala:204:7]\n .io_status_gva (io_status_gva_0),\t// @[execution-unit.scala:204:7]\n .io_status_tsr (io_status_tsr_0),\t// @[execution-unit.scala:204:7]\n .io_status_tw (io_status_tw_0),\t// @[execution-unit.scala:204:7]\n .io_status_tvm (io_status_tvm_0),\t// @[execution-unit.scala:204:7]\n .io_status_mxr (io_status_mxr_0),\t// @[execution-unit.scala:204:7]\n .io_status_sum (io_status_sum_0),\t// @[execution-unit.scala:204:7]\n .io_status_mprv (io_status_mprv_0),\t// @[execution-unit.scala:204:7]\n .io_status_fs (io_status_fs_0),\t// @[execution-unit.scala:204:7]\n .io_status_mpp (io_status_mpp_0),\t// @[execution-unit.scala:204:7]\n .io_status_spp (io_status_spp_0),\t// @[execution-unit.scala:204:7]\n .io_status_mpie (io_status_mpie_0),\t// @[execution-unit.scala:204:7]\n .io_status_spie (io_status_spie_0),\t// @[execution-unit.scala:204:7]\n .io_status_mie (io_status_mie_0),\t// @[execution-unit.scala:204:7]\n .io_status_sie (io_status_sie_0)\t// @[execution-unit.scala:204:7]\n );\t// @[execution-unit.scala:388:27]\n assign io_ll_iresp_valid = io_ll_iresp_valid_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_uopc = io_ll_iresp_bits_uop_uopc_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_inst = io_ll_iresp_bits_uop_inst_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_debug_inst = io_ll_iresp_bits_uop_debug_inst_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_is_rvc = io_ll_iresp_bits_uop_is_rvc_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_debug_pc = io_ll_iresp_bits_uop_debug_pc_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_iq_type = io_ll_iresp_bits_uop_iq_type_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_fu_code = io_ll_iresp_bits_uop_fu_code_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_ctrl_br_type = io_ll_iresp_bits_uop_ctrl_br_type_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_ctrl_op1_sel = io_ll_iresp_bits_uop_ctrl_op1_sel_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_ctrl_op2_sel = io_ll_iresp_bits_uop_ctrl_op2_sel_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_ctrl_imm_sel = io_ll_iresp_bits_uop_ctrl_imm_sel_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_ctrl_op_fcn = io_ll_iresp_bits_uop_ctrl_op_fcn_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_ctrl_fcn_dw = io_ll_iresp_bits_uop_ctrl_fcn_dw_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_ctrl_csr_cmd = io_ll_iresp_bits_uop_ctrl_csr_cmd_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_ctrl_is_load = io_ll_iresp_bits_uop_ctrl_is_load_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_ctrl_is_sta = io_ll_iresp_bits_uop_ctrl_is_sta_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_ctrl_is_std = io_ll_iresp_bits_uop_ctrl_is_std_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_iw_state = io_ll_iresp_bits_uop_iw_state_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_iw_p1_poisoned = io_ll_iresp_bits_uop_iw_p1_poisoned_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_iw_p2_poisoned = io_ll_iresp_bits_uop_iw_p2_poisoned_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_is_br = io_ll_iresp_bits_uop_is_br_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_is_jalr = io_ll_iresp_bits_uop_is_jalr_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_is_jal = io_ll_iresp_bits_uop_is_jal_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_is_sfb = io_ll_iresp_bits_uop_is_sfb_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_br_mask = io_ll_iresp_bits_uop_br_mask_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_br_tag = io_ll_iresp_bits_uop_br_tag_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_ftq_idx = io_ll_iresp_bits_uop_ftq_idx_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_edge_inst = io_ll_iresp_bits_uop_edge_inst_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_pc_lob = io_ll_iresp_bits_uop_pc_lob_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_taken = io_ll_iresp_bits_uop_taken_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_imm_packed = io_ll_iresp_bits_uop_imm_packed_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_csr_addr = io_ll_iresp_bits_uop_csr_addr_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_rob_idx = io_ll_iresp_bits_uop_rob_idx_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_ldq_idx = io_ll_iresp_bits_uop_ldq_idx_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_stq_idx = io_ll_iresp_bits_uop_stq_idx_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_rxq_idx = io_ll_iresp_bits_uop_rxq_idx_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_pdst = io_ll_iresp_bits_uop_pdst_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_prs1 = io_ll_iresp_bits_uop_prs1_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_prs2 = io_ll_iresp_bits_uop_prs2_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_prs3 = io_ll_iresp_bits_uop_prs3_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_ppred = io_ll_iresp_bits_uop_ppred_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_prs1_busy = io_ll_iresp_bits_uop_prs1_busy_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_prs2_busy = io_ll_iresp_bits_uop_prs2_busy_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_prs3_busy = io_ll_iresp_bits_uop_prs3_busy_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_ppred_busy = io_ll_iresp_bits_uop_ppred_busy_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_stale_pdst = io_ll_iresp_bits_uop_stale_pdst_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_exception = io_ll_iresp_bits_uop_exception_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_exc_cause = io_ll_iresp_bits_uop_exc_cause_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_bypassable = io_ll_iresp_bits_uop_bypassable_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_mem_cmd = io_ll_iresp_bits_uop_mem_cmd_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_mem_size = io_ll_iresp_bits_uop_mem_size_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_mem_signed = io_ll_iresp_bits_uop_mem_signed_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_is_fence = io_ll_iresp_bits_uop_is_fence_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_is_fencei = io_ll_iresp_bits_uop_is_fencei_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_is_amo = io_ll_iresp_bits_uop_is_amo_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_uses_ldq = io_ll_iresp_bits_uop_uses_ldq_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_uses_stq = io_ll_iresp_bits_uop_uses_stq_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_is_sys_pc2epc = io_ll_iresp_bits_uop_is_sys_pc2epc_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_is_unique = io_ll_iresp_bits_uop_is_unique_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_flush_on_commit = io_ll_iresp_bits_uop_flush_on_commit_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_ldst_is_rs1 = io_ll_iresp_bits_uop_ldst_is_rs1_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_ldst = io_ll_iresp_bits_uop_ldst_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_lrs1 = io_ll_iresp_bits_uop_lrs1_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_lrs2 = io_ll_iresp_bits_uop_lrs2_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_lrs3 = io_ll_iresp_bits_uop_lrs3_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_ldst_val = io_ll_iresp_bits_uop_ldst_val_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_dst_rtype = io_ll_iresp_bits_uop_dst_rtype_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_lrs1_rtype = io_ll_iresp_bits_uop_lrs1_rtype_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_lrs2_rtype = io_ll_iresp_bits_uop_lrs2_rtype_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_frs3_en = io_ll_iresp_bits_uop_frs3_en_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_fp_val = io_ll_iresp_bits_uop_fp_val_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_fp_single = io_ll_iresp_bits_uop_fp_single_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_xcpt_pf_if = io_ll_iresp_bits_uop_xcpt_pf_if_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_xcpt_ae_if = io_ll_iresp_bits_uop_xcpt_ae_if_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_xcpt_ma_if = io_ll_iresp_bits_uop_xcpt_ma_if_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_bp_debug_if = io_ll_iresp_bits_uop_bp_debug_if_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_bp_xcpt_if = io_ll_iresp_bits_uop_bp_xcpt_if_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_debug_fsrc = io_ll_iresp_bits_uop_debug_fsrc_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_uop_debug_tsrc = io_ll_iresp_bits_uop_debug_tsrc_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_iresp_bits_data = io_ll_iresp_bits_data_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_valid = io_ll_fresp_valid_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_uopc = io_ll_fresp_bits_uop_uopc_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_inst = io_ll_fresp_bits_uop_inst_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_debug_inst = io_ll_fresp_bits_uop_debug_inst_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_is_rvc = io_ll_fresp_bits_uop_is_rvc_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_debug_pc = io_ll_fresp_bits_uop_debug_pc_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_iq_type = io_ll_fresp_bits_uop_iq_type_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_fu_code = io_ll_fresp_bits_uop_fu_code_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_ctrl_br_type = io_ll_fresp_bits_uop_ctrl_br_type_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_ctrl_op1_sel = io_ll_fresp_bits_uop_ctrl_op1_sel_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_ctrl_op2_sel = io_ll_fresp_bits_uop_ctrl_op2_sel_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_ctrl_imm_sel = io_ll_fresp_bits_uop_ctrl_imm_sel_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_ctrl_op_fcn = io_ll_fresp_bits_uop_ctrl_op_fcn_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_ctrl_fcn_dw = io_ll_fresp_bits_uop_ctrl_fcn_dw_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_ctrl_csr_cmd = io_ll_fresp_bits_uop_ctrl_csr_cmd_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_ctrl_is_load = io_ll_fresp_bits_uop_ctrl_is_load_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_ctrl_is_sta = io_ll_fresp_bits_uop_ctrl_is_sta_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_ctrl_is_std = io_ll_fresp_bits_uop_ctrl_is_std_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_iw_state = io_ll_fresp_bits_uop_iw_state_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_iw_p1_poisoned = io_ll_fresp_bits_uop_iw_p1_poisoned_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_iw_p2_poisoned = io_ll_fresp_bits_uop_iw_p2_poisoned_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_is_br = io_ll_fresp_bits_uop_is_br_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_is_jalr = io_ll_fresp_bits_uop_is_jalr_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_is_jal = io_ll_fresp_bits_uop_is_jal_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_is_sfb = io_ll_fresp_bits_uop_is_sfb_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_br_mask = io_ll_fresp_bits_uop_br_mask_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_br_tag = io_ll_fresp_bits_uop_br_tag_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_ftq_idx = io_ll_fresp_bits_uop_ftq_idx_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_edge_inst = io_ll_fresp_bits_uop_edge_inst_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_pc_lob = io_ll_fresp_bits_uop_pc_lob_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_taken = io_ll_fresp_bits_uop_taken_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_imm_packed = io_ll_fresp_bits_uop_imm_packed_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_csr_addr = io_ll_fresp_bits_uop_csr_addr_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_rob_idx = io_ll_fresp_bits_uop_rob_idx_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_ldq_idx = io_ll_fresp_bits_uop_ldq_idx_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_stq_idx = io_ll_fresp_bits_uop_stq_idx_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_rxq_idx = io_ll_fresp_bits_uop_rxq_idx_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_pdst = io_ll_fresp_bits_uop_pdst_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_prs1 = io_ll_fresp_bits_uop_prs1_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_prs2 = io_ll_fresp_bits_uop_prs2_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_prs3 = io_ll_fresp_bits_uop_prs3_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_ppred = io_ll_fresp_bits_uop_ppred_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_prs1_busy = io_ll_fresp_bits_uop_prs1_busy_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_prs2_busy = io_ll_fresp_bits_uop_prs2_busy_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_prs3_busy = io_ll_fresp_bits_uop_prs3_busy_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_ppred_busy = io_ll_fresp_bits_uop_ppred_busy_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_stale_pdst = io_ll_fresp_bits_uop_stale_pdst_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_exception = io_ll_fresp_bits_uop_exception_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_exc_cause = io_ll_fresp_bits_uop_exc_cause_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_bypassable = io_ll_fresp_bits_uop_bypassable_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_mem_cmd = io_ll_fresp_bits_uop_mem_cmd_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_mem_size = io_ll_fresp_bits_uop_mem_size_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_mem_signed = io_ll_fresp_bits_uop_mem_signed_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_is_fence = io_ll_fresp_bits_uop_is_fence_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_is_fencei = io_ll_fresp_bits_uop_is_fencei_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_is_amo = io_ll_fresp_bits_uop_is_amo_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_uses_ldq = io_ll_fresp_bits_uop_uses_ldq_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_uses_stq = io_ll_fresp_bits_uop_uses_stq_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_is_sys_pc2epc = io_ll_fresp_bits_uop_is_sys_pc2epc_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_is_unique = io_ll_fresp_bits_uop_is_unique_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_flush_on_commit = io_ll_fresp_bits_uop_flush_on_commit_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_ldst_is_rs1 = io_ll_fresp_bits_uop_ldst_is_rs1_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_ldst = io_ll_fresp_bits_uop_ldst_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_lrs1 = io_ll_fresp_bits_uop_lrs1_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_lrs2 = io_ll_fresp_bits_uop_lrs2_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_lrs3 = io_ll_fresp_bits_uop_lrs3_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_ldst_val = io_ll_fresp_bits_uop_ldst_val_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_dst_rtype = io_ll_fresp_bits_uop_dst_rtype_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_lrs1_rtype = io_ll_fresp_bits_uop_lrs1_rtype_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_lrs2_rtype = io_ll_fresp_bits_uop_lrs2_rtype_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_frs3_en = io_ll_fresp_bits_uop_frs3_en_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_fp_val = io_ll_fresp_bits_uop_fp_val_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_fp_single = io_ll_fresp_bits_uop_fp_single_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_xcpt_pf_if = io_ll_fresp_bits_uop_xcpt_pf_if_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_xcpt_ae_if = io_ll_fresp_bits_uop_xcpt_ae_if_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_xcpt_ma_if = io_ll_fresp_bits_uop_xcpt_ma_if_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_bp_debug_if = io_ll_fresp_bits_uop_bp_debug_if_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_bp_xcpt_if = io_ll_fresp_bits_uop_bp_xcpt_if_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_debug_fsrc = io_ll_fresp_bits_uop_debug_fsrc_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_uop_debug_tsrc = io_ll_fresp_bits_uop_debug_tsrc_0;\t// @[execution-unit.scala:204:7]\n assign io_ll_fresp_bits_data = io_ll_fresp_bits_data_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_valid = io_lsu_io_req_valid_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_uopc = io_lsu_io_req_bits_uop_uopc_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_inst = io_lsu_io_req_bits_uop_inst_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_debug_inst = io_lsu_io_req_bits_uop_debug_inst_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_is_rvc = io_lsu_io_req_bits_uop_is_rvc_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_debug_pc = io_lsu_io_req_bits_uop_debug_pc_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_iq_type = io_lsu_io_req_bits_uop_iq_type_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_fu_code = io_lsu_io_req_bits_uop_fu_code_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_ctrl_br_type = io_lsu_io_req_bits_uop_ctrl_br_type_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_ctrl_op1_sel = io_lsu_io_req_bits_uop_ctrl_op1_sel_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_ctrl_op2_sel = io_lsu_io_req_bits_uop_ctrl_op2_sel_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_ctrl_imm_sel = io_lsu_io_req_bits_uop_ctrl_imm_sel_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_ctrl_op_fcn = io_lsu_io_req_bits_uop_ctrl_op_fcn_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_ctrl_fcn_dw = io_lsu_io_req_bits_uop_ctrl_fcn_dw_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_ctrl_csr_cmd = io_lsu_io_req_bits_uop_ctrl_csr_cmd_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_ctrl_is_load = io_lsu_io_req_bits_uop_ctrl_is_load_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_ctrl_is_sta = io_lsu_io_req_bits_uop_ctrl_is_sta_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_ctrl_is_std = io_lsu_io_req_bits_uop_ctrl_is_std_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_iw_state = io_lsu_io_req_bits_uop_iw_state_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_iw_p1_poisoned = io_lsu_io_req_bits_uop_iw_p1_poisoned_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_iw_p2_poisoned = io_lsu_io_req_bits_uop_iw_p2_poisoned_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_is_br = io_lsu_io_req_bits_uop_is_br_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_is_jalr = io_lsu_io_req_bits_uop_is_jalr_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_is_jal = io_lsu_io_req_bits_uop_is_jal_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_is_sfb = io_lsu_io_req_bits_uop_is_sfb_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_br_mask = io_lsu_io_req_bits_uop_br_mask_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_br_tag = io_lsu_io_req_bits_uop_br_tag_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_ftq_idx = io_lsu_io_req_bits_uop_ftq_idx_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_edge_inst = io_lsu_io_req_bits_uop_edge_inst_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_pc_lob = io_lsu_io_req_bits_uop_pc_lob_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_taken = io_lsu_io_req_bits_uop_taken_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_imm_packed = io_lsu_io_req_bits_uop_imm_packed_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_csr_addr = io_lsu_io_req_bits_uop_csr_addr_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_rob_idx = io_lsu_io_req_bits_uop_rob_idx_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_ldq_idx = io_lsu_io_req_bits_uop_ldq_idx_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_stq_idx = io_lsu_io_req_bits_uop_stq_idx_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_rxq_idx = io_lsu_io_req_bits_uop_rxq_idx_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_pdst = io_lsu_io_req_bits_uop_pdst_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_prs1 = io_lsu_io_req_bits_uop_prs1_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_prs2 = io_lsu_io_req_bits_uop_prs2_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_prs3 = io_lsu_io_req_bits_uop_prs3_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_ppred = io_lsu_io_req_bits_uop_ppred_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_prs1_busy = io_lsu_io_req_bits_uop_prs1_busy_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_prs2_busy = io_lsu_io_req_bits_uop_prs2_busy_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_prs3_busy = io_lsu_io_req_bits_uop_prs3_busy_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_ppred_busy = io_lsu_io_req_bits_uop_ppred_busy_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_stale_pdst = io_lsu_io_req_bits_uop_stale_pdst_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_exception = io_lsu_io_req_bits_uop_exception_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_exc_cause = io_lsu_io_req_bits_uop_exc_cause_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_bypassable = io_lsu_io_req_bits_uop_bypassable_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_mem_cmd = io_lsu_io_req_bits_uop_mem_cmd_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_mem_size = io_lsu_io_req_bits_uop_mem_size_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_mem_signed = io_lsu_io_req_bits_uop_mem_signed_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_is_fence = io_lsu_io_req_bits_uop_is_fence_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_is_fencei = io_lsu_io_req_bits_uop_is_fencei_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_is_amo = io_lsu_io_req_bits_uop_is_amo_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_uses_ldq = io_lsu_io_req_bits_uop_uses_ldq_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_uses_stq = io_lsu_io_req_bits_uop_uses_stq_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_is_sys_pc2epc = io_lsu_io_req_bits_uop_is_sys_pc2epc_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_is_unique = io_lsu_io_req_bits_uop_is_unique_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_flush_on_commit = io_lsu_io_req_bits_uop_flush_on_commit_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_ldst_is_rs1 = io_lsu_io_req_bits_uop_ldst_is_rs1_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_ldst = io_lsu_io_req_bits_uop_ldst_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_lrs1 = io_lsu_io_req_bits_uop_lrs1_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_lrs2 = io_lsu_io_req_bits_uop_lrs2_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_lrs3 = io_lsu_io_req_bits_uop_lrs3_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_ldst_val = io_lsu_io_req_bits_uop_ldst_val_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_dst_rtype = io_lsu_io_req_bits_uop_dst_rtype_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_lrs1_rtype = io_lsu_io_req_bits_uop_lrs1_rtype_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_lrs2_rtype = io_lsu_io_req_bits_uop_lrs2_rtype_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_frs3_en = io_lsu_io_req_bits_uop_frs3_en_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_fp_val = io_lsu_io_req_bits_uop_fp_val_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_fp_single = io_lsu_io_req_bits_uop_fp_single_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_xcpt_pf_if = io_lsu_io_req_bits_uop_xcpt_pf_if_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_xcpt_ae_if = io_lsu_io_req_bits_uop_xcpt_ae_if_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_xcpt_ma_if = io_lsu_io_req_bits_uop_xcpt_ma_if_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_bp_debug_if = io_lsu_io_req_bits_uop_bp_debug_if_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_bp_xcpt_if = io_lsu_io_req_bits_uop_bp_xcpt_if_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_debug_fsrc = io_lsu_io_req_bits_uop_debug_fsrc_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_uop_debug_tsrc = io_lsu_io_req_bits_uop_debug_tsrc_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_data = io_lsu_io_req_bits_data_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_addr = io_lsu_io_req_bits_addr_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_mxcpt_valid = io_lsu_io_req_bits_mxcpt_valid_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_mxcpt_bits = io_lsu_io_req_bits_mxcpt_bits_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_sfence_valid = io_lsu_io_req_bits_sfence_valid_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_sfence_bits_rs1 = io_lsu_io_req_bits_sfence_bits_rs1_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_sfence_bits_rs2 = io_lsu_io_req_bits_sfence_bits_rs2_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_sfence_bits_addr = io_lsu_io_req_bits_sfence_bits_addr_0;\t// @[execution-unit.scala:204:7]\n assign io_lsu_io_req_bits_sfence_bits_asid = io_lsu_io_req_bits_sfence_bits_asid_0;\t// @[execution-unit.scala:204:7]\nendmodule"}}},{"rowIdx":34192,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module TLXbar_i2_o1_a32d128s5k4z4u : \n input clock : Clock \n input reset : Reset \n output auto : { flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}} \n\n\n wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}} \n invalidate anonIn.d.bits.corrupt \n invalidate anonIn.d.bits.data \n invalidate anonIn.d.bits.denied \n invalidate anonIn.d.bits.sink \n invalidate anonIn.d.bits.source \n invalidate anonIn.d.bits.size \n invalidate anonIn.d.bits.param \n invalidate anonIn.d.bits.opcode \n invalidate anonIn.d.valid \n invalidate anonIn.d.ready \n invalidate anonIn.a.bits.corrupt \n invalidate anonIn.a.bits.data \n invalidate anonIn.a.bits.mask \n invalidate anonIn.a.bits.address \n invalidate anonIn.a.bits.source \n invalidate anonIn.a.bits.size \n invalidate anonIn.a.bits.param \n invalidate anonIn.a.bits.opcode \n invalidate anonIn.a.valid \n invalidate anonIn.a.ready \n wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}} \n invalidate anonIn_1.d.bits.corrupt \n invalidate anonIn_1.d.bits.data \n invalidate anonIn_1.d.bits.denied \n invalidate anonIn_1.d.bits.sink \n invalidate anonIn_1.d.bits.source \n invalidate anonIn_1.d.bits.size \n invalidate anonIn_1.d.bits.param \n invalidate anonIn_1.d.bits.opcode \n invalidate anonIn_1.d.valid \n invalidate anonIn_1.d.ready \n invalidate anonIn_1.a.bits.corrupt \n invalidate anonIn_1.a.bits.data \n invalidate anonIn_1.a.bits.mask \n invalidate anonIn_1.a.bits.address \n invalidate anonIn_1.a.bits.source \n invalidate anonIn_1.a.bits.size \n invalidate anonIn_1.a.bits.param \n invalidate anonIn_1.a.bits.opcode \n invalidate anonIn_1.a.valid \n invalidate anonIn_1.a.ready \n inst monitor of TLMonitor_43 \n connect monitor.clock, clock\n\n connect monitor.reset, reset\n\n connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt \n connect monitor.io.in.d.bits.data, anonIn.d.bits.data \n connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied \n connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink \n connect monitor.io.in.d.bits.source, anonIn.d.bits.source \n connect monitor.io.in.d.bits.size, anonIn.d.bits.size \n connect monitor.io.in.d.bits.param, anonIn.d.bits.param \n connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode \n connect monitor.io.in.d.valid, anonIn.d.valid \n connect monitor.io.in.d.ready, anonIn.d.ready \n connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt \n connect monitor.io.in.a.bits.data, anonIn.a.bits.data \n connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask \n connect monitor.io.in.a.bits.address, anonIn.a.bits.address \n connect monitor.io.in.a.bits.source, anonIn.a.bits.source \n connect monitor.io.in.a.bits.size, anonIn.a.bits.size \n connect monitor.io.in.a.bits.param, anonIn.a.bits.param \n connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode \n connect monitor.io.in.a.valid, anonIn.a.valid \n connect monitor.io.in.a.ready, anonIn.a.ready \n inst monitor_1 of TLMonitor_44 \n connect monitor_1.clock, clock\n\n connect monitor_1.reset, reset\n\n connect monitor_1.io.in.d.bits.corrupt, anonIn_1.d.bits.corrupt \n connect monitor_1.io.in.d.bits.data, anonIn_1.d.bits.data \n connect monitor_1.io.in.d.bits.denied, anonIn_1.d.bits.denied \n connect monitor_1.io.in.d.bits.sink, anonIn_1.d.bits.sink \n connect monitor_1.io.in.d.bits.source, anonIn_1.d.bits.source \n connect monitor_1.io.in.d.bits.size, anonIn_1.d.bits.size \n connect monitor_1.io.in.d.bits.param, anonIn_1.d.bits.param \n connect monitor_1.io.in.d.bits.opcode, anonIn_1.d.bits.opcode \n connect monitor_1.io.in.d.valid, anonIn_1.d.valid \n connect monitor_1.io.in.d.ready, anonIn_1.d.ready \n connect monitor_1.io.in.a.bits.corrupt, anonIn_1.a.bits.corrupt \n connect monitor_1.io.in.a.bits.data, anonIn_1.a.bits.data \n connect monitor_1.io.in.a.bits.mask, anonIn_1.a.bits.mask \n connect monitor_1.io.in.a.bits.address, anonIn_1.a.bits.address \n connect monitor_1.io.in.a.bits.source, anonIn_1.a.bits.source \n connect monitor_1.io.in.a.bits.size, anonIn_1.a.bits.size \n connect monitor_1.io.in.a.bits.param, anonIn_1.a.bits.param \n connect monitor_1.io.in.a.bits.opcode, anonIn_1.a.bits.opcode \n connect monitor_1.io.in.a.valid, anonIn_1.a.valid \n connect monitor_1.io.in.a.ready, anonIn_1.a.ready \n wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}} \n invalidate anonOut.d.bits.corrupt \n invalidate anonOut.d.bits.data \n invalidate anonOut.d.bits.denied \n invalidate anonOut.d.bits.sink \n invalidate anonOut.d.bits.source \n invalidate anonOut.d.bits.size \n invalidate anonOut.d.bits.param \n invalidate anonOut.d.bits.opcode \n invalidate anonOut.d.valid \n invalidate anonOut.d.ready \n invalidate anonOut.a.bits.corrupt \n invalidate anonOut.a.bits.data \n invalidate anonOut.a.bits.mask \n invalidate anonOut.a.bits.address \n invalidate anonOut.a.bits.source \n invalidate anonOut.a.bits.size \n invalidate anonOut.a.bits.param \n invalidate anonOut.a.bits.opcode \n invalidate anonOut.a.valid \n invalidate anonOut.a.ready \n connect auto.anon_out, anonOut \n connect anonIn, auto.anon_in_0 \n connect anonIn_1, auto.anon_in_1 \n wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}[2] \n connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt \n connect in[0].a.bits.data, anonIn.a.bits.data \n connect in[0].a.bits.mask, anonIn.a.bits.mask \n connect in[0].a.bits.address, anonIn.a.bits.address \n connect in[0].a.bits.source, anonIn.a.bits.source \n connect in[0].a.bits.size, anonIn.a.bits.size \n connect in[0].a.bits.param, anonIn.a.bits.param \n connect in[0].a.bits.opcode, anonIn.a.bits.opcode \n connect in[0].a.valid, anonIn.a.valid \n connect anonIn.a.ready, in[0].a.ready \n node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<5>(0h10)) \n connect in[0].a.bits.source, _in_0_a_bits_source_T \n wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE.bits.corrupt, UInt<1>(0h0) \n connect _WIRE.bits.data, UInt<128>(0h0) \n connect _WIRE.bits.mask, UInt<16>(0h0) \n connect _WIRE.bits.address, UInt<32>(0h0) \n connect _WIRE.bits.source, UInt<5>(0h0) \n connect _WIRE.bits.size, UInt<4>(0h0) \n connect _WIRE.bits.param, UInt<2>(0h0) \n connect _WIRE.bits.opcode, UInt<3>(0h0) \n connect _WIRE.valid, UInt<1>(0h0) \n connect _WIRE.ready, UInt<1>(0h0) \n wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_1.bits, _WIRE.bits \n connect _WIRE_1.valid, _WIRE.valid \n connect _WIRE_1.ready, _WIRE.ready \n invalidate _WIRE_1.bits.corrupt \n invalidate _WIRE_1.bits.data \n invalidate _WIRE_1.bits.mask \n invalidate _WIRE_1.bits.address \n invalidate _WIRE_1.bits.source \n invalidate _WIRE_1.bits.size \n invalidate _WIRE_1.bits.param \n invalidate _WIRE_1.bits.opcode \n invalidate _WIRE_1.valid \n invalidate _WIRE_1.ready \n wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_2.bits.data, UInt<128>(0h0) \n connect _WIRE_2.bits.mask, UInt<16>(0h0) \n connect _WIRE_2.bits.address, UInt<32>(0h0) \n connect _WIRE_2.bits.source, UInt<4>(0h0) \n connect _WIRE_2.bits.size, UInt<4>(0h0) \n connect _WIRE_2.bits.param, UInt<2>(0h0) \n connect _WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _WIRE_2.valid, UInt<1>(0h0) \n connect _WIRE_2.ready, UInt<1>(0h0) \n wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_3.bits, _WIRE_2.bits \n connect _WIRE_3.valid, _WIRE_2.valid \n connect _WIRE_3.ready, _WIRE_2.ready \n invalidate _WIRE_3.bits.corrupt \n invalidate _WIRE_3.bits.data \n invalidate _WIRE_3.bits.mask \n invalidate _WIRE_3.bits.address \n invalidate _WIRE_3.bits.source \n invalidate _WIRE_3.bits.size \n invalidate _WIRE_3.bits.param \n invalidate _WIRE_3.bits.opcode \n invalidate _WIRE_3.valid \n invalidate _WIRE_3.ready \n wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_4.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_4.bits.data, UInt<128>(0h0) \n connect _WIRE_4.bits.mask, UInt<16>(0h0) \n connect _WIRE_4.bits.address, UInt<32>(0h0) \n connect _WIRE_4.bits.source, UInt<5>(0h0) \n connect _WIRE_4.bits.size, UInt<4>(0h0) \n connect _WIRE_4.bits.param, UInt<2>(0h0) \n connect _WIRE_4.bits.opcode, UInt<3>(0h0) \n connect _WIRE_4.valid, UInt<1>(0h0) \n connect _WIRE_4.ready, UInt<1>(0h0) \n wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_5.bits, _WIRE_4.bits \n connect _WIRE_5.valid, _WIRE_4.valid \n connect _WIRE_5.ready, _WIRE_4.ready \n connect _WIRE_5.ready, UInt<1>(0h1) \n wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_6.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_6.bits.data, UInt<128>(0h0) \n connect _WIRE_6.bits.mask, UInt<16>(0h0) \n connect _WIRE_6.bits.address, UInt<32>(0h0) \n connect _WIRE_6.bits.source, UInt<4>(0h0) \n connect _WIRE_6.bits.size, UInt<4>(0h0) \n connect _WIRE_6.bits.param, UInt<2>(0h0) \n connect _WIRE_6.bits.opcode, UInt<3>(0h0) \n connect _WIRE_6.valid, UInt<1>(0h0) \n connect _WIRE_6.ready, UInt<1>(0h0) \n wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_7.bits, _WIRE_6.bits \n connect _WIRE_7.valid, _WIRE_6.valid \n connect _WIRE_7.ready, _WIRE_6.ready \n connect _WIRE_7.valid, UInt<1>(0h0) \n wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_8.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_8.bits.data, UInt<128>(0h0) \n connect _WIRE_8.bits.address, UInt<32>(0h0) \n connect _WIRE_8.bits.source, UInt<5>(0h0) \n connect _WIRE_8.bits.size, UInt<4>(0h0) \n connect _WIRE_8.bits.param, UInt<3>(0h0) \n connect _WIRE_8.bits.opcode, UInt<3>(0h0) \n connect _WIRE_8.valid, UInt<1>(0h0) \n connect _WIRE_8.ready, UInt<1>(0h0) \n wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_9.bits, _WIRE_8.bits \n connect _WIRE_9.valid, _WIRE_8.valid \n connect _WIRE_9.ready, _WIRE_8.ready \n invalidate _WIRE_9.bits.corrupt \n invalidate _WIRE_9.bits.data \n invalidate _WIRE_9.bits.address \n invalidate _WIRE_9.bits.source \n invalidate _WIRE_9.bits.size \n invalidate _WIRE_9.bits.param \n invalidate _WIRE_9.bits.opcode \n invalidate _WIRE_9.valid \n invalidate _WIRE_9.ready \n wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_10.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_10.bits.data, UInt<128>(0h0) \n connect _WIRE_10.bits.address, UInt<32>(0h0) \n connect _WIRE_10.bits.source, UInt<4>(0h0) \n connect _WIRE_10.bits.size, UInt<4>(0h0) \n connect _WIRE_10.bits.param, UInt<3>(0h0) \n connect _WIRE_10.bits.opcode, UInt<3>(0h0) \n connect _WIRE_10.valid, UInt<1>(0h0) \n connect _WIRE_10.ready, UInt<1>(0h0) \n wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_11.bits, _WIRE_10.bits \n connect _WIRE_11.valid, _WIRE_10.valid \n connect _WIRE_11.ready, _WIRE_10.ready \n invalidate _WIRE_11.bits.corrupt \n invalidate _WIRE_11.bits.data \n invalidate _WIRE_11.bits.address \n invalidate _WIRE_11.bits.source \n invalidate _WIRE_11.bits.size \n invalidate _WIRE_11.bits.param \n invalidate _WIRE_11.bits.opcode \n invalidate _WIRE_11.valid \n invalidate _WIRE_11.ready \n wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_12.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_12.bits.data, UInt<128>(0h0) \n connect _WIRE_12.bits.address, UInt<32>(0h0) \n connect _WIRE_12.bits.source, UInt<5>(0h0) \n connect _WIRE_12.bits.size, UInt<4>(0h0) \n connect _WIRE_12.bits.param, UInt<3>(0h0) \n connect _WIRE_12.bits.opcode, UInt<3>(0h0) \n connect _WIRE_12.valid, UInt<1>(0h0) \n connect _WIRE_12.ready, UInt<1>(0h0) \n wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_13.bits, _WIRE_12.bits \n connect _WIRE_13.valid, _WIRE_12.valid \n connect _WIRE_13.ready, _WIRE_12.ready \n connect _WIRE_13.valid, UInt<1>(0h0) \n wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_14.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_14.bits.data, UInt<128>(0h0) \n connect _WIRE_14.bits.address, UInt<32>(0h0) \n connect _WIRE_14.bits.source, UInt<4>(0h0) \n connect _WIRE_14.bits.size, UInt<4>(0h0) \n connect _WIRE_14.bits.param, UInt<3>(0h0) \n connect _WIRE_14.bits.opcode, UInt<3>(0h0) \n connect _WIRE_14.valid, UInt<1>(0h0) \n connect _WIRE_14.ready, UInt<1>(0h0) \n wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_15.bits, _WIRE_14.bits \n connect _WIRE_15.valid, _WIRE_14.valid \n connect _WIRE_15.ready, _WIRE_14.ready \n connect _WIRE_15.ready, UInt<1>(0h1) \n connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt \n connect anonIn.d.bits.data, in[0].d.bits.data \n connect anonIn.d.bits.denied, in[0].d.bits.denied \n connect anonIn.d.bits.sink, in[0].d.bits.sink \n connect anonIn.d.bits.source, in[0].d.bits.source \n connect anonIn.d.bits.size, in[0].d.bits.size \n connect anonIn.d.bits.param, in[0].d.bits.param \n connect anonIn.d.bits.opcode, in[0].d.bits.opcode \n connect anonIn.d.valid, in[0].d.valid \n connect in[0].d.ready, anonIn.d.ready \n node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 3, 0) \n connect anonIn.d.bits.source, _anonIn_d_bits_source_T \n wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _WIRE_16.bits.sink, UInt<4>(0h0) \n connect _WIRE_16.valid, UInt<1>(0h0) \n connect _WIRE_16.ready, UInt<1>(0h0) \n wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _WIRE_17.bits, _WIRE_16.bits \n connect _WIRE_17.valid, _WIRE_16.valid \n connect _WIRE_17.ready, _WIRE_16.ready \n invalidate _WIRE_17.bits.sink \n invalidate _WIRE_17.valid \n invalidate _WIRE_17.ready \n wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _WIRE_18.bits.sink, UInt<4>(0h0) \n connect _WIRE_18.valid, UInt<1>(0h0) \n connect _WIRE_18.ready, UInt<1>(0h0) \n wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _WIRE_19.bits, _WIRE_18.bits \n connect _WIRE_19.valid, _WIRE_18.valid \n connect _WIRE_19.ready, _WIRE_18.ready \n invalidate _WIRE_19.bits.sink \n invalidate _WIRE_19.valid \n invalidate _WIRE_19.ready \n wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _WIRE_20.bits.sink, UInt<4>(0h0) \n connect _WIRE_20.valid, UInt<1>(0h0) \n connect _WIRE_20.ready, UInt<1>(0h0) \n wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _WIRE_21.bits, _WIRE_20.bits \n connect _WIRE_21.valid, _WIRE_20.valid \n connect _WIRE_21.ready, _WIRE_20.ready \n connect _WIRE_21.valid, UInt<1>(0h0) \n wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _WIRE_22.bits.sink, UInt<4>(0h0) \n connect _WIRE_22.valid, UInt<1>(0h0) \n connect _WIRE_22.ready, UInt<1>(0h0) \n wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _WIRE_23.bits, _WIRE_22.bits \n connect _WIRE_23.valid, _WIRE_22.valid \n connect _WIRE_23.ready, _WIRE_22.ready \n connect _WIRE_23.ready, UInt<1>(0h1) \n connect in[1].a.bits.corrupt, anonIn_1.a.bits.corrupt \n connect in[1].a.bits.data, anonIn_1.a.bits.data \n connect in[1].a.bits.mask, anonIn_1.a.bits.mask \n connect in[1].a.bits.address, anonIn_1.a.bits.address \n connect in[1].a.bits.source, anonIn_1.a.bits.source \n connect in[1].a.bits.size, anonIn_1.a.bits.size \n connect in[1].a.bits.param, anonIn_1.a.bits.param \n connect in[1].a.bits.opcode, anonIn_1.a.bits.opcode \n connect in[1].a.valid, anonIn_1.a.valid \n connect anonIn_1.a.ready, in[1].a.ready \n node _in_1_a_bits_source_T = or(anonIn_1.a.bits.source, UInt<1>(0h0)) \n connect in[1].a.bits.source, _in_1_a_bits_source_T \n wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_24.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_24.bits.data, UInt<128>(0h0) \n connect _WIRE_24.bits.mask, UInt<16>(0h0) \n connect _WIRE_24.bits.address, UInt<32>(0h0) \n connect _WIRE_24.bits.source, UInt<5>(0h0) \n connect _WIRE_24.bits.size, UInt<4>(0h0) \n connect _WIRE_24.bits.param, UInt<2>(0h0) \n connect _WIRE_24.bits.opcode, UInt<3>(0h0) \n connect _WIRE_24.valid, UInt<1>(0h0) \n connect _WIRE_24.ready, UInt<1>(0h0) \n wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_25.bits, _WIRE_24.bits \n connect _WIRE_25.valid, _WIRE_24.valid \n connect _WIRE_25.ready, _WIRE_24.ready \n invalidate _WIRE_25.bits.corrupt \n invalidate _WIRE_25.bits.data \n invalidate _WIRE_25.bits.mask \n invalidate _WIRE_25.bits.address \n invalidate _WIRE_25.bits.source \n invalidate _WIRE_25.bits.size \n invalidate _WIRE_25.bits.param \n invalidate _WIRE_25.bits.opcode \n invalidate _WIRE_25.valid \n invalidate _WIRE_25.ready \n wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_26.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_26.bits.data, UInt<128>(0h0) \n connect _WIRE_26.bits.mask, UInt<16>(0h0) \n connect _WIRE_26.bits.address, UInt<32>(0h0) \n connect _WIRE_26.bits.source, UInt<4>(0h0) \n connect _WIRE_26.bits.size, UInt<4>(0h0) \n connect _WIRE_26.bits.param, UInt<2>(0h0) \n connect _WIRE_26.bits.opcode, UInt<3>(0h0) \n connect _WIRE_26.valid, UInt<1>(0h0) \n connect _WIRE_26.ready, UInt<1>(0h0) \n wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_27.bits, _WIRE_26.bits \n connect _WIRE_27.valid, _WIRE_26.valid \n connect _WIRE_27.ready, _WIRE_26.ready \n invalidate _WIRE_27.bits.corrupt \n invalidate _WIRE_27.bits.data \n invalidate _WIRE_27.bits.mask \n invalidate _WIRE_27.bits.address \n invalidate _WIRE_27.bits.source \n invalidate _WIRE_27.bits.size \n invalidate _WIRE_27.bits.param \n invalidate _WIRE_27.bits.opcode \n invalidate _WIRE_27.valid \n invalidate _WIRE_27.ready \n wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_28.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_28.bits.data, UInt<128>(0h0) \n connect _WIRE_28.bits.mask, UInt<16>(0h0) \n connect _WIRE_28.bits.address, UInt<32>(0h0) \n connect _WIRE_28.bits.source, UInt<5>(0h0) \n connect _WIRE_28.bits.size, UInt<4>(0h0) \n connect _WIRE_28.bits.param, UInt<2>(0h0) \n connect _WIRE_28.bits.opcode, UInt<3>(0h0) \n connect _WIRE_28.valid, UInt<1>(0h0) \n connect _WIRE_28.ready, UInt<1>(0h0) \n wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_29.bits, _WIRE_28.bits \n connect _WIRE_29.valid, _WIRE_28.valid \n connect _WIRE_29.ready, _WIRE_28.ready \n connect _WIRE_29.ready, UInt<1>(0h1) \n wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_30.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_30.bits.data, UInt<128>(0h0) \n connect _WIRE_30.bits.mask, UInt<16>(0h0) \n connect _WIRE_30.bits.address, UInt<32>(0h0) \n connect _WIRE_30.bits.source, UInt<4>(0h0) \n connect _WIRE_30.bits.size, UInt<4>(0h0) \n connect _WIRE_30.bits.param, UInt<2>(0h0) \n connect _WIRE_30.bits.opcode, UInt<3>(0h0) \n connect _WIRE_30.valid, UInt<1>(0h0) \n connect _WIRE_30.ready, UInt<1>(0h0) \n wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_31.bits, _WIRE_30.bits \n connect _WIRE_31.valid, _WIRE_30.valid \n connect _WIRE_31.ready, _WIRE_30.ready \n connect _WIRE_31.valid, UInt<1>(0h0) \n wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_32.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_32.bits.data, UInt<128>(0h0) \n connect _WIRE_32.bits.address, UInt<32>(0h0) \n connect _WIRE_32.bits.source, UInt<5>(0h0) \n connect _WIRE_32.bits.size, UInt<4>(0h0) \n connect _WIRE_32.bits.param, UInt<3>(0h0) \n connect _WIRE_32.bits.opcode, UInt<3>(0h0) \n connect _WIRE_32.valid, UInt<1>(0h0) \n connect _WIRE_32.ready, UInt<1>(0h0) \n wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_33.bits, _WIRE_32.bits \n connect _WIRE_33.valid, _WIRE_32.valid \n connect _WIRE_33.ready, _WIRE_32.ready \n invalidate _WIRE_33.bits.corrupt \n invalidate _WIRE_33.bits.data \n invalidate _WIRE_33.bits.address \n invalidate _WIRE_33.bits.source \n invalidate _WIRE_33.bits.size \n invalidate _WIRE_33.bits.param \n invalidate _WIRE_33.bits.opcode \n invalidate _WIRE_33.valid \n invalidate _WIRE_33.ready \n wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_34.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_34.bits.data, UInt<128>(0h0) \n connect _WIRE_34.bits.address, UInt<32>(0h0) \n connect _WIRE_34.bits.source, UInt<4>(0h0) \n connect _WIRE_34.bits.size, UInt<4>(0h0) \n connect _WIRE_34.bits.param, UInt<3>(0h0) \n connect _WIRE_34.bits.opcode, UInt<3>(0h0) \n connect _WIRE_34.valid, UInt<1>(0h0) \n connect _WIRE_34.ready, UInt<1>(0h0) \n wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_35.bits, _WIRE_34.bits \n connect _WIRE_35.valid, _WIRE_34.valid \n connect _WIRE_35.ready, _WIRE_34.ready \n invalidate _WIRE_35.bits.corrupt \n invalidate _WIRE_35.bits.data \n invalidate _WIRE_35.bits.address \n invalidate _WIRE_35.bits.source \n invalidate _WIRE_35.bits.size \n invalidate _WIRE_35.bits.param \n invalidate _WIRE_35.bits.opcode \n invalidate _WIRE_35.valid \n invalidate _WIRE_35.ready \n wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_36.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_36.bits.data, UInt<128>(0h0) \n connect _WIRE_36.bits.address, UInt<32>(0h0) \n connect _WIRE_36.bits.source, UInt<5>(0h0) \n connect _WIRE_36.bits.size, UInt<4>(0h0) \n connect _WIRE_36.bits.param, UInt<3>(0h0) \n connect _WIRE_36.bits.opcode, UInt<3>(0h0) \n connect _WIRE_36.valid, UInt<1>(0h0) \n connect _WIRE_36.ready, UInt<1>(0h0) \n wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_37.bits, _WIRE_36.bits \n connect _WIRE_37.valid, _WIRE_36.valid \n connect _WIRE_37.ready, _WIRE_36.ready \n connect _WIRE_37.valid, UInt<1>(0h0) \n wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_38.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_38.bits.data, UInt<128>(0h0) \n connect _WIRE_38.bits.address, UInt<32>(0h0) \n connect _WIRE_38.bits.source, UInt<4>(0h0) \n connect _WIRE_38.bits.size, UInt<4>(0h0) \n connect _WIRE_38.bits.param, UInt<3>(0h0) \n connect _WIRE_38.bits.opcode, UInt<3>(0h0) \n connect _WIRE_38.valid, UInt<1>(0h0) \n connect _WIRE_38.ready, UInt<1>(0h0) \n wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_39.bits, _WIRE_38.bits \n connect _WIRE_39.valid, _WIRE_38.valid \n connect _WIRE_39.ready, _WIRE_38.ready \n connect _WIRE_39.ready, UInt<1>(0h1) \n connect anonIn_1.d.bits.corrupt, in[1].d.bits.corrupt \n connect anonIn_1.d.bits.data, in[1].d.bits.data \n connect anonIn_1.d.bits.denied, in[1].d.bits.denied \n connect anonIn_1.d.bits.sink, in[1].d.bits.sink \n connect anonIn_1.d.bits.source, in[1].d.bits.source \n connect anonIn_1.d.bits.size, in[1].d.bits.size \n connect anonIn_1.d.bits.param, in[1].d.bits.param \n connect anonIn_1.d.bits.opcode, in[1].d.bits.opcode \n connect anonIn_1.d.valid, in[1].d.valid \n connect in[1].d.ready, anonIn_1.d.ready \n node _anonIn_d_bits_source_T_1 = bits(in[1].d.bits.source, 3, 0) \n connect anonIn_1.d.bits.source, _anonIn_d_bits_source_T_1 \n wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _WIRE_40.bits.sink, UInt<4>(0h0) \n connect _WIRE_40.valid, UInt<1>(0h0) \n connect _WIRE_40.ready, UInt<1>(0h0) \n wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _WIRE_41.bits, _WIRE_40.bits \n connect _WIRE_41.valid, _WIRE_40.valid \n connect _WIRE_41.ready, _WIRE_40.ready \n invalidate _WIRE_41.bits.sink \n invalidate _WIRE_41.valid \n invalidate _WIRE_41.ready \n wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _WIRE_42.bits.sink, UInt<4>(0h0) \n connect _WIRE_42.valid, UInt<1>(0h0) \n connect _WIRE_42.ready, UInt<1>(0h0) \n wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _WIRE_43.bits, _WIRE_42.bits \n connect _WIRE_43.valid, _WIRE_42.valid \n connect _WIRE_43.ready, _WIRE_42.ready \n invalidate _WIRE_43.bits.sink \n invalidate _WIRE_43.valid \n invalidate _WIRE_43.ready \n wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _WIRE_44.bits.sink, UInt<4>(0h0) \n connect _WIRE_44.valid, UInt<1>(0h0) \n connect _WIRE_44.ready, UInt<1>(0h0) \n wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _WIRE_45.bits, _WIRE_44.bits \n connect _WIRE_45.valid, _WIRE_44.valid \n connect _WIRE_45.ready, _WIRE_44.ready \n connect _WIRE_45.valid, UInt<1>(0h0) \n wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _WIRE_46.bits.sink, UInt<4>(0h0) \n connect _WIRE_46.valid, UInt<1>(0h0) \n connect _WIRE_46.ready, UInt<1>(0h0) \n wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _WIRE_47.bits, _WIRE_46.bits \n connect _WIRE_47.valid, _WIRE_46.valid \n connect _WIRE_47.ready, _WIRE_46.ready \n connect _WIRE_47.ready, UInt<1>(0h1) \n wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}[1] \n connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt \n connect anonOut.a.bits.data, out[0].a.bits.data \n connect anonOut.a.bits.mask, out[0].a.bits.mask \n connect anonOut.a.bits.address, out[0].a.bits.address \n connect anonOut.a.bits.source, out[0].a.bits.source \n connect anonOut.a.bits.size, out[0].a.bits.size \n connect anonOut.a.bits.param, out[0].a.bits.param \n connect anonOut.a.bits.opcode, out[0].a.bits.opcode \n connect anonOut.a.valid, out[0].a.valid \n connect out[0].a.ready, anonOut.a.ready \n wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_48.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_48.bits.data, UInt<128>(0h0) \n connect _WIRE_48.bits.mask, UInt<16>(0h0) \n connect _WIRE_48.bits.address, UInt<32>(0h0) \n connect _WIRE_48.bits.source, UInt<5>(0h0) \n connect _WIRE_48.bits.size, UInt<4>(0h0) \n connect _WIRE_48.bits.param, UInt<2>(0h0) \n connect _WIRE_48.bits.opcode, UInt<3>(0h0) \n connect _WIRE_48.valid, UInt<1>(0h0) \n connect _WIRE_48.ready, UInt<1>(0h0) \n wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_49.bits, _WIRE_48.bits \n connect _WIRE_49.valid, _WIRE_48.valid \n connect _WIRE_49.ready, _WIRE_48.ready \n invalidate _WIRE_49.bits.corrupt \n invalidate _WIRE_49.bits.data \n invalidate _WIRE_49.bits.mask \n invalidate _WIRE_49.bits.address \n invalidate _WIRE_49.bits.source \n invalidate _WIRE_49.bits.size \n invalidate _WIRE_49.bits.param \n invalidate _WIRE_49.bits.opcode \n invalidate _WIRE_49.valid \n invalidate _WIRE_49.ready \n wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_50.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_50.bits.data, UInt<128>(0h0) \n connect _WIRE_50.bits.mask, UInt<16>(0h0) \n connect _WIRE_50.bits.address, UInt<32>(0h0) \n connect _WIRE_50.bits.source, UInt<5>(0h0) \n connect _WIRE_50.bits.size, UInt<4>(0h0) \n connect _WIRE_50.bits.param, UInt<2>(0h0) \n connect _WIRE_50.bits.opcode, UInt<3>(0h0) \n connect _WIRE_50.valid, UInt<1>(0h0) \n connect _WIRE_50.ready, UInt<1>(0h0) \n wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_51.bits, _WIRE_50.bits \n connect _WIRE_51.valid, _WIRE_50.valid \n connect _WIRE_51.ready, _WIRE_50.ready \n invalidate _WIRE_51.bits.corrupt \n invalidate _WIRE_51.bits.data \n invalidate _WIRE_51.bits.mask \n invalidate _WIRE_51.bits.address \n invalidate _WIRE_51.bits.source \n invalidate _WIRE_51.bits.size \n invalidate _WIRE_51.bits.param \n invalidate _WIRE_51.bits.opcode \n invalidate _WIRE_51.valid \n invalidate _WIRE_51.ready \n wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_52.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_52.bits.data, UInt<128>(0h0) \n connect _WIRE_52.bits.mask, UInt<16>(0h0) \n connect _WIRE_52.bits.address, UInt<32>(0h0) \n connect _WIRE_52.bits.source, UInt<5>(0h0) \n connect _WIRE_52.bits.size, UInt<4>(0h0) \n connect _WIRE_52.bits.param, UInt<2>(0h0) \n connect _WIRE_52.bits.opcode, UInt<3>(0h0) \n connect _WIRE_52.valid, UInt<1>(0h0) \n connect _WIRE_52.ready, UInt<1>(0h0) \n wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_53.bits, _WIRE_52.bits \n connect _WIRE_53.valid, _WIRE_52.valid \n connect _WIRE_53.ready, _WIRE_52.ready \n connect _WIRE_53.valid, UInt<1>(0h0) \n wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_54.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_54.bits.data, UInt<128>(0h0) \n connect _WIRE_54.bits.mask, UInt<16>(0h0) \n connect _WIRE_54.bits.address, UInt<32>(0h0) \n connect _WIRE_54.bits.source, UInt<5>(0h0) \n connect _WIRE_54.bits.size, UInt<4>(0h0) \n connect _WIRE_54.bits.param, UInt<2>(0h0) \n connect _WIRE_54.bits.opcode, UInt<3>(0h0) \n connect _WIRE_54.valid, UInt<1>(0h0) \n connect _WIRE_54.ready, UInt<1>(0h0) \n wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_55.bits, _WIRE_54.bits \n connect _WIRE_55.valid, _WIRE_54.valid \n connect _WIRE_55.ready, _WIRE_54.ready \n connect _WIRE_55.ready, UInt<1>(0h1) \n wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_56.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_56.bits.data, UInt<128>(0h0) \n connect _WIRE_56.bits.address, UInt<32>(0h0) \n connect _WIRE_56.bits.source, UInt<5>(0h0) \n connect _WIRE_56.bits.size, UInt<4>(0h0) \n connect _WIRE_56.bits.param, UInt<3>(0h0) \n connect _WIRE_56.bits.opcode, UInt<3>(0h0) \n connect _WIRE_56.valid, UInt<1>(0h0) \n connect _WIRE_56.ready, UInt<1>(0h0) \n wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_57.bits, _WIRE_56.bits \n connect _WIRE_57.valid, _WIRE_56.valid \n connect _WIRE_57.ready, _WIRE_56.ready \n invalidate _WIRE_57.bits.corrupt \n invalidate _WIRE_57.bits.data \n invalidate _WIRE_57.bits.address \n invalidate _WIRE_57.bits.source \n invalidate _WIRE_57.bits.size \n invalidate _WIRE_57.bits.param \n invalidate _WIRE_57.bits.opcode \n invalidate _WIRE_57.valid \n invalidate _WIRE_57.ready \n wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_58.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_58.bits.data, UInt<128>(0h0) \n connect _WIRE_58.bits.address, UInt<32>(0h0) \n connect _WIRE_58.bits.source, UInt<5>(0h0) \n connect _WIRE_58.bits.size, UInt<4>(0h0) \n connect _WIRE_58.bits.param, UInt<3>(0h0) \n connect _WIRE_58.bits.opcode, UInt<3>(0h0) \n connect _WIRE_58.valid, UInt<1>(0h0) \n connect _WIRE_58.ready, UInt<1>(0h0) \n wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_59.bits, _WIRE_58.bits \n connect _WIRE_59.valid, _WIRE_58.valid \n connect _WIRE_59.ready, _WIRE_58.ready \n invalidate _WIRE_59.bits.corrupt \n invalidate _WIRE_59.bits.data \n invalidate _WIRE_59.bits.address \n invalidate _WIRE_59.bits.source \n invalidate _WIRE_59.bits.size \n invalidate _WIRE_59.bits.param \n invalidate _WIRE_59.bits.opcode \n invalidate _WIRE_59.valid \n invalidate _WIRE_59.ready \n wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_60.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_60.bits.data, UInt<128>(0h0) \n connect _WIRE_60.bits.address, UInt<32>(0h0) \n connect _WIRE_60.bits.source, UInt<5>(0h0) \n connect _WIRE_60.bits.size, UInt<4>(0h0) \n connect _WIRE_60.bits.param, UInt<3>(0h0) \n connect _WIRE_60.bits.opcode, UInt<3>(0h0) \n connect _WIRE_60.valid, UInt<1>(0h0) \n connect _WIRE_60.ready, UInt<1>(0h0) \n wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_61.bits, _WIRE_60.bits \n connect _WIRE_61.valid, _WIRE_60.valid \n connect _WIRE_61.ready, _WIRE_60.ready \n connect _WIRE_61.ready, UInt<1>(0h1) \n wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_62.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_62.bits.data, UInt<128>(0h0) \n connect _WIRE_62.bits.address, UInt<32>(0h0) \n connect _WIRE_62.bits.source, UInt<5>(0h0) \n connect _WIRE_62.bits.size, UInt<4>(0h0) \n connect _WIRE_62.bits.param, UInt<3>(0h0) \n connect _WIRE_62.bits.opcode, UInt<3>(0h0) \n connect _WIRE_62.valid, UInt<1>(0h0) \n connect _WIRE_62.ready, UInt<1>(0h0) \n wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_63.bits, _WIRE_62.bits \n connect _WIRE_63.valid, _WIRE_62.valid \n connect _WIRE_63.ready, _WIRE_62.ready \n connect _WIRE_63.valid, UInt<1>(0h0) \n connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt \n connect out[0].d.bits.data, anonOut.d.bits.data \n connect out[0].d.bits.denied, anonOut.d.bits.denied \n connect out[0].d.bits.sink, anonOut.d.bits.sink \n connect out[0].d.bits.source, anonOut.d.bits.source \n connect out[0].d.bits.size, anonOut.d.bits.size \n connect out[0].d.bits.param, anonOut.d.bits.param \n connect out[0].d.bits.opcode, anonOut.d.bits.opcode \n connect out[0].d.valid, anonOut.d.valid \n connect anonOut.d.ready, out[0].d.ready \n node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0)) \n connect out[0].d.bits.sink, _out_0_d_bits_sink_T \n wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _WIRE_64.bits.sink, UInt<4>(0h0) \n connect _WIRE_64.valid, UInt<1>(0h0) \n connect _WIRE_64.ready, UInt<1>(0h0) \n wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _WIRE_65.bits, _WIRE_64.bits \n connect _WIRE_65.valid, _WIRE_64.valid \n connect _WIRE_65.ready, _WIRE_64.ready \n invalidate _WIRE_65.bits.sink \n invalidate _WIRE_65.valid \n invalidate _WIRE_65.ready \n wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _WIRE_66.bits.sink, UInt<4>(0h0) \n connect _WIRE_66.valid, UInt<1>(0h0) \n connect _WIRE_66.ready, UInt<1>(0h0) \n wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _WIRE_67.bits, _WIRE_66.bits \n connect _WIRE_67.valid, _WIRE_66.valid \n connect _WIRE_67.ready, _WIRE_66.ready \n invalidate _WIRE_67.bits.sink \n invalidate _WIRE_67.valid \n invalidate _WIRE_67.ready \n wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _WIRE_68.bits.sink, UInt<4>(0h0) \n connect _WIRE_68.valid, UInt<1>(0h0) \n connect _WIRE_68.ready, UInt<1>(0h0) \n wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _WIRE_69.bits, _WIRE_68.bits \n connect _WIRE_69.valid, _WIRE_68.valid \n connect _WIRE_69.ready, _WIRE_68.ready \n connect _WIRE_69.ready, UInt<1>(0h1) \n wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _WIRE_70.bits.sink, UInt<4>(0h0) \n connect _WIRE_70.valid, UInt<1>(0h0) \n connect _WIRE_70.ready, UInt<1>(0h0) \n wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _WIRE_71.bits, _WIRE_70.bits \n connect _WIRE_71.valid, _WIRE_70.valid \n connect _WIRE_71.ready, _WIRE_70.ready \n connect _WIRE_71.valid, UInt<1>(0h0) \n wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _addressC_WIRE.bits.data, UInt<128>(0h0) \n connect _addressC_WIRE.bits.address, UInt<32>(0h0) \n connect _addressC_WIRE.bits.source, UInt<5>(0h0) \n connect _addressC_WIRE.bits.size, UInt<4>(0h0) \n connect _addressC_WIRE.bits.param, UInt<3>(0h0) \n connect _addressC_WIRE.bits.opcode, UInt<3>(0h0) \n connect _addressC_WIRE.valid, UInt<1>(0h0) \n connect _addressC_WIRE.ready, UInt<1>(0h0) \n wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _addressC_WIRE_1.bits, _addressC_WIRE.bits \n connect _addressC_WIRE_1.valid, _addressC_WIRE.valid \n connect _addressC_WIRE_1.ready, _addressC_WIRE.ready \n wire _addressC_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _addressC_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _addressC_WIRE_2.bits.data, UInt<128>(0h0) \n connect _addressC_WIRE_2.bits.address, UInt<32>(0h0) \n connect _addressC_WIRE_2.bits.source, UInt<5>(0h0) \n connect _addressC_WIRE_2.bits.size, UInt<4>(0h0) \n connect _addressC_WIRE_2.bits.param, UInt<3>(0h0) \n connect _addressC_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _addressC_WIRE_2.valid, UInt<1>(0h0) \n connect _addressC_WIRE_2.ready, UInt<1>(0h0) \n wire _addressC_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _addressC_WIRE_3.bits, _addressC_WIRE_2.bits \n connect _addressC_WIRE_3.valid, _addressC_WIRE_2.valid \n connect _addressC_WIRE_3.ready, _addressC_WIRE_2.ready \n node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0)) \n node _requestAIO_T_1 = cvt(_requestAIO_T) \n node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<1>(0h0))) \n node _requestAIO_T_3 = asSInt(_requestAIO_T_2) \n node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0))) \n node requestAIO_0_0 = or(UInt<1>(0h1), _requestAIO_T_4) \n node _requestAIO_T_5 = xor(in[1].a.bits.address, UInt<1>(0h0)) \n node _requestAIO_T_6 = cvt(_requestAIO_T_5) \n node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<1>(0h0))) \n node _requestAIO_T_8 = asSInt(_requestAIO_T_7) \n node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0))) \n node requestAIO_1_0 = or(UInt<1>(0h1), _requestAIO_T_9) \n node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0)) \n node _requestCIO_T_1 = cvt(_requestCIO_T) \n node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0))) \n node _requestCIO_T_3 = asSInt(_requestCIO_T_2) \n node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0))) \n node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4) \n node _requestCIO_T_5 = xor(_addressC_WIRE_3.bits.address, UInt<1>(0h0)) \n node _requestCIO_T_6 = cvt(_requestCIO_T_5) \n node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0))) \n node _requestCIO_T_8 = asSInt(_requestCIO_T_7) \n node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0))) \n node requestCIO_1_0 = or(UInt<1>(0h1), _requestCIO_T_9) \n wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _requestBOI_WIRE.bits.data, UInt<128>(0h0) \n connect _requestBOI_WIRE.bits.mask, UInt<16>(0h0) \n connect _requestBOI_WIRE.bits.address, UInt<32>(0h0) \n connect _requestBOI_WIRE.bits.source, UInt<5>(0h0) \n connect _requestBOI_WIRE.bits.size, UInt<4>(0h0) \n connect _requestBOI_WIRE.bits.param, UInt<2>(0h0) \n connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0) \n connect _requestBOI_WIRE.valid, UInt<1>(0h0) \n connect _requestBOI_WIRE.ready, UInt<1>(0h0) \n wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits \n connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid \n connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready \n node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_1.bits.source, UInt<4>(0h0)) \n node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 3, 0) \n node _requestBOI_T = shr(_requestBOI_WIRE_1.bits.source, 4) \n node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h1)) \n node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits) \n node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2) \n node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<4>(0hf)) \n node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4) \n wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _requestBOI_WIRE_2.bits.data, UInt<128>(0h0) \n connect _requestBOI_WIRE_2.bits.mask, UInt<16>(0h0) \n connect _requestBOI_WIRE_2.bits.address, UInt<32>(0h0) \n connect _requestBOI_WIRE_2.bits.source, UInt<5>(0h0) \n connect _requestBOI_WIRE_2.bits.size, UInt<4>(0h0) \n connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0) \n connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _requestBOI_WIRE_2.valid, UInt<1>(0h0) \n connect _requestBOI_WIRE_2.ready, UInt<1>(0h0) \n wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits \n connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid \n connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready \n node _requestBOI_uncommonBits_T_1 = or(_requestBOI_WIRE_3.bits.source, UInt<4>(0h0)) \n node requestBOI_uncommonBits_1 = bits(_requestBOI_uncommonBits_T_1, 3, 0) \n node _requestBOI_T_5 = shr(_requestBOI_WIRE_3.bits.source, 4) \n node _requestBOI_T_6 = eq(_requestBOI_T_5, UInt<1>(0h0)) \n node _requestBOI_T_7 = leq(UInt<1>(0h0), requestBOI_uncommonBits_1) \n node _requestBOI_T_8 = and(_requestBOI_T_6, _requestBOI_T_7) \n node _requestBOI_T_9 = leq(requestBOI_uncommonBits_1, UInt<4>(0hf)) \n node requestBOI_0_1 = and(_requestBOI_T_8, _requestBOI_T_9) \n node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<4>(0h0)) \n node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 3, 0) \n node _requestDOI_T = shr(out[0].d.bits.source, 4) \n node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h1)) \n node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits) \n node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2) \n node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<4>(0hf)) \n node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4) \n node _requestDOI_uncommonBits_T_1 = or(out[0].d.bits.source, UInt<4>(0h0)) \n node requestDOI_uncommonBits_1 = bits(_requestDOI_uncommonBits_T_1, 3, 0) \n node _requestDOI_T_5 = shr(out[0].d.bits.source, 4) \n node _requestDOI_T_6 = eq(_requestDOI_T_5, UInt<1>(0h0)) \n node _requestDOI_T_7 = leq(UInt<1>(0h0), requestDOI_uncommonBits_1) \n node _requestDOI_T_8 = and(_requestDOI_T_6, _requestDOI_T_7) \n node _requestDOI_T_9 = leq(requestDOI_uncommonBits_1, UInt<4>(0hf)) \n node requestDOI_0_1 = and(_requestDOI_T_8, _requestDOI_T_9) \n wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _requestEIO_WIRE.bits.sink, UInt<4>(0h0) \n connect _requestEIO_WIRE.valid, UInt<1>(0h0) \n connect _requestEIO_WIRE.ready, UInt<1>(0h0) \n wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits \n connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid \n connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready \n node _requestEIO_uncommonBits_T = or(_requestEIO_WIRE_1.bits.sink, UInt<4>(0h0)) \n node requestEIO_uncommonBits = bits(_requestEIO_uncommonBits_T, 3, 0) \n node _requestEIO_T = shr(_requestEIO_WIRE_1.bits.sink, 4) \n node _requestEIO_T_1 = eq(_requestEIO_T, UInt<1>(0h0)) \n node _requestEIO_T_2 = leq(UInt<1>(0h0), requestEIO_uncommonBits) \n node _requestEIO_T_3 = and(_requestEIO_T_1, _requestEIO_T_2) \n node _requestEIO_T_4 = leq(requestEIO_uncommonBits, UInt<4>(0hf)) \n node requestEIO_0_0 = and(_requestEIO_T_3, _requestEIO_T_4) \n wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _requestEIO_WIRE_2.bits.sink, UInt<4>(0h0) \n connect _requestEIO_WIRE_2.valid, UInt<1>(0h0) \n connect _requestEIO_WIRE_2.ready, UInt<1>(0h0) \n wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits \n connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid \n connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready \n node _requestEIO_uncommonBits_T_1 = or(_requestEIO_WIRE_3.bits.sink, UInt<4>(0h0)) \n node requestEIO_uncommonBits_1 = bits(_requestEIO_uncommonBits_T_1, 3, 0) \n node _requestEIO_T_5 = shr(_requestEIO_WIRE_3.bits.sink, 4) \n node _requestEIO_T_6 = eq(_requestEIO_T_5, UInt<1>(0h0)) \n node _requestEIO_T_7 = leq(UInt<1>(0h0), requestEIO_uncommonBits_1) \n node _requestEIO_T_8 = and(_requestEIO_T_6, _requestEIO_T_7) \n node _requestEIO_T_9 = leq(requestEIO_uncommonBits_1, UInt<4>(0hf)) \n node requestEIO_1_0 = and(_requestEIO_T_8, _requestEIO_T_9) \n node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size) \n node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0) \n node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1) \n node beatsAI_decode = shr(_beatsAI_decode_T_2, 4) \n node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2) \n node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0)) \n node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0)) \n node _beatsAI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].a.bits.size) \n node _beatsAI_decode_T_4 = bits(_beatsAI_decode_T_3, 11, 0) \n node _beatsAI_decode_T_5 = not(_beatsAI_decode_T_4) \n node beatsAI_decode_1 = shr(_beatsAI_decode_T_5, 4) \n node _beatsAI_opdata_T_1 = bits(in[1].a.bits.opcode, 2, 2) \n node beatsAI_opdata_1 = eq(_beatsAI_opdata_T_1, UInt<1>(0h0)) \n node beatsAI_1 = mux(beatsAI_opdata_1, beatsAI_decode_1, UInt<1>(0h0)) \n wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _beatsBO_WIRE.bits.data, UInt<128>(0h0) \n connect _beatsBO_WIRE.bits.mask, UInt<16>(0h0) \n connect _beatsBO_WIRE.bits.address, UInt<32>(0h0) \n connect _beatsBO_WIRE.bits.source, UInt<5>(0h0) \n connect _beatsBO_WIRE.bits.size, UInt<4>(0h0) \n connect _beatsBO_WIRE.bits.param, UInt<2>(0h0) \n connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0) \n connect _beatsBO_WIRE.valid, UInt<1>(0h0) \n connect _beatsBO_WIRE.ready, UInt<1>(0h0) \n wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits \n connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid \n connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready \n node _beatsBO_decode_T = dshl(UInt<12>(0hfff), _beatsBO_WIRE_1.bits.size) \n node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0) \n node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1) \n node beatsBO_decode = shr(_beatsBO_decode_T_2, 4) \n node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2) \n node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0)) \n node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0)) \n wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _beatsCI_WIRE.bits.data, UInt<128>(0h0) \n connect _beatsCI_WIRE.bits.address, UInt<32>(0h0) \n connect _beatsCI_WIRE.bits.source, UInt<5>(0h0) \n connect _beatsCI_WIRE.bits.size, UInt<4>(0h0) \n connect _beatsCI_WIRE.bits.param, UInt<3>(0h0) \n connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0) \n connect _beatsCI_WIRE.valid, UInt<1>(0h0) \n connect _beatsCI_WIRE.ready, UInt<1>(0h0) \n wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits \n connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid \n connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready \n node _beatsCI_decode_T = dshl(UInt<12>(0hfff), _beatsCI_WIRE_1.bits.size) \n node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0) \n node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1) \n node beatsCI_decode = shr(_beatsCI_decode_T_2, 4) \n node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0) \n node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0)) \n wire _beatsCI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _beatsCI_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _beatsCI_WIRE_2.bits.data, UInt<128>(0h0) \n connect _beatsCI_WIRE_2.bits.address, UInt<32>(0h0) \n connect _beatsCI_WIRE_2.bits.source, UInt<5>(0h0) \n connect _beatsCI_WIRE_2.bits.size, UInt<4>(0h0) \n connect _beatsCI_WIRE_2.bits.param, UInt<3>(0h0) \n connect _beatsCI_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _beatsCI_WIRE_2.valid, UInt<1>(0h0) \n connect _beatsCI_WIRE_2.ready, UInt<1>(0h0) \n wire _beatsCI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _beatsCI_WIRE_3.bits, _beatsCI_WIRE_2.bits \n connect _beatsCI_WIRE_3.valid, _beatsCI_WIRE_2.valid \n connect _beatsCI_WIRE_3.ready, _beatsCI_WIRE_2.ready \n node _beatsCI_decode_T_3 = dshl(UInt<12>(0hfff), _beatsCI_WIRE_3.bits.size) \n node _beatsCI_decode_T_4 = bits(_beatsCI_decode_T_3, 11, 0) \n node _beatsCI_decode_T_5 = not(_beatsCI_decode_T_4) \n node beatsCI_decode_1 = shr(_beatsCI_decode_T_5, 4) \n node beatsCI_opdata_1 = bits(_beatsCI_WIRE_3.bits.opcode, 0, 0) \n node beatsCI_1 = mux(UInt<1>(0h0), beatsCI_decode_1, UInt<1>(0h0)) \n node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size) \n node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0) \n node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1) \n node beatsDO_decode = shr(_beatsDO_decode_T_2, 4) \n node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0) \n node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0)) \n wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _beatsEI_WIRE.bits.sink, UInt<4>(0h0) \n connect _beatsEI_WIRE.valid, UInt<1>(0h0) \n connect _beatsEI_WIRE.ready, UInt<1>(0h0) \n wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits \n connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid \n connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready \n wire _beatsEI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _beatsEI_WIRE_2.bits.sink, UInt<4>(0h0) \n connect _beatsEI_WIRE_2.valid, UInt<1>(0h0) \n connect _beatsEI_WIRE_2.ready, UInt<1>(0h0) \n wire _beatsEI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _beatsEI_WIRE_3.bits, _beatsEI_WIRE_2.bits \n connect _beatsEI_WIRE_3.valid, _beatsEI_WIRE_2.valid \n connect _beatsEI_WIRE_3.ready, _beatsEI_WIRE_2.ready \n wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}[1] \n connect portsAOI_filtered[0].bits, in[0].a.bits \n node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h1)) \n node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T) \n connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1 \n connect in[0].a.ready, portsAOI_filtered[0].ready \n wire portsAOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}[1] \n connect portsAOI_filtered_1[0].bits, in[1].a.bits \n node _portsAOI_filtered_0_valid_T_2 = or(requestAIO_1_0, UInt<1>(0h1)) \n node _portsAOI_filtered_0_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_0_valid_T_2) \n connect portsAOI_filtered_1[0].valid, _portsAOI_filtered_0_valid_T_3 \n connect in[1].a.ready, portsAOI_filtered_1[0].ready \n wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _portsBIO_WIRE.bits.data, UInt<128>(0h0) \n connect _portsBIO_WIRE.bits.mask, UInt<16>(0h0) \n connect _portsBIO_WIRE.bits.address, UInt<32>(0h0) \n connect _portsBIO_WIRE.bits.source, UInt<5>(0h0) \n connect _portsBIO_WIRE.bits.size, UInt<4>(0h0) \n connect _portsBIO_WIRE.bits.param, UInt<2>(0h0) \n connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0) \n connect _portsBIO_WIRE.valid, UInt<1>(0h0) \n connect _portsBIO_WIRE.ready, UInt<1>(0h0) \n wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits \n connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid \n connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready \n wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}[2] \n connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits \n node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h0)) \n node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T) \n connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1 \n connect portsBIO_filtered[1].bits, _portsBIO_WIRE_1.bits \n node _portsBIO_filtered_1_valid_T = or(requestBOI_0_1, UInt<1>(0h0)) \n node _portsBIO_filtered_1_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_1_valid_T) \n connect portsBIO_filtered[1].valid, _portsBIO_filtered_1_valid_T_1 \n node _portsBIO_T = mux(requestBOI_0_0, portsBIO_filtered[0].ready, UInt<1>(0h0)) \n node _portsBIO_T_1 = mux(requestBOI_0_1, portsBIO_filtered[1].ready, UInt<1>(0h0)) \n node _portsBIO_T_2 = or(_portsBIO_T, _portsBIO_T_1) \n wire _portsBIO_WIRE_2 : UInt<1> \n connect _portsBIO_WIRE_2, _portsBIO_T_2 \n connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE_2 \n wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0) \n connect _portsCOI_WIRE.bits.data, UInt<128>(0h0) \n connect _portsCOI_WIRE.bits.address, UInt<32>(0h0) \n connect _portsCOI_WIRE.bits.source, UInt<5>(0h0) \n connect _portsCOI_WIRE.bits.size, UInt<4>(0h0) \n connect _portsCOI_WIRE.bits.param, UInt<3>(0h0) \n connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0) \n connect _portsCOI_WIRE.valid, UInt<1>(0h0) \n connect _portsCOI_WIRE.ready, UInt<1>(0h0) \n wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits \n connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid \n connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready \n wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}[1] \n connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits \n node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h1)) \n node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T) \n connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1 \n connect _portsCOI_WIRE_1.ready, portsCOI_filtered[0].ready \n wire _portsCOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _portsCOI_WIRE_2.bits.corrupt, UInt<1>(0h0) \n connect _portsCOI_WIRE_2.bits.data, UInt<128>(0h0) \n connect _portsCOI_WIRE_2.bits.address, UInt<32>(0h0) \n connect _portsCOI_WIRE_2.bits.source, UInt<5>(0h0) \n connect _portsCOI_WIRE_2.bits.size, UInt<4>(0h0) \n connect _portsCOI_WIRE_2.bits.param, UInt<3>(0h0) \n connect _portsCOI_WIRE_2.bits.opcode, UInt<3>(0h0) \n connect _portsCOI_WIRE_2.valid, UInt<1>(0h0) \n connect _portsCOI_WIRE_2.ready, UInt<1>(0h0) \n wire _portsCOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _portsCOI_WIRE_3.bits, _portsCOI_WIRE_2.bits \n connect _portsCOI_WIRE_3.valid, _portsCOI_WIRE_2.valid \n connect _portsCOI_WIRE_3.ready, _portsCOI_WIRE_2.ready \n wire portsCOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}[1] \n connect portsCOI_filtered_1[0].bits, _portsCOI_WIRE_3.bits \n node _portsCOI_filtered_0_valid_T_2 = or(requestCIO_1_0, UInt<1>(0h1)) \n node _portsCOI_filtered_0_valid_T_3 = and(_portsCOI_WIRE_3.valid, _portsCOI_filtered_0_valid_T_2) \n connect portsCOI_filtered_1[0].valid, _portsCOI_filtered_0_valid_T_3 \n connect _portsCOI_WIRE_3.ready, portsCOI_filtered_1[0].ready \n wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}[2] \n connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt \n connect portsDIO_filtered[0].bits.data, out[0].d.bits.data \n connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied \n connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink \n connect portsDIO_filtered[0].bits.source, out[0].d.bits.source \n connect portsDIO_filtered[0].bits.size, out[0].d.bits.size \n connect portsDIO_filtered[0].bits.param, out[0].d.bits.param \n connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode \n node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h0)) \n node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T) \n connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1 \n connect portsDIO_filtered[1].bits.corrupt, out[0].d.bits.corrupt \n connect portsDIO_filtered[1].bits.data, out[0].d.bits.data \n connect portsDIO_filtered[1].bits.denied, out[0].d.bits.denied \n connect portsDIO_filtered[1].bits.sink, out[0].d.bits.sink \n connect portsDIO_filtered[1].bits.source, out[0].d.bits.source \n connect portsDIO_filtered[1].bits.size, out[0].d.bits.size \n connect portsDIO_filtered[1].bits.param, out[0].d.bits.param \n connect portsDIO_filtered[1].bits.opcode, out[0].d.bits.opcode \n node _portsDIO_filtered_1_valid_T = or(requestDOI_0_1, UInt<1>(0h0)) \n node _portsDIO_filtered_1_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_1_valid_T) \n connect portsDIO_filtered[1].valid, _portsDIO_filtered_1_valid_T_1 \n node _portsDIO_out_0_d_ready_T = mux(requestDOI_0_0, portsDIO_filtered[0].ready, UInt<1>(0h0)) \n node _portsDIO_out_0_d_ready_T_1 = mux(requestDOI_0_1, portsDIO_filtered[1].ready, UInt<1>(0h0)) \n node _portsDIO_out_0_d_ready_T_2 = or(_portsDIO_out_0_d_ready_T, _portsDIO_out_0_d_ready_T_1) \n wire _portsDIO_out_0_d_ready_WIRE : UInt<1> \n connect _portsDIO_out_0_d_ready_WIRE, _portsDIO_out_0_d_ready_T_2 \n connect out[0].d.ready, _portsDIO_out_0_d_ready_WIRE \n wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _portsEOI_WIRE.bits.sink, UInt<4>(0h0) \n connect _portsEOI_WIRE.valid, UInt<1>(0h0) \n connect _portsEOI_WIRE.ready, UInt<1>(0h0) \n wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits \n connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid \n connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready \n wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}[1] \n connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits \n node _portsEOI_filtered_0_valid_T = or(requestEIO_0_0, UInt<1>(0h1)) \n node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T) \n connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1 \n connect _portsEOI_WIRE_1.ready, portsEOI_filtered[0].ready \n wire _portsEOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _portsEOI_WIRE_2.bits.sink, UInt<4>(0h0) \n connect _portsEOI_WIRE_2.valid, UInt<1>(0h0) \n connect _portsEOI_WIRE_2.ready, UInt<1>(0h0) \n wire _portsEOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _portsEOI_WIRE_3.bits, _portsEOI_WIRE_2.bits \n connect _portsEOI_WIRE_3.valid, _portsEOI_WIRE_2.valid \n connect _portsEOI_WIRE_3.ready, _portsEOI_WIRE_2.ready \n wire portsEOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}[1] \n connect portsEOI_filtered_1[0].bits, _portsEOI_WIRE_3.bits \n node _portsEOI_filtered_0_valid_T_2 = or(requestEIO_1_0, UInt<1>(0h1)) \n node _portsEOI_filtered_0_valid_T_3 = and(_portsEOI_WIRE_3.valid, _portsEOI_filtered_0_valid_T_2) \n connect portsEOI_filtered_1[0].valid, _portsEOI_filtered_0_valid_T_3 \n connect _portsEOI_WIRE_3.ready, portsEOI_filtered_1[0].ready \n regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0) \n node idle = eq(beatsLeft, UInt<1>(0h0)) \n node latch = and(idle, out[0].a.ready) \n node _readys_T = cat(portsAOI_filtered_1[0].valid, portsAOI_filtered[0].valid) \n node readys_valid = bits(_readys_T, 1, 0) \n node _readys_T_1 = eq(readys_valid, _readys_T) \n node _readys_T_2 = asUInt(reset) \n node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0)) \n when _readys_T_3 : \n node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0)) \n when _readys_T_4 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at Arbiter.scala:22 assert (valid === valids)\\n\") : readys_printf \n assert(clock, _readys_T_1, UInt<1>(0h1), \"\") : readys_assert \n regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3) \n node _readys_filter_T = not(readys_mask) \n node _readys_filter_T_1 = and(readys_valid, _readys_filter_T) \n node readys_filter = cat(_readys_filter_T_1, readys_valid) \n node _readys_unready_T = shr(readys_filter, 1) \n node _readys_unready_T_1 = or(readys_filter, _readys_unready_T) \n node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0) \n node _readys_unready_T_3 = shr(_readys_unready_T_2, 1) \n node _readys_unready_T_4 = shl(readys_mask, 2) \n node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4) \n node _readys_readys_T = shr(readys_unready, 2) \n node _readys_readys_T_1 = bits(readys_unready, 1, 0) \n node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1) \n node readys_readys = not(_readys_readys_T_2) \n node _readys_T_5 = orr(readys_valid) \n node _readys_T_6 = and(latch, _readys_T_5) \n when _readys_T_6 : \n node _readys_mask_T = and(readys_readys, readys_valid) \n node _readys_mask_T_1 = shl(_readys_mask_T, 1) \n node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0) \n node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2) \n node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0) \n connect readys_mask, _readys_mask_T_4 \n node _readys_T_7 = bits(readys_readys, 1, 0) \n node _readys_T_8 = bits(_readys_T_7, 0, 0) \n node _readys_T_9 = bits(_readys_T_7, 1, 1) \n wire readys : UInt<1>[2] \n connect readys[0], _readys_T_8 \n connect readys[1], _readys_T_9 \n node _winner_T = and(readys[0], portsAOI_filtered[0].valid) \n node _winner_T_1 = and(readys[1], portsAOI_filtered_1[0].valid) \n wire winner : UInt<1>[2] \n connect winner[0], _winner_T \n connect winner[1], _winner_T_1 \n node prefixOR_1 = or(UInt<1>(0h0), winner[0]) \n node _prefixOR_T = or(prefixOR_1, winner[1]) \n node _T = eq(UInt<1>(0h0), UInt<1>(0h0)) \n node _T_1 = eq(winner[0], UInt<1>(0h0)) \n node _T_2 = or(_T, _T_1) \n node _T_3 = eq(prefixOR_1, UInt<1>(0h0)) \n node _T_4 = eq(winner[1], UInt<1>(0h0)) \n node _T_5 = or(_T_3, _T_4) \n node _T_6 = and(_T_2, _T_5) \n node _T_7 = asUInt(reset) \n node _T_8 = eq(_T_7, UInt<1>(0h0)) \n when _T_8 : \n node _T_9 = eq(_T_6, UInt<1>(0h0)) \n when _T_9 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\\n\") : printf \n assert(clock, _T_6, UInt<1>(0h1), \"\") : assert \n node _T_10 = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) \n node _T_11 = eq(_T_10, UInt<1>(0h0)) \n node _T_12 = or(winner[0], winner[1]) \n node _T_13 = or(_T_11, _T_12) \n node _T_14 = asUInt(reset) \n node _T_15 = eq(_T_14, UInt<1>(0h0)) \n when _T_15 : \n node _T_16 = eq(_T_13, UInt<1>(0h0)) \n when _T_16 : \n printf(clock, UInt<1>(0h1), \"Assertion failed\\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\\n\") : printf_1 \n assert(clock, _T_13, UInt<1>(0h1), \"\") : assert_1 \n node maskedBeats_0 = mux(winner[0], beatsAI_0, UInt<1>(0h0)) \n node maskedBeats_1 = mux(winner[1], beatsAI_1, UInt<1>(0h0)) \n node initBeats = or(maskedBeats_0, maskedBeats_1) \n node _beatsLeft_T = and(out[0].a.ready, out[0].a.valid) \n node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T) \n node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1) \n node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2) \n connect beatsLeft, _beatsLeft_T_3 \n wire _state_WIRE : UInt<1>[2] \n connect _state_WIRE[0], UInt<1>(0h0) \n connect _state_WIRE[1], UInt<1>(0h0) \n regreset state : UInt<1>[2], clock, reset, _state_WIRE \n node muxState = mux(idle, winner, state) \n connect state, muxState \n node allowed = mux(idle, readys, state) \n node _filtered_0_ready_T = and(out[0].a.ready, allowed[0]) \n connect portsAOI_filtered[0].ready, _filtered_0_ready_T \n node _filtered_0_ready_T_1 = and(out[0].a.ready, allowed[1]) \n connect portsAOI_filtered_1[0].ready, _filtered_0_ready_T_1 \n node _out_0_a_valid_T = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid) \n node _out_0_a_valid_T_1 = mux(state[0], portsAOI_filtered[0].valid, UInt<1>(0h0)) \n node _out_0_a_valid_T_2 = mux(state[1], portsAOI_filtered_1[0].valid, UInt<1>(0h0)) \n node _out_0_a_valid_T_3 = or(_out_0_a_valid_T_1, _out_0_a_valid_T_2) \n wire _out_0_a_valid_WIRE : UInt<1> \n connect _out_0_a_valid_WIRE, _out_0_a_valid_T_3 \n node _out_0_a_valid_T_4 = mux(idle, _out_0_a_valid_T, _out_0_a_valid_WIRE) \n connect out[0].a.valid, _out_0_a_valid_T_4 \n wire _out_0_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>} \n node _out_0_a_bits_T = mux(muxState[0], portsAOI_filtered[0].bits.corrupt, UInt<1>(0h0)) \n node _out_0_a_bits_T_1 = mux(muxState[1], portsAOI_filtered_1[0].bits.corrupt, UInt<1>(0h0)) \n node _out_0_a_bits_T_2 = or(_out_0_a_bits_T, _out_0_a_bits_T_1) \n wire _out_0_a_bits_WIRE_1 : UInt<1> \n connect _out_0_a_bits_WIRE_1, _out_0_a_bits_T_2 \n connect _out_0_a_bits_WIRE.corrupt, _out_0_a_bits_WIRE_1 \n node _out_0_a_bits_T_3 = mux(muxState[0], portsAOI_filtered[0].bits.data, UInt<1>(0h0)) \n node _out_0_a_bits_T_4 = mux(muxState[1], portsAOI_filtered_1[0].bits.data, UInt<1>(0h0)) \n node _out_0_a_bits_T_5 = or(_out_0_a_bits_T_3, _out_0_a_bits_T_4) \n wire _out_0_a_bits_WIRE_2 : UInt<128> \n connect _out_0_a_bits_WIRE_2, _out_0_a_bits_T_5 \n connect _out_0_a_bits_WIRE.data, _out_0_a_bits_WIRE_2 \n node _out_0_a_bits_T_6 = mux(muxState[0], portsAOI_filtered[0].bits.mask, UInt<1>(0h0)) \n node _out_0_a_bits_T_7 = mux(muxState[1], portsAOI_filtered_1[0].bits.mask, UInt<1>(0h0)) \n node _out_0_a_bits_T_8 = or(_out_0_a_bits_T_6, _out_0_a_bits_T_7) \n wire _out_0_a_bits_WIRE_3 : UInt<16> \n connect _out_0_a_bits_WIRE_3, _out_0_a_bits_T_8 \n connect _out_0_a_bits_WIRE.mask, _out_0_a_bits_WIRE_3 \n wire _out_0_a_bits_WIRE_4 : { } \n connect _out_0_a_bits_WIRE.echo, _out_0_a_bits_WIRE_4 \n wire _out_0_a_bits_WIRE_5 : { } \n connect _out_0_a_bits_WIRE.user, _out_0_a_bits_WIRE_5 \n node _out_0_a_bits_T_9 = mux(muxState[0], portsAOI_filtered[0].bits.address, UInt<1>(0h0)) \n node _out_0_a_bits_T_10 = mux(muxState[1], portsAOI_filtered_1[0].bits.address, UInt<1>(0h0)) \n node _out_0_a_bits_T_11 = or(_out_0_a_bits_T_9, _out_0_a_bits_T_10) \n wire _out_0_a_bits_WIRE_6 : UInt<32> \n connect _out_0_a_bits_WIRE_6, _out_0_a_bits_T_11 \n connect _out_0_a_bits_WIRE.address, _out_0_a_bits_WIRE_6 \n node _out_0_a_bits_T_12 = mux(muxState[0], portsAOI_filtered[0].bits.source, UInt<1>(0h0)) \n node _out_0_a_bits_T_13 = mux(muxState[1], portsAOI_filtered_1[0].bits.source, UInt<1>(0h0)) \n node _out_0_a_bits_T_14 = or(_out_0_a_bits_T_12, _out_0_a_bits_T_13) \n wire _out_0_a_bits_WIRE_7 : UInt<5> \n connect _out_0_a_bits_WIRE_7, _out_0_a_bits_T_14 \n connect _out_0_a_bits_WIRE.source, _out_0_a_bits_WIRE_7 \n node _out_0_a_bits_T_15 = mux(muxState[0], portsAOI_filtered[0].bits.size, UInt<1>(0h0)) \n node _out_0_a_bits_T_16 = mux(muxState[1], portsAOI_filtered_1[0].bits.size, UInt<1>(0h0)) \n node _out_0_a_bits_T_17 = or(_out_0_a_bits_T_15, _out_0_a_bits_T_16) \n wire _out_0_a_bits_WIRE_8 : UInt<4> \n connect _out_0_a_bits_WIRE_8, _out_0_a_bits_T_17 \n connect _out_0_a_bits_WIRE.size, _out_0_a_bits_WIRE_8 \n node _out_0_a_bits_T_18 = mux(muxState[0], portsAOI_filtered[0].bits.param, UInt<1>(0h0)) \n node _out_0_a_bits_T_19 = mux(muxState[1], portsAOI_filtered_1[0].bits.param, UInt<1>(0h0)) \n node _out_0_a_bits_T_20 = or(_out_0_a_bits_T_18, _out_0_a_bits_T_19) \n wire _out_0_a_bits_WIRE_9 : UInt<3> \n connect _out_0_a_bits_WIRE_9, _out_0_a_bits_T_20 \n connect _out_0_a_bits_WIRE.param, _out_0_a_bits_WIRE_9 \n node _out_0_a_bits_T_21 = mux(muxState[0], portsAOI_filtered[0].bits.opcode, UInt<1>(0h0)) \n node _out_0_a_bits_T_22 = mux(muxState[1], portsAOI_filtered_1[0].bits.opcode, UInt<1>(0h0)) \n node _out_0_a_bits_T_23 = or(_out_0_a_bits_T_21, _out_0_a_bits_T_22) \n wire _out_0_a_bits_WIRE_10 : UInt<3> \n connect _out_0_a_bits_WIRE_10, _out_0_a_bits_T_23 \n connect _out_0_a_bits_WIRE.opcode, _out_0_a_bits_WIRE_10 \n connect out[0].a.bits.corrupt, _out_0_a_bits_WIRE.corrupt \n connect out[0].a.bits.data, _out_0_a_bits_WIRE.data \n connect out[0].a.bits.mask, _out_0_a_bits_WIRE.mask \n connect out[0].a.bits.address, _out_0_a_bits_WIRE.address \n connect out[0].a.bits.source, _out_0_a_bits_WIRE.source \n connect out[0].a.bits.size, _out_0_a_bits_WIRE.size \n connect out[0].a.bits.param, _out_0_a_bits_WIRE.param \n connect out[0].a.bits.opcode, _out_0_a_bits_WIRE.opcode \n wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_72.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_72.bits.data, UInt<128>(0h0) \n connect _WIRE_72.bits.address, UInt<32>(0h0) \n connect _WIRE_72.bits.source, UInt<5>(0h0) \n connect _WIRE_72.bits.size, UInt<4>(0h0) \n connect _WIRE_72.bits.param, UInt<3>(0h0) \n connect _WIRE_72.bits.opcode, UInt<3>(0h0) \n connect _WIRE_72.valid, UInt<1>(0h0) \n connect _WIRE_72.ready, UInt<1>(0h0) \n wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_73.bits, _WIRE_72.bits \n connect _WIRE_73.valid, _WIRE_72.valid \n connect _WIRE_73.ready, _WIRE_72.ready \n invalidate _WIRE_73.bits.corrupt \n invalidate _WIRE_73.bits.data \n invalidate _WIRE_73.bits.address \n invalidate _WIRE_73.bits.source \n invalidate _WIRE_73.bits.size \n invalidate _WIRE_73.bits.param \n invalidate _WIRE_73.bits.opcode \n wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _WIRE_74.bits.sink, UInt<4>(0h0) \n connect _WIRE_74.valid, UInt<1>(0h0) \n connect _WIRE_74.ready, UInt<1>(0h0) \n wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} \n connect _WIRE_75.bits, _WIRE_74.bits \n connect _WIRE_75.valid, _WIRE_74.valid \n connect _WIRE_75.ready, _WIRE_74.ready \n invalidate _WIRE_75.bits.sink \n connect portsCOI_filtered[0].ready, UInt<1>(0h0) \n connect portsCOI_filtered_1[0].ready, UInt<1>(0h0) \n connect portsEOI_filtered[0].ready, UInt<1>(0h0) \n connect portsEOI_filtered_1[0].ready, UInt<1>(0h0) \n wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_76.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_76.bits.data, UInt<128>(0h0) \n connect _WIRE_76.bits.mask, UInt<16>(0h0) \n connect _WIRE_76.bits.address, UInt<32>(0h0) \n connect _WIRE_76.bits.source, UInt<5>(0h0) \n connect _WIRE_76.bits.size, UInt<4>(0h0) \n connect _WIRE_76.bits.param, UInt<2>(0h0) \n connect _WIRE_76.bits.opcode, UInt<3>(0h0) \n connect _WIRE_76.valid, UInt<1>(0h0) \n connect _WIRE_76.ready, UInt<1>(0h0) \n wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_77.bits, _WIRE_76.bits \n connect _WIRE_77.valid, _WIRE_76.valid \n connect _WIRE_77.ready, _WIRE_76.ready \n invalidate _WIRE_77.bits.corrupt \n invalidate _WIRE_77.bits.data \n invalidate _WIRE_77.bits.mask \n invalidate _WIRE_77.bits.address \n invalidate _WIRE_77.bits.source \n invalidate _WIRE_77.bits.size \n invalidate _WIRE_77.bits.param \n invalidate _WIRE_77.bits.opcode \n connect in[0].d, portsDIO_filtered[0] \n connect portsBIO_filtered[0].ready, UInt<1>(0h0) \n wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_78.bits.corrupt, UInt<1>(0h0) \n connect _WIRE_78.bits.data, UInt<128>(0h0) \n connect _WIRE_78.bits.mask, UInt<16>(0h0) \n connect _WIRE_78.bits.address, UInt<32>(0h0) \n connect _WIRE_78.bits.source, UInt<5>(0h0) \n connect _WIRE_78.bits.size, UInt<4>(0h0) \n connect _WIRE_78.bits.param, UInt<2>(0h0) \n connect _WIRE_78.bits.opcode, UInt<3>(0h0) \n connect _WIRE_78.valid, UInt<1>(0h0) \n connect _WIRE_78.ready, UInt<1>(0h0) \n wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} \n connect _WIRE_79.bits, _WIRE_78.bits \n connect _WIRE_79.valid, _WIRE_78.valid \n connect _WIRE_79.ready, _WIRE_78.ready \n invalidate _WIRE_79.bits.corrupt \n invalidate _WIRE_79.bits.data \n invalidate _WIRE_79.bits.mask \n invalidate _WIRE_79.bits.address \n invalidate _WIRE_79.bits.source \n invalidate _WIRE_79.bits.size \n invalidate _WIRE_79.bits.param \n invalidate _WIRE_79.bits.opcode \n connect in[1].d, portsDIO_filtered[1] \n connect portsBIO_filtered[1].ready, UInt<1>(0h0)"},"response":{"kind":"string","value":"module TLXbar_i2_o1_a32d128s5k4z4u(\t// @[Xbar.scala:74:9]\n input clock,\t// @[Xbar.scala:74:9]\n input reset,\t// @[Xbar.scala:74:9]\n output auto_anon_in_1_a_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_1_a_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_anon_in_1_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_anon_in_1_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_anon_in_1_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_anon_in_1_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_anon_in_1_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input [15:0] auto_anon_in_1_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n input [127:0] auto_anon_in_1_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_1_a_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_1_d_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_1_d_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_anon_in_1_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_anon_in_1_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_anon_in_1_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_anon_in_1_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_anon_in_1_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_1_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n output [127:0] auto_anon_in_1_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_1_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_0_a_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_0_a_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_anon_in_0_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_anon_in_0_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_anon_in_0_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_anon_in_0_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [31:0] auto_anon_in_0_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n input [15:0] auto_anon_in_0_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n input [127:0] auto_anon_in_0_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_0_a_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_in_0_d_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_0_d_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_anon_in_0_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [1:0] auto_anon_in_0_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_anon_in_0_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_anon_in_0_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_anon_in_0_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_0_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n output [127:0] auto_anon_in_0_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_in_0_d_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_a_ready,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_a_valid,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_anon_out_a_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n output [2:0] auto_anon_out_a_bits_param,\t// @[LazyModuleImp.scala:107:25]\n output [3:0] auto_anon_out_a_bits_size,\t// @[LazyModuleImp.scala:107:25]\n output [4:0] auto_anon_out_a_bits_source,\t// @[LazyModuleImp.scala:107:25]\n output [31:0] auto_anon_out_a_bits_address,\t// @[LazyModuleImp.scala:107:25]\n output [15:0] auto_anon_out_a_bits_mask,\t// @[LazyModuleImp.scala:107:25]\n output [127:0] auto_anon_out_a_bits_data,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_a_bits_corrupt,\t// @[LazyModuleImp.scala:107:25]\n output auto_anon_out_d_ready,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_d_valid,\t// @[LazyModuleImp.scala:107:25]\n input [2:0] auto_anon_out_d_bits_opcode,\t// @[LazyModuleImp.scala:107:25]\n input [1:0] auto_anon_out_d_bits_param,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_anon_out_d_bits_size,\t// @[LazyModuleImp.scala:107:25]\n input [4:0] auto_anon_out_d_bits_source,\t// @[LazyModuleImp.scala:107:25]\n input [3:0] auto_anon_out_d_bits_sink,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_d_bits_denied,\t// @[LazyModuleImp.scala:107:25]\n input [127:0] auto_anon_out_d_bits_data,\t// @[LazyModuleImp.scala:107:25]\n input auto_anon_out_d_bits_corrupt\t// @[LazyModuleImp.scala:107:25]\n);\n\n wire [3:0] out_0_d_bits_sink;\t// @[Xbar.scala:216:19]\n wire [4:0] in_1_a_bits_source;\t// @[Xbar.scala:159:18]\n wire [4:0] in_0_a_bits_source;\t// @[Xbar.scala:159:18]\n wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_in_1_a_bits_opcode_0 = auto_anon_in_1_a_bits_opcode;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_in_1_a_bits_param_0 = auto_anon_in_1_a_bits_param;\t// @[Xbar.scala:74:9]\n wire [3:0] auto_anon_in_1_a_bits_size_0 = auto_anon_in_1_a_bits_size;\t// @[Xbar.scala:74:9]\n wire [3:0] auto_anon_in_1_a_bits_source_0 = auto_anon_in_1_a_bits_source;\t// @[Xbar.scala:74:9]\n wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address;\t// @[Xbar.scala:74:9]\n wire [15:0] auto_anon_in_1_a_bits_mask_0 = auto_anon_in_1_a_bits_mask;\t// @[Xbar.scala:74:9]\n wire [127:0] auto_anon_in_1_a_bits_data_0 = auto_anon_in_1_a_bits_data;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_1_a_bits_corrupt_0 = auto_anon_in_1_a_bits_corrupt;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_1_d_ready_0 = auto_anon_in_1_d_ready;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param;\t// @[Xbar.scala:74:9]\n wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size;\t// @[Xbar.scala:74:9]\n wire [3:0] auto_anon_in_0_a_bits_source_0 = auto_anon_in_0_a_bits_source;\t// @[Xbar.scala:74:9]\n wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address;\t// @[Xbar.scala:74:9]\n wire [15:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask;\t// @[Xbar.scala:74:9]\n wire [127:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_a_bits_corrupt_0 = auto_anon_in_0_a_bits_corrupt;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready;\t// @[Xbar.scala:74:9]\n wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready;\t// @[Xbar.scala:74:9]\n wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode;\t// @[Xbar.scala:74:9]\n wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param;\t// @[Xbar.scala:74:9]\n wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size;\t// @[Xbar.scala:74:9]\n wire [4:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source;\t// @[Xbar.scala:74:9]\n wire [3:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink;\t// @[Xbar.scala:74:9]\n wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied;\t// @[Xbar.scala:74:9]\n wire [127:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data;\t// @[Xbar.scala:74:9]\n wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt;\t// @[Xbar.scala:74:9]\n wire _readys_T_2 = reset;\t// @[Arbiter.scala:22:12]\n wire _addressC_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _addressC_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _addressC_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _addressC_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _addressC_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _addressC_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _addressC_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _addressC_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _addressC_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _addressC_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _addressC_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _addressC_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire _requestBOI_WIRE_ready = 1'h0;\t// @[Bundles.scala:264:74]\n wire _requestBOI_WIRE_valid = 1'h0;\t// @[Bundles.scala:264:74]\n wire _requestBOI_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:264:74]\n wire _requestBOI_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:264:61]\n wire _requestBOI_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:264:61]\n wire _requestBOI_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:264:61]\n wire _requestBOI_T = 1'h0;\t// @[Parameters.scala:54:10]\n wire _requestBOI_T_1 = 1'h0;\t// @[Parameters.scala:54:32]\n wire _requestBOI_T_3 = 1'h0;\t// @[Parameters.scala:54:67]\n wire requestBOI_0_0 = 1'h0;\t// @[Parameters.scala:56:48]\n wire _requestBOI_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:264:74]\n wire _requestBOI_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:264:74]\n wire _requestBOI_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:264:74]\n wire _requestBOI_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:264:61]\n wire _requestBOI_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:264:61]\n wire _requestBOI_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:264:61]\n wire _requestBOI_T_5 = 1'h0;\t// @[Parameters.scala:54:10]\n wire _requestEIO_WIRE_ready = 1'h0;\t// @[Bundles.scala:267:74]\n wire _requestEIO_WIRE_valid = 1'h0;\t// @[Bundles.scala:267:74]\n wire _requestEIO_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:267:61]\n wire _requestEIO_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:267:61]\n wire _requestEIO_T = 1'h0;\t// @[Parameters.scala:54:10]\n wire _requestEIO_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:267:74]\n wire _requestEIO_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:267:74]\n wire _requestEIO_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:267:61]\n wire _requestEIO_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:267:61]\n wire _requestEIO_T_5 = 1'h0;\t// @[Parameters.scala:54:10]\n wire _beatsBO_WIRE_ready = 1'h0;\t// @[Bundles.scala:264:74]\n wire _beatsBO_WIRE_valid = 1'h0;\t// @[Bundles.scala:264:74]\n wire _beatsBO_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:264:74]\n wire _beatsBO_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:264:61]\n wire _beatsBO_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:264:61]\n wire _beatsBO_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:264:61]\n wire _beatsBO_opdata_T = 1'h0;\t// @[Edges.scala:97:37]\n wire _beatsCI_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _beatsCI_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _beatsCI_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _beatsCI_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _beatsCI_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _beatsCI_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire beatsCI_opdata = 1'h0;\t// @[Edges.scala:102:36]\n wire _beatsCI_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _beatsCI_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _beatsCI_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _beatsCI_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _beatsCI_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _beatsCI_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire beatsCI_opdata_1 = 1'h0;\t// @[Edges.scala:102:36]\n wire _beatsEI_WIRE_ready = 1'h0;\t// @[Bundles.scala:267:74]\n wire _beatsEI_WIRE_valid = 1'h0;\t// @[Bundles.scala:267:74]\n wire _beatsEI_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:267:61]\n wire _beatsEI_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:267:61]\n wire _beatsEI_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:267:74]\n wire _beatsEI_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:267:74]\n wire _beatsEI_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:267:61]\n wire _beatsEI_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:267:61]\n wire _portsBIO_WIRE_ready = 1'h0;\t// @[Bundles.scala:264:74]\n wire _portsBIO_WIRE_valid = 1'h0;\t// @[Bundles.scala:264:74]\n wire _portsBIO_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:264:74]\n wire _portsBIO_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:264:61]\n wire _portsBIO_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:264:61]\n wire _portsBIO_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:264:61]\n wire portsBIO_filtered_0_ready = 1'h0;\t// @[Xbar.scala:352:24]\n wire portsBIO_filtered_0_valid = 1'h0;\t// @[Xbar.scala:352:24]\n wire portsBIO_filtered_0_bits_corrupt = 1'h0;\t// @[Xbar.scala:352:24]\n wire portsBIO_filtered_1_ready = 1'h0;\t// @[Xbar.scala:352:24]\n wire portsBIO_filtered_1_valid = 1'h0;\t// @[Xbar.scala:352:24]\n wire portsBIO_filtered_1_bits_corrupt = 1'h0;\t// @[Xbar.scala:352:24]\n wire _portsBIO_filtered_0_valid_T = 1'h0;\t// @[Xbar.scala:355:54]\n wire _portsBIO_filtered_0_valid_T_1 = 1'h0;\t// @[Xbar.scala:355:40]\n wire _portsBIO_filtered_1_valid_T_1 = 1'h0;\t// @[Xbar.scala:355:40]\n wire _portsBIO_T = 1'h0;\t// @[Mux.scala:30:73]\n wire _portsBIO_T_1 = 1'h0;\t// @[Mux.scala:30:73]\n wire _portsBIO_T_2 = 1'h0;\t// @[Mux.scala:30:73]\n wire _portsBIO_WIRE_2 = 1'h0;\t// @[Mux.scala:30:73]\n wire _portsCOI_WIRE_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _portsCOI_WIRE_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _portsCOI_WIRE_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _portsCOI_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _portsCOI_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _portsCOI_WIRE_1_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire portsCOI_filtered_0_ready = 1'h0;\t// @[Xbar.scala:352:24]\n wire portsCOI_filtered_0_valid = 1'h0;\t// @[Xbar.scala:352:24]\n wire portsCOI_filtered_0_bits_corrupt = 1'h0;\t// @[Xbar.scala:352:24]\n wire _portsCOI_filtered_0_valid_T_1 = 1'h0;\t// @[Xbar.scala:355:40]\n wire _portsCOI_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:265:74]\n wire _portsCOI_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:265:74]\n wire _portsCOI_WIRE_2_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:74]\n wire _portsCOI_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:265:61]\n wire _portsCOI_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:265:61]\n wire _portsCOI_WIRE_3_bits_corrupt = 1'h0;\t// @[Bundles.scala:265:61]\n wire portsCOI_filtered_1_0_ready = 1'h0;\t// @[Xbar.scala:352:24]\n wire portsCOI_filtered_1_0_valid = 1'h0;\t// @[Xbar.scala:352:24]\n wire portsCOI_filtered_1_0_bits_corrupt = 1'h0;\t// @[Xbar.scala:352:24]\n wire _portsCOI_filtered_0_valid_T_3 = 1'h0;\t// @[Xbar.scala:355:40]\n wire _portsEOI_WIRE_ready = 1'h0;\t// @[Bundles.scala:267:74]\n wire _portsEOI_WIRE_valid = 1'h0;\t// @[Bundles.scala:267:74]\n wire _portsEOI_WIRE_1_ready = 1'h0;\t// @[Bundles.scala:267:61]\n wire _portsEOI_WIRE_1_valid = 1'h0;\t// @[Bundles.scala:267:61]\n wire portsEOI_filtered_0_ready = 1'h0;\t// @[Xbar.scala:352:24]\n wire portsEOI_filtered_0_valid = 1'h0;\t// @[Xbar.scala:352:24]\n wire _portsEOI_filtered_0_valid_T_1 = 1'h0;\t// @[Xbar.scala:355:40]\n wire _portsEOI_WIRE_2_ready = 1'h0;\t// @[Bundles.scala:267:74]\n wire _portsEOI_WIRE_2_valid = 1'h0;\t// @[Bundles.scala:267:74]\n wire _portsEOI_WIRE_3_ready = 1'h0;\t// @[Bundles.scala:267:61]\n wire _portsEOI_WIRE_3_valid = 1'h0;\t// @[Bundles.scala:267:61]\n wire portsEOI_filtered_1_0_ready = 1'h0;\t// @[Xbar.scala:352:24]\n wire portsEOI_filtered_1_0_valid = 1'h0;\t// @[Xbar.scala:352:24]\n wire _portsEOI_filtered_0_valid_T_3 = 1'h0;\t// @[Xbar.scala:355:40]\n wire _state_WIRE_0 = 1'h0;\t// @[Arbiter.scala:88:34]\n wire _state_WIRE_1 = 1'h0;\t// @[Arbiter.scala:88:34]\n wire _requestAIO_T_4 = 1'h1;\t// @[Parameters.scala:137:59]\n wire requestAIO_0_0 = 1'h1;\t// @[Xbar.scala:307:107]\n wire _requestAIO_T_9 = 1'h1;\t// @[Parameters.scala:137:59]\n wire requestAIO_1_0 = 1'h1;\t// @[Xbar.scala:307:107]\n wire _requestCIO_T_4 = 1'h1;\t// @[Parameters.scala:137:59]\n wire requestCIO_0_0 = 1'h1;\t// @[Xbar.scala:308:107]\n wire _requestCIO_T_9 = 1'h1;\t// @[Parameters.scala:137:59]\n wire requestCIO_1_0 = 1'h1;\t// @[Xbar.scala:308:107]\n wire _requestBOI_T_2 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _requestBOI_T_4 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _requestBOI_T_6 = 1'h1;\t// @[Parameters.scala:54:32]\n wire _requestBOI_T_7 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _requestBOI_T_8 = 1'h1;\t// @[Parameters.scala:54:67]\n wire _requestBOI_T_9 = 1'h1;\t// @[Parameters.scala:57:20]\n wire requestBOI_0_1 = 1'h1;\t// @[Parameters.scala:56:48]\n wire _requestDOI_T_2 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _requestDOI_T_4 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _requestDOI_T_7 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _requestDOI_T_9 = 1'h1;\t// @[Parameters.scala:57:20]\n wire _requestEIO_T_1 = 1'h1;\t// @[Parameters.scala:54:32]\n wire _requestEIO_T_2 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _requestEIO_T_3 = 1'h1;\t// @[Parameters.scala:54:67]\n wire _requestEIO_T_4 = 1'h1;\t// @[Parameters.scala:57:20]\n wire requestEIO_0_0 = 1'h1;\t// @[Parameters.scala:56:48]\n wire _requestEIO_T_6 = 1'h1;\t// @[Parameters.scala:54:32]\n wire _requestEIO_T_7 = 1'h1;\t// @[Parameters.scala:56:32]\n wire _requestEIO_T_8 = 1'h1;\t// @[Parameters.scala:54:67]\n wire _requestEIO_T_9 = 1'h1;\t// @[Parameters.scala:57:20]\n wire requestEIO_1_0 = 1'h1;\t// @[Parameters.scala:56:48]\n wire beatsBO_opdata = 1'h1;\t// @[Edges.scala:97:28]\n wire _portsAOI_filtered_0_valid_T = 1'h1;\t// @[Xbar.scala:355:54]\n wire _portsAOI_filtered_0_valid_T_2 = 1'h1;\t// @[Xbar.scala:355:54]\n wire _portsBIO_filtered_1_valid_T = 1'h1;\t// @[Xbar.scala:355:54]\n wire _portsCOI_filtered_0_valid_T = 1'h1;\t// @[Xbar.scala:355:54]\n wire _portsCOI_filtered_0_valid_T_2 = 1'h1;\t// @[Xbar.scala:355:54]\n wire _portsEOI_filtered_0_valid_T = 1'h1;\t// @[Xbar.scala:355:54]\n wire _portsEOI_filtered_0_valid_T_2 = 1'h1;\t// @[Xbar.scala:355:54]\n wire [3:0] _addressC_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _addressC_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _addressC_WIRE_2_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _addressC_WIRE_3_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _requestBOI_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:264:74]\n wire [3:0] _requestBOI_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:264:61]\n wire [3:0] requestBOI_uncommonBits = 4'h0;\t// @[Parameters.scala:52:56]\n wire [3:0] _requestBOI_WIRE_2_bits_size = 4'h0;\t// @[Bundles.scala:264:74]\n wire [3:0] _requestBOI_WIRE_3_bits_size = 4'h0;\t// @[Bundles.scala:264:61]\n wire [3:0] requestBOI_uncommonBits_1 = 4'h0;\t// @[Parameters.scala:52:56]\n wire [3:0] _requestEIO_WIRE_bits_sink = 4'h0;\t// @[Bundles.scala:267:74]\n wire [3:0] _requestEIO_WIRE_1_bits_sink = 4'h0;\t// @[Bundles.scala:267:61]\n wire [3:0] _requestEIO_uncommonBits_T = 4'h0;\t// @[Parameters.scala:52:29]\n wire [3:0] requestEIO_uncommonBits = 4'h0;\t// @[Parameters.scala:52:56]\n wire [3:0] _requestEIO_WIRE_2_bits_sink = 4'h0;\t// @[Bundles.scala:267:74]\n wire [3:0] _requestEIO_WIRE_3_bits_sink = 4'h0;\t// @[Bundles.scala:267:61]\n wire [3:0] _requestEIO_uncommonBits_T_1 = 4'h0;\t// @[Parameters.scala:52:29]\n wire [3:0] requestEIO_uncommonBits_1 = 4'h0;\t// @[Parameters.scala:52:56]\n wire [3:0] _beatsBO_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:264:74]\n wire [3:0] _beatsBO_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:264:61]\n wire [3:0] _beatsCI_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _beatsCI_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _beatsCI_WIRE_2_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _beatsCI_WIRE_3_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] _beatsEI_WIRE_bits_sink = 4'h0;\t// @[Bundles.scala:267:74]\n wire [3:0] _beatsEI_WIRE_1_bits_sink = 4'h0;\t// @[Bundles.scala:267:61]\n wire [3:0] _beatsEI_WIRE_2_bits_sink = 4'h0;\t// @[Bundles.scala:267:74]\n wire [3:0] _beatsEI_WIRE_3_bits_sink = 4'h0;\t// @[Bundles.scala:267:61]\n wire [3:0] _portsBIO_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:264:74]\n wire [3:0] _portsBIO_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:264:61]\n wire [3:0] portsBIO_filtered_0_bits_size = 4'h0;\t// @[Xbar.scala:352:24]\n wire [3:0] portsBIO_filtered_1_bits_size = 4'h0;\t// @[Xbar.scala:352:24]\n wire [3:0] _portsCOI_WIRE_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _portsCOI_WIRE_1_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] portsCOI_filtered_0_bits_size = 4'h0;\t// @[Xbar.scala:352:24]\n wire [3:0] _portsCOI_WIRE_2_bits_size = 4'h0;\t// @[Bundles.scala:265:74]\n wire [3:0] _portsCOI_WIRE_3_bits_size = 4'h0;\t// @[Bundles.scala:265:61]\n wire [3:0] portsCOI_filtered_1_0_bits_size = 4'h0;\t// @[Xbar.scala:352:24]\n wire [3:0] _portsEOI_WIRE_bits_sink = 4'h0;\t// @[Bundles.scala:267:74]\n wire [3:0] _portsEOI_WIRE_1_bits_sink = 4'h0;\t// @[Bundles.scala:267:61]\n wire [3:0] portsEOI_filtered_0_bits_sink = 4'h0;\t// @[Xbar.scala:352:24]\n wire [3:0] _portsEOI_WIRE_2_bits_sink = 4'h0;\t// @[Bundles.scala:267:74]\n wire [3:0] _portsEOI_WIRE_3_bits_sink = 4'h0;\t// @[Bundles.scala:267:61]\n wire [3:0] portsEOI_filtered_1_0_bits_sink = 4'h0;\t// @[Xbar.scala:352:24]\n wire [127:0] _addressC_WIRE_bits_data = 128'h0;\t// @[Bundles.scala:265:74]\n wire [127:0] _addressC_WIRE_1_bits_data = 128'h0;\t// @[Bundles.scala:265:61]\n wire [127:0] _addressC_WIRE_2_bits_data = 128'h0;\t// @[Bundles.scala:265:74]\n wire [127:0] _addressC_WIRE_3_bits_data = 128'h0;\t// @[Bundles.scala:265:61]\n wire [127:0] _requestBOI_WIRE_bits_data = 128'h0;\t// @[Bundles.scala:264:74]\n wire [127:0] _requestBOI_WIRE_1_bits_data = 128'h0;\t// @[Bundles.scala:264:61]\n wire [127:0] _requestBOI_WIRE_2_bits_data = 128'h0;\t// @[Bundles.scala:264:74]\n wire [127:0] _requestBOI_WIRE_3_bits_data = 128'h0;\t// @[Bundles.scala:264:61]\n wire [127:0] _beatsBO_WIRE_bits_data = 128'h0;\t// @[Bundles.scala:264:74]\n wire [127:0] _beatsBO_WIRE_1_bits_data = 128'h0;\t// @[Bundles.scala:264:61]\n wire [127:0] _beatsCI_WIRE_bits_data = 128'h0;\t// @[Bundles.scala:265:74]\n wire [127:0] _beatsCI_WIRE_1_bits_data = 128'h0;\t// @[Bundles.scala:265:61]\n wire [127:0] _beatsCI_WIRE_2_bits_data = 128'h0;\t// @[Bundles.scala:265:74]\n wire [127:0] _beatsCI_WIRE_3_bits_data = 128'h0;\t// @[Bundles.scala:265:61]\n wire [127:0] _portsBIO_WIRE_bits_data = 128'h0;\t// @[Bundles.scala:264:74]\n wire [127:0] _portsBIO_WIRE_1_bits_data = 128'h0;\t// @[Bundles.scala:264:61]\n wire [127:0] portsBIO_filtered_0_bits_data = 128'h0;\t// @[Xbar.scala:352:24]\n wire [127:0] portsBIO_filtered_1_bits_data = 128'h0;\t// @[Xbar.scala:352:24]\n wire [127:0] _portsCOI_WIRE_bits_data = 128'h0;\t// @[Bundles.scala:265:74]\n wire [127:0] _portsCOI_WIRE_1_bits_data = 128'h0;\t// @[Bundles.scala:265:61]\n wire [127:0] portsCOI_filtered_0_bits_data = 128'h0;\t// @[Xbar.scala:352:24]\n wire [127:0] _portsCOI_WIRE_2_bits_data = 128'h0;\t// @[Bundles.scala:265:74]\n wire [127:0] _portsCOI_WIRE_3_bits_data = 128'h0;\t// @[Bundles.scala:265:61]\n wire [127:0] portsCOI_filtered_1_0_bits_data = 128'h0;\t// @[Xbar.scala:352:24]\n wire [31:0] _addressC_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _addressC_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _addressC_WIRE_2_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _addressC_WIRE_3_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _requestCIO_T = 32'h0;\t// @[Parameters.scala:137:31]\n wire [31:0] _requestCIO_T_5 = 32'h0;\t// @[Parameters.scala:137:31]\n wire [31:0] _requestBOI_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:264:74]\n wire [31:0] _requestBOI_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:264:61]\n wire [31:0] _requestBOI_WIRE_2_bits_address = 32'h0;\t// @[Bundles.scala:264:74]\n wire [31:0] _requestBOI_WIRE_3_bits_address = 32'h0;\t// @[Bundles.scala:264:61]\n wire [31:0] _beatsBO_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:264:74]\n wire [31:0] _beatsBO_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:264:61]\n wire [31:0] _beatsCI_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _beatsCI_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _beatsCI_WIRE_2_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _beatsCI_WIRE_3_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] _portsBIO_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:264:74]\n wire [31:0] _portsBIO_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:264:61]\n wire [31:0] portsBIO_filtered_0_bits_address = 32'h0;\t// @[Xbar.scala:352:24]\n wire [31:0] portsBIO_filtered_1_bits_address = 32'h0;\t// @[Xbar.scala:352:24]\n wire [31:0] _portsCOI_WIRE_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _portsCOI_WIRE_1_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] portsCOI_filtered_0_bits_address = 32'h0;\t// @[Xbar.scala:352:24]\n wire [31:0] _portsCOI_WIRE_2_bits_address = 32'h0;\t// @[Bundles.scala:265:74]\n wire [31:0] _portsCOI_WIRE_3_bits_address = 32'h0;\t// @[Bundles.scala:265:61]\n wire [31:0] portsCOI_filtered_1_0_bits_address = 32'h0;\t// @[Xbar.scala:352:24]\n wire [4:0] _addressC_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _addressC_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _addressC_WIRE_2_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _addressC_WIRE_3_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _requestBOI_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:264:74]\n wire [4:0] _requestBOI_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:264:61]\n wire [4:0] _requestBOI_uncommonBits_T = 5'h0;\t// @[Parameters.scala:52:29]\n wire [4:0] _requestBOI_WIRE_2_bits_source = 5'h0;\t// @[Bundles.scala:264:74]\n wire [4:0] _requestBOI_WIRE_3_bits_source = 5'h0;\t// @[Bundles.scala:264:61]\n wire [4:0] _requestBOI_uncommonBits_T_1 = 5'h0;\t// @[Parameters.scala:52:29]\n wire [4:0] _beatsBO_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:264:74]\n wire [4:0] _beatsBO_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:264:61]\n wire [4:0] _beatsCI_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _beatsCI_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _beatsCI_WIRE_2_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _beatsCI_WIRE_3_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] _portsBIO_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:264:74]\n wire [4:0] _portsBIO_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:264:61]\n wire [4:0] portsBIO_filtered_0_bits_source = 5'h0;\t// @[Xbar.scala:352:24]\n wire [4:0] portsBIO_filtered_1_bits_source = 5'h0;\t// @[Xbar.scala:352:24]\n wire [4:0] _portsCOI_WIRE_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _portsCOI_WIRE_1_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] portsCOI_filtered_0_bits_source = 5'h0;\t// @[Xbar.scala:352:24]\n wire [4:0] _portsCOI_WIRE_2_bits_source = 5'h0;\t// @[Bundles.scala:265:74]\n wire [4:0] _portsCOI_WIRE_3_bits_source = 5'h0;\t// @[Bundles.scala:265:61]\n wire [4:0] portsCOI_filtered_1_0_bits_source = 5'h0;\t// @[Xbar.scala:352:24]\n wire [2:0] _addressC_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _addressC_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _addressC_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _addressC_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _addressC_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _addressC_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _addressC_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:264:74]\n wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:264:61]\n wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:264:74]\n wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:264:61]\n wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:264:74]\n wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:264:61]\n wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _beatsCI_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _beatsCI_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _beatsCI_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _beatsCI_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _beatsCI_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:264:74]\n wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:264:61]\n wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0;\t// @[Xbar.scala:352:24]\n wire [2:0] portsBIO_filtered_1_bits_opcode = 3'h0;\t// @[Xbar.scala:352:24]\n wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _portsCOI_WIRE_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0;\t// @[Xbar.scala:352:24]\n wire [2:0] portsCOI_filtered_0_bits_param = 3'h0;\t// @[Xbar.scala:352:24]\n wire [2:0] _portsCOI_WIRE_2_bits_opcode = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _portsCOI_WIRE_2_bits_param = 3'h0;\t// @[Bundles.scala:265:74]\n wire [2:0] _portsCOI_WIRE_3_bits_opcode = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] _portsCOI_WIRE_3_bits_param = 3'h0;\t// @[Bundles.scala:265:61]\n wire [2:0] portsCOI_filtered_1_0_bits_opcode = 3'h0;\t// @[Xbar.scala:352:24]\n wire [2:0] portsCOI_filtered_1_0_bits_param = 3'h0;\t// @[Xbar.scala:352:24]\n wire [15:0] _requestBOI_WIRE_bits_mask = 16'h0;\t// @[Bundles.scala:264:74]\n wire [15:0] _requestBOI_WIRE_1_bits_mask = 16'h0;\t// @[Bundles.scala:264:61]\n wire [15:0] _requestBOI_WIRE_2_bits_mask = 16'h0;\t// @[Bundles.scala:264:74]\n wire [15:0] _requestBOI_WIRE_3_bits_mask = 16'h0;\t// @[Bundles.scala:264:61]\n wire [15:0] _beatsBO_WIRE_bits_mask = 16'h0;\t// @[Bundles.scala:264:74]\n wire [15:0] _beatsBO_WIRE_1_bits_mask = 16'h0;\t// @[Bundles.scala:264:61]\n wire [15:0] _portsBIO_WIRE_bits_mask = 16'h0;\t// @[Bundles.scala:264:74]\n wire [15:0] _portsBIO_WIRE_1_bits_mask = 16'h0;\t// @[Bundles.scala:264:61]\n wire [15:0] portsBIO_filtered_0_bits_mask = 16'h0;\t// @[Xbar.scala:352:24]\n wire [15:0] portsBIO_filtered_1_bits_mask = 16'h0;\t// @[Xbar.scala:352:24]\n wire [1:0] _requestBOI_WIRE_bits_param = 2'h0;\t// @[Bundles.scala:264:74]\n wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0;\t// @[Bundles.scala:264:61]\n wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0;\t// @[Bundles.scala:264:74]\n wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0;\t// @[Bundles.scala:264:61]\n wire [1:0] _beatsBO_WIRE_bits_param = 2'h0;\t// @[Bundles.scala:264:74]\n wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0;\t// @[Bundles.scala:264:61]\n wire [1:0] _portsBIO_WIRE_bits_param = 2'h0;\t// @[Bundles.scala:264:74]\n wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0;\t// @[Bundles.scala:264:61]\n wire [1:0] portsBIO_filtered_0_bits_param = 2'h0;\t// @[Xbar.scala:352:24]\n wire [1:0] portsBIO_filtered_1_bits_param = 2'h0;\t// @[Xbar.scala:352:24]\n wire [7:0] beatsBO_decode = 8'h0;\t// @[Edges.scala:220:59]\n wire [7:0] beatsBO_0 = 8'h0;\t// @[Edges.scala:221:14]\n wire [7:0] beatsCI_decode = 8'h0;\t// @[Edges.scala:220:59]\n wire [7:0] beatsCI_0 = 8'h0;\t// @[Edges.scala:221:14]\n wire [7:0] beatsCI_decode_1 = 8'h0;\t// @[Edges.scala:220:59]\n wire [7:0] beatsCI_1 = 8'h0;\t// @[Edges.scala:221:14]\n wire [11:0] _beatsBO_decode_T_2 = 12'h0;\t// @[package.scala:243:46]\n wire [11:0] _beatsCI_decode_T_2 = 12'h0;\t// @[package.scala:243:46]\n wire [11:0] _beatsCI_decode_T_5 = 12'h0;\t// @[package.scala:243:46]\n wire [11:0] _beatsBO_decode_T_1 = 12'hFFF;\t// @[package.scala:243:76]\n wire [11:0] _beatsCI_decode_T_1 = 12'hFFF;\t// @[package.scala:243:76]\n wire [11:0] _beatsCI_decode_T_4 = 12'hFFF;\t// @[package.scala:243:76]\n wire [26:0] _beatsBO_decode_T = 27'hFFF;\t// @[package.scala:243:71]\n wire [26:0] _beatsCI_decode_T = 27'hFFF;\t// @[package.scala:243:71]\n wire [26:0] _beatsCI_decode_T_3 = 27'hFFF;\t// @[package.scala:243:71]\n wire [32:0] _requestAIO_T_2 = 33'h0;\t// @[Parameters.scala:137:46]\n wire [32:0] _requestAIO_T_3 = 33'h0;\t// @[Parameters.scala:137:46]\n wire [32:0] _requestAIO_T_7 = 33'h0;\t// @[Parameters.scala:137:46]\n wire [32:0] _requestAIO_T_8 = 33'h0;\t// @[Parameters.scala:137:46]\n wire [32:0] _requestCIO_T_1 = 33'h0;\t// @[Parameters.scala:137:41]\n wire [32:0] _requestCIO_T_2 = 33'h0;\t// @[Parameters.scala:137:46]\n wire [32:0] _requestCIO_T_3 = 33'h0;\t// @[Parameters.scala:137:46]\n wire [32:0] _requestCIO_T_6 = 33'h0;\t// @[Parameters.scala:137:41]\n wire [32:0] _requestCIO_T_7 = 33'h0;\t// @[Parameters.scala:137:46]\n wire [32:0] _requestCIO_T_8 = 33'h0;\t// @[Parameters.scala:137:46]\n wire anonIn_1_a_ready;\t// @[MixedNode.scala:551:17]\n wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0;\t// @[Xbar.scala:74:9]\n wire [2:0] anonIn_1_a_bits_opcode = auto_anon_in_1_a_bits_opcode_0;\t// @[Xbar.scala:74:9]\n wire [2:0] anonIn_1_a_bits_param = auto_anon_in_1_a_bits_param_0;\t// @[Xbar.scala:74:9]\n wire [3:0] anonIn_1_a_bits_size = auto_anon_in_1_a_bits_size_0;\t// @[Xbar.scala:74:9]\n wire [3:0] anonIn_1_a_bits_source = auto_anon_in_1_a_bits_source_0;\t// @[Xbar.scala:74:9]\n wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0;\t// @[Xbar.scala:74:9]\n wire [15:0] anonIn_1_a_bits_mask = auto_anon_in_1_a_bits_mask_0;\t// @[Xbar.scala:74:9]\n wire [127:0] anonIn_1_a_bits_data = auto_anon_in_1_a_bits_data_0;\t// @[Xbar.scala:74:9]\n wire anonIn_1_a_bits_corrupt = auto_anon_in_1_a_bits_corrupt_0;\t// @[Xbar.scala:74:9]\n wire anonIn_1_d_ready = auto_anon_in_1_d_ready_0;\t// @[Xbar.scala:74:9]\n wire anonIn_1_d_valid;\t// @[MixedNode.scala:551:17]\n wire [2:0] anonIn_1_d_bits_opcode;\t// @[MixedNode.scala:551:17]\n wire [1:0] anonIn_1_d_bits_param;\t// @[MixedNode.scala:551:17]\n wire [3:0] anonIn_1_d_bits_size;\t// @[MixedNode.scala:551:17]\n wire [3:0] anonIn_1_d_bits_source;\t// @[MixedNode.scala:551:17]\n wire [3:0] anonIn_1_d_bits_sink;\t// @[MixedNode.scala:551:17]\n wire anonIn_1_d_bits_denied;\t// @[MixedNode.scala:551:17]\n wire [127:0] anonIn_1_d_bits_data;\t// @[MixedNode.scala:551:17]\n wire anonIn_1_d_bits_corrupt;\t// @[MixedNode.scala:551:17]\n wire anonIn_a_ready;\t// @[MixedNode.scala:551:17]\n wire anonIn_a_valid = auto_anon_in_0_a_valid_0;\t// @[Xbar.scala:74:9]\n wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0;\t// @[Xbar.scala:74:9]\n wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0;\t// @[Xbar.scala:74:9]\n wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0;\t// @[Xbar.scala:74:9]\n wire [3:0] anonIn_a_bits_source = auto_anon_in_0_a_bits_source_0;\t// @[Xbar.scala:74:9]\n wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0;\t// @[Xbar.scala:74:9]\n wire [15:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0;\t// @[Xbar.scala:74:9]\n wire [127:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0;\t// @[Xbar.scala:74:9]\n wire anonIn_a_bits_corrupt = auto_anon_in_0_a_bits_corrupt_0;\t// @[Xbar.scala:74:9]\n wire anonIn_d_ready = auto_anon_in_0_d_ready_0;\t// @[Xbar.scala:74:9]\n wire anonIn_d_valid;\t// @[MixedNode.scala:551:17]\n wire [2:0] anonIn_d_bits_opcode;\t// @[MixedNode.scala:551:17]\n wire [1:0] anonIn_d_bits_param;\t// @[MixedNode.scala:551:17]\n wire [3:0] anonIn_d_bits_size;\t// @[MixedNode.scala:551:17]\n wire [3:0] anonIn_d_bits_source;\t// @[MixedNode.scala:551:17]\n wire [3:0] anonIn_d_bits_sink;\t// @[MixedNode.scala:551:17]\n wire anonIn_d_bits_denied;\t// @[MixedNode.scala:551:17]\n wire [127:0] anonIn_d_bits_data;\t// @[MixedNode.scala:551:17]\n wire anonIn_d_bits_corrupt;\t// @[MixedNode.scala:551:17]\n wire anonOut_a_ready = auto_anon_out_a_ready_0;\t// @[Xbar.scala:74:9]\n wire anonOut_a_valid;\t// @[MixedNode.scala:542:17]\n wire [2:0] anonOut_a_bits_opcode;\t// @[MixedNode.scala:542:17]\n wire [2:0] anonOut_a_bits_param;\t// @[MixedNode.scala:542:17]\n wire [3:0] anonOut_a_bits_size;\t// @[MixedNode.scala:542:17]\n wire [4:0] anonOut_a_bits_source;\t// @[MixedNode.scala:542:17]\n wire [31:0] anonOut_a_bits_address;\t// @[MixedNode.scala:542:17]\n wire [15:0] anonOut_a_bits_mask;\t// @[MixedNode.scala:542:17]\n wire [127:0] anonOut_a_bits_data;\t// @[MixedNode.scala:542:17]\n wire anonOut_a_bits_corrupt;\t// @[MixedNode.scala:542:17]\n wire anonOut_d_ready;\t// @[MixedNode.scala:542:17]\n wire anonOut_d_valid = auto_anon_out_d_valid_0;\t// @[Xbar.scala:74:9]\n wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0;\t// @[Xbar.scala:74:9]\n wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0;\t// @[Xbar.scala:74:9]\n wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0;\t// @[Xbar.scala:74:9]\n wire [4:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0;\t// @[Xbar.scala:74:9]\n wire [3:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0;\t// @[Xbar.scala:74:9]\n wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0;\t// @[Xbar.scala:74:9]\n wire [127:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0;\t// @[Xbar.scala:74:9]\n wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_1_a_ready_0;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_in_1_d_bits_opcode_0;\t// @[Xbar.scala:74:9]\n wire [1:0] auto_anon_in_1_d_bits_param_0;\t// @[Xbar.scala:74:9]\n wire [3:0] auto_anon_in_1_d_bits_size_0;\t// @[Xbar.scala:74:9]\n wire [3:0] auto_anon_in_1_d_bits_source_0;\t// @[Xbar.scala:74:9]\n wire [3:0] auto_anon_in_1_d_bits_sink_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_1_d_bits_denied_0;\t// @[Xbar.scala:74:9]\n wire [127:0] auto_anon_in_1_d_bits_data_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_1_d_bits_corrupt_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_1_d_valid_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_a_ready_0;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_in_0_d_bits_opcode_0;\t// @[Xbar.scala:74:9]\n wire [1:0] auto_anon_in_0_d_bits_param_0;\t// @[Xbar.scala:74:9]\n wire [3:0] auto_anon_in_0_d_bits_size_0;\t// @[Xbar.scala:74:9]\n wire [3:0] auto_anon_in_0_d_bits_source_0;\t// @[Xbar.scala:74:9]\n wire [3:0] auto_anon_in_0_d_bits_sink_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_d_bits_denied_0;\t// @[Xbar.scala:74:9]\n wire [127:0] auto_anon_in_0_d_bits_data_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_d_bits_corrupt_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_in_0_d_valid_0;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_out_a_bits_opcode_0;\t// @[Xbar.scala:74:9]\n wire [2:0] auto_anon_out_a_bits_param_0;\t// @[Xbar.scala:74:9]\n wire [3:0] auto_anon_out_a_bits_size_0;\t// @[Xbar.scala:74:9]\n wire [4:0] auto_anon_out_a_bits_source_0;\t// @[Xbar.scala:74:9]\n wire [31:0] auto_anon_out_a_bits_address_0;\t// @[Xbar.scala:74:9]\n wire [15:0] auto_anon_out_a_bits_mask_0;\t// @[Xbar.scala:74:9]\n wire [127:0] auto_anon_out_a_bits_data_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_out_a_bits_corrupt_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_out_a_valid_0;\t// @[Xbar.scala:74:9]\n wire auto_anon_out_d_ready_0;\t// @[Xbar.scala:74:9]\n wire in_0_a_ready;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_a_ready_0 = anonIn_a_ready;\t// @[Xbar.scala:74:9]\n wire in_0_a_valid = anonIn_a_valid;\t// @[Xbar.scala:159:18]\n wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode;\t// @[Xbar.scala:159:18]\n wire [2:0] in_0_a_bits_param = anonIn_a_bits_param;\t// @[Xbar.scala:159:18]\n wire [3:0] in_0_a_bits_size = anonIn_a_bits_size;\t// @[Xbar.scala:159:18]\n wire [31:0] in_0_a_bits_address = anonIn_a_bits_address;\t// @[Xbar.scala:159:18]\n wire [15:0] in_0_a_bits_mask = anonIn_a_bits_mask;\t// @[Xbar.scala:159:18]\n wire [127:0] in_0_a_bits_data = anonIn_a_bits_data;\t// @[Xbar.scala:159:18]\n wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt;\t// @[Xbar.scala:159:18]\n wire in_0_d_ready = anonIn_d_ready;\t// @[Xbar.scala:159:18]\n wire in_0_d_valid;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_d_valid_0 = anonIn_d_valid;\t// @[Xbar.scala:74:9]\n wire [2:0] in_0_d_bits_opcode;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode;\t// @[Xbar.scala:74:9]\n wire [1:0] in_0_d_bits_param;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param;\t// @[Xbar.scala:74:9]\n wire [3:0] in_0_d_bits_size;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size;\t// @[Xbar.scala:74:9]\n wire [3:0] _anonIn_d_bits_source_T;\t// @[Xbar.scala:156:69]\n assign auto_anon_in_0_d_bits_source_0 = anonIn_d_bits_source;\t// @[Xbar.scala:74:9]\n wire [3:0] in_0_d_bits_sink;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink;\t// @[Xbar.scala:74:9]\n wire in_0_d_bits_denied;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied;\t// @[Xbar.scala:74:9]\n wire [127:0] in_0_d_bits_data;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data;\t// @[Xbar.scala:74:9]\n wire in_0_d_bits_corrupt;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt;\t// @[Xbar.scala:74:9]\n wire in_1_a_ready;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready;\t// @[Xbar.scala:74:9]\n wire in_1_a_valid = anonIn_1_a_valid;\t// @[Xbar.scala:159:18]\n wire [2:0] in_1_a_bits_opcode = anonIn_1_a_bits_opcode;\t// @[Xbar.scala:159:18]\n wire [2:0] in_1_a_bits_param = anonIn_1_a_bits_param;\t// @[Xbar.scala:159:18]\n wire [3:0] in_1_a_bits_size = anonIn_1_a_bits_size;\t// @[Xbar.scala:159:18]\n wire [3:0] _in_1_a_bits_source_T = anonIn_1_a_bits_source;\t// @[Xbar.scala:166:55]\n wire [31:0] in_1_a_bits_address = anonIn_1_a_bits_address;\t// @[Xbar.scala:159:18]\n wire [15:0] in_1_a_bits_mask = anonIn_1_a_bits_mask;\t// @[Xbar.scala:159:18]\n wire [127:0] in_1_a_bits_data = anonIn_1_a_bits_data;\t// @[Xbar.scala:159:18]\n wire in_1_a_bits_corrupt = anonIn_1_a_bits_corrupt;\t// @[Xbar.scala:159:18]\n wire in_1_d_ready = anonIn_1_d_ready;\t// @[Xbar.scala:159:18]\n wire in_1_d_valid;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid;\t// @[Xbar.scala:74:9]\n wire [2:0] in_1_d_bits_opcode;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode;\t// @[Xbar.scala:74:9]\n wire [1:0] in_1_d_bits_param;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param;\t// @[Xbar.scala:74:9]\n wire [3:0] in_1_d_bits_size;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size;\t// @[Xbar.scala:74:9]\n wire [3:0] _anonIn_d_bits_source_T_1;\t// @[Xbar.scala:156:69]\n assign auto_anon_in_1_d_bits_source_0 = anonIn_1_d_bits_source;\t// @[Xbar.scala:74:9]\n wire [3:0] in_1_d_bits_sink;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink;\t// @[Xbar.scala:74:9]\n wire in_1_d_bits_denied;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied;\t// @[Xbar.scala:74:9]\n wire [127:0] in_1_d_bits_data;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data;\t// @[Xbar.scala:74:9]\n wire in_1_d_bits_corrupt;\t// @[Xbar.scala:159:18]\n assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt;\t// @[Xbar.scala:74:9]\n wire out_0_a_ready = anonOut_a_ready;\t// @[Xbar.scala:216:19]\n wire out_0_a_valid;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_a_valid_0 = anonOut_a_valid;\t// @[Xbar.scala:74:9]\n wire [2:0] out_0_a_bits_opcode;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode;\t// @[Xbar.scala:74:9]\n wire [2:0] out_0_a_bits_param;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param;\t// @[Xbar.scala:74:9]\n wire [3:0] out_0_a_bits_size;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size;\t// @[Xbar.scala:74:9]\n wire [4:0] out_0_a_bits_source;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source;\t// @[Xbar.scala:74:9]\n wire [31:0] out_0_a_bits_address;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address;\t// @[Xbar.scala:74:9]\n wire [15:0] out_0_a_bits_mask;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask;\t// @[Xbar.scala:74:9]\n wire [127:0] out_0_a_bits_data;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data;\t// @[Xbar.scala:74:9]\n wire out_0_a_bits_corrupt;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt;\t// @[Xbar.scala:74:9]\n wire out_0_d_ready;\t// @[Xbar.scala:216:19]\n assign auto_anon_out_d_ready_0 = anonOut_d_ready;\t// @[Xbar.scala:74:9]\n wire out_0_d_valid = anonOut_d_valid;\t// @[Xbar.scala:216:19]\n wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode;\t// @[Xbar.scala:216:19]\n wire [1:0] out_0_d_bits_param = anonOut_d_bits_param;\t// @[Xbar.scala:216:19]\n wire [3:0] out_0_d_bits_size = anonOut_d_bits_size;\t// @[Xbar.scala:216:19]\n wire [4:0] out_0_d_bits_source = anonOut_d_bits_source;\t// @[Xbar.scala:216:19]\n wire [3:0] _out_0_d_bits_sink_T = anonOut_d_bits_sink;\t// @[Xbar.scala:251:53]\n wire out_0_d_bits_denied = anonOut_d_bits_denied;\t// @[Xbar.scala:216:19]\n wire [127:0] out_0_d_bits_data = anonOut_d_bits_data;\t// @[Xbar.scala:216:19]\n wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt;\t// @[Xbar.scala:216:19]\n wire portsAOI_filtered_0_ready;\t// @[Xbar.scala:352:24]\n assign anonIn_a_ready = in_0_a_ready;\t// @[Xbar.scala:159:18]\n wire _portsAOI_filtered_0_valid_T_1 = in_0_a_valid;\t// @[Xbar.scala:159:18, :355:40]\n wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode;\t// @[Xbar.scala:159:18, :352:24]\n wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param;\t// @[Xbar.scala:159:18, :352:24]\n wire [4:0] _in_0_a_bits_source_T;\t// @[Xbar.scala:166:55]\n wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size;\t// @[Xbar.scala:159:18, :352:24]\n wire [4:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source;\t// @[Xbar.scala:159:18, :352:24]\n wire [31:0] _requestAIO_T = in_0_a_bits_address;\t// @[Xbar.scala:159:18]\n wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address;\t// @[Xbar.scala:159:18, :352:24]\n wire [15:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask;\t// @[Xbar.scala:159:18, :352:24]\n wire [127:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data;\t// @[Xbar.scala:159:18, :352:24]\n wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt;\t// @[Xbar.scala:159:18, :352:24]\n wire portsDIO_filtered_0_ready = in_0_d_ready;\t// @[Xbar.scala:159:18, :352:24]\n wire portsDIO_filtered_0_valid;\t// @[Xbar.scala:352:24]\n assign anonIn_d_valid = in_0_d_valid;\t// @[Xbar.scala:159:18]\n wire [2:0] portsDIO_filtered_0_bits_opcode;\t// @[Xbar.scala:352:24]\n assign anonIn_d_bits_opcode = in_0_d_bits_opcode;\t// @[Xbar.scala:159:18]\n wire [1:0] portsDIO_filtered_0_bits_param;\t// @[Xbar.scala:352:24]\n assign anonIn_d_bits_param = in_0_d_bits_param;\t// @[Xbar.scala:159:18]\n wire [3:0] portsDIO_filtered_0_bits_size;\t// @[Xbar.scala:352:24]\n assign anonIn_d_bits_size = in_0_d_bits_size;\t// @[Xbar.scala:159:18]\n wire [4:0] portsDIO_filtered_0_bits_source;\t// @[Xbar.scala:352:24]\n wire [3:0] portsDIO_filtered_0_bits_sink;\t// @[Xbar.scala:352:24]\n assign anonIn_d_bits_sink = in_0_d_bits_sink;\t// @[Xbar.scala:159:18]\n wire portsDIO_filtered_0_bits_denied;\t// @[Xbar.scala:352:24]\n assign anonIn_d_bits_denied = in_0_d_bits_denied;\t// @[Xbar.scala:159:18]\n wire [127:0] portsDIO_filtered_0_bits_data;\t// @[Xbar.scala:352:24]\n assign anonIn_d_bits_data = in_0_d_bits_data;\t// @[Xbar.scala:159:18]\n wire portsDIO_filtered_0_bits_corrupt;\t// @[Xbar.scala:352:24]\n assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt;\t// @[Xbar.scala:159:18]\n wire portsAOI_filtered_1_0_ready;\t// @[Xbar.scala:352:24]\n assign anonIn_1_a_ready = in_1_a_ready;\t// @[Xbar.scala:159:18]\n wire _portsAOI_filtered_0_valid_T_3 = in_1_a_valid;\t// @[Xbar.scala:159:18, :355:40]\n wire [2:0] portsAOI_filtered_1_0_bits_opcode = in_1_a_bits_opcode;\t// @[Xbar.scala:159:18, :352:24]\n wire [2:0] portsAOI_filtered_1_0_bits_param = in_1_a_bits_param;\t// @[Xbar.scala:159:18, :352:24]\n wire [3:0] portsAOI_filtered_1_0_bits_size = in_1_a_bits_size;\t// @[Xbar.scala:159:18, :352:24]\n wire [4:0] portsAOI_filtered_1_0_bits_source = in_1_a_bits_source;\t// @[Xbar.scala:159:18, :352:24]\n wire [31:0] _requestAIO_T_5 = in_1_a_bits_address;\t// @[Xbar.scala:159:18]\n wire [31:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address;\t// @[Xbar.scala:159:18, :352:24]\n wire [15:0] portsAOI_filtered_1_0_bits_mask = in_1_a_bits_mask;\t// @[Xbar.scala:159:18, :352:24]\n wire [127:0] portsAOI_filtered_1_0_bits_data = in_1_a_bits_data;\t// @[Xbar.scala:159:18, :352:24]\n wire portsAOI_filtered_1_0_bits_corrupt = in_1_a_bits_corrupt;\t// @[Xbar.scala:159:18, :352:24]\n wire portsDIO_filtered_1_ready = in_1_d_ready;\t// @[Xbar.scala:159:18, :352:24]\n wire portsDIO_filtered_1_valid;\t// @[Xbar.scala:352:24]\n assign anonIn_1_d_valid = in_1_d_valid;\t// @[Xbar.scala:159:18]\n wire [2:0] portsDIO_filtered_1_bits_opcode;\t// @[Xbar.scala:352:24]\n assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode;\t// @[Xbar.scala:159:18]\n wire [1:0] portsDIO_filtered_1_bits_param;\t// @[Xbar.scala:352:24]\n assign anonIn_1_d_bits_param = in_1_d_bits_param;\t// @[Xbar.scala:159:18]\n wire [3:0] portsDIO_filtered_1_bits_size;\t// @[Xbar.scala:352:24]\n assign anonIn_1_d_bits_size = in_1_d_bits_size;\t// @[Xbar.scala:159:18]\n wire [4:0] portsDIO_filtered_1_bits_source;\t// @[Xbar.scala:352:24]\n wire [3:0] portsDIO_filtered_1_bits_sink;\t// @[Xbar.scala:352:24]\n assign anonIn_1_d_bits_sink = in_1_d_bits_sink;\t// @[Xbar.scala:159:18]\n wire portsDIO_filtered_1_bits_denied;\t// @[Xbar.scala:352:24]\n assign anonIn_1_d_bits_denied = in_1_d_bits_denied;\t// @[Xbar.scala:159:18]\n wire [127:0] portsDIO_filtered_1_bits_data;\t// @[Xbar.scala:352:24]\n assign anonIn_1_d_bits_data = in_1_d_bits_data;\t// @[Xbar.scala:159:18]\n wire portsDIO_filtered_1_bits_corrupt;\t// @[Xbar.scala:352:24]\n assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt;\t// @[Xbar.scala:159:18]\n wire [4:0] in_0_d_bits_source;\t// @[Xbar.scala:159:18]\n wire [4:0] in_1_d_bits_source;\t// @[Xbar.scala:159:18]\n assign _in_0_a_bits_source_T = {1'h1, anonIn_a_bits_source};\t// @[Xbar.scala:166:55]\n assign in_0_a_bits_source = _in_0_a_bits_source_T;\t// @[Xbar.scala:159:18, :166:55]\n assign _anonIn_d_bits_source_T = in_0_d_bits_source[3:0];\t// @[Xbar.scala:156:69, :159:18]\n assign anonIn_d_bits_source = _anonIn_d_bits_source_T;\t// @[Xbar.scala:156:69]\n assign in_1_a_bits_source = {1'h0, _in_1_a_bits_source_T};\t// @[Xbar.scala:159:18, :166:{29,55}]\n assign _anonIn_d_bits_source_T_1 = in_1_d_bits_source[3:0];\t// @[Xbar.scala:156:69, :159:18]\n assign anonIn_1_d_bits_source = _anonIn_d_bits_source_T_1;\t// @[Xbar.scala:156:69]\n wire _out_0_a_valid_T_4;\t// @[Arbiter.scala:96:24]\n assign anonOut_a_valid = out_0_a_valid;\t// @[Xbar.scala:216:19]\n wire [2:0] _out_0_a_bits_WIRE_opcode;\t// @[Mux.scala:30:73]\n assign anonOut_a_bits_opcode = out_0_a_bits_opcode;\t// @[Xbar.scala:216:19]\n wire [2:0] _out_0_a_bits_WIRE_param;\t// @[Mux.scala:30:73]\n assign anonOut_a_bits_param = out_0_a_bits_param;\t// @[Xbar.scala:216:19]\n wire [3:0] _out_0_a_bits_WIRE_size;\t// @[Mux.scala:30:73]\n assign anonOut_a_bits_size = out_0_a_bits_size;\t// @[Xbar.scala:216:19]\n wire [4:0] _out_0_a_bits_WIRE_source;\t// @[Mux.scala:30:73]\n assign anonOut_a_bits_source = out_0_a_bits_source;\t// @[Xbar.scala:216:19]\n wire [31:0] _out_0_a_bits_WIRE_address;\t// @[Mux.scala:30:73]\n assign anonOut_a_bits_address = out_0_a_bits_address;\t// @[Xbar.scala:216:19]\n wire [15:0] _out_0_a_bits_WIRE_mask;\t// @[Mux.scala:30:73]\n assign anonOut_a_bits_mask = out_0_a_bits_mask;\t// @[Xbar.scala:216:19]\n wire [127:0] _out_0_a_bits_WIRE_data;\t// @[Mux.scala:30:73]\n assign anonOut_a_bits_data = out_0_a_bits_data;\t// @[Xbar.scala:216:19]\n wire _out_0_a_bits_WIRE_corrupt;\t// @[Mux.scala:30:73]\n assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt;\t// @[Xbar.scala:216:19]\n wire _portsDIO_out_0_d_ready_WIRE;\t// @[Mux.scala:30:73]\n assign anonOut_d_ready = out_0_d_ready;\t// @[Xbar.scala:216:19]\n assign portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_0_bits_param = out_0_d_bits_param;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_1_bits_param = out_0_d_bits_param;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_0_bits_size = out_0_d_bits_size;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_1_bits_size = out_0_d_bits_size;\t// @[Xbar.scala:216:19, :352:24]\n wire [4:0] _requestDOI_uncommonBits_T = out_0_d_bits_source;\t// @[Xbar.scala:216:19]\n wire [4:0] _requestDOI_uncommonBits_T_1 = out_0_d_bits_source;\t// @[Xbar.scala:216:19]\n assign portsDIO_filtered_0_bits_source = out_0_d_bits_source;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_1_bits_source = out_0_d_bits_source;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_0_bits_sink = out_0_d_bits_sink;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_1_bits_sink = out_0_d_bits_sink;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_0_bits_denied = out_0_d_bits_denied;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_1_bits_denied = out_0_d_bits_denied;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_0_bits_data = out_0_d_bits_data;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_1_bits_data = out_0_d_bits_data;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt;\t// @[Xbar.scala:216:19, :352:24]\n assign portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt;\t// @[Xbar.scala:216:19, :352:24]\n assign out_0_d_bits_sink = _out_0_d_bits_sink_T;\t// @[Xbar.scala:216:19, :251:53]\n wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T};\t// @[Parameters.scala:137:{31,41}]\n wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5};\t// @[Parameters.scala:137:{31,41}]\n wire [3:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T[3:0];\t// @[Parameters.scala:52:{29,56}]\n wire _requestDOI_T = out_0_d_bits_source[4];\t// @[Xbar.scala:216:19]\n wire _requestDOI_T_5 = out_0_d_bits_source[4];\t// @[Xbar.scala:216:19]\n wire _requestDOI_T_1 = _requestDOI_T;\t// @[Parameters.scala:54:{10,32}]\n wire _requestDOI_T_3 = _requestDOI_T_1;\t// @[Parameters.scala:54:{32,67}]\n wire requestDOI_0_0 = _requestDOI_T_3;\t// @[Parameters.scala:54:67, :56:48]\n wire _portsDIO_filtered_0_valid_T = requestDOI_0_0;\t// @[Xbar.scala:355:54]\n wire [3:0] requestDOI_uncommonBits_1 = _requestDOI_uncommonBits_T_1[3:0];\t// @[Parameters.scala:52:{29,56}]\n wire _requestDOI_T_6 = ~_requestDOI_T_5;\t// @[Parameters.scala:54:{10,32}]\n wire _requestDOI_T_8 = _requestDOI_T_6;\t// @[Parameters.scala:54:{32,67}]\n wire requestDOI_0_1 = _requestDOI_T_8;\t// @[Parameters.scala:54:67, :56:48]\n wire _portsDIO_filtered_1_valid_T = requestDOI_0_1;\t// @[Xbar.scala:355:54]\n wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size;\t// @[package.scala:243:71]\n wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [7:0] beatsAI_decode = _beatsAI_decode_T_2[11:4];\t// @[package.scala:243:46]\n wire _beatsAI_opdata_T = in_0_a_bits_opcode[2];\t// @[Xbar.scala:159:18]\n wire beatsAI_opdata = ~_beatsAI_opdata_T;\t// @[Edges.scala:92:{28,37}]\n wire [7:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 8'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n wire [26:0] _beatsAI_decode_T_3 = 27'hFFF << in_1_a_bits_size;\t// @[package.scala:243:71]\n wire [11:0] _beatsAI_decode_T_4 = _beatsAI_decode_T_3[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _beatsAI_decode_T_5 = ~_beatsAI_decode_T_4;\t// @[package.scala:243:{46,76}]\n wire [7:0] beatsAI_decode_1 = _beatsAI_decode_T_5[11:4];\t// @[package.scala:243:46]\n wire _beatsAI_opdata_T_1 = in_1_a_bits_opcode[2];\t// @[Xbar.scala:159:18]\n wire beatsAI_opdata_1 = ~_beatsAI_opdata_T_1;\t// @[Edges.scala:92:{28,37}]\n wire [7:0] beatsAI_1 = beatsAI_opdata_1 ? beatsAI_decode_1 : 8'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size;\t// @[package.scala:243:71]\n wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0];\t// @[package.scala:243:{71,76}]\n wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [7:0] beatsDO_decode = _beatsDO_decode_T_2[11:4];\t// @[package.scala:243:46]\n wire beatsDO_opdata = out_0_d_bits_opcode[0];\t// @[Xbar.scala:216:19]\n wire [7:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 8'h0;\t// @[Edges.scala:106:36, :220:59, :221:14]\n wire _filtered_0_ready_T;\t// @[Arbiter.scala:94:31]\n assign in_0_a_ready = portsAOI_filtered_0_ready;\t// @[Xbar.scala:159:18, :352:24]\n wire portsAOI_filtered_0_valid;\t// @[Xbar.scala:352:24]\n assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1;\t// @[Xbar.scala:352:24, :355:40]\n wire _filtered_0_ready_T_1;\t// @[Arbiter.scala:94:31]\n assign in_1_a_ready = portsAOI_filtered_1_0_ready;\t// @[Xbar.scala:159:18, :352:24]\n wire portsAOI_filtered_1_0_valid;\t// @[Xbar.scala:352:24]\n assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3;\t// @[Xbar.scala:352:24, :355:40]\n wire _portsDIO_filtered_0_valid_T_1;\t// @[Xbar.scala:355:40]\n assign in_0_d_valid = portsDIO_filtered_0_valid;\t// @[Xbar.scala:159:18, :352:24]\n assign in_0_d_bits_opcode = portsDIO_filtered_0_bits_opcode;\t// @[Xbar.scala:159:18, :352:24]\n assign in_0_d_bits_param = portsDIO_filtered_0_bits_param;\t// @[Xbar.scala:159:18, :352:24]\n assign in_0_d_bits_size = portsDIO_filtered_0_bits_size;\t// @[Xbar.scala:159:18, :352:24]\n assign in_0_d_bits_source = portsDIO_filtered_0_bits_source;\t// @[Xbar.scala:159:18, :352:24]\n assign in_0_d_bits_sink = portsDIO_filtered_0_bits_sink;\t// @[Xbar.scala:159:18, :352:24]\n assign in_0_d_bits_denied = portsDIO_filtered_0_bits_denied;\t// @[Xbar.scala:159:18, :352:24]\n assign in_0_d_bits_data = portsDIO_filtered_0_bits_data;\t// @[Xbar.scala:159:18, :352:24]\n assign in_0_d_bits_corrupt = portsDIO_filtered_0_bits_corrupt;\t// @[Xbar.scala:159:18, :352:24]\n wire _portsDIO_filtered_1_valid_T_1;\t// @[Xbar.scala:355:40]\n assign in_1_d_valid = portsDIO_filtered_1_valid;\t// @[Xbar.scala:159:18, :352:24]\n assign in_1_d_bits_opcode = portsDIO_filtered_1_bits_opcode;\t// @[Xbar.scala:159:18, :352:24]\n assign in_1_d_bits_param = portsDIO_filtered_1_bits_param;\t// @[Xbar.scala:159:18, :352:24]\n assign in_1_d_bits_size = portsDIO_filtered_1_bits_size;\t// @[Xbar.scala:159:18, :352:24]\n assign in_1_d_bits_source = portsDIO_filtered_1_bits_source;\t// @[Xbar.scala:159:18, :352:24]\n assign in_1_d_bits_sink = portsDIO_filtered_1_bits_sink;\t// @[Xbar.scala:159:18, :352:24]\n assign in_1_d_bits_denied = portsDIO_filtered_1_bits_denied;\t// @[Xbar.scala:159:18, :352:24]\n assign in_1_d_bits_data = portsDIO_filtered_1_bits_data;\t// @[Xbar.scala:159:18, :352:24]\n assign in_1_d_bits_corrupt = portsDIO_filtered_1_bits_corrupt;\t// @[Xbar.scala:159:18, :352:24]\n assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T;\t// @[Xbar.scala:216:19, :355:{40,54}]\n assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1;\t// @[Xbar.scala:352:24, :355:40]\n assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T;\t// @[Xbar.scala:216:19, :355:{40,54}]\n assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1;\t// @[Xbar.scala:352:24, :355:40]\n wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready;\t// @[Mux.scala:30:73]\n wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1 & portsDIO_filtered_1_ready;\t// @[Mux.scala:30:73]\n wire _portsDIO_out_0_d_ready_T_2 = _portsDIO_out_0_d_ready_T | _portsDIO_out_0_d_ready_T_1;\t// @[Mux.scala:30:73]\n assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_2;\t// @[Mux.scala:30:73]\n assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE;\t// @[Mux.scala:30:73]\n reg [7:0] beatsLeft;\t// @[Arbiter.scala:60:30]\n wire idle = beatsLeft == 8'h0;\t// @[Arbiter.scala:60:30, :61:28]\n wire latch = idle & out_0_a_ready;\t// @[Xbar.scala:216:19]\n wire [1:0] _readys_T = {portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid};\t// @[Xbar.scala:352:24]\n wire [1:0] readys_valid = _readys_T;\t// @[Arbiter.scala:21:23, :68:51]\n wire _readys_T_1 = readys_valid == _readys_T;\t// @[Arbiter.scala:21:23, :22:19, :68:51]\n wire _readys_T_3 = ~_readys_T_2;\t// @[Arbiter.scala:22:12]\n wire _readys_T_4 = ~_readys_T_1;\t// @[Arbiter.scala:22:{12,19}]\n reg [1:0] readys_mask;\t// @[Arbiter.scala:23:23]\n wire [1:0] _readys_filter_T = ~readys_mask;\t// @[Arbiter.scala:23:23, :24:30]\n wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T;\t// @[Arbiter.scala:21:23, :24:{28,30}]\n wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid};\t// @[Arbiter.scala:21:23, :24:{21,28}]\n wire [2:0] _readys_unready_T = readys_filter[3:1];\t// @[package.scala:262:48]\n wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] | _readys_unready_T};\t// @[package.scala:262:{43,48}]\n wire [3:0] _readys_unready_T_2 = _readys_unready_T_1;\t// @[package.scala:262:43, :263:17]\n wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1];\t// @[package.scala:263:17]\n wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0};\t// @[Arbiter.scala:23:23, :25:66]\n wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} | _readys_unready_T_4;\t// @[Arbiter.scala:25:{52,58,66}]\n wire [1:0] _readys_readys_T = readys_unready[3:2];\t// @[Arbiter.scala:25:58, :26:29]\n wire [1:0] _readys_readys_T_1 = readys_unready[1:0];\t// @[Arbiter.scala:25:58, :26:48]\n wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1;\t// @[Arbiter.scala:26:{29,39,48}]\n wire [1:0] readys_readys = ~_readys_readys_T_2;\t// @[Arbiter.scala:26:{18,39}]\n wire [1:0] _readys_T_7 = readys_readys;\t// @[Arbiter.scala:26:18, :30:11]\n wire _readys_T_5 = |readys_valid;\t// @[Arbiter.scala:21:23, :27:27]\n wire _readys_T_6 = latch & _readys_T_5;\t// @[Arbiter.scala:27:{18,27}, :62:24]\n wire [1:0] _readys_mask_T = readys_readys & readys_valid;\t// @[Arbiter.scala:21:23, :26:18, :28:29]\n wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0};\t// @[package.scala:253:48]\n wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0];\t// @[package.scala:253:{48,53}]\n wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2;\t// @[package.scala:253:{43,53}]\n wire [1:0] _readys_mask_T_4 = _readys_mask_T_3;\t// @[package.scala:253:43, :254:17]\n wire _readys_T_8 = _readys_T_7[0];\t// @[Arbiter.scala:30:11, :68:76]\n wire readys_0 = _readys_T_8;\t// @[Arbiter.scala:68:{27,76}]\n wire _readys_T_9 = _readys_T_7[1];\t// @[Arbiter.scala:30:11, :68:76]\n wire readys_1 = _readys_T_9;\t// @[Arbiter.scala:68:{27,76}]\n wire _winner_T = readys_0 & portsAOI_filtered_0_valid;\t// @[Xbar.scala:352:24]\n wire winner_0 = _winner_T;\t// @[Arbiter.scala:71:{27,69}]\n wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid;\t// @[Xbar.scala:352:24]\n wire winner_1 = _winner_T_1;\t// @[Arbiter.scala:71:{27,69}]\n wire prefixOR_1 = winner_0;\t// @[Arbiter.scala:71:27, :76:48]\n wire _prefixOR_T = prefixOR_1 | winner_1;\t// @[Arbiter.scala:71:27, :76:48]\n wire _out_0_a_valid_T = portsAOI_filtered_0_valid | portsAOI_filtered_1_0_valid;\t// @[Xbar.scala:352:24]"}}},{"rowIdx":34193,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module PE_495 : \n input clock : Clock \n input reset : Reset \n output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} \n\n\n inst mac_unit of MacUnit_239 \n connect mac_unit.clock, clock\n\n connect mac_unit.reset, reset\n\n reg c1 : SInt<32>, clock \n reg c2 : SInt<32>, clock \n connect io.out_a, io.in_a \n connect io.out_control.dataflow, io.in_control.dataflow \n connect io.out_control.propagate, io.in_control.propagate \n connect io.out_control.shift, io.in_control.shift \n connect io.out_id, io.in_id \n connect io.out_last, io.in_last \n connect io.out_valid, io.in_valid \n connect mac_unit.io.in_a, io.in_a \n reg last_s : UInt<1>, clock \n when io.in_valid : \n connect last_s, io.in_control.propagate \n node flip = neq(last_s, io.in_control.propagate) \n node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) \n connect io.bad_dataflow, UInt<1>(0h0) \n node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) \n node _T_1 = and(UInt<1>(0h1), _T) \n node _T_2 = or(UInt<1>(0h0), _T_1) \n when _T_2 : \n node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) \n when _T_3 : \n node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) \n node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) \n node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) \n node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) \n node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) \n node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) \n node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) \n node _io_out_c_zeros_T_1 = asUInt(c1) \n node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) \n node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) \n node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) \n node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) \n node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) \n node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) \n node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) \n node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) \n node _io_out_c_ones_digit_T = dshr(c1, shift_offset) \n node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) \n node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) \n node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) \n node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) \n node _io_out_c_T = dshr(c1, shift_offset) \n node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) \n node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) \n node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) \n node _io_out_c_T_4 = asSInt(_io_out_c_T_3) \n node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) \n node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) \n node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) \n node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) \n node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) \n node _io_out_c_T_10 = asSInt(_io_out_c_T_9) \n connect io.out_c, _io_out_c_T_10 \n connect io.out_b, io.in_b \n wire _mac_unit_io_in_b_WIRE : SInt<8> \n node _mac_unit_io_in_b_T = asUInt(io.in_b) \n node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) \n connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 \n connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE \n connect mac_unit.io.in_c, c2 \n connect c2, mac_unit.io.out_d \n node c1_sign = bits(io.in_d, 19, 19) \n node c1_lo_lo_hi = cat(c1_sign, c1_sign) \n node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) \n node c1_lo_hi_hi = cat(c1_sign, c1_sign) \n node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) \n node c1_lo = cat(c1_lo_hi, c1_lo_lo) \n node c1_hi_lo_hi = cat(c1_sign, c1_sign) \n node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) \n node c1_hi_hi_hi = cat(c1_sign, c1_sign) \n node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) \n node c1_hi = cat(c1_hi_hi, c1_hi_lo) \n node _c1_T = cat(c1_hi, c1_lo) \n node c1_lo_1 = asUInt(io.in_d) \n node _c1_T_1 = cat(_c1_T, c1_lo_1) \n wire _c1_WIRE : SInt<32> \n node _c1_T_2 = asSInt(_c1_T_1) \n connect _c1_WIRE, _c1_T_2 \n connect c1, _c1_WIRE \n else :\n\n node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) \n node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) \n node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) \n node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) \n node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) \n node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) \n node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) \n node _io_out_c_zeros_T_10 = asUInt(c2) \n node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) \n node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) \n node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) \n node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) \n node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) \n node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) \n node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) \n node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) \n node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) \n node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) \n node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) \n node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) \n node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) \n node _io_out_c_T_11 = dshr(c2, shift_offset) \n node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) \n node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) \n node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) \n node _io_out_c_T_15 = asSInt(_io_out_c_T_14) \n node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) \n node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) \n node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) \n node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) \n node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) \n node _io_out_c_T_21 = asSInt(_io_out_c_T_20) \n connect io.out_c, _io_out_c_T_21 \n connect io.out_b, io.in_b \n wire _mac_unit_io_in_b_WIRE_1 : SInt<8> \n node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) \n node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) \n connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 \n connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 \n connect mac_unit.io.in_c, c1 \n connect c1, mac_unit.io.out_d \n node c2_sign = bits(io.in_d, 19, 19) \n node c2_lo_lo_hi = cat(c2_sign, c2_sign) \n node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) \n node c2_lo_hi_hi = cat(c2_sign, c2_sign) \n node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) \n node c2_lo = cat(c2_lo_hi, c2_lo_lo) \n node c2_hi_lo_hi = cat(c2_sign, c2_sign) \n node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) \n node c2_hi_hi_hi = cat(c2_sign, c2_sign) \n node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) \n node c2_hi = cat(c2_hi_hi, c2_hi_lo) \n node _c2_T = cat(c2_hi, c2_lo) \n node c2_lo_1 = asUInt(io.in_d) \n node _c2_T_1 = cat(_c2_T, c2_lo_1) \n wire _c2_WIRE : SInt<32> \n node _c2_T_2 = asSInt(_c2_T_1) \n connect _c2_WIRE, _c2_T_2 \n connect c2, _c2_WIRE \n else :\n\n node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) \n node _T_5 = and(UInt<1>(0h1), _T_4) \n node _T_6 = or(UInt<1>(0h0), _T_5) \n when _T_6 : \n node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) \n when _T_7 : \n connect io.out_c, c1 \n wire _mac_unit_io_in_b_WIRE_2 : SInt<8> \n node _mac_unit_io_in_b_T_4 = asUInt(c2) \n node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) \n connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 \n connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 \n connect mac_unit.io.in_c, io.in_b \n connect io.out_b, mac_unit.io.out_d \n connect c1, io.in_d \n else :\n\n connect io.out_c, c2 \n wire _mac_unit_io_in_b_WIRE_3 : SInt<8> \n node _mac_unit_io_in_b_T_6 = asUInt(c1) \n node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) \n connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 \n connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 \n connect mac_unit.io.in_c, io.in_b \n connect io.out_b, mac_unit.io.out_d \n connect c2, io.in_d \n else :\n\n connect io.bad_dataflow, UInt<1>(0h1) \n invalidate io.out_c \n invalidate io.out_b \n wire _mac_unit_io_in_b_WIRE_4 : SInt<8> \n node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) \n node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) \n connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 \n connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 \n connect mac_unit.io.in_c, c2 \n node _T_8 = eq(io.in_valid, UInt<1>(0h0)) \n when _T_8 : \n connect c1, c1 \n connect c2, c2 \n invalidate mac_unit.io.in_b \n invalidate mac_unit.io.in_c"},"response":{"kind":"string","value":"module PE_495(\t// @[PE.scala:31:7]\n input clock,\t// @[PE.scala:31:7]\n input reset,\t// @[PE.scala:31:7]\n input [7:0] io_in_a,\t// @[PE.scala:35:14]\n input [19:0] io_in_b,\t// @[PE.scala:35:14]\n input [19:0] io_in_d,\t// @[PE.scala:35:14]\n output [7:0] io_out_a,\t// @[PE.scala:35:14]\n output [19:0] io_out_b,\t// @[PE.scala:35:14]\n output [19:0] io_out_c,\t// @[PE.scala:35:14]\n input io_in_control_dataflow,\t// @[PE.scala:35:14]\n input io_in_control_propagate,\t// @[PE.scala:35:14]\n input [4:0] io_in_control_shift,\t// @[PE.scala:35:14]\n output io_out_control_dataflow,\t// @[PE.scala:35:14]\n output io_out_control_propagate,\t// @[PE.scala:35:14]\n output [4:0] io_out_control_shift,\t// @[PE.scala:35:14]\n input [2:0] io_in_id,\t// @[PE.scala:35:14]\n output [2:0] io_out_id,\t// @[PE.scala:35:14]\n input io_in_last,\t// @[PE.scala:35:14]\n output io_out_last,\t// @[PE.scala:35:14]\n input io_in_valid,\t// @[PE.scala:35:14]\n output io_out_valid,\t// @[PE.scala:35:14]\n output io_bad_dataflow\t// @[PE.scala:35:14]\n);\n\n wire [19:0] _mac_unit_io_out_d;\t// @[PE.scala:64:24]\n wire [7:0] io_in_a_0 = io_in_a;\t// @[PE.scala:31:7]\n wire [19:0] io_in_b_0 = io_in_b;\t// @[PE.scala:31:7]\n wire [19:0] io_in_d_0 = io_in_d;\t// @[PE.scala:31:7]\n wire io_in_control_dataflow_0 = io_in_control_dataflow;\t// @[PE.scala:31:7]\n wire io_in_control_propagate_0 = io_in_control_propagate;\t// @[PE.scala:31:7]\n wire [4:0] io_in_control_shift_0 = io_in_control_shift;\t// @[PE.scala:31:7]\n wire [2:0] io_in_id_0 = io_in_id;\t// @[PE.scala:31:7]\n wire io_in_last_0 = io_in_last;\t// @[PE.scala:31:7]\n wire io_in_valid_0 = io_in_valid;\t// @[PE.scala:31:7]\n wire io_bad_dataflow_0 = 1'h0;\t// @[PE.scala:31:7]\n wire [7:0] io_out_a_0 = io_in_a_0;\t// @[PE.scala:31:7]\n wire [19:0] _mac_unit_io_in_b_T = io_in_b_0;\t// @[PE.scala:31:7, :106:37]\n wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0;\t// @[PE.scala:31:7, :113:37]\n wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0;\t// @[PE.scala:31:7, :137:35]\n wire [19:0] c1_lo_1 = io_in_d_0;\t// @[PE.scala:31:7]\n wire [19:0] c2_lo_1 = io_in_d_0;\t// @[PE.scala:31:7]\n wire io_out_control_dataflow_0 = io_in_control_dataflow_0;\t// @[PE.scala:31:7]\n wire io_out_control_propagate_0 = io_in_control_propagate_0;\t// @[PE.scala:31:7]\n wire [4:0] io_out_control_shift_0 = io_in_control_shift_0;\t// @[PE.scala:31:7]\n wire [2:0] io_out_id_0 = io_in_id_0;\t// @[PE.scala:31:7]\n wire io_out_last_0 = io_in_last_0;\t// @[PE.scala:31:7]\n wire io_out_valid_0 = io_in_valid_0;\t// @[PE.scala:31:7]\n wire [19:0] io_out_b_0;\t// @[PE.scala:31:7]\n wire [19:0] io_out_c_0;\t// @[PE.scala:31:7]\n reg [31:0] c1;\t// @[PE.scala:70:15]\n wire [31:0] _io_out_c_zeros_T_1 = c1;\t// @[PE.scala:70:15]\n wire [31:0] _mac_unit_io_in_b_T_6 = c1;\t// @[PE.scala:70:15, :127:38]\n reg [31:0] c2;\t// @[PE.scala:71:15]\n wire [31:0] _io_out_c_zeros_T_10 = c2;\t// @[PE.scala:71:15]\n wire [31:0] _mac_unit_io_in_b_T_4 = c2;\t// @[PE.scala:71:15, :121:38]\n reg last_s;\t// @[PE.scala:89:25]\n wire flip = last_s != io_in_control_propagate_0;\t// @[PE.scala:31:7, :89:25, :90:21]\n wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0;\t// @[PE.scala:31:7, :90:21, :91:25]\n wire _GEN = shift_offset == 5'h0;\t// @[PE.scala:91:25]\n wire _io_out_c_point_five_T;\t// @[Arithmetic.scala:101:32]\n assign _io_out_c_point_five_T = _GEN;\t// @[Arithmetic.scala:101:32]\n wire _io_out_c_point_five_T_5;\t// @[Arithmetic.scala:101:32]\n assign _io_out_c_point_five_T_5 = _GEN;\t// @[Arithmetic.scala:101:32]\n wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1;\t// @[PE.scala:91:25]\n wire [5:0] _io_out_c_point_five_T_1;\t// @[Arithmetic.scala:101:53]\n assign _io_out_c_point_five_T_1 = _GEN_0;\t// @[Arithmetic.scala:101:53]\n wire [5:0] _io_out_c_zeros_T_2;\t// @[Arithmetic.scala:102:66]\n assign _io_out_c_zeros_T_2 = _GEN_0;\t// @[Arithmetic.scala:101:53, :102:66]\n wire [5:0] _io_out_c_point_five_T_6;\t// @[Arithmetic.scala:101:53]\n assign _io_out_c_point_five_T_6 = _GEN_0;\t// @[Arithmetic.scala:101:53]\n wire [5:0] _io_out_c_zeros_T_11;\t// @[Arithmetic.scala:102:66]\n assign _io_out_c_zeros_T_11 = _GEN_0;\t// @[Arithmetic.scala:101:53, :102:66]\n wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0];\t// @[Arithmetic.scala:101:53]\n wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2);\t// @[PE.scala:70:15]\n wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0];\t// @[Arithmetic.scala:101:50]\n wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4;\t// @[Arithmetic.scala:101:{29,32,50}]\n wire _GEN_1 = shift_offset < 5'h2;\t// @[PE.scala:91:25]\n wire _io_out_c_zeros_T;\t// @[Arithmetic.scala:102:27]\n assign _io_out_c_zeros_T = _GEN_1;\t// @[Arithmetic.scala:102:27]\n wire _io_out_c_zeros_T_9;\t// @[Arithmetic.scala:102:27]\n assign _io_out_c_zeros_T_9 = _GEN_1;\t// @[Arithmetic.scala:102:27]\n wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0];\t// @[Arithmetic.scala:102:66]\n wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3;\t// @[Arithmetic.scala:102:{60,66}]\n wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1;\t// @[Arithmetic.scala:102:{60,81}]\n wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0];\t// @[Arithmetic.scala:102:81]\n wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6;\t// @[Arithmetic.scala:102:{45,52,81}]\n wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7;\t// @[Arithmetic.scala:102:{24,27,52}]\n wire io_out_c_zeros = |_io_out_c_zeros_T_8;\t// @[Arithmetic.scala:102:{24,89}]\n wire [31:0] _GEN_2 = {27'h0, shift_offset};\t// @[PE.scala:91:25]\n wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2);\t// @[PE.scala:70:15]\n wire [31:0] _io_out_c_ones_digit_T;\t// @[Arithmetic.scala:103:30]\n assign _io_out_c_ones_digit_T = _GEN_3;\t// @[Arithmetic.scala:103:30]\n wire [31:0] _io_out_c_T;\t// @[Arithmetic.scala:107:15]\n assign _io_out_c_T = _GEN_3;\t// @[Arithmetic.scala:103:30, :107:15]\n wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0];\t// @[Arithmetic.scala:103:30]\n wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit;\t// @[Arithmetic.scala:102:89, :103:30, :105:38]\n wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T;\t// @[Arithmetic.scala:101:29, :105:{29,38}]\n wire io_out_c_r = _io_out_c_r_T_1;\t// @[Arithmetic.scala:105:{29,53}]\n wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r};\t// @[Arithmetic.scala:105:53, :107:33]\n wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1};\t// @[Arithmetic.scala:107:{15,28,33}]\n wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0];\t// @[Arithmetic.scala:107:28]\n wire [31:0] _io_out_c_T_4 = _io_out_c_T_3;\t// @[Arithmetic.scala:107:28]\n wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF;\t// @[Arithmetic.scala:107:28, :125:33]\n wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000;\t// @[Arithmetic.scala:107:28, :125:60]\n wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4;\t// @[Mux.scala:126:16]\n wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7;\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0];\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_10 = _io_out_c_T_9;\t// @[Arithmetic.scala:125:{81,99}]\n wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T;\t// @[PE.scala:106:37]\n wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0];\t// @[PE.scala:106:37]\n wire c1_sign = io_in_d_0[19];\t// @[PE.scala:31:7]\n wire c2_sign = io_in_d_0[19];\t// @[PE.scala:31:7]\n wire [1:0] _GEN_4 = {2{c1_sign}};\t// @[Arithmetic.scala:117:26, :118:18]\n wire [1:0] c1_lo_lo_hi;\t// @[Arithmetic.scala:118:18]\n assign c1_lo_lo_hi = _GEN_4;\t// @[Arithmetic.scala:118:18]\n wire [1:0] c1_lo_hi_hi;\t// @[Arithmetic.scala:118:18]\n assign c1_lo_hi_hi = _GEN_4;\t// @[Arithmetic.scala:118:18]\n wire [1:0] c1_hi_lo_hi;\t// @[Arithmetic.scala:118:18]\n assign c1_hi_lo_hi = _GEN_4;\t// @[Arithmetic.scala:118:18]\n wire [1:0] c1_hi_hi_hi;\t// @[Arithmetic.scala:118:18]\n assign c1_hi_hi_hi = _GEN_4;\t// @[Arithmetic.scala:118:18]\n wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign};\t// @[Arithmetic.scala:117:26, :118:18]\n wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign};\t// @[Arithmetic.scala:117:26, :118:18]\n wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo};\t// @[Arithmetic.scala:118:18]\n wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign};\t// @[Arithmetic.scala:117:26, :118:18]\n wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign};\t// @[Arithmetic.scala:117:26, :118:18]\n wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo};\t// @[Arithmetic.scala:118:18]\n wire [11:0] _c1_T = {c1_hi, c1_lo};\t// @[Arithmetic.scala:118:18]\n wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1};\t// @[Arithmetic.scala:118:{14,18}]\n wire [31:0] _c1_T_2 = _c1_T_1;\t// @[Arithmetic.scala:118:{14,61}]\n wire [31:0] _c1_WIRE = _c1_T_2;\t// @[Arithmetic.scala:118:61]\n wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0];\t// @[Arithmetic.scala:101:53]\n wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7);\t// @[PE.scala:71:15]\n wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0];\t// @[Arithmetic.scala:101:50]\n wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9;\t// @[Arithmetic.scala:101:{29,32,50}]\n wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0];\t// @[Arithmetic.scala:102:66]\n wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12;\t// @[Arithmetic.scala:102:{60,66}]\n wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1;\t// @[Arithmetic.scala:102:{60,81}]\n wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0];\t// @[Arithmetic.scala:102:81]\n wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15;\t// @[Arithmetic.scala:102:{45,52,81}]\n wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16;\t// @[Arithmetic.scala:102:{24,27,52}]\n wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17;\t// @[Arithmetic.scala:102:{24,89}]\n wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2);\t// @[PE.scala:71:15]\n wire [31:0] _io_out_c_ones_digit_T_1;\t// @[Arithmetic.scala:103:30]\n assign _io_out_c_ones_digit_T_1 = _GEN_5;\t// @[Arithmetic.scala:103:30]\n wire [31:0] _io_out_c_T_11;\t// @[Arithmetic.scala:107:15]\n assign _io_out_c_T_11 = _GEN_5;\t// @[Arithmetic.scala:103:30, :107:15]\n wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0];\t// @[Arithmetic.scala:103:30]\n wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1;\t// @[Arithmetic.scala:102:89, :103:30, :105:38]\n wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2;\t// @[Arithmetic.scala:101:29, :105:{29,38}]\n wire io_out_c_r_1 = _io_out_c_r_T_3;\t// @[Arithmetic.scala:105:{29,53}]\n wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1};\t// @[Arithmetic.scala:105:53, :107:33]\n wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12};\t// @[Arithmetic.scala:107:{15,28,33}]\n wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0];\t// @[Arithmetic.scala:107:28]\n wire [31:0] _io_out_c_T_15 = _io_out_c_T_14;\t// @[Arithmetic.scala:107:28]\n wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF;\t// @[Arithmetic.scala:107:28, :125:33]\n wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000;\t// @[Arithmetic.scala:107:28, :125:60]\n wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15;\t// @[Mux.scala:126:16]\n wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18;\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0];\t// @[Mux.scala:126:16]\n wire [19:0] _io_out_c_T_21 = _io_out_c_T_20;\t// @[Arithmetic.scala:125:{81,99}]\n wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2;\t// @[PE.scala:113:37]\n wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0];\t// @[PE.scala:113:37]\n wire [1:0] _GEN_6 = {2{c2_sign}};\t// @[Arithmetic.scala:117:26, :118:18]\n wire [1:0] c2_lo_lo_hi;\t// @[Arithmetic.scala:118:18]\n assign c2_lo_lo_hi = _GEN_6;\t// @[Arithmetic.scala:118:18]\n wire [1:0] c2_lo_hi_hi;\t// @[Arithmetic.scala:118:18]\n assign c2_lo_hi_hi = _GEN_6;\t// @[Arithmetic.scala:118:18]\n wire [1:0] c2_hi_lo_hi;\t// @[Arithmetic.scala:118:18]\n assign c2_hi_lo_hi = _GEN_6;\t// @[Arithmetic.scala:118:18]\n wire [1:0] c2_hi_hi_hi;\t// @[Arithmetic.scala:118:18]\n assign c2_hi_hi_hi = _GEN_6;\t// @[Arithmetic.scala:118:18]\n wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign};\t// @[Arithmetic.scala:117:26, :118:18]\n wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign};\t// @[Arithmetic.scala:117:26, :118:18]\n wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo};\t// @[Arithmetic.scala:118:18]\n wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign};\t// @[Arithmetic.scala:117:26, :118:18]\n wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign};\t// @[Arithmetic.scala:117:26, :118:18]\n wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo};\t// @[Arithmetic.scala:118:18]\n wire [11:0] _c2_T = {c2_hi, c2_lo};\t// @[Arithmetic.scala:118:18]\n wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1};\t// @[Arithmetic.scala:118:{14,18}]\n wire [31:0] _c2_T_2 = _c2_T_1;\t// @[Arithmetic.scala:118:{14,61}]\n wire [31:0] _c2_WIRE = _c2_T_2;\t// @[Arithmetic.scala:118:61]\n wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4;\t// @[PE.scala:121:38]\n wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0];\t// @[PE.scala:121:38]\n wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6;\t// @[PE.scala:127:38]\n wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0];\t// @[PE.scala:127:38]\n assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21;\t// @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]\n assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0;\t// @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]\n wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8;\t// @[PE.scala:137:35]\n wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0];\t// @[PE.scala:137:35]\n wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0};\t// @[PE.scala:31:7, :124:10]\n wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d};\t// @[PE.scala:64:24, :108:10]\n always @(posedge clock) begin\t// @[PE.scala:31:7]\n if (io_in_valid_0) begin\t// @[PE.scala:31:7]\n if (io_in_control_dataflow_0) begin\t// @[PE.scala:31:7]\n if (io_in_control_dataflow_0 & io_in_control_propagate_0)\t// @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]\n c1 <= _GEN_7;\t// @[PE.scala:70:15, :124:10]\n if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin\t// @[PE.scala:31:7, :71:15, :118:101, :119:30]\n end\n else\t// @[PE.scala:71:15, :118:101, :119:30]\n c2 <= _GEN_7;\t// @[PE.scala:71:15, :124:10]\n end\n else begin\t// @[PE.scala:31:7]\n c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8;\t// @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]\n c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE;\t// @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]\n end\n last_s <= io_in_control_propagate_0;\t// @[PE.scala:31:7, :89:25]\n end\n always @(posedge)\n MacUnit_239 mac_unit (\t// @[PE.scala:64:24]\n .clock (clock),\n .reset (reset),\n .io_in_a (io_in_a_0),\t// @[PE.scala:31:7]\n .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1),\t// @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]\n .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1),\t// @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]\n .io_out_d (_mac_unit_io_out_d)\n );\t// @[PE.scala:64:24]\n assign io_out_a = io_out_a_0;\t// @[PE.scala:31:7]\n assign io_out_b = io_out_b_0;\t// @[PE.scala:31:7]\n assign io_out_c = io_out_c_0;\t// @[PE.scala:31:7]\n assign io_out_control_dataflow = io_out_control_dataflow_0;\t// @[PE.scala:31:7]\n assign io_out_control_propagate = io_out_control_propagate_0;\t// @[PE.scala:31:7]\n assign io_out_control_shift = io_out_control_shift_0;\t// @[PE.scala:31:7]\n assign io_out_id = io_out_id_0;\t// @[PE.scala:31:7]\n assign io_out_last = io_out_last_0;\t// @[PE.scala:31:7]\n assign io_out_valid = io_out_valid_0;\t// @[PE.scala:31:7]\n assign io_bad_dataflow = io_bad_dataflow_0;\t// @[PE.scala:31:7]\nendmodule"}}},{"rowIdx":34194,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module TLCToNoC : \n input clock : Clock \n input reset : Reset \n output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<65>, egress_id : UInt}}} \n\n\n inst q of Queue1_TLBundleC_a32d64s6k5z4c \n connect q.clock, clock\n\n connect q.reset, reset\n\n wire has_body : UInt<1> \n node _head_T = and(q.io.deq.ready, q.io.deq.valid) \n node _head_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size) \n node _head_beats1_decode_T_1 = bits(_head_beats1_decode_T, 11, 0) \n node _head_beats1_decode_T_2 = not(_head_beats1_decode_T_1) \n node head_beats1_decode = shr(_head_beats1_decode_T_2, 3) \n node head_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) \n node head_beats1 = mux(UInt<1>(0h0), head_beats1_decode, UInt<1>(0h0)) \n regreset head_counter : UInt<9>, clock, reset, UInt<9>(0h0) \n node _head_counter1_T = sub(head_counter, UInt<1>(0h1)) \n node head_counter1 = tail(_head_counter1_T, 1) \n node head = eq(head_counter, UInt<1>(0h0)) \n node _head_last_T = eq(head_counter, UInt<1>(0h1)) \n node _head_last_T_1 = eq(head_beats1, UInt<1>(0h0)) \n node head_last = or(_head_last_T, _head_last_T_1) \n node head_done = and(head_last, _head_T) \n node _head_count_T = not(head_counter1) \n node head_count = and(head_beats1, _head_count_T) \n when _head_T : \n node _head_counter_T = mux(head, head_beats1, head_counter1) \n connect head_counter, _head_counter_T \n node _tail_T = and(q.io.deq.ready, q.io.deq.valid) \n node _tail_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size) \n node _tail_beats1_decode_T_1 = bits(_tail_beats1_decode_T, 11, 0) \n node _tail_beats1_decode_T_2 = not(_tail_beats1_decode_T_1) \n node tail_beats1_decode = shr(_tail_beats1_decode_T_2, 3) \n node tail_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0) \n node tail_beats1 = mux(UInt<1>(0h0), tail_beats1_decode, UInt<1>(0h0)) \n regreset tail_counter : UInt<9>, clock, reset, UInt<9>(0h0) \n node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1)) \n node tail_counter1 = tail(_tail_counter1_T, 1) \n node tail_first = eq(tail_counter, UInt<1>(0h0)) \n node _tail_last_T = eq(tail_counter, UInt<1>(0h1)) \n node _tail_last_T_1 = eq(tail_beats1, UInt<1>(0h0)) \n node tail = or(_tail_last_T, _tail_last_T_1) \n node tail_done = and(tail, _tail_T) \n node _tail_count_T = not(tail_counter1) \n node tail_count = and(tail_beats1, _tail_count_T) \n when _tail_T : \n node _tail_counter_T = mux(tail_first, tail_beats1, tail_counter1) \n connect tail_counter, _tail_counter_T \n node body = cat(q.io.deq.bits.data, q.io.deq.bits.corrupt) \n node const_lo = cat(q.io.deq.bits.source, q.io.deq.bits.address) \n node const_hi_hi = cat(q.io.deq.bits.opcode, q.io.deq.bits.param) \n node const_hi = cat(const_hi_hi, q.io.deq.bits.size) \n node const = cat(const_hi, const_lo) \n regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0) \n connect io.flit.valid, q.io.deq.valid \n node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0)) \n node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T) \n node _q_io_deq_ready_T_2 = and(io.flit.ready, _q_io_deq_ready_T_1) \n connect q.io.deq.ready, _q_io_deq_ready_T_2 \n node _io_flit_bits_head_T = eq(is_body, UInt<1>(0h0)) \n node _io_flit_bits_head_T_1 = and(head, _io_flit_bits_head_T) \n connect io.flit.bits.head, _io_flit_bits_head_T_1 \n node _io_flit_bits_tail_T = eq(has_body, UInt<1>(0h0)) \n node _io_flit_bits_tail_T_1 = or(is_body, _io_flit_bits_tail_T) \n node _io_flit_bits_tail_T_2 = and(tail, _io_flit_bits_tail_T_1) \n connect io.flit.bits.tail, _io_flit_bits_tail_T_2 \n node _io_flit_bits_egress_id_requestOH_T = xor(q.io.deq.bits.address, UInt<1>(0h0)) \n node _io_flit_bits_egress_id_requestOH_T_1 = cvt(_io_flit_bits_egress_id_requestOH_T) \n node _io_flit_bits_egress_id_requestOH_T_2 = and(_io_flit_bits_egress_id_requestOH_T_1, asSInt(UInt<1>(0h0))) \n node _io_flit_bits_egress_id_requestOH_T_3 = asSInt(_io_flit_bits_egress_id_requestOH_T_2) \n node _io_flit_bits_egress_id_requestOH_T_4 = eq(_io_flit_bits_egress_id_requestOH_T_3, asSInt(UInt<1>(0h0))) \n node _io_flit_bits_egress_id_requestOH_T_5 = or(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_4) \n node io_flit_bits_egress_id_requestOH_0 = and(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_5) \n node _io_flit_bits_egress_id_requestOH_T_6 = xor(q.io.deq.bits.address, UInt<1>(0h0)) \n node _io_flit_bits_egress_id_requestOH_T_7 = cvt(_io_flit_bits_egress_id_requestOH_T_6) \n node _io_flit_bits_egress_id_requestOH_T_8 = and(_io_flit_bits_egress_id_requestOH_T_7, asSInt(UInt<1>(0h0))) \n node _io_flit_bits_egress_id_requestOH_T_9 = asSInt(_io_flit_bits_egress_id_requestOH_T_8) \n node _io_flit_bits_egress_id_requestOH_T_10 = eq(_io_flit_bits_egress_id_requestOH_T_9, asSInt(UInt<1>(0h0))) \n node _io_flit_bits_egress_id_requestOH_T_11 = or(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_10) \n node io_flit_bits_egress_id_requestOH_1 = and(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_11) \n node _io_flit_bits_egress_id_requestOH_T_12 = xor(q.io.deq.bits.address, UInt<1>(0h0)) \n node _io_flit_bits_egress_id_requestOH_T_13 = cvt(_io_flit_bits_egress_id_requestOH_T_12) \n node _io_flit_bits_egress_id_requestOH_T_14 = and(_io_flit_bits_egress_id_requestOH_T_13, asSInt(UInt<1>(0h0))) \n node _io_flit_bits_egress_id_requestOH_T_15 = asSInt(_io_flit_bits_egress_id_requestOH_T_14) \n node _io_flit_bits_egress_id_requestOH_T_16 = eq(_io_flit_bits_egress_id_requestOH_T_15, asSInt(UInt<1>(0h0))) \n node _io_flit_bits_egress_id_requestOH_T_17 = or(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_16) \n node io_flit_bits_egress_id_requestOH_2 = and(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_17) \n node _io_flit_bits_egress_id_requestOH_T_18 = xor(q.io.deq.bits.address, UInt<1>(0h0)) \n node _io_flit_bits_egress_id_requestOH_T_19 = cvt(_io_flit_bits_egress_id_requestOH_T_18) \n node _io_flit_bits_egress_id_requestOH_T_20 = and(_io_flit_bits_egress_id_requestOH_T_19, asSInt(UInt<1>(0h0))) \n node _io_flit_bits_egress_id_requestOH_T_21 = asSInt(_io_flit_bits_egress_id_requestOH_T_20) \n node _io_flit_bits_egress_id_requestOH_T_22 = eq(_io_flit_bits_egress_id_requestOH_T_21, asSInt(UInt<1>(0h0))) \n node _io_flit_bits_egress_id_requestOH_T_23 = or(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_22) \n node io_flit_bits_egress_id_requestOH_3 = and(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_23) \n node _io_flit_bits_egress_id_requestOH_T_24 = xor(q.io.deq.bits.address, UInt<1>(0h0)) \n node _io_flit_bits_egress_id_requestOH_T_25 = cvt(_io_flit_bits_egress_id_requestOH_T_24) \n node _io_flit_bits_egress_id_requestOH_T_26 = and(_io_flit_bits_egress_id_requestOH_T_25, asSInt(UInt<1>(0h0))) \n node _io_flit_bits_egress_id_requestOH_T_27 = asSInt(_io_flit_bits_egress_id_requestOH_T_26) \n node _io_flit_bits_egress_id_requestOH_T_28 = eq(_io_flit_bits_egress_id_requestOH_T_27, asSInt(UInt<1>(0h0))) \n node _io_flit_bits_egress_id_requestOH_T_29 = or(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_28) \n node io_flit_bits_egress_id_requestOH_4 = and(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_29) \n node _io_flit_bits_egress_id_T = mux(io_flit_bits_egress_id_requestOH_0, UInt<4>(0hb), UInt<1>(0h0)) \n node _io_flit_bits_egress_id_T_1 = mux(io_flit_bits_egress_id_requestOH_1, UInt<4>(0he), UInt<1>(0h0)) \n node _io_flit_bits_egress_id_T_2 = mux(io_flit_bits_egress_id_requestOH_2, UInt<5>(0h11), UInt<1>(0h0)) \n node _io_flit_bits_egress_id_T_3 = mux(io_flit_bits_egress_id_requestOH_3, UInt<5>(0h14), UInt<1>(0h0)) \n node _io_flit_bits_egress_id_T_4 = mux(io_flit_bits_egress_id_requestOH_4, UInt<5>(0h17), UInt<1>(0h0)) \n node _io_flit_bits_egress_id_T_5 = or(_io_flit_bits_egress_id_T, _io_flit_bits_egress_id_T_1) \n node _io_flit_bits_egress_id_T_6 = or(_io_flit_bits_egress_id_T_5, _io_flit_bits_egress_id_T_2) \n node _io_flit_bits_egress_id_T_7 = or(_io_flit_bits_egress_id_T_6, _io_flit_bits_egress_id_T_3) \n node _io_flit_bits_egress_id_T_8 = or(_io_flit_bits_egress_id_T_7, _io_flit_bits_egress_id_T_4) \n wire _io_flit_bits_egress_id_WIRE : UInt<5> \n connect _io_flit_bits_egress_id_WIRE, _io_flit_bits_egress_id_T_8 \n connect io.flit.bits.egress_id, _io_flit_bits_egress_id_WIRE \n node _io_flit_bits_payload_T = mux(is_body, body, const) \n connect io.flit.bits.payload, _io_flit_bits_payload_T \n node _T = and(io.flit.ready, io.flit.valid) \n node _T_1 = and(_T, io.flit.bits.head) \n when _T_1 : \n connect is_body, UInt<1>(0h1) \n node _T_2 = and(io.flit.ready, io.flit.valid) \n node _T_3 = and(_T_2, io.flit.bits.tail) \n when _T_3 : \n connect is_body, UInt<1>(0h0) \n node has_body_opdata = bits(q.io.deq.bits.opcode, 0, 0) \n connect has_body, UInt<1>(0h0) \n connect q.io.enq, io.protocol \n node _q_io_enq_bits_source_T = or(io.protocol.bits.source, UInt<1>(0h0)) \n connect q.io.enq.bits.source, _q_io_enq_bits_source_T"},"response":{"kind":"string","value":"module TLCToNoC(\t// @[TilelinkAdapters.scala:151:7]\n input clock,\t// @[TilelinkAdapters.scala:151:7]\n input reset,\t// @[TilelinkAdapters.scala:151:7]\n output io_flit_valid\t// @[TilelinkAdapters.scala:19:14]\n);\n\n Queue1_TLBundleC_a32d64s6k5z4c q (\t// @[TilelinkAdapters.scala:26:17]\n .clock (clock),\n .reset (reset),\n .io_enq_ready (/* unused */),\n .io_enq_valid (1'h0),\t// @[Decoupled.scala:51:35]\n .io_enq_bits_opcode (3'h0),\t// @[TilelinkAdapters.scala:19:14, :26:17]\n .io_enq_bits_param (3'h0),\t// @[TilelinkAdapters.scala:19:14, :26:17]\n .io_enq_bits_size (4'h0),\t// @[TilelinkAdapters.scala:19:14, :26:17]\n .io_enq_bits_source (6'h0),\t// @[TilelinkAdapters.scala:19:14, :26:17]\n .io_enq_bits_address (32'h0),\t// @[TilelinkAdapters.scala:19:14, :26:17]\n .io_enq_bits_data (64'h0),\t// @[TilelinkAdapters.scala:19:14, :26:17]\n .io_enq_bits_corrupt (1'h0),\t// @[Decoupled.scala:51:35]\n .io_deq_ready (1'h0),\t// @[Decoupled.scala:51:35]\n .io_deq_valid (io_flit_valid),\n .io_deq_bits_opcode (/* unused */),\n .io_deq_bits_param (/* unused */),\n .io_deq_bits_size (/* unused */),\n .io_deq_bits_source (/* unused */),\n .io_deq_bits_address (/* unused */),\n .io_deq_bits_data (/* unused */),\n .io_deq_bits_corrupt (/* unused */)\n );\t// @[TilelinkAdapters.scala:26:17]\nendmodule"}}},{"rowIdx":34195,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_364 : \n input clock : Clock \n input reset : AsyncReset \n output io : { flip d : UInt<1>, q : UInt<1>} \n\n\n regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) \n regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) \n regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) \n node _sync_2_T = bits(io.d, 0, 0) \n connect sync_2, _sync_2_T \n connect sync_0, sync_1 \n connect sync_1, sync_2 \n connect io.q, sync_0"},"response":{"kind":"string","value":"module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_364(\t// @[SynchronizerReg.scala:68:19]\n input clock,\t// @[SynchronizerReg.scala:68:19]\n input reset,\t// @[SynchronizerReg.scala:68:19]\n input io_d,\t// @[ShiftReg.scala:36:14]\n output io_q\t// @[ShiftReg.scala:36:14]\n);\n\n wire io_d_0 = io_d;\t// @[SynchronizerReg.scala:68:19]\n wire _sync_2_T = io_d_0;\t// @[SynchronizerReg.scala:54:22, :68:19]\n wire io_q_0;\t// @[SynchronizerReg.scala:68:19]\n reg sync_0;\t// @[SynchronizerReg.scala:51:87]\n assign io_q_0 = sync_0;\t// @[SynchronizerReg.scala:51:87, :68:19]\n reg sync_1;\t// @[SynchronizerReg.scala:51:87]\n reg sync_2;\t// @[SynchronizerReg.scala:51:87]\n always @(posedge clock or posedge reset) begin\t// @[SynchronizerReg.scala:68:19]\n if (reset) begin\t// @[SynchronizerReg.scala:68:19]\n sync_0 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n sync_1 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n sync_2 <= 1'h0;\t// @[SynchronizerReg.scala:51:87]\n end\n else begin\t// @[SynchronizerReg.scala:68:19]\n sync_0 <= sync_1;\t// @[SynchronizerReg.scala:51:87]\n sync_1 <= sync_2;\t// @[SynchronizerReg.scala:51:87]\n sync_2 <= _sync_2_T;\t// @[SynchronizerReg.scala:51:87, :54:22]\n end\n always @(posedge, posedge)"}}},{"rowIdx":34196,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_294 : \n input clock : Clock \n input reset : Reset \n output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} \n\n\n connect io.y, io.x"},"response":{"kind":"string","value":"module OptimizationBarrier_TLBEntryData_294(\t// @[package.scala:267:30]\n input clock,\t// @[package.scala:267:30]\n input reset,\t// @[package.scala:267:30]\n input [19:0] io_x_ppn,\t// @[package.scala:268:18]\n input io_x_u,\t// @[package.scala:268:18]\n input io_x_g,\t// @[package.scala:268:18]\n input io_x_ae_ptw,\t// @[package.scala:268:18]\n input io_x_ae_final,\t// @[package.scala:268:18]\n input io_x_ae_stage2,\t// @[package.scala:268:18]\n input io_x_pf,\t// @[package.scala:268:18]\n input io_x_gf,\t// @[package.scala:268:18]\n input io_x_sw,\t// @[package.scala:268:18]\n input io_x_sx,\t// @[package.scala:268:18]\n input io_x_sr,\t// @[package.scala:268:18]\n input io_x_hw,\t// @[package.scala:268:18]\n input io_x_hx,\t// @[package.scala:268:18]\n input io_x_hr,\t// @[package.scala:268:18]\n input io_x_pw,\t// @[package.scala:268:18]\n input io_x_px,\t// @[package.scala:268:18]\n input io_x_pr,\t// @[package.scala:268:18]\n input io_x_ppp,\t// @[package.scala:268:18]\n input io_x_pal,\t// @[package.scala:268:18]\n input io_x_paa,\t// @[package.scala:268:18]\n input io_x_eff,\t// @[package.scala:268:18]\n input io_x_c,\t// @[package.scala:268:18]\n input io_x_fragmented_superpage,\t// @[package.scala:268:18]\n output [19:0] io_y_ppn\t// @[package.scala:268:18]\n);\n\n wire [19:0] io_x_ppn_0 = io_x_ppn;\t// @[package.scala:267:30]\n wire io_x_u_0 = io_x_u;\t// @[package.scala:267:30]\n wire io_x_g_0 = io_x_g;\t// @[package.scala:267:30]\n wire io_x_ae_ptw_0 = io_x_ae_ptw;\t// @[package.scala:267:30]\n wire io_x_ae_final_0 = io_x_ae_final;\t// @[package.scala:267:30]\n wire io_x_ae_stage2_0 = io_x_ae_stage2;\t// @[package.scala:267:30]\n wire io_x_pf_0 = io_x_pf;\t// @[package.scala:267:30]\n wire io_x_gf_0 = io_x_gf;\t// @[package.scala:267:30]\n wire io_x_sw_0 = io_x_sw;\t// @[package.scala:267:30]\n wire io_x_sx_0 = io_x_sx;\t// @[package.scala:267:30]\n wire io_x_sr_0 = io_x_sr;\t// @[package.scala:267:30]\n wire io_x_hw_0 = io_x_hw;\t// @[package.scala:267:30]\n wire io_x_hx_0 = io_x_hx;\t// @[package.scala:267:30]\n wire io_x_hr_0 = io_x_hr;\t// @[package.scala:267:30]\n wire io_x_pw_0 = io_x_pw;\t// @[package.scala:267:30]\n wire io_x_px_0 = io_x_px;\t// @[package.scala:267:30]\n wire io_x_pr_0 = io_x_pr;\t// @[package.scala:267:30]\n wire io_x_ppp_0 = io_x_ppp;\t// @[package.scala:267:30]\n wire io_x_pal_0 = io_x_pal;\t// @[package.scala:267:30]\n wire io_x_paa_0 = io_x_paa;\t// @[package.scala:267:30]\n wire io_x_eff_0 = io_x_eff;\t// @[package.scala:267:30]\n wire io_x_c_0 = io_x_c;\t// @[package.scala:267:30]\n wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage;\t// @[package.scala:267:30]\n wire [19:0] io_y_ppn_0 = io_x_ppn_0;\t// @[package.scala:267:30]\n wire io_y_u = io_x_u_0;\t// @[package.scala:267:30]\n wire io_y_g = io_x_g_0;\t// @[package.scala:267:30]\n wire io_y_ae_ptw = io_x_ae_ptw_0;\t// @[package.scala:267:30]\n wire io_y_ae_final = io_x_ae_final_0;\t// @[package.scala:267:30]\n wire io_y_ae_stage2 = io_x_ae_stage2_0;\t// @[package.scala:267:30]\n wire io_y_pf = io_x_pf_0;\t// @[package.scala:267:30]\n wire io_y_gf = io_x_gf_0;\t// @[package.scala:267:30]\n wire io_y_sw = io_x_sw_0;\t// @[package.scala:267:30]\n wire io_y_sx = io_x_sx_0;\t// @[package.scala:267:30]\n wire io_y_sr = io_x_sr_0;\t// @[package.scala:267:30]\n wire io_y_hw = io_x_hw_0;\t// @[package.scala:267:30]\n wire io_y_hx = io_x_hx_0;\t// @[package.scala:267:30]\n wire io_y_hr = io_x_hr_0;\t// @[package.scala:267:30]\n wire io_y_pw = io_x_pw_0;\t// @[package.scala:267:30]\n wire io_y_px = io_x_px_0;\t// @[package.scala:267:30]\n wire io_y_pr = io_x_pr_0;\t// @[package.scala:267:30]\n wire io_y_ppp = io_x_ppp_0;\t// @[package.scala:267:30]\n wire io_y_pal = io_x_pal_0;\t// @[package.scala:267:30]\n wire io_y_paa = io_x_paa_0;\t// @[package.scala:267:30]\n wire io_y_eff = io_x_eff_0;\t// @[package.scala:267:30]\n wire io_y_c = io_x_c_0;\t// @[package.scala:267:30]\n wire io_y_fragmented_superpage = io_x_fragmented_superpage_0;\t// @[package.scala:267:30]\n assign io_y_ppn = io_y_ppn_0;\t// @[package.scala:267:30]\nendmodule"}}},{"rowIdx":34197,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_14 : \n output io : { flip in : UInt<1>, out : UInt<1>} \n input clock : Clock \n input reset : AsyncReset \n\n\n inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_23 \n connect io_out_source_extend.clock, clock\n\n connect io_out_source_extend.reset, reset\n\n connect io_out_source_extend.io.d, io.in \n wire _io_out_WIRE : UInt<1> \n connect _io_out_WIRE, io_out_source_extend.io.q \n connect io.out, _io_out_WIRE"},"response":{"kind":"string","value":"module AsyncValidSync_14(\t// @[AsyncQueue.scala:58:7]\n input io_in,\t// @[AsyncQueue.scala:59:14]\n output io_out,\t// @[AsyncQueue.scala:59:14]\n input clock,\t// @[AsyncQueue.scala:63:17]\n input reset\t// @[AsyncQueue.scala:64:17]\n);\n\n wire io_in_0 = io_in;\t// @[AsyncQueue.scala:58:7]\n wire _io_out_WIRE;\t// @[ShiftReg.scala:48:24]\n wire io_out_0;\t// @[AsyncQueue.scala:58:7]\n assign io_out_0 = _io_out_WIRE;\t// @[ShiftReg.scala:48:24]\n AsyncResetSynchronizerShiftReg_w1_d3_i0_23 io_out_source_extend (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (reset),\n .io_d (io_in_0),\t// @[AsyncQueue.scala:58:7]\n .io_q (_io_out_WIRE)\n );\t// @[ShiftReg.scala:45:23]\n assign io_out = io_out_0;\t// @[AsyncQueue.scala:58:7]\nendmodule"}}},{"rowIdx":34198,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module SinkA : \n input clock : Clock \n input reset : Reset \n output io : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}}, flip a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip pb_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, pb_beat : { data : UInt<32>, mask : UInt<4>, corrupt : UInt<1>}} \n\n\n inst putbuffer of ListBuffer_PutBufferAEntry_q40_e40 \n connect putbuffer.clock, clock\n\n connect putbuffer.reset, reset\n\n regreset lists : UInt<40>, clock, reset, UInt<40>(0h0) \n wire lists_set : UInt<40> \n connect lists_set, UInt<40>(0h0) \n wire lists_clr : UInt<40> \n connect lists_clr, UInt<40>(0h0) \n node _lists_T = or(lists, lists_set) \n node _lists_T_1 = not(lists_clr) \n node _lists_T_2 = and(_lists_T, _lists_T_1) \n connect lists, _lists_T_2 \n node _free_T = andr(lists) \n node free = eq(_free_T, UInt<1>(0h0)) \n node _freeOH_T = not(lists) \n node _freeOH_T_1 = shl(_freeOH_T, 1) \n node _freeOH_T_2 = bits(_freeOH_T_1, 39, 0) \n node _freeOH_T_3 = or(_freeOH_T, _freeOH_T_2) \n node _freeOH_T_4 = shl(_freeOH_T_3, 2) \n node _freeOH_T_5 = bits(_freeOH_T_4, 39, 0) \n node _freeOH_T_6 = or(_freeOH_T_3, _freeOH_T_5) \n node _freeOH_T_7 = shl(_freeOH_T_6, 4) \n node _freeOH_T_8 = bits(_freeOH_T_7, 39, 0) \n node _freeOH_T_9 = or(_freeOH_T_6, _freeOH_T_8) \n node _freeOH_T_10 = shl(_freeOH_T_9, 8) \n node _freeOH_T_11 = bits(_freeOH_T_10, 39, 0) \n node _freeOH_T_12 = or(_freeOH_T_9, _freeOH_T_11) \n node _freeOH_T_13 = shl(_freeOH_T_12, 16) \n node _freeOH_T_14 = bits(_freeOH_T_13, 39, 0) \n node _freeOH_T_15 = or(_freeOH_T_12, _freeOH_T_14) \n node _freeOH_T_16 = shl(_freeOH_T_15, 32) \n node _freeOH_T_17 = bits(_freeOH_T_16, 39, 0) \n node _freeOH_T_18 = or(_freeOH_T_15, _freeOH_T_17) \n node _freeOH_T_19 = bits(_freeOH_T_18, 39, 0) \n node _freeOH_T_20 = shl(_freeOH_T_19, 1) \n node _freeOH_T_21 = not(_freeOH_T_20) \n node _freeOH_T_22 = not(lists) \n node freeOH = and(_freeOH_T_21, _freeOH_T_22) \n node freeIdx_hi = bits(freeOH, 40, 32) \n node freeIdx_lo = bits(freeOH, 31, 0) \n node _freeIdx_T = orr(freeIdx_hi) \n node _freeIdx_T_1 = or(freeIdx_hi, freeIdx_lo) \n node freeIdx_hi_1 = bits(_freeIdx_T_1, 31, 16) \n node freeIdx_lo_1 = bits(_freeIdx_T_1, 15, 0) \n node _freeIdx_T_2 = orr(freeIdx_hi_1) \n node _freeIdx_T_3 = or(freeIdx_hi_1, freeIdx_lo_1) \n node freeIdx_hi_2 = bits(_freeIdx_T_3, 15, 8) \n node freeIdx_lo_2 = bits(_freeIdx_T_3, 7, 0) \n node _freeIdx_T_4 = orr(freeIdx_hi_2) \n node _freeIdx_T_5 = or(freeIdx_hi_2, freeIdx_lo_2) \n node freeIdx_hi_3 = bits(_freeIdx_T_5, 7, 4) \n node freeIdx_lo_3 = bits(_freeIdx_T_5, 3, 0) \n node _freeIdx_T_6 = orr(freeIdx_hi_3) \n node _freeIdx_T_7 = or(freeIdx_hi_3, freeIdx_lo_3) \n node freeIdx_hi_4 = bits(_freeIdx_T_7, 3, 2) \n node freeIdx_lo_4 = bits(_freeIdx_T_7, 1, 0) \n node _freeIdx_T_8 = orr(freeIdx_hi_4) \n node _freeIdx_T_9 = or(freeIdx_hi_4, freeIdx_lo_4) \n node _freeIdx_T_10 = bits(_freeIdx_T_9, 1, 1) \n node _freeIdx_T_11 = cat(_freeIdx_T_8, _freeIdx_T_10) \n node _freeIdx_T_12 = cat(_freeIdx_T_6, _freeIdx_T_11) \n node _freeIdx_T_13 = cat(_freeIdx_T_4, _freeIdx_T_12) \n node _freeIdx_T_14 = cat(_freeIdx_T_2, _freeIdx_T_13) \n node freeIdx = cat(_freeIdx_T, _freeIdx_T_14) \n node _first_T = and(io.a.ready, io.a.valid) \n node _first_beats1_decode_T = dshl(UInt<6>(0h3f), io.a.bits.size) \n node _first_beats1_decode_T_1 = bits(_first_beats1_decode_T, 5, 0) \n node _first_beats1_decode_T_2 = not(_first_beats1_decode_T_1) \n node first_beats1_decode = shr(_first_beats1_decode_T_2, 2) \n node _first_beats1_opdata_T = bits(io.a.bits.opcode, 2, 2) \n node first_beats1_opdata = eq(_first_beats1_opdata_T, UInt<1>(0h0)) \n node first_beats1 = mux(first_beats1_opdata, first_beats1_decode, UInt<1>(0h0)) \n regreset first_counter : UInt<4>, clock, reset, UInt<4>(0h0) \n node _first_counter1_T = sub(first_counter, UInt<1>(0h1)) \n node first_counter1 = tail(_first_counter1_T, 1) \n node first = eq(first_counter, UInt<1>(0h0)) \n node _first_last_T = eq(first_counter, UInt<1>(0h1)) \n node _first_last_T_1 = eq(first_beats1, UInt<1>(0h0)) \n node first_last = or(_first_last_T, _first_last_T_1) \n node first_done = and(first_last, _first_T) \n node _first_count_T = not(first_counter1) \n node first_count = and(first_beats1, _first_count_T) \n when _first_T : \n node _first_counter_T = mux(first, first_beats1, first_counter1) \n connect first_counter, _first_counter_T \n node _hasData_opdata_T = bits(io.a.bits.opcode, 2, 2) \n node hasData = eq(_hasData_opdata_T, UInt<1>(0h0)) \n node _req_block_T = eq(io.req.ready, UInt<1>(0h0)) \n node req_block = and(first, _req_block_T) \n node _buf_block_T = eq(putbuffer.io.push.ready, UInt<1>(0h0)) \n node buf_block = and(hasData, _buf_block_T) \n node _set_block_T = and(hasData, first) \n node _set_block_T_1 = eq(free, UInt<1>(0h0)) \n node set_block = and(_set_block_T, _set_block_T_1) \n node _T = and(io.a.valid, req_block) \n node _T_1 = and(io.a.valid, buf_block) \n node _T_2 = and(io.a.valid, set_block) \n node _io_a_ready_T = eq(req_block, UInt<1>(0h0)) \n node _io_a_ready_T_1 = eq(buf_block, UInt<1>(0h0)) \n node _io_a_ready_T_2 = and(_io_a_ready_T, _io_a_ready_T_1) \n node _io_a_ready_T_3 = eq(set_block, UInt<1>(0h0)) \n node _io_a_ready_T_4 = and(_io_a_ready_T_2, _io_a_ready_T_3) \n connect io.a.ready, _io_a_ready_T_4 \n node _io_req_valid_T = and(io.a.valid, first) \n node _io_req_valid_T_1 = eq(buf_block, UInt<1>(0h0)) \n node _io_req_valid_T_2 = and(_io_req_valid_T, _io_req_valid_T_1) \n node _io_req_valid_T_3 = eq(set_block, UInt<1>(0h0)) \n node _io_req_valid_T_4 = and(_io_req_valid_T_2, _io_req_valid_T_3) \n connect io.req.valid, _io_req_valid_T_4 \n node _putbuffer_io_push_valid_T = and(io.a.valid, hasData) \n node _putbuffer_io_push_valid_T_1 = eq(req_block, UInt<1>(0h0)) \n node _putbuffer_io_push_valid_T_2 = and(_putbuffer_io_push_valid_T, _putbuffer_io_push_valid_T_1) \n node _putbuffer_io_push_valid_T_3 = eq(set_block, UInt<1>(0h0)) \n node _putbuffer_io_push_valid_T_4 = and(_putbuffer_io_push_valid_T_2, _putbuffer_io_push_valid_T_3) \n connect putbuffer.io.push.valid, _putbuffer_io_push_valid_T_4 \n node _T_3 = and(io.a.valid, first) \n node _T_4 = and(_T_3, hasData) \n node _T_5 = eq(req_block, UInt<1>(0h0)) \n node _T_6 = and(_T_4, _T_5) \n node _T_7 = eq(buf_block, UInt<1>(0h0)) \n node _T_8 = and(_T_6, _T_7) \n when _T_8 : \n connect lists_set, freeOH \n node _offset_T = bits(io.a.bits.address, 0, 0) \n node _offset_T_1 = bits(io.a.bits.address, 1, 1) \n node _offset_T_2 = bits(io.a.bits.address, 2, 2) \n node _offset_T_3 = bits(io.a.bits.address, 3, 3) \n node _offset_T_4 = bits(io.a.bits.address, 4, 4) \n node _offset_T_5 = bits(io.a.bits.address, 5, 5) \n node _offset_T_6 = bits(io.a.bits.address, 6, 6) \n node _offset_T_7 = bits(io.a.bits.address, 7, 7) \n node _offset_T_8 = bits(io.a.bits.address, 8, 8) \n node _offset_T_9 = bits(io.a.bits.address, 9, 9) \n node _offset_T_10 = bits(io.a.bits.address, 10, 10) \n node _offset_T_11 = bits(io.a.bits.address, 11, 11) \n node _offset_T_12 = bits(io.a.bits.address, 12, 12) \n node _offset_T_13 = bits(io.a.bits.address, 13, 13) \n node _offset_T_14 = bits(io.a.bits.address, 14, 14) \n node _offset_T_15 = bits(io.a.bits.address, 15, 15) \n node _offset_T_16 = bits(io.a.bits.address, 16, 16) \n node _offset_T_17 = bits(io.a.bits.address, 17, 17) \n node _offset_T_18 = bits(io.a.bits.address, 18, 18) \n node _offset_T_19 = bits(io.a.bits.address, 19, 19) \n node _offset_T_20 = bits(io.a.bits.address, 20, 20) \n node _offset_T_21 = bits(io.a.bits.address, 21, 21) \n node _offset_T_22 = bits(io.a.bits.address, 22, 22) \n node _offset_T_23 = bits(io.a.bits.address, 23, 23) \n node _offset_T_24 = bits(io.a.bits.address, 24, 24) \n node _offset_T_25 = bits(io.a.bits.address, 25, 25) \n node _offset_T_26 = bits(io.a.bits.address, 26, 26) \n node _offset_T_27 = bits(io.a.bits.address, 27, 27) \n node _offset_T_28 = bits(io.a.bits.address, 31, 31) \n node offset_lo_lo_lo_hi = cat(_offset_T_2, _offset_T_1) \n node offset_lo_lo_lo = cat(offset_lo_lo_lo_hi, _offset_T) \n node offset_lo_lo_hi_lo = cat(_offset_T_4, _offset_T_3) \n node offset_lo_lo_hi_hi = cat(_offset_T_6, _offset_T_5) \n node offset_lo_lo_hi = cat(offset_lo_lo_hi_hi, offset_lo_lo_hi_lo) \n node offset_lo_lo = cat(offset_lo_lo_hi, offset_lo_lo_lo) \n node offset_lo_hi_lo_hi = cat(_offset_T_9, _offset_T_8) \n node offset_lo_hi_lo = cat(offset_lo_hi_lo_hi, _offset_T_7) \n node offset_lo_hi_hi_lo = cat(_offset_T_11, _offset_T_10) \n node offset_lo_hi_hi_hi = cat(_offset_T_13, _offset_T_12) \n node offset_lo_hi_hi = cat(offset_lo_hi_hi_hi, offset_lo_hi_hi_lo) \n node offset_lo_hi = cat(offset_lo_hi_hi, offset_lo_hi_lo) \n node offset_lo = cat(offset_lo_hi, offset_lo_lo) \n node offset_hi_lo_lo_hi = cat(_offset_T_16, _offset_T_15) \n node offset_hi_lo_lo = cat(offset_hi_lo_lo_hi, _offset_T_14) \n node offset_hi_lo_hi_lo = cat(_offset_T_18, _offset_T_17) \n node offset_hi_lo_hi_hi = cat(_offset_T_20, _offset_T_19) \n node offset_hi_lo_hi = cat(offset_hi_lo_hi_hi, offset_hi_lo_hi_lo) \n node offset_hi_lo = cat(offset_hi_lo_hi, offset_hi_lo_lo) \n node offset_hi_hi_lo_lo = cat(_offset_T_22, _offset_T_21) \n node offset_hi_hi_lo_hi = cat(_offset_T_24, _offset_T_23) \n node offset_hi_hi_lo = cat(offset_hi_hi_lo_hi, offset_hi_hi_lo_lo) \n node offset_hi_hi_hi_lo = cat(_offset_T_26, _offset_T_25) \n node offset_hi_hi_hi_hi = cat(_offset_T_28, _offset_T_27) \n node offset_hi_hi_hi = cat(offset_hi_hi_hi_hi, offset_hi_hi_hi_lo) \n node offset_hi_hi = cat(offset_hi_hi_hi, offset_hi_hi_lo) \n node offset_hi = cat(offset_hi_hi, offset_hi_lo) \n node offset = cat(offset_hi, offset_lo) \n node set = shr(offset, 6) \n node tag = shr(set, 10) \n node tag_1 = bits(tag, 12, 0) \n node set_1 = bits(set, 9, 0) \n node offset_1 = bits(offset, 5, 0) \n reg put_r : UInt<6>, clock \n when first : \n connect put_r, freeIdx \n node put = mux(first, freeIdx, put_r) \n wire _WIRE : UInt<1>[3] \n connect _WIRE[0], UInt<1>(0h1) \n connect _WIRE[1], UInt<1>(0h0) \n connect _WIRE[2], UInt<1>(0h0) \n connect io.req.bits.prio, _WIRE \n connect io.req.bits.control, UInt<1>(0h0) \n connect io.req.bits.opcode, io.a.bits.opcode \n connect io.req.bits.param, io.a.bits.param \n connect io.req.bits.size, io.a.bits.size \n connect io.req.bits.source, io.a.bits.source \n connect io.req.bits.offset, offset_1 \n connect io.req.bits.set, set_1 \n connect io.req.bits.tag, tag_1 \n connect io.req.bits.put, put \n connect putbuffer.io.push.bits.index, put \n connect putbuffer.io.push.bits.data.data, io.a.bits.data \n connect putbuffer.io.push.bits.data.mask, io.a.bits.mask \n connect putbuffer.io.push.bits.data.corrupt, io.a.bits.corrupt \n connect putbuffer.io.pop.bits, io.pb_pop.bits.index \n node _putbuffer_io_pop_valid_T = and(io.pb_pop.ready, io.pb_pop.valid) \n connect putbuffer.io.pop.valid, _putbuffer_io_pop_valid_T \n node _io_pb_pop_ready_T = dshr(putbuffer.io.valid, io.pb_pop.bits.index) \n node _io_pb_pop_ready_T_1 = bits(_io_pb_pop_ready_T, 0, 0) \n connect io.pb_pop.ready, _io_pb_pop_ready_T_1 \n connect io.pb_beat, putbuffer.io.data \n node _T_9 = and(io.pb_pop.ready, io.pb_pop.valid) \n node _T_10 = and(_T_9, io.pb_pop.bits.last) \n when _T_10 : \n node lists_clr_shiftAmount = bits(io.pb_pop.bits.index, 5, 0) \n node _lists_clr_T = dshl(UInt<1>(0h1), lists_clr_shiftAmount) \n node _lists_clr_T_1 = bits(_lists_clr_T, 39, 0) \n connect lists_clr, _lists_clr_T_1"},"response":{"kind":"string","value":"module SinkA(\t// @[SinkA.scala:38:7]\n input clock,\t// @[SinkA.scala:38:7]\n input reset,\t// @[SinkA.scala:38:7]\n input io_req_ready,\t// @[SinkA.scala:40:14]\n output io_req_valid,\t// @[SinkA.scala:40:14]\n output [2:0] io_req_bits_opcode,\t// @[SinkA.scala:40:14]\n output [2:0] io_req_bits_param,\t// @[SinkA.scala:40:14]\n output [2:0] io_req_bits_size,\t// @[SinkA.scala:40:14]\n output [5:0] io_req_bits_source,\t// @[SinkA.scala:40:14]\n output [12:0] io_req_bits_tag,\t// @[SinkA.scala:40:14]\n output [5:0] io_req_bits_offset,\t// @[SinkA.scala:40:14]\n output [5:0] io_req_bits_put,\t// @[SinkA.scala:40:14]\n output [9:0] io_req_bits_set,\t// @[SinkA.scala:40:14]\n output io_a_ready,\t// @[SinkA.scala:40:14]\n input io_a_valid,\t// @[SinkA.scala:40:14]\n input [2:0] io_a_bits_opcode,\t// @[SinkA.scala:40:14]\n input [2:0] io_a_bits_param,\t// @[SinkA.scala:40:14]\n input [2:0] io_a_bits_size,\t// @[SinkA.scala:40:14]\n input [5:0] io_a_bits_source,\t// @[SinkA.scala:40:14]\n input [31:0] io_a_bits_address,\t// @[SinkA.scala:40:14]\n input [3:0] io_a_bits_mask,\t// @[SinkA.scala:40:14]\n input [31:0] io_a_bits_data,\t// @[SinkA.scala:40:14]\n input io_a_bits_corrupt,\t// @[SinkA.scala:40:14]\n output io_pb_pop_ready,\t// @[SinkA.scala:40:14]\n input io_pb_pop_valid,\t// @[SinkA.scala:40:14]\n input [5:0] io_pb_pop_bits_index,\t// @[SinkA.scala:40:14]\n input io_pb_pop_bits_last,\t// @[SinkA.scala:40:14]\n output [31:0] io_pb_beat_data,\t// @[SinkA.scala:40:14]\n output [3:0] io_pb_beat_mask,\t// @[SinkA.scala:40:14]\n output io_pb_beat_corrupt\t// @[SinkA.scala:40:14]\n);\n\n wire _putbuffer_io_push_ready;\t// @[SinkA.scala:51:25]\n wire [39:0] _putbuffer_io_valid;\t// @[SinkA.scala:51:25]\n wire io_req_ready_0 = io_req_ready;\t// @[SinkA.scala:38:7]\n wire io_a_valid_0 = io_a_valid;\t// @[SinkA.scala:38:7]\n wire [2:0] io_a_bits_opcode_0 = io_a_bits_opcode;\t// @[SinkA.scala:38:7]\n wire [2:0] io_a_bits_param_0 = io_a_bits_param;\t// @[SinkA.scala:38:7]\n wire [2:0] io_a_bits_size_0 = io_a_bits_size;\t// @[SinkA.scala:38:7]\n wire [5:0] io_a_bits_source_0 = io_a_bits_source;\t// @[SinkA.scala:38:7]\n wire [31:0] io_a_bits_address_0 = io_a_bits_address;\t// @[SinkA.scala:38:7]\n wire [3:0] io_a_bits_mask_0 = io_a_bits_mask;\t// @[SinkA.scala:38:7]\n wire [31:0] io_a_bits_data_0 = io_a_bits_data;\t// @[SinkA.scala:38:7]\n wire io_a_bits_corrupt_0 = io_a_bits_corrupt;\t// @[SinkA.scala:38:7]\n wire io_pb_pop_valid_0 = io_pb_pop_valid;\t// @[SinkA.scala:38:7]\n wire [5:0] io_pb_pop_bits_index_0 = io_pb_pop_bits_index;\t// @[SinkA.scala:38:7]\n wire io_pb_pop_bits_last_0 = io_pb_pop_bits_last;\t// @[SinkA.scala:38:7]\n wire io_req_bits_prio_1 = 1'h0;\t// @[SinkA.scala:38:7]\n wire io_req_bits_prio_2 = 1'h0;\t// @[SinkA.scala:38:7]\n wire io_req_bits_control = 1'h0;\t// @[SinkA.scala:38:7]\n wire io_req_bits_prio_0 = 1'h1;\t// @[SinkA.scala:38:7]\n wire _io_req_valid_T_4;\t// @[SinkA.scala:79:50]\n wire [12:0] tag_1;\t// @[Parameters.scala:217:9]\n wire [5:0] offset_1;\t// @[Parameters.scala:217:50]\n wire [5:0] put;\t// @[SinkA.scala:84:16]\n wire [9:0] set_1;\t// @[Parameters.scala:217:28]\n wire _io_a_ready_T_4;\t// @[SinkA.scala:78:39]\n wire [2:0] io_req_bits_opcode_0 = io_a_bits_opcode_0;\t// @[SinkA.scala:38:7]\n wire [2:0] io_req_bits_param_0 = io_a_bits_param_0;\t// @[SinkA.scala:38:7]\n wire [2:0] io_req_bits_size_0 = io_a_bits_size_0;\t// @[SinkA.scala:38:7]\n wire [5:0] io_req_bits_source_0 = io_a_bits_source_0;\t// @[SinkA.scala:38:7]\n wire _io_pb_pop_ready_T_1;\t// @[SinkA.scala:105:40]\n wire [5:0] lists_clr_shiftAmount = io_pb_pop_bits_index_0;\t// @[OneHot.scala:64:49]\n wire [12:0] io_req_bits_tag_0;\t// @[SinkA.scala:38:7]\n wire [5:0] io_req_bits_offset_0;\t// @[SinkA.scala:38:7]\n wire [5:0] io_req_bits_put_0;\t// @[SinkA.scala:38:7]\n wire [9:0] io_req_bits_set_0;\t// @[SinkA.scala:38:7]\n wire io_req_valid_0;\t// @[SinkA.scala:38:7]\n wire io_a_ready_0;\t// @[SinkA.scala:38:7]\n wire io_pb_pop_ready_0;\t// @[SinkA.scala:38:7]\n wire [31:0] io_pb_beat_data_0;\t// @[SinkA.scala:38:7]\n wire [3:0] io_pb_beat_mask_0;\t// @[SinkA.scala:38:7]\n wire io_pb_beat_corrupt_0;\t// @[SinkA.scala:38:7]\n reg [39:0] lists;\t// @[SinkA.scala:52:22]\n wire [39:0] lists_set;\t// @[SinkA.scala:54:27]\n wire [39:0] lists_clr;\t// @[SinkA.scala:55:27]\n wire [39:0] _lists_T = lists | lists_set;\t// @[SinkA.scala:52:22, :54:27, :56:19]\n wire [39:0] _lists_T_1 = ~lists_clr;\t// @[SinkA.scala:55:27, :56:34]\n wire [39:0] _lists_T_2 = _lists_T & _lists_T_1;\t// @[SinkA.scala:56:{19,32,34}]\n wire _free_T = &lists;\t// @[SinkA.scala:52:22, :58:21]\n wire free = ~_free_T;\t// @[SinkA.scala:58:{14,21}]\n wire [39:0] _freeOH_T = ~lists;\t// @[SinkA.scala:52:22, :59:25]\n wire [40:0] _freeOH_T_1 = {_freeOH_T, 1'h0};\t// @[package.scala:253:48]\n wire [39:0] _freeOH_T_2 = _freeOH_T_1[39:0];\t// @[package.scala:253:{48,53}]\n wire [39:0] _freeOH_T_3 = _freeOH_T | _freeOH_T_2;\t// @[package.scala:253:{43,53}]\n wire [41:0] _freeOH_T_4 = {_freeOH_T_3, 2'h0};\t// @[package.scala:253:{43,48}]\n wire [39:0] _freeOH_T_5 = _freeOH_T_4[39:0];\t// @[package.scala:253:{48,53}]\n wire [39:0] _freeOH_T_6 = _freeOH_T_3 | _freeOH_T_5;\t// @[package.scala:253:{43,53}]\n wire [43:0] _freeOH_T_7 = {_freeOH_T_6, 4'h0};\t// @[package.scala:253:{43,48}]\n wire [39:0] _freeOH_T_8 = _freeOH_T_7[39:0];\t// @[package.scala:253:{48,53}]\n wire [39:0] _freeOH_T_9 = _freeOH_T_6 | _freeOH_T_8;\t// @[package.scala:253:{43,53}]\n wire [47:0] _freeOH_T_10 = {_freeOH_T_9, 8'h0};\t// @[package.scala:253:{43,48}]\n wire [39:0] _freeOH_T_11 = _freeOH_T_10[39:0];\t// @[package.scala:253:{48,53}]\n wire [39:0] _freeOH_T_12 = _freeOH_T_9 | _freeOH_T_11;\t// @[package.scala:253:{43,53}]\n wire [55:0] _freeOH_T_13 = {_freeOH_T_12, 16'h0};\t// @[package.scala:253:{43,48}]\n wire [39:0] _freeOH_T_14 = _freeOH_T_13[39:0];\t// @[package.scala:253:{48,53}]\n wire [39:0] _freeOH_T_15 = _freeOH_T_12 | _freeOH_T_14;\t// @[package.scala:253:{43,53}]\n wire [71:0] _freeOH_T_16 = {_freeOH_T_15, 32'h0};\t// @[package.scala:253:{43,48}]\n wire [39:0] _freeOH_T_17 = _freeOH_T_16[39:0];\t// @[package.scala:253:{48,53}]\n wire [39:0] _freeOH_T_18 = _freeOH_T_15 | _freeOH_T_17;\t// @[package.scala:253:{43,53}]\n wire [39:0] _freeOH_T_19 = _freeOH_T_18;\t// @[package.scala:253:43, :254:17]\n wire [40:0] _freeOH_T_20 = {_freeOH_T_19, 1'h0};\t// @[package.scala:254:17]\n wire [40:0] _freeOH_T_21 = ~_freeOH_T_20;\t// @[SinkA.scala:59:{16,33}]\n wire [39:0] _freeOH_T_22 = ~lists;\t// @[SinkA.scala:52:22, :59:{25,41}]\n wire [40:0] freeOH = {1'h0, _freeOH_T_21[39:0] & _freeOH_T_22};\t// @[SinkA.scala:59:{16,39,41}]\n wire [8:0] freeIdx_hi = freeOH[40:32];\t// @[OneHot.scala:30:18]\n wire [31:0] freeIdx_lo = freeOH[31:0];\t// @[OneHot.scala:31:18]\n wire _freeIdx_T = |freeIdx_hi;\t// @[OneHot.scala:30:18, :32:14]\n wire [31:0] _freeIdx_T_1 = {23'h0, freeIdx_hi} | freeIdx_lo;\t// @[OneHot.scala:30:18, :31:18, :32:28]\n wire [15:0] freeIdx_hi_1 = _freeIdx_T_1[31:16];\t// @[OneHot.scala:30:18, :32:28]\n wire [15:0] freeIdx_lo_1 = _freeIdx_T_1[15:0];\t// @[OneHot.scala:31:18, :32:28]\n wire _freeIdx_T_2 = |freeIdx_hi_1;\t// @[OneHot.scala:30:18, :32:14]\n wire [15:0] _freeIdx_T_3 = freeIdx_hi_1 | freeIdx_lo_1;\t// @[OneHot.scala:30:18, :31:18, :32:28]\n wire [7:0] freeIdx_hi_2 = _freeIdx_T_3[15:8];\t// @[OneHot.scala:30:18, :32:28]\n wire [7:0] freeIdx_lo_2 = _freeIdx_T_3[7:0];\t// @[OneHot.scala:31:18, :32:28]\n wire _freeIdx_T_4 = |freeIdx_hi_2;\t// @[OneHot.scala:30:18, :32:14]\n wire [7:0] _freeIdx_T_5 = freeIdx_hi_2 | freeIdx_lo_2;\t// @[OneHot.scala:30:18, :31:18, :32:28]\n wire [3:0] freeIdx_hi_3 = _freeIdx_T_5[7:4];\t// @[OneHot.scala:30:18, :32:28]\n wire [3:0] freeIdx_lo_3 = _freeIdx_T_5[3:0];\t// @[OneHot.scala:31:18, :32:28]\n wire _freeIdx_T_6 = |freeIdx_hi_3;\t// @[OneHot.scala:30:18, :32:14]\n wire [3:0] _freeIdx_T_7 = freeIdx_hi_3 | freeIdx_lo_3;\t// @[OneHot.scala:30:18, :31:18, :32:28]\n wire [1:0] freeIdx_hi_4 = _freeIdx_T_7[3:2];\t// @[OneHot.scala:30:18, :32:28]\n wire [1:0] freeIdx_lo_4 = _freeIdx_T_7[1:0];\t// @[OneHot.scala:31:18, :32:28]\n wire _freeIdx_T_8 = |freeIdx_hi_4;\t// @[OneHot.scala:30:18, :32:14]\n wire [1:0] _freeIdx_T_9 = freeIdx_hi_4 | freeIdx_lo_4;\t// @[OneHot.scala:30:18, :31:18, :32:28]\n wire _freeIdx_T_10 = _freeIdx_T_9[1];\t// @[OneHot.scala:32:28]\n wire [1:0] _freeIdx_T_11 = {_freeIdx_T_8, _freeIdx_T_10};\t// @[OneHot.scala:32:{10,14}]\n wire [2:0] _freeIdx_T_12 = {_freeIdx_T_6, _freeIdx_T_11};\t// @[OneHot.scala:32:{10,14}]\n wire [3:0] _freeIdx_T_13 = {_freeIdx_T_4, _freeIdx_T_12};\t// @[OneHot.scala:32:{10,14}]\n wire [4:0] _freeIdx_T_14 = {_freeIdx_T_2, _freeIdx_T_13};\t// @[OneHot.scala:32:{10,14}]\n wire [5:0] freeIdx = {_freeIdx_T, _freeIdx_T_14};\t// @[OneHot.scala:32:{10,14}]\n wire _first_T = io_a_ready_0 & io_a_valid_0;\t// @[Decoupled.scala:51:35]\n wire [12:0] _first_beats1_decode_T = 13'h3F << io_a_bits_size_0;\t// @[package.scala:243:71]\n wire [5:0] _first_beats1_decode_T_1 = _first_beats1_decode_T[5:0];\t// @[package.scala:243:{71,76}]\n wire [5:0] _first_beats1_decode_T_2 = ~_first_beats1_decode_T_1;\t// @[package.scala:243:{46,76}]\n wire [3:0] first_beats1_decode = _first_beats1_decode_T_2[5:2];\t// @[package.scala:243:46]\n wire _first_beats1_opdata_T = io_a_bits_opcode_0[2];\t// @[Edges.scala:92:37]\n wire _hasData_opdata_T = io_a_bits_opcode_0[2];\t// @[Edges.scala:92:37]\n wire first_beats1_opdata = ~_first_beats1_opdata_T;\t// @[Edges.scala:92:{28,37}]\n wire [3:0] first_beats1 = first_beats1_opdata ? first_beats1_decode : 4'h0;\t// @[Edges.scala:92:28, :220:59, :221:14]\n reg [3:0] first_counter;\t// @[Edges.scala:229:27]\n wire [4:0] _first_counter1_T = {1'h0, first_counter} - 5'h1;\t// @[Edges.scala:229:27, :230:28]\n wire [3:0] first_counter1 = _first_counter1_T[3:0];\t// @[Edges.scala:230:28]\n wire first = first_counter == 4'h0;\t// @[Edges.scala:229:27, :231:25]\n wire _first_last_T = first_counter == 4'h1;\t// @[Edges.scala:229:27, :232:25]\n wire _first_last_T_1 = first_beats1 == 4'h0;\t// @[Edges.scala:221:14, :232:43]\n wire first_last = _first_last_T | _first_last_T_1;\t// @[Edges.scala:232:{25,33,43}]\n wire first_done = first_last & _first_T;\t// @[Decoupled.scala:51:35]\n wire [3:0] _first_count_T = ~first_counter1;\t// @[Edges.scala:230:28, :234:27]\n wire [3:0] first_count = first_beats1 & _first_count_T;\t// @[Edges.scala:221:14, :234:{25,27}]\n wire [3:0] _first_counter_T = first ? first_beats1 : first_counter1;\t// @[Edges.scala:221:14, :230:28, :231:25, :236:21]\n wire hasData = ~_hasData_opdata_T;\t// @[Edges.scala:92:{28,37}]\n wire _req_block_T = ~io_req_ready_0;\t// @[SinkA.scala:38:7, :70:28]\n wire req_block = first & _req_block_T;\t// @[Edges.scala:231:25]\n wire _buf_block_T = ~_putbuffer_io_push_ready;\t// @[SinkA.scala:51:25, :71:30]\n wire buf_block = hasData & _buf_block_T;\t// @[Edges.scala:92:28]\n wire _set_block_T = hasData & first;\t// @[Edges.scala:92:28, :231:25]\n wire _set_block_T_1 = ~free;\t// @[SinkA.scala:58:14, :72:39]\n wire set_block = _set_block_T & _set_block_T_1;\t// @[SinkA.scala:72:{27,36,39}]\n wire _io_a_ready_T = ~req_block;\t// @[SinkA.scala:70:25, :78:14]\n wire _io_a_ready_T_1 = ~buf_block;\t// @[SinkA.scala:71:27, :78:28]\n wire _io_a_ready_T_2 = _io_a_ready_T & _io_a_ready_T_1;\t// @[SinkA.scala:78:{14,25,28}]\n wire _io_a_ready_T_3 = ~set_block;\t// @[SinkA.scala:72:36, :78:42]\n assign _io_a_ready_T_4 = _io_a_ready_T_2 & _io_a_ready_T_3;\t// @[SinkA.scala:78:{25,39,42}]\n assign io_a_ready_0 = _io_a_ready_T_4;\t// @[SinkA.scala:38:7, :78:39]\n wire _io_req_valid_T = io_a_valid_0 & first;\t// @[Edges.scala:231:25]\n wire _io_req_valid_T_1 = ~buf_block;\t// @[SinkA.scala:71:27, :78:28, :79:39]\n wire _io_req_valid_T_2 = _io_req_valid_T & _io_req_valid_T_1;\t// @[SinkA.scala:79:{27,36,39}]\n wire _io_req_valid_T_3 = ~set_block;\t// @[SinkA.scala:72:36, :78:42, :79:53]\n assign _io_req_valid_T_4 = _io_req_valid_T_2 & _io_req_valid_T_3;\t// @[SinkA.scala:79:{36,50,53}]\n assign io_req_valid_0 = _io_req_valid_T_4;\t// @[SinkA.scala:38:7, :79:50]\n wire _putbuffer_io_push_valid_T = io_a_valid_0 & hasData;\t// @[Edges.scala:92:28]\n wire _putbuffer_io_push_valid_T_1 = ~req_block;\t// @[SinkA.scala:70:25, :78:14, :80:52]\n wire _putbuffer_io_push_valid_T_2 = _putbuffer_io_push_valid_T & _putbuffer_io_push_valid_T_1;\t// @[SinkA.scala:80:{38,49,52}]\n wire _putbuffer_io_push_valid_T_3 = ~set_block;\t// @[SinkA.scala:72:36, :78:42, :80:66]\n wire _putbuffer_io_push_valid_T_4 = _putbuffer_io_push_valid_T_2 & _putbuffer_io_push_valid_T_3;\t// @[SinkA.scala:80:{49,63,66}]\n assign lists_set = _io_req_valid_T & hasData & ~req_block & ~buf_block ? freeOH[39:0] : 40'h0;\t// @[Edges.scala:92:28]\n wire _offset_T = io_a_bits_address_0[0];\t// @[SinkA.scala:38:7]\n wire _offset_T_1 = io_a_bits_address_0[1];\t// @[SinkA.scala:38:7]\n wire _offset_T_2 = io_a_bits_address_0[2];\t// @[SinkA.scala:38:7]\n wire _offset_T_3 = io_a_bits_address_0[3];\t// @[SinkA.scala:38:7]\n wire _offset_T_4 = io_a_bits_address_0[4];\t// @[SinkA.scala:38:7]\n wire _offset_T_5 = io_a_bits_address_0[5];\t// @[SinkA.scala:38:7]\n wire _offset_T_6 = io_a_bits_address_0[6];\t// @[SinkA.scala:38:7]\n wire _offset_T_7 = io_a_bits_address_0[7];\t// @[SinkA.scala:38:7]\n wire _offset_T_8 = io_a_bits_address_0[8];\t// @[SinkA.scala:38:7]\n wire _offset_T_9 = io_a_bits_address_0[9];\t// @[SinkA.scala:38:7]\n wire _offset_T_10 = io_a_bits_address_0[10];\t// @[SinkA.scala:38:7]\n wire _offset_T_11 = io_a_bits_address_0[11];\t// @[SinkA.scala:38:7]\n wire _offset_T_12 = io_a_bits_address_0[12];\t// @[SinkA.scala:38:7]\n wire _offset_T_13 = io_a_bits_address_0[13];\t// @[SinkA.scala:38:7]\n wire _offset_T_14 = io_a_bits_address_0[14];\t// @[SinkA.scala:38:7]\n wire _offset_T_15 = io_a_bits_address_0[15];\t// @[SinkA.scala:38:7]\n wire _offset_T_16 = io_a_bits_address_0[16];\t// @[SinkA.scala:38:7]\n wire _offset_T_17 = io_a_bits_address_0[17];\t// @[SinkA.scala:38:7]\n wire _offset_T_18 = io_a_bits_address_0[18];\t// @[SinkA.scala:38:7]\n wire _offset_T_19 = io_a_bits_address_0[19];\t// @[SinkA.scala:38:7]\n wire _offset_T_20 = io_a_bits_address_0[20];\t// @[SinkA.scala:38:7]\n wire _offset_T_21 = io_a_bits_address_0[21];\t// @[SinkA.scala:38:7]\n wire _offset_T_22 = io_a_bits_address_0[22];\t// @[SinkA.scala:38:7]\n wire _offset_T_23 = io_a_bits_address_0[23];\t// @[SinkA.scala:38:7]\n wire _offset_T_24 = io_a_bits_address_0[24];\t// @[SinkA.scala:38:7]\n wire _offset_T_25 = io_a_bits_address_0[25];\t// @[SinkA.scala:38:7]\n wire _offset_T_26 = io_a_bits_address_0[26];\t// @[SinkA.scala:38:7]\n wire _offset_T_27 = io_a_bits_address_0[27];\t// @[SinkA.scala:38:7]\n wire _offset_T_28 = io_a_bits_address_0[31];\t// @[SinkA.scala:38:7]\n wire [1:0] offset_lo_lo_lo_hi = {_offset_T_2, _offset_T_1};\t// @[Parameters.scala:214:{21,47}]\n wire [2:0] offset_lo_lo_lo = {offset_lo_lo_lo_hi, _offset_T};\t// @[Parameters.scala:214:{21,47}]\n wire [1:0] offset_lo_lo_hi_lo = {_offset_T_4, _offset_T_3};\t// @[Parameters.scala:214:{21,47}]\n wire [1:0] offset_lo_lo_hi_hi = {_offset_T_6, _offset_T_5};\t// @[Parameters.scala:214:{21,47}]\n wire [3:0] offset_lo_lo_hi = {offset_lo_lo_hi_hi, offset_lo_lo_hi_lo};\t// @[Parameters.scala:214:21]\n wire [6:0] offset_lo_lo = {offset_lo_lo_hi, offset_lo_lo_lo};\t// @[Parameters.scala:214:21]\n wire [1:0] offset_lo_hi_lo_hi = {_offset_T_9, _offset_T_8};\t// @[Parameters.scala:214:{21,47}]\n wire [2:0] offset_lo_hi_lo = {offset_lo_hi_lo_hi, _offset_T_7};\t// @[Parameters.scala:214:{21,47}]\n wire [1:0] offset_lo_hi_hi_lo = {_offset_T_11, _offset_T_10};\t// @[Parameters.scala:214:{21,47}]\n wire [1:0] offset_lo_hi_hi_hi = {_offset_T_13, _offset_T_12};\t// @[Parameters.scala:214:{21,47}]\n wire [3:0] offset_lo_hi_hi = {offset_lo_hi_hi_hi, offset_lo_hi_hi_lo};\t// @[Parameters.scala:214:21]\n wire [6:0] offset_lo_hi = {offset_lo_hi_hi, offset_lo_hi_lo};\t// @[Parameters.scala:214:21]\n wire [13:0] offset_lo = {offset_lo_hi, offset_lo_lo};\t// @[Parameters.scala:214:21]\n wire [1:0] offset_hi_lo_lo_hi = {_offset_T_16, _offset_T_15};\t// @[Parameters.scala:214:{21,47}]\n wire [2:0] offset_hi_lo_lo = {offset_hi_lo_lo_hi, _offset_T_14};\t// @[Parameters.scala:214:{21,47}]\n wire [1:0] offset_hi_lo_hi_lo = {_offset_T_18, _offset_T_17};\t// @[Parameters.scala:214:{21,47}]\n wire [1:0] offset_hi_lo_hi_hi = {_offset_T_20, _offset_T_19};\t// @[Parameters.scala:214:{21,47}]\n wire [3:0] offset_hi_lo_hi = {offset_hi_lo_hi_hi, offset_hi_lo_hi_lo};\t// @[Parameters.scala:214:21]\n wire [6:0] offset_hi_lo = {offset_hi_lo_hi, offset_hi_lo_lo};\t// @[Parameters.scala:214:21]\n wire [1:0] offset_hi_hi_lo_lo = {_offset_T_22, _offset_T_21};\t// @[Parameters.scala:214:{21,47}]\n wire [1:0] offset_hi_hi_lo_hi = {_offset_T_24, _offset_T_23};\t// @[Parameters.scala:214:{21,47}]\n wire [3:0] offset_hi_hi_lo = {offset_hi_hi_lo_hi, offset_hi_hi_lo_lo};\t// @[Parameters.scala:214:21]\n wire [1:0] offset_hi_hi_hi_lo = {_offset_T_26, _offset_T_25};\t// @[Parameters.scala:214:{21,47}]\n wire [1:0] offset_hi_hi_hi_hi = {_offset_T_28, _offset_T_27};\t// @[Parameters.scala:214:{21,47}]\n wire [3:0] offset_hi_hi_hi = {offset_hi_hi_hi_hi, offset_hi_hi_hi_lo};\t// @[Parameters.scala:214:21]\n wire [7:0] offset_hi_hi = {offset_hi_hi_hi, offset_hi_hi_lo};\t// @[Parameters.scala:214:21]\n wire [14:0] offset_hi = {offset_hi_hi, offset_hi_lo};\t// @[Parameters.scala:214:21]\n wire [28:0] offset = {offset_hi, offset_lo};\t// @[Parameters.scala:214:21]\n wire [22:0] set = offset[28:6];\t// @[Parameters.scala:214:21, :215:22]\n wire [12:0] tag = set[22:10];\t// @[Parameters.scala:215:22, :216:19]\n assign tag_1 = tag;\t// @[Parameters.scala:216:19, :217:9]\n assign io_req_bits_tag_0 = tag_1;\t// @[SinkA.scala:38:7]\n assign set_1 = set[9:0];\t// @[Parameters.scala:215:22, :217:28]\n assign io_req_bits_set_0 = set_1;\t// @[SinkA.scala:38:7]\n assign offset_1 = offset[5:0];\t// @[Parameters.scala:214:21, :217:50]\n assign io_req_bits_offset_0 = offset_1;\t// @[SinkA.scala:38:7]\n reg [5:0] put_r;\t// @[SinkA.scala:84:42]\n assign put = first ? freeIdx : put_r;\t// @[OneHot.scala:32:10]\n assign io_req_bits_put_0 = put;\t// @[SinkA.scala:38:7, :84:16]\n wire _putbuffer_io_pop_valid_T = io_pb_pop_ready_0 & io_pb_pop_valid_0;\t// @[Decoupled.scala:51:35]\n wire [39:0] _io_pb_pop_ready_T = _putbuffer_io_valid >> io_pb_pop_bits_index_0;\t// @[SinkA.scala:38:7, :51:25, :105:40]\n assign _io_pb_pop_ready_T_1 = _io_pb_pop_ready_T[0];\t// @[SinkA.scala:105:40]\n assign io_pb_pop_ready_0 = _io_pb_pop_ready_T_1;\t// @[SinkA.scala:38:7, :105:40]\n wire [63:0] _lists_clr_T = 64'h1 << lists_clr_shiftAmount;\t// @[OneHot.scala:64:49, :65:12]\n wire [39:0] _lists_clr_T_1 = _lists_clr_T[39:0];\t// @[OneHot.scala:65:{12,27}]\n assign lists_clr = _putbuffer_io_pop_valid_T & io_pb_pop_bits_last_0 ? _lists_clr_T_1 : 40'h0;\t// @[OneHot.scala:65:27]\n always @(posedge clock) begin\t// @[SinkA.scala:38:7]\n if (reset) begin\t// @[SinkA.scala:38:7]\n lists <= 40'h0;\t// @[SinkA.scala:52:22]\n first_counter <= 4'h0;\t// @[Edges.scala:229:27]\n end\n else begin\t// @[SinkA.scala:38:7]\n lists <= _lists_T_2;\t// @[SinkA.scala:52:22, :56:32]\n if (_first_T)\t// @[Decoupled.scala:51:35]\n first_counter <= _first_counter_T;\t// @[Edges.scala:229:27, :236:21]\n end\n if (first)\t// @[Edges.scala:231:25]\n put_r <= freeIdx;\t// @[OneHot.scala:32:10]\n always @(posedge)\n ListBuffer_PutBufferAEntry_q40_e40 putbuffer (\t// @[SinkA.scala:51:25]\n .clock (clock),\n .reset (reset),\n .io_push_ready (_putbuffer_io_push_ready),\n .io_push_valid (_putbuffer_io_push_valid_T_4),\t// @[SinkA.scala:80:63]\n .io_push_bits_index (put),\t// @[SinkA.scala:84:16]\n .io_push_bits_data_data (io_a_bits_data_0),\t// @[SinkA.scala:38:7]\n .io_push_bits_data_mask (io_a_bits_mask_0),\t// @[SinkA.scala:38:7]\n .io_push_bits_data_corrupt (io_a_bits_corrupt_0),\t// @[SinkA.scala:38:7]\n .io_valid (_putbuffer_io_valid),\n .io_pop_valid (_putbuffer_io_pop_valid_T),\t// @[Decoupled.scala:51:35]\n .io_pop_bits (io_pb_pop_bits_index_0),\t// @[SinkA.scala:38:7]\n .io_data_data (io_pb_beat_data_0),\n .io_data_mask (io_pb_beat_mask_0),\n .io_data_corrupt (io_pb_beat_corrupt_0)\n );\t// @[SinkA.scala:51:25]\n assign io_req_valid = io_req_valid_0;\t// @[SinkA.scala:38:7]\n assign io_req_bits_opcode = io_req_bits_opcode_0;\t// @[SinkA.scala:38:7]\n assign io_req_bits_param = io_req_bits_param_0;\t// @[SinkA.scala:38:7]\n assign io_req_bits_size = io_req_bits_size_0;\t// @[SinkA.scala:38:7]\n assign io_req_bits_source = io_req_bits_source_0;\t// @[SinkA.scala:38:7]\n assign io_req_bits_tag = io_req_bits_tag_0;\t// @[SinkA.scala:38:7]\n assign io_req_bits_offset = io_req_bits_offset_0;\t// @[SinkA.scala:38:7]\n assign io_req_bits_put = io_req_bits_put_0;\t// @[SinkA.scala:38:7]\n assign io_req_bits_set = io_req_bits_set_0;\t// @[SinkA.scala:38:7]\n assign io_a_ready = io_a_ready_0;\t// @[SinkA.scala:38:7]\n assign io_pb_pop_ready = io_pb_pop_ready_0;\t// @[SinkA.scala:38:7]\n assign io_pb_beat_data = io_pb_beat_data_0;\t// @[SinkA.scala:38:7]\n assign io_pb_beat_mask = io_pb_beat_mask_0;\t// @[SinkA.scala:38:7]\n assign io_pb_beat_corrupt = io_pb_beat_corrupt_0;\t// @[SinkA.scala:38:7]\nendmodule"}}},{"rowIdx":34199,"cells":{"prompt":{"kind":"string","value":"Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_7 : \n output io : { flip in : UInt<1>, out : UInt<1>} \n input clock : Clock \n input reset : AsyncReset \n\n\n inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_9 \n connect io_out_source_valid.clock, clock\n\n connect io_out_source_valid.reset, reset\n\n connect io_out_source_valid.io.d, io.in \n wire _io_out_WIRE : UInt<1> \n connect _io_out_WIRE, io_out_source_valid.io.q \n connect io.out, _io_out_WIRE"},"response":{"kind":"string","value":"module AsyncValidSync_7(\t// @[AsyncQueue.scala:58:7]\n input io_in,\t// @[AsyncQueue.scala:59:14]\n output io_out,\t// @[AsyncQueue.scala:59:14]\n input clock,\t// @[AsyncQueue.scala:63:17]\n input reset\t// @[AsyncQueue.scala:64:17]\n);\n\n wire io_in_0 = io_in;\t// @[AsyncQueue.scala:58:7]\n wire _io_out_WIRE;\t// @[ShiftReg.scala:48:24]\n wire io_out_0;\t// @[AsyncQueue.scala:58:7]\n assign io_out_0 = _io_out_WIRE;\t// @[ShiftReg.scala:48:24]\n AsyncResetSynchronizerShiftReg_w1_d3_i0_9 io_out_source_valid (\t// @[ShiftReg.scala:45:23]\n .clock (clock),\n .reset (reset),\n .io_d (io_in_0),\t// @[AsyncQueue.scala:58:7]\n .io_q (_io_out_WIRE)\n );\t// @[ShiftReg.scala:45:23]\n assign io_out = io_out_0;\t// @[AsyncQueue.scala:58:7]\nendmodule"}}}],"truncated":false,"partial":false},"paginationData":{"pageIndex":341,"numItemsPerPage":100,"numTotalItems":35529,"offset":34100,"length":100}},"jwt":"eyJhbGciOiJFZERTQSJ9.eyJyZWFkIjp0cnVlLCJwZXJtaXNzaW9ucyI6eyJyZXBvLmNvbnRlbnQucmVhZCI6dHJ1ZX0sImlhdCI6MTc1MjQ1MTQwOSwic3ViIjoiL2RhdGFzZXRzL3J0bC1sbG0vY2hpc2VsLXZlcmlsb2ctcGFpcnMiLCJleHAiOjE3NTI0NTUwMDksImlzcyI6Imh0dHBzOi8vaHVnZ2luZ2ZhY2UuY28ifQ.0gKEg112IuGIVzUg9pecCSxUe0q7SaVqJNHkP4YaBxvhVJKDUVbhL3YfMmBShI48_OvxT8Gtp53z4dYsC9G5Ag","displayUrls":true},"discussionsStats":{"closed":0,"open":1,"total":1},"fullWidth":true,"hasGatedAccess":true,"hasFullAccess":true,"isEmbedded":false,"savedQueries":{"community":[],"user":[]}}">
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Generate the Verilog code corresponding to this FIRRTL code module BoomRAS :
input clock : Clock
input reset : Reset
output io : { flip read_idx : UInt<5>, read_addr : UInt<40>, flip write_valid : UInt<1>, flip write_idx : UInt<5>, flip write_addr : UInt<40>}
reg ras : UInt<40>[32], clock
node _io_read_addr_T = eq(io.write_idx, io.read_idx)
node _io_read_addr_T_1 = and(io.write_valid, _io_read_addr_T)
reg io_read_addr_REG : UInt<1>, clock
connect io_read_addr_REG, _io_read_addr_T_1
reg io_read_addr_REG_1 : UInt, clock
connect io_read_addr_REG_1, io.write_addr
reg io_read_addr_REG_2 : UInt, clock
connect io_read_addr_REG_2, ras[io.read_idx]
node _io_read_addr_T_2 = mux(io_read_addr_REG, io_read_addr_REG_1, io_read_addr_REG_2)
connect io.read_addr, _io_read_addr_T_2
when io.write_valid :
connect ras[io.write_idx], io.write_addr | module BoomRAS( // @[ras.scala:25:7]
input clock, // @[ras.scala:25:7]
input reset, // @[ras.scala:25:7]
input [4:0] io_read_idx, // @[ras.scala:27:14]
output [39:0] io_read_addr, // @[ras.scala:27:14]
input io_write_valid, // @[ras.scala:27:14]
input [4:0] io_write_idx, // @[ras.scala:27:14]
input [39:0] io_write_addr // @[ras.scala:27:14]
);
wire [4:0] io_read_idx_0 = io_read_idx; // @[ras.scala:25:7]
wire io_write_valid_0 = io_write_valid; // @[ras.scala:25:7]
wire [4:0] io_write_idx_0 = io_write_idx; // @[ras.scala:25:7]
wire [39:0] io_write_addr_0 = io_write_addr; // @[ras.scala:25:7]
wire [39:0] _io_read_addr_T_2; // @[ras.scala:37:22]
wire [39:0] io_read_addr_0; // @[ras.scala:25:7]
reg [39:0] ras_0; // @[ras.scala:35:16]
reg [39:0] ras_1; // @[ras.scala:35:16]
reg [39:0] ras_2; // @[ras.scala:35:16]
reg [39:0] ras_3; // @[ras.scala:35:16]
reg [39:0] ras_4; // @[ras.scala:35:16]
reg [39:0] ras_5; // @[ras.scala:35:16]
reg [39:0] ras_6; // @[ras.scala:35:16]
reg [39:0] ras_7; // @[ras.scala:35:16]
reg [39:0] ras_8; // @[ras.scala:35:16]
reg [39:0] ras_9; // @[ras.scala:35:16]
reg [39:0] ras_10; // @[ras.scala:35:16]
reg [39:0] ras_11; // @[ras.scala:35:16]
reg [39:0] ras_12; // @[ras.scala:35:16]
reg [39:0] ras_13; // @[ras.scala:35:16]
reg [39:0] ras_14; // @[ras.scala:35:16]
reg [39:0] ras_15; // @[ras.scala:35:16]
reg [39:0] ras_16; // @[ras.scala:35:16]
reg [39:0] ras_17; // @[ras.scala:35:16]
reg [39:0] ras_18; // @[ras.scala:35:16]
reg [39:0] ras_19; // @[ras.scala:35:16]
reg [39:0] ras_20; // @[ras.scala:35:16]
reg [39:0] ras_21; // @[ras.scala:35:16]
reg [39:0] ras_22; // @[ras.scala:35:16]
reg [39:0] ras_23; // @[ras.scala:35:16]
reg [39:0] ras_24; // @[ras.scala:35:16]
reg [39:0] ras_25; // @[ras.scala:35:16]
reg [39:0] ras_26; // @[ras.scala:35:16]
reg [39:0] ras_27; // @[ras.scala:35:16]
reg [39:0] ras_28; // @[ras.scala:35:16]
reg [39:0] ras_29; // @[ras.scala:35:16]
reg [39:0] ras_30; // @[ras.scala:35:16]
reg [39:0] ras_31; // @[ras.scala:35:16]
wire _io_read_addr_T = io_write_idx_0 == io_read_idx_0; // @[ras.scala:25:7, :37:62]
wire _io_read_addr_T_1 = io_write_valid_0 & _io_read_addr_T; // @[ras.scala:25:7, :37:{46,62}]
reg io_read_addr_REG; // @[ras.scala:37:30]
reg [39:0] io_read_addr_REG_1; // @[ras.scala:38:12]
reg [39:0] io_read_addr_REG_2; // @[ras.scala:39:12]
assign _io_read_addr_T_2 = io_read_addr_REG ? io_read_addr_REG_1 : io_read_addr_REG_2; // @[ras.scala:37:{22,30}, :38:12, :39:12]
assign io_read_addr_0 = _io_read_addr_T_2; // @[ras.scala:25:7, :37:22]
wire [31:0][39:0] _GEN = {{ras_31}, {ras_30}, {ras_29}, {ras_28}, {ras_27}, {ras_26}, {ras_25}, {ras_24}, {ras_23}, {ras_22}, {ras_21}, {ras_20}, {ras_19}, {ras_18}, {ras_17}, {ras_16}, {ras_15}, {ras_14}, {ras_13}, {ras_12}, {ras_11}, {ras_10}, {ras_9}, {ras_8}, {ras_7}, {ras_6}, {ras_5}, {ras_4}, {ras_3}, {ras_2}, {ras_1}, {ras_0}}; // @[ras.scala:35:16, :39:12]
always @(posedge clock) begin // @[ras.scala:25:7]
if (io_write_valid_0 & io_write_idx_0 == 5'h0) // @[ras.scala:25:7, :35:16, :41:25, :42:23]
ras_0 <= io_write_addr_0; // @[ras.scala:25:7, :35:16]
if (io_write_valid_0 & io_write_idx_0 == 5'h1) // @[ras.scala:25:7, :35:16, :41:25, :42:23]
ras_1 <= io_write_addr_0; // @[ras.scala:25:7, :35:16]
if (io_write_valid_0 & io_write_idx_0 == 5'h2) // @[ras.scala:25:7, :35:16, :41:25, :42:23]
ras_2 <= io_write_addr_0; // @[ras.scala:25:7, :35:16]
if (io_write_valid_0 & io_write_idx_0 == 5'h3) // @[ras.scala:25:7, :35:16, :41:25, :42:23]
ras_3 <= io_write_addr_0; // @[ras.scala:25:7, :35:16]
if (io_write_valid_0 & io_write_idx_0 == 5'h4) // @[ras.scala:25:7, :35:16, :41:25, :42:23]
ras_4 <= io_write_addr_0; // @[ras.scala:25:7, :35:16]
if (io_write_valid_0 & io_write_idx_0 == 5'h5) // @[ras.scala:25:7, :35:16, :41:25, :42:23]
ras_5 <= io_write_addr_0; // @[ras.scala:25:7, :35:16]
if (io_write_valid_0 & io_write_idx_0 == 5'h6) // @[ras.scala:25:7, :35:16, :41:25, :42:23]
ras_6 <= io_write_addr_0; // @[ras.scala:25:7, :35:16]
if (io_write_valid_0 & io_write_idx_0 == 5'h7) // @[ras.scala:25:7, :35:16, :41:25, :42:23]
ras_7 <= io_write_addr_0; // @[ras.scala:25:7, :35:16]
if (io_write_valid_0 & io_write_idx_0 == 5'h8) // @[ras.scala:25:7, :35:16, :41:25, :42:23]
ras_8 <= io_write_addr_0; // @[ras.scala:25:7, :35:16]
if (io_write_valid_0 & io_write_idx_0 == 5'h9) // @[ras.scala:25:7, :35:16, :41:25, :42:23]
ras_9 <= io_write_addr_0; // @[ras.scala:25:7, :35:16]
if (io_write_valid_0 & io_write_idx_0 == 5'hA) // @[ras.scala:25:7, :35:16, :41:25, :42:23]
ras_10 <= io_write_addr_0; // @[ras.scala:25:7, :35:16]
if (io_write_valid_0 & io_write_idx_0 == 5'hB) // @[ras.scala:25:7, :35:16, :41:25, :42:23]
ras_11 <= io_write_addr_0; // @[ras.scala:25:7, :35:16]
if (io_write_valid_0 & io_write_idx_0 == 5'hC) // @[ras.scala:25:7, :35:16, :41:25, :42:23]
ras_12 <= io_write_addr_0; // @[ras.scala:25:7, :35:16]
if (io_write_valid_0 & io_write_idx_0 == 5'hD) // @[ras.scala:25:7, :35:16, :41:25, :42:23]
ras_13 <= io_write_addr_0; // @[ras.scala:25:7, :35:16]
if (io_write_valid_0 & io_write_idx_0 == 5'hE) // @[ras.scala:25:7, :35:16, :41:25, :42:23]
ras_14 <= io_write_addr_0; // @[ras.scala:25:7, :35:16]
if (io_write_valid_0 & io_write_idx_0 == 5'hF) // @[ras.scala:25:7, :35:16, :41:25, :42:23]
ras_15 <= io_write_addr_0; // @[ras.scala:25:7, :35:16]
if (io_write_valid_0 & io_write_idx_0 == 5'h10) // @[ras.scala:25:7, :35:16, :41:25, :42:23]
ras_16 <= io_write_addr_0; // @[ras.scala:25:7, :35:16]
if (io_write_valid_0 & io_write_idx_0 == 5'h11) // @[ras.scala:25:7, :35:16, :41:25, :42:23]
ras_17 <= io_write_addr_0; // @[ras.scala:25:7, :35:16]
if (io_write_valid_0 & io_write_idx_0 == 5'h12) // @[ras.scala:25:7, :35:16, :41:25, :42:23]
ras_18 <= io_write_addr_0; // @[ras.scala:25:7, :35:16]
if (io_write_valid_0 & io_write_idx_0 == 5'h13) // @[ras.scala:25:7, :35:16, :41:25, :42:23]
ras_19 <= io_write_addr_0; // @[ras.scala:25:7, :35:16]
if (io_write_valid_0 & io_write_idx_0 == 5'h14) // @[ras.scala:25:7, :35:16, :41:25, :42:23]
ras_20 <= io_write_addr_0; // @[ras.scala:25:7, :35:16]
if (io_write_valid_0 & io_write_idx_0 == 5'h15) // @[ras.scala:25:7, :35:16, :41:25, :42:23]
ras_21 <= io_write_addr_0; // @[ras.scala:25:7, :35:16]
if (io_write_valid_0 & io_write_idx_0 == 5'h16) // @[ras.scala:25:7, :35:16, :41:25, :42:23]
ras_22 <= io_write_addr_0; // @[ras.scala:25:7, :35:16]
if (io_write_valid_0 & io_write_idx_0 == 5'h17) // @[ras.scala:25:7, :35:16, :41:25, :42:23]
ras_23 <= io_write_addr_0; // @[ras.scala:25:7, :35:16]
if (io_write_valid_0 & io_write_idx_0 == 5'h18) // @[ras.scala:25:7, :35:16, :41:25, :42:23]
ras_24 <= io_write_addr_0; // @[ras.scala:25:7, :35:16]
if (io_write_valid_0 & io_write_idx_0 == 5'h19) // @[ras.scala:25:7, :35:16, :41:25, :42:23]
ras_25 <= io_write_addr_0; // @[ras.scala:25:7, :35:16]
if (io_write_valid_0 & io_write_idx_0 == 5'h1A) // @[ras.scala:25:7, :35:16, :41:25, :42:23]
ras_26 <= io_write_addr_0; // @[ras.scala:25:7, :35:16]
if (io_write_valid_0 & io_write_idx_0 == 5'h1B) // @[ras.scala:25:7, :35:16, :41:25, :42:23]
ras_27 <= io_write_addr_0; // @[ras.scala:25:7, :35:16]
if (io_write_valid_0 & io_write_idx_0 == 5'h1C) // @[ras.scala:25:7, :35:16, :41:25, :42:23]
ras_28 <= io_write_addr_0; // @[ras.scala:25:7, :35:16]
if (io_write_valid_0 & io_write_idx_0 == 5'h1D) // @[ras.scala:25:7, :35:16, :41:25, :42:23]
ras_29 <= io_write_addr_0; // @[ras.scala:25:7, :35:16]
if (io_write_valid_0 & io_write_idx_0 == 5'h1E) // @[ras.scala:25:7, :35:16, :41:25, :42:23]
ras_30 <= io_write_addr_0; // @[ras.scala:25:7, :35:16]
if (io_write_valid_0 & (&io_write_idx_0)) // @[ras.scala:25:7, :35:16, :41:25, :42:23]
ras_31 <= io_write_addr_0; // @[ras.scala:25:7, :35:16]
io_read_addr_REG <= _io_read_addr_T_1; // @[ras.scala:37:{30,46}]
io_read_addr_REG_1 <= io_write_addr_0; // @[ras.scala:25:7, :38:12]
io_read_addr_REG_2 <= _GEN[io_read_idx_0]; // @[ras.scala:25:7, :39:12]
always @(posedge)
assign io_read_addr = io_read_addr_0; // @[ras.scala:25:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module HellaCacheArbiter_2 :
input clock : Clock
input reset : Reset
output io : { flip requestor : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}[2], mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}}
reg s1_id : UInt, clock
reg s2_id : UInt, clock
connect s2_id, s1_id
node _io_mem_keep_clock_enabled_T = or(io.requestor[0].keep_clock_enabled, io.requestor[1].keep_clock_enabled)
connect io.mem.keep_clock_enabled, _io_mem_keep_clock_enabled_T
node _io_mem_req_valid_T = or(io.requestor[0].req.valid, io.requestor[1].req.valid)
connect io.mem.req.valid, _io_mem_req_valid_T
connect io.requestor[0].req.ready, io.mem.req.ready
node _io_requestor_1_req_ready_T = eq(io.requestor[0].req.valid, UInt<1>(0h0))
node _io_requestor_1_req_ready_T_1 = and(io.requestor[0].req.ready, _io_requestor_1_req_ready_T)
connect io.requestor[1].req.ready, _io_requestor_1_req_ready_T_1
connect io.mem.req.bits, io.requestor[1].req.bits
node _io_mem_req_bits_tag_T = cat(io.requestor[1].req.bits.tag, UInt<1>(0h1))
connect io.mem.req.bits.tag, _io_mem_req_bits_tag_T
connect s1_id, UInt<1>(0h1)
connect io.mem.s1_kill, io.requestor[1].s1_kill
connect io.mem.s1_data, io.requestor[1].s1_data
connect io.mem.s2_kill, io.requestor[1].s2_kill
when io.requestor[0].req.valid :
connect io.mem.req.bits, io.requestor[0].req.bits
node _io_mem_req_bits_tag_T_1 = cat(io.requestor[0].req.bits.tag, UInt<1>(0h0))
connect io.mem.req.bits.tag, _io_mem_req_bits_tag_T_1
connect s1_id, UInt<1>(0h0)
node _T = eq(s1_id, UInt<1>(0h0))
when _T :
connect io.mem.s1_kill, io.requestor[0].s1_kill
connect io.mem.s1_data, io.requestor[0].s1_data
node _T_1 = eq(s2_id, UInt<1>(0h0))
when _T_1 :
connect io.mem.s2_kill, io.requestor[0].s2_kill
node _tag_hit_T = bits(io.mem.resp.bits.tag, 0, 0)
node tag_hit = eq(_tag_hit_T, UInt<1>(0h0))
node _io_requestor_0_resp_valid_T = and(io.mem.resp.valid, tag_hit)
connect io.requestor[0].resp.valid, _io_requestor_0_resp_valid_T
connect io.requestor[0].s2_xcpt, io.mem.s2_xcpt
connect io.requestor[0].s2_gpa, io.mem.s2_gpa
connect io.requestor[0].s2_gpa_is_pte, io.mem.s2_gpa_is_pte
connect io.requestor[0].ordered, io.mem.ordered
connect io.requestor[0].store_pending, io.mem.store_pending
connect io.requestor[0].perf, io.mem.perf
node _io_requestor_0_s2_nack_T = eq(s2_id, UInt<1>(0h0))
node _io_requestor_0_s2_nack_T_1 = and(io.mem.s2_nack, _io_requestor_0_s2_nack_T)
connect io.requestor[0].s2_nack, _io_requestor_0_s2_nack_T_1
connect io.requestor[0].s2_nack_cause_raw, io.mem.s2_nack_cause_raw
connect io.requestor[0].s2_uncached, io.mem.s2_uncached
connect io.requestor[0].s2_paddr, io.mem.s2_paddr
connect io.requestor[0].clock_enabled, io.mem.clock_enabled
connect io.requestor[0].resp.bits, io.mem.resp.bits
node _io_requestor_0_resp_bits_tag_T = shr(io.mem.resp.bits.tag, 1)
connect io.requestor[0].resp.bits.tag, _io_requestor_0_resp_bits_tag_T
connect io.requestor[0].replay_next, io.mem.replay_next
node _tag_hit_T_1 = bits(io.mem.resp.bits.tag, 0, 0)
node tag_hit_1 = eq(_tag_hit_T_1, UInt<1>(0h1))
node _io_requestor_1_resp_valid_T = and(io.mem.resp.valid, tag_hit_1)
connect io.requestor[1].resp.valid, _io_requestor_1_resp_valid_T
connect io.requestor[1].s2_xcpt, io.mem.s2_xcpt
connect io.requestor[1].s2_gpa, io.mem.s2_gpa
connect io.requestor[1].s2_gpa_is_pte, io.mem.s2_gpa_is_pte
connect io.requestor[1].ordered, io.mem.ordered
connect io.requestor[1].store_pending, io.mem.store_pending
connect io.requestor[1].perf, io.mem.perf
node _io_requestor_1_s2_nack_T = eq(s2_id, UInt<1>(0h1))
node _io_requestor_1_s2_nack_T_1 = and(io.mem.s2_nack, _io_requestor_1_s2_nack_T)
connect io.requestor[1].s2_nack, _io_requestor_1_s2_nack_T_1
connect io.requestor[1].s2_nack_cause_raw, io.mem.s2_nack_cause_raw
connect io.requestor[1].s2_uncached, io.mem.s2_uncached
connect io.requestor[1].s2_paddr, io.mem.s2_paddr
connect io.requestor[1].clock_enabled, io.mem.clock_enabled
connect io.requestor[1].resp.bits, io.mem.resp.bits
node _io_requestor_1_resp_bits_tag_T = shr(io.mem.resp.bits.tag, 1)
connect io.requestor[1].resp.bits.tag, _io_requestor_1_resp_bits_tag_T
connect io.requestor[1].replay_next, io.mem.replay_next | module HellaCacheArbiter_2( // @[HellaCacheArbiter.scala:10:7]
input clock, // @[HellaCacheArbiter.scala:10:7]
input reset, // @[HellaCacheArbiter.scala:10:7]
output io_requestor_0_req_ready, // @[HellaCacheArbiter.scala:12:14]
input io_requestor_0_req_valid, // @[HellaCacheArbiter.scala:12:14]
input [39:0] io_requestor_0_req_bits_addr, // @[HellaCacheArbiter.scala:12:14]
input io_requestor_0_req_bits_dv, // @[HellaCacheArbiter.scala:12:14]
input io_requestor_0_s1_kill, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_s2_nack, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_s2_uncached, // @[HellaCacheArbiter.scala:12:14]
output [31:0] io_requestor_0_s2_paddr, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_resp_valid, // @[HellaCacheArbiter.scala:12:14]
output [39:0] io_requestor_0_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14]
output [6:0] io_requestor_0_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14]
output [4:0] io_requestor_0_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14]
output [1:0] io_requestor_0_resp_bits_size, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14]
output [1:0] io_requestor_0_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14]
output [63:0] io_requestor_0_resp_bits_data, // @[HellaCacheArbiter.scala:12:14]
output [7:0] io_requestor_0_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14]
output [63:0] io_requestor_0_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14]
output [63:0] io_requestor_0_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14]
output [63:0] io_requestor_0_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_replay_next, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14]
output [39:0] io_requestor_0_s2_gpa, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_ordered, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_store_pending, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_perf_acquire, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_perf_release, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_perf_grant, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_perf_tlbMiss, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_perf_blocked, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_0_perf_storeBufferEmptyAfterStore, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_req_ready, // @[HellaCacheArbiter.scala:12:14]
input io_requestor_1_req_valid, // @[HellaCacheArbiter.scala:12:14]
input [39:0] io_requestor_1_req_bits_addr, // @[HellaCacheArbiter.scala:12:14]
input [6:0] io_requestor_1_req_bits_tag, // @[HellaCacheArbiter.scala:12:14]
input [4:0] io_requestor_1_req_bits_cmd, // @[HellaCacheArbiter.scala:12:14]
input [1:0] io_requestor_1_req_bits_size, // @[HellaCacheArbiter.scala:12:14]
input io_requestor_1_req_bits_signed, // @[HellaCacheArbiter.scala:12:14]
input [1:0] io_requestor_1_req_bits_dprv, // @[HellaCacheArbiter.scala:12:14]
input io_requestor_1_req_bits_dv, // @[HellaCacheArbiter.scala:12:14]
input io_requestor_1_req_bits_no_resp, // @[HellaCacheArbiter.scala:12:14]
input io_requestor_1_s1_kill, // @[HellaCacheArbiter.scala:12:14]
input [63:0] io_requestor_1_s1_data_data, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_s2_nack, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_s2_uncached, // @[HellaCacheArbiter.scala:12:14]
output [31:0] io_requestor_1_s2_paddr, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_resp_valid, // @[HellaCacheArbiter.scala:12:14]
output [39:0] io_requestor_1_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14]
output [6:0] io_requestor_1_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14]
output [4:0] io_requestor_1_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14]
output [1:0] io_requestor_1_resp_bits_size, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14]
output [1:0] io_requestor_1_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14]
output [63:0] io_requestor_1_resp_bits_data, // @[HellaCacheArbiter.scala:12:14]
output [7:0] io_requestor_1_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14]
output [63:0] io_requestor_1_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14]
output [63:0] io_requestor_1_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14]
output [63:0] io_requestor_1_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_replay_next, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14]
output [39:0] io_requestor_1_s2_gpa, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_ordered, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_store_pending, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_perf_acquire, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_perf_release, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_perf_grant, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_perf_tlbMiss, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_perf_blocked, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14]
output io_requestor_1_perf_storeBufferEmptyAfterStore, // @[HellaCacheArbiter.scala:12:14]
input io_requestor_1_keep_clock_enabled, // @[HellaCacheArbiter.scala:12:14]
input io_mem_req_ready, // @[HellaCacheArbiter.scala:12:14]
output io_mem_req_valid, // @[HellaCacheArbiter.scala:12:14]
output [39:0] io_mem_req_bits_addr, // @[HellaCacheArbiter.scala:12:14]
output [6:0] io_mem_req_bits_tag, // @[HellaCacheArbiter.scala:12:14]
output [4:0] io_mem_req_bits_cmd, // @[HellaCacheArbiter.scala:12:14]
output [1:0] io_mem_req_bits_size, // @[HellaCacheArbiter.scala:12:14]
output io_mem_req_bits_signed, // @[HellaCacheArbiter.scala:12:14]
output [1:0] io_mem_req_bits_dprv, // @[HellaCacheArbiter.scala:12:14]
output io_mem_req_bits_dv, // @[HellaCacheArbiter.scala:12:14]
output io_mem_req_bits_phys, // @[HellaCacheArbiter.scala:12:14]
output io_mem_req_bits_no_resp, // @[HellaCacheArbiter.scala:12:14]
output io_mem_s1_kill, // @[HellaCacheArbiter.scala:12:14]
output [63:0] io_mem_s1_data_data, // @[HellaCacheArbiter.scala:12:14]
input io_mem_s2_nack, // @[HellaCacheArbiter.scala:12:14]
input io_mem_s2_nack_cause_raw, // @[HellaCacheArbiter.scala:12:14]
input io_mem_s2_uncached, // @[HellaCacheArbiter.scala:12:14]
input [31:0] io_mem_s2_paddr, // @[HellaCacheArbiter.scala:12:14]
input io_mem_resp_valid, // @[HellaCacheArbiter.scala:12:14]
input [39:0] io_mem_resp_bits_addr, // @[HellaCacheArbiter.scala:12:14]
input [6:0] io_mem_resp_bits_tag, // @[HellaCacheArbiter.scala:12:14]
input [4:0] io_mem_resp_bits_cmd, // @[HellaCacheArbiter.scala:12:14]
input [1:0] io_mem_resp_bits_size, // @[HellaCacheArbiter.scala:12:14]
input io_mem_resp_bits_signed, // @[HellaCacheArbiter.scala:12:14]
input [1:0] io_mem_resp_bits_dprv, // @[HellaCacheArbiter.scala:12:14]
input io_mem_resp_bits_dv, // @[HellaCacheArbiter.scala:12:14]
input [63:0] io_mem_resp_bits_data, // @[HellaCacheArbiter.scala:12:14]
input [7:0] io_mem_resp_bits_mask, // @[HellaCacheArbiter.scala:12:14]
input io_mem_resp_bits_replay, // @[HellaCacheArbiter.scala:12:14]
input io_mem_resp_bits_has_data, // @[HellaCacheArbiter.scala:12:14]
input [63:0] io_mem_resp_bits_data_word_bypass, // @[HellaCacheArbiter.scala:12:14]
input [63:0] io_mem_resp_bits_data_raw, // @[HellaCacheArbiter.scala:12:14]
input [63:0] io_mem_resp_bits_store_data, // @[HellaCacheArbiter.scala:12:14]
input io_mem_replay_next, // @[HellaCacheArbiter.scala:12:14]
input io_mem_s2_xcpt_ma_ld, // @[HellaCacheArbiter.scala:12:14]
input io_mem_s2_xcpt_ma_st, // @[HellaCacheArbiter.scala:12:14]
input io_mem_s2_xcpt_pf_ld, // @[HellaCacheArbiter.scala:12:14]
input io_mem_s2_xcpt_pf_st, // @[HellaCacheArbiter.scala:12:14]
input io_mem_s2_xcpt_ae_ld, // @[HellaCacheArbiter.scala:12:14]
input io_mem_s2_xcpt_ae_st, // @[HellaCacheArbiter.scala:12:14]
input [39:0] io_mem_s2_gpa, // @[HellaCacheArbiter.scala:12:14]
input io_mem_ordered, // @[HellaCacheArbiter.scala:12:14]
input io_mem_store_pending, // @[HellaCacheArbiter.scala:12:14]
input io_mem_perf_acquire, // @[HellaCacheArbiter.scala:12:14]
input io_mem_perf_release, // @[HellaCacheArbiter.scala:12:14]
input io_mem_perf_grant, // @[HellaCacheArbiter.scala:12:14]
input io_mem_perf_tlbMiss, // @[HellaCacheArbiter.scala:12:14]
input io_mem_perf_blocked, // @[HellaCacheArbiter.scala:12:14]
input io_mem_perf_canAcceptStoreThenLoad, // @[HellaCacheArbiter.scala:12:14]
input io_mem_perf_canAcceptStoreThenRMW, // @[HellaCacheArbiter.scala:12:14]
input io_mem_perf_canAcceptLoadThenLoad, // @[HellaCacheArbiter.scala:12:14]
input io_mem_perf_storeBufferEmptyAfterLoad, // @[HellaCacheArbiter.scala:12:14]
input io_mem_perf_storeBufferEmptyAfterStore, // @[HellaCacheArbiter.scala:12:14]
output io_mem_keep_clock_enabled // @[HellaCacheArbiter.scala:12:14]
);
wire io_requestor_0_req_valid_0 = io_requestor_0_req_valid; // @[HellaCacheArbiter.scala:10:7]
wire [39:0] io_requestor_0_req_bits_addr_0 = io_requestor_0_req_bits_addr; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_req_bits_dv_0 = io_requestor_0_req_bits_dv; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s1_kill_0 = io_requestor_0_s1_kill; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_req_valid_0 = io_requestor_1_req_valid; // @[HellaCacheArbiter.scala:10:7]
wire [39:0] io_requestor_1_req_bits_addr_0 = io_requestor_1_req_bits_addr; // @[HellaCacheArbiter.scala:10:7]
wire [6:0] io_requestor_1_req_bits_tag_0 = io_requestor_1_req_bits_tag; // @[HellaCacheArbiter.scala:10:7]
wire [4:0] io_requestor_1_req_bits_cmd_0 = io_requestor_1_req_bits_cmd; // @[HellaCacheArbiter.scala:10:7]
wire [1:0] io_requestor_1_req_bits_size_0 = io_requestor_1_req_bits_size; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_req_bits_signed_0 = io_requestor_1_req_bits_signed; // @[HellaCacheArbiter.scala:10:7]
wire [1:0] io_requestor_1_req_bits_dprv_0 = io_requestor_1_req_bits_dprv; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_req_bits_dv_0 = io_requestor_1_req_bits_dv; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_req_bits_no_resp_0 = io_requestor_1_req_bits_no_resp; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_s1_kill_0 = io_requestor_1_s1_kill; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_requestor_1_s1_data_data_0 = io_requestor_1_s1_data_data; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_keep_clock_enabled_0 = io_requestor_1_keep_clock_enabled; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_req_ready_0 = io_mem_req_ready; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_nack_0 = io_mem_s2_nack; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_uncached_0 = io_mem_s2_uncached; // @[HellaCacheArbiter.scala:10:7]
wire [31:0] io_mem_s2_paddr_0 = io_mem_s2_paddr; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[HellaCacheArbiter.scala:10:7]
wire [39:0] io_mem_resp_bits_addr_0 = io_mem_resp_bits_addr; // @[HellaCacheArbiter.scala:10:7]
wire [6:0] io_mem_resp_bits_tag_0 = io_mem_resp_bits_tag; // @[HellaCacheArbiter.scala:10:7]
wire [4:0] io_mem_resp_bits_cmd_0 = io_mem_resp_bits_cmd; // @[HellaCacheArbiter.scala:10:7]
wire [1:0] io_mem_resp_bits_size_0 = io_mem_resp_bits_size; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_resp_bits_signed_0 = io_mem_resp_bits_signed; // @[HellaCacheArbiter.scala:10:7]
wire [1:0] io_mem_resp_bits_dprv_0 = io_mem_resp_bits_dprv; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_resp_bits_dv_0 = io_mem_resp_bits_dv; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[HellaCacheArbiter.scala:10:7]
wire [7:0] io_mem_resp_bits_mask_0 = io_mem_resp_bits_mask; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_resp_bits_replay_0 = io_mem_resp_bits_replay; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_resp_bits_has_data_0 = io_mem_resp_bits_has_data; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_mem_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_mem_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_mem_resp_bits_store_data_0 = io_mem_resp_bits_store_data; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_replay_next_0 = io_mem_replay_next; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st; // @[HellaCacheArbiter.scala:10:7]
wire [39:0] io_mem_s2_gpa_0 = io_mem_s2_gpa; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_ordered_0 = io_mem_ordered; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_store_pending_0 = io_mem_store_pending; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_perf_acquire_0 = io_mem_perf_acquire; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_perf_release_0 = io_mem_perf_release; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_perf_grant_0 = io_mem_perf_grant; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_perf_tlbMiss_0 = io_mem_perf_tlbMiss; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_perf_blocked_0 = io_mem_perf_blocked; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore; // @[HellaCacheArbiter.scala:10:7]
wire [7:0] io_requestor_0_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :34:35, :39:24, :50:26, :51:30]
wire [7:0] io_requestor_0_s1_data_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :34:35, :39:24, :50:26, :51:30]
wire [7:0] io_requestor_1_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :34:35, :39:24, :50:26, :51:30]
wire [7:0] io_requestor_1_s1_data_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :34:35, :39:24, :50:26, :51:30]
wire [7:0] io_mem_req_bits_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :34:35, :39:24, :50:26, :51:30]
wire [7:0] io_mem_s1_data_mask = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :34:35, :39:24, :50:26, :51:30]
wire [7:0] _io_mem_req_bits_tag_T_1 = 8'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :34:35, :39:24, :50:26, :51:30]
wire [63:0] io_requestor_0_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26]
wire [63:0] io_requestor_0_s1_data_data = 64'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26]
wire [63:0] io_requestor_1_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26]
wire [63:0] io_mem_req_bits_data = 64'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26]
wire [1:0] io_requestor_0_req_bits_dprv = 2'h1; // @[HellaCacheArbiter.scala:10:7, :12:14]
wire [1:0] io_requestor_0_req_bits_size = 2'h3; // @[HellaCacheArbiter.scala:10:7, :12:14]
wire [4:0] io_requestor_0_req_bits_cmd = 5'h0; // @[HellaCacheArbiter.scala:10:7, :12:14]
wire [6:0] io_requestor_0_req_bits_tag = 7'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :34:29]
wire io_requestor_0_req_bits_phys = 1'h1; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_clock_enabled = 1'h1; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_req_bits_signed = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_req_bits_no_resp = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_req_bits_no_xcpt = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_keep_clock_enabled = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_req_bits_phys = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_req_bits_no_xcpt = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_req_bits_no_alloc = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_req_bits_no_xcpt = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_kill = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_xcpt_gf_ld = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_xcpt_gf_st = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s2_gpa_is_pte = 1'h0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_req_bits_phys_0 = io_requestor_0_req_valid_0; // @[HellaCacheArbiter.scala:10:7]
wire _io_requestor_0_s2_nack_T_1; // @[HellaCacheArbiter.scala:68:49]
wire _io_requestor_0_resp_valid_T; // @[HellaCacheArbiter.scala:61:39]
wire _io_requestor_1_req_ready_T_1; // @[HellaCacheArbiter.scala:28:64]
wire _io_requestor_1_s2_nack_T_1; // @[HellaCacheArbiter.scala:68:49]
wire _io_requestor_1_resp_valid_T; // @[HellaCacheArbiter.scala:61:39]
wire _io_mem_keep_clock_enabled_T = io_requestor_1_keep_clock_enabled_0; // @[HellaCacheArbiter.scala:10:7, :23:81]
wire io_requestor_0_req_ready_0 = io_mem_req_ready_0; // @[HellaCacheArbiter.scala:10:7]
wire _io_mem_req_valid_T; // @[HellaCacheArbiter.scala:25:63]
wire io_requestor_0_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_s2_nack_cause_raw_0 = io_mem_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_uncached_0 = io_mem_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_s2_uncached_0 = io_mem_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7]
wire [31:0] io_requestor_0_s2_paddr_0 = io_mem_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7]
wire [31:0] io_requestor_1_s2_paddr_0 = io_mem_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7]
wire [39:0] io_requestor_0_resp_bits_addr_0 = io_mem_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7]
wire [39:0] io_requestor_1_resp_bits_addr_0 = io_mem_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7]
wire [4:0] io_requestor_0_resp_bits_cmd_0 = io_mem_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7]
wire [4:0] io_requestor_1_resp_bits_cmd_0 = io_mem_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7]
wire [1:0] io_requestor_0_resp_bits_size_0 = io_mem_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7]
wire [1:0] io_requestor_1_resp_bits_size_0 = io_mem_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_resp_bits_signed_0 = io_mem_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_resp_bits_signed_0 = io_mem_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7]
wire [1:0] io_requestor_0_resp_bits_dprv_0 = io_mem_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7]
wire [1:0] io_requestor_1_resp_bits_dprv_0 = io_mem_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_resp_bits_dv_0 = io_mem_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_resp_bits_dv_0 = io_mem_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_requestor_0_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_requestor_1_resp_bits_data_0 = io_mem_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7]
wire [7:0] io_requestor_0_resp_bits_mask_0 = io_mem_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7]
wire [7:0] io_requestor_1_resp_bits_mask_0 = io_mem_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_resp_bits_replay_0 = io_mem_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_resp_bits_replay_0 = io_mem_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_resp_bits_has_data_0 = io_mem_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_resp_bits_has_data_0 = io_mem_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_requestor_0_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_requestor_1_resp_bits_data_word_bypass_0 = io_mem_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_requestor_0_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_requestor_1_resp_bits_data_raw_0 = io_mem_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_requestor_0_resp_bits_store_data_0 = io_mem_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_requestor_1_resp_bits_store_data_0 = io_mem_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_replay_next_0 = io_mem_replay_next_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_replay_next_0 = io_mem_replay_next_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_s2_xcpt_ma_ld_0 = io_mem_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_s2_xcpt_ma_st_0 = io_mem_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_s2_xcpt_pf_ld_0 = io_mem_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_s2_xcpt_pf_st_0 = io_mem_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_s2_xcpt_ae_ld_0 = io_mem_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_s2_xcpt_ae_st_0 = io_mem_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7]
wire [39:0] io_requestor_0_s2_gpa_0 = io_mem_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7]
wire [39:0] io_requestor_1_s2_gpa_0 = io_mem_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_ordered_0 = io_mem_ordered_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_ordered_0 = io_mem_ordered_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_store_pending_0 = io_mem_store_pending_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_store_pending_0 = io_mem_store_pending_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_perf_acquire_0 = io_mem_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_perf_acquire_0 = io_mem_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_perf_release_0 = io_mem_perf_release_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_perf_release_0 = io_mem_perf_release_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_perf_grant_0 = io_mem_perf_grant_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_perf_grant_0 = io_mem_perf_grant_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_perf_tlbMiss_0 = io_mem_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_perf_tlbMiss_0 = io_mem_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_perf_blocked_0 = io_mem_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_perf_blocked_0 = io_mem_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_perf_canAcceptStoreThenLoad_0 = io_mem_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_perf_canAcceptStoreThenRMW_0 = io_mem_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_perf_canAcceptLoadThenLoad_0 = io_mem_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_perf_storeBufferEmptyAfterLoad_0 = io_mem_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_perf_storeBufferEmptyAfterStore_0 = io_mem_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7]
wire [6:0] io_requestor_0_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_resp_valid_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_0_s2_nack_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_req_ready_0; // @[HellaCacheArbiter.scala:10:7]
wire [6:0] io_requestor_1_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_resp_valid_0; // @[HellaCacheArbiter.scala:10:7]
wire io_requestor_1_s2_nack_0; // @[HellaCacheArbiter.scala:10:7]
wire [39:0] io_mem_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7]
wire [6:0] io_mem_req_bits_tag_0; // @[HellaCacheArbiter.scala:10:7]
wire [4:0] io_mem_req_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7]
wire [1:0] io_mem_req_bits_size_0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_req_bits_signed_0; // @[HellaCacheArbiter.scala:10:7]
wire [1:0] io_mem_req_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_req_bits_no_resp_0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_req_valid_0; // @[HellaCacheArbiter.scala:10:7]
wire [63:0] io_mem_s1_data_data_0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_s1_kill_0; // @[HellaCacheArbiter.scala:10:7]
wire io_mem_keep_clock_enabled_0; // @[HellaCacheArbiter.scala:10:7]
reg s1_id; // @[HellaCacheArbiter.scala:20:20]
reg s2_id; // @[HellaCacheArbiter.scala:21:24]
wire _io_requestor_1_s2_nack_T = s2_id; // @[HellaCacheArbiter.scala:21:24, :68:58]
assign io_mem_keep_clock_enabled_0 = _io_mem_keep_clock_enabled_T; // @[HellaCacheArbiter.scala:10:7, :23:81]
assign _io_mem_req_valid_T = io_requestor_0_req_valid_0 | io_requestor_1_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :25:63]
assign io_mem_req_valid_0 = _io_mem_req_valid_T; // @[HellaCacheArbiter.scala:10:7, :25:63]
wire _io_requestor_1_req_ready_T = ~io_requestor_0_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :28:67]
assign _io_requestor_1_req_ready_T_1 = io_requestor_0_req_ready_0 & _io_requestor_1_req_ready_T; // @[HellaCacheArbiter.scala:10:7, :28:{64,67}]
assign io_requestor_1_req_ready_0 = _io_requestor_1_req_ready_T_1; // @[HellaCacheArbiter.scala:10:7, :28:64]
wire [7:0] _io_mem_req_bits_tag_T = {io_requestor_1_req_bits_tag_0, 1'h1}; // @[HellaCacheArbiter.scala:10:7, :34:35]
assign io_mem_req_bits_addr_0 = io_requestor_0_req_valid_0 ? io_requestor_0_req_bits_addr_0 : io_requestor_1_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26]
assign io_mem_req_bits_cmd_0 = io_requestor_0_req_valid_0 ? 5'h0 : io_requestor_1_req_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26]
assign io_mem_req_bits_size_0 = io_requestor_0_req_valid_0 ? 2'h3 : io_requestor_1_req_bits_size_0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26]
assign io_mem_req_bits_signed_0 = ~io_requestor_0_req_valid_0 & io_requestor_1_req_bits_signed_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26]
assign io_mem_req_bits_dprv_0 = io_requestor_0_req_valid_0 ? 2'h1 : io_requestor_1_req_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7, :12:14, :33:25, :50:26]
assign io_mem_req_bits_dv_0 = io_requestor_0_req_valid_0 ? io_requestor_0_req_bits_dv_0 : io_requestor_1_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26]
assign io_mem_req_bits_no_resp_0 = ~io_requestor_0_req_valid_0 & io_requestor_1_req_bits_no_resp_0; // @[HellaCacheArbiter.scala:10:7, :33:25, :50:26]
assign io_mem_req_bits_tag_0 = io_requestor_0_req_valid_0 ? 7'h0 : _io_mem_req_bits_tag_T[6:0]; // @[HellaCacheArbiter.scala:10:7, :12:14, :34:{29,35}, :50:26]
assign io_mem_s1_kill_0 = s1_id ? io_requestor_1_s1_kill_0 : io_requestor_0_s1_kill_0; // @[HellaCacheArbiter.scala:10:7, :20:20, :38:24, :51:30]
assign io_mem_s1_data_data_0 = s1_id ? io_requestor_1_s1_data_data_0 : 64'h0; // @[HellaCacheArbiter.scala:10:7, :12:14, :20:20, :33:25, :39:24, :50:26, :51:30]
wire _io_requestor_0_s2_nack_T = ~s2_id; // @[HellaCacheArbiter.scala:21:24, :52:21, :68:58]
wire _tag_hit_T = io_mem_resp_bits_tag_0[0]; // @[HellaCacheArbiter.scala:10:7, :60:41]
wire _tag_hit_T_1 = io_mem_resp_bits_tag_0[0]; // @[HellaCacheArbiter.scala:10:7, :60:41]
wire tag_hit = ~_tag_hit_T; // @[HellaCacheArbiter.scala:60:{41,57}]
assign _io_requestor_0_resp_valid_T = io_mem_resp_valid_0 & tag_hit; // @[HellaCacheArbiter.scala:10:7, :60:57, :61:39]
assign io_requestor_0_resp_valid_0 = _io_requestor_0_resp_valid_T; // @[HellaCacheArbiter.scala:10:7, :61:39]
assign _io_requestor_0_s2_nack_T_1 = io_mem_s2_nack_0 & _io_requestor_0_s2_nack_T; // @[HellaCacheArbiter.scala:10:7, :68:{49,58}]
assign io_requestor_0_s2_nack_0 = _io_requestor_0_s2_nack_T_1; // @[HellaCacheArbiter.scala:10:7, :68:49]
wire [5:0] _io_requestor_0_resp_bits_tag_T = io_mem_resp_bits_tag_0[6:1]; // @[HellaCacheArbiter.scala:10:7, :74:45]
wire [5:0] _io_requestor_1_resp_bits_tag_T = io_mem_resp_bits_tag_0[6:1]; // @[HellaCacheArbiter.scala:10:7, :74:45]
assign io_requestor_0_resp_bits_tag_0 = {1'h0, _io_requestor_0_resp_bits_tag_T}; // @[HellaCacheArbiter.scala:10:7, :74:{21,45}]
wire tag_hit_1 = _tag_hit_T_1; // @[HellaCacheArbiter.scala:60:{41,57}]
assign _io_requestor_1_resp_valid_T = io_mem_resp_valid_0 & tag_hit_1; // @[HellaCacheArbiter.scala:10:7, :60:57, :61:39]
assign io_requestor_1_resp_valid_0 = _io_requestor_1_resp_valid_T; // @[HellaCacheArbiter.scala:10:7, :61:39]
assign _io_requestor_1_s2_nack_T_1 = io_mem_s2_nack_0 & _io_requestor_1_s2_nack_T; // @[HellaCacheArbiter.scala:10:7, :68:{49,58}]
assign io_requestor_1_s2_nack_0 = _io_requestor_1_s2_nack_T_1; // @[HellaCacheArbiter.scala:10:7, :68:49]
assign io_requestor_1_resp_bits_tag_0 = {1'h0, _io_requestor_1_resp_bits_tag_T}; // @[HellaCacheArbiter.scala:10:7, :74:{21,45}]
always @(posedge clock) begin // @[HellaCacheArbiter.scala:10:7]
s1_id <= ~io_requestor_0_req_valid_0; // @[HellaCacheArbiter.scala:10:7, :20:20, :28:67]
s2_id <= s1_id; // @[HellaCacheArbiter.scala:20:20, :21:24]
always @(posedge)
assign io_requestor_0_req_ready = io_requestor_0_req_ready_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_s2_nack = io_requestor_0_s2_nack_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_s2_nack_cause_raw = io_requestor_0_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_s2_uncached = io_requestor_0_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_s2_paddr = io_requestor_0_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_valid = io_requestor_0_resp_valid_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_addr = io_requestor_0_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_tag = io_requestor_0_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_cmd = io_requestor_0_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_size = io_requestor_0_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_signed = io_requestor_0_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_dprv = io_requestor_0_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_dv = io_requestor_0_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_data = io_requestor_0_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_mask = io_requestor_0_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_replay = io_requestor_0_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_has_data = io_requestor_0_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_data_word_bypass = io_requestor_0_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_data_raw = io_requestor_0_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_resp_bits_store_data = io_requestor_0_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_replay_next = io_requestor_0_replay_next_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_s2_xcpt_ma_ld = io_requestor_0_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_s2_xcpt_ma_st = io_requestor_0_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_s2_xcpt_pf_ld = io_requestor_0_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_s2_xcpt_pf_st = io_requestor_0_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_s2_xcpt_ae_ld = io_requestor_0_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_s2_xcpt_ae_st = io_requestor_0_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_s2_gpa = io_requestor_0_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_ordered = io_requestor_0_ordered_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_store_pending = io_requestor_0_store_pending_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_perf_acquire = io_requestor_0_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_perf_release = io_requestor_0_perf_release_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_perf_grant = io_requestor_0_perf_grant_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_perf_tlbMiss = io_requestor_0_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_perf_blocked = io_requestor_0_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_perf_canAcceptStoreThenLoad = io_requestor_0_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_perf_canAcceptStoreThenRMW = io_requestor_0_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_perf_canAcceptLoadThenLoad = io_requestor_0_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_perf_storeBufferEmptyAfterLoad = io_requestor_0_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_0_perf_storeBufferEmptyAfterStore = io_requestor_0_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_req_ready = io_requestor_1_req_ready_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_s2_nack = io_requestor_1_s2_nack_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_s2_nack_cause_raw = io_requestor_1_s2_nack_cause_raw_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_s2_uncached = io_requestor_1_s2_uncached_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_s2_paddr = io_requestor_1_s2_paddr_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_resp_valid = io_requestor_1_resp_valid_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_resp_bits_addr = io_requestor_1_resp_bits_addr_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_resp_bits_tag = io_requestor_1_resp_bits_tag_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_resp_bits_cmd = io_requestor_1_resp_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_resp_bits_size = io_requestor_1_resp_bits_size_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_resp_bits_signed = io_requestor_1_resp_bits_signed_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_resp_bits_dprv = io_requestor_1_resp_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_resp_bits_dv = io_requestor_1_resp_bits_dv_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_resp_bits_data = io_requestor_1_resp_bits_data_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_resp_bits_mask = io_requestor_1_resp_bits_mask_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_resp_bits_replay = io_requestor_1_resp_bits_replay_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_resp_bits_has_data = io_requestor_1_resp_bits_has_data_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_resp_bits_data_word_bypass = io_requestor_1_resp_bits_data_word_bypass_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_resp_bits_data_raw = io_requestor_1_resp_bits_data_raw_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_resp_bits_store_data = io_requestor_1_resp_bits_store_data_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_replay_next = io_requestor_1_replay_next_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_s2_xcpt_ma_ld = io_requestor_1_s2_xcpt_ma_ld_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_s2_xcpt_ma_st = io_requestor_1_s2_xcpt_ma_st_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_s2_xcpt_pf_ld = io_requestor_1_s2_xcpt_pf_ld_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_s2_xcpt_pf_st = io_requestor_1_s2_xcpt_pf_st_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_s2_xcpt_ae_ld = io_requestor_1_s2_xcpt_ae_ld_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_s2_xcpt_ae_st = io_requestor_1_s2_xcpt_ae_st_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_s2_gpa = io_requestor_1_s2_gpa_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_ordered = io_requestor_1_ordered_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_store_pending = io_requestor_1_store_pending_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_perf_acquire = io_requestor_1_perf_acquire_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_perf_release = io_requestor_1_perf_release_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_perf_grant = io_requestor_1_perf_grant_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_perf_tlbMiss = io_requestor_1_perf_tlbMiss_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_perf_blocked = io_requestor_1_perf_blocked_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_perf_canAcceptStoreThenLoad = io_requestor_1_perf_canAcceptStoreThenLoad_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_perf_canAcceptStoreThenRMW = io_requestor_1_perf_canAcceptStoreThenRMW_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_perf_canAcceptLoadThenLoad = io_requestor_1_perf_canAcceptLoadThenLoad_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_perf_storeBufferEmptyAfterLoad = io_requestor_1_perf_storeBufferEmptyAfterLoad_0; // @[HellaCacheArbiter.scala:10:7]
assign io_requestor_1_perf_storeBufferEmptyAfterStore = io_requestor_1_perf_storeBufferEmptyAfterStore_0; // @[HellaCacheArbiter.scala:10:7]
assign io_mem_req_valid = io_mem_req_valid_0; // @[HellaCacheArbiter.scala:10:7]
assign io_mem_req_bits_addr = io_mem_req_bits_addr_0; // @[HellaCacheArbiter.scala:10:7]
assign io_mem_req_bits_tag = io_mem_req_bits_tag_0; // @[HellaCacheArbiter.scala:10:7]
assign io_mem_req_bits_cmd = io_mem_req_bits_cmd_0; // @[HellaCacheArbiter.scala:10:7]
assign io_mem_req_bits_size = io_mem_req_bits_size_0; // @[HellaCacheArbiter.scala:10:7]
assign io_mem_req_bits_signed = io_mem_req_bits_signed_0; // @[HellaCacheArbiter.scala:10:7]
assign io_mem_req_bits_dprv = io_mem_req_bits_dprv_0; // @[HellaCacheArbiter.scala:10:7]
assign io_mem_req_bits_dv = io_mem_req_bits_dv_0; // @[HellaCacheArbiter.scala:10:7]
assign io_mem_req_bits_phys = io_mem_req_bits_phys_0; // @[HellaCacheArbiter.scala:10:7]
assign io_mem_req_bits_no_resp = io_mem_req_bits_no_resp_0; // @[HellaCacheArbiter.scala:10:7]
assign io_mem_s1_kill = io_mem_s1_kill_0; // @[HellaCacheArbiter.scala:10:7]
assign io_mem_s1_data_data = io_mem_s1_data_data_0; // @[HellaCacheArbiter.scala:10:7]
assign io_mem_keep_clock_enabled = io_mem_keep_clock_enabled_0; // @[HellaCacheArbiter.scala:10:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_52 :
input clock : Clock
input reset : Reset
output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}}
regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff)
reg value_reg : { symbol : UInt<10>}, clock
connect io.output_prev.key, key_reg
connect io.output_prev.value, value_reg
connect io.output_nxt.key, key_reg
connect io.output_nxt.value, value_reg
connect io.cur_output_keyval.key, key_reg
connect io.cur_output_keyval.value, value_reg
when io.cmd.valid :
node _T = eq(UInt<1>(0h0), io.cmd.bits)
when _T :
connect key_reg, io.input_nxt.key
connect value_reg, io.input_nxt.value
else :
node _T_1 = eq(UInt<1>(0h1), io.cmd.bits)
when _T_1 :
when io.insert_here :
connect key_reg, io.cur_input_keyval.key
connect value_reg, io.cur_input_keyval.value
else :
node _T_2 = geq(key_reg, io.cur_input_keyval.key)
when _T_2 :
connect key_reg, io.input_prev.key
connect value_reg, io.input_prev.value
else :
skip | module PriorityQueueStage_52( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_133 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_225
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_133( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_225 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_28 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0)
node _source_ok_T_31 = shr(io.in.a.bits.source, 3)
node _source_ok_T_32 = eq(_source_ok_T_31, UInt<3>(0h6))
node _source_ok_T_33 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_34 = and(_source_ok_T_32, _source_ok_T_33)
node _source_ok_T_35 = leq(source_ok_uncommonBits_4, UInt<3>(0h4))
node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35)
node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 2, 0)
node _source_ok_T_39 = shr(io.in.a.bits.source, 3)
node _source_ok_T_40 = eq(_source_ok_T_39, UInt<3>(0h4))
node _source_ok_T_41 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41)
node _source_ok_T_43 = leq(source_ok_uncommonBits_5, UInt<3>(0h4))
node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43)
node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _source_ok_WIRE : UInt<1>[18]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_27
connect _source_ok_WIRE[8], _source_ok_T_28
connect _source_ok_WIRE[9], _source_ok_T_29
connect _source_ok_WIRE[10], _source_ok_T_30
connect _source_ok_WIRE[11], _source_ok_T_36
connect _source_ok_WIRE[12], _source_ok_T_37
connect _source_ok_WIRE[13], _source_ok_T_38
connect _source_ok_WIRE[14], _source_ok_T_44
connect _source_ok_WIRE[15], _source_ok_T_45
connect _source_ok_WIRE[16], _source_ok_T_46
connect _source_ok_WIRE[17], _source_ok_T_47
node _source_ok_T_48 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[2])
node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[3])
node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[4])
node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[5])
node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[6])
node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[7])
node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE[8])
node _source_ok_T_56 = or(_source_ok_T_55, _source_ok_WIRE[9])
node _source_ok_T_57 = or(_source_ok_T_56, _source_ok_WIRE[10])
node _source_ok_T_58 = or(_source_ok_T_57, _source_ok_WIRE[11])
node _source_ok_T_59 = or(_source_ok_T_58, _source_ok_WIRE[12])
node _source_ok_T_60 = or(_source_ok_T_59, _source_ok_WIRE[13])
node _source_ok_T_61 = or(_source_ok_T_60, _source_ok_WIRE[14])
node _source_ok_T_62 = or(_source_ok_T_61, _source_ok_WIRE[15])
node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[16])
node source_ok = or(_source_ok_T_63, _source_ok_WIRE[17])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_83 = cvt(_T_82)
node _T_84 = and(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = asSInt(_T_84)
node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = or(_T_81, _T_86)
node _T_88 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_89 = eq(_T_88, UInt<1>(0h0))
node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<1>(0h0)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_89, _T_94)
node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_99 = cvt(_T_98)
node _T_100 = and(_T_99, asSInt(UInt<1>(0h0)))
node _T_101 = asSInt(_T_100)
node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = or(_T_97, _T_102)
node _T_104 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _T_105 = eq(_T_104, UInt<1>(0h0))
node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_107 = cvt(_T_106)
node _T_108 = and(_T_107, asSInt(UInt<1>(0h0)))
node _T_109 = asSInt(_T_108)
node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = or(_T_105, _T_110)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0)
node _T_112 = shr(io.in.a.bits.source, 3)
node _T_113 = eq(_T_112, UInt<3>(0h6))
node _T_114 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_115 = and(_T_113, _T_114)
node _T_116 = leq(uncommonBits_4, UInt<3>(0h4))
node _T_117 = and(_T_115, _T_116)
node _T_118 = eq(_T_117, UInt<1>(0h0))
node _T_119 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_120 = cvt(_T_119)
node _T_121 = and(_T_120, asSInt(UInt<1>(0h0)))
node _T_122 = asSInt(_T_121)
node _T_123 = eq(_T_122, asSInt(UInt<1>(0h0)))
node _T_124 = or(_T_118, _T_123)
node _T_125 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_126 = eq(_T_125, UInt<1>(0h0))
node _T_127 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_128 = cvt(_T_127)
node _T_129 = and(_T_128, asSInt(UInt<1>(0h0)))
node _T_130 = asSInt(_T_129)
node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0)))
node _T_132 = or(_T_126, _T_131)
node _T_133 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _T_134 = eq(_T_133, UInt<1>(0h0))
node _T_135 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_136 = cvt(_T_135)
node _T_137 = and(_T_136, asSInt(UInt<1>(0h0)))
node _T_138 = asSInt(_T_137)
node _T_139 = eq(_T_138, asSInt(UInt<1>(0h0)))
node _T_140 = or(_T_134, _T_139)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 2, 0)
node _T_141 = shr(io.in.a.bits.source, 3)
node _T_142 = eq(_T_141, UInt<3>(0h4))
node _T_143 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_144 = and(_T_142, _T_143)
node _T_145 = leq(uncommonBits_5, UInt<3>(0h4))
node _T_146 = and(_T_144, _T_145)
node _T_147 = eq(_T_146, UInt<1>(0h0))
node _T_148 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_149 = cvt(_T_148)
node _T_150 = and(_T_149, asSInt(UInt<1>(0h0)))
node _T_151 = asSInt(_T_150)
node _T_152 = eq(_T_151, asSInt(UInt<1>(0h0)))
node _T_153 = or(_T_147, _T_152)
node _T_154 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_155 = eq(_T_154, UInt<1>(0h0))
node _T_156 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_157 = cvt(_T_156)
node _T_158 = and(_T_157, asSInt(UInt<1>(0h0)))
node _T_159 = asSInt(_T_158)
node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0)))
node _T_161 = or(_T_155, _T_160)
node _T_162 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_163 = eq(_T_162, UInt<1>(0h0))
node _T_164 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_165 = cvt(_T_164)
node _T_166 = and(_T_165, asSInt(UInt<1>(0h0)))
node _T_167 = asSInt(_T_166)
node _T_168 = eq(_T_167, asSInt(UInt<1>(0h0)))
node _T_169 = or(_T_163, _T_168)
node _T_170 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_171 = eq(_T_170, UInt<1>(0h0))
node _T_172 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_173 = cvt(_T_172)
node _T_174 = and(_T_173, asSInt(UInt<1>(0h0)))
node _T_175 = asSInt(_T_174)
node _T_176 = eq(_T_175, asSInt(UInt<1>(0h0)))
node _T_177 = or(_T_171, _T_176)
node _T_178 = and(_T_11, _T_24)
node _T_179 = and(_T_178, _T_37)
node _T_180 = and(_T_179, _T_50)
node _T_181 = and(_T_180, _T_63)
node _T_182 = and(_T_181, _T_71)
node _T_183 = and(_T_182, _T_79)
node _T_184 = and(_T_183, _T_87)
node _T_185 = and(_T_184, _T_95)
node _T_186 = and(_T_185, _T_103)
node _T_187 = and(_T_186, _T_111)
node _T_188 = and(_T_187, _T_124)
node _T_189 = and(_T_188, _T_132)
node _T_190 = and(_T_189, _T_140)
node _T_191 = and(_T_190, _T_153)
node _T_192 = and(_T_191, _T_161)
node _T_193 = and(_T_192, _T_169)
node _T_194 = and(_T_193, _T_177)
node _T_195 = asUInt(reset)
node _T_196 = eq(_T_195, UInt<1>(0h0))
when _T_196 :
node _T_197 = eq(_T_194, UInt<1>(0h0))
when _T_197 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_194, UInt<1>(0h1), "") : assert_1
node _T_198 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_198 :
node _T_199 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_200 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_201 = and(_T_199, _T_200)
node _T_202 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_203 = shr(io.in.a.bits.source, 2)
node _T_204 = eq(_T_203, UInt<1>(0h0))
node _T_205 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_206 = and(_T_204, _T_205)
node _T_207 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_208 = and(_T_206, _T_207)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_209 = shr(io.in.a.bits.source, 2)
node _T_210 = eq(_T_209, UInt<1>(0h1))
node _T_211 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_212 = and(_T_210, _T_211)
node _T_213 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_214 = and(_T_212, _T_213)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_215 = shr(io.in.a.bits.source, 2)
node _T_216 = eq(_T_215, UInt<2>(0h2))
node _T_217 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_218 = and(_T_216, _T_217)
node _T_219 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_220 = and(_T_218, _T_219)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_221 = shr(io.in.a.bits.source, 2)
node _T_222 = eq(_T_221, UInt<2>(0h3))
node _T_223 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_224 = and(_T_222, _T_223)
node _T_225 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_226 = and(_T_224, _T_225)
node _T_227 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_228 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_229 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_230 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_231 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_232 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 2, 0)
node _T_233 = shr(io.in.a.bits.source, 3)
node _T_234 = eq(_T_233, UInt<3>(0h6))
node _T_235 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_236 = and(_T_234, _T_235)
node _T_237 = leq(uncommonBits_10, UInt<3>(0h4))
node _T_238 = and(_T_236, _T_237)
node _T_239 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 2, 0)
node _T_241 = shr(io.in.a.bits.source, 3)
node _T_242 = eq(_T_241, UInt<3>(0h4))
node _T_243 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_244 = and(_T_242, _T_243)
node _T_245 = leq(uncommonBits_11, UInt<3>(0h4))
node _T_246 = and(_T_244, _T_245)
node _T_247 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_249 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_250 = or(_T_202, _T_208)
node _T_251 = or(_T_250, _T_214)
node _T_252 = or(_T_251, _T_220)
node _T_253 = or(_T_252, _T_226)
node _T_254 = or(_T_253, _T_227)
node _T_255 = or(_T_254, _T_228)
node _T_256 = or(_T_255, _T_229)
node _T_257 = or(_T_256, _T_230)
node _T_258 = or(_T_257, _T_231)
node _T_259 = or(_T_258, _T_232)
node _T_260 = or(_T_259, _T_238)
node _T_261 = or(_T_260, _T_239)
node _T_262 = or(_T_261, _T_240)
node _T_263 = or(_T_262, _T_246)
node _T_264 = or(_T_263, _T_247)
node _T_265 = or(_T_264, _T_248)
node _T_266 = or(_T_265, _T_249)
node _T_267 = and(_T_201, _T_266)
node _T_268 = or(UInt<1>(0h0), _T_267)
node _T_269 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_270 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_271 = cvt(_T_270)
node _T_272 = and(_T_271, asSInt(UInt<17>(0h10000)))
node _T_273 = asSInt(_T_272)
node _T_274 = eq(_T_273, asSInt(UInt<1>(0h0)))
node _T_275 = and(_T_269, _T_274)
node _T_276 = or(UInt<1>(0h0), _T_275)
node _T_277 = and(_T_268, _T_276)
node _T_278 = asUInt(reset)
node _T_279 = eq(_T_278, UInt<1>(0h0))
when _T_279 :
node _T_280 = eq(_T_277, UInt<1>(0h0))
when _T_280 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_277, UInt<1>(0h1), "") : assert_2
node _T_281 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_282 = shr(io.in.a.bits.source, 2)
node _T_283 = eq(_T_282, UInt<1>(0h0))
node _T_284 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_285 = and(_T_283, _T_284)
node _T_286 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_287 = and(_T_285, _T_286)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_288 = shr(io.in.a.bits.source, 2)
node _T_289 = eq(_T_288, UInt<1>(0h1))
node _T_290 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_291 = and(_T_289, _T_290)
node _T_292 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_293 = and(_T_291, _T_292)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_294 = shr(io.in.a.bits.source, 2)
node _T_295 = eq(_T_294, UInt<2>(0h2))
node _T_296 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_297 = and(_T_295, _T_296)
node _T_298 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_299 = and(_T_297, _T_298)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_300 = shr(io.in.a.bits.source, 2)
node _T_301 = eq(_T_300, UInt<2>(0h3))
node _T_302 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_303 = and(_T_301, _T_302)
node _T_304 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_305 = and(_T_303, _T_304)
node _T_306 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_307 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_308 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_309 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_310 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_311 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 2, 0)
node _T_312 = shr(io.in.a.bits.source, 3)
node _T_313 = eq(_T_312, UInt<3>(0h6))
node _T_314 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_315 = and(_T_313, _T_314)
node _T_316 = leq(uncommonBits_16, UInt<3>(0h4))
node _T_317 = and(_T_315, _T_316)
node _T_318 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_319 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 2, 0)
node _T_320 = shr(io.in.a.bits.source, 3)
node _T_321 = eq(_T_320, UInt<3>(0h4))
node _T_322 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_323 = and(_T_321, _T_322)
node _T_324 = leq(uncommonBits_17, UInt<3>(0h4))
node _T_325 = and(_T_323, _T_324)
node _T_326 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_328 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _WIRE : UInt<1>[18]
connect _WIRE[0], _T_281
connect _WIRE[1], _T_287
connect _WIRE[2], _T_293
connect _WIRE[3], _T_299
connect _WIRE[4], _T_305
connect _WIRE[5], _T_306
connect _WIRE[6], _T_307
connect _WIRE[7], _T_308
connect _WIRE[8], _T_309
connect _WIRE[9], _T_310
connect _WIRE[10], _T_311
connect _WIRE[11], _T_317
connect _WIRE[12], _T_318
connect _WIRE[13], _T_319
connect _WIRE[14], _T_325
connect _WIRE[15], _T_326
connect _WIRE[16], _T_327
connect _WIRE[17], _T_328
node _T_329 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_330 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_331 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_332 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_333 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_334 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_335 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_336 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_337 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_338 = mux(_WIRE[5], _T_329, UInt<1>(0h0))
node _T_339 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_340 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_341 = mux(_WIRE[8], _T_330, UInt<1>(0h0))
node _T_342 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_343 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_344 = mux(_WIRE[11], _T_331, UInt<1>(0h0))
node _T_345 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_346 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_347 = mux(_WIRE[14], _T_332, UInt<1>(0h0))
node _T_348 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_349 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_350 = mux(_WIRE[17], UInt<1>(0h0), UInt<1>(0h0))
node _T_351 = or(_T_333, _T_334)
node _T_352 = or(_T_351, _T_335)
node _T_353 = or(_T_352, _T_336)
node _T_354 = or(_T_353, _T_337)
node _T_355 = or(_T_354, _T_338)
node _T_356 = or(_T_355, _T_339)
node _T_357 = or(_T_356, _T_340)
node _T_358 = or(_T_357, _T_341)
node _T_359 = or(_T_358, _T_342)
node _T_360 = or(_T_359, _T_343)
node _T_361 = or(_T_360, _T_344)
node _T_362 = or(_T_361, _T_345)
node _T_363 = or(_T_362, _T_346)
node _T_364 = or(_T_363, _T_347)
node _T_365 = or(_T_364, _T_348)
node _T_366 = or(_T_365, _T_349)
node _T_367 = or(_T_366, _T_350)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_367
node _T_368 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_369 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_370 = and(_T_368, _T_369)
node _T_371 = or(UInt<1>(0h0), _T_370)
node _T_372 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_373 = cvt(_T_372)
node _T_374 = and(_T_373, asSInt(UInt<17>(0h10000)))
node _T_375 = asSInt(_T_374)
node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0)))
node _T_377 = and(_T_371, _T_376)
node _T_378 = or(UInt<1>(0h0), _T_377)
node _T_379 = and(_WIRE_1, _T_378)
node _T_380 = asUInt(reset)
node _T_381 = eq(_T_380, UInt<1>(0h0))
when _T_381 :
node _T_382 = eq(_T_379, UInt<1>(0h0))
when _T_382 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_379, UInt<1>(0h1), "") : assert_3
node _T_383 = asUInt(reset)
node _T_384 = eq(_T_383, UInt<1>(0h0))
when _T_384 :
node _T_385 = eq(source_ok, UInt<1>(0h0))
when _T_385 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_386 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_387 = asUInt(reset)
node _T_388 = eq(_T_387, UInt<1>(0h0))
when _T_388 :
node _T_389 = eq(_T_386, UInt<1>(0h0))
when _T_389 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_386, UInt<1>(0h1), "") : assert_5
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(is_aligned, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_393 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_393, UInt<1>(0h1), "") : assert_7
node _T_397 = not(io.in.a.bits.mask)
node _T_398 = eq(_T_397, UInt<1>(0h0))
node _T_399 = asUInt(reset)
node _T_400 = eq(_T_399, UInt<1>(0h0))
when _T_400 :
node _T_401 = eq(_T_398, UInt<1>(0h0))
when _T_401 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_398, UInt<1>(0h1), "") : assert_8
node _T_402 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_403 = asUInt(reset)
node _T_404 = eq(_T_403, UInt<1>(0h0))
when _T_404 :
node _T_405 = eq(_T_402, UInt<1>(0h0))
when _T_405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_402, UInt<1>(0h1), "") : assert_9
node _T_406 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_406 :
node _T_407 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_408 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_409 = and(_T_407, _T_408)
node _T_410 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_411 = shr(io.in.a.bits.source, 2)
node _T_412 = eq(_T_411, UInt<1>(0h0))
node _T_413 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_414 = and(_T_412, _T_413)
node _T_415 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_416 = and(_T_414, _T_415)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_417 = shr(io.in.a.bits.source, 2)
node _T_418 = eq(_T_417, UInt<1>(0h1))
node _T_419 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_420 = and(_T_418, _T_419)
node _T_421 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_422 = and(_T_420, _T_421)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_423 = shr(io.in.a.bits.source, 2)
node _T_424 = eq(_T_423, UInt<2>(0h2))
node _T_425 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_426 = and(_T_424, _T_425)
node _T_427 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_428 = and(_T_426, _T_427)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_429 = shr(io.in.a.bits.source, 2)
node _T_430 = eq(_T_429, UInt<2>(0h3))
node _T_431 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_432 = and(_T_430, _T_431)
node _T_433 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_434 = and(_T_432, _T_433)
node _T_435 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_436 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_437 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_438 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_439 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_440 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 2, 0)
node _T_441 = shr(io.in.a.bits.source, 3)
node _T_442 = eq(_T_441, UInt<3>(0h6))
node _T_443 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_444 = and(_T_442, _T_443)
node _T_445 = leq(uncommonBits_22, UInt<3>(0h4))
node _T_446 = and(_T_444, _T_445)
node _T_447 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_448 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 2, 0)
node _T_449 = shr(io.in.a.bits.source, 3)
node _T_450 = eq(_T_449, UInt<3>(0h4))
node _T_451 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_452 = and(_T_450, _T_451)
node _T_453 = leq(uncommonBits_23, UInt<3>(0h4))
node _T_454 = and(_T_452, _T_453)
node _T_455 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_456 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_457 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_458 = or(_T_410, _T_416)
node _T_459 = or(_T_458, _T_422)
node _T_460 = or(_T_459, _T_428)
node _T_461 = or(_T_460, _T_434)
node _T_462 = or(_T_461, _T_435)
node _T_463 = or(_T_462, _T_436)
node _T_464 = or(_T_463, _T_437)
node _T_465 = or(_T_464, _T_438)
node _T_466 = or(_T_465, _T_439)
node _T_467 = or(_T_466, _T_440)
node _T_468 = or(_T_467, _T_446)
node _T_469 = or(_T_468, _T_447)
node _T_470 = or(_T_469, _T_448)
node _T_471 = or(_T_470, _T_454)
node _T_472 = or(_T_471, _T_455)
node _T_473 = or(_T_472, _T_456)
node _T_474 = or(_T_473, _T_457)
node _T_475 = and(_T_409, _T_474)
node _T_476 = or(UInt<1>(0h0), _T_475)
node _T_477 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_478 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_479 = cvt(_T_478)
node _T_480 = and(_T_479, asSInt(UInt<17>(0h10000)))
node _T_481 = asSInt(_T_480)
node _T_482 = eq(_T_481, asSInt(UInt<1>(0h0)))
node _T_483 = and(_T_477, _T_482)
node _T_484 = or(UInt<1>(0h0), _T_483)
node _T_485 = and(_T_476, _T_484)
node _T_486 = asUInt(reset)
node _T_487 = eq(_T_486, UInt<1>(0h0))
when _T_487 :
node _T_488 = eq(_T_485, UInt<1>(0h0))
when _T_488 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_485, UInt<1>(0h1), "") : assert_10
node _T_489 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_490 = shr(io.in.a.bits.source, 2)
node _T_491 = eq(_T_490, UInt<1>(0h0))
node _T_492 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_493 = and(_T_491, _T_492)
node _T_494 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_495 = and(_T_493, _T_494)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_496 = shr(io.in.a.bits.source, 2)
node _T_497 = eq(_T_496, UInt<1>(0h1))
node _T_498 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_499 = and(_T_497, _T_498)
node _T_500 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_501 = and(_T_499, _T_500)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_502 = shr(io.in.a.bits.source, 2)
node _T_503 = eq(_T_502, UInt<2>(0h2))
node _T_504 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_505 = and(_T_503, _T_504)
node _T_506 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_507 = and(_T_505, _T_506)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_508 = shr(io.in.a.bits.source, 2)
node _T_509 = eq(_T_508, UInt<2>(0h3))
node _T_510 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_511 = and(_T_509, _T_510)
node _T_512 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_513 = and(_T_511, _T_512)
node _T_514 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_515 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_516 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_517 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_518 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_519 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 2, 0)
node _T_520 = shr(io.in.a.bits.source, 3)
node _T_521 = eq(_T_520, UInt<3>(0h6))
node _T_522 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_523 = and(_T_521, _T_522)
node _T_524 = leq(uncommonBits_28, UInt<3>(0h4))
node _T_525 = and(_T_523, _T_524)
node _T_526 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_527 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 2, 0)
node _T_528 = shr(io.in.a.bits.source, 3)
node _T_529 = eq(_T_528, UInt<3>(0h4))
node _T_530 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_531 = and(_T_529, _T_530)
node _T_532 = leq(uncommonBits_29, UInt<3>(0h4))
node _T_533 = and(_T_531, _T_532)
node _T_534 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_535 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_536 = eq(io.in.a.bits.source, UInt<8>(0h80))
wire _WIRE_2 : UInt<1>[18]
connect _WIRE_2[0], _T_489
connect _WIRE_2[1], _T_495
connect _WIRE_2[2], _T_501
connect _WIRE_2[3], _T_507
connect _WIRE_2[4], _T_513
connect _WIRE_2[5], _T_514
connect _WIRE_2[6], _T_515
connect _WIRE_2[7], _T_516
connect _WIRE_2[8], _T_517
connect _WIRE_2[9], _T_518
connect _WIRE_2[10], _T_519
connect _WIRE_2[11], _T_525
connect _WIRE_2[12], _T_526
connect _WIRE_2[13], _T_527
connect _WIRE_2[14], _T_533
connect _WIRE_2[15], _T_534
connect _WIRE_2[16], _T_535
connect _WIRE_2[17], _T_536
node _T_537 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_538 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_539 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_540 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_541 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_542 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_543 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_544 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_545 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_546 = mux(_WIRE_2[5], _T_537, UInt<1>(0h0))
node _T_547 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_548 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_549 = mux(_WIRE_2[8], _T_538, UInt<1>(0h0))
node _T_550 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_551 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_552 = mux(_WIRE_2[11], _T_539, UInt<1>(0h0))
node _T_553 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_554 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_555 = mux(_WIRE_2[14], _T_540, UInt<1>(0h0))
node _T_556 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_557 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_558 = mux(_WIRE_2[17], UInt<1>(0h0), UInt<1>(0h0))
node _T_559 = or(_T_541, _T_542)
node _T_560 = or(_T_559, _T_543)
node _T_561 = or(_T_560, _T_544)
node _T_562 = or(_T_561, _T_545)
node _T_563 = or(_T_562, _T_546)
node _T_564 = or(_T_563, _T_547)
node _T_565 = or(_T_564, _T_548)
node _T_566 = or(_T_565, _T_549)
node _T_567 = or(_T_566, _T_550)
node _T_568 = or(_T_567, _T_551)
node _T_569 = or(_T_568, _T_552)
node _T_570 = or(_T_569, _T_553)
node _T_571 = or(_T_570, _T_554)
node _T_572 = or(_T_571, _T_555)
node _T_573 = or(_T_572, _T_556)
node _T_574 = or(_T_573, _T_557)
node _T_575 = or(_T_574, _T_558)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_575
node _T_576 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_577 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_578 = and(_T_576, _T_577)
node _T_579 = or(UInt<1>(0h0), _T_578)
node _T_580 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_581 = cvt(_T_580)
node _T_582 = and(_T_581, asSInt(UInt<17>(0h10000)))
node _T_583 = asSInt(_T_582)
node _T_584 = eq(_T_583, asSInt(UInt<1>(0h0)))
node _T_585 = and(_T_579, _T_584)
node _T_586 = or(UInt<1>(0h0), _T_585)
node _T_587 = and(_WIRE_3, _T_586)
node _T_588 = asUInt(reset)
node _T_589 = eq(_T_588, UInt<1>(0h0))
when _T_589 :
node _T_590 = eq(_T_587, UInt<1>(0h0))
when _T_590 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_587, UInt<1>(0h1), "") : assert_11
node _T_591 = asUInt(reset)
node _T_592 = eq(_T_591, UInt<1>(0h0))
when _T_592 :
node _T_593 = eq(source_ok, UInt<1>(0h0))
when _T_593 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_594 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_595 = asUInt(reset)
node _T_596 = eq(_T_595, UInt<1>(0h0))
when _T_596 :
node _T_597 = eq(_T_594, UInt<1>(0h0))
when _T_597 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_594, UInt<1>(0h1), "") : assert_13
node _T_598 = asUInt(reset)
node _T_599 = eq(_T_598, UInt<1>(0h0))
when _T_599 :
node _T_600 = eq(is_aligned, UInt<1>(0h0))
when _T_600 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_601 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_601, UInt<1>(0h1), "") : assert_15
node _T_605 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_606 = asUInt(reset)
node _T_607 = eq(_T_606, UInt<1>(0h0))
when _T_607 :
node _T_608 = eq(_T_605, UInt<1>(0h0))
when _T_608 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_605, UInt<1>(0h1), "") : assert_16
node _T_609 = not(io.in.a.bits.mask)
node _T_610 = eq(_T_609, UInt<1>(0h0))
node _T_611 = asUInt(reset)
node _T_612 = eq(_T_611, UInt<1>(0h0))
when _T_612 :
node _T_613 = eq(_T_610, UInt<1>(0h0))
when _T_613 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_610, UInt<1>(0h1), "") : assert_17
node _T_614 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_615 = asUInt(reset)
node _T_616 = eq(_T_615, UInt<1>(0h0))
when _T_616 :
node _T_617 = eq(_T_614, UInt<1>(0h0))
when _T_617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_614, UInt<1>(0h1), "") : assert_18
node _T_618 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_618 :
node _T_619 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_620 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_621 = and(_T_619, _T_620)
node _T_622 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_623 = shr(io.in.a.bits.source, 2)
node _T_624 = eq(_T_623, UInt<1>(0h0))
node _T_625 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_626 = and(_T_624, _T_625)
node _T_627 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_628 = and(_T_626, _T_627)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_629 = shr(io.in.a.bits.source, 2)
node _T_630 = eq(_T_629, UInt<1>(0h1))
node _T_631 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_632 = and(_T_630, _T_631)
node _T_633 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_634 = and(_T_632, _T_633)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_635 = shr(io.in.a.bits.source, 2)
node _T_636 = eq(_T_635, UInt<2>(0h2))
node _T_637 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_638 = and(_T_636, _T_637)
node _T_639 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_640 = and(_T_638, _T_639)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_641 = shr(io.in.a.bits.source, 2)
node _T_642 = eq(_T_641, UInt<2>(0h3))
node _T_643 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_644 = and(_T_642, _T_643)
node _T_645 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_646 = and(_T_644, _T_645)
node _T_647 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_648 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_649 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_650 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_651 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_652 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0)
node _T_653 = shr(io.in.a.bits.source, 3)
node _T_654 = eq(_T_653, UInt<3>(0h6))
node _T_655 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_656 = and(_T_654, _T_655)
node _T_657 = leq(uncommonBits_34, UInt<3>(0h4))
node _T_658 = and(_T_656, _T_657)
node _T_659 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_660 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 2, 0)
node _T_661 = shr(io.in.a.bits.source, 3)
node _T_662 = eq(_T_661, UInt<3>(0h4))
node _T_663 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_664 = and(_T_662, _T_663)
node _T_665 = leq(uncommonBits_35, UInt<3>(0h4))
node _T_666 = and(_T_664, _T_665)
node _T_667 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_668 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_669 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_670 = or(_T_622, _T_628)
node _T_671 = or(_T_670, _T_634)
node _T_672 = or(_T_671, _T_640)
node _T_673 = or(_T_672, _T_646)
node _T_674 = or(_T_673, _T_647)
node _T_675 = or(_T_674, _T_648)
node _T_676 = or(_T_675, _T_649)
node _T_677 = or(_T_676, _T_650)
node _T_678 = or(_T_677, _T_651)
node _T_679 = or(_T_678, _T_652)
node _T_680 = or(_T_679, _T_658)
node _T_681 = or(_T_680, _T_659)
node _T_682 = or(_T_681, _T_660)
node _T_683 = or(_T_682, _T_666)
node _T_684 = or(_T_683, _T_667)
node _T_685 = or(_T_684, _T_668)
node _T_686 = or(_T_685, _T_669)
node _T_687 = and(_T_621, _T_686)
node _T_688 = or(UInt<1>(0h0), _T_687)
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(_T_688, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_688, UInt<1>(0h1), "") : assert_19
node _T_692 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_693 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_694 = and(_T_692, _T_693)
node _T_695 = or(UInt<1>(0h0), _T_694)
node _T_696 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_697 = cvt(_T_696)
node _T_698 = and(_T_697, asSInt(UInt<17>(0h10000)))
node _T_699 = asSInt(_T_698)
node _T_700 = eq(_T_699, asSInt(UInt<1>(0h0)))
node _T_701 = and(_T_695, _T_700)
node _T_702 = or(UInt<1>(0h0), _T_701)
node _T_703 = asUInt(reset)
node _T_704 = eq(_T_703, UInt<1>(0h0))
when _T_704 :
node _T_705 = eq(_T_702, UInt<1>(0h0))
when _T_705 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_702, UInt<1>(0h1), "") : assert_20
node _T_706 = asUInt(reset)
node _T_707 = eq(_T_706, UInt<1>(0h0))
when _T_707 :
node _T_708 = eq(source_ok, UInt<1>(0h0))
when _T_708 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_709 = asUInt(reset)
node _T_710 = eq(_T_709, UInt<1>(0h0))
when _T_710 :
node _T_711 = eq(is_aligned, UInt<1>(0h0))
when _T_711 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_712 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_712, UInt<1>(0h1), "") : assert_23
node _T_716 = eq(io.in.a.bits.mask, mask)
node _T_717 = asUInt(reset)
node _T_718 = eq(_T_717, UInt<1>(0h0))
when _T_718 :
node _T_719 = eq(_T_716, UInt<1>(0h0))
when _T_719 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_716, UInt<1>(0h1), "") : assert_24
node _T_720 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_721 = asUInt(reset)
node _T_722 = eq(_T_721, UInt<1>(0h0))
when _T_722 :
node _T_723 = eq(_T_720, UInt<1>(0h0))
when _T_723 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_720, UInt<1>(0h1), "") : assert_25
node _T_724 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_724 :
node _T_725 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_726 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_727 = and(_T_725, _T_726)
node _T_728 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_729 = shr(io.in.a.bits.source, 2)
node _T_730 = eq(_T_729, UInt<1>(0h0))
node _T_731 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_732 = and(_T_730, _T_731)
node _T_733 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_734 = and(_T_732, _T_733)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_735 = shr(io.in.a.bits.source, 2)
node _T_736 = eq(_T_735, UInt<1>(0h1))
node _T_737 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_738 = and(_T_736, _T_737)
node _T_739 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_740 = and(_T_738, _T_739)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_741 = shr(io.in.a.bits.source, 2)
node _T_742 = eq(_T_741, UInt<2>(0h2))
node _T_743 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_744 = and(_T_742, _T_743)
node _T_745 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_746 = and(_T_744, _T_745)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_747 = shr(io.in.a.bits.source, 2)
node _T_748 = eq(_T_747, UInt<2>(0h3))
node _T_749 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_750 = and(_T_748, _T_749)
node _T_751 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_752 = and(_T_750, _T_751)
node _T_753 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_754 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_755 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_756 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_757 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_758 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 2, 0)
node _T_759 = shr(io.in.a.bits.source, 3)
node _T_760 = eq(_T_759, UInt<3>(0h6))
node _T_761 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_762 = and(_T_760, _T_761)
node _T_763 = leq(uncommonBits_40, UInt<3>(0h4))
node _T_764 = and(_T_762, _T_763)
node _T_765 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_766 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 2, 0)
node _T_767 = shr(io.in.a.bits.source, 3)
node _T_768 = eq(_T_767, UInt<3>(0h4))
node _T_769 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_770 = and(_T_768, _T_769)
node _T_771 = leq(uncommonBits_41, UInt<3>(0h4))
node _T_772 = and(_T_770, _T_771)
node _T_773 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_774 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_775 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_776 = or(_T_728, _T_734)
node _T_777 = or(_T_776, _T_740)
node _T_778 = or(_T_777, _T_746)
node _T_779 = or(_T_778, _T_752)
node _T_780 = or(_T_779, _T_753)
node _T_781 = or(_T_780, _T_754)
node _T_782 = or(_T_781, _T_755)
node _T_783 = or(_T_782, _T_756)
node _T_784 = or(_T_783, _T_757)
node _T_785 = or(_T_784, _T_758)
node _T_786 = or(_T_785, _T_764)
node _T_787 = or(_T_786, _T_765)
node _T_788 = or(_T_787, _T_766)
node _T_789 = or(_T_788, _T_772)
node _T_790 = or(_T_789, _T_773)
node _T_791 = or(_T_790, _T_774)
node _T_792 = or(_T_791, _T_775)
node _T_793 = and(_T_727, _T_792)
node _T_794 = or(UInt<1>(0h0), _T_793)
node _T_795 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_796 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_797 = and(_T_795, _T_796)
node _T_798 = or(UInt<1>(0h0), _T_797)
node _T_799 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_800 = cvt(_T_799)
node _T_801 = and(_T_800, asSInt(UInt<17>(0h10000)))
node _T_802 = asSInt(_T_801)
node _T_803 = eq(_T_802, asSInt(UInt<1>(0h0)))
node _T_804 = and(_T_798, _T_803)
node _T_805 = or(UInt<1>(0h0), _T_804)
node _T_806 = and(_T_794, _T_805)
node _T_807 = asUInt(reset)
node _T_808 = eq(_T_807, UInt<1>(0h0))
when _T_808 :
node _T_809 = eq(_T_806, UInt<1>(0h0))
when _T_809 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_806, UInt<1>(0h1), "") : assert_26
node _T_810 = asUInt(reset)
node _T_811 = eq(_T_810, UInt<1>(0h0))
when _T_811 :
node _T_812 = eq(source_ok, UInt<1>(0h0))
when _T_812 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_813 = asUInt(reset)
node _T_814 = eq(_T_813, UInt<1>(0h0))
when _T_814 :
node _T_815 = eq(is_aligned, UInt<1>(0h0))
when _T_815 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_816 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_817 = asUInt(reset)
node _T_818 = eq(_T_817, UInt<1>(0h0))
when _T_818 :
node _T_819 = eq(_T_816, UInt<1>(0h0))
when _T_819 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_816, UInt<1>(0h1), "") : assert_29
node _T_820 = eq(io.in.a.bits.mask, mask)
node _T_821 = asUInt(reset)
node _T_822 = eq(_T_821, UInt<1>(0h0))
when _T_822 :
node _T_823 = eq(_T_820, UInt<1>(0h0))
when _T_823 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_820, UInt<1>(0h1), "") : assert_30
node _T_824 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_824 :
node _T_825 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_826 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_827 = and(_T_825, _T_826)
node _T_828 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_829 = shr(io.in.a.bits.source, 2)
node _T_830 = eq(_T_829, UInt<1>(0h0))
node _T_831 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_832 = and(_T_830, _T_831)
node _T_833 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_834 = and(_T_832, _T_833)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_835 = shr(io.in.a.bits.source, 2)
node _T_836 = eq(_T_835, UInt<1>(0h1))
node _T_837 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_838 = and(_T_836, _T_837)
node _T_839 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_840 = and(_T_838, _T_839)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_841 = shr(io.in.a.bits.source, 2)
node _T_842 = eq(_T_841, UInt<2>(0h2))
node _T_843 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_844 = and(_T_842, _T_843)
node _T_845 = leq(uncommonBits_44, UInt<2>(0h3))
node _T_846 = and(_T_844, _T_845)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_847 = shr(io.in.a.bits.source, 2)
node _T_848 = eq(_T_847, UInt<2>(0h3))
node _T_849 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_850 = and(_T_848, _T_849)
node _T_851 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_852 = and(_T_850, _T_851)
node _T_853 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_854 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_855 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_856 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_857 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_858 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 2, 0)
node _T_859 = shr(io.in.a.bits.source, 3)
node _T_860 = eq(_T_859, UInt<3>(0h6))
node _T_861 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_862 = and(_T_860, _T_861)
node _T_863 = leq(uncommonBits_46, UInt<3>(0h4))
node _T_864 = and(_T_862, _T_863)
node _T_865 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_866 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 2, 0)
node _T_867 = shr(io.in.a.bits.source, 3)
node _T_868 = eq(_T_867, UInt<3>(0h4))
node _T_869 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_870 = and(_T_868, _T_869)
node _T_871 = leq(uncommonBits_47, UInt<3>(0h4))
node _T_872 = and(_T_870, _T_871)
node _T_873 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_874 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_875 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_876 = or(_T_828, _T_834)
node _T_877 = or(_T_876, _T_840)
node _T_878 = or(_T_877, _T_846)
node _T_879 = or(_T_878, _T_852)
node _T_880 = or(_T_879, _T_853)
node _T_881 = or(_T_880, _T_854)
node _T_882 = or(_T_881, _T_855)
node _T_883 = or(_T_882, _T_856)
node _T_884 = or(_T_883, _T_857)
node _T_885 = or(_T_884, _T_858)
node _T_886 = or(_T_885, _T_864)
node _T_887 = or(_T_886, _T_865)
node _T_888 = or(_T_887, _T_866)
node _T_889 = or(_T_888, _T_872)
node _T_890 = or(_T_889, _T_873)
node _T_891 = or(_T_890, _T_874)
node _T_892 = or(_T_891, _T_875)
node _T_893 = and(_T_827, _T_892)
node _T_894 = or(UInt<1>(0h0), _T_893)
node _T_895 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_896 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_897 = and(_T_895, _T_896)
node _T_898 = or(UInt<1>(0h0), _T_897)
node _T_899 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_900 = cvt(_T_899)
node _T_901 = and(_T_900, asSInt(UInt<17>(0h10000)))
node _T_902 = asSInt(_T_901)
node _T_903 = eq(_T_902, asSInt(UInt<1>(0h0)))
node _T_904 = and(_T_898, _T_903)
node _T_905 = or(UInt<1>(0h0), _T_904)
node _T_906 = and(_T_894, _T_905)
node _T_907 = asUInt(reset)
node _T_908 = eq(_T_907, UInt<1>(0h0))
when _T_908 :
node _T_909 = eq(_T_906, UInt<1>(0h0))
when _T_909 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_906, UInt<1>(0h1), "") : assert_31
node _T_910 = asUInt(reset)
node _T_911 = eq(_T_910, UInt<1>(0h0))
when _T_911 :
node _T_912 = eq(source_ok, UInt<1>(0h0))
when _T_912 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_913 = asUInt(reset)
node _T_914 = eq(_T_913, UInt<1>(0h0))
when _T_914 :
node _T_915 = eq(is_aligned, UInt<1>(0h0))
when _T_915 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_916 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_917 = asUInt(reset)
node _T_918 = eq(_T_917, UInt<1>(0h0))
when _T_918 :
node _T_919 = eq(_T_916, UInt<1>(0h0))
when _T_919 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_916, UInt<1>(0h1), "") : assert_34
node _T_920 = not(mask)
node _T_921 = and(io.in.a.bits.mask, _T_920)
node _T_922 = eq(_T_921, UInt<1>(0h0))
node _T_923 = asUInt(reset)
node _T_924 = eq(_T_923, UInt<1>(0h0))
when _T_924 :
node _T_925 = eq(_T_922, UInt<1>(0h0))
when _T_925 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_922, UInt<1>(0h1), "") : assert_35
node _T_926 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_926 :
node _T_927 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_928 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_929 = and(_T_927, _T_928)
node _T_930 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_931 = shr(io.in.a.bits.source, 2)
node _T_932 = eq(_T_931, UInt<1>(0h0))
node _T_933 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_934 = and(_T_932, _T_933)
node _T_935 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_936 = and(_T_934, _T_935)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_937 = shr(io.in.a.bits.source, 2)
node _T_938 = eq(_T_937, UInt<1>(0h1))
node _T_939 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_940 = and(_T_938, _T_939)
node _T_941 = leq(uncommonBits_49, UInt<2>(0h3))
node _T_942 = and(_T_940, _T_941)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_943 = shr(io.in.a.bits.source, 2)
node _T_944 = eq(_T_943, UInt<2>(0h2))
node _T_945 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_946 = and(_T_944, _T_945)
node _T_947 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_948 = and(_T_946, _T_947)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_949 = shr(io.in.a.bits.source, 2)
node _T_950 = eq(_T_949, UInt<2>(0h3))
node _T_951 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_952 = and(_T_950, _T_951)
node _T_953 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_954 = and(_T_952, _T_953)
node _T_955 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_956 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_957 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_958 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_959 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_960 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 2, 0)
node _T_961 = shr(io.in.a.bits.source, 3)
node _T_962 = eq(_T_961, UInt<3>(0h6))
node _T_963 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_964 = and(_T_962, _T_963)
node _T_965 = leq(uncommonBits_52, UInt<3>(0h4))
node _T_966 = and(_T_964, _T_965)
node _T_967 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_968 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 2, 0)
node _T_969 = shr(io.in.a.bits.source, 3)
node _T_970 = eq(_T_969, UInt<3>(0h4))
node _T_971 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_972 = and(_T_970, _T_971)
node _T_973 = leq(uncommonBits_53, UInt<3>(0h4))
node _T_974 = and(_T_972, _T_973)
node _T_975 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_976 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_977 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_978 = or(_T_930, _T_936)
node _T_979 = or(_T_978, _T_942)
node _T_980 = or(_T_979, _T_948)
node _T_981 = or(_T_980, _T_954)
node _T_982 = or(_T_981, _T_955)
node _T_983 = or(_T_982, _T_956)
node _T_984 = or(_T_983, _T_957)
node _T_985 = or(_T_984, _T_958)
node _T_986 = or(_T_985, _T_959)
node _T_987 = or(_T_986, _T_960)
node _T_988 = or(_T_987, _T_966)
node _T_989 = or(_T_988, _T_967)
node _T_990 = or(_T_989, _T_968)
node _T_991 = or(_T_990, _T_974)
node _T_992 = or(_T_991, _T_975)
node _T_993 = or(_T_992, _T_976)
node _T_994 = or(_T_993, _T_977)
node _T_995 = and(_T_929, _T_994)
node _T_996 = or(UInt<1>(0h0), _T_995)
node _T_997 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_998 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_999 = cvt(_T_998)
node _T_1000 = and(_T_999, asSInt(UInt<17>(0h10000)))
node _T_1001 = asSInt(_T_1000)
node _T_1002 = eq(_T_1001, asSInt(UInt<1>(0h0)))
node _T_1003 = and(_T_997, _T_1002)
node _T_1004 = or(UInt<1>(0h0), _T_1003)
node _T_1005 = and(_T_996, _T_1004)
node _T_1006 = asUInt(reset)
node _T_1007 = eq(_T_1006, UInt<1>(0h0))
when _T_1007 :
node _T_1008 = eq(_T_1005, UInt<1>(0h0))
when _T_1008 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_1005, UInt<1>(0h1), "") : assert_36
node _T_1009 = asUInt(reset)
node _T_1010 = eq(_T_1009, UInt<1>(0h0))
when _T_1010 :
node _T_1011 = eq(source_ok, UInt<1>(0h0))
when _T_1011 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_1012 = asUInt(reset)
node _T_1013 = eq(_T_1012, UInt<1>(0h0))
when _T_1013 :
node _T_1014 = eq(is_aligned, UInt<1>(0h0))
when _T_1014 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_1015 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_1016 = asUInt(reset)
node _T_1017 = eq(_T_1016, UInt<1>(0h0))
when _T_1017 :
node _T_1018 = eq(_T_1015, UInt<1>(0h0))
when _T_1018 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_1015, UInt<1>(0h1), "") : assert_39
node _T_1019 = eq(io.in.a.bits.mask, mask)
node _T_1020 = asUInt(reset)
node _T_1021 = eq(_T_1020, UInt<1>(0h0))
when _T_1021 :
node _T_1022 = eq(_T_1019, UInt<1>(0h0))
when _T_1022 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_1019, UInt<1>(0h1), "") : assert_40
node _T_1023 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_1023 :
node _T_1024 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1025 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1026 = and(_T_1024, _T_1025)
node _T_1027 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0)
node _T_1028 = shr(io.in.a.bits.source, 2)
node _T_1029 = eq(_T_1028, UInt<1>(0h0))
node _T_1030 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_1031 = and(_T_1029, _T_1030)
node _T_1032 = leq(uncommonBits_54, UInt<2>(0h3))
node _T_1033 = and(_T_1031, _T_1032)
node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0)
node _T_1034 = shr(io.in.a.bits.source, 2)
node _T_1035 = eq(_T_1034, UInt<1>(0h1))
node _T_1036 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_1037 = and(_T_1035, _T_1036)
node _T_1038 = leq(uncommonBits_55, UInt<2>(0h3))
node _T_1039 = and(_T_1037, _T_1038)
node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0)
node _T_1040 = shr(io.in.a.bits.source, 2)
node _T_1041 = eq(_T_1040, UInt<2>(0h2))
node _T_1042 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_1043 = and(_T_1041, _T_1042)
node _T_1044 = leq(uncommonBits_56, UInt<2>(0h3))
node _T_1045 = and(_T_1043, _T_1044)
node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0)
node _T_1046 = shr(io.in.a.bits.source, 2)
node _T_1047 = eq(_T_1046, UInt<2>(0h3))
node _T_1048 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_1049 = and(_T_1047, _T_1048)
node _T_1050 = leq(uncommonBits_57, UInt<2>(0h3))
node _T_1051 = and(_T_1049, _T_1050)
node _T_1052 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_1053 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_1054 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_1055 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1056 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_1057 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 2, 0)
node _T_1058 = shr(io.in.a.bits.source, 3)
node _T_1059 = eq(_T_1058, UInt<3>(0h6))
node _T_1060 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_1061 = and(_T_1059, _T_1060)
node _T_1062 = leq(uncommonBits_58, UInt<3>(0h4))
node _T_1063 = and(_T_1061, _T_1062)
node _T_1064 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_1065 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 2, 0)
node _T_1066 = shr(io.in.a.bits.source, 3)
node _T_1067 = eq(_T_1066, UInt<3>(0h4))
node _T_1068 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_1069 = and(_T_1067, _T_1068)
node _T_1070 = leq(uncommonBits_59, UInt<3>(0h4))
node _T_1071 = and(_T_1069, _T_1070)
node _T_1072 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1073 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1074 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_1075 = or(_T_1027, _T_1033)
node _T_1076 = or(_T_1075, _T_1039)
node _T_1077 = or(_T_1076, _T_1045)
node _T_1078 = or(_T_1077, _T_1051)
node _T_1079 = or(_T_1078, _T_1052)
node _T_1080 = or(_T_1079, _T_1053)
node _T_1081 = or(_T_1080, _T_1054)
node _T_1082 = or(_T_1081, _T_1055)
node _T_1083 = or(_T_1082, _T_1056)
node _T_1084 = or(_T_1083, _T_1057)
node _T_1085 = or(_T_1084, _T_1063)
node _T_1086 = or(_T_1085, _T_1064)
node _T_1087 = or(_T_1086, _T_1065)
node _T_1088 = or(_T_1087, _T_1071)
node _T_1089 = or(_T_1088, _T_1072)
node _T_1090 = or(_T_1089, _T_1073)
node _T_1091 = or(_T_1090, _T_1074)
node _T_1092 = and(_T_1026, _T_1091)
node _T_1093 = or(UInt<1>(0h0), _T_1092)
node _T_1094 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1095 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1096 = cvt(_T_1095)
node _T_1097 = and(_T_1096, asSInt(UInt<17>(0h10000)))
node _T_1098 = asSInt(_T_1097)
node _T_1099 = eq(_T_1098, asSInt(UInt<1>(0h0)))
node _T_1100 = and(_T_1094, _T_1099)
node _T_1101 = or(UInt<1>(0h0), _T_1100)
node _T_1102 = and(_T_1093, _T_1101)
node _T_1103 = asUInt(reset)
node _T_1104 = eq(_T_1103, UInt<1>(0h0))
when _T_1104 :
node _T_1105 = eq(_T_1102, UInt<1>(0h0))
when _T_1105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1102, UInt<1>(0h1), "") : assert_41
node _T_1106 = asUInt(reset)
node _T_1107 = eq(_T_1106, UInt<1>(0h0))
when _T_1107 :
node _T_1108 = eq(source_ok, UInt<1>(0h0))
when _T_1108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1109 = asUInt(reset)
node _T_1110 = eq(_T_1109, UInt<1>(0h0))
when _T_1110 :
node _T_1111 = eq(is_aligned, UInt<1>(0h0))
when _T_1111 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1112 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1113 = asUInt(reset)
node _T_1114 = eq(_T_1113, UInt<1>(0h0))
when _T_1114 :
node _T_1115 = eq(_T_1112, UInt<1>(0h0))
when _T_1115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1112, UInt<1>(0h1), "") : assert_44
node _T_1116 = eq(io.in.a.bits.mask, mask)
node _T_1117 = asUInt(reset)
node _T_1118 = eq(_T_1117, UInt<1>(0h0))
when _T_1118 :
node _T_1119 = eq(_T_1116, UInt<1>(0h0))
when _T_1119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1116, UInt<1>(0h1), "") : assert_45
node _T_1120 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1120 :
node _T_1121 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1122 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1123 = and(_T_1121, _T_1122)
node _T_1124 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0)
node _T_1125 = shr(io.in.a.bits.source, 2)
node _T_1126 = eq(_T_1125, UInt<1>(0h0))
node _T_1127 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_1128 = and(_T_1126, _T_1127)
node _T_1129 = leq(uncommonBits_60, UInt<2>(0h3))
node _T_1130 = and(_T_1128, _T_1129)
node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0)
node _T_1131 = shr(io.in.a.bits.source, 2)
node _T_1132 = eq(_T_1131, UInt<1>(0h1))
node _T_1133 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_1134 = and(_T_1132, _T_1133)
node _T_1135 = leq(uncommonBits_61, UInt<2>(0h3))
node _T_1136 = and(_T_1134, _T_1135)
node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0)
node _T_1137 = shr(io.in.a.bits.source, 2)
node _T_1138 = eq(_T_1137, UInt<2>(0h2))
node _T_1139 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_1140 = and(_T_1138, _T_1139)
node _T_1141 = leq(uncommonBits_62, UInt<2>(0h3))
node _T_1142 = and(_T_1140, _T_1141)
node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0)
node _T_1143 = shr(io.in.a.bits.source, 2)
node _T_1144 = eq(_T_1143, UInt<2>(0h3))
node _T_1145 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_1146 = and(_T_1144, _T_1145)
node _T_1147 = leq(uncommonBits_63, UInt<2>(0h3))
node _T_1148 = and(_T_1146, _T_1147)
node _T_1149 = eq(io.in.a.bits.source, UInt<7>(0h44))
node _T_1150 = eq(io.in.a.bits.source, UInt<7>(0h45))
node _T_1151 = eq(io.in.a.bits.source, UInt<7>(0h46))
node _T_1152 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1153 = eq(io.in.a.bits.source, UInt<7>(0h41))
node _T_1154 = eq(io.in.a.bits.source, UInt<7>(0h42))
node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 2, 0)
node _T_1155 = shr(io.in.a.bits.source, 3)
node _T_1156 = eq(_T_1155, UInt<3>(0h6))
node _T_1157 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_1158 = and(_T_1156, _T_1157)
node _T_1159 = leq(uncommonBits_64, UInt<3>(0h4))
node _T_1160 = and(_T_1158, _T_1159)
node _T_1161 = eq(io.in.a.bits.source, UInt<6>(0h35))
node _T_1162 = eq(io.in.a.bits.source, UInt<6>(0h38))
node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<3>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 2, 0)
node _T_1163 = shr(io.in.a.bits.source, 3)
node _T_1164 = eq(_T_1163, UInt<3>(0h4))
node _T_1165 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_1166 = and(_T_1164, _T_1165)
node _T_1167 = leq(uncommonBits_65, UInt<3>(0h4))
node _T_1168 = and(_T_1166, _T_1167)
node _T_1169 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1170 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1171 = eq(io.in.a.bits.source, UInt<8>(0h80))
node _T_1172 = or(_T_1124, _T_1130)
node _T_1173 = or(_T_1172, _T_1136)
node _T_1174 = or(_T_1173, _T_1142)
node _T_1175 = or(_T_1174, _T_1148)
node _T_1176 = or(_T_1175, _T_1149)
node _T_1177 = or(_T_1176, _T_1150)
node _T_1178 = or(_T_1177, _T_1151)
node _T_1179 = or(_T_1178, _T_1152)
node _T_1180 = or(_T_1179, _T_1153)
node _T_1181 = or(_T_1180, _T_1154)
node _T_1182 = or(_T_1181, _T_1160)
node _T_1183 = or(_T_1182, _T_1161)
node _T_1184 = or(_T_1183, _T_1162)
node _T_1185 = or(_T_1184, _T_1168)
node _T_1186 = or(_T_1185, _T_1169)
node _T_1187 = or(_T_1186, _T_1170)
node _T_1188 = or(_T_1187, _T_1171)
node _T_1189 = and(_T_1123, _T_1188)
node _T_1190 = or(UInt<1>(0h0), _T_1189)
node _T_1191 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1192 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_1193 = cvt(_T_1192)
node _T_1194 = and(_T_1193, asSInt(UInt<17>(0h10000)))
node _T_1195 = asSInt(_T_1194)
node _T_1196 = eq(_T_1195, asSInt(UInt<1>(0h0)))
node _T_1197 = and(_T_1191, _T_1196)
node _T_1198 = or(UInt<1>(0h0), _T_1197)
node _T_1199 = and(_T_1190, _T_1198)
node _T_1200 = asUInt(reset)
node _T_1201 = eq(_T_1200, UInt<1>(0h0))
when _T_1201 :
node _T_1202 = eq(_T_1199, UInt<1>(0h0))
when _T_1202 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1199, UInt<1>(0h1), "") : assert_46
node _T_1203 = asUInt(reset)
node _T_1204 = eq(_T_1203, UInt<1>(0h0))
when _T_1204 :
node _T_1205 = eq(source_ok, UInt<1>(0h0))
when _T_1205 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1206 = asUInt(reset)
node _T_1207 = eq(_T_1206, UInt<1>(0h0))
when _T_1207 :
node _T_1208 = eq(is_aligned, UInt<1>(0h0))
when _T_1208 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1209 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1210 = asUInt(reset)
node _T_1211 = eq(_T_1210, UInt<1>(0h0))
when _T_1211 :
node _T_1212 = eq(_T_1209, UInt<1>(0h0))
when _T_1212 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1209, UInt<1>(0h1), "") : assert_49
node _T_1213 = eq(io.in.a.bits.mask, mask)
node _T_1214 = asUInt(reset)
node _T_1215 = eq(_T_1214, UInt<1>(0h0))
when _T_1215 :
node _T_1216 = eq(_T_1213, UInt<1>(0h0))
when _T_1216 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1213, UInt<1>(0h1), "") : assert_50
node _T_1217 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1218 = asUInt(reset)
node _T_1219 = eq(_T_1218, UInt<1>(0h0))
when _T_1219 :
node _T_1220 = eq(_T_1217, UInt<1>(0h0))
when _T_1220 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1217, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1221 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1222 = asUInt(reset)
node _T_1223 = eq(_T_1222, UInt<1>(0h0))
when _T_1223 :
node _T_1224 = eq(_T_1221, UInt<1>(0h0))
when _T_1224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1221, UInt<1>(0h1), "") : assert_52
node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_65 = shr(io.in.d.bits.source, 2)
node _source_ok_T_66 = eq(_source_ok_T_65, UInt<1>(0h0))
node _source_ok_T_67 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67)
node _source_ok_T_69 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_71 = shr(io.in.d.bits.source, 2)
node _source_ok_T_72 = eq(_source_ok_T_71, UInt<1>(0h1))
node _source_ok_T_73 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73)
node _source_ok_T_75 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_77 = shr(io.in.d.bits.source, 2)
node _source_ok_T_78 = eq(_source_ok_T_77, UInt<2>(0h2))
node _source_ok_T_79 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79)
node _source_ok_T_81 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_83 = shr(io.in.d.bits.source, 2)
node _source_ok_T_84 = eq(_source_ok_T_83, UInt<2>(0h3))
node _source_ok_T_85 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_86 = and(_source_ok_T_84, _source_ok_T_85)
node _source_ok_T_87 = leq(source_ok_uncommonBits_9, UInt<2>(0h3))
node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87)
node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<7>(0h44))
node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<7>(0h45))
node _source_ok_T_91 = eq(io.in.d.bits.source, UInt<7>(0h46))
node _source_ok_T_92 = eq(io.in.d.bits.source, UInt<7>(0h40))
node _source_ok_T_93 = eq(io.in.d.bits.source, UInt<7>(0h41))
node _source_ok_T_94 = eq(io.in.d.bits.source, UInt<7>(0h42))
node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 2, 0)
node _source_ok_T_95 = shr(io.in.d.bits.source, 3)
node _source_ok_T_96 = eq(_source_ok_T_95, UInt<3>(0h6))
node _source_ok_T_97 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_98 = and(_source_ok_T_96, _source_ok_T_97)
node _source_ok_T_99 = leq(source_ok_uncommonBits_10, UInt<3>(0h4))
node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99)
node _source_ok_T_101 = eq(io.in.d.bits.source, UInt<6>(0h35))
node _source_ok_T_102 = eq(io.in.d.bits.source, UInt<6>(0h38))
node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<3>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 2, 0)
node _source_ok_T_103 = shr(io.in.d.bits.source, 3)
node _source_ok_T_104 = eq(_source_ok_T_103, UInt<3>(0h4))
node _source_ok_T_105 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_106 = and(_source_ok_T_104, _source_ok_T_105)
node _source_ok_T_107 = leq(source_ok_uncommonBits_11, UInt<3>(0h4))
node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107)
node _source_ok_T_109 = eq(io.in.d.bits.source, UInt<6>(0h25))
node _source_ok_T_110 = eq(io.in.d.bits.source, UInt<6>(0h28))
node _source_ok_T_111 = eq(io.in.d.bits.source, UInt<8>(0h80))
wire _source_ok_WIRE_1 : UInt<1>[18]
connect _source_ok_WIRE_1[0], _source_ok_T_64
connect _source_ok_WIRE_1[1], _source_ok_T_70
connect _source_ok_WIRE_1[2], _source_ok_T_76
connect _source_ok_WIRE_1[3], _source_ok_T_82
connect _source_ok_WIRE_1[4], _source_ok_T_88
connect _source_ok_WIRE_1[5], _source_ok_T_89
connect _source_ok_WIRE_1[6], _source_ok_T_90
connect _source_ok_WIRE_1[7], _source_ok_T_91
connect _source_ok_WIRE_1[8], _source_ok_T_92
connect _source_ok_WIRE_1[9], _source_ok_T_93
connect _source_ok_WIRE_1[10], _source_ok_T_94
connect _source_ok_WIRE_1[11], _source_ok_T_100
connect _source_ok_WIRE_1[12], _source_ok_T_101
connect _source_ok_WIRE_1[13], _source_ok_T_102
connect _source_ok_WIRE_1[14], _source_ok_T_108
connect _source_ok_WIRE_1[15], _source_ok_T_109
connect _source_ok_WIRE_1[16], _source_ok_T_110
connect _source_ok_WIRE_1[17], _source_ok_T_111
node _source_ok_T_112 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_113 = or(_source_ok_T_112, _source_ok_WIRE_1[2])
node _source_ok_T_114 = or(_source_ok_T_113, _source_ok_WIRE_1[3])
node _source_ok_T_115 = or(_source_ok_T_114, _source_ok_WIRE_1[4])
node _source_ok_T_116 = or(_source_ok_T_115, _source_ok_WIRE_1[5])
node _source_ok_T_117 = or(_source_ok_T_116, _source_ok_WIRE_1[6])
node _source_ok_T_118 = or(_source_ok_T_117, _source_ok_WIRE_1[7])
node _source_ok_T_119 = or(_source_ok_T_118, _source_ok_WIRE_1[8])
node _source_ok_T_120 = or(_source_ok_T_119, _source_ok_WIRE_1[9])
node _source_ok_T_121 = or(_source_ok_T_120, _source_ok_WIRE_1[10])
node _source_ok_T_122 = or(_source_ok_T_121, _source_ok_WIRE_1[11])
node _source_ok_T_123 = or(_source_ok_T_122, _source_ok_WIRE_1[12])
node _source_ok_T_124 = or(_source_ok_T_123, _source_ok_WIRE_1[13])
node _source_ok_T_125 = or(_source_ok_T_124, _source_ok_WIRE_1[14])
node _source_ok_T_126 = or(_source_ok_T_125, _source_ok_WIRE_1[15])
node _source_ok_T_127 = or(_source_ok_T_126, _source_ok_WIRE_1[16])
node source_ok_1 = or(_source_ok_T_127, _source_ok_WIRE_1[17])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1225 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1225 :
node _T_1226 = asUInt(reset)
node _T_1227 = eq(_T_1226, UInt<1>(0h0))
when _T_1227 :
node _T_1228 = eq(source_ok_1, UInt<1>(0h0))
when _T_1228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1229 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1230 = asUInt(reset)
node _T_1231 = eq(_T_1230, UInt<1>(0h0))
when _T_1231 :
node _T_1232 = eq(_T_1229, UInt<1>(0h0))
when _T_1232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1229, UInt<1>(0h1), "") : assert_54
node _T_1233 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1234 = asUInt(reset)
node _T_1235 = eq(_T_1234, UInt<1>(0h0))
when _T_1235 :
node _T_1236 = eq(_T_1233, UInt<1>(0h0))
when _T_1236 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1233, UInt<1>(0h1), "") : assert_55
node _T_1237 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1238 = asUInt(reset)
node _T_1239 = eq(_T_1238, UInt<1>(0h0))
when _T_1239 :
node _T_1240 = eq(_T_1237, UInt<1>(0h0))
when _T_1240 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1237, UInt<1>(0h1), "") : assert_56
node _T_1241 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1242 = asUInt(reset)
node _T_1243 = eq(_T_1242, UInt<1>(0h0))
when _T_1243 :
node _T_1244 = eq(_T_1241, UInt<1>(0h0))
when _T_1244 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1241, UInt<1>(0h1), "") : assert_57
node _T_1245 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1245 :
node _T_1246 = asUInt(reset)
node _T_1247 = eq(_T_1246, UInt<1>(0h0))
when _T_1247 :
node _T_1248 = eq(source_ok_1, UInt<1>(0h0))
when _T_1248 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1249 = asUInt(reset)
node _T_1250 = eq(_T_1249, UInt<1>(0h0))
when _T_1250 :
node _T_1251 = eq(sink_ok, UInt<1>(0h0))
when _T_1251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1252 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1253 = asUInt(reset)
node _T_1254 = eq(_T_1253, UInt<1>(0h0))
when _T_1254 :
node _T_1255 = eq(_T_1252, UInt<1>(0h0))
when _T_1255 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1252, UInt<1>(0h1), "") : assert_60
node _T_1256 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1257 = asUInt(reset)
node _T_1258 = eq(_T_1257, UInt<1>(0h0))
when _T_1258 :
node _T_1259 = eq(_T_1256, UInt<1>(0h0))
when _T_1259 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1256, UInt<1>(0h1), "") : assert_61
node _T_1260 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1261 = asUInt(reset)
node _T_1262 = eq(_T_1261, UInt<1>(0h0))
when _T_1262 :
node _T_1263 = eq(_T_1260, UInt<1>(0h0))
when _T_1263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1260, UInt<1>(0h1), "") : assert_62
node _T_1264 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1265 = asUInt(reset)
node _T_1266 = eq(_T_1265, UInt<1>(0h0))
when _T_1266 :
node _T_1267 = eq(_T_1264, UInt<1>(0h0))
when _T_1267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1264, UInt<1>(0h1), "") : assert_63
node _T_1268 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1269 = or(UInt<1>(0h0), _T_1268)
node _T_1270 = asUInt(reset)
node _T_1271 = eq(_T_1270, UInt<1>(0h0))
when _T_1271 :
node _T_1272 = eq(_T_1269, UInt<1>(0h0))
when _T_1272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1269, UInt<1>(0h1), "") : assert_64
node _T_1273 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1273 :
node _T_1274 = asUInt(reset)
node _T_1275 = eq(_T_1274, UInt<1>(0h0))
when _T_1275 :
node _T_1276 = eq(source_ok_1, UInt<1>(0h0))
when _T_1276 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1277 = asUInt(reset)
node _T_1278 = eq(_T_1277, UInt<1>(0h0))
when _T_1278 :
node _T_1279 = eq(sink_ok, UInt<1>(0h0))
when _T_1279 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1280 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1281 = asUInt(reset)
node _T_1282 = eq(_T_1281, UInt<1>(0h0))
when _T_1282 :
node _T_1283 = eq(_T_1280, UInt<1>(0h0))
when _T_1283 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1280, UInt<1>(0h1), "") : assert_67
node _T_1284 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1285 = asUInt(reset)
node _T_1286 = eq(_T_1285, UInt<1>(0h0))
when _T_1286 :
node _T_1287 = eq(_T_1284, UInt<1>(0h0))
when _T_1287 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1284, UInt<1>(0h1), "") : assert_68
node _T_1288 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1289 = asUInt(reset)
node _T_1290 = eq(_T_1289, UInt<1>(0h0))
when _T_1290 :
node _T_1291 = eq(_T_1288, UInt<1>(0h0))
when _T_1291 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1288, UInt<1>(0h1), "") : assert_69
node _T_1292 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1293 = or(_T_1292, io.in.d.bits.corrupt)
node _T_1294 = asUInt(reset)
node _T_1295 = eq(_T_1294, UInt<1>(0h0))
when _T_1295 :
node _T_1296 = eq(_T_1293, UInt<1>(0h0))
when _T_1296 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1293, UInt<1>(0h1), "") : assert_70
node _T_1297 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1298 = or(UInt<1>(0h0), _T_1297)
node _T_1299 = asUInt(reset)
node _T_1300 = eq(_T_1299, UInt<1>(0h0))
when _T_1300 :
node _T_1301 = eq(_T_1298, UInt<1>(0h0))
when _T_1301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1298, UInt<1>(0h1), "") : assert_71
node _T_1302 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1302 :
node _T_1303 = asUInt(reset)
node _T_1304 = eq(_T_1303, UInt<1>(0h0))
when _T_1304 :
node _T_1305 = eq(source_ok_1, UInt<1>(0h0))
when _T_1305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1306 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1307 = asUInt(reset)
node _T_1308 = eq(_T_1307, UInt<1>(0h0))
when _T_1308 :
node _T_1309 = eq(_T_1306, UInt<1>(0h0))
when _T_1309 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1306, UInt<1>(0h1), "") : assert_73
node _T_1310 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1311 = asUInt(reset)
node _T_1312 = eq(_T_1311, UInt<1>(0h0))
when _T_1312 :
node _T_1313 = eq(_T_1310, UInt<1>(0h0))
when _T_1313 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1310, UInt<1>(0h1), "") : assert_74
node _T_1314 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1315 = or(UInt<1>(0h0), _T_1314)
node _T_1316 = asUInt(reset)
node _T_1317 = eq(_T_1316, UInt<1>(0h0))
when _T_1317 :
node _T_1318 = eq(_T_1315, UInt<1>(0h0))
when _T_1318 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1315, UInt<1>(0h1), "") : assert_75
node _T_1319 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1319 :
node _T_1320 = asUInt(reset)
node _T_1321 = eq(_T_1320, UInt<1>(0h0))
when _T_1321 :
node _T_1322 = eq(source_ok_1, UInt<1>(0h0))
when _T_1322 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1323 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1324 = asUInt(reset)
node _T_1325 = eq(_T_1324, UInt<1>(0h0))
when _T_1325 :
node _T_1326 = eq(_T_1323, UInt<1>(0h0))
when _T_1326 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1323, UInt<1>(0h1), "") : assert_77
node _T_1327 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1328 = or(_T_1327, io.in.d.bits.corrupt)
node _T_1329 = asUInt(reset)
node _T_1330 = eq(_T_1329, UInt<1>(0h0))
when _T_1330 :
node _T_1331 = eq(_T_1328, UInt<1>(0h0))
when _T_1331 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1328, UInt<1>(0h1), "") : assert_78
node _T_1332 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1333 = or(UInt<1>(0h0), _T_1332)
node _T_1334 = asUInt(reset)
node _T_1335 = eq(_T_1334, UInt<1>(0h0))
when _T_1335 :
node _T_1336 = eq(_T_1333, UInt<1>(0h0))
when _T_1336 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1333, UInt<1>(0h1), "") : assert_79
node _T_1337 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1337 :
node _T_1338 = asUInt(reset)
node _T_1339 = eq(_T_1338, UInt<1>(0h0))
when _T_1339 :
node _T_1340 = eq(source_ok_1, UInt<1>(0h0))
when _T_1340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1341 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1342 = asUInt(reset)
node _T_1343 = eq(_T_1342, UInt<1>(0h0))
when _T_1343 :
node _T_1344 = eq(_T_1341, UInt<1>(0h0))
when _T_1344 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1341, UInt<1>(0h1), "") : assert_81
node _T_1345 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1346 = asUInt(reset)
node _T_1347 = eq(_T_1346, UInt<1>(0h0))
when _T_1347 :
node _T_1348 = eq(_T_1345, UInt<1>(0h0))
when _T_1348 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1345, UInt<1>(0h1), "") : assert_82
node _T_1349 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1350 = or(UInt<1>(0h0), _T_1349)
node _T_1351 = asUInt(reset)
node _T_1352 = eq(_T_1351, UInt<1>(0h0))
when _T_1352 :
node _T_1353 = eq(_T_1350, UInt<1>(0h0))
when _T_1353 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1350, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<26>(0h0)
connect _WIRE_4.bits.source, UInt<8>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<26>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1354 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1355 = asUInt(reset)
node _T_1356 = eq(_T_1355, UInt<1>(0h0))
when _T_1356 :
node _T_1357 = eq(_T_1354, UInt<1>(0h0))
when _T_1357 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1354, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<26>(0h0)
connect _WIRE_6.bits.source, UInt<8>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1358 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1359 = asUInt(reset)
node _T_1360 = eq(_T_1359, UInt<1>(0h0))
when _T_1360 :
node _T_1361 = eq(_T_1358, UInt<1>(0h0))
when _T_1361 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1358, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1362 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1363 = asUInt(reset)
node _T_1364 = eq(_T_1363, UInt<1>(0h0))
when _T_1364 :
node _T_1365 = eq(_T_1362, UInt<1>(0h0))
when _T_1365 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1362, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1366 = eq(a_first, UInt<1>(0h0))
node _T_1367 = and(io.in.a.valid, _T_1366)
when _T_1367 :
node _T_1368 = eq(io.in.a.bits.opcode, opcode)
node _T_1369 = asUInt(reset)
node _T_1370 = eq(_T_1369, UInt<1>(0h0))
when _T_1370 :
node _T_1371 = eq(_T_1368, UInt<1>(0h0))
when _T_1371 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1368, UInt<1>(0h1), "") : assert_87
node _T_1372 = eq(io.in.a.bits.param, param)
node _T_1373 = asUInt(reset)
node _T_1374 = eq(_T_1373, UInt<1>(0h0))
when _T_1374 :
node _T_1375 = eq(_T_1372, UInt<1>(0h0))
when _T_1375 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1372, UInt<1>(0h1), "") : assert_88
node _T_1376 = eq(io.in.a.bits.size, size)
node _T_1377 = asUInt(reset)
node _T_1378 = eq(_T_1377, UInt<1>(0h0))
when _T_1378 :
node _T_1379 = eq(_T_1376, UInt<1>(0h0))
when _T_1379 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1376, UInt<1>(0h1), "") : assert_89
node _T_1380 = eq(io.in.a.bits.source, source)
node _T_1381 = asUInt(reset)
node _T_1382 = eq(_T_1381, UInt<1>(0h0))
when _T_1382 :
node _T_1383 = eq(_T_1380, UInt<1>(0h0))
when _T_1383 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1380, UInt<1>(0h1), "") : assert_90
node _T_1384 = eq(io.in.a.bits.address, address)
node _T_1385 = asUInt(reset)
node _T_1386 = eq(_T_1385, UInt<1>(0h0))
when _T_1386 :
node _T_1387 = eq(_T_1384, UInt<1>(0h0))
when _T_1387 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1384, UInt<1>(0h1), "") : assert_91
node _T_1388 = and(io.in.a.ready, io.in.a.valid)
node _T_1389 = and(_T_1388, a_first)
when _T_1389 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1390 = eq(d_first, UInt<1>(0h0))
node _T_1391 = and(io.in.d.valid, _T_1390)
when _T_1391 :
node _T_1392 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1393 = asUInt(reset)
node _T_1394 = eq(_T_1393, UInt<1>(0h0))
when _T_1394 :
node _T_1395 = eq(_T_1392, UInt<1>(0h0))
when _T_1395 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1392, UInt<1>(0h1), "") : assert_92
node _T_1396 = eq(io.in.d.bits.param, param_1)
node _T_1397 = asUInt(reset)
node _T_1398 = eq(_T_1397, UInt<1>(0h0))
when _T_1398 :
node _T_1399 = eq(_T_1396, UInt<1>(0h0))
when _T_1399 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1396, UInt<1>(0h1), "") : assert_93
node _T_1400 = eq(io.in.d.bits.size, size_1)
node _T_1401 = asUInt(reset)
node _T_1402 = eq(_T_1401, UInt<1>(0h0))
when _T_1402 :
node _T_1403 = eq(_T_1400, UInt<1>(0h0))
when _T_1403 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1400, UInt<1>(0h1), "") : assert_94
node _T_1404 = eq(io.in.d.bits.source, source_1)
node _T_1405 = asUInt(reset)
node _T_1406 = eq(_T_1405, UInt<1>(0h0))
when _T_1406 :
node _T_1407 = eq(_T_1404, UInt<1>(0h0))
when _T_1407 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1404, UInt<1>(0h1), "") : assert_95
node _T_1408 = eq(io.in.d.bits.sink, sink)
node _T_1409 = asUInt(reset)
node _T_1410 = eq(_T_1409, UInt<1>(0h0))
when _T_1410 :
node _T_1411 = eq(_T_1408, UInt<1>(0h0))
when _T_1411 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1408, UInt<1>(0h1), "") : assert_96
node _T_1412 = eq(io.in.d.bits.denied, denied)
node _T_1413 = asUInt(reset)
node _T_1414 = eq(_T_1413, UInt<1>(0h0))
when _T_1414 :
node _T_1415 = eq(_T_1412, UInt<1>(0h0))
when _T_1415 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1412, UInt<1>(0h1), "") : assert_97
node _T_1416 = and(io.in.d.ready, io.in.d.valid)
node _T_1417 = and(_T_1416, d_first)
when _T_1417 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0)
regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0)
regreset inflight_sizes : UInt<516>, clock, reset, UInt<516>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<129>
connect a_set, UInt<129>(0h0)
wire a_set_wo_ready : UInt<129>
connect a_set_wo_ready, UInt<129>(0h0)
wire a_opcodes_set : UInt<516>
connect a_opcodes_set, UInt<516>(0h0)
wire a_sizes_set : UInt<516>
connect a_sizes_set, UInt<516>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1418 = and(io.in.a.valid, a_first_1)
node _T_1419 = and(_T_1418, UInt<1>(0h1))
when _T_1419 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1420 = and(io.in.a.ready, io.in.a.valid)
node _T_1421 = and(_T_1420, a_first_1)
node _T_1422 = and(_T_1421, UInt<1>(0h1))
when _T_1422 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1423 = dshr(inflight, io.in.a.bits.source)
node _T_1424 = bits(_T_1423, 0, 0)
node _T_1425 = eq(_T_1424, UInt<1>(0h0))
node _T_1426 = asUInt(reset)
node _T_1427 = eq(_T_1426, UInt<1>(0h0))
when _T_1427 :
node _T_1428 = eq(_T_1425, UInt<1>(0h0))
when _T_1428 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1425, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<129>
connect d_clr, UInt<129>(0h0)
wire d_clr_wo_ready : UInt<129>
connect d_clr_wo_ready, UInt<129>(0h0)
wire d_opcodes_clr : UInt<516>
connect d_opcodes_clr, UInt<516>(0h0)
wire d_sizes_clr : UInt<516>
connect d_sizes_clr, UInt<516>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1429 = and(io.in.d.valid, d_first_1)
node _T_1430 = and(_T_1429, UInt<1>(0h1))
node _T_1431 = eq(d_release_ack, UInt<1>(0h0))
node _T_1432 = and(_T_1430, _T_1431)
when _T_1432 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1433 = and(io.in.d.ready, io.in.d.valid)
node _T_1434 = and(_T_1433, d_first_1)
node _T_1435 = and(_T_1434, UInt<1>(0h1))
node _T_1436 = eq(d_release_ack, UInt<1>(0h0))
node _T_1437 = and(_T_1435, _T_1436)
when _T_1437 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1438 = and(io.in.d.valid, d_first_1)
node _T_1439 = and(_T_1438, UInt<1>(0h1))
node _T_1440 = eq(d_release_ack, UInt<1>(0h0))
node _T_1441 = and(_T_1439, _T_1440)
when _T_1441 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1442 = dshr(inflight, io.in.d.bits.source)
node _T_1443 = bits(_T_1442, 0, 0)
node _T_1444 = or(_T_1443, same_cycle_resp)
node _T_1445 = asUInt(reset)
node _T_1446 = eq(_T_1445, UInt<1>(0h0))
when _T_1446 :
node _T_1447 = eq(_T_1444, UInt<1>(0h0))
when _T_1447 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1444, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1448 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1449 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1450 = or(_T_1448, _T_1449)
node _T_1451 = asUInt(reset)
node _T_1452 = eq(_T_1451, UInt<1>(0h0))
when _T_1452 :
node _T_1453 = eq(_T_1450, UInt<1>(0h0))
when _T_1453 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1450, UInt<1>(0h1), "") : assert_100
node _T_1454 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1455 = asUInt(reset)
node _T_1456 = eq(_T_1455, UInt<1>(0h0))
when _T_1456 :
node _T_1457 = eq(_T_1454, UInt<1>(0h0))
when _T_1457 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1454, UInt<1>(0h1), "") : assert_101
else :
node _T_1458 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1459 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1460 = or(_T_1458, _T_1459)
node _T_1461 = asUInt(reset)
node _T_1462 = eq(_T_1461, UInt<1>(0h0))
when _T_1462 :
node _T_1463 = eq(_T_1460, UInt<1>(0h0))
when _T_1463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1460, UInt<1>(0h1), "") : assert_102
node _T_1464 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1465 = asUInt(reset)
node _T_1466 = eq(_T_1465, UInt<1>(0h0))
when _T_1466 :
node _T_1467 = eq(_T_1464, UInt<1>(0h0))
when _T_1467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1464, UInt<1>(0h1), "") : assert_103
node _T_1468 = and(io.in.d.valid, d_first_1)
node _T_1469 = and(_T_1468, a_first_1)
node _T_1470 = and(_T_1469, io.in.a.valid)
node _T_1471 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1472 = and(_T_1470, _T_1471)
node _T_1473 = eq(d_release_ack, UInt<1>(0h0))
node _T_1474 = and(_T_1472, _T_1473)
when _T_1474 :
node _T_1475 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1476 = or(_T_1475, io.in.a.ready)
node _T_1477 = asUInt(reset)
node _T_1478 = eq(_T_1477, UInt<1>(0h0))
when _T_1478 :
node _T_1479 = eq(_T_1476, UInt<1>(0h0))
when _T_1479 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1476, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_56
node _T_1480 = orr(inflight)
node _T_1481 = eq(_T_1480, UInt<1>(0h0))
node _T_1482 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1483 = or(_T_1481, _T_1482)
node _T_1484 = lt(watchdog, plusarg_reader.out)
node _T_1485 = or(_T_1483, _T_1484)
node _T_1486 = asUInt(reset)
node _T_1487 = eq(_T_1486, UInt<1>(0h0))
when _T_1487 :
node _T_1488 = eq(_T_1485, UInt<1>(0h0))
when _T_1488 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1485, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1489 = and(io.in.a.ready, io.in.a.valid)
node _T_1490 = and(io.in.d.ready, io.in.d.valid)
node _T_1491 = or(_T_1489, _T_1490)
when _T_1491 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0)
regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0)
regreset inflight_sizes_1 : UInt<516>, clock, reset, UInt<516>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<26>(0h0)
connect _c_first_WIRE.bits.source, UInt<8>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<26>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<8>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<129>
connect c_set, UInt<129>(0h0)
wire c_set_wo_ready : UInt<129>
connect c_set_wo_ready, UInt<129>(0h0)
wire c_opcodes_set : UInt<516>
connect c_opcodes_set, UInt<516>(0h0)
wire c_sizes_set : UInt<516>
connect c_sizes_set, UInt<516>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<26>(0h0)
connect _WIRE_10.bits.source, UInt<8>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1492 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<26>(0h0)
connect _WIRE_12.bits.source, UInt<8>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1493 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1494 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1495 = and(_T_1493, _T_1494)
node _T_1496 = and(_T_1492, _T_1495)
when _T_1496 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<26>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<26>(0h0)
connect _WIRE_14.bits.source, UInt<8>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1497 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1498 = and(_T_1497, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<26>(0h0)
connect _WIRE_16.bits.source, UInt<8>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1499 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1500 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1501 = and(_T_1499, _T_1500)
node _T_1502 = and(_T_1498, _T_1501)
when _T_1502 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<26>(0h0)
connect _c_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<26>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<26>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<26>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<26>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<26>(0h0)
connect _WIRE_18.bits.source, UInt<8>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1503 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1504 = bits(_T_1503, 0, 0)
node _T_1505 = eq(_T_1504, UInt<1>(0h0))
node _T_1506 = asUInt(reset)
node _T_1507 = eq(_T_1506, UInt<1>(0h0))
when _T_1507 :
node _T_1508 = eq(_T_1505, UInt<1>(0h0))
when _T_1508 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1505, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<26>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<26>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<129>
connect d_clr_1, UInt<129>(0h0)
wire d_clr_wo_ready_1 : UInt<129>
connect d_clr_wo_ready_1, UInt<129>(0h0)
wire d_opcodes_clr_1 : UInt<516>
connect d_opcodes_clr_1, UInt<516>(0h0)
wire d_sizes_clr_1 : UInt<516>
connect d_sizes_clr_1, UInt<516>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1509 = and(io.in.d.valid, d_first_2)
node _T_1510 = and(_T_1509, UInt<1>(0h1))
node _T_1511 = and(_T_1510, d_release_ack_1)
when _T_1511 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1512 = and(io.in.d.ready, io.in.d.valid)
node _T_1513 = and(_T_1512, d_first_2)
node _T_1514 = and(_T_1513, UInt<1>(0h1))
node _T_1515 = and(_T_1514, d_release_ack_1)
when _T_1515 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1516 = and(io.in.d.valid, d_first_2)
node _T_1517 = and(_T_1516, UInt<1>(0h1))
node _T_1518 = and(_T_1517, d_release_ack_1)
when _T_1518 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<26>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<26>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<26>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1519 = dshr(inflight_1, io.in.d.bits.source)
node _T_1520 = bits(_T_1519, 0, 0)
node _T_1521 = or(_T_1520, same_cycle_resp_1)
node _T_1522 = asUInt(reset)
node _T_1523 = eq(_T_1522, UInt<1>(0h0))
when _T_1523 :
node _T_1524 = eq(_T_1521, UInt<1>(0h0))
when _T_1524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_1521, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<26>(0h0)
connect _WIRE_20.bits.source, UInt<8>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1525 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1526 = asUInt(reset)
node _T_1527 = eq(_T_1526, UInt<1>(0h0))
when _T_1527 :
node _T_1528 = eq(_T_1525, UInt<1>(0h0))
when _T_1528 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1525, UInt<1>(0h1), "") : assert_108
else :
node _T_1529 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1530 = asUInt(reset)
node _T_1531 = eq(_T_1530, UInt<1>(0h0))
when _T_1531 :
node _T_1532 = eq(_T_1529, UInt<1>(0h0))
when _T_1532 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1529, UInt<1>(0h1), "") : assert_109
node _T_1533 = and(io.in.d.valid, d_first_2)
node _T_1534 = and(_T_1533, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<26>(0h0)
connect _WIRE_22.bits.source, UInt<8>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1535 = and(_T_1534, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<26>(0h0)
connect _WIRE_24.bits.source, UInt<8>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1536 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1537 = and(_T_1535, _T_1536)
node _T_1538 = and(_T_1537, d_release_ack_1)
node _T_1539 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1540 = and(_T_1538, _T_1539)
when _T_1540 :
node _T_1541 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<26>(0h0)
connect _WIRE_26.bits.source, UInt<8>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1542 = or(_T_1541, _WIRE_27.ready)
node _T_1543 = asUInt(reset)
node _T_1544 = eq(_T_1543, UInt<1>(0h0))
when _T_1544 :
node _T_1545 = eq(_T_1542, UInt<1>(0h0))
when _T_1545 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1542, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_57
node _T_1546 = orr(inflight_1)
node _T_1547 = eq(_T_1546, UInt<1>(0h0))
node _T_1548 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1549 = or(_T_1547, _T_1548)
node _T_1550 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1551 = or(_T_1549, _T_1550)
node _T_1552 = asUInt(reset)
node _T_1553 = eq(_T_1552, UInt<1>(0h0))
when _T_1553 :
node _T_1554 = eq(_T_1551, UInt<1>(0h0))
when _T_1554 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/CLINT.scala:113:101)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1551, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<26>(0h0)
connect _WIRE_28.bits.source, UInt<8>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<26>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1555 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1556 = and(io.in.d.ready, io.in.d.valid)
node _T_1557 = or(_T_1555, _T_1556)
when _T_1557 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_28( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [25:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [25:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_33 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_41 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_97 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_105 = 1'h1; // @[Parameters.scala:56:32]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_first_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_first_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_first_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_first_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_set_wo_ready_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_set_wo_ready_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_opcodes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_opcodes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_sizes_set_interm_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_sizes_set_interm_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_opcodes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_opcodes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_sizes_set_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_sizes_set_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_probe_ack_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_probe_ack_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _c_probe_ack_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _c_probe_ack_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_1_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_2_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_3_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [25:0] _same_cycle_resp_WIRE_4_bits_address = 26'h0; // @[Bundles.scala:265:74]
wire [25:0] _same_cycle_resp_WIRE_5_bits_address = 26'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74]
wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54]
wire [2050:0] _c_sizes_set_T_1 = 2051'h0; // @[Monitor.scala:768:52]
wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79]
wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35]
wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35]
wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34]
wire [515:0] c_sizes_set = 516'h0; // @[Monitor.scala:741:34]
wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34]
wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 8'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 6'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 6'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 6'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 6'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 8'h44; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 8'h45; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire _source_ok_T_27 = io_in_a_bits_source_0 == 8'h46; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31]
wire _source_ok_T_28 = io_in_a_bits_source_0 == 8'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31]
wire _source_ok_T_29 = io_in_a_bits_source_0 == 8'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31]
wire _source_ok_T_30 = io_in_a_bits_source_0 == 8'h42; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_31 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_39 = io_in_a_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_32 = _source_ok_T_31 == 5'h6; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_34 = _source_ok_T_32; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_35 = source_ok_uncommonBits_4 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_36 = _source_ok_T_34 & _source_ok_T_35; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_11 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire _source_ok_T_37 = io_in_a_bits_source_0 == 8'h35; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_12 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire _source_ok_T_38 = io_in_a_bits_source_0 == 8'h38; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_13 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_40 = _source_ok_T_39 == 5'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_42 = _source_ok_T_40; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_43 = source_ok_uncommonBits_5 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_44 = _source_ok_T_42 & _source_ok_T_43; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_14 = _source_ok_T_44; // @[Parameters.scala:1138:31]
wire _source_ok_T_45 = io_in_a_bits_source_0 == 8'h25; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_15 = _source_ok_T_45; // @[Parameters.scala:1138:31]
wire _source_ok_T_46 = io_in_a_bits_source_0 == 8'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_16 = _source_ok_T_46; // @[Parameters.scala:1138:31]
wire _source_ok_T_47 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_17 = _source_ok_T_47; // @[Parameters.scala:1138:31]
wire _source_ok_T_48 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_56 = _source_ok_T_55 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_57 = _source_ok_T_56 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_58 = _source_ok_T_57 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_59 = _source_ok_T_58 | _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_60 = _source_ok_T_59 | _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_61 = _source_ok_T_60 | _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_62 = _source_ok_T_61 | _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_63 | _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [25:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 26'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_5 = _uncommonBits_T_5[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_10 = _uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_11 = _uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_16 = _uncommonBits_T_16[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_17 = _uncommonBits_T_17[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_22 = _uncommonBits_T_22[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_23 = _uncommonBits_T_23[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_28 = _uncommonBits_T_28[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_35 = _uncommonBits_T_35[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_40 = _uncommonBits_T_40[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_41 = _uncommonBits_T_41[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_46 = _uncommonBits_T_46[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_47 = _uncommonBits_T_47[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_52 = _uncommonBits_T_52[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_53 = _uncommonBits_T_53[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_58 = _uncommonBits_T_58[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_59 = _uncommonBits_T_59[2:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_64 = _uncommonBits_T_64[2:0]; // @[Parameters.scala:52:{29,56}]
wire [2:0] uncommonBits_65 = _uncommonBits_T_65[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_64 = io_in_d_bits_source_0 == 8'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_64; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [5:0] _source_ok_T_65 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_71 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_77 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire [5:0] _source_ok_T_83 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_66 = _source_ok_T_65 == 6'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_70; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_72 = _source_ok_T_71 == 6'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_76; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_78 = _source_ok_T_77 == 6'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_82; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_84 = _source_ok_T_83 == 6'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_88; // @[Parameters.scala:1138:31]
wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h44; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_89; // @[Parameters.scala:1138:31]
wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h45; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire _source_ok_T_91 = io_in_d_bits_source_0 == 8'h46; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_91; // @[Parameters.scala:1138:31]
wire _source_ok_T_92 = io_in_d_bits_source_0 == 8'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_92; // @[Parameters.scala:1138:31]
wire _source_ok_T_93 = io_in_d_bits_source_0 == 8'h41; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_93; // @[Parameters.scala:1138:31]
wire _source_ok_T_94 = io_in_d_bits_source_0 == 8'h42; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_94; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[2:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_95 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_103 = io_in_d_bits_source_0[7:3]; // @[Monitor.scala:36:7]
wire _source_ok_T_96 = _source_ok_T_95 == 5'h6; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_98 = _source_ok_T_96; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_99 = source_ok_uncommonBits_10 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_100 = _source_ok_T_98 & _source_ok_T_99; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_11 = _source_ok_T_100; // @[Parameters.scala:1138:31]
wire _source_ok_T_101 = io_in_d_bits_source_0 == 8'h35; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_12 = _source_ok_T_101; // @[Parameters.scala:1138:31]
wire _source_ok_T_102 = io_in_d_bits_source_0 == 8'h38; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_13 = _source_ok_T_102; // @[Parameters.scala:1138:31]
wire [2:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[2:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_104 = _source_ok_T_103 == 5'h4; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_106 = _source_ok_T_104; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_107 = source_ok_uncommonBits_11 < 3'h5; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_108 = _source_ok_T_106 & _source_ok_T_107; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_14 = _source_ok_T_108; // @[Parameters.scala:1138:31]
wire _source_ok_T_109 = io_in_d_bits_source_0 == 8'h25; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_15 = _source_ok_T_109; // @[Parameters.scala:1138:31]
wire _source_ok_T_110 = io_in_d_bits_source_0 == 8'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_16 = _source_ok_T_110; // @[Parameters.scala:1138:31]
wire _source_ok_T_111 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_17 = _source_ok_T_111; // @[Parameters.scala:1138:31]
wire _source_ok_T_112 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_113 = _source_ok_T_112 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_114 = _source_ok_T_113 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_115 = _source_ok_T_114 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_116 = _source_ok_T_115 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_117 = _source_ok_T_116 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_118 = _source_ok_T_117 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_119 = _source_ok_T_118 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_120 = _source_ok_T_119 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_121 = _source_ok_T_120 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_122 = _source_ok_T_121 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_123 = _source_ok_T_122 | _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_124 = _source_ok_T_123 | _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_125 = _source_ok_T_124 | _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_126 = _source_ok_T_125 | _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_127 = _source_ok_T_126 | _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_127 | _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1489 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1489; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1489; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [7:0] source; // @[Monitor.scala:390:22]
reg [25:0] address; // @[Monitor.scala:391:22]
wire _T_1557 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1557; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1557; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1557; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [7:0] source_1; // @[Monitor.scala:541:22]
reg [128:0] inflight; // @[Monitor.scala:614:27]
reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [515:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [128:0] a_set; // @[Monitor.scala:626:34]
wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [515:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [515:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [515:0] _a_size_lookup_T_6 = {512'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [515:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[515:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [255:0] _GEN_2 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [255:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1422 = _T_1489 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1422 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1422 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1422 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [10:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [10:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [10:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1422 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [2050:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1422 ? _a_sizes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [128:0] d_clr; // @[Monitor.scala:664:34]
wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [515:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1468 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1468 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1437 = _T_1557 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1437 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1437 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [2062:0] _d_sizes_clr_T_5 = 2063'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1437 ? _d_sizes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [515:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [515:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [515:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [128:0] inflight_1; // @[Monitor.scala:726:35]
wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [515:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [515:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [515:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [515:0] _c_size_lookup_T_6 = {512'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [515:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[515:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [128:0] d_clr_1; // @[Monitor.scala:774:34]
wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [515:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1533 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1533 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire _T_1515 = _T_1557 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1515 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35]
wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1515 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [2062:0] _d_sizes_clr_T_11 = 2063'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1515 ? _d_sizes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113]
wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [515:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [515:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_51 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_51( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_6 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], credit_return : UInt<8>, vc_free : UInt<8>}}
wire _in_flight_WIRE : UInt<1>[8]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
connect _in_flight_WIRE[2], UInt<1>(0h0)
connect _in_flight_WIRE[3], UInt<1>(0h0)
connect _in_flight_WIRE[4], UInt<1>(0h0)
connect _in_flight_WIRE[5], UInt<1>(0h0)
connect _in_flight_WIRE[6], UInt<1>(0h0)
connect _in_flight_WIRE[7], UInt<1>(0h0)
regreset in_flight : UInt<1>[8], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_8 = and(_T_6, _T_7)
node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_10 = and(_T_8, _T_9)
node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_12 = and(_T_10, _T_11)
node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_15 = and(_T_13, _T_14)
node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_19 = and(_T_17, _T_18)
node _T_20 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_21 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_24 = and(_T_22, _T_23)
node _T_25 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_26 = and(_T_24, _T_25)
node _T_27 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_28 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_29 = and(_T_27, _T_28)
node _T_30 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_33 = and(_T_31, _T_32)
node _T_34 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb))
node _T_35 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_36 = and(_T_34, _T_35)
node _T_37 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_38 = and(_T_36, _T_37)
node _T_39 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_40 = and(_T_38, _T_39)
node _T_41 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hd))
node _T_42 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_45 = and(_T_43, _T_44)
node _T_46 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_47 = and(_T_45, _T_46)
node _T_48 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_49 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_50 = and(_T_48, _T_49)
node _T_51 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_52 = and(_T_50, _T_51)
node _T_53 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_54 = and(_T_52, _T_53)
node _T_55 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_56 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_57 = and(_T_55, _T_56)
node _T_58 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_59 = and(_T_57, _T_58)
node _T_60 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_61 = and(_T_59, _T_60)
node _T_62 = or(_T_12, _T_19)
node _T_63 = or(_T_62, _T_26)
node _T_64 = or(_T_63, _T_33)
node _T_65 = or(_T_64, _T_40)
node _T_66 = or(_T_65, _T_47)
node _T_67 = or(_T_66, _T_54)
node _T_68 = or(_T_67, _T_61)
node _T_69 = or(_T_5, _T_68)
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_69, UInt<1>(0h1), "") : assert_1
node _T_73 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_74 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_75 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_76 = and(_T_74, _T_75)
node _T_77 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_78 = and(_T_76, _T_77)
node _T_79 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_80 = and(_T_78, _T_79)
node _T_81 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_82 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_83 = and(_T_81, _T_82)
node _T_84 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_85 = and(_T_83, _T_84)
node _T_86 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_87 = and(_T_85, _T_86)
node _T_88 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_89 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_90 = and(_T_88, _T_89)
node _T_91 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_92 = and(_T_90, _T_91)
node _T_93 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_94 = and(_T_92, _T_93)
node _T_95 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_96 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_97 = and(_T_95, _T_96)
node _T_98 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_99 = and(_T_97, _T_98)
node _T_100 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_101 = and(_T_99, _T_100)
node _T_102 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb))
node _T_103 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_104 = and(_T_102, _T_103)
node _T_105 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_106 = and(_T_104, _T_105)
node _T_107 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_108 = and(_T_106, _T_107)
node _T_109 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hd))
node _T_110 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_111 = and(_T_109, _T_110)
node _T_112 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_113 = and(_T_111, _T_112)
node _T_114 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_115 = and(_T_113, _T_114)
node _T_116 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_117 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_118 = and(_T_116, _T_117)
node _T_119 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_120 = and(_T_118, _T_119)
node _T_121 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_122 = and(_T_120, _T_121)
node _T_123 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_124 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_125 = and(_T_123, _T_124)
node _T_126 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_127 = and(_T_125, _T_126)
node _T_128 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_129 = and(_T_127, _T_128)
node _T_130 = or(_T_80, _T_87)
node _T_131 = or(_T_130, _T_94)
node _T_132 = or(_T_131, _T_101)
node _T_133 = or(_T_132, _T_108)
node _T_134 = or(_T_133, _T_115)
node _T_135 = or(_T_134, _T_122)
node _T_136 = or(_T_135, _T_129)
node _T_137 = or(_T_73, _T_136)
node _T_138 = asUInt(reset)
node _T_139 = eq(_T_138, UInt<1>(0h0))
when _T_139 :
node _T_140 = eq(_T_137, UInt<1>(0h0))
when _T_140 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_137, UInt<1>(0h1), "") : assert_2
node _T_141 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_142 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_143 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_144 = and(_T_142, _T_143)
node _T_145 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_146 = and(_T_144, _T_145)
node _T_147 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_148 = and(_T_146, _T_147)
node _T_149 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_150 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_151 = and(_T_149, _T_150)
node _T_152 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_153 = and(_T_151, _T_152)
node _T_154 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_155 = and(_T_153, _T_154)
node _T_156 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_157 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_158 = and(_T_156, _T_157)
node _T_159 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_160 = and(_T_158, _T_159)
node _T_161 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_162 = and(_T_160, _T_161)
node _T_163 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_164 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_165 = and(_T_163, _T_164)
node _T_166 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_167 = and(_T_165, _T_166)
node _T_168 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_169 = and(_T_167, _T_168)
node _T_170 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_171 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_172 = and(_T_170, _T_171)
node _T_173 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_174 = and(_T_172, _T_173)
node _T_175 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_176 = and(_T_174, _T_175)
node _T_177 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_178 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_179 = and(_T_177, _T_178)
node _T_180 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_181 = and(_T_179, _T_180)
node _T_182 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_183 = and(_T_181, _T_182)
node _T_184 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hd))
node _T_185 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_186 = and(_T_184, _T_185)
node _T_187 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_188 = and(_T_186, _T_187)
node _T_189 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_190 = and(_T_188, _T_189)
node _T_191 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_192 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_193 = and(_T_191, _T_192)
node _T_194 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_195 = and(_T_193, _T_194)
node _T_196 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_197 = and(_T_195, _T_196)
node _T_198 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_199 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_200 = and(_T_198, _T_199)
node _T_201 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_202 = and(_T_200, _T_201)
node _T_203 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_204 = and(_T_202, _T_203)
node _T_205 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb))
node _T_206 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_207 = and(_T_205, _T_206)
node _T_208 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_209 = and(_T_207, _T_208)
node _T_210 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_211 = and(_T_209, _T_210)
node _T_212 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_213 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_214 = and(_T_212, _T_213)
node _T_215 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_216 = and(_T_214, _T_215)
node _T_217 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_218 = and(_T_216, _T_217)
node _T_219 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hd))
node _T_220 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_221 = and(_T_219, _T_220)
node _T_222 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_223 = and(_T_221, _T_222)
node _T_224 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_225 = and(_T_223, _T_224)
node _T_226 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb))
node _T_227 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_228 = and(_T_226, _T_227)
node _T_229 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_230 = and(_T_228, _T_229)
node _T_231 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_232 = and(_T_230, _T_231)
node _T_233 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_234 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_235 = and(_T_233, _T_234)
node _T_236 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_237 = and(_T_235, _T_236)
node _T_238 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_239 = and(_T_237, _T_238)
node _T_240 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_241 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_242 = and(_T_240, _T_241)
node _T_243 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_244 = and(_T_242, _T_243)
node _T_245 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_246 = and(_T_244, _T_245)
node _T_247 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_248 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_249 = and(_T_247, _T_248)
node _T_250 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_251 = and(_T_249, _T_250)
node _T_252 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_253 = and(_T_251, _T_252)
node _T_254 = or(_T_148, _T_155)
node _T_255 = or(_T_254, _T_162)
node _T_256 = or(_T_255, _T_169)
node _T_257 = or(_T_256, _T_176)
node _T_258 = or(_T_257, _T_183)
node _T_259 = or(_T_258, _T_190)
node _T_260 = or(_T_259, _T_197)
node _T_261 = or(_T_260, _T_204)
node _T_262 = or(_T_261, _T_211)
node _T_263 = or(_T_262, _T_218)
node _T_264 = or(_T_263, _T_225)
node _T_265 = or(_T_264, _T_232)
node _T_266 = or(_T_265, _T_239)
node _T_267 = or(_T_266, _T_246)
node _T_268 = or(_T_267, _T_253)
node _T_269 = or(_T_141, _T_268)
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3
assert(clock, _T_269, UInt<1>(0h1), "") : assert_3
node _T_273 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_274 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_275 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_276 = and(_T_274, _T_275)
node _T_277 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_278 = and(_T_276, _T_277)
node _T_279 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_280 = and(_T_278, _T_279)
node _T_281 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_282 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_283 = and(_T_281, _T_282)
node _T_284 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_285 = and(_T_283, _T_284)
node _T_286 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_287 = and(_T_285, _T_286)
node _T_288 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_289 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_290 = and(_T_288, _T_289)
node _T_291 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_292 = and(_T_290, _T_291)
node _T_293 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_294 = and(_T_292, _T_293)
node _T_295 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_296 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_297 = and(_T_295, _T_296)
node _T_298 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_299 = and(_T_297, _T_298)
node _T_300 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_301 = and(_T_299, _T_300)
node _T_302 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_303 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_304 = and(_T_302, _T_303)
node _T_305 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_306 = and(_T_304, _T_305)
node _T_307 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_308 = and(_T_306, _T_307)
node _T_309 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_310 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_311 = and(_T_309, _T_310)
node _T_312 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_313 = and(_T_311, _T_312)
node _T_314 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_315 = and(_T_313, _T_314)
node _T_316 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hd))
node _T_317 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_318 = and(_T_316, _T_317)
node _T_319 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_320 = and(_T_318, _T_319)
node _T_321 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_322 = and(_T_320, _T_321)
node _T_323 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_324 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_325 = and(_T_323, _T_324)
node _T_326 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_327 = and(_T_325, _T_326)
node _T_328 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_329 = and(_T_327, _T_328)
node _T_330 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_331 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_332 = and(_T_330, _T_331)
node _T_333 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_334 = and(_T_332, _T_333)
node _T_335 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_336 = and(_T_334, _T_335)
node _T_337 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb))
node _T_338 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_339 = and(_T_337, _T_338)
node _T_340 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_341 = and(_T_339, _T_340)
node _T_342 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_343 = and(_T_341, _T_342)
node _T_344 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_345 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_346 = and(_T_344, _T_345)
node _T_347 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_348 = and(_T_346, _T_347)
node _T_349 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_350 = and(_T_348, _T_349)
node _T_351 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hd))
node _T_352 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_353 = and(_T_351, _T_352)
node _T_354 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_355 = and(_T_353, _T_354)
node _T_356 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_357 = and(_T_355, _T_356)
node _T_358 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb))
node _T_359 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_360 = and(_T_358, _T_359)
node _T_361 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_362 = and(_T_360, _T_361)
node _T_363 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_364 = and(_T_362, _T_363)
node _T_365 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_366 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_367 = and(_T_365, _T_366)
node _T_368 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_369 = and(_T_367, _T_368)
node _T_370 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_371 = and(_T_369, _T_370)
node _T_372 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_373 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_374 = and(_T_372, _T_373)
node _T_375 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_376 = and(_T_374, _T_375)
node _T_377 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_378 = and(_T_376, _T_377)
node _T_379 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_380 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_381 = and(_T_379, _T_380)
node _T_382 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_383 = and(_T_381, _T_382)
node _T_384 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_385 = and(_T_383, _T_384)
node _T_386 = or(_T_280, _T_287)
node _T_387 = or(_T_386, _T_294)
node _T_388 = or(_T_387, _T_301)
node _T_389 = or(_T_388, _T_308)
node _T_390 = or(_T_389, _T_315)
node _T_391 = or(_T_390, _T_322)
node _T_392 = or(_T_391, _T_329)
node _T_393 = or(_T_392, _T_336)
node _T_394 = or(_T_393, _T_343)
node _T_395 = or(_T_394, _T_350)
node _T_396 = or(_T_395, _T_357)
node _T_397 = or(_T_396, _T_364)
node _T_398 = or(_T_397, _T_371)
node _T_399 = or(_T_398, _T_378)
node _T_400 = or(_T_399, _T_385)
node _T_401 = or(_T_273, _T_400)
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_T_401, UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_4
assert(clock, _T_401, UInt<1>(0h1), "") : assert_4
node _T_405 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h4))
node _T_406 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_407 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_408 = and(_T_406, _T_407)
node _T_409 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_410 = and(_T_408, _T_409)
node _T_411 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_412 = and(_T_410, _T_411)
node _T_413 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_414 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_415 = and(_T_413, _T_414)
node _T_416 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_417 = and(_T_415, _T_416)
node _T_418 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_419 = and(_T_417, _T_418)
node _T_420 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_421 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_422 = and(_T_420, _T_421)
node _T_423 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_424 = and(_T_422, _T_423)
node _T_425 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_426 = and(_T_424, _T_425)
node _T_427 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_428 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_429 = and(_T_427, _T_428)
node _T_430 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_431 = and(_T_429, _T_430)
node _T_432 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_433 = and(_T_431, _T_432)
node _T_434 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hd))
node _T_435 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_436 = and(_T_434, _T_435)
node _T_437 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_438 = and(_T_436, _T_437)
node _T_439 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_440 = and(_T_438, _T_439)
node _T_441 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_442 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_443 = and(_T_441, _T_442)
node _T_444 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_445 = and(_T_443, _T_444)
node _T_446 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_447 = and(_T_445, _T_446)
node _T_448 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb))
node _T_449 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_450 = and(_T_448, _T_449)
node _T_451 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_452 = and(_T_450, _T_451)
node _T_453 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_454 = and(_T_452, _T_453)
node _T_455 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_456 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_457 = and(_T_455, _T_456)
node _T_458 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_459 = and(_T_457, _T_458)
node _T_460 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_461 = and(_T_459, _T_460)
node _T_462 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hd))
node _T_463 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_464 = and(_T_462, _T_463)
node _T_465 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_466 = and(_T_464, _T_465)
node _T_467 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_468 = and(_T_466, _T_467)
node _T_469 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_470 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_471 = and(_T_469, _T_470)
node _T_472 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_473 = and(_T_471, _T_472)
node _T_474 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_475 = and(_T_473, _T_474)
node _T_476 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb))
node _T_477 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_478 = and(_T_476, _T_477)
node _T_479 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_480 = and(_T_478, _T_479)
node _T_481 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_482 = and(_T_480, _T_481)
node _T_483 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_484 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_485 = and(_T_483, _T_484)
node _T_486 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_487 = and(_T_485, _T_486)
node _T_488 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_489 = and(_T_487, _T_488)
node _T_490 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_491 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_492 = and(_T_490, _T_491)
node _T_493 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_494 = and(_T_492, _T_493)
node _T_495 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_496 = and(_T_494, _T_495)
node _T_497 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_498 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_499 = and(_T_497, _T_498)
node _T_500 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_501 = and(_T_499, _T_500)
node _T_502 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_503 = and(_T_501, _T_502)
node _T_504 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_505 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_506 = and(_T_504, _T_505)
node _T_507 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_508 = and(_T_506, _T_507)
node _T_509 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_510 = and(_T_508, _T_509)
node _T_511 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_512 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_513 = and(_T_511, _T_512)
node _T_514 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_515 = and(_T_513, _T_514)
node _T_516 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_517 = and(_T_515, _T_516)
node _T_518 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hd))
node _T_519 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_520 = and(_T_518, _T_519)
node _T_521 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_522 = and(_T_520, _T_521)
node _T_523 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_524 = and(_T_522, _T_523)
node _T_525 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb))
node _T_526 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_527 = and(_T_525, _T_526)
node _T_528 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_529 = and(_T_527, _T_528)
node _T_530 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_531 = and(_T_529, _T_530)
node _T_532 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_533 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_534 = and(_T_532, _T_533)
node _T_535 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_536 = and(_T_534, _T_535)
node _T_537 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_538 = and(_T_536, _T_537)
node _T_539 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_540 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_541 = and(_T_539, _T_540)
node _T_542 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_543 = and(_T_541, _T_542)
node _T_544 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_545 = and(_T_543, _T_544)
node _T_546 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_547 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_548 = and(_T_546, _T_547)
node _T_549 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_550 = and(_T_548, _T_549)
node _T_551 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_552 = and(_T_550, _T_551)
node _T_553 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_554 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_555 = and(_T_553, _T_554)
node _T_556 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_557 = and(_T_555, _T_556)
node _T_558 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_559 = and(_T_557, _T_558)
node _T_560 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_561 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_562 = and(_T_560, _T_561)
node _T_563 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_564 = and(_T_562, _T_563)
node _T_565 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_566 = and(_T_564, _T_565)
node _T_567 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_568 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_569 = and(_T_567, _T_568)
node _T_570 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_571 = and(_T_569, _T_570)
node _T_572 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_573 = and(_T_571, _T_572)
node _T_574 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_575 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_576 = and(_T_574, _T_575)
node _T_577 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_578 = and(_T_576, _T_577)
node _T_579 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_580 = and(_T_578, _T_579)
node _T_581 = or(_T_412, _T_419)
node _T_582 = or(_T_581, _T_426)
node _T_583 = or(_T_582, _T_433)
node _T_584 = or(_T_583, _T_440)
node _T_585 = or(_T_584, _T_447)
node _T_586 = or(_T_585, _T_454)
node _T_587 = or(_T_586, _T_461)
node _T_588 = or(_T_587, _T_468)
node _T_589 = or(_T_588, _T_475)
node _T_590 = or(_T_589, _T_482)
node _T_591 = or(_T_590, _T_489)
node _T_592 = or(_T_591, _T_496)
node _T_593 = or(_T_592, _T_503)
node _T_594 = or(_T_593, _T_510)
node _T_595 = or(_T_594, _T_517)
node _T_596 = or(_T_595, _T_524)
node _T_597 = or(_T_596, _T_531)
node _T_598 = or(_T_597, _T_538)
node _T_599 = or(_T_598, _T_545)
node _T_600 = or(_T_599, _T_552)
node _T_601 = or(_T_600, _T_559)
node _T_602 = or(_T_601, _T_566)
node _T_603 = or(_T_602, _T_573)
node _T_604 = or(_T_603, _T_580)
node _T_605 = or(_T_405, _T_604)
node _T_606 = asUInt(reset)
node _T_607 = eq(_T_606, UInt<1>(0h0))
when _T_607 :
node _T_608 = eq(_T_605, UInt<1>(0h0))
when _T_608 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_5
assert(clock, _T_605, UInt<1>(0h1), "") : assert_5
node _T_609 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5))
node _T_610 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_611 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_612 = and(_T_610, _T_611)
node _T_613 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_614 = and(_T_612, _T_613)
node _T_615 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_616 = and(_T_614, _T_615)
node _T_617 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_618 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_619 = and(_T_617, _T_618)
node _T_620 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_621 = and(_T_619, _T_620)
node _T_622 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_623 = and(_T_621, _T_622)
node _T_624 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_625 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_626 = and(_T_624, _T_625)
node _T_627 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_628 = and(_T_626, _T_627)
node _T_629 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_630 = and(_T_628, _T_629)
node _T_631 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_632 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_633 = and(_T_631, _T_632)
node _T_634 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_635 = and(_T_633, _T_634)
node _T_636 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_637 = and(_T_635, _T_636)
node _T_638 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hd))
node _T_639 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_640 = and(_T_638, _T_639)
node _T_641 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_642 = and(_T_640, _T_641)
node _T_643 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_644 = and(_T_642, _T_643)
node _T_645 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_646 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_647 = and(_T_645, _T_646)
node _T_648 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_649 = and(_T_647, _T_648)
node _T_650 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_651 = and(_T_649, _T_650)
node _T_652 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb))
node _T_653 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_654 = and(_T_652, _T_653)
node _T_655 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_656 = and(_T_654, _T_655)
node _T_657 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_658 = and(_T_656, _T_657)
node _T_659 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_660 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_661 = and(_T_659, _T_660)
node _T_662 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_663 = and(_T_661, _T_662)
node _T_664 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_665 = and(_T_663, _T_664)
node _T_666 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hd))
node _T_667 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_668 = and(_T_666, _T_667)
node _T_669 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_670 = and(_T_668, _T_669)
node _T_671 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_672 = and(_T_670, _T_671)
node _T_673 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_674 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_675 = and(_T_673, _T_674)
node _T_676 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_677 = and(_T_675, _T_676)
node _T_678 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_679 = and(_T_677, _T_678)
node _T_680 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb))
node _T_681 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_682 = and(_T_680, _T_681)
node _T_683 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_684 = and(_T_682, _T_683)
node _T_685 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_686 = and(_T_684, _T_685)
node _T_687 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_688 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_689 = and(_T_687, _T_688)
node _T_690 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_691 = and(_T_689, _T_690)
node _T_692 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_693 = and(_T_691, _T_692)
node _T_694 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_695 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_696 = and(_T_694, _T_695)
node _T_697 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_698 = and(_T_696, _T_697)
node _T_699 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_700 = and(_T_698, _T_699)
node _T_701 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_702 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_703 = and(_T_701, _T_702)
node _T_704 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_705 = and(_T_703, _T_704)
node _T_706 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_707 = and(_T_705, _T_706)
node _T_708 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_709 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_710 = and(_T_708, _T_709)
node _T_711 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_712 = and(_T_710, _T_711)
node _T_713 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_714 = and(_T_712, _T_713)
node _T_715 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_716 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_717 = and(_T_715, _T_716)
node _T_718 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_719 = and(_T_717, _T_718)
node _T_720 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_721 = and(_T_719, _T_720)
node _T_722 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hd))
node _T_723 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_724 = and(_T_722, _T_723)
node _T_725 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_726 = and(_T_724, _T_725)
node _T_727 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_728 = and(_T_726, _T_727)
node _T_729 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb))
node _T_730 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_731 = and(_T_729, _T_730)
node _T_732 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_733 = and(_T_731, _T_732)
node _T_734 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_735 = and(_T_733, _T_734)
node _T_736 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_737 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_738 = and(_T_736, _T_737)
node _T_739 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_740 = and(_T_738, _T_739)
node _T_741 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_742 = and(_T_740, _T_741)
node _T_743 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_744 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_745 = and(_T_743, _T_744)
node _T_746 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_747 = and(_T_745, _T_746)
node _T_748 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_749 = and(_T_747, _T_748)
node _T_750 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_751 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_752 = and(_T_750, _T_751)
node _T_753 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_754 = and(_T_752, _T_753)
node _T_755 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_756 = and(_T_754, _T_755)
node _T_757 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_758 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_759 = and(_T_757, _T_758)
node _T_760 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_761 = and(_T_759, _T_760)
node _T_762 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_763 = and(_T_761, _T_762)
node _T_764 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_765 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_766 = and(_T_764, _T_765)
node _T_767 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_768 = and(_T_766, _T_767)
node _T_769 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_770 = and(_T_768, _T_769)
node _T_771 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_772 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_773 = and(_T_771, _T_772)
node _T_774 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_775 = and(_T_773, _T_774)
node _T_776 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_777 = and(_T_775, _T_776)
node _T_778 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_779 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_780 = and(_T_778, _T_779)
node _T_781 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_782 = and(_T_780, _T_781)
node _T_783 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_784 = and(_T_782, _T_783)
node _T_785 = or(_T_616, _T_623)
node _T_786 = or(_T_785, _T_630)
node _T_787 = or(_T_786, _T_637)
node _T_788 = or(_T_787, _T_644)
node _T_789 = or(_T_788, _T_651)
node _T_790 = or(_T_789, _T_658)
node _T_791 = or(_T_790, _T_665)
node _T_792 = or(_T_791, _T_672)
node _T_793 = or(_T_792, _T_679)
node _T_794 = or(_T_793, _T_686)
node _T_795 = or(_T_794, _T_693)
node _T_796 = or(_T_795, _T_700)
node _T_797 = or(_T_796, _T_707)
node _T_798 = or(_T_797, _T_714)
node _T_799 = or(_T_798, _T_721)
node _T_800 = or(_T_799, _T_728)
node _T_801 = or(_T_800, _T_735)
node _T_802 = or(_T_801, _T_742)
node _T_803 = or(_T_802, _T_749)
node _T_804 = or(_T_803, _T_756)
node _T_805 = or(_T_804, _T_763)
node _T_806 = or(_T_805, _T_770)
node _T_807 = or(_T_806, _T_777)
node _T_808 = or(_T_807, _T_784)
node _T_809 = or(_T_609, _T_808)
node _T_810 = asUInt(reset)
node _T_811 = eq(_T_810, UInt<1>(0h0))
when _T_811 :
node _T_812 = eq(_T_809, UInt<1>(0h0))
when _T_812 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_6
assert(clock, _T_809, UInt<1>(0h1), "") : assert_6
node _T_813 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h6))
node _T_814 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_815 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_816 = and(_T_814, _T_815)
node _T_817 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_818 = and(_T_816, _T_817)
node _T_819 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_820 = and(_T_818, _T_819)
node _T_821 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_822 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_823 = and(_T_821, _T_822)
node _T_824 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_825 = and(_T_823, _T_824)
node _T_826 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_827 = and(_T_825, _T_826)
node _T_828 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_829 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_830 = and(_T_828, _T_829)
node _T_831 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_832 = and(_T_830, _T_831)
node _T_833 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_834 = and(_T_832, _T_833)
node _T_835 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_836 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_837 = and(_T_835, _T_836)
node _T_838 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_839 = and(_T_837, _T_838)
node _T_840 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_841 = and(_T_839, _T_840)
node _T_842 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hd))
node _T_843 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_844 = and(_T_842, _T_843)
node _T_845 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_846 = and(_T_844, _T_845)
node _T_847 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_848 = and(_T_846, _T_847)
node _T_849 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_850 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_851 = and(_T_849, _T_850)
node _T_852 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_853 = and(_T_851, _T_852)
node _T_854 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_855 = and(_T_853, _T_854)
node _T_856 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb))
node _T_857 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_858 = and(_T_856, _T_857)
node _T_859 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_860 = and(_T_858, _T_859)
node _T_861 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_862 = and(_T_860, _T_861)
node _T_863 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_864 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_865 = and(_T_863, _T_864)
node _T_866 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_867 = and(_T_865, _T_866)
node _T_868 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_869 = and(_T_867, _T_868)
node _T_870 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hd))
node _T_871 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_872 = and(_T_870, _T_871)
node _T_873 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_874 = and(_T_872, _T_873)
node _T_875 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_876 = and(_T_874, _T_875)
node _T_877 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_878 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_879 = and(_T_877, _T_878)
node _T_880 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_881 = and(_T_879, _T_880)
node _T_882 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_883 = and(_T_881, _T_882)
node _T_884 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb))
node _T_885 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_886 = and(_T_884, _T_885)
node _T_887 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_888 = and(_T_886, _T_887)
node _T_889 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_890 = and(_T_888, _T_889)
node _T_891 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_892 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_893 = and(_T_891, _T_892)
node _T_894 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_895 = and(_T_893, _T_894)
node _T_896 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_897 = and(_T_895, _T_896)
node _T_898 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_899 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_900 = and(_T_898, _T_899)
node _T_901 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_902 = and(_T_900, _T_901)
node _T_903 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_904 = and(_T_902, _T_903)
node _T_905 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_906 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_907 = and(_T_905, _T_906)
node _T_908 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_909 = and(_T_907, _T_908)
node _T_910 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_911 = and(_T_909, _T_910)
node _T_912 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_913 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_914 = and(_T_912, _T_913)
node _T_915 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_916 = and(_T_914, _T_915)
node _T_917 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_918 = and(_T_916, _T_917)
node _T_919 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_920 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_921 = and(_T_919, _T_920)
node _T_922 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_923 = and(_T_921, _T_922)
node _T_924 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_925 = and(_T_923, _T_924)
node _T_926 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hd))
node _T_927 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_928 = and(_T_926, _T_927)
node _T_929 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_930 = and(_T_928, _T_929)
node _T_931 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_932 = and(_T_930, _T_931)
node _T_933 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb))
node _T_934 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_935 = and(_T_933, _T_934)
node _T_936 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_937 = and(_T_935, _T_936)
node _T_938 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_939 = and(_T_937, _T_938)
node _T_940 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_941 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_942 = and(_T_940, _T_941)
node _T_943 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_944 = and(_T_942, _T_943)
node _T_945 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_946 = and(_T_944, _T_945)
node _T_947 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_948 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_949 = and(_T_947, _T_948)
node _T_950 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_951 = and(_T_949, _T_950)
node _T_952 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_953 = and(_T_951, _T_952)
node _T_954 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_955 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_956 = and(_T_954, _T_955)
node _T_957 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_958 = and(_T_956, _T_957)
node _T_959 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_960 = and(_T_958, _T_959)
node _T_961 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_962 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_963 = and(_T_961, _T_962)
node _T_964 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_965 = and(_T_963, _T_964)
node _T_966 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_967 = and(_T_965, _T_966)
node _T_968 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_969 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_970 = and(_T_968, _T_969)
node _T_971 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_972 = and(_T_970, _T_971)
node _T_973 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_974 = and(_T_972, _T_973)
node _T_975 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_976 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_977 = and(_T_975, _T_976)
node _T_978 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_979 = and(_T_977, _T_978)
node _T_980 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_981 = and(_T_979, _T_980)
node _T_982 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_983 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_984 = and(_T_982, _T_983)
node _T_985 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_986 = and(_T_984, _T_985)
node _T_987 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_988 = and(_T_986, _T_987)
node _T_989 = or(_T_820, _T_827)
node _T_990 = or(_T_989, _T_834)
node _T_991 = or(_T_990, _T_841)
node _T_992 = or(_T_991, _T_848)
node _T_993 = or(_T_992, _T_855)
node _T_994 = or(_T_993, _T_862)
node _T_995 = or(_T_994, _T_869)
node _T_996 = or(_T_995, _T_876)
node _T_997 = or(_T_996, _T_883)
node _T_998 = or(_T_997, _T_890)
node _T_999 = or(_T_998, _T_897)
node _T_1000 = or(_T_999, _T_904)
node _T_1001 = or(_T_1000, _T_911)
node _T_1002 = or(_T_1001, _T_918)
node _T_1003 = or(_T_1002, _T_925)
node _T_1004 = or(_T_1003, _T_932)
node _T_1005 = or(_T_1004, _T_939)
node _T_1006 = or(_T_1005, _T_946)
node _T_1007 = or(_T_1006, _T_953)
node _T_1008 = or(_T_1007, _T_960)
node _T_1009 = or(_T_1008, _T_967)
node _T_1010 = or(_T_1009, _T_974)
node _T_1011 = or(_T_1010, _T_981)
node _T_1012 = or(_T_1011, _T_988)
node _T_1013 = or(_T_813, _T_1012)
node _T_1014 = asUInt(reset)
node _T_1015 = eq(_T_1014, UInt<1>(0h0))
when _T_1015 :
node _T_1016 = eq(_T_1013, UInt<1>(0h0))
when _T_1016 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_7
assert(clock, _T_1013, UInt<1>(0h1), "") : assert_7
node _T_1017 = neq(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h7))
node _T_1018 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_1019 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_1020 = and(_T_1018, _T_1019)
node _T_1021 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_1022 = and(_T_1020, _T_1021)
node _T_1023 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_1024 = and(_T_1022, _T_1023)
node _T_1025 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_1026 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_1027 = and(_T_1025, _T_1026)
node _T_1028 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_1029 = and(_T_1027, _T_1028)
node _T_1030 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_1031 = and(_T_1029, _T_1030)
node _T_1032 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_1033 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_1034 = and(_T_1032, _T_1033)
node _T_1035 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_1036 = and(_T_1034, _T_1035)
node _T_1037 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_1038 = and(_T_1036, _T_1037)
node _T_1039 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_1040 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_1041 = and(_T_1039, _T_1040)
node _T_1042 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_1043 = and(_T_1041, _T_1042)
node _T_1044 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_1045 = and(_T_1043, _T_1044)
node _T_1046 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hd))
node _T_1047 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_1048 = and(_T_1046, _T_1047)
node _T_1049 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_1050 = and(_T_1048, _T_1049)
node _T_1051 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_1052 = and(_T_1050, _T_1051)
node _T_1053 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_1054 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_1055 = and(_T_1053, _T_1054)
node _T_1056 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_1057 = and(_T_1055, _T_1056)
node _T_1058 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_1059 = and(_T_1057, _T_1058)
node _T_1060 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb))
node _T_1061 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_1062 = and(_T_1060, _T_1061)
node _T_1063 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_1064 = and(_T_1062, _T_1063)
node _T_1065 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_1066 = and(_T_1064, _T_1065)
node _T_1067 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_1068 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_1069 = and(_T_1067, _T_1068)
node _T_1070 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_1071 = and(_T_1069, _T_1070)
node _T_1072 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_1073 = and(_T_1071, _T_1072)
node _T_1074 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hd))
node _T_1075 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_1076 = and(_T_1074, _T_1075)
node _T_1077 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_1078 = and(_T_1076, _T_1077)
node _T_1079 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_1080 = and(_T_1078, _T_1079)
node _T_1081 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h0))
node _T_1082 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_1083 = and(_T_1081, _T_1082)
node _T_1084 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_1085 = and(_T_1083, _T_1084)
node _T_1086 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_1087 = and(_T_1085, _T_1086)
node _T_1088 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb))
node _T_1089 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_1090 = and(_T_1088, _T_1089)
node _T_1091 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_1092 = and(_T_1090, _T_1091)
node _T_1093 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_1094 = and(_T_1092, _T_1093)
node _T_1095 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_1096 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_1097 = and(_T_1095, _T_1096)
node _T_1098 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_1099 = and(_T_1097, _T_1098)
node _T_1100 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_1101 = and(_T_1099, _T_1100)
node _T_1102 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_1103 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_1104 = and(_T_1102, _T_1103)
node _T_1105 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_1106 = and(_T_1104, _T_1105)
node _T_1107 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_1108 = and(_T_1106, _T_1107)
node _T_1109 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_1110 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_1111 = and(_T_1109, _T_1110)
node _T_1112 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_1113 = and(_T_1111, _T_1112)
node _T_1114 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_1115 = and(_T_1113, _T_1114)
node _T_1116 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_1117 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_1118 = and(_T_1116, _T_1117)
node _T_1119 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_1120 = and(_T_1118, _T_1119)
node _T_1121 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_1122 = and(_T_1120, _T_1121)
node _T_1123 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_1124 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_1125 = and(_T_1123, _T_1124)
node _T_1126 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_1127 = and(_T_1125, _T_1126)
node _T_1128 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_1129 = and(_T_1127, _T_1128)
node _T_1130 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hd))
node _T_1131 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_1132 = and(_T_1130, _T_1131)
node _T_1133 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_1134 = and(_T_1132, _T_1133)
node _T_1135 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_1136 = and(_T_1134, _T_1135)
node _T_1137 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0hb))
node _T_1138 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_1139 = and(_T_1137, _T_1138)
node _T_1140 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1))
node _T_1141 = and(_T_1139, _T_1140)
node _T_1142 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1))
node _T_1143 = and(_T_1141, _T_1142)
node _T_1144 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<2>(0h2))
node _T_1145 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_1146 = and(_T_1144, _T_1145)
node _T_1147 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_1148 = and(_T_1146, _T_1147)
node _T_1149 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_1150 = and(_T_1148, _T_1149)
node _T_1151 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<1>(0h1))
node _T_1152 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_1153 = and(_T_1151, _T_1152)
node _T_1154 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_1155 = and(_T_1153, _T_1154)
node _T_1156 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_1157 = and(_T_1155, _T_1156)
node _T_1158 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h7))
node _T_1159 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_1160 = and(_T_1158, _T_1159)
node _T_1161 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_1162 = and(_T_1160, _T_1161)
node _T_1163 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_1164 = and(_T_1162, _T_1163)
node _T_1165 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_1166 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_1167 = and(_T_1165, _T_1166)
node _T_1168 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_1169 = and(_T_1167, _T_1168)
node _T_1170 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_1171 = and(_T_1169, _T_1170)
node _T_1172 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_1173 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_1174 = and(_T_1172, _T_1173)
node _T_1175 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_1176 = and(_T_1174, _T_1175)
node _T_1177 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_1178 = and(_T_1176, _T_1177)
node _T_1179 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0he))
node _T_1180 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_1181 = and(_T_1179, _T_1180)
node _T_1182 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_1183 = and(_T_1181, _T_1182)
node _T_1184 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_1185 = and(_T_1183, _T_1184)
node _T_1186 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h8))
node _T_1187 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_1188 = and(_T_1186, _T_1187)
node _T_1189 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<2>(0h2))
node _T_1190 = and(_T_1188, _T_1189)
node _T_1191 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<2>(0h2))
node _T_1192 = and(_T_1190, _T_1191)
node _T_1193 = or(_T_1024, _T_1031)
node _T_1194 = or(_T_1193, _T_1038)
node _T_1195 = or(_T_1194, _T_1045)
node _T_1196 = or(_T_1195, _T_1052)
node _T_1197 = or(_T_1196, _T_1059)
node _T_1198 = or(_T_1197, _T_1066)
node _T_1199 = or(_T_1198, _T_1073)
node _T_1200 = or(_T_1199, _T_1080)
node _T_1201 = or(_T_1200, _T_1087)
node _T_1202 = or(_T_1201, _T_1094)
node _T_1203 = or(_T_1202, _T_1101)
node _T_1204 = or(_T_1203, _T_1108)
node _T_1205 = or(_T_1204, _T_1115)
node _T_1206 = or(_T_1205, _T_1122)
node _T_1207 = or(_T_1206, _T_1129)
node _T_1208 = or(_T_1207, _T_1136)
node _T_1209 = or(_T_1208, _T_1143)
node _T_1210 = or(_T_1209, _T_1150)
node _T_1211 = or(_T_1210, _T_1157)
node _T_1212 = or(_T_1211, _T_1164)
node _T_1213 = or(_T_1212, _T_1171)
node _T_1214 = or(_T_1213, _T_1178)
node _T_1215 = or(_T_1214, _T_1185)
node _T_1216 = or(_T_1215, _T_1192)
node _T_1217 = or(_T_1017, _T_1216)
node _T_1218 = asUInt(reset)
node _T_1219 = eq(_T_1218, UInt<1>(0h0))
when _T_1219 :
node _T_1220 = eq(_T_1217, UInt<1>(0h0))
when _T_1220 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_8
assert(clock, _T_1217, UInt<1>(0h1), "") : assert_8 | module NoCMonitor_6( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [4:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input [2:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26]
reg in_flight_2; // @[Monitor.scala:16:26]
reg in_flight_3; // @[Monitor.scala:16:26]
reg in_flight_4; // @[Monitor.scala:16:26]
reg in_flight_5; // @[Monitor.scala:16:26]
reg in_flight_6; // @[Monitor.scala:16:26]
reg in_flight_7; // @[Monitor.scala:16:26] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_77 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_117
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_77( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_117 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_61 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], credit_return : UInt<2>, vc_free : UInt<2>}}
wire _in_flight_WIRE : UInt<1>[2]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
regreset in_flight : UInt<1>[2], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_7 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6))
node _T_8 = and(_T_6, _T_7)
node _T_9 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_10 = and(_T_8, _T_9)
node _T_11 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_12 = and(_T_10, _T_11)
node _T_13 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4))
node _T_14 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha))
node _T_15 = and(_T_13, _T_14)
node _T_16 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_19 = and(_T_17, _T_18)
node _T_20 = or(_T_12, _T_19)
node _T_21 = or(_T_5, _T_20)
node _T_22 = asUInt(reset)
node _T_23 = eq(_T_22, UInt<1>(0h0))
when _T_23 :
node _T_24 = eq(_T_21, UInt<1>(0h0))
when _T_24 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_21, UInt<1>(0h1), "") : assert_1
node _T_25 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_26 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_27 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h7))
node _T_28 = and(_T_26, _T_27)
node _T_29 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_32 = and(_T_30, _T_31)
node _T_33 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_34 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h3))
node _T_35 = and(_T_33, _T_34)
node _T_36 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_37 = and(_T_35, _T_36)
node _T_38 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_39 = and(_T_37, _T_38)
node _T_40 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_41 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0he))
node _T_42 = and(_T_40, _T_41)
node _T_43 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_44 = and(_T_42, _T_43)
node _T_45 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_46 = and(_T_44, _T_45)
node _T_47 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_48 = eq(io.in.flit[0].bits.flow.egress_node, UInt<2>(0h2))
node _T_49 = and(_T_47, _T_48)
node _T_50 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_51 = and(_T_49, _T_50)
node _T_52 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_53 = and(_T_51, _T_52)
node _T_54 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_55 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hb))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_58 = and(_T_56, _T_57)
node _T_59 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_60 = and(_T_58, _T_59)
node _T_61 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_62 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hf))
node _T_63 = and(_T_61, _T_62)
node _T_64 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_65 = and(_T_63, _T_64)
node _T_66 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_67 = and(_T_65, _T_66)
node _T_68 = or(_T_32, _T_39)
node _T_69 = or(_T_68, _T_46)
node _T_70 = or(_T_69, _T_53)
node _T_71 = or(_T_70, _T_60)
node _T_72 = or(_T_71, _T_67)
node _T_73 = or(_T_25, _T_72)
node _T_74 = asUInt(reset)
node _T_75 = eq(_T_74, UInt<1>(0h0))
when _T_75 :
node _T_76 = eq(_T_73, UInt<1>(0h0))
when _T_76 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_73, UInt<1>(0h1), "") : assert_2 | module NoCMonitor_61( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26] |
Generate the Verilog code corresponding to this FIRRTL code module SerialTL0ClockSinkDomain :
output auto : { serdesser_client_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<6>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip clock_in : { clock : Clock, reset : Reset}}
output serial_tl_0 : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, flip clock_in : Clock}
output serial_tl_0_debug : { ser_busy : UInt<1>, des_busy : UInt<1>}
output clock : Clock
output reset : Reset
wire childClock : Clock
wire childReset : Reset
node _childClock_T = asClock(UInt<1>(0h0))
connect childClock, _childClock_T
invalidate childReset
inst serdesser of TLSerdesser_serial_tl_0
connect serdesser.clock, childClock
connect serdesser.reset, childReset
wire clockNodeIn : { clock : Clock, reset : Reset}
invalidate clockNodeIn.reset
invalidate clockNodeIn.clock
connect clockNodeIn, auto.clock_in
connect serdesser.auto.client_out.d, auto.serdesser_client_out.d
connect auto.serdesser_client_out.a.bits, serdesser.auto.client_out.a.bits
connect auto.serdesser_client_out.a.valid, serdesser.auto.client_out.a.valid
connect serdesser.auto.client_out.a.ready, auto.serdesser_client_out.a.ready
node _outer_reset_T = asUInt(serdesser.reset)
inst outer_reset_catcher of ResetCatchAndSync_d3
connect outer_reset_catcher.clock, serial_tl_0.clock_in
connect outer_reset_catcher.reset, _outer_reset_T
wire _outer_reset_catcher_io_psd_WIRE : { test_mode : UInt<1>, test_mode_reset : UInt<1>}
connect _outer_reset_catcher_io_psd_WIRE.test_mode_reset, UInt<1>(0h0)
connect _outer_reset_catcher_io_psd_WIRE.test_mode, UInt<1>(0h0)
wire _outer_reset_catcher_io_psd_WIRE_1 : { test_mode : UInt<1>, test_mode_reset : UInt<1>}
connect _outer_reset_catcher_io_psd_WIRE_1, _outer_reset_catcher_io_psd_WIRE
connect outer_reset_catcher.io.psd, _outer_reset_catcher_io_psd_WIRE_1
inst phy of DecoupledSerialPhy
connect phy.io.outer_clock, serial_tl_0.clock_in
node _phy_io_outer_reset_T = asUInt(serdesser.reset)
inst phy_io_outer_reset_catcher of ResetCatchAndSync_d3_1
connect phy_io_outer_reset_catcher.clock, serial_tl_0.clock_in
connect phy_io_outer_reset_catcher.reset, _phy_io_outer_reset_T
wire _phy_io_outer_reset_catcher_io_psd_WIRE : { test_mode : UInt<1>, test_mode_reset : UInt<1>}
connect _phy_io_outer_reset_catcher_io_psd_WIRE.test_mode_reset, UInt<1>(0h0)
connect _phy_io_outer_reset_catcher_io_psd_WIRE.test_mode, UInt<1>(0h0)
wire _phy_io_outer_reset_catcher_io_psd_WIRE_1 : { test_mode : UInt<1>, test_mode_reset : UInt<1>}
connect _phy_io_outer_reset_catcher_io_psd_WIRE_1, _phy_io_outer_reset_catcher_io_psd_WIRE
connect phy_io_outer_reset_catcher.io.psd, _phy_io_outer_reset_catcher_io_psd_WIRE_1
connect phy.io.outer_reset, phy_io_outer_reset_catcher.io.sync_reset
connect phy.io.inner_clock, serdesser.clock
connect phy.io.inner_reset, serdesser.reset
connect serial_tl_0.out.bits, phy.io.outer_ser.out.bits
connect serial_tl_0.out.valid, phy.io.outer_ser.out.valid
connect phy.io.outer_ser.out.ready, serial_tl_0.out.ready
connect phy.io.outer_ser.in, serial_tl_0.in
connect phy.io.inner_ser, serdesser.io.ser
connect serial_tl_0_debug, serdesser.io.debug
connect childClock, clockNodeIn.clock
connect childReset, clockNodeIn.reset
connect clock, clockNodeIn.clock
connect reset, clockNodeIn.reset | module SerialTL0ClockSinkDomain( // @[ClockDomain.scala:14:9]
input auto_serdesser_client_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_serdesser_client_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_serdesser_client_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_serdesser_client_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_serdesser_client_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_serdesser_client_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_serdesser_client_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_serdesser_client_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_serdesser_client_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_serdesser_client_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_serdesser_client_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_serdesser_client_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_serdesser_client_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_serdesser_client_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_serdesser_client_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_serdesser_client_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_serdesser_client_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_serdesser_client_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_serdesser_client_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_serdesser_client_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_clock, // @[LazyModuleImp.scala:107:25]
input auto_clock_in_reset, // @[LazyModuleImp.scala:107:25]
output serial_tl_0_in_ready, // @[PeripheryTLSerial.scala:165:24]
input serial_tl_0_in_valid, // @[PeripheryTLSerial.scala:165:24]
input [31:0] serial_tl_0_in_bits_phit, // @[PeripheryTLSerial.scala:165:24]
input serial_tl_0_out_ready, // @[PeripheryTLSerial.scala:165:24]
output serial_tl_0_out_valid, // @[PeripheryTLSerial.scala:165:24]
output [31:0] serial_tl_0_out_bits_phit, // @[PeripheryTLSerial.scala:165:24]
input serial_tl_0_clock_in // @[PeripheryTLSerial.scala:165:24]
);
wire _phy_io_outer_reset_catcher_io_sync_reset; // @[ResetCatchAndSync.scala:39:28]
wire _phy_io_inner_ser_0_in_valid; // @[PeripheryTLSerial.scala:186:27]
wire [31:0] _phy_io_inner_ser_0_in_bits_flit; // @[PeripheryTLSerial.scala:186:27]
wire _phy_io_inner_ser_1_in_valid; // @[PeripheryTLSerial.scala:186:27]
wire [31:0] _phy_io_inner_ser_1_in_bits_flit; // @[PeripheryTLSerial.scala:186:27]
wire _phy_io_inner_ser_1_out_ready; // @[PeripheryTLSerial.scala:186:27]
wire _phy_io_inner_ser_2_in_valid; // @[PeripheryTLSerial.scala:186:27]
wire [31:0] _phy_io_inner_ser_2_in_bits_flit; // @[PeripheryTLSerial.scala:186:27]
wire _phy_io_inner_ser_3_in_valid; // @[PeripheryTLSerial.scala:186:27]
wire [31:0] _phy_io_inner_ser_3_in_bits_flit; // @[PeripheryTLSerial.scala:186:27]
wire _phy_io_inner_ser_3_out_ready; // @[PeripheryTLSerial.scala:186:27]
wire _phy_io_inner_ser_4_in_valid; // @[PeripheryTLSerial.scala:186:27]
wire [31:0] _phy_io_inner_ser_4_in_bits_flit; // @[PeripheryTLSerial.scala:186:27]
wire _serdesser_io_ser_0_in_ready; // @[PeripheryTLSerial.scala:129:50]
wire _serdesser_io_ser_1_in_ready; // @[PeripheryTLSerial.scala:129:50]
wire _serdesser_io_ser_1_out_valid; // @[PeripheryTLSerial.scala:129:50]
wire [31:0] _serdesser_io_ser_1_out_bits_flit; // @[PeripheryTLSerial.scala:129:50]
wire _serdesser_io_ser_2_in_ready; // @[PeripheryTLSerial.scala:129:50]
wire _serdesser_io_ser_3_in_ready; // @[PeripheryTLSerial.scala:129:50]
wire _serdesser_io_ser_3_out_valid; // @[PeripheryTLSerial.scala:129:50]
wire [31:0] _serdesser_io_ser_3_out_bits_flit; // @[PeripheryTLSerial.scala:129:50]
wire _serdesser_io_ser_4_in_ready; // @[PeripheryTLSerial.scala:129:50]
TLSerdesser_serial_tl_0 serdesser ( // @[PeripheryTLSerial.scala:129:50]
.clock (auto_clock_in_clock),
.reset (auto_clock_in_reset),
.auto_client_out_a_ready (auto_serdesser_client_out_a_ready),
.auto_client_out_a_valid (auto_serdesser_client_out_a_valid),
.auto_client_out_a_bits_opcode (auto_serdesser_client_out_a_bits_opcode),
.auto_client_out_a_bits_param (auto_serdesser_client_out_a_bits_param),
.auto_client_out_a_bits_size (auto_serdesser_client_out_a_bits_size),
.auto_client_out_a_bits_source (auto_serdesser_client_out_a_bits_source),
.auto_client_out_a_bits_address (auto_serdesser_client_out_a_bits_address),
.auto_client_out_a_bits_mask (auto_serdesser_client_out_a_bits_mask),
.auto_client_out_a_bits_data (auto_serdesser_client_out_a_bits_data),
.auto_client_out_a_bits_corrupt (auto_serdesser_client_out_a_bits_corrupt),
.auto_client_out_d_ready (auto_serdesser_client_out_d_ready),
.auto_client_out_d_valid (auto_serdesser_client_out_d_valid),
.auto_client_out_d_bits_opcode (auto_serdesser_client_out_d_bits_opcode),
.auto_client_out_d_bits_param (auto_serdesser_client_out_d_bits_param),
.auto_client_out_d_bits_size (auto_serdesser_client_out_d_bits_size),
.auto_client_out_d_bits_source (auto_serdesser_client_out_d_bits_source),
.auto_client_out_d_bits_sink (auto_serdesser_client_out_d_bits_sink),
.auto_client_out_d_bits_denied (auto_serdesser_client_out_d_bits_denied),
.auto_client_out_d_bits_data (auto_serdesser_client_out_d_bits_data),
.auto_client_out_d_bits_corrupt (auto_serdesser_client_out_d_bits_corrupt),
.io_ser_0_in_ready (_serdesser_io_ser_0_in_ready),
.io_ser_0_in_valid (_phy_io_inner_ser_0_in_valid), // @[PeripheryTLSerial.scala:186:27]
.io_ser_0_in_bits_flit (_phy_io_inner_ser_0_in_bits_flit), // @[PeripheryTLSerial.scala:186:27]
.io_ser_1_in_ready (_serdesser_io_ser_1_in_ready),
.io_ser_1_in_valid (_phy_io_inner_ser_1_in_valid), // @[PeripheryTLSerial.scala:186:27]
.io_ser_1_in_bits_flit (_phy_io_inner_ser_1_in_bits_flit), // @[PeripheryTLSerial.scala:186:27]
.io_ser_1_out_ready (_phy_io_inner_ser_1_out_ready), // @[PeripheryTLSerial.scala:186:27]
.io_ser_1_out_valid (_serdesser_io_ser_1_out_valid),
.io_ser_1_out_bits_flit (_serdesser_io_ser_1_out_bits_flit),
.io_ser_2_in_ready (_serdesser_io_ser_2_in_ready),
.io_ser_2_in_valid (_phy_io_inner_ser_2_in_valid), // @[PeripheryTLSerial.scala:186:27]
.io_ser_2_in_bits_flit (_phy_io_inner_ser_2_in_bits_flit), // @[PeripheryTLSerial.scala:186:27]
.io_ser_3_in_ready (_serdesser_io_ser_3_in_ready),
.io_ser_3_in_valid (_phy_io_inner_ser_3_in_valid), // @[PeripheryTLSerial.scala:186:27]
.io_ser_3_in_bits_flit (_phy_io_inner_ser_3_in_bits_flit), // @[PeripheryTLSerial.scala:186:27]
.io_ser_3_out_ready (_phy_io_inner_ser_3_out_ready), // @[PeripheryTLSerial.scala:186:27]
.io_ser_3_out_valid (_serdesser_io_ser_3_out_valid),
.io_ser_3_out_bits_flit (_serdesser_io_ser_3_out_bits_flit),
.io_ser_4_in_ready (_serdesser_io_ser_4_in_ready),
.io_ser_4_in_valid (_phy_io_inner_ser_4_in_valid), // @[PeripheryTLSerial.scala:186:27]
.io_ser_4_in_bits_flit (_phy_io_inner_ser_4_in_bits_flit) // @[PeripheryTLSerial.scala:186:27]
); // @[PeripheryTLSerial.scala:129:50]
ResetCatchAndSync_d3 outer_reset_catcher ( // @[ResetCatchAndSync.scala:39:28]
.clock (serial_tl_0_clock_in),
.reset (auto_clock_in_reset),
.io_sync_reset (/* unused */)
); // @[ResetCatchAndSync.scala:39:28]
DecoupledSerialPhy phy ( // @[PeripheryTLSerial.scala:186:27]
.io_outer_clock (serial_tl_0_clock_in),
.io_outer_reset (_phy_io_outer_reset_catcher_io_sync_reset), // @[ResetCatchAndSync.scala:39:28]
.io_inner_clock (auto_clock_in_clock),
.io_inner_reset (auto_clock_in_reset),
.io_outer_ser_in_ready (serial_tl_0_in_ready),
.io_outer_ser_in_valid (serial_tl_0_in_valid),
.io_outer_ser_in_bits_phit (serial_tl_0_in_bits_phit),
.io_outer_ser_out_ready (serial_tl_0_out_ready),
.io_outer_ser_out_valid (serial_tl_0_out_valid),
.io_outer_ser_out_bits_phit (serial_tl_0_out_bits_phit),
.io_inner_ser_0_in_ready (_serdesser_io_ser_0_in_ready), // @[PeripheryTLSerial.scala:129:50]
.io_inner_ser_0_in_valid (_phy_io_inner_ser_0_in_valid),
.io_inner_ser_0_in_bits_flit (_phy_io_inner_ser_0_in_bits_flit),
.io_inner_ser_0_out_bits_flit (32'h0), // @[PeripheryTLSerial.scala:129:50, :186:27]
.io_inner_ser_1_in_ready (_serdesser_io_ser_1_in_ready), // @[PeripheryTLSerial.scala:129:50]
.io_inner_ser_1_in_valid (_phy_io_inner_ser_1_in_valid),
.io_inner_ser_1_in_bits_flit (_phy_io_inner_ser_1_in_bits_flit),
.io_inner_ser_1_out_ready (_phy_io_inner_ser_1_out_ready),
.io_inner_ser_1_out_valid (_serdesser_io_ser_1_out_valid), // @[PeripheryTLSerial.scala:129:50]
.io_inner_ser_1_out_bits_flit (_serdesser_io_ser_1_out_bits_flit), // @[PeripheryTLSerial.scala:129:50]
.io_inner_ser_2_in_ready (_serdesser_io_ser_2_in_ready), // @[PeripheryTLSerial.scala:129:50]
.io_inner_ser_2_in_valid (_phy_io_inner_ser_2_in_valid),
.io_inner_ser_2_in_bits_flit (_phy_io_inner_ser_2_in_bits_flit),
.io_inner_ser_2_out_ready (/* unused */),
.io_inner_ser_2_out_valid (1'h0), // @[PeripheryTLSerial.scala:129:50, :186:27]
.io_inner_ser_2_out_bits_flit (32'h0), // @[PeripheryTLSerial.scala:129:50, :186:27]
.io_inner_ser_3_in_ready (_serdesser_io_ser_3_in_ready), // @[PeripheryTLSerial.scala:129:50]
.io_inner_ser_3_in_valid (_phy_io_inner_ser_3_in_valid),
.io_inner_ser_3_in_bits_flit (_phy_io_inner_ser_3_in_bits_flit),
.io_inner_ser_3_out_ready (_phy_io_inner_ser_3_out_ready),
.io_inner_ser_3_out_valid (_serdesser_io_ser_3_out_valid), // @[PeripheryTLSerial.scala:129:50]
.io_inner_ser_3_out_bits_flit (_serdesser_io_ser_3_out_bits_flit), // @[PeripheryTLSerial.scala:129:50]
.io_inner_ser_4_in_ready (_serdesser_io_ser_4_in_ready), // @[PeripheryTLSerial.scala:129:50]
.io_inner_ser_4_in_valid (_phy_io_inner_ser_4_in_valid),
.io_inner_ser_4_in_bits_flit (_phy_io_inner_ser_4_in_bits_flit),
.io_inner_ser_4_out_ready (/* unused */),
.io_inner_ser_4_out_valid (1'h0), // @[PeripheryTLSerial.scala:129:50, :186:27]
.io_inner_ser_4_out_bits_flit (32'h0) // @[PeripheryTLSerial.scala:129:50, :186:27]
); // @[PeripheryTLSerial.scala:186:27]
ResetCatchAndSync_d3 phy_io_outer_reset_catcher ( // @[ResetCatchAndSync.scala:39:28]
.clock (serial_tl_0_clock_in),
.reset (auto_clock_in_reset),
.io_sync_reset (_phy_io_outer_reset_catcher_io_sync_reset)
); // @[ResetCatchAndSync.scala:39:28]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IngressUnit_10 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<0>, vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, flip out_credit_available : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], debug : { va_stall : UInt<0>, sa_stall : UInt<0>}, flip block : UInt<1>, flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, egress_id : UInt}}}
inst route_buffer of Queue2_Flit_20
connect route_buffer.clock, clock
connect route_buffer.reset, reset
inst route_q of Queue2_RouteComputerResp_10
connect route_q.clock, clock
connect route_q.reset, reset
node _T = eq(UInt<5>(0h10), io.in.bits.egress_id)
node _T_1 = eq(UInt<5>(0h12), io.in.bits.egress_id)
node _T_2 = eq(UInt<5>(0h14), io.in.bits.egress_id)
node _T_3 = eq(UInt<5>(0h16), io.in.bits.egress_id)
node _T_4 = or(_T, _T_1)
node _T_5 = or(_T_4, _T_2)
node _T_6 = or(_T_5, _T_3)
node _T_7 = eq(_T_6, UInt<1>(0h0))
node _T_8 = and(io.in.valid, _T_7)
node _T_9 = eq(_T_8, UInt<1>(0h0))
node _T_10 = asUInt(reset)
node _T_11 = eq(_T_10, UInt<1>(0h0))
when _T_11 :
node _T_12 = eq(_T_9, UInt<1>(0h0))
when _T_12 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:30 assert(!(io.in.valid && !cParam.possibleFlows.toSeq.map(_.egressId.U === io.in.bits.egress_id).orR))\n") : printf
assert(clock, _T_9, UInt<1>(0h1), "") : assert
connect route_buffer.io.enq.bits.head, io.in.bits.head
connect route_buffer.io.enq.bits.tail, io.in.bits.tail
connect route_buffer.io.enq.bits.flow.ingress_node, UInt<2>(0h3)
connect route_buffer.io.enq.bits.flow.ingress_node_id, UInt<1>(0h1)
connect route_buffer.io.enq.bits.flow.vnet_id, UInt<1>(0h1)
node _route_buffer_io_enq_bits_flow_egress_node_T = eq(UInt<5>(0h10), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_1 = eq(UInt<5>(0h12), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_2 = eq(UInt<5>(0h14), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_3 = eq(UInt<5>(0h16), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_T, UInt<3>(0h5), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_1, UInt<3>(0h6), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_2, UInt<4>(0h9), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_T_3, UInt<4>(0ha), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_T_4, _route_buffer_io_enq_bits_flow_egress_node_T_5)
node _route_buffer_io_enq_bits_flow_egress_node_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_T_8, _route_buffer_io_enq_bits_flow_egress_node_T_6)
node _route_buffer_io_enq_bits_flow_egress_node_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_T_9, _route_buffer_io_enq_bits_flow_egress_node_T_7)
wire _route_buffer_io_enq_bits_flow_egress_node_WIRE : UInt<4>
connect _route_buffer_io_enq_bits_flow_egress_node_WIRE, _route_buffer_io_enq_bits_flow_egress_node_T_10
connect route_buffer.io.enq.bits.flow.egress_node, _route_buffer_io_enq_bits_flow_egress_node_WIRE
node _route_buffer_io_enq_bits_flow_egress_node_id_T = eq(UInt<5>(0h10), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_1 = eq(UInt<5>(0h12), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_2 = eq(UInt<5>(0h14), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_3 = eq(UInt<5>(0h16), io.in.bits.egress_id)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T, UInt<1>(0h1), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_1, UInt<1>(0h1), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_2, UInt<1>(0h1), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = mux(_route_buffer_io_enq_bits_flow_egress_node_id_T_3, UInt<1>(0h1), UInt<1>(0h0))
node _route_buffer_io_enq_bits_flow_egress_node_id_T_8 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_4, _route_buffer_io_enq_bits_flow_egress_node_id_T_5)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_9 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_8, _route_buffer_io_enq_bits_flow_egress_node_id_T_6)
node _route_buffer_io_enq_bits_flow_egress_node_id_T_10 = or(_route_buffer_io_enq_bits_flow_egress_node_id_T_9, _route_buffer_io_enq_bits_flow_egress_node_id_T_7)
wire _route_buffer_io_enq_bits_flow_egress_node_id_WIRE : UInt<1>
connect _route_buffer_io_enq_bits_flow_egress_node_id_WIRE, _route_buffer_io_enq_bits_flow_egress_node_id_T_10
connect route_buffer.io.enq.bits.flow.egress_node_id, _route_buffer_io_enq_bits_flow_egress_node_id_WIRE
connect route_buffer.io.enq.bits.payload, io.in.bits.payload
invalidate route_buffer.io.enq.bits.virt_channel_id
connect io.router_req.bits.src_virt_id, UInt<1>(0h0)
connect io.router_req.bits.flow.egress_node_id, route_buffer.io.enq.bits.flow.egress_node_id
connect io.router_req.bits.flow.egress_node, route_buffer.io.enq.bits.flow.egress_node
connect io.router_req.bits.flow.ingress_node_id, route_buffer.io.enq.bits.flow.ingress_node_id
connect io.router_req.bits.flow.ingress_node, route_buffer.io.enq.bits.flow.ingress_node
connect io.router_req.bits.flow.vnet_id, route_buffer.io.enq.bits.flow.vnet_id
node at_dest = eq(route_buffer.io.enq.bits.flow.egress_node, UInt<2>(0h3))
node _route_buffer_io_enq_valid_T = eq(io.in.bits.head, UInt<1>(0h0))
node _route_buffer_io_enq_valid_T_1 = or(io.router_req.ready, _route_buffer_io_enq_valid_T)
node _route_buffer_io_enq_valid_T_2 = or(_route_buffer_io_enq_valid_T_1, at_dest)
node _route_buffer_io_enq_valid_T_3 = and(io.in.valid, _route_buffer_io_enq_valid_T_2)
connect route_buffer.io.enq.valid, _route_buffer_io_enq_valid_T_3
node _io_router_req_valid_T = and(io.in.valid, route_buffer.io.enq.ready)
node _io_router_req_valid_T_1 = and(_io_router_req_valid_T, io.in.bits.head)
node _io_router_req_valid_T_2 = eq(at_dest, UInt<1>(0h0))
node _io_router_req_valid_T_3 = and(_io_router_req_valid_T_1, _io_router_req_valid_T_2)
connect io.router_req.valid, _io_router_req_valid_T_3
node _io_in_ready_T = eq(io.in.bits.head, UInt<1>(0h0))
node _io_in_ready_T_1 = or(io.router_req.ready, _io_in_ready_T)
node _io_in_ready_T_2 = or(_io_in_ready_T_1, at_dest)
node _io_in_ready_T_3 = and(route_buffer.io.enq.ready, _io_in_ready_T_2)
connect io.in.ready, _io_in_ready_T_3
node _route_q_io_enq_valid_T = and(io.router_req.ready, io.router_req.valid)
connect route_q.io.enq.valid, _route_q_io_enq_valid_T
connect route_q.io.enq.bits.vc_sel.`0`[0], io.router_resp.vc_sel.`0`[0]
connect route_q.io.enq.bits.vc_sel.`0`[1], io.router_resp.vc_sel.`0`[1]
connect route_q.io.enq.bits.vc_sel.`0`[2], io.router_resp.vc_sel.`0`[2]
connect route_q.io.enq.bits.vc_sel.`1`[0], io.router_resp.vc_sel.`1`[0]
connect route_q.io.enq.bits.vc_sel.`1`[1], io.router_resp.vc_sel.`1`[1]
connect route_q.io.enq.bits.vc_sel.`1`[2], io.router_resp.vc_sel.`1`[2]
connect route_q.io.enq.bits.vc_sel.`2`[0], io.router_resp.vc_sel.`2`[0]
node _T_13 = and(io.in.ready, io.in.valid)
node _T_14 = and(_T_13, io.in.bits.head)
node _T_15 = and(_T_14, at_dest)
when _T_15 :
connect route_q.io.enq.valid, UInt<1>(0h1)
connect route_q.io.enq.bits.vc_sel.`0`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[1], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`0`[2], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`1`[0], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`1`[1], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`1`[2], UInt<1>(0h0)
connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h0)
node _T_16 = eq(UInt<3>(0h4), io.in.bits.egress_id)
when _T_16 :
connect route_q.io.enq.bits.vc_sel.`2`[0], UInt<1>(0h1)
node _T_17 = eq(route_q.io.enq.ready, UInt<1>(0h0))
node _T_18 = and(route_q.io.enq.valid, _T_17)
node _T_19 = eq(_T_18, UInt<1>(0h0))
node _T_20 = asUInt(reset)
node _T_21 = eq(_T_20, UInt<1>(0h0))
when _T_21 :
node _T_22 = eq(_T_19, UInt<1>(0h0))
when _T_22 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:73 assert(!(route_q.io.enq.valid && !route_q.io.enq.ready))\n") : printf_1
assert(clock, _T_19, UInt<1>(0h1), "") : assert_1
inst vcalloc_buffer of Queue2_Flit_21
connect vcalloc_buffer.clock, clock
connect vcalloc_buffer.reset, reset
inst vcalloc_q of Queue1_VCAllocResp_10
connect vcalloc_q.clock, clock
connect vcalloc_q.reset, reset
connect vcalloc_buffer.io.enq.bits.virt_channel_id, route_buffer.io.deq.bits.virt_channel_id
connect vcalloc_buffer.io.enq.bits.flow.egress_node_id, route_buffer.io.deq.bits.flow.egress_node_id
connect vcalloc_buffer.io.enq.bits.flow.egress_node, route_buffer.io.deq.bits.flow.egress_node
connect vcalloc_buffer.io.enq.bits.flow.ingress_node_id, route_buffer.io.deq.bits.flow.ingress_node_id
connect vcalloc_buffer.io.enq.bits.flow.ingress_node, route_buffer.io.deq.bits.flow.ingress_node
connect vcalloc_buffer.io.enq.bits.flow.vnet_id, route_buffer.io.deq.bits.flow.vnet_id
connect vcalloc_buffer.io.enq.bits.payload, route_buffer.io.deq.bits.payload
connect vcalloc_buffer.io.enq.bits.tail, route_buffer.io.deq.bits.tail
connect vcalloc_buffer.io.enq.bits.head, route_buffer.io.deq.bits.head
connect io.vcalloc_req.bits.vc_sel.`0`, route_q.io.deq.bits.vc_sel.`0`
connect io.vcalloc_req.bits.vc_sel.`1`, route_q.io.deq.bits.vc_sel.`1`
connect io.vcalloc_req.bits.vc_sel.`2`, route_q.io.deq.bits.vc_sel.`2`
connect io.vcalloc_req.bits.flow, route_buffer.io.deq.bits.flow
connect io.vcalloc_req.bits.in_vc, UInt<1>(0h0)
node _vcalloc_buffer_io_enq_valid_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _vcalloc_buffer_io_enq_valid_T_1 = or(route_q.io.deq.valid, _vcalloc_buffer_io_enq_valid_T)
node _vcalloc_buffer_io_enq_valid_T_2 = and(route_buffer.io.deq.valid, _vcalloc_buffer_io_enq_valid_T_1)
node _vcalloc_buffer_io_enq_valid_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _vcalloc_buffer_io_enq_valid_T_4 = or(io.vcalloc_req.ready, _vcalloc_buffer_io_enq_valid_T_3)
node _vcalloc_buffer_io_enq_valid_T_5 = and(_vcalloc_buffer_io_enq_valid_T_2, _vcalloc_buffer_io_enq_valid_T_4)
connect vcalloc_buffer.io.enq.valid, _vcalloc_buffer_io_enq_valid_T_5
node _io_vcalloc_req_valid_T = and(route_buffer.io.deq.valid, route_q.io.deq.valid)
node _io_vcalloc_req_valid_T_1 = and(_io_vcalloc_req_valid_T, route_buffer.io.deq.bits.head)
node _io_vcalloc_req_valid_T_2 = and(_io_vcalloc_req_valid_T_1, vcalloc_buffer.io.enq.ready)
node _io_vcalloc_req_valid_T_3 = and(_io_vcalloc_req_valid_T_2, vcalloc_q.io.enq.ready)
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3
node _route_buffer_io_deq_ready_T = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_1 = or(route_q.io.deq.valid, _route_buffer_io_deq_ready_T)
node _route_buffer_io_deq_ready_T_2 = and(vcalloc_buffer.io.enq.ready, _route_buffer_io_deq_ready_T_1)
node _route_buffer_io_deq_ready_T_3 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_4 = or(io.vcalloc_req.ready, _route_buffer_io_deq_ready_T_3)
node _route_buffer_io_deq_ready_T_5 = and(_route_buffer_io_deq_ready_T_2, _route_buffer_io_deq_ready_T_4)
node _route_buffer_io_deq_ready_T_6 = eq(route_buffer.io.deq.bits.head, UInt<1>(0h0))
node _route_buffer_io_deq_ready_T_7 = or(vcalloc_q.io.enq.ready, _route_buffer_io_deq_ready_T_6)
node _route_buffer_io_deq_ready_T_8 = and(_route_buffer_io_deq_ready_T_5, _route_buffer_io_deq_ready_T_7)
connect route_buffer.io.deq.ready, _route_buffer_io_deq_ready_T_8
node _route_q_io_deq_ready_T = and(route_buffer.io.deq.ready, route_buffer.io.deq.valid)
node _route_q_io_deq_ready_T_1 = and(_route_q_io_deq_ready_T, route_buffer.io.deq.bits.tail)
connect route_q.io.deq.ready, _route_q_io_deq_ready_T_1
node _vcalloc_q_io_enq_valid_T = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
connect vcalloc_q.io.enq.valid, _vcalloc_q_io_enq_valid_T
connect vcalloc_q.io.enq.bits.vc_sel.`0`[0], io.vcalloc_resp.vc_sel.`0`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[1], io.vcalloc_resp.vc_sel.`0`[1]
connect vcalloc_q.io.enq.bits.vc_sel.`0`[2], io.vcalloc_resp.vc_sel.`0`[2]
connect vcalloc_q.io.enq.bits.vc_sel.`1`[0], io.vcalloc_resp.vc_sel.`1`[0]
connect vcalloc_q.io.enq.bits.vc_sel.`1`[1], io.vcalloc_resp.vc_sel.`1`[1]
connect vcalloc_q.io.enq.bits.vc_sel.`1`[2], io.vcalloc_resp.vc_sel.`1`[2]
connect vcalloc_q.io.enq.bits.vc_sel.`2`[0], io.vcalloc_resp.vc_sel.`2`[0]
node _T_23 = eq(vcalloc_q.io.enq.ready, UInt<1>(0h0))
node _T_24 = and(vcalloc_q.io.enq.valid, _T_23)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = asUInt(reset)
node _T_27 = eq(_T_26, UInt<1>(0h0))
when _T_27 :
node _T_28 = eq(_T_25, UInt<1>(0h0))
when _T_28 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at IngressUnit.scala:102 assert(!(vcalloc_q.io.enq.valid && !vcalloc_q.io.enq.ready))\n") : printf_2
assert(clock, _T_25, UInt<1>(0h1), "") : assert_2
connect io.salloc_req[0].bits.vc_sel.`0`, vcalloc_q.io.deq.bits.vc_sel.`0`
connect io.salloc_req[0].bits.vc_sel.`1`, vcalloc_q.io.deq.bits.vc_sel.`1`
connect io.salloc_req[0].bits.vc_sel.`2`, vcalloc_q.io.deq.bits.vc_sel.`2`
connect io.salloc_req[0].bits.tail, vcalloc_buffer.io.deq.bits.tail
node c_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[2], vcalloc_q.io.deq.bits.vc_sel.`0`[1])
node _c_T = cat(c_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[0])
node c_hi_1 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[2], vcalloc_q.io.deq.bits.vc_sel.`1`[1])
node _c_T_1 = cat(c_hi_1, vcalloc_q.io.deq.bits.vc_sel.`1`[0])
node c_hi_2 = cat(vcalloc_q.io.deq.bits.vc_sel.`2`[0], _c_T_1)
node _c_T_2 = cat(c_hi_2, _c_T)
node c_hi_3 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1])
node _c_T_3 = cat(c_hi_3, io.out_credit_available.`0`[0])
node c_hi_4 = cat(io.out_credit_available.`1`[2], io.out_credit_available.`1`[1])
node _c_T_4 = cat(c_hi_4, io.out_credit_available.`1`[0])
node c_hi_5 = cat(io.out_credit_available.`2`[0], _c_T_4)
node _c_T_5 = cat(c_hi_5, _c_T_3)
node _c_T_6 = and(_c_T_2, _c_T_5)
node c = neq(_c_T_6, UInt<1>(0h0))
node _io_salloc_req_0_valid_T = and(vcalloc_buffer.io.deq.valid, vcalloc_q.io.deq.valid)
node _io_salloc_req_0_valid_T_1 = and(_io_salloc_req_0_valid_T, c)
node _io_salloc_req_0_valid_T_2 = eq(io.block, UInt<1>(0h0))
node _io_salloc_req_0_valid_T_3 = and(_io_salloc_req_0_valid_T_1, _io_salloc_req_0_valid_T_2)
connect io.salloc_req[0].valid, _io_salloc_req_0_valid_T_3
node _vcalloc_buffer_io_deq_ready_T = and(io.salloc_req[0].ready, vcalloc_q.io.deq.valid)
node _vcalloc_buffer_io_deq_ready_T_1 = and(_vcalloc_buffer_io_deq_ready_T, c)
node _vcalloc_buffer_io_deq_ready_T_2 = eq(io.block, UInt<1>(0h0))
node _vcalloc_buffer_io_deq_ready_T_3 = and(_vcalloc_buffer_io_deq_ready_T_1, _vcalloc_buffer_io_deq_ready_T_2)
connect vcalloc_buffer.io.deq.ready, _vcalloc_buffer_io_deq_ready_T_3
node _vcalloc_q_io_deq_ready_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid)
node _vcalloc_q_io_deq_ready_T_1 = and(vcalloc_buffer.io.deq.bits.tail, _vcalloc_q_io_deq_ready_T)
connect vcalloc_q.io.deq.ready, _vcalloc_q_io_deq_ready_T_1
wire out_bundle : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}
connect io.out[0], out_bundle
node _out_bundle_valid_T = and(vcalloc_buffer.io.deq.ready, vcalloc_buffer.io.deq.valid)
connect out_bundle.valid, _out_bundle_valid_T
connect out_bundle.bits.flit, vcalloc_buffer.io.deq.bits
connect out_bundle.bits.flit.virt_channel_id, UInt<1>(0h0)
node _out_channel_oh_T = or(vcalloc_q.io.deq.bits.vc_sel.`0`[0], vcalloc_q.io.deq.bits.vc_sel.`0`[1])
node out_channel_oh_0 = or(_out_channel_oh_T, vcalloc_q.io.deq.bits.vc_sel.`0`[2])
node _out_channel_oh_T_1 = or(vcalloc_q.io.deq.bits.vc_sel.`1`[0], vcalloc_q.io.deq.bits.vc_sel.`1`[1])
node out_channel_oh_1 = or(_out_channel_oh_T_1, vcalloc_q.io.deq.bits.vc_sel.`1`[2])
node out_bundle_bits_out_virt_channel_hi = cat(vcalloc_q.io.deq.bits.vc_sel.`0`[2], vcalloc_q.io.deq.bits.vc_sel.`0`[1])
node _out_bundle_bits_out_virt_channel_T = cat(out_bundle_bits_out_virt_channel_hi, vcalloc_q.io.deq.bits.vc_sel.`0`[0])
node out_bundle_bits_out_virt_channel_hi_1 = bits(_out_bundle_bits_out_virt_channel_T, 2, 2)
node out_bundle_bits_out_virt_channel_lo = bits(_out_bundle_bits_out_virt_channel_T, 1, 0)
node _out_bundle_bits_out_virt_channel_T_1 = orr(out_bundle_bits_out_virt_channel_hi_1)
node _out_bundle_bits_out_virt_channel_T_2 = or(out_bundle_bits_out_virt_channel_hi_1, out_bundle_bits_out_virt_channel_lo)
node _out_bundle_bits_out_virt_channel_T_3 = bits(_out_bundle_bits_out_virt_channel_T_2, 1, 1)
node _out_bundle_bits_out_virt_channel_T_4 = cat(_out_bundle_bits_out_virt_channel_T_1, _out_bundle_bits_out_virt_channel_T_3)
node out_bundle_bits_out_virt_channel_hi_2 = cat(vcalloc_q.io.deq.bits.vc_sel.`1`[2], vcalloc_q.io.deq.bits.vc_sel.`1`[1])
node _out_bundle_bits_out_virt_channel_T_5 = cat(out_bundle_bits_out_virt_channel_hi_2, vcalloc_q.io.deq.bits.vc_sel.`1`[0])
node out_bundle_bits_out_virt_channel_hi_3 = bits(_out_bundle_bits_out_virt_channel_T_5, 2, 2)
node out_bundle_bits_out_virt_channel_lo_1 = bits(_out_bundle_bits_out_virt_channel_T_5, 1, 0)
node _out_bundle_bits_out_virt_channel_T_6 = orr(out_bundle_bits_out_virt_channel_hi_3)
node _out_bundle_bits_out_virt_channel_T_7 = or(out_bundle_bits_out_virt_channel_hi_3, out_bundle_bits_out_virt_channel_lo_1)
node _out_bundle_bits_out_virt_channel_T_8 = bits(_out_bundle_bits_out_virt_channel_T_7, 1, 1)
node _out_bundle_bits_out_virt_channel_T_9 = cat(_out_bundle_bits_out_virt_channel_T_6, _out_bundle_bits_out_virt_channel_T_8)
node _out_bundle_bits_out_virt_channel_T_10 = mux(out_channel_oh_0, _out_bundle_bits_out_virt_channel_T_4, UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_11 = mux(out_channel_oh_1, _out_bundle_bits_out_virt_channel_T_9, UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_12 = mux(vcalloc_q.io.deq.bits.vc_sel.`2`[0], UInt<1>(0h0), UInt<1>(0h0))
node _out_bundle_bits_out_virt_channel_T_13 = or(_out_bundle_bits_out_virt_channel_T_10, _out_bundle_bits_out_virt_channel_T_11)
node _out_bundle_bits_out_virt_channel_T_14 = or(_out_bundle_bits_out_virt_channel_T_13, _out_bundle_bits_out_virt_channel_T_12)
wire _out_bundle_bits_out_virt_channel_WIRE : UInt<2>
connect _out_bundle_bits_out_virt_channel_WIRE, _out_bundle_bits_out_virt_channel_T_14
connect out_bundle.bits.out_virt_channel, _out_bundle_bits_out_virt_channel_WIRE
node _io_debug_va_stall_T = eq(io.vcalloc_req.ready, UInt<1>(0h0))
node _io_debug_va_stall_T_1 = and(io.vcalloc_req.valid, _io_debug_va_stall_T)
connect io.debug.va_stall, _io_debug_va_stall_T_1
node _io_debug_sa_stall_T = eq(io.salloc_req[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(io.salloc_req[0].valid, _io_debug_sa_stall_T)
connect io.debug.sa_stall, _io_debug_sa_stall_T_1 | module IngressUnit_10( // @[IngressUnit.scala:11:7]
input clock, // @[IngressUnit.scala:11:7]
input reset, // @[IngressUnit.scala:11:7]
input io_vcalloc_req_ready, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_valid, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_1_2, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_2_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_1_2, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_0, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_1, // @[IngressUnit.scala:24:14]
input io_vcalloc_resp_vc_sel_0_2, // @[IngressUnit.scala:24:14]
input io_out_credit_available_2_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_1_0, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_1, // @[IngressUnit.scala:24:14]
input io_out_credit_available_0_2, // @[IngressUnit.scala:24:14]
input io_salloc_req_0_ready, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_valid, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_1_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[IngressUnit.scala:24:14]
output io_salloc_req_0_bits_tail, // @[IngressUnit.scala:24:14]
output io_out_0_valid, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_head, // @[IngressUnit.scala:24:14]
output io_out_0_bits_flit_tail, // @[IngressUnit.scala:24:14]
output [144:0] io_out_0_bits_flit_payload, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[IngressUnit.scala:24:14]
output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[IngressUnit.scala:24:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[IngressUnit.scala:24:14]
output [1:0] io_out_0_bits_out_virt_channel, // @[IngressUnit.scala:24:14]
output io_in_ready, // @[IngressUnit.scala:24:14]
input io_in_valid, // @[IngressUnit.scala:24:14]
input io_in_bits_head, // @[IngressUnit.scala:24:14]
input io_in_bits_tail, // @[IngressUnit.scala:24:14]
input [144:0] io_in_bits_payload, // @[IngressUnit.scala:24:14]
input [4:0] io_in_bits_egress_id // @[IngressUnit.scala:24:14]
);
wire _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_valid; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_2_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_1_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_0; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_1; // @[IngressUnit.scala:76:25]
wire _vcalloc_q_io_deq_bits_vc_sel_0_2; // @[IngressUnit.scala:76:25]
wire _vcalloc_buffer_io_enq_ready; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_valid; // @[IngressUnit.scala:75:30]
wire _vcalloc_buffer_io_deq_bits_tail; // @[IngressUnit.scala:75:30]
wire _route_q_io_enq_ready; // @[IngressUnit.scala:27:23]
wire _route_q_io_deq_valid; // @[IngressUnit.scala:27:23]
wire _route_buffer_io_enq_ready; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_valid; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_head; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_deq_bits_tail; // @[IngressUnit.scala:26:28]
wire [144:0] _route_buffer_io_deq_bits_payload; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_vnet_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_ingress_node; // @[IngressUnit.scala:26:28]
wire [2:0] _route_buffer_io_deq_bits_flow_ingress_node_id; // @[IngressUnit.scala:26:28]
wire [3:0] _route_buffer_io_deq_bits_flow_egress_node; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_flow_egress_node_id; // @[IngressUnit.scala:26:28]
wire [1:0] _route_buffer_io_deq_bits_virt_channel_id; // @[IngressUnit.scala:26:28]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_4 = io_in_bits_egress_id == 5'h10; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_5 = io_in_bits_egress_id == 5'h12; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_6 = io_in_bits_egress_id == 5'h14; // @[IngressUnit.scala:30:72]
wire _route_buffer_io_enq_bits_flow_egress_node_id_T_7 = io_in_bits_egress_id == 5'h16; // @[IngressUnit.scala:30:72]
wire [3:0] _route_buffer_io_enq_bits_flow_egress_node_T_10 = {1'h0, (_route_buffer_io_enq_bits_flow_egress_node_id_T_4 ? 3'h5 : 3'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_5 ? 3'h6 : 3'h0)} | (_route_buffer_io_enq_bits_flow_egress_node_id_T_6 ? 4'h9 : 4'h0) | (_route_buffer_io_enq_bits_flow_egress_node_id_T_7 ? 4'hA : 4'h0); // @[Mux.scala:30:73]
wire _GEN = _route_buffer_io_enq_ready & io_in_valid & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 == 4'h3; // @[Mux.scala:30:73]
wire route_q_io_enq_valid = _GEN | io_in_valid & _route_buffer_io_enq_ready & io_in_bits_head & _route_buffer_io_enq_bits_flow_egress_node_T_10 != 4'h3; // @[Mux.scala:30:73]
wire io_vcalloc_req_valid_0 = _route_buffer_io_deq_valid & _route_q_io_deq_valid & _route_buffer_io_deq_bits_head & _vcalloc_buffer_io_enq_ready & _vcalloc_q_io_enq_ready; // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :91:{54,78}, :92:{10,41}]
wire route_buffer_io_deq_ready = _vcalloc_buffer_io_enq_ready & (_route_q_io_deq_valid | ~_route_buffer_io_deq_bits_head) & (io_vcalloc_req_ready | ~_route_buffer_io_deq_bits_head) & (_vcalloc_q_io_enq_ready | ~_route_buffer_io_deq_bits_head); // @[IngressUnit.scala:26:28, :27:23, :75:30, :76:25, :88:30, :93:61, :94:{27,37}, :95:{27,37}, :96:29]
wire vcalloc_q_io_enq_valid = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to this FIRRTL code module CSRFile :
input clock : Clock
input reset : Reset
output io : { flip ungated_clock : Clock, flip interrupts : { debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>, meip : UInt<1>, seip : UInt<1>, lip : UInt<1>[0]}, flip hartid : UInt<1>, rw : { flip addr : UInt<12>, flip cmd : UInt<3>, rdata : UInt<64>, flip wdata : UInt<64>}, decode : { flip inst : UInt<32>, fp_illegal : UInt<1>, vector_illegal : UInt<1>, fp_csr : UInt<1>, vector_csr : UInt<1>, rocc_illegal : UInt<1>, read_illegal : UInt<1>, write_illegal : UInt<1>, write_flush : UInt<1>, system_illegal : UInt<1>, virtual_access_illegal : UInt<1>, virtual_system_illegal : UInt<1>}[1], csr_stall : UInt<1>, rw_stall : UInt<1>, eret : UInt<1>, singleStep : UInt<1>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, evec : UInt<40>, flip exception : UInt<1>, flip retire : UInt<1>, flip cause : UInt<64>, flip pc : UInt<40>, flip tval : UInt<40>, flip htval : UInt<40>, flip mhtinst_read_pseudo : UInt<1>, flip gva : UInt<1>, time : UInt<64>, fcsr_rm : UInt<3>, flip fcsr_flags : { valid : UInt<1>, bits : UInt<5>}, flip rocc_interrupt : UInt<1>, interrupt : UInt<1>, interrupt_cause : UInt<64>, bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[1], pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], counters : { eventSel : UInt<64>, flip inc : UInt<1>}[0], csrw_counter : UInt<32>, inhibit_cycle : UInt<1>, flip inst : UInt<32>[1], trace : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[1], mcontext : UInt<0>, scontext : UInt<0>, fiom : UInt<1>, customCSRs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4], roccCSRs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[0]}
connect io.rw_stall, UInt<1>(0h0)
wire _reset_mstatus_WIRE : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}
connect _reset_mstatus_WIRE.uie, UInt<1>(0h0)
connect _reset_mstatus_WIRE.sie, UInt<1>(0h0)
connect _reset_mstatus_WIRE.hie, UInt<1>(0h0)
connect _reset_mstatus_WIRE.mie, UInt<1>(0h0)
connect _reset_mstatus_WIRE.upie, UInt<1>(0h0)
connect _reset_mstatus_WIRE.spie, UInt<1>(0h0)
connect _reset_mstatus_WIRE.ube, UInt<1>(0h0)
connect _reset_mstatus_WIRE.mpie, UInt<1>(0h0)
connect _reset_mstatus_WIRE.spp, UInt<1>(0h0)
connect _reset_mstatus_WIRE.vs, UInt<2>(0h0)
connect _reset_mstatus_WIRE.mpp, UInt<2>(0h0)
connect _reset_mstatus_WIRE.fs, UInt<2>(0h0)
connect _reset_mstatus_WIRE.xs, UInt<2>(0h0)
connect _reset_mstatus_WIRE.mprv, UInt<1>(0h0)
connect _reset_mstatus_WIRE.sum, UInt<1>(0h0)
connect _reset_mstatus_WIRE.mxr, UInt<1>(0h0)
connect _reset_mstatus_WIRE.tvm, UInt<1>(0h0)
connect _reset_mstatus_WIRE.tw, UInt<1>(0h0)
connect _reset_mstatus_WIRE.tsr, UInt<1>(0h0)
connect _reset_mstatus_WIRE.zero1, UInt<8>(0h0)
connect _reset_mstatus_WIRE.sd_rv32, UInt<1>(0h0)
connect _reset_mstatus_WIRE.uxl, UInt<2>(0h0)
connect _reset_mstatus_WIRE.sxl, UInt<2>(0h0)
connect _reset_mstatus_WIRE.sbe, UInt<1>(0h0)
connect _reset_mstatus_WIRE.mbe, UInt<1>(0h0)
connect _reset_mstatus_WIRE.gva, UInt<1>(0h0)
connect _reset_mstatus_WIRE.mpv, UInt<1>(0h0)
connect _reset_mstatus_WIRE.zero2, UInt<23>(0h0)
connect _reset_mstatus_WIRE.sd, UInt<1>(0h0)
connect _reset_mstatus_WIRE.v, UInt<1>(0h0)
connect _reset_mstatus_WIRE.prv, UInt<2>(0h0)
connect _reset_mstatus_WIRE.dv, UInt<1>(0h0)
connect _reset_mstatus_WIRE.dprv, UInt<2>(0h0)
connect _reset_mstatus_WIRE.isa, UInt<32>(0h0)
connect _reset_mstatus_WIRE.wfi, UInt<1>(0h0)
connect _reset_mstatus_WIRE.cease, UInt<1>(0h0)
connect _reset_mstatus_WIRE.debug, UInt<1>(0h0)
wire reset_mstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}
connect reset_mstatus, _reset_mstatus_WIRE
connect reset_mstatus.mpp, UInt<2>(0h3)
connect reset_mstatus.prv, UInt<2>(0h3)
connect reset_mstatus.xs, UInt<2>(0h3)
regreset reg_mstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, clock, reset, reset_mstatus
wire new_prv : UInt
connect new_prv, reg_mstatus.prv
node _reg_mstatus_prv_T = eq(new_prv, UInt<2>(0h2))
node _reg_mstatus_prv_T_1 = mux(_reg_mstatus_prv_T, UInt<1>(0h0), new_prv)
connect reg_mstatus.prv, _reg_mstatus_prv_T_1
wire _reset_dcsr_WIRE : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>}
connect _reset_dcsr_WIRE.prv, UInt<2>(0h0)
connect _reset_dcsr_WIRE.step, UInt<1>(0h0)
connect _reset_dcsr_WIRE.zero1, UInt<2>(0h0)
connect _reset_dcsr_WIRE.v, UInt<1>(0h0)
connect _reset_dcsr_WIRE.cause, UInt<3>(0h0)
connect _reset_dcsr_WIRE.stoptime, UInt<1>(0h0)
connect _reset_dcsr_WIRE.stopcycle, UInt<1>(0h0)
connect _reset_dcsr_WIRE.zero2, UInt<1>(0h0)
connect _reset_dcsr_WIRE.ebreaku, UInt<1>(0h0)
connect _reset_dcsr_WIRE.ebreaks, UInt<1>(0h0)
connect _reset_dcsr_WIRE.ebreakh, UInt<1>(0h0)
connect _reset_dcsr_WIRE.ebreakm, UInt<1>(0h0)
connect _reset_dcsr_WIRE.zero3, UInt<12>(0h0)
connect _reset_dcsr_WIRE.zero4, UInt<2>(0h0)
connect _reset_dcsr_WIRE.xdebugver, UInt<2>(0h0)
wire reset_dcsr : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>}
connect reset_dcsr, _reset_dcsr_WIRE
connect reset_dcsr.xdebugver, UInt<1>(0h1)
connect reset_dcsr.prv, UInt<2>(0h3)
regreset reg_dcsr : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>}, clock, reset, reset_dcsr
wire sup : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
connect sup.usip, UInt<1>(0h0)
connect sup.ssip, UInt<1>(0h1)
connect sup.vssip, UInt<1>(0h0)
connect sup.msip, UInt<1>(0h1)
connect sup.utip, UInt<1>(0h0)
connect sup.stip, UInt<1>(0h1)
connect sup.vstip, UInt<1>(0h0)
connect sup.mtip, UInt<1>(0h1)
connect sup.ueip, UInt<1>(0h0)
connect sup.seip, UInt<1>(0h1)
connect sup.vseip, UInt<1>(0h0)
connect sup.meip, UInt<1>(0h1)
connect sup.sgeip, UInt<1>(0h0)
connect sup.rocc, UInt<1>(0h1)
connect sup.debug, UInt<1>(0h0)
connect sup.zero1, UInt<1>(0h0)
wire del : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
connect del, sup
connect del.msip, UInt<1>(0h0)
connect del.mtip, UInt<1>(0h0)
connect del.meip, UInt<1>(0h0)
node lo_lo_lo = cat(sup.ssip, sup.usip)
node lo_lo_hi = cat(sup.msip, sup.vssip)
node lo_lo = cat(lo_lo_hi, lo_lo_lo)
node lo_hi_lo = cat(sup.stip, sup.utip)
node lo_hi_hi = cat(sup.mtip, sup.vstip)
node lo_hi = cat(lo_hi_hi, lo_hi_lo)
node lo = cat(lo_hi, lo_lo)
node hi_lo_lo = cat(sup.seip, sup.ueip)
node hi_lo_hi = cat(sup.meip, sup.vseip)
node hi_lo = cat(hi_lo_hi, hi_lo_lo)
node hi_hi_lo = cat(sup.rocc, sup.sgeip)
node hi_hi_hi_hi = cat(UInt<0>(0h0), sup.zero1)
node hi_hi_hi = cat(hi_hi_hi_hi, sup.debug)
node hi_hi = cat(hi_hi_hi, hi_hi_lo)
node hi = cat(hi_hi, hi_lo)
node _T = cat(hi, lo)
node supported_interrupts = or(_T, UInt<1>(0h0))
node lo_lo_lo_1 = cat(del.ssip, del.usip)
node lo_lo_hi_1 = cat(del.msip, del.vssip)
node lo_lo_1 = cat(lo_lo_hi_1, lo_lo_lo_1)
node lo_hi_lo_1 = cat(del.stip, del.utip)
node lo_hi_hi_1 = cat(del.mtip, del.vstip)
node lo_hi_1 = cat(lo_hi_hi_1, lo_hi_lo_1)
node lo_1 = cat(lo_hi_1, lo_lo_1)
node hi_lo_lo_1 = cat(del.seip, del.ueip)
node hi_lo_hi_1 = cat(del.meip, del.vseip)
node hi_lo_1 = cat(hi_lo_hi_1, hi_lo_lo_1)
node hi_hi_lo_1 = cat(del.rocc, del.sgeip)
node hi_hi_hi_hi_1 = cat(UInt<0>(0h0), del.zero1)
node hi_hi_hi_1 = cat(hi_hi_hi_hi_1, del.debug)
node hi_hi_1 = cat(hi_hi_hi_1, hi_hi_lo_1)
node hi_1 = cat(hi_hi_1, hi_lo_1)
node delegable_interrupts = cat(hi_1, lo_1)
wire _always_WIRE : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
connect _always_WIRE.usip, UInt<1>(0h0)
connect _always_WIRE.ssip, UInt<1>(0h0)
connect _always_WIRE.vssip, UInt<1>(0h0)
connect _always_WIRE.msip, UInt<1>(0h0)
connect _always_WIRE.utip, UInt<1>(0h0)
connect _always_WIRE.stip, UInt<1>(0h0)
connect _always_WIRE.vstip, UInt<1>(0h0)
connect _always_WIRE.mtip, UInt<1>(0h0)
connect _always_WIRE.ueip, UInt<1>(0h0)
connect _always_WIRE.seip, UInt<1>(0h0)
connect _always_WIRE.vseip, UInt<1>(0h0)
connect _always_WIRE.meip, UInt<1>(0h0)
connect _always_WIRE.sgeip, UInt<1>(0h0)
connect _always_WIRE.rocc, UInt<1>(0h0)
connect _always_WIRE.debug, UInt<1>(0h0)
connect _always_WIRE.zero1, UInt<1>(0h0)
wire always : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
connect always, _always_WIRE
connect always.vssip, UInt<1>(0h0)
connect always.vstip, UInt<1>(0h0)
connect always.vseip, UInt<1>(0h0)
wire deleg : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
connect deleg, always
node lo_lo_lo_2 = cat(deleg.ssip, deleg.usip)
node lo_lo_hi_2 = cat(deleg.msip, deleg.vssip)
node lo_lo_2 = cat(lo_lo_hi_2, lo_lo_lo_2)
node lo_hi_lo_2 = cat(deleg.stip, deleg.utip)
node lo_hi_hi_2 = cat(deleg.mtip, deleg.vstip)
node lo_hi_2 = cat(lo_hi_hi_2, lo_hi_lo_2)
node lo_2 = cat(lo_hi_2, lo_lo_2)
node hi_lo_lo_2 = cat(deleg.seip, deleg.ueip)
node hi_lo_hi_2 = cat(deleg.meip, deleg.vseip)
node hi_lo_2 = cat(hi_lo_hi_2, hi_lo_lo_2)
node hi_hi_lo_2 = cat(deleg.rocc, deleg.sgeip)
node hi_hi_hi_hi_2 = cat(UInt<0>(0h0), deleg.zero1)
node hi_hi_hi_2 = cat(hi_hi_hi_hi_2, deleg.debug)
node hi_hi_2 = cat(hi_hi_hi_2, hi_hi_lo_2)
node hi_2 = cat(hi_hi_2, hi_lo_2)
node hs_delegable_interrupts = cat(hi_2, lo_2)
node lo_lo_lo_3 = cat(always.ssip, always.usip)
node lo_lo_hi_3 = cat(always.msip, always.vssip)
node lo_lo_3 = cat(lo_lo_hi_3, lo_lo_lo_3)
node lo_hi_lo_3 = cat(always.stip, always.utip)
node lo_hi_hi_3 = cat(always.mtip, always.vstip)
node lo_hi_3 = cat(lo_hi_hi_3, lo_hi_lo_3)
node lo_3 = cat(lo_hi_3, lo_lo_3)
node hi_lo_lo_3 = cat(always.seip, always.ueip)
node hi_lo_hi_3 = cat(always.meip, always.vseip)
node hi_lo_3 = cat(hi_lo_hi_3, hi_lo_lo_3)
node hi_hi_lo_3 = cat(always.rocc, always.sgeip)
node hi_hi_hi_hi_3 = cat(UInt<0>(0h0), always.zero1)
node hi_hi_hi_3 = cat(hi_hi_hi_hi_3, always.debug)
node hi_hi_3 = cat(hi_hi_hi_3, hi_hi_lo_3)
node hi_3 = cat(hi_hi_3, hi_lo_3)
node mideleg_always_hs = cat(hi_3, lo_3)
regreset reg_debug : UInt<1>, clock, reset, UInt<1>(0h0)
reg reg_dpc : UInt<40>, clock
reg reg_dscratch0 : UInt<64>, clock
reg reg_singleStepped : UInt<1>, clock
reg reg_tselect : UInt<1>, clock
reg reg_bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[2], clock
reg reg_pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>}[8], clock
reg reg_mie : UInt<64>, clock
reg reg_mideleg : UInt<64>, clock
node _T_1 = and(reg_mideleg, delegable_interrupts)
node _T_2 = or(_T_1, mideleg_always_hs)
node read_mideleg = mux(UInt<1>(0h1), _T_2, UInt<1>(0h0))
reg reg_medeleg : UInt<64>, clock
node _T_3 = and(reg_medeleg, UInt<16>(0hb15d))
node read_medeleg = mux(UInt<1>(0h1), _T_3, UInt<1>(0h0))
reg reg_mip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}, clock
reg reg_mepc : UInt<40>, clock
regreset reg_mcause : UInt<64>, clock, reset, UInt<64>(0h0)
reg reg_mtval : UInt<40>, clock
reg reg_mtval2 : UInt<40>, clock
reg reg_mscratch : UInt<64>, clock
regreset reg_mtvec : UInt<32>, clock, reset, UInt<32>(0h0)
wire _reset_mnstatus_WIRE : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>}
connect _reset_mnstatus_WIRE.zero1, UInt<3>(0h0)
connect _reset_mnstatus_WIRE.mie, UInt<1>(0h0)
connect _reset_mnstatus_WIRE.zero2, UInt<3>(0h0)
connect _reset_mnstatus_WIRE.mpv, UInt<1>(0h0)
connect _reset_mnstatus_WIRE.zero3, UInt<3>(0h0)
connect _reset_mnstatus_WIRE.mpp, UInt<2>(0h0)
wire reset_mnstatus : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>}
connect reset_mnstatus, _reset_mnstatus_WIRE
connect reset_mnstatus.mpp, UInt<2>(0h3)
reg reg_mnscratch : UInt<64>, clock
reg reg_mnepc : UInt<40>, clock
regreset reg_mncause : UInt<64>, clock, reset, UInt<64>(0h0)
regreset reg_mnstatus : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>}, clock, reset, reset_mnstatus
regreset reg_rnmie : UInt<1>, clock, reset, UInt<1>(0h1)
wire _reg_menvcfg_WIRE : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}
connect _reg_menvcfg_WIRE.fiom, UInt<1>(0h0)
connect _reg_menvcfg_WIRE.zero3, UInt<3>(0h0)
connect _reg_menvcfg_WIRE.cbie, UInt<2>(0h0)
connect _reg_menvcfg_WIRE.cbcfe, UInt<1>(0h0)
connect _reg_menvcfg_WIRE.cbze, UInt<1>(0h0)
connect _reg_menvcfg_WIRE.zero54, UInt<54>(0h0)
connect _reg_menvcfg_WIRE.pbmte, UInt<1>(0h0)
connect _reg_menvcfg_WIRE.stce, UInt<1>(0h0)
regreset reg_menvcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}, clock, reset, _reg_menvcfg_WIRE
wire _reg_senvcfg_WIRE : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}
connect _reg_senvcfg_WIRE.fiom, UInt<1>(0h0)
connect _reg_senvcfg_WIRE.zero3, UInt<3>(0h0)
connect _reg_senvcfg_WIRE.cbie, UInt<2>(0h0)
connect _reg_senvcfg_WIRE.cbcfe, UInt<1>(0h0)
connect _reg_senvcfg_WIRE.cbze, UInt<1>(0h0)
connect _reg_senvcfg_WIRE.zero54, UInt<54>(0h0)
connect _reg_senvcfg_WIRE.pbmte, UInt<1>(0h0)
connect _reg_senvcfg_WIRE.stce, UInt<1>(0h0)
regreset reg_senvcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}, clock, reset, _reg_senvcfg_WIRE
wire _reg_henvcfg_WIRE : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}
connect _reg_henvcfg_WIRE.fiom, UInt<1>(0h0)
connect _reg_henvcfg_WIRE.zero3, UInt<3>(0h0)
connect _reg_henvcfg_WIRE.cbie, UInt<2>(0h0)
connect _reg_henvcfg_WIRE.cbcfe, UInt<1>(0h0)
connect _reg_henvcfg_WIRE.cbze, UInt<1>(0h0)
connect _reg_henvcfg_WIRE.zero54, UInt<54>(0h0)
connect _reg_henvcfg_WIRE.pbmte, UInt<1>(0h0)
connect _reg_henvcfg_WIRE.stce, UInt<1>(0h0)
regreset reg_henvcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}, clock, reset, _reg_henvcfg_WIRE
reg reg_mcounteren : UInt<32>, clock
node _T_4 = and(reg_mcounteren, UInt<3>(0h7))
node read_mcounteren = mux(UInt<1>(0h1), _T_4, UInt<1>(0h0))
reg reg_scounteren : UInt<32>, clock
node _T_5 = and(reg_scounteren, UInt<3>(0h7))
node read_scounteren = mux(UInt<1>(0h1), _T_5, UInt<1>(0h0))
reg reg_hideleg : UInt<64>, clock
node _T_6 = and(reg_hideleg, hs_delegable_interrupts)
node read_hideleg = mux(UInt<1>(0h0), _T_6, UInt<1>(0h0))
reg reg_hedeleg : UInt<64>, clock
node _T_7 = and(reg_hedeleg, UInt<16>(0hb1ff))
node read_hedeleg = mux(UInt<1>(0h0), _T_7, UInt<1>(0h0))
reg reg_hcounteren : UInt<32>, clock
node _T_8 = and(reg_hcounteren, UInt<3>(0h7))
node read_hcounteren = mux(UInt<1>(0h0), _T_8, UInt<1>(0h0))
wire _reg_hstatus_WIRE : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}
connect _reg_hstatus_WIRE.zero1, UInt<5>(0h0)
connect _reg_hstatus_WIRE.vsbe, UInt<1>(0h0)
connect _reg_hstatus_WIRE.gva, UInt<1>(0h0)
connect _reg_hstatus_WIRE.spv, UInt<1>(0h0)
connect _reg_hstatus_WIRE.spvp, UInt<1>(0h0)
connect _reg_hstatus_WIRE.hu, UInt<1>(0h0)
connect _reg_hstatus_WIRE.zero2, UInt<2>(0h0)
connect _reg_hstatus_WIRE.vgein, UInt<6>(0h0)
connect _reg_hstatus_WIRE.zero3, UInt<2>(0h0)
connect _reg_hstatus_WIRE.vtvm, UInt<1>(0h0)
connect _reg_hstatus_WIRE.vtw, UInt<1>(0h0)
connect _reg_hstatus_WIRE.vtsr, UInt<1>(0h0)
connect _reg_hstatus_WIRE.zero5, UInt<9>(0h0)
connect _reg_hstatus_WIRE.vsxl, UInt<2>(0h0)
connect _reg_hstatus_WIRE.zero6, UInt<30>(0h0)
regreset reg_hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, clock, reset, _reg_hstatus_WIRE
reg reg_hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock
reg reg_htval : UInt<40>, clock
node read_hvip_lo_lo_lo = cat(reg_mip.ssip, reg_mip.usip)
node read_hvip_lo_lo_hi = cat(reg_mip.msip, reg_mip.vssip)
node read_hvip_lo_lo = cat(read_hvip_lo_lo_hi, read_hvip_lo_lo_lo)
node read_hvip_lo_hi_lo = cat(reg_mip.stip, reg_mip.utip)
node read_hvip_lo_hi_hi = cat(reg_mip.mtip, reg_mip.vstip)
node read_hvip_lo_hi = cat(read_hvip_lo_hi_hi, read_hvip_lo_hi_lo)
node read_hvip_lo = cat(read_hvip_lo_hi, read_hvip_lo_lo)
node read_hvip_hi_lo_lo = cat(reg_mip.seip, reg_mip.ueip)
node read_hvip_hi_lo_hi = cat(reg_mip.meip, reg_mip.vseip)
node read_hvip_hi_lo = cat(read_hvip_hi_lo_hi, read_hvip_hi_lo_lo)
node read_hvip_hi_hi_lo = cat(reg_mip.rocc, reg_mip.sgeip)
node read_hvip_hi_hi_hi_hi = cat(UInt<0>(0h0), reg_mip.zero1)
node read_hvip_hi_hi_hi = cat(read_hvip_hi_hi_hi_hi, reg_mip.debug)
node read_hvip_hi_hi = cat(read_hvip_hi_hi_hi, read_hvip_hi_hi_lo)
node read_hvip_hi = cat(read_hvip_hi_hi, read_hvip_hi_lo)
node _read_hvip_T = cat(read_hvip_hi, read_hvip_lo)
node read_hvip = and(_read_hvip_T, hs_delegable_interrupts)
node read_hie = and(reg_mie, hs_delegable_interrupts)
reg reg_vstvec : UInt<40>, clock
node _T_9 = bits(reg_vstvec, 0, 0)
node _T_10 = mux(_T_9, UInt<8>(0hfe), UInt<2>(0h2))
node _T_11 = and(reg_vstvec, UInt<1>(0h0))
node _T_12 = or(_T_10, _T_11)
node _T_13 = not(_T_12)
node _T_14 = and(reg_vstvec, _T_13)
node _T_15 = bits(_T_14, 39, 39)
node _T_16 = mux(_T_15, UInt<24>(0hffffff), UInt<24>(0h0))
node read_vstvec = cat(_T_16, _T_14)
reg reg_vsstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, clock
reg reg_vsscratch : UInt<64>, clock
reg reg_vsepc : UInt<40>, clock
reg reg_vscause : UInt<64>, clock
reg reg_vstval : UInt<40>, clock
reg reg_vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock
reg reg_sepc : UInt<40>, clock
reg reg_scause : UInt<64>, clock
reg reg_stval : UInt<40>, clock
reg reg_sscratch : UInt<64>, clock
reg reg_stvec : UInt<39>, clock
reg reg_satp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, clock
regreset reg_wfi : UInt<1>, io.ungated_clock, reset, UInt<1>(0h0)
reg reg_fflags : UInt<5>, clock
reg reg_frm : UInt<3>, clock
reg reg_mtinst_read_pseudo : UInt<1>, clock
reg reg_htinst_read_pseudo : UInt<1>, clock
node hi_4 = cat(reg_mtinst_read_pseudo, reg_mtinst_read_pseudo)
node read_mtinst = cat(hi_4, UInt<12>(0h0))
node hi_5 = cat(reg_htinst_read_pseudo, reg_htinst_read_pseudo)
node read_htinst = cat(hi_5, UInt<12>(0h0))
regreset reg_mcountinhibit : UInt<3>, clock, reset, UInt<3>(0h0)
node _io_inhibit_cycle_T = bits(reg_mcountinhibit, 0, 0)
connect io.inhibit_cycle, _io_inhibit_cycle_T
node x3 = bits(reg_mcountinhibit, 2, 2)
regreset small : UInt<6>, clock, reset, UInt<6>(0h0)
node nextSmall = add(small, io.retire)
node _T_17 = eq(x3, UInt<1>(0h0))
when _T_17 :
connect small, nextSmall
regreset large : UInt<58>, clock, reset, UInt<58>(0h0)
node _large_T = bits(nextSmall, 6, 6)
node _large_T_1 = eq(x3, UInt<1>(0h0))
node _large_T_2 = and(_large_T, _large_T_1)
when _large_T_2 :
node _large_r_T = add(large, UInt<1>(0h1))
node _large_r_T_1 = tail(_large_r_T, 1)
connect large, _large_r_T_1
node value = cat(large, small)
node x10 = eq(io.csr_stall, UInt<1>(0h0))
node x11 = bits(reg_mcountinhibit, 0, 0)
regreset small_1 : UInt<6>, io.ungated_clock, reset, UInt<6>(0h0)
node nextSmall_1 = add(small_1, x10)
node _T_18 = eq(x11, UInt<1>(0h0))
when _T_18 :
connect small_1, nextSmall_1
regreset large_1 : UInt<58>, io.ungated_clock, reset, UInt<58>(0h0)
node _large_T_3 = bits(nextSmall_1, 6, 6)
node _large_T_4 = eq(x11, UInt<1>(0h0))
node _large_T_5 = and(_large_T_3, _large_T_4)
when _large_T_5 :
node _large_r_T_2 = add(large_1, UInt<1>(0h1))
node _large_r_T_3 = tail(_large_r_T_2, 1)
connect large_1, _large_r_T_3
node value_1 = cat(large_1, small_1)
wire mip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
connect mip, reg_mip
connect mip.mtip, io.interrupts.mtip
connect mip.msip, io.interrupts.msip
connect mip.meip, io.interrupts.meip
node _mip_seip_T = or(reg_mip.seip, io.interrupts.seip)
connect mip.seip, _mip_seip_T
connect mip.rocc, io.rocc_interrupt
node read_mip_lo_lo_lo = cat(mip.ssip, mip.usip)
node read_mip_lo_lo_hi = cat(mip.msip, mip.vssip)
node read_mip_lo_lo = cat(read_mip_lo_lo_hi, read_mip_lo_lo_lo)
node read_mip_lo_hi_lo = cat(mip.stip, mip.utip)
node read_mip_lo_hi_hi = cat(mip.mtip, mip.vstip)
node read_mip_lo_hi = cat(read_mip_lo_hi_hi, read_mip_lo_hi_lo)
node read_mip_lo = cat(read_mip_lo_hi, read_mip_lo_lo)
node read_mip_hi_lo_lo = cat(mip.seip, mip.ueip)
node read_mip_hi_lo_hi = cat(mip.meip, mip.vseip)
node read_mip_hi_lo = cat(read_mip_hi_lo_hi, read_mip_hi_lo_lo)
node read_mip_hi_hi_lo = cat(mip.rocc, mip.sgeip)
node read_mip_hi_hi_hi_hi = cat(UInt<0>(0h0), mip.zero1)
node read_mip_hi_hi_hi = cat(read_mip_hi_hi_hi_hi, mip.debug)
node read_mip_hi_hi = cat(read_mip_hi_hi_hi, read_mip_hi_hi_lo)
node read_mip_hi = cat(read_mip_hi_hi, read_mip_hi_lo)
node _read_mip_T = cat(read_mip_hi, read_mip_lo)
node read_mip = and(_read_mip_T, supported_interrupts)
node read_hip = and(read_mip, hs_delegable_interrupts)
node _pending_interrupts_T = and(read_mip, reg_mie)
node pending_interrupts = or(UInt<1>(0h0), _pending_interrupts_T)
node d_interrupts = shl(io.interrupts.debug, 14)
node _m_interrupts_T = leq(reg_mstatus.prv, UInt<1>(0h1))
node _m_interrupts_T_1 = or(_m_interrupts_T, reg_mstatus.mie)
node _m_interrupts_T_2 = and(reg_rnmie, _m_interrupts_T_1)
node _m_interrupts_T_3 = not(pending_interrupts)
node _m_interrupts_T_4 = or(_m_interrupts_T_3, read_mideleg)
node _m_interrupts_T_5 = not(_m_interrupts_T_4)
node m_interrupts = mux(_m_interrupts_T_2, _m_interrupts_T_5, UInt<1>(0h0))
node _s_interrupts_T = lt(reg_mstatus.prv, UInt<1>(0h1))
node _s_interrupts_T_1 = or(reg_mstatus.v, _s_interrupts_T)
node _s_interrupts_T_2 = eq(reg_mstatus.prv, UInt<1>(0h1))
node _s_interrupts_T_3 = and(_s_interrupts_T_2, reg_mstatus.sie)
node _s_interrupts_T_4 = or(_s_interrupts_T_1, _s_interrupts_T_3)
node _s_interrupts_T_5 = and(reg_rnmie, _s_interrupts_T_4)
node _s_interrupts_T_6 = and(pending_interrupts, read_mideleg)
node _s_interrupts_T_7 = not(read_hideleg)
node _s_interrupts_T_8 = and(_s_interrupts_T_6, _s_interrupts_T_7)
node s_interrupts = mux(_s_interrupts_T_5, _s_interrupts_T_8, UInt<1>(0h0))
node _vs_interrupts_T = lt(reg_mstatus.prv, UInt<1>(0h1))
node _vs_interrupts_T_1 = eq(reg_mstatus.prv, UInt<1>(0h1))
node _vs_interrupts_T_2 = and(_vs_interrupts_T_1, reg_vsstatus.sie)
node _vs_interrupts_T_3 = or(_vs_interrupts_T, _vs_interrupts_T_2)
node _vs_interrupts_T_4 = and(reg_mstatus.v, _vs_interrupts_T_3)
node _vs_interrupts_T_5 = and(reg_rnmie, _vs_interrupts_T_4)
node _vs_interrupts_T_6 = and(pending_interrupts, read_hideleg)
node vs_interrupts = mux(_vs_interrupts_T_5, _vs_interrupts_T_6, UInt<1>(0h0))
node _any_T = bits(d_interrupts, 14, 14)
node _any_T_1 = bits(d_interrupts, 13, 13)
node _any_T_2 = bits(d_interrupts, 12, 12)
node _any_T_3 = bits(d_interrupts, 11, 11)
node _any_T_4 = bits(d_interrupts, 3, 3)
node _any_T_5 = bits(d_interrupts, 7, 7)
node _any_T_6 = bits(d_interrupts, 9, 9)
node _any_T_7 = bits(d_interrupts, 1, 1)
node _any_T_8 = bits(d_interrupts, 5, 5)
node _any_T_9 = bits(d_interrupts, 10, 10)
node _any_T_10 = bits(d_interrupts, 2, 2)
node _any_T_11 = bits(d_interrupts, 6, 6)
node _any_T_12 = bits(d_interrupts, 8, 8)
node _any_T_13 = bits(d_interrupts, 0, 0)
node _any_T_14 = bits(d_interrupts, 4, 4)
node _any_T_15 = bits(m_interrupts, 15, 15)
node _any_T_16 = bits(m_interrupts, 14, 14)
node _any_T_17 = bits(m_interrupts, 13, 13)
node _any_T_18 = bits(m_interrupts, 12, 12)
node _any_T_19 = bits(m_interrupts, 11, 11)
node _any_T_20 = bits(m_interrupts, 3, 3)
node _any_T_21 = bits(m_interrupts, 7, 7)
node _any_T_22 = bits(m_interrupts, 9, 9)
node _any_T_23 = bits(m_interrupts, 1, 1)
node _any_T_24 = bits(m_interrupts, 5, 5)
node _any_T_25 = bits(m_interrupts, 10, 10)
node _any_T_26 = bits(m_interrupts, 2, 2)
node _any_T_27 = bits(m_interrupts, 6, 6)
node _any_T_28 = bits(m_interrupts, 8, 8)
node _any_T_29 = bits(m_interrupts, 0, 0)
node _any_T_30 = bits(m_interrupts, 4, 4)
node _any_T_31 = bits(s_interrupts, 15, 15)
node _any_T_32 = bits(s_interrupts, 14, 14)
node _any_T_33 = bits(s_interrupts, 13, 13)
node _any_T_34 = bits(s_interrupts, 12, 12)
node _any_T_35 = bits(s_interrupts, 11, 11)
node _any_T_36 = bits(s_interrupts, 3, 3)
node _any_T_37 = bits(s_interrupts, 7, 7)
node _any_T_38 = bits(s_interrupts, 9, 9)
node _any_T_39 = bits(s_interrupts, 1, 1)
node _any_T_40 = bits(s_interrupts, 5, 5)
node _any_T_41 = bits(s_interrupts, 10, 10)
node _any_T_42 = bits(s_interrupts, 2, 2)
node _any_T_43 = bits(s_interrupts, 6, 6)
node _any_T_44 = bits(s_interrupts, 8, 8)
node _any_T_45 = bits(s_interrupts, 0, 0)
node _any_T_46 = bits(s_interrupts, 4, 4)
node _any_T_47 = bits(vs_interrupts, 15, 15)
node _any_T_48 = bits(vs_interrupts, 14, 14)
node _any_T_49 = bits(vs_interrupts, 13, 13)
node _any_T_50 = bits(vs_interrupts, 12, 12)
node _any_T_51 = bits(vs_interrupts, 11, 11)
node _any_T_52 = bits(vs_interrupts, 3, 3)
node _any_T_53 = bits(vs_interrupts, 7, 7)
node _any_T_54 = bits(vs_interrupts, 9, 9)
node _any_T_55 = bits(vs_interrupts, 1, 1)
node _any_T_56 = bits(vs_interrupts, 5, 5)
node _any_T_57 = bits(vs_interrupts, 10, 10)
node _any_T_58 = bits(vs_interrupts, 2, 2)
node _any_T_59 = bits(vs_interrupts, 6, 6)
node _any_T_60 = bits(vs_interrupts, 8, 8)
node _any_T_61 = bits(vs_interrupts, 0, 0)
node _any_T_62 = bits(vs_interrupts, 4, 4)
node _any_T_63 = or(_any_T, _any_T_1)
node _any_T_64 = or(_any_T_63, _any_T_2)
node _any_T_65 = or(_any_T_64, _any_T_3)
node _any_T_66 = or(_any_T_65, _any_T_4)
node _any_T_67 = or(_any_T_66, _any_T_5)
node _any_T_68 = or(_any_T_67, _any_T_6)
node _any_T_69 = or(_any_T_68, _any_T_7)
node _any_T_70 = or(_any_T_69, _any_T_8)
node _any_T_71 = or(_any_T_70, _any_T_9)
node _any_T_72 = or(_any_T_71, _any_T_10)
node _any_T_73 = or(_any_T_72, _any_T_11)
node _any_T_74 = or(_any_T_73, _any_T_12)
node _any_T_75 = or(_any_T_74, _any_T_13)
node _any_T_76 = or(_any_T_75, _any_T_14)
node _any_T_77 = or(_any_T_76, UInt<1>(0h0))
node _any_T_78 = or(_any_T_77, _any_T_15)
node _any_T_79 = or(_any_T_78, _any_T_16)
node _any_T_80 = or(_any_T_79, _any_T_17)
node _any_T_81 = or(_any_T_80, _any_T_18)
node _any_T_82 = or(_any_T_81, _any_T_19)
node _any_T_83 = or(_any_T_82, _any_T_20)
node _any_T_84 = or(_any_T_83, _any_T_21)
node _any_T_85 = or(_any_T_84, _any_T_22)
node _any_T_86 = or(_any_T_85, _any_T_23)
node _any_T_87 = or(_any_T_86, _any_T_24)
node _any_T_88 = or(_any_T_87, _any_T_25)
node _any_T_89 = or(_any_T_88, _any_T_26)
node _any_T_90 = or(_any_T_89, _any_T_27)
node _any_T_91 = or(_any_T_90, _any_T_28)
node _any_T_92 = or(_any_T_91, _any_T_29)
node _any_T_93 = or(_any_T_92, _any_T_30)
node _any_T_94 = or(_any_T_93, _any_T_31)
node _any_T_95 = or(_any_T_94, _any_T_32)
node _any_T_96 = or(_any_T_95, _any_T_33)
node _any_T_97 = or(_any_T_96, _any_T_34)
node _any_T_98 = or(_any_T_97, _any_T_35)
node _any_T_99 = or(_any_T_98, _any_T_36)
node _any_T_100 = or(_any_T_99, _any_T_37)
node _any_T_101 = or(_any_T_100, _any_T_38)
node _any_T_102 = or(_any_T_101, _any_T_39)
node _any_T_103 = or(_any_T_102, _any_T_40)
node _any_T_104 = or(_any_T_103, _any_T_41)
node _any_T_105 = or(_any_T_104, _any_T_42)
node _any_T_106 = or(_any_T_105, _any_T_43)
node _any_T_107 = or(_any_T_106, _any_T_44)
node _any_T_108 = or(_any_T_107, _any_T_45)
node _any_T_109 = or(_any_T_108, _any_T_46)
node _any_T_110 = or(_any_T_109, _any_T_47)
node _any_T_111 = or(_any_T_110, _any_T_48)
node _any_T_112 = or(_any_T_111, _any_T_49)
node _any_T_113 = or(_any_T_112, _any_T_50)
node _any_T_114 = or(_any_T_113, _any_T_51)
node _any_T_115 = or(_any_T_114, _any_T_52)
node _any_T_116 = or(_any_T_115, _any_T_53)
node _any_T_117 = or(_any_T_116, _any_T_54)
node _any_T_118 = or(_any_T_117, _any_T_55)
node _any_T_119 = or(_any_T_118, _any_T_56)
node _any_T_120 = or(_any_T_119, _any_T_57)
node _any_T_121 = or(_any_T_120, _any_T_58)
node _any_T_122 = or(_any_T_121, _any_T_59)
node _any_T_123 = or(_any_T_122, _any_T_60)
node _any_T_124 = or(_any_T_123, _any_T_61)
node anyInterrupt = or(_any_T_124, _any_T_62)
node _which_T = bits(d_interrupts, 14, 14)
node _which_T_1 = bits(d_interrupts, 13, 13)
node _which_T_2 = bits(d_interrupts, 12, 12)
node _which_T_3 = bits(d_interrupts, 11, 11)
node _which_T_4 = bits(d_interrupts, 3, 3)
node _which_T_5 = bits(d_interrupts, 7, 7)
node _which_T_6 = bits(d_interrupts, 9, 9)
node _which_T_7 = bits(d_interrupts, 1, 1)
node _which_T_8 = bits(d_interrupts, 5, 5)
node _which_T_9 = bits(d_interrupts, 10, 10)
node _which_T_10 = bits(d_interrupts, 2, 2)
node _which_T_11 = bits(d_interrupts, 6, 6)
node _which_T_12 = bits(d_interrupts, 8, 8)
node _which_T_13 = bits(d_interrupts, 0, 0)
node _which_T_14 = bits(d_interrupts, 4, 4)
node _which_T_15 = bits(m_interrupts, 15, 15)
node _which_T_16 = bits(m_interrupts, 14, 14)
node _which_T_17 = bits(m_interrupts, 13, 13)
node _which_T_18 = bits(m_interrupts, 12, 12)
node _which_T_19 = bits(m_interrupts, 11, 11)
node _which_T_20 = bits(m_interrupts, 3, 3)
node _which_T_21 = bits(m_interrupts, 7, 7)
node _which_T_22 = bits(m_interrupts, 9, 9)
node _which_T_23 = bits(m_interrupts, 1, 1)
node _which_T_24 = bits(m_interrupts, 5, 5)
node _which_T_25 = bits(m_interrupts, 10, 10)
node _which_T_26 = bits(m_interrupts, 2, 2)
node _which_T_27 = bits(m_interrupts, 6, 6)
node _which_T_28 = bits(m_interrupts, 8, 8)
node _which_T_29 = bits(m_interrupts, 0, 0)
node _which_T_30 = bits(m_interrupts, 4, 4)
node _which_T_31 = bits(s_interrupts, 15, 15)
node _which_T_32 = bits(s_interrupts, 14, 14)
node _which_T_33 = bits(s_interrupts, 13, 13)
node _which_T_34 = bits(s_interrupts, 12, 12)
node _which_T_35 = bits(s_interrupts, 11, 11)
node _which_T_36 = bits(s_interrupts, 3, 3)
node _which_T_37 = bits(s_interrupts, 7, 7)
node _which_T_38 = bits(s_interrupts, 9, 9)
node _which_T_39 = bits(s_interrupts, 1, 1)
node _which_T_40 = bits(s_interrupts, 5, 5)
node _which_T_41 = bits(s_interrupts, 10, 10)
node _which_T_42 = bits(s_interrupts, 2, 2)
node _which_T_43 = bits(s_interrupts, 6, 6)
node _which_T_44 = bits(s_interrupts, 8, 8)
node _which_T_45 = bits(s_interrupts, 0, 0)
node _which_T_46 = bits(s_interrupts, 4, 4)
node _which_T_47 = bits(vs_interrupts, 15, 15)
node _which_T_48 = bits(vs_interrupts, 14, 14)
node _which_T_49 = bits(vs_interrupts, 13, 13)
node _which_T_50 = bits(vs_interrupts, 12, 12)
node _which_T_51 = bits(vs_interrupts, 11, 11)
node _which_T_52 = bits(vs_interrupts, 3, 3)
node _which_T_53 = bits(vs_interrupts, 7, 7)
node _which_T_54 = bits(vs_interrupts, 9, 9)
node _which_T_55 = bits(vs_interrupts, 1, 1)
node _which_T_56 = bits(vs_interrupts, 5, 5)
node _which_T_57 = bits(vs_interrupts, 10, 10)
node _which_T_58 = bits(vs_interrupts, 2, 2)
node _which_T_59 = bits(vs_interrupts, 6, 6)
node _which_T_60 = bits(vs_interrupts, 8, 8)
node _which_T_61 = bits(vs_interrupts, 0, 0)
node _which_T_62 = bits(vs_interrupts, 4, 4)
node _which_T_63 = mux(_which_T_61, UInt<1>(0h0), UInt<3>(0h4))
node _which_T_64 = mux(_which_T_60, UInt<4>(0h8), _which_T_63)
node _which_T_65 = mux(_which_T_59, UInt<3>(0h6), _which_T_64)
node _which_T_66 = mux(_which_T_58, UInt<2>(0h2), _which_T_65)
node _which_T_67 = mux(_which_T_57, UInt<4>(0ha), _which_T_66)
node _which_T_68 = mux(_which_T_56, UInt<3>(0h5), _which_T_67)
node _which_T_69 = mux(_which_T_55, UInt<1>(0h1), _which_T_68)
node _which_T_70 = mux(_which_T_54, UInt<4>(0h9), _which_T_69)
node _which_T_71 = mux(_which_T_53, UInt<3>(0h7), _which_T_70)
node _which_T_72 = mux(_which_T_52, UInt<2>(0h3), _which_T_71)
node _which_T_73 = mux(_which_T_51, UInt<4>(0hb), _which_T_72)
node _which_T_74 = mux(_which_T_50, UInt<4>(0hc), _which_T_73)
node _which_T_75 = mux(_which_T_49, UInt<4>(0hd), _which_T_74)
node _which_T_76 = mux(_which_T_48, UInt<4>(0he), _which_T_75)
node _which_T_77 = mux(_which_T_47, UInt<4>(0hf), _which_T_76)
node _which_T_78 = mux(_which_T_46, UInt<3>(0h4), _which_T_77)
node _which_T_79 = mux(_which_T_45, UInt<1>(0h0), _which_T_78)
node _which_T_80 = mux(_which_T_44, UInt<4>(0h8), _which_T_79)
node _which_T_81 = mux(_which_T_43, UInt<3>(0h6), _which_T_80)
node _which_T_82 = mux(_which_T_42, UInt<2>(0h2), _which_T_81)
node _which_T_83 = mux(_which_T_41, UInt<4>(0ha), _which_T_82)
node _which_T_84 = mux(_which_T_40, UInt<3>(0h5), _which_T_83)
node _which_T_85 = mux(_which_T_39, UInt<1>(0h1), _which_T_84)
node _which_T_86 = mux(_which_T_38, UInt<4>(0h9), _which_T_85)
node _which_T_87 = mux(_which_T_37, UInt<3>(0h7), _which_T_86)
node _which_T_88 = mux(_which_T_36, UInt<2>(0h3), _which_T_87)
node _which_T_89 = mux(_which_T_35, UInt<4>(0hb), _which_T_88)
node _which_T_90 = mux(_which_T_34, UInt<4>(0hc), _which_T_89)
node _which_T_91 = mux(_which_T_33, UInt<4>(0hd), _which_T_90)
node _which_T_92 = mux(_which_T_32, UInt<4>(0he), _which_T_91)
node _which_T_93 = mux(_which_T_31, UInt<4>(0hf), _which_T_92)
node _which_T_94 = mux(_which_T_30, UInt<3>(0h4), _which_T_93)
node _which_T_95 = mux(_which_T_29, UInt<1>(0h0), _which_T_94)
node _which_T_96 = mux(_which_T_28, UInt<4>(0h8), _which_T_95)
node _which_T_97 = mux(_which_T_27, UInt<3>(0h6), _which_T_96)
node _which_T_98 = mux(_which_T_26, UInt<2>(0h2), _which_T_97)
node _which_T_99 = mux(_which_T_25, UInt<4>(0ha), _which_T_98)
node _which_T_100 = mux(_which_T_24, UInt<3>(0h5), _which_T_99)
node _which_T_101 = mux(_which_T_23, UInt<1>(0h1), _which_T_100)
node _which_T_102 = mux(_which_T_22, UInt<4>(0h9), _which_T_101)
node _which_T_103 = mux(_which_T_21, UInt<3>(0h7), _which_T_102)
node _which_T_104 = mux(_which_T_20, UInt<2>(0h3), _which_T_103)
node _which_T_105 = mux(_which_T_19, UInt<4>(0hb), _which_T_104)
node _which_T_106 = mux(_which_T_18, UInt<4>(0hc), _which_T_105)
node _which_T_107 = mux(_which_T_17, UInt<4>(0hd), _which_T_106)
node _which_T_108 = mux(_which_T_16, UInt<4>(0he), _which_T_107)
node _which_T_109 = mux(_which_T_15, UInt<4>(0hf), _which_T_108)
node _which_T_110 = mux(UInt<1>(0h0), UInt<1>(0h0), _which_T_109)
node _which_T_111 = mux(_which_T_14, UInt<3>(0h4), _which_T_110)
node _which_T_112 = mux(_which_T_13, UInt<1>(0h0), _which_T_111)
node _which_T_113 = mux(_which_T_12, UInt<4>(0h8), _which_T_112)
node _which_T_114 = mux(_which_T_11, UInt<3>(0h6), _which_T_113)
node _which_T_115 = mux(_which_T_10, UInt<2>(0h2), _which_T_114)
node _which_T_116 = mux(_which_T_9, UInt<4>(0ha), _which_T_115)
node _which_T_117 = mux(_which_T_8, UInt<3>(0h5), _which_T_116)
node _which_T_118 = mux(_which_T_7, UInt<1>(0h1), _which_T_117)
node _which_T_119 = mux(_which_T_6, UInt<4>(0h9), _which_T_118)
node _which_T_120 = mux(_which_T_5, UInt<3>(0h7), _which_T_119)
node _which_T_121 = mux(_which_T_4, UInt<2>(0h3), _which_T_120)
node _which_T_122 = mux(_which_T_3, UInt<4>(0hb), _which_T_121)
node _which_T_123 = mux(_which_T_2, UInt<4>(0hc), _which_T_122)
node _which_T_124 = mux(_which_T_1, UInt<4>(0hd), _which_T_123)
node whichInterrupt = mux(_which_T, UInt<4>(0he), _which_T_124)
node _interruptCause_T = shl(UInt<1>(0h0), 62)
node _interruptCause_T_1 = add(UInt<64>(0h8000000000000000), _interruptCause_T)
node _interruptCause_T_2 = tail(_interruptCause_T_1, 1)
node _interruptCause_T_3 = add(_interruptCause_T_2, whichInterrupt)
node interruptCause = tail(_interruptCause_T_3, 1)
node _io_interrupt_T = eq(io.singleStep, UInt<1>(0h0))
node _io_interrupt_T_1 = and(anyInterrupt, _io_interrupt_T)
node _io_interrupt_T_2 = or(_io_interrupt_T_1, reg_singleStepped)
node _io_interrupt_T_3 = or(reg_debug, io.status.cease)
node _io_interrupt_T_4 = eq(_io_interrupt_T_3, UInt<1>(0h0))
node _io_interrupt_T_5 = and(_io_interrupt_T_2, _io_interrupt_T_4)
connect io.interrupt, _io_interrupt_T_5
connect io.interrupt_cause, interruptCause
connect io.bp[0], reg_bp[0]
connect io.mcontext, UInt<1>(0h0)
connect io.scontext, UInt<1>(0h0)
node _io_fiom_T = lt(reg_mstatus.prv, UInt<2>(0h3))
node _io_fiom_T_1 = and(_io_fiom_T, reg_menvcfg.fiom)
node _io_fiom_T_2 = lt(reg_mstatus.prv, UInt<1>(0h1))
node _io_fiom_T_3 = and(_io_fiom_T_2, reg_senvcfg.fiom)
node _io_fiom_T_4 = or(_io_fiom_T_1, _io_fiom_T_3)
node _io_fiom_T_5 = and(reg_mstatus.v, reg_henvcfg.fiom)
node _io_fiom_T_6 = or(_io_fiom_T_4, _io_fiom_T_5)
connect io.fiom, _io_fiom_T_6
wire pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect pmp.cfg, reg_pmp[0].cfg
connect pmp.addr, reg_pmp[0].addr
node _pmp_mask_base_T = bits(pmp.cfg.a, 0, 0)
node _pmp_mask_base_T_1 = cat(pmp.addr, _pmp_mask_base_T)
node _pmp_mask_base_T_2 = shr(UInt<2>(0h3), 2)
node pmp_mask_base = or(_pmp_mask_base_T_1, _pmp_mask_base_T_2)
node _pmp_mask_T = add(pmp_mask_base, UInt<1>(0h1))
node _pmp_mask_T_1 = tail(_pmp_mask_T, 1)
node _pmp_mask_T_2 = not(_pmp_mask_T_1)
node _pmp_mask_T_3 = and(pmp_mask_base, _pmp_mask_T_2)
node _pmp_mask_T_4 = cat(_pmp_mask_T_3, UInt<2>(0h3))
connect pmp.mask, _pmp_mask_T_4
wire pmp_1 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect pmp_1.cfg, reg_pmp[1].cfg
connect pmp_1.addr, reg_pmp[1].addr
node _pmp_mask_base_T_3 = bits(pmp_1.cfg.a, 0, 0)
node _pmp_mask_base_T_4 = cat(pmp_1.addr, _pmp_mask_base_T_3)
node _pmp_mask_base_T_5 = shr(UInt<2>(0h3), 2)
node pmp_mask_base_1 = or(_pmp_mask_base_T_4, _pmp_mask_base_T_5)
node _pmp_mask_T_5 = add(pmp_mask_base_1, UInt<1>(0h1))
node _pmp_mask_T_6 = tail(_pmp_mask_T_5, 1)
node _pmp_mask_T_7 = not(_pmp_mask_T_6)
node _pmp_mask_T_8 = and(pmp_mask_base_1, _pmp_mask_T_7)
node _pmp_mask_T_9 = cat(_pmp_mask_T_8, UInt<2>(0h3))
connect pmp_1.mask, _pmp_mask_T_9
wire pmp_2 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect pmp_2.cfg, reg_pmp[2].cfg
connect pmp_2.addr, reg_pmp[2].addr
node _pmp_mask_base_T_6 = bits(pmp_2.cfg.a, 0, 0)
node _pmp_mask_base_T_7 = cat(pmp_2.addr, _pmp_mask_base_T_6)
node _pmp_mask_base_T_8 = shr(UInt<2>(0h3), 2)
node pmp_mask_base_2 = or(_pmp_mask_base_T_7, _pmp_mask_base_T_8)
node _pmp_mask_T_10 = add(pmp_mask_base_2, UInt<1>(0h1))
node _pmp_mask_T_11 = tail(_pmp_mask_T_10, 1)
node _pmp_mask_T_12 = not(_pmp_mask_T_11)
node _pmp_mask_T_13 = and(pmp_mask_base_2, _pmp_mask_T_12)
node _pmp_mask_T_14 = cat(_pmp_mask_T_13, UInt<2>(0h3))
connect pmp_2.mask, _pmp_mask_T_14
wire pmp_3 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect pmp_3.cfg, reg_pmp[3].cfg
connect pmp_3.addr, reg_pmp[3].addr
node _pmp_mask_base_T_9 = bits(pmp_3.cfg.a, 0, 0)
node _pmp_mask_base_T_10 = cat(pmp_3.addr, _pmp_mask_base_T_9)
node _pmp_mask_base_T_11 = shr(UInt<2>(0h3), 2)
node pmp_mask_base_3 = or(_pmp_mask_base_T_10, _pmp_mask_base_T_11)
node _pmp_mask_T_15 = add(pmp_mask_base_3, UInt<1>(0h1))
node _pmp_mask_T_16 = tail(_pmp_mask_T_15, 1)
node _pmp_mask_T_17 = not(_pmp_mask_T_16)
node _pmp_mask_T_18 = and(pmp_mask_base_3, _pmp_mask_T_17)
node _pmp_mask_T_19 = cat(_pmp_mask_T_18, UInt<2>(0h3))
connect pmp_3.mask, _pmp_mask_T_19
wire pmp_4 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect pmp_4.cfg, reg_pmp[4].cfg
connect pmp_4.addr, reg_pmp[4].addr
node _pmp_mask_base_T_12 = bits(pmp_4.cfg.a, 0, 0)
node _pmp_mask_base_T_13 = cat(pmp_4.addr, _pmp_mask_base_T_12)
node _pmp_mask_base_T_14 = shr(UInt<2>(0h3), 2)
node pmp_mask_base_4 = or(_pmp_mask_base_T_13, _pmp_mask_base_T_14)
node _pmp_mask_T_20 = add(pmp_mask_base_4, UInt<1>(0h1))
node _pmp_mask_T_21 = tail(_pmp_mask_T_20, 1)
node _pmp_mask_T_22 = not(_pmp_mask_T_21)
node _pmp_mask_T_23 = and(pmp_mask_base_4, _pmp_mask_T_22)
node _pmp_mask_T_24 = cat(_pmp_mask_T_23, UInt<2>(0h3))
connect pmp_4.mask, _pmp_mask_T_24
wire pmp_5 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect pmp_5.cfg, reg_pmp[5].cfg
connect pmp_5.addr, reg_pmp[5].addr
node _pmp_mask_base_T_15 = bits(pmp_5.cfg.a, 0, 0)
node _pmp_mask_base_T_16 = cat(pmp_5.addr, _pmp_mask_base_T_15)
node _pmp_mask_base_T_17 = shr(UInt<2>(0h3), 2)
node pmp_mask_base_5 = or(_pmp_mask_base_T_16, _pmp_mask_base_T_17)
node _pmp_mask_T_25 = add(pmp_mask_base_5, UInt<1>(0h1))
node _pmp_mask_T_26 = tail(_pmp_mask_T_25, 1)
node _pmp_mask_T_27 = not(_pmp_mask_T_26)
node _pmp_mask_T_28 = and(pmp_mask_base_5, _pmp_mask_T_27)
node _pmp_mask_T_29 = cat(_pmp_mask_T_28, UInt<2>(0h3))
connect pmp_5.mask, _pmp_mask_T_29
wire pmp_6 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect pmp_6.cfg, reg_pmp[6].cfg
connect pmp_6.addr, reg_pmp[6].addr
node _pmp_mask_base_T_18 = bits(pmp_6.cfg.a, 0, 0)
node _pmp_mask_base_T_19 = cat(pmp_6.addr, _pmp_mask_base_T_18)
node _pmp_mask_base_T_20 = shr(UInt<2>(0h3), 2)
node pmp_mask_base_6 = or(_pmp_mask_base_T_19, _pmp_mask_base_T_20)
node _pmp_mask_T_30 = add(pmp_mask_base_6, UInt<1>(0h1))
node _pmp_mask_T_31 = tail(_pmp_mask_T_30, 1)
node _pmp_mask_T_32 = not(_pmp_mask_T_31)
node _pmp_mask_T_33 = and(pmp_mask_base_6, _pmp_mask_T_32)
node _pmp_mask_T_34 = cat(_pmp_mask_T_33, UInt<2>(0h3))
connect pmp_6.mask, _pmp_mask_T_34
wire pmp_7 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect pmp_7.cfg, reg_pmp[7].cfg
connect pmp_7.addr, reg_pmp[7].addr
node _pmp_mask_base_T_21 = bits(pmp_7.cfg.a, 0, 0)
node _pmp_mask_base_T_22 = cat(pmp_7.addr, _pmp_mask_base_T_21)
node _pmp_mask_base_T_23 = shr(UInt<2>(0h3), 2)
node pmp_mask_base_7 = or(_pmp_mask_base_T_22, _pmp_mask_base_T_23)
node _pmp_mask_T_35 = add(pmp_mask_base_7, UInt<1>(0h1))
node _pmp_mask_T_36 = tail(_pmp_mask_T_35, 1)
node _pmp_mask_T_37 = not(_pmp_mask_T_36)
node _pmp_mask_T_38 = and(pmp_mask_base_7, _pmp_mask_T_37)
node _pmp_mask_T_39 = cat(_pmp_mask_T_38, UInt<2>(0h3))
connect pmp_7.mask, _pmp_mask_T_39
connect io.pmp[0], pmp
connect io.pmp[1], pmp_1
connect io.pmp[2], pmp_2
connect io.pmp[3], pmp_3
connect io.pmp[4], pmp_4
connect io.pmp[5], pmp_5
connect io.pmp[6], pmp_6
connect io.pmp[7], pmp_7
regreset reg_misa : UInt, clock, reset, UInt<64>(0h800000000094112d)
node read_mstatus_lo_lo_lo_lo = cat(io.status.sie, io.status.uie)
node read_mstatus_lo_lo_lo_hi = cat(io.status.mie, io.status.hie)
node read_mstatus_lo_lo_lo = cat(read_mstatus_lo_lo_lo_hi, read_mstatus_lo_lo_lo_lo)
node read_mstatus_lo_lo_hi_lo = cat(io.status.spie, io.status.upie)
node read_mstatus_lo_lo_hi_hi_hi = cat(io.status.spp, io.status.mpie)
node read_mstatus_lo_lo_hi_hi = cat(read_mstatus_lo_lo_hi_hi_hi, io.status.ube)
node read_mstatus_lo_lo_hi = cat(read_mstatus_lo_lo_hi_hi, read_mstatus_lo_lo_hi_lo)
node read_mstatus_lo_lo = cat(read_mstatus_lo_lo_hi, read_mstatus_lo_lo_lo)
node read_mstatus_lo_hi_lo_lo = cat(io.status.mpp, io.status.vs)
node read_mstatus_lo_hi_lo_hi = cat(io.status.xs, io.status.fs)
node read_mstatus_lo_hi_lo = cat(read_mstatus_lo_hi_lo_hi, read_mstatus_lo_hi_lo_lo)
node read_mstatus_lo_hi_hi_lo = cat(io.status.sum, io.status.mprv)
node read_mstatus_lo_hi_hi_hi_hi = cat(io.status.tw, io.status.tvm)
node read_mstatus_lo_hi_hi_hi = cat(read_mstatus_lo_hi_hi_hi_hi, io.status.mxr)
node read_mstatus_lo_hi_hi = cat(read_mstatus_lo_hi_hi_hi, read_mstatus_lo_hi_hi_lo)
node read_mstatus_lo_hi = cat(read_mstatus_lo_hi_hi, read_mstatus_lo_hi_lo)
node read_mstatus_lo = cat(read_mstatus_lo_hi, read_mstatus_lo_lo)
node read_mstatus_hi_lo_lo_lo = cat(io.status.zero1, io.status.tsr)
node read_mstatus_hi_lo_lo_hi = cat(io.status.uxl, io.status.sd_rv32)
node read_mstatus_hi_lo_lo = cat(read_mstatus_hi_lo_lo_hi, read_mstatus_hi_lo_lo_lo)
node read_mstatus_hi_lo_hi_lo = cat(io.status.sbe, io.status.sxl)
node read_mstatus_hi_lo_hi_hi_hi = cat(io.status.mpv, io.status.gva)
node read_mstatus_hi_lo_hi_hi = cat(read_mstatus_hi_lo_hi_hi_hi, io.status.mbe)
node read_mstatus_hi_lo_hi = cat(read_mstatus_hi_lo_hi_hi, read_mstatus_hi_lo_hi_lo)
node read_mstatus_hi_lo = cat(read_mstatus_hi_lo_hi, read_mstatus_hi_lo_lo)
node read_mstatus_hi_hi_lo_lo = cat(io.status.sd, io.status.zero2)
node read_mstatus_hi_hi_lo_hi_hi = cat(io.status.dv, io.status.prv)
node read_mstatus_hi_hi_lo_hi = cat(read_mstatus_hi_hi_lo_hi_hi, io.status.v)
node read_mstatus_hi_hi_lo = cat(read_mstatus_hi_hi_lo_hi, read_mstatus_hi_hi_lo_lo)
node read_mstatus_hi_hi_hi_lo = cat(io.status.isa, io.status.dprv)
node read_mstatus_hi_hi_hi_hi_hi = cat(io.status.debug, io.status.cease)
node read_mstatus_hi_hi_hi_hi = cat(read_mstatus_hi_hi_hi_hi_hi, io.status.wfi)
node read_mstatus_hi_hi_hi = cat(read_mstatus_hi_hi_hi_hi, read_mstatus_hi_hi_hi_lo)
node read_mstatus_hi_hi = cat(read_mstatus_hi_hi_hi, read_mstatus_hi_hi_lo)
node read_mstatus_hi = cat(read_mstatus_hi_hi, read_mstatus_hi_lo)
node _read_mstatus_T = cat(read_mstatus_hi, read_mstatus_lo)
node read_mstatus = bits(_read_mstatus_T, 63, 0)
node _read_mtvec_T = bits(reg_mtvec, 0, 0)
node _read_mtvec_T_1 = mux(_read_mtvec_T, UInt<8>(0hfe), UInt<2>(0h2))
node _read_mtvec_T_2 = and(reg_mtvec, UInt<1>(0h0))
node _read_mtvec_T_3 = or(_read_mtvec_T_1, _read_mtvec_T_2)
node _read_mtvec_T_4 = not(_read_mtvec_T_3)
node _read_mtvec_T_5 = and(reg_mtvec, _read_mtvec_T_4)
node read_mtvec = cat(UInt<32>(0h0), _read_mtvec_T_5)
node _read_stvec_T = bits(reg_stvec, 0, 0)
node _read_stvec_T_1 = mux(_read_stvec_T, UInt<8>(0hfe), UInt<2>(0h2))
node _read_stvec_T_2 = and(reg_stvec, UInt<1>(0h0))
node _read_stvec_T_3 = or(_read_stvec_T_1, _read_stvec_T_2)
node _read_stvec_T_4 = not(_read_stvec_T_3)
node _read_stvec_T_5 = and(reg_stvec, _read_stvec_T_4)
node _read_stvec_T_6 = bits(_read_stvec_T_5, 38, 38)
node _read_stvec_T_7 = mux(_read_stvec_T_6, UInt<25>(0h1ffffff), UInt<25>(0h0))
node read_stvec = cat(_read_stvec_T_7, _read_stvec_T_5)
node read_mapping_lo_lo_hi = cat(reg_bp[reg_tselect].control.x, reg_bp[reg_tselect].control.w)
node read_mapping_lo_lo = cat(read_mapping_lo_lo_hi, reg_bp[reg_tselect].control.r)
node read_mapping_lo_hi_lo = cat(reg_bp[reg_tselect].control.s, reg_bp[reg_tselect].control.u)
node read_mapping_lo_hi_hi = cat(reg_bp[reg_tselect].control.m, reg_bp[reg_tselect].control.h)
node read_mapping_lo_hi = cat(read_mapping_lo_hi_hi, read_mapping_lo_hi_lo)
node read_mapping_lo = cat(read_mapping_lo_hi, read_mapping_lo_lo)
node read_mapping_hi_lo_lo = cat(reg_bp[reg_tselect].control.zero, reg_bp[reg_tselect].control.tmatch)
node read_mapping_hi_lo_hi = cat(reg_bp[reg_tselect].control.action, reg_bp[reg_tselect].control.chain)
node read_mapping_hi_lo = cat(read_mapping_hi_lo_hi, read_mapping_hi_lo_lo)
node read_mapping_hi_hi_lo = cat(reg_bp[reg_tselect].control.maskmax, reg_bp[reg_tselect].control.reserved)
node read_mapping_hi_hi_hi = cat(reg_bp[reg_tselect].control.ttype, reg_bp[reg_tselect].control.dmode)
node read_mapping_hi_hi = cat(read_mapping_hi_hi_hi, read_mapping_hi_hi_lo)
node read_mapping_hi = cat(read_mapping_hi_hi, read_mapping_hi_lo)
node read_mapping_1_2 = cat(read_mapping_hi, read_mapping_lo)
node _read_mapping_T = bits(reg_bp[reg_tselect].address, 38, 38)
node _read_mapping_T_1 = mux(_read_mapping_T, UInt<25>(0h1ffffff), UInt<25>(0h0))
node read_mapping_2_2 = cat(_read_mapping_T_1, reg_bp[reg_tselect].address)
node read_mapping_lo_hi_1 = cat(reg_bp[reg_tselect].textra.svalue, reg_bp[reg_tselect].textra.pad1)
node read_mapping_lo_1 = cat(read_mapping_lo_hi_1, reg_bp[reg_tselect].textra.sselect)
node read_mapping_hi_hi_1 = cat(reg_bp[reg_tselect].textra.mvalue, reg_bp[reg_tselect].textra.mselect)
node read_mapping_hi_1 = cat(read_mapping_hi_hi_1, reg_bp[reg_tselect].textra.pad2)
node read_mapping_3_2 = cat(read_mapping_hi_1, read_mapping_lo_1)
node _read_mapping_T_2 = not(reg_mepc)
node _read_mapping_T_3 = bits(reg_misa, 2, 2)
node _read_mapping_T_4 = mux(_read_mapping_T_3, UInt<1>(0h1), UInt<2>(0h3))
node _read_mapping_T_5 = or(_read_mapping_T_2, _read_mapping_T_4)
node _read_mapping_T_6 = not(_read_mapping_T_5)
node _read_mapping_T_7 = bits(_read_mapping_T_6, 39, 39)
node _read_mapping_T_8 = mux(_read_mapping_T_7, UInt<24>(0hffffff), UInt<24>(0h0))
node read_mapping_10_2 = cat(_read_mapping_T_8, _read_mapping_T_6)
node _read_mapping_T_9 = bits(reg_mtval, 39, 39)
node _read_mapping_T_10 = mux(_read_mapping_T_9, UInt<24>(0hffffff), UInt<24>(0h0))
node read_mapping_11_2 = cat(_read_mapping_T_10, reg_mtval)
node debug_csrs_lo_lo_hi = cat(reg_dcsr.zero1, reg_dcsr.step)
node debug_csrs_lo_lo = cat(debug_csrs_lo_lo_hi, reg_dcsr.prv)
node debug_csrs_lo_hi_lo = cat(reg_dcsr.cause, reg_dcsr.v)
node debug_csrs_lo_hi_hi = cat(reg_dcsr.stopcycle, reg_dcsr.stoptime)
node debug_csrs_lo_hi = cat(debug_csrs_lo_hi_hi, debug_csrs_lo_hi_lo)
node debug_csrs_lo = cat(debug_csrs_lo_hi, debug_csrs_lo_lo)
node debug_csrs_hi_lo_lo = cat(reg_dcsr.ebreaku, reg_dcsr.zero2)
node debug_csrs_hi_lo_hi = cat(reg_dcsr.ebreakh, reg_dcsr.ebreaks)
node debug_csrs_hi_lo = cat(debug_csrs_hi_lo_hi, debug_csrs_hi_lo_lo)
node debug_csrs_hi_hi_lo = cat(reg_dcsr.zero3, reg_dcsr.ebreakm)
node debug_csrs_hi_hi_hi = cat(reg_dcsr.xdebugver, reg_dcsr.zero4)
node debug_csrs_hi_hi = cat(debug_csrs_hi_hi_hi, debug_csrs_hi_hi_lo)
node debug_csrs_hi = cat(debug_csrs_hi_hi, debug_csrs_hi_lo)
node debug_csrs_0_2 = cat(debug_csrs_hi, debug_csrs_lo)
node _debug_csrs_T = not(reg_dpc)
node _debug_csrs_T_1 = bits(reg_misa, 2, 2)
node _debug_csrs_T_2 = mux(_debug_csrs_T_1, UInt<1>(0h1), UInt<2>(0h3))
node _debug_csrs_T_3 = or(_debug_csrs_T, _debug_csrs_T_2)
node _debug_csrs_T_4 = not(_debug_csrs_T_3)
node _debug_csrs_T_5 = bits(_debug_csrs_T_4, 39, 39)
node _debug_csrs_T_6 = mux(_debug_csrs_T_5, UInt<24>(0hffffff), UInt<24>(0h0))
node debug_csrs_1_2 = cat(_debug_csrs_T_6, _debug_csrs_T_4)
wire _read_mnstatus_WIRE : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>}
connect _read_mnstatus_WIRE.zero1, UInt<3>(0h0)
connect _read_mnstatus_WIRE.mie, UInt<1>(0h0)
connect _read_mnstatus_WIRE.zero2, UInt<3>(0h0)
connect _read_mnstatus_WIRE.mpv, UInt<1>(0h0)
connect _read_mnstatus_WIRE.zero3, UInt<3>(0h0)
connect _read_mnstatus_WIRE.mpp, UInt<2>(0h0)
wire read_mnstatus : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>}
connect read_mnstatus, _read_mnstatus_WIRE
connect read_mnstatus.mpp, reg_mnstatus.mpp
connect read_mnstatus.mpv, reg_mnstatus.mpv
connect read_mnstatus.mie, reg_rnmie
node read_fcsr = cat(reg_frm, reg_fflags)
node read_vcsr = cat(UInt<1>(0h0), UInt<1>(0h0))
node lo_lo_4 = cat(reg_menvcfg.zero3, reg_menvcfg.fiom)
node lo_hi_4 = cat(reg_menvcfg.cbcfe, reg_menvcfg.cbie)
node lo_4 = cat(lo_hi_4, lo_lo_4)
node hi_lo_4 = cat(reg_menvcfg.zero54, reg_menvcfg.cbze)
node hi_hi_4 = cat(reg_menvcfg.stce, reg_menvcfg.pbmte)
node hi_6 = cat(hi_hi_4, hi_lo_4)
node _T_19 = cat(hi_6, lo_4)
wire _sie_mask_sgeip_mask_WIRE : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
connect _sie_mask_sgeip_mask_WIRE.usip, UInt<1>(0h0)
connect _sie_mask_sgeip_mask_WIRE.ssip, UInt<1>(0h0)
connect _sie_mask_sgeip_mask_WIRE.vssip, UInt<1>(0h0)
connect _sie_mask_sgeip_mask_WIRE.msip, UInt<1>(0h0)
connect _sie_mask_sgeip_mask_WIRE.utip, UInt<1>(0h0)
connect _sie_mask_sgeip_mask_WIRE.stip, UInt<1>(0h0)
connect _sie_mask_sgeip_mask_WIRE.vstip, UInt<1>(0h0)
connect _sie_mask_sgeip_mask_WIRE.mtip, UInt<1>(0h0)
connect _sie_mask_sgeip_mask_WIRE.ueip, UInt<1>(0h0)
connect _sie_mask_sgeip_mask_WIRE.seip, UInt<1>(0h0)
connect _sie_mask_sgeip_mask_WIRE.vseip, UInt<1>(0h0)
connect _sie_mask_sgeip_mask_WIRE.meip, UInt<1>(0h0)
connect _sie_mask_sgeip_mask_WIRE.sgeip, UInt<1>(0h0)
connect _sie_mask_sgeip_mask_WIRE.rocc, UInt<1>(0h0)
connect _sie_mask_sgeip_mask_WIRE.debug, UInt<1>(0h0)
connect _sie_mask_sgeip_mask_WIRE.zero1, UInt<1>(0h0)
wire sie_mask_sgeip_mask : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
connect sie_mask_sgeip_mask, _sie_mask_sgeip_mask_WIRE
connect sie_mask_sgeip_mask.sgeip, UInt<1>(0h1)
node sie_mask_lo_lo_lo = cat(sie_mask_sgeip_mask.ssip, sie_mask_sgeip_mask.usip)
node sie_mask_lo_lo_hi = cat(sie_mask_sgeip_mask.msip, sie_mask_sgeip_mask.vssip)
node sie_mask_lo_lo = cat(sie_mask_lo_lo_hi, sie_mask_lo_lo_lo)
node sie_mask_lo_hi_lo = cat(sie_mask_sgeip_mask.stip, sie_mask_sgeip_mask.utip)
node sie_mask_lo_hi_hi = cat(sie_mask_sgeip_mask.mtip, sie_mask_sgeip_mask.vstip)
node sie_mask_lo_hi = cat(sie_mask_lo_hi_hi, sie_mask_lo_hi_lo)
node sie_mask_lo = cat(sie_mask_lo_hi, sie_mask_lo_lo)
node sie_mask_hi_lo_lo = cat(sie_mask_sgeip_mask.seip, sie_mask_sgeip_mask.ueip)
node sie_mask_hi_lo_hi = cat(sie_mask_sgeip_mask.meip, sie_mask_sgeip_mask.vseip)
node sie_mask_hi_lo = cat(sie_mask_hi_lo_hi, sie_mask_hi_lo_lo)
node sie_mask_hi_hi_lo = cat(sie_mask_sgeip_mask.rocc, sie_mask_sgeip_mask.sgeip)
node sie_mask_hi_hi_hi_hi = cat(UInt<0>(0h0), sie_mask_sgeip_mask.zero1)
node sie_mask_hi_hi_hi = cat(sie_mask_hi_hi_hi_hi, sie_mask_sgeip_mask.debug)
node sie_mask_hi_hi = cat(sie_mask_hi_hi_hi, sie_mask_hi_hi_lo)
node sie_mask_hi = cat(sie_mask_hi_hi, sie_mask_hi_lo)
node _sie_mask_T = cat(sie_mask_hi, sie_mask_lo)
node _sie_mask_T_1 = or(hs_delegable_interrupts, _sie_mask_T)
node _sie_mask_T_2 = not(_sie_mask_T_1)
node sie_mask = and(read_mideleg, _sie_mask_T_2)
node read_sie = and(reg_mie, sie_mask)
node read_sip = and(read_mip, sie_mask)
wire _read_sstatus_WIRE : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}
connect _read_sstatus_WIRE.uie, UInt<1>(0h0)
connect _read_sstatus_WIRE.sie, UInt<1>(0h0)
connect _read_sstatus_WIRE.hie, UInt<1>(0h0)
connect _read_sstatus_WIRE.mie, UInt<1>(0h0)
connect _read_sstatus_WIRE.upie, UInt<1>(0h0)
connect _read_sstatus_WIRE.spie, UInt<1>(0h0)
connect _read_sstatus_WIRE.ube, UInt<1>(0h0)
connect _read_sstatus_WIRE.mpie, UInt<1>(0h0)
connect _read_sstatus_WIRE.spp, UInt<1>(0h0)
connect _read_sstatus_WIRE.vs, UInt<2>(0h0)
connect _read_sstatus_WIRE.mpp, UInt<2>(0h0)
connect _read_sstatus_WIRE.fs, UInt<2>(0h0)
connect _read_sstatus_WIRE.xs, UInt<2>(0h0)
connect _read_sstatus_WIRE.mprv, UInt<1>(0h0)
connect _read_sstatus_WIRE.sum, UInt<1>(0h0)
connect _read_sstatus_WIRE.mxr, UInt<1>(0h0)
connect _read_sstatus_WIRE.tvm, UInt<1>(0h0)
connect _read_sstatus_WIRE.tw, UInt<1>(0h0)
connect _read_sstatus_WIRE.tsr, UInt<1>(0h0)
connect _read_sstatus_WIRE.zero1, UInt<8>(0h0)
connect _read_sstatus_WIRE.sd_rv32, UInt<1>(0h0)
connect _read_sstatus_WIRE.uxl, UInt<2>(0h0)
connect _read_sstatus_WIRE.sxl, UInt<2>(0h0)
connect _read_sstatus_WIRE.sbe, UInt<1>(0h0)
connect _read_sstatus_WIRE.mbe, UInt<1>(0h0)
connect _read_sstatus_WIRE.gva, UInt<1>(0h0)
connect _read_sstatus_WIRE.mpv, UInt<1>(0h0)
connect _read_sstatus_WIRE.zero2, UInt<23>(0h0)
connect _read_sstatus_WIRE.sd, UInt<1>(0h0)
connect _read_sstatus_WIRE.v, UInt<1>(0h0)
connect _read_sstatus_WIRE.prv, UInt<2>(0h0)
connect _read_sstatus_WIRE.dv, UInt<1>(0h0)
connect _read_sstatus_WIRE.dprv, UInt<2>(0h0)
connect _read_sstatus_WIRE.isa, UInt<32>(0h0)
connect _read_sstatus_WIRE.wfi, UInt<1>(0h0)
connect _read_sstatus_WIRE.cease, UInt<1>(0h0)
connect _read_sstatus_WIRE.debug, UInt<1>(0h0)
wire read_sstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}
connect read_sstatus, _read_sstatus_WIRE
connect read_sstatus.sd, io.status.sd
connect read_sstatus.uxl, io.status.uxl
connect read_sstatus.sd_rv32, io.status.sd_rv32
connect read_sstatus.mxr, io.status.mxr
connect read_sstatus.sum, io.status.sum
connect read_sstatus.xs, io.status.xs
connect read_sstatus.fs, io.status.fs
connect read_sstatus.vs, io.status.vs
connect read_sstatus.spp, io.status.spp
connect read_sstatus.spie, io.status.spie
connect read_sstatus.sie, io.status.sie
node lo_lo_lo_lo = cat(read_sstatus.sie, read_sstatus.uie)
node lo_lo_lo_hi = cat(read_sstatus.mie, read_sstatus.hie)
node lo_lo_lo_4 = cat(lo_lo_lo_hi, lo_lo_lo_lo)
node lo_lo_hi_lo = cat(read_sstatus.spie, read_sstatus.upie)
node lo_lo_hi_hi_hi = cat(read_sstatus.spp, read_sstatus.mpie)
node lo_lo_hi_hi = cat(lo_lo_hi_hi_hi, read_sstatus.ube)
node lo_lo_hi_4 = cat(lo_lo_hi_hi, lo_lo_hi_lo)
node lo_lo_5 = cat(lo_lo_hi_4, lo_lo_lo_4)
node lo_hi_lo_lo = cat(read_sstatus.mpp, read_sstatus.vs)
node lo_hi_lo_hi = cat(read_sstatus.xs, read_sstatus.fs)
node lo_hi_lo_4 = cat(lo_hi_lo_hi, lo_hi_lo_lo)
node lo_hi_hi_lo = cat(read_sstatus.sum, read_sstatus.mprv)
node lo_hi_hi_hi_hi = cat(read_sstatus.tw, read_sstatus.tvm)
node lo_hi_hi_hi = cat(lo_hi_hi_hi_hi, read_sstatus.mxr)
node lo_hi_hi_4 = cat(lo_hi_hi_hi, lo_hi_hi_lo)
node lo_hi_5 = cat(lo_hi_hi_4, lo_hi_lo_4)
node lo_5 = cat(lo_hi_5, lo_lo_5)
node hi_lo_lo_lo = cat(read_sstatus.zero1, read_sstatus.tsr)
node hi_lo_lo_hi = cat(read_sstatus.uxl, read_sstatus.sd_rv32)
node hi_lo_lo_4 = cat(hi_lo_lo_hi, hi_lo_lo_lo)
node hi_lo_hi_lo = cat(read_sstatus.sbe, read_sstatus.sxl)
node hi_lo_hi_hi_hi = cat(read_sstatus.mpv, read_sstatus.gva)
node hi_lo_hi_hi = cat(hi_lo_hi_hi_hi, read_sstatus.mbe)
node hi_lo_hi_4 = cat(hi_lo_hi_hi, hi_lo_hi_lo)
node hi_lo_5 = cat(hi_lo_hi_4, hi_lo_lo_4)
node hi_hi_lo_lo = cat(read_sstatus.sd, read_sstatus.zero2)
node hi_hi_lo_hi_hi = cat(read_sstatus.dv, read_sstatus.prv)
node hi_hi_lo_hi = cat(hi_hi_lo_hi_hi, read_sstatus.v)
node hi_hi_lo_4 = cat(hi_hi_lo_hi, hi_hi_lo_lo)
node hi_hi_hi_lo = cat(read_sstatus.isa, read_sstatus.dprv)
node hi_hi_hi_hi_hi = cat(read_sstatus.debug, read_sstatus.cease)
node hi_hi_hi_hi_4 = cat(hi_hi_hi_hi_hi, read_sstatus.wfi)
node hi_hi_hi_4 = cat(hi_hi_hi_hi_4, hi_hi_hi_lo)
node hi_hi_5 = cat(hi_hi_hi_4, hi_hi_lo_4)
node hi_7 = cat(hi_hi_5, hi_lo_5)
node _T_20 = cat(hi_7, lo_5)
node _T_21 = bits(_T_20, 63, 0)
node _T_22 = bits(reg_stval, 39, 39)
node _T_23 = mux(_T_22, UInt<24>(0hffffff), UInt<24>(0h0))
node _T_24 = cat(_T_23, reg_stval)
node hi_8 = cat(reg_satp.mode, reg_satp.asid)
node _T_25 = cat(hi_8, reg_satp.ppn)
node _T_26 = not(reg_sepc)
node _T_27 = bits(reg_misa, 2, 2)
node _T_28 = mux(_T_27, UInt<1>(0h1), UInt<2>(0h3))
node _T_29 = or(_T_26, _T_28)
node _T_30 = not(_T_29)
node _T_31 = bits(_T_30, 39, 39)
node _T_32 = mux(_T_31, UInt<24>(0hffffff), UInt<24>(0h0))
node _T_33 = cat(_T_32, _T_30)
node lo_lo_6 = cat(reg_senvcfg.zero3, reg_senvcfg.fiom)
node lo_hi_6 = cat(reg_senvcfg.cbcfe, reg_senvcfg.cbie)
node lo_6 = cat(lo_hi_6, lo_lo_6)
node hi_lo_6 = cat(reg_senvcfg.zero54, reg_senvcfg.cbze)
node hi_hi_6 = cat(reg_senvcfg.stce, reg_senvcfg.pbmte)
node hi_9 = cat(hi_hi_6, hi_lo_6)
node _T_34 = cat(hi_9, lo_6)
wire read_pmp_15 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}
connect read_pmp_15.mask, UInt<32>(0h0)
connect read_pmp_15.addr, UInt<30>(0h0)
connect read_pmp_15.cfg.r, UInt<1>(0h0)
connect read_pmp_15.cfg.w, UInt<1>(0h0)
connect read_pmp_15.cfg.x, UInt<1>(0h0)
connect read_pmp_15.cfg.a, UInt<2>(0h0)
connect read_pmp_15.cfg.res, UInt<2>(0h0)
connect read_pmp_15.cfg.l, UInt<1>(0h0)
node lo_hi_7 = cat(reg_pmp[0].cfg.x, reg_pmp[0].cfg.w)
node lo_7 = cat(lo_hi_7, reg_pmp[0].cfg.r)
node hi_hi_7 = cat(reg_pmp[0].cfg.l, reg_pmp[0].cfg.res)
node hi_10 = cat(hi_hi_7, reg_pmp[0].cfg.a)
node _T_35 = cat(hi_10, lo_7)
node lo_hi_8 = cat(reg_pmp[1].cfg.x, reg_pmp[1].cfg.w)
node lo_8 = cat(lo_hi_8, reg_pmp[1].cfg.r)
node hi_hi_8 = cat(reg_pmp[1].cfg.l, reg_pmp[1].cfg.res)
node hi_11 = cat(hi_hi_8, reg_pmp[1].cfg.a)
node _T_36 = cat(hi_11, lo_8)
node lo_hi_9 = cat(reg_pmp[2].cfg.x, reg_pmp[2].cfg.w)
node lo_9 = cat(lo_hi_9, reg_pmp[2].cfg.r)
node hi_hi_9 = cat(reg_pmp[2].cfg.l, reg_pmp[2].cfg.res)
node hi_12 = cat(hi_hi_9, reg_pmp[2].cfg.a)
node _T_37 = cat(hi_12, lo_9)
node lo_hi_10 = cat(reg_pmp[3].cfg.x, reg_pmp[3].cfg.w)
node lo_10 = cat(lo_hi_10, reg_pmp[3].cfg.r)
node hi_hi_10 = cat(reg_pmp[3].cfg.l, reg_pmp[3].cfg.res)
node hi_13 = cat(hi_hi_10, reg_pmp[3].cfg.a)
node _T_38 = cat(hi_13, lo_10)
node lo_hi_11 = cat(reg_pmp[4].cfg.x, reg_pmp[4].cfg.w)
node lo_11 = cat(lo_hi_11, reg_pmp[4].cfg.r)
node hi_hi_11 = cat(reg_pmp[4].cfg.l, reg_pmp[4].cfg.res)
node hi_14 = cat(hi_hi_11, reg_pmp[4].cfg.a)
node _T_39 = cat(hi_14, lo_11)
node lo_hi_12 = cat(reg_pmp[5].cfg.x, reg_pmp[5].cfg.w)
node lo_12 = cat(lo_hi_12, reg_pmp[5].cfg.r)
node hi_hi_12 = cat(reg_pmp[5].cfg.l, reg_pmp[5].cfg.res)
node hi_15 = cat(hi_hi_12, reg_pmp[5].cfg.a)
node _T_40 = cat(hi_15, lo_12)
node lo_hi_13 = cat(reg_pmp[6].cfg.x, reg_pmp[6].cfg.w)
node lo_13 = cat(lo_hi_13, reg_pmp[6].cfg.r)
node hi_hi_13 = cat(reg_pmp[6].cfg.l, reg_pmp[6].cfg.res)
node hi_16 = cat(hi_hi_13, reg_pmp[6].cfg.a)
node _T_41 = cat(hi_16, lo_13)
node lo_hi_14 = cat(reg_pmp[7].cfg.x, reg_pmp[7].cfg.w)
node lo_14 = cat(lo_hi_14, reg_pmp[7].cfg.r)
node hi_hi_14 = cat(reg_pmp[7].cfg.l, reg_pmp[7].cfg.res)
node hi_17 = cat(hi_hi_14, reg_pmp[7].cfg.a)
node _T_42 = cat(hi_17, lo_14)
node lo_lo_7 = cat(_T_36, _T_35)
node lo_hi_15 = cat(_T_38, _T_37)
node lo_15 = cat(lo_hi_15, lo_lo_7)
node hi_lo_7 = cat(_T_40, _T_39)
node hi_hi_15 = cat(_T_42, _T_41)
node hi_18 = cat(hi_hi_15, hi_lo_7)
node _T_43 = cat(hi_18, lo_15)
node lo_hi_16 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w)
node lo_16 = cat(lo_hi_16, read_pmp_15.cfg.r)
node hi_hi_16 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res)
node hi_19 = cat(hi_hi_16, read_pmp_15.cfg.a)
node _T_44 = cat(hi_19, lo_16)
node lo_hi_17 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w)
node lo_17 = cat(lo_hi_17, read_pmp_15.cfg.r)
node hi_hi_17 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res)
node hi_20 = cat(hi_hi_17, read_pmp_15.cfg.a)
node _T_45 = cat(hi_20, lo_17)
node lo_hi_18 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w)
node lo_18 = cat(lo_hi_18, read_pmp_15.cfg.r)
node hi_hi_18 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res)
node hi_21 = cat(hi_hi_18, read_pmp_15.cfg.a)
node _T_46 = cat(hi_21, lo_18)
node lo_hi_19 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w)
node lo_19 = cat(lo_hi_19, read_pmp_15.cfg.r)
node hi_hi_19 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res)
node hi_22 = cat(hi_hi_19, read_pmp_15.cfg.a)
node _T_47 = cat(hi_22, lo_19)
node lo_hi_20 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w)
node lo_20 = cat(lo_hi_20, read_pmp_15.cfg.r)
node hi_hi_20 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res)
node hi_23 = cat(hi_hi_20, read_pmp_15.cfg.a)
node _T_48 = cat(hi_23, lo_20)
node lo_hi_21 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w)
node lo_21 = cat(lo_hi_21, read_pmp_15.cfg.r)
node hi_hi_21 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res)
node hi_24 = cat(hi_hi_21, read_pmp_15.cfg.a)
node _T_49 = cat(hi_24, lo_21)
node lo_hi_22 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w)
node lo_22 = cat(lo_hi_22, read_pmp_15.cfg.r)
node hi_hi_22 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res)
node hi_25 = cat(hi_hi_22, read_pmp_15.cfg.a)
node _T_50 = cat(hi_25, lo_22)
node lo_hi_23 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w)
node lo_23 = cat(lo_hi_23, read_pmp_15.cfg.r)
node hi_hi_23 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res)
node hi_26 = cat(hi_hi_23, read_pmp_15.cfg.a)
node _T_51 = cat(hi_26, lo_23)
node lo_lo_8 = cat(_T_45, _T_44)
node lo_hi_24 = cat(_T_47, _T_46)
node lo_24 = cat(lo_hi_24, lo_lo_8)
node hi_lo_8 = cat(_T_49, _T_48)
node hi_hi_24 = cat(_T_51, _T_50)
node hi_27 = cat(hi_hi_24, hi_lo_8)
node _T_52 = cat(hi_27, lo_24)
regreset reg_custom_0 : UInt<64>, clock, reset, UInt<64>(0h208)
node _reg_custom_read_T = neq(io.rw.cmd, UInt<3>(0h0))
node _reg_custom_read_T_1 = eq(io.rw.addr, UInt<11>(0h7c1))
node reg_custom_read = and(_reg_custom_read_T, _reg_custom_read_T_1)
connect io.customCSRs[0].ren, reg_custom_read
node _reg_custom_T = and(reg_custom_read, io.customCSRs[0].stall)
when _reg_custom_T :
connect io.rw_stall, UInt<1>(0h1)
regreset reg_custom_1 : UInt<64>, clock, reset, UInt<64>(0h1)
node _reg_custom_read_T_2 = neq(io.rw.cmd, UInt<3>(0h0))
node _reg_custom_read_T_3 = eq(io.rw.addr, UInt<12>(0hf12))
node reg_custom_read_1 = and(_reg_custom_read_T_2, _reg_custom_read_T_3)
connect io.customCSRs[1].ren, reg_custom_read_1
node _reg_custom_T_1 = and(reg_custom_read_1, io.customCSRs[1].stall)
when _reg_custom_T_1 :
connect io.rw_stall, UInt<1>(0h1)
regreset reg_custom_2 : UInt<64>, clock, reset, UInt<64>(0h0)
node _reg_custom_read_T_4 = neq(io.rw.cmd, UInt<3>(0h0))
node _reg_custom_read_T_5 = eq(io.rw.addr, UInt<12>(0hf11))
node reg_custom_read_2 = and(_reg_custom_read_T_4, _reg_custom_read_T_5)
connect io.customCSRs[2].ren, reg_custom_read_2
node _reg_custom_T_2 = and(reg_custom_read_2, io.customCSRs[2].stall)
when _reg_custom_T_2 :
connect io.rw_stall, UInt<1>(0h1)
regreset reg_custom_3 : UInt<64>, clock, reset, UInt<64>(0h20181004)
node _reg_custom_read_T_6 = neq(io.rw.cmd, UInt<3>(0h0))
node _reg_custom_read_T_7 = eq(io.rw.addr, UInt<12>(0hf13))
node reg_custom_read_3 = and(_reg_custom_read_T_6, _reg_custom_read_T_7)
connect io.customCSRs[3].ren, reg_custom_read_3
node _reg_custom_T_3 = and(reg_custom_read_3, io.customCSRs[3].stall)
when _reg_custom_T_3 :
connect io.rw_stall, UInt<1>(0h1)
node decoded_addr_addr = cat(io.status.v, io.rw.addr)
wire decoded_addr_decoded_decoded_plaInput : UInt<12>
node decoded_addr_decoded_decoded_invInputs = not(decoded_addr_decoded_decoded_plaInput)
wire decoded_addr_decoded_decoded : UInt<150>
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo)
node decoded_addr_decoded_decoded_andMatrixOutputs_138_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_1)
node decoded_addr_decoded_decoded_andMatrixOutputs_134_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_2)
node decoded_addr_decoded_decoded_andMatrixOutputs_41_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_3)
node decoded_addr_decoded_decoded_andMatrixOutputs_1_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_4)
node decoded_addr_decoded_decoded_andMatrixOutputs_89_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_5)
node decoded_addr_decoded_decoded_andMatrixOutputs_123_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_6)
node decoded_addr_decoded_decoded_andMatrixOutputs_27_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_7)
node decoded_addr_decoded_decoded_andMatrixOutputs_0_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_8)
node decoded_addr_decoded_decoded_andMatrixOutputs_92_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_9)
node decoded_addr_decoded_decoded_andMatrixOutputs_59_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_10)
node decoded_addr_decoded_decoded_andMatrixOutputs_24_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_11)
node decoded_addr_decoded_decoded_andMatrixOutputs_116_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_11)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_12)
node decoded_addr_decoded_decoded_andMatrixOutputs_121_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_12)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_13)
node decoded_addr_decoded_decoded_andMatrixOutputs_74_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_13)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_14)
node decoded_addr_decoded_decoded_andMatrixOutputs_114_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_14)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_15)
node decoded_addr_decoded_decoded_andMatrixOutputs_104_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_15)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_16)
node decoded_addr_decoded_decoded_andMatrixOutputs_82_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_16)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_17)
node decoded_addr_decoded_decoded_andMatrixOutputs_28_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_17)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_18)
node decoded_addr_decoded_decoded_andMatrixOutputs_91_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_18)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_19)
node decoded_addr_decoded_decoded_andMatrixOutputs_68_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_19)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_20)
node decoded_addr_decoded_decoded_andMatrixOutputs_84_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_20)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_21)
node decoded_addr_decoded_decoded_andMatrixOutputs_40_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_21)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_22)
node decoded_addr_decoded_decoded_andMatrixOutputs_34_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_22)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_23)
node decoded_addr_decoded_decoded_andMatrixOutputs_136_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_23)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_24)
node decoded_addr_decoded_decoded_andMatrixOutputs_55_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_24)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_25)
node decoded_addr_decoded_decoded_andMatrixOutputs_105_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_25)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_26)
node decoded_addr_decoded_decoded_andMatrixOutputs_109_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_26)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_27)
node decoded_addr_decoded_decoded_andMatrixOutputs_7_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_27)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_28)
node decoded_addr_decoded_decoded_andMatrixOutputs_47_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_28)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_29)
node decoded_addr_decoded_decoded_andMatrixOutputs_141_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_29)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_30)
node decoded_addr_decoded_decoded_andMatrixOutputs_11_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_30)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_31)
node decoded_addr_decoded_decoded_andMatrixOutputs_118_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_31)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_32)
node decoded_addr_decoded_decoded_andMatrixOutputs_120_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_32)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_33)
node decoded_addr_decoded_decoded_andMatrixOutputs_139_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_33)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_34)
node decoded_addr_decoded_decoded_andMatrixOutputs_86_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_34)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_35)
node decoded_addr_decoded_decoded_andMatrixOutputs_8_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_35)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_36)
node decoded_addr_decoded_decoded_andMatrixOutputs_61_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_36)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_37)
node decoded_addr_decoded_decoded_andMatrixOutputs_83_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_37)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_38)
node decoded_addr_decoded_decoded_andMatrixOutputs_129_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_38)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_39)
node decoded_addr_decoded_decoded_andMatrixOutputs_17_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_39)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_40)
node decoded_addr_decoded_decoded_andMatrixOutputs_87_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_40)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_41)
node decoded_addr_decoded_decoded_andMatrixOutputs_133_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_41)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_42)
node decoded_addr_decoded_decoded_andMatrixOutputs_142_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_42)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_43)
node decoded_addr_decoded_decoded_andMatrixOutputs_22_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_43)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_44)
node decoded_addr_decoded_decoded_andMatrixOutputs_94_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_44)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_45)
node decoded_addr_decoded_decoded_andMatrixOutputs_65_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_45)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_46)
node decoded_addr_decoded_decoded_andMatrixOutputs_36_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_46)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_47)
node decoded_addr_decoded_decoded_andMatrixOutputs_33_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_47)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_48)
node decoded_addr_decoded_decoded_andMatrixOutputs_63_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_48)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_49)
node decoded_addr_decoded_decoded_andMatrixOutputs_39_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_49)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_50)
node decoded_addr_decoded_decoded_andMatrixOutputs_32_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_50)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_51)
node decoded_addr_decoded_decoded_andMatrixOutputs_144_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_51)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_52)
node decoded_addr_decoded_decoded_andMatrixOutputs_66_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_52)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_53)
node decoded_addr_decoded_decoded_andMatrixOutputs_106_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_53)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_54)
node decoded_addr_decoded_decoded_andMatrixOutputs_80_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_54)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_55)
node decoded_addr_decoded_decoded_andMatrixOutputs_122_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_55)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_56)
node decoded_addr_decoded_decoded_andMatrixOutputs_119_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_56)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_57)
node decoded_addr_decoded_decoded_andMatrixOutputs_67_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_57)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_58)
node decoded_addr_decoded_decoded_andMatrixOutputs_48_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_58)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_59)
node decoded_addr_decoded_decoded_andMatrixOutputs_10_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_59)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_60)
node decoded_addr_decoded_decoded_andMatrixOutputs_45_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_60)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_61)
node decoded_addr_decoded_decoded_andMatrixOutputs_18_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_61)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_62)
node decoded_addr_decoded_decoded_andMatrixOutputs_88_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_62)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_63)
node decoded_addr_decoded_decoded_andMatrixOutputs_57_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_63)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_64)
node decoded_addr_decoded_decoded_andMatrixOutputs_85_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_64)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_65)
node decoded_addr_decoded_decoded_andMatrixOutputs_100_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_65)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_66)
node decoded_addr_decoded_decoded_andMatrixOutputs_111_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_66)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_67)
node decoded_addr_decoded_decoded_andMatrixOutputs_93_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_67)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_68)
node decoded_addr_decoded_decoded_andMatrixOutputs_137_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_68)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_69)
node decoded_addr_decoded_decoded_andMatrixOutputs_72_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_69)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_70)
node decoded_addr_decoded_decoded_andMatrixOutputs_42_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_70)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_71)
node decoded_addr_decoded_decoded_andMatrixOutputs_145_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_71)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_72)
node decoded_addr_decoded_decoded_andMatrixOutputs_98_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_72)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_73)
node decoded_addr_decoded_decoded_andMatrixOutputs_113_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_73)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_74)
node decoded_addr_decoded_decoded_andMatrixOutputs_149_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_74)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_75)
node decoded_addr_decoded_decoded_andMatrixOutputs_2_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_75)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_76)
node decoded_addr_decoded_decoded_andMatrixOutputs_146_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_76)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_77)
node decoded_addr_decoded_decoded_andMatrixOutputs_128_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_77)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_78)
node decoded_addr_decoded_decoded_andMatrixOutputs_56_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_78)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_79)
node decoded_addr_decoded_decoded_andMatrixOutputs_3_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_79)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_80)
node decoded_addr_decoded_decoded_andMatrixOutputs_50_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_80)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_lo_81)
node decoded_addr_decoded_decoded_andMatrixOutputs_23_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_81)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_82)
node decoded_addr_decoded_decoded_andMatrixOutputs_12_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_82)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_83)
node decoded_addr_decoded_decoded_andMatrixOutputs_76_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_83)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_84)
node decoded_addr_decoded_decoded_andMatrixOutputs_79_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_84)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_85)
node decoded_addr_decoded_decoded_andMatrixOutputs_95_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_85)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_86)
node decoded_addr_decoded_decoded_andMatrixOutputs_26_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_86)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_87)
node decoded_addr_decoded_decoded_andMatrixOutputs_124_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_87)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_88)
node decoded_addr_decoded_decoded_andMatrixOutputs_147_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_88)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_89)
node decoded_addr_decoded_decoded_andMatrixOutputs_77_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_89)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_90)
node decoded_addr_decoded_decoded_andMatrixOutputs_140_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_90)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_91)
node decoded_addr_decoded_decoded_andMatrixOutputs_44_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_91)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_92)
node decoded_addr_decoded_decoded_andMatrixOutputs_31_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_92)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_93)
node decoded_addr_decoded_decoded_andMatrixOutputs_62_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_93)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_94)
node decoded_addr_decoded_decoded_andMatrixOutputs_58_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_94)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_95)
node decoded_addr_decoded_decoded_andMatrixOutputs_132_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_95)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_96)
node decoded_addr_decoded_decoded_andMatrixOutputs_9_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_96)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_97)
node decoded_addr_decoded_decoded_andMatrixOutputs_115_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_97)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_98)
node decoded_addr_decoded_decoded_andMatrixOutputs_5_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_98)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_99)
node decoded_addr_decoded_decoded_andMatrixOutputs_71_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_99)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_100)
node decoded_addr_decoded_decoded_andMatrixOutputs_130_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_100)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_101)
node decoded_addr_decoded_decoded_andMatrixOutputs_102_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_101)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_102)
node decoded_addr_decoded_decoded_andMatrixOutputs_4_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_102)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_103)
node decoded_addr_decoded_decoded_andMatrixOutputs_29_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_103)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_104)
node decoded_addr_decoded_decoded_andMatrixOutputs_16_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_104)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_105)
node decoded_addr_decoded_decoded_andMatrixOutputs_143_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_105)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_106)
node decoded_addr_decoded_decoded_andMatrixOutputs_131_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_106)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_107)
node decoded_addr_decoded_decoded_andMatrixOutputs_14_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_107)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_108)
node decoded_addr_decoded_decoded_andMatrixOutputs_90_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_108)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_109)
node decoded_addr_decoded_decoded_andMatrixOutputs_97_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_109)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_110)
node decoded_addr_decoded_decoded_andMatrixOutputs_60_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_110)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_111)
node decoded_addr_decoded_decoded_andMatrixOutputs_96_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_111)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_112)
node decoded_addr_decoded_decoded_andMatrixOutputs_54_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_112)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_113)
node decoded_addr_decoded_decoded_andMatrixOutputs_126_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_113)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_114)
node decoded_addr_decoded_decoded_andMatrixOutputs_49_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_114)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_115)
node decoded_addr_decoded_decoded_andMatrixOutputs_52_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_115)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_116)
node decoded_addr_decoded_decoded_andMatrixOutputs_20_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_116)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_117)
node decoded_addr_decoded_decoded_andMatrixOutputs_107_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_117)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_118)
node decoded_addr_decoded_decoded_andMatrixOutputs_6_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_118)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_119)
node decoded_addr_decoded_decoded_andMatrixOutputs_21_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_119)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_120)
node decoded_addr_decoded_decoded_andMatrixOutputs_30_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_120)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_121)
node decoded_addr_decoded_decoded_andMatrixOutputs_127_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_121)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_122)
node decoded_addr_decoded_decoded_andMatrixOutputs_35_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_122)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_123)
node decoded_addr_decoded_decoded_andMatrixOutputs_73_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_123)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_124)
node decoded_addr_decoded_decoded_andMatrixOutputs_53_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_124)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_125)
node decoded_addr_decoded_decoded_andMatrixOutputs_135_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_125)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_126)
node decoded_addr_decoded_decoded_andMatrixOutputs_37_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_126)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_127)
node decoded_addr_decoded_decoded_andMatrixOutputs_25_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_127)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_128)
node decoded_addr_decoded_decoded_andMatrixOutputs_64_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_128)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_129)
node decoded_addr_decoded_decoded_andMatrixOutputs_19_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_129)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_130)
node decoded_addr_decoded_decoded_andMatrixOutputs_112_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_130)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_131)
node decoded_addr_decoded_decoded_andMatrixOutputs_108_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_131)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_132)
node decoded_addr_decoded_decoded_andMatrixOutputs_148_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_132)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_133)
node decoded_addr_decoded_decoded_andMatrixOutputs_69_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_133)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_134)
node decoded_addr_decoded_decoded_andMatrixOutputs_103_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_134)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_135)
node decoded_addr_decoded_decoded_andMatrixOutputs_99_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_135)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_136)
node decoded_addr_decoded_decoded_andMatrixOutputs_125_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_136)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_137)
node decoded_addr_decoded_decoded_andMatrixOutputs_117_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_137)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_138)
node decoded_addr_decoded_decoded_andMatrixOutputs_46_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_138)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_139)
node decoded_addr_decoded_decoded_andMatrixOutputs_15_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_139)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_140)
node decoded_addr_decoded_decoded_andMatrixOutputs_51_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_140)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_141)
node decoded_addr_decoded_decoded_andMatrixOutputs_43_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_141)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_142)
node decoded_addr_decoded_decoded_andMatrixOutputs_70_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_142)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_143)
node decoded_addr_decoded_decoded_andMatrixOutputs_78_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_143)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_144)
node decoded_addr_decoded_decoded_andMatrixOutputs_110_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_144)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_145)
node decoded_addr_decoded_decoded_andMatrixOutputs_101_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_145)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_146)
node decoded_addr_decoded_decoded_andMatrixOutputs_38_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_146)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_147)
node decoded_addr_decoded_decoded_andMatrixOutputs_13_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_147)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_148)
node decoded_addr_decoded_decoded_andMatrixOutputs_81_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_148)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10)
node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147)
node decoded_addr_decoded_decoded_andMatrixOutputs_lo_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149)
node decoded_addr_decoded_decoded_andMatrixOutputs_hi_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147)
node _decoded_addr_decoded_decoded_andMatrixOutputs_T_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_lo_149)
node decoded_addr_decoded_decoded_andMatrixOutputs_75_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_149)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T = orr(decoded_addr_decoded_decoded_andMatrixOutputs_75_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_1 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_13_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_2 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_101_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_3 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_38_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_4 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_12_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_5 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_149_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_6 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_113_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_7 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_98_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_8 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_145_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_9 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_42_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_10 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_72_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_11 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_137_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_12 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_93_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_13 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_111_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_14 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_100_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_15 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_85_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_16 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_57_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_17 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_88_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_18 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_18_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_19 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_45_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_20 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_10_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_21 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_48_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_22 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_67_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_23 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_0_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_24 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_82_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_25 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_28_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_26 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_27_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_27 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_123_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_28 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_59_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_29 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_74_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_30 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_116_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_31 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_24_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_32 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_92_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_33 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_89_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_34 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_121_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_35 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_1_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_36 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_40_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_37 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_52_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_38 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_49_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_39 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_84_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_40 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_110_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_41 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_126_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_42 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_144_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_43 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_78_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_44 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_54_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_45 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_32_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_46 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_70_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_47 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_96_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_48 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_39_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_49 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_43_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_50 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_60_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_51 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_63_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_52 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_51_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_53 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_97_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_54 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_33_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_55 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_15_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_56 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_90_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_57 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_36_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_58 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_46_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_59 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_14_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_60 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_65_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_61 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_117_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_62 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_131_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_63 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_94_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_64 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_125_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_65 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_143_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_66 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_22_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_67 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_99_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_68 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_16_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_69 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_142_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_70 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_103_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_71 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_29_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_72 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_133_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_73 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_69_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_74 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_4_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_75 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_87_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_76 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_148_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_77 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_102_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_78 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_17_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_79 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_108_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_80 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_130_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_81 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_129_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_82 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_112_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_83 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_71_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_84 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_83_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_85 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_19_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_86 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_5_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_87 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_61_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_88 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_64_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_89 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_115_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_90 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_8_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_91 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_25_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_92 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_9_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_93 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_86_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_94 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_37_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_95 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_132_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_96 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_139_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_97 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_135_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_98 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_58_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_99 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_120_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_100 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_53_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_101 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_62_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_102 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_118_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_103 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_73_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_104 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_31_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_105 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_11_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_106 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_35_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_107 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_44_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_108 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_141_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_109 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_127_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_110 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_140_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_111 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_47_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_112 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_30_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_113 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_77_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_114 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_7_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_115 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_21_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_116 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_147_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_117 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_109_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_118 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_6_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_119 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_124_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_120 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_105_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_121 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_107_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_122 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_26_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_123 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_55_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_124 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_20_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_125 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_95_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_126 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_136_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_127 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_79_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_128 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_76_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_129 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_34_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_130 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_41_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_131 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_134_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_132 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_138_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_133 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_23_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_134 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_50_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_135 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_3_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_136 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_81_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_137 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_80_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_138 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_122_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_139 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_106_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_140 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_66_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_141 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_91_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_142 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_119_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_143 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_68_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_144 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_114_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_145 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_104_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_146 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_56_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_147 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_128_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_148 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_146_2)
node _decoded_addr_decoded_decoded_orMatrixOutputs_T_149 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_2_2)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_1, _decoded_addr_decoded_decoded_orMatrixOutputs_T)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_3, _decoded_addr_decoded_decoded_orMatrixOutputs_T_2)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_5, _decoded_addr_decoded_decoded_orMatrixOutputs_T_4)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_8, _decoded_addr_decoded_decoded_orMatrixOutputs_T_7)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_6)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_10, _decoded_addr_decoded_decoded_orMatrixOutputs_T_9)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_12, _decoded_addr_decoded_decoded_orMatrixOutputs_T_11)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_14, _decoded_addr_decoded_decoded_orMatrixOutputs_T_13)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_17, _decoded_addr_decoded_decoded_orMatrixOutputs_T_16)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_15)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_19, _decoded_addr_decoded_decoded_orMatrixOutputs_T_18)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_21, _decoded_addr_decoded_decoded_orMatrixOutputs_T_20)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_23, _decoded_addr_decoded_decoded_orMatrixOutputs_T_22)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_26, _decoded_addr_decoded_decoded_orMatrixOutputs_T_25)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_24)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_28, _decoded_addr_decoded_decoded_orMatrixOutputs_T_27)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_31, _decoded_addr_decoded_decoded_orMatrixOutputs_T_30)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_29)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_33, _decoded_addr_decoded_decoded_orMatrixOutputs_T_32)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_36, _decoded_addr_decoded_decoded_orMatrixOutputs_T_35)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_34)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_38, _decoded_addr_decoded_decoded_orMatrixOutputs_T_37)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_40, _decoded_addr_decoded_decoded_orMatrixOutputs_T_39)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_42, _decoded_addr_decoded_decoded_orMatrixOutputs_T_41)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_45, _decoded_addr_decoded_decoded_orMatrixOutputs_T_44)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_43)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_47, _decoded_addr_decoded_decoded_orMatrixOutputs_T_46)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_50, _decoded_addr_decoded_decoded_orMatrixOutputs_T_49)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_48)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_52, _decoded_addr_decoded_decoded_orMatrixOutputs_T_51)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_55, _decoded_addr_decoded_decoded_orMatrixOutputs_T_54)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_53)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_57, _decoded_addr_decoded_decoded_orMatrixOutputs_T_56)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_59, _decoded_addr_decoded_decoded_orMatrixOutputs_T_58)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_61, _decoded_addr_decoded_decoded_orMatrixOutputs_T_60)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_64, _decoded_addr_decoded_decoded_orMatrixOutputs_T_63)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_62)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_66, _decoded_addr_decoded_decoded_orMatrixOutputs_T_65)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_69, _decoded_addr_decoded_decoded_orMatrixOutputs_T_68)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_67)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_71, _decoded_addr_decoded_decoded_orMatrixOutputs_T_70)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_74, _decoded_addr_decoded_decoded_orMatrixOutputs_T_73)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_72)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_76, _decoded_addr_decoded_decoded_orMatrixOutputs_T_75)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_78, _decoded_addr_decoded_decoded_orMatrixOutputs_T_77)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_80, _decoded_addr_decoded_decoded_orMatrixOutputs_T_79)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_83, _decoded_addr_decoded_decoded_orMatrixOutputs_T_82)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_81)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_85, _decoded_addr_decoded_decoded_orMatrixOutputs_T_84)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_87, _decoded_addr_decoded_decoded_orMatrixOutputs_T_86)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_89, _decoded_addr_decoded_decoded_orMatrixOutputs_T_88)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_92, _decoded_addr_decoded_decoded_orMatrixOutputs_T_91)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_90)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_94, _decoded_addr_decoded_decoded_orMatrixOutputs_T_93)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_96, _decoded_addr_decoded_decoded_orMatrixOutputs_T_95)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_98, _decoded_addr_decoded_decoded_orMatrixOutputs_T_97)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_101, _decoded_addr_decoded_decoded_orMatrixOutputs_T_100)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_99)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_103, _decoded_addr_decoded_decoded_orMatrixOutputs_T_102)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_106, _decoded_addr_decoded_decoded_orMatrixOutputs_T_105)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_104)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_108, _decoded_addr_decoded_decoded_orMatrixOutputs_T_107)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_111, _decoded_addr_decoded_decoded_orMatrixOutputs_T_110)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_109)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_113, _decoded_addr_decoded_decoded_orMatrixOutputs_T_112)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_115, _decoded_addr_decoded_decoded_orMatrixOutputs_T_114)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_117, _decoded_addr_decoded_decoded_orMatrixOutputs_T_116)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_120, _decoded_addr_decoded_decoded_orMatrixOutputs_T_119)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_118)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_122, _decoded_addr_decoded_decoded_orMatrixOutputs_T_121)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_125, _decoded_addr_decoded_decoded_orMatrixOutputs_T_124)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_123)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_127, _decoded_addr_decoded_decoded_orMatrixOutputs_T_126)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_130, _decoded_addr_decoded_decoded_orMatrixOutputs_T_129)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_128)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_132, _decoded_addr_decoded_decoded_orMatrixOutputs_T_131)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_134, _decoded_addr_decoded_decoded_orMatrixOutputs_T_133)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_136, _decoded_addr_decoded_decoded_orMatrixOutputs_T_135)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_139, _decoded_addr_decoded_decoded_orMatrixOutputs_T_138)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_137)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_141, _decoded_addr_decoded_decoded_orMatrixOutputs_T_140)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_144, _decoded_addr_decoded_decoded_orMatrixOutputs_T_143)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_142)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_146, _decoded_addr_decoded_decoded_orMatrixOutputs_T_145)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_149, _decoded_addr_decoded_decoded_orMatrixOutputs_T_148)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_147)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo)
node decoded_addr_decoded_decoded_orMatrixOutputs = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 0, 0)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_1 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 1, 1)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_2 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 2, 2)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_3 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 3, 3)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_4 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 4, 4)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_5 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 5, 5)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_6 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 6, 6)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_7 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 7, 7)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_8 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 8, 8)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_9 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 9, 9)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_10 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 10, 10)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_11 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 11, 11)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_12 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 12, 12)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_13 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 13, 13)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_14 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 14, 14)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_15 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 15, 15)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_16 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 16, 16)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_17 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 17, 17)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_18 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 18, 18)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_19 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 19, 19)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_20 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 20, 20)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_21 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 21, 21)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_22 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 22, 22)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_23 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 23, 23)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_24 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 24, 24)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_25 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 25, 25)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_26 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 26, 26)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_27 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 27, 27)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_28 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 28, 28)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_29 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 29, 29)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_30 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 30, 30)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_31 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 31, 31)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_32 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 32, 32)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_33 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 33, 33)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_34 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 34, 34)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_35 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 35, 35)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_36 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 36, 36)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_37 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 37, 37)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_38 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 38, 38)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_39 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 39, 39)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_40 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 40, 40)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_41 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 41, 41)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_42 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 42, 42)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_43 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 43, 43)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_44 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 44, 44)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_45 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 45, 45)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_46 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 46, 46)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_47 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 47, 47)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_48 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 48, 48)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_49 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 49, 49)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_50 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 50, 50)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_51 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 51, 51)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_52 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 52, 52)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_53 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 53, 53)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_54 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 54, 54)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_55 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 55, 55)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_56 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 56, 56)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_57 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 57, 57)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_58 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 58, 58)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_59 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 59, 59)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_60 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 60, 60)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_61 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 61, 61)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_62 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 62, 62)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_63 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 63, 63)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_64 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 64, 64)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_65 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 65, 65)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_66 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 66, 66)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_67 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 67, 67)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_68 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 68, 68)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_69 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 69, 69)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_70 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 70, 70)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_71 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 71, 71)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_72 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 72, 72)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_73 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 73, 73)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_74 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 74, 74)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_75 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 75, 75)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_76 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 76, 76)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_77 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 77, 77)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_78 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 78, 78)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_79 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 79, 79)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_80 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 80, 80)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_81 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 81, 81)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_82 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 82, 82)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_83 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 83, 83)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_84 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 84, 84)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_85 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 85, 85)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_86 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 86, 86)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_87 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 87, 87)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_88 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 88, 88)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_89 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 89, 89)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_90 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 90, 90)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_91 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 91, 91)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_92 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 92, 92)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_93 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 93, 93)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_94 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 94, 94)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_95 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 95, 95)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_96 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 96, 96)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_97 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 97, 97)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_98 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 98, 98)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_99 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 99, 99)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_100 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 100, 100)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_101 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 101, 101)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_102 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 102, 102)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_103 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 103, 103)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_104 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 104, 104)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_105 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 105, 105)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_106 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 106, 106)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_107 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 107, 107)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_108 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 108, 108)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_109 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 109, 109)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_110 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 110, 110)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_111 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 111, 111)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_112 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 112, 112)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_113 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 113, 113)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_114 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 114, 114)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_115 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 115, 115)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_116 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 116, 116)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_117 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 117, 117)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_118 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 118, 118)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_119 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 119, 119)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_120 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 120, 120)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_121 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 121, 121)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_122 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 122, 122)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_123 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 123, 123)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_124 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 124, 124)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_125 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 125, 125)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_126 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 126, 126)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_127 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 127, 127)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_128 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 128, 128)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_129 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 129, 129)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_130 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 130, 130)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_131 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 131, 131)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_132 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 132, 132)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_133 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 133, 133)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_134 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 134, 134)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_135 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 135, 135)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_136 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 136, 136)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_137 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 137, 137)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_138 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 138, 138)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_139 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 139, 139)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_140 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 140, 140)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_141 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 141, 141)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_142 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 142, 142)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_143 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 143, 143)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_144 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 144, 144)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_145 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 145, 145)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_146 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 146, 146)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_147 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 147, 147)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_148 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 148, 148)
node _decoded_addr_decoded_decoded_invMatrixOutputs_T_149 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 149, 149)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_1, _decoded_addr_decoded_decoded_invMatrixOutputs_T)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_3, _decoded_addr_decoded_decoded_invMatrixOutputs_T_2)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_5, _decoded_addr_decoded_decoded_invMatrixOutputs_T_4)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_8, _decoded_addr_decoded_decoded_invMatrixOutputs_T_7)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_6)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_10, _decoded_addr_decoded_decoded_invMatrixOutputs_T_9)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_12, _decoded_addr_decoded_decoded_invMatrixOutputs_T_11)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_14, _decoded_addr_decoded_decoded_invMatrixOutputs_T_13)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_17, _decoded_addr_decoded_decoded_invMatrixOutputs_T_16)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_15)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_19, _decoded_addr_decoded_decoded_invMatrixOutputs_T_18)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_21, _decoded_addr_decoded_decoded_invMatrixOutputs_T_20)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_23, _decoded_addr_decoded_decoded_invMatrixOutputs_T_22)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_26, _decoded_addr_decoded_decoded_invMatrixOutputs_T_25)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_24)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_28, _decoded_addr_decoded_decoded_invMatrixOutputs_T_27)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_31, _decoded_addr_decoded_decoded_invMatrixOutputs_T_30)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_29)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_33, _decoded_addr_decoded_decoded_invMatrixOutputs_T_32)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_36, _decoded_addr_decoded_decoded_invMatrixOutputs_T_35)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_34)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_38, _decoded_addr_decoded_decoded_invMatrixOutputs_T_37)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_40, _decoded_addr_decoded_decoded_invMatrixOutputs_T_39)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_42, _decoded_addr_decoded_decoded_invMatrixOutputs_T_41)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_45, _decoded_addr_decoded_decoded_invMatrixOutputs_T_44)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_43)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_47, _decoded_addr_decoded_decoded_invMatrixOutputs_T_46)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_50, _decoded_addr_decoded_decoded_invMatrixOutputs_T_49)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_48)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_52, _decoded_addr_decoded_decoded_invMatrixOutputs_T_51)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_55, _decoded_addr_decoded_decoded_invMatrixOutputs_T_54)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_53)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_57, _decoded_addr_decoded_decoded_invMatrixOutputs_T_56)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_59, _decoded_addr_decoded_decoded_invMatrixOutputs_T_58)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_61, _decoded_addr_decoded_decoded_invMatrixOutputs_T_60)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_64, _decoded_addr_decoded_decoded_invMatrixOutputs_T_63)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_62)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_66, _decoded_addr_decoded_decoded_invMatrixOutputs_T_65)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_69, _decoded_addr_decoded_decoded_invMatrixOutputs_T_68)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_67)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_71, _decoded_addr_decoded_decoded_invMatrixOutputs_T_70)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_74, _decoded_addr_decoded_decoded_invMatrixOutputs_T_73)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_72)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_76, _decoded_addr_decoded_decoded_invMatrixOutputs_T_75)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_78, _decoded_addr_decoded_decoded_invMatrixOutputs_T_77)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_80, _decoded_addr_decoded_decoded_invMatrixOutputs_T_79)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_83, _decoded_addr_decoded_decoded_invMatrixOutputs_T_82)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_81)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_85, _decoded_addr_decoded_decoded_invMatrixOutputs_T_84)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_87, _decoded_addr_decoded_decoded_invMatrixOutputs_T_86)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_89, _decoded_addr_decoded_decoded_invMatrixOutputs_T_88)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_92, _decoded_addr_decoded_decoded_invMatrixOutputs_T_91)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_90)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_94, _decoded_addr_decoded_decoded_invMatrixOutputs_T_93)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_96, _decoded_addr_decoded_decoded_invMatrixOutputs_T_95)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_98, _decoded_addr_decoded_decoded_invMatrixOutputs_T_97)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_101, _decoded_addr_decoded_decoded_invMatrixOutputs_T_100)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_99)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_103, _decoded_addr_decoded_decoded_invMatrixOutputs_T_102)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_106, _decoded_addr_decoded_decoded_invMatrixOutputs_T_105)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_104)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_108, _decoded_addr_decoded_decoded_invMatrixOutputs_T_107)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_111, _decoded_addr_decoded_decoded_invMatrixOutputs_T_110)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_109)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_113, _decoded_addr_decoded_decoded_invMatrixOutputs_T_112)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_115, _decoded_addr_decoded_decoded_invMatrixOutputs_T_114)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_117, _decoded_addr_decoded_decoded_invMatrixOutputs_T_116)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_120, _decoded_addr_decoded_decoded_invMatrixOutputs_T_119)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_118)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_122, _decoded_addr_decoded_decoded_invMatrixOutputs_T_121)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_125, _decoded_addr_decoded_decoded_invMatrixOutputs_T_124)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_123)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_127, _decoded_addr_decoded_decoded_invMatrixOutputs_T_126)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_130, _decoded_addr_decoded_decoded_invMatrixOutputs_T_129)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_128)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_132, _decoded_addr_decoded_decoded_invMatrixOutputs_T_131)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_134, _decoded_addr_decoded_decoded_invMatrixOutputs_T_133)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_136, _decoded_addr_decoded_decoded_invMatrixOutputs_T_135)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_139, _decoded_addr_decoded_decoded_invMatrixOutputs_T_138)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_137)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_141, _decoded_addr_decoded_decoded_invMatrixOutputs_T_140)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_144, _decoded_addr_decoded_decoded_invMatrixOutputs_T_143)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_142)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_146, _decoded_addr_decoded_decoded_invMatrixOutputs_T_145)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_149, _decoded_addr_decoded_decoded_invMatrixOutputs_T_148)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_147)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo)
node decoded_addr_decoded_decoded_invMatrixOutputs = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo)
connect decoded_addr_decoded_decoded, decoded_addr_decoded_decoded_invMatrixOutputs
connect decoded_addr_decoded_decoded_plaInput, decoded_addr_addr
node decoded_addr_decoded_0 = bits(decoded_addr_decoded_decoded, 149, 149)
node decoded_addr_decoded_1 = bits(decoded_addr_decoded_decoded, 148, 148)
node decoded_addr_decoded_2 = bits(decoded_addr_decoded_decoded, 147, 147)
node decoded_addr_decoded_3 = bits(decoded_addr_decoded_decoded, 146, 146)
node decoded_addr_decoded_4 = bits(decoded_addr_decoded_decoded, 145, 145)
node decoded_addr_decoded_5 = bits(decoded_addr_decoded_decoded, 144, 144)
node decoded_addr_decoded_6 = bits(decoded_addr_decoded_decoded, 143, 143)
node decoded_addr_decoded_7 = bits(decoded_addr_decoded_decoded, 142, 142)
node decoded_addr_decoded_8 = bits(decoded_addr_decoded_decoded, 141, 141)
node decoded_addr_decoded_9 = bits(decoded_addr_decoded_decoded, 140, 140)
node decoded_addr_decoded_10 = bits(decoded_addr_decoded_decoded, 139, 139)
node decoded_addr_decoded_11 = bits(decoded_addr_decoded_decoded, 138, 138)
node decoded_addr_decoded_12 = bits(decoded_addr_decoded_decoded, 137, 137)
node decoded_addr_decoded_13 = bits(decoded_addr_decoded_decoded, 136, 136)
node decoded_addr_decoded_14 = bits(decoded_addr_decoded_decoded, 135, 135)
node decoded_addr_decoded_15 = bits(decoded_addr_decoded_decoded, 134, 134)
node decoded_addr_decoded_16 = bits(decoded_addr_decoded_decoded, 133, 133)
node decoded_addr_decoded_17 = bits(decoded_addr_decoded_decoded, 132, 132)
node decoded_addr_decoded_18 = bits(decoded_addr_decoded_decoded, 131, 131)
node decoded_addr_decoded_19 = bits(decoded_addr_decoded_decoded, 130, 130)
node decoded_addr_decoded_20 = bits(decoded_addr_decoded_decoded, 129, 129)
node decoded_addr_decoded_21 = bits(decoded_addr_decoded_decoded, 128, 128)
node decoded_addr_decoded_22 = bits(decoded_addr_decoded_decoded, 127, 127)
node decoded_addr_decoded_23 = bits(decoded_addr_decoded_decoded, 126, 126)
node decoded_addr_decoded_24 = bits(decoded_addr_decoded_decoded, 125, 125)
node decoded_addr_decoded_25 = bits(decoded_addr_decoded_decoded, 124, 124)
node decoded_addr_decoded_26 = bits(decoded_addr_decoded_decoded, 123, 123)
node decoded_addr_decoded_27 = bits(decoded_addr_decoded_decoded, 122, 122)
node decoded_addr_decoded_28 = bits(decoded_addr_decoded_decoded, 121, 121)
node decoded_addr_decoded_29 = bits(decoded_addr_decoded_decoded, 120, 120)
node decoded_addr_decoded_30 = bits(decoded_addr_decoded_decoded, 119, 119)
node decoded_addr_decoded_31 = bits(decoded_addr_decoded_decoded, 118, 118)
node decoded_addr_decoded_32 = bits(decoded_addr_decoded_decoded, 117, 117)
node decoded_addr_decoded_33 = bits(decoded_addr_decoded_decoded, 116, 116)
node decoded_addr_decoded_34 = bits(decoded_addr_decoded_decoded, 115, 115)
node decoded_addr_decoded_35 = bits(decoded_addr_decoded_decoded, 114, 114)
node decoded_addr_decoded_36 = bits(decoded_addr_decoded_decoded, 113, 113)
node decoded_addr_decoded_37 = bits(decoded_addr_decoded_decoded, 112, 112)
node decoded_addr_decoded_38 = bits(decoded_addr_decoded_decoded, 111, 111)
node decoded_addr_decoded_39 = bits(decoded_addr_decoded_decoded, 110, 110)
node decoded_addr_decoded_40 = bits(decoded_addr_decoded_decoded, 109, 109)
node decoded_addr_decoded_41 = bits(decoded_addr_decoded_decoded, 108, 108)
node decoded_addr_decoded_42 = bits(decoded_addr_decoded_decoded, 107, 107)
node decoded_addr_decoded_43 = bits(decoded_addr_decoded_decoded, 106, 106)
node decoded_addr_decoded_44 = bits(decoded_addr_decoded_decoded, 105, 105)
node decoded_addr_decoded_45 = bits(decoded_addr_decoded_decoded, 104, 104)
node decoded_addr_decoded_46 = bits(decoded_addr_decoded_decoded, 103, 103)
node decoded_addr_decoded_47 = bits(decoded_addr_decoded_decoded, 102, 102)
node decoded_addr_decoded_48 = bits(decoded_addr_decoded_decoded, 101, 101)
node decoded_addr_decoded_49 = bits(decoded_addr_decoded_decoded, 100, 100)
node decoded_addr_decoded_50 = bits(decoded_addr_decoded_decoded, 99, 99)
node decoded_addr_decoded_51 = bits(decoded_addr_decoded_decoded, 98, 98)
node decoded_addr_decoded_52 = bits(decoded_addr_decoded_decoded, 97, 97)
node decoded_addr_decoded_53 = bits(decoded_addr_decoded_decoded, 96, 96)
node decoded_addr_decoded_54 = bits(decoded_addr_decoded_decoded, 95, 95)
node decoded_addr_decoded_55 = bits(decoded_addr_decoded_decoded, 94, 94)
node decoded_addr_decoded_56 = bits(decoded_addr_decoded_decoded, 93, 93)
node decoded_addr_decoded_57 = bits(decoded_addr_decoded_decoded, 92, 92)
node decoded_addr_decoded_58 = bits(decoded_addr_decoded_decoded, 91, 91)
node decoded_addr_decoded_59 = bits(decoded_addr_decoded_decoded, 90, 90)
node decoded_addr_decoded_60 = bits(decoded_addr_decoded_decoded, 89, 89)
node decoded_addr_decoded_61 = bits(decoded_addr_decoded_decoded, 88, 88)
node decoded_addr_decoded_62 = bits(decoded_addr_decoded_decoded, 87, 87)
node decoded_addr_decoded_63 = bits(decoded_addr_decoded_decoded, 86, 86)
node decoded_addr_decoded_64 = bits(decoded_addr_decoded_decoded, 85, 85)
node decoded_addr_decoded_65 = bits(decoded_addr_decoded_decoded, 84, 84)
node decoded_addr_decoded_66 = bits(decoded_addr_decoded_decoded, 83, 83)
node decoded_addr_decoded_67 = bits(decoded_addr_decoded_decoded, 82, 82)
node decoded_addr_decoded_68 = bits(decoded_addr_decoded_decoded, 81, 81)
node decoded_addr_decoded_69 = bits(decoded_addr_decoded_decoded, 80, 80)
node decoded_addr_decoded_70 = bits(decoded_addr_decoded_decoded, 79, 79)
node decoded_addr_decoded_71 = bits(decoded_addr_decoded_decoded, 78, 78)
node decoded_addr_decoded_72 = bits(decoded_addr_decoded_decoded, 77, 77)
node decoded_addr_decoded_73 = bits(decoded_addr_decoded_decoded, 76, 76)
node decoded_addr_decoded_74 = bits(decoded_addr_decoded_decoded, 75, 75)
node decoded_addr_decoded_75 = bits(decoded_addr_decoded_decoded, 74, 74)
node decoded_addr_decoded_76 = bits(decoded_addr_decoded_decoded, 73, 73)
node decoded_addr_decoded_77 = bits(decoded_addr_decoded_decoded, 72, 72)
node decoded_addr_decoded_78 = bits(decoded_addr_decoded_decoded, 71, 71)
node decoded_addr_decoded_79 = bits(decoded_addr_decoded_decoded, 70, 70)
node decoded_addr_decoded_80 = bits(decoded_addr_decoded_decoded, 69, 69)
node decoded_addr_decoded_81 = bits(decoded_addr_decoded_decoded, 68, 68)
node decoded_addr_decoded_82 = bits(decoded_addr_decoded_decoded, 67, 67)
node decoded_addr_decoded_83 = bits(decoded_addr_decoded_decoded, 66, 66)
node decoded_addr_decoded_84 = bits(decoded_addr_decoded_decoded, 65, 65)
node decoded_addr_decoded_85 = bits(decoded_addr_decoded_decoded, 64, 64)
node decoded_addr_decoded_86 = bits(decoded_addr_decoded_decoded, 63, 63)
node decoded_addr_decoded_87 = bits(decoded_addr_decoded_decoded, 62, 62)
node decoded_addr_decoded_88 = bits(decoded_addr_decoded_decoded, 61, 61)
node decoded_addr_decoded_89 = bits(decoded_addr_decoded_decoded, 60, 60)
node decoded_addr_decoded_90 = bits(decoded_addr_decoded_decoded, 59, 59)
node decoded_addr_decoded_91 = bits(decoded_addr_decoded_decoded, 58, 58)
node decoded_addr_decoded_92 = bits(decoded_addr_decoded_decoded, 57, 57)
node decoded_addr_decoded_93 = bits(decoded_addr_decoded_decoded, 56, 56)
node decoded_addr_decoded_94 = bits(decoded_addr_decoded_decoded, 55, 55)
node decoded_addr_decoded_95 = bits(decoded_addr_decoded_decoded, 54, 54)
node decoded_addr_decoded_96 = bits(decoded_addr_decoded_decoded, 53, 53)
node decoded_addr_decoded_97 = bits(decoded_addr_decoded_decoded, 52, 52)
node decoded_addr_decoded_98 = bits(decoded_addr_decoded_decoded, 51, 51)
node decoded_addr_decoded_99 = bits(decoded_addr_decoded_decoded, 50, 50)
node decoded_addr_decoded_100 = bits(decoded_addr_decoded_decoded, 49, 49)
node decoded_addr_decoded_101 = bits(decoded_addr_decoded_decoded, 48, 48)
node decoded_addr_decoded_102 = bits(decoded_addr_decoded_decoded, 47, 47)
node decoded_addr_decoded_103 = bits(decoded_addr_decoded_decoded, 46, 46)
node decoded_addr_decoded_104 = bits(decoded_addr_decoded_decoded, 45, 45)
node decoded_addr_decoded_105 = bits(decoded_addr_decoded_decoded, 44, 44)
node decoded_addr_decoded_106 = bits(decoded_addr_decoded_decoded, 43, 43)
node decoded_addr_decoded_107 = bits(decoded_addr_decoded_decoded, 42, 42)
node decoded_addr_decoded_108 = bits(decoded_addr_decoded_decoded, 41, 41)
node decoded_addr_decoded_109 = bits(decoded_addr_decoded_decoded, 40, 40)
node decoded_addr_decoded_110 = bits(decoded_addr_decoded_decoded, 39, 39)
node decoded_addr_decoded_111 = bits(decoded_addr_decoded_decoded, 38, 38)
node decoded_addr_decoded_112 = bits(decoded_addr_decoded_decoded, 37, 37)
node decoded_addr_decoded_113 = bits(decoded_addr_decoded_decoded, 36, 36)
node decoded_addr_decoded_114 = bits(decoded_addr_decoded_decoded, 35, 35)
node decoded_addr_decoded_115 = bits(decoded_addr_decoded_decoded, 34, 34)
node decoded_addr_decoded_116 = bits(decoded_addr_decoded_decoded, 33, 33)
node decoded_addr_decoded_117 = bits(decoded_addr_decoded_decoded, 32, 32)
node decoded_addr_decoded_118 = bits(decoded_addr_decoded_decoded, 31, 31)
node decoded_addr_decoded_119 = bits(decoded_addr_decoded_decoded, 30, 30)
node decoded_addr_decoded_120 = bits(decoded_addr_decoded_decoded, 29, 29)
node decoded_addr_decoded_121 = bits(decoded_addr_decoded_decoded, 28, 28)
node decoded_addr_decoded_122 = bits(decoded_addr_decoded_decoded, 27, 27)
node decoded_addr_decoded_123 = bits(decoded_addr_decoded_decoded, 26, 26)
node decoded_addr_decoded_124 = bits(decoded_addr_decoded_decoded, 25, 25)
node decoded_addr_decoded_125 = bits(decoded_addr_decoded_decoded, 24, 24)
node decoded_addr_decoded_126 = bits(decoded_addr_decoded_decoded, 23, 23)
node decoded_addr_decoded_127 = bits(decoded_addr_decoded_decoded, 22, 22)
node decoded_addr_decoded_128 = bits(decoded_addr_decoded_decoded, 21, 21)
node decoded_addr_decoded_129 = bits(decoded_addr_decoded_decoded, 20, 20)
node decoded_addr_decoded_130 = bits(decoded_addr_decoded_decoded, 19, 19)
node decoded_addr_decoded_131 = bits(decoded_addr_decoded_decoded, 18, 18)
node decoded_addr_decoded_132 = bits(decoded_addr_decoded_decoded, 17, 17)
node decoded_addr_decoded_133 = bits(decoded_addr_decoded_decoded, 16, 16)
node decoded_addr_decoded_134 = bits(decoded_addr_decoded_decoded, 15, 15)
node decoded_addr_decoded_135 = bits(decoded_addr_decoded_decoded, 14, 14)
node decoded_addr_decoded_136 = bits(decoded_addr_decoded_decoded, 13, 13)
node decoded_addr_decoded_137 = bits(decoded_addr_decoded_decoded, 12, 12)
node decoded_addr_decoded_138 = bits(decoded_addr_decoded_decoded, 11, 11)
node decoded_addr_decoded_139 = bits(decoded_addr_decoded_decoded, 10, 10)
node decoded_addr_decoded_140 = bits(decoded_addr_decoded_decoded, 9, 9)
node decoded_addr_decoded_141 = bits(decoded_addr_decoded_decoded, 8, 8)
node decoded_addr_decoded_142 = bits(decoded_addr_decoded_decoded, 7, 7)
node decoded_addr_decoded_143 = bits(decoded_addr_decoded_decoded, 6, 6)
node decoded_addr_decoded_144 = bits(decoded_addr_decoded_decoded, 5, 5)
node decoded_addr_decoded_145 = bits(decoded_addr_decoded_decoded, 4, 4)
node decoded_addr_decoded_146 = bits(decoded_addr_decoded_decoded, 3, 3)
node decoded_addr_decoded_147 = bits(decoded_addr_decoded_decoded, 2, 2)
node decoded_addr_decoded_148 = bits(decoded_addr_decoded_decoded, 1, 1)
node decoded_addr_decoded_149 = bits(decoded_addr_decoded_decoded, 0, 0)
node decoded_addr_97_2 = bits(decoded_addr_decoded_0, 0, 0)
node decoded_addr_55_2 = bits(decoded_addr_decoded_1, 0, 0)
node decoded_addr_10_2 = bits(decoded_addr_decoded_2, 0, 0)
node decoded_addr_118_2 = bits(decoded_addr_decoded_3, 0, 0)
node decoded_addr_94_2 = bits(decoded_addr_decoded_4, 0, 0)
node decoded_addr_100_2 = bits(decoded_addr_decoded_5, 0, 0)
node decoded_addr_72_2 = bits(decoded_addr_decoded_6, 0, 0)
node decoded_addr_108_2 = bits(decoded_addr_decoded_7, 0, 0)
node decoded_addr_76_2 = bits(decoded_addr_decoded_8, 0, 0)
node decoded_addr_129_2 = bits(decoded_addr_decoded_9, 0, 0)
node decoded_addr_132_2 = bits(decoded_addr_decoded_10, 0, 0)
node decoded_addr_136_2 = bits(decoded_addr_decoded_11, 0, 0)
node decoded_addr_29_2 = bits(decoded_addr_decoded_12, 0, 0)
node decoded_addr_131_2 = bits(decoded_addr_decoded_13, 0, 0)
node decoded_addr_49_2 = bits(decoded_addr_decoded_14, 0, 0)
node decoded_addr_89_2 = bits(decoded_addr_decoded_15, 0, 0)
node decoded_addr_57_2 = bits(decoded_addr_decoded_16, 0, 0)
node decoded_addr_36_2 = bits(decoded_addr_decoded_17, 0, 0)
node decoded_addr_68_2 = bits(decoded_addr_decoded_18, 0, 0)
node decoded_addr_99_2 = bits(decoded_addr_decoded_19, 0, 0)
node decoded_addr_130_2 = bits(decoded_addr_decoded_20, 0, 0)
node decoded_addr_103_2 = bits(decoded_addr_decoded_21, 0, 0)
node decoded_addr_121_2 = bits(decoded_addr_decoded_22, 0, 0)
node decoded_addr_146_2 = bits(decoded_addr_decoded_23, 0, 0)
node decoded_addr_17_2 = bits(decoded_addr_decoded_24, 0, 0)
node decoded_addr_27_2 = bits(decoded_addr_decoded_25, 0, 0)
node decoded_addr_83_2 = bits(decoded_addr_decoded_26, 0, 0)
node decoded_addr_52_2 = bits(decoded_addr_decoded_27, 0, 0)
node decoded_addr_144_2 = bits(decoded_addr_decoded_28, 0, 0)
node decoded_addr_70_2 = bits(decoded_addr_decoded_29, 0, 0)
node decoded_addr_111_2 = bits(decoded_addr_decoded_30, 0, 0)
node decoded_addr_82_2 = bits(decoded_addr_decoded_31, 0, 0)
node decoded_addr_31_2 = bits(decoded_addr_decoded_32, 0, 0)
node decoded_addr_0_2 = bits(decoded_addr_decoded_33, 0, 0)
node decoded_addr_59_2 = bits(decoded_addr_decoded_34, 0, 0)
node decoded_addr_138_2 = bits(decoded_addr_decoded_35, 0, 0)
node decoded_addr_126_2 = bits(decoded_addr_decoded_36, 0, 0)
node decoded_addr_74_2 = bits(decoded_addr_decoded_37, 0, 0)
node decoded_addr_116_2 = bits(decoded_addr_decoded_38, 0, 0)
node decoded_addr_90_2 = bits(decoded_addr_decoded_39, 0, 0)
node decoded_addr_113_2 = bits(decoded_addr_decoded_40, 0, 0)
node decoded_addr_1_2 = bits(decoded_addr_decoded_41, 0, 0)
node decoded_addr_16_2 = bits(decoded_addr_decoded_42, 0, 0)
node decoded_addr_78_2 = bits(decoded_addr_decoded_43, 0, 0)
node decoded_addr_39_2 = bits(decoded_addr_decoded_44, 0, 0)
node decoded_addr_51_2 = bits(decoded_addr_decoded_45, 0, 0)
node decoded_addr_109_2 = bits(decoded_addr_decoded_46, 0, 0)
node decoded_addr_91_2 = bits(decoded_addr_decoded_47, 0, 0)
node decoded_addr_81_2 = bits(decoded_addr_decoded_48, 0, 0)
node decoded_addr_67_2 = bits(decoded_addr_decoded_49, 0, 0)
node decoded_addr_105_2 = bits(decoded_addr_decoded_50, 0, 0)
node decoded_addr_122_2 = bits(decoded_addr_decoded_51, 0, 0)
node decoded_addr_24_2 = bits(decoded_addr_decoded_52, 0, 0)
node decoded_addr_124_2 = bits(decoded_addr_decoded_53, 0, 0)
node decoded_addr_26_2 = bits(decoded_addr_decoded_54, 0, 0)
node decoded_addr_128_2 = bits(decoded_addr_decoded_55, 0, 0)
node decoded_addr_7_2 = bits(decoded_addr_decoded_56, 0, 0)
node decoded_addr_62_2 = bits(decoded_addr_decoded_57, 0, 0)
node decoded_addr_77_2 = bits(decoded_addr_decoded_58, 0, 0)
node decoded_addr_46_2 = bits(decoded_addr_decoded_59, 0, 0)
node decoded_addr_112_2 = bits(decoded_addr_decoded_60, 0, 0)
node decoded_addr_60_2 = bits(decoded_addr_decoded_61, 0, 0)
node decoded_addr_92_2 = bits(decoded_addr_decoded_62, 0, 0)
node decoded_addr_148_2 = bits(decoded_addr_decoded_63, 0, 0)
node decoded_addr_14_2 = bits(decoded_addr_decoded_64, 0, 0)
node decoded_addr_21_2 = bits(decoded_addr_decoded_65, 0, 0)
node decoded_addr_33_2 = bits(decoded_addr_decoded_66, 0, 0)
node decoded_addr_19_2 = bits(decoded_addr_decoded_67, 0, 0)
node decoded_addr_133_2 = bits(decoded_addr_decoded_68, 0, 0)
node decoded_addr_149_2 = bits(decoded_addr_decoded_69, 0, 0)
node decoded_addr_50_2 = bits(decoded_addr_decoded_70, 0, 0)
node decoded_addr_75_2 = bits(decoded_addr_decoded_71, 0, 0)
node decoded_addr_102_2 = bits(decoded_addr_decoded_72, 0, 0)
node decoded_addr_84_2 = bits(decoded_addr_decoded_73, 0, 0)
node decoded_addr_45_2 = bits(decoded_addr_decoded_74, 0, 0)
node decoded_addr_64_2 = bits(decoded_addr_decoded_75, 0, 0)
node decoded_addr_120_2 = bits(decoded_addr_decoded_76, 0, 0)
node decoded_addr_30_2 = bits(decoded_addr_decoded_77, 0, 0)
node decoded_addr_5_2 = bits(decoded_addr_decoded_78, 0, 0)
node decoded_addr_32_2 = bits(decoded_addr_decoded_79, 0, 0)
node decoded_addr_143_2 = bits(decoded_addr_decoded_80, 0, 0)
node decoded_addr_117_2 = bits(decoded_addr_decoded_81, 0, 0)
node decoded_addr_63_2 = bits(decoded_addr_decoded_82, 0, 0)
node decoded_addr_107_2 = bits(decoded_addr_decoded_83, 0, 0)
node decoded_addr_88_2 = bits(decoded_addr_decoded_84, 0, 0)
node decoded_addr_114_2 = bits(decoded_addr_decoded_85, 0, 0)
node decoded_addr_73_2 = bits(decoded_addr_decoded_86, 0, 0)
node decoded_addr_53_2 = bits(decoded_addr_decoded_87, 0, 0)
node decoded_addr_147_2 = bits(decoded_addr_decoded_88, 0, 0)
node decoded_addr_41_2 = bits(decoded_addr_decoded_89, 0, 0)
node decoded_addr_56_2 = bits(decoded_addr_decoded_90, 0, 0)
node decoded_addr_37_2 = bits(decoded_addr_decoded_91, 0, 0)
node decoded_addr_79_2 = bits(decoded_addr_decoded_92, 0, 0)
node decoded_addr_96_2 = bits(decoded_addr_decoded_93, 0, 0)
node decoded_addr_4_2 = bits(decoded_addr_decoded_94, 0, 0)
node decoded_addr_101_2 = bits(decoded_addr_decoded_95, 0, 0)
node decoded_addr_119_2 = bits(decoded_addr_decoded_96, 0, 0)
node decoded_addr_22_2 = bits(decoded_addr_decoded_97, 0, 0)
node decoded_addr_139_2 = bits(decoded_addr_decoded_98, 0, 0)
node decoded_addr_11_2 = bits(decoded_addr_decoded_99, 0, 0)
node decoded_addr_134_2 = bits(decoded_addr_decoded_100, 0, 0)
node decoded_addr_12_2 = bits(decoded_addr_decoded_101, 0, 0)
node decoded_addr_65_2 = bits(decoded_addr_decoded_102, 0, 0)
node decoded_addr_86_2 = bits(decoded_addr_decoded_103, 0, 0)
node decoded_addr_47_2 = bits(decoded_addr_decoded_104, 0, 0)
node decoded_addr_106_2 = bits(decoded_addr_decoded_105, 0, 0)
node decoded_addr_58_2 = bits(decoded_addr_decoded_106, 0, 0)
node decoded_addr_87_2 = bits(decoded_addr_decoded_107, 0, 0)
node decoded_addr_142_2 = bits(decoded_addr_decoded_108, 0, 0)
node decoded_addr_13_2 = bits(decoded_addr_decoded_109, 0, 0)
node decoded_addr_35_2 = bits(decoded_addr_decoded_110, 0, 0)
node decoded_addr_2_2 = bits(decoded_addr_decoded_111, 0, 0)
node decoded_addr_66_2 = bits(decoded_addr_decoded_112, 0, 0)
node decoded_addr_42_2 = bits(decoded_addr_decoded_113, 0, 0)
node decoded_addr_61_2 = bits(decoded_addr_decoded_114, 0, 0)
node decoded_addr_48_2 = bits(decoded_addr_decoded_115, 0, 0)
node decoded_addr_44_2 = bits(decoded_addr_decoded_116, 0, 0)
node decoded_addr_15_2 = bits(decoded_addr_decoded_117, 0, 0)
node decoded_addr_145_2 = bits(decoded_addr_decoded_118, 0, 0)
node decoded_addr_93_2 = bits(decoded_addr_decoded_119, 0, 0)
node decoded_addr_6_2 = bits(decoded_addr_decoded_120, 0, 0)
node decoded_addr_28_2 = bits(decoded_addr_decoded_121, 0, 0)
node decoded_addr_25_2 = bits(decoded_addr_decoded_122, 0, 0)
node decoded_addr_137_2 = bits(decoded_addr_decoded_123, 0, 0)
node decoded_addr_123_2 = bits(decoded_addr_decoded_124, 0, 0)
node decoded_addr_23_2 = bits(decoded_addr_decoded_125, 0, 0)
node decoded_addr_69_2 = bits(decoded_addr_decoded_126, 0, 0)
node decoded_addr_141_2 = bits(decoded_addr_decoded_127, 0, 0)
node decoded_addr_9_2 = bits(decoded_addr_decoded_128, 0, 0)
node decoded_addr_104_2 = bits(decoded_addr_decoded_129, 0, 0)
node decoded_addr_8_2 = bits(decoded_addr_decoded_130, 0, 0)
node decoded_addr_125_2 = bits(decoded_addr_decoded_131, 0, 0)
node decoded_addr_85_2 = bits(decoded_addr_decoded_132, 0, 0)
node decoded_addr_54_2 = bits(decoded_addr_decoded_133, 0, 0)
node decoded_addr_20_2 = bits(decoded_addr_decoded_134, 0, 0)
node decoded_addr_135_2 = bits(decoded_addr_decoded_135, 0, 0)
node decoded_addr_115_2 = bits(decoded_addr_decoded_136, 0, 0)
node decoded_addr_43_2 = bits(decoded_addr_decoded_137, 0, 0)
node decoded_addr_71_2 = bits(decoded_addr_decoded_138, 0, 0)
node decoded_addr_110_2 = bits(decoded_addr_decoded_139, 0, 0)
node decoded_addr_140_2 = bits(decoded_addr_decoded_140, 0, 0)
node decoded_addr_34_2 = bits(decoded_addr_decoded_141, 0, 0)
node decoded_addr_40_2 = bits(decoded_addr_decoded_142, 0, 0)
node decoded_addr_80_2 = bits(decoded_addr_decoded_143, 0, 0)
node decoded_addr_98_2 = bits(decoded_addr_decoded_144, 0, 0)
node decoded_addr_18_2 = bits(decoded_addr_decoded_145, 0, 0)
node decoded_addr_3_2 = bits(decoded_addr_decoded_146, 0, 0)
node decoded_addr_38_2 = bits(decoded_addr_decoded_147, 0, 0)
node decoded_addr_127_2 = bits(decoded_addr_decoded_148, 0, 0)
node decoded_addr_95_2 = bits(decoded_addr_decoded_149, 0, 0)
node _wdata_T = bits(io.rw.cmd, 1, 1)
node _wdata_T_1 = mux(_wdata_T, io.rw.rdata, UInt<1>(0h0))
node _wdata_T_2 = or(_wdata_T_1, io.rw.wdata)
node _wdata_T_3 = bits(io.rw.cmd, 1, 0)
node _wdata_T_4 = andr(_wdata_T_3)
node _wdata_T_5 = mux(_wdata_T_4, io.rw.wdata, UInt<1>(0h0))
node _wdata_T_6 = not(_wdata_T_5)
node wdata = and(_wdata_T_2, _wdata_T_6)
node system_insn = eq(io.rw.cmd, UInt<3>(0h4))
node _insn_T = shl(io.rw.addr, 20)
node insn = or(UInt<7>(0h73), _insn_T)
wire decoded_plaInput : UInt<32>
node decoded_invInputs = not(decoded_plaInput)
wire decoded : UInt<9>
node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 20, 20)
node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_invInputs, 21, 21)
node decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_invInputs, 22, 22)
node decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_invInputs, 23, 23)
node decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_invInputs, 24, 24)
node decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_invInputs, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_invInputs, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_invInputs, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_invInputs, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_invInputs, 29, 29)
node decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_invInputs, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_invInputs, 31, 31)
node decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_9, decoded_andMatrixOutputs_andMatrixInput_10)
node decoded_andMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_andMatrixInput_11)
node decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_6, decoded_andMatrixOutputs_andMatrixInput_7)
node decoded_andMatrixOutputs_lo_hi = cat(decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_8)
node decoded_andMatrixOutputs_lo = cat(decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo)
node decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_3, decoded_andMatrixOutputs_andMatrixInput_4)
node decoded_andMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_andMatrixInput_5)
node decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1)
node decoded_andMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2)
node decoded_andMatrixOutputs_hi = cat(decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo)
node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo)
node decoded_andMatrixOutputs_6_2 = andr(_decoded_andMatrixOutputs_T)
node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_plaInput, 20, 20)
node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_invInputs, 21, 21)
node decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_invInputs, 22, 22)
node decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_invInputs, 23, 23)
node decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_invInputs, 24, 24)
node decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_invInputs, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_invInputs, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_invInputs, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_invInputs, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_invInputs, 29, 29)
node decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_invInputs, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_invInputs, 31, 31)
node decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_andMatrixOutputs_andMatrixInput_10_1)
node decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_11_1)
node decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_andMatrixOutputs_andMatrixInput_7_1)
node decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_8_1)
node decoded_andMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1)
node decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_andMatrixOutputs_andMatrixInput_4_1)
node decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_5_1)
node decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1)
node decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_1)
node decoded_andMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1)
node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1)
node decoded_andMatrixOutputs_4_2 = andr(_decoded_andMatrixOutputs_T_1)
node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_invInputs, 22, 22)
node decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_invInputs, 23, 23)
node decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_invInputs, 24, 24)
node decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_invInputs, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_invInputs, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_invInputs, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_plaInput, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_invInputs, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_invInputs, 31, 31)
node decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_8_2, decoded_andMatrixOutputs_andMatrixInput_9_2)
node decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_5_2, decoded_andMatrixOutputs_andMatrixInput_6_2)
node decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_7_2)
node decoded_andMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2)
node decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_andMatrixOutputs_andMatrixInput_4_2)
node decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2)
node decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_2)
node decoded_andMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2)
node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2)
node decoded_andMatrixOutputs_3_2 = andr(_decoded_andMatrixOutputs_T_2)
node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_plaInput, 22, 22)
node decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_invInputs, 23, 23)
node decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_invInputs, 24, 24)
node decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_invInputs, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_invInputs, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_invInputs, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_plaInput, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_invInputs, 29, 29)
node decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_invInputs, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_invInputs, 31, 31)
node decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_andMatrixOutputs_andMatrixInput_9_3)
node decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_andMatrixOutputs_andMatrixInput_6_3)
node decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_7_3)
node decoded_andMatrixOutputs_lo_3 = cat(decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3)
node decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_andMatrixOutputs_andMatrixInput_4_3)
node decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3)
node decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_3)
node decoded_andMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3)
node _decoded_andMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3)
node decoded_andMatrixOutputs_1_2 = andr(_decoded_andMatrixOutputs_T_3)
node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_plaInput, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_plaInput, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_invInputs, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_invInputs, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_plaInput, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_plaInput, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_plaInput, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_invInputs, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_invInputs, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_invInputs, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_plaInput, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_invInputs, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_12 = bits(decoded_invInputs, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_13 = bits(decoded_plaInput, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_14 = bits(decoded_invInputs, 29, 29)
node decoded_andMatrixOutputs_andMatrixInput_15 = bits(decoded_invInputs, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_16 = bits(decoded_invInputs, 31, 31)
node decoded_andMatrixOutputs_lo_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_15, decoded_andMatrixOutputs_andMatrixInput_16)
node decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_13, decoded_andMatrixOutputs_andMatrixInput_14)
node decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_lo_lo_lo)
node decoded_andMatrixOutputs_lo_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_11_2, decoded_andMatrixOutputs_andMatrixInput_12)
node decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_andMatrixOutputs_andMatrixInput_10_2)
node decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_lo_hi_lo)
node decoded_andMatrixOutputs_lo_4 = cat(decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4)
node decoded_andMatrixOutputs_hi_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_7_4, decoded_andMatrixOutputs_andMatrixInput_8_4)
node decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_5_4, decoded_andMatrixOutputs_andMatrixInput_6_4)
node decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_hi_lo_lo)
node decoded_andMatrixOutputs_hi_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_andMatrixOutputs_andMatrixInput_4_4)
node decoded_andMatrixOutputs_hi_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4)
node decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2_4)
node decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_hi_hi_lo)
node decoded_andMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4)
node _decoded_andMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4)
node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T_4)
node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_plaInput, 22, 22)
node decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_invInputs, 23, 23)
node decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_invInputs, 24, 24)
node decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_invInputs, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_invInputs, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_invInputs, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_plaInput, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_plaInput, 29, 29)
node decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_invInputs, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_invInputs, 31, 31)
node decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_8_5, decoded_andMatrixOutputs_andMatrixInput_9_5)
node decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_5_5, decoded_andMatrixOutputs_andMatrixInput_6_5)
node decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_7_5)
node decoded_andMatrixOutputs_lo_5 = cat(decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5)
node decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_andMatrixOutputs_andMatrixInput_4_5)
node decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5)
node decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_2_5)
node decoded_andMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5)
node _decoded_andMatrixOutputs_T_5 = cat(decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5)
node decoded_andMatrixOutputs_5_2 = andr(_decoded_andMatrixOutputs_T_5)
node decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_plaInput, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_invInputs, 31, 31)
node _decoded_andMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6)
node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T_6)
node _decoded_orMatrixOutputs_T = orr(decoded_andMatrixOutputs_0_2)
node _decoded_orMatrixOutputs_T_1 = orr(decoded_andMatrixOutputs_1_2)
node _decoded_orMatrixOutputs_T_2 = orr(decoded_andMatrixOutputs_5_2)
node _decoded_orMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_2_2)
node _decoded_orMatrixOutputs_T_4 = orr(_decoded_orMatrixOutputs_T_3)
node _decoded_orMatrixOutputs_T_5 = orr(decoded_andMatrixOutputs_4_2)
node _decoded_orMatrixOutputs_T_6 = orr(decoded_andMatrixOutputs_6_2)
node decoded_orMatrixOutputs_lo_lo = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_hi = cat(_decoded_orMatrixOutputs_T, UInt<1>(0h0))
node decoded_orMatrixOutputs_lo = cat(decoded_orMatrixOutputs_lo_hi, decoded_orMatrixOutputs_lo_lo)
node decoded_orMatrixOutputs_hi_lo = cat(_decoded_orMatrixOutputs_T_2, _decoded_orMatrixOutputs_T_1)
node decoded_orMatrixOutputs_hi_hi_hi = cat(_decoded_orMatrixOutputs_T_6, _decoded_orMatrixOutputs_T_5)
node decoded_orMatrixOutputs_hi_hi = cat(decoded_orMatrixOutputs_hi_hi_hi, _decoded_orMatrixOutputs_T_4)
node decoded_orMatrixOutputs_hi = cat(decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo)
node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo)
node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0)
node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1)
node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2)
node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3)
node _decoded_invMatrixOutputs_T_4 = bits(decoded_orMatrixOutputs, 4, 4)
node _decoded_invMatrixOutputs_T_5 = bits(decoded_orMatrixOutputs, 5, 5)
node _decoded_invMatrixOutputs_T_6 = bits(decoded_orMatrixOutputs, 6, 6)
node _decoded_invMatrixOutputs_T_7 = bits(decoded_orMatrixOutputs, 7, 7)
node _decoded_invMatrixOutputs_T_8 = bits(decoded_orMatrixOutputs, 8, 8)
node decoded_invMatrixOutputs_lo_lo = cat(_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T)
node decoded_invMatrixOutputs_lo_hi = cat(_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2)
node decoded_invMatrixOutputs_lo = cat(decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo)
node decoded_invMatrixOutputs_hi_lo = cat(_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4)
node decoded_invMatrixOutputs_hi_hi_hi = cat(_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7)
node decoded_invMatrixOutputs_hi_hi = cat(decoded_invMatrixOutputs_hi_hi_hi, _decoded_invMatrixOutputs_T_6)
node decoded_invMatrixOutputs_hi = cat(decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo)
node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo)
connect decoded, decoded_invMatrixOutputs
connect decoded_plaInput, insn
node _T_53 = bits(decoded, 8, 8)
node _T_54 = bits(decoded, 7, 7)
node _T_55 = bits(decoded, 6, 6)
node _T_56 = bits(decoded, 5, 5)
node _T_57 = bits(decoded, 4, 4)
node _T_58 = bits(decoded, 3, 3)
node _T_59 = bits(decoded, 2, 2)
node _T_60 = bits(decoded, 1, 1)
node _T_61 = bits(decoded, 0, 0)
node _T_62 = bits(_T_53, 0, 0)
node insn_call = and(system_insn, _T_62)
node _T_63 = bits(_T_54, 0, 0)
node insn_break = and(system_insn, _T_63)
node _T_64 = bits(_T_55, 0, 0)
node insn_ret = and(system_insn, _T_64)
node _T_65 = bits(_T_56, 0, 0)
node insn_cease = and(system_insn, _T_65)
node _T_66 = bits(_T_57, 0, 0)
node insn_wfi = and(system_insn, _T_66)
node _T_67 = bits(_T_58, 0, 0)
node _T_68 = and(system_insn, _T_67)
node _T_69 = bits(_T_59, 0, 0)
node _T_70 = and(system_insn, _T_69)
node _T_71 = bits(_T_60, 0, 0)
node _T_72 = and(system_insn, _T_71)
node _T_73 = bits(_T_61, 0, 0)
node _T_74 = and(system_insn, _T_73)
node addr = bits(io.decode[0].inst, 31, 20)
wire decoded_plaInput_1 : UInt<32>
node decoded_invInputs_1 = not(decoded_plaInput_1)
wire decoded_1 : UInt<9>
node decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_invInputs_1, 20, 20)
node decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_invInputs_1, 21, 21)
node decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_invInputs_1, 22, 22)
node decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_invInputs_1, 23, 23)
node decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_invInputs_1, 24, 24)
node decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_invInputs_1, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_invInputs_1, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_invInputs_1, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_invInputs_1, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_invInputs_1, 29, 29)
node decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_invInputs_1, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_invInputs_1, 31, 31)
node decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_andMatrixOutputs_andMatrixInput_10_3)
node decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_11_3)
node decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_andMatrixOutputs_andMatrixInput_7_6)
node decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_8_6)
node decoded_andMatrixOutputs_lo_6 = cat(decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6)
node decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_andMatrixOutputs_andMatrixInput_4_6)
node decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_5_6)
node decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7)
node decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_2_6)
node decoded_andMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6)
node _decoded_andMatrixOutputs_T_7 = cat(decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6)
node decoded_andMatrixOutputs_6_2_1 = andr(_decoded_andMatrixOutputs_T_7)
node decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_plaInput_1, 20, 20)
node decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_invInputs_1, 21, 21)
node decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_invInputs_1, 22, 22)
node decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_invInputs_1, 23, 23)
node decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_invInputs_1, 24, 24)
node decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_invInputs_1, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_invInputs_1, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_invInputs_1, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_invInputs_1, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_invInputs_1, 29, 29)
node decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoded_invInputs_1, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoded_invInputs_1, 31, 31)
node decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_andMatrixOutputs_andMatrixInput_10_4)
node decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_11_4)
node decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_6_7, decoded_andMatrixOutputs_andMatrixInput_7_7)
node decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_8_7)
node decoded_andMatrixOutputs_lo_7 = cat(decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7)
node decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_andMatrixOutputs_andMatrixInput_4_7)
node decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_5_7)
node decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8)
node decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_2_7)
node decoded_andMatrixOutputs_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7)
node _decoded_andMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7)
node decoded_andMatrixOutputs_4_2_1 = andr(_decoded_andMatrixOutputs_T_8)
node decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_plaInput_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_invInputs_1, 22, 22)
node decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_invInputs_1, 23, 23)
node decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_invInputs_1, 24, 24)
node decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoded_invInputs_1, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoded_invInputs_1, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoded_invInputs_1, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoded_plaInput_1, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoded_invInputs_1, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoded_invInputs_1, 31, 31)
node decoded_andMatrixOutputs_lo_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_8_8, decoded_andMatrixOutputs_andMatrixInput_9_8)
node decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_5_8, decoded_andMatrixOutputs_andMatrixInput_6_8)
node decoded_andMatrixOutputs_lo_hi_8 = cat(decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_7_8)
node decoded_andMatrixOutputs_lo_8 = cat(decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8)
node decoded_andMatrixOutputs_hi_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_andMatrixOutputs_andMatrixInput_4_8)
node decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9)
node decoded_andMatrixOutputs_hi_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_2_8)
node decoded_andMatrixOutputs_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8)
node _decoded_andMatrixOutputs_T_9 = cat(decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8)
node decoded_andMatrixOutputs_3_2_1 = andr(_decoded_andMatrixOutputs_T_9)
node decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_plaInput_1, 22, 22)
node decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_invInputs_1, 23, 23)
node decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_invInputs_1, 24, 24)
node decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_invInputs_1, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoded_invInputs_1, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoded_invInputs_1, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoded_plaInput_1, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoded_invInputs_1, 29, 29)
node decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoded_invInputs_1, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoded_invInputs_1, 31, 31)
node decoded_andMatrixOutputs_lo_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_8_9, decoded_andMatrixOutputs_andMatrixInput_9_9)
node decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_5_9, decoded_andMatrixOutputs_andMatrixInput_6_9)
node decoded_andMatrixOutputs_lo_hi_9 = cat(decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_7_9)
node decoded_andMatrixOutputs_lo_9 = cat(decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9)
node decoded_andMatrixOutputs_hi_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_andMatrixOutputs_andMatrixInput_4_9)
node decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10)
node decoded_andMatrixOutputs_hi_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_2_9)
node decoded_andMatrixOutputs_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9)
node _decoded_andMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_9)
node decoded_andMatrixOutputs_1_2_1 = andr(_decoded_andMatrixOutputs_T_10)
node decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_plaInput_1, 0, 0)
node decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_plaInput_1, 1, 1)
node decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoded_invInputs_1, 2, 2)
node decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoded_invInputs_1, 3, 3)
node decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoded_plaInput_1, 4, 4)
node decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoded_plaInput_1, 5, 5)
node decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoded_plaInput_1, 6, 6)
node decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoded_invInputs_1, 7, 7)
node decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoded_invInputs_1, 8, 8)
node decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoded_invInputs_1, 9, 9)
node decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoded_plaInput_1, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoded_invInputs_1, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_12_1 = bits(decoded_invInputs_1, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_13_1 = bits(decoded_plaInput_1, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_14_1 = bits(decoded_invInputs_1, 29, 29)
node decoded_andMatrixOutputs_andMatrixInput_15_1 = bits(decoded_invInputs_1, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_16_1 = bits(decoded_invInputs_1, 31, 31)
node decoded_andMatrixOutputs_lo_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_15_1, decoded_andMatrixOutputs_andMatrixInput_16_1)
node decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_13_1, decoded_andMatrixOutputs_andMatrixInput_14_1)
node decoded_andMatrixOutputs_lo_lo_10 = cat(decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_lo_lo_lo_1)
node decoded_andMatrixOutputs_lo_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_11_5, decoded_andMatrixOutputs_andMatrixInput_12_1)
node decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_andMatrixOutputs_andMatrixInput_10_5)
node decoded_andMatrixOutputs_lo_hi_10 = cat(decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_lo_hi_lo_1)
node decoded_andMatrixOutputs_lo_10 = cat(decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10)
node decoded_andMatrixOutputs_hi_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_7_10, decoded_andMatrixOutputs_andMatrixInput_8_10)
node decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_5_10, decoded_andMatrixOutputs_andMatrixInput_6_10)
node decoded_andMatrixOutputs_hi_lo_10 = cat(decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_hi_lo_lo_1)
node decoded_andMatrixOutputs_hi_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_andMatrixOutputs_andMatrixInput_4_10)
node decoded_andMatrixOutputs_hi_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11)
node decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_10)
node decoded_andMatrixOutputs_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_hi_hi_lo_1)
node decoded_andMatrixOutputs_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10)
node _decoded_andMatrixOutputs_T_11 = cat(decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_10)
node decoded_andMatrixOutputs_0_2_1 = andr(_decoded_andMatrixOutputs_T_11)
node decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoded_plaInput_1, 22, 22)
node decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoded_invInputs_1, 23, 23)
node decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoded_invInputs_1, 24, 24)
node decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoded_invInputs_1, 25, 25)
node decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoded_invInputs_1, 26, 26)
node decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoded_invInputs_1, 27, 27)
node decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoded_plaInput_1, 28, 28)
node decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoded_plaInput_1, 29, 29)
node decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoded_invInputs_1, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(decoded_invInputs_1, 31, 31)
node decoded_andMatrixOutputs_lo_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_8_11, decoded_andMatrixOutputs_andMatrixInput_9_11)
node decoded_andMatrixOutputs_lo_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_5_11, decoded_andMatrixOutputs_andMatrixInput_6_11)
node decoded_andMatrixOutputs_lo_hi_11 = cat(decoded_andMatrixOutputs_lo_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_7_11)
node decoded_andMatrixOutputs_lo_11 = cat(decoded_andMatrixOutputs_lo_hi_11, decoded_andMatrixOutputs_lo_lo_11)
node decoded_andMatrixOutputs_hi_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_andMatrixOutputs_andMatrixInput_4_11)
node decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_12)
node decoded_andMatrixOutputs_hi_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_2_11)
node decoded_andMatrixOutputs_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_hi_lo_11)
node _decoded_andMatrixOutputs_T_12 = cat(decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_11)
node decoded_andMatrixOutputs_5_2_1 = andr(_decoded_andMatrixOutputs_T_12)
node decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoded_plaInput_1, 30, 30)
node decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoded_invInputs_1, 31, 31)
node _decoded_andMatrixOutputs_T_13 = cat(decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_13)
node decoded_andMatrixOutputs_2_2_1 = andr(_decoded_andMatrixOutputs_T_13)
node _decoded_orMatrixOutputs_T_7 = orr(decoded_andMatrixOutputs_0_2_1)
node _decoded_orMatrixOutputs_T_8 = orr(decoded_andMatrixOutputs_1_2_1)
node _decoded_orMatrixOutputs_T_9 = orr(decoded_andMatrixOutputs_5_2_1)
node _decoded_orMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_3_2_1, decoded_andMatrixOutputs_2_2_1)
node _decoded_orMatrixOutputs_T_11 = orr(_decoded_orMatrixOutputs_T_10)
node _decoded_orMatrixOutputs_T_12 = orr(decoded_andMatrixOutputs_4_2_1)
node _decoded_orMatrixOutputs_T_13 = orr(decoded_andMatrixOutputs_6_2_1)
node decoded_orMatrixOutputs_lo_lo_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_hi_1 = cat(_decoded_orMatrixOutputs_T_7, UInt<1>(0h0))
node decoded_orMatrixOutputs_lo_1 = cat(decoded_orMatrixOutputs_lo_hi_1, decoded_orMatrixOutputs_lo_lo_1)
node decoded_orMatrixOutputs_hi_lo_1 = cat(_decoded_orMatrixOutputs_T_9, _decoded_orMatrixOutputs_T_8)
node decoded_orMatrixOutputs_hi_hi_hi_1 = cat(_decoded_orMatrixOutputs_T_13, _decoded_orMatrixOutputs_T_12)
node decoded_orMatrixOutputs_hi_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_hi_1, _decoded_orMatrixOutputs_T_11)
node decoded_orMatrixOutputs_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_1, decoded_orMatrixOutputs_hi_lo_1)
node decoded_orMatrixOutputs_1 = cat(decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1)
node _decoded_invMatrixOutputs_T_9 = bits(decoded_orMatrixOutputs_1, 0, 0)
node _decoded_invMatrixOutputs_T_10 = bits(decoded_orMatrixOutputs_1, 1, 1)
node _decoded_invMatrixOutputs_T_11 = bits(decoded_orMatrixOutputs_1, 2, 2)
node _decoded_invMatrixOutputs_T_12 = bits(decoded_orMatrixOutputs_1, 3, 3)
node _decoded_invMatrixOutputs_T_13 = bits(decoded_orMatrixOutputs_1, 4, 4)
node _decoded_invMatrixOutputs_T_14 = bits(decoded_orMatrixOutputs_1, 5, 5)
node _decoded_invMatrixOutputs_T_15 = bits(decoded_orMatrixOutputs_1, 6, 6)
node _decoded_invMatrixOutputs_T_16 = bits(decoded_orMatrixOutputs_1, 7, 7)
node _decoded_invMatrixOutputs_T_17 = bits(decoded_orMatrixOutputs_1, 8, 8)
node decoded_invMatrixOutputs_lo_lo_1 = cat(_decoded_invMatrixOutputs_T_10, _decoded_invMatrixOutputs_T_9)
node decoded_invMatrixOutputs_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_12, _decoded_invMatrixOutputs_T_11)
node decoded_invMatrixOutputs_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1)
node decoded_invMatrixOutputs_hi_lo_1 = cat(_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13)
node decoded_invMatrixOutputs_hi_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16)
node decoded_invMatrixOutputs_hi_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_hi_1, _decoded_invMatrixOutputs_T_15)
node decoded_invMatrixOutputs_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1)
node decoded_invMatrixOutputs_1 = cat(decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1)
connect decoded_1, decoded_invMatrixOutputs_1
connect decoded_plaInput_1, io.decode[0].inst
node _T_75 = bits(decoded_1, 8, 8)
node _T_76 = bits(decoded_1, 7, 7)
node _T_77 = bits(decoded_1, 6, 6)
node _T_78 = bits(decoded_1, 5, 5)
node _T_79 = bits(decoded_1, 4, 4)
node _T_80 = bits(decoded_1, 3, 3)
node _T_81 = bits(decoded_1, 2, 2)
node _T_82 = bits(decoded_1, 1, 1)
node _T_83 = bits(decoded_1, 0, 0)
node _T_84 = bits(_T_75, 0, 0)
node is_break = bits(_T_76, 0, 0)
node is_ret = bits(_T_77, 0, 0)
node _T_85 = bits(_T_78, 0, 0)
node is_wfi = bits(_T_79, 0, 0)
node is_sfence = bits(_T_80, 0, 0)
node is_hfence_vvma = bits(_T_81, 0, 0)
node is_hfence_gvma = bits(_T_82, 0, 0)
node is_hlsv = bits(_T_83, 0, 0)
node _is_counter_T = geq(addr, UInt<12>(0hc00))
node _is_counter_T_1 = lt(addr, UInt<12>(0hc20))
node _is_counter_T_2 = and(_is_counter_T, _is_counter_T_1)
node _is_counter_T_3 = geq(addr, UInt<12>(0hc80))
node _is_counter_T_4 = lt(addr, UInt<12>(0hca0))
node _is_counter_T_5 = and(_is_counter_T_3, _is_counter_T_4)
node is_counter = or(_is_counter_T_2, _is_counter_T_5)
node _allow_wfi_T = gt(reg_mstatus.prv, UInt<1>(0h1))
node _allow_wfi_T_1 = or(UInt<1>(0h0), _allow_wfi_T)
node _allow_wfi_T_2 = eq(reg_mstatus.tw, UInt<1>(0h0))
node _allow_wfi_T_3 = eq(reg_mstatus.v, UInt<1>(0h0))
node _allow_wfi_T_4 = eq(reg_hstatus.vtw, UInt<1>(0h0))
node _allow_wfi_T_5 = or(_allow_wfi_T_3, _allow_wfi_T_4)
node _allow_wfi_T_6 = and(_allow_wfi_T_2, _allow_wfi_T_5)
node allow_wfi = or(_allow_wfi_T_1, _allow_wfi_T_6)
node _allow_sfence_vma_T = gt(reg_mstatus.prv, UInt<1>(0h1))
node _allow_sfence_vma_T_1 = or(UInt<1>(0h0), _allow_sfence_vma_T)
node _allow_sfence_vma_T_2 = mux(reg_mstatus.v, reg_hstatus.vtvm, reg_mstatus.tvm)
node _allow_sfence_vma_T_3 = eq(_allow_sfence_vma_T_2, UInt<1>(0h0))
node allow_sfence_vma = or(_allow_sfence_vma_T_1, _allow_sfence_vma_T_3)
node _allow_hfence_vvma_T = eq(reg_mstatus.v, UInt<1>(0h0))
node _allow_hfence_vvma_T_1 = geq(reg_mstatus.prv, UInt<1>(0h1))
node _allow_hfence_vvma_T_2 = and(_allow_hfence_vvma_T, _allow_hfence_vvma_T_1)
node allow_hfence_vvma = or(UInt<1>(0h1), _allow_hfence_vvma_T_2)
node _allow_hlsv_T = eq(reg_mstatus.v, UInt<1>(0h0))
node _allow_hlsv_T_1 = geq(reg_mstatus.prv, UInt<1>(0h1))
node _allow_hlsv_T_2 = or(_allow_hlsv_T_1, reg_hstatus.hu)
node _allow_hlsv_T_3 = and(_allow_hlsv_T, _allow_hlsv_T_2)
node allow_hlsv = or(UInt<1>(0h1), _allow_hlsv_T_3)
node _allow_sret_T = gt(reg_mstatus.prv, UInt<1>(0h1))
node _allow_sret_T_1 = or(UInt<1>(0h0), _allow_sret_T)
node _allow_sret_T_2 = mux(reg_mstatus.v, reg_hstatus.vtsr, reg_mstatus.tsr)
node _allow_sret_T_3 = eq(_allow_sret_T_2, UInt<1>(0h0))
node allow_sret = or(_allow_sret_T_1, _allow_sret_T_3)
node counter_addr = bits(addr, 4, 0)
node _allow_counter_T = gt(reg_mstatus.prv, UInt<1>(0h1))
node _allow_counter_T_1 = dshr(read_mcounteren, counter_addr)
node _allow_counter_T_2 = bits(_allow_counter_T_1, 0, 0)
node _allow_counter_T_3 = or(_allow_counter_T, _allow_counter_T_2)
node _allow_counter_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _allow_counter_T_5 = geq(reg_mstatus.prv, UInt<1>(0h1))
node _allow_counter_T_6 = or(_allow_counter_T_4, _allow_counter_T_5)
node _allow_counter_T_7 = dshr(read_scounteren, counter_addr)
node _allow_counter_T_8 = bits(_allow_counter_T_7, 0, 0)
node _allow_counter_T_9 = or(_allow_counter_T_6, _allow_counter_T_8)
node _allow_counter_T_10 = and(_allow_counter_T_3, _allow_counter_T_9)
node _allow_counter_T_11 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _allow_counter_T_12 = eq(reg_mstatus.v, UInt<1>(0h0))
node _allow_counter_T_13 = or(_allow_counter_T_11, _allow_counter_T_12)
node _allow_counter_T_14 = dshr(read_hcounteren, counter_addr)
node _allow_counter_T_15 = bits(_allow_counter_T_14, 0, 0)
node _allow_counter_T_16 = or(_allow_counter_T_13, _allow_counter_T_15)
node allow_counter = and(_allow_counter_T_10, _allow_counter_T_16)
node _io_decode_0_fp_illegal_T = eq(io.status.fs, UInt<1>(0h0))
node _io_decode_0_fp_illegal_T_1 = eq(reg_vsstatus.fs, UInt<1>(0h0))
node _io_decode_0_fp_illegal_T_2 = and(reg_mstatus.v, _io_decode_0_fp_illegal_T_1)
node _io_decode_0_fp_illegal_T_3 = or(_io_decode_0_fp_illegal_T, _io_decode_0_fp_illegal_T_2)
node _io_decode_0_fp_illegal_T_4 = bits(reg_misa, 5, 5)
node _io_decode_0_fp_illegal_T_5 = eq(_io_decode_0_fp_illegal_T_4, UInt<1>(0h0))
node _io_decode_0_fp_illegal_T_6 = or(_io_decode_0_fp_illegal_T_3, _io_decode_0_fp_illegal_T_5)
connect io.decode[0].fp_illegal, _io_decode_0_fp_illegal_T_6
node _io_decode_0_vector_illegal_T = eq(io.status.vs, UInt<1>(0h0))
node _io_decode_0_vector_illegal_T_1 = eq(reg_vsstatus.vs, UInt<1>(0h0))
node _io_decode_0_vector_illegal_T_2 = and(reg_mstatus.v, _io_decode_0_vector_illegal_T_1)
node _io_decode_0_vector_illegal_T_3 = or(_io_decode_0_vector_illegal_T, _io_decode_0_vector_illegal_T_2)
node _io_decode_0_vector_illegal_T_4 = bits(reg_misa, 21, 21)
node _io_decode_0_vector_illegal_T_5 = eq(_io_decode_0_vector_illegal_T_4, UInt<1>(0h0))
node _io_decode_0_vector_illegal_T_6 = or(_io_decode_0_vector_illegal_T_3, _io_decode_0_vector_illegal_T_5)
connect io.decode[0].vector_illegal, _io_decode_0_vector_illegal_T_6
wire io_decode_0_fp_csr_plaInput : UInt<12>
node io_decode_0_fp_csr_invInputs = not(io_decode_0_fp_csr_plaInput)
wire io_decode_0_fp_csr_plaOutput : UInt<1>
node io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0 = bits(io_decode_0_fp_csr_invInputs, 8, 8)
node io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1 = bits(io_decode_0_fp_csr_invInputs, 9, 9)
node io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2 = bits(io_decode_0_fp_csr_invInputs, 10, 10)
node io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3 = bits(io_decode_0_fp_csr_invInputs, 11, 11)
node io_decode_0_fp_csr_andMatrixOutputs_lo = cat(io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3)
node io_decode_0_fp_csr_andMatrixOutputs_hi = cat(io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1)
node _io_decode_0_fp_csr_andMatrixOutputs_T = cat(io_decode_0_fp_csr_andMatrixOutputs_hi, io_decode_0_fp_csr_andMatrixOutputs_lo)
node io_decode_0_fp_csr_andMatrixOutputs_0_2 = andr(_io_decode_0_fp_csr_andMatrixOutputs_T)
node io_decode_0_fp_csr_orMatrixOutputs = orr(io_decode_0_fp_csr_andMatrixOutputs_0_2)
node io_decode_0_fp_csr_invMatrixOutputs = bits(io_decode_0_fp_csr_orMatrixOutputs, 0, 0)
connect io_decode_0_fp_csr_plaOutput, io_decode_0_fp_csr_invMatrixOutputs
connect io_decode_0_fp_csr_plaInput, addr
node _io_decode_0_fp_csr_T = bits(io_decode_0_fp_csr_plaOutput, 0, 0)
connect io.decode[0].fp_csr, _io_decode_0_fp_csr_T
wire io_decode_0_vector_csr_plaInput : UInt<12>
node io_decode_0_vector_csr_invInputs = not(io_decode_0_vector_csr_plaInput)
wire io_decode_0_vector_csr_plaOutput : UInt<1>
connect io_decode_0_vector_csr_plaOutput, UInt<1>(0h0)
connect io_decode_0_vector_csr_plaInput, addr
node _io_decode_0_vector_csr_T = bits(io_decode_0_vector_csr_plaOutput, 0, 0)
connect io.decode[0].vector_csr, _io_decode_0_vector_csr_T
node _io_decode_0_rocc_illegal_T = eq(io.status.xs, UInt<1>(0h0))
node _io_decode_0_rocc_illegal_T_1 = eq(reg_vsstatus.xs, UInt<1>(0h0))
node _io_decode_0_rocc_illegal_T_2 = and(reg_mstatus.v, _io_decode_0_rocc_illegal_T_1)
node _io_decode_0_rocc_illegal_T_3 = or(_io_decode_0_rocc_illegal_T, _io_decode_0_rocc_illegal_T_2)
node _io_decode_0_rocc_illegal_T_4 = bits(reg_misa, 23, 23)
node _io_decode_0_rocc_illegal_T_5 = eq(_io_decode_0_rocc_illegal_T_4, UInt<1>(0h0))
node _io_decode_0_rocc_illegal_T_6 = or(_io_decode_0_rocc_illegal_T_3, _io_decode_0_rocc_illegal_T_5)
connect io.decode[0].rocc_illegal, _io_decode_0_rocc_illegal_T_6
node _csr_addr_legal_T = bits(addr, 9, 8)
node _csr_addr_legal_T_1 = geq(reg_mstatus.prv, _csr_addr_legal_T)
node _csr_addr_legal_T_2 = eq(reg_mstatus.v, UInt<1>(0h0))
node _csr_addr_legal_T_3 = and(UInt<1>(0h0), _csr_addr_legal_T_2)
node _csr_addr_legal_T_4 = eq(reg_mstatus.prv, UInt<1>(0h1))
node _csr_addr_legal_T_5 = and(_csr_addr_legal_T_3, _csr_addr_legal_T_4)
node _csr_addr_legal_T_6 = bits(addr, 9, 8)
node _csr_addr_legal_T_7 = eq(_csr_addr_legal_T_6, UInt<2>(0h2))
node _csr_addr_legal_T_8 = and(_csr_addr_legal_T_5, _csr_addr_legal_T_7)
node csr_addr_legal = or(_csr_addr_legal_T_1, _csr_addr_legal_T_8)
node _csr_exists_T = eq(addr, UInt<11>(0h7a0))
node _csr_exists_T_1 = eq(addr, UInt<11>(0h7a1))
node _csr_exists_T_2 = eq(addr, UInt<11>(0h7a2))
node _csr_exists_T_3 = eq(addr, UInt<11>(0h7a3))
node _csr_exists_T_4 = eq(addr, UInt<10>(0h301))
node _csr_exists_T_5 = eq(addr, UInt<10>(0h300))
node _csr_exists_T_6 = eq(addr, UInt<10>(0h305))
node _csr_exists_T_7 = eq(addr, UInt<10>(0h344))
node _csr_exists_T_8 = eq(addr, UInt<10>(0h304))
node _csr_exists_T_9 = eq(addr, UInt<10>(0h340))
node _csr_exists_T_10 = eq(addr, UInt<10>(0h341))
node _csr_exists_T_11 = eq(addr, UInt<10>(0h343))
node _csr_exists_T_12 = eq(addr, UInt<10>(0h342))
node _csr_exists_T_13 = eq(addr, UInt<12>(0hf14))
node _csr_exists_T_14 = eq(addr, UInt<11>(0h7b0))
node _csr_exists_T_15 = eq(addr, UInt<11>(0h7b1))
node _csr_exists_T_16 = eq(addr, UInt<11>(0h7b2))
node _csr_exists_T_17 = eq(addr, UInt<1>(0h1))
node _csr_exists_T_18 = eq(addr, UInt<2>(0h2))
node _csr_exists_T_19 = eq(addr, UInt<2>(0h3))
node _csr_exists_T_20 = eq(addr, UInt<10>(0h320))
node _csr_exists_T_21 = eq(addr, UInt<12>(0hb00))
node _csr_exists_T_22 = eq(addr, UInt<12>(0hb02))
node _csr_exists_T_23 = eq(addr, UInt<10>(0h323))
node _csr_exists_T_24 = eq(addr, UInt<12>(0hb03))
node _csr_exists_T_25 = eq(addr, UInt<12>(0hc03))
node _csr_exists_T_26 = eq(addr, UInt<10>(0h324))
node _csr_exists_T_27 = eq(addr, UInt<12>(0hb04))
node _csr_exists_T_28 = eq(addr, UInt<12>(0hc04))
node _csr_exists_T_29 = eq(addr, UInt<10>(0h325))
node _csr_exists_T_30 = eq(addr, UInt<12>(0hb05))
node _csr_exists_T_31 = eq(addr, UInt<12>(0hc05))
node _csr_exists_T_32 = eq(addr, UInt<10>(0h326))
node _csr_exists_T_33 = eq(addr, UInt<12>(0hb06))
node _csr_exists_T_34 = eq(addr, UInt<12>(0hc06))
node _csr_exists_T_35 = eq(addr, UInt<10>(0h327))
node _csr_exists_T_36 = eq(addr, UInt<12>(0hb07))
node _csr_exists_T_37 = eq(addr, UInt<12>(0hc07))
node _csr_exists_T_38 = eq(addr, UInt<10>(0h328))
node _csr_exists_T_39 = eq(addr, UInt<12>(0hb08))
node _csr_exists_T_40 = eq(addr, UInt<12>(0hc08))
node _csr_exists_T_41 = eq(addr, UInt<10>(0h329))
node _csr_exists_T_42 = eq(addr, UInt<12>(0hb09))
node _csr_exists_T_43 = eq(addr, UInt<12>(0hc09))
node _csr_exists_T_44 = eq(addr, UInt<10>(0h32a))
node _csr_exists_T_45 = eq(addr, UInt<12>(0hb0a))
node _csr_exists_T_46 = eq(addr, UInt<12>(0hc0a))
node _csr_exists_T_47 = eq(addr, UInt<10>(0h32b))
node _csr_exists_T_48 = eq(addr, UInt<12>(0hb0b))
node _csr_exists_T_49 = eq(addr, UInt<12>(0hc0b))
node _csr_exists_T_50 = eq(addr, UInt<10>(0h32c))
node _csr_exists_T_51 = eq(addr, UInt<12>(0hb0c))
node _csr_exists_T_52 = eq(addr, UInt<12>(0hc0c))
node _csr_exists_T_53 = eq(addr, UInt<10>(0h32d))
node _csr_exists_T_54 = eq(addr, UInt<12>(0hb0d))
node _csr_exists_T_55 = eq(addr, UInt<12>(0hc0d))
node _csr_exists_T_56 = eq(addr, UInt<10>(0h32e))
node _csr_exists_T_57 = eq(addr, UInt<12>(0hb0e))
node _csr_exists_T_58 = eq(addr, UInt<12>(0hc0e))
node _csr_exists_T_59 = eq(addr, UInt<10>(0h32f))
node _csr_exists_T_60 = eq(addr, UInt<12>(0hb0f))
node _csr_exists_T_61 = eq(addr, UInt<12>(0hc0f))
node _csr_exists_T_62 = eq(addr, UInt<10>(0h330))
node _csr_exists_T_63 = eq(addr, UInt<12>(0hb10))
node _csr_exists_T_64 = eq(addr, UInt<12>(0hc10))
node _csr_exists_T_65 = eq(addr, UInt<10>(0h331))
node _csr_exists_T_66 = eq(addr, UInt<12>(0hb11))
node _csr_exists_T_67 = eq(addr, UInt<12>(0hc11))
node _csr_exists_T_68 = eq(addr, UInt<10>(0h332))
node _csr_exists_T_69 = eq(addr, UInt<12>(0hb12))
node _csr_exists_T_70 = eq(addr, UInt<12>(0hc12))
node _csr_exists_T_71 = eq(addr, UInt<10>(0h333))
node _csr_exists_T_72 = eq(addr, UInt<12>(0hb13))
node _csr_exists_T_73 = eq(addr, UInt<12>(0hc13))
node _csr_exists_T_74 = eq(addr, UInt<10>(0h334))
node _csr_exists_T_75 = eq(addr, UInt<12>(0hb14))
node _csr_exists_T_76 = eq(addr, UInt<12>(0hc14))
node _csr_exists_T_77 = eq(addr, UInt<10>(0h335))
node _csr_exists_T_78 = eq(addr, UInt<12>(0hb15))
node _csr_exists_T_79 = eq(addr, UInt<12>(0hc15))
node _csr_exists_T_80 = eq(addr, UInt<10>(0h336))
node _csr_exists_T_81 = eq(addr, UInt<12>(0hb16))
node _csr_exists_T_82 = eq(addr, UInt<12>(0hc16))
node _csr_exists_T_83 = eq(addr, UInt<10>(0h337))
node _csr_exists_T_84 = eq(addr, UInt<12>(0hb17))
node _csr_exists_T_85 = eq(addr, UInt<12>(0hc17))
node _csr_exists_T_86 = eq(addr, UInt<10>(0h338))
node _csr_exists_T_87 = eq(addr, UInt<12>(0hb18))
node _csr_exists_T_88 = eq(addr, UInt<12>(0hc18))
node _csr_exists_T_89 = eq(addr, UInt<10>(0h339))
node _csr_exists_T_90 = eq(addr, UInt<12>(0hb19))
node _csr_exists_T_91 = eq(addr, UInt<12>(0hc19))
node _csr_exists_T_92 = eq(addr, UInt<10>(0h33a))
node _csr_exists_T_93 = eq(addr, UInt<12>(0hb1a))
node _csr_exists_T_94 = eq(addr, UInt<12>(0hc1a))
node _csr_exists_T_95 = eq(addr, UInt<10>(0h33b))
node _csr_exists_T_96 = eq(addr, UInt<12>(0hb1b))
node _csr_exists_T_97 = eq(addr, UInt<12>(0hc1b))
node _csr_exists_T_98 = eq(addr, UInt<10>(0h33c))
node _csr_exists_T_99 = eq(addr, UInt<12>(0hb1c))
node _csr_exists_T_100 = eq(addr, UInt<12>(0hc1c))
node _csr_exists_T_101 = eq(addr, UInt<10>(0h33d))
node _csr_exists_T_102 = eq(addr, UInt<12>(0hb1d))
node _csr_exists_T_103 = eq(addr, UInt<12>(0hc1d))
node _csr_exists_T_104 = eq(addr, UInt<10>(0h33e))
node _csr_exists_T_105 = eq(addr, UInt<12>(0hb1e))
node _csr_exists_T_106 = eq(addr, UInt<12>(0hc1e))
node _csr_exists_T_107 = eq(addr, UInt<10>(0h33f))
node _csr_exists_T_108 = eq(addr, UInt<12>(0hb1f))
node _csr_exists_T_109 = eq(addr, UInt<12>(0hc1f))
node _csr_exists_T_110 = eq(addr, UInt<10>(0h306))
node _csr_exists_T_111 = eq(addr, UInt<12>(0hc00))
node _csr_exists_T_112 = eq(addr, UInt<12>(0hc02))
node _csr_exists_T_113 = eq(addr, UInt<10>(0h30a))
node _csr_exists_T_114 = eq(addr, UInt<9>(0h100))
node _csr_exists_T_115 = eq(addr, UInt<9>(0h144))
node _csr_exists_T_116 = eq(addr, UInt<9>(0h104))
node _csr_exists_T_117 = eq(addr, UInt<9>(0h140))
node _csr_exists_T_118 = eq(addr, UInt<9>(0h142))
node _csr_exists_T_119 = eq(addr, UInt<9>(0h143))
node _csr_exists_T_120 = eq(addr, UInt<9>(0h180))
node _csr_exists_T_121 = eq(addr, UInt<9>(0h141))
node _csr_exists_T_122 = eq(addr, UInt<9>(0h105))
node _csr_exists_T_123 = eq(addr, UInt<9>(0h106))
node _csr_exists_T_124 = eq(addr, UInt<10>(0h303))
node _csr_exists_T_125 = eq(addr, UInt<10>(0h302))
node _csr_exists_T_126 = eq(addr, UInt<9>(0h10a))
node _csr_exists_T_127 = eq(addr, UInt<10>(0h3a0))
node _csr_exists_T_128 = eq(addr, UInt<10>(0h3a2))
node _csr_exists_T_129 = eq(addr, UInt<10>(0h3b0))
node _csr_exists_T_130 = eq(addr, UInt<10>(0h3b1))
node _csr_exists_T_131 = eq(addr, UInt<10>(0h3b2))
node _csr_exists_T_132 = eq(addr, UInt<10>(0h3b3))
node _csr_exists_T_133 = eq(addr, UInt<10>(0h3b4))
node _csr_exists_T_134 = eq(addr, UInt<10>(0h3b5))
node _csr_exists_T_135 = eq(addr, UInt<10>(0h3b6))
node _csr_exists_T_136 = eq(addr, UInt<10>(0h3b7))
node _csr_exists_T_137 = eq(addr, UInt<10>(0h3b8))
node _csr_exists_T_138 = eq(addr, UInt<10>(0h3b9))
node _csr_exists_T_139 = eq(addr, UInt<10>(0h3ba))
node _csr_exists_T_140 = eq(addr, UInt<10>(0h3bb))
node _csr_exists_T_141 = eq(addr, UInt<10>(0h3bc))
node _csr_exists_T_142 = eq(addr, UInt<10>(0h3bd))
node _csr_exists_T_143 = eq(addr, UInt<10>(0h3be))
node _csr_exists_T_144 = eq(addr, UInt<10>(0h3bf))
node _csr_exists_T_145 = eq(addr, UInt<11>(0h7c1))
node _csr_exists_T_146 = eq(addr, UInt<12>(0hf12))
node _csr_exists_T_147 = eq(addr, UInt<12>(0hf11))
node _csr_exists_T_148 = eq(addr, UInt<12>(0hf13))
node _csr_exists_T_149 = eq(addr, UInt<12>(0hf15))
node _csr_exists_T_150 = or(_csr_exists_T, _csr_exists_T_1)
node _csr_exists_T_151 = or(_csr_exists_T_150, _csr_exists_T_2)
node _csr_exists_T_152 = or(_csr_exists_T_151, _csr_exists_T_3)
node _csr_exists_T_153 = or(_csr_exists_T_152, _csr_exists_T_4)
node _csr_exists_T_154 = or(_csr_exists_T_153, _csr_exists_T_5)
node _csr_exists_T_155 = or(_csr_exists_T_154, _csr_exists_T_6)
node _csr_exists_T_156 = or(_csr_exists_T_155, _csr_exists_T_7)
node _csr_exists_T_157 = or(_csr_exists_T_156, _csr_exists_T_8)
node _csr_exists_T_158 = or(_csr_exists_T_157, _csr_exists_T_9)
node _csr_exists_T_159 = or(_csr_exists_T_158, _csr_exists_T_10)
node _csr_exists_T_160 = or(_csr_exists_T_159, _csr_exists_T_11)
node _csr_exists_T_161 = or(_csr_exists_T_160, _csr_exists_T_12)
node _csr_exists_T_162 = or(_csr_exists_T_161, _csr_exists_T_13)
node _csr_exists_T_163 = or(_csr_exists_T_162, _csr_exists_T_14)
node _csr_exists_T_164 = or(_csr_exists_T_163, _csr_exists_T_15)
node _csr_exists_T_165 = or(_csr_exists_T_164, _csr_exists_T_16)
node _csr_exists_T_166 = or(_csr_exists_T_165, _csr_exists_T_17)
node _csr_exists_T_167 = or(_csr_exists_T_166, _csr_exists_T_18)
node _csr_exists_T_168 = or(_csr_exists_T_167, _csr_exists_T_19)
node _csr_exists_T_169 = or(_csr_exists_T_168, _csr_exists_T_20)
node _csr_exists_T_170 = or(_csr_exists_T_169, _csr_exists_T_21)
node _csr_exists_T_171 = or(_csr_exists_T_170, _csr_exists_T_22)
node _csr_exists_T_172 = or(_csr_exists_T_171, _csr_exists_T_23)
node _csr_exists_T_173 = or(_csr_exists_T_172, _csr_exists_T_24)
node _csr_exists_T_174 = or(_csr_exists_T_173, _csr_exists_T_25)
node _csr_exists_T_175 = or(_csr_exists_T_174, _csr_exists_T_26)
node _csr_exists_T_176 = or(_csr_exists_T_175, _csr_exists_T_27)
node _csr_exists_T_177 = or(_csr_exists_T_176, _csr_exists_T_28)
node _csr_exists_T_178 = or(_csr_exists_T_177, _csr_exists_T_29)
node _csr_exists_T_179 = or(_csr_exists_T_178, _csr_exists_T_30)
node _csr_exists_T_180 = or(_csr_exists_T_179, _csr_exists_T_31)
node _csr_exists_T_181 = or(_csr_exists_T_180, _csr_exists_T_32)
node _csr_exists_T_182 = or(_csr_exists_T_181, _csr_exists_T_33)
node _csr_exists_T_183 = or(_csr_exists_T_182, _csr_exists_T_34)
node _csr_exists_T_184 = or(_csr_exists_T_183, _csr_exists_T_35)
node _csr_exists_T_185 = or(_csr_exists_T_184, _csr_exists_T_36)
node _csr_exists_T_186 = or(_csr_exists_T_185, _csr_exists_T_37)
node _csr_exists_T_187 = or(_csr_exists_T_186, _csr_exists_T_38)
node _csr_exists_T_188 = or(_csr_exists_T_187, _csr_exists_T_39)
node _csr_exists_T_189 = or(_csr_exists_T_188, _csr_exists_T_40)
node _csr_exists_T_190 = or(_csr_exists_T_189, _csr_exists_T_41)
node _csr_exists_T_191 = or(_csr_exists_T_190, _csr_exists_T_42)
node _csr_exists_T_192 = or(_csr_exists_T_191, _csr_exists_T_43)
node _csr_exists_T_193 = or(_csr_exists_T_192, _csr_exists_T_44)
node _csr_exists_T_194 = or(_csr_exists_T_193, _csr_exists_T_45)
node _csr_exists_T_195 = or(_csr_exists_T_194, _csr_exists_T_46)
node _csr_exists_T_196 = or(_csr_exists_T_195, _csr_exists_T_47)
node _csr_exists_T_197 = or(_csr_exists_T_196, _csr_exists_T_48)
node _csr_exists_T_198 = or(_csr_exists_T_197, _csr_exists_T_49)
node _csr_exists_T_199 = or(_csr_exists_T_198, _csr_exists_T_50)
node _csr_exists_T_200 = or(_csr_exists_T_199, _csr_exists_T_51)
node _csr_exists_T_201 = or(_csr_exists_T_200, _csr_exists_T_52)
node _csr_exists_T_202 = or(_csr_exists_T_201, _csr_exists_T_53)
node _csr_exists_T_203 = or(_csr_exists_T_202, _csr_exists_T_54)
node _csr_exists_T_204 = or(_csr_exists_T_203, _csr_exists_T_55)
node _csr_exists_T_205 = or(_csr_exists_T_204, _csr_exists_T_56)
node _csr_exists_T_206 = or(_csr_exists_T_205, _csr_exists_T_57)
node _csr_exists_T_207 = or(_csr_exists_T_206, _csr_exists_T_58)
node _csr_exists_T_208 = or(_csr_exists_T_207, _csr_exists_T_59)
node _csr_exists_T_209 = or(_csr_exists_T_208, _csr_exists_T_60)
node _csr_exists_T_210 = or(_csr_exists_T_209, _csr_exists_T_61)
node _csr_exists_T_211 = or(_csr_exists_T_210, _csr_exists_T_62)
node _csr_exists_T_212 = or(_csr_exists_T_211, _csr_exists_T_63)
node _csr_exists_T_213 = or(_csr_exists_T_212, _csr_exists_T_64)
node _csr_exists_T_214 = or(_csr_exists_T_213, _csr_exists_T_65)
node _csr_exists_T_215 = or(_csr_exists_T_214, _csr_exists_T_66)
node _csr_exists_T_216 = or(_csr_exists_T_215, _csr_exists_T_67)
node _csr_exists_T_217 = or(_csr_exists_T_216, _csr_exists_T_68)
node _csr_exists_T_218 = or(_csr_exists_T_217, _csr_exists_T_69)
node _csr_exists_T_219 = or(_csr_exists_T_218, _csr_exists_T_70)
node _csr_exists_T_220 = or(_csr_exists_T_219, _csr_exists_T_71)
node _csr_exists_T_221 = or(_csr_exists_T_220, _csr_exists_T_72)
node _csr_exists_T_222 = or(_csr_exists_T_221, _csr_exists_T_73)
node _csr_exists_T_223 = or(_csr_exists_T_222, _csr_exists_T_74)
node _csr_exists_T_224 = or(_csr_exists_T_223, _csr_exists_T_75)
node _csr_exists_T_225 = or(_csr_exists_T_224, _csr_exists_T_76)
node _csr_exists_T_226 = or(_csr_exists_T_225, _csr_exists_T_77)
node _csr_exists_T_227 = or(_csr_exists_T_226, _csr_exists_T_78)
node _csr_exists_T_228 = or(_csr_exists_T_227, _csr_exists_T_79)
node _csr_exists_T_229 = or(_csr_exists_T_228, _csr_exists_T_80)
node _csr_exists_T_230 = or(_csr_exists_T_229, _csr_exists_T_81)
node _csr_exists_T_231 = or(_csr_exists_T_230, _csr_exists_T_82)
node _csr_exists_T_232 = or(_csr_exists_T_231, _csr_exists_T_83)
node _csr_exists_T_233 = or(_csr_exists_T_232, _csr_exists_T_84)
node _csr_exists_T_234 = or(_csr_exists_T_233, _csr_exists_T_85)
node _csr_exists_T_235 = or(_csr_exists_T_234, _csr_exists_T_86)
node _csr_exists_T_236 = or(_csr_exists_T_235, _csr_exists_T_87)
node _csr_exists_T_237 = or(_csr_exists_T_236, _csr_exists_T_88)
node _csr_exists_T_238 = or(_csr_exists_T_237, _csr_exists_T_89)
node _csr_exists_T_239 = or(_csr_exists_T_238, _csr_exists_T_90)
node _csr_exists_T_240 = or(_csr_exists_T_239, _csr_exists_T_91)
node _csr_exists_T_241 = or(_csr_exists_T_240, _csr_exists_T_92)
node _csr_exists_T_242 = or(_csr_exists_T_241, _csr_exists_T_93)
node _csr_exists_T_243 = or(_csr_exists_T_242, _csr_exists_T_94)
node _csr_exists_T_244 = or(_csr_exists_T_243, _csr_exists_T_95)
node _csr_exists_T_245 = or(_csr_exists_T_244, _csr_exists_T_96)
node _csr_exists_T_246 = or(_csr_exists_T_245, _csr_exists_T_97)
node _csr_exists_T_247 = or(_csr_exists_T_246, _csr_exists_T_98)
node _csr_exists_T_248 = or(_csr_exists_T_247, _csr_exists_T_99)
node _csr_exists_T_249 = or(_csr_exists_T_248, _csr_exists_T_100)
node _csr_exists_T_250 = or(_csr_exists_T_249, _csr_exists_T_101)
node _csr_exists_T_251 = or(_csr_exists_T_250, _csr_exists_T_102)
node _csr_exists_T_252 = or(_csr_exists_T_251, _csr_exists_T_103)
node _csr_exists_T_253 = or(_csr_exists_T_252, _csr_exists_T_104)
node _csr_exists_T_254 = or(_csr_exists_T_253, _csr_exists_T_105)
node _csr_exists_T_255 = or(_csr_exists_T_254, _csr_exists_T_106)
node _csr_exists_T_256 = or(_csr_exists_T_255, _csr_exists_T_107)
node _csr_exists_T_257 = or(_csr_exists_T_256, _csr_exists_T_108)
node _csr_exists_T_258 = or(_csr_exists_T_257, _csr_exists_T_109)
node _csr_exists_T_259 = or(_csr_exists_T_258, _csr_exists_T_110)
node _csr_exists_T_260 = or(_csr_exists_T_259, _csr_exists_T_111)
node _csr_exists_T_261 = or(_csr_exists_T_260, _csr_exists_T_112)
node _csr_exists_T_262 = or(_csr_exists_T_261, _csr_exists_T_113)
node _csr_exists_T_263 = or(_csr_exists_T_262, _csr_exists_T_114)
node _csr_exists_T_264 = or(_csr_exists_T_263, _csr_exists_T_115)
node _csr_exists_T_265 = or(_csr_exists_T_264, _csr_exists_T_116)
node _csr_exists_T_266 = or(_csr_exists_T_265, _csr_exists_T_117)
node _csr_exists_T_267 = or(_csr_exists_T_266, _csr_exists_T_118)
node _csr_exists_T_268 = or(_csr_exists_T_267, _csr_exists_T_119)
node _csr_exists_T_269 = or(_csr_exists_T_268, _csr_exists_T_120)
node _csr_exists_T_270 = or(_csr_exists_T_269, _csr_exists_T_121)
node _csr_exists_T_271 = or(_csr_exists_T_270, _csr_exists_T_122)
node _csr_exists_T_272 = or(_csr_exists_T_271, _csr_exists_T_123)
node _csr_exists_T_273 = or(_csr_exists_T_272, _csr_exists_T_124)
node _csr_exists_T_274 = or(_csr_exists_T_273, _csr_exists_T_125)
node _csr_exists_T_275 = or(_csr_exists_T_274, _csr_exists_T_126)
node _csr_exists_T_276 = or(_csr_exists_T_275, _csr_exists_T_127)
node _csr_exists_T_277 = or(_csr_exists_T_276, _csr_exists_T_128)
node _csr_exists_T_278 = or(_csr_exists_T_277, _csr_exists_T_129)
node _csr_exists_T_279 = or(_csr_exists_T_278, _csr_exists_T_130)
node _csr_exists_T_280 = or(_csr_exists_T_279, _csr_exists_T_131)
node _csr_exists_T_281 = or(_csr_exists_T_280, _csr_exists_T_132)
node _csr_exists_T_282 = or(_csr_exists_T_281, _csr_exists_T_133)
node _csr_exists_T_283 = or(_csr_exists_T_282, _csr_exists_T_134)
node _csr_exists_T_284 = or(_csr_exists_T_283, _csr_exists_T_135)
node _csr_exists_T_285 = or(_csr_exists_T_284, _csr_exists_T_136)
node _csr_exists_T_286 = or(_csr_exists_T_285, _csr_exists_T_137)
node _csr_exists_T_287 = or(_csr_exists_T_286, _csr_exists_T_138)
node _csr_exists_T_288 = or(_csr_exists_T_287, _csr_exists_T_139)
node _csr_exists_T_289 = or(_csr_exists_T_288, _csr_exists_T_140)
node _csr_exists_T_290 = or(_csr_exists_T_289, _csr_exists_T_141)
node _csr_exists_T_291 = or(_csr_exists_T_290, _csr_exists_T_142)
node _csr_exists_T_292 = or(_csr_exists_T_291, _csr_exists_T_143)
node _csr_exists_T_293 = or(_csr_exists_T_292, _csr_exists_T_144)
node _csr_exists_T_294 = or(_csr_exists_T_293, _csr_exists_T_145)
node _csr_exists_T_295 = or(_csr_exists_T_294, _csr_exists_T_146)
node _csr_exists_T_296 = or(_csr_exists_T_295, _csr_exists_T_147)
node _csr_exists_T_297 = or(_csr_exists_T_296, _csr_exists_T_148)
node csr_exists = or(_csr_exists_T_297, _csr_exists_T_149)
node _io_decode_0_read_illegal_T = eq(csr_addr_legal, UInt<1>(0h0))
node _io_decode_0_read_illegal_T_1 = eq(csr_exists, UInt<1>(0h0))
node _io_decode_0_read_illegal_T_2 = or(_io_decode_0_read_illegal_T, _io_decode_0_read_illegal_T_1)
node _io_decode_0_read_illegal_T_3 = eq(addr, UInt<9>(0h180))
node _io_decode_0_read_illegal_T_4 = eq(addr, UInt<11>(0h680))
node _io_decode_0_read_illegal_T_5 = or(_io_decode_0_read_illegal_T_3, _io_decode_0_read_illegal_T_4)
node _io_decode_0_read_illegal_T_6 = eq(allow_sfence_vma, UInt<1>(0h0))
node _io_decode_0_read_illegal_T_7 = and(_io_decode_0_read_illegal_T_5, _io_decode_0_read_illegal_T_6)
node _io_decode_0_read_illegal_T_8 = or(_io_decode_0_read_illegal_T_2, _io_decode_0_read_illegal_T_7)
node _io_decode_0_read_illegal_T_9 = eq(allow_counter, UInt<1>(0h0))
node _io_decode_0_read_illegal_T_10 = and(is_counter, _io_decode_0_read_illegal_T_9)
node _io_decode_0_read_illegal_T_11 = or(_io_decode_0_read_illegal_T_8, _io_decode_0_read_illegal_T_10)
wire io_decode_0_read_illegal_plaInput : UInt<12>
node io_decode_0_read_illegal_invInputs = not(io_decode_0_read_illegal_plaInput)
wire io_decode_0_read_illegal_plaOutput : UInt<1>
node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0 = bits(io_decode_0_read_illegal_plaInput, 4, 4)
node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1 = bits(io_decode_0_read_illegal_plaInput, 5, 5)
node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2 = bits(io_decode_0_read_illegal_invInputs, 6, 6)
node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3 = bits(io_decode_0_read_illegal_plaInput, 7, 7)
node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4 = bits(io_decode_0_read_illegal_plaInput, 8, 8)
node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5 = bits(io_decode_0_read_illegal_plaInput, 9, 9)
node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6 = bits(io_decode_0_read_illegal_plaInput, 10, 10)
node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7 = bits(io_decode_0_read_illegal_invInputs, 11, 11)
node io_decode_0_read_illegal_andMatrixOutputs_lo_lo = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7)
node io_decode_0_read_illegal_andMatrixOutputs_lo_hi = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5)
node io_decode_0_read_illegal_andMatrixOutputs_lo = cat(io_decode_0_read_illegal_andMatrixOutputs_lo_hi, io_decode_0_read_illegal_andMatrixOutputs_lo_lo)
node io_decode_0_read_illegal_andMatrixOutputs_hi_lo = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3)
node io_decode_0_read_illegal_andMatrixOutputs_hi_hi = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1)
node io_decode_0_read_illegal_andMatrixOutputs_hi = cat(io_decode_0_read_illegal_andMatrixOutputs_hi_hi, io_decode_0_read_illegal_andMatrixOutputs_hi_lo)
node _io_decode_0_read_illegal_andMatrixOutputs_T = cat(io_decode_0_read_illegal_andMatrixOutputs_hi, io_decode_0_read_illegal_andMatrixOutputs_lo)
node io_decode_0_read_illegal_andMatrixOutputs_0_2 = andr(_io_decode_0_read_illegal_andMatrixOutputs_T)
node io_decode_0_read_illegal_orMatrixOutputs = orr(io_decode_0_read_illegal_andMatrixOutputs_0_2)
node io_decode_0_read_illegal_invMatrixOutputs = bits(io_decode_0_read_illegal_orMatrixOutputs, 0, 0)
connect io_decode_0_read_illegal_plaOutput, io_decode_0_read_illegal_invMatrixOutputs
connect io_decode_0_read_illegal_plaInput, addr
node _io_decode_0_read_illegal_T_12 = bits(io_decode_0_read_illegal_plaOutput, 0, 0)
node _io_decode_0_read_illegal_T_13 = eq(reg_debug, UInt<1>(0h0))
node _io_decode_0_read_illegal_T_14 = and(_io_decode_0_read_illegal_T_12, _io_decode_0_read_illegal_T_13)
node _io_decode_0_read_illegal_T_15 = or(_io_decode_0_read_illegal_T_11, _io_decode_0_read_illegal_T_14)
wire io_decode_0_read_illegal_plaInput_1 : UInt<12>
node io_decode_0_read_illegal_invInputs_1 = not(io_decode_0_read_illegal_plaInput_1)
wire io_decode_0_read_illegal_plaOutput_1 : UInt<1>
connect io_decode_0_read_illegal_plaOutput_1, UInt<1>(0h0)
connect io_decode_0_read_illegal_plaInput_1, addr
node _io_decode_0_read_illegal_T_16 = bits(io_decode_0_read_illegal_plaOutput_1, 0, 0)
node _io_decode_0_read_illegal_T_17 = and(_io_decode_0_read_illegal_T_16, io.decode[0].vector_illegal)
node _io_decode_0_read_illegal_T_18 = or(_io_decode_0_read_illegal_T_15, _io_decode_0_read_illegal_T_17)
node _io_decode_0_read_illegal_T_19 = and(io.decode[0].fp_csr, io.decode[0].fp_illegal)
node _io_decode_0_read_illegal_T_20 = or(_io_decode_0_read_illegal_T_18, _io_decode_0_read_illegal_T_19)
connect io.decode[0].read_illegal, _io_decode_0_read_illegal_T_20
node _io_decode_0_write_illegal_T = bits(addr, 11, 10)
node _io_decode_0_write_illegal_T_1 = andr(_io_decode_0_write_illegal_T)
connect io.decode[0].write_illegal, _io_decode_0_write_illegal_T_1
node _io_decode_0_write_flush_addr_m_T = shl(UInt<2>(0h3), 8)
node io_decode_0_write_flush_addr_m = or(addr, _io_decode_0_write_flush_addr_m_T)
node _io_decode_0_write_flush_T = geq(io_decode_0_write_flush_addr_m, UInt<10>(0h340))
node _io_decode_0_write_flush_T_1 = leq(io_decode_0_write_flush_addr_m, UInt<10>(0h343))
node _io_decode_0_write_flush_T_2 = and(_io_decode_0_write_flush_T, _io_decode_0_write_flush_T_1)
node _io_decode_0_write_flush_T_3 = eq(_io_decode_0_write_flush_T_2, UInt<1>(0h0))
connect io.decode[0].write_flush, _io_decode_0_write_flush_T_3
node _io_decode_0_system_illegal_T = eq(csr_addr_legal, UInt<1>(0h0))
node _io_decode_0_system_illegal_T_1 = eq(is_hlsv, UInt<1>(0h0))
node _io_decode_0_system_illegal_T_2 = and(_io_decode_0_system_illegal_T, _io_decode_0_system_illegal_T_1)
node _io_decode_0_system_illegal_T_3 = eq(allow_wfi, UInt<1>(0h0))
node _io_decode_0_system_illegal_T_4 = and(is_wfi, _io_decode_0_system_illegal_T_3)
node _io_decode_0_system_illegal_T_5 = or(_io_decode_0_system_illegal_T_2, _io_decode_0_system_illegal_T_4)
node _io_decode_0_system_illegal_T_6 = eq(allow_sret, UInt<1>(0h0))
node _io_decode_0_system_illegal_T_7 = and(is_ret, _io_decode_0_system_illegal_T_6)
node _io_decode_0_system_illegal_T_8 = or(_io_decode_0_system_illegal_T_5, _io_decode_0_system_illegal_T_7)
node _io_decode_0_system_illegal_T_9 = bits(addr, 10, 10)
node _io_decode_0_system_illegal_T_10 = and(is_ret, _io_decode_0_system_illegal_T_9)
node _io_decode_0_system_illegal_T_11 = bits(addr, 7, 7)
node _io_decode_0_system_illegal_T_12 = and(_io_decode_0_system_illegal_T_10, _io_decode_0_system_illegal_T_11)
node _io_decode_0_system_illegal_T_13 = eq(reg_debug, UInt<1>(0h0))
node _io_decode_0_system_illegal_T_14 = and(_io_decode_0_system_illegal_T_12, _io_decode_0_system_illegal_T_13)
node _io_decode_0_system_illegal_T_15 = or(_io_decode_0_system_illegal_T_8, _io_decode_0_system_illegal_T_14)
node _io_decode_0_system_illegal_T_16 = or(is_sfence, is_hfence_gvma)
node _io_decode_0_system_illegal_T_17 = eq(allow_sfence_vma, UInt<1>(0h0))
node _io_decode_0_system_illegal_T_18 = and(_io_decode_0_system_illegal_T_16, _io_decode_0_system_illegal_T_17)
node _io_decode_0_system_illegal_T_19 = or(_io_decode_0_system_illegal_T_15, _io_decode_0_system_illegal_T_18)
node _io_decode_0_system_illegal_T_20 = eq(allow_hfence_vvma, UInt<1>(0h0))
node _io_decode_0_system_illegal_T_21 = and(is_hfence_vvma, _io_decode_0_system_illegal_T_20)
node _io_decode_0_system_illegal_T_22 = or(_io_decode_0_system_illegal_T_19, _io_decode_0_system_illegal_T_21)
node _io_decode_0_system_illegal_T_23 = eq(allow_hlsv, UInt<1>(0h0))
node _io_decode_0_system_illegal_T_24 = and(is_hlsv, _io_decode_0_system_illegal_T_23)
node _io_decode_0_system_illegal_T_25 = or(_io_decode_0_system_illegal_T_22, _io_decode_0_system_illegal_T_24)
connect io.decode[0].system_illegal, _io_decode_0_system_illegal_T_25
node _io_decode_0_virtual_access_illegal_T = and(reg_mstatus.v, csr_exists)
node _io_decode_0_virtual_access_illegal_T_1 = bits(addr, 9, 8)
node _io_decode_0_virtual_access_illegal_T_2 = eq(_io_decode_0_virtual_access_illegal_T_1, UInt<2>(0h2))
node _io_decode_0_virtual_access_illegal_T_3 = dshr(read_mcounteren, counter_addr)
node _io_decode_0_virtual_access_illegal_T_4 = bits(_io_decode_0_virtual_access_illegal_T_3, 0, 0)
node _io_decode_0_virtual_access_illegal_T_5 = and(is_counter, _io_decode_0_virtual_access_illegal_T_4)
node _io_decode_0_virtual_access_illegal_T_6 = dshr(read_hcounteren, counter_addr)
node _io_decode_0_virtual_access_illegal_T_7 = bits(_io_decode_0_virtual_access_illegal_T_6, 0, 0)
node _io_decode_0_virtual_access_illegal_T_8 = eq(_io_decode_0_virtual_access_illegal_T_7, UInt<1>(0h0))
node _io_decode_0_virtual_access_illegal_T_9 = bits(reg_mstatus.prv, 0, 0)
node _io_decode_0_virtual_access_illegal_T_10 = eq(_io_decode_0_virtual_access_illegal_T_9, UInt<1>(0h0))
node _io_decode_0_virtual_access_illegal_T_11 = dshr(read_scounteren, counter_addr)
node _io_decode_0_virtual_access_illegal_T_12 = bits(_io_decode_0_virtual_access_illegal_T_11, 0, 0)
node _io_decode_0_virtual_access_illegal_T_13 = eq(_io_decode_0_virtual_access_illegal_T_12, UInt<1>(0h0))
node _io_decode_0_virtual_access_illegal_T_14 = and(_io_decode_0_virtual_access_illegal_T_10, _io_decode_0_virtual_access_illegal_T_13)
node _io_decode_0_virtual_access_illegal_T_15 = or(_io_decode_0_virtual_access_illegal_T_8, _io_decode_0_virtual_access_illegal_T_14)
node _io_decode_0_virtual_access_illegal_T_16 = and(_io_decode_0_virtual_access_illegal_T_5, _io_decode_0_virtual_access_illegal_T_15)
node _io_decode_0_virtual_access_illegal_T_17 = or(_io_decode_0_virtual_access_illegal_T_2, _io_decode_0_virtual_access_illegal_T_16)
node _io_decode_0_virtual_access_illegal_T_18 = bits(addr, 9, 8)
node _io_decode_0_virtual_access_illegal_T_19 = eq(_io_decode_0_virtual_access_illegal_T_18, UInt<1>(0h1))
node _io_decode_0_virtual_access_illegal_T_20 = bits(reg_mstatus.prv, 0, 0)
node _io_decode_0_virtual_access_illegal_T_21 = eq(_io_decode_0_virtual_access_illegal_T_20, UInt<1>(0h0))
node _io_decode_0_virtual_access_illegal_T_22 = and(_io_decode_0_virtual_access_illegal_T_19, _io_decode_0_virtual_access_illegal_T_21)
node _io_decode_0_virtual_access_illegal_T_23 = or(_io_decode_0_virtual_access_illegal_T_17, _io_decode_0_virtual_access_illegal_T_22)
node _io_decode_0_virtual_access_illegal_T_24 = eq(addr, UInt<9>(0h180))
node _io_decode_0_virtual_access_illegal_T_25 = bits(reg_mstatus.prv, 0, 0)
node _io_decode_0_virtual_access_illegal_T_26 = and(_io_decode_0_virtual_access_illegal_T_24, _io_decode_0_virtual_access_illegal_T_25)
node _io_decode_0_virtual_access_illegal_T_27 = and(_io_decode_0_virtual_access_illegal_T_26, reg_hstatus.vtvm)
node _io_decode_0_virtual_access_illegal_T_28 = or(_io_decode_0_virtual_access_illegal_T_23, _io_decode_0_virtual_access_illegal_T_27)
node _io_decode_0_virtual_access_illegal_T_29 = and(_io_decode_0_virtual_access_illegal_T, _io_decode_0_virtual_access_illegal_T_28)
connect io.decode[0].virtual_access_illegal, _io_decode_0_virtual_access_illegal_T_29
node _io_decode_0_virtual_system_illegal_T = or(is_hfence_vvma, is_hfence_gvma)
node _io_decode_0_virtual_system_illegal_T_1 = or(_io_decode_0_virtual_system_illegal_T, is_hlsv)
node _io_decode_0_virtual_system_illegal_T_2 = bits(reg_mstatus.prv, 0, 0)
node _io_decode_0_virtual_system_illegal_T_3 = eq(_io_decode_0_virtual_system_illegal_T_2, UInt<1>(0h0))
node _io_decode_0_virtual_system_illegal_T_4 = eq(reg_mstatus.tw, UInt<1>(0h0))
node _io_decode_0_virtual_system_illegal_T_5 = and(_io_decode_0_virtual_system_illegal_T_4, reg_hstatus.vtw)
node _io_decode_0_virtual_system_illegal_T_6 = or(_io_decode_0_virtual_system_illegal_T_3, _io_decode_0_virtual_system_illegal_T_5)
node _io_decode_0_virtual_system_illegal_T_7 = and(is_wfi, _io_decode_0_virtual_system_illegal_T_6)
node _io_decode_0_virtual_system_illegal_T_8 = or(_io_decode_0_virtual_system_illegal_T_1, _io_decode_0_virtual_system_illegal_T_7)
node _io_decode_0_virtual_system_illegal_T_9 = bits(addr, 9, 8)
node _io_decode_0_virtual_system_illegal_T_10 = eq(_io_decode_0_virtual_system_illegal_T_9, UInt<1>(0h1))
node _io_decode_0_virtual_system_illegal_T_11 = and(is_ret, _io_decode_0_virtual_system_illegal_T_10)
node _io_decode_0_virtual_system_illegal_T_12 = bits(reg_mstatus.prv, 0, 0)
node _io_decode_0_virtual_system_illegal_T_13 = eq(_io_decode_0_virtual_system_illegal_T_12, UInt<1>(0h0))
node _io_decode_0_virtual_system_illegal_T_14 = or(_io_decode_0_virtual_system_illegal_T_13, reg_hstatus.vtsr)
node _io_decode_0_virtual_system_illegal_T_15 = and(_io_decode_0_virtual_system_illegal_T_11, _io_decode_0_virtual_system_illegal_T_14)
node _io_decode_0_virtual_system_illegal_T_16 = or(_io_decode_0_virtual_system_illegal_T_8, _io_decode_0_virtual_system_illegal_T_15)
node _io_decode_0_virtual_system_illegal_T_17 = bits(reg_mstatus.prv, 0, 0)
node _io_decode_0_virtual_system_illegal_T_18 = eq(_io_decode_0_virtual_system_illegal_T_17, UInt<1>(0h0))
node _io_decode_0_virtual_system_illegal_T_19 = or(_io_decode_0_virtual_system_illegal_T_18, reg_hstatus.vtvm)
node _io_decode_0_virtual_system_illegal_T_20 = and(is_sfence, _io_decode_0_virtual_system_illegal_T_19)
node _io_decode_0_virtual_system_illegal_T_21 = or(_io_decode_0_virtual_system_illegal_T_16, _io_decode_0_virtual_system_illegal_T_20)
node _io_decode_0_virtual_system_illegal_T_22 = and(reg_mstatus.v, _io_decode_0_virtual_system_illegal_T_21)
connect io.decode[0].virtual_system_illegal, _io_decode_0_virtual_system_illegal_T_22
node _cause_T = bits(reg_mstatus.prv, 0, 0)
node _cause_T_1 = and(_cause_T, reg_mstatus.v)
node _cause_T_2 = mux(_cause_T_1, UInt<2>(0h2), reg_mstatus.prv)
node _cause_T_3 = add(UInt<4>(0h8), _cause_T_2)
node _cause_T_4 = tail(_cause_T_3, 1)
node _cause_T_5 = mux(insn_break, UInt<2>(0h3), io.cause)
node cause = mux(insn_call, _cause_T_4, _cause_T_5)
node cause_lsbs = bits(cause, 7, 0)
node cause_deleg_lsbs = bits(cause, 5, 0)
node _causeIsDebugInt_T = bits(cause, 63, 63)
node _causeIsDebugInt_T_1 = eq(cause_lsbs, UInt<4>(0he))
node causeIsDebugInt = and(_causeIsDebugInt_T, _causeIsDebugInt_T_1)
node _causeIsDebugTrigger_T = bits(cause, 63, 63)
node _causeIsDebugTrigger_T_1 = eq(_causeIsDebugTrigger_T, UInt<1>(0h0))
node _causeIsDebugTrigger_T_2 = eq(cause_lsbs, UInt<4>(0he))
node causeIsDebugTrigger = and(_causeIsDebugTrigger_T_1, _causeIsDebugTrigger_T_2)
node _causeIsDebugBreak_T = bits(cause, 63, 63)
node _causeIsDebugBreak_T_1 = eq(_causeIsDebugBreak_T, UInt<1>(0h0))
node _causeIsDebugBreak_T_2 = and(_causeIsDebugBreak_T_1, insn_break)
node causeIsDebugBreak_lo = cat(reg_dcsr.ebreaks, reg_dcsr.ebreaku)
node causeIsDebugBreak_hi = cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh)
node _causeIsDebugBreak_T_3 = cat(causeIsDebugBreak_hi, causeIsDebugBreak_lo)
node _causeIsDebugBreak_T_4 = dshr(_causeIsDebugBreak_T_3, reg_mstatus.prv)
node _causeIsDebugBreak_T_5 = bits(_causeIsDebugBreak_T_4, 0, 0)
node causeIsDebugBreak = and(_causeIsDebugBreak_T_2, _causeIsDebugBreak_T_5)
node _trapToDebug_T = or(reg_singleStepped, causeIsDebugInt)
node _trapToDebug_T_1 = or(_trapToDebug_T, causeIsDebugTrigger)
node _trapToDebug_T_2 = or(_trapToDebug_T_1, causeIsDebugBreak)
node _trapToDebug_T_3 = or(_trapToDebug_T_2, reg_debug)
node trapToDebug = and(UInt<1>(0h1), _trapToDebug_T_3)
node _debugTVec_T = mux(insn_break, UInt<12>(0h800), UInt<12>(0h808))
node debugTVec = mux(reg_debug, _debugTVec_T, UInt<12>(0h800))
node _delegate_T = leq(reg_mstatus.prv, UInt<1>(0h1))
node _delegate_T_1 = and(UInt<1>(0h1), _delegate_T)
node _delegate_T_2 = bits(cause, 63, 63)
node _delegate_T_3 = dshr(read_mideleg, cause_deleg_lsbs)
node _delegate_T_4 = bits(_delegate_T_3, 0, 0)
node _delegate_T_5 = dshr(read_medeleg, cause_deleg_lsbs)
node _delegate_T_6 = bits(_delegate_T_5, 0, 0)
node _delegate_T_7 = mux(_delegate_T_2, _delegate_T_4, _delegate_T_6)
node delegate = and(_delegate_T_1, _delegate_T_7)
node _delegateVS_T = and(reg_mstatus.v, delegate)
node _delegateVS_T_1 = bits(cause, 63, 63)
node _delegateVS_T_2 = dshr(read_hideleg, cause_deleg_lsbs)
node _delegateVS_T_3 = bits(_delegateVS_T_2, 0, 0)
node _delegateVS_T_4 = dshr(read_hedeleg, cause_deleg_lsbs)
node _delegateVS_T_5 = bits(_delegateVS_T_4, 0, 0)
node _delegateVS_T_6 = mux(_delegateVS_T_1, _delegateVS_T_3, _delegateVS_T_5)
node delegateVS = and(_delegateVS_T, _delegateVS_T_6)
node _notDebugTVec_base_T = mux(delegateVS, read_vstvec, read_stvec)
node notDebugTVec_base = mux(delegate, _notDebugTVec_base_T, read_mtvec)
node _notDebugTVec_interruptOffset_T = bits(cause, 5, 0)
node notDebugTVec_interruptOffset = shl(_notDebugTVec_interruptOffset_T, 2)
node _notDebugTVec_interruptVec_T = shr(notDebugTVec_base, 8)
node notDebugTVec_interruptVec = cat(_notDebugTVec_interruptVec_T, notDebugTVec_interruptOffset)
node _notDebugTVec_doVector_T = bits(notDebugTVec_base, 0, 0)
node _notDebugTVec_doVector_T_1 = bits(cause, 63, 63)
node _notDebugTVec_doVector_T_2 = and(_notDebugTVec_doVector_T, _notDebugTVec_doVector_T_1)
node _notDebugTVec_doVector_T_3 = shr(cause_lsbs, 6)
node _notDebugTVec_doVector_T_4 = eq(_notDebugTVec_doVector_T_3, UInt<1>(0h0))
node notDebugTVec_doVector = and(_notDebugTVec_doVector_T_2, _notDebugTVec_doVector_T_4)
node _notDebugTVec_T = shr(notDebugTVec_base, 2)
node _notDebugTVec_T_1 = shl(_notDebugTVec_T, 2)
node notDebugTVec = mux(notDebugTVec_doVector, notDebugTVec_interruptVec, _notDebugTVec_T_1)
node _causeIsRnmiInt_T = bits(cause, 63, 63)
node _causeIsRnmiInt_T_1 = bits(cause, 62, 62)
node _causeIsRnmiInt_T_2 = and(_causeIsRnmiInt_T, _causeIsRnmiInt_T_1)
node _causeIsRnmiInt_T_3 = eq(cause_lsbs, UInt<4>(0hd))
node _causeIsRnmiInt_T_4 = eq(cause_lsbs, UInt<4>(0hc))
node _causeIsRnmiInt_T_5 = or(_causeIsRnmiInt_T_3, _causeIsRnmiInt_T_4)
node causeIsRnmiInt = and(_causeIsRnmiInt_T_2, _causeIsRnmiInt_T_5)
node _causeIsRnmiBEU_T = bits(cause, 63, 63)
node _causeIsRnmiBEU_T_1 = bits(cause, 62, 62)
node _causeIsRnmiBEU_T_2 = and(_causeIsRnmiBEU_T, _causeIsRnmiBEU_T_1)
node _causeIsRnmiBEU_T_3 = eq(cause_lsbs, UInt<4>(0hc))
node causeIsRnmiBEU = and(_causeIsRnmiBEU_T_2, _causeIsRnmiBEU_T_3)
node trapToNmiInt = and(UInt<1>(0h0), causeIsRnmiInt)
node _trapToNmiXcpt_T = eq(reg_rnmie, UInt<1>(0h0))
node trapToNmiXcpt = and(UInt<1>(0h0), _trapToNmiXcpt_T)
node trapToNmi = or(trapToNmiInt, trapToNmiXcpt)
node _nmiTVec_T = mux(causeIsRnmiInt, UInt<1>(0h0), UInt<1>(0h0))
node _nmiTVec_T_1 = shr(_nmiTVec_T, 1)
node nmiTVec = shl(_nmiTVec_T_1, 1)
node _tvec_T = mux(trapToNmi, nmiTVec, notDebugTVec)
node tvec = mux(trapToDebug, debugTVec, _tvec_T)
connect io.evec, tvec
connect io.ptbr, reg_satp
connect io.hgatp, reg_hgatp
connect io.vsatp, reg_vsatp
node _io_eret_T = or(insn_call, insn_break)
node _io_eret_T_1 = or(_io_eret_T, insn_ret)
connect io.eret, _io_eret_T_1
node _io_singleStep_T = eq(reg_debug, UInt<1>(0h0))
node _io_singleStep_T_1 = and(reg_dcsr.step, _io_singleStep_T)
connect io.singleStep, _io_singleStep_T_1
connect io.status, reg_mstatus
node _io_status_sd_T = andr(io.status.fs)
node _io_status_sd_T_1 = andr(io.status.xs)
node _io_status_sd_T_2 = or(_io_status_sd_T, _io_status_sd_T_1)
node _io_status_sd_T_3 = andr(io.status.vs)
node _io_status_sd_T_4 = or(_io_status_sd_T_2, _io_status_sd_T_3)
connect io.status.sd, _io_status_sd_T_4
connect io.status.debug, reg_debug
connect io.status.isa, reg_misa
connect io.status.uxl, UInt<2>(0h2)
connect io.status.sxl, UInt<2>(0h2)
node _io_status_dprv_T = eq(reg_debug, UInt<1>(0h0))
node _io_status_dprv_T_1 = and(reg_mstatus.mprv, _io_status_dprv_T)
node _io_status_dprv_T_2 = mux(_io_status_dprv_T_1, reg_mstatus.mpp, reg_mstatus.prv)
connect io.status.dprv, _io_status_dprv_T_2
node _io_status_dv_T = eq(reg_debug, UInt<1>(0h0))
node _io_status_dv_T_1 = and(reg_mstatus.mprv, _io_status_dv_T)
node _io_status_dv_T_2 = mux(_io_status_dv_T_1, reg_mstatus.mpv, UInt<1>(0h0))
node _io_status_dv_T_3 = or(reg_mstatus.v, _io_status_dv_T_2)
connect io.status.dv, _io_status_dv_T_3
node _io_status_sd_rv32_T = and(UInt<1>(0h0), io.status.sd)
connect io.status.sd_rv32, _io_status_sd_rv32_T
connect io.status.mpv, reg_mstatus.mpv
connect io.status.gva, reg_mstatus.gva
connect io.hstatus, reg_hstatus
connect io.hstatus.vsxl, UInt<2>(0h2)
connect io.gstatus, reg_vsstatus
node _io_gstatus_sd_T = andr(io.gstatus.fs)
node _io_gstatus_sd_T_1 = andr(io.gstatus.xs)
node _io_gstatus_sd_T_2 = or(_io_gstatus_sd_T, _io_gstatus_sd_T_1)
node _io_gstatus_sd_T_3 = andr(io.gstatus.vs)
node _io_gstatus_sd_T_4 = or(_io_gstatus_sd_T_2, _io_gstatus_sd_T_3)
connect io.gstatus.sd, _io_gstatus_sd_T_4
connect io.gstatus.uxl, UInt<2>(0h2)
node _io_gstatus_sd_rv32_T = and(UInt<1>(0h0), io.gstatus.sd)
connect io.gstatus.sd_rv32, _io_gstatus_sd_rv32_T
node _exception_T = or(insn_call, insn_break)
node exception = or(_exception_T, io.exception)
node _T_86 = add(insn_ret, insn_call)
node _T_87 = bits(_T_86, 1, 0)
node _T_88 = add(insn_break, io.exception)
node _T_89 = bits(_T_88, 1, 0)
node _T_90 = add(_T_87, _T_89)
node _T_91 = bits(_T_90, 2, 0)
node _T_92 = leq(_T_91, UInt<1>(0h1))
node _T_93 = asUInt(reset)
node _T_94 = eq(_T_93, UInt<1>(0h0))
when _T_94 :
node _T_95 = eq(_T_92, UInt<1>(0h0))
when _T_95 :
printf(clock, UInt<1>(0h1), "Assertion failed: these conditions must be mutually exclusive\n at CSR.scala:1021 assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1.U, \"these conditions must be mutually exclusive\")\n") : printf
assert(clock, _T_92, UInt<1>(0h1), "") : assert
node _T_96 = eq(io.singleStep, UInt<1>(0h0))
node _T_97 = and(insn_wfi, _T_96)
node _T_98 = eq(reg_debug, UInt<1>(0h0))
node _T_99 = and(_T_97, _T_98)
when _T_99 :
connect reg_wfi, UInt<1>(0h1)
node _T_100 = orr(pending_interrupts)
node _T_101 = or(_T_100, io.interrupts.debug)
node _T_102 = or(_T_101, exception)
when _T_102 :
connect reg_wfi, UInt<1>(0h0)
node _T_103 = bits(io.retire, 0, 0)
node _T_104 = or(_T_103, exception)
when _T_104 :
connect reg_singleStepped, UInt<1>(0h1)
node _T_105 = eq(io.singleStep, UInt<1>(0h0))
when _T_105 :
connect reg_singleStepped, UInt<1>(0h0)
node _T_106 = eq(io.singleStep, UInt<1>(0h0))
node _T_107 = leq(io.retire, UInt<1>(0h1))
node _T_108 = or(_T_106, _T_107)
node _T_109 = asUInt(reset)
node _T_110 = eq(_T_109, UInt<1>(0h0))
when _T_110 :
node _T_111 = eq(_T_108, UInt<1>(0h0))
when _T_111 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at CSR.scala:1029 assert(!io.singleStep || io.retire <= 1.U)\n") : printf_1
assert(clock, _T_108, UInt<1>(0h1), "") : assert_1
node _T_112 = eq(reg_singleStepped, UInt<1>(0h0))
node _T_113 = eq(io.retire, UInt<1>(0h0))
node _T_114 = or(_T_112, _T_113)
node _T_115 = asUInt(reset)
node _T_116 = eq(_T_115, UInt<1>(0h0))
when _T_116 :
node _T_117 = eq(_T_114, UInt<1>(0h0))
when _T_117 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at CSR.scala:1030 assert(!reg_singleStepped || io.retire === 0.U)\n") : printf_2
assert(clock, _T_114, UInt<1>(0h1), "") : assert_2
node _epc_T = not(io.pc)
node _epc_T_1 = or(_epc_T, UInt<1>(0h1))
node epc = not(_epc_T_1)
node tval = mux(insn_break, epc, io.tval)
when exception :
when trapToDebug :
node _T_118 = eq(reg_debug, UInt<1>(0h0))
when _T_118 :
connect reg_mstatus.v, UInt<1>(0h0)
connect reg_debug, UInt<1>(0h1)
connect reg_dpc, epc
node _reg_dcsr_cause_T = mux(causeIsDebugTrigger, UInt<2>(0h2), UInt<1>(0h1))
node _reg_dcsr_cause_T_1 = mux(causeIsDebugInt, UInt<2>(0h3), _reg_dcsr_cause_T)
node _reg_dcsr_cause_T_2 = mux(reg_singleStepped, UInt<3>(0h4), _reg_dcsr_cause_T_1)
connect reg_dcsr.cause, _reg_dcsr_cause_T_2
connect reg_dcsr.prv, reg_mstatus.prv
connect reg_dcsr.v, reg_mstatus.v
connect new_prv, UInt<2>(0h3)
else :
when trapToNmiInt :
when reg_rnmie :
connect reg_mstatus.v, UInt<1>(0h0)
connect reg_mnstatus.mpv, reg_mstatus.v
connect reg_rnmie, UInt<1>(0h0)
connect reg_mnepc, epc
node _reg_mncause_T = mux(causeIsRnmiBEU, UInt<2>(0h3), UInt<2>(0h2))
node _reg_mncause_T_1 = or(UInt<64>(0h8000000000000000), _reg_mncause_T)
connect reg_mncause, _reg_mncause_T_1
connect reg_mnstatus.mpp, reg_mstatus.prv
connect new_prv, UInt<2>(0h3)
else :
node _T_119 = and(delegateVS, reg_rnmie)
when _T_119 :
connect reg_mstatus.v, UInt<1>(0h1)
connect reg_vsstatus.spp, reg_mstatus.prv
connect reg_vsepc, epc
node _reg_vscause_T = bits(cause, 63, 63)
node _reg_vscause_T_1 = bits(cause, 63, 2)
node _reg_vscause_T_2 = cat(_reg_vscause_T_1, UInt<2>(0h1))
node _reg_vscause_T_3 = mux(_reg_vscause_T, _reg_vscause_T_2, cause)
connect reg_vscause, _reg_vscause_T_3
connect reg_vstval, tval
connect reg_vsstatus.spie, reg_vsstatus.sie
connect reg_vsstatus.sie, UInt<1>(0h0)
connect new_prv, UInt<1>(0h1)
else :
node _T_120 = and(delegate, reg_rnmie)
when _T_120 :
connect reg_mstatus.v, UInt<1>(0h0)
node _reg_hstatus_spvp_T = bits(reg_mstatus.prv, 0, 0)
node _reg_hstatus_spvp_T_1 = mux(reg_mstatus.v, _reg_hstatus_spvp_T, reg_hstatus.spvp)
connect reg_hstatus.spvp, _reg_hstatus_spvp_T_1
connect reg_hstatus.gva, io.gva
connect reg_hstatus.spv, reg_mstatus.v
connect reg_sepc, epc
connect reg_scause, cause
connect reg_stval, tval
connect reg_htval, io.htval
connect reg_htinst_read_pseudo, io.mhtinst_read_pseudo
connect reg_mstatus.spie, reg_mstatus.sie
connect reg_mstatus.spp, reg_mstatus.prv
connect reg_mstatus.sie, UInt<1>(0h0)
connect new_prv, UInt<1>(0h1)
else :
connect reg_mstatus.v, UInt<1>(0h0)
connect reg_mstatus.mpv, reg_mstatus.v
connect reg_mstatus.gva, io.gva
connect reg_mepc, epc
connect reg_mcause, cause
connect reg_mtval, tval
connect reg_mtval2, io.htval
connect reg_mtinst_read_pseudo, io.mhtinst_read_pseudo
connect reg_mstatus.mpie, reg_mstatus.mie
connect reg_mstatus.mpp, reg_mstatus.prv
connect reg_mstatus.mie, UInt<1>(0h0)
connect new_prv, UInt<2>(0h3)
node _en_T = and(supported_interrupts, UInt<1>(0h1))
node _en_T_1 = neq(_en_T, UInt<1>(0h0))
node _en_T_2 = and(exception, _en_T_1)
node _en_T_3 = add(UInt<64>(0h8000000000000000), UInt<1>(0h0))
node _en_T_4 = tail(_en_T_3, 1)
node _en_T_5 = eq(cause, _en_T_4)
node en = and(_en_T_2, _en_T_5)
node _delegable_T = and(delegable_interrupts, UInt<1>(0h1))
node delegable = neq(_delegable_T, UInt<1>(0h0))
node _T_121 = eq(delegate, UInt<1>(0h0))
node _T_122 = and(en, _T_121)
node _T_123 = and(en, delegable)
node _T_124 = and(_T_123, delegate)
node _en_T_6 = and(supported_interrupts, UInt<2>(0h2))
node _en_T_7 = neq(_en_T_6, UInt<1>(0h0))
node _en_T_8 = and(exception, _en_T_7)
node _en_T_9 = add(UInt<64>(0h8000000000000000), UInt<1>(0h1))
node _en_T_10 = tail(_en_T_9, 1)
node _en_T_11 = eq(cause, _en_T_10)
node en_1 = and(_en_T_8, _en_T_11)
node _delegable_T_1 = and(delegable_interrupts, UInt<2>(0h2))
node delegable_1 = neq(_delegable_T_1, UInt<1>(0h0))
node _T_125 = eq(delegate, UInt<1>(0h0))
node _T_126 = and(en_1, _T_125)
node _T_127 = and(en_1, delegable_1)
node _T_128 = and(_T_127, delegate)
node _en_T_12 = and(supported_interrupts, UInt<3>(0h4))
node _en_T_13 = neq(_en_T_12, UInt<1>(0h0))
node _en_T_14 = and(exception, _en_T_13)
node _en_T_15 = add(UInt<64>(0h8000000000000000), UInt<2>(0h2))
node _en_T_16 = tail(_en_T_15, 1)
node _en_T_17 = eq(cause, _en_T_16)
node en_2 = and(_en_T_14, _en_T_17)
node _delegable_T_2 = and(delegable_interrupts, UInt<3>(0h4))
node delegable_2 = neq(_delegable_T_2, UInt<1>(0h0))
node _T_129 = eq(delegate, UInt<1>(0h0))
node _T_130 = and(en_2, _T_129)
node _T_131 = and(en_2, delegable_2)
node _T_132 = and(_T_131, delegate)
node _en_T_18 = and(supported_interrupts, UInt<4>(0h8))
node _en_T_19 = neq(_en_T_18, UInt<1>(0h0))
node _en_T_20 = and(exception, _en_T_19)
node _en_T_21 = add(UInt<64>(0h8000000000000000), UInt<2>(0h3))
node _en_T_22 = tail(_en_T_21, 1)
node _en_T_23 = eq(cause, _en_T_22)
node en_3 = and(_en_T_20, _en_T_23)
node _delegable_T_3 = and(delegable_interrupts, UInt<4>(0h8))
node delegable_3 = neq(_delegable_T_3, UInt<1>(0h0))
node _T_133 = eq(delegate, UInt<1>(0h0))
node _T_134 = and(en_3, _T_133)
node _T_135 = and(en_3, delegable_3)
node _T_136 = and(_T_135, delegate)
node _en_T_24 = and(supported_interrupts, UInt<5>(0h10))
node _en_T_25 = neq(_en_T_24, UInt<1>(0h0))
node _en_T_26 = and(exception, _en_T_25)
node _en_T_27 = add(UInt<64>(0h8000000000000000), UInt<3>(0h4))
node _en_T_28 = tail(_en_T_27, 1)
node _en_T_29 = eq(cause, _en_T_28)
node en_4 = and(_en_T_26, _en_T_29)
node _delegable_T_4 = and(delegable_interrupts, UInt<5>(0h10))
node delegable_4 = neq(_delegable_T_4, UInt<1>(0h0))
node _T_137 = eq(delegate, UInt<1>(0h0))
node _T_138 = and(en_4, _T_137)
node _T_139 = and(en_4, delegable_4)
node _T_140 = and(_T_139, delegate)
node _en_T_30 = and(supported_interrupts, UInt<6>(0h20))
node _en_T_31 = neq(_en_T_30, UInt<1>(0h0))
node _en_T_32 = and(exception, _en_T_31)
node _en_T_33 = add(UInt<64>(0h8000000000000000), UInt<3>(0h5))
node _en_T_34 = tail(_en_T_33, 1)
node _en_T_35 = eq(cause, _en_T_34)
node en_5 = and(_en_T_32, _en_T_35)
node _delegable_T_5 = and(delegable_interrupts, UInt<6>(0h20))
node delegable_5 = neq(_delegable_T_5, UInt<1>(0h0))
node _T_141 = eq(delegate, UInt<1>(0h0))
node _T_142 = and(en_5, _T_141)
node _T_143 = and(en_5, delegable_5)
node _T_144 = and(_T_143, delegate)
node _en_T_36 = and(supported_interrupts, UInt<7>(0h40))
node _en_T_37 = neq(_en_T_36, UInt<1>(0h0))
node _en_T_38 = and(exception, _en_T_37)
node _en_T_39 = add(UInt<64>(0h8000000000000000), UInt<3>(0h6))
node _en_T_40 = tail(_en_T_39, 1)
node _en_T_41 = eq(cause, _en_T_40)
node en_6 = and(_en_T_38, _en_T_41)
node _delegable_T_6 = and(delegable_interrupts, UInt<7>(0h40))
node delegable_6 = neq(_delegable_T_6, UInt<1>(0h0))
node _T_145 = eq(delegate, UInt<1>(0h0))
node _T_146 = and(en_6, _T_145)
node _T_147 = and(en_6, delegable_6)
node _T_148 = and(_T_147, delegate)
node _en_T_42 = and(supported_interrupts, UInt<8>(0h80))
node _en_T_43 = neq(_en_T_42, UInt<1>(0h0))
node _en_T_44 = and(exception, _en_T_43)
node _en_T_45 = add(UInt<64>(0h8000000000000000), UInt<3>(0h7))
node _en_T_46 = tail(_en_T_45, 1)
node _en_T_47 = eq(cause, _en_T_46)
node en_7 = and(_en_T_44, _en_T_47)
node _delegable_T_7 = and(delegable_interrupts, UInt<8>(0h80))
node delegable_7 = neq(_delegable_T_7, UInt<1>(0h0))
node _T_149 = eq(delegate, UInt<1>(0h0))
node _T_150 = and(en_7, _T_149)
node _T_151 = and(en_7, delegable_7)
node _T_152 = and(_T_151, delegate)
node _en_T_48 = and(supported_interrupts, UInt<9>(0h100))
node _en_T_49 = neq(_en_T_48, UInt<1>(0h0))
node _en_T_50 = and(exception, _en_T_49)
node _en_T_51 = add(UInt<64>(0h8000000000000000), UInt<4>(0h8))
node _en_T_52 = tail(_en_T_51, 1)
node _en_T_53 = eq(cause, _en_T_52)
node en_8 = and(_en_T_50, _en_T_53)
node _delegable_T_8 = and(delegable_interrupts, UInt<9>(0h100))
node delegable_8 = neq(_delegable_T_8, UInt<1>(0h0))
node _T_153 = eq(delegate, UInt<1>(0h0))
node _T_154 = and(en_8, _T_153)
node _T_155 = and(en_8, delegable_8)
node _T_156 = and(_T_155, delegate)
node _en_T_54 = and(supported_interrupts, UInt<10>(0h200))
node _en_T_55 = neq(_en_T_54, UInt<1>(0h0))
node _en_T_56 = and(exception, _en_T_55)
node _en_T_57 = add(UInt<64>(0h8000000000000000), UInt<4>(0h9))
node _en_T_58 = tail(_en_T_57, 1)
node _en_T_59 = eq(cause, _en_T_58)
node en_9 = and(_en_T_56, _en_T_59)
node _delegable_T_9 = and(delegable_interrupts, UInt<10>(0h200))
node delegable_9 = neq(_delegable_T_9, UInt<1>(0h0))
node _T_157 = eq(delegate, UInt<1>(0h0))
node _T_158 = and(en_9, _T_157)
node _T_159 = and(en_9, delegable_9)
node _T_160 = and(_T_159, delegate)
node _en_T_60 = and(supported_interrupts, UInt<11>(0h400))
node _en_T_61 = neq(_en_T_60, UInt<1>(0h0))
node _en_T_62 = and(exception, _en_T_61)
node _en_T_63 = add(UInt<64>(0h8000000000000000), UInt<4>(0ha))
node _en_T_64 = tail(_en_T_63, 1)
node _en_T_65 = eq(cause, _en_T_64)
node en_10 = and(_en_T_62, _en_T_65)
node _delegable_T_10 = and(delegable_interrupts, UInt<11>(0h400))
node delegable_10 = neq(_delegable_T_10, UInt<1>(0h0))
node _T_161 = eq(delegate, UInt<1>(0h0))
node _T_162 = and(en_10, _T_161)
node _T_163 = and(en_10, delegable_10)
node _T_164 = and(_T_163, delegate)
node _en_T_66 = and(supported_interrupts, UInt<12>(0h800))
node _en_T_67 = neq(_en_T_66, UInt<1>(0h0))
node _en_T_68 = and(exception, _en_T_67)
node _en_T_69 = add(UInt<64>(0h8000000000000000), UInt<4>(0hb))
node _en_T_70 = tail(_en_T_69, 1)
node _en_T_71 = eq(cause, _en_T_70)
node en_11 = and(_en_T_68, _en_T_71)
node _delegable_T_11 = and(delegable_interrupts, UInt<12>(0h800))
node delegable_11 = neq(_delegable_T_11, UInt<1>(0h0))
node _T_165 = eq(delegate, UInt<1>(0h0))
node _T_166 = and(en_11, _T_165)
node _T_167 = and(en_11, delegable_11)
node _T_168 = and(_T_167, delegate)
node _en_T_72 = and(supported_interrupts, UInt<13>(0h1000))
node _en_T_73 = neq(_en_T_72, UInt<1>(0h0))
node _en_T_74 = and(exception, _en_T_73)
node _en_T_75 = add(UInt<64>(0h8000000000000000), UInt<4>(0hc))
node _en_T_76 = tail(_en_T_75, 1)
node _en_T_77 = eq(cause, _en_T_76)
node en_12 = and(_en_T_74, _en_T_77)
node _delegable_T_12 = and(delegable_interrupts, UInt<13>(0h1000))
node delegable_12 = neq(_delegable_T_12, UInt<1>(0h0))
node _T_169 = eq(delegate, UInt<1>(0h0))
node _T_170 = and(en_12, _T_169)
node _T_171 = and(en_12, delegable_12)
node _T_172 = and(_T_171, delegate)
node _en_T_78 = and(supported_interrupts, UInt<14>(0h2000))
node _en_T_79 = neq(_en_T_78, UInt<1>(0h0))
node _en_T_80 = and(exception, _en_T_79)
node _en_T_81 = add(UInt<64>(0h8000000000000000), UInt<4>(0hd))
node _en_T_82 = tail(_en_T_81, 1)
node _en_T_83 = eq(cause, _en_T_82)
node en_13 = and(_en_T_80, _en_T_83)
node _delegable_T_13 = and(delegable_interrupts, UInt<14>(0h2000))
node delegable_13 = neq(_delegable_T_13, UInt<1>(0h0))
node _T_173 = eq(delegate, UInt<1>(0h0))
node _T_174 = and(en_13, _T_173)
node _T_175 = and(en_13, delegable_13)
node _T_176 = and(_T_175, delegate)
node _en_T_84 = and(supported_interrupts, UInt<15>(0h4000))
node _en_T_85 = neq(_en_T_84, UInt<1>(0h0))
node _en_T_86 = and(exception, _en_T_85)
node _en_T_87 = add(UInt<64>(0h8000000000000000), UInt<4>(0he))
node _en_T_88 = tail(_en_T_87, 1)
node _en_T_89 = eq(cause, _en_T_88)
node en_14 = and(_en_T_86, _en_T_89)
node _delegable_T_14 = and(delegable_interrupts, UInt<15>(0h4000))
node delegable_14 = neq(_delegable_T_14, UInt<1>(0h0))
node _T_177 = eq(delegate, UInt<1>(0h0))
node _T_178 = and(en_14, _T_177)
node _T_179 = and(en_14, delegable_14)
node _T_180 = and(_T_179, delegate)
node _en_T_90 = and(supported_interrupts, UInt<16>(0h8000))
node _en_T_91 = neq(_en_T_90, UInt<1>(0h0))
node _en_T_92 = and(exception, _en_T_91)
node _en_T_93 = add(UInt<64>(0h8000000000000000), UInt<4>(0hf))
node _en_T_94 = tail(_en_T_93, 1)
node _en_T_95 = eq(cause, _en_T_94)
node en_15 = and(_en_T_92, _en_T_95)
node _delegable_T_15 = and(delegable_interrupts, UInt<16>(0h8000))
node delegable_15 = neq(_delegable_T_15, UInt<1>(0h0))
node _T_181 = eq(delegate, UInt<1>(0h0))
node _T_182 = and(en_15, _T_181)
node _T_183 = and(en_15, delegable_15)
node _T_184 = and(_T_183, delegate)
node _en_T_96 = eq(cause, UInt<1>(0h0))
node en_16 = and(exception, _en_T_96)
node _delegable_T_16 = and(UInt<16>(0hb15d), UInt<1>(0h1))
node delegable_16 = neq(_delegable_T_16, UInt<1>(0h0))
node _T_185 = eq(delegate, UInt<1>(0h0))
node _T_186 = and(en_16, _T_185)
node _T_187 = and(en_16, delegable_16)
node _T_188 = and(_T_187, delegate)
node _en_T_97 = eq(cause, UInt<1>(0h1))
node en_17 = and(exception, _en_T_97)
node _delegable_T_17 = and(UInt<16>(0hb15d), UInt<2>(0h2))
node delegable_17 = neq(_delegable_T_17, UInt<1>(0h0))
node _T_189 = eq(delegate, UInt<1>(0h0))
node _T_190 = and(en_17, _T_189)
node _T_191 = and(en_17, delegable_17)
node _T_192 = and(_T_191, delegate)
node _en_T_98 = eq(cause, UInt<2>(0h2))
node en_18 = and(exception, _en_T_98)
node _delegable_T_18 = and(UInt<16>(0hb15d), UInt<3>(0h4))
node delegable_18 = neq(_delegable_T_18, UInt<1>(0h0))
node _T_193 = eq(delegate, UInt<1>(0h0))
node _T_194 = and(en_18, _T_193)
node _T_195 = and(en_18, delegable_18)
node _T_196 = and(_T_195, delegate)
node _en_T_99 = eq(cause, UInt<2>(0h3))
node en_19 = and(exception, _en_T_99)
node _delegable_T_19 = and(UInt<16>(0hb15d), UInt<4>(0h8))
node delegable_19 = neq(_delegable_T_19, UInt<1>(0h0))
node _T_197 = eq(delegate, UInt<1>(0h0))
node _T_198 = and(en_19, _T_197)
node _T_199 = and(en_19, delegable_19)
node _T_200 = and(_T_199, delegate)
node _en_T_100 = eq(cause, UInt<3>(0h4))
node en_20 = and(exception, _en_T_100)
node _delegable_T_20 = and(UInt<16>(0hb15d), UInt<5>(0h10))
node delegable_20 = neq(_delegable_T_20, UInt<1>(0h0))
node _T_201 = eq(delegate, UInt<1>(0h0))
node _T_202 = and(en_20, _T_201)
node _T_203 = and(en_20, delegable_20)
node _T_204 = and(_T_203, delegate)
node _en_T_101 = eq(cause, UInt<3>(0h5))
node en_21 = and(exception, _en_T_101)
node _delegable_T_21 = and(UInt<16>(0hb15d), UInt<6>(0h20))
node delegable_21 = neq(_delegable_T_21, UInt<1>(0h0))
node _T_205 = eq(delegate, UInt<1>(0h0))
node _T_206 = and(en_21, _T_205)
node _T_207 = and(en_21, delegable_21)
node _T_208 = and(_T_207, delegate)
node _en_T_102 = eq(cause, UInt<3>(0h6))
node en_22 = and(exception, _en_T_102)
node _delegable_T_22 = and(UInt<16>(0hb15d), UInt<7>(0h40))
node delegable_22 = neq(_delegable_T_22, UInt<1>(0h0))
node _T_209 = eq(delegate, UInt<1>(0h0))
node _T_210 = and(en_22, _T_209)
node _T_211 = and(en_22, delegable_22)
node _T_212 = and(_T_211, delegate)
node _en_T_103 = eq(cause, UInt<3>(0h7))
node en_23 = and(exception, _en_T_103)
node _delegable_T_23 = and(UInt<16>(0hb15d), UInt<8>(0h80))
node delegable_23 = neq(_delegable_T_23, UInt<1>(0h0))
node _T_213 = eq(delegate, UInt<1>(0h0))
node _T_214 = and(en_23, _T_213)
node _T_215 = and(en_23, delegable_23)
node _T_216 = and(_T_215, delegate)
node _en_T_104 = eq(cause, UInt<4>(0h8))
node en_24 = and(exception, _en_T_104)
node _delegable_T_24 = and(UInt<16>(0hb15d), UInt<9>(0h100))
node delegable_24 = neq(_delegable_T_24, UInt<1>(0h0))
node _T_217 = eq(delegate, UInt<1>(0h0))
node _T_218 = and(en_24, _T_217)
node _T_219 = and(en_24, delegable_24)
node _T_220 = and(_T_219, delegate)
node _en_T_105 = eq(cause, UInt<4>(0h9))
node en_25 = and(exception, _en_T_105)
node _delegable_T_25 = and(UInt<16>(0hb15d), UInt<10>(0h200))
node delegable_25 = neq(_delegable_T_25, UInt<1>(0h0))
node _T_221 = eq(delegate, UInt<1>(0h0))
node _T_222 = and(en_25, _T_221)
node _T_223 = and(en_25, delegable_25)
node _T_224 = and(_T_223, delegate)
node _en_T_106 = eq(cause, UInt<4>(0hb))
node en_26 = and(exception, _en_T_106)
node _delegable_T_26 = and(UInt<16>(0hb15d), UInt<12>(0h800))
node delegable_26 = neq(_delegable_T_26, UInt<1>(0h0))
node _T_225 = eq(delegate, UInt<1>(0h0))
node _T_226 = and(en_26, _T_225)
node _T_227 = and(en_26, delegable_26)
node _T_228 = and(_T_227, delegate)
node _en_T_107 = eq(cause, UInt<4>(0hc))
node en_27 = and(exception, _en_T_107)
node _delegable_T_27 = and(UInt<16>(0hb15d), UInt<13>(0h1000))
node delegable_27 = neq(_delegable_T_27, UInt<1>(0h0))
node _T_229 = eq(delegate, UInt<1>(0h0))
node _T_230 = and(en_27, _T_229)
node _T_231 = and(en_27, delegable_27)
node _T_232 = and(_T_231, delegate)
node _en_T_108 = eq(cause, UInt<4>(0hd))
node en_28 = and(exception, _en_T_108)
node _delegable_T_28 = and(UInt<16>(0hb15d), UInt<14>(0h2000))
node delegable_28 = neq(_delegable_T_28, UInt<1>(0h0))
node _T_233 = eq(delegate, UInt<1>(0h0))
node _T_234 = and(en_28, _T_233)
node _T_235 = and(en_28, delegable_28)
node _T_236 = and(_T_235, delegate)
node _en_T_109 = eq(cause, UInt<4>(0hf))
node en_29 = and(exception, _en_T_109)
node _delegable_T_29 = and(UInt<16>(0hb15d), UInt<16>(0h8000))
node delegable_29 = neq(_delegable_T_29, UInt<1>(0h0))
node _T_237 = eq(delegate, UInt<1>(0h0))
node _T_238 = and(en_29, _T_237)
node _T_239 = and(en_29, delegable_29)
node _T_240 = and(_T_239, delegate)
when insn_ret :
wire ret_prv : UInt
invalidate ret_prv
node _T_241 = bits(io.rw.addr, 9, 9)
node _T_242 = eq(_T_241, UInt<1>(0h0))
node _T_243 = and(UInt<1>(0h1), _T_242)
when _T_243 :
node _T_244 = eq(reg_mstatus.v, UInt<1>(0h0))
when _T_244 :
connect reg_mstatus.sie, reg_mstatus.spie
connect reg_mstatus.spie, UInt<1>(0h1)
connect reg_mstatus.spp, UInt<1>(0h0)
connect ret_prv, reg_mstatus.spp
node _reg_mstatus_v_T = and(UInt<1>(0h0), reg_hstatus.spv)
connect reg_mstatus.v, _reg_mstatus_v_T
node _io_evec_T = not(reg_sepc)
node _io_evec_T_1 = bits(reg_misa, 2, 2)
node _io_evec_T_2 = mux(_io_evec_T_1, UInt<1>(0h1), UInt<2>(0h3))
node _io_evec_T_3 = or(_io_evec_T, _io_evec_T_2)
node _io_evec_T_4 = not(_io_evec_T_3)
connect io.evec, _io_evec_T_4
connect reg_hstatus.spv, UInt<1>(0h0)
else :
connect reg_vsstatus.sie, reg_vsstatus.spie
connect reg_vsstatus.spie, UInt<1>(0h1)
connect reg_vsstatus.spp, UInt<1>(0h0)
connect ret_prv, reg_vsstatus.spp
connect reg_mstatus.v, UInt<1>(0h0)
node _io_evec_T_5 = not(reg_vsepc)
node _io_evec_T_6 = bits(reg_misa, 2, 2)
node _io_evec_T_7 = mux(_io_evec_T_6, UInt<1>(0h1), UInt<2>(0h3))
node _io_evec_T_8 = or(_io_evec_T_5, _io_evec_T_7)
node _io_evec_T_9 = not(_io_evec_T_8)
connect io.evec, _io_evec_T_9
else :
node _T_245 = bits(io.rw.addr, 10, 10)
node _T_246 = and(UInt<1>(0h1), _T_245)
node _T_247 = bits(io.rw.addr, 7, 7)
node _T_248 = and(_T_246, _T_247)
when _T_248 :
connect ret_prv, reg_dcsr.prv
node _reg_mstatus_v_T_1 = and(UInt<1>(0h0), reg_dcsr.v)
node _reg_mstatus_v_T_2 = leq(reg_dcsr.prv, UInt<1>(0h1))
node _reg_mstatus_v_T_3 = and(_reg_mstatus_v_T_1, _reg_mstatus_v_T_2)
connect reg_mstatus.v, _reg_mstatus_v_T_3
connect reg_debug, UInt<1>(0h0)
node _io_evec_T_10 = not(reg_dpc)
node _io_evec_T_11 = bits(reg_misa, 2, 2)
node _io_evec_T_12 = mux(_io_evec_T_11, UInt<1>(0h1), UInt<2>(0h3))
node _io_evec_T_13 = or(_io_evec_T_10, _io_evec_T_12)
node _io_evec_T_14 = not(_io_evec_T_13)
connect io.evec, _io_evec_T_14
else :
node _T_249 = bits(io.rw.addr, 10, 10)
node _T_250 = and(UInt<1>(0h0), _T_249)
node _T_251 = bits(io.rw.addr, 7, 7)
node _T_252 = eq(_T_251, UInt<1>(0h0))
node _T_253 = and(_T_250, _T_252)
when _T_253 :
connect ret_prv, reg_mnstatus.mpp
node _reg_mstatus_v_T_4 = and(UInt<1>(0h0), reg_mnstatus.mpv)
node _reg_mstatus_v_T_5 = leq(reg_mnstatus.mpp, UInt<1>(0h1))
node _reg_mstatus_v_T_6 = and(_reg_mstatus_v_T_4, _reg_mstatus_v_T_5)
connect reg_mstatus.v, _reg_mstatus_v_T_6
connect reg_rnmie, UInt<1>(0h1)
node _io_evec_T_15 = not(reg_mnepc)
node _io_evec_T_16 = bits(reg_misa, 2, 2)
node _io_evec_T_17 = mux(_io_evec_T_16, UInt<1>(0h1), UInt<2>(0h3))
node _io_evec_T_18 = or(_io_evec_T_15, _io_evec_T_17)
node _io_evec_T_19 = not(_io_evec_T_18)
connect io.evec, _io_evec_T_19
else :
connect reg_mstatus.mie, reg_mstatus.mpie
connect reg_mstatus.mpie, UInt<1>(0h1)
node _reg_mstatus_mpp_T = eq(UInt<1>(0h0), UInt<2>(0h2))
node _reg_mstatus_mpp_T_1 = mux(_reg_mstatus_mpp_T, UInt<1>(0h0), UInt<1>(0h0))
connect reg_mstatus.mpp, _reg_mstatus_mpp_T_1
connect reg_mstatus.mpv, UInt<1>(0h0)
connect ret_prv, reg_mstatus.mpp
node _reg_mstatus_v_T_7 = and(UInt<1>(0h0), reg_mstatus.mpv)
node _reg_mstatus_v_T_8 = leq(reg_mstatus.mpp, UInt<1>(0h1))
node _reg_mstatus_v_T_9 = and(_reg_mstatus_v_T_7, _reg_mstatus_v_T_8)
connect reg_mstatus.v, _reg_mstatus_v_T_9
node _io_evec_T_20 = not(reg_mepc)
node _io_evec_T_21 = bits(reg_misa, 2, 2)
node _io_evec_T_22 = mux(_io_evec_T_21, UInt<1>(0h1), UInt<2>(0h3))
node _io_evec_T_23 = or(_io_evec_T_20, _io_evec_T_22)
node _io_evec_T_24 = not(_io_evec_T_23)
connect io.evec, _io_evec_T_24
connect new_prv, ret_prv
node _T_254 = leq(ret_prv, UInt<1>(0h1))
node _T_255 = and(UInt<1>(0h1), _T_254)
when _T_255 :
connect reg_mstatus.mprv, UInt<1>(0h0)
connect io.time, value_1
node _io_csr_stall_T = or(reg_wfi, io.status.cease)
connect io.csr_stall, _io_csr_stall_T
regreset io_status_cease_r : UInt<1>, clock, reset, UInt<1>(0h0)
when insn_cease :
connect io_status_cease_r, UInt<1>(0h1)
connect io.status.cease, io_status_cease_r
connect io.status.wfi, reg_wfi
connect io.customCSRs[0].wen, UInt<1>(0h0)
connect io.customCSRs[0].wdata, wdata
connect io.customCSRs[0].value, reg_custom_0
connect io.customCSRs[1].wen, UInt<1>(0h0)
connect io.customCSRs[1].wdata, wdata
connect io.customCSRs[1].value, reg_custom_1
connect io.customCSRs[2].wen, UInt<1>(0h0)
connect io.customCSRs[2].wdata, wdata
connect io.customCSRs[2].value, reg_custom_2
connect io.customCSRs[3].wen, UInt<1>(0h0)
connect io.customCSRs[3].wdata, wdata
connect io.customCSRs[3].value, reg_custom_3
node _io_rw_rdata_T = mux(decoded_addr_97_2, reg_tselect, UInt<1>(0h0))
node _io_rw_rdata_T_1 = mux(decoded_addr_55_2, read_mapping_1_2, UInt<1>(0h0))
node _io_rw_rdata_T_2 = mux(decoded_addr_10_2, read_mapping_2_2, UInt<1>(0h0))
node _io_rw_rdata_T_3 = mux(decoded_addr_118_2, read_mapping_3_2, UInt<1>(0h0))
node _io_rw_rdata_T_4 = mux(decoded_addr_94_2, reg_misa, UInt<1>(0h0))
node _io_rw_rdata_T_5 = mux(decoded_addr_100_2, read_mstatus, UInt<1>(0h0))
node _io_rw_rdata_T_6 = mux(decoded_addr_72_2, read_mtvec, UInt<1>(0h0))
node _io_rw_rdata_T_7 = mux(decoded_addr_108_2, read_mip, UInt<1>(0h0))
node _io_rw_rdata_T_8 = mux(decoded_addr_76_2, reg_mie, UInt<1>(0h0))
node _io_rw_rdata_T_9 = mux(decoded_addr_129_2, reg_mscratch, UInt<1>(0h0))
node _io_rw_rdata_T_10 = mux(decoded_addr_132_2, read_mapping_10_2, UInt<1>(0h0))
node _io_rw_rdata_T_11 = mux(decoded_addr_136_2, read_mapping_11_2, UInt<1>(0h0))
node _io_rw_rdata_T_12 = mux(decoded_addr_29_2, reg_mcause, UInt<1>(0h0))
node _io_rw_rdata_T_13 = mux(decoded_addr_131_2, io.hartid, UInt<1>(0h0))
node _io_rw_rdata_T_14 = mux(decoded_addr_49_2, debug_csrs_0_2, UInt<1>(0h0))
node _io_rw_rdata_T_15 = mux(decoded_addr_89_2, debug_csrs_1_2, UInt<1>(0h0))
node _io_rw_rdata_T_16 = mux(decoded_addr_57_2, reg_dscratch0, UInt<1>(0h0))
node _io_rw_rdata_T_17 = mux(decoded_addr_36_2, reg_fflags, UInt<1>(0h0))
node _io_rw_rdata_T_18 = mux(decoded_addr_68_2, reg_frm, UInt<1>(0h0))
node _io_rw_rdata_T_19 = mux(decoded_addr_99_2, read_fcsr, UInt<1>(0h0))
node _io_rw_rdata_T_20 = mux(decoded_addr_130_2, reg_mcountinhibit, UInt<1>(0h0))
node _io_rw_rdata_T_21 = mux(decoded_addr_103_2, value_1, UInt<1>(0h0))
node _io_rw_rdata_T_22 = mux(decoded_addr_121_2, value, UInt<1>(0h0))
node _io_rw_rdata_T_23 = mux(decoded_addr_146_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_24 = mux(decoded_addr_17_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_25 = mux(decoded_addr_27_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_26 = mux(decoded_addr_83_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_27 = mux(decoded_addr_52_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_28 = mux(decoded_addr_144_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_29 = mux(decoded_addr_70_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_30 = mux(decoded_addr_111_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_31 = mux(decoded_addr_82_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_32 = mux(decoded_addr_31_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_33 = mux(decoded_addr_0_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_34 = mux(decoded_addr_59_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_35 = mux(decoded_addr_138_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_36 = mux(decoded_addr_126_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_37 = mux(decoded_addr_74_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_38 = mux(decoded_addr_116_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_39 = mux(decoded_addr_90_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_40 = mux(decoded_addr_113_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_41 = mux(decoded_addr_1_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_42 = mux(decoded_addr_16_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_43 = mux(decoded_addr_78_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_44 = mux(decoded_addr_39_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_45 = mux(decoded_addr_51_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_46 = mux(decoded_addr_109_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_47 = mux(decoded_addr_91_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_48 = mux(decoded_addr_81_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_49 = mux(decoded_addr_67_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_50 = mux(decoded_addr_105_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_51 = mux(decoded_addr_122_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_52 = mux(decoded_addr_24_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_53 = mux(decoded_addr_124_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_54 = mux(decoded_addr_26_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_55 = mux(decoded_addr_128_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_56 = mux(decoded_addr_7_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_57 = mux(decoded_addr_62_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_58 = mux(decoded_addr_77_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_59 = mux(decoded_addr_46_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_60 = mux(decoded_addr_112_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_61 = mux(decoded_addr_60_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_62 = mux(decoded_addr_92_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_63 = mux(decoded_addr_148_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_64 = mux(decoded_addr_14_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_65 = mux(decoded_addr_21_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_66 = mux(decoded_addr_33_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_67 = mux(decoded_addr_19_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_68 = mux(decoded_addr_133_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_69 = mux(decoded_addr_149_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_70 = mux(decoded_addr_50_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_71 = mux(decoded_addr_75_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_72 = mux(decoded_addr_102_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_73 = mux(decoded_addr_84_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_74 = mux(decoded_addr_45_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_75 = mux(decoded_addr_64_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_76 = mux(decoded_addr_120_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_77 = mux(decoded_addr_30_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_78 = mux(decoded_addr_5_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_79 = mux(decoded_addr_32_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_80 = mux(decoded_addr_143_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_81 = mux(decoded_addr_117_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_82 = mux(decoded_addr_63_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_83 = mux(decoded_addr_107_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_84 = mux(decoded_addr_88_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_85 = mux(decoded_addr_114_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_86 = mux(decoded_addr_73_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_87 = mux(decoded_addr_53_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_88 = mux(decoded_addr_147_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_89 = mux(decoded_addr_41_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_90 = mux(decoded_addr_56_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_91 = mux(decoded_addr_37_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_92 = mux(decoded_addr_79_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_93 = mux(decoded_addr_96_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_94 = mux(decoded_addr_4_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_95 = mux(decoded_addr_101_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_96 = mux(decoded_addr_119_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_97 = mux(decoded_addr_22_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_98 = mux(decoded_addr_139_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_99 = mux(decoded_addr_11_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_100 = mux(decoded_addr_134_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_101 = mux(decoded_addr_12_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_102 = mux(decoded_addr_65_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_103 = mux(decoded_addr_86_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_104 = mux(decoded_addr_47_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_105 = mux(decoded_addr_106_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_106 = mux(decoded_addr_58_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_107 = mux(decoded_addr_87_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_108 = mux(decoded_addr_142_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_109 = mux(decoded_addr_13_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_110 = mux(decoded_addr_35_2, read_mcounteren, UInt<1>(0h0))
node _io_rw_rdata_T_111 = mux(decoded_addr_2_2, value_1, UInt<1>(0h0))
node _io_rw_rdata_T_112 = mux(decoded_addr_66_2, value, UInt<1>(0h0))
node _io_rw_rdata_T_113 = mux(decoded_addr_42_2, _T_19, UInt<1>(0h0))
node _io_rw_rdata_T_114 = mux(decoded_addr_61_2, _T_21, UInt<1>(0h0))
node _io_rw_rdata_T_115 = mux(decoded_addr_48_2, read_sip, UInt<1>(0h0))
node _io_rw_rdata_T_116 = mux(decoded_addr_44_2, read_sie, UInt<1>(0h0))
node _io_rw_rdata_T_117 = mux(decoded_addr_15_2, reg_sscratch, UInt<1>(0h0))
node _io_rw_rdata_T_118 = mux(decoded_addr_145_2, reg_scause, UInt<1>(0h0))
node _io_rw_rdata_T_119 = mux(decoded_addr_93_2, _T_24, UInt<1>(0h0))
node _io_rw_rdata_T_120 = mux(decoded_addr_6_2, _T_25, UInt<1>(0h0))
node _io_rw_rdata_T_121 = mux(decoded_addr_28_2, _T_33, UInt<1>(0h0))
node _io_rw_rdata_T_122 = mux(decoded_addr_25_2, read_stvec, UInt<1>(0h0))
node _io_rw_rdata_T_123 = mux(decoded_addr_137_2, read_scounteren, UInt<1>(0h0))
node _io_rw_rdata_T_124 = mux(decoded_addr_123_2, read_mideleg, UInt<1>(0h0))
node _io_rw_rdata_T_125 = mux(decoded_addr_23_2, read_medeleg, UInt<1>(0h0))
node _io_rw_rdata_T_126 = mux(decoded_addr_69_2, _T_34, UInt<1>(0h0))
node _io_rw_rdata_T_127 = mux(decoded_addr_141_2, _T_43, UInt<1>(0h0))
node _io_rw_rdata_T_128 = mux(decoded_addr_9_2, _T_52, UInt<1>(0h0))
node _io_rw_rdata_T_129 = mux(decoded_addr_104_2, reg_pmp[0].addr, UInt<1>(0h0))
node _io_rw_rdata_T_130 = mux(decoded_addr_8_2, reg_pmp[1].addr, UInt<1>(0h0))
node _io_rw_rdata_T_131 = mux(decoded_addr_125_2, reg_pmp[2].addr, UInt<1>(0h0))
node _io_rw_rdata_T_132 = mux(decoded_addr_85_2, reg_pmp[3].addr, UInt<1>(0h0))
node _io_rw_rdata_T_133 = mux(decoded_addr_54_2, reg_pmp[4].addr, UInt<1>(0h0))
node _io_rw_rdata_T_134 = mux(decoded_addr_20_2, reg_pmp[5].addr, UInt<1>(0h0))
node _io_rw_rdata_T_135 = mux(decoded_addr_135_2, reg_pmp[6].addr, UInt<1>(0h0))
node _io_rw_rdata_T_136 = mux(decoded_addr_115_2, reg_pmp[7].addr, UInt<1>(0h0))
node _io_rw_rdata_T_137 = mux(decoded_addr_43_2, read_pmp_15.addr, UInt<1>(0h0))
node _io_rw_rdata_T_138 = mux(decoded_addr_71_2, read_pmp_15.addr, UInt<1>(0h0))
node _io_rw_rdata_T_139 = mux(decoded_addr_110_2, read_pmp_15.addr, UInt<1>(0h0))
node _io_rw_rdata_T_140 = mux(decoded_addr_140_2, read_pmp_15.addr, UInt<1>(0h0))
node _io_rw_rdata_T_141 = mux(decoded_addr_34_2, read_pmp_15.addr, UInt<1>(0h0))
node _io_rw_rdata_T_142 = mux(decoded_addr_40_2, read_pmp_15.addr, UInt<1>(0h0))
node _io_rw_rdata_T_143 = mux(decoded_addr_80_2, read_pmp_15.addr, UInt<1>(0h0))
node _io_rw_rdata_T_144 = mux(decoded_addr_98_2, read_pmp_15.addr, UInt<1>(0h0))
node _io_rw_rdata_T_145 = mux(decoded_addr_18_2, reg_custom_0, UInt<1>(0h0))
node _io_rw_rdata_T_146 = mux(decoded_addr_3_2, reg_custom_1, UInt<1>(0h0))
node _io_rw_rdata_T_147 = mux(decoded_addr_38_2, reg_custom_2, UInt<1>(0h0))
node _io_rw_rdata_T_148 = mux(decoded_addr_127_2, reg_custom_3, UInt<1>(0h0))
node _io_rw_rdata_T_149 = mux(decoded_addr_95_2, UInt<1>(0h0), UInt<1>(0h0))
node _io_rw_rdata_T_150 = or(_io_rw_rdata_T, _io_rw_rdata_T_1)
node _io_rw_rdata_T_151 = or(_io_rw_rdata_T_150, _io_rw_rdata_T_2)
node _io_rw_rdata_T_152 = or(_io_rw_rdata_T_151, _io_rw_rdata_T_3)
node _io_rw_rdata_T_153 = or(_io_rw_rdata_T_152, _io_rw_rdata_T_4)
node _io_rw_rdata_T_154 = or(_io_rw_rdata_T_153, _io_rw_rdata_T_5)
node _io_rw_rdata_T_155 = or(_io_rw_rdata_T_154, _io_rw_rdata_T_6)
node _io_rw_rdata_T_156 = or(_io_rw_rdata_T_155, _io_rw_rdata_T_7)
node _io_rw_rdata_T_157 = or(_io_rw_rdata_T_156, _io_rw_rdata_T_8)
node _io_rw_rdata_T_158 = or(_io_rw_rdata_T_157, _io_rw_rdata_T_9)
node _io_rw_rdata_T_159 = or(_io_rw_rdata_T_158, _io_rw_rdata_T_10)
node _io_rw_rdata_T_160 = or(_io_rw_rdata_T_159, _io_rw_rdata_T_11)
node _io_rw_rdata_T_161 = or(_io_rw_rdata_T_160, _io_rw_rdata_T_12)
node _io_rw_rdata_T_162 = or(_io_rw_rdata_T_161, _io_rw_rdata_T_13)
node _io_rw_rdata_T_163 = or(_io_rw_rdata_T_162, _io_rw_rdata_T_14)
node _io_rw_rdata_T_164 = or(_io_rw_rdata_T_163, _io_rw_rdata_T_15)
node _io_rw_rdata_T_165 = or(_io_rw_rdata_T_164, _io_rw_rdata_T_16)
node _io_rw_rdata_T_166 = or(_io_rw_rdata_T_165, _io_rw_rdata_T_17)
node _io_rw_rdata_T_167 = or(_io_rw_rdata_T_166, _io_rw_rdata_T_18)
node _io_rw_rdata_T_168 = or(_io_rw_rdata_T_167, _io_rw_rdata_T_19)
node _io_rw_rdata_T_169 = or(_io_rw_rdata_T_168, _io_rw_rdata_T_20)
node _io_rw_rdata_T_170 = or(_io_rw_rdata_T_169, _io_rw_rdata_T_21)
node _io_rw_rdata_T_171 = or(_io_rw_rdata_T_170, _io_rw_rdata_T_22)
node _io_rw_rdata_T_172 = or(_io_rw_rdata_T_171, _io_rw_rdata_T_23)
node _io_rw_rdata_T_173 = or(_io_rw_rdata_T_172, _io_rw_rdata_T_24)
node _io_rw_rdata_T_174 = or(_io_rw_rdata_T_173, _io_rw_rdata_T_25)
node _io_rw_rdata_T_175 = or(_io_rw_rdata_T_174, _io_rw_rdata_T_26)
node _io_rw_rdata_T_176 = or(_io_rw_rdata_T_175, _io_rw_rdata_T_27)
node _io_rw_rdata_T_177 = or(_io_rw_rdata_T_176, _io_rw_rdata_T_28)
node _io_rw_rdata_T_178 = or(_io_rw_rdata_T_177, _io_rw_rdata_T_29)
node _io_rw_rdata_T_179 = or(_io_rw_rdata_T_178, _io_rw_rdata_T_30)
node _io_rw_rdata_T_180 = or(_io_rw_rdata_T_179, _io_rw_rdata_T_31)
node _io_rw_rdata_T_181 = or(_io_rw_rdata_T_180, _io_rw_rdata_T_32)
node _io_rw_rdata_T_182 = or(_io_rw_rdata_T_181, _io_rw_rdata_T_33)
node _io_rw_rdata_T_183 = or(_io_rw_rdata_T_182, _io_rw_rdata_T_34)
node _io_rw_rdata_T_184 = or(_io_rw_rdata_T_183, _io_rw_rdata_T_35)
node _io_rw_rdata_T_185 = or(_io_rw_rdata_T_184, _io_rw_rdata_T_36)
node _io_rw_rdata_T_186 = or(_io_rw_rdata_T_185, _io_rw_rdata_T_37)
node _io_rw_rdata_T_187 = or(_io_rw_rdata_T_186, _io_rw_rdata_T_38)
node _io_rw_rdata_T_188 = or(_io_rw_rdata_T_187, _io_rw_rdata_T_39)
node _io_rw_rdata_T_189 = or(_io_rw_rdata_T_188, _io_rw_rdata_T_40)
node _io_rw_rdata_T_190 = or(_io_rw_rdata_T_189, _io_rw_rdata_T_41)
node _io_rw_rdata_T_191 = or(_io_rw_rdata_T_190, _io_rw_rdata_T_42)
node _io_rw_rdata_T_192 = or(_io_rw_rdata_T_191, _io_rw_rdata_T_43)
node _io_rw_rdata_T_193 = or(_io_rw_rdata_T_192, _io_rw_rdata_T_44)
node _io_rw_rdata_T_194 = or(_io_rw_rdata_T_193, _io_rw_rdata_T_45)
node _io_rw_rdata_T_195 = or(_io_rw_rdata_T_194, _io_rw_rdata_T_46)
node _io_rw_rdata_T_196 = or(_io_rw_rdata_T_195, _io_rw_rdata_T_47)
node _io_rw_rdata_T_197 = or(_io_rw_rdata_T_196, _io_rw_rdata_T_48)
node _io_rw_rdata_T_198 = or(_io_rw_rdata_T_197, _io_rw_rdata_T_49)
node _io_rw_rdata_T_199 = or(_io_rw_rdata_T_198, _io_rw_rdata_T_50)
node _io_rw_rdata_T_200 = or(_io_rw_rdata_T_199, _io_rw_rdata_T_51)
node _io_rw_rdata_T_201 = or(_io_rw_rdata_T_200, _io_rw_rdata_T_52)
node _io_rw_rdata_T_202 = or(_io_rw_rdata_T_201, _io_rw_rdata_T_53)
node _io_rw_rdata_T_203 = or(_io_rw_rdata_T_202, _io_rw_rdata_T_54)
node _io_rw_rdata_T_204 = or(_io_rw_rdata_T_203, _io_rw_rdata_T_55)
node _io_rw_rdata_T_205 = or(_io_rw_rdata_T_204, _io_rw_rdata_T_56)
node _io_rw_rdata_T_206 = or(_io_rw_rdata_T_205, _io_rw_rdata_T_57)
node _io_rw_rdata_T_207 = or(_io_rw_rdata_T_206, _io_rw_rdata_T_58)
node _io_rw_rdata_T_208 = or(_io_rw_rdata_T_207, _io_rw_rdata_T_59)
node _io_rw_rdata_T_209 = or(_io_rw_rdata_T_208, _io_rw_rdata_T_60)
node _io_rw_rdata_T_210 = or(_io_rw_rdata_T_209, _io_rw_rdata_T_61)
node _io_rw_rdata_T_211 = or(_io_rw_rdata_T_210, _io_rw_rdata_T_62)
node _io_rw_rdata_T_212 = or(_io_rw_rdata_T_211, _io_rw_rdata_T_63)
node _io_rw_rdata_T_213 = or(_io_rw_rdata_T_212, _io_rw_rdata_T_64)
node _io_rw_rdata_T_214 = or(_io_rw_rdata_T_213, _io_rw_rdata_T_65)
node _io_rw_rdata_T_215 = or(_io_rw_rdata_T_214, _io_rw_rdata_T_66)
node _io_rw_rdata_T_216 = or(_io_rw_rdata_T_215, _io_rw_rdata_T_67)
node _io_rw_rdata_T_217 = or(_io_rw_rdata_T_216, _io_rw_rdata_T_68)
node _io_rw_rdata_T_218 = or(_io_rw_rdata_T_217, _io_rw_rdata_T_69)
node _io_rw_rdata_T_219 = or(_io_rw_rdata_T_218, _io_rw_rdata_T_70)
node _io_rw_rdata_T_220 = or(_io_rw_rdata_T_219, _io_rw_rdata_T_71)
node _io_rw_rdata_T_221 = or(_io_rw_rdata_T_220, _io_rw_rdata_T_72)
node _io_rw_rdata_T_222 = or(_io_rw_rdata_T_221, _io_rw_rdata_T_73)
node _io_rw_rdata_T_223 = or(_io_rw_rdata_T_222, _io_rw_rdata_T_74)
node _io_rw_rdata_T_224 = or(_io_rw_rdata_T_223, _io_rw_rdata_T_75)
node _io_rw_rdata_T_225 = or(_io_rw_rdata_T_224, _io_rw_rdata_T_76)
node _io_rw_rdata_T_226 = or(_io_rw_rdata_T_225, _io_rw_rdata_T_77)
node _io_rw_rdata_T_227 = or(_io_rw_rdata_T_226, _io_rw_rdata_T_78)
node _io_rw_rdata_T_228 = or(_io_rw_rdata_T_227, _io_rw_rdata_T_79)
node _io_rw_rdata_T_229 = or(_io_rw_rdata_T_228, _io_rw_rdata_T_80)
node _io_rw_rdata_T_230 = or(_io_rw_rdata_T_229, _io_rw_rdata_T_81)
node _io_rw_rdata_T_231 = or(_io_rw_rdata_T_230, _io_rw_rdata_T_82)
node _io_rw_rdata_T_232 = or(_io_rw_rdata_T_231, _io_rw_rdata_T_83)
node _io_rw_rdata_T_233 = or(_io_rw_rdata_T_232, _io_rw_rdata_T_84)
node _io_rw_rdata_T_234 = or(_io_rw_rdata_T_233, _io_rw_rdata_T_85)
node _io_rw_rdata_T_235 = or(_io_rw_rdata_T_234, _io_rw_rdata_T_86)
node _io_rw_rdata_T_236 = or(_io_rw_rdata_T_235, _io_rw_rdata_T_87)
node _io_rw_rdata_T_237 = or(_io_rw_rdata_T_236, _io_rw_rdata_T_88)
node _io_rw_rdata_T_238 = or(_io_rw_rdata_T_237, _io_rw_rdata_T_89)
node _io_rw_rdata_T_239 = or(_io_rw_rdata_T_238, _io_rw_rdata_T_90)
node _io_rw_rdata_T_240 = or(_io_rw_rdata_T_239, _io_rw_rdata_T_91)
node _io_rw_rdata_T_241 = or(_io_rw_rdata_T_240, _io_rw_rdata_T_92)
node _io_rw_rdata_T_242 = or(_io_rw_rdata_T_241, _io_rw_rdata_T_93)
node _io_rw_rdata_T_243 = or(_io_rw_rdata_T_242, _io_rw_rdata_T_94)
node _io_rw_rdata_T_244 = or(_io_rw_rdata_T_243, _io_rw_rdata_T_95)
node _io_rw_rdata_T_245 = or(_io_rw_rdata_T_244, _io_rw_rdata_T_96)
node _io_rw_rdata_T_246 = or(_io_rw_rdata_T_245, _io_rw_rdata_T_97)
node _io_rw_rdata_T_247 = or(_io_rw_rdata_T_246, _io_rw_rdata_T_98)
node _io_rw_rdata_T_248 = or(_io_rw_rdata_T_247, _io_rw_rdata_T_99)
node _io_rw_rdata_T_249 = or(_io_rw_rdata_T_248, _io_rw_rdata_T_100)
node _io_rw_rdata_T_250 = or(_io_rw_rdata_T_249, _io_rw_rdata_T_101)
node _io_rw_rdata_T_251 = or(_io_rw_rdata_T_250, _io_rw_rdata_T_102)
node _io_rw_rdata_T_252 = or(_io_rw_rdata_T_251, _io_rw_rdata_T_103)
node _io_rw_rdata_T_253 = or(_io_rw_rdata_T_252, _io_rw_rdata_T_104)
node _io_rw_rdata_T_254 = or(_io_rw_rdata_T_253, _io_rw_rdata_T_105)
node _io_rw_rdata_T_255 = or(_io_rw_rdata_T_254, _io_rw_rdata_T_106)
node _io_rw_rdata_T_256 = or(_io_rw_rdata_T_255, _io_rw_rdata_T_107)
node _io_rw_rdata_T_257 = or(_io_rw_rdata_T_256, _io_rw_rdata_T_108)
node _io_rw_rdata_T_258 = or(_io_rw_rdata_T_257, _io_rw_rdata_T_109)
node _io_rw_rdata_T_259 = or(_io_rw_rdata_T_258, _io_rw_rdata_T_110)
node _io_rw_rdata_T_260 = or(_io_rw_rdata_T_259, _io_rw_rdata_T_111)
node _io_rw_rdata_T_261 = or(_io_rw_rdata_T_260, _io_rw_rdata_T_112)
node _io_rw_rdata_T_262 = or(_io_rw_rdata_T_261, _io_rw_rdata_T_113)
node _io_rw_rdata_T_263 = or(_io_rw_rdata_T_262, _io_rw_rdata_T_114)
node _io_rw_rdata_T_264 = or(_io_rw_rdata_T_263, _io_rw_rdata_T_115)
node _io_rw_rdata_T_265 = or(_io_rw_rdata_T_264, _io_rw_rdata_T_116)
node _io_rw_rdata_T_266 = or(_io_rw_rdata_T_265, _io_rw_rdata_T_117)
node _io_rw_rdata_T_267 = or(_io_rw_rdata_T_266, _io_rw_rdata_T_118)
node _io_rw_rdata_T_268 = or(_io_rw_rdata_T_267, _io_rw_rdata_T_119)
node _io_rw_rdata_T_269 = or(_io_rw_rdata_T_268, _io_rw_rdata_T_120)
node _io_rw_rdata_T_270 = or(_io_rw_rdata_T_269, _io_rw_rdata_T_121)
node _io_rw_rdata_T_271 = or(_io_rw_rdata_T_270, _io_rw_rdata_T_122)
node _io_rw_rdata_T_272 = or(_io_rw_rdata_T_271, _io_rw_rdata_T_123)
node _io_rw_rdata_T_273 = or(_io_rw_rdata_T_272, _io_rw_rdata_T_124)
node _io_rw_rdata_T_274 = or(_io_rw_rdata_T_273, _io_rw_rdata_T_125)
node _io_rw_rdata_T_275 = or(_io_rw_rdata_T_274, _io_rw_rdata_T_126)
node _io_rw_rdata_T_276 = or(_io_rw_rdata_T_275, _io_rw_rdata_T_127)
node _io_rw_rdata_T_277 = or(_io_rw_rdata_T_276, _io_rw_rdata_T_128)
node _io_rw_rdata_T_278 = or(_io_rw_rdata_T_277, _io_rw_rdata_T_129)
node _io_rw_rdata_T_279 = or(_io_rw_rdata_T_278, _io_rw_rdata_T_130)
node _io_rw_rdata_T_280 = or(_io_rw_rdata_T_279, _io_rw_rdata_T_131)
node _io_rw_rdata_T_281 = or(_io_rw_rdata_T_280, _io_rw_rdata_T_132)
node _io_rw_rdata_T_282 = or(_io_rw_rdata_T_281, _io_rw_rdata_T_133)
node _io_rw_rdata_T_283 = or(_io_rw_rdata_T_282, _io_rw_rdata_T_134)
node _io_rw_rdata_T_284 = or(_io_rw_rdata_T_283, _io_rw_rdata_T_135)
node _io_rw_rdata_T_285 = or(_io_rw_rdata_T_284, _io_rw_rdata_T_136)
node _io_rw_rdata_T_286 = or(_io_rw_rdata_T_285, _io_rw_rdata_T_137)
node _io_rw_rdata_T_287 = or(_io_rw_rdata_T_286, _io_rw_rdata_T_138)
node _io_rw_rdata_T_288 = or(_io_rw_rdata_T_287, _io_rw_rdata_T_139)
node _io_rw_rdata_T_289 = or(_io_rw_rdata_T_288, _io_rw_rdata_T_140)
node _io_rw_rdata_T_290 = or(_io_rw_rdata_T_289, _io_rw_rdata_T_141)
node _io_rw_rdata_T_291 = or(_io_rw_rdata_T_290, _io_rw_rdata_T_142)
node _io_rw_rdata_T_292 = or(_io_rw_rdata_T_291, _io_rw_rdata_T_143)
node _io_rw_rdata_T_293 = or(_io_rw_rdata_T_292, _io_rw_rdata_T_144)
node _io_rw_rdata_T_294 = or(_io_rw_rdata_T_293, _io_rw_rdata_T_145)
node _io_rw_rdata_T_295 = or(_io_rw_rdata_T_294, _io_rw_rdata_T_146)
node _io_rw_rdata_T_296 = or(_io_rw_rdata_T_295, _io_rw_rdata_T_147)
node _io_rw_rdata_T_297 = or(_io_rw_rdata_T_296, _io_rw_rdata_T_148)
node _io_rw_rdata_T_298 = or(_io_rw_rdata_T_297, _io_rw_rdata_T_149)
wire _io_rw_rdata_WIRE : UInt
connect _io_rw_rdata_WIRE, _io_rw_rdata_T_298
connect io.rw.rdata, _io_rw_rdata_WIRE
node _T_256 = andr(UInt<2>(0h1))
node _T_257 = eq(_T_256, UInt<1>(0h0))
when _T_257 :
node _T_258 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_259 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_260 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_261 = or(_T_258, _T_259)
node _T_262 = or(_T_261, _T_260)
node _T_263 = eq(io.rw.addr, UInt<11>(0h7a0))
node _T_264 = and(_T_262, _T_263)
else :
node _T_265 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_266 = eq(io.rw.addr, UInt<11>(0h7a0))
node _T_267 = and(_T_265, _T_266)
node _T_268 = andr(UInt<2>(0h1))
node _T_269 = eq(_T_268, UInt<1>(0h0))
when _T_269 :
node _T_270 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_271 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_272 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_273 = or(_T_270, _T_271)
node _T_274 = or(_T_273, _T_272)
node _T_275 = eq(io.rw.addr, UInt<11>(0h7a1))
node _T_276 = and(_T_274, _T_275)
else :
node _T_277 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_278 = eq(io.rw.addr, UInt<11>(0h7a1))
node _T_279 = and(_T_277, _T_278)
node _T_280 = andr(UInt<2>(0h1))
node _T_281 = eq(_T_280, UInt<1>(0h0))
when _T_281 :
node _T_282 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_283 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_284 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_285 = or(_T_282, _T_283)
node _T_286 = or(_T_285, _T_284)
node _T_287 = eq(io.rw.addr, UInt<11>(0h7a2))
node _T_288 = and(_T_286, _T_287)
else :
node _T_289 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_290 = eq(io.rw.addr, UInt<11>(0h7a2))
node _T_291 = and(_T_289, _T_290)
node _T_292 = andr(UInt<2>(0h1))
node _T_293 = eq(_T_292, UInt<1>(0h0))
when _T_293 :
node _T_294 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_295 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_296 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_297 = or(_T_294, _T_295)
node _T_298 = or(_T_297, _T_296)
node _T_299 = eq(io.rw.addr, UInt<11>(0h7a3))
node _T_300 = and(_T_298, _T_299)
else :
node _T_301 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_302 = eq(io.rw.addr, UInt<11>(0h7a3))
node _T_303 = and(_T_301, _T_302)
node _T_304 = andr(UInt<2>(0h0))
node _T_305 = eq(_T_304, UInt<1>(0h0))
when _T_305 :
node _T_306 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_307 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_308 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_309 = or(_T_306, _T_307)
node _T_310 = or(_T_309, _T_308)
node _T_311 = eq(io.rw.addr, UInt<10>(0h301))
node _T_312 = and(_T_310, _T_311)
else :
node _T_313 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_314 = eq(io.rw.addr, UInt<10>(0h301))
node _T_315 = and(_T_313, _T_314)
node _T_316 = andr(UInt<2>(0h0))
node _T_317 = eq(_T_316, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_319 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_320 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_321 = or(_T_318, _T_319)
node _T_322 = or(_T_321, _T_320)
node _T_323 = eq(io.rw.addr, UInt<10>(0h300))
node _T_324 = and(_T_322, _T_323)
else :
node _T_325 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_326 = eq(io.rw.addr, UInt<10>(0h300))
node _T_327 = and(_T_325, _T_326)
node _T_328 = andr(UInt<2>(0h0))
node _T_329 = eq(_T_328, UInt<1>(0h0))
when _T_329 :
node _T_330 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_331 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_332 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_333 = or(_T_330, _T_331)
node _T_334 = or(_T_333, _T_332)
node _T_335 = eq(io.rw.addr, UInt<10>(0h305))
node _T_336 = and(_T_334, _T_335)
else :
node _T_337 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_338 = eq(io.rw.addr, UInt<10>(0h305))
node _T_339 = and(_T_337, _T_338)
node _T_340 = andr(UInt<2>(0h0))
node _T_341 = eq(_T_340, UInt<1>(0h0))
when _T_341 :
node _T_342 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_343 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_344 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_345 = or(_T_342, _T_343)
node _T_346 = or(_T_345, _T_344)
node _T_347 = eq(io.rw.addr, UInt<10>(0h344))
node _T_348 = and(_T_346, _T_347)
else :
node _T_349 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_350 = eq(io.rw.addr, UInt<10>(0h344))
node _T_351 = and(_T_349, _T_350)
node _T_352 = andr(UInt<2>(0h0))
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_355 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_356 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_357 = or(_T_354, _T_355)
node _T_358 = or(_T_357, _T_356)
node _T_359 = eq(io.rw.addr, UInt<10>(0h304))
node _T_360 = and(_T_358, _T_359)
else :
node _T_361 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_362 = eq(io.rw.addr, UInt<10>(0h304))
node _T_363 = and(_T_361, _T_362)
node _T_364 = andr(UInt<2>(0h0))
node _T_365 = eq(_T_364, UInt<1>(0h0))
when _T_365 :
node _T_366 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_367 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_368 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_369 = or(_T_366, _T_367)
node _T_370 = or(_T_369, _T_368)
node _T_371 = eq(io.rw.addr, UInt<10>(0h340))
node _T_372 = and(_T_370, _T_371)
else :
node _T_373 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_374 = eq(io.rw.addr, UInt<10>(0h340))
node _T_375 = and(_T_373, _T_374)
node _T_376 = andr(UInt<2>(0h0))
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_379 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_380 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_381 = or(_T_378, _T_379)
node _T_382 = or(_T_381, _T_380)
node _T_383 = eq(io.rw.addr, UInt<10>(0h341))
node _T_384 = and(_T_382, _T_383)
else :
node _T_385 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_386 = eq(io.rw.addr, UInt<10>(0h341))
node _T_387 = and(_T_385, _T_386)
node _T_388 = andr(UInt<2>(0h0))
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_391 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_392 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_393 = or(_T_390, _T_391)
node _T_394 = or(_T_393, _T_392)
node _T_395 = eq(io.rw.addr, UInt<10>(0h343))
node _T_396 = and(_T_394, _T_395)
else :
node _T_397 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_398 = eq(io.rw.addr, UInt<10>(0h343))
node _T_399 = and(_T_397, _T_398)
node _T_400 = andr(UInt<2>(0h0))
node _T_401 = eq(_T_400, UInt<1>(0h0))
when _T_401 :
node _T_402 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_403 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_404 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_405 = or(_T_402, _T_403)
node _T_406 = or(_T_405, _T_404)
node _T_407 = eq(io.rw.addr, UInt<10>(0h342))
node _T_408 = and(_T_406, _T_407)
else :
node _T_409 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_410 = eq(io.rw.addr, UInt<10>(0h342))
node _T_411 = and(_T_409, _T_410)
node _T_412 = andr(UInt<2>(0h3))
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_415 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_416 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_417 = or(_T_414, _T_415)
node _T_418 = or(_T_417, _T_416)
node _T_419 = eq(io.rw.addr, UInt<12>(0hf14))
node _T_420 = and(_T_418, _T_419)
else :
node _T_421 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_422 = eq(io.rw.addr, UInt<12>(0hf14))
node _T_423 = and(_T_421, _T_422)
node _T_424 = andr(UInt<2>(0h1))
node _T_425 = eq(_T_424, UInt<1>(0h0))
when _T_425 :
node _T_426 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_427 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_428 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_429 = or(_T_426, _T_427)
node _T_430 = or(_T_429, _T_428)
node _T_431 = eq(io.rw.addr, UInt<11>(0h7b0))
node _T_432 = and(_T_430, _T_431)
else :
node _T_433 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_434 = eq(io.rw.addr, UInt<11>(0h7b0))
node _T_435 = and(_T_433, _T_434)
node _T_436 = andr(UInt<2>(0h1))
node _T_437 = eq(_T_436, UInt<1>(0h0))
when _T_437 :
node _T_438 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_439 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_440 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_441 = or(_T_438, _T_439)
node _T_442 = or(_T_441, _T_440)
node _T_443 = eq(io.rw.addr, UInt<11>(0h7b1))
node _T_444 = and(_T_442, _T_443)
else :
node _T_445 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_446 = eq(io.rw.addr, UInt<11>(0h7b1))
node _T_447 = and(_T_445, _T_446)
node _T_448 = andr(UInt<2>(0h1))
node _T_449 = eq(_T_448, UInt<1>(0h0))
when _T_449 :
node _T_450 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_451 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_452 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_453 = or(_T_450, _T_451)
node _T_454 = or(_T_453, _T_452)
node _T_455 = eq(io.rw.addr, UInt<11>(0h7b2))
node _T_456 = and(_T_454, _T_455)
else :
node _T_457 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_458 = eq(io.rw.addr, UInt<11>(0h7b2))
node _T_459 = and(_T_457, _T_458)
node _T_460 = andr(UInt<2>(0h0))
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_463 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_464 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_465 = or(_T_462, _T_463)
node _T_466 = or(_T_465, _T_464)
node _T_467 = eq(io.rw.addr, UInt<1>(0h1))
node _T_468 = and(_T_466, _T_467)
else :
node _T_469 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_470 = eq(io.rw.addr, UInt<1>(0h1))
node _T_471 = and(_T_469, _T_470)
node _T_472 = andr(UInt<2>(0h0))
node _T_473 = eq(_T_472, UInt<1>(0h0))
when _T_473 :
node _T_474 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_475 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_476 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_477 = or(_T_474, _T_475)
node _T_478 = or(_T_477, _T_476)
node _T_479 = eq(io.rw.addr, UInt<2>(0h2))
node _T_480 = and(_T_478, _T_479)
else :
node _T_481 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_482 = eq(io.rw.addr, UInt<2>(0h2))
node _T_483 = and(_T_481, _T_482)
node _T_484 = andr(UInt<2>(0h0))
node _T_485 = eq(_T_484, UInt<1>(0h0))
when _T_485 :
node _T_486 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_487 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_488 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_489 = or(_T_486, _T_487)
node _T_490 = or(_T_489, _T_488)
node _T_491 = eq(io.rw.addr, UInt<2>(0h3))
node _T_492 = and(_T_490, _T_491)
else :
node _T_493 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_494 = eq(io.rw.addr, UInt<2>(0h3))
node _T_495 = and(_T_493, _T_494)
node _T_496 = andr(UInt<2>(0h0))
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_499 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_500 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_501 = or(_T_498, _T_499)
node _T_502 = or(_T_501, _T_500)
node _T_503 = eq(io.rw.addr, UInt<10>(0h320))
node _T_504 = and(_T_502, _T_503)
else :
node _T_505 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_506 = eq(io.rw.addr, UInt<10>(0h320))
node _T_507 = and(_T_505, _T_506)
node _T_508 = andr(UInt<2>(0h2))
node _T_509 = eq(_T_508, UInt<1>(0h0))
when _T_509 :
node _T_510 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_511 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_512 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_513 = or(_T_510, _T_511)
node _T_514 = or(_T_513, _T_512)
node _T_515 = eq(io.rw.addr, UInt<12>(0hb00))
node _T_516 = and(_T_514, _T_515)
else :
node _T_517 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_518 = eq(io.rw.addr, UInt<12>(0hb00))
node _T_519 = and(_T_517, _T_518)
node _T_520 = andr(UInt<2>(0h2))
node _T_521 = eq(_T_520, UInt<1>(0h0))
when _T_521 :
node _T_522 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_523 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_524 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_525 = or(_T_522, _T_523)
node _T_526 = or(_T_525, _T_524)
node _T_527 = eq(io.rw.addr, UInt<12>(0hb02))
node _T_528 = and(_T_526, _T_527)
else :
node _T_529 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_530 = eq(io.rw.addr, UInt<12>(0hb02))
node _T_531 = and(_T_529, _T_530)
node _T_532 = andr(UInt<2>(0h0))
node _T_533 = eq(_T_532, UInt<1>(0h0))
when _T_533 :
node _T_534 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_535 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_536 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_537 = or(_T_534, _T_535)
node _T_538 = or(_T_537, _T_536)
node _T_539 = eq(io.rw.addr, UInt<10>(0h323))
node _T_540 = and(_T_538, _T_539)
else :
node _T_541 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_542 = eq(io.rw.addr, UInt<10>(0h323))
node _T_543 = and(_T_541, _T_542)
node _T_544 = andr(UInt<2>(0h2))
node _T_545 = eq(_T_544, UInt<1>(0h0))
when _T_545 :
node _T_546 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_547 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_548 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_549 = or(_T_546, _T_547)
node _T_550 = or(_T_549, _T_548)
node _T_551 = eq(io.rw.addr, UInt<12>(0hb03))
node _T_552 = and(_T_550, _T_551)
else :
node _T_553 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_554 = eq(io.rw.addr, UInt<12>(0hb03))
node _T_555 = and(_T_553, _T_554)
node _T_556 = andr(UInt<2>(0h0))
node _T_557 = eq(_T_556, UInt<1>(0h0))
when _T_557 :
node _T_558 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_559 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_560 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_561 = or(_T_558, _T_559)
node _T_562 = or(_T_561, _T_560)
node _T_563 = eq(io.rw.addr, UInt<10>(0h324))
node _T_564 = and(_T_562, _T_563)
else :
node _T_565 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_566 = eq(io.rw.addr, UInt<10>(0h324))
node _T_567 = and(_T_565, _T_566)
node _T_568 = andr(UInt<2>(0h2))
node _T_569 = eq(_T_568, UInt<1>(0h0))
when _T_569 :
node _T_570 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_571 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_572 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_573 = or(_T_570, _T_571)
node _T_574 = or(_T_573, _T_572)
node _T_575 = eq(io.rw.addr, UInt<12>(0hb04))
node _T_576 = and(_T_574, _T_575)
else :
node _T_577 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_578 = eq(io.rw.addr, UInt<12>(0hb04))
node _T_579 = and(_T_577, _T_578)
node _T_580 = andr(UInt<2>(0h0))
node _T_581 = eq(_T_580, UInt<1>(0h0))
when _T_581 :
node _T_582 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_583 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_584 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_585 = or(_T_582, _T_583)
node _T_586 = or(_T_585, _T_584)
node _T_587 = eq(io.rw.addr, UInt<10>(0h325))
node _T_588 = and(_T_586, _T_587)
else :
node _T_589 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_590 = eq(io.rw.addr, UInt<10>(0h325))
node _T_591 = and(_T_589, _T_590)
node _T_592 = andr(UInt<2>(0h2))
node _T_593 = eq(_T_592, UInt<1>(0h0))
when _T_593 :
node _T_594 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_595 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_596 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_597 = or(_T_594, _T_595)
node _T_598 = or(_T_597, _T_596)
node _T_599 = eq(io.rw.addr, UInt<12>(0hb05))
node _T_600 = and(_T_598, _T_599)
else :
node _T_601 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_602 = eq(io.rw.addr, UInt<12>(0hb05))
node _T_603 = and(_T_601, _T_602)
node _T_604 = andr(UInt<2>(0h0))
node _T_605 = eq(_T_604, UInt<1>(0h0))
when _T_605 :
node _T_606 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_607 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_608 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_609 = or(_T_606, _T_607)
node _T_610 = or(_T_609, _T_608)
node _T_611 = eq(io.rw.addr, UInt<10>(0h326))
node _T_612 = and(_T_610, _T_611)
else :
node _T_613 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_614 = eq(io.rw.addr, UInt<10>(0h326))
node _T_615 = and(_T_613, _T_614)
node _T_616 = andr(UInt<2>(0h2))
node _T_617 = eq(_T_616, UInt<1>(0h0))
when _T_617 :
node _T_618 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_619 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_620 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_621 = or(_T_618, _T_619)
node _T_622 = or(_T_621, _T_620)
node _T_623 = eq(io.rw.addr, UInt<12>(0hb06))
node _T_624 = and(_T_622, _T_623)
else :
node _T_625 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_626 = eq(io.rw.addr, UInt<12>(0hb06))
node _T_627 = and(_T_625, _T_626)
node _T_628 = andr(UInt<2>(0h0))
node _T_629 = eq(_T_628, UInt<1>(0h0))
when _T_629 :
node _T_630 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_631 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_632 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_633 = or(_T_630, _T_631)
node _T_634 = or(_T_633, _T_632)
node _T_635 = eq(io.rw.addr, UInt<10>(0h327))
node _T_636 = and(_T_634, _T_635)
else :
node _T_637 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_638 = eq(io.rw.addr, UInt<10>(0h327))
node _T_639 = and(_T_637, _T_638)
node _T_640 = andr(UInt<2>(0h2))
node _T_641 = eq(_T_640, UInt<1>(0h0))
when _T_641 :
node _T_642 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_643 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_644 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_645 = or(_T_642, _T_643)
node _T_646 = or(_T_645, _T_644)
node _T_647 = eq(io.rw.addr, UInt<12>(0hb07))
node _T_648 = and(_T_646, _T_647)
else :
node _T_649 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_650 = eq(io.rw.addr, UInt<12>(0hb07))
node _T_651 = and(_T_649, _T_650)
node _T_652 = andr(UInt<2>(0h0))
node _T_653 = eq(_T_652, UInt<1>(0h0))
when _T_653 :
node _T_654 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_655 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_656 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_657 = or(_T_654, _T_655)
node _T_658 = or(_T_657, _T_656)
node _T_659 = eq(io.rw.addr, UInt<10>(0h328))
node _T_660 = and(_T_658, _T_659)
else :
node _T_661 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_662 = eq(io.rw.addr, UInt<10>(0h328))
node _T_663 = and(_T_661, _T_662)
node _T_664 = andr(UInt<2>(0h2))
node _T_665 = eq(_T_664, UInt<1>(0h0))
when _T_665 :
node _T_666 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_667 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_668 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_669 = or(_T_666, _T_667)
node _T_670 = or(_T_669, _T_668)
node _T_671 = eq(io.rw.addr, UInt<12>(0hb08))
node _T_672 = and(_T_670, _T_671)
else :
node _T_673 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_674 = eq(io.rw.addr, UInt<12>(0hb08))
node _T_675 = and(_T_673, _T_674)
node _T_676 = andr(UInt<2>(0h0))
node _T_677 = eq(_T_676, UInt<1>(0h0))
when _T_677 :
node _T_678 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_679 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_680 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_681 = or(_T_678, _T_679)
node _T_682 = or(_T_681, _T_680)
node _T_683 = eq(io.rw.addr, UInt<10>(0h329))
node _T_684 = and(_T_682, _T_683)
else :
node _T_685 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_686 = eq(io.rw.addr, UInt<10>(0h329))
node _T_687 = and(_T_685, _T_686)
node _T_688 = andr(UInt<2>(0h2))
node _T_689 = eq(_T_688, UInt<1>(0h0))
when _T_689 :
node _T_690 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_691 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_692 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_693 = or(_T_690, _T_691)
node _T_694 = or(_T_693, _T_692)
node _T_695 = eq(io.rw.addr, UInt<12>(0hb09))
node _T_696 = and(_T_694, _T_695)
else :
node _T_697 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_698 = eq(io.rw.addr, UInt<12>(0hb09))
node _T_699 = and(_T_697, _T_698)
node _T_700 = andr(UInt<2>(0h0))
node _T_701 = eq(_T_700, UInt<1>(0h0))
when _T_701 :
node _T_702 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_703 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_704 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_705 = or(_T_702, _T_703)
node _T_706 = or(_T_705, _T_704)
node _T_707 = eq(io.rw.addr, UInt<10>(0h32a))
node _T_708 = and(_T_706, _T_707)
else :
node _T_709 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_710 = eq(io.rw.addr, UInt<10>(0h32a))
node _T_711 = and(_T_709, _T_710)
node _T_712 = andr(UInt<2>(0h2))
node _T_713 = eq(_T_712, UInt<1>(0h0))
when _T_713 :
node _T_714 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_715 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_716 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_717 = or(_T_714, _T_715)
node _T_718 = or(_T_717, _T_716)
node _T_719 = eq(io.rw.addr, UInt<12>(0hb0a))
node _T_720 = and(_T_718, _T_719)
else :
node _T_721 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_722 = eq(io.rw.addr, UInt<12>(0hb0a))
node _T_723 = and(_T_721, _T_722)
node _T_724 = andr(UInt<2>(0h0))
node _T_725 = eq(_T_724, UInt<1>(0h0))
when _T_725 :
node _T_726 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_727 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_728 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_729 = or(_T_726, _T_727)
node _T_730 = or(_T_729, _T_728)
node _T_731 = eq(io.rw.addr, UInt<10>(0h32b))
node _T_732 = and(_T_730, _T_731)
else :
node _T_733 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_734 = eq(io.rw.addr, UInt<10>(0h32b))
node _T_735 = and(_T_733, _T_734)
node _T_736 = andr(UInt<2>(0h2))
node _T_737 = eq(_T_736, UInt<1>(0h0))
when _T_737 :
node _T_738 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_739 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_740 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_741 = or(_T_738, _T_739)
node _T_742 = or(_T_741, _T_740)
node _T_743 = eq(io.rw.addr, UInt<12>(0hb0b))
node _T_744 = and(_T_742, _T_743)
else :
node _T_745 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_746 = eq(io.rw.addr, UInt<12>(0hb0b))
node _T_747 = and(_T_745, _T_746)
node _T_748 = andr(UInt<2>(0h0))
node _T_749 = eq(_T_748, UInt<1>(0h0))
when _T_749 :
node _T_750 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_751 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_752 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_753 = or(_T_750, _T_751)
node _T_754 = or(_T_753, _T_752)
node _T_755 = eq(io.rw.addr, UInt<10>(0h32c))
node _T_756 = and(_T_754, _T_755)
else :
node _T_757 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_758 = eq(io.rw.addr, UInt<10>(0h32c))
node _T_759 = and(_T_757, _T_758)
node _T_760 = andr(UInt<2>(0h2))
node _T_761 = eq(_T_760, UInt<1>(0h0))
when _T_761 :
node _T_762 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_763 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_764 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_765 = or(_T_762, _T_763)
node _T_766 = or(_T_765, _T_764)
node _T_767 = eq(io.rw.addr, UInt<12>(0hb0c))
node _T_768 = and(_T_766, _T_767)
else :
node _T_769 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_770 = eq(io.rw.addr, UInt<12>(0hb0c))
node _T_771 = and(_T_769, _T_770)
node _T_772 = andr(UInt<2>(0h0))
node _T_773 = eq(_T_772, UInt<1>(0h0))
when _T_773 :
node _T_774 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_775 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_776 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_777 = or(_T_774, _T_775)
node _T_778 = or(_T_777, _T_776)
node _T_779 = eq(io.rw.addr, UInt<10>(0h32d))
node _T_780 = and(_T_778, _T_779)
else :
node _T_781 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_782 = eq(io.rw.addr, UInt<10>(0h32d))
node _T_783 = and(_T_781, _T_782)
node _T_784 = andr(UInt<2>(0h2))
node _T_785 = eq(_T_784, UInt<1>(0h0))
when _T_785 :
node _T_786 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_787 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_788 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_789 = or(_T_786, _T_787)
node _T_790 = or(_T_789, _T_788)
node _T_791 = eq(io.rw.addr, UInt<12>(0hb0d))
node _T_792 = and(_T_790, _T_791)
else :
node _T_793 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_794 = eq(io.rw.addr, UInt<12>(0hb0d))
node _T_795 = and(_T_793, _T_794)
node _T_796 = andr(UInt<2>(0h0))
node _T_797 = eq(_T_796, UInt<1>(0h0))
when _T_797 :
node _T_798 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_799 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_800 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_801 = or(_T_798, _T_799)
node _T_802 = or(_T_801, _T_800)
node _T_803 = eq(io.rw.addr, UInt<10>(0h32e))
node _T_804 = and(_T_802, _T_803)
else :
node _T_805 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_806 = eq(io.rw.addr, UInt<10>(0h32e))
node _T_807 = and(_T_805, _T_806)
node _T_808 = andr(UInt<2>(0h2))
node _T_809 = eq(_T_808, UInt<1>(0h0))
when _T_809 :
node _T_810 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_811 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_812 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_813 = or(_T_810, _T_811)
node _T_814 = or(_T_813, _T_812)
node _T_815 = eq(io.rw.addr, UInt<12>(0hb0e))
node _T_816 = and(_T_814, _T_815)
else :
node _T_817 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_818 = eq(io.rw.addr, UInt<12>(0hb0e))
node _T_819 = and(_T_817, _T_818)
node _T_820 = andr(UInt<2>(0h0))
node _T_821 = eq(_T_820, UInt<1>(0h0))
when _T_821 :
node _T_822 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_823 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_824 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_825 = or(_T_822, _T_823)
node _T_826 = or(_T_825, _T_824)
node _T_827 = eq(io.rw.addr, UInt<10>(0h32f))
node _T_828 = and(_T_826, _T_827)
else :
node _T_829 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_830 = eq(io.rw.addr, UInt<10>(0h32f))
node _T_831 = and(_T_829, _T_830)
node _T_832 = andr(UInt<2>(0h2))
node _T_833 = eq(_T_832, UInt<1>(0h0))
when _T_833 :
node _T_834 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_835 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_836 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_837 = or(_T_834, _T_835)
node _T_838 = or(_T_837, _T_836)
node _T_839 = eq(io.rw.addr, UInt<12>(0hb0f))
node _T_840 = and(_T_838, _T_839)
else :
node _T_841 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_842 = eq(io.rw.addr, UInt<12>(0hb0f))
node _T_843 = and(_T_841, _T_842)
node _T_844 = andr(UInt<2>(0h0))
node _T_845 = eq(_T_844, UInt<1>(0h0))
when _T_845 :
node _T_846 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_847 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_848 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_849 = or(_T_846, _T_847)
node _T_850 = or(_T_849, _T_848)
node _T_851 = eq(io.rw.addr, UInt<10>(0h330))
node _T_852 = and(_T_850, _T_851)
else :
node _T_853 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_854 = eq(io.rw.addr, UInt<10>(0h330))
node _T_855 = and(_T_853, _T_854)
node _T_856 = andr(UInt<2>(0h2))
node _T_857 = eq(_T_856, UInt<1>(0h0))
when _T_857 :
node _T_858 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_859 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_860 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_861 = or(_T_858, _T_859)
node _T_862 = or(_T_861, _T_860)
node _T_863 = eq(io.rw.addr, UInt<12>(0hb10))
node _T_864 = and(_T_862, _T_863)
else :
node _T_865 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_866 = eq(io.rw.addr, UInt<12>(0hb10))
node _T_867 = and(_T_865, _T_866)
node _T_868 = andr(UInt<2>(0h0))
node _T_869 = eq(_T_868, UInt<1>(0h0))
when _T_869 :
node _T_870 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_871 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_872 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_873 = or(_T_870, _T_871)
node _T_874 = or(_T_873, _T_872)
node _T_875 = eq(io.rw.addr, UInt<10>(0h331))
node _T_876 = and(_T_874, _T_875)
else :
node _T_877 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_878 = eq(io.rw.addr, UInt<10>(0h331))
node _T_879 = and(_T_877, _T_878)
node _T_880 = andr(UInt<2>(0h2))
node _T_881 = eq(_T_880, UInt<1>(0h0))
when _T_881 :
node _T_882 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_883 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_884 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_885 = or(_T_882, _T_883)
node _T_886 = or(_T_885, _T_884)
node _T_887 = eq(io.rw.addr, UInt<12>(0hb11))
node _T_888 = and(_T_886, _T_887)
else :
node _T_889 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_890 = eq(io.rw.addr, UInt<12>(0hb11))
node _T_891 = and(_T_889, _T_890)
node _T_892 = andr(UInt<2>(0h0))
node _T_893 = eq(_T_892, UInt<1>(0h0))
when _T_893 :
node _T_894 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_895 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_896 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_897 = or(_T_894, _T_895)
node _T_898 = or(_T_897, _T_896)
node _T_899 = eq(io.rw.addr, UInt<10>(0h332))
node _T_900 = and(_T_898, _T_899)
else :
node _T_901 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_902 = eq(io.rw.addr, UInt<10>(0h332))
node _T_903 = and(_T_901, _T_902)
node _T_904 = andr(UInt<2>(0h2))
node _T_905 = eq(_T_904, UInt<1>(0h0))
when _T_905 :
node _T_906 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_907 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_908 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_909 = or(_T_906, _T_907)
node _T_910 = or(_T_909, _T_908)
node _T_911 = eq(io.rw.addr, UInt<12>(0hb12))
node _T_912 = and(_T_910, _T_911)
else :
node _T_913 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_914 = eq(io.rw.addr, UInt<12>(0hb12))
node _T_915 = and(_T_913, _T_914)
node _T_916 = andr(UInt<2>(0h0))
node _T_917 = eq(_T_916, UInt<1>(0h0))
when _T_917 :
node _T_918 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_919 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_920 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_921 = or(_T_918, _T_919)
node _T_922 = or(_T_921, _T_920)
node _T_923 = eq(io.rw.addr, UInt<10>(0h333))
node _T_924 = and(_T_922, _T_923)
else :
node _T_925 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_926 = eq(io.rw.addr, UInt<10>(0h333))
node _T_927 = and(_T_925, _T_926)
node _T_928 = andr(UInt<2>(0h2))
node _T_929 = eq(_T_928, UInt<1>(0h0))
when _T_929 :
node _T_930 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_931 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_932 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_933 = or(_T_930, _T_931)
node _T_934 = or(_T_933, _T_932)
node _T_935 = eq(io.rw.addr, UInt<12>(0hb13))
node _T_936 = and(_T_934, _T_935)
else :
node _T_937 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_938 = eq(io.rw.addr, UInt<12>(0hb13))
node _T_939 = and(_T_937, _T_938)
node _T_940 = andr(UInt<2>(0h0))
node _T_941 = eq(_T_940, UInt<1>(0h0))
when _T_941 :
node _T_942 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_943 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_944 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_945 = or(_T_942, _T_943)
node _T_946 = or(_T_945, _T_944)
node _T_947 = eq(io.rw.addr, UInt<10>(0h334))
node _T_948 = and(_T_946, _T_947)
else :
node _T_949 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_950 = eq(io.rw.addr, UInt<10>(0h334))
node _T_951 = and(_T_949, _T_950)
node _T_952 = andr(UInt<2>(0h2))
node _T_953 = eq(_T_952, UInt<1>(0h0))
when _T_953 :
node _T_954 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_955 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_956 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_957 = or(_T_954, _T_955)
node _T_958 = or(_T_957, _T_956)
node _T_959 = eq(io.rw.addr, UInt<12>(0hb14))
node _T_960 = and(_T_958, _T_959)
else :
node _T_961 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_962 = eq(io.rw.addr, UInt<12>(0hb14))
node _T_963 = and(_T_961, _T_962)
node _T_964 = andr(UInt<2>(0h0))
node _T_965 = eq(_T_964, UInt<1>(0h0))
when _T_965 :
node _T_966 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_967 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_968 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_969 = or(_T_966, _T_967)
node _T_970 = or(_T_969, _T_968)
node _T_971 = eq(io.rw.addr, UInt<10>(0h335))
node _T_972 = and(_T_970, _T_971)
else :
node _T_973 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_974 = eq(io.rw.addr, UInt<10>(0h335))
node _T_975 = and(_T_973, _T_974)
node _T_976 = andr(UInt<2>(0h2))
node _T_977 = eq(_T_976, UInt<1>(0h0))
when _T_977 :
node _T_978 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_979 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_980 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_981 = or(_T_978, _T_979)
node _T_982 = or(_T_981, _T_980)
node _T_983 = eq(io.rw.addr, UInt<12>(0hb15))
node _T_984 = and(_T_982, _T_983)
else :
node _T_985 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_986 = eq(io.rw.addr, UInt<12>(0hb15))
node _T_987 = and(_T_985, _T_986)
node _T_988 = andr(UInt<2>(0h0))
node _T_989 = eq(_T_988, UInt<1>(0h0))
when _T_989 :
node _T_990 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_991 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_992 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_993 = or(_T_990, _T_991)
node _T_994 = or(_T_993, _T_992)
node _T_995 = eq(io.rw.addr, UInt<10>(0h336))
node _T_996 = and(_T_994, _T_995)
else :
node _T_997 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_998 = eq(io.rw.addr, UInt<10>(0h336))
node _T_999 = and(_T_997, _T_998)
node _T_1000 = andr(UInt<2>(0h2))
node _T_1001 = eq(_T_1000, UInt<1>(0h0))
when _T_1001 :
node _T_1002 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1003 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1004 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1005 = or(_T_1002, _T_1003)
node _T_1006 = or(_T_1005, _T_1004)
node _T_1007 = eq(io.rw.addr, UInt<12>(0hb16))
node _T_1008 = and(_T_1006, _T_1007)
else :
node _T_1009 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1010 = eq(io.rw.addr, UInt<12>(0hb16))
node _T_1011 = and(_T_1009, _T_1010)
node _T_1012 = andr(UInt<2>(0h0))
node _T_1013 = eq(_T_1012, UInt<1>(0h0))
when _T_1013 :
node _T_1014 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1015 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1016 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1017 = or(_T_1014, _T_1015)
node _T_1018 = or(_T_1017, _T_1016)
node _T_1019 = eq(io.rw.addr, UInt<10>(0h337))
node _T_1020 = and(_T_1018, _T_1019)
else :
node _T_1021 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1022 = eq(io.rw.addr, UInt<10>(0h337))
node _T_1023 = and(_T_1021, _T_1022)
node _T_1024 = andr(UInt<2>(0h2))
node _T_1025 = eq(_T_1024, UInt<1>(0h0))
when _T_1025 :
node _T_1026 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1027 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1028 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1029 = or(_T_1026, _T_1027)
node _T_1030 = or(_T_1029, _T_1028)
node _T_1031 = eq(io.rw.addr, UInt<12>(0hb17))
node _T_1032 = and(_T_1030, _T_1031)
else :
node _T_1033 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1034 = eq(io.rw.addr, UInt<12>(0hb17))
node _T_1035 = and(_T_1033, _T_1034)
node _T_1036 = andr(UInt<2>(0h0))
node _T_1037 = eq(_T_1036, UInt<1>(0h0))
when _T_1037 :
node _T_1038 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1039 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1040 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1041 = or(_T_1038, _T_1039)
node _T_1042 = or(_T_1041, _T_1040)
node _T_1043 = eq(io.rw.addr, UInt<10>(0h338))
node _T_1044 = and(_T_1042, _T_1043)
else :
node _T_1045 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1046 = eq(io.rw.addr, UInt<10>(0h338))
node _T_1047 = and(_T_1045, _T_1046)
node _T_1048 = andr(UInt<2>(0h2))
node _T_1049 = eq(_T_1048, UInt<1>(0h0))
when _T_1049 :
node _T_1050 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1051 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1052 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1053 = or(_T_1050, _T_1051)
node _T_1054 = or(_T_1053, _T_1052)
node _T_1055 = eq(io.rw.addr, UInt<12>(0hb18))
node _T_1056 = and(_T_1054, _T_1055)
else :
node _T_1057 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1058 = eq(io.rw.addr, UInt<12>(0hb18))
node _T_1059 = and(_T_1057, _T_1058)
node _T_1060 = andr(UInt<2>(0h0))
node _T_1061 = eq(_T_1060, UInt<1>(0h0))
when _T_1061 :
node _T_1062 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1063 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1064 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1065 = or(_T_1062, _T_1063)
node _T_1066 = or(_T_1065, _T_1064)
node _T_1067 = eq(io.rw.addr, UInt<10>(0h339))
node _T_1068 = and(_T_1066, _T_1067)
else :
node _T_1069 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1070 = eq(io.rw.addr, UInt<10>(0h339))
node _T_1071 = and(_T_1069, _T_1070)
node _T_1072 = andr(UInt<2>(0h2))
node _T_1073 = eq(_T_1072, UInt<1>(0h0))
when _T_1073 :
node _T_1074 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1075 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1076 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1077 = or(_T_1074, _T_1075)
node _T_1078 = or(_T_1077, _T_1076)
node _T_1079 = eq(io.rw.addr, UInt<12>(0hb19))
node _T_1080 = and(_T_1078, _T_1079)
else :
node _T_1081 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1082 = eq(io.rw.addr, UInt<12>(0hb19))
node _T_1083 = and(_T_1081, _T_1082)
node _T_1084 = andr(UInt<2>(0h0))
node _T_1085 = eq(_T_1084, UInt<1>(0h0))
when _T_1085 :
node _T_1086 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1087 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1088 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1089 = or(_T_1086, _T_1087)
node _T_1090 = or(_T_1089, _T_1088)
node _T_1091 = eq(io.rw.addr, UInt<10>(0h33a))
node _T_1092 = and(_T_1090, _T_1091)
else :
node _T_1093 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1094 = eq(io.rw.addr, UInt<10>(0h33a))
node _T_1095 = and(_T_1093, _T_1094)
node _T_1096 = andr(UInt<2>(0h2))
node _T_1097 = eq(_T_1096, UInt<1>(0h0))
when _T_1097 :
node _T_1098 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1099 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1100 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1101 = or(_T_1098, _T_1099)
node _T_1102 = or(_T_1101, _T_1100)
node _T_1103 = eq(io.rw.addr, UInt<12>(0hb1a))
node _T_1104 = and(_T_1102, _T_1103)
else :
node _T_1105 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1106 = eq(io.rw.addr, UInt<12>(0hb1a))
node _T_1107 = and(_T_1105, _T_1106)
node _T_1108 = andr(UInt<2>(0h0))
node _T_1109 = eq(_T_1108, UInt<1>(0h0))
when _T_1109 :
node _T_1110 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1111 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1112 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1113 = or(_T_1110, _T_1111)
node _T_1114 = or(_T_1113, _T_1112)
node _T_1115 = eq(io.rw.addr, UInt<10>(0h33b))
node _T_1116 = and(_T_1114, _T_1115)
else :
node _T_1117 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1118 = eq(io.rw.addr, UInt<10>(0h33b))
node _T_1119 = and(_T_1117, _T_1118)
node _T_1120 = andr(UInt<2>(0h2))
node _T_1121 = eq(_T_1120, UInt<1>(0h0))
when _T_1121 :
node _T_1122 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1123 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1124 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1125 = or(_T_1122, _T_1123)
node _T_1126 = or(_T_1125, _T_1124)
node _T_1127 = eq(io.rw.addr, UInt<12>(0hb1b))
node _T_1128 = and(_T_1126, _T_1127)
else :
node _T_1129 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1130 = eq(io.rw.addr, UInt<12>(0hb1b))
node _T_1131 = and(_T_1129, _T_1130)
node _T_1132 = andr(UInt<2>(0h0))
node _T_1133 = eq(_T_1132, UInt<1>(0h0))
when _T_1133 :
node _T_1134 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1135 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1136 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1137 = or(_T_1134, _T_1135)
node _T_1138 = or(_T_1137, _T_1136)
node _T_1139 = eq(io.rw.addr, UInt<10>(0h33c))
node _T_1140 = and(_T_1138, _T_1139)
else :
node _T_1141 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1142 = eq(io.rw.addr, UInt<10>(0h33c))
node _T_1143 = and(_T_1141, _T_1142)
node _T_1144 = andr(UInt<2>(0h2))
node _T_1145 = eq(_T_1144, UInt<1>(0h0))
when _T_1145 :
node _T_1146 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1147 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1148 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1149 = or(_T_1146, _T_1147)
node _T_1150 = or(_T_1149, _T_1148)
node _T_1151 = eq(io.rw.addr, UInt<12>(0hb1c))
node _T_1152 = and(_T_1150, _T_1151)
else :
node _T_1153 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1154 = eq(io.rw.addr, UInt<12>(0hb1c))
node _T_1155 = and(_T_1153, _T_1154)
node _T_1156 = andr(UInt<2>(0h0))
node _T_1157 = eq(_T_1156, UInt<1>(0h0))
when _T_1157 :
node _T_1158 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1159 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1160 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1161 = or(_T_1158, _T_1159)
node _T_1162 = or(_T_1161, _T_1160)
node _T_1163 = eq(io.rw.addr, UInt<10>(0h33d))
node _T_1164 = and(_T_1162, _T_1163)
else :
node _T_1165 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1166 = eq(io.rw.addr, UInt<10>(0h33d))
node _T_1167 = and(_T_1165, _T_1166)
node _T_1168 = andr(UInt<2>(0h2))
node _T_1169 = eq(_T_1168, UInt<1>(0h0))
when _T_1169 :
node _T_1170 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1171 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1172 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1173 = or(_T_1170, _T_1171)
node _T_1174 = or(_T_1173, _T_1172)
node _T_1175 = eq(io.rw.addr, UInt<12>(0hb1d))
node _T_1176 = and(_T_1174, _T_1175)
else :
node _T_1177 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1178 = eq(io.rw.addr, UInt<12>(0hb1d))
node _T_1179 = and(_T_1177, _T_1178)
node _T_1180 = andr(UInt<2>(0h0))
node _T_1181 = eq(_T_1180, UInt<1>(0h0))
when _T_1181 :
node _T_1182 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1183 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1184 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1185 = or(_T_1182, _T_1183)
node _T_1186 = or(_T_1185, _T_1184)
node _T_1187 = eq(io.rw.addr, UInt<10>(0h33e))
node _T_1188 = and(_T_1186, _T_1187)
else :
node _T_1189 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1190 = eq(io.rw.addr, UInt<10>(0h33e))
node _T_1191 = and(_T_1189, _T_1190)
node _T_1192 = andr(UInt<2>(0h2))
node _T_1193 = eq(_T_1192, UInt<1>(0h0))
when _T_1193 :
node _T_1194 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1195 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1196 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1197 = or(_T_1194, _T_1195)
node _T_1198 = or(_T_1197, _T_1196)
node _T_1199 = eq(io.rw.addr, UInt<12>(0hb1e))
node _T_1200 = and(_T_1198, _T_1199)
else :
node _T_1201 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1202 = eq(io.rw.addr, UInt<12>(0hb1e))
node _T_1203 = and(_T_1201, _T_1202)
node _T_1204 = andr(UInt<2>(0h0))
node _T_1205 = eq(_T_1204, UInt<1>(0h0))
when _T_1205 :
node _T_1206 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1207 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1208 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1209 = or(_T_1206, _T_1207)
node _T_1210 = or(_T_1209, _T_1208)
node _T_1211 = eq(io.rw.addr, UInt<10>(0h33f))
node _T_1212 = and(_T_1210, _T_1211)
else :
node _T_1213 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1214 = eq(io.rw.addr, UInt<10>(0h33f))
node _T_1215 = and(_T_1213, _T_1214)
node _T_1216 = andr(UInt<2>(0h2))
node _T_1217 = eq(_T_1216, UInt<1>(0h0))
when _T_1217 :
node _T_1218 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1219 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1220 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1221 = or(_T_1218, _T_1219)
node _T_1222 = or(_T_1221, _T_1220)
node _T_1223 = eq(io.rw.addr, UInt<12>(0hb1f))
node _T_1224 = and(_T_1222, _T_1223)
else :
node _T_1225 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1226 = eq(io.rw.addr, UInt<12>(0hb1f))
node _T_1227 = and(_T_1225, _T_1226)
node _T_1228 = andr(UInt<2>(0h0))
node _T_1229 = eq(_T_1228, UInt<1>(0h0))
when _T_1229 :
node _T_1230 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1231 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1232 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1233 = or(_T_1230, _T_1231)
node _T_1234 = or(_T_1233, _T_1232)
node _T_1235 = eq(io.rw.addr, UInt<10>(0h306))
node _T_1236 = and(_T_1234, _T_1235)
else :
node _T_1237 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1238 = eq(io.rw.addr, UInt<10>(0h306))
node _T_1239 = and(_T_1237, _T_1238)
node _T_1240 = andr(UInt<2>(0h3))
node _T_1241 = eq(_T_1240, UInt<1>(0h0))
when _T_1241 :
node _T_1242 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1243 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1244 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1245 = or(_T_1242, _T_1243)
node _T_1246 = or(_T_1245, _T_1244)
node _T_1247 = eq(io.rw.addr, UInt<12>(0hc00))
node _T_1248 = and(_T_1246, _T_1247)
else :
node _T_1249 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1250 = eq(io.rw.addr, UInt<12>(0hc00))
node _T_1251 = and(_T_1249, _T_1250)
node _T_1252 = andr(UInt<2>(0h3))
node _T_1253 = eq(_T_1252, UInt<1>(0h0))
when _T_1253 :
node _T_1254 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1255 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1256 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1257 = or(_T_1254, _T_1255)
node _T_1258 = or(_T_1257, _T_1256)
node _T_1259 = eq(io.rw.addr, UInt<12>(0hc02))
node _T_1260 = and(_T_1258, _T_1259)
else :
node _T_1261 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1262 = eq(io.rw.addr, UInt<12>(0hc02))
node _T_1263 = and(_T_1261, _T_1262)
node _T_1264 = andr(UInt<2>(0h0))
node _T_1265 = eq(_T_1264, UInt<1>(0h0))
when _T_1265 :
node _T_1266 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1267 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1268 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1269 = or(_T_1266, _T_1267)
node _T_1270 = or(_T_1269, _T_1268)
node _T_1271 = eq(io.rw.addr, UInt<10>(0h30a))
node _T_1272 = and(_T_1270, _T_1271)
else :
node _T_1273 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1274 = eq(io.rw.addr, UInt<10>(0h30a))
node _T_1275 = and(_T_1273, _T_1274)
node _T_1276 = andr(UInt<2>(0h0))
node _T_1277 = eq(_T_1276, UInt<1>(0h0))
when _T_1277 :
node _T_1278 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1279 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1280 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1281 = or(_T_1278, _T_1279)
node _T_1282 = or(_T_1281, _T_1280)
node _T_1283 = eq(io.rw.addr, UInt<9>(0h100))
node _T_1284 = and(_T_1282, _T_1283)
else :
node _T_1285 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1286 = eq(io.rw.addr, UInt<9>(0h100))
node _T_1287 = and(_T_1285, _T_1286)
node _T_1288 = andr(UInt<2>(0h0))
node _T_1289 = eq(_T_1288, UInt<1>(0h0))
when _T_1289 :
node _T_1290 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1291 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1292 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1293 = or(_T_1290, _T_1291)
node _T_1294 = or(_T_1293, _T_1292)
node _T_1295 = eq(io.rw.addr, UInt<9>(0h144))
node _T_1296 = and(_T_1294, _T_1295)
else :
node _T_1297 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1298 = eq(io.rw.addr, UInt<9>(0h144))
node _T_1299 = and(_T_1297, _T_1298)
node _T_1300 = andr(UInt<2>(0h0))
node _T_1301 = eq(_T_1300, UInt<1>(0h0))
when _T_1301 :
node _T_1302 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1303 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1304 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1305 = or(_T_1302, _T_1303)
node _T_1306 = or(_T_1305, _T_1304)
node _T_1307 = eq(io.rw.addr, UInt<9>(0h104))
node _T_1308 = and(_T_1306, _T_1307)
else :
node _T_1309 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1310 = eq(io.rw.addr, UInt<9>(0h104))
node _T_1311 = and(_T_1309, _T_1310)
node _T_1312 = andr(UInt<2>(0h0))
node _T_1313 = eq(_T_1312, UInt<1>(0h0))
when _T_1313 :
node _T_1314 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1315 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1316 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1317 = or(_T_1314, _T_1315)
node _T_1318 = or(_T_1317, _T_1316)
node _T_1319 = eq(io.rw.addr, UInt<9>(0h140))
node _T_1320 = and(_T_1318, _T_1319)
else :
node _T_1321 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1322 = eq(io.rw.addr, UInt<9>(0h140))
node _T_1323 = and(_T_1321, _T_1322)
node _T_1324 = andr(UInt<2>(0h0))
node _T_1325 = eq(_T_1324, UInt<1>(0h0))
when _T_1325 :
node _T_1326 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1327 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1328 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1329 = or(_T_1326, _T_1327)
node _T_1330 = or(_T_1329, _T_1328)
node _T_1331 = eq(io.rw.addr, UInt<9>(0h142))
node _T_1332 = and(_T_1330, _T_1331)
else :
node _T_1333 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1334 = eq(io.rw.addr, UInt<9>(0h142))
node _T_1335 = and(_T_1333, _T_1334)
node _T_1336 = andr(UInt<2>(0h0))
node _T_1337 = eq(_T_1336, UInt<1>(0h0))
when _T_1337 :
node _T_1338 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1339 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1340 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1341 = or(_T_1338, _T_1339)
node _T_1342 = or(_T_1341, _T_1340)
node _T_1343 = eq(io.rw.addr, UInt<9>(0h143))
node _T_1344 = and(_T_1342, _T_1343)
else :
node _T_1345 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1346 = eq(io.rw.addr, UInt<9>(0h143))
node _T_1347 = and(_T_1345, _T_1346)
node _T_1348 = andr(UInt<2>(0h0))
node _T_1349 = eq(_T_1348, UInt<1>(0h0))
when _T_1349 :
node _T_1350 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1351 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1352 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1353 = or(_T_1350, _T_1351)
node _T_1354 = or(_T_1353, _T_1352)
node _T_1355 = eq(io.rw.addr, UInt<9>(0h180))
node _T_1356 = and(_T_1354, _T_1355)
else :
node _T_1357 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1358 = eq(io.rw.addr, UInt<9>(0h180))
node _T_1359 = and(_T_1357, _T_1358)
node _T_1360 = andr(UInt<2>(0h0))
node _T_1361 = eq(_T_1360, UInt<1>(0h0))
when _T_1361 :
node _T_1362 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1363 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1364 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1365 = or(_T_1362, _T_1363)
node _T_1366 = or(_T_1365, _T_1364)
node _T_1367 = eq(io.rw.addr, UInt<9>(0h141))
node _T_1368 = and(_T_1366, _T_1367)
else :
node _T_1369 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1370 = eq(io.rw.addr, UInt<9>(0h141))
node _T_1371 = and(_T_1369, _T_1370)
node _T_1372 = andr(UInt<2>(0h0))
node _T_1373 = eq(_T_1372, UInt<1>(0h0))
when _T_1373 :
node _T_1374 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1375 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1376 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1377 = or(_T_1374, _T_1375)
node _T_1378 = or(_T_1377, _T_1376)
node _T_1379 = eq(io.rw.addr, UInt<9>(0h105))
node _T_1380 = and(_T_1378, _T_1379)
else :
node _T_1381 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1382 = eq(io.rw.addr, UInt<9>(0h105))
node _T_1383 = and(_T_1381, _T_1382)
node _T_1384 = andr(UInt<2>(0h0))
node _T_1385 = eq(_T_1384, UInt<1>(0h0))
when _T_1385 :
node _T_1386 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1387 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1388 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1389 = or(_T_1386, _T_1387)
node _T_1390 = or(_T_1389, _T_1388)
node _T_1391 = eq(io.rw.addr, UInt<9>(0h106))
node _T_1392 = and(_T_1390, _T_1391)
else :
node _T_1393 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1394 = eq(io.rw.addr, UInt<9>(0h106))
node _T_1395 = and(_T_1393, _T_1394)
node _T_1396 = andr(UInt<2>(0h0))
node _T_1397 = eq(_T_1396, UInt<1>(0h0))
when _T_1397 :
node _T_1398 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1399 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1400 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1401 = or(_T_1398, _T_1399)
node _T_1402 = or(_T_1401, _T_1400)
node _T_1403 = eq(io.rw.addr, UInt<10>(0h303))
node _T_1404 = and(_T_1402, _T_1403)
else :
node _T_1405 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1406 = eq(io.rw.addr, UInt<10>(0h303))
node _T_1407 = and(_T_1405, _T_1406)
node _T_1408 = andr(UInt<2>(0h0))
node _T_1409 = eq(_T_1408, UInt<1>(0h0))
when _T_1409 :
node _T_1410 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1411 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1412 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1413 = or(_T_1410, _T_1411)
node _T_1414 = or(_T_1413, _T_1412)
node _T_1415 = eq(io.rw.addr, UInt<10>(0h302))
node _T_1416 = and(_T_1414, _T_1415)
else :
node _T_1417 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1418 = eq(io.rw.addr, UInt<10>(0h302))
node _T_1419 = and(_T_1417, _T_1418)
node _T_1420 = andr(UInt<2>(0h0))
node _T_1421 = eq(_T_1420, UInt<1>(0h0))
when _T_1421 :
node _T_1422 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1423 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1424 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1425 = or(_T_1422, _T_1423)
node _T_1426 = or(_T_1425, _T_1424)
node _T_1427 = eq(io.rw.addr, UInt<9>(0h10a))
node _T_1428 = and(_T_1426, _T_1427)
else :
node _T_1429 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1430 = eq(io.rw.addr, UInt<9>(0h10a))
node _T_1431 = and(_T_1429, _T_1430)
node _T_1432 = andr(UInt<2>(0h0))
node _T_1433 = eq(_T_1432, UInt<1>(0h0))
when _T_1433 :
node _T_1434 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1435 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1436 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1437 = or(_T_1434, _T_1435)
node _T_1438 = or(_T_1437, _T_1436)
node _T_1439 = eq(io.rw.addr, UInt<10>(0h3a0))
node _T_1440 = and(_T_1438, _T_1439)
else :
node _T_1441 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1442 = eq(io.rw.addr, UInt<10>(0h3a0))
node _T_1443 = and(_T_1441, _T_1442)
node _T_1444 = andr(UInt<2>(0h0))
node _T_1445 = eq(_T_1444, UInt<1>(0h0))
when _T_1445 :
node _T_1446 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1447 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1448 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1449 = or(_T_1446, _T_1447)
node _T_1450 = or(_T_1449, _T_1448)
node _T_1451 = eq(io.rw.addr, UInt<10>(0h3a2))
node _T_1452 = and(_T_1450, _T_1451)
else :
node _T_1453 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1454 = eq(io.rw.addr, UInt<10>(0h3a2))
node _T_1455 = and(_T_1453, _T_1454)
node _T_1456 = andr(UInt<2>(0h0))
node _T_1457 = eq(_T_1456, UInt<1>(0h0))
when _T_1457 :
node _T_1458 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1459 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1460 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1461 = or(_T_1458, _T_1459)
node _T_1462 = or(_T_1461, _T_1460)
node _T_1463 = eq(io.rw.addr, UInt<10>(0h3b0))
node _T_1464 = and(_T_1462, _T_1463)
else :
node _T_1465 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1466 = eq(io.rw.addr, UInt<10>(0h3b0))
node _T_1467 = and(_T_1465, _T_1466)
node _T_1468 = andr(UInt<2>(0h0))
node _T_1469 = eq(_T_1468, UInt<1>(0h0))
when _T_1469 :
node _T_1470 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1471 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1472 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1473 = or(_T_1470, _T_1471)
node _T_1474 = or(_T_1473, _T_1472)
node _T_1475 = eq(io.rw.addr, UInt<10>(0h3b1))
node _T_1476 = and(_T_1474, _T_1475)
else :
node _T_1477 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1478 = eq(io.rw.addr, UInt<10>(0h3b1))
node _T_1479 = and(_T_1477, _T_1478)
node _T_1480 = andr(UInt<2>(0h0))
node _T_1481 = eq(_T_1480, UInt<1>(0h0))
when _T_1481 :
node _T_1482 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1483 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1484 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1485 = or(_T_1482, _T_1483)
node _T_1486 = or(_T_1485, _T_1484)
node _T_1487 = eq(io.rw.addr, UInt<10>(0h3b2))
node _T_1488 = and(_T_1486, _T_1487)
else :
node _T_1489 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1490 = eq(io.rw.addr, UInt<10>(0h3b2))
node _T_1491 = and(_T_1489, _T_1490)
node _T_1492 = andr(UInt<2>(0h0))
node _T_1493 = eq(_T_1492, UInt<1>(0h0))
when _T_1493 :
node _T_1494 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1495 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1496 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1497 = or(_T_1494, _T_1495)
node _T_1498 = or(_T_1497, _T_1496)
node _T_1499 = eq(io.rw.addr, UInt<10>(0h3b3))
node _T_1500 = and(_T_1498, _T_1499)
else :
node _T_1501 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1502 = eq(io.rw.addr, UInt<10>(0h3b3))
node _T_1503 = and(_T_1501, _T_1502)
node _T_1504 = andr(UInt<2>(0h0))
node _T_1505 = eq(_T_1504, UInt<1>(0h0))
when _T_1505 :
node _T_1506 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1507 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1508 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1509 = or(_T_1506, _T_1507)
node _T_1510 = or(_T_1509, _T_1508)
node _T_1511 = eq(io.rw.addr, UInt<10>(0h3b4))
node _T_1512 = and(_T_1510, _T_1511)
else :
node _T_1513 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1514 = eq(io.rw.addr, UInt<10>(0h3b4))
node _T_1515 = and(_T_1513, _T_1514)
node _T_1516 = andr(UInt<2>(0h0))
node _T_1517 = eq(_T_1516, UInt<1>(0h0))
when _T_1517 :
node _T_1518 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1519 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1520 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1521 = or(_T_1518, _T_1519)
node _T_1522 = or(_T_1521, _T_1520)
node _T_1523 = eq(io.rw.addr, UInt<10>(0h3b5))
node _T_1524 = and(_T_1522, _T_1523)
else :
node _T_1525 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1526 = eq(io.rw.addr, UInt<10>(0h3b5))
node _T_1527 = and(_T_1525, _T_1526)
node _T_1528 = andr(UInt<2>(0h0))
node _T_1529 = eq(_T_1528, UInt<1>(0h0))
when _T_1529 :
node _T_1530 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1531 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1532 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1533 = or(_T_1530, _T_1531)
node _T_1534 = or(_T_1533, _T_1532)
node _T_1535 = eq(io.rw.addr, UInt<10>(0h3b6))
node _T_1536 = and(_T_1534, _T_1535)
else :
node _T_1537 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1538 = eq(io.rw.addr, UInt<10>(0h3b6))
node _T_1539 = and(_T_1537, _T_1538)
node _T_1540 = andr(UInt<2>(0h0))
node _T_1541 = eq(_T_1540, UInt<1>(0h0))
when _T_1541 :
node _T_1542 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1543 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1544 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1545 = or(_T_1542, _T_1543)
node _T_1546 = or(_T_1545, _T_1544)
node _T_1547 = eq(io.rw.addr, UInt<10>(0h3b7))
node _T_1548 = and(_T_1546, _T_1547)
else :
node _T_1549 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1550 = eq(io.rw.addr, UInt<10>(0h3b7))
node _T_1551 = and(_T_1549, _T_1550)
node _T_1552 = andr(UInt<2>(0h0))
node _T_1553 = eq(_T_1552, UInt<1>(0h0))
when _T_1553 :
node _T_1554 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1555 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1556 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1557 = or(_T_1554, _T_1555)
node _T_1558 = or(_T_1557, _T_1556)
node _T_1559 = eq(io.rw.addr, UInt<10>(0h3b8))
node _T_1560 = and(_T_1558, _T_1559)
else :
node _T_1561 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1562 = eq(io.rw.addr, UInt<10>(0h3b8))
node _T_1563 = and(_T_1561, _T_1562)
node _T_1564 = andr(UInt<2>(0h0))
node _T_1565 = eq(_T_1564, UInt<1>(0h0))
when _T_1565 :
node _T_1566 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1567 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1568 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1569 = or(_T_1566, _T_1567)
node _T_1570 = or(_T_1569, _T_1568)
node _T_1571 = eq(io.rw.addr, UInt<10>(0h3b9))
node _T_1572 = and(_T_1570, _T_1571)
else :
node _T_1573 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1574 = eq(io.rw.addr, UInt<10>(0h3b9))
node _T_1575 = and(_T_1573, _T_1574)
node _T_1576 = andr(UInt<2>(0h0))
node _T_1577 = eq(_T_1576, UInt<1>(0h0))
when _T_1577 :
node _T_1578 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1579 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1580 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1581 = or(_T_1578, _T_1579)
node _T_1582 = or(_T_1581, _T_1580)
node _T_1583 = eq(io.rw.addr, UInt<10>(0h3ba))
node _T_1584 = and(_T_1582, _T_1583)
else :
node _T_1585 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1586 = eq(io.rw.addr, UInt<10>(0h3ba))
node _T_1587 = and(_T_1585, _T_1586)
node _T_1588 = andr(UInt<2>(0h0))
node _T_1589 = eq(_T_1588, UInt<1>(0h0))
when _T_1589 :
node _T_1590 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1591 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1592 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1593 = or(_T_1590, _T_1591)
node _T_1594 = or(_T_1593, _T_1592)
node _T_1595 = eq(io.rw.addr, UInt<10>(0h3bb))
node _T_1596 = and(_T_1594, _T_1595)
else :
node _T_1597 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1598 = eq(io.rw.addr, UInt<10>(0h3bb))
node _T_1599 = and(_T_1597, _T_1598)
node _T_1600 = andr(UInt<2>(0h0))
node _T_1601 = eq(_T_1600, UInt<1>(0h0))
when _T_1601 :
node _T_1602 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1603 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1604 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1605 = or(_T_1602, _T_1603)
node _T_1606 = or(_T_1605, _T_1604)
node _T_1607 = eq(io.rw.addr, UInt<10>(0h3bc))
node _T_1608 = and(_T_1606, _T_1607)
else :
node _T_1609 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1610 = eq(io.rw.addr, UInt<10>(0h3bc))
node _T_1611 = and(_T_1609, _T_1610)
node _T_1612 = andr(UInt<2>(0h0))
node _T_1613 = eq(_T_1612, UInt<1>(0h0))
when _T_1613 :
node _T_1614 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1615 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1616 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1617 = or(_T_1614, _T_1615)
node _T_1618 = or(_T_1617, _T_1616)
node _T_1619 = eq(io.rw.addr, UInt<10>(0h3bd))
node _T_1620 = and(_T_1618, _T_1619)
else :
node _T_1621 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1622 = eq(io.rw.addr, UInt<10>(0h3bd))
node _T_1623 = and(_T_1621, _T_1622)
node _T_1624 = andr(UInt<2>(0h0))
node _T_1625 = eq(_T_1624, UInt<1>(0h0))
when _T_1625 :
node _T_1626 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1627 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1628 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1629 = or(_T_1626, _T_1627)
node _T_1630 = or(_T_1629, _T_1628)
node _T_1631 = eq(io.rw.addr, UInt<10>(0h3be))
node _T_1632 = and(_T_1630, _T_1631)
else :
node _T_1633 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1634 = eq(io.rw.addr, UInt<10>(0h3be))
node _T_1635 = and(_T_1633, _T_1634)
node _T_1636 = andr(UInt<2>(0h0))
node _T_1637 = eq(_T_1636, UInt<1>(0h0))
when _T_1637 :
node _T_1638 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1639 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1640 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1641 = or(_T_1638, _T_1639)
node _T_1642 = or(_T_1641, _T_1640)
node _T_1643 = eq(io.rw.addr, UInt<10>(0h3bf))
node _T_1644 = and(_T_1642, _T_1643)
else :
node _T_1645 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1646 = eq(io.rw.addr, UInt<10>(0h3bf))
node _T_1647 = and(_T_1645, _T_1646)
node _T_1648 = andr(UInt<2>(0h1))
node _T_1649 = eq(_T_1648, UInt<1>(0h0))
when _T_1649 :
node _T_1650 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1651 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1652 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1653 = or(_T_1650, _T_1651)
node _T_1654 = or(_T_1653, _T_1652)
node _T_1655 = eq(io.rw.addr, UInt<11>(0h7c1))
node _T_1656 = and(_T_1654, _T_1655)
else :
node _T_1657 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1658 = eq(io.rw.addr, UInt<11>(0h7c1))
node _T_1659 = and(_T_1657, _T_1658)
node _T_1660 = andr(UInt<2>(0h3))
node _T_1661 = eq(_T_1660, UInt<1>(0h0))
when _T_1661 :
node _T_1662 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1663 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1664 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1665 = or(_T_1662, _T_1663)
node _T_1666 = or(_T_1665, _T_1664)
node _T_1667 = eq(io.rw.addr, UInt<12>(0hf12))
node _T_1668 = and(_T_1666, _T_1667)
else :
node _T_1669 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1670 = eq(io.rw.addr, UInt<12>(0hf12))
node _T_1671 = and(_T_1669, _T_1670)
node _T_1672 = andr(UInt<2>(0h3))
node _T_1673 = eq(_T_1672, UInt<1>(0h0))
when _T_1673 :
node _T_1674 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1675 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1676 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1677 = or(_T_1674, _T_1675)
node _T_1678 = or(_T_1677, _T_1676)
node _T_1679 = eq(io.rw.addr, UInt<12>(0hf11))
node _T_1680 = and(_T_1678, _T_1679)
else :
node _T_1681 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1682 = eq(io.rw.addr, UInt<12>(0hf11))
node _T_1683 = and(_T_1681, _T_1682)
node _T_1684 = andr(UInt<2>(0h3))
node _T_1685 = eq(_T_1684, UInt<1>(0h0))
when _T_1685 :
node _T_1686 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1687 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1688 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1689 = or(_T_1686, _T_1687)
node _T_1690 = or(_T_1689, _T_1688)
node _T_1691 = eq(io.rw.addr, UInt<12>(0hf13))
node _T_1692 = and(_T_1690, _T_1691)
else :
node _T_1693 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1694 = eq(io.rw.addr, UInt<12>(0hf13))
node _T_1695 = and(_T_1693, _T_1694)
node _T_1696 = andr(UInt<2>(0h3))
node _T_1697 = eq(_T_1696, UInt<1>(0h0))
when _T_1697 :
node _T_1698 = eq(io.rw.cmd, UInt<3>(0h5))
node _T_1699 = eq(io.rw.cmd, UInt<3>(0h6))
node _T_1700 = eq(io.rw.cmd, UInt<3>(0h7))
node _T_1701 = or(_T_1698, _T_1699)
node _T_1702 = or(_T_1701, _T_1700)
node _T_1703 = eq(io.rw.addr, UInt<12>(0hf15))
node _T_1704 = and(_T_1702, _T_1703)
else :
node _T_1705 = eq(io.rw.cmd, UInt<3>(0h2))
node _T_1706 = eq(io.rw.addr, UInt<12>(0hf15))
node _T_1707 = and(_T_1705, _T_1706)
wire set_vs_dirty : UInt<1>
connect set_vs_dirty, UInt<1>(0h0)
wire set_fs_dirty : UInt<1>
connect set_fs_dirty, UInt<1>(0h0)
connect io.fcsr_rm, reg_frm
when io.fcsr_flags.valid :
node _reg_fflags_T = or(reg_fflags, io.fcsr_flags.bits)
connect reg_fflags, _reg_fflags_T
connect set_fs_dirty, UInt<1>(0h1)
node _csr_wen_T = eq(io.rw.cmd, UInt<3>(0h6))
node _csr_wen_T_1 = eq(io.rw.cmd, UInt<3>(0h7))
node _csr_wen_T_2 = eq(io.rw.cmd, UInt<3>(0h5))
node _csr_wen_T_3 = or(_csr_wen_T, _csr_wen_T_1)
node _csr_wen_T_4 = or(_csr_wen_T_3, _csr_wen_T_2)
node _csr_wen_T_5 = eq(io.rw_stall, UInt<1>(0h0))
node csr_wen = and(_csr_wen_T_4, _csr_wen_T_5)
node _io_csrw_counter_T = and(UInt<1>(0h1), csr_wen)
node _io_csrw_counter_T_1 = geq(io.rw.addr, UInt<12>(0hb00))
node _io_csrw_counter_T_2 = lt(io.rw.addr, UInt<12>(0hb20))
node _io_csrw_counter_T_3 = and(_io_csrw_counter_T_1, _io_csrw_counter_T_2)
node _io_csrw_counter_T_4 = geq(io.rw.addr, UInt<12>(0hb80))
node _io_csrw_counter_T_5 = lt(io.rw.addr, UInt<12>(0hba0))
node _io_csrw_counter_T_6 = and(_io_csrw_counter_T_4, _io_csrw_counter_T_5)
node _io_csrw_counter_T_7 = or(_io_csrw_counter_T_3, _io_csrw_counter_T_6)
node _io_csrw_counter_T_8 = and(_io_csrw_counter_T, _io_csrw_counter_T_7)
node _io_csrw_counter_T_9 = bits(io.rw.addr, 4, 0)
node _io_csrw_counter_T_10 = dshl(UInt<1>(0h1), _io_csrw_counter_T_9)
node _io_csrw_counter_T_11 = mux(_io_csrw_counter_T_8, _io_csrw_counter_T_10, UInt<1>(0h0))
connect io.csrw_counter, _io_csrw_counter_T_11
when csr_wen :
when decoded_addr_100_2 :
wire new_mstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}
wire _new_mstatus_WIRE : UInt<105>
connect _new_mstatus_WIRE, wdata
node _new_mstatus_T = bits(_new_mstatus_WIRE, 0, 0)
connect new_mstatus.uie, _new_mstatus_T
node _new_mstatus_T_1 = bits(_new_mstatus_WIRE, 1, 1)
connect new_mstatus.sie, _new_mstatus_T_1
node _new_mstatus_T_2 = bits(_new_mstatus_WIRE, 2, 2)
connect new_mstatus.hie, _new_mstatus_T_2
node _new_mstatus_T_3 = bits(_new_mstatus_WIRE, 3, 3)
connect new_mstatus.mie, _new_mstatus_T_3
node _new_mstatus_T_4 = bits(_new_mstatus_WIRE, 4, 4)
connect new_mstatus.upie, _new_mstatus_T_4
node _new_mstatus_T_5 = bits(_new_mstatus_WIRE, 5, 5)
connect new_mstatus.spie, _new_mstatus_T_5
node _new_mstatus_T_6 = bits(_new_mstatus_WIRE, 6, 6)
connect new_mstatus.ube, _new_mstatus_T_6
node _new_mstatus_T_7 = bits(_new_mstatus_WIRE, 7, 7)
connect new_mstatus.mpie, _new_mstatus_T_7
node _new_mstatus_T_8 = bits(_new_mstatus_WIRE, 8, 8)
connect new_mstatus.spp, _new_mstatus_T_8
node _new_mstatus_T_9 = bits(_new_mstatus_WIRE, 10, 9)
connect new_mstatus.vs, _new_mstatus_T_9
node _new_mstatus_T_10 = bits(_new_mstatus_WIRE, 12, 11)
connect new_mstatus.mpp, _new_mstatus_T_10
node _new_mstatus_T_11 = bits(_new_mstatus_WIRE, 14, 13)
connect new_mstatus.fs, _new_mstatus_T_11
node _new_mstatus_T_12 = bits(_new_mstatus_WIRE, 16, 15)
connect new_mstatus.xs, _new_mstatus_T_12
node _new_mstatus_T_13 = bits(_new_mstatus_WIRE, 17, 17)
connect new_mstatus.mprv, _new_mstatus_T_13
node _new_mstatus_T_14 = bits(_new_mstatus_WIRE, 18, 18)
connect new_mstatus.sum, _new_mstatus_T_14
node _new_mstatus_T_15 = bits(_new_mstatus_WIRE, 19, 19)
connect new_mstatus.mxr, _new_mstatus_T_15
node _new_mstatus_T_16 = bits(_new_mstatus_WIRE, 20, 20)
connect new_mstatus.tvm, _new_mstatus_T_16
node _new_mstatus_T_17 = bits(_new_mstatus_WIRE, 21, 21)
connect new_mstatus.tw, _new_mstatus_T_17
node _new_mstatus_T_18 = bits(_new_mstatus_WIRE, 22, 22)
connect new_mstatus.tsr, _new_mstatus_T_18
node _new_mstatus_T_19 = bits(_new_mstatus_WIRE, 30, 23)
connect new_mstatus.zero1, _new_mstatus_T_19
node _new_mstatus_T_20 = bits(_new_mstatus_WIRE, 31, 31)
connect new_mstatus.sd_rv32, _new_mstatus_T_20
node _new_mstatus_T_21 = bits(_new_mstatus_WIRE, 33, 32)
connect new_mstatus.uxl, _new_mstatus_T_21
node _new_mstatus_T_22 = bits(_new_mstatus_WIRE, 35, 34)
connect new_mstatus.sxl, _new_mstatus_T_22
node _new_mstatus_T_23 = bits(_new_mstatus_WIRE, 36, 36)
connect new_mstatus.sbe, _new_mstatus_T_23
node _new_mstatus_T_24 = bits(_new_mstatus_WIRE, 37, 37)
connect new_mstatus.mbe, _new_mstatus_T_24
node _new_mstatus_T_25 = bits(_new_mstatus_WIRE, 38, 38)
connect new_mstatus.gva, _new_mstatus_T_25
node _new_mstatus_T_26 = bits(_new_mstatus_WIRE, 39, 39)
connect new_mstatus.mpv, _new_mstatus_T_26
node _new_mstatus_T_27 = bits(_new_mstatus_WIRE, 62, 40)
connect new_mstatus.zero2, _new_mstatus_T_27
node _new_mstatus_T_28 = bits(_new_mstatus_WIRE, 63, 63)
connect new_mstatus.sd, _new_mstatus_T_28
node _new_mstatus_T_29 = bits(_new_mstatus_WIRE, 64, 64)
connect new_mstatus.v, _new_mstatus_T_29
node _new_mstatus_T_30 = bits(_new_mstatus_WIRE, 66, 65)
connect new_mstatus.prv, _new_mstatus_T_30
node _new_mstatus_T_31 = bits(_new_mstatus_WIRE, 67, 67)
connect new_mstatus.dv, _new_mstatus_T_31
node _new_mstatus_T_32 = bits(_new_mstatus_WIRE, 69, 68)
connect new_mstatus.dprv, _new_mstatus_T_32
node _new_mstatus_T_33 = bits(_new_mstatus_WIRE, 101, 70)
connect new_mstatus.isa, _new_mstatus_T_33
node _new_mstatus_T_34 = bits(_new_mstatus_WIRE, 102, 102)
connect new_mstatus.wfi, _new_mstatus_T_34
node _new_mstatus_T_35 = bits(_new_mstatus_WIRE, 103, 103)
connect new_mstatus.cease, _new_mstatus_T_35
node _new_mstatus_T_36 = bits(_new_mstatus_WIRE, 104, 104)
connect new_mstatus.debug, _new_mstatus_T_36
connect reg_mstatus.mie, new_mstatus.mie
connect reg_mstatus.mpie, new_mstatus.mpie
connect reg_mstatus.mprv, new_mstatus.mprv
node _reg_mstatus_mpp_T_2 = eq(new_mstatus.mpp, UInt<2>(0h2))
node _reg_mstatus_mpp_T_3 = mux(_reg_mstatus_mpp_T_2, UInt<1>(0h0), new_mstatus.mpp)
connect reg_mstatus.mpp, _reg_mstatus_mpp_T_3
connect reg_mstatus.spp, new_mstatus.spp
connect reg_mstatus.spie, new_mstatus.spie
connect reg_mstatus.sie, new_mstatus.sie
connect reg_mstatus.tw, new_mstatus.tw
connect reg_mstatus.tsr, new_mstatus.tsr
connect reg_mstatus.mxr, new_mstatus.mxr
connect reg_mstatus.sum, new_mstatus.sum
connect reg_mstatus.tvm, new_mstatus.tvm
node _reg_mstatus_fs_T = orr(new_mstatus.fs)
node _reg_mstatus_fs_T_1 = mux(_reg_mstatus_fs_T, UInt<2>(0h3), UInt<2>(0h0))
connect reg_mstatus.fs, _reg_mstatus_fs_T_1
connect reg_mstatus.vs, UInt<1>(0h0)
when decoded_addr_94_2 :
node f = bits(wdata, 5, 5)
node _T_1708 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _T_1709 = bits(io.pc, 1, 1)
node _T_1710 = eq(_T_1709, UInt<1>(0h0))
node _T_1711 = or(_T_1708, _T_1710)
node _T_1712 = bits(wdata, 2, 2)
node _T_1713 = or(_T_1711, _T_1712)
when _T_1713 :
node _reg_misa_T = not(wdata)
node _reg_misa_T_1 = eq(f, UInt<1>(0h0))
node _reg_misa_T_2 = shl(_reg_misa_T_1, 3)
node _reg_misa_T_3 = or(_reg_misa_T, _reg_misa_T_2)
node _reg_misa_T_4 = not(_reg_misa_T_3)
node _reg_misa_T_5 = and(_reg_misa_T_4, UInt<64>(0h102d))
node _reg_misa_T_6 = not(UInt<64>(0h102d))
node _reg_misa_T_7 = and(reg_misa, _reg_misa_T_6)
node _reg_misa_T_8 = or(_reg_misa_T_5, _reg_misa_T_7)
connect reg_misa, _reg_misa_T_8
when decoded_addr_108_2 :
node new_mip_lo_lo_lo = cat(reg_mip.ssip, reg_mip.usip)
node new_mip_lo_lo_hi = cat(reg_mip.msip, reg_mip.vssip)
node new_mip_lo_lo = cat(new_mip_lo_lo_hi, new_mip_lo_lo_lo)
node new_mip_lo_hi_lo = cat(reg_mip.stip, reg_mip.utip)
node new_mip_lo_hi_hi = cat(reg_mip.mtip, reg_mip.vstip)
node new_mip_lo_hi = cat(new_mip_lo_hi_hi, new_mip_lo_hi_lo)
node new_mip_lo = cat(new_mip_lo_hi, new_mip_lo_lo)
node new_mip_hi_lo_lo = cat(reg_mip.seip, reg_mip.ueip)
node new_mip_hi_lo_hi = cat(reg_mip.meip, reg_mip.vseip)
node new_mip_hi_lo = cat(new_mip_hi_lo_hi, new_mip_hi_lo_lo)
node new_mip_hi_hi_lo = cat(reg_mip.rocc, reg_mip.sgeip)
node new_mip_hi_hi_hi_hi = cat(UInt<0>(0h0), reg_mip.zero1)
node new_mip_hi_hi_hi = cat(new_mip_hi_hi_hi_hi, reg_mip.debug)
node new_mip_hi_hi = cat(new_mip_hi_hi_hi, new_mip_hi_hi_lo)
node new_mip_hi = cat(new_mip_hi_hi, new_mip_hi_lo)
node _new_mip_T = cat(new_mip_hi, new_mip_lo)
node _new_mip_T_1 = bits(io.rw.cmd, 1, 1)
node _new_mip_T_2 = mux(_new_mip_T_1, _new_mip_T, UInt<1>(0h0))
node _new_mip_T_3 = or(_new_mip_T_2, io.rw.wdata)
node _new_mip_T_4 = bits(io.rw.cmd, 1, 0)
node _new_mip_T_5 = andr(_new_mip_T_4)
node _new_mip_T_6 = mux(_new_mip_T_5, io.rw.wdata, UInt<1>(0h0))
node _new_mip_T_7 = not(_new_mip_T_6)
node _new_mip_T_8 = and(_new_mip_T_3, _new_mip_T_7)
wire new_mip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
wire _new_mip_WIRE : UInt<16>
connect _new_mip_WIRE, _new_mip_T_8
node _new_mip_T_9 = bits(_new_mip_WIRE, 0, 0)
connect new_mip.usip, _new_mip_T_9
node _new_mip_T_10 = bits(_new_mip_WIRE, 1, 1)
connect new_mip.ssip, _new_mip_T_10
node _new_mip_T_11 = bits(_new_mip_WIRE, 2, 2)
connect new_mip.vssip, _new_mip_T_11
node _new_mip_T_12 = bits(_new_mip_WIRE, 3, 3)
connect new_mip.msip, _new_mip_T_12
node _new_mip_T_13 = bits(_new_mip_WIRE, 4, 4)
connect new_mip.utip, _new_mip_T_13
node _new_mip_T_14 = bits(_new_mip_WIRE, 5, 5)
connect new_mip.stip, _new_mip_T_14
node _new_mip_T_15 = bits(_new_mip_WIRE, 6, 6)
connect new_mip.vstip, _new_mip_T_15
node _new_mip_T_16 = bits(_new_mip_WIRE, 7, 7)
connect new_mip.mtip, _new_mip_T_16
node _new_mip_T_17 = bits(_new_mip_WIRE, 8, 8)
connect new_mip.ueip, _new_mip_T_17
node _new_mip_T_18 = bits(_new_mip_WIRE, 9, 9)
connect new_mip.seip, _new_mip_T_18
node _new_mip_T_19 = bits(_new_mip_WIRE, 10, 10)
connect new_mip.vseip, _new_mip_T_19
node _new_mip_T_20 = bits(_new_mip_WIRE, 11, 11)
connect new_mip.meip, _new_mip_T_20
node _new_mip_T_21 = bits(_new_mip_WIRE, 12, 12)
connect new_mip.sgeip, _new_mip_T_21
node _new_mip_T_22 = bits(_new_mip_WIRE, 13, 13)
connect new_mip.rocc, _new_mip_T_22
node _new_mip_T_23 = bits(_new_mip_WIRE, 14, 14)
connect new_mip.debug, _new_mip_T_23
node _new_mip_T_24 = bits(_new_mip_WIRE, 15, 15)
connect new_mip.zero1, _new_mip_T_24
connect reg_mip.ssip, new_mip.ssip
connect reg_mip.stip, new_mip.stip
connect reg_mip.seip, new_mip.seip
when decoded_addr_76_2 :
node _reg_mie_T = and(wdata, supported_interrupts)
connect reg_mie, _reg_mie_T
when decoded_addr_132_2 :
node _reg_mepc_T = not(wdata)
node _reg_mepc_T_1 = or(_reg_mepc_T, UInt<1>(0h1))
node _reg_mepc_T_2 = not(_reg_mepc_T_1)
connect reg_mepc, _reg_mepc_T_2
when decoded_addr_129_2 :
connect reg_mscratch, wdata
when decoded_addr_72_2 :
connect reg_mtvec, wdata
when decoded_addr_29_2 :
node _reg_mcause_T = and(wdata, UInt<64>(0h800000000000000f))
connect reg_mcause, _reg_mcause_T
when decoded_addr_136_2 :
connect reg_mtval, wdata
when decoded_addr_130_2 :
node _reg_mcountinhibit_T = not(UInt<64>(0h2))
node _reg_mcountinhibit_T_1 = and(wdata, _reg_mcountinhibit_T)
connect reg_mcountinhibit, _reg_mcountinhibit_T_1
when decoded_addr_103_2 :
node _T_1714 = bits(wdata, 63, 0)
connect small_1, _T_1714
node _large_T_6 = shr(_T_1714, 6)
connect large_1, _large_T_6
when decoded_addr_121_2 :
node _T_1715 = bits(wdata, 63, 0)
connect small, _T_1715
node _large_T_7 = shr(_T_1715, 6)
connect large, _large_T_7
when decoded_addr_36_2 :
connect set_fs_dirty, UInt<1>(0h1)
connect reg_fflags, wdata
when decoded_addr_68_2 :
connect set_fs_dirty, UInt<1>(0h1)
connect reg_frm, wdata
when decoded_addr_99_2 :
connect set_fs_dirty, UInt<1>(0h1)
connect reg_fflags, wdata
node _reg_frm_T = shr(wdata, 5)
connect reg_frm, _reg_frm_T
when decoded_addr_49_2 :
wire new_dcsr : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>}
wire _new_dcsr_WIRE : UInt<32>
connect _new_dcsr_WIRE, wdata
node _new_dcsr_T = bits(_new_dcsr_WIRE, 1, 0)
connect new_dcsr.prv, _new_dcsr_T
node _new_dcsr_T_1 = bits(_new_dcsr_WIRE, 2, 2)
connect new_dcsr.step, _new_dcsr_T_1
node _new_dcsr_T_2 = bits(_new_dcsr_WIRE, 4, 3)
connect new_dcsr.zero1, _new_dcsr_T_2
node _new_dcsr_T_3 = bits(_new_dcsr_WIRE, 5, 5)
connect new_dcsr.v, _new_dcsr_T_3
node _new_dcsr_T_4 = bits(_new_dcsr_WIRE, 8, 6)
connect new_dcsr.cause, _new_dcsr_T_4
node _new_dcsr_T_5 = bits(_new_dcsr_WIRE, 9, 9)
connect new_dcsr.stoptime, _new_dcsr_T_5
node _new_dcsr_T_6 = bits(_new_dcsr_WIRE, 10, 10)
connect new_dcsr.stopcycle, _new_dcsr_T_6
node _new_dcsr_T_7 = bits(_new_dcsr_WIRE, 11, 11)
connect new_dcsr.zero2, _new_dcsr_T_7
node _new_dcsr_T_8 = bits(_new_dcsr_WIRE, 12, 12)
connect new_dcsr.ebreaku, _new_dcsr_T_8
node _new_dcsr_T_9 = bits(_new_dcsr_WIRE, 13, 13)
connect new_dcsr.ebreaks, _new_dcsr_T_9
node _new_dcsr_T_10 = bits(_new_dcsr_WIRE, 14, 14)
connect new_dcsr.ebreakh, _new_dcsr_T_10
node _new_dcsr_T_11 = bits(_new_dcsr_WIRE, 15, 15)
connect new_dcsr.ebreakm, _new_dcsr_T_11
node _new_dcsr_T_12 = bits(_new_dcsr_WIRE, 27, 16)
connect new_dcsr.zero3, _new_dcsr_T_12
node _new_dcsr_T_13 = bits(_new_dcsr_WIRE, 29, 28)
connect new_dcsr.zero4, _new_dcsr_T_13
node _new_dcsr_T_14 = bits(_new_dcsr_WIRE, 31, 30)
connect new_dcsr.xdebugver, _new_dcsr_T_14
connect reg_dcsr.step, new_dcsr.step
connect reg_dcsr.ebreakm, new_dcsr.ebreakm
connect reg_dcsr.ebreaks, new_dcsr.ebreaks
connect reg_dcsr.ebreaku, new_dcsr.ebreaku
node _reg_dcsr_prv_T = eq(new_dcsr.prv, UInt<2>(0h2))
node _reg_dcsr_prv_T_1 = mux(_reg_dcsr_prv_T, UInt<1>(0h0), new_dcsr.prv)
connect reg_dcsr.prv, _reg_dcsr_prv_T_1
when decoded_addr_89_2 :
node _reg_dpc_T = not(wdata)
node _reg_dpc_T_1 = or(_reg_dpc_T, UInt<1>(0h1))
node _reg_dpc_T_2 = not(_reg_dpc_T_1)
connect reg_dpc, _reg_dpc_T_2
when decoded_addr_57_2 :
connect reg_dscratch0, wdata
when decoded_addr_61_2 :
wire new_sstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}
wire _new_sstatus_WIRE : UInt<105>
connect _new_sstatus_WIRE, wdata
node _new_sstatus_T = bits(_new_sstatus_WIRE, 0, 0)
connect new_sstatus.uie, _new_sstatus_T
node _new_sstatus_T_1 = bits(_new_sstatus_WIRE, 1, 1)
connect new_sstatus.sie, _new_sstatus_T_1
node _new_sstatus_T_2 = bits(_new_sstatus_WIRE, 2, 2)
connect new_sstatus.hie, _new_sstatus_T_2
node _new_sstatus_T_3 = bits(_new_sstatus_WIRE, 3, 3)
connect new_sstatus.mie, _new_sstatus_T_3
node _new_sstatus_T_4 = bits(_new_sstatus_WIRE, 4, 4)
connect new_sstatus.upie, _new_sstatus_T_4
node _new_sstatus_T_5 = bits(_new_sstatus_WIRE, 5, 5)
connect new_sstatus.spie, _new_sstatus_T_5
node _new_sstatus_T_6 = bits(_new_sstatus_WIRE, 6, 6)
connect new_sstatus.ube, _new_sstatus_T_6
node _new_sstatus_T_7 = bits(_new_sstatus_WIRE, 7, 7)
connect new_sstatus.mpie, _new_sstatus_T_7
node _new_sstatus_T_8 = bits(_new_sstatus_WIRE, 8, 8)
connect new_sstatus.spp, _new_sstatus_T_8
node _new_sstatus_T_9 = bits(_new_sstatus_WIRE, 10, 9)
connect new_sstatus.vs, _new_sstatus_T_9
node _new_sstatus_T_10 = bits(_new_sstatus_WIRE, 12, 11)
connect new_sstatus.mpp, _new_sstatus_T_10
node _new_sstatus_T_11 = bits(_new_sstatus_WIRE, 14, 13)
connect new_sstatus.fs, _new_sstatus_T_11
node _new_sstatus_T_12 = bits(_new_sstatus_WIRE, 16, 15)
connect new_sstatus.xs, _new_sstatus_T_12
node _new_sstatus_T_13 = bits(_new_sstatus_WIRE, 17, 17)
connect new_sstatus.mprv, _new_sstatus_T_13
node _new_sstatus_T_14 = bits(_new_sstatus_WIRE, 18, 18)
connect new_sstatus.sum, _new_sstatus_T_14
node _new_sstatus_T_15 = bits(_new_sstatus_WIRE, 19, 19)
connect new_sstatus.mxr, _new_sstatus_T_15
node _new_sstatus_T_16 = bits(_new_sstatus_WIRE, 20, 20)
connect new_sstatus.tvm, _new_sstatus_T_16
node _new_sstatus_T_17 = bits(_new_sstatus_WIRE, 21, 21)
connect new_sstatus.tw, _new_sstatus_T_17
node _new_sstatus_T_18 = bits(_new_sstatus_WIRE, 22, 22)
connect new_sstatus.tsr, _new_sstatus_T_18
node _new_sstatus_T_19 = bits(_new_sstatus_WIRE, 30, 23)
connect new_sstatus.zero1, _new_sstatus_T_19
node _new_sstatus_T_20 = bits(_new_sstatus_WIRE, 31, 31)
connect new_sstatus.sd_rv32, _new_sstatus_T_20
node _new_sstatus_T_21 = bits(_new_sstatus_WIRE, 33, 32)
connect new_sstatus.uxl, _new_sstatus_T_21
node _new_sstatus_T_22 = bits(_new_sstatus_WIRE, 35, 34)
connect new_sstatus.sxl, _new_sstatus_T_22
node _new_sstatus_T_23 = bits(_new_sstatus_WIRE, 36, 36)
connect new_sstatus.sbe, _new_sstatus_T_23
node _new_sstatus_T_24 = bits(_new_sstatus_WIRE, 37, 37)
connect new_sstatus.mbe, _new_sstatus_T_24
node _new_sstatus_T_25 = bits(_new_sstatus_WIRE, 38, 38)
connect new_sstatus.gva, _new_sstatus_T_25
node _new_sstatus_T_26 = bits(_new_sstatus_WIRE, 39, 39)
connect new_sstatus.mpv, _new_sstatus_T_26
node _new_sstatus_T_27 = bits(_new_sstatus_WIRE, 62, 40)
connect new_sstatus.zero2, _new_sstatus_T_27
node _new_sstatus_T_28 = bits(_new_sstatus_WIRE, 63, 63)
connect new_sstatus.sd, _new_sstatus_T_28
node _new_sstatus_T_29 = bits(_new_sstatus_WIRE, 64, 64)
connect new_sstatus.v, _new_sstatus_T_29
node _new_sstatus_T_30 = bits(_new_sstatus_WIRE, 66, 65)
connect new_sstatus.prv, _new_sstatus_T_30
node _new_sstatus_T_31 = bits(_new_sstatus_WIRE, 67, 67)
connect new_sstatus.dv, _new_sstatus_T_31
node _new_sstatus_T_32 = bits(_new_sstatus_WIRE, 69, 68)
connect new_sstatus.dprv, _new_sstatus_T_32
node _new_sstatus_T_33 = bits(_new_sstatus_WIRE, 101, 70)
connect new_sstatus.isa, _new_sstatus_T_33
node _new_sstatus_T_34 = bits(_new_sstatus_WIRE, 102, 102)
connect new_sstatus.wfi, _new_sstatus_T_34
node _new_sstatus_T_35 = bits(_new_sstatus_WIRE, 103, 103)
connect new_sstatus.cease, _new_sstatus_T_35
node _new_sstatus_T_36 = bits(_new_sstatus_WIRE, 104, 104)
connect new_sstatus.debug, _new_sstatus_T_36
connect reg_mstatus.sie, new_sstatus.sie
connect reg_mstatus.spie, new_sstatus.spie
connect reg_mstatus.spp, new_sstatus.spp
node _reg_mstatus_fs_T_2 = orr(new_sstatus.fs)
node _reg_mstatus_fs_T_3 = mux(_reg_mstatus_fs_T_2, UInt<2>(0h3), UInt<2>(0h0))
connect reg_mstatus.fs, _reg_mstatus_fs_T_3
connect reg_mstatus.vs, UInt<1>(0h0)
connect reg_mstatus.mxr, new_sstatus.mxr
connect reg_mstatus.sum, new_sstatus.sum
when decoded_addr_48_2 :
node _new_sip_T = not(read_mideleg)
node _new_sip_T_1 = and(read_mip, _new_sip_T)
node _new_sip_T_2 = and(wdata, read_mideleg)
node _new_sip_T_3 = or(_new_sip_T_1, _new_sip_T_2)
wire new_sip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}
wire _new_sip_WIRE : UInt<16>
connect _new_sip_WIRE, _new_sip_T_3
node _new_sip_T_4 = bits(_new_sip_WIRE, 0, 0)
connect new_sip.usip, _new_sip_T_4
node _new_sip_T_5 = bits(_new_sip_WIRE, 1, 1)
connect new_sip.ssip, _new_sip_T_5
node _new_sip_T_6 = bits(_new_sip_WIRE, 2, 2)
connect new_sip.vssip, _new_sip_T_6
node _new_sip_T_7 = bits(_new_sip_WIRE, 3, 3)
connect new_sip.msip, _new_sip_T_7
node _new_sip_T_8 = bits(_new_sip_WIRE, 4, 4)
connect new_sip.utip, _new_sip_T_8
node _new_sip_T_9 = bits(_new_sip_WIRE, 5, 5)
connect new_sip.stip, _new_sip_T_9
node _new_sip_T_10 = bits(_new_sip_WIRE, 6, 6)
connect new_sip.vstip, _new_sip_T_10
node _new_sip_T_11 = bits(_new_sip_WIRE, 7, 7)
connect new_sip.mtip, _new_sip_T_11
node _new_sip_T_12 = bits(_new_sip_WIRE, 8, 8)
connect new_sip.ueip, _new_sip_T_12
node _new_sip_T_13 = bits(_new_sip_WIRE, 9, 9)
connect new_sip.seip, _new_sip_T_13
node _new_sip_T_14 = bits(_new_sip_WIRE, 10, 10)
connect new_sip.vseip, _new_sip_T_14
node _new_sip_T_15 = bits(_new_sip_WIRE, 11, 11)
connect new_sip.meip, _new_sip_T_15
node _new_sip_T_16 = bits(_new_sip_WIRE, 12, 12)
connect new_sip.sgeip, _new_sip_T_16
node _new_sip_T_17 = bits(_new_sip_WIRE, 13, 13)
connect new_sip.rocc, _new_sip_T_17
node _new_sip_T_18 = bits(_new_sip_WIRE, 14, 14)
connect new_sip.debug, _new_sip_T_18
node _new_sip_T_19 = bits(_new_sip_WIRE, 15, 15)
connect new_sip.zero1, _new_sip_T_19
connect reg_mip.ssip, new_sip.ssip
when decoded_addr_6_2 :
wire new_satp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}
wire _new_satp_WIRE : UInt<64>
connect _new_satp_WIRE, wdata
node _new_satp_T = bits(_new_satp_WIRE, 43, 0)
connect new_satp.ppn, _new_satp_T
node _new_satp_T_1 = bits(_new_satp_WIRE, 59, 44)
connect new_satp.asid, _new_satp_T_1
node _new_satp_T_2 = bits(_new_satp_WIRE, 63, 60)
connect new_satp.mode, _new_satp_T_2
node _T_1716 = eq(new_satp.mode, UInt<1>(0h0))
node _T_1717 = eq(new_satp.mode, UInt<4>(0h8))
node _T_1718 = or(_T_1716, _T_1717)
when _T_1718 :
node _reg_satp_mode_T = and(new_satp.mode, UInt<4>(0h8))
connect reg_satp.mode, _reg_satp_mode_T
node _reg_satp_ppn_T = bits(new_satp.ppn, 19, 0)
connect reg_satp.ppn, _reg_satp_ppn_T
when decoded_addr_44_2 :
node _reg_mie_T_1 = not(sie_mask)
node _reg_mie_T_2 = and(reg_mie, _reg_mie_T_1)
node _reg_mie_T_3 = and(wdata, sie_mask)
node _reg_mie_T_4 = or(_reg_mie_T_2, _reg_mie_T_3)
connect reg_mie, _reg_mie_T_4
when decoded_addr_15_2 :
connect reg_sscratch, wdata
when decoded_addr_28_2 :
node _reg_sepc_T = not(wdata)
node _reg_sepc_T_1 = or(_reg_sepc_T, UInt<1>(0h1))
node _reg_sepc_T_2 = not(_reg_sepc_T_1)
connect reg_sepc, _reg_sepc_T_2
when decoded_addr_25_2 :
connect reg_stvec, wdata
when decoded_addr_145_2 :
node _reg_scause_T = and(wdata, UInt<64>(0h800000000000001f))
connect reg_scause, _reg_scause_T
when decoded_addr_93_2 :
connect reg_stval, wdata
when decoded_addr_123_2 :
connect reg_mideleg, wdata
when decoded_addr_23_2 :
connect reg_medeleg, wdata
when decoded_addr_137_2 :
connect reg_scounteren, wdata
when decoded_addr_69_2 :
wire new_envcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}
wire _new_envcfg_WIRE : UInt<64>
connect _new_envcfg_WIRE, wdata
node _new_envcfg_T = bits(_new_envcfg_WIRE, 0, 0)
connect new_envcfg.fiom, _new_envcfg_T
node _new_envcfg_T_1 = bits(_new_envcfg_WIRE, 3, 1)
connect new_envcfg.zero3, _new_envcfg_T_1
node _new_envcfg_T_2 = bits(_new_envcfg_WIRE, 5, 4)
connect new_envcfg.cbie, _new_envcfg_T_2
node _new_envcfg_T_3 = bits(_new_envcfg_WIRE, 6, 6)
connect new_envcfg.cbcfe, _new_envcfg_T_3
node _new_envcfg_T_4 = bits(_new_envcfg_WIRE, 7, 7)
connect new_envcfg.cbze, _new_envcfg_T_4
node _new_envcfg_T_5 = bits(_new_envcfg_WIRE, 61, 8)
connect new_envcfg.zero54, _new_envcfg_T_5
node _new_envcfg_T_6 = bits(_new_envcfg_WIRE, 62, 62)
connect new_envcfg.pbmte, _new_envcfg_T_6
node _new_envcfg_T_7 = bits(_new_envcfg_WIRE, 63, 63)
connect new_envcfg.stce, _new_envcfg_T_7
connect reg_senvcfg.fiom, new_envcfg.fiom
when decoded_addr_35_2 :
connect reg_mcounteren, wdata
when decoded_addr_42_2 :
wire new_envcfg_1 : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}
wire _new_envcfg_WIRE_1 : UInt<64>
connect _new_envcfg_WIRE_1, wdata
node _new_envcfg_T_8 = bits(_new_envcfg_WIRE_1, 0, 0)
connect new_envcfg_1.fiom, _new_envcfg_T_8
node _new_envcfg_T_9 = bits(_new_envcfg_WIRE_1, 3, 1)
connect new_envcfg_1.zero3, _new_envcfg_T_9
node _new_envcfg_T_10 = bits(_new_envcfg_WIRE_1, 5, 4)
connect new_envcfg_1.cbie, _new_envcfg_T_10
node _new_envcfg_T_11 = bits(_new_envcfg_WIRE_1, 6, 6)
connect new_envcfg_1.cbcfe, _new_envcfg_T_11
node _new_envcfg_T_12 = bits(_new_envcfg_WIRE_1, 7, 7)
connect new_envcfg_1.cbze, _new_envcfg_T_12
node _new_envcfg_T_13 = bits(_new_envcfg_WIRE_1, 61, 8)
connect new_envcfg_1.zero54, _new_envcfg_T_13
node _new_envcfg_T_14 = bits(_new_envcfg_WIRE_1, 62, 62)
connect new_envcfg_1.pbmte, _new_envcfg_T_14
node _new_envcfg_T_15 = bits(_new_envcfg_WIRE_1, 63, 63)
connect new_envcfg_1.stce, _new_envcfg_T_15
connect reg_menvcfg.fiom, new_envcfg_1.fiom
when decoded_addr_97_2 :
connect reg_tselect, wdata
node _T_1719 = eq(UInt<1>(0h0), reg_tselect)
node _T_1720 = eq(reg_bp[0].control.dmode, UInt<1>(0h0))
node _T_1721 = or(_T_1720, reg_debug)
node _T_1722 = and(_T_1719, _T_1721)
when _T_1722 :
when decoded_addr_10_2 :
connect reg_bp[0].address, wdata
when decoded_addr_118_2 :
skip
when decoded_addr_55_2 :
wire _reg_bp_0_control_WIRE : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}
wire _reg_bp_0_control_WIRE_1 : UInt<64>
connect _reg_bp_0_control_WIRE_1, wdata
node _reg_bp_0_control_T = bits(_reg_bp_0_control_WIRE_1, 0, 0)
connect _reg_bp_0_control_WIRE.r, _reg_bp_0_control_T
node _reg_bp_0_control_T_1 = bits(_reg_bp_0_control_WIRE_1, 1, 1)
connect _reg_bp_0_control_WIRE.w, _reg_bp_0_control_T_1
node _reg_bp_0_control_T_2 = bits(_reg_bp_0_control_WIRE_1, 2, 2)
connect _reg_bp_0_control_WIRE.x, _reg_bp_0_control_T_2
node _reg_bp_0_control_T_3 = bits(_reg_bp_0_control_WIRE_1, 3, 3)
connect _reg_bp_0_control_WIRE.u, _reg_bp_0_control_T_3
node _reg_bp_0_control_T_4 = bits(_reg_bp_0_control_WIRE_1, 4, 4)
connect _reg_bp_0_control_WIRE.s, _reg_bp_0_control_T_4
node _reg_bp_0_control_T_5 = bits(_reg_bp_0_control_WIRE_1, 5, 5)
connect _reg_bp_0_control_WIRE.h, _reg_bp_0_control_T_5
node _reg_bp_0_control_T_6 = bits(_reg_bp_0_control_WIRE_1, 6, 6)
connect _reg_bp_0_control_WIRE.m, _reg_bp_0_control_T_6
node _reg_bp_0_control_T_7 = bits(_reg_bp_0_control_WIRE_1, 8, 7)
connect _reg_bp_0_control_WIRE.tmatch, _reg_bp_0_control_T_7
node _reg_bp_0_control_T_8 = bits(_reg_bp_0_control_WIRE_1, 10, 9)
connect _reg_bp_0_control_WIRE.zero, _reg_bp_0_control_T_8
node _reg_bp_0_control_T_9 = bits(_reg_bp_0_control_WIRE_1, 11, 11)
connect _reg_bp_0_control_WIRE.chain, _reg_bp_0_control_T_9
node _reg_bp_0_control_T_10 = bits(_reg_bp_0_control_WIRE_1, 12, 12)
connect _reg_bp_0_control_WIRE.action, _reg_bp_0_control_T_10
node _reg_bp_0_control_T_11 = bits(_reg_bp_0_control_WIRE_1, 52, 13)
connect _reg_bp_0_control_WIRE.reserved, _reg_bp_0_control_T_11
node _reg_bp_0_control_T_12 = bits(_reg_bp_0_control_WIRE_1, 58, 53)
connect _reg_bp_0_control_WIRE.maskmax, _reg_bp_0_control_T_12
node _reg_bp_0_control_T_13 = bits(_reg_bp_0_control_WIRE_1, 59, 59)
connect _reg_bp_0_control_WIRE.dmode, _reg_bp_0_control_T_13
node _reg_bp_0_control_T_14 = bits(_reg_bp_0_control_WIRE_1, 63, 60)
connect _reg_bp_0_control_WIRE.ttype, _reg_bp_0_control_T_14
connect reg_bp[0].control, _reg_bp_0_control_WIRE
node newBPC_lo_lo_hi = cat(reg_bp[0].control.x, reg_bp[0].control.w)
node newBPC_lo_lo = cat(newBPC_lo_lo_hi, reg_bp[0].control.r)
node newBPC_lo_hi_lo = cat(reg_bp[0].control.s, reg_bp[0].control.u)
node newBPC_lo_hi_hi = cat(reg_bp[0].control.m, reg_bp[0].control.h)
node newBPC_lo_hi = cat(newBPC_lo_hi_hi, newBPC_lo_hi_lo)
node newBPC_lo = cat(newBPC_lo_hi, newBPC_lo_lo)
node newBPC_hi_lo_lo = cat(reg_bp[0].control.zero, reg_bp[0].control.tmatch)
node newBPC_hi_lo_hi = cat(reg_bp[0].control.action, reg_bp[0].control.chain)
node newBPC_hi_lo = cat(newBPC_hi_lo_hi, newBPC_hi_lo_lo)
node newBPC_hi_hi_lo = cat(reg_bp[0].control.maskmax, reg_bp[0].control.reserved)
node newBPC_hi_hi_hi = cat(reg_bp[0].control.ttype, reg_bp[0].control.dmode)
node newBPC_hi_hi = cat(newBPC_hi_hi_hi, newBPC_hi_hi_lo)
node newBPC_hi = cat(newBPC_hi_hi, newBPC_hi_lo)
node _newBPC_T = cat(newBPC_hi, newBPC_lo)
node _newBPC_T_1 = bits(io.rw.cmd, 1, 1)
node _newBPC_T_2 = mux(_newBPC_T_1, _newBPC_T, UInt<1>(0h0))
node _newBPC_T_3 = or(_newBPC_T_2, io.rw.wdata)
node _newBPC_T_4 = bits(io.rw.cmd, 1, 0)
node _newBPC_T_5 = andr(_newBPC_T_4)
node _newBPC_T_6 = mux(_newBPC_T_5, io.rw.wdata, UInt<1>(0h0))
node _newBPC_T_7 = not(_newBPC_T_6)
node _newBPC_T_8 = and(_newBPC_T_3, _newBPC_T_7)
wire newBPC : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}
wire _newBPC_WIRE : UInt<64>
connect _newBPC_WIRE, _newBPC_T_8
node _newBPC_T_9 = bits(_newBPC_WIRE, 0, 0)
connect newBPC.r, _newBPC_T_9
node _newBPC_T_10 = bits(_newBPC_WIRE, 1, 1)
connect newBPC.w, _newBPC_T_10
node _newBPC_T_11 = bits(_newBPC_WIRE, 2, 2)
connect newBPC.x, _newBPC_T_11
node _newBPC_T_12 = bits(_newBPC_WIRE, 3, 3)
connect newBPC.u, _newBPC_T_12
node _newBPC_T_13 = bits(_newBPC_WIRE, 4, 4)
connect newBPC.s, _newBPC_T_13
node _newBPC_T_14 = bits(_newBPC_WIRE, 5, 5)
connect newBPC.h, _newBPC_T_14
node _newBPC_T_15 = bits(_newBPC_WIRE, 6, 6)
connect newBPC.m, _newBPC_T_15
node _newBPC_T_16 = bits(_newBPC_WIRE, 8, 7)
connect newBPC.tmatch, _newBPC_T_16
node _newBPC_T_17 = bits(_newBPC_WIRE, 10, 9)
connect newBPC.zero, _newBPC_T_17
node _newBPC_T_18 = bits(_newBPC_WIRE, 11, 11)
connect newBPC.chain, _newBPC_T_18
node _newBPC_T_19 = bits(_newBPC_WIRE, 12, 12)
connect newBPC.action, _newBPC_T_19
node _newBPC_T_20 = bits(_newBPC_WIRE, 52, 13)
connect newBPC.reserved, _newBPC_T_20
node _newBPC_T_21 = bits(_newBPC_WIRE, 58, 53)
connect newBPC.maskmax, _newBPC_T_21
node _newBPC_T_22 = bits(_newBPC_WIRE, 59, 59)
connect newBPC.dmode, _newBPC_T_22
node _newBPC_T_23 = bits(_newBPC_WIRE, 63, 60)
connect newBPC.ttype, _newBPC_T_23
node _dMode_T = and(newBPC.dmode, reg_debug)
node _dMode_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _dMode_T_2 = or(UInt<1>(0h0), _dMode_T_1)
node dMode = and(_dMode_T, _dMode_T_2)
connect reg_bp[0].control.dmode, dMode
node _T_1723 = gt(newBPC.action, UInt<1>(0h1))
node _T_1724 = or(dMode, _T_1723)
when _T_1724 :
connect reg_bp[0].control.action, newBPC.action
else :
connect reg_bp[0].control.action, UInt<1>(0h0)
node _reg_bp_0_control_chain_T = or(UInt<1>(0h0), UInt<1>(0h1))
node _reg_bp_0_control_chain_T_1 = eq(_reg_bp_0_control_chain_T, UInt<1>(0h0))
node _reg_bp_0_control_chain_T_2 = and(newBPC.chain, _reg_bp_0_control_chain_T_1)
node _reg_bp_0_control_chain_T_3 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _reg_bp_0_control_chain_T_4 = or(dMode, _reg_bp_0_control_chain_T_3)
node _reg_bp_0_control_chain_T_5 = and(_reg_bp_0_control_chain_T_2, _reg_bp_0_control_chain_T_4)
connect reg_bp[0].control.chain, _reg_bp_0_control_chain_T_5
node _T_1725 = eq(UInt<1>(0h1), reg_tselect)
node _T_1726 = eq(reg_bp[1].control.dmode, UInt<1>(0h0))
node _T_1727 = or(_T_1726, reg_debug)
node _T_1728 = and(_T_1725, _T_1727)
when _T_1728 :
when decoded_addr_10_2 :
connect reg_bp[1].address, wdata
when decoded_addr_118_2 :
skip
when decoded_addr_55_2 :
wire _reg_bp_1_control_WIRE : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}
wire _reg_bp_1_control_WIRE_1 : UInt<64>
connect _reg_bp_1_control_WIRE_1, wdata
node _reg_bp_1_control_T = bits(_reg_bp_1_control_WIRE_1, 0, 0)
connect _reg_bp_1_control_WIRE.r, _reg_bp_1_control_T
node _reg_bp_1_control_T_1 = bits(_reg_bp_1_control_WIRE_1, 1, 1)
connect _reg_bp_1_control_WIRE.w, _reg_bp_1_control_T_1
node _reg_bp_1_control_T_2 = bits(_reg_bp_1_control_WIRE_1, 2, 2)
connect _reg_bp_1_control_WIRE.x, _reg_bp_1_control_T_2
node _reg_bp_1_control_T_3 = bits(_reg_bp_1_control_WIRE_1, 3, 3)
connect _reg_bp_1_control_WIRE.u, _reg_bp_1_control_T_3
node _reg_bp_1_control_T_4 = bits(_reg_bp_1_control_WIRE_1, 4, 4)
connect _reg_bp_1_control_WIRE.s, _reg_bp_1_control_T_4
node _reg_bp_1_control_T_5 = bits(_reg_bp_1_control_WIRE_1, 5, 5)
connect _reg_bp_1_control_WIRE.h, _reg_bp_1_control_T_5
node _reg_bp_1_control_T_6 = bits(_reg_bp_1_control_WIRE_1, 6, 6)
connect _reg_bp_1_control_WIRE.m, _reg_bp_1_control_T_6
node _reg_bp_1_control_T_7 = bits(_reg_bp_1_control_WIRE_1, 8, 7)
connect _reg_bp_1_control_WIRE.tmatch, _reg_bp_1_control_T_7
node _reg_bp_1_control_T_8 = bits(_reg_bp_1_control_WIRE_1, 10, 9)
connect _reg_bp_1_control_WIRE.zero, _reg_bp_1_control_T_8
node _reg_bp_1_control_T_9 = bits(_reg_bp_1_control_WIRE_1, 11, 11)
connect _reg_bp_1_control_WIRE.chain, _reg_bp_1_control_T_9
node _reg_bp_1_control_T_10 = bits(_reg_bp_1_control_WIRE_1, 12, 12)
connect _reg_bp_1_control_WIRE.action, _reg_bp_1_control_T_10
node _reg_bp_1_control_T_11 = bits(_reg_bp_1_control_WIRE_1, 52, 13)
connect _reg_bp_1_control_WIRE.reserved, _reg_bp_1_control_T_11
node _reg_bp_1_control_T_12 = bits(_reg_bp_1_control_WIRE_1, 58, 53)
connect _reg_bp_1_control_WIRE.maskmax, _reg_bp_1_control_T_12
node _reg_bp_1_control_T_13 = bits(_reg_bp_1_control_WIRE_1, 59, 59)
connect _reg_bp_1_control_WIRE.dmode, _reg_bp_1_control_T_13
node _reg_bp_1_control_T_14 = bits(_reg_bp_1_control_WIRE_1, 63, 60)
connect _reg_bp_1_control_WIRE.ttype, _reg_bp_1_control_T_14
connect reg_bp[1].control, _reg_bp_1_control_WIRE
node newBPC_lo_lo_hi_1 = cat(reg_bp[1].control.x, reg_bp[1].control.w)
node newBPC_lo_lo_1 = cat(newBPC_lo_lo_hi_1, reg_bp[1].control.r)
node newBPC_lo_hi_lo_1 = cat(reg_bp[1].control.s, reg_bp[1].control.u)
node newBPC_lo_hi_hi_1 = cat(reg_bp[1].control.m, reg_bp[1].control.h)
node newBPC_lo_hi_1 = cat(newBPC_lo_hi_hi_1, newBPC_lo_hi_lo_1)
node newBPC_lo_1 = cat(newBPC_lo_hi_1, newBPC_lo_lo_1)
node newBPC_hi_lo_lo_1 = cat(reg_bp[1].control.zero, reg_bp[1].control.tmatch)
node newBPC_hi_lo_hi_1 = cat(reg_bp[1].control.action, reg_bp[1].control.chain)
node newBPC_hi_lo_1 = cat(newBPC_hi_lo_hi_1, newBPC_hi_lo_lo_1)
node newBPC_hi_hi_lo_1 = cat(reg_bp[1].control.maskmax, reg_bp[1].control.reserved)
node newBPC_hi_hi_hi_1 = cat(reg_bp[1].control.ttype, reg_bp[1].control.dmode)
node newBPC_hi_hi_1 = cat(newBPC_hi_hi_hi_1, newBPC_hi_hi_lo_1)
node newBPC_hi_1 = cat(newBPC_hi_hi_1, newBPC_hi_lo_1)
node _newBPC_T_24 = cat(newBPC_hi_1, newBPC_lo_1)
node _newBPC_T_25 = bits(io.rw.cmd, 1, 1)
node _newBPC_T_26 = mux(_newBPC_T_25, _newBPC_T_24, UInt<1>(0h0))
node _newBPC_T_27 = or(_newBPC_T_26, io.rw.wdata)
node _newBPC_T_28 = bits(io.rw.cmd, 1, 0)
node _newBPC_T_29 = andr(_newBPC_T_28)
node _newBPC_T_30 = mux(_newBPC_T_29, io.rw.wdata, UInt<1>(0h0))
node _newBPC_T_31 = not(_newBPC_T_30)
node _newBPC_T_32 = and(_newBPC_T_27, _newBPC_T_31)
wire newBPC_1 : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}
wire _newBPC_WIRE_1 : UInt<64>
connect _newBPC_WIRE_1, _newBPC_T_32
node _newBPC_T_33 = bits(_newBPC_WIRE_1, 0, 0)
connect newBPC_1.r, _newBPC_T_33
node _newBPC_T_34 = bits(_newBPC_WIRE_1, 1, 1)
connect newBPC_1.w, _newBPC_T_34
node _newBPC_T_35 = bits(_newBPC_WIRE_1, 2, 2)
connect newBPC_1.x, _newBPC_T_35
node _newBPC_T_36 = bits(_newBPC_WIRE_1, 3, 3)
connect newBPC_1.u, _newBPC_T_36
node _newBPC_T_37 = bits(_newBPC_WIRE_1, 4, 4)
connect newBPC_1.s, _newBPC_T_37
node _newBPC_T_38 = bits(_newBPC_WIRE_1, 5, 5)
connect newBPC_1.h, _newBPC_T_38
node _newBPC_T_39 = bits(_newBPC_WIRE_1, 6, 6)
connect newBPC_1.m, _newBPC_T_39
node _newBPC_T_40 = bits(_newBPC_WIRE_1, 8, 7)
connect newBPC_1.tmatch, _newBPC_T_40
node _newBPC_T_41 = bits(_newBPC_WIRE_1, 10, 9)
connect newBPC_1.zero, _newBPC_T_41
node _newBPC_T_42 = bits(_newBPC_WIRE_1, 11, 11)
connect newBPC_1.chain, _newBPC_T_42
node _newBPC_T_43 = bits(_newBPC_WIRE_1, 12, 12)
connect newBPC_1.action, _newBPC_T_43
node _newBPC_T_44 = bits(_newBPC_WIRE_1, 52, 13)
connect newBPC_1.reserved, _newBPC_T_44
node _newBPC_T_45 = bits(_newBPC_WIRE_1, 58, 53)
connect newBPC_1.maskmax, _newBPC_T_45
node _newBPC_T_46 = bits(_newBPC_WIRE_1, 59, 59)
connect newBPC_1.dmode, _newBPC_T_46
node _newBPC_T_47 = bits(_newBPC_WIRE_1, 63, 60)
connect newBPC_1.ttype, _newBPC_T_47
node _dMode_T_3 = and(newBPC_1.dmode, reg_debug)
node _dMode_T_4 = eq(reg_bp[0].control.chain, UInt<1>(0h0))
node _dMode_T_5 = or(reg_bp[0].control.dmode, _dMode_T_4)
node dMode_1 = and(_dMode_T_3, _dMode_T_5)
connect reg_bp[1].control.dmode, dMode_1
node _T_1729 = gt(newBPC_1.action, UInt<1>(0h1))
node _T_1730 = or(dMode_1, _T_1729)
when _T_1730 :
connect reg_bp[1].control.action, newBPC_1.action
else :
connect reg_bp[1].control.action, UInt<1>(0h0)
node _reg_bp_1_control_chain_T = or(reg_bp[0].control.chain, UInt<1>(0h1))
node _reg_bp_1_control_chain_T_1 = eq(_reg_bp_1_control_chain_T, UInt<1>(0h0))
node _reg_bp_1_control_chain_T_2 = and(newBPC_1.chain, _reg_bp_1_control_chain_T_1)
node _reg_bp_1_control_chain_T_3 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _reg_bp_1_control_chain_T_4 = or(dMode_1, _reg_bp_1_control_chain_T_3)
node _reg_bp_1_control_chain_T_5 = and(_reg_bp_1_control_chain_T_2, _reg_bp_1_control_chain_T_4)
connect reg_bp[1].control.chain, _reg_bp_1_control_chain_T_5
node _T_1731 = eq(reg_pmp[0].cfg.l, UInt<1>(0h0))
node _T_1732 = and(decoded_addr_141_2, _T_1731)
when _T_1732 :
node _newCfg_T = shr(wdata, 0)
wire newCfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}
wire _newCfg_WIRE : UInt<8>
connect _newCfg_WIRE, _newCfg_T
node _newCfg_T_1 = bits(_newCfg_WIRE, 0, 0)
connect newCfg.r, _newCfg_T_1
node _newCfg_T_2 = bits(_newCfg_WIRE, 1, 1)
connect newCfg.w, _newCfg_T_2
node _newCfg_T_3 = bits(_newCfg_WIRE, 2, 2)
connect newCfg.x, _newCfg_T_3
node _newCfg_T_4 = bits(_newCfg_WIRE, 4, 3)
connect newCfg.a, _newCfg_T_4
node _newCfg_T_5 = bits(_newCfg_WIRE, 6, 5)
connect newCfg.res, _newCfg_T_5
node _newCfg_T_6 = bits(_newCfg_WIRE, 7, 7)
connect newCfg.l, _newCfg_T_6
connect reg_pmp[0].cfg, newCfg
node _reg_pmp_0_cfg_w_T = and(newCfg.w, newCfg.r)
connect reg_pmp[0].cfg.w, _reg_pmp_0_cfg_w_T
node _T_1733 = bits(reg_pmp[1].cfg.a, 1, 1)
node _T_1734 = eq(_T_1733, UInt<1>(0h0))
node _T_1735 = bits(reg_pmp[1].cfg.a, 0, 0)
node _T_1736 = and(_T_1734, _T_1735)
node _T_1737 = and(reg_pmp[1].cfg.l, _T_1736)
node _T_1738 = or(reg_pmp[0].cfg.l, _T_1737)
node _T_1739 = eq(_T_1738, UInt<1>(0h0))
node _T_1740 = and(decoded_addr_104_2, _T_1739)
when _T_1740 :
connect reg_pmp[0].addr, wdata
node _T_1741 = eq(reg_pmp[1].cfg.l, UInt<1>(0h0))
node _T_1742 = and(decoded_addr_141_2, _T_1741)
when _T_1742 :
node _newCfg_T_7 = shr(wdata, 8)
wire newCfg_1 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}
wire _newCfg_WIRE_1 : UInt<8>
connect _newCfg_WIRE_1, _newCfg_T_7
node _newCfg_T_8 = bits(_newCfg_WIRE_1, 0, 0)
connect newCfg_1.r, _newCfg_T_8
node _newCfg_T_9 = bits(_newCfg_WIRE_1, 1, 1)
connect newCfg_1.w, _newCfg_T_9
node _newCfg_T_10 = bits(_newCfg_WIRE_1, 2, 2)
connect newCfg_1.x, _newCfg_T_10
node _newCfg_T_11 = bits(_newCfg_WIRE_1, 4, 3)
connect newCfg_1.a, _newCfg_T_11
node _newCfg_T_12 = bits(_newCfg_WIRE_1, 6, 5)
connect newCfg_1.res, _newCfg_T_12
node _newCfg_T_13 = bits(_newCfg_WIRE_1, 7, 7)
connect newCfg_1.l, _newCfg_T_13
connect reg_pmp[1].cfg, newCfg_1
node _reg_pmp_1_cfg_w_T = and(newCfg_1.w, newCfg_1.r)
connect reg_pmp[1].cfg.w, _reg_pmp_1_cfg_w_T
node _T_1743 = bits(reg_pmp[2].cfg.a, 1, 1)
node _T_1744 = eq(_T_1743, UInt<1>(0h0))
node _T_1745 = bits(reg_pmp[2].cfg.a, 0, 0)
node _T_1746 = and(_T_1744, _T_1745)
node _T_1747 = and(reg_pmp[2].cfg.l, _T_1746)
node _T_1748 = or(reg_pmp[1].cfg.l, _T_1747)
node _T_1749 = eq(_T_1748, UInt<1>(0h0))
node _T_1750 = and(decoded_addr_8_2, _T_1749)
when _T_1750 :
connect reg_pmp[1].addr, wdata
node _T_1751 = eq(reg_pmp[2].cfg.l, UInt<1>(0h0))
node _T_1752 = and(decoded_addr_141_2, _T_1751)
when _T_1752 :
node _newCfg_T_14 = shr(wdata, 16)
wire newCfg_2 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}
wire _newCfg_WIRE_2 : UInt<8>
connect _newCfg_WIRE_2, _newCfg_T_14
node _newCfg_T_15 = bits(_newCfg_WIRE_2, 0, 0)
connect newCfg_2.r, _newCfg_T_15
node _newCfg_T_16 = bits(_newCfg_WIRE_2, 1, 1)
connect newCfg_2.w, _newCfg_T_16
node _newCfg_T_17 = bits(_newCfg_WIRE_2, 2, 2)
connect newCfg_2.x, _newCfg_T_17
node _newCfg_T_18 = bits(_newCfg_WIRE_2, 4, 3)
connect newCfg_2.a, _newCfg_T_18
node _newCfg_T_19 = bits(_newCfg_WIRE_2, 6, 5)
connect newCfg_2.res, _newCfg_T_19
node _newCfg_T_20 = bits(_newCfg_WIRE_2, 7, 7)
connect newCfg_2.l, _newCfg_T_20
connect reg_pmp[2].cfg, newCfg_2
node _reg_pmp_2_cfg_w_T = and(newCfg_2.w, newCfg_2.r)
connect reg_pmp[2].cfg.w, _reg_pmp_2_cfg_w_T
node _T_1753 = bits(reg_pmp[3].cfg.a, 1, 1)
node _T_1754 = eq(_T_1753, UInt<1>(0h0))
node _T_1755 = bits(reg_pmp[3].cfg.a, 0, 0)
node _T_1756 = and(_T_1754, _T_1755)
node _T_1757 = and(reg_pmp[3].cfg.l, _T_1756)
node _T_1758 = or(reg_pmp[2].cfg.l, _T_1757)
node _T_1759 = eq(_T_1758, UInt<1>(0h0))
node _T_1760 = and(decoded_addr_125_2, _T_1759)
when _T_1760 :
connect reg_pmp[2].addr, wdata
node _T_1761 = eq(reg_pmp[3].cfg.l, UInt<1>(0h0))
node _T_1762 = and(decoded_addr_141_2, _T_1761)
when _T_1762 :
node _newCfg_T_21 = shr(wdata, 24)
wire newCfg_3 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}
wire _newCfg_WIRE_3 : UInt<8>
connect _newCfg_WIRE_3, _newCfg_T_21
node _newCfg_T_22 = bits(_newCfg_WIRE_3, 0, 0)
connect newCfg_3.r, _newCfg_T_22
node _newCfg_T_23 = bits(_newCfg_WIRE_3, 1, 1)
connect newCfg_3.w, _newCfg_T_23
node _newCfg_T_24 = bits(_newCfg_WIRE_3, 2, 2)
connect newCfg_3.x, _newCfg_T_24
node _newCfg_T_25 = bits(_newCfg_WIRE_3, 4, 3)
connect newCfg_3.a, _newCfg_T_25
node _newCfg_T_26 = bits(_newCfg_WIRE_3, 6, 5)
connect newCfg_3.res, _newCfg_T_26
node _newCfg_T_27 = bits(_newCfg_WIRE_3, 7, 7)
connect newCfg_3.l, _newCfg_T_27
connect reg_pmp[3].cfg, newCfg_3
node _reg_pmp_3_cfg_w_T = and(newCfg_3.w, newCfg_3.r)
connect reg_pmp[3].cfg.w, _reg_pmp_3_cfg_w_T
node _T_1763 = bits(reg_pmp[4].cfg.a, 1, 1)
node _T_1764 = eq(_T_1763, UInt<1>(0h0))
node _T_1765 = bits(reg_pmp[4].cfg.a, 0, 0)
node _T_1766 = and(_T_1764, _T_1765)
node _T_1767 = and(reg_pmp[4].cfg.l, _T_1766)
node _T_1768 = or(reg_pmp[3].cfg.l, _T_1767)
node _T_1769 = eq(_T_1768, UInt<1>(0h0))
node _T_1770 = and(decoded_addr_85_2, _T_1769)
when _T_1770 :
connect reg_pmp[3].addr, wdata
node _T_1771 = eq(reg_pmp[4].cfg.l, UInt<1>(0h0))
node _T_1772 = and(decoded_addr_141_2, _T_1771)
when _T_1772 :
node _newCfg_T_28 = shr(wdata, 32)
wire newCfg_4 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}
wire _newCfg_WIRE_4 : UInt<8>
connect _newCfg_WIRE_4, _newCfg_T_28
node _newCfg_T_29 = bits(_newCfg_WIRE_4, 0, 0)
connect newCfg_4.r, _newCfg_T_29
node _newCfg_T_30 = bits(_newCfg_WIRE_4, 1, 1)
connect newCfg_4.w, _newCfg_T_30
node _newCfg_T_31 = bits(_newCfg_WIRE_4, 2, 2)
connect newCfg_4.x, _newCfg_T_31
node _newCfg_T_32 = bits(_newCfg_WIRE_4, 4, 3)
connect newCfg_4.a, _newCfg_T_32
node _newCfg_T_33 = bits(_newCfg_WIRE_4, 6, 5)
connect newCfg_4.res, _newCfg_T_33
node _newCfg_T_34 = bits(_newCfg_WIRE_4, 7, 7)
connect newCfg_4.l, _newCfg_T_34
connect reg_pmp[4].cfg, newCfg_4
node _reg_pmp_4_cfg_w_T = and(newCfg_4.w, newCfg_4.r)
connect reg_pmp[4].cfg.w, _reg_pmp_4_cfg_w_T
node _T_1773 = bits(reg_pmp[5].cfg.a, 1, 1)
node _T_1774 = eq(_T_1773, UInt<1>(0h0))
node _T_1775 = bits(reg_pmp[5].cfg.a, 0, 0)
node _T_1776 = and(_T_1774, _T_1775)
node _T_1777 = and(reg_pmp[5].cfg.l, _T_1776)
node _T_1778 = or(reg_pmp[4].cfg.l, _T_1777)
node _T_1779 = eq(_T_1778, UInt<1>(0h0))
node _T_1780 = and(decoded_addr_54_2, _T_1779)
when _T_1780 :
connect reg_pmp[4].addr, wdata
node _T_1781 = eq(reg_pmp[5].cfg.l, UInt<1>(0h0))
node _T_1782 = and(decoded_addr_141_2, _T_1781)
when _T_1782 :
node _newCfg_T_35 = shr(wdata, 40)
wire newCfg_5 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}
wire _newCfg_WIRE_5 : UInt<8>
connect _newCfg_WIRE_5, _newCfg_T_35
node _newCfg_T_36 = bits(_newCfg_WIRE_5, 0, 0)
connect newCfg_5.r, _newCfg_T_36
node _newCfg_T_37 = bits(_newCfg_WIRE_5, 1, 1)
connect newCfg_5.w, _newCfg_T_37
node _newCfg_T_38 = bits(_newCfg_WIRE_5, 2, 2)
connect newCfg_5.x, _newCfg_T_38
node _newCfg_T_39 = bits(_newCfg_WIRE_5, 4, 3)
connect newCfg_5.a, _newCfg_T_39
node _newCfg_T_40 = bits(_newCfg_WIRE_5, 6, 5)
connect newCfg_5.res, _newCfg_T_40
node _newCfg_T_41 = bits(_newCfg_WIRE_5, 7, 7)
connect newCfg_5.l, _newCfg_T_41
connect reg_pmp[5].cfg, newCfg_5
node _reg_pmp_5_cfg_w_T = and(newCfg_5.w, newCfg_5.r)
connect reg_pmp[5].cfg.w, _reg_pmp_5_cfg_w_T
node _T_1783 = bits(reg_pmp[6].cfg.a, 1, 1)
node _T_1784 = eq(_T_1783, UInt<1>(0h0))
node _T_1785 = bits(reg_pmp[6].cfg.a, 0, 0)
node _T_1786 = and(_T_1784, _T_1785)
node _T_1787 = and(reg_pmp[6].cfg.l, _T_1786)
node _T_1788 = or(reg_pmp[5].cfg.l, _T_1787)
node _T_1789 = eq(_T_1788, UInt<1>(0h0))
node _T_1790 = and(decoded_addr_20_2, _T_1789)
when _T_1790 :
connect reg_pmp[5].addr, wdata
node _T_1791 = eq(reg_pmp[6].cfg.l, UInt<1>(0h0))
node _T_1792 = and(decoded_addr_141_2, _T_1791)
when _T_1792 :
node _newCfg_T_42 = shr(wdata, 48)
wire newCfg_6 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}
wire _newCfg_WIRE_6 : UInt<8>
connect _newCfg_WIRE_6, _newCfg_T_42
node _newCfg_T_43 = bits(_newCfg_WIRE_6, 0, 0)
connect newCfg_6.r, _newCfg_T_43
node _newCfg_T_44 = bits(_newCfg_WIRE_6, 1, 1)
connect newCfg_6.w, _newCfg_T_44
node _newCfg_T_45 = bits(_newCfg_WIRE_6, 2, 2)
connect newCfg_6.x, _newCfg_T_45
node _newCfg_T_46 = bits(_newCfg_WIRE_6, 4, 3)
connect newCfg_6.a, _newCfg_T_46
node _newCfg_T_47 = bits(_newCfg_WIRE_6, 6, 5)
connect newCfg_6.res, _newCfg_T_47
node _newCfg_T_48 = bits(_newCfg_WIRE_6, 7, 7)
connect newCfg_6.l, _newCfg_T_48
connect reg_pmp[6].cfg, newCfg_6
node _reg_pmp_6_cfg_w_T = and(newCfg_6.w, newCfg_6.r)
connect reg_pmp[6].cfg.w, _reg_pmp_6_cfg_w_T
node _T_1793 = bits(reg_pmp[7].cfg.a, 1, 1)
node _T_1794 = eq(_T_1793, UInt<1>(0h0))
node _T_1795 = bits(reg_pmp[7].cfg.a, 0, 0)
node _T_1796 = and(_T_1794, _T_1795)
node _T_1797 = and(reg_pmp[7].cfg.l, _T_1796)
node _T_1798 = or(reg_pmp[6].cfg.l, _T_1797)
node _T_1799 = eq(_T_1798, UInt<1>(0h0))
node _T_1800 = and(decoded_addr_135_2, _T_1799)
when _T_1800 :
connect reg_pmp[6].addr, wdata
node _T_1801 = eq(reg_pmp[7].cfg.l, UInt<1>(0h0))
node _T_1802 = and(decoded_addr_141_2, _T_1801)
when _T_1802 :
node _newCfg_T_49 = shr(wdata, 56)
wire newCfg_7 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}
wire _newCfg_WIRE_7 : UInt<8>
connect _newCfg_WIRE_7, _newCfg_T_49
node _newCfg_T_50 = bits(_newCfg_WIRE_7, 0, 0)
connect newCfg_7.r, _newCfg_T_50
node _newCfg_T_51 = bits(_newCfg_WIRE_7, 1, 1)
connect newCfg_7.w, _newCfg_T_51
node _newCfg_T_52 = bits(_newCfg_WIRE_7, 2, 2)
connect newCfg_7.x, _newCfg_T_52
node _newCfg_T_53 = bits(_newCfg_WIRE_7, 4, 3)
connect newCfg_7.a, _newCfg_T_53
node _newCfg_T_54 = bits(_newCfg_WIRE_7, 6, 5)
connect newCfg_7.res, _newCfg_T_54
node _newCfg_T_55 = bits(_newCfg_WIRE_7, 7, 7)
connect newCfg_7.l, _newCfg_T_55
connect reg_pmp[7].cfg, newCfg_7
node _reg_pmp_7_cfg_w_T = and(newCfg_7.w, newCfg_7.r)
connect reg_pmp[7].cfg.w, _reg_pmp_7_cfg_w_T
node _T_1803 = bits(reg_pmp[7].cfg.a, 1, 1)
node _T_1804 = eq(_T_1803, UInt<1>(0h0))
node _T_1805 = bits(reg_pmp[7].cfg.a, 0, 0)
node _T_1806 = and(_T_1804, _T_1805)
node _T_1807 = and(reg_pmp[7].cfg.l, _T_1806)
node _T_1808 = or(reg_pmp[7].cfg.l, _T_1807)
node _T_1809 = eq(_T_1808, UInt<1>(0h0))
node _T_1810 = and(decoded_addr_115_2, _T_1809)
when _T_1810 :
connect reg_pmp[7].addr, wdata
when decoded_addr_18_2 :
node _reg_custom_0_T = and(wdata, UInt<64>(0h208))
node _reg_custom_0_T_1 = not(UInt<64>(0h208))
node _reg_custom_0_T_2 = and(reg_custom_0, _reg_custom_0_T_1)
node _reg_custom_0_T_3 = or(_reg_custom_0_T, _reg_custom_0_T_2)
connect reg_custom_0, _reg_custom_0_T_3
connect io.customCSRs[0].wen, UInt<1>(0h1)
when decoded_addr_3_2 :
node _reg_custom_1_T = and(wdata, UInt<64>(0h0))
node _reg_custom_1_T_1 = not(UInt<64>(0h0))
node _reg_custom_1_T_2 = and(reg_custom_1, _reg_custom_1_T_1)
node _reg_custom_1_T_3 = or(_reg_custom_1_T, _reg_custom_1_T_2)
connect reg_custom_1, _reg_custom_1_T_3
connect io.customCSRs[1].wen, UInt<1>(0h1)
when decoded_addr_38_2 :
node _reg_custom_2_T = and(wdata, UInt<64>(0h0))
node _reg_custom_2_T_1 = not(UInt<64>(0h0))
node _reg_custom_2_T_2 = and(reg_custom_2, _reg_custom_2_T_1)
node _reg_custom_2_T_3 = or(_reg_custom_2_T, _reg_custom_2_T_2)
connect reg_custom_2, _reg_custom_2_T_3
connect io.customCSRs[2].wen, UInt<1>(0h1)
when decoded_addr_127_2 :
node _reg_custom_3_T = and(wdata, UInt<64>(0h0))
node _reg_custom_3_T_1 = not(UInt<64>(0h0))
node _reg_custom_3_T_2 = and(reg_custom_3, _reg_custom_3_T_1)
node _reg_custom_3_T_3 = or(_reg_custom_3_T, _reg_custom_3_T_2)
connect reg_custom_3, _reg_custom_3_T_3
connect io.customCSRs[3].wen, UInt<1>(0h1)
when io.customCSRs[0].set :
node _reg_custom_0_T_4 = and(io.customCSRs[0].sdata, UInt<64>(0h208))
node _reg_custom_0_T_5 = not(UInt<64>(0h208))
node _reg_custom_0_T_6 = and(reg_custom_0, _reg_custom_0_T_5)
node _reg_custom_0_T_7 = or(_reg_custom_0_T_4, _reg_custom_0_T_6)
connect reg_custom_0, _reg_custom_0_T_7
when io.customCSRs[1].set :
node _reg_custom_1_T_4 = and(io.customCSRs[1].sdata, UInt<64>(0h0))
node _reg_custom_1_T_5 = not(UInt<64>(0h0))
node _reg_custom_1_T_6 = and(reg_custom_1, _reg_custom_1_T_5)
node _reg_custom_1_T_7 = or(_reg_custom_1_T_4, _reg_custom_1_T_6)
connect reg_custom_1, _reg_custom_1_T_7
when io.customCSRs[2].set :
node _reg_custom_2_T_4 = and(io.customCSRs[2].sdata, UInt<64>(0h0))
node _reg_custom_2_T_5 = not(UInt<64>(0h0))
node _reg_custom_2_T_6 = and(reg_custom_2, _reg_custom_2_T_5)
node _reg_custom_2_T_7 = or(_reg_custom_2_T_4, _reg_custom_2_T_6)
connect reg_custom_2, _reg_custom_2_T_7
when io.customCSRs[3].set :
node _reg_custom_3_T_4 = and(io.customCSRs[3].sdata, UInt<64>(0h0))
node _reg_custom_3_T_5 = not(UInt<64>(0h0))
node _reg_custom_3_T_6 = and(reg_custom_3, _reg_custom_3_T_5)
node _reg_custom_3_T_7 = or(_reg_custom_3_T_4, _reg_custom_3_T_6)
connect reg_custom_3, _reg_custom_3_T_7
node _T_1811 = asUInt(reset)
when _T_1811 :
connect reg_satp.mode, UInt<1>(0h0)
connect reg_vsatp.mode, UInt<1>(0h0)
connect reg_hgatp.mode, UInt<1>(0h0)
connect reg_vsatp.mode, UInt<1>(0h0)
connect reg_vsatp.ppn, UInt<1>(0h0)
connect reg_vsatp.asid, UInt<1>(0h0)
connect reg_hgatp.mode, UInt<1>(0h0)
connect reg_hgatp.ppn, UInt<1>(0h0)
connect reg_hgatp.asid, UInt<1>(0h0)
connect reg_satp.asid, UInt<1>(0h0)
connect reg_vsatp.asid, UInt<1>(0h0)
connect reg_hgatp.asid, UInt<1>(0h0)
connect reg_vsstatus.xs, UInt<2>(0h3)
connect reg_tselect, UInt<1>(0h0)
connect reg_bp[0].control.ttype, UInt<2>(0h2)
connect reg_bp[0].control.maskmax, UInt<3>(0h4)
connect reg_bp[0].control.reserved, UInt<1>(0h0)
connect reg_bp[0].control.zero, UInt<1>(0h0)
connect reg_bp[0].control.h, UInt<1>(0h0)
node _T_1812 = asUInt(reset)
when _T_1812 :
connect reg_bp[0].control.action, UInt<1>(0h0)
connect reg_bp[0].control.dmode, UInt<1>(0h0)
connect reg_bp[0].control.chain, UInt<1>(0h0)
connect reg_bp[0].control.r, UInt<1>(0h0)
connect reg_bp[0].control.w, UInt<1>(0h0)
connect reg_bp[0].control.x, UInt<1>(0h0)
connect reg_bp[1].control.ttype, UInt<2>(0h2)
connect reg_bp[1].control.maskmax, UInt<3>(0h4)
connect reg_bp[1].control.reserved, UInt<1>(0h0)
connect reg_bp[1].control.zero, UInt<1>(0h0)
connect reg_bp[1].control.h, UInt<1>(0h0)
node _T_1813 = asUInt(reset)
when _T_1813 :
connect reg_bp[1].control.action, UInt<1>(0h0)
connect reg_bp[1].control.dmode, UInt<1>(0h0)
connect reg_bp[1].control.chain, UInt<1>(0h0)
connect reg_bp[1].control.r, UInt<1>(0h0)
connect reg_bp[1].control.w, UInt<1>(0h0)
connect reg_bp[1].control.x, UInt<1>(0h0)
connect reg_bp[0].textra.mselect, UInt<1>(0h0)
connect reg_bp[0].textra.sselect, UInt<1>(0h0)
connect reg_bp[1].textra.mselect, UInt<1>(0h0)
connect reg_bp[1].textra.sselect, UInt<1>(0h0)
wire _reg_bp_1_WIRE : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}
connect _reg_bp_1_WIRE.textra.sselect, UInt<1>(0h0)
connect _reg_bp_1_WIRE.textra.pad1, UInt<1>(0h0)
invalidate _reg_bp_1_WIRE.textra.svalue
connect _reg_bp_1_WIRE.textra.pad2, UInt<48>(0h0)
connect _reg_bp_1_WIRE.textra.mselect, UInt<1>(0h0)
invalidate _reg_bp_1_WIRE.textra.mvalue
connect _reg_bp_1_WIRE.address, UInt<39>(0h0)
connect _reg_bp_1_WIRE.control.r, UInt<1>(0h0)
connect _reg_bp_1_WIRE.control.w, UInt<1>(0h0)
connect _reg_bp_1_WIRE.control.x, UInt<1>(0h0)
connect _reg_bp_1_WIRE.control.u, UInt<1>(0h0)
connect _reg_bp_1_WIRE.control.s, UInt<1>(0h0)
connect _reg_bp_1_WIRE.control.h, UInt<1>(0h0)
connect _reg_bp_1_WIRE.control.m, UInt<1>(0h0)
connect _reg_bp_1_WIRE.control.tmatch, UInt<2>(0h0)
connect _reg_bp_1_WIRE.control.zero, UInt<2>(0h0)
connect _reg_bp_1_WIRE.control.chain, UInt<1>(0h0)
connect _reg_bp_1_WIRE.control.action, UInt<1>(0h0)
connect _reg_bp_1_WIRE.control.reserved, UInt<40>(0h0)
connect _reg_bp_1_WIRE.control.maskmax, UInt<6>(0h0)
connect _reg_bp_1_WIRE.control.dmode, UInt<1>(0h0)
connect _reg_bp_1_WIRE.control.ttype, UInt<4>(0h0)
connect reg_bp[1], _reg_bp_1_WIRE
connect reg_pmp[0].cfg.res, UInt<1>(0h0)
node _T_1814 = asUInt(reset)
when _T_1814 :
connect reg_pmp[0].cfg.a, UInt<1>(0h0)
connect reg_pmp[0].cfg.l, UInt<1>(0h0)
connect reg_pmp[1].cfg.res, UInt<1>(0h0)
node _T_1815 = asUInt(reset)
when _T_1815 :
connect reg_pmp[1].cfg.a, UInt<1>(0h0)
connect reg_pmp[1].cfg.l, UInt<1>(0h0)
connect reg_pmp[2].cfg.res, UInt<1>(0h0)
node _T_1816 = asUInt(reset)
when _T_1816 :
connect reg_pmp[2].cfg.a, UInt<1>(0h0)
connect reg_pmp[2].cfg.l, UInt<1>(0h0)
connect reg_pmp[3].cfg.res, UInt<1>(0h0)
node _T_1817 = asUInt(reset)
when _T_1817 :
connect reg_pmp[3].cfg.a, UInt<1>(0h0)
connect reg_pmp[3].cfg.l, UInt<1>(0h0)
connect reg_pmp[4].cfg.res, UInt<1>(0h0)
node _T_1818 = asUInt(reset)
when _T_1818 :
connect reg_pmp[4].cfg.a, UInt<1>(0h0)
connect reg_pmp[4].cfg.l, UInt<1>(0h0)
connect reg_pmp[5].cfg.res, UInt<1>(0h0)
node _T_1819 = asUInt(reset)
when _T_1819 :
connect reg_pmp[5].cfg.a, UInt<1>(0h0)
connect reg_pmp[5].cfg.l, UInt<1>(0h0)
connect reg_pmp[6].cfg.res, UInt<1>(0h0)
node _T_1820 = asUInt(reset)
when _T_1820 :
connect reg_pmp[6].cfg.a, UInt<1>(0h0)
connect reg_pmp[6].cfg.l, UInt<1>(0h0)
connect reg_pmp[7].cfg.res, UInt<1>(0h0)
node _T_1821 = asUInt(reset)
when _T_1821 :
connect reg_pmp[7].cfg.a, UInt<1>(0h0)
connect reg_pmp[7].cfg.l, UInt<1>(0h0)
node _io_trace_0_exception_T = geq(io.retire, UInt<1>(0h0))
node _io_trace_0_exception_T_1 = and(_io_trace_0_exception_T, exception)
connect io.trace[0].exception, _io_trace_0_exception_T_1
node _io_trace_0_valid_T = gt(io.retire, UInt<1>(0h0))
node _io_trace_0_valid_T_1 = or(_io_trace_0_valid_T, io.trace[0].exception)
connect io.trace[0].valid, _io_trace_0_valid_T_1
connect io.trace[0].insn, io.inst[0]
connect io.trace[0].iaddr, io.pc
node _io_trace_0_priv_T = cat(reg_debug, reg_mstatus.prv)
connect io.trace[0].priv, _io_trace_0_priv_T
connect io.trace[0].cause, cause
node _io_trace_0_interrupt_T = bits(cause, 63, 63)
connect io.trace[0].interrupt, _io_trace_0_interrupt_T
connect io.trace[0].tval, io.tval | module CSRFile( // @[CSR.scala:377:7]
input clock, // @[CSR.scala:377:7]
input reset, // @[CSR.scala:377:7]
input io_ungated_clock, // @[CSR.scala:384:14]
input io_interrupts_debug, // @[CSR.scala:384:14]
input io_interrupts_mtip, // @[CSR.scala:384:14]
input io_interrupts_msip, // @[CSR.scala:384:14]
input io_interrupts_meip, // @[CSR.scala:384:14]
input io_interrupts_seip, // @[CSR.scala:384:14]
input io_hartid, // @[CSR.scala:384:14]
input [11:0] io_rw_addr, // @[CSR.scala:384:14]
input [2:0] io_rw_cmd, // @[CSR.scala:384:14]
output [63:0] io_rw_rdata, // @[CSR.scala:384:14]
input [63:0] io_rw_wdata, // @[CSR.scala:384:14]
input [31:0] io_decode_0_inst, // @[CSR.scala:384:14]
output io_decode_0_fp_illegal, // @[CSR.scala:384:14]
output io_decode_0_fp_csr, // @[CSR.scala:384:14]
output io_decode_0_rocc_illegal, // @[CSR.scala:384:14]
output io_decode_0_read_illegal, // @[CSR.scala:384:14]
output io_decode_0_write_illegal, // @[CSR.scala:384:14]
output io_decode_0_write_flush, // @[CSR.scala:384:14]
output io_decode_0_system_illegal, // @[CSR.scala:384:14]
output io_decode_0_virtual_access_illegal, // @[CSR.scala:384:14]
output io_decode_0_virtual_system_illegal, // @[CSR.scala:384:14]
output io_csr_stall, // @[CSR.scala:384:14]
output io_eret, // @[CSR.scala:384:14]
output io_singleStep, // @[CSR.scala:384:14]
output io_status_debug, // @[CSR.scala:384:14]
output io_status_cease, // @[CSR.scala:384:14]
output io_status_wfi, // @[CSR.scala:384:14]
output [31:0] io_status_isa, // @[CSR.scala:384:14]
output [1:0] io_status_dprv, // @[CSR.scala:384:14]
output io_status_dv, // @[CSR.scala:384:14]
output [1:0] io_status_prv, // @[CSR.scala:384:14]
output io_status_v, // @[CSR.scala:384:14]
output io_status_mpv, // @[CSR.scala:384:14]
output io_status_gva, // @[CSR.scala:384:14]
output io_status_tsr, // @[CSR.scala:384:14]
output io_status_tw, // @[CSR.scala:384:14]
output io_status_tvm, // @[CSR.scala:384:14]
output io_status_mxr, // @[CSR.scala:384:14]
output io_status_sum, // @[CSR.scala:384:14]
output io_status_mprv, // @[CSR.scala:384:14]
output [1:0] io_status_fs, // @[CSR.scala:384:14]
output [1:0] io_status_mpp, // @[CSR.scala:384:14]
output io_status_spp, // @[CSR.scala:384:14]
output io_status_mpie, // @[CSR.scala:384:14]
output io_status_spie, // @[CSR.scala:384:14]
output io_status_mie, // @[CSR.scala:384:14]
output io_status_sie, // @[CSR.scala:384:14]
output io_hstatus_spvp, // @[CSR.scala:384:14]
output io_hstatus_spv, // @[CSR.scala:384:14]
output io_hstatus_gva, // @[CSR.scala:384:14]
output io_gstatus_debug, // @[CSR.scala:384:14]
output io_gstatus_cease, // @[CSR.scala:384:14]
output io_gstatus_wfi, // @[CSR.scala:384:14]
output [31:0] io_gstatus_isa, // @[CSR.scala:384:14]
output [1:0] io_gstatus_dprv, // @[CSR.scala:384:14]
output io_gstatus_dv, // @[CSR.scala:384:14]
output [1:0] io_gstatus_prv, // @[CSR.scala:384:14]
output io_gstatus_v, // @[CSR.scala:384:14]
output [22:0] io_gstatus_zero2, // @[CSR.scala:384:14]
output io_gstatus_mpv, // @[CSR.scala:384:14]
output io_gstatus_gva, // @[CSR.scala:384:14]
output io_gstatus_mbe, // @[CSR.scala:384:14]
output io_gstatus_sbe, // @[CSR.scala:384:14]
output [1:0] io_gstatus_sxl, // @[CSR.scala:384:14]
output [7:0] io_gstatus_zero1, // @[CSR.scala:384:14]
output io_gstatus_tsr, // @[CSR.scala:384:14]
output io_gstatus_tw, // @[CSR.scala:384:14]
output io_gstatus_tvm, // @[CSR.scala:384:14]
output io_gstatus_mxr, // @[CSR.scala:384:14]
output io_gstatus_sum, // @[CSR.scala:384:14]
output io_gstatus_mprv, // @[CSR.scala:384:14]
output [1:0] io_gstatus_fs, // @[CSR.scala:384:14]
output [1:0] io_gstatus_mpp, // @[CSR.scala:384:14]
output [1:0] io_gstatus_vs, // @[CSR.scala:384:14]
output io_gstatus_spp, // @[CSR.scala:384:14]
output io_gstatus_mpie, // @[CSR.scala:384:14]
output io_gstatus_ube, // @[CSR.scala:384:14]
output io_gstatus_spie, // @[CSR.scala:384:14]
output io_gstatus_upie, // @[CSR.scala:384:14]
output io_gstatus_mie, // @[CSR.scala:384:14]
output io_gstatus_hie, // @[CSR.scala:384:14]
output io_gstatus_sie, // @[CSR.scala:384:14]
output io_gstatus_uie, // @[CSR.scala:384:14]
output [3:0] io_ptbr_mode, // @[CSR.scala:384:14]
output [43:0] io_ptbr_ppn, // @[CSR.scala:384:14]
output [39:0] io_evec, // @[CSR.scala:384:14]
input io_exception, // @[CSR.scala:384:14]
input io_retire, // @[CSR.scala:384:14]
input [63:0] io_cause, // @[CSR.scala:384:14]
input [39:0] io_pc, // @[CSR.scala:384:14]
input [39:0] io_tval, // @[CSR.scala:384:14]
input [39:0] io_htval, // @[CSR.scala:384:14]
input io_mhtinst_read_pseudo, // @[CSR.scala:384:14]
input io_gva, // @[CSR.scala:384:14]
output [63:0] io_time, // @[CSR.scala:384:14]
output [2:0] io_fcsr_rm, // @[CSR.scala:384:14]
input io_fcsr_flags_valid, // @[CSR.scala:384:14]
input [4:0] io_fcsr_flags_bits, // @[CSR.scala:384:14]
input io_rocc_interrupt, // @[CSR.scala:384:14]
output io_interrupt, // @[CSR.scala:384:14]
output [63:0] io_interrupt_cause, // @[CSR.scala:384:14]
output io_bp_0_control_dmode, // @[CSR.scala:384:14]
output io_bp_0_control_action, // @[CSR.scala:384:14]
output [1:0] io_bp_0_control_tmatch, // @[CSR.scala:384:14]
output io_bp_0_control_m, // @[CSR.scala:384:14]
output io_bp_0_control_s, // @[CSR.scala:384:14]
output io_bp_0_control_u, // @[CSR.scala:384:14]
output io_bp_0_control_x, // @[CSR.scala:384:14]
output io_bp_0_control_w, // @[CSR.scala:384:14]
output io_bp_0_control_r, // @[CSR.scala:384:14]
output [38:0] io_bp_0_address, // @[CSR.scala:384:14]
output [47:0] io_bp_0_textra_pad2, // @[CSR.scala:384:14]
output io_bp_0_textra_pad1, // @[CSR.scala:384:14]
output io_pmp_0_cfg_l, // @[CSR.scala:384:14]
output [1:0] io_pmp_0_cfg_a, // @[CSR.scala:384:14]
output io_pmp_0_cfg_x, // @[CSR.scala:384:14]
output io_pmp_0_cfg_w, // @[CSR.scala:384:14]
output io_pmp_0_cfg_r, // @[CSR.scala:384:14]
output [29:0] io_pmp_0_addr, // @[CSR.scala:384:14]
output [31:0] io_pmp_0_mask, // @[CSR.scala:384:14]
output io_pmp_1_cfg_l, // @[CSR.scala:384:14]
output [1:0] io_pmp_1_cfg_a, // @[CSR.scala:384:14]
output io_pmp_1_cfg_x, // @[CSR.scala:384:14]
output io_pmp_1_cfg_w, // @[CSR.scala:384:14]
output io_pmp_1_cfg_r, // @[CSR.scala:384:14]
output [29:0] io_pmp_1_addr, // @[CSR.scala:384:14]
output [31:0] io_pmp_1_mask, // @[CSR.scala:384:14]
output io_pmp_2_cfg_l, // @[CSR.scala:384:14]
output [1:0] io_pmp_2_cfg_a, // @[CSR.scala:384:14]
output io_pmp_2_cfg_x, // @[CSR.scala:384:14]
output io_pmp_2_cfg_w, // @[CSR.scala:384:14]
output io_pmp_2_cfg_r, // @[CSR.scala:384:14]
output [29:0] io_pmp_2_addr, // @[CSR.scala:384:14]
output [31:0] io_pmp_2_mask, // @[CSR.scala:384:14]
output io_pmp_3_cfg_l, // @[CSR.scala:384:14]
output [1:0] io_pmp_3_cfg_a, // @[CSR.scala:384:14]
output io_pmp_3_cfg_x, // @[CSR.scala:384:14]
output io_pmp_3_cfg_w, // @[CSR.scala:384:14]
output io_pmp_3_cfg_r, // @[CSR.scala:384:14]
output [29:0] io_pmp_3_addr, // @[CSR.scala:384:14]
output [31:0] io_pmp_3_mask, // @[CSR.scala:384:14]
output io_pmp_4_cfg_l, // @[CSR.scala:384:14]
output [1:0] io_pmp_4_cfg_a, // @[CSR.scala:384:14]
output io_pmp_4_cfg_x, // @[CSR.scala:384:14]
output io_pmp_4_cfg_w, // @[CSR.scala:384:14]
output io_pmp_4_cfg_r, // @[CSR.scala:384:14]
output [29:0] io_pmp_4_addr, // @[CSR.scala:384:14]
output [31:0] io_pmp_4_mask, // @[CSR.scala:384:14]
output io_pmp_5_cfg_l, // @[CSR.scala:384:14]
output [1:0] io_pmp_5_cfg_a, // @[CSR.scala:384:14]
output io_pmp_5_cfg_x, // @[CSR.scala:384:14]
output io_pmp_5_cfg_w, // @[CSR.scala:384:14]
output io_pmp_5_cfg_r, // @[CSR.scala:384:14]
output [29:0] io_pmp_5_addr, // @[CSR.scala:384:14]
output [31:0] io_pmp_5_mask, // @[CSR.scala:384:14]
output io_pmp_6_cfg_l, // @[CSR.scala:384:14]
output [1:0] io_pmp_6_cfg_a, // @[CSR.scala:384:14]
output io_pmp_6_cfg_x, // @[CSR.scala:384:14]
output io_pmp_6_cfg_w, // @[CSR.scala:384:14]
output io_pmp_6_cfg_r, // @[CSR.scala:384:14]
output [29:0] io_pmp_6_addr, // @[CSR.scala:384:14]
output [31:0] io_pmp_6_mask, // @[CSR.scala:384:14]
output io_pmp_7_cfg_l, // @[CSR.scala:384:14]
output [1:0] io_pmp_7_cfg_a, // @[CSR.scala:384:14]
output io_pmp_7_cfg_x, // @[CSR.scala:384:14]
output io_pmp_7_cfg_w, // @[CSR.scala:384:14]
output io_pmp_7_cfg_r, // @[CSR.scala:384:14]
output [29:0] io_pmp_7_addr, // @[CSR.scala:384:14]
output [31:0] io_pmp_7_mask, // @[CSR.scala:384:14]
output io_inhibit_cycle, // @[CSR.scala:384:14]
input [31:0] io_inst_0, // @[CSR.scala:384:14]
output io_trace_0_valid, // @[CSR.scala:384:14]
output [39:0] io_trace_0_iaddr, // @[CSR.scala:384:14]
output [31:0] io_trace_0_insn, // @[CSR.scala:384:14]
output [2:0] io_trace_0_priv, // @[CSR.scala:384:14]
output io_trace_0_exception, // @[CSR.scala:384:14]
output io_trace_0_interrupt, // @[CSR.scala:384:14]
output [63:0] io_trace_0_cause, // @[CSR.scala:384:14]
output [39:0] io_trace_0_tval, // @[CSR.scala:384:14]
output io_customCSRs_0_ren, // @[CSR.scala:384:14]
output io_customCSRs_0_wen, // @[CSR.scala:384:14]
output [63:0] io_customCSRs_0_wdata, // @[CSR.scala:384:14]
output [63:0] io_customCSRs_0_value, // @[CSR.scala:384:14]
output io_customCSRs_1_ren, // @[CSR.scala:384:14]
output io_customCSRs_1_wen, // @[CSR.scala:384:14]
output [63:0] io_customCSRs_1_wdata, // @[CSR.scala:384:14]
output [63:0] io_customCSRs_1_value, // @[CSR.scala:384:14]
output io_customCSRs_2_ren, // @[CSR.scala:384:14]
output io_customCSRs_2_wen, // @[CSR.scala:384:14]
output [63:0] io_customCSRs_2_wdata, // @[CSR.scala:384:14]
output [63:0] io_customCSRs_2_value, // @[CSR.scala:384:14]
output io_customCSRs_3_ren, // @[CSR.scala:384:14]
output io_customCSRs_3_wen, // @[CSR.scala:384:14]
output [63:0] io_customCSRs_3_wdata, // @[CSR.scala:384:14]
output [63:0] io_customCSRs_3_value // @[CSR.scala:384:14]
);
wire io_status_sie_0; // @[CSR.scala:377:7]
wire io_status_spie_0; // @[CSR.scala:377:7]
wire io_status_spp_0; // @[CSR.scala:377:7]
wire [1:0] io_status_fs_0; // @[CSR.scala:377:7]
wire io_status_sum_0; // @[CSR.scala:377:7]
wire io_status_mxr_0; // @[CSR.scala:377:7]
wire io_ungated_clock_0 = io_ungated_clock; // @[CSR.scala:377:7]
wire io_interrupts_debug_0 = io_interrupts_debug; // @[CSR.scala:377:7]
wire io_interrupts_mtip_0 = io_interrupts_mtip; // @[CSR.scala:377:7]
wire io_interrupts_msip_0 = io_interrupts_msip; // @[CSR.scala:377:7]
wire io_interrupts_meip_0 = io_interrupts_meip; // @[CSR.scala:377:7]
wire io_interrupts_seip_0 = io_interrupts_seip; // @[CSR.scala:377:7]
wire io_hartid_0 = io_hartid; // @[CSR.scala:377:7]
wire [11:0] io_rw_addr_0 = io_rw_addr; // @[CSR.scala:377:7]
wire [2:0] io_rw_cmd_0 = io_rw_cmd; // @[CSR.scala:377:7]
wire [63:0] io_rw_wdata_0 = io_rw_wdata; // @[CSR.scala:377:7]
wire [31:0] io_decode_0_inst_0 = io_decode_0_inst; // @[CSR.scala:377:7]
wire io_exception_0 = io_exception; // @[CSR.scala:377:7]
wire io_retire_0 = io_retire; // @[CSR.scala:377:7]
wire [63:0] io_cause_0 = io_cause; // @[CSR.scala:377:7]
wire [39:0] io_pc_0 = io_pc; // @[CSR.scala:377:7]
wire [39:0] io_tval_0 = io_tval; // @[CSR.scala:377:7]
wire [39:0] io_htval_0 = io_htval; // @[CSR.scala:377:7]
wire io_mhtinst_read_pseudo_0 = io_mhtinst_read_pseudo; // @[CSR.scala:377:7]
wire io_gva_0 = io_gva; // @[CSR.scala:377:7]
wire io_fcsr_flags_valid_0 = io_fcsr_flags_valid; // @[CSR.scala:377:7]
wire [4:0] io_fcsr_flags_bits_0 = io_fcsr_flags_bits; // @[CSR.scala:377:7]
wire io_rocc_interrupt_0 = io_rocc_interrupt; // @[CSR.scala:377:7]
wire [31:0] io_inst_0_0 = io_inst_0; // @[CSR.scala:377:7]
wire io_decode_0_vector_illegal = 1'h1; // @[CSR.scala:377:7]
wire io_status_sd = 1'h1; // @[CSR.scala:377:7]
wire io_gstatus_sd = 1'h1; // @[CSR.scala:377:7]
wire sup_rocc = 1'h1; // @[CSR.scala:406:19]
wire sup_meip = 1'h1; // @[CSR.scala:406:19]
wire sup_seip = 1'h1; // @[CSR.scala:406:19]
wire sup_mtip = 1'h1; // @[CSR.scala:406:19]
wire sup_stip = 1'h1; // @[CSR.scala:406:19]
wire sup_msip = 1'h1; // @[CSR.scala:406:19]
wire sup_ssip = 1'h1; // @[CSR.scala:406:19]
wire del_rocc = 1'h1; // @[CSR.scala:426:26]
wire del_seip = 1'h1; // @[CSR.scala:426:26]
wire del_stip = 1'h1; // @[CSR.scala:426:26]
wire del_ssip = 1'h1; // @[CSR.scala:426:26]
wire read_mnstatus_mie = 1'h1; // @[CSR.scala:675:31]
wire sie_mask_sgeip_mask_sgeip = 1'h1; // @[CSR.scala:748:30]
wire read_sstatus_sd = 1'h1; // @[CSR.scala:755:35]
wire _allow_wfi_T_4 = 1'h1; // @[CSR.scala:906:112]
wire _allow_wfi_T_5 = 1'h1; // @[CSR.scala:906:109]
wire allow_hfence_vvma = 1'h1; // @[CSR.scala:908:50]
wire allow_hlsv = 1'h1; // @[CSR.scala:909:43]
wire _allow_counter_T_11 = 1'h1; // @[CSR.scala:914:8]
wire _allow_counter_T_13 = 1'h1; // @[CSR.scala:914:27]
wire _allow_counter_T_16 = 1'h1; // @[CSR.scala:914:45]
wire _io_decode_0_fp_illegal_T_1 = 1'h1; // @[CSR.scala:915:83]
wire _io_decode_0_vector_illegal_T = 1'h1; // @[CSR.scala:916:43]
wire _io_decode_0_vector_illegal_T_1 = 1'h1; // @[CSR.scala:916:87]
wire _io_decode_0_vector_illegal_T_3 = 1'h1; // @[CSR.scala:916:51]
wire _io_decode_0_vector_illegal_T_6 = 1'h1; // @[CSR.scala:916:95]
wire _io_status_sd_T_1 = 1'h1; // @[CSR.scala:1003:53]
wire _io_status_sd_T_2 = 1'h1; // @[CSR.scala:1003:37]
wire _io_status_sd_T_4 = 1'h1; // @[CSR.scala:1003:58]
wire _io_gstatus_sd_T_1 = 1'h1; // @[CSR.scala:1016:56]
wire _io_gstatus_sd_T_2 = 1'h1; // @[CSR.scala:1016:39]
wire _io_gstatus_sd_T_4 = 1'h1; // @[CSR.scala:1016:61]
wire _en_T_7 = 1'h1; // @[CSR.scala:1096:71]
wire delegable_1 = 1'h1; // @[CSR.scala:1097:65]
wire _en_T_19 = 1'h1; // @[CSR.scala:1096:71]
wire _en_T_31 = 1'h1; // @[CSR.scala:1096:71]
wire delegable_5 = 1'h1; // @[CSR.scala:1097:65]
wire _en_T_43 = 1'h1; // @[CSR.scala:1096:71]
wire _en_T_55 = 1'h1; // @[CSR.scala:1096:71]
wire delegable_9 = 1'h1; // @[CSR.scala:1097:65]
wire _en_T_67 = 1'h1; // @[CSR.scala:1096:71]
wire _en_T_79 = 1'h1; // @[CSR.scala:1096:71]
wire delegable_13 = 1'h1; // @[CSR.scala:1097:65]
wire delegable_16 = 1'h1; // @[CSR.scala:1109:67]
wire delegable_18 = 1'h1; // @[CSR.scala:1109:67]
wire delegable_19 = 1'h1; // @[CSR.scala:1109:67]
wire delegable_20 = 1'h1; // @[CSR.scala:1109:67]
wire delegable_22 = 1'h1; // @[CSR.scala:1109:67]
wire delegable_24 = 1'h1; // @[CSR.scala:1109:67]
wire delegable_27 = 1'h1; // @[CSR.scala:1109:67]
wire delegable_28 = 1'h1; // @[CSR.scala:1109:67]
wire delegable_29 = 1'h1; // @[CSR.scala:1109:67]
wire _csr_wen_T_5 = 1'h1; // @[CSR.scala:1222:59]
wire _dMode_T_1 = 1'h1; // @[CSR.scala:1478:68]
wire _dMode_T_2 = 1'h1; // @[CSR.scala:1478:65]
wire _reg_bp_0_control_chain_T = 1'h1; // @[CSR.scala:1481:61]
wire _dMode_T_4 = 1'h1; // @[CSR.scala:1478:68]
wire _dMode_T_5 = 1'h1; // @[CSR.scala:1478:65]
wire _reg_bp_1_control_chain_T = 1'h1; // @[CSR.scala:1481:61]
wire _io_trace_0_exception_T = 1'h1; // @[CSR.scala:1620:30]
wire [22:0] io_status_zero2 = 23'h0; // @[CSR.scala:377:7]
wire [22:0] io_gstatus_zero2_0 = 23'h0; // @[CSR.scala:377:7]
wire [22:0] _reset_mstatus_WIRE_zero2 = 23'h0; // @[CSR.scala:391:47]
wire [22:0] reset_mstatus_zero2 = 23'h0; // @[CSR.scala:391:34]
wire [22:0] _read_sstatus_WIRE_zero2 = 23'h0; // @[CSR.scala:755:48]
wire [22:0] read_sstatus_zero2 = 23'h0; // @[CSR.scala:755:35]
wire io_decode_0_vector_csr = 1'h0; // @[CSR.scala:377:7]
wire io_rw_stall = 1'h0; // @[CSR.scala:377:7]
wire io_status_mbe = 1'h0; // @[CSR.scala:377:7]
wire io_status_sbe = 1'h0; // @[CSR.scala:377:7]
wire io_status_sd_rv32 = 1'h0; // @[CSR.scala:377:7]
wire io_status_ube = 1'h0; // @[CSR.scala:377:7]
wire io_status_upie = 1'h0; // @[CSR.scala:377:7]
wire io_status_hie = 1'h0; // @[CSR.scala:377:7]
wire io_status_uie = 1'h0; // @[CSR.scala:377:7]
wire io_hstatus_vtsr = 1'h0; // @[CSR.scala:377:7]
wire io_hstatus_vtw = 1'h0; // @[CSR.scala:377:7]
wire io_hstatus_vtvm = 1'h0; // @[CSR.scala:377:7]
wire io_hstatus_hu = 1'h0; // @[CSR.scala:377:7]
wire io_hstatus_vsbe = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_debug_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_cease_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_wfi_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_dv_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_v_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_mpv_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_gva_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_mbe_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_sbe_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_sd_rv32 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_tsr_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_tw_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_tvm_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_mxr_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_sum_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_mprv_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_mpie_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_ube_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_upie_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_mie_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_hie_0 = 1'h0; // @[CSR.scala:377:7]
wire io_gstatus_uie_0 = 1'h0; // @[CSR.scala:377:7]
wire io_bp_0_control_chain = 1'h0; // @[CSR.scala:377:7]
wire io_bp_0_control_h = 1'h0; // @[CSR.scala:377:7]
wire io_bp_0_textra_mselect = 1'h0; // @[CSR.scala:377:7]
wire io_bp_0_textra_pad1_0 = 1'h0; // @[CSR.scala:377:7]
wire io_bp_0_textra_sselect = 1'h0; // @[CSR.scala:377:7]
wire io_customCSRs_0_stall = 1'h0; // @[CSR.scala:377:7]
wire io_customCSRs_0_set = 1'h0; // @[CSR.scala:377:7]
wire io_customCSRs_1_stall = 1'h0; // @[CSR.scala:377:7]
wire io_customCSRs_1_set = 1'h0; // @[CSR.scala:377:7]
wire io_customCSRs_2_stall = 1'h0; // @[CSR.scala:377:7]
wire io_customCSRs_2_set = 1'h0; // @[CSR.scala:377:7]
wire io_customCSRs_3_stall = 1'h0; // @[CSR.scala:377:7]
wire io_customCSRs_3_set = 1'h0; // @[CSR.scala:377:7]
wire _reset_mstatus_WIRE_debug = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_cease = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_wfi = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_dv = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_v = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_sd = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_mpv = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_gva = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_mbe = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_sbe = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_sd_rv32 = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_tsr = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_tw = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_tvm = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_mxr = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_sum = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_mprv = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_spp = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_mpie = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_ube = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_spie = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_upie = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_mie = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_hie = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_sie = 1'h0; // @[CSR.scala:391:47]
wire _reset_mstatus_WIRE_uie = 1'h0; // @[CSR.scala:391:47]
wire reset_mstatus_debug = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_cease = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_wfi = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_dv = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_v = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_sd = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_mpv = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_gva = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_mbe = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_sbe = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_sd_rv32 = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_tsr = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_tw = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_tvm = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_mxr = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_sum = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_mprv = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_spp = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_mpie = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_ube = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_spie = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_upie = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_mie = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_hie = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_sie = 1'h0; // @[CSR.scala:391:34]
wire reset_mstatus_uie = 1'h0; // @[CSR.scala:391:34]
wire _reset_dcsr_WIRE_ebreakm = 1'h0; // @[CSR.scala:400:44]
wire _reset_dcsr_WIRE_ebreakh = 1'h0; // @[CSR.scala:400:44]
wire _reset_dcsr_WIRE_ebreaks = 1'h0; // @[CSR.scala:400:44]
wire _reset_dcsr_WIRE_ebreaku = 1'h0; // @[CSR.scala:400:44]
wire _reset_dcsr_WIRE_zero2 = 1'h0; // @[CSR.scala:400:44]
wire _reset_dcsr_WIRE_stopcycle = 1'h0; // @[CSR.scala:400:44]
wire _reset_dcsr_WIRE_stoptime = 1'h0; // @[CSR.scala:400:44]
wire _reset_dcsr_WIRE_v = 1'h0; // @[CSR.scala:400:44]
wire _reset_dcsr_WIRE_step = 1'h0; // @[CSR.scala:400:44]
wire reset_dcsr_ebreakm = 1'h0; // @[CSR.scala:400:31]
wire reset_dcsr_ebreakh = 1'h0; // @[CSR.scala:400:31]
wire reset_dcsr_ebreaks = 1'h0; // @[CSR.scala:400:31]
wire reset_dcsr_ebreaku = 1'h0; // @[CSR.scala:400:31]
wire reset_dcsr_zero2 = 1'h0; // @[CSR.scala:400:31]
wire reset_dcsr_stopcycle = 1'h0; // @[CSR.scala:400:31]
wire reset_dcsr_stoptime = 1'h0; // @[CSR.scala:400:31]
wire reset_dcsr_v = 1'h0; // @[CSR.scala:400:31]
wire reset_dcsr_step = 1'h0; // @[CSR.scala:400:31]
wire sup_zero1 = 1'h0; // @[CSR.scala:406:19]
wire sup_debug = 1'h0; // @[CSR.scala:406:19]
wire sup_sgeip = 1'h0; // @[CSR.scala:406:19]
wire sup_vseip = 1'h0; // @[CSR.scala:406:19]
wire sup_ueip = 1'h0; // @[CSR.scala:406:19]
wire sup_vstip = 1'h0; // @[CSR.scala:406:19]
wire sup_utip = 1'h0; // @[CSR.scala:406:19]
wire sup_vssip = 1'h0; // @[CSR.scala:406:19]
wire sup_usip = 1'h0; // @[CSR.scala:406:19]
wire del_zero1 = 1'h0; // @[CSR.scala:426:26]
wire del_debug = 1'h0; // @[CSR.scala:426:26]
wire del_sgeip = 1'h0; // @[CSR.scala:426:26]
wire del_meip = 1'h0; // @[CSR.scala:426:26]
wire del_vseip = 1'h0; // @[CSR.scala:426:26]
wire del_ueip = 1'h0; // @[CSR.scala:426:26]
wire del_mtip = 1'h0; // @[CSR.scala:426:26]
wire del_vstip = 1'h0; // @[CSR.scala:426:26]
wire del_utip = 1'h0; // @[CSR.scala:426:26]
wire del_msip = 1'h0; // @[CSR.scala:426:26]
wire del_vssip = 1'h0; // @[CSR.scala:426:26]
wire del_usip = 1'h0; // @[CSR.scala:426:26]
wire hi_hi_hi_hi = 1'h0; // @[CSR.scala:431:10]
wire hi_hi_hi_hi_1 = 1'h0; // @[CSR.scala:431:50]
wire _always_WIRE_zero1 = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_debug = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_rocc = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_sgeip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_meip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_vseip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_seip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_ueip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_mtip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_vstip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_stip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_utip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_msip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_vssip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_ssip = 1'h0; // @[CSR.scala:471:42]
wire _always_WIRE_usip = 1'h0; // @[CSR.scala:471:42]
wire always_zero1 = 1'h0; // @[CSR.scala:471:29]
wire always_debug = 1'h0; // @[CSR.scala:471:29]
wire always_rocc = 1'h0; // @[CSR.scala:471:29]
wire always_sgeip = 1'h0; // @[CSR.scala:471:29]
wire always_meip = 1'h0; // @[CSR.scala:471:29]
wire always_vseip = 1'h0; // @[CSR.scala:471:29]
wire always_seip = 1'h0; // @[CSR.scala:471:29]
wire always_ueip = 1'h0; // @[CSR.scala:471:29]
wire always_mtip = 1'h0; // @[CSR.scala:471:29]
wire always_vstip = 1'h0; // @[CSR.scala:471:29]
wire always_stip = 1'h0; // @[CSR.scala:471:29]
wire always_utip = 1'h0; // @[CSR.scala:471:29]
wire always_msip = 1'h0; // @[CSR.scala:471:29]
wire always_vssip = 1'h0; // @[CSR.scala:471:29]
wire always_ssip = 1'h0; // @[CSR.scala:471:29]
wire always_usip = 1'h0; // @[CSR.scala:471:29]
wire deleg_zero1 = 1'h0; // @[CSR.scala:476:28]
wire deleg_debug = 1'h0; // @[CSR.scala:476:28]
wire deleg_rocc = 1'h0; // @[CSR.scala:476:28]
wire deleg_sgeip = 1'h0; // @[CSR.scala:476:28]
wire deleg_meip = 1'h0; // @[CSR.scala:476:28]
wire deleg_vseip = 1'h0; // @[CSR.scala:476:28]
wire deleg_seip = 1'h0; // @[CSR.scala:476:28]
wire deleg_ueip = 1'h0; // @[CSR.scala:476:28]
wire deleg_mtip = 1'h0; // @[CSR.scala:476:28]
wire deleg_vstip = 1'h0; // @[CSR.scala:476:28]
wire deleg_stip = 1'h0; // @[CSR.scala:476:28]
wire deleg_utip = 1'h0; // @[CSR.scala:476:28]
wire deleg_msip = 1'h0; // @[CSR.scala:476:28]
wire deleg_vssip = 1'h0; // @[CSR.scala:476:28]
wire deleg_ssip = 1'h0; // @[CSR.scala:476:28]
wire deleg_usip = 1'h0; // @[CSR.scala:476:28]
wire hi_hi_hi_hi_2 = 1'h0; // @[CSR.scala:479:12]
wire hi_hi_hi_hi_3 = 1'h0; // @[CSR.scala:479:27]
wire _reset_mnstatus_WIRE_mpv = 1'h0; // @[CSR.scala:516:48]
wire _reset_mnstatus_WIRE_mie = 1'h0; // @[CSR.scala:516:48]
wire reset_mnstatus_mpv = 1'h0; // @[CSR.scala:516:35]
wire reset_mnstatus_mie = 1'h0; // @[CSR.scala:516:35]
wire _reg_menvcfg_WIRE_stce = 1'h0; // @[CSR.scala:525:41]
wire _reg_menvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:525:41]
wire _reg_menvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:525:41]
wire _reg_menvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:525:41]
wire _reg_menvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:525:41]
wire _reg_senvcfg_WIRE_stce = 1'h0; // @[CSR.scala:526:41]
wire _reg_senvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:526:41]
wire _reg_senvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:526:41]
wire _reg_senvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:526:41]
wire _reg_senvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:526:41]
wire _reg_henvcfg_WIRE_stce = 1'h0; // @[CSR.scala:527:41]
wire _reg_henvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:527:41]
wire _reg_henvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:527:41]
wire _reg_henvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:527:41]
wire _reg_henvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:527:41]
wire _reg_hstatus_WIRE_vtsr = 1'h0; // @[CSR.scala:552:41]
wire _reg_hstatus_WIRE_vtw = 1'h0; // @[CSR.scala:552:41]
wire _reg_hstatus_WIRE_vtvm = 1'h0; // @[CSR.scala:552:41]
wire _reg_hstatus_WIRE_hu = 1'h0; // @[CSR.scala:552:41]
wire _reg_hstatus_WIRE_spvp = 1'h0; // @[CSR.scala:552:41]
wire _reg_hstatus_WIRE_spv = 1'h0; // @[CSR.scala:552:41]
wire _reg_hstatus_WIRE_gva = 1'h0; // @[CSR.scala:552:41]
wire _reg_hstatus_WIRE_vsbe = 1'h0; // @[CSR.scala:552:41]
wire read_hvip_hi_hi_hi_hi = 1'h0; // @[CSR.scala:555:27]
wire mip_zero1 = 1'h0; // @[CSR.scala:600:24]
wire mip_debug = 1'h0; // @[CSR.scala:600:24]
wire mip_sgeip = 1'h0; // @[CSR.scala:600:24]
wire mip_vseip = 1'h0; // @[CSR.scala:600:24]
wire mip_ueip = 1'h0; // @[CSR.scala:600:24]
wire mip_vstip = 1'h0; // @[CSR.scala:600:24]
wire mip_utip = 1'h0; // @[CSR.scala:600:24]
wire mip_vssip = 1'h0; // @[CSR.scala:600:24]
wire mip_usip = 1'h0; // @[CSR.scala:600:24]
wire _any_T_47 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_48 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_49 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_50 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_51 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_52 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_53 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_54 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_55 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_56 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_57 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_58 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_59 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_60 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_61 = 1'h0; // @[CSR.scala:1637:76]
wire _any_T_62 = 1'h0; // @[CSR.scala:1637:76]
wire _which_T_47 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_48 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_49 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_50 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_51 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_52 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_53 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_54 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_55 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_56 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_57 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_58 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_59 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_60 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_61 = 1'h0; // @[CSR.scala:1638:91]
wire _which_T_62 = 1'h0; // @[CSR.scala:1638:91]
wire _io_fiom_T_5 = 1'h0; // @[CSR.scala:631:131]
wire _pmp_mask_base_T_2 = 1'h0; // @[PMP.scala:57:62]
wire _pmp_mask_base_T_5 = 1'h0; // @[PMP.scala:57:62]
wire _pmp_mask_base_T_8 = 1'h0; // @[PMP.scala:57:62]
wire _pmp_mask_base_T_11 = 1'h0; // @[PMP.scala:57:62]
wire _pmp_mask_base_T_14 = 1'h0; // @[PMP.scala:57:62]
wire _pmp_mask_base_T_17 = 1'h0; // @[PMP.scala:57:62]
wire _pmp_mask_base_T_20 = 1'h0; // @[PMP.scala:57:62]
wire _pmp_mask_base_T_23 = 1'h0; // @[PMP.scala:57:62]
wire read_mapping_lo_hi_1 = 1'h0; // @[CSR.scala:657:47]
wire read_mapping_hi_hi_1 = 1'h0; // @[CSR.scala:657:47]
wire _read_mnstatus_WIRE_mpv = 1'h0; // @[CSR.scala:675:44]
wire _read_mnstatus_WIRE_mie = 1'h0; // @[CSR.scala:675:44]
wire read_mnstatus_mpv = 1'h0; // @[CSR.scala:675:31]
wire _sie_mask_sgeip_mask_WIRE_zero1 = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_debug = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_rocc = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_sgeip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_meip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_vseip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_seip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_ueip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_mtip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_vstip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_stip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_utip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_msip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_vssip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_ssip = 1'h0; // @[CSR.scala:748:43]
wire _sie_mask_sgeip_mask_WIRE_usip = 1'h0; // @[CSR.scala:748:43]
wire sie_mask_sgeip_mask_zero1 = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_debug = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_rocc = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_meip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_vseip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_seip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_ueip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_mtip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_vstip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_stip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_utip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_msip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_vssip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_ssip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_sgeip_mask_usip = 1'h0; // @[CSR.scala:748:30]
wire sie_mask_hi_hi_hi_hi = 1'h0; // @[CSR.scala:750:59]
wire _read_sstatus_WIRE_debug = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_cease = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_wfi = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_dv = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_v = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_sd = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_mpv = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_gva = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_mbe = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_sbe = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_sd_rv32 = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_tsr = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_tw = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_tvm = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_mxr = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_sum = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_mprv = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_spp = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_mpie = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_ube = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_spie = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_upie = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_mie = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_hie = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_sie = 1'h0; // @[CSR.scala:755:48]
wire _read_sstatus_WIRE_uie = 1'h0; // @[CSR.scala:755:48]
wire read_sstatus_debug = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_cease = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_wfi = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_dv = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_v = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_mpv = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_gva = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_mbe = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_sbe = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_sd_rv32 = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_tsr = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_tw = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_tvm = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_mprv = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_mpie = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_ube = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_upie = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_mie = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_hie = 1'h0; // @[CSR.scala:755:35]
wire read_sstatus_uie = 1'h0; // @[CSR.scala:755:35]
wire read_pmp_15_cfg_l = 1'h0; // @[CSR.scala:787:59]
wire read_pmp_15_cfg_x = 1'h0; // @[CSR.scala:787:59]
wire read_pmp_15_cfg_w = 1'h0; // @[CSR.scala:787:59]
wire read_pmp_15_cfg_r = 1'h0; // @[CSR.scala:787:59]
wire _reg_custom_T = 1'h0; // @[CSR.scala:801:16]
wire _reg_custom_T_1 = 1'h0; // @[CSR.scala:801:16]
wire _reg_custom_T_2 = 1'h0; // @[CSR.scala:801:16]
wire _reg_custom_T_3 = 1'h0; // @[CSR.scala:801:16]
wire _allow_counter_T_4 = 1'h0; // @[CSR.scala:913:8]
wire io_decode_0_vector_csr_plaOutput = 1'h0; // @[pla.scala:81:23]
wire _io_decode_0_vector_csr_T = 1'h0; // @[Decode.scala:55:116]
wire _io_decode_0_rocc_illegal_T = 1'h0; // @[CSR.scala:919:41]
wire _io_decode_0_rocc_illegal_T_1 = 1'h0; // @[CSR.scala:919:85]
wire _io_decode_0_rocc_illegal_T_2 = 1'h0; // @[CSR.scala:919:66]
wire _io_decode_0_rocc_illegal_T_3 = 1'h0; // @[CSR.scala:919:49]
wire _csr_addr_legal_T_3 = 1'h0; // @[CSR.scala:921:25]
wire _csr_addr_legal_T_5 = 1'h0; // @[CSR.scala:921:43]
wire _csr_addr_legal_T_8 = 1'h0; // @[CSR.scala:921:74]
wire io_decode_0_read_illegal_plaOutput_1 = 1'h0; // @[pla.scala:81:23]
wire _io_decode_0_read_illegal_T_16 = 1'h0; // @[Decode.scala:55:116]
wire _io_decode_0_read_illegal_T_17 = 1'h0; // @[CSR.scala:928:43]
wire _io_decode_0_system_illegal_T_20 = 1'h0; // @[CSR.scala:940:25]
wire _io_decode_0_system_illegal_T_21 = 1'h0; // @[CSR.scala:940:22]
wire _io_decode_0_system_illegal_T_23 = 1'h0; // @[CSR.scala:941:18]
wire _io_decode_0_system_illegal_T_24 = 1'h0; // @[CSR.scala:941:15]
wire _io_decode_0_virtual_access_illegal_T_27 = 1'h0; // @[CSR.scala:947:50]
wire _io_decode_0_virtual_system_illegal_T_5 = 1'h0; // @[CSR.scala:953:57]
wire trapToNmiInt = 1'h0; // @[CSR.scala:990:33]
wire _trapToNmiXcpt_T = 1'h0; // @[CSR.scala:991:37]
wire trapToNmiXcpt = 1'h0; // @[CSR.scala:991:34]
wire trapToNmi = 1'h0; // @[CSR.scala:992:32]
wire _nmiTVec_T = 1'h0; // @[CSR.scala:993:21]
wire _nmiTVec_T_1 = 1'h0; // @[CSR.scala:993:58]
wire _io_status_sd_T_3 = 1'h0; // @[CSR.scala:1003:74]
wire _io_status_sd_rv32_T = 1'h0; // @[CSR.scala:1010:39]
wire _io_gstatus_sd_rv32_T = 1'h0; // @[CSR.scala:1018:40]
wire _en_T_1 = 1'h0; // @[CSR.scala:1096:71]
wire _en_T_2 = 1'h0; // @[CSR.scala:1096:24]
wire en = 1'h0; // @[CSR.scala:1096:79]
wire delegable = 1'h0; // @[CSR.scala:1097:65]
wire _en_T_13 = 1'h0; // @[CSR.scala:1096:71]
wire _en_T_14 = 1'h0; // @[CSR.scala:1096:24]
wire en_2 = 1'h0; // @[CSR.scala:1096:79]
wire delegable_2 = 1'h0; // @[CSR.scala:1097:65]
wire delegable_3 = 1'h0; // @[CSR.scala:1097:65]
wire _en_T_25 = 1'h0; // @[CSR.scala:1096:71]
wire _en_T_26 = 1'h0; // @[CSR.scala:1096:24]
wire en_4 = 1'h0; // @[CSR.scala:1096:79]
wire delegable_4 = 1'h0; // @[CSR.scala:1097:65]
wire _en_T_37 = 1'h0; // @[CSR.scala:1096:71]
wire _en_T_38 = 1'h0; // @[CSR.scala:1096:24]
wire en_6 = 1'h0; // @[CSR.scala:1096:79]
wire delegable_6 = 1'h0; // @[CSR.scala:1097:65]
wire delegable_7 = 1'h0; // @[CSR.scala:1097:65]
wire _en_T_49 = 1'h0; // @[CSR.scala:1096:71]
wire _en_T_50 = 1'h0; // @[CSR.scala:1096:24]
wire en_8 = 1'h0; // @[CSR.scala:1096:79]
wire delegable_8 = 1'h0; // @[CSR.scala:1097:65]
wire _en_T_61 = 1'h0; // @[CSR.scala:1096:71]
wire _en_T_62 = 1'h0; // @[CSR.scala:1096:24]
wire en_10 = 1'h0; // @[CSR.scala:1096:79]
wire delegable_10 = 1'h0; // @[CSR.scala:1097:65]
wire delegable_11 = 1'h0; // @[CSR.scala:1097:65]
wire _en_T_73 = 1'h0; // @[CSR.scala:1096:71]
wire _en_T_74 = 1'h0; // @[CSR.scala:1096:24]
wire en_12 = 1'h0; // @[CSR.scala:1096:79]
wire delegable_12 = 1'h0; // @[CSR.scala:1097:65]
wire _en_T_85 = 1'h0; // @[CSR.scala:1096:71]
wire _en_T_86 = 1'h0; // @[CSR.scala:1096:24]
wire en_14 = 1'h0; // @[CSR.scala:1096:79]
wire delegable_14 = 1'h0; // @[CSR.scala:1097:65]
wire _en_T_91 = 1'h0; // @[CSR.scala:1096:71]
wire _en_T_92 = 1'h0; // @[CSR.scala:1096:24]
wire en_15 = 1'h0; // @[CSR.scala:1096:79]
wire delegable_15 = 1'h0; // @[CSR.scala:1097:65]
wire delegable_17 = 1'h0; // @[CSR.scala:1109:67]
wire delegable_21 = 1'h0; // @[CSR.scala:1109:67]
wire delegable_23 = 1'h0; // @[CSR.scala:1109:67]
wire delegable_25 = 1'h0; // @[CSR.scala:1109:67]
wire delegable_26 = 1'h0; // @[CSR.scala:1109:67]
wire _reg_mstatus_v_T = 1'h0; // @[CSR.scala:1123:44]
wire _reg_mstatus_v_T_1 = 1'h0; // @[CSR.scala:1136:42]
wire _reg_mstatus_v_T_3 = 1'h0; // @[CSR.scala:1136:56]
wire _reg_mstatus_v_T_4 = 1'h0; // @[CSR.scala:1141:42]
wire _reg_mstatus_v_T_5 = 1'h0; // @[CSR.scala:1141:82]
wire _reg_mstatus_v_T_6 = 1'h0; // @[CSR.scala:1141:62]
wire _reg_mstatus_mpp_T = 1'h0; // @[CSR.scala:1647:35]
wire _reg_mstatus_mpp_T_1 = 1'h0; // @[CSR.scala:1647:29]
wire _reg_mstatus_v_T_7 = 1'h0; // @[CSR.scala:1150:42]
wire _reg_mstatus_v_T_9 = 1'h0; // @[CSR.scala:1150:61]
wire _io_rw_rdata_T = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_23 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_24 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_25 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_26 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_27 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_28 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_29 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_30 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_31 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_32 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_33 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_34 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_35 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_36 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_37 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_38 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_39 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_40 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_41 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_42 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_43 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_44 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_45 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_46 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_47 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_48 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_49 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_50 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_51 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_52 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_53 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_54 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_55 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_56 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_57 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_58 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_59 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_60 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_61 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_62 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_63 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_64 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_65 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_66 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_67 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_68 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_69 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_70 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_71 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_72 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_73 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_74 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_75 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_76 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_77 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_78 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_79 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_80 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_81 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_82 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_83 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_84 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_85 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_86 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_87 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_88 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_89 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_90 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_91 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_92 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_93 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_94 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_95 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_96 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_97 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_98 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_99 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_100 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_101 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_102 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_103 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_104 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_105 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_106 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_107 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_108 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_109 = 1'h0; // @[Mux.scala:30:73]
wire _io_rw_rdata_T_149 = 1'h0; // @[Mux.scala:30:73]
wire set_vs_dirty = 1'h0; // @[CSR.scala:1191:33]
wire new_mip_hi_hi_hi_hi = 1'h0; // @[CSR.scala:1271:59]
wire _reg_bp_0_control_chain_T_1 = 1'h0; // @[CSR.scala:1481:49]
wire _reg_bp_0_control_chain_T_2 = 1'h0; // @[CSR.scala:1481:46]
wire _reg_bp_0_control_chain_T_3 = 1'h0; // @[CSR.scala:1481:88]
wire _reg_bp_0_control_chain_T_5 = 1'h0; // @[CSR.scala:1481:75]
wire _reg_bp_1_control_chain_T_1 = 1'h0; // @[CSR.scala:1481:49]
wire _reg_bp_1_control_chain_T_2 = 1'h0; // @[CSR.scala:1481:46]
wire _reg_bp_1_control_chain_T_3 = 1'h0; // @[CSR.scala:1481:88]
wire _reg_bp_1_control_chain_T_5 = 1'h0; // @[CSR.scala:1481:75]
wire _reg_bp_1_WIRE_control_dmode = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_control_action = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_control_chain = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_control_m = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_control_h = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_control_s = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_control_u = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_control_x = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_control_w = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_control_r = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_textra_mselect = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_textra_pad1 = 1'h0; // @[CSR.scala:1613:23]
wire _reg_bp_1_WIRE_textra_sselect = 1'h0; // @[CSR.scala:1613:23]
wire [7:0] io_status_zero1 = 8'h0; // @[CSR.scala:377:7]
wire [7:0] io_gstatus_zero1_0 = 8'h0; // @[CSR.scala:377:7]
wire [7:0] _reset_mstatus_WIRE_zero1 = 8'h0; // @[CSR.scala:391:47]
wire [7:0] reset_mstatus_zero1 = 8'h0; // @[CSR.scala:391:34]
wire [7:0] lo_2 = 8'h0; // @[CSR.scala:479:12]
wire [7:0] hi_2 = 8'h0; // @[CSR.scala:479:12]
wire [7:0] lo_3 = 8'h0; // @[CSR.scala:479:27]
wire [7:0] hi_3 = 8'h0; // @[CSR.scala:479:27]
wire [7:0] sie_mask_lo = 8'h0; // @[CSR.scala:750:59]
wire [7:0] _read_sstatus_WIRE_zero1 = 8'h0; // @[CSR.scala:755:48]
wire [7:0] read_sstatus_zero1 = 8'h0; // @[CSR.scala:755:35]
wire [1:0] io_status_xs = 2'h3; // @[CSR.scala:377:7]
wire [1:0] io_gstatus_xs = 2'h3; // @[CSR.scala:377:7]
wire [1:0] reset_mstatus_prv = 2'h3; // @[CSR.scala:391:34]
wire [1:0] reset_mstatus_xs = 2'h3; // @[CSR.scala:391:34]
wire [1:0] reset_mstatus_mpp = 2'h3; // @[CSR.scala:391:34]
wire [1:0] reset_dcsr_prv = 2'h3; // @[CSR.scala:400:31]
wire [1:0] reset_mnstatus_mpp = 2'h3; // @[CSR.scala:516:35]
wire [1:0] read_mnstatus_mpp = 2'h3; // @[CSR.scala:675:31]
wire [1:0] read_sstatus_xs = 2'h3; // @[CSR.scala:755:35]
wire [1:0] io_status_vs = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_hstatus_zero3 = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_hstatus_zero2 = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_gstatus_dprv_0 = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_gstatus_prv_0 = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_gstatus_sxl_0 = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_gstatus_fs_0 = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_gstatus_mpp_0 = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_gstatus_vs_0 = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_bp_0_control_zero = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[CSR.scala:377:7]
wire [1:0] _reset_mstatus_WIRE_dprv = 2'h0; // @[CSR.scala:391:47]
wire [1:0] _reset_mstatus_WIRE_prv = 2'h0; // @[CSR.scala:391:47]
wire [1:0] _reset_mstatus_WIRE_sxl = 2'h0; // @[CSR.scala:391:47]
wire [1:0] _reset_mstatus_WIRE_uxl = 2'h0; // @[CSR.scala:391:47]
wire [1:0] _reset_mstatus_WIRE_xs = 2'h0; // @[CSR.scala:391:47]
wire [1:0] _reset_mstatus_WIRE_fs = 2'h0; // @[CSR.scala:391:47]
wire [1:0] _reset_mstatus_WIRE_mpp = 2'h0; // @[CSR.scala:391:47]
wire [1:0] _reset_mstatus_WIRE_vs = 2'h0; // @[CSR.scala:391:47]
wire [1:0] reset_mstatus_dprv = 2'h0; // @[CSR.scala:391:34]
wire [1:0] reset_mstatus_sxl = 2'h0; // @[CSR.scala:391:34]
wire [1:0] reset_mstatus_uxl = 2'h0; // @[CSR.scala:391:34]
wire [1:0] reset_mstatus_fs = 2'h0; // @[CSR.scala:391:34]
wire [1:0] reset_mstatus_vs = 2'h0; // @[CSR.scala:391:34]
wire [1:0] _reset_dcsr_WIRE_xdebugver = 2'h0; // @[CSR.scala:400:44]
wire [1:0] _reset_dcsr_WIRE_zero4 = 2'h0; // @[CSR.scala:400:44]
wire [1:0] _reset_dcsr_WIRE_zero1 = 2'h0; // @[CSR.scala:400:44]
wire [1:0] _reset_dcsr_WIRE_prv = 2'h0; // @[CSR.scala:400:44]
wire [1:0] reset_dcsr_zero4 = 2'h0; // @[CSR.scala:400:31]
wire [1:0] reset_dcsr_zero1 = 2'h0; // @[CSR.scala:400:31]
wire [1:0] hi_hi_hi = 2'h0; // @[CSR.scala:431:10]
wire [1:0] lo_lo_hi_1 = 2'h0; // @[CSR.scala:431:50]
wire [1:0] lo_hi_hi_1 = 2'h0; // @[CSR.scala:431:50]
wire [1:0] hi_lo_hi_1 = 2'h0; // @[CSR.scala:431:50]
wire [1:0] hi_hi_hi_1 = 2'h0; // @[CSR.scala:431:50]
wire [1:0] lo_lo_lo_2 = 2'h0; // @[CSR.scala:479:12]
wire [1:0] lo_lo_hi_2 = 2'h0; // @[CSR.scala:479:12]
wire [1:0] lo_hi_lo_2 = 2'h0; // @[CSR.scala:479:12]
wire [1:0] lo_hi_hi_2 = 2'h0; // @[CSR.scala:479:12]
wire [1:0] hi_lo_lo_2 = 2'h0; // @[CSR.scala:479:12]
wire [1:0] hi_lo_hi_2 = 2'h0; // @[CSR.scala:479:12]
wire [1:0] hi_hi_lo_2 = 2'h0; // @[CSR.scala:479:12]
wire [1:0] hi_hi_hi_2 = 2'h0; // @[CSR.scala:479:12]
wire [1:0] lo_lo_lo_3 = 2'h0; // @[CSR.scala:479:27]
wire [1:0] lo_lo_hi_3 = 2'h0; // @[CSR.scala:479:27]
wire [1:0] lo_hi_lo_3 = 2'h0; // @[CSR.scala:479:27]
wire [1:0] lo_hi_hi_3 = 2'h0; // @[CSR.scala:479:27]
wire [1:0] hi_lo_lo_3 = 2'h0; // @[CSR.scala:479:27]
wire [1:0] hi_lo_hi_3 = 2'h0; // @[CSR.scala:479:27]
wire [1:0] hi_hi_lo_3 = 2'h0; // @[CSR.scala:479:27]
wire [1:0] hi_hi_hi_3 = 2'h0; // @[CSR.scala:479:27]
wire [1:0] _reset_mnstatus_WIRE_mpp = 2'h0; // @[CSR.scala:516:48]
wire [1:0] _reg_menvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:525:41]
wire [1:0] _reg_senvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:526:41]
wire [1:0] _reg_henvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:527:41]
wire [1:0] _reg_hstatus_WIRE_vsxl = 2'h0; // @[CSR.scala:552:41]
wire [1:0] _reg_hstatus_WIRE_zero3 = 2'h0; // @[CSR.scala:552:41]
wire [1:0] _reg_hstatus_WIRE_zero2 = 2'h0; // @[CSR.scala:552:41]
wire [1:0] read_hvip_lo_lo_hi = 2'h0; // @[CSR.scala:555:27]
wire [1:0] read_hvip_lo_hi_hi = 2'h0; // @[CSR.scala:555:27]
wire [1:0] read_hvip_hi_lo_hi = 2'h0; // @[CSR.scala:555:27]
wire [1:0] read_hvip_hi_hi_lo = 2'h0; // @[CSR.scala:555:27]
wire [1:0] pmp_cfg_res = 2'h0; // @[PMP.scala:24:19]
wire [1:0] pmp_1_cfg_res = 2'h0; // @[PMP.scala:24:19]
wire [1:0] pmp_2_cfg_res = 2'h0; // @[PMP.scala:24:19]
wire [1:0] pmp_3_cfg_res = 2'h0; // @[PMP.scala:24:19]
wire [1:0] pmp_4_cfg_res = 2'h0; // @[PMP.scala:24:19]
wire [1:0] pmp_5_cfg_res = 2'h0; // @[PMP.scala:24:19]
wire [1:0] pmp_6_cfg_res = 2'h0; // @[PMP.scala:24:19]
wire [1:0] pmp_7_cfg_res = 2'h0; // @[PMP.scala:24:19]
wire [1:0] debug_csrs_lo_hi_hi = 2'h0; // @[CSR.scala:670:27]
wire [1:0] _read_mnstatus_WIRE_mpp = 2'h0; // @[CSR.scala:675:44]
wire [1:0] read_vcsr = 2'h0; // @[CSR.scala:695:22]
wire [1:0] hi_hi_4 = 2'h0; // @[CSR.scala:742:49]
wire [1:0] sie_mask_lo_lo_lo = 2'h0; // @[CSR.scala:750:59]
wire [1:0] sie_mask_lo_lo_hi = 2'h0; // @[CSR.scala:750:59]
wire [1:0] sie_mask_lo_hi_lo = 2'h0; // @[CSR.scala:750:59]
wire [1:0] sie_mask_lo_hi_hi = 2'h0; // @[CSR.scala:750:59]
wire [1:0] sie_mask_hi_lo_lo = 2'h0; // @[CSR.scala:750:59]
wire [1:0] sie_mask_hi_lo_hi = 2'h0; // @[CSR.scala:750:59]
wire [1:0] sie_mask_hi_hi_hi = 2'h0; // @[CSR.scala:750:59]
wire [1:0] _read_sstatus_WIRE_dprv = 2'h0; // @[CSR.scala:755:48]
wire [1:0] _read_sstatus_WIRE_prv = 2'h0; // @[CSR.scala:755:48]
wire [1:0] _read_sstatus_WIRE_sxl = 2'h0; // @[CSR.scala:755:48]
wire [1:0] _read_sstatus_WIRE_uxl = 2'h0; // @[CSR.scala:755:48]
wire [1:0] _read_sstatus_WIRE_xs = 2'h0; // @[CSR.scala:755:48]
wire [1:0] _read_sstatus_WIRE_fs = 2'h0; // @[CSR.scala:755:48]
wire [1:0] _read_sstatus_WIRE_mpp = 2'h0; // @[CSR.scala:755:48]
wire [1:0] _read_sstatus_WIRE_vs = 2'h0; // @[CSR.scala:755:48]
wire [1:0] read_sstatus_dprv = 2'h0; // @[CSR.scala:755:35]
wire [1:0] read_sstatus_prv = 2'h0; // @[CSR.scala:755:35]
wire [1:0] read_sstatus_sxl = 2'h0; // @[CSR.scala:755:35]
wire [1:0] read_sstatus_mpp = 2'h0; // @[CSR.scala:755:35]
wire [1:0] read_sstatus_vs = 2'h0; // @[CSR.scala:755:35]
wire [1:0] lo_lo_lo_hi = 2'h0; // @[CSR.scala:768:51]
wire [1:0] lo_hi_hi_hi_hi = 2'h0; // @[CSR.scala:768:51]
wire [1:0] hi_lo_hi_hi_hi = 2'h0; // @[CSR.scala:768:51]
wire [1:0] hi_hi_hi_hi_hi = 2'h0; // @[CSR.scala:768:51]
wire [1:0] hi_hi_6 = 2'h0; // @[CSR.scala:780:49]
wire [1:0] read_pmp_15_cfg_res = 2'h0; // @[CSR.scala:787:59]
wire [1:0] read_pmp_15_cfg_a = 2'h0; // @[CSR.scala:787:59]
wire [1:0] lo_hi_16 = 2'h0; // @[package.scala:45:36]
wire [1:0] lo_hi_17 = 2'h0; // @[package.scala:45:36]
wire [1:0] lo_hi_18 = 2'h0; // @[package.scala:45:36]
wire [1:0] lo_hi_19 = 2'h0; // @[package.scala:45:36]
wire [1:0] lo_hi_20 = 2'h0; // @[package.scala:45:36]
wire [1:0] lo_hi_21 = 2'h0; // @[package.scala:45:36]
wire [1:0] lo_hi_22 = 2'h0; // @[package.scala:45:36]
wire [1:0] lo_hi_23 = 2'h0; // @[package.scala:45:36]
wire [1:0] decoded_orMatrixOutputs_lo_lo = 2'h0; // @[pla.scala:102:36]
wire [1:0] decoded_orMatrixOutputs_lo_lo_1 = 2'h0; // @[pla.scala:102:36]
wire [1:0] nmiTVec = 2'h0; // @[CSR.scala:993:62]
wire [1:0] new_mip_lo_lo_hi = 2'h0; // @[CSR.scala:1271:59]
wire [1:0] new_mip_lo_hi_hi = 2'h0; // @[CSR.scala:1271:59]
wire [1:0] new_mip_hi_lo_hi = 2'h0; // @[CSR.scala:1271:59]
wire [1:0] new_mip_hi_hi_lo = 2'h0; // @[CSR.scala:1271:59]
wire [1:0] newBPC_lo_lo_hi_1 = 2'h0; // @[CSR.scala:1477:67]
wire [1:0] newBPC_lo_hi_lo_1 = 2'h0; // @[CSR.scala:1477:67]
wire [1:0] newBPC_lo_hi_hi_1 = 2'h0; // @[CSR.scala:1477:67]
wire [1:0] newBPC_hi_lo_hi_1 = 2'h0; // @[CSR.scala:1477:67]
wire [1:0] _reg_bp_1_WIRE_control_zero = 2'h0; // @[CSR.scala:1613:23]
wire [1:0] _reg_bp_1_WIRE_control_tmatch = 2'h0; // @[CSR.scala:1613:23]
wire [29:0] io_hstatus_zero6 = 30'h0; // @[CSR.scala:377:7]
wire [29:0] _reg_hstatus_WIRE_zero6 = 30'h0; // @[CSR.scala:552:41]
wire [29:0] read_pmp_15_addr = 30'h0; // @[CSR.scala:787:59]
wire [29:0] _io_rw_rdata_T_137 = 30'h0; // @[Mux.scala:30:73]
wire [29:0] _io_rw_rdata_T_138 = 30'h0; // @[Mux.scala:30:73]
wire [29:0] _io_rw_rdata_T_139 = 30'h0; // @[Mux.scala:30:73]
wire [29:0] _io_rw_rdata_T_140 = 30'h0; // @[Mux.scala:30:73]
wire [29:0] _io_rw_rdata_T_141 = 30'h0; // @[Mux.scala:30:73]
wire [29:0] _io_rw_rdata_T_142 = 30'h0; // @[Mux.scala:30:73]
wire [29:0] _io_rw_rdata_T_143 = 30'h0; // @[Mux.scala:30:73]
wire [29:0] _io_rw_rdata_T_144 = 30'h0; // @[Mux.scala:30:73]
wire [8:0] io_hstatus_zero5 = 9'h0; // @[CSR.scala:377:7]
wire [8:0] _reg_hstatus_WIRE_zero5 = 9'h0; // @[CSR.scala:552:41]
wire [8:0] hi_lo_lo_lo = 9'h0; // @[CSR.scala:768:51]
wire [5:0] io_hstatus_vgein = 6'h0; // @[CSR.scala:377:7]
wire [5:0] _reg_hstatus_WIRE_vgein = 6'h0; // @[CSR.scala:552:41]
wire [5:0] hi_lo_hi_4 = 6'h0; // @[CSR.scala:768:51]
wire [5:0] newBPC_hi_lo_1 = 6'h0; // @[CSR.scala:1477:67]
wire [5:0] _reg_bp_1_WIRE_control_maskmax = 6'h0; // @[CSR.scala:1613:23]
wire [4:0] io_hstatus_zero1 = 5'h0; // @[CSR.scala:377:7]
wire [4:0] _reg_hstatus_WIRE_zero1 = 5'h0; // @[CSR.scala:552:41]
wire [4:0] hi_19 = 5'h0; // @[package.scala:45:36]
wire [4:0] hi_20 = 5'h0; // @[package.scala:45:36]
wire [4:0] hi_21 = 5'h0; // @[package.scala:45:36]
wire [4:0] hi_22 = 5'h0; // @[package.scala:45:36]
wire [4:0] hi_23 = 5'h0; // @[package.scala:45:36]
wire [4:0] hi_24 = 5'h0; // @[package.scala:45:36]
wire [4:0] hi_25 = 5'h0; // @[package.scala:45:36]
wire [4:0] hi_26 = 5'h0; // @[package.scala:45:36]
wire [4:0] newBPC_hi_hi_hi_1 = 5'h0; // @[CSR.scala:1477:67]
wire [15:0] io_ptbr_asid = 16'h0; // @[CSR.scala:377:7]
wire [15:0] io_hgatp_asid = 16'h0; // @[CSR.scala:377:7]
wire [15:0] io_vsatp_asid = 16'h0; // @[CSR.scala:377:7]
wire [15:0] hs_delegable_interrupts = 16'h0; // @[CSR.scala:479:12]
wire [15:0] mideleg_always_hs = 16'h0; // @[CSR.scala:479:27]
wire [15:0] read_hvip = 16'h0; // @[CSR.scala:555:34]
wire [15:0] read_hip = 16'h0; // @[CSR.scala:611:27]
wire [15:0] lo_lo_8 = 16'h0; // @[package.scala:45:27]
wire [15:0] lo_hi_24 = 16'h0; // @[package.scala:45:27]
wire [15:0] hi_lo_8 = 16'h0; // @[package.scala:45:27]
wire [15:0] hi_hi_24 = 16'h0; // @[package.scala:45:27]
wire [15:0] _en_T = 16'h0; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _en_T_12 = 16'h0; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_2 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _delegable_T_3 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _en_T_24 = 16'h0; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_4 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _en_T_36 = 16'h0; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_6 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _delegable_T_7 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _en_T_48 = 16'h0; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_8 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _en_T_60 = 16'h0; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_10 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _delegable_T_11 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _en_T_72 = 16'h0; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_12 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _en_T_84 = 16'h0; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_14 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _en_T_90 = 16'h0; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_15 = 16'h0; // @[CSR.scala:1097:43]
wire [15:0] _delegable_T_17 = 16'h0; // @[CSR.scala:1109:45]
wire [15:0] _delegable_T_21 = 16'h0; // @[CSR.scala:1109:45]
wire [15:0] _delegable_T_23 = 16'h0; // @[CSR.scala:1109:45]
wire [15:0] _delegable_T_25 = 16'h0; // @[CSR.scala:1109:45]
wire [15:0] _delegable_T_26 = 16'h0; // @[CSR.scala:1109:45]
wire [3:0] io_hgatp_mode = 4'h0; // @[CSR.scala:377:7]
wire [3:0] io_vsatp_mode = 4'h0; // @[CSR.scala:377:7]
wire [3:0] lo_lo_2 = 4'h0; // @[CSR.scala:479:12]
wire [3:0] lo_hi_2 = 4'h0; // @[CSR.scala:479:12]
wire [3:0] hi_lo_2 = 4'h0; // @[CSR.scala:479:12]
wire [3:0] hi_hi_2 = 4'h0; // @[CSR.scala:479:12]
wire [3:0] lo_lo_3 = 4'h0; // @[CSR.scala:479:27]
wire [3:0] lo_hi_3 = 4'h0; // @[CSR.scala:479:27]
wire [3:0] hi_lo_3 = 4'h0; // @[CSR.scala:479:27]
wire [3:0] hi_hi_3 = 4'h0; // @[CSR.scala:479:27]
wire [3:0] sie_mask_lo_lo = 4'h0; // @[CSR.scala:750:59]
wire [3:0] sie_mask_lo_hi = 4'h0; // @[CSR.scala:750:59]
wire [3:0] sie_mask_hi_lo = 4'h0; // @[CSR.scala:750:59]
wire [3:0] lo_hi_lo_lo = 4'h0; // @[CSR.scala:768:51]
wire [3:0] hi_hi_lo_hi = 4'h0; // @[CSR.scala:768:51]
wire [3:0] newBPC_lo_hi_1 = 4'h0; // @[CSR.scala:1477:67]
wire [3:0] newBPC_hi_lo_lo_1 = 4'h0; // @[CSR.scala:1477:67]
wire [3:0] _reg_bp_1_WIRE_control_ttype = 4'h0; // @[CSR.scala:1613:23]
wire [43:0] io_hgatp_ppn = 44'h0; // @[CSR.scala:377:7]
wire [43:0] io_vsatp_ppn = 44'h0; // @[CSR.scala:377:7]
wire [3:0] io_bp_0_control_ttype = 4'h2; // @[CSR.scala:377:7]
wire [3:0] hi_hi = 4'h2; // @[CSR.scala:431:10]
wire [3:0] lo_lo_1 = 4'h2; // @[CSR.scala:431:50]
wire [3:0] lo_hi_1 = 4'h2; // @[CSR.scala:431:50]
wire [3:0] hi_lo_1 = 4'h2; // @[CSR.scala:431:50]
wire [3:0] hi_hi_1 = 4'h2; // @[CSR.scala:431:50]
wire [5:0] io_bp_0_control_maskmax = 6'h4; // @[CSR.scala:377:7]
wire [39:0] io_bp_0_control_reserved = 40'h0; // @[CSR.scala:377:7]
wire [39:0] _reg_bp_1_WIRE_control_reserved = 40'h0; // @[CSR.scala:1613:23]
wire [63:0] io_customCSRs_0_sdata = 64'h0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_1_sdata = 64'h0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_2_sdata = 64'h0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_3_sdata = 64'h0; // @[CSR.scala:377:7]
wire [63:0] read_hideleg = 64'h0; // @[CSR.scala:541:14]
wire [63:0] read_hedeleg = 64'h0; // @[CSR.scala:545:14]
wire [63:0] read_hie = 64'h0; // @[CSR.scala:556:26]
wire [63:0] read_vstvec = 64'h0; // @[package.scala:132:15]
wire [63:0] _vs_interrupts_T_6 = 64'h0; // @[CSR.scala:622:153]
wire [63:0] vs_interrupts = 64'h0; // @[CSR.scala:622:26]
wire [63:0] _io_rw_rdata_T_128 = 64'h0; // @[Mux.scala:30:73]
wire [63:0] _newBPC_T_24 = 64'h0; // @[CSR.scala:1477:67]
wire [63:0] _newBPC_T_26 = 64'h0; // @[CSR.scala:1643:9]
wire [63:0] _reg_custom_1_T = 64'h0; // @[CSR.scala:1506:23]
wire [63:0] _reg_custom_2_T = 64'h0; // @[CSR.scala:1506:23]
wire [63:0] _reg_custom_3_T = 64'h0; // @[CSR.scala:1506:23]
wire [63:0] _reg_custom_0_T_4 = 64'h0; // @[CSR.scala:1531:24]
wire [63:0] _reg_custom_1_T_4 = 64'h0; // @[CSR.scala:1531:24]
wire [63:0] _reg_custom_2_T_4 = 64'h0; // @[CSR.scala:1531:24]
wire [63:0] _reg_custom_3_T_4 = 64'h0; // @[CSR.scala:1531:24]
wire [56:0] hi_6 = 57'h0; // @[CSR.scala:742:49]
wire [56:0] hi_9 = 57'h0; // @[CSR.scala:780:49]
wire [56:0] newBPC_hi_1 = 57'h0; // @[CSR.scala:1477:67]
wire [50:0] newBPC_hi_hi_1 = 51'h0; // @[CSR.scala:1477:67]
wire [45:0] newBPC_hi_hi_lo_1 = 46'h0; // @[CSR.scala:1477:67]
wire [6:0] newBPC_lo_1 = 7'h0; // @[CSR.scala:1477:67]
wire [2:0] _reset_dcsr_WIRE_cause = 3'h0; // @[CSR.scala:400:44]
wire [2:0] reset_dcsr_cause = 3'h0; // @[CSR.scala:400:31]
wire [2:0] _reset_mnstatus_WIRE_zero3 = 3'h0; // @[CSR.scala:516:48]
wire [2:0] _reset_mnstatus_WIRE_zero2 = 3'h0; // @[CSR.scala:516:48]
wire [2:0] _reset_mnstatus_WIRE_zero1 = 3'h0; // @[CSR.scala:516:48]
wire [2:0] reset_mnstatus_zero3 = 3'h0; // @[CSR.scala:516:35]
wire [2:0] reset_mnstatus_zero2 = 3'h0; // @[CSR.scala:516:35]
wire [2:0] reset_mnstatus_zero1 = 3'h0; // @[CSR.scala:516:35]
wire [2:0] _reg_menvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:525:41]
wire [2:0] _reg_senvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:526:41]
wire [2:0] _reg_henvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:527:41]
wire [2:0] _read_mnstatus_WIRE_zero3 = 3'h0; // @[CSR.scala:675:44]
wire [2:0] _read_mnstatus_WIRE_zero2 = 3'h0; // @[CSR.scala:675:44]
wire [2:0] _read_mnstatus_WIRE_zero1 = 3'h0; // @[CSR.scala:675:44]
wire [2:0] read_mnstatus_zero3 = 3'h0; // @[CSR.scala:675:31]
wire [2:0] read_mnstatus_zero2 = 3'h0; // @[CSR.scala:675:31]
wire [2:0] read_mnstatus_zero1 = 3'h0; // @[CSR.scala:675:31]
wire [2:0] lo_hi_4 = 3'h0; // @[CSR.scala:742:49]
wire [2:0] hi_lo_hi_lo = 3'h0; // @[CSR.scala:768:51]
wire [2:0] hi_lo_hi_hi = 3'h0; // @[CSR.scala:768:51]
wire [2:0] hi_hi_lo_hi_hi = 3'h0; // @[CSR.scala:768:51]
wire [2:0] hi_hi_hi_hi_4 = 3'h0; // @[CSR.scala:768:51]
wire [2:0] lo_hi_6 = 3'h0; // @[CSR.scala:780:49]
wire [2:0] lo_16 = 3'h0; // @[package.scala:45:36]
wire [2:0] hi_hi_16 = 3'h0; // @[package.scala:45:36]
wire [2:0] lo_17 = 3'h0; // @[package.scala:45:36]
wire [2:0] hi_hi_17 = 3'h0; // @[package.scala:45:36]
wire [2:0] lo_18 = 3'h0; // @[package.scala:45:36]
wire [2:0] hi_hi_18 = 3'h0; // @[package.scala:45:36]
wire [2:0] lo_19 = 3'h0; // @[package.scala:45:36]
wire [2:0] hi_hi_19 = 3'h0; // @[package.scala:45:36]
wire [2:0] lo_20 = 3'h0; // @[package.scala:45:36]
wire [2:0] hi_hi_20 = 3'h0; // @[package.scala:45:36]
wire [2:0] lo_21 = 3'h0; // @[package.scala:45:36]
wire [2:0] hi_hi_21 = 3'h0; // @[package.scala:45:36]
wire [2:0] lo_22 = 3'h0; // @[package.scala:45:36]
wire [2:0] hi_hi_22 = 3'h0; // @[package.scala:45:36]
wire [2:0] lo_23 = 3'h0; // @[package.scala:45:36]
wire [2:0] hi_hi_23 = 3'h0; // @[package.scala:45:36]
wire [2:0] newBPC_lo_lo_1 = 3'h0; // @[CSR.scala:1477:67]
wire [45:0] read_mapping_hi_hi_lo = 46'h40000000000; // @[CSR.scala:655:48]
wire [45:0] newBPC_hi_hi_lo = 46'h40000000000; // @[CSR.scala:1477:67]
wire [54:0] hi_lo_4 = 55'h0; // @[CSR.scala:742:49]
wire [54:0] hi_lo_6 = 55'h0; // @[CSR.scala:780:49]
wire [82:0] hi_7 = 83'h20000000800; // @[CSR.scala:768:51]
wire [64:0] hi_hi_5 = 65'h800000; // @[CSR.scala:768:51]
wire [27:0] hi_hi_lo_4 = 28'h800000; // @[CSR.scala:768:51]
wire [23:0] read_mstatus_hi_hi_lo_lo = 24'h800000; // @[CSR.scala:649:32]
wire [23:0] hi_hi_lo_lo = 24'h800000; // @[CSR.scala:768:51]
wire [3:0] _which_T_64 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_65 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_66 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_67 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_68 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_69 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_70 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_71 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_72 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_73 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_74 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_75 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_76 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_77 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] _which_T_78 = 4'h4; // @[Mux.scala:50:70]
wire [3:0] debug_csrs_hi_hi_hi = 4'h4; // @[CSR.scala:670:27]
wire [2:0] read_mstatus_hi_lo_hi_lo = 3'h2; // @[CSR.scala:649:32]
wire [47:0] io_bp_0_textra_pad2_0 = 48'h0; // @[CSR.scala:377:7]
wire [47:0] _reg_bp_1_WIRE_textra_pad2 = 48'h0; // @[CSR.scala:1613:23]
wire [38:0] _read_stvec_T_2 = 39'h0; // @[package.scala:174:46]
wire [38:0] _reg_bp_1_WIRE_address = 39'h0; // @[CSR.scala:1613:23]
wire [1:0] io_status_sxl = 2'h2; // @[CSR.scala:377:7]
wire [1:0] io_status_uxl = 2'h2; // @[CSR.scala:377:7]
wire [1:0] io_hstatus_vsxl = 2'h2; // @[CSR.scala:377:7]
wire [1:0] io_gstatus_uxl = 2'h2; // @[CSR.scala:377:7]
wire [1:0] lo_lo_lo = 2'h2; // @[CSR.scala:431:10]
wire [1:0] lo_lo_hi = 2'h2; // @[CSR.scala:431:10]
wire [1:0] lo_hi_lo = 2'h2; // @[CSR.scala:431:10]
wire [1:0] lo_hi_hi = 2'h2; // @[CSR.scala:431:10]
wire [1:0] hi_lo_lo = 2'h2; // @[CSR.scala:431:10]
wire [1:0] hi_lo_hi = 2'h2; // @[CSR.scala:431:10]
wire [1:0] hi_hi_lo = 2'h2; // @[CSR.scala:431:10]
wire [1:0] lo_lo_lo_1 = 2'h2; // @[CSR.scala:431:50]
wire [1:0] lo_hi_lo_1 = 2'h2; // @[CSR.scala:431:50]
wire [1:0] hi_lo_lo_1 = 2'h2; // @[CSR.scala:431:50]
wire [1:0] hi_hi_lo_1 = 2'h2; // @[CSR.scala:431:50]
wire [1:0] read_sstatus_uxl = 2'h2; // @[CSR.scala:755:35]
wire [63:0] _s_interrupts_T_7 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:621:168]
wire [63:0] _reg_custom_1_T_1 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1506:40]
wire [63:0] _reg_custom_2_T_1 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1506:40]
wire [63:0] _reg_custom_3_T_1 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1506:40]
wire [63:0] _reg_custom_1_T_5 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1531:41]
wire [63:0] _reg_custom_2_T_5 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1531:41]
wire [63:0] _reg_custom_3_T_5 = 64'hFFFFFFFFFFFFFFFF; // @[CSR.scala:1531:41]
wire [63:0] _reg_custom_0_T_1 = 64'hFFFFFFFFFFFFFDF7; // @[CSR.scala:1506:40]
wire [63:0] _reg_custom_0_T_5 = 64'hFFFFFFFFFFFFFDF7; // @[CSR.scala:1531:41]
wire [63:0] _reg_mcountinhibit_T = 64'hFFFFFFFFFFFFFFFD; // @[CSR.scala:1306:78]
wire [63:0] _reg_misa_T_6 = 64'hFFFFFFFFFFFFEFD2; // @[CSR.scala:1263:75]
wire [15:0] _en_T_78 = 16'h2000; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_13 = 16'h2000; // @[CSR.scala:1097:43]
wire [15:0] _delegable_T_28 = 16'h2000; // @[CSR.scala:1109:45]
wire [15:0] _sie_mask_T = 16'h1000; // @[CSR.scala:750:59]
wire [15:0] _sie_mask_T_1 = 16'h1000; // @[CSR.scala:750:46]
wire [15:0] _delegable_T_27 = 16'h1000; // @[CSR.scala:1109:45]
wire [15:0] _en_T_18 = 16'h8; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_19 = 16'h8; // @[CSR.scala:1109:45]
wire [63:0] _en_T_94 = 64'h800000000000000F; // @[CSR.scala:1096:120]
wire [63:0] _en_T_88 = 64'h800000000000000E; // @[CSR.scala:1096:120]
wire [63:0] _en_T_82 = 64'h800000000000000D; // @[CSR.scala:1096:120]
wire [63:0] _en_T_76 = 64'h800000000000000C; // @[CSR.scala:1096:120]
wire [63:0] _en_T_70 = 64'h800000000000000B; // @[CSR.scala:1096:120]
wire [15:0] _en_T_66 = 16'h800; // @[CSR.scala:1096:49]
wire [63:0] _en_T_64 = 64'h800000000000000A; // @[CSR.scala:1096:120]
wire [15:0] _en_T_54 = 16'h200; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_9 = 16'h200; // @[CSR.scala:1097:43]
wire [63:0] _en_T_58 = 64'h8000000000000009; // @[CSR.scala:1096:120]
wire [63:0] _en_T_52 = 64'h8000000000000008; // @[CSR.scala:1096:120]
wire [63:0] _en_T_46 = 64'h8000000000000007; // @[CSR.scala:1096:120]
wire [15:0] _en_T_42 = 16'h80; // @[CSR.scala:1096:49]
wire [63:0] _en_T_40 = 64'h8000000000000006; // @[CSR.scala:1096:120]
wire [15:0] _en_T_30 = 16'h20; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_5 = 16'h20; // @[CSR.scala:1097:43]
wire [63:0] _en_T_34 = 64'h8000000000000005; // @[CSR.scala:1096:120]
wire [63:0] _en_T_28 = 64'h8000000000000004; // @[CSR.scala:1096:120]
wire [63:0] _en_T_22 = 64'h8000000000000003; // @[CSR.scala:1096:120]
wire [63:0] _en_T_16 = 64'h8000000000000002; // @[CSR.scala:1096:120]
wire [15:0] _en_T_6 = 16'h2; // @[CSR.scala:1096:49]
wire [15:0] _delegable_T_1 = 16'h2; // @[CSR.scala:1097:43]
wire [63:0] _en_T_10 = 64'h8000000000000001; // @[CSR.scala:1096:120]
wire [63:0] _interruptCause_T_2 = 64'h8000000000000000; // @[CSR.scala:625:39]
wire [63:0] _en_T_4 = 64'h8000000000000000; // @[CSR.scala:1096:120]
wire [64:0] _interruptCause_T_1 = 65'h8000000000000000; // @[CSR.scala:625:39]
wire [64:0] _en_T_3 = 65'h8000000000000000; // @[CSR.scala:1096:120]
wire [9:0] _io_decode_0_write_flush_addr_m_T = 10'h300; // @[CSR.scala:932:36]
wire [31:0] io_gstatus_isa_0 = 32'h0; // @[CSR.scala:377:7]
wire [31:0] _reset_mstatus_WIRE_isa = 32'h0; // @[CSR.scala:391:47]
wire [31:0] reset_mstatus_isa = 32'h0; // @[CSR.scala:391:34]
wire [31:0] read_hcounteren = 32'h0; // @[CSR.scala:550:14]
wire [31:0] _read_mtvec_T_2 = 32'h0; // @[package.scala:174:46]
wire [31:0] _read_sstatus_WIRE_isa = 32'h0; // @[CSR.scala:755:48]
wire [31:0] read_sstatus_isa = 32'h0; // @[CSR.scala:755:35]
wire [31:0] read_pmp_15_mask = 32'h0; // @[CSR.scala:787:59]
wire [31:0] lo_24 = 32'h0; // @[package.scala:45:27]
wire [31:0] hi_27 = 32'h0; // @[package.scala:45:27]
wire [36:0] hi_hi_hi_4 = 37'h0; // @[CSR.scala:768:51]
wire [33:0] hi_hi_hi_lo = 34'h0; // @[CSR.scala:768:51]
wire [17:0] hi_lo_5 = 18'h800; // @[CSR.scala:768:51]
wire [11:0] hi_lo_lo_4 = 12'h800; // @[CSR.scala:768:51]
wire [2:0] _which_T_63 = 3'h4; // @[Mux.scala:50:70]
wire [2:0] read_mstatus_hi_lo_lo_hi = 3'h4; // @[CSR.scala:649:32]
wire [2:0] hi_lo_lo_hi = 3'h4; // @[CSR.scala:768:51]
wire [15:0] _sie_mask_T_2 = 16'hEFFF; // @[CSR.scala:750:20]
wire [7:0] sie_mask_hi = 8'h10; // @[CSR.scala:750:59]
wire [3:0] sie_mask_hi_hi = 4'h1; // @[CSR.scala:750:59]
wire [1:0] reset_dcsr_xdebugver = 2'h1; // @[CSR.scala:400:31]
wire [1:0] sie_mask_hi_hi_lo = 2'h1; // @[CSR.scala:750:59]
wire [53:0] _reg_menvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:525:41]
wire [53:0] _reg_senvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:526:41]
wire [53:0] _reg_henvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:527:41]
wire [15:0] delegable_interrupts = 16'h2222; // @[CSR.scala:431:50]
wire [7:0] lo_1 = 8'h22; // @[CSR.scala:431:50]
wire [7:0] hi_1 = 8'h22; // @[CSR.scala:431:50]
wire [15:0] supported_interrupts = 16'h2AAA; // @[CSR.scala:431:17]
wire [7:0] hi = 8'h2A; // @[CSR.scala:431:10]
wire [3:0] lo_lo = 4'hA; // @[CSR.scala:431:10]
wire [3:0] lo_hi = 4'hA; // @[CSR.scala:431:10]
wire [3:0] hi_lo = 4'hA; // @[CSR.scala:431:10]
wire [7:0] lo = 8'hAA; // @[CSR.scala:431:10]
wire [11:0] _reset_dcsr_WIRE_zero3 = 12'h0; // @[CSR.scala:400:44]
wire [11:0] reset_dcsr_zero3 = 12'h0; // @[CSR.scala:400:31]
wire [15:0] _delegable_T_24 = 16'h100; // @[CSR.scala:1109:45]
wire [15:0] _delegable_T_22 = 16'h40; // @[CSR.scala:1109:45]
wire [15:0] _delegable_T_20 = 16'h10; // @[CSR.scala:1109:45]
wire [15:0] _delegable_T_18 = 16'h4; // @[CSR.scala:1109:45]
wire [15:0] _delegable_T_16 = 16'h1; // @[CSR.scala:1109:45]
wire [64:0] _en_T_93 = 65'h800000000000000F; // @[CSR.scala:1096:120]
wire [64:0] _en_T_87 = 65'h800000000000000E; // @[CSR.scala:1096:120]
wire [64:0] _en_T_81 = 65'h800000000000000D; // @[CSR.scala:1096:120]
wire [64:0] _en_T_75 = 65'h800000000000000C; // @[CSR.scala:1096:120]
wire [64:0] _en_T_69 = 65'h800000000000000B; // @[CSR.scala:1096:120]
wire [64:0] _en_T_63 = 65'h800000000000000A; // @[CSR.scala:1096:120]
wire [64:0] _en_T_57 = 65'h8000000000000009; // @[CSR.scala:1096:120]
wire [64:0] _en_T_51 = 65'h8000000000000008; // @[CSR.scala:1096:120]
wire [64:0] _en_T_45 = 65'h8000000000000007; // @[CSR.scala:1096:120]
wire [64:0] _en_T_39 = 65'h8000000000000006; // @[CSR.scala:1096:120]
wire [64:0] _en_T_33 = 65'h8000000000000005; // @[CSR.scala:1096:120]
wire [64:0] _en_T_27 = 65'h8000000000000004; // @[CSR.scala:1096:120]
wire [64:0] _en_T_21 = 65'h8000000000000003; // @[CSR.scala:1096:120]
wire [64:0] _en_T_15 = 65'h8000000000000002; // @[CSR.scala:1096:120]
wire [64:0] _en_T_9 = 65'h8000000000000001; // @[CSR.scala:1096:120]
wire [62:0] _interruptCause_T = 63'h0; // @[CSR.scala:625:50]
wire [15:0] _delegable_T_29 = 16'h8000; // @[CSR.scala:1109:45]
wire [39:0] _io_evec_T_15 = 40'hFFFFFFFFFF; // @[CSR.scala:1665:28]
wire [48:0] read_mapping_hi_1 = 49'h0; // @[CSR.scala:657:47]
wire mip_mtip = io_interrupts_mtip_0; // @[CSR.scala:377:7, :600:24]
wire mip_msip = io_interrupts_msip_0; // @[CSR.scala:377:7, :600:24]
wire mip_meip = io_interrupts_meip_0; // @[CSR.scala:377:7, :600:24]
wire [63:0] _io_rw_rdata_WIRE; // @[Mux.scala:30:73]
wire [63:0] _newBPC_T_27 = io_rw_wdata_0; // @[CSR.scala:377:7, :1643:30]
wire [31:0] decoded_plaInput_1 = io_decode_0_inst_0; // @[pla.scala:77:22]
wire _io_decode_0_fp_illegal_T_6; // @[CSR.scala:915:91]
wire _io_decode_0_fp_csr_T; // @[Decode.scala:55:116]
wire _io_decode_0_rocc_illegal_T_6; // @[CSR.scala:919:93]
wire _io_decode_0_read_illegal_T_20; // @[CSR.scala:928:68]
wire _io_decode_0_write_illegal_T_1; // @[CSR.scala:930:41]
wire _io_decode_0_write_flush_T_3; // @[CSR.scala:933:7]
wire _io_decode_0_system_illegal_T_25; // @[CSR.scala:940:44]
wire _io_decode_0_virtual_access_illegal_T_29; // @[CSR.scala:943:66]
wire _io_decode_0_virtual_system_illegal_T_22; // @[CSR.scala:949:52]
wire _io_csr_stall_T; // @[CSR.scala:1161:27]
wire _io_eret_T_1; // @[CSR.scala:1000:38]
wire _io_singleStep_T_1; // @[CSR.scala:1001:34]
wire [1:0] _io_status_dprv_T_2; // @[CSR.scala:1008:24]
wire _io_status_dv_T_3; // @[CSR.scala:1009:33]
wire read_sstatus_mxr = io_status_mxr_0; // @[CSR.scala:377:7, :755:35]
wire read_sstatus_sum = io_status_sum_0; // @[CSR.scala:377:7, :755:35]
wire [1:0] read_sstatus_fs = io_status_fs_0; // @[CSR.scala:377:7, :755:35]
wire read_sstatus_spp = io_status_spp_0; // @[CSR.scala:377:7, :755:35]
wire read_sstatus_spie = io_status_spie_0; // @[CSR.scala:377:7, :755:35]
wire read_sstatus_sie = io_status_sie_0; // @[CSR.scala:377:7, :755:35]
wire _io_trace_0_valid_T = io_retire_0; // @[CSR.scala:377:7, :1621:26]
wire [39:0] io_trace_0_iaddr_0 = io_pc_0; // @[CSR.scala:377:7]
wire [39:0] io_trace_0_tval_0 = io_tval_0; // @[CSR.scala:377:7]
wire [63:0] value_1; // @[Counters.scala:55:30]
wire mip_rocc = io_rocc_interrupt_0; // @[CSR.scala:377:7, :600:24]
wire _io_interrupt_T_5; // @[CSR.scala:626:73]
wire [63:0] interruptCause; // @[CSR.scala:625:63]
wire pmp_cfg_l; // @[PMP.scala:24:19]
wire [1:0] pmp_cfg_a; // @[PMP.scala:24:19]
wire pmp_cfg_x; // @[PMP.scala:24:19]
wire pmp_cfg_w; // @[PMP.scala:24:19]
wire pmp_cfg_r; // @[PMP.scala:24:19]
wire [29:0] pmp_addr; // @[PMP.scala:24:19]
wire [31:0] pmp_mask; // @[PMP.scala:24:19]
wire pmp_1_cfg_l; // @[PMP.scala:24:19]
wire [1:0] pmp_1_cfg_a; // @[PMP.scala:24:19]
wire pmp_1_cfg_x; // @[PMP.scala:24:19]
wire pmp_1_cfg_w; // @[PMP.scala:24:19]
wire pmp_1_cfg_r; // @[PMP.scala:24:19]
wire [29:0] pmp_1_addr; // @[PMP.scala:24:19]
wire [31:0] pmp_1_mask; // @[PMP.scala:24:19]
wire pmp_2_cfg_l; // @[PMP.scala:24:19]
wire [1:0] pmp_2_cfg_a; // @[PMP.scala:24:19]
wire pmp_2_cfg_x; // @[PMP.scala:24:19]
wire pmp_2_cfg_w; // @[PMP.scala:24:19]
wire pmp_2_cfg_r; // @[PMP.scala:24:19]
wire [29:0] pmp_2_addr; // @[PMP.scala:24:19]
wire [31:0] pmp_2_mask; // @[PMP.scala:24:19]
wire pmp_3_cfg_l; // @[PMP.scala:24:19]
wire [1:0] pmp_3_cfg_a; // @[PMP.scala:24:19]
wire pmp_3_cfg_x; // @[PMP.scala:24:19]
wire pmp_3_cfg_w; // @[PMP.scala:24:19]
wire pmp_3_cfg_r; // @[PMP.scala:24:19]
wire [29:0] pmp_3_addr; // @[PMP.scala:24:19]
wire [31:0] pmp_3_mask; // @[PMP.scala:24:19]
wire pmp_4_cfg_l; // @[PMP.scala:24:19]
wire [1:0] pmp_4_cfg_a; // @[PMP.scala:24:19]
wire pmp_4_cfg_x; // @[PMP.scala:24:19]
wire pmp_4_cfg_w; // @[PMP.scala:24:19]
wire pmp_4_cfg_r; // @[PMP.scala:24:19]
wire [29:0] pmp_4_addr; // @[PMP.scala:24:19]
wire [31:0] pmp_4_mask; // @[PMP.scala:24:19]
wire pmp_5_cfg_l; // @[PMP.scala:24:19]
wire [1:0] pmp_5_cfg_a; // @[PMP.scala:24:19]
wire pmp_5_cfg_x; // @[PMP.scala:24:19]
wire pmp_5_cfg_w; // @[PMP.scala:24:19]
wire pmp_5_cfg_r; // @[PMP.scala:24:19]
wire [29:0] pmp_5_addr; // @[PMP.scala:24:19]
wire [31:0] pmp_5_mask; // @[PMP.scala:24:19]
wire pmp_6_cfg_l; // @[PMP.scala:24:19]
wire [1:0] pmp_6_cfg_a; // @[PMP.scala:24:19]
wire pmp_6_cfg_x; // @[PMP.scala:24:19]
wire pmp_6_cfg_w; // @[PMP.scala:24:19]
wire pmp_6_cfg_r; // @[PMP.scala:24:19]
wire [29:0] pmp_6_addr; // @[PMP.scala:24:19]
wire [31:0] pmp_6_mask; // @[PMP.scala:24:19]
wire pmp_7_cfg_l; // @[PMP.scala:24:19]
wire [1:0] pmp_7_cfg_a; // @[PMP.scala:24:19]
wire pmp_7_cfg_x; // @[PMP.scala:24:19]
wire pmp_7_cfg_w; // @[PMP.scala:24:19]
wire pmp_7_cfg_r; // @[PMP.scala:24:19]
wire [29:0] pmp_7_addr; // @[PMP.scala:24:19]
wire [31:0] pmp_7_mask; // @[PMP.scala:24:19]
wire [31:0] _io_csrw_counter_T_11; // @[CSR.scala:1223:25]
wire _io_inhibit_cycle_T; // @[CSR.scala:591:40]
wire [31:0] io_trace_0_insn_0 = io_inst_0_0; // @[CSR.scala:377:7]
wire _io_trace_0_valid_T_1; // @[CSR.scala:1621:32]
wire [2:0] _io_trace_0_priv_T; // @[CSR.scala:1624:18]
wire _io_trace_0_exception_T_1; // @[CSR.scala:1620:37]
wire _io_trace_0_interrupt_T; // @[CSR.scala:1626:25]
wire [63:0] cause; // @[CSR.scala:959:8]
wire _io_fiom_T_6; // @[CSR.scala:631:113]
wire reg_custom_read; // @[CSR.scala:799:36]
wire [63:0] wdata; // @[CSR.scala:1643:39]
wire reg_custom_read_1; // @[CSR.scala:799:36]
wire reg_custom_read_2; // @[CSR.scala:799:36]
wire reg_custom_read_3; // @[CSR.scala:799:36]
wire [63:0] io_rw_rdata_0; // @[CSR.scala:377:7]
wire io_decode_0_fp_illegal_0; // @[CSR.scala:377:7]
wire io_decode_0_fp_csr_0; // @[CSR.scala:377:7]
wire io_decode_0_rocc_illegal_0; // @[CSR.scala:377:7]
wire io_decode_0_read_illegal_0; // @[CSR.scala:377:7]
wire io_decode_0_write_illegal_0; // @[CSR.scala:377:7]
wire io_decode_0_write_flush_0; // @[CSR.scala:377:7]
wire io_decode_0_system_illegal_0; // @[CSR.scala:377:7]
wire io_decode_0_virtual_access_illegal_0; // @[CSR.scala:377:7]
wire io_decode_0_virtual_system_illegal_0; // @[CSR.scala:377:7]
wire io_status_debug_0; // @[CSR.scala:377:7]
wire io_status_cease_0; // @[CSR.scala:377:7]
wire io_status_wfi_0; // @[CSR.scala:377:7]
wire [31:0] io_status_isa_0; // @[CSR.scala:377:7]
wire [1:0] io_status_dprv_0; // @[CSR.scala:377:7]
wire io_status_dv_0; // @[CSR.scala:377:7]
wire [1:0] io_status_prv_0; // @[CSR.scala:377:7]
wire io_status_v_0; // @[CSR.scala:377:7]
wire io_status_mpv_0; // @[CSR.scala:377:7]
wire io_status_gva_0; // @[CSR.scala:377:7]
wire io_status_tsr_0; // @[CSR.scala:377:7]
wire io_status_tw_0; // @[CSR.scala:377:7]
wire io_status_tvm_0; // @[CSR.scala:377:7]
wire io_status_mprv_0; // @[CSR.scala:377:7]
wire [1:0] io_status_mpp_0; // @[CSR.scala:377:7]
wire io_status_mpie_0; // @[CSR.scala:377:7]
wire io_status_mie_0; // @[CSR.scala:377:7]
wire io_hstatus_spvp_0; // @[CSR.scala:377:7]
wire io_hstatus_spv_0; // @[CSR.scala:377:7]
wire io_hstatus_gva_0; // @[CSR.scala:377:7]
wire io_gstatus_spp_0; // @[CSR.scala:377:7]
wire io_gstatus_spie_0; // @[CSR.scala:377:7]
wire io_gstatus_sie_0; // @[CSR.scala:377:7]
wire [3:0] io_ptbr_mode_0; // @[CSR.scala:377:7]
wire [43:0] io_ptbr_ppn_0; // @[CSR.scala:377:7]
wire io_bp_0_control_dmode_0; // @[CSR.scala:377:7]
wire io_bp_0_control_action_0; // @[CSR.scala:377:7]
wire [1:0] io_bp_0_control_tmatch_0; // @[CSR.scala:377:7]
wire io_bp_0_control_m_0; // @[CSR.scala:377:7]
wire io_bp_0_control_s_0; // @[CSR.scala:377:7]
wire io_bp_0_control_u_0; // @[CSR.scala:377:7]
wire io_bp_0_control_x_0; // @[CSR.scala:377:7]
wire io_bp_0_control_w_0; // @[CSR.scala:377:7]
wire io_bp_0_control_r_0; // @[CSR.scala:377:7]
wire [38:0] io_bp_0_address_0; // @[CSR.scala:377:7]
wire io_pmp_0_cfg_l_0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_0_cfg_a_0; // @[CSR.scala:377:7]
wire io_pmp_0_cfg_x_0; // @[CSR.scala:377:7]
wire io_pmp_0_cfg_w_0; // @[CSR.scala:377:7]
wire io_pmp_0_cfg_r_0; // @[CSR.scala:377:7]
wire [29:0] io_pmp_0_addr_0; // @[CSR.scala:377:7]
wire [31:0] io_pmp_0_mask_0; // @[CSR.scala:377:7]
wire io_pmp_1_cfg_l_0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_1_cfg_a_0; // @[CSR.scala:377:7]
wire io_pmp_1_cfg_x_0; // @[CSR.scala:377:7]
wire io_pmp_1_cfg_w_0; // @[CSR.scala:377:7]
wire io_pmp_1_cfg_r_0; // @[CSR.scala:377:7]
wire [29:0] io_pmp_1_addr_0; // @[CSR.scala:377:7]
wire [31:0] io_pmp_1_mask_0; // @[CSR.scala:377:7]
wire io_pmp_2_cfg_l_0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_2_cfg_a_0; // @[CSR.scala:377:7]
wire io_pmp_2_cfg_x_0; // @[CSR.scala:377:7]
wire io_pmp_2_cfg_w_0; // @[CSR.scala:377:7]
wire io_pmp_2_cfg_r_0; // @[CSR.scala:377:7]
wire [29:0] io_pmp_2_addr_0; // @[CSR.scala:377:7]
wire [31:0] io_pmp_2_mask_0; // @[CSR.scala:377:7]
wire io_pmp_3_cfg_l_0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_3_cfg_a_0; // @[CSR.scala:377:7]
wire io_pmp_3_cfg_x_0; // @[CSR.scala:377:7]
wire io_pmp_3_cfg_w_0; // @[CSR.scala:377:7]
wire io_pmp_3_cfg_r_0; // @[CSR.scala:377:7]
wire [29:0] io_pmp_3_addr_0; // @[CSR.scala:377:7]
wire [31:0] io_pmp_3_mask_0; // @[CSR.scala:377:7]
wire io_pmp_4_cfg_l_0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_4_cfg_a_0; // @[CSR.scala:377:7]
wire io_pmp_4_cfg_x_0; // @[CSR.scala:377:7]
wire io_pmp_4_cfg_w_0; // @[CSR.scala:377:7]
wire io_pmp_4_cfg_r_0; // @[CSR.scala:377:7]
wire [29:0] io_pmp_4_addr_0; // @[CSR.scala:377:7]
wire [31:0] io_pmp_4_mask_0; // @[CSR.scala:377:7]
wire io_pmp_5_cfg_l_0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_5_cfg_a_0; // @[CSR.scala:377:7]
wire io_pmp_5_cfg_x_0; // @[CSR.scala:377:7]
wire io_pmp_5_cfg_w_0; // @[CSR.scala:377:7]
wire io_pmp_5_cfg_r_0; // @[CSR.scala:377:7]
wire [29:0] io_pmp_5_addr_0; // @[CSR.scala:377:7]
wire [31:0] io_pmp_5_mask_0; // @[CSR.scala:377:7]
wire io_pmp_6_cfg_l_0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_6_cfg_a_0; // @[CSR.scala:377:7]
wire io_pmp_6_cfg_x_0; // @[CSR.scala:377:7]
wire io_pmp_6_cfg_w_0; // @[CSR.scala:377:7]
wire io_pmp_6_cfg_r_0; // @[CSR.scala:377:7]
wire [29:0] io_pmp_6_addr_0; // @[CSR.scala:377:7]
wire [31:0] io_pmp_6_mask_0; // @[CSR.scala:377:7]
wire io_pmp_7_cfg_l_0; // @[CSR.scala:377:7]
wire [1:0] io_pmp_7_cfg_a_0; // @[CSR.scala:377:7]
wire io_pmp_7_cfg_x_0; // @[CSR.scala:377:7]
wire io_pmp_7_cfg_w_0; // @[CSR.scala:377:7]
wire io_pmp_7_cfg_r_0; // @[CSR.scala:377:7]
wire [29:0] io_pmp_7_addr_0; // @[CSR.scala:377:7]
wire [31:0] io_pmp_7_mask_0; // @[CSR.scala:377:7]
wire io_trace_0_valid_0; // @[CSR.scala:377:7]
wire [2:0] io_trace_0_priv_0; // @[CSR.scala:377:7]
wire io_trace_0_exception_0; // @[CSR.scala:377:7]
wire io_trace_0_interrupt_0; // @[CSR.scala:377:7]
wire [63:0] io_trace_0_cause_0; // @[CSR.scala:377:7]
wire io_customCSRs_0_ren_0; // @[CSR.scala:377:7]
wire io_customCSRs_0_wen_0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_0_wdata_0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_0_value_0; // @[CSR.scala:377:7]
wire io_customCSRs_1_ren_0; // @[CSR.scala:377:7]
wire io_customCSRs_1_wen_0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_1_wdata_0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_1_value_0; // @[CSR.scala:377:7]
wire io_customCSRs_2_ren_0; // @[CSR.scala:377:7]
wire io_customCSRs_2_wen_0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_2_wdata_0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_2_value_0; // @[CSR.scala:377:7]
wire io_customCSRs_3_ren_0; // @[CSR.scala:377:7]
wire io_customCSRs_3_wen_0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_3_wdata_0; // @[CSR.scala:377:7]
wire [63:0] io_customCSRs_3_value_0; // @[CSR.scala:377:7]
wire io_csr_stall_0; // @[CSR.scala:377:7]
wire io_eret_0; // @[CSR.scala:377:7]
wire io_singleStep_0; // @[CSR.scala:377:7]
wire [39:0] io_evec_0; // @[CSR.scala:377:7]
wire [63:0] io_time_0; // @[CSR.scala:377:7]
wire [2:0] io_fcsr_rm_0; // @[CSR.scala:377:7]
wire io_interrupt_0; // @[CSR.scala:377:7]
wire [63:0] io_interrupt_cause_0; // @[CSR.scala:377:7]
wire [31:0] io_csrw_counter; // @[CSR.scala:377:7]
wire io_inhibit_cycle_0; // @[CSR.scala:377:7]
wire io_fiom; // @[CSR.scala:377:7]
reg [1:0] reg_mstatus_prv; // @[CSR.scala:395:28]
assign io_status_prv_0 = reg_mstatus_prv; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_v; // @[CSR.scala:395:28]
assign io_status_v_0 = reg_mstatus_v; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_mpv; // @[CSR.scala:395:28]
assign io_status_mpv_0 = reg_mstatus_mpv; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_gva; // @[CSR.scala:395:28]
assign io_status_gva_0 = reg_mstatus_gva; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_tsr; // @[CSR.scala:395:28]
assign io_status_tsr_0 = reg_mstatus_tsr; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_tw; // @[CSR.scala:395:28]
assign io_status_tw_0 = reg_mstatus_tw; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_tvm; // @[CSR.scala:395:28]
assign io_status_tvm_0 = reg_mstatus_tvm; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_mxr; // @[CSR.scala:395:28]
assign io_status_mxr_0 = reg_mstatus_mxr; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_sum; // @[CSR.scala:395:28]
assign io_status_sum_0 = reg_mstatus_sum; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_mprv; // @[CSR.scala:395:28]
assign io_status_mprv_0 = reg_mstatus_mprv; // @[CSR.scala:377:7, :395:28]
reg [1:0] reg_mstatus_fs; // @[CSR.scala:395:28]
assign io_status_fs_0 = reg_mstatus_fs; // @[CSR.scala:377:7, :395:28]
reg [1:0] reg_mstatus_mpp; // @[CSR.scala:395:28]
assign io_status_mpp_0 = reg_mstatus_mpp; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_spp; // @[CSR.scala:395:28]
assign io_status_spp_0 = reg_mstatus_spp; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_mpie; // @[CSR.scala:395:28]
assign io_status_mpie_0 = reg_mstatus_mpie; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_spie; // @[CSR.scala:395:28]
assign io_status_spie_0 = reg_mstatus_spie; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_mie; // @[CSR.scala:395:28]
assign io_status_mie_0 = reg_mstatus_mie; // @[CSR.scala:377:7, :395:28]
reg reg_mstatus_sie; // @[CSR.scala:395:28]
assign io_status_sie_0 = reg_mstatus_sie; // @[CSR.scala:377:7, :395:28]
wire [1:0] new_prv; // @[CSR.scala:397:28]
wire _reg_mstatus_prv_T = new_prv == 2'h2; // @[CSR.scala:397:28, :1647:35]
wire [1:0] _reg_mstatus_prv_T_1 = _reg_mstatus_prv_T ? 2'h0 : new_prv; // @[CSR.scala:397:28, :1647:{29,35}]
reg reg_dcsr_ebreakm; // @[CSR.scala:403:25]
reg reg_dcsr_ebreaks; // @[CSR.scala:403:25]
reg reg_dcsr_ebreaku; // @[CSR.scala:403:25]
reg [2:0] reg_dcsr_cause; // @[CSR.scala:403:25]
reg reg_dcsr_v; // @[CSR.scala:403:25]
reg reg_dcsr_step; // @[CSR.scala:403:25]
reg [1:0] reg_dcsr_prv; // @[CSR.scala:403:25]
reg reg_debug; // @[CSR.scala:482:26]
assign io_status_debug_0 = reg_debug; // @[CSR.scala:377:7, :482:26]
reg [39:0] reg_dpc; // @[CSR.scala:483:20]
reg [63:0] reg_dscratch0; // @[CSR.scala:484:26]
reg reg_singleStepped; // @[CSR.scala:486:30]
reg reg_bp_0_control_dmode; // @[CSR.scala:492:19]
assign io_bp_0_control_dmode_0 = reg_bp_0_control_dmode; // @[CSR.scala:377:7, :492:19]
reg reg_bp_0_control_action; // @[CSR.scala:492:19]
assign io_bp_0_control_action_0 = reg_bp_0_control_action; // @[CSR.scala:377:7, :492:19]
reg [1:0] reg_bp_0_control_tmatch; // @[CSR.scala:492:19]
assign io_bp_0_control_tmatch_0 = reg_bp_0_control_tmatch; // @[CSR.scala:377:7, :492:19]
reg reg_bp_0_control_m; // @[CSR.scala:492:19]
assign io_bp_0_control_m_0 = reg_bp_0_control_m; // @[CSR.scala:377:7, :492:19]
reg reg_bp_0_control_s; // @[CSR.scala:492:19]
assign io_bp_0_control_s_0 = reg_bp_0_control_s; // @[CSR.scala:377:7, :492:19]
reg reg_bp_0_control_u; // @[CSR.scala:492:19]
assign io_bp_0_control_u_0 = reg_bp_0_control_u; // @[CSR.scala:377:7, :492:19]
reg reg_bp_0_control_x; // @[CSR.scala:492:19]
assign io_bp_0_control_x_0 = reg_bp_0_control_x; // @[CSR.scala:377:7, :492:19]
reg reg_bp_0_control_w; // @[CSR.scala:492:19]
assign io_bp_0_control_w_0 = reg_bp_0_control_w; // @[CSR.scala:377:7, :492:19]
reg reg_bp_0_control_r; // @[CSR.scala:492:19]
assign io_bp_0_control_r_0 = reg_bp_0_control_r; // @[CSR.scala:377:7, :492:19]
reg [38:0] reg_bp_0_address; // @[CSR.scala:492:19]
assign io_bp_0_address_0 = reg_bp_0_address; // @[CSR.scala:377:7, :492:19]
reg reg_pmp_0_cfg_l; // @[CSR.scala:493:20]
assign pmp_cfg_l = reg_pmp_0_cfg_l; // @[PMP.scala:24:19]
reg [1:0] reg_pmp_0_cfg_a; // @[CSR.scala:493:20]
assign pmp_cfg_a = reg_pmp_0_cfg_a; // @[PMP.scala:24:19]
reg reg_pmp_0_cfg_x; // @[CSR.scala:493:20]
assign pmp_cfg_x = reg_pmp_0_cfg_x; // @[PMP.scala:24:19]
reg reg_pmp_0_cfg_w; // @[CSR.scala:493:20]
assign pmp_cfg_w = reg_pmp_0_cfg_w; // @[PMP.scala:24:19]
reg reg_pmp_0_cfg_r; // @[CSR.scala:493:20]
assign pmp_cfg_r = reg_pmp_0_cfg_r; // @[PMP.scala:24:19]
reg [29:0] reg_pmp_0_addr; // @[CSR.scala:493:20]
assign pmp_addr = reg_pmp_0_addr; // @[PMP.scala:24:19]
reg reg_pmp_1_cfg_l; // @[CSR.scala:493:20]
assign pmp_1_cfg_l = reg_pmp_1_cfg_l; // @[PMP.scala:24:19]
reg [1:0] reg_pmp_1_cfg_a; // @[CSR.scala:493:20]
assign pmp_1_cfg_a = reg_pmp_1_cfg_a; // @[PMP.scala:24:19]
reg reg_pmp_1_cfg_x; // @[CSR.scala:493:20]
assign pmp_1_cfg_x = reg_pmp_1_cfg_x; // @[PMP.scala:24:19]
reg reg_pmp_1_cfg_w; // @[CSR.scala:493:20]
assign pmp_1_cfg_w = reg_pmp_1_cfg_w; // @[PMP.scala:24:19]
reg reg_pmp_1_cfg_r; // @[CSR.scala:493:20]
assign pmp_1_cfg_r = reg_pmp_1_cfg_r; // @[PMP.scala:24:19]
reg [29:0] reg_pmp_1_addr; // @[CSR.scala:493:20]
assign pmp_1_addr = reg_pmp_1_addr; // @[PMP.scala:24:19]
reg reg_pmp_2_cfg_l; // @[CSR.scala:493:20]
assign pmp_2_cfg_l = reg_pmp_2_cfg_l; // @[PMP.scala:24:19]
reg [1:0] reg_pmp_2_cfg_a; // @[CSR.scala:493:20]
assign pmp_2_cfg_a = reg_pmp_2_cfg_a; // @[PMP.scala:24:19]
reg reg_pmp_2_cfg_x; // @[CSR.scala:493:20]
assign pmp_2_cfg_x = reg_pmp_2_cfg_x; // @[PMP.scala:24:19]
reg reg_pmp_2_cfg_w; // @[CSR.scala:493:20]
assign pmp_2_cfg_w = reg_pmp_2_cfg_w; // @[PMP.scala:24:19]
reg reg_pmp_2_cfg_r; // @[CSR.scala:493:20]
assign pmp_2_cfg_r = reg_pmp_2_cfg_r; // @[PMP.scala:24:19]
reg [29:0] reg_pmp_2_addr; // @[CSR.scala:493:20]
assign pmp_2_addr = reg_pmp_2_addr; // @[PMP.scala:24:19]
reg reg_pmp_3_cfg_l; // @[CSR.scala:493:20]
assign pmp_3_cfg_l = reg_pmp_3_cfg_l; // @[PMP.scala:24:19]
reg [1:0] reg_pmp_3_cfg_a; // @[CSR.scala:493:20]
assign pmp_3_cfg_a = reg_pmp_3_cfg_a; // @[PMP.scala:24:19]
reg reg_pmp_3_cfg_x; // @[CSR.scala:493:20]
assign pmp_3_cfg_x = reg_pmp_3_cfg_x; // @[PMP.scala:24:19]
reg reg_pmp_3_cfg_w; // @[CSR.scala:493:20]
assign pmp_3_cfg_w = reg_pmp_3_cfg_w; // @[PMP.scala:24:19]
reg reg_pmp_3_cfg_r; // @[CSR.scala:493:20]
assign pmp_3_cfg_r = reg_pmp_3_cfg_r; // @[PMP.scala:24:19]
reg [29:0] reg_pmp_3_addr; // @[CSR.scala:493:20]
assign pmp_3_addr = reg_pmp_3_addr; // @[PMP.scala:24:19]
reg reg_pmp_4_cfg_l; // @[CSR.scala:493:20]
assign pmp_4_cfg_l = reg_pmp_4_cfg_l; // @[PMP.scala:24:19]
reg [1:0] reg_pmp_4_cfg_a; // @[CSR.scala:493:20]
assign pmp_4_cfg_a = reg_pmp_4_cfg_a; // @[PMP.scala:24:19]
reg reg_pmp_4_cfg_x; // @[CSR.scala:493:20]
assign pmp_4_cfg_x = reg_pmp_4_cfg_x; // @[PMP.scala:24:19]
reg reg_pmp_4_cfg_w; // @[CSR.scala:493:20]
assign pmp_4_cfg_w = reg_pmp_4_cfg_w; // @[PMP.scala:24:19]
reg reg_pmp_4_cfg_r; // @[CSR.scala:493:20]
assign pmp_4_cfg_r = reg_pmp_4_cfg_r; // @[PMP.scala:24:19]
reg [29:0] reg_pmp_4_addr; // @[CSR.scala:493:20]
assign pmp_4_addr = reg_pmp_4_addr; // @[PMP.scala:24:19]
reg reg_pmp_5_cfg_l; // @[CSR.scala:493:20]
assign pmp_5_cfg_l = reg_pmp_5_cfg_l; // @[PMP.scala:24:19]
reg [1:0] reg_pmp_5_cfg_a; // @[CSR.scala:493:20]
assign pmp_5_cfg_a = reg_pmp_5_cfg_a; // @[PMP.scala:24:19]
reg reg_pmp_5_cfg_x; // @[CSR.scala:493:20]
assign pmp_5_cfg_x = reg_pmp_5_cfg_x; // @[PMP.scala:24:19]
reg reg_pmp_5_cfg_w; // @[CSR.scala:493:20]
assign pmp_5_cfg_w = reg_pmp_5_cfg_w; // @[PMP.scala:24:19]
reg reg_pmp_5_cfg_r; // @[CSR.scala:493:20]
assign pmp_5_cfg_r = reg_pmp_5_cfg_r; // @[PMP.scala:24:19]
reg [29:0] reg_pmp_5_addr; // @[CSR.scala:493:20]
assign pmp_5_addr = reg_pmp_5_addr; // @[PMP.scala:24:19]
reg reg_pmp_6_cfg_l; // @[CSR.scala:493:20]
assign pmp_6_cfg_l = reg_pmp_6_cfg_l; // @[PMP.scala:24:19]
reg [1:0] reg_pmp_6_cfg_a; // @[CSR.scala:493:20]
assign pmp_6_cfg_a = reg_pmp_6_cfg_a; // @[PMP.scala:24:19]
reg reg_pmp_6_cfg_x; // @[CSR.scala:493:20]
assign pmp_6_cfg_x = reg_pmp_6_cfg_x; // @[PMP.scala:24:19]
reg reg_pmp_6_cfg_w; // @[CSR.scala:493:20]
assign pmp_6_cfg_w = reg_pmp_6_cfg_w; // @[PMP.scala:24:19]
reg reg_pmp_6_cfg_r; // @[CSR.scala:493:20]
assign pmp_6_cfg_r = reg_pmp_6_cfg_r; // @[PMP.scala:24:19]
reg [29:0] reg_pmp_6_addr; // @[CSR.scala:493:20]
assign pmp_6_addr = reg_pmp_6_addr; // @[PMP.scala:24:19]
reg reg_pmp_7_cfg_l; // @[CSR.scala:493:20]
assign pmp_7_cfg_l = reg_pmp_7_cfg_l; // @[PMP.scala:24:19]
reg [1:0] reg_pmp_7_cfg_a; // @[CSR.scala:493:20]
assign pmp_7_cfg_a = reg_pmp_7_cfg_a; // @[PMP.scala:24:19]
reg reg_pmp_7_cfg_x; // @[CSR.scala:493:20]
assign pmp_7_cfg_x = reg_pmp_7_cfg_x; // @[PMP.scala:24:19]
reg reg_pmp_7_cfg_w; // @[CSR.scala:493:20]
assign pmp_7_cfg_w = reg_pmp_7_cfg_w; // @[PMP.scala:24:19]
reg reg_pmp_7_cfg_r; // @[CSR.scala:493:20]
assign pmp_7_cfg_r = reg_pmp_7_cfg_r; // @[PMP.scala:24:19]
reg [29:0] reg_pmp_7_addr; // @[CSR.scala:493:20]
assign pmp_7_addr = reg_pmp_7_addr; // @[PMP.scala:24:19]
reg [63:0] reg_mie; // @[CSR.scala:495:20]
reg [63:0] reg_mideleg; // @[CSR.scala:497:18]
wire [63:0] read_mideleg = {50'h0, reg_mideleg[13:1] & 13'h1111, 1'h0}; // @[CSR.scala:497:18, :498:{14,38,61}]
reg [63:0] reg_medeleg; // @[CSR.scala:501:18]
wire [63:0] read_medeleg = {48'h0, reg_medeleg[15:0] & 16'hB15D}; // @[CSR.scala:501:18, :502:{14,38}]
reg reg_mip_seip; // @[CSR.scala:504:20]
reg reg_mip_stip; // @[CSR.scala:504:20]
wire mip_stip = reg_mip_stip; // @[CSR.scala:504:20, :600:24]
reg reg_mip_ssip; // @[CSR.scala:504:20]
wire mip_ssip = reg_mip_ssip; // @[CSR.scala:504:20, :600:24]
reg [39:0] reg_mepc; // @[CSR.scala:505:21]
reg [63:0] reg_mcause; // @[CSR.scala:506:27]
reg [39:0] reg_mtval; // @[CSR.scala:507:22]
reg [39:0] reg_mtval2; // @[CSR.scala:508:23]
reg [63:0] reg_mscratch; // @[CSR.scala:509:25]
reg [31:0] reg_mtvec; // @[CSR.scala:512:31]
reg reg_menvcfg_fiom; // @[CSR.scala:525:28]
reg reg_senvcfg_fiom; // @[CSR.scala:526:28]
reg [31:0] reg_mcounteren; // @[CSR.scala:531:18]
wire [31:0] read_mcounteren = {29'h0, reg_mcounteren[2:0]}; // @[CSR.scala:531:18, :532:{14,32}]
reg [31:0] reg_scounteren; // @[CSR.scala:535:18]
wire [31:0] read_scounteren = {29'h0, reg_scounteren[2:0]}; // @[CSR.scala:535:18, :536:{14,38}]
reg reg_hstatus_spvp; // @[CSR.scala:552:28]
assign io_hstatus_spvp_0 = reg_hstatus_spvp; // @[CSR.scala:377:7, :552:28]
reg reg_hstatus_spv; // @[CSR.scala:552:28]
assign io_hstatus_spv_0 = reg_hstatus_spv; // @[CSR.scala:377:7, :552:28]
reg reg_hstatus_gva; // @[CSR.scala:552:28]
assign io_hstatus_gva_0 = reg_hstatus_gva; // @[CSR.scala:377:7, :552:28]
reg [39:0] reg_htval; // @[CSR.scala:554:22]
wire [1:0] _GEN = {reg_mip_ssip, 1'h0}; // @[CSR.scala:504:20, :555:27]
wire [1:0] read_hvip_lo_lo_lo; // @[CSR.scala:555:27]
assign read_hvip_lo_lo_lo = _GEN; // @[CSR.scala:555:27]
wire [1:0] new_mip_lo_lo_lo; // @[CSR.scala:1271:59]
assign new_mip_lo_lo_lo = _GEN; // @[CSR.scala:555:27, :1271:59]
wire [3:0] read_hvip_lo_lo = {read_hvip_lo_lo_hi, read_hvip_lo_lo_lo}; // @[CSR.scala:555:27]
wire [1:0] _GEN_0 = {reg_mip_stip, 1'h0}; // @[CSR.scala:504:20, :555:27]
wire [1:0] read_hvip_lo_hi_lo; // @[CSR.scala:555:27]
assign read_hvip_lo_hi_lo = _GEN_0; // @[CSR.scala:555:27]
wire [1:0] new_mip_lo_hi_lo; // @[CSR.scala:1271:59]
assign new_mip_lo_hi_lo = _GEN_0; // @[CSR.scala:555:27, :1271:59]
wire [3:0] read_hvip_lo_hi = {read_hvip_lo_hi_hi, read_hvip_lo_hi_lo}; // @[CSR.scala:555:27]
wire [7:0] read_hvip_lo = {read_hvip_lo_hi, read_hvip_lo_lo}; // @[CSR.scala:555:27]
wire [1:0] _GEN_1 = {reg_mip_seip, 1'h0}; // @[CSR.scala:504:20, :555:27]
wire [1:0] read_hvip_hi_lo_lo; // @[CSR.scala:555:27]
assign read_hvip_hi_lo_lo = _GEN_1; // @[CSR.scala:555:27]
wire [1:0] new_mip_hi_lo_lo; // @[CSR.scala:1271:59]
assign new_mip_hi_lo_lo = _GEN_1; // @[CSR.scala:555:27, :1271:59]
wire [3:0] read_hvip_hi_lo = {read_hvip_hi_lo_hi, read_hvip_hi_lo_lo}; // @[CSR.scala:555:27]
wire [1:0] read_hvip_hi_hi_hi = {read_hvip_hi_hi_hi_hi, 1'h0}; // @[CSR.scala:555:27]
wire [3:0] read_hvip_hi_hi = {read_hvip_hi_hi_hi, read_hvip_hi_hi_lo}; // @[CSR.scala:555:27]
wire [7:0] read_hvip_hi = {read_hvip_hi_hi, read_hvip_hi_lo}; // @[CSR.scala:555:27]
wire [15:0] _read_hvip_T = {read_hvip_hi, read_hvip_lo}; // @[CSR.scala:555:27]
reg reg_vsstatus_spp; // @[CSR.scala:562:25]
assign io_gstatus_spp_0 = reg_vsstatus_spp; // @[CSR.scala:377:7, :562:25]
reg reg_vsstatus_spie; // @[CSR.scala:562:25]
assign io_gstatus_spie_0 = reg_vsstatus_spie; // @[CSR.scala:377:7, :562:25]
reg reg_vsstatus_sie; // @[CSR.scala:562:25]
assign io_gstatus_sie_0 = reg_vsstatus_sie; // @[CSR.scala:377:7, :562:25]
reg [39:0] reg_vsepc; // @[CSR.scala:564:22]
reg [63:0] reg_vscause; // @[CSR.scala:565:24]
reg [39:0] reg_vstval; // @[CSR.scala:566:23]
reg [39:0] reg_sepc; // @[CSR.scala:569:21]
reg [63:0] reg_scause; // @[CSR.scala:570:23]
reg [39:0] reg_stval; // @[CSR.scala:571:22]
reg [63:0] reg_sscratch; // @[CSR.scala:572:25]
reg [38:0] reg_stvec; // @[CSR.scala:573:22]
reg [3:0] reg_satp_mode; // @[CSR.scala:574:21]
assign io_ptbr_mode_0 = reg_satp_mode; // @[CSR.scala:377:7, :574:21]
reg [43:0] reg_satp_ppn; // @[CSR.scala:574:21]
assign io_ptbr_ppn_0 = reg_satp_ppn; // @[CSR.scala:377:7, :574:21]
reg reg_wfi; // @[CSR.scala:575:54]
assign io_status_wfi_0 = reg_wfi; // @[CSR.scala:377:7, :575:54]
reg [4:0] reg_fflags; // @[CSR.scala:577:23]
reg [2:0] reg_frm; // @[CSR.scala:578:20]
assign io_fcsr_rm_0 = reg_frm; // @[CSR.scala:377:7, :578:20]
reg reg_mtinst_read_pseudo; // @[CSR.scala:584:35]
reg reg_htinst_read_pseudo; // @[CSR.scala:585:35]
wire [1:0] hi_4 = {2{reg_mtinst_read_pseudo}}; // @[CSR.scala:584:35, :588:103]
wire [13:0] read_mtinst = {hi_4, 12'h0}; // @[CSR.scala:588:103]
wire [1:0] hi_5 = {2{reg_htinst_read_pseudo}}; // @[CSR.scala:585:35, :588:103]
wire [13:0] read_htinst = {hi_5, 12'h0}; // @[CSR.scala:588:103]
reg [2:0] reg_mcountinhibit; // @[CSR.scala:590:34]
assign _io_inhibit_cycle_T = reg_mcountinhibit[0]; // @[CSR.scala:590:34, :591:40]
wire x11 = reg_mcountinhibit[0]; // @[CSR.scala:590:34, :591:40, :594:98]
assign io_inhibit_cycle_0 = _io_inhibit_cycle_T; // @[CSR.scala:377:7, :591:40]
wire x3 = reg_mcountinhibit[2]; // @[CSR.scala:590:34, :592:75]
reg [5:0] small_0; // @[Counters.scala:45:41]
wire [6:0] nextSmall = {1'h0, small_0} + {6'h0, io_retire_0}; // @[Counters.scala:45:41, :46:33]
wire _large_T_1 = ~x3; // @[Counters.scala:47:9, :51:36]
reg [57:0] large_0; // @[Counters.scala:50:31]
wire _large_T = nextSmall[6]; // @[Counters.scala:46:33, :51:20]
wire _large_T_2 = _large_T & _large_T_1; // @[Counters.scala:51:{20,33,36}]
wire [58:0] _large_r_T = {1'h0, large_0} + 59'h1; // @[Counters.scala:50:31, :51:55]
wire [57:0] _large_r_T_1 = _large_r_T[57:0]; // @[Counters.scala:51:55]
wire [63:0] value = {large_0, small_0}; // @[Counters.scala:45:41, :50:31, :55:30]
wire x10 = ~io_csr_stall_0; // @[CSR.scala:377:7, :594:56]
reg [5:0] small_1; // @[Counters.scala:45:41]
wire [6:0] nextSmall_1 = {1'h0, small_1} + {6'h0, x10}; // @[Counters.scala:45:41, :46:33]
wire _large_T_4 = ~x11; // @[Counters.scala:47:9, :51:36]
reg [57:0] large_1; // @[Counters.scala:50:31]
wire _large_T_3 = nextSmall_1[6]; // @[Counters.scala:46:33, :51:20]
wire _large_T_5 = _large_T_3 & _large_T_4; // @[Counters.scala:51:{20,33,36}]
wire [58:0] _large_r_T_2 = {1'h0, large_1} + 59'h1; // @[Counters.scala:50:31, :51:55]
wire [57:0] _large_r_T_3 = _large_r_T_2[57:0]; // @[Counters.scala:51:55]
assign value_1 = {large_1, small_1}; // @[Counters.scala:45:41, :50:31, :55:30]
assign io_time_0 = value_1; // @[Counters.scala:55:30]
wire read_mip_hi_hi_hi_hi = mip_zero1; // @[CSR.scala:600:24, :610:22]
wire _mip_seip_T; // @[CSR.scala:606:57]
wire mip_seip; // @[CSR.scala:600:24]
assign _mip_seip_T = reg_mip_seip | io_interrupts_seip_0; // @[CSR.scala:377:7, :504:20, :606:57]
assign mip_seip = _mip_seip_T; // @[CSR.scala:600:24, :606:57]
wire [1:0] read_mip_lo_lo_lo = {mip_ssip, mip_usip}; // @[CSR.scala:600:24, :610:22]
wire [1:0] read_mip_lo_lo_hi = {mip_msip, mip_vssip}; // @[CSR.scala:600:24, :610:22]
wire [3:0] read_mip_lo_lo = {read_mip_lo_lo_hi, read_mip_lo_lo_lo}; // @[CSR.scala:610:22]
wire [1:0] read_mip_lo_hi_lo = {mip_stip, mip_utip}; // @[CSR.scala:600:24, :610:22]
wire [1:0] read_mip_lo_hi_hi = {mip_mtip, mip_vstip}; // @[CSR.scala:600:24, :610:22]
wire [3:0] read_mip_lo_hi = {read_mip_lo_hi_hi, read_mip_lo_hi_lo}; // @[CSR.scala:610:22]
wire [7:0] read_mip_lo = {read_mip_lo_hi, read_mip_lo_lo}; // @[CSR.scala:610:22]
wire [1:0] read_mip_hi_lo_lo = {mip_seip, mip_ueip}; // @[CSR.scala:600:24, :610:22]
wire [1:0] read_mip_hi_lo_hi = {mip_meip, mip_vseip}; // @[CSR.scala:600:24, :610:22]
wire [3:0] read_mip_hi_lo = {read_mip_hi_lo_hi, read_mip_hi_lo_lo}; // @[CSR.scala:610:22]
wire [1:0] read_mip_hi_hi_lo = {mip_rocc, mip_sgeip}; // @[CSR.scala:600:24, :610:22]
wire [1:0] read_mip_hi_hi_hi = {read_mip_hi_hi_hi_hi, mip_debug}; // @[CSR.scala:600:24, :610:22]
wire [3:0] read_mip_hi_hi = {read_mip_hi_hi_hi, read_mip_hi_hi_lo}; // @[CSR.scala:610:22]
wire [7:0] read_mip_hi = {read_mip_hi_hi, read_mip_hi_lo}; // @[CSR.scala:610:22]
wire [15:0] _read_mip_T = {read_mip_hi, read_mip_lo}; // @[CSR.scala:610:22]
wire [15:0] read_mip = _read_mip_T & 16'h2AAA; // @[CSR.scala:610:{22,29}]
wire [63:0] _pending_interrupts_T = {48'h0, reg_mie[15:0] & read_mip}; // @[CSR.scala:495:20, :610:29, :614:56]
wire [63:0] pending_interrupts = _pending_interrupts_T; // @[CSR.scala:614:{44,56}]
wire [14:0] d_interrupts = {io_interrupts_debug_0, 14'h0}; // @[CSR.scala:377:7, :615:42]
wire _allow_wfi_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :906:61]
wire _allow_sfence_vma_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :907:60]
wire _allow_sret_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :910:62]
wire _allow_counter_T = reg_mstatus_prv[1]; // @[CSR.scala:395:28, :620:51, :912:42]
wire _m_interrupts_T = ~(reg_mstatus_prv[1]); // @[CSR.scala:395:28, :620:51]
wire _m_interrupts_T_1 = _m_interrupts_T | reg_mstatus_mie; // @[CSR.scala:395:28, :620:{51,62}]
wire _m_interrupts_T_2 = _m_interrupts_T_1; // @[CSR.scala:620:{31,62}]
wire [63:0] _m_interrupts_T_3 = ~pending_interrupts; // @[CSR.scala:614:44, :620:85]
wire [63:0] _m_interrupts_T_4 = _m_interrupts_T_3 | read_mideleg; // @[CSR.scala:498:14, :620:{85,105}]
wire [63:0] _m_interrupts_T_5 = ~_m_interrupts_T_4; // @[CSR.scala:620:{83,105}]
wire [63:0] m_interrupts = _m_interrupts_T_2 ? _m_interrupts_T_5 : 64'h0; // @[CSR.scala:620:{25,31,83}]
wire _GEN_2 = reg_mstatus_prv == 2'h0; // @[CSR.scala:395:28, :621:68]
wire _s_interrupts_T; // @[CSR.scala:621:68]
assign _s_interrupts_T = _GEN_2; // @[CSR.scala:621:68]
wire _vs_interrupts_T; // @[CSR.scala:622:70]
assign _vs_interrupts_T = _GEN_2; // @[CSR.scala:621:68, :622:70]
wire _io_fiom_T_2; // @[CSR.scala:631:82]
assign _io_fiom_T_2 = _GEN_2; // @[CSR.scala:621:68, :631:82]
wire _s_interrupts_T_1 = reg_mstatus_v | _s_interrupts_T; // @[CSR.scala:395:28, :621:{49,68}]
wire _GEN_3 = reg_mstatus_prv == 2'h1; // @[CSR.scala:395:28, :621:98]
wire _s_interrupts_T_2; // @[CSR.scala:621:98]
assign _s_interrupts_T_2 = _GEN_3; // @[CSR.scala:621:98]
wire _vs_interrupts_T_1; // @[CSR.scala:622:99]
assign _vs_interrupts_T_1 = _GEN_3; // @[CSR.scala:621:98, :622:99]
wire _csr_addr_legal_T_4; // @[CSR.scala:921:62]
assign _csr_addr_legal_T_4 = _GEN_3; // @[CSR.scala:621:98, :921:62]
wire _s_interrupts_T_3 = _s_interrupts_T_2 & reg_mstatus_sie; // @[CSR.scala:395:28, :621:{98,110}]
wire _s_interrupts_T_4 = _s_interrupts_T_1 | _s_interrupts_T_3; // @[CSR.scala:621:{49,78,110}]
wire _s_interrupts_T_5 = _s_interrupts_T_4; // @[CSR.scala:621:{31,78}]
wire [63:0] _s_interrupts_T_6 = pending_interrupts & read_mideleg; // @[CSR.scala:498:14, :614:44, :621:151]
wire [63:0] _s_interrupts_T_8 = _s_interrupts_T_6; // @[CSR.scala:621:{151,166}]
wire [63:0] s_interrupts = _s_interrupts_T_5 ? _s_interrupts_T_8 : 64'h0; // @[CSR.scala:621:{25,31,166}]
wire _vs_interrupts_T_2 = _vs_interrupts_T_1 & reg_vsstatus_sie; // @[CSR.scala:562:25, :622:{99,111}]
wire _vs_interrupts_T_3 = _vs_interrupts_T | _vs_interrupts_T_2; // @[CSR.scala:622:{70,80,111}]
wire _vs_interrupts_T_4 = reg_mstatus_v & _vs_interrupts_T_3; // @[CSR.scala:395:28, :622:{50,80}]
wire _vs_interrupts_T_5 = _vs_interrupts_T_4; // @[CSR.scala:622:{32,50}]
wire _any_T = d_interrupts[14]; // @[CSR.scala:615:42, :1637:76]
wire _which_T = d_interrupts[14]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_1 = d_interrupts[13]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_1 = d_interrupts[13]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_2 = d_interrupts[12]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_2 = d_interrupts[12]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_3 = d_interrupts[11]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_3 = d_interrupts[11]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_4 = d_interrupts[3]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_4 = d_interrupts[3]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_5 = d_interrupts[7]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_5 = d_interrupts[7]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_6 = d_interrupts[9]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_6 = d_interrupts[9]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_7 = d_interrupts[1]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_7 = d_interrupts[1]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_8 = d_interrupts[5]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_8 = d_interrupts[5]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_9 = d_interrupts[10]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_9 = d_interrupts[10]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_10 = d_interrupts[2]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_10 = d_interrupts[2]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_11 = d_interrupts[6]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_11 = d_interrupts[6]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_12 = d_interrupts[8]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_12 = d_interrupts[8]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_13 = d_interrupts[0]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_13 = d_interrupts[0]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_14 = d_interrupts[4]; // @[CSR.scala:615:42, :1637:76]
wire _which_T_14 = d_interrupts[4]; // @[CSR.scala:615:42, :1637:76, :1638:91]
wire _any_T_15 = m_interrupts[15]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_15 = m_interrupts[15]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_16 = m_interrupts[14]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_16 = m_interrupts[14]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_17 = m_interrupts[13]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_17 = m_interrupts[13]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_18 = m_interrupts[12]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_18 = m_interrupts[12]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_19 = m_interrupts[11]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_19 = m_interrupts[11]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_20 = m_interrupts[3]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_20 = m_interrupts[3]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_21 = m_interrupts[7]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_21 = m_interrupts[7]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_22 = m_interrupts[9]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_22 = m_interrupts[9]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_23 = m_interrupts[1]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_23 = m_interrupts[1]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_24 = m_interrupts[5]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_24 = m_interrupts[5]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_25 = m_interrupts[10]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_25 = m_interrupts[10]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_26 = m_interrupts[2]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_26 = m_interrupts[2]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_27 = m_interrupts[6]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_27 = m_interrupts[6]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_28 = m_interrupts[8]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_28 = m_interrupts[8]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_29 = m_interrupts[0]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_29 = m_interrupts[0]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_30 = m_interrupts[4]; // @[CSR.scala:620:25, :1637:76]
wire _which_T_30 = m_interrupts[4]; // @[CSR.scala:620:25, :1637:76, :1638:91]
wire _any_T_31 = s_interrupts[15]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_31 = s_interrupts[15]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_32 = s_interrupts[14]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_32 = s_interrupts[14]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_33 = s_interrupts[13]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_33 = s_interrupts[13]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_34 = s_interrupts[12]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_34 = s_interrupts[12]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_35 = s_interrupts[11]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_35 = s_interrupts[11]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_36 = s_interrupts[3]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_36 = s_interrupts[3]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_37 = s_interrupts[7]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_37 = s_interrupts[7]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_38 = s_interrupts[9]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_38 = s_interrupts[9]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_39 = s_interrupts[1]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_39 = s_interrupts[1]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_40 = s_interrupts[5]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_40 = s_interrupts[5]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_41 = s_interrupts[10]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_41 = s_interrupts[10]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_42 = s_interrupts[2]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_42 = s_interrupts[2]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_43 = s_interrupts[6]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_43 = s_interrupts[6]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_44 = s_interrupts[8]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_44 = s_interrupts[8]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_45 = s_interrupts[0]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_45 = s_interrupts[0]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_46 = s_interrupts[4]; // @[CSR.scala:621:25, :1637:76]
wire _which_T_46 = s_interrupts[4]; // @[CSR.scala:621:25, :1637:76, :1638:91]
wire _any_T_63 = _any_T | _any_T_1; // @[CSR.scala:1637:{76,90}]
wire _any_T_64 = _any_T_63 | _any_T_2; // @[CSR.scala:1637:{76,90}]
wire _any_T_65 = _any_T_64 | _any_T_3; // @[CSR.scala:1637:{76,90}]
wire _any_T_66 = _any_T_65 | _any_T_4; // @[CSR.scala:1637:{76,90}]
wire _any_T_67 = _any_T_66 | _any_T_5; // @[CSR.scala:1637:{76,90}]
wire _any_T_68 = _any_T_67 | _any_T_6; // @[CSR.scala:1637:{76,90}]
wire _any_T_69 = _any_T_68 | _any_T_7; // @[CSR.scala:1637:{76,90}]
wire _any_T_70 = _any_T_69 | _any_T_8; // @[CSR.scala:1637:{76,90}]
wire _any_T_71 = _any_T_70 | _any_T_9; // @[CSR.scala:1637:{76,90}]
wire _any_T_72 = _any_T_71 | _any_T_10; // @[CSR.scala:1637:{76,90}]
wire _any_T_73 = _any_T_72 | _any_T_11; // @[CSR.scala:1637:{76,90}]
wire _any_T_74 = _any_T_73 | _any_T_12; // @[CSR.scala:1637:{76,90}]
wire _any_T_75 = _any_T_74 | _any_T_13; // @[CSR.scala:1637:{76,90}]
wire _any_T_76 = _any_T_75 | _any_T_14; // @[CSR.scala:1637:{76,90}]
wire _any_T_77 = _any_T_76; // @[CSR.scala:1637:90]
wire _any_T_78 = _any_T_77 | _any_T_15; // @[CSR.scala:1637:{76,90}]
wire _any_T_79 = _any_T_78 | _any_T_16; // @[CSR.scala:1637:{76,90}]
wire _any_T_80 = _any_T_79 | _any_T_17; // @[CSR.scala:1637:{76,90}]
wire _any_T_81 = _any_T_80 | _any_T_18; // @[CSR.scala:1637:{76,90}]
wire _any_T_82 = _any_T_81 | _any_T_19; // @[CSR.scala:1637:{76,90}]
wire _any_T_83 = _any_T_82 | _any_T_20; // @[CSR.scala:1637:{76,90}]
wire _any_T_84 = _any_T_83 | _any_T_21; // @[CSR.scala:1637:{76,90}]
wire _any_T_85 = _any_T_84 | _any_T_22; // @[CSR.scala:1637:{76,90}]
wire _any_T_86 = _any_T_85 | _any_T_23; // @[CSR.scala:1637:{76,90}]
wire _any_T_87 = _any_T_86 | _any_T_24; // @[CSR.scala:1637:{76,90}]
wire _any_T_88 = _any_T_87 | _any_T_25; // @[CSR.scala:1637:{76,90}]
wire _any_T_89 = _any_T_88 | _any_T_26; // @[CSR.scala:1637:{76,90}]
wire _any_T_90 = _any_T_89 | _any_T_27; // @[CSR.scala:1637:{76,90}]
wire _any_T_91 = _any_T_90 | _any_T_28; // @[CSR.scala:1637:{76,90}]
wire _any_T_92 = _any_T_91 | _any_T_29; // @[CSR.scala:1637:{76,90}]
wire _any_T_93 = _any_T_92 | _any_T_30; // @[CSR.scala:1637:{76,90}]
wire _any_T_94 = _any_T_93 | _any_T_31; // @[CSR.scala:1637:{76,90}]
wire _any_T_95 = _any_T_94 | _any_T_32; // @[CSR.scala:1637:{76,90}]
wire _any_T_96 = _any_T_95 | _any_T_33; // @[CSR.scala:1637:{76,90}]
wire _any_T_97 = _any_T_96 | _any_T_34; // @[CSR.scala:1637:{76,90}]
wire _any_T_98 = _any_T_97 | _any_T_35; // @[CSR.scala:1637:{76,90}]
wire _any_T_99 = _any_T_98 | _any_T_36; // @[CSR.scala:1637:{76,90}]
wire _any_T_100 = _any_T_99 | _any_T_37; // @[CSR.scala:1637:{76,90}]
wire _any_T_101 = _any_T_100 | _any_T_38; // @[CSR.scala:1637:{76,90}]
wire _any_T_102 = _any_T_101 | _any_T_39; // @[CSR.scala:1637:{76,90}]
wire _any_T_103 = _any_T_102 | _any_T_40; // @[CSR.scala:1637:{76,90}]
wire _any_T_104 = _any_T_103 | _any_T_41; // @[CSR.scala:1637:{76,90}]
wire _any_T_105 = _any_T_104 | _any_T_42; // @[CSR.scala:1637:{76,90}]
wire _any_T_106 = _any_T_105 | _any_T_43; // @[CSR.scala:1637:{76,90}]
wire _any_T_107 = _any_T_106 | _any_T_44; // @[CSR.scala:1637:{76,90}]
wire _any_T_108 = _any_T_107 | _any_T_45; // @[CSR.scala:1637:{76,90}]
wire _any_T_109 = _any_T_108 | _any_T_46; // @[CSR.scala:1637:{76,90}]
wire _any_T_110 = _any_T_109; // @[CSR.scala:1637:90]
wire _any_T_111 = _any_T_110; // @[CSR.scala:1637:90]
wire _any_T_112 = _any_T_111; // @[CSR.scala:1637:90]
wire _any_T_113 = _any_T_112; // @[CSR.scala:1637:90]
wire _any_T_114 = _any_T_113; // @[CSR.scala:1637:90]
wire _any_T_115 = _any_T_114; // @[CSR.scala:1637:90]
wire _any_T_116 = _any_T_115; // @[CSR.scala:1637:90]
wire _any_T_117 = _any_T_116; // @[CSR.scala:1637:90]
wire _any_T_118 = _any_T_117; // @[CSR.scala:1637:90]
wire _any_T_119 = _any_T_118; // @[CSR.scala:1637:90]
wire _any_T_120 = _any_T_119; // @[CSR.scala:1637:90]
wire _any_T_121 = _any_T_120; // @[CSR.scala:1637:90]
wire _any_T_122 = _any_T_121; // @[CSR.scala:1637:90]
wire _any_T_123 = _any_T_122; // @[CSR.scala:1637:90]
wire _any_T_124 = _any_T_123; // @[CSR.scala:1637:90]
wire anyInterrupt = _any_T_124; // @[CSR.scala:1637:90]
wire [3:0] _which_T_79 = {1'h0, ~_which_T_45, 2'h0}; // @[Mux.scala:50:70]
wire [3:0] _which_T_80 = _which_T_44 ? 4'h8 : _which_T_79; // @[Mux.scala:50:70]
wire [3:0] _which_T_81 = _which_T_43 ? 4'h6 : _which_T_80; // @[Mux.scala:50:70]
wire [3:0] _which_T_82 = _which_T_42 ? 4'h2 : _which_T_81; // @[Mux.scala:50:70]
wire [3:0] _which_T_83 = _which_T_41 ? 4'hA : _which_T_82; // @[Mux.scala:50:70]
wire [3:0] _which_T_84 = _which_T_40 ? 4'h5 : _which_T_83; // @[Mux.scala:50:70]
wire [3:0] _which_T_85 = _which_T_39 ? 4'h1 : _which_T_84; // @[Mux.scala:50:70]
wire [3:0] _which_T_86 = _which_T_38 ? 4'h9 : _which_T_85; // @[Mux.scala:50:70]
wire [3:0] _which_T_87 = _which_T_37 ? 4'h7 : _which_T_86; // @[Mux.scala:50:70]
wire [3:0] _which_T_88 = _which_T_36 ? 4'h3 : _which_T_87; // @[Mux.scala:50:70]
wire [3:0] _which_T_89 = _which_T_35 ? 4'hB : _which_T_88; // @[Mux.scala:50:70]
wire [3:0] _which_T_90 = _which_T_34 ? 4'hC : _which_T_89; // @[Mux.scala:50:70]
wire [3:0] _which_T_91 = _which_T_33 ? 4'hD : _which_T_90; // @[Mux.scala:50:70]
wire [3:0] _which_T_92 = _which_T_32 ? 4'hE : _which_T_91; // @[Mux.scala:50:70]
wire [3:0] _which_T_93 = _which_T_31 ? 4'hF : _which_T_92; // @[Mux.scala:50:70]
wire [3:0] _which_T_94 = _which_T_30 ? 4'h4 : _which_T_93; // @[Mux.scala:50:70]
wire [3:0] _which_T_95 = _which_T_29 ? 4'h0 : _which_T_94; // @[Mux.scala:50:70]
wire [3:0] _which_T_96 = _which_T_28 ? 4'h8 : _which_T_95; // @[Mux.scala:50:70]
wire [3:0] _which_T_97 = _which_T_27 ? 4'h6 : _which_T_96; // @[Mux.scala:50:70]
wire [3:0] _which_T_98 = _which_T_26 ? 4'h2 : _which_T_97; // @[Mux.scala:50:70]
wire [3:0] _which_T_99 = _which_T_25 ? 4'hA : _which_T_98; // @[Mux.scala:50:70]
wire [3:0] _which_T_100 = _which_T_24 ? 4'h5 : _which_T_99; // @[Mux.scala:50:70]
wire [3:0] _which_T_101 = _which_T_23 ? 4'h1 : _which_T_100; // @[Mux.scala:50:70]
wire [3:0] _which_T_102 = _which_T_22 ? 4'h9 : _which_T_101; // @[Mux.scala:50:70]
wire [3:0] _which_T_103 = _which_T_21 ? 4'h7 : _which_T_102; // @[Mux.scala:50:70]
wire [3:0] _which_T_104 = _which_T_20 ? 4'h3 : _which_T_103; // @[Mux.scala:50:70]
wire [3:0] _which_T_105 = _which_T_19 ? 4'hB : _which_T_104; // @[Mux.scala:50:70]
wire [3:0] _which_T_106 = _which_T_18 ? 4'hC : _which_T_105; // @[Mux.scala:50:70]
wire [3:0] _which_T_107 = _which_T_17 ? 4'hD : _which_T_106; // @[Mux.scala:50:70]
wire [3:0] _which_T_108 = _which_T_16 ? 4'hE : _which_T_107; // @[Mux.scala:50:70]
wire [3:0] _which_T_109 = _which_T_15 ? 4'hF : _which_T_108; // @[Mux.scala:50:70]
wire [3:0] _which_T_110 = _which_T_109; // @[Mux.scala:50:70]
wire [3:0] _which_T_111 = _which_T_14 ? 4'h4 : _which_T_110; // @[Mux.scala:50:70]
wire [3:0] _which_T_112 = _which_T_13 ? 4'h0 : _which_T_111; // @[Mux.scala:50:70]
wire [3:0] _which_T_113 = _which_T_12 ? 4'h8 : _which_T_112; // @[Mux.scala:50:70]
wire [3:0] _which_T_114 = _which_T_11 ? 4'h6 : _which_T_113; // @[Mux.scala:50:70]
wire [3:0] _which_T_115 = _which_T_10 ? 4'h2 : _which_T_114; // @[Mux.scala:50:70]
wire [3:0] _which_T_116 = _which_T_9 ? 4'hA : _which_T_115; // @[Mux.scala:50:70]
wire [3:0] _which_T_117 = _which_T_8 ? 4'h5 : _which_T_116; // @[Mux.scala:50:70]
wire [3:0] _which_T_118 = _which_T_7 ? 4'h1 : _which_T_117; // @[Mux.scala:50:70]
wire [3:0] _which_T_119 = _which_T_6 ? 4'h9 : _which_T_118; // @[Mux.scala:50:70]
wire [3:0] _which_T_120 = _which_T_5 ? 4'h7 : _which_T_119; // @[Mux.scala:50:70]
wire [3:0] _which_T_121 = _which_T_4 ? 4'h3 : _which_T_120; // @[Mux.scala:50:70]
wire [3:0] _which_T_122 = _which_T_3 ? 4'hB : _which_T_121; // @[Mux.scala:50:70]
wire [3:0] _which_T_123 = _which_T_2 ? 4'hC : _which_T_122; // @[Mux.scala:50:70]
wire [3:0] _which_T_124 = _which_T_1 ? 4'hD : _which_T_123; // @[Mux.scala:50:70]
wire [3:0] whichInterrupt = _which_T ? 4'hE : _which_T_124; // @[Mux.scala:50:70]
wire [64:0] _interruptCause_T_3 = {61'h0, whichInterrupt} + 65'h8000000000000000; // @[Mux.scala:50:70]
assign interruptCause = _interruptCause_T_3[63:0]; // @[CSR.scala:625:63]
assign io_interrupt_cause_0 = interruptCause; // @[CSR.scala:377:7, :625:63]
wire _io_interrupt_T = ~io_singleStep_0; // @[CSR.scala:377:7, :626:36]
wire _io_interrupt_T_1 = anyInterrupt & _io_interrupt_T; // @[CSR.scala:626:{33,36}, :1637:90]
wire _io_interrupt_T_2 = _io_interrupt_T_1 | reg_singleStepped; // @[CSR.scala:486:30, :626:{33,51}]
wire _io_interrupt_T_3 = reg_debug | io_status_cease_0; // @[CSR.scala:377:7, :482:26, :626:88]
wire _io_interrupt_T_4 = ~_io_interrupt_T_3; // @[CSR.scala:626:{76,88}]
assign _io_interrupt_T_5 = _io_interrupt_T_2 & _io_interrupt_T_4; // @[CSR.scala:626:{51,73,76}]
assign io_interrupt_0 = _io_interrupt_T_5; // @[CSR.scala:377:7, :626:73]
wire _io_fiom_T = reg_mstatus_prv != 2'h3; // @[CSR.scala:395:28, :631:31]
wire _io_fiom_T_1 = _io_fiom_T & reg_menvcfg_fiom; // @[CSR.scala:525:28, :631:{31,41}]
wire _io_fiom_T_3 = _io_fiom_T_2 & reg_senvcfg_fiom; // @[CSR.scala:526:28, :631:{82,92}]
wire _io_fiom_T_4 = _io_fiom_T_1 | _io_fiom_T_3; // @[CSR.scala:631:{41,62,92}]
assign _io_fiom_T_6 = _io_fiom_T_4; // @[CSR.scala:631:{62,113}]
assign io_fiom = _io_fiom_T_6; // @[CSR.scala:377:7, :631:113]
assign io_pmp_0_cfg_l_0 = pmp_cfg_l; // @[PMP.scala:24:19]
assign io_pmp_0_cfg_a_0 = pmp_cfg_a; // @[PMP.scala:24:19]
assign io_pmp_0_cfg_x_0 = pmp_cfg_x; // @[PMP.scala:24:19]
assign io_pmp_0_cfg_w_0 = pmp_cfg_w; // @[PMP.scala:24:19]
assign io_pmp_0_cfg_r_0 = pmp_cfg_r; // @[PMP.scala:24:19]
assign io_pmp_0_addr_0 = pmp_addr; // @[PMP.scala:24:19]
assign io_pmp_0_mask_0 = pmp_mask; // @[PMP.scala:24:19]
wire _pmp_mask_base_T = pmp_cfg_a[0]; // @[PMP.scala:24:19, :57:31]
wire [30:0] _pmp_mask_base_T_1 = {pmp_addr, _pmp_mask_base_T}; // @[PMP.scala:24:19, :57:{19,31}]
wire [30:0] pmp_mask_base = _pmp_mask_base_T_1; // @[PMP.scala:57:{19,36}]
wire [31:0] _pmp_mask_T = {1'h0, pmp_mask_base} + 32'h1; // @[PMP.scala:57:36, :58:23]
wire [30:0] _pmp_mask_T_1 = _pmp_mask_T[30:0]; // @[PMP.scala:58:23]
wire [30:0] _pmp_mask_T_2 = ~_pmp_mask_T_1; // @[PMP.scala:58:{16,23}]
wire [30:0] _pmp_mask_T_3 = pmp_mask_base & _pmp_mask_T_2; // @[PMP.scala:57:36, :58:{14,16}]
wire [32:0] _pmp_mask_T_4 = {_pmp_mask_T_3, 2'h3}; // @[PMP.scala:58:{8,14}]
assign pmp_mask = _pmp_mask_T_4[31:0]; // @[PMP.scala:24:19, :27:14, :58:8]
assign io_pmp_1_cfg_l_0 = pmp_1_cfg_l; // @[PMP.scala:24:19]
assign io_pmp_1_cfg_a_0 = pmp_1_cfg_a; // @[PMP.scala:24:19]
assign io_pmp_1_cfg_x_0 = pmp_1_cfg_x; // @[PMP.scala:24:19]
assign io_pmp_1_cfg_w_0 = pmp_1_cfg_w; // @[PMP.scala:24:19]
assign io_pmp_1_cfg_r_0 = pmp_1_cfg_r; // @[PMP.scala:24:19]
assign io_pmp_1_addr_0 = pmp_1_addr; // @[PMP.scala:24:19]
assign io_pmp_1_mask_0 = pmp_1_mask; // @[PMP.scala:24:19]
wire _pmp_mask_base_T_3 = pmp_1_cfg_a[0]; // @[PMP.scala:24:19, :57:31]
wire [30:0] _pmp_mask_base_T_4 = {pmp_1_addr, _pmp_mask_base_T_3}; // @[PMP.scala:24:19, :57:{19,31}]
wire [30:0] pmp_mask_base_1 = _pmp_mask_base_T_4; // @[PMP.scala:57:{19,36}]
wire [31:0] _pmp_mask_T_5 = {1'h0, pmp_mask_base_1} + 32'h1; // @[PMP.scala:57:36, :58:23]
wire [30:0] _pmp_mask_T_6 = _pmp_mask_T_5[30:0]; // @[PMP.scala:58:23]
wire [30:0] _pmp_mask_T_7 = ~_pmp_mask_T_6; // @[PMP.scala:58:{16,23}]
wire [30:0] _pmp_mask_T_8 = pmp_mask_base_1 & _pmp_mask_T_7; // @[PMP.scala:57:36, :58:{14,16}]
wire [32:0] _pmp_mask_T_9 = {_pmp_mask_T_8, 2'h3}; // @[PMP.scala:58:{8,14}]
assign pmp_1_mask = _pmp_mask_T_9[31:0]; // @[PMP.scala:24:19, :27:14, :58:8]
assign io_pmp_2_cfg_l_0 = pmp_2_cfg_l; // @[PMP.scala:24:19]
assign io_pmp_2_cfg_a_0 = pmp_2_cfg_a; // @[PMP.scala:24:19]
assign io_pmp_2_cfg_x_0 = pmp_2_cfg_x; // @[PMP.scala:24:19]
assign io_pmp_2_cfg_w_0 = pmp_2_cfg_w; // @[PMP.scala:24:19]
assign io_pmp_2_cfg_r_0 = pmp_2_cfg_r; // @[PMP.scala:24:19]
assign io_pmp_2_addr_0 = pmp_2_addr; // @[PMP.scala:24:19]
assign io_pmp_2_mask_0 = pmp_2_mask; // @[PMP.scala:24:19]
wire _pmp_mask_base_T_6 = pmp_2_cfg_a[0]; // @[PMP.scala:24:19, :57:31]
wire [30:0] _pmp_mask_base_T_7 = {pmp_2_addr, _pmp_mask_base_T_6}; // @[PMP.scala:24:19, :57:{19,31}]
wire [30:0] pmp_mask_base_2 = _pmp_mask_base_T_7; // @[PMP.scala:57:{19,36}]
wire [31:0] _pmp_mask_T_10 = {1'h0, pmp_mask_base_2} + 32'h1; // @[PMP.scala:57:36, :58:23]
wire [30:0] _pmp_mask_T_11 = _pmp_mask_T_10[30:0]; // @[PMP.scala:58:23]
wire [30:0] _pmp_mask_T_12 = ~_pmp_mask_T_11; // @[PMP.scala:58:{16,23}]
wire [30:0] _pmp_mask_T_13 = pmp_mask_base_2 & _pmp_mask_T_12; // @[PMP.scala:57:36, :58:{14,16}]
wire [32:0] _pmp_mask_T_14 = {_pmp_mask_T_13, 2'h3}; // @[PMP.scala:58:{8,14}]
assign pmp_2_mask = _pmp_mask_T_14[31:0]; // @[PMP.scala:24:19, :27:14, :58:8]
assign io_pmp_3_cfg_l_0 = pmp_3_cfg_l; // @[PMP.scala:24:19]
assign io_pmp_3_cfg_a_0 = pmp_3_cfg_a; // @[PMP.scala:24:19]
assign io_pmp_3_cfg_x_0 = pmp_3_cfg_x; // @[PMP.scala:24:19]
assign io_pmp_3_cfg_w_0 = pmp_3_cfg_w; // @[PMP.scala:24:19]
assign io_pmp_3_cfg_r_0 = pmp_3_cfg_r; // @[PMP.scala:24:19]
assign io_pmp_3_addr_0 = pmp_3_addr; // @[PMP.scala:24:19]
assign io_pmp_3_mask_0 = pmp_3_mask; // @[PMP.scala:24:19]
wire _pmp_mask_base_T_9 = pmp_3_cfg_a[0]; // @[PMP.scala:24:19, :57:31]
wire [30:0] _pmp_mask_base_T_10 = {pmp_3_addr, _pmp_mask_base_T_9}; // @[PMP.scala:24:19, :57:{19,31}]
wire [30:0] pmp_mask_base_3 = _pmp_mask_base_T_10; // @[PMP.scala:57:{19,36}]
wire [31:0] _pmp_mask_T_15 = {1'h0, pmp_mask_base_3} + 32'h1; // @[PMP.scala:57:36, :58:23]
wire [30:0] _pmp_mask_T_16 = _pmp_mask_T_15[30:0]; // @[PMP.scala:58:23]
wire [30:0] _pmp_mask_T_17 = ~_pmp_mask_T_16; // @[PMP.scala:58:{16,23}]
wire [30:0] _pmp_mask_T_18 = pmp_mask_base_3 & _pmp_mask_T_17; // @[PMP.scala:57:36, :58:{14,16}]
wire [32:0] _pmp_mask_T_19 = {_pmp_mask_T_18, 2'h3}; // @[PMP.scala:58:{8,14}]
assign pmp_3_mask = _pmp_mask_T_19[31:0]; // @[PMP.scala:24:19, :27:14, :58:8]
assign io_pmp_4_cfg_l_0 = pmp_4_cfg_l; // @[PMP.scala:24:19]
assign io_pmp_4_cfg_a_0 = pmp_4_cfg_a; // @[PMP.scala:24:19]
assign io_pmp_4_cfg_x_0 = pmp_4_cfg_x; // @[PMP.scala:24:19]
assign io_pmp_4_cfg_w_0 = pmp_4_cfg_w; // @[PMP.scala:24:19]
assign io_pmp_4_cfg_r_0 = pmp_4_cfg_r; // @[PMP.scala:24:19]
assign io_pmp_4_addr_0 = pmp_4_addr; // @[PMP.scala:24:19]
assign io_pmp_4_mask_0 = pmp_4_mask; // @[PMP.scala:24:19]
wire _pmp_mask_base_T_12 = pmp_4_cfg_a[0]; // @[PMP.scala:24:19, :57:31]
wire [30:0] _pmp_mask_base_T_13 = {pmp_4_addr, _pmp_mask_base_T_12}; // @[PMP.scala:24:19, :57:{19,31}]
wire [30:0] pmp_mask_base_4 = _pmp_mask_base_T_13; // @[PMP.scala:57:{19,36}]
wire [31:0] _pmp_mask_T_20 = {1'h0, pmp_mask_base_4} + 32'h1; // @[PMP.scala:57:36, :58:23]
wire [30:0] _pmp_mask_T_21 = _pmp_mask_T_20[30:0]; // @[PMP.scala:58:23]
wire [30:0] _pmp_mask_T_22 = ~_pmp_mask_T_21; // @[PMP.scala:58:{16,23}]
wire [30:0] _pmp_mask_T_23 = pmp_mask_base_4 & _pmp_mask_T_22; // @[PMP.scala:57:36, :58:{14,16}]
wire [32:0] _pmp_mask_T_24 = {_pmp_mask_T_23, 2'h3}; // @[PMP.scala:58:{8,14}]
assign pmp_4_mask = _pmp_mask_T_24[31:0]; // @[PMP.scala:24:19, :27:14, :58:8]
assign io_pmp_5_cfg_l_0 = pmp_5_cfg_l; // @[PMP.scala:24:19]
assign io_pmp_5_cfg_a_0 = pmp_5_cfg_a; // @[PMP.scala:24:19]
assign io_pmp_5_cfg_x_0 = pmp_5_cfg_x; // @[PMP.scala:24:19]
assign io_pmp_5_cfg_w_0 = pmp_5_cfg_w; // @[PMP.scala:24:19]
assign io_pmp_5_cfg_r_0 = pmp_5_cfg_r; // @[PMP.scala:24:19]
assign io_pmp_5_addr_0 = pmp_5_addr; // @[PMP.scala:24:19]
assign io_pmp_5_mask_0 = pmp_5_mask; // @[PMP.scala:24:19]
wire _pmp_mask_base_T_15 = pmp_5_cfg_a[0]; // @[PMP.scala:24:19, :57:31]
wire [30:0] _pmp_mask_base_T_16 = {pmp_5_addr, _pmp_mask_base_T_15}; // @[PMP.scala:24:19, :57:{19,31}]
wire [30:0] pmp_mask_base_5 = _pmp_mask_base_T_16; // @[PMP.scala:57:{19,36}]
wire [31:0] _pmp_mask_T_25 = {1'h0, pmp_mask_base_5} + 32'h1; // @[PMP.scala:57:36, :58:23]
wire [30:0] _pmp_mask_T_26 = _pmp_mask_T_25[30:0]; // @[PMP.scala:58:23]
wire [30:0] _pmp_mask_T_27 = ~_pmp_mask_T_26; // @[PMP.scala:58:{16,23}]
wire [30:0] _pmp_mask_T_28 = pmp_mask_base_5 & _pmp_mask_T_27; // @[PMP.scala:57:36, :58:{14,16}]
wire [32:0] _pmp_mask_T_29 = {_pmp_mask_T_28, 2'h3}; // @[PMP.scala:58:{8,14}]
assign pmp_5_mask = _pmp_mask_T_29[31:0]; // @[PMP.scala:24:19, :27:14, :58:8]
assign io_pmp_6_cfg_l_0 = pmp_6_cfg_l; // @[PMP.scala:24:19]
assign io_pmp_6_cfg_a_0 = pmp_6_cfg_a; // @[PMP.scala:24:19]
assign io_pmp_6_cfg_x_0 = pmp_6_cfg_x; // @[PMP.scala:24:19]
assign io_pmp_6_cfg_w_0 = pmp_6_cfg_w; // @[PMP.scala:24:19]
assign io_pmp_6_cfg_r_0 = pmp_6_cfg_r; // @[PMP.scala:24:19]
assign io_pmp_6_addr_0 = pmp_6_addr; // @[PMP.scala:24:19]
assign io_pmp_6_mask_0 = pmp_6_mask; // @[PMP.scala:24:19]
wire _pmp_mask_base_T_18 = pmp_6_cfg_a[0]; // @[PMP.scala:24:19, :57:31]
wire [30:0] _pmp_mask_base_T_19 = {pmp_6_addr, _pmp_mask_base_T_18}; // @[PMP.scala:24:19, :57:{19,31}]
wire [30:0] pmp_mask_base_6 = _pmp_mask_base_T_19; // @[PMP.scala:57:{19,36}]
wire [31:0] _pmp_mask_T_30 = {1'h0, pmp_mask_base_6} + 32'h1; // @[PMP.scala:57:36, :58:23]
wire [30:0] _pmp_mask_T_31 = _pmp_mask_T_30[30:0]; // @[PMP.scala:58:23]
wire [30:0] _pmp_mask_T_32 = ~_pmp_mask_T_31; // @[PMP.scala:58:{16,23}]
wire [30:0] _pmp_mask_T_33 = pmp_mask_base_6 & _pmp_mask_T_32; // @[PMP.scala:57:36, :58:{14,16}]
wire [32:0] _pmp_mask_T_34 = {_pmp_mask_T_33, 2'h3}; // @[PMP.scala:58:{8,14}]
assign pmp_6_mask = _pmp_mask_T_34[31:0]; // @[PMP.scala:24:19, :27:14, :58:8]
assign io_pmp_7_cfg_l_0 = pmp_7_cfg_l; // @[PMP.scala:24:19]
assign io_pmp_7_cfg_a_0 = pmp_7_cfg_a; // @[PMP.scala:24:19]
assign io_pmp_7_cfg_x_0 = pmp_7_cfg_x; // @[PMP.scala:24:19]
assign io_pmp_7_cfg_w_0 = pmp_7_cfg_w; // @[PMP.scala:24:19]
assign io_pmp_7_cfg_r_0 = pmp_7_cfg_r; // @[PMP.scala:24:19]
assign io_pmp_7_addr_0 = pmp_7_addr; // @[PMP.scala:24:19]
assign io_pmp_7_mask_0 = pmp_7_mask; // @[PMP.scala:24:19]
wire _pmp_mask_base_T_21 = pmp_7_cfg_a[0]; // @[PMP.scala:24:19, :57:31]
wire [30:0] _pmp_mask_base_T_22 = {pmp_7_addr, _pmp_mask_base_T_21}; // @[PMP.scala:24:19, :57:{19,31}]
wire [30:0] pmp_mask_base_7 = _pmp_mask_base_T_22; // @[PMP.scala:57:{19,36}]
wire [31:0] _pmp_mask_T_35 = {1'h0, pmp_mask_base_7} + 32'h1; // @[PMP.scala:57:36, :58:23]
wire [30:0] _pmp_mask_T_36 = _pmp_mask_T_35[30:0]; // @[PMP.scala:58:23]
wire [30:0] _pmp_mask_T_37 = ~_pmp_mask_T_36; // @[PMP.scala:58:{16,23}]
wire [30:0] _pmp_mask_T_38 = pmp_mask_base_7 & _pmp_mask_T_37; // @[PMP.scala:57:36, :58:{14,16}]
wire [32:0] _pmp_mask_T_39 = {_pmp_mask_T_38, 2'h3}; // @[PMP.scala:58:{8,14}]
assign pmp_7_mask = _pmp_mask_T_39[31:0]; // @[PMP.scala:24:19, :27:14, :58:8]
reg [63:0] reg_misa; // @[CSR.scala:648:25]
wire [1:0] read_mstatus_lo_lo_lo_lo = {io_status_sie_0, 1'h0}; // @[CSR.scala:377:7, :649:32]
wire [1:0] read_mstatus_lo_lo_lo_hi = {io_status_mie_0, 1'h0}; // @[CSR.scala:377:7, :649:32]
wire [3:0] read_mstatus_lo_lo_lo = {read_mstatus_lo_lo_lo_hi, read_mstatus_lo_lo_lo_lo}; // @[CSR.scala:649:32]
wire [1:0] read_mstatus_lo_lo_hi_lo = {io_status_spie_0, 1'h0}; // @[CSR.scala:377:7, :649:32]
wire [1:0] read_mstatus_lo_lo_hi_hi_hi = {io_status_spp_0, io_status_mpie_0}; // @[CSR.scala:377:7, :649:32]
wire [2:0] read_mstatus_lo_lo_hi_hi = {read_mstatus_lo_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:649:32]
wire [4:0] read_mstatus_lo_lo_hi = {read_mstatus_lo_lo_hi_hi, read_mstatus_lo_lo_hi_lo}; // @[CSR.scala:649:32]
wire [8:0] read_mstatus_lo_lo = {read_mstatus_lo_lo_hi, read_mstatus_lo_lo_lo}; // @[CSR.scala:649:32]
wire [3:0] read_mstatus_lo_hi_lo_lo = {io_status_mpp_0, 2'h0}; // @[CSR.scala:377:7, :649:32]
wire [3:0] read_mstatus_lo_hi_lo_hi = {2'h3, io_status_fs_0}; // @[CSR.scala:377:7, :649:32]
wire [7:0] read_mstatus_lo_hi_lo = {read_mstatus_lo_hi_lo_hi, read_mstatus_lo_hi_lo_lo}; // @[CSR.scala:649:32]
wire [1:0] read_mstatus_lo_hi_hi_lo = {io_status_sum_0, io_status_mprv_0}; // @[CSR.scala:377:7, :649:32]
wire [1:0] read_mstatus_lo_hi_hi_hi_hi = {io_status_tw_0, io_status_tvm_0}; // @[CSR.scala:377:7, :649:32]
wire [2:0] read_mstatus_lo_hi_hi_hi = {read_mstatus_lo_hi_hi_hi_hi, io_status_mxr_0}; // @[CSR.scala:377:7, :649:32]
wire [4:0] read_mstatus_lo_hi_hi = {read_mstatus_lo_hi_hi_hi, read_mstatus_lo_hi_hi_lo}; // @[CSR.scala:649:32]
wire [12:0] read_mstatus_lo_hi = {read_mstatus_lo_hi_hi, read_mstatus_lo_hi_lo}; // @[CSR.scala:649:32]
wire [21:0] read_mstatus_lo = {read_mstatus_lo_hi, read_mstatus_lo_lo}; // @[CSR.scala:649:32]
wire [8:0] read_mstatus_hi_lo_lo_lo = {8'h0, io_status_tsr_0}; // @[CSR.scala:377:7, :649:32]
wire [11:0] read_mstatus_hi_lo_lo = {3'h4, read_mstatus_hi_lo_lo_lo}; // @[CSR.scala:649:32]
wire [1:0] read_mstatus_hi_lo_hi_hi_hi = {io_status_mpv_0, io_status_gva_0}; // @[CSR.scala:377:7, :649:32]
wire [2:0] read_mstatus_hi_lo_hi_hi = {read_mstatus_hi_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:649:32]
wire [5:0] read_mstatus_hi_lo_hi = {read_mstatus_hi_lo_hi_hi, 3'h2}; // @[CSR.scala:649:32]
wire [17:0] read_mstatus_hi_lo = {read_mstatus_hi_lo_hi, read_mstatus_hi_lo_lo}; // @[CSR.scala:649:32]
wire [2:0] read_mstatus_hi_hi_lo_hi_hi = {io_status_dv_0, io_status_prv_0}; // @[CSR.scala:377:7, :649:32]
wire [3:0] read_mstatus_hi_hi_lo_hi = {read_mstatus_hi_hi_lo_hi_hi, io_status_v_0}; // @[CSR.scala:377:7, :649:32]
wire [27:0] read_mstatus_hi_hi_lo = {read_mstatus_hi_hi_lo_hi, 24'h800000}; // @[CSR.scala:649:32]
wire [33:0] read_mstatus_hi_hi_hi_lo = {io_status_isa_0, io_status_dprv_0}; // @[CSR.scala:377:7, :649:32]
wire [1:0] read_mstatus_hi_hi_hi_hi_hi = {io_status_debug_0, io_status_cease_0}; // @[CSR.scala:377:7, :649:32]
wire [2:0] read_mstatus_hi_hi_hi_hi = {read_mstatus_hi_hi_hi_hi_hi, io_status_wfi_0}; // @[CSR.scala:377:7, :649:32]
wire [36:0] read_mstatus_hi_hi_hi = {read_mstatus_hi_hi_hi_hi, read_mstatus_hi_hi_hi_lo}; // @[CSR.scala:649:32]
wire [64:0] read_mstatus_hi_hi = {read_mstatus_hi_hi_hi, read_mstatus_hi_hi_lo}; // @[CSR.scala:649:32]
wire [82:0] read_mstatus_hi = {read_mstatus_hi_hi, read_mstatus_hi_lo}; // @[CSR.scala:649:32]
wire [104:0] _read_mstatus_T = {read_mstatus_hi, read_mstatus_lo}; // @[CSR.scala:649:32]
wire [63:0] read_mstatus = _read_mstatus_T[63:0]; // @[package.scala:163:13]
wire _read_mtvec_T = reg_mtvec[0]; // @[CSR.scala:512:31, :1666:41]
wire [7:0] _read_mtvec_T_1 = _read_mtvec_T ? 8'hFE : 8'h2; // @[CSR.scala:1666:{39,41}]
wire [31:0] _read_mtvec_T_3 = {24'h0, _read_mtvec_T_1}; // @[package.scala:174:41]
wire [31:0] _read_mtvec_T_4 = ~_read_mtvec_T_3; // @[package.scala:174:{37,41}]
wire [31:0] _read_mtvec_T_5 = reg_mtvec & _read_mtvec_T_4; // @[package.scala:174:{35,37}]
wire [63:0] read_mtvec = {32'h0, _read_mtvec_T_5}; // @[package.scala:138:15, :174:35]
wire _read_stvec_T = reg_stvec[0]; // @[CSR.scala:573:22, :1666:41]
wire [7:0] _read_stvec_T_1 = _read_stvec_T ? 8'hFE : 8'h2; // @[CSR.scala:1666:{39,41}]
wire [38:0] _read_stvec_T_3 = {31'h0, _read_stvec_T_1}; // @[package.scala:174:41]
wire [38:0] _read_stvec_T_4 = ~_read_stvec_T_3; // @[package.scala:174:{37,41}]
wire [38:0] _read_stvec_T_5 = reg_stvec & _read_stvec_T_4; // @[package.scala:174:{35,37}]
wire _read_stvec_T_6 = _read_stvec_T_5[38]; // @[package.scala:132:38, :174:35]
wire [24:0] _read_stvec_T_7 = {25{_read_stvec_T_6}}; // @[package.scala:132:{20,38}]
wire [63:0] read_stvec = {_read_stvec_T_7, _read_stvec_T_5}; // @[package.scala:132:{15,20}, :174:35]
wire [1:0] _GEN_4 = {reg_bp_0_control_x, reg_bp_0_control_w}; // @[CSR.scala:492:19, :655:48]
wire [1:0] read_mapping_lo_lo_hi; // @[CSR.scala:655:48]
assign read_mapping_lo_lo_hi = _GEN_4; // @[CSR.scala:655:48]
wire [1:0] newBPC_lo_lo_hi; // @[CSR.scala:1477:67]
assign newBPC_lo_lo_hi = _GEN_4; // @[CSR.scala:655:48, :1477:67]
wire [2:0] read_mapping_lo_lo = {read_mapping_lo_lo_hi, reg_bp_0_control_r}; // @[CSR.scala:492:19, :655:48]
wire [1:0] _GEN_5 = {reg_bp_0_control_s, reg_bp_0_control_u}; // @[CSR.scala:492:19, :655:48]
wire [1:0] read_mapping_lo_hi_lo; // @[CSR.scala:655:48]
assign read_mapping_lo_hi_lo = _GEN_5; // @[CSR.scala:655:48]
wire [1:0] newBPC_lo_hi_lo; // @[CSR.scala:1477:67]
assign newBPC_lo_hi_lo = _GEN_5; // @[CSR.scala:655:48, :1477:67]
wire [1:0] _GEN_6 = {reg_bp_0_control_m, 1'h0}; // @[CSR.scala:492:19, :655:48]
wire [1:0] read_mapping_lo_hi_hi; // @[CSR.scala:655:48]
assign read_mapping_lo_hi_hi = _GEN_6; // @[CSR.scala:655:48]
wire [1:0] newBPC_lo_hi_hi; // @[CSR.scala:1477:67]
assign newBPC_lo_hi_hi = _GEN_6; // @[CSR.scala:655:48, :1477:67]
wire [3:0] read_mapping_lo_hi = {read_mapping_lo_hi_hi, read_mapping_lo_hi_lo}; // @[CSR.scala:655:48]
wire [6:0] read_mapping_lo = {read_mapping_lo_hi, read_mapping_lo_lo}; // @[CSR.scala:655:48]
wire [3:0] _GEN_7 = {2'h0, reg_bp_0_control_tmatch}; // @[CSR.scala:492:19, :655:48]
wire [3:0] read_mapping_hi_lo_lo; // @[CSR.scala:655:48]
assign read_mapping_hi_lo_lo = _GEN_7; // @[CSR.scala:655:48]
wire [3:0] newBPC_hi_lo_lo; // @[CSR.scala:1477:67]
assign newBPC_hi_lo_lo = _GEN_7; // @[CSR.scala:655:48, :1477:67]
wire [1:0] _GEN_8 = {reg_bp_0_control_action, 1'h0}; // @[CSR.scala:492:19, :655:48]
wire [1:0] read_mapping_hi_lo_hi; // @[CSR.scala:655:48]
assign read_mapping_hi_lo_hi = _GEN_8; // @[CSR.scala:655:48]
wire [1:0] newBPC_hi_lo_hi; // @[CSR.scala:1477:67]
assign newBPC_hi_lo_hi = _GEN_8; // @[CSR.scala:655:48, :1477:67]
wire [5:0] read_mapping_hi_lo = {read_mapping_hi_lo_hi, read_mapping_hi_lo_lo}; // @[CSR.scala:655:48]
wire [4:0] _GEN_9 = {4'h2, reg_bp_0_control_dmode}; // @[CSR.scala:492:19, :655:48]
wire [4:0] read_mapping_hi_hi_hi; // @[CSR.scala:655:48]
assign read_mapping_hi_hi_hi = _GEN_9; // @[CSR.scala:655:48]
wire [4:0] newBPC_hi_hi_hi; // @[CSR.scala:1477:67]
assign newBPC_hi_hi_hi = _GEN_9; // @[CSR.scala:655:48, :1477:67]
wire [50:0] read_mapping_hi_hi = {read_mapping_hi_hi_hi, 46'h40000000000}; // @[CSR.scala:655:48]
wire [56:0] read_mapping_hi = {read_mapping_hi_hi, read_mapping_hi_lo}; // @[CSR.scala:655:48]
wire [63:0] read_mapping_1_2 = {read_mapping_hi, read_mapping_lo}; // @[CSR.scala:655:48]
wire _read_mapping_T = reg_bp_0_address[38]; // @[package.scala:132:38]
wire [24:0] _read_mapping_T_1 = {25{_read_mapping_T}}; // @[package.scala:132:{20,38}]
wire [63:0] read_mapping_2_2 = {_read_mapping_T_1, reg_bp_0_address}; // @[package.scala:132:{15,20}]
wire [1:0] read_mapping_lo_1 = {read_mapping_lo_hi_1, 1'h0}; // @[CSR.scala:657:47]
wire [50:0] read_mapping_3_2 = {read_mapping_hi_1, read_mapping_lo_1}; // @[CSR.scala:657:47]
wire [39:0] _read_mapping_T_2 = ~reg_mepc; // @[CSR.scala:505:21, :1665:28]
wire _read_mapping_T_3 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45]
wire _debug_csrs_T_1 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45]
wire _io_evec_T_1 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45]
wire _io_evec_T_6 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45]
wire _io_evec_T_11 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45]
wire _io_evec_T_16 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45]
wire _io_evec_T_21 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45]
wire [1:0] _read_mapping_T_4 = {~_read_mapping_T_3, 1'h1}; // @[CSR.scala:1665:{36,45}]
wire [39:0] _read_mapping_T_5 = {_read_mapping_T_2[39:2], _read_mapping_T_2[1:0] | _read_mapping_T_4}; // @[CSR.scala:1665:{28,31,36}]
wire [39:0] _read_mapping_T_6 = ~_read_mapping_T_5; // @[CSR.scala:1665:{26,31}]
wire _read_mapping_T_7 = _read_mapping_T_6[39]; // @[package.scala:132:38]
wire [23:0] _read_mapping_T_8 = {24{_read_mapping_T_7}}; // @[package.scala:132:{20,38}]
wire [63:0] read_mapping_10_2 = {_read_mapping_T_8, _read_mapping_T_6}; // @[package.scala:132:{15,20}]
wire _read_mapping_T_9 = reg_mtval[39]; // @[package.scala:132:38]
wire [23:0] _read_mapping_T_10 = {24{_read_mapping_T_9}}; // @[package.scala:132:{20,38}]
wire [63:0] read_mapping_11_2 = {_read_mapping_T_10, reg_mtval}; // @[package.scala:132:{15,20}]
wire [2:0] debug_csrs_lo_lo_hi = {2'h0, reg_dcsr_step}; // @[CSR.scala:403:25, :670:27]
wire [4:0] debug_csrs_lo_lo = {debug_csrs_lo_lo_hi, reg_dcsr_prv}; // @[CSR.scala:403:25, :670:27]
wire [3:0] debug_csrs_lo_hi_lo = {reg_dcsr_cause, reg_dcsr_v}; // @[CSR.scala:403:25, :670:27]
wire [5:0] debug_csrs_lo_hi = {2'h0, debug_csrs_lo_hi_lo}; // @[CSR.scala:670:27]
wire [10:0] debug_csrs_lo = {debug_csrs_lo_hi, debug_csrs_lo_lo}; // @[CSR.scala:670:27]
wire [1:0] debug_csrs_hi_lo_lo = {reg_dcsr_ebreaku, 1'h0}; // @[CSR.scala:403:25, :670:27]
wire [1:0] debug_csrs_hi_lo_hi = {1'h0, reg_dcsr_ebreaks}; // @[CSR.scala:403:25, :670:27]
wire [3:0] debug_csrs_hi_lo = {debug_csrs_hi_lo_hi, debug_csrs_hi_lo_lo}; // @[CSR.scala:670:27]
wire [12:0] debug_csrs_hi_hi_lo = {12'h0, reg_dcsr_ebreakm}; // @[CSR.scala:403:25, :670:27]
wire [16:0] debug_csrs_hi_hi = {4'h4, debug_csrs_hi_hi_lo}; // @[CSR.scala:670:27]
wire [20:0] debug_csrs_hi = {debug_csrs_hi_hi, debug_csrs_hi_lo}; // @[CSR.scala:670:27]
wire [31:0] debug_csrs_0_2 = {debug_csrs_hi, debug_csrs_lo}; // @[CSR.scala:670:27]
wire [39:0] _debug_csrs_T = ~reg_dpc; // @[CSR.scala:483:20, :1665:28]
wire [1:0] _debug_csrs_T_2 = {~_debug_csrs_T_1, 1'h1}; // @[CSR.scala:1665:{36,45}]
wire [39:0] _debug_csrs_T_3 = {_debug_csrs_T[39:2], _debug_csrs_T[1:0] | _debug_csrs_T_2}; // @[CSR.scala:1665:{28,31,36}]
wire [39:0] _debug_csrs_T_4 = ~_debug_csrs_T_3; // @[CSR.scala:1665:{26,31}]
wire _debug_csrs_T_5 = _debug_csrs_T_4[39]; // @[package.scala:132:38]
wire [23:0] _debug_csrs_T_6 = {24{_debug_csrs_T_5}}; // @[package.scala:132:{20,38}]
wire [63:0] debug_csrs_1_2 = {_debug_csrs_T_6, _debug_csrs_T_4}; // @[package.scala:132:{15,20}]
wire [7:0] read_fcsr = {reg_frm, reg_fflags}; // @[CSR.scala:577:23, :578:20, :689:22]
wire [3:0] lo_lo_4 = {3'h0, reg_menvcfg_fiom}; // @[CSR.scala:525:28, :742:49]
wire [6:0] lo_4 = {3'h0, lo_lo_4}; // @[CSR.scala:742:49]
wire [63:0] sie_mask = {48'h0, read_mideleg[15:0] & 16'hEFFF}; // @[CSR.scala:498:14, :750:18]
wire [63:0] read_sie = reg_mie & sie_mask; // @[CSR.scala:495:20, :750:18, :753:28]
wire [63:0] read_sip = {48'h0, sie_mask[15:0] & read_mip}; // @[CSR.scala:610:29, :750:18, :754:29]
wire [1:0] lo_lo_lo_lo = {read_sstatus_sie, 1'h0}; // @[CSR.scala:755:35, :768:51]
wire [3:0] lo_lo_lo_4 = {2'h0, lo_lo_lo_lo}; // @[CSR.scala:768:51]
wire [1:0] lo_lo_hi_lo = {read_sstatus_spie, 1'h0}; // @[CSR.scala:755:35, :768:51]
wire [1:0] lo_lo_hi_hi_hi = {read_sstatus_spp, 1'h0}; // @[CSR.scala:755:35, :768:51]
wire [2:0] lo_lo_hi_hi = {lo_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:768:51]
wire [4:0] lo_lo_hi_4 = {lo_lo_hi_hi, lo_lo_hi_lo}; // @[CSR.scala:768:51]
wire [8:0] lo_lo_5 = {lo_lo_hi_4, lo_lo_lo_4}; // @[CSR.scala:768:51]
wire [3:0] lo_hi_lo_hi = {2'h3, read_sstatus_fs}; // @[CSR.scala:755:35, :768:51]
wire [7:0] lo_hi_lo_4 = {lo_hi_lo_hi, 4'h0}; // @[CSR.scala:768:51]
wire [1:0] lo_hi_hi_lo = {read_sstatus_sum, 1'h0}; // @[CSR.scala:755:35, :768:51]
wire [2:0] lo_hi_hi_hi = {2'h0, read_sstatus_mxr}; // @[CSR.scala:755:35, :768:51]
wire [4:0] lo_hi_hi_4 = {lo_hi_hi_hi, lo_hi_hi_lo}; // @[CSR.scala:768:51]
wire [12:0] lo_hi_5 = {lo_hi_hi_4, lo_hi_lo_4}; // @[CSR.scala:768:51]
wire [21:0] lo_5 = {lo_hi_5, lo_lo_5}; // @[CSR.scala:768:51]
wire [19:0] hi_8 = {reg_satp_mode, 16'h0}; // @[CSR.scala:574:21, :774:43]
wire [39:0] _io_evec_T = ~reg_sepc; // @[CSR.scala:569:21, :1665:28]
wire [39:0] _T_30 = ~{_io_evec_T[39:2], _io_evec_T[1:0] | {~(reg_misa[2]), 1'h1}}; // @[CSR.scala:648:25, :1665:{26,28,31,36,45}]
wire [3:0] lo_lo_6 = {3'h0, reg_senvcfg_fiom}; // @[CSR.scala:526:28, :780:49]
wire [6:0] lo_6 = {3'h0, lo_lo_6}; // @[CSR.scala:780:49]
wire [1:0] lo_hi_7 = {reg_pmp_0_cfg_x, reg_pmp_0_cfg_w}; // @[package.scala:45:36]
wire [2:0] lo_7 = {lo_hi_7, reg_pmp_0_cfg_r}; // @[package.scala:45:36]
wire [2:0] hi_hi_7 = {reg_pmp_0_cfg_l, 2'h0}; // @[package.scala:45:36]
wire [4:0] hi_10 = {hi_hi_7, reg_pmp_0_cfg_a}; // @[package.scala:45:36]
wire [1:0] lo_hi_8 = {reg_pmp_1_cfg_x, reg_pmp_1_cfg_w}; // @[package.scala:45:36]
wire [2:0] lo_8 = {lo_hi_8, reg_pmp_1_cfg_r}; // @[package.scala:45:36]
wire [2:0] hi_hi_8 = {reg_pmp_1_cfg_l, 2'h0}; // @[package.scala:45:36]
wire [4:0] hi_11 = {hi_hi_8, reg_pmp_1_cfg_a}; // @[package.scala:45:36]
wire [1:0] lo_hi_9 = {reg_pmp_2_cfg_x, reg_pmp_2_cfg_w}; // @[package.scala:45:36]
wire [2:0] lo_9 = {lo_hi_9, reg_pmp_2_cfg_r}; // @[package.scala:45:36]
wire [2:0] hi_hi_9 = {reg_pmp_2_cfg_l, 2'h0}; // @[package.scala:45:36]
wire [4:0] hi_12 = {hi_hi_9, reg_pmp_2_cfg_a}; // @[package.scala:45:36]
wire [1:0] lo_hi_10 = {reg_pmp_3_cfg_x, reg_pmp_3_cfg_w}; // @[package.scala:45:36]
wire [2:0] lo_10 = {lo_hi_10, reg_pmp_3_cfg_r}; // @[package.scala:45:36]
wire [2:0] hi_hi_10 = {reg_pmp_3_cfg_l, 2'h0}; // @[package.scala:45:36]
wire [4:0] hi_13 = {hi_hi_10, reg_pmp_3_cfg_a}; // @[package.scala:45:36]
wire [1:0] lo_hi_11 = {reg_pmp_4_cfg_x, reg_pmp_4_cfg_w}; // @[package.scala:45:36]
wire [2:0] lo_11 = {lo_hi_11, reg_pmp_4_cfg_r}; // @[package.scala:45:36]
wire [2:0] hi_hi_11 = {reg_pmp_4_cfg_l, 2'h0}; // @[package.scala:45:36]
wire [4:0] hi_14 = {hi_hi_11, reg_pmp_4_cfg_a}; // @[package.scala:45:36]
wire [1:0] lo_hi_12 = {reg_pmp_5_cfg_x, reg_pmp_5_cfg_w}; // @[package.scala:45:36]
wire [2:0] lo_12 = {lo_hi_12, reg_pmp_5_cfg_r}; // @[package.scala:45:36]
wire [2:0] hi_hi_12 = {reg_pmp_5_cfg_l, 2'h0}; // @[package.scala:45:36]
wire [4:0] hi_15 = {hi_hi_12, reg_pmp_5_cfg_a}; // @[package.scala:45:36]
wire [1:0] lo_hi_13 = {reg_pmp_6_cfg_x, reg_pmp_6_cfg_w}; // @[package.scala:45:36]
wire [2:0] lo_13 = {lo_hi_13, reg_pmp_6_cfg_r}; // @[package.scala:45:36]
wire [2:0] hi_hi_13 = {reg_pmp_6_cfg_l, 2'h0}; // @[package.scala:45:36]
wire [4:0] hi_16 = {hi_hi_13, reg_pmp_6_cfg_a}; // @[package.scala:45:36]
wire [1:0] lo_hi_14 = {reg_pmp_7_cfg_x, reg_pmp_7_cfg_w}; // @[package.scala:45:36]
wire [2:0] lo_14 = {lo_hi_14, reg_pmp_7_cfg_r}; // @[package.scala:45:36]
wire [2:0] hi_hi_14 = {reg_pmp_7_cfg_l, 2'h0}; // @[package.scala:45:36]
wire [4:0] hi_17 = {hi_hi_14, reg_pmp_7_cfg_a}; // @[package.scala:45:36]
wire [15:0] lo_lo_7 = {hi_11, lo_8, hi_10, lo_7}; // @[package.scala:45:{27,36}]
wire [15:0] lo_hi_15 = {hi_13, lo_10, hi_12, lo_9}; // @[package.scala:45:{27,36}]
wire [31:0] lo_15 = {lo_hi_15, lo_lo_7}; // @[package.scala:45:27]
wire [15:0] hi_lo_7 = {hi_15, lo_12, hi_14, lo_11}; // @[package.scala:45:{27,36}]
wire [15:0] hi_hi_15 = {hi_17, lo_14, hi_16, lo_13}; // @[package.scala:45:{27,36}]
wire [31:0] hi_18 = {hi_hi_15, hi_lo_7}; // @[package.scala:45:27]
reg [63:0] reg_custom_0; // @[CSR.scala:798:43]
assign io_customCSRs_0_value_0 = reg_custom_0; // @[CSR.scala:377:7, :798:43]
wire _reg_custom_read_T = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26]
wire _reg_custom_read_T_1 = io_rw_addr_0 == 12'h7C1; // @[CSR.scala:377:7, :799:50]
assign reg_custom_read = _reg_custom_read_T & _reg_custom_read_T_1; // @[CSR.scala:799:{26,36,50}]
assign io_customCSRs_0_ren_0 = reg_custom_read; // @[CSR.scala:377:7, :799:36]
reg [63:0] reg_custom_1; // @[CSR.scala:798:43]
assign io_customCSRs_1_value_0 = reg_custom_1; // @[CSR.scala:377:7, :798:43]
wire [63:0] _reg_custom_1_T_2 = reg_custom_1; // @[CSR.scala:798:43, :1506:38]
wire [63:0] _reg_custom_1_T_6 = reg_custom_1; // @[CSR.scala:798:43, :1531:39]
wire _reg_custom_read_T_2 = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26]
wire _reg_custom_read_T_3 = io_rw_addr_0 == 12'hF12; // @[CSR.scala:377:7, :799:50]
assign reg_custom_read_1 = _reg_custom_read_T_2 & _reg_custom_read_T_3; // @[CSR.scala:799:{26,36,50}]
assign io_customCSRs_1_ren_0 = reg_custom_read_1; // @[CSR.scala:377:7, :799:36]
reg [63:0] reg_custom_2; // @[CSR.scala:798:43]
assign io_customCSRs_2_value_0 = reg_custom_2; // @[CSR.scala:377:7, :798:43]
wire [63:0] _reg_custom_2_T_2 = reg_custom_2; // @[CSR.scala:798:43, :1506:38]
wire [63:0] _reg_custom_2_T_6 = reg_custom_2; // @[CSR.scala:798:43, :1531:39]
wire _reg_custom_read_T_4 = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26]
wire _reg_custom_read_T_5 = io_rw_addr_0 == 12'hF11; // @[CSR.scala:377:7, :799:50]
assign reg_custom_read_2 = _reg_custom_read_T_4 & _reg_custom_read_T_5; // @[CSR.scala:799:{26,36,50}]
assign io_customCSRs_2_ren_0 = reg_custom_read_2; // @[CSR.scala:377:7, :799:36]
reg [63:0] reg_custom_3; // @[CSR.scala:798:43]
assign io_customCSRs_3_value_0 = reg_custom_3; // @[CSR.scala:377:7, :798:43]
wire [63:0] _reg_custom_3_T_2 = reg_custom_3; // @[CSR.scala:798:43, :1506:38]
wire [63:0] _reg_custom_3_T_6 = reg_custom_3; // @[CSR.scala:798:43, :1531:39]
wire _reg_custom_read_T_6 = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26]
wire _reg_custom_read_T_7 = io_rw_addr_0 == 12'hF13; // @[CSR.scala:377:7, :799:50]
assign reg_custom_read_3 = _reg_custom_read_T_6 & _reg_custom_read_T_7; // @[CSR.scala:799:{26,36,50}]
assign io_customCSRs_3_ren_0 = reg_custom_read_3; // @[CSR.scala:377:7, :799:36]
wire [12:0] decoded_addr_addr = {io_status_v_0, io_rw_addr_0}; // @[CSR.scala:377:7, :851:19]
wire [11:0] decoded_addr_decoded_decoded_plaInput; // @[pla.scala:77:22]
wire [11:0] decoded_addr_decoded_decoded_invInputs = ~decoded_addr_decoded_decoded_plaInput; // @[pla.scala:77:22, :78:21]
wire [149:0] decoded_addr_decoded_decoded_invMatrixOutputs; // @[pla.scala:120:37]
wire [149:0] decoded_addr_decoded_decoded; // @[pla.scala:81:23]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T = {decoded_addr_decoded_decoded_andMatrixOutputs_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_138_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_132 = decoded_addr_decoded_decoded_andMatrixOutputs_138_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_134_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_131 = decoded_addr_decoded_decoded_andMatrixOutputs_134_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_41_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_130 = decoded_addr_decoded_decoded_andMatrixOutputs_41_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53]
wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_1_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_35 = decoded_addr_decoded_decoded_andMatrixOutputs_1_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_89_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_33 = decoded_addr_decoded_decoded_andMatrixOutputs_89_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_123_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_27 = decoded_addr_decoded_decoded_andMatrixOutputs_123_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_27_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_26 = decoded_addr_decoded_decoded_andMatrixOutputs_27_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53]
wire [8:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_0_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_23 = decoded_addr_decoded_decoded_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_92_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_32 = decoded_addr_decoded_decoded_andMatrixOutputs_92_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_59_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_28 = decoded_addr_decoded_decoded_andMatrixOutputs_59_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_24_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_31 = decoded_addr_decoded_decoded_andMatrixOutputs_24_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_116_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_30 = decoded_addr_decoded_decoded_andMatrixOutputs_116_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53]
wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_121_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_34 = decoded_addr_decoded_decoded_andMatrixOutputs_121_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13}; // @[pla.scala:91:29, :98:53]
wire [4:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_74_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_29 = decoded_addr_decoded_decoded_andMatrixOutputs_74_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_114_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_144 = decoded_addr_decoded_decoded_andMatrixOutputs_114_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_104_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_145 = decoded_addr_decoded_decoded_andMatrixOutputs_104_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_82_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_24 = decoded_addr_decoded_decoded_andMatrixOutputs_82_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_28_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_25 = decoded_addr_decoded_decoded_andMatrixOutputs_28_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_91_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_141 = decoded_addr_decoded_decoded_andMatrixOutputs_91_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_68_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_143 = decoded_addr_decoded_decoded_andMatrixOutputs_68_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_84_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_39 = decoded_addr_decoded_decoded_andMatrixOutputs_84_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53]
wire [8:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_40_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_36 = decoded_addr_decoded_decoded_andMatrixOutputs_40_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_34_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_129 = decoded_addr_decoded_decoded_andMatrixOutputs_34_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_136_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_126 = decoded_addr_decoded_decoded_andMatrixOutputs_136_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_55_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_123 = decoded_addr_decoded_decoded_andMatrixOutputs_55_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_105_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_120 = decoded_addr_decoded_decoded_andMatrixOutputs_105_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_109_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_117 = decoded_addr_decoded_decoded_andMatrixOutputs_109_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_7_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_114 = decoded_addr_decoded_decoded_andMatrixOutputs_7_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_47_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_111 = decoded_addr_decoded_decoded_andMatrixOutputs_47_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_141_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_108 = decoded_addr_decoded_decoded_andMatrixOutputs_141_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_11_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_105 = decoded_addr_decoded_decoded_andMatrixOutputs_11_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_118_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_102 = decoded_addr_decoded_decoded_andMatrixOutputs_118_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_120_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_99 = decoded_addr_decoded_decoded_andMatrixOutputs_120_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_139_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_96 = decoded_addr_decoded_decoded_andMatrixOutputs_139_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_86_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_93 = decoded_addr_decoded_decoded_andMatrixOutputs_86_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_8_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_90 = decoded_addr_decoded_decoded_andMatrixOutputs_8_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_61_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_87 = decoded_addr_decoded_decoded_andMatrixOutputs_61_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_83_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_84 = decoded_addr_decoded_decoded_andMatrixOutputs_83_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_129_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_81 = decoded_addr_decoded_decoded_andMatrixOutputs_129_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_17_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_78 = decoded_addr_decoded_decoded_andMatrixOutputs_17_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_87_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_75 = decoded_addr_decoded_decoded_andMatrixOutputs_87_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_133_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_72 = decoded_addr_decoded_decoded_andMatrixOutputs_133_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_142_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_69 = decoded_addr_decoded_decoded_andMatrixOutputs_142_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_22_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_66 = decoded_addr_decoded_decoded_andMatrixOutputs_22_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_94_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_63 = decoded_addr_decoded_decoded_andMatrixOutputs_94_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_65_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_60 = decoded_addr_decoded_decoded_andMatrixOutputs_65_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_36_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_57 = decoded_addr_decoded_decoded_andMatrixOutputs_36_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_33_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_54 = decoded_addr_decoded_decoded_andMatrixOutputs_33_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_63_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_51 = decoded_addr_decoded_decoded_andMatrixOutputs_63_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_39_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_48 = decoded_addr_decoded_decoded_andMatrixOutputs_39_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_32_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_45 = decoded_addr_decoded_decoded_andMatrixOutputs_32_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_144_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_42 = decoded_addr_decoded_decoded_andMatrixOutputs_144_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_66_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_140 = decoded_addr_decoded_decoded_andMatrixOutputs_66_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_106_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_139 = decoded_addr_decoded_decoded_andMatrixOutputs_106_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_80_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_137 = decoded_addr_decoded_decoded_andMatrixOutputs_80_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_122_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_138 = decoded_addr_decoded_decoded_andMatrixOutputs_122_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53]
wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_119_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_142 = decoded_addr_decoded_decoded_andMatrixOutputs_119_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_67_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_22 = decoded_addr_decoded_decoded_andMatrixOutputs_67_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_48_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_21 = decoded_addr_decoded_decoded_andMatrixOutputs_48_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_10_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_20 = decoded_addr_decoded_decoded_andMatrixOutputs_10_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_45_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_19 = decoded_addr_decoded_decoded_andMatrixOutputs_45_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_18_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_18 = decoded_addr_decoded_decoded_andMatrixOutputs_18_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_88_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_17 = decoded_addr_decoded_decoded_andMatrixOutputs_88_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_57_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_16 = decoded_addr_decoded_decoded_andMatrixOutputs_57_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_85_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_15 = decoded_addr_decoded_decoded_andMatrixOutputs_85_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_100_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_14 = decoded_addr_decoded_decoded_andMatrixOutputs_100_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_111_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_13 = decoded_addr_decoded_decoded_andMatrixOutputs_111_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_93_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_12 = decoded_addr_decoded_decoded_andMatrixOutputs_93_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_137_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_11 = decoded_addr_decoded_decoded_andMatrixOutputs_137_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_72_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_10 = decoded_addr_decoded_decoded_andMatrixOutputs_72_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_42_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_9 = decoded_addr_decoded_decoded_andMatrixOutputs_42_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_145_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_8 = decoded_addr_decoded_decoded_andMatrixOutputs_145_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_98_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_7 = decoded_addr_decoded_decoded_andMatrixOutputs_98_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_113_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_6 = decoded_addr_decoded_decoded_andMatrixOutputs_113_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_149_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_5 = decoded_addr_decoded_decoded_andMatrixOutputs_149_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_2_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_149 = decoded_addr_decoded_decoded_andMatrixOutputs_2_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_146_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_148 = decoded_addr_decoded_decoded_andMatrixOutputs_146_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_77}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_128_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_77; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_147 = decoded_addr_decoded_decoded_andMatrixOutputs_128_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_78}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_56_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_78; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_146 = decoded_addr_decoded_decoded_andMatrixOutputs_56_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_79}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_3_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_79; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_135 = decoded_addr_decoded_decoded_andMatrixOutputs_3_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_80}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_50_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_80; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_134 = decoded_addr_decoded_decoded_andMatrixOutputs_50_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_lo_81}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_23_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_81; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_133 = decoded_addr_decoded_decoded_andMatrixOutputs_23_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82}; // @[pla.scala:90:45, :98:53]
wire [5:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_82}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_12_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_82; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_4 = decoded_addr_decoded_decoded_andMatrixOutputs_12_2; // @[pla.scala:98:70, :114:36]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_83}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_76_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_83; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_128 = decoded_addr_decoded_decoded_andMatrixOutputs_76_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_84}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_79_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_84; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_127 = decoded_addr_decoded_decoded_andMatrixOutputs_79_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_85}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_95_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_85; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_125 = decoded_addr_decoded_decoded_andMatrixOutputs_95_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_86}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_26_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_86; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_122 = decoded_addr_decoded_decoded_andMatrixOutputs_26_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_87}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_124_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_87; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_119 = decoded_addr_decoded_decoded_andMatrixOutputs_124_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_88}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_147_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_88; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_116 = decoded_addr_decoded_decoded_andMatrixOutputs_147_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_89}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_77_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_89; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_113 = decoded_addr_decoded_decoded_andMatrixOutputs_77_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_90}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_140_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_90; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_110 = decoded_addr_decoded_decoded_andMatrixOutputs_140_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_91}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_44_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_91; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_107 = decoded_addr_decoded_decoded_andMatrixOutputs_44_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_92}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_31_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_92; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_104 = decoded_addr_decoded_decoded_andMatrixOutputs_31_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_93}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_62_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_93; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_101 = decoded_addr_decoded_decoded_andMatrixOutputs_62_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_94}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_58_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_94; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_98 = decoded_addr_decoded_decoded_andMatrixOutputs_58_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_95}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_132_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_95; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_95 = decoded_addr_decoded_decoded_andMatrixOutputs_132_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_96}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_9_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_96; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_92 = decoded_addr_decoded_decoded_andMatrixOutputs_9_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_97}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_115_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_97; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_89 = decoded_addr_decoded_decoded_andMatrixOutputs_115_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_98}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_5_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_98; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_86 = decoded_addr_decoded_decoded_andMatrixOutputs_5_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_99}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_71_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_99; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_83 = decoded_addr_decoded_decoded_andMatrixOutputs_71_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_100}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_130_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_100; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_80 = decoded_addr_decoded_decoded_andMatrixOutputs_130_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_101}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_102_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_101; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_77 = decoded_addr_decoded_decoded_andMatrixOutputs_102_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_102}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_4_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_102; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_74 = decoded_addr_decoded_decoded_andMatrixOutputs_4_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_103}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_29_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_103; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_71 = decoded_addr_decoded_decoded_andMatrixOutputs_29_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_104}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_16_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_104; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_68 = decoded_addr_decoded_decoded_andMatrixOutputs_16_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_105}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_143_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_105; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_65 = decoded_addr_decoded_decoded_andMatrixOutputs_143_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_106}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_131_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_106; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_62 = decoded_addr_decoded_decoded_andMatrixOutputs_131_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_107}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_14_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_107; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_59 = decoded_addr_decoded_decoded_andMatrixOutputs_14_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_108}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_90_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_108; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_56 = decoded_addr_decoded_decoded_andMatrixOutputs_90_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_109}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_97_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_109; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_53 = decoded_addr_decoded_decoded_andMatrixOutputs_97_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_110}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_60_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_110; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_50 = decoded_addr_decoded_decoded_andMatrixOutputs_60_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_111}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_96_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_111; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_47 = decoded_addr_decoded_decoded_andMatrixOutputs_96_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_112}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_54_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_112; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_44 = decoded_addr_decoded_decoded_andMatrixOutputs_54_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_113}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_126_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_113; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_41 = decoded_addr_decoded_decoded_andMatrixOutputs_126_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_114}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_49_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_114; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_38 = decoded_addr_decoded_decoded_andMatrixOutputs_49_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_115}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_52_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_115; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_37 = decoded_addr_decoded_decoded_andMatrixOutputs_52_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_116}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_20_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_116; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_124 = decoded_addr_decoded_decoded_andMatrixOutputs_20_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_117}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_107_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_117; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_121 = decoded_addr_decoded_decoded_andMatrixOutputs_107_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_118}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_6_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_118; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_118 = decoded_addr_decoded_decoded_andMatrixOutputs_6_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_119}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_21_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_119; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_115 = decoded_addr_decoded_decoded_andMatrixOutputs_21_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_120}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_30_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_120; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_112 = decoded_addr_decoded_decoded_andMatrixOutputs_30_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_121}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_127_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_121; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_109 = decoded_addr_decoded_decoded_andMatrixOutputs_127_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_122}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_35_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_122; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_106 = decoded_addr_decoded_decoded_andMatrixOutputs_35_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_123}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_73_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_123; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_103 = decoded_addr_decoded_decoded_andMatrixOutputs_73_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_124}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_53_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_124; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_100 = decoded_addr_decoded_decoded_andMatrixOutputs_53_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_125}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_135_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_125; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_97 = decoded_addr_decoded_decoded_andMatrixOutputs_135_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_126}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_37_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_126; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_94 = decoded_addr_decoded_decoded_andMatrixOutputs_37_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_127}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_25_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_127; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_91 = decoded_addr_decoded_decoded_andMatrixOutputs_25_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_128}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_64_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_128; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_88 = decoded_addr_decoded_decoded_andMatrixOutputs_64_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_129}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_19_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_129; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_85 = decoded_addr_decoded_decoded_andMatrixOutputs_19_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_130}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_112_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_130; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_82 = decoded_addr_decoded_decoded_andMatrixOutputs_112_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_131}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_108_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_131; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_79 = decoded_addr_decoded_decoded_andMatrixOutputs_108_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_132}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_148_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_132; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_76 = decoded_addr_decoded_decoded_andMatrixOutputs_148_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_133}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_69_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_133; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_73 = decoded_addr_decoded_decoded_andMatrixOutputs_69_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_134}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_103_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_134; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_70 = decoded_addr_decoded_decoded_andMatrixOutputs_103_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_135}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_99_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_135; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_67 = decoded_addr_decoded_decoded_andMatrixOutputs_99_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_136}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_125_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_136; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_64 = decoded_addr_decoded_decoded_andMatrixOutputs_125_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_137}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_117_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_137; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_61 = decoded_addr_decoded_decoded_andMatrixOutputs_117_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_138}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_46_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_138; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_58 = decoded_addr_decoded_decoded_andMatrixOutputs_46_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_139}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_15_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_139; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_55 = decoded_addr_decoded_decoded_andMatrixOutputs_15_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_140}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_51_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_140; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_52 = decoded_addr_decoded_decoded_andMatrixOutputs_51_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_141}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_43_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_141; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_49 = decoded_addr_decoded_decoded_andMatrixOutputs_43_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_142}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_70_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_142; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_46 = decoded_addr_decoded_decoded_andMatrixOutputs_70_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_143}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_78_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_143; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_43 = decoded_addr_decoded_decoded_andMatrixOutputs_78_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_144}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_110_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_144; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_40 = decoded_addr_decoded_decoded_andMatrixOutputs_110_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143}; // @[pla.scala:98:53]
wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_145}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_101_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_145; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_2 = decoded_addr_decoded_decoded_andMatrixOutputs_101_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_146}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_38_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_146; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_3 = decoded_addr_decoded_decoded_andMatrixOutputs_38_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_147}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_13_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_147; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_1 = decoded_addr_decoded_decoded_andMatrixOutputs_13_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_148}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_81_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_148; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_136 = decoded_addr_decoded_decoded_andMatrixOutputs_81_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131}; // @[pla.scala:90:45, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147}; // @[pla.scala:98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149}; // @[pla.scala:90:45, :98:53]
wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147}; // @[pla.scala:98:53]
wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_lo_149}; // @[pla.scala:98:53]
wire decoded_addr_decoded_decoded_andMatrixOutputs_75_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_149; // @[pla.scala:98:{53,70}]
wire _decoded_addr_decoded_decoded_orMatrixOutputs_T = decoded_addr_decoded_decoded_andMatrixOutputs_75_2; // @[pla.scala:98:70, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_1, _decoded_addr_decoded_decoded_orMatrixOutputs_T}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_3, _decoded_addr_decoded_decoded_orMatrixOutputs_T_2}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_5, _decoded_addr_decoded_decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_8, _decoded_addr_decoded_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_6}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo}; // @[pla.scala:102:36]
wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_10, _decoded_addr_decoded_decoded_orMatrixOutputs_T_9}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_12, _decoded_addr_decoded_decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_14, _decoded_addr_decoded_decoded_orMatrixOutputs_T_13}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_17, _decoded_addr_decoded_decoded_orMatrixOutputs_T_16}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_15}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo}; // @[pla.scala:102:36]
wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:102:36]
wire [17:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_19, _decoded_addr_decoded_decoded_orMatrixOutputs_T_18}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_21, _decoded_addr_decoded_decoded_orMatrixOutputs_T_20}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_23, _decoded_addr_decoded_decoded_orMatrixOutputs_T_22}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_26, _decoded_addr_decoded_decoded_orMatrixOutputs_T_25}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_24}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo}; // @[pla.scala:102:36]
wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_28, _decoded_addr_decoded_decoded_orMatrixOutputs_T_27}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_31, _decoded_addr_decoded_decoded_orMatrixOutputs_T_30}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_29}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_33, _decoded_addr_decoded_decoded_orMatrixOutputs_T_32}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_36, _decoded_addr_decoded_decoded_orMatrixOutputs_T_35}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_34}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo}; // @[pla.scala:102:36]
wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:102:36]
wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:102:36]
wire [36:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_38, _decoded_addr_decoded_decoded_orMatrixOutputs_T_37}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_40, _decoded_addr_decoded_decoded_orMatrixOutputs_T_39}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_42, _decoded_addr_decoded_decoded_orMatrixOutputs_T_41}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_45, _decoded_addr_decoded_decoded_orMatrixOutputs_T_44}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_43}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo}; // @[pla.scala:102:36]
wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_47, _decoded_addr_decoded_decoded_orMatrixOutputs_T_46}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_50, _decoded_addr_decoded_decoded_orMatrixOutputs_T_49}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_48}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_52, _decoded_addr_decoded_decoded_orMatrixOutputs_T_51}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_55, _decoded_addr_decoded_decoded_orMatrixOutputs_T_54}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_53}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo}; // @[pla.scala:102:36]
wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:102:36]
wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_57, _decoded_addr_decoded_decoded_orMatrixOutputs_T_56}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_59, _decoded_addr_decoded_decoded_orMatrixOutputs_T_58}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_61, _decoded_addr_decoded_decoded_orMatrixOutputs_T_60}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_64, _decoded_addr_decoded_decoded_orMatrixOutputs_T_63}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_62}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo}; // @[pla.scala:102:36]
wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_66, _decoded_addr_decoded_decoded_orMatrixOutputs_T_65}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_69, _decoded_addr_decoded_decoded_orMatrixOutputs_T_68}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_67}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_71, _decoded_addr_decoded_decoded_orMatrixOutputs_T_70}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_74, _decoded_addr_decoded_decoded_orMatrixOutputs_T_73}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_72}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo}; // @[pla.scala:102:36]
wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:102:36]
wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:102:36]
wire [37:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:102:36]
wire [74:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_76, _decoded_addr_decoded_decoded_orMatrixOutputs_T_75}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_78, _decoded_addr_decoded_decoded_orMatrixOutputs_T_77}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_80, _decoded_addr_decoded_decoded_orMatrixOutputs_T_79}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_83, _decoded_addr_decoded_decoded_orMatrixOutputs_T_82}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_81}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo}; // @[pla.scala:102:36]
wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_85, _decoded_addr_decoded_decoded_orMatrixOutputs_T_84}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_87, _decoded_addr_decoded_decoded_orMatrixOutputs_T_86}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_89, _decoded_addr_decoded_decoded_orMatrixOutputs_T_88}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_92, _decoded_addr_decoded_decoded_orMatrixOutputs_T_91}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_90}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo}; // @[pla.scala:102:36]
wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:102:36]
wire [17:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_94, _decoded_addr_decoded_decoded_orMatrixOutputs_T_93}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_96, _decoded_addr_decoded_decoded_orMatrixOutputs_T_95}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_98, _decoded_addr_decoded_decoded_orMatrixOutputs_T_97}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_101, _decoded_addr_decoded_decoded_orMatrixOutputs_T_100}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_99}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo}; // @[pla.scala:102:36]
wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_103, _decoded_addr_decoded_decoded_orMatrixOutputs_T_102}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_106, _decoded_addr_decoded_decoded_orMatrixOutputs_T_105}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_104}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_108, _decoded_addr_decoded_decoded_orMatrixOutputs_T_107}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_111, _decoded_addr_decoded_decoded_orMatrixOutputs_T_110}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_109}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo}; // @[pla.scala:102:36]
wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:102:36]
wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:102:36]
wire [36:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_113, _decoded_addr_decoded_decoded_orMatrixOutputs_T_112}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_115, _decoded_addr_decoded_decoded_orMatrixOutputs_T_114}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_117, _decoded_addr_decoded_decoded_orMatrixOutputs_T_116}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_120, _decoded_addr_decoded_decoded_orMatrixOutputs_T_119}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_118}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo}; // @[pla.scala:102:36]
wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_122, _decoded_addr_decoded_decoded_orMatrixOutputs_T_121}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_125, _decoded_addr_decoded_decoded_orMatrixOutputs_T_124}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_123}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_127, _decoded_addr_decoded_decoded_orMatrixOutputs_T_126}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_130, _decoded_addr_decoded_decoded_orMatrixOutputs_T_129}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_128}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo}; // @[pla.scala:102:36]
wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:102:36]
wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_132, _decoded_addr_decoded_decoded_orMatrixOutputs_T_131}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_134, _decoded_addr_decoded_decoded_orMatrixOutputs_T_133}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_136, _decoded_addr_decoded_decoded_orMatrixOutputs_T_135}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_139, _decoded_addr_decoded_decoded_orMatrixOutputs_T_138}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_137}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo}; // @[pla.scala:102:36]
wire [8:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_141, _decoded_addr_decoded_decoded_orMatrixOutputs_T_140}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_144, _decoded_addr_decoded_decoded_orMatrixOutputs_T_143}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_142}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo}; // @[pla.scala:102:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_146, _decoded_addr_decoded_decoded_orMatrixOutputs_T_145}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_149, _decoded_addr_decoded_decoded_orMatrixOutputs_T_148}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_147}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo}; // @[pla.scala:102:36]
wire [9:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:102:36]
wire [18:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:102:36]
wire [37:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:102:36]
wire [74:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:102:36]
wire [149:0] decoded_addr_decoded_decoded_orMatrixOutputs = {decoded_addr_decoded_decoded_orMatrixOutputs_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo}; // @[pla.scala:102:36]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T = decoded_addr_decoded_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_1 = decoded_addr_decoded_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_2 = decoded_addr_decoded_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_3 = decoded_addr_decoded_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_4 = decoded_addr_decoded_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_5 = decoded_addr_decoded_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_6 = decoded_addr_decoded_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_7 = decoded_addr_decoded_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_8 = decoded_addr_decoded_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_9 = decoded_addr_decoded_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_10 = decoded_addr_decoded_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_11 = decoded_addr_decoded_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_12 = decoded_addr_decoded_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_13 = decoded_addr_decoded_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_14 = decoded_addr_decoded_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_15 = decoded_addr_decoded_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_16 = decoded_addr_decoded_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_17 = decoded_addr_decoded_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_18 = decoded_addr_decoded_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_19 = decoded_addr_decoded_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_20 = decoded_addr_decoded_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_21 = decoded_addr_decoded_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_22 = decoded_addr_decoded_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_23 = decoded_addr_decoded_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_24 = decoded_addr_decoded_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_25 = decoded_addr_decoded_decoded_orMatrixOutputs[25]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_26 = decoded_addr_decoded_decoded_orMatrixOutputs[26]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_27 = decoded_addr_decoded_decoded_orMatrixOutputs[27]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_28 = decoded_addr_decoded_decoded_orMatrixOutputs[28]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_29 = decoded_addr_decoded_decoded_orMatrixOutputs[29]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_30 = decoded_addr_decoded_decoded_orMatrixOutputs[30]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_31 = decoded_addr_decoded_decoded_orMatrixOutputs[31]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_32 = decoded_addr_decoded_decoded_orMatrixOutputs[32]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_33 = decoded_addr_decoded_decoded_orMatrixOutputs[33]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_34 = decoded_addr_decoded_decoded_orMatrixOutputs[34]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_35 = decoded_addr_decoded_decoded_orMatrixOutputs[35]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_36 = decoded_addr_decoded_decoded_orMatrixOutputs[36]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_37 = decoded_addr_decoded_decoded_orMatrixOutputs[37]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_38 = decoded_addr_decoded_decoded_orMatrixOutputs[38]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_39 = decoded_addr_decoded_decoded_orMatrixOutputs[39]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_40 = decoded_addr_decoded_decoded_orMatrixOutputs[40]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_41 = decoded_addr_decoded_decoded_orMatrixOutputs[41]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_42 = decoded_addr_decoded_decoded_orMatrixOutputs[42]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_43 = decoded_addr_decoded_decoded_orMatrixOutputs[43]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_44 = decoded_addr_decoded_decoded_orMatrixOutputs[44]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_45 = decoded_addr_decoded_decoded_orMatrixOutputs[45]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_46 = decoded_addr_decoded_decoded_orMatrixOutputs[46]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_47 = decoded_addr_decoded_decoded_orMatrixOutputs[47]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_48 = decoded_addr_decoded_decoded_orMatrixOutputs[48]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_49 = decoded_addr_decoded_decoded_orMatrixOutputs[49]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_50 = decoded_addr_decoded_decoded_orMatrixOutputs[50]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_51 = decoded_addr_decoded_decoded_orMatrixOutputs[51]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_52 = decoded_addr_decoded_decoded_orMatrixOutputs[52]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_53 = decoded_addr_decoded_decoded_orMatrixOutputs[53]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_54 = decoded_addr_decoded_decoded_orMatrixOutputs[54]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_55 = decoded_addr_decoded_decoded_orMatrixOutputs[55]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_56 = decoded_addr_decoded_decoded_orMatrixOutputs[56]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_57 = decoded_addr_decoded_decoded_orMatrixOutputs[57]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_58 = decoded_addr_decoded_decoded_orMatrixOutputs[58]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_59 = decoded_addr_decoded_decoded_orMatrixOutputs[59]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_60 = decoded_addr_decoded_decoded_orMatrixOutputs[60]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_61 = decoded_addr_decoded_decoded_orMatrixOutputs[61]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_62 = decoded_addr_decoded_decoded_orMatrixOutputs[62]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_63 = decoded_addr_decoded_decoded_orMatrixOutputs[63]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_64 = decoded_addr_decoded_decoded_orMatrixOutputs[64]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_65 = decoded_addr_decoded_decoded_orMatrixOutputs[65]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_66 = decoded_addr_decoded_decoded_orMatrixOutputs[66]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_67 = decoded_addr_decoded_decoded_orMatrixOutputs[67]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_68 = decoded_addr_decoded_decoded_orMatrixOutputs[68]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_69 = decoded_addr_decoded_decoded_orMatrixOutputs[69]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_70 = decoded_addr_decoded_decoded_orMatrixOutputs[70]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_71 = decoded_addr_decoded_decoded_orMatrixOutputs[71]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_72 = decoded_addr_decoded_decoded_orMatrixOutputs[72]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_73 = decoded_addr_decoded_decoded_orMatrixOutputs[73]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_74 = decoded_addr_decoded_decoded_orMatrixOutputs[74]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_75 = decoded_addr_decoded_decoded_orMatrixOutputs[75]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_76 = decoded_addr_decoded_decoded_orMatrixOutputs[76]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_77 = decoded_addr_decoded_decoded_orMatrixOutputs[77]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_78 = decoded_addr_decoded_decoded_orMatrixOutputs[78]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_79 = decoded_addr_decoded_decoded_orMatrixOutputs[79]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_80 = decoded_addr_decoded_decoded_orMatrixOutputs[80]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_81 = decoded_addr_decoded_decoded_orMatrixOutputs[81]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_82 = decoded_addr_decoded_decoded_orMatrixOutputs[82]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_83 = decoded_addr_decoded_decoded_orMatrixOutputs[83]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_84 = decoded_addr_decoded_decoded_orMatrixOutputs[84]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_85 = decoded_addr_decoded_decoded_orMatrixOutputs[85]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_86 = decoded_addr_decoded_decoded_orMatrixOutputs[86]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_87 = decoded_addr_decoded_decoded_orMatrixOutputs[87]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_88 = decoded_addr_decoded_decoded_orMatrixOutputs[88]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_89 = decoded_addr_decoded_decoded_orMatrixOutputs[89]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_90 = decoded_addr_decoded_decoded_orMatrixOutputs[90]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_91 = decoded_addr_decoded_decoded_orMatrixOutputs[91]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_92 = decoded_addr_decoded_decoded_orMatrixOutputs[92]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_93 = decoded_addr_decoded_decoded_orMatrixOutputs[93]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_94 = decoded_addr_decoded_decoded_orMatrixOutputs[94]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_95 = decoded_addr_decoded_decoded_orMatrixOutputs[95]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_96 = decoded_addr_decoded_decoded_orMatrixOutputs[96]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_97 = decoded_addr_decoded_decoded_orMatrixOutputs[97]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_98 = decoded_addr_decoded_decoded_orMatrixOutputs[98]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_99 = decoded_addr_decoded_decoded_orMatrixOutputs[99]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_100 = decoded_addr_decoded_decoded_orMatrixOutputs[100]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_101 = decoded_addr_decoded_decoded_orMatrixOutputs[101]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_102 = decoded_addr_decoded_decoded_orMatrixOutputs[102]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_103 = decoded_addr_decoded_decoded_orMatrixOutputs[103]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_104 = decoded_addr_decoded_decoded_orMatrixOutputs[104]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_105 = decoded_addr_decoded_decoded_orMatrixOutputs[105]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_106 = decoded_addr_decoded_decoded_orMatrixOutputs[106]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_107 = decoded_addr_decoded_decoded_orMatrixOutputs[107]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_108 = decoded_addr_decoded_decoded_orMatrixOutputs[108]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_109 = decoded_addr_decoded_decoded_orMatrixOutputs[109]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_110 = decoded_addr_decoded_decoded_orMatrixOutputs[110]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_111 = decoded_addr_decoded_decoded_orMatrixOutputs[111]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_112 = decoded_addr_decoded_decoded_orMatrixOutputs[112]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_113 = decoded_addr_decoded_decoded_orMatrixOutputs[113]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_114 = decoded_addr_decoded_decoded_orMatrixOutputs[114]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_115 = decoded_addr_decoded_decoded_orMatrixOutputs[115]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_116 = decoded_addr_decoded_decoded_orMatrixOutputs[116]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_117 = decoded_addr_decoded_decoded_orMatrixOutputs[117]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_118 = decoded_addr_decoded_decoded_orMatrixOutputs[118]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_119 = decoded_addr_decoded_decoded_orMatrixOutputs[119]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_120 = decoded_addr_decoded_decoded_orMatrixOutputs[120]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_121 = decoded_addr_decoded_decoded_orMatrixOutputs[121]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_122 = decoded_addr_decoded_decoded_orMatrixOutputs[122]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_123 = decoded_addr_decoded_decoded_orMatrixOutputs[123]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_124 = decoded_addr_decoded_decoded_orMatrixOutputs[124]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_125 = decoded_addr_decoded_decoded_orMatrixOutputs[125]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_126 = decoded_addr_decoded_decoded_orMatrixOutputs[126]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_127 = decoded_addr_decoded_decoded_orMatrixOutputs[127]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_128 = decoded_addr_decoded_decoded_orMatrixOutputs[128]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_129 = decoded_addr_decoded_decoded_orMatrixOutputs[129]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_130 = decoded_addr_decoded_decoded_orMatrixOutputs[130]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_131 = decoded_addr_decoded_decoded_orMatrixOutputs[131]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_132 = decoded_addr_decoded_decoded_orMatrixOutputs[132]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_133 = decoded_addr_decoded_decoded_orMatrixOutputs[133]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_134 = decoded_addr_decoded_decoded_orMatrixOutputs[134]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_135 = decoded_addr_decoded_decoded_orMatrixOutputs[135]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_136 = decoded_addr_decoded_decoded_orMatrixOutputs[136]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_137 = decoded_addr_decoded_decoded_orMatrixOutputs[137]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_138 = decoded_addr_decoded_decoded_orMatrixOutputs[138]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_139 = decoded_addr_decoded_decoded_orMatrixOutputs[139]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_140 = decoded_addr_decoded_decoded_orMatrixOutputs[140]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_141 = decoded_addr_decoded_decoded_orMatrixOutputs[141]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_142 = decoded_addr_decoded_decoded_orMatrixOutputs[142]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_143 = decoded_addr_decoded_decoded_orMatrixOutputs[143]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_144 = decoded_addr_decoded_decoded_orMatrixOutputs[144]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_145 = decoded_addr_decoded_decoded_orMatrixOutputs[145]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_146 = decoded_addr_decoded_decoded_orMatrixOutputs[146]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_147 = decoded_addr_decoded_decoded_orMatrixOutputs[147]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_148 = decoded_addr_decoded_decoded_orMatrixOutputs[148]; // @[pla.scala:102:36, :124:31]
wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_149 = decoded_addr_decoded_decoded_orMatrixOutputs[149]; // @[pla.scala:102:36, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_1, _decoded_addr_decoded_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_3, _decoded_addr_decoded_decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_5, _decoded_addr_decoded_decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_8, _decoded_addr_decoded_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo}; // @[pla.scala:120:37]
wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_10, _decoded_addr_decoded_decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_12, _decoded_addr_decoded_decoded_invMatrixOutputs_T_11}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_14, _decoded_addr_decoded_decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_17, _decoded_addr_decoded_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo}; // @[pla.scala:120:37]
wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:120:37]
wire [17:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_19, _decoded_addr_decoded_decoded_invMatrixOutputs_T_18}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_21, _decoded_addr_decoded_decoded_invMatrixOutputs_T_20}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_23, _decoded_addr_decoded_decoded_invMatrixOutputs_T_22}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_26, _decoded_addr_decoded_decoded_invMatrixOutputs_T_25}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo}; // @[pla.scala:120:37]
wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_28, _decoded_addr_decoded_decoded_invMatrixOutputs_T_27}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_31, _decoded_addr_decoded_decoded_invMatrixOutputs_T_30}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_29}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_33, _decoded_addr_decoded_decoded_invMatrixOutputs_T_32}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_36, _decoded_addr_decoded_decoded_invMatrixOutputs_T_35}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_34}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo}; // @[pla.scala:120:37]
wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:120:37]
wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:120:37]
wire [36:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_38, _decoded_addr_decoded_decoded_invMatrixOutputs_T_37}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_40, _decoded_addr_decoded_decoded_invMatrixOutputs_T_39}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_42, _decoded_addr_decoded_decoded_invMatrixOutputs_T_41}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_45, _decoded_addr_decoded_decoded_invMatrixOutputs_T_44}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_43}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo}; // @[pla.scala:120:37]
wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_47, _decoded_addr_decoded_decoded_invMatrixOutputs_T_46}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_50, _decoded_addr_decoded_decoded_invMatrixOutputs_T_49}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_48}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_52, _decoded_addr_decoded_decoded_invMatrixOutputs_T_51}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_55, _decoded_addr_decoded_decoded_invMatrixOutputs_T_54}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_53}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo}; // @[pla.scala:120:37]
wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:120:37]
wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_57, _decoded_addr_decoded_decoded_invMatrixOutputs_T_56}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_59, _decoded_addr_decoded_decoded_invMatrixOutputs_T_58}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_61, _decoded_addr_decoded_decoded_invMatrixOutputs_T_60}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_64, _decoded_addr_decoded_decoded_invMatrixOutputs_T_63}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_62}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo}; // @[pla.scala:120:37]
wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_66, _decoded_addr_decoded_decoded_invMatrixOutputs_T_65}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_69, _decoded_addr_decoded_decoded_invMatrixOutputs_T_68}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_67}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_71, _decoded_addr_decoded_decoded_invMatrixOutputs_T_70}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_74, _decoded_addr_decoded_decoded_invMatrixOutputs_T_73}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_72}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo}; // @[pla.scala:120:37]
wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:120:37]
wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:120:37]
wire [37:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37]
wire [74:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_76, _decoded_addr_decoded_decoded_invMatrixOutputs_T_75}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_78, _decoded_addr_decoded_decoded_invMatrixOutputs_T_77}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_80, _decoded_addr_decoded_decoded_invMatrixOutputs_T_79}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_83, _decoded_addr_decoded_decoded_invMatrixOutputs_T_82}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_81}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo}; // @[pla.scala:120:37]
wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_85, _decoded_addr_decoded_decoded_invMatrixOutputs_T_84}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_87, _decoded_addr_decoded_decoded_invMatrixOutputs_T_86}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_89, _decoded_addr_decoded_decoded_invMatrixOutputs_T_88}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_92, _decoded_addr_decoded_decoded_invMatrixOutputs_T_91}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_90}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo}; // @[pla.scala:120:37]
wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:120:37]
wire [17:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_94, _decoded_addr_decoded_decoded_invMatrixOutputs_T_93}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_96, _decoded_addr_decoded_decoded_invMatrixOutputs_T_95}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_98, _decoded_addr_decoded_decoded_invMatrixOutputs_T_97}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_101, _decoded_addr_decoded_decoded_invMatrixOutputs_T_100}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_99}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo}; // @[pla.scala:120:37]
wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_103, _decoded_addr_decoded_decoded_invMatrixOutputs_T_102}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_106, _decoded_addr_decoded_decoded_invMatrixOutputs_T_105}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_104}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_108, _decoded_addr_decoded_decoded_invMatrixOutputs_T_107}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_111, _decoded_addr_decoded_decoded_invMatrixOutputs_T_110}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_109}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo}; // @[pla.scala:120:37]
wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:120:37]
wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:120:37]
wire [36:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_113, _decoded_addr_decoded_decoded_invMatrixOutputs_T_112}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_115, _decoded_addr_decoded_decoded_invMatrixOutputs_T_114}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_117, _decoded_addr_decoded_decoded_invMatrixOutputs_T_116}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_120, _decoded_addr_decoded_decoded_invMatrixOutputs_T_119}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_118}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo}; // @[pla.scala:120:37]
wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_122, _decoded_addr_decoded_decoded_invMatrixOutputs_T_121}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_125, _decoded_addr_decoded_decoded_invMatrixOutputs_T_124}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_123}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_127, _decoded_addr_decoded_decoded_invMatrixOutputs_T_126}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_130, _decoded_addr_decoded_decoded_invMatrixOutputs_T_129}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_128}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo}; // @[pla.scala:120:37]
wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:120:37]
wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_132, _decoded_addr_decoded_decoded_invMatrixOutputs_T_131}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_134, _decoded_addr_decoded_decoded_invMatrixOutputs_T_133}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_136, _decoded_addr_decoded_decoded_invMatrixOutputs_T_135}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_139, _decoded_addr_decoded_decoded_invMatrixOutputs_T_138}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_137}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo}; // @[pla.scala:120:37]
wire [8:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_141, _decoded_addr_decoded_decoded_invMatrixOutputs_T_140}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_144, _decoded_addr_decoded_decoded_invMatrixOutputs_T_143}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_142}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_146, _decoded_addr_decoded_decoded_invMatrixOutputs_T_145}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_149, _decoded_addr_decoded_decoded_invMatrixOutputs_T_148}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_147}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo}; // @[pla.scala:120:37]
wire [9:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:120:37]
wire [18:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37]
wire [37:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37]
wire [74:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37]
assign decoded_addr_decoded_decoded_invMatrixOutputs = {decoded_addr_decoded_decoded_invMatrixOutputs_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37]
assign decoded_addr_decoded_decoded = decoded_addr_decoded_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37]
assign decoded_addr_decoded_decoded_plaInput = decoded_addr_addr[11:0]; // @[pla.scala:77:22]
wire decoded_addr_decoded_0 = decoded_addr_decoded_decoded[149]; // @[pla.scala:81:23]
wire decoded_addr_97_2 = decoded_addr_decoded_0; // @[Decode.scala:50:77]
wire decoded_addr_decoded_1 = decoded_addr_decoded_decoded[148]; // @[pla.scala:81:23]
wire decoded_addr_55_2 = decoded_addr_decoded_1; // @[Decode.scala:50:77]
wire decoded_addr_decoded_2 = decoded_addr_decoded_decoded[147]; // @[pla.scala:81:23]
wire decoded_addr_10_2 = decoded_addr_decoded_2; // @[Decode.scala:50:77]
wire decoded_addr_decoded_3 = decoded_addr_decoded_decoded[146]; // @[pla.scala:81:23]
wire decoded_addr_118_2 = decoded_addr_decoded_3; // @[Decode.scala:50:77]
wire decoded_addr_decoded_4 = decoded_addr_decoded_decoded[145]; // @[pla.scala:81:23]
wire decoded_addr_94_2 = decoded_addr_decoded_4; // @[Decode.scala:50:77]
wire decoded_addr_decoded_5 = decoded_addr_decoded_decoded[144]; // @[pla.scala:81:23]
wire decoded_addr_100_2 = decoded_addr_decoded_5; // @[Decode.scala:50:77]
wire decoded_addr_decoded_6 = decoded_addr_decoded_decoded[143]; // @[pla.scala:81:23]
wire decoded_addr_72_2 = decoded_addr_decoded_6; // @[Decode.scala:50:77]
wire decoded_addr_decoded_7 = decoded_addr_decoded_decoded[142]; // @[pla.scala:81:23]
wire decoded_addr_108_2 = decoded_addr_decoded_7; // @[Decode.scala:50:77]
wire decoded_addr_decoded_8 = decoded_addr_decoded_decoded[141]; // @[pla.scala:81:23]
wire decoded_addr_76_2 = decoded_addr_decoded_8; // @[Decode.scala:50:77]
wire decoded_addr_decoded_9 = decoded_addr_decoded_decoded[140]; // @[pla.scala:81:23]
wire decoded_addr_129_2 = decoded_addr_decoded_9; // @[Decode.scala:50:77]
wire decoded_addr_decoded_10 = decoded_addr_decoded_decoded[139]; // @[pla.scala:81:23]
wire decoded_addr_132_2 = decoded_addr_decoded_10; // @[Decode.scala:50:77]
wire decoded_addr_decoded_11 = decoded_addr_decoded_decoded[138]; // @[pla.scala:81:23]
wire decoded_addr_136_2 = decoded_addr_decoded_11; // @[Decode.scala:50:77]
wire decoded_addr_decoded_12 = decoded_addr_decoded_decoded[137]; // @[pla.scala:81:23]
wire decoded_addr_29_2 = decoded_addr_decoded_12; // @[Decode.scala:50:77]
wire decoded_addr_decoded_13 = decoded_addr_decoded_decoded[136]; // @[pla.scala:81:23]
wire decoded_addr_131_2 = decoded_addr_decoded_13; // @[Decode.scala:50:77]
wire decoded_addr_decoded_14 = decoded_addr_decoded_decoded[135]; // @[pla.scala:81:23]
wire decoded_addr_49_2 = decoded_addr_decoded_14; // @[Decode.scala:50:77]
wire decoded_addr_decoded_15 = decoded_addr_decoded_decoded[134]; // @[pla.scala:81:23]
wire decoded_addr_89_2 = decoded_addr_decoded_15; // @[Decode.scala:50:77]
wire decoded_addr_decoded_16 = decoded_addr_decoded_decoded[133]; // @[pla.scala:81:23]
wire decoded_addr_57_2 = decoded_addr_decoded_16; // @[Decode.scala:50:77]
wire decoded_addr_decoded_17 = decoded_addr_decoded_decoded[132]; // @[pla.scala:81:23]
wire decoded_addr_36_2 = decoded_addr_decoded_17; // @[Decode.scala:50:77]
wire decoded_addr_decoded_18 = decoded_addr_decoded_decoded[131]; // @[pla.scala:81:23]
wire decoded_addr_68_2 = decoded_addr_decoded_18; // @[Decode.scala:50:77]
wire decoded_addr_decoded_19 = decoded_addr_decoded_decoded[130]; // @[pla.scala:81:23]
wire decoded_addr_99_2 = decoded_addr_decoded_19; // @[Decode.scala:50:77]
wire decoded_addr_decoded_20 = decoded_addr_decoded_decoded[129]; // @[pla.scala:81:23]
wire decoded_addr_130_2 = decoded_addr_decoded_20; // @[Decode.scala:50:77]
wire decoded_addr_decoded_21 = decoded_addr_decoded_decoded[128]; // @[pla.scala:81:23]
wire decoded_addr_103_2 = decoded_addr_decoded_21; // @[Decode.scala:50:77]
wire decoded_addr_decoded_22 = decoded_addr_decoded_decoded[127]; // @[pla.scala:81:23]
wire decoded_addr_121_2 = decoded_addr_decoded_22; // @[Decode.scala:50:77]
wire decoded_addr_decoded_23 = decoded_addr_decoded_decoded[126]; // @[pla.scala:81:23]
wire decoded_addr_146_2 = decoded_addr_decoded_23; // @[Decode.scala:50:77]
wire decoded_addr_decoded_24 = decoded_addr_decoded_decoded[125]; // @[pla.scala:81:23]
wire decoded_addr_17_2 = decoded_addr_decoded_24; // @[Decode.scala:50:77]
wire decoded_addr_decoded_25 = decoded_addr_decoded_decoded[124]; // @[pla.scala:81:23]
wire decoded_addr_27_2 = decoded_addr_decoded_25; // @[Decode.scala:50:77]
wire decoded_addr_decoded_26 = decoded_addr_decoded_decoded[123]; // @[pla.scala:81:23]
wire decoded_addr_83_2 = decoded_addr_decoded_26; // @[Decode.scala:50:77]
wire decoded_addr_decoded_27 = decoded_addr_decoded_decoded[122]; // @[pla.scala:81:23]
wire decoded_addr_52_2 = decoded_addr_decoded_27; // @[Decode.scala:50:77]
wire decoded_addr_decoded_28 = decoded_addr_decoded_decoded[121]; // @[pla.scala:81:23]
wire decoded_addr_144_2 = decoded_addr_decoded_28; // @[Decode.scala:50:77]
wire decoded_addr_decoded_29 = decoded_addr_decoded_decoded[120]; // @[pla.scala:81:23]
wire decoded_addr_70_2 = decoded_addr_decoded_29; // @[Decode.scala:50:77]
wire decoded_addr_decoded_30 = decoded_addr_decoded_decoded[119]; // @[pla.scala:81:23]
wire decoded_addr_111_2 = decoded_addr_decoded_30; // @[Decode.scala:50:77]
wire decoded_addr_decoded_31 = decoded_addr_decoded_decoded[118]; // @[pla.scala:81:23]
wire decoded_addr_82_2 = decoded_addr_decoded_31; // @[Decode.scala:50:77]
wire decoded_addr_decoded_32 = decoded_addr_decoded_decoded[117]; // @[pla.scala:81:23]
wire decoded_addr_31_2 = decoded_addr_decoded_32; // @[Decode.scala:50:77]
wire decoded_addr_decoded_33 = decoded_addr_decoded_decoded[116]; // @[pla.scala:81:23]
wire decoded_addr_0_2 = decoded_addr_decoded_33; // @[Decode.scala:50:77]
wire decoded_addr_decoded_34 = decoded_addr_decoded_decoded[115]; // @[pla.scala:81:23]
wire decoded_addr_59_2 = decoded_addr_decoded_34; // @[Decode.scala:50:77]
wire decoded_addr_decoded_35 = decoded_addr_decoded_decoded[114]; // @[pla.scala:81:23]
wire decoded_addr_138_2 = decoded_addr_decoded_35; // @[Decode.scala:50:77]
wire decoded_addr_decoded_36 = decoded_addr_decoded_decoded[113]; // @[pla.scala:81:23]
wire decoded_addr_126_2 = decoded_addr_decoded_36; // @[Decode.scala:50:77]
wire decoded_addr_decoded_37 = decoded_addr_decoded_decoded[112]; // @[pla.scala:81:23]
wire decoded_addr_74_2 = decoded_addr_decoded_37; // @[Decode.scala:50:77]
wire decoded_addr_decoded_38 = decoded_addr_decoded_decoded[111]; // @[pla.scala:81:23]
wire decoded_addr_116_2 = decoded_addr_decoded_38; // @[Decode.scala:50:77]
wire decoded_addr_decoded_39 = decoded_addr_decoded_decoded[110]; // @[pla.scala:81:23]
wire decoded_addr_90_2 = decoded_addr_decoded_39; // @[Decode.scala:50:77]
wire decoded_addr_decoded_40 = decoded_addr_decoded_decoded[109]; // @[pla.scala:81:23]
wire decoded_addr_113_2 = decoded_addr_decoded_40; // @[Decode.scala:50:77]
wire decoded_addr_decoded_41 = decoded_addr_decoded_decoded[108]; // @[pla.scala:81:23]
wire decoded_addr_1_2 = decoded_addr_decoded_41; // @[Decode.scala:50:77]
wire decoded_addr_decoded_42 = decoded_addr_decoded_decoded[107]; // @[pla.scala:81:23]
wire decoded_addr_16_2 = decoded_addr_decoded_42; // @[Decode.scala:50:77]
wire decoded_addr_decoded_43 = decoded_addr_decoded_decoded[106]; // @[pla.scala:81:23]
wire decoded_addr_78_2 = decoded_addr_decoded_43; // @[Decode.scala:50:77]
wire decoded_addr_decoded_44 = decoded_addr_decoded_decoded[105]; // @[pla.scala:81:23]
wire decoded_addr_39_2 = decoded_addr_decoded_44; // @[Decode.scala:50:77]
wire decoded_addr_decoded_45 = decoded_addr_decoded_decoded[104]; // @[pla.scala:81:23]
wire decoded_addr_51_2 = decoded_addr_decoded_45; // @[Decode.scala:50:77]
wire decoded_addr_decoded_46 = decoded_addr_decoded_decoded[103]; // @[pla.scala:81:23]
wire decoded_addr_109_2 = decoded_addr_decoded_46; // @[Decode.scala:50:77]
wire decoded_addr_decoded_47 = decoded_addr_decoded_decoded[102]; // @[pla.scala:81:23]
wire decoded_addr_91_2 = decoded_addr_decoded_47; // @[Decode.scala:50:77]
wire decoded_addr_decoded_48 = decoded_addr_decoded_decoded[101]; // @[pla.scala:81:23]
wire decoded_addr_81_2 = decoded_addr_decoded_48; // @[Decode.scala:50:77]
wire decoded_addr_decoded_49 = decoded_addr_decoded_decoded[100]; // @[pla.scala:81:23]
wire decoded_addr_67_2 = decoded_addr_decoded_49; // @[Decode.scala:50:77]
wire decoded_addr_decoded_50 = decoded_addr_decoded_decoded[99]; // @[pla.scala:81:23]
wire decoded_addr_105_2 = decoded_addr_decoded_50; // @[Decode.scala:50:77]
wire decoded_addr_decoded_51 = decoded_addr_decoded_decoded[98]; // @[pla.scala:81:23]
wire decoded_addr_122_2 = decoded_addr_decoded_51; // @[Decode.scala:50:77]
wire decoded_addr_decoded_52 = decoded_addr_decoded_decoded[97]; // @[pla.scala:81:23]
wire decoded_addr_24_2 = decoded_addr_decoded_52; // @[Decode.scala:50:77]
wire decoded_addr_decoded_53 = decoded_addr_decoded_decoded[96]; // @[pla.scala:81:23]
wire decoded_addr_124_2 = decoded_addr_decoded_53; // @[Decode.scala:50:77]
wire decoded_addr_decoded_54 = decoded_addr_decoded_decoded[95]; // @[pla.scala:81:23]
wire decoded_addr_26_2 = decoded_addr_decoded_54; // @[Decode.scala:50:77]
wire decoded_addr_decoded_55 = decoded_addr_decoded_decoded[94]; // @[pla.scala:81:23]
wire decoded_addr_128_2 = decoded_addr_decoded_55; // @[Decode.scala:50:77]
wire decoded_addr_decoded_56 = decoded_addr_decoded_decoded[93]; // @[pla.scala:81:23]
wire decoded_addr_7_2 = decoded_addr_decoded_56; // @[Decode.scala:50:77]
wire decoded_addr_decoded_57 = decoded_addr_decoded_decoded[92]; // @[pla.scala:81:23]
wire decoded_addr_62_2 = decoded_addr_decoded_57; // @[Decode.scala:50:77]
wire decoded_addr_decoded_58 = decoded_addr_decoded_decoded[91]; // @[pla.scala:81:23]
wire decoded_addr_77_2 = decoded_addr_decoded_58; // @[Decode.scala:50:77]
wire decoded_addr_decoded_59 = decoded_addr_decoded_decoded[90]; // @[pla.scala:81:23]
wire decoded_addr_46_2 = decoded_addr_decoded_59; // @[Decode.scala:50:77]
wire decoded_addr_decoded_60 = decoded_addr_decoded_decoded[89]; // @[pla.scala:81:23]
wire decoded_addr_112_2 = decoded_addr_decoded_60; // @[Decode.scala:50:77]
wire decoded_addr_decoded_61 = decoded_addr_decoded_decoded[88]; // @[pla.scala:81:23]
wire decoded_addr_60_2 = decoded_addr_decoded_61; // @[Decode.scala:50:77]
wire decoded_addr_decoded_62 = decoded_addr_decoded_decoded[87]; // @[pla.scala:81:23]
wire decoded_addr_92_2 = decoded_addr_decoded_62; // @[Decode.scala:50:77]
wire decoded_addr_decoded_63 = decoded_addr_decoded_decoded[86]; // @[pla.scala:81:23]
wire decoded_addr_148_2 = decoded_addr_decoded_63; // @[Decode.scala:50:77]
wire decoded_addr_decoded_64 = decoded_addr_decoded_decoded[85]; // @[pla.scala:81:23]
wire decoded_addr_14_2 = decoded_addr_decoded_64; // @[Decode.scala:50:77]
wire decoded_addr_decoded_65 = decoded_addr_decoded_decoded[84]; // @[pla.scala:81:23]
wire decoded_addr_21_2 = decoded_addr_decoded_65; // @[Decode.scala:50:77]
wire decoded_addr_decoded_66 = decoded_addr_decoded_decoded[83]; // @[pla.scala:81:23]
wire decoded_addr_33_2 = decoded_addr_decoded_66; // @[Decode.scala:50:77]
wire decoded_addr_decoded_67 = decoded_addr_decoded_decoded[82]; // @[pla.scala:81:23]
wire decoded_addr_19_2 = decoded_addr_decoded_67; // @[Decode.scala:50:77]
wire decoded_addr_decoded_68 = decoded_addr_decoded_decoded[81]; // @[pla.scala:81:23]
wire decoded_addr_133_2 = decoded_addr_decoded_68; // @[Decode.scala:50:77]
wire decoded_addr_decoded_69 = decoded_addr_decoded_decoded[80]; // @[pla.scala:81:23]
wire decoded_addr_149_2 = decoded_addr_decoded_69; // @[Decode.scala:50:77]
wire decoded_addr_decoded_70 = decoded_addr_decoded_decoded[79]; // @[pla.scala:81:23]
wire decoded_addr_50_2 = decoded_addr_decoded_70; // @[Decode.scala:50:77]
wire decoded_addr_decoded_71 = decoded_addr_decoded_decoded[78]; // @[pla.scala:81:23]
wire decoded_addr_75_2 = decoded_addr_decoded_71; // @[Decode.scala:50:77]
wire decoded_addr_decoded_72 = decoded_addr_decoded_decoded[77]; // @[pla.scala:81:23]
wire decoded_addr_102_2 = decoded_addr_decoded_72; // @[Decode.scala:50:77]
wire decoded_addr_decoded_73 = decoded_addr_decoded_decoded[76]; // @[pla.scala:81:23]
wire decoded_addr_84_2 = decoded_addr_decoded_73; // @[Decode.scala:50:77]
wire decoded_addr_decoded_74 = decoded_addr_decoded_decoded[75]; // @[pla.scala:81:23]
wire decoded_addr_45_2 = decoded_addr_decoded_74; // @[Decode.scala:50:77]
wire decoded_addr_decoded_75 = decoded_addr_decoded_decoded[74]; // @[pla.scala:81:23]
wire decoded_addr_64_2 = decoded_addr_decoded_75; // @[Decode.scala:50:77]
wire decoded_addr_decoded_76 = decoded_addr_decoded_decoded[73]; // @[pla.scala:81:23]
wire decoded_addr_120_2 = decoded_addr_decoded_76; // @[Decode.scala:50:77]
wire decoded_addr_decoded_77 = decoded_addr_decoded_decoded[72]; // @[pla.scala:81:23]
wire decoded_addr_30_2 = decoded_addr_decoded_77; // @[Decode.scala:50:77]
wire decoded_addr_decoded_78 = decoded_addr_decoded_decoded[71]; // @[pla.scala:81:23]
wire decoded_addr_5_2 = decoded_addr_decoded_78; // @[Decode.scala:50:77]
wire decoded_addr_decoded_79 = decoded_addr_decoded_decoded[70]; // @[pla.scala:81:23]
wire decoded_addr_32_2 = decoded_addr_decoded_79; // @[Decode.scala:50:77]
wire decoded_addr_decoded_80 = decoded_addr_decoded_decoded[69]; // @[pla.scala:81:23]
wire decoded_addr_143_2 = decoded_addr_decoded_80; // @[Decode.scala:50:77]
wire decoded_addr_decoded_81 = decoded_addr_decoded_decoded[68]; // @[pla.scala:81:23]
wire decoded_addr_117_2 = decoded_addr_decoded_81; // @[Decode.scala:50:77]
wire decoded_addr_decoded_82 = decoded_addr_decoded_decoded[67]; // @[pla.scala:81:23]
wire decoded_addr_63_2 = decoded_addr_decoded_82; // @[Decode.scala:50:77]
wire decoded_addr_decoded_83 = decoded_addr_decoded_decoded[66]; // @[pla.scala:81:23]
wire decoded_addr_107_2 = decoded_addr_decoded_83; // @[Decode.scala:50:77]
wire decoded_addr_decoded_84 = decoded_addr_decoded_decoded[65]; // @[pla.scala:81:23]
wire decoded_addr_88_2 = decoded_addr_decoded_84; // @[Decode.scala:50:77]
wire decoded_addr_decoded_85 = decoded_addr_decoded_decoded[64]; // @[pla.scala:81:23]
wire decoded_addr_114_2 = decoded_addr_decoded_85; // @[Decode.scala:50:77]
wire decoded_addr_decoded_86 = decoded_addr_decoded_decoded[63]; // @[pla.scala:81:23]
wire decoded_addr_73_2 = decoded_addr_decoded_86; // @[Decode.scala:50:77]
wire decoded_addr_decoded_87 = decoded_addr_decoded_decoded[62]; // @[pla.scala:81:23]
wire decoded_addr_53_2 = decoded_addr_decoded_87; // @[Decode.scala:50:77]
wire decoded_addr_decoded_88 = decoded_addr_decoded_decoded[61]; // @[pla.scala:81:23]
wire decoded_addr_147_2 = decoded_addr_decoded_88; // @[Decode.scala:50:77]
wire decoded_addr_decoded_89 = decoded_addr_decoded_decoded[60]; // @[pla.scala:81:23]
wire decoded_addr_41_2 = decoded_addr_decoded_89; // @[Decode.scala:50:77]
wire decoded_addr_decoded_90 = decoded_addr_decoded_decoded[59]; // @[pla.scala:81:23]
wire decoded_addr_56_2 = decoded_addr_decoded_90; // @[Decode.scala:50:77]
wire decoded_addr_decoded_91 = decoded_addr_decoded_decoded[58]; // @[pla.scala:81:23]
wire decoded_addr_37_2 = decoded_addr_decoded_91; // @[Decode.scala:50:77]
wire decoded_addr_decoded_92 = decoded_addr_decoded_decoded[57]; // @[pla.scala:81:23]
wire decoded_addr_79_2 = decoded_addr_decoded_92; // @[Decode.scala:50:77]
wire decoded_addr_decoded_93 = decoded_addr_decoded_decoded[56]; // @[pla.scala:81:23]
wire decoded_addr_96_2 = decoded_addr_decoded_93; // @[Decode.scala:50:77]
wire decoded_addr_decoded_94 = decoded_addr_decoded_decoded[55]; // @[pla.scala:81:23]
wire decoded_addr_4_2 = decoded_addr_decoded_94; // @[Decode.scala:50:77]
wire decoded_addr_decoded_95 = decoded_addr_decoded_decoded[54]; // @[pla.scala:81:23]
wire decoded_addr_101_2 = decoded_addr_decoded_95; // @[Decode.scala:50:77]
wire decoded_addr_decoded_96 = decoded_addr_decoded_decoded[53]; // @[pla.scala:81:23]
wire decoded_addr_119_2 = decoded_addr_decoded_96; // @[Decode.scala:50:77]
wire decoded_addr_decoded_97 = decoded_addr_decoded_decoded[52]; // @[pla.scala:81:23]
wire decoded_addr_22_2 = decoded_addr_decoded_97; // @[Decode.scala:50:77]
wire decoded_addr_decoded_98 = decoded_addr_decoded_decoded[51]; // @[pla.scala:81:23]
wire decoded_addr_139_2 = decoded_addr_decoded_98; // @[Decode.scala:50:77]
wire decoded_addr_decoded_99 = decoded_addr_decoded_decoded[50]; // @[pla.scala:81:23]
wire decoded_addr_11_2 = decoded_addr_decoded_99; // @[Decode.scala:50:77]
wire decoded_addr_decoded_100 = decoded_addr_decoded_decoded[49]; // @[pla.scala:81:23]
wire decoded_addr_134_2 = decoded_addr_decoded_100; // @[Decode.scala:50:77]
wire decoded_addr_decoded_101 = decoded_addr_decoded_decoded[48]; // @[pla.scala:81:23]
wire decoded_addr_12_2 = decoded_addr_decoded_101; // @[Decode.scala:50:77]
wire decoded_addr_decoded_102 = decoded_addr_decoded_decoded[47]; // @[pla.scala:81:23]
wire decoded_addr_65_2 = decoded_addr_decoded_102; // @[Decode.scala:50:77]
wire decoded_addr_decoded_103 = decoded_addr_decoded_decoded[46]; // @[pla.scala:81:23]
wire decoded_addr_86_2 = decoded_addr_decoded_103; // @[Decode.scala:50:77]
wire decoded_addr_decoded_104 = decoded_addr_decoded_decoded[45]; // @[pla.scala:81:23]
wire decoded_addr_47_2 = decoded_addr_decoded_104; // @[Decode.scala:50:77]
wire decoded_addr_decoded_105 = decoded_addr_decoded_decoded[44]; // @[pla.scala:81:23]
wire decoded_addr_106_2 = decoded_addr_decoded_105; // @[Decode.scala:50:77]
wire decoded_addr_decoded_106 = decoded_addr_decoded_decoded[43]; // @[pla.scala:81:23]
wire decoded_addr_58_2 = decoded_addr_decoded_106; // @[Decode.scala:50:77]
wire decoded_addr_decoded_107 = decoded_addr_decoded_decoded[42]; // @[pla.scala:81:23]
wire decoded_addr_87_2 = decoded_addr_decoded_107; // @[Decode.scala:50:77]
wire decoded_addr_decoded_108 = decoded_addr_decoded_decoded[41]; // @[pla.scala:81:23]
wire decoded_addr_142_2 = decoded_addr_decoded_108; // @[Decode.scala:50:77]
wire decoded_addr_decoded_109 = decoded_addr_decoded_decoded[40]; // @[pla.scala:81:23]
wire decoded_addr_13_2 = decoded_addr_decoded_109; // @[Decode.scala:50:77]
wire decoded_addr_decoded_110 = decoded_addr_decoded_decoded[39]; // @[pla.scala:81:23]
wire decoded_addr_35_2 = decoded_addr_decoded_110; // @[Decode.scala:50:77]
wire decoded_addr_decoded_111 = decoded_addr_decoded_decoded[38]; // @[pla.scala:81:23]
wire decoded_addr_2_2 = decoded_addr_decoded_111; // @[Decode.scala:50:77]
wire decoded_addr_decoded_112 = decoded_addr_decoded_decoded[37]; // @[pla.scala:81:23]
wire decoded_addr_66_2 = decoded_addr_decoded_112; // @[Decode.scala:50:77]
wire decoded_addr_decoded_113 = decoded_addr_decoded_decoded[36]; // @[pla.scala:81:23]
wire decoded_addr_42_2 = decoded_addr_decoded_113; // @[Decode.scala:50:77]
wire decoded_addr_decoded_114 = decoded_addr_decoded_decoded[35]; // @[pla.scala:81:23]
wire decoded_addr_61_2 = decoded_addr_decoded_114; // @[Decode.scala:50:77]
wire decoded_addr_decoded_115 = decoded_addr_decoded_decoded[34]; // @[pla.scala:81:23]
wire decoded_addr_48_2 = decoded_addr_decoded_115; // @[Decode.scala:50:77]
wire decoded_addr_decoded_116 = decoded_addr_decoded_decoded[33]; // @[pla.scala:81:23]
wire decoded_addr_44_2 = decoded_addr_decoded_116; // @[Decode.scala:50:77]
wire decoded_addr_decoded_117 = decoded_addr_decoded_decoded[32]; // @[pla.scala:81:23]
wire decoded_addr_15_2 = decoded_addr_decoded_117; // @[Decode.scala:50:77]
wire decoded_addr_decoded_118 = decoded_addr_decoded_decoded[31]; // @[pla.scala:81:23]
wire decoded_addr_145_2 = decoded_addr_decoded_118; // @[Decode.scala:50:77]
wire decoded_addr_decoded_119 = decoded_addr_decoded_decoded[30]; // @[pla.scala:81:23]
wire decoded_addr_93_2 = decoded_addr_decoded_119; // @[Decode.scala:50:77]
wire decoded_addr_decoded_120 = decoded_addr_decoded_decoded[29]; // @[pla.scala:81:23]
wire decoded_addr_6_2 = decoded_addr_decoded_120; // @[Decode.scala:50:77]
wire decoded_addr_decoded_121 = decoded_addr_decoded_decoded[28]; // @[pla.scala:81:23]
wire decoded_addr_28_2 = decoded_addr_decoded_121; // @[Decode.scala:50:77]
wire decoded_addr_decoded_122 = decoded_addr_decoded_decoded[27]; // @[pla.scala:81:23]
wire decoded_addr_25_2 = decoded_addr_decoded_122; // @[Decode.scala:50:77]
wire decoded_addr_decoded_123 = decoded_addr_decoded_decoded[26]; // @[pla.scala:81:23]
wire decoded_addr_137_2 = decoded_addr_decoded_123; // @[Decode.scala:50:77]
wire decoded_addr_decoded_124 = decoded_addr_decoded_decoded[25]; // @[pla.scala:81:23]
wire decoded_addr_123_2 = decoded_addr_decoded_124; // @[Decode.scala:50:77]
wire decoded_addr_decoded_125 = decoded_addr_decoded_decoded[24]; // @[pla.scala:81:23]
wire decoded_addr_23_2 = decoded_addr_decoded_125; // @[Decode.scala:50:77]
wire decoded_addr_decoded_126 = decoded_addr_decoded_decoded[23]; // @[pla.scala:81:23]
wire decoded_addr_69_2 = decoded_addr_decoded_126; // @[Decode.scala:50:77]
wire decoded_addr_decoded_127 = decoded_addr_decoded_decoded[22]; // @[pla.scala:81:23]
wire decoded_addr_141_2 = decoded_addr_decoded_127; // @[Decode.scala:50:77]
wire decoded_addr_decoded_128 = decoded_addr_decoded_decoded[21]; // @[pla.scala:81:23]
wire decoded_addr_9_2 = decoded_addr_decoded_128; // @[Decode.scala:50:77]
wire decoded_addr_decoded_129 = decoded_addr_decoded_decoded[20]; // @[pla.scala:81:23]
wire decoded_addr_104_2 = decoded_addr_decoded_129; // @[Decode.scala:50:77]
wire decoded_addr_decoded_130 = decoded_addr_decoded_decoded[19]; // @[pla.scala:81:23]
wire decoded_addr_8_2 = decoded_addr_decoded_130; // @[Decode.scala:50:77]
wire decoded_addr_decoded_131 = decoded_addr_decoded_decoded[18]; // @[pla.scala:81:23]
wire decoded_addr_125_2 = decoded_addr_decoded_131; // @[Decode.scala:50:77]
wire decoded_addr_decoded_132 = decoded_addr_decoded_decoded[17]; // @[pla.scala:81:23]
wire decoded_addr_85_2 = decoded_addr_decoded_132; // @[Decode.scala:50:77]
wire decoded_addr_decoded_133 = decoded_addr_decoded_decoded[16]; // @[pla.scala:81:23]
wire decoded_addr_54_2 = decoded_addr_decoded_133; // @[Decode.scala:50:77]
wire decoded_addr_decoded_134 = decoded_addr_decoded_decoded[15]; // @[pla.scala:81:23]
wire decoded_addr_20_2 = decoded_addr_decoded_134; // @[Decode.scala:50:77]
wire decoded_addr_decoded_135 = decoded_addr_decoded_decoded[14]; // @[pla.scala:81:23]
wire decoded_addr_135_2 = decoded_addr_decoded_135; // @[Decode.scala:50:77]
wire decoded_addr_decoded_136 = decoded_addr_decoded_decoded[13]; // @[pla.scala:81:23]
wire decoded_addr_115_2 = decoded_addr_decoded_136; // @[Decode.scala:50:77]
wire decoded_addr_decoded_137 = decoded_addr_decoded_decoded[12]; // @[pla.scala:81:23]
wire decoded_addr_43_2 = decoded_addr_decoded_137; // @[Decode.scala:50:77]
wire decoded_addr_decoded_138 = decoded_addr_decoded_decoded[11]; // @[pla.scala:81:23]
wire decoded_addr_71_2 = decoded_addr_decoded_138; // @[Decode.scala:50:77]
wire decoded_addr_decoded_139 = decoded_addr_decoded_decoded[10]; // @[pla.scala:81:23]
wire decoded_addr_110_2 = decoded_addr_decoded_139; // @[Decode.scala:50:77]
wire decoded_addr_decoded_140 = decoded_addr_decoded_decoded[9]; // @[pla.scala:81:23]
wire decoded_addr_140_2 = decoded_addr_decoded_140; // @[Decode.scala:50:77]
wire decoded_addr_decoded_141 = decoded_addr_decoded_decoded[8]; // @[pla.scala:81:23]
wire decoded_addr_34_2 = decoded_addr_decoded_141; // @[Decode.scala:50:77]
wire decoded_addr_decoded_142 = decoded_addr_decoded_decoded[7]; // @[pla.scala:81:23]
wire decoded_addr_40_2 = decoded_addr_decoded_142; // @[Decode.scala:50:77]
wire decoded_addr_decoded_143 = decoded_addr_decoded_decoded[6]; // @[pla.scala:81:23]
wire decoded_addr_80_2 = decoded_addr_decoded_143; // @[Decode.scala:50:77]
wire decoded_addr_decoded_144 = decoded_addr_decoded_decoded[5]; // @[pla.scala:81:23]
wire decoded_addr_98_2 = decoded_addr_decoded_144; // @[Decode.scala:50:77]
wire decoded_addr_decoded_145 = decoded_addr_decoded_decoded[4]; // @[pla.scala:81:23]
wire decoded_addr_18_2 = decoded_addr_decoded_145; // @[Decode.scala:50:77]
wire decoded_addr_decoded_146 = decoded_addr_decoded_decoded[3]; // @[pla.scala:81:23]
wire decoded_addr_3_2 = decoded_addr_decoded_146; // @[Decode.scala:50:77]
wire decoded_addr_decoded_147 = decoded_addr_decoded_decoded[2]; // @[pla.scala:81:23]
wire decoded_addr_38_2 = decoded_addr_decoded_147; // @[Decode.scala:50:77]
wire decoded_addr_decoded_148 = decoded_addr_decoded_decoded[1]; // @[pla.scala:81:23]
wire decoded_addr_127_2 = decoded_addr_decoded_148; // @[Decode.scala:50:77]
wire decoded_addr_decoded_149 = decoded_addr_decoded_decoded[0]; // @[pla.scala:81:23]
wire decoded_addr_95_2 = decoded_addr_decoded_149; // @[Decode.scala:50:77]
wire _wdata_T = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13]
wire _new_mip_T_1 = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13]
wire _newBPC_T_1 = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13]
wire _newBPC_T_25 = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13]
wire [63:0] _wdata_T_1 = _wdata_T ? io_rw_rdata_0 : 64'h0; // @[CSR.scala:377:7, :1643:{9,13}]
wire [63:0] _wdata_T_2 = _wdata_T_1 | io_rw_wdata_0; // @[CSR.scala:377:7, :1643:{9,30}]
wire [1:0] _wdata_T_3 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49]
wire [1:0] _new_mip_T_4 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49]
wire [1:0] _newBPC_T_4 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49]
wire [1:0] _newBPC_T_28 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49]
wire _wdata_T_4 = &_wdata_T_3; // @[CSR.scala:1643:{49,55}]
wire [63:0] _wdata_T_5 = _wdata_T_4 ? io_rw_wdata_0 : 64'h0; // @[CSR.scala:377:7, :1643:{45,55}]
wire [63:0] _wdata_T_6 = ~_wdata_T_5; // @[CSR.scala:1643:{41,45}]
assign wdata = _wdata_T_2 & _wdata_T_6; // @[CSR.scala:1643:{30,39,41}]
assign io_customCSRs_0_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39]
assign io_customCSRs_1_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39]
assign io_customCSRs_2_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39]
assign io_customCSRs_3_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39]
wire [63:0] _new_satp_WIRE = wdata; // @[CSR.scala:1355:40, :1643:39]
wire [63:0] _new_envcfg_WIRE = wdata; // @[CSR.scala:137:36, :1643:39]
wire [63:0] _new_envcfg_WIRE_1 = wdata; // @[CSR.scala:137:36, :1643:39]
wire [63:0] _reg_bp_0_control_WIRE_1 = wdata; // @[CSR.scala:1471:41, :1643:39]
wire [63:0] _reg_bp_1_control_WIRE_1 = wdata; // @[CSR.scala:1471:41, :1643:39]
wire [63:0] _newCfg_T = wdata; // @[CSR.scala:1491:29, :1643:39]
wire system_insn = io_rw_cmd_0 == 3'h4; // @[CSR.scala:377:7, :876:31]
wire [31:0] _insn_T = {io_rw_addr_0, 20'h0}; // @[CSR.scala:377:7, :892:44]
wire [31:0] insn = {_insn_T[31:7], _insn_T[6:0] | 7'h73}; // @[CSR.scala:892:{30,44}]
wire [31:0] decoded_plaInput = insn; // @[pla.scala:77:22]
wire [31:0] decoded_invInputs = ~decoded_plaInput; // @[pla.scala:77:22, :78:21]
wire [8:0] decoded_invMatrixOutputs; // @[pla.scala:120:37]
wire [8:0] decoded; // @[pla.scala:81:23]
wire decoded_andMatrixOutputs_andMatrixInput_0 = decoded_invInputs[20]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1 = decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_invInputs[21]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_1 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_1 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_2 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_3 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_5 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_1 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_2 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_3 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_5 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_1 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_2 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_3 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_5 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_6 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_6_1 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_2 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_3 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_11_2 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_5 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_7 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_7_1 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_6_2 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_3 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_12 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_5 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8 = decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_1 = decoded_invInputs[28]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_1 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_7_3 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_14 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_10 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_10_1 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_2 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_3 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_15 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_5 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_11 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_11_1 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_2 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_3 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_16 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_5 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_6 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29]
wire [1:0] decoded_andMatrixOutputs_lo_lo_hi = {decoded_andMatrixOutputs_andMatrixInput_9, decoded_andMatrixOutputs_andMatrixInput_10}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_lo = {decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_6, decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi = {decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_andMatrixOutputs_lo = {decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_hi = {decoded_andMatrixOutputs_andMatrixInput_3, decoded_andMatrixOutputs_andMatrixInput_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_lo = {decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi = {decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_andMatrixOutputs_hi = {decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53]
wire [11:0] _decoded_andMatrixOutputs_T = {decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_6_2 = &_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_6 = decoded_andMatrixOutputs_6_2; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_plaInput[20]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_lo_1 = {decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_1 = {decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_andMatrixOutputs_lo_1 = {decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_lo_1 = {decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_1 = {decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_andMatrixOutputs_hi_1 = {decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53]
wire [11:0] _decoded_andMatrixOutputs_T_1 = {decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_4_2 = &_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_5 = decoded_andMatrixOutputs_4_2; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_7_2 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_6_3 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_13 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_6_5 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_8_2, decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_5_2, decoded_andMatrixOutputs_andMatrixInput_6_2}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_2 = {decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_andMatrixOutputs_lo_2 = {decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_2 = {decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_2}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_hi_2 = {decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53]
wire [9:0] _decoded_andMatrixOutputs_T_2 = {decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_3_2 = &_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}]
wire decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_plaInput[22]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_plaInput[22]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_3 = {decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_3 = {decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_7_3}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_lo_3 = {decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_3 = {decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_3 = {decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_3}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_hi_3 = {decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53]
wire [9:0] _decoded_andMatrixOutputs_T_3 = {decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_1_2 = &_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_1 = decoded_andMatrixOutputs_1_2; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_1_4 = decoded_plaInput[1]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_2_4 = decoded_invInputs[2]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_4 = decoded_invInputs[3]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_4 = decoded_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_5_4 = decoded_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_6_4 = decoded_plaInput[6]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_7_4 = decoded_invInputs[7]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_4 = decoded_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_4 = decoded_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_10_2 = decoded_plaInput[25]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_lo = {decoded_andMatrixOutputs_andMatrixInput_15, decoded_andMatrixOutputs_andMatrixInput_16}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_13, decoded_andMatrixOutputs_andMatrixInput_14}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoded_andMatrixOutputs_lo_lo_4 = {decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_lo_lo_lo}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_lo = {decoded_andMatrixOutputs_andMatrixInput_11_2, decoded_andMatrixOutputs_andMatrixInput_12}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_andMatrixOutputs_andMatrixInput_10_2}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoded_andMatrixOutputs_lo_hi_4 = {decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_lo_hi_lo}; // @[pla.scala:98:53]
wire [7:0] decoded_andMatrixOutputs_lo_4 = {decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_lo = {decoded_andMatrixOutputs_andMatrixInput_7_4, decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_5_4, decoded_andMatrixOutputs_andMatrixInput_6_4}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoded_andMatrixOutputs_hi_lo_4 = {decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_hi_lo_lo}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_lo = {decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_hi_4 = {decoded_andMatrixOutputs_hi_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_hi_hi_4 = {decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_hi_hi_lo}; // @[pla.scala:98:53]
wire [8:0] decoded_andMatrixOutputs_hi_4 = {decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53]
wire [16:0] _decoded_andMatrixOutputs_T_4 = {decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_0_2 = &_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T = decoded_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_7_5 = decoded_plaInput[29]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_5 = {decoded_andMatrixOutputs_andMatrixInput_8_5, decoded_andMatrixOutputs_andMatrixInput_9_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_5_5, decoded_andMatrixOutputs_andMatrixInput_6_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_5 = {decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_andMatrixOutputs_lo_5 = {decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_5 = {decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_5 = {decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_hi_5 = {decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53]
wire [9:0] _decoded_andMatrixOutputs_T_5 = {decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_5_2 = &_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_2 = decoded_andMatrixOutputs_5_2; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_0_6 = decoded_plaInput[30]; // @[pla.scala:77:22, :90:45]
wire [1:0] _decoded_andMatrixOutputs_T_6 = {decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:90:45, :91:29, :98:53]
wire decoded_andMatrixOutputs_2_2 = &_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}]
wire [1:0] _decoded_orMatrixOutputs_T_3 = {decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19]
wire _decoded_orMatrixOutputs_T_4 = |_decoded_orMatrixOutputs_T_3; // @[pla.scala:114:{19,36}]
wire [1:0] decoded_orMatrixOutputs_lo_hi = {_decoded_orMatrixOutputs_T, 1'h0}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_orMatrixOutputs_lo = {decoded_orMatrixOutputs_lo_hi, 2'h0}; // @[pla.scala:102:36]
wire [1:0] decoded_orMatrixOutputs_hi_lo = {_decoded_orMatrixOutputs_T_2, _decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_orMatrixOutputs_hi_hi_hi = {_decoded_orMatrixOutputs_T_6, _decoded_orMatrixOutputs_T_5}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_orMatrixOutputs_hi_hi = {decoded_orMatrixOutputs_hi_hi_hi, _decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_orMatrixOutputs_hi = {decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:102:36]
wire [8:0] decoded_orMatrixOutputs = {decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo}; // @[pla.scala:102:36]
wire _decoded_invMatrixOutputs_T = decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_1 = decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_2 = decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_3 = decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_4 = decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_5 = decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_6 = decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_7 = decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_8 = decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31]
wire [1:0] decoded_invMatrixOutputs_lo_lo = {_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_invMatrixOutputs_lo_hi = {_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_invMatrixOutputs_lo = {decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37]
wire [1:0] decoded_invMatrixOutputs_hi_lo = {_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_invMatrixOutputs_hi_hi_hi = {_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_invMatrixOutputs_hi_hi = {decoded_invMatrixOutputs_hi_hi_hi, _decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_invMatrixOutputs_hi = {decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37]
assign decoded_invMatrixOutputs = {decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37]
assign decoded = decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37]
wire insn_call = system_insn & decoded[8]; // @[pla.scala:81:23]
wire insn_break = system_insn & decoded[7]; // @[pla.scala:81:23]
wire insn_ret = system_insn & decoded[6]; // @[pla.scala:81:23]
wire insn_cease = system_insn & decoded[5]; // @[pla.scala:81:23]
wire insn_wfi = system_insn & decoded[4]; // @[pla.scala:81:23]
wire [11:0] addr = io_decode_0_inst_0[31:20]; // @[CSR.scala:377:7, :897:27]
wire [11:0] io_decode_0_fp_csr_plaInput = addr; // @[pla.scala:77:22]
wire [11:0] io_decode_0_vector_csr_plaInput = addr; // @[pla.scala:77:22]
wire [11:0] io_decode_0_read_illegal_plaInput = addr; // @[pla.scala:77:22]
wire [11:0] io_decode_0_read_illegal_plaInput_1 = addr; // @[pla.scala:77:22]
wire [31:0] decoded_invInputs_1 = ~decoded_plaInput_1; // @[pla.scala:77:22, :78:21]
wire [8:0] decoded_invMatrixOutputs_1; // @[pla.scala:120:37]
wire [8:0] decoded_1; // @[pla.scala:81:23]
wire decoded_andMatrixOutputs_andMatrixInput_0_7 = decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_7 = decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_8 = decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_6 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_7 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_9 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_6 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_7 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_8 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_10 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_12 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_6 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_7 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_8 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_9 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_2_11 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_6 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_7 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_8 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_9 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_11 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_6_6 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_6_7 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_8 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_9 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_11_5 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_11 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_7_6 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_7_7 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_6_8 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_9 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_12_1 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_5_11 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_6 = decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_7 = decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_6 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_7 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_7_9 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_14_1 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_10_3 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_10_4 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_8 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_9 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_15_1 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_11 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_11_3 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_11_4 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_8 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_9 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_16_1 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_11 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_1_13 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29]
wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_andMatrixOutputs_andMatrixInput_10_3}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_lo_6 = {decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_6 = {decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_6 = {decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_8_6}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_andMatrixOutputs_lo_6 = {decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_lo_6 = {decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_6 = {decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_6 = {decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_andMatrixOutputs_hi_6 = {decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53]
wire [11:0] _decoded_andMatrixOutputs_T_7 = {decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_6_2_1 = &_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_13 = decoded_andMatrixOutputs_6_2_1; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_0_8 = decoded_plaInput_1[20]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_andMatrixOutputs_andMatrixInput_10_4}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_lo_7 = {decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_7 = {decoded_andMatrixOutputs_andMatrixInput_6_7, decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_7 = {decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_8_7}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_andMatrixOutputs_lo_7 = {decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_lo_7 = {decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_7 = {decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_7 = {decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:91:29, :98:53]
wire [5:0] decoded_andMatrixOutputs_hi_7 = {decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53]
wire [11:0] _decoded_andMatrixOutputs_T_8 = {decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_4_2_1 = &_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_12 = decoded_andMatrixOutputs_4_2_1; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_0_9 = decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_0_11 = decoded_plaInput_1[0]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_7_8 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_6_9 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_13_1 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_6_11 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_8 = {decoded_andMatrixOutputs_andMatrixInput_8_8, decoded_andMatrixOutputs_andMatrixInput_9_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_8 = {decoded_andMatrixOutputs_andMatrixInput_5_8, decoded_andMatrixOutputs_andMatrixInput_6_8}; // @[pla.scala:91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_8 = {decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_andMatrixOutputs_lo_8 = {decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_8 = {decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_8 = {decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_8 = {decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_hi_8 = {decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53]
wire [9:0] _decoded_andMatrixOutputs_T_9 = {decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_3_2_1 = &_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}]
wire decoded_andMatrixOutputs_andMatrixInput_0_10 = decoded_plaInput_1[22]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_0_12 = decoded_plaInput_1[22]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_9 = {decoded_andMatrixOutputs_andMatrixInput_8_9, decoded_andMatrixOutputs_andMatrixInput_9_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_9 = {decoded_andMatrixOutputs_andMatrixInput_5_9, decoded_andMatrixOutputs_andMatrixInput_6_9}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_9 = {decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_lo_9 = {decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_9 = {decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_9 = {decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_9 = {decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_hi_9 = {decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53]
wire [9:0] _decoded_andMatrixOutputs_T_10 = {decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_1_2_1 = &_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_8 = decoded_andMatrixOutputs_1_2_1; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_1_11 = decoded_plaInput_1[1]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_2_10 = decoded_invInputs_1[2]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_3_10 = decoded_invInputs_1[3]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_4_10 = decoded_plaInput_1[4]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_5_10 = decoded_plaInput_1[5]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_6_10 = decoded_plaInput_1[6]; // @[pla.scala:77:22, :90:45]
wire decoded_andMatrixOutputs_andMatrixInput_7_10 = decoded_invInputs_1[7]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_8_10 = decoded_invInputs_1[8]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_9_10 = decoded_invInputs_1[9]; // @[pla.scala:78:21, :91:29]
wire decoded_andMatrixOutputs_andMatrixInput_10_5 = decoded_plaInput_1[25]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_15_1, decoded_andMatrixOutputs_andMatrixInput_16_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_13_1, decoded_andMatrixOutputs_andMatrixInput_14_1}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoded_andMatrixOutputs_lo_lo_10 = {decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_lo_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_11_5, decoded_andMatrixOutputs_andMatrixInput_12_1}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_10 = {decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_andMatrixOutputs_andMatrixInput_10_5}; // @[pla.scala:90:45, :91:29, :98:53]
wire [3:0] decoded_andMatrixOutputs_lo_hi_10 = {decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_lo_hi_lo_1}; // @[pla.scala:98:53]
wire [7:0] decoded_andMatrixOutputs_lo_10 = {decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_7_10, decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_5_10, decoded_andMatrixOutputs_andMatrixInput_6_10}; // @[pla.scala:90:45, :98:53]
wire [3:0] decoded_andMatrixOutputs_hi_lo_10 = {decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_hi_lo_lo_1}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_lo_1 = {decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_hi_10 = {decoded_andMatrixOutputs_hi_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_hi_hi_10 = {decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_hi_hi_lo_1}; // @[pla.scala:98:53]
wire [8:0] decoded_andMatrixOutputs_hi_10 = {decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53]
wire [16:0] _decoded_andMatrixOutputs_T_11 = {decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_0_2_1 = &_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_7 = decoded_andMatrixOutputs_0_2_1; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_7_11 = decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45]
wire [1:0] decoded_andMatrixOutputs_lo_lo_11 = {decoded_andMatrixOutputs_andMatrixInput_8_11, decoded_andMatrixOutputs_andMatrixInput_9_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_11 = {decoded_andMatrixOutputs_andMatrixInput_5_11, decoded_andMatrixOutputs_andMatrixInput_6_11}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_lo_hi_11 = {decoded_andMatrixOutputs_lo_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:90:45, :98:53]
wire [4:0] decoded_andMatrixOutputs_lo_11 = {decoded_andMatrixOutputs_lo_hi_11, decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53]
wire [1:0] decoded_andMatrixOutputs_hi_lo_11 = {decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:91:29, :98:53]
wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_11 = {decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :91:29, :98:53]
wire [2:0] decoded_andMatrixOutputs_hi_hi_11 = {decoded_andMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:91:29, :98:53]
wire [4:0] decoded_andMatrixOutputs_hi_11 = {decoded_andMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53]
wire [9:0] _decoded_andMatrixOutputs_T_12 = {decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53]
wire decoded_andMatrixOutputs_5_2_1 = &_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}]
wire _decoded_orMatrixOutputs_T_9 = decoded_andMatrixOutputs_5_2_1; // @[pla.scala:98:70, :114:36]
wire decoded_andMatrixOutputs_andMatrixInput_0_13 = decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45]
wire [1:0] _decoded_andMatrixOutputs_T_13 = {decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :91:29, :98:53]
wire decoded_andMatrixOutputs_2_2_1 = &_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}]
wire [1:0] _decoded_orMatrixOutputs_T_10 = {decoded_andMatrixOutputs_3_2_1, decoded_andMatrixOutputs_2_2_1}; // @[pla.scala:98:70, :114:19]
wire _decoded_orMatrixOutputs_T_11 = |_decoded_orMatrixOutputs_T_10; // @[pla.scala:114:{19,36}]
wire [1:0] decoded_orMatrixOutputs_lo_hi_1 = {_decoded_orMatrixOutputs_T_7, 1'h0}; // @[pla.scala:102:36, :114:36]
wire [3:0] decoded_orMatrixOutputs_lo_1 = {decoded_orMatrixOutputs_lo_hi_1, 2'h0}; // @[pla.scala:102:36]
wire [1:0] decoded_orMatrixOutputs_hi_lo_1 = {_decoded_orMatrixOutputs_T_9, _decoded_orMatrixOutputs_T_8}; // @[pla.scala:102:36, :114:36]
wire [1:0] decoded_orMatrixOutputs_hi_hi_hi_1 = {_decoded_orMatrixOutputs_T_13, _decoded_orMatrixOutputs_T_12}; // @[pla.scala:102:36, :114:36]
wire [2:0] decoded_orMatrixOutputs_hi_hi_1 = {decoded_orMatrixOutputs_hi_hi_hi_1, _decoded_orMatrixOutputs_T_11}; // @[pla.scala:102:36, :114:36]
wire [4:0] decoded_orMatrixOutputs_hi_1 = {decoded_orMatrixOutputs_hi_hi_1, decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:102:36]
wire [8:0] decoded_orMatrixOutputs_1 = {decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1}; // @[pla.scala:102:36]
wire _decoded_invMatrixOutputs_T_9 = decoded_orMatrixOutputs_1[0]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_10 = decoded_orMatrixOutputs_1[1]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_11 = decoded_orMatrixOutputs_1[2]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_12 = decoded_orMatrixOutputs_1[3]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_13 = decoded_orMatrixOutputs_1[4]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_14 = decoded_orMatrixOutputs_1[5]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_15 = decoded_orMatrixOutputs_1[6]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_16 = decoded_orMatrixOutputs_1[7]; // @[pla.scala:102:36, :124:31]
wire _decoded_invMatrixOutputs_T_17 = decoded_orMatrixOutputs_1[8]; // @[pla.scala:102:36, :124:31]
wire [1:0] decoded_invMatrixOutputs_lo_lo_1 = {_decoded_invMatrixOutputs_T_10, _decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_invMatrixOutputs_lo_hi_1 = {_decoded_invMatrixOutputs_T_12, _decoded_invMatrixOutputs_T_11}; // @[pla.scala:120:37, :124:31]
wire [3:0] decoded_invMatrixOutputs_lo_1 = {decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1}; // @[pla.scala:120:37]
wire [1:0] decoded_invMatrixOutputs_hi_lo_1 = {_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31]
wire [1:0] decoded_invMatrixOutputs_hi_hi_hi_1 = {_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31]
wire [2:0] decoded_invMatrixOutputs_hi_hi_1 = {decoded_invMatrixOutputs_hi_hi_hi_1, _decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31]
wire [4:0] decoded_invMatrixOutputs_hi_1 = {decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1}; // @[pla.scala:120:37]
assign decoded_invMatrixOutputs_1 = {decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1}; // @[pla.scala:120:37]
assign decoded_1 = decoded_invMatrixOutputs_1; // @[pla.scala:81:23, :120:37]
wire is_break = decoded_1[7]; // @[pla.scala:81:23]
wire is_ret = decoded_1[6]; // @[pla.scala:81:23]
wire is_wfi = decoded_1[4]; // @[pla.scala:81:23]
wire is_sfence = decoded_1[3]; // @[pla.scala:81:23]
wire is_hfence_vvma = decoded_1[2]; // @[pla.scala:81:23]
wire is_hfence_gvma = decoded_1[1]; // @[pla.scala:81:23]
wire is_hlsv = decoded_1[0]; // @[pla.scala:81:23]
wire _is_counter_T = addr > 12'hBFF; // @[package.scala:213:47]
wire _is_counter_T_1 = addr < 12'hC20; // @[package.scala:213:60]
wire _is_counter_T_2 = _is_counter_T & _is_counter_T_1; // @[package.scala:213:{47,55,60}]
wire _is_counter_T_3 = addr > 12'hC7F; // @[package.scala:213:47]
wire _is_counter_T_4 = addr < 12'hCA0; // @[package.scala:213:60]
wire _is_counter_T_5 = _is_counter_T_3 & _is_counter_T_4; // @[package.scala:213:{47,55,60}]
wire is_counter = _is_counter_T_2 | _is_counter_T_5; // @[package.scala:213:55]
wire _allow_wfi_T_1 = _allow_wfi_T; // @[CSR.scala:906:{42,61}]
wire _allow_wfi_T_2 = ~reg_mstatus_tw; // @[CSR.scala:395:28, :906:74]
wire _allow_wfi_T_6 = _allow_wfi_T_2; // @[CSR.scala:906:{74,90}]
wire _allow_wfi_T_3 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94]
wire allow_wfi = _allow_wfi_T_1 | _allow_wfi_T_6; // @[CSR.scala:906:{42,71,90}]
wire _allow_sfence_vma_T_1 = _allow_sfence_vma_T; // @[CSR.scala:907:{41,60}]
wire _allow_sfence_vma_T_2 = ~reg_mstatus_v & reg_mstatus_tvm; // @[CSR.scala:395:28, :907:77]
wire _allow_sfence_vma_T_3 = ~_allow_sfence_vma_T_2; // @[CSR.scala:907:{73,77}]
wire allow_sfence_vma = _allow_sfence_vma_T_1 | _allow_sfence_vma_T_3; // @[CSR.scala:907:{41,70,73}]
wire _allow_hfence_vvma_T = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :908:53]
wire _allow_hfence_vvma_T_1 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88]
wire _allow_hfence_vvma_T_2 = _allow_hfence_vvma_T & _allow_hfence_vvma_T_1; // @[CSR.scala:908:{53,68,88}]
wire _allow_hlsv_T = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :909:46]
wire _allow_hlsv_T_1 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88, :909:81]
wire _allow_hlsv_T_2 = _allow_hlsv_T_1; // @[CSR.scala:909:{81,92}]
wire _allow_hlsv_T_3 = _allow_hlsv_T & _allow_hlsv_T_2; // @[CSR.scala:909:{46,61,92}]
wire _allow_sret_T_1 = _allow_sret_T; // @[CSR.scala:910:{43,62}]
wire _allow_sret_T_2 = ~reg_mstatus_v & reg_mstatus_tsr; // @[CSR.scala:395:28, :907:77, :910:79]
wire _allow_sret_T_3 = ~_allow_sret_T_2; // @[CSR.scala:910:{75,79}]
wire allow_sret = _allow_sret_T_1 | _allow_sret_T_3; // @[CSR.scala:910:{43,72,75}]
wire [4:0] counter_addr = addr[4:0]; // @[CSR.scala:897:27, :911:28]
wire [31:0] _GEN_10 = {27'h0, counter_addr}; // @[CSR.scala:911:28, :912:70]
wire [31:0] _GEN_11 = read_mcounteren >> _GEN_10; // @[CSR.scala:532:14, :912:70]
wire [31:0] _allow_counter_T_1; // @[CSR.scala:912:70]
assign _allow_counter_T_1 = _GEN_11; // @[CSR.scala:912:70]
wire [31:0] _io_decode_0_virtual_access_illegal_T_3; // @[CSR.scala:945:36]
assign _io_decode_0_virtual_access_illegal_T_3 = _GEN_11; // @[CSR.scala:912:70, :945:36]
wire _allow_counter_T_2 = _allow_counter_T_1[0]; // @[CSR.scala:912:70]
wire _allow_counter_T_3 = _allow_counter_T | _allow_counter_T_2; // @[CSR.scala:912:{42,52,70}]
wire _allow_counter_T_5 = |reg_mstatus_prv; // @[CSR.scala:395:28, :908:88, :913:46]
wire _allow_counter_T_6 = _allow_counter_T_5; // @[CSR.scala:913:{27,46}]
wire [31:0] _GEN_12 = read_scounteren >> _GEN_10; // @[CSR.scala:536:14, :912:70, :913:75]
wire [31:0] _allow_counter_T_7; // @[CSR.scala:913:75]
assign _allow_counter_T_7 = _GEN_12; // @[CSR.scala:913:75]
wire [31:0] _io_decode_0_virtual_access_illegal_T_11; // @[CSR.scala:945:128]
assign _io_decode_0_virtual_access_illegal_T_11 = _GEN_12; // @[CSR.scala:913:75, :945:128]
wire _allow_counter_T_8 = _allow_counter_T_7[0]; // @[CSR.scala:913:75]
wire _allow_counter_T_9 = _allow_counter_T_6 | _allow_counter_T_8; // @[CSR.scala:913:{27,57,75}]
wire _allow_counter_T_10 = _allow_counter_T_3 & _allow_counter_T_9; // @[CSR.scala:912:{52,86}, :913:57]
wire allow_counter = _allow_counter_T_10; // @[CSR.scala:912:86, :913:91]
wire _allow_counter_T_12 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :914:30]
wire [31:0] _GEN_13 = 32'h0 >> _GEN_10; // @[CSR.scala:912:70, :914:63]
wire [31:0] _allow_counter_T_14; // @[CSR.scala:914:63]
assign _allow_counter_T_14 = _GEN_13; // @[CSR.scala:914:63]
wire [31:0] _io_decode_0_virtual_access_illegal_T_6; // @[CSR.scala:945:71]
assign _io_decode_0_virtual_access_illegal_T_6 = _GEN_13; // @[CSR.scala:914:63, :945:71]
wire _allow_counter_T_15 = _allow_counter_T_14[0]; // @[CSR.scala:914:63]
wire _io_decode_0_fp_illegal_T = io_status_fs_0 == 2'h0; // @[CSR.scala:377:7, :915:39]
wire _io_decode_0_fp_illegal_T_2 = reg_mstatus_v & _io_decode_0_fp_illegal_T_1; // @[CSR.scala:395:28, :915:{64,83}]
wire _io_decode_0_fp_illegal_T_3 = _io_decode_0_fp_illegal_T | _io_decode_0_fp_illegal_T_2; // @[CSR.scala:915:{39,47,64}]
wire _io_decode_0_fp_illegal_T_4 = reg_misa[5]; // @[CSR.scala:648:25, :915:103]
wire _io_decode_0_fp_illegal_T_5 = ~_io_decode_0_fp_illegal_T_4; // @[CSR.scala:915:{94,103}]
assign _io_decode_0_fp_illegal_T_6 = _io_decode_0_fp_illegal_T_3 | _io_decode_0_fp_illegal_T_5; // @[CSR.scala:915:{47,91,94}]
assign io_decode_0_fp_illegal_0 = _io_decode_0_fp_illegal_T_6; // @[CSR.scala:377:7, :915:91]
wire _io_decode_0_vector_illegal_T_2 = reg_mstatus_v & _io_decode_0_vector_illegal_T_1; // @[CSR.scala:395:28, :916:{68,87}]
wire _io_decode_0_vector_illegal_T_4 = reg_misa[21]; // @[CSR.scala:648:25, :916:107]
wire _io_decode_0_vector_illegal_T_5 = ~_io_decode_0_vector_illegal_T_4; // @[CSR.scala:916:{98,107}]
wire [11:0] io_decode_0_fp_csr_invInputs = ~io_decode_0_fp_csr_plaInput; // @[pla.scala:77:22, :78:21]
wire io_decode_0_fp_csr_invMatrixOutputs; // @[pla.scala:124:31]
wire io_decode_0_fp_csr_plaOutput; // @[pla.scala:81:23]
assign _io_decode_0_fp_csr_T = io_decode_0_fp_csr_plaOutput; // @[pla.scala:81:23]
wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0 = io_decode_0_fp_csr_invInputs[8]; // @[pla.scala:78:21, :91:29]
wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1 = io_decode_0_fp_csr_invInputs[9]; // @[pla.scala:78:21, :91:29]
wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2 = io_decode_0_fp_csr_invInputs[10]; // @[pla.scala:78:21, :91:29]
wire io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3 = io_decode_0_fp_csr_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire [1:0] io_decode_0_fp_csr_andMatrixOutputs_lo = {io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_2, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:91:29, :98:53]
wire [1:0] io_decode_0_fp_csr_andMatrixOutputs_hi = {io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_0, io_decode_0_fp_csr_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53]
wire [3:0] _io_decode_0_fp_csr_andMatrixOutputs_T = {io_decode_0_fp_csr_andMatrixOutputs_hi, io_decode_0_fp_csr_andMatrixOutputs_lo}; // @[pla.scala:98:53]
wire io_decode_0_fp_csr_andMatrixOutputs_0_2 = &_io_decode_0_fp_csr_andMatrixOutputs_T; // @[pla.scala:98:{53,70}]
wire io_decode_0_fp_csr_orMatrixOutputs = io_decode_0_fp_csr_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36]
assign io_decode_0_fp_csr_invMatrixOutputs = io_decode_0_fp_csr_orMatrixOutputs; // @[pla.scala:114:36, :124:31]
assign io_decode_0_fp_csr_plaOutput = io_decode_0_fp_csr_invMatrixOutputs; // @[pla.scala:81:23, :124:31]
assign io_decode_0_fp_csr_0 = _io_decode_0_fp_csr_T; // @[Decode.scala:55:116]
wire [11:0] io_decode_0_vector_csr_invInputs = ~io_decode_0_vector_csr_plaInput; // @[pla.scala:77:22, :78:21]
wire _io_decode_0_rocc_illegal_T_4 = reg_misa[23]; // @[CSR.scala:648:25, :919:105]
wire _io_decode_0_rocc_illegal_T_5 = ~_io_decode_0_rocc_illegal_T_4; // @[CSR.scala:919:{96,105}]
assign _io_decode_0_rocc_illegal_T_6 = _io_decode_0_rocc_illegal_T_5; // @[CSR.scala:919:{93,96}]
assign io_decode_0_rocc_illegal_0 = _io_decode_0_rocc_illegal_T_6; // @[CSR.scala:377:7, :919:93]
wire [1:0] _csr_addr_legal_T = addr[9:8]; // @[CSR.scala:190:36, :897:27]
wire [1:0] _csr_addr_legal_T_6 = addr[9:8]; // @[CSR.scala:190:36, :897:27]
wire [1:0] _io_decode_0_virtual_access_illegal_T_1 = addr[9:8]; // @[CSR.scala:190:36, :897:27]
wire [1:0] _io_decode_0_virtual_access_illegal_T_18 = addr[9:8]; // @[CSR.scala:190:36, :897:27]
wire [1:0] _io_decode_0_virtual_system_illegal_T_9 = addr[9:8]; // @[CSR.scala:190:36, :897:27]
wire _csr_addr_legal_T_1 = reg_mstatus_prv >= _csr_addr_legal_T; // @[CSR.scala:190:36, :395:28, :920:42]
wire csr_addr_legal = _csr_addr_legal_T_1; // @[CSR.scala:920:{42,60}]
wire _csr_addr_legal_T_2 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :921:28]
wire _csr_addr_legal_T_7 = _csr_addr_legal_T_6 == 2'h2; // @[CSR.scala:190:36, :921:92]
wire _csr_exists_T = addr == 12'h7A0; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_1 = addr == 12'h7A1; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_2 = addr == 12'h7A2; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_3 = addr == 12'h7A3; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_4 = addr == 12'h301; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_5 = addr == 12'h300; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_6 = addr == 12'h305; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_7 = addr == 12'h344; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_8 = addr == 12'h304; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_9 = addr == 12'h340; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_10 = addr == 12'h341; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_11 = addr == 12'h343; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_12 = addr == 12'h342; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_13 = addr == 12'hF14; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_14 = addr == 12'h7B0; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_15 = addr == 12'h7B1; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_16 = addr == 12'h7B2; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_17 = addr == 12'h1; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_18 = addr == 12'h2; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_19 = addr == 12'h3; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_20 = addr == 12'h320; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_21 = addr == 12'hB00; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_22 = addr == 12'hB02; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_23 = addr == 12'h323; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_24 = addr == 12'hB03; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_25 = addr == 12'hC03; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_26 = addr == 12'h324; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_27 = addr == 12'hB04; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_28 = addr == 12'hC04; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_29 = addr == 12'h325; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_30 = addr == 12'hB05; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_31 = addr == 12'hC05; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_32 = addr == 12'h326; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_33 = addr == 12'hB06; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_34 = addr == 12'hC06; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_35 = addr == 12'h327; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_36 = addr == 12'hB07; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_37 = addr == 12'hC07; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_38 = addr == 12'h328; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_39 = addr == 12'hB08; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_40 = addr == 12'hC08; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_41 = addr == 12'h329; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_42 = addr == 12'hB09; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_43 = addr == 12'hC09; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_44 = addr == 12'h32A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_45 = addr == 12'hB0A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_46 = addr == 12'hC0A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_47 = addr == 12'h32B; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_48 = addr == 12'hB0B; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_49 = addr == 12'hC0B; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_50 = addr == 12'h32C; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_51 = addr == 12'hB0C; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_52 = addr == 12'hC0C; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_53 = addr == 12'h32D; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_54 = addr == 12'hB0D; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_55 = addr == 12'hC0D; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_56 = addr == 12'h32E; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_57 = addr == 12'hB0E; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_58 = addr == 12'hC0E; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_59 = addr == 12'h32F; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_60 = addr == 12'hB0F; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_61 = addr == 12'hC0F; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_62 = addr == 12'h330; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_63 = addr == 12'hB10; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_64 = addr == 12'hC10; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_65 = addr == 12'h331; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_66 = addr == 12'hB11; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_67 = addr == 12'hC11; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_68 = addr == 12'h332; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_69 = addr == 12'hB12; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_70 = addr == 12'hC12; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_71 = addr == 12'h333; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_72 = addr == 12'hB13; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_73 = addr == 12'hC13; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_74 = addr == 12'h334; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_75 = addr == 12'hB14; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_76 = addr == 12'hC14; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_77 = addr == 12'h335; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_78 = addr == 12'hB15; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_79 = addr == 12'hC15; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_80 = addr == 12'h336; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_81 = addr == 12'hB16; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_82 = addr == 12'hC16; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_83 = addr == 12'h337; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_84 = addr == 12'hB17; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_85 = addr == 12'hC17; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_86 = addr == 12'h338; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_87 = addr == 12'hB18; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_88 = addr == 12'hC18; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_89 = addr == 12'h339; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_90 = addr == 12'hB19; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_91 = addr == 12'hC19; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_92 = addr == 12'h33A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_93 = addr == 12'hB1A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_94 = addr == 12'hC1A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_95 = addr == 12'h33B; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_96 = addr == 12'hB1B; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_97 = addr == 12'hC1B; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_98 = addr == 12'h33C; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_99 = addr == 12'hB1C; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_100 = addr == 12'hC1C; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_101 = addr == 12'h33D; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_102 = addr == 12'hB1D; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_103 = addr == 12'hC1D; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_104 = addr == 12'h33E; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_105 = addr == 12'hB1E; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_106 = addr == 12'hC1E; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_107 = addr == 12'h33F; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_108 = addr == 12'hB1F; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_109 = addr == 12'hC1F; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_110 = addr == 12'h306; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_111 = addr == 12'hC00; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_112 = addr == 12'hC02; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_113 = addr == 12'h30A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_114 = addr == 12'h100; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_115 = addr == 12'h144; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_116 = addr == 12'h104; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_117 = addr == 12'h140; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_118 = addr == 12'h142; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_119 = addr == 12'h143; // @[CSR.scala:897:27, :899:93]
wire _GEN_14 = addr == 12'h180; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_120; // @[CSR.scala:899:93]
assign _csr_exists_T_120 = _GEN_14; // @[CSR.scala:899:93]
wire _io_decode_0_read_illegal_T_3; // @[CSR.scala:925:14]
assign _io_decode_0_read_illegal_T_3 = _GEN_14; // @[CSR.scala:899:93, :925:14]
wire _io_decode_0_virtual_access_illegal_T_24; // @[CSR.scala:947:12]
assign _io_decode_0_virtual_access_illegal_T_24 = _GEN_14; // @[CSR.scala:899:93, :947:12]
wire _csr_exists_T_121 = addr == 12'h141; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_122 = addr == 12'h105; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_123 = addr == 12'h106; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_124 = addr == 12'h303; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_125 = addr == 12'h302; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_126 = addr == 12'h10A; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_127 = addr == 12'h3A0; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_128 = addr == 12'h3A2; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_129 = addr == 12'h3B0; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_130 = addr == 12'h3B1; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_131 = addr == 12'h3B2; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_132 = addr == 12'h3B3; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_133 = addr == 12'h3B4; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_134 = addr == 12'h3B5; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_135 = addr == 12'h3B6; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_136 = addr == 12'h3B7; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_137 = addr == 12'h3B8; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_138 = addr == 12'h3B9; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_139 = addr == 12'h3BA; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_140 = addr == 12'h3BB; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_141 = addr == 12'h3BC; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_142 = addr == 12'h3BD; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_143 = addr == 12'h3BE; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_144 = addr == 12'h3BF; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_145 = addr == 12'h7C1; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_146 = addr == 12'hF12; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_147 = addr == 12'hF11; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_148 = addr == 12'hF13; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_149 = addr == 12'hF15; // @[CSR.scala:897:27, :899:93]
wire _csr_exists_T_150 = _csr_exists_T | _csr_exists_T_1; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_151 = _csr_exists_T_150 | _csr_exists_T_2; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_152 = _csr_exists_T_151 | _csr_exists_T_3; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_153 = _csr_exists_T_152 | _csr_exists_T_4; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_154 = _csr_exists_T_153 | _csr_exists_T_5; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_155 = _csr_exists_T_154 | _csr_exists_T_6; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_156 = _csr_exists_T_155 | _csr_exists_T_7; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_157 = _csr_exists_T_156 | _csr_exists_T_8; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_158 = _csr_exists_T_157 | _csr_exists_T_9; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_159 = _csr_exists_T_158 | _csr_exists_T_10; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_160 = _csr_exists_T_159 | _csr_exists_T_11; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_161 = _csr_exists_T_160 | _csr_exists_T_12; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_162 = _csr_exists_T_161 | _csr_exists_T_13; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_163 = _csr_exists_T_162 | _csr_exists_T_14; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_164 = _csr_exists_T_163 | _csr_exists_T_15; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_165 = _csr_exists_T_164 | _csr_exists_T_16; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_166 = _csr_exists_T_165 | _csr_exists_T_17; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_167 = _csr_exists_T_166 | _csr_exists_T_18; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_168 = _csr_exists_T_167 | _csr_exists_T_19; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_169 = _csr_exists_T_168 | _csr_exists_T_20; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_170 = _csr_exists_T_169 | _csr_exists_T_21; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_171 = _csr_exists_T_170 | _csr_exists_T_22; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_172 = _csr_exists_T_171 | _csr_exists_T_23; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_173 = _csr_exists_T_172 | _csr_exists_T_24; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_174 = _csr_exists_T_173 | _csr_exists_T_25; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_175 = _csr_exists_T_174 | _csr_exists_T_26; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_176 = _csr_exists_T_175 | _csr_exists_T_27; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_177 = _csr_exists_T_176 | _csr_exists_T_28; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_178 = _csr_exists_T_177 | _csr_exists_T_29; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_179 = _csr_exists_T_178 | _csr_exists_T_30; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_180 = _csr_exists_T_179 | _csr_exists_T_31; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_181 = _csr_exists_T_180 | _csr_exists_T_32; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_182 = _csr_exists_T_181 | _csr_exists_T_33; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_183 = _csr_exists_T_182 | _csr_exists_T_34; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_184 = _csr_exists_T_183 | _csr_exists_T_35; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_185 = _csr_exists_T_184 | _csr_exists_T_36; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_186 = _csr_exists_T_185 | _csr_exists_T_37; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_187 = _csr_exists_T_186 | _csr_exists_T_38; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_188 = _csr_exists_T_187 | _csr_exists_T_39; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_189 = _csr_exists_T_188 | _csr_exists_T_40; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_190 = _csr_exists_T_189 | _csr_exists_T_41; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_191 = _csr_exists_T_190 | _csr_exists_T_42; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_192 = _csr_exists_T_191 | _csr_exists_T_43; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_193 = _csr_exists_T_192 | _csr_exists_T_44; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_194 = _csr_exists_T_193 | _csr_exists_T_45; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_195 = _csr_exists_T_194 | _csr_exists_T_46; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_196 = _csr_exists_T_195 | _csr_exists_T_47; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_197 = _csr_exists_T_196 | _csr_exists_T_48; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_198 = _csr_exists_T_197 | _csr_exists_T_49; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_199 = _csr_exists_T_198 | _csr_exists_T_50; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_200 = _csr_exists_T_199 | _csr_exists_T_51; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_201 = _csr_exists_T_200 | _csr_exists_T_52; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_202 = _csr_exists_T_201 | _csr_exists_T_53; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_203 = _csr_exists_T_202 | _csr_exists_T_54; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_204 = _csr_exists_T_203 | _csr_exists_T_55; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_205 = _csr_exists_T_204 | _csr_exists_T_56; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_206 = _csr_exists_T_205 | _csr_exists_T_57; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_207 = _csr_exists_T_206 | _csr_exists_T_58; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_208 = _csr_exists_T_207 | _csr_exists_T_59; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_209 = _csr_exists_T_208 | _csr_exists_T_60; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_210 = _csr_exists_T_209 | _csr_exists_T_61; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_211 = _csr_exists_T_210 | _csr_exists_T_62; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_212 = _csr_exists_T_211 | _csr_exists_T_63; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_213 = _csr_exists_T_212 | _csr_exists_T_64; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_214 = _csr_exists_T_213 | _csr_exists_T_65; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_215 = _csr_exists_T_214 | _csr_exists_T_66; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_216 = _csr_exists_T_215 | _csr_exists_T_67; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_217 = _csr_exists_T_216 | _csr_exists_T_68; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_218 = _csr_exists_T_217 | _csr_exists_T_69; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_219 = _csr_exists_T_218 | _csr_exists_T_70; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_220 = _csr_exists_T_219 | _csr_exists_T_71; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_221 = _csr_exists_T_220 | _csr_exists_T_72; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_222 = _csr_exists_T_221 | _csr_exists_T_73; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_223 = _csr_exists_T_222 | _csr_exists_T_74; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_224 = _csr_exists_T_223 | _csr_exists_T_75; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_225 = _csr_exists_T_224 | _csr_exists_T_76; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_226 = _csr_exists_T_225 | _csr_exists_T_77; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_227 = _csr_exists_T_226 | _csr_exists_T_78; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_228 = _csr_exists_T_227 | _csr_exists_T_79; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_229 = _csr_exists_T_228 | _csr_exists_T_80; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_230 = _csr_exists_T_229 | _csr_exists_T_81; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_231 = _csr_exists_T_230 | _csr_exists_T_82; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_232 = _csr_exists_T_231 | _csr_exists_T_83; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_233 = _csr_exists_T_232 | _csr_exists_T_84; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_234 = _csr_exists_T_233 | _csr_exists_T_85; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_235 = _csr_exists_T_234 | _csr_exists_T_86; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_236 = _csr_exists_T_235 | _csr_exists_T_87; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_237 = _csr_exists_T_236 | _csr_exists_T_88; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_238 = _csr_exists_T_237 | _csr_exists_T_89; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_239 = _csr_exists_T_238 | _csr_exists_T_90; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_240 = _csr_exists_T_239 | _csr_exists_T_91; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_241 = _csr_exists_T_240 | _csr_exists_T_92; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_242 = _csr_exists_T_241 | _csr_exists_T_93; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_243 = _csr_exists_T_242 | _csr_exists_T_94; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_244 = _csr_exists_T_243 | _csr_exists_T_95; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_245 = _csr_exists_T_244 | _csr_exists_T_96; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_246 = _csr_exists_T_245 | _csr_exists_T_97; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_247 = _csr_exists_T_246 | _csr_exists_T_98; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_248 = _csr_exists_T_247 | _csr_exists_T_99; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_249 = _csr_exists_T_248 | _csr_exists_T_100; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_250 = _csr_exists_T_249 | _csr_exists_T_101; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_251 = _csr_exists_T_250 | _csr_exists_T_102; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_252 = _csr_exists_T_251 | _csr_exists_T_103; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_253 = _csr_exists_T_252 | _csr_exists_T_104; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_254 = _csr_exists_T_253 | _csr_exists_T_105; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_255 = _csr_exists_T_254 | _csr_exists_T_106; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_256 = _csr_exists_T_255 | _csr_exists_T_107; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_257 = _csr_exists_T_256 | _csr_exists_T_108; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_258 = _csr_exists_T_257 | _csr_exists_T_109; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_259 = _csr_exists_T_258 | _csr_exists_T_110; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_260 = _csr_exists_T_259 | _csr_exists_T_111; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_261 = _csr_exists_T_260 | _csr_exists_T_112; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_262 = _csr_exists_T_261 | _csr_exists_T_113; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_263 = _csr_exists_T_262 | _csr_exists_T_114; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_264 = _csr_exists_T_263 | _csr_exists_T_115; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_265 = _csr_exists_T_264 | _csr_exists_T_116; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_266 = _csr_exists_T_265 | _csr_exists_T_117; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_267 = _csr_exists_T_266 | _csr_exists_T_118; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_268 = _csr_exists_T_267 | _csr_exists_T_119; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_269 = _csr_exists_T_268 | _csr_exists_T_120; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_270 = _csr_exists_T_269 | _csr_exists_T_121; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_271 = _csr_exists_T_270 | _csr_exists_T_122; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_272 = _csr_exists_T_271 | _csr_exists_T_123; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_273 = _csr_exists_T_272 | _csr_exists_T_124; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_274 = _csr_exists_T_273 | _csr_exists_T_125; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_275 = _csr_exists_T_274 | _csr_exists_T_126; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_276 = _csr_exists_T_275 | _csr_exists_T_127; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_277 = _csr_exists_T_276 | _csr_exists_T_128; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_278 = _csr_exists_T_277 | _csr_exists_T_129; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_279 = _csr_exists_T_278 | _csr_exists_T_130; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_280 = _csr_exists_T_279 | _csr_exists_T_131; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_281 = _csr_exists_T_280 | _csr_exists_T_132; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_282 = _csr_exists_T_281 | _csr_exists_T_133; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_283 = _csr_exists_T_282 | _csr_exists_T_134; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_284 = _csr_exists_T_283 | _csr_exists_T_135; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_285 = _csr_exists_T_284 | _csr_exists_T_136; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_286 = _csr_exists_T_285 | _csr_exists_T_137; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_287 = _csr_exists_T_286 | _csr_exists_T_138; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_288 = _csr_exists_T_287 | _csr_exists_T_139; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_289 = _csr_exists_T_288 | _csr_exists_T_140; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_290 = _csr_exists_T_289 | _csr_exists_T_141; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_291 = _csr_exists_T_290 | _csr_exists_T_142; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_292 = _csr_exists_T_291 | _csr_exists_T_143; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_293 = _csr_exists_T_292 | _csr_exists_T_144; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_294 = _csr_exists_T_293 | _csr_exists_T_145; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_295 = _csr_exists_T_294 | _csr_exists_T_146; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_296 = _csr_exists_T_295 | _csr_exists_T_147; // @[CSR.scala:899:{93,111}]
wire _csr_exists_T_297 = _csr_exists_T_296 | _csr_exists_T_148; // @[CSR.scala:899:{93,111}]
wire csr_exists = _csr_exists_T_297 | _csr_exists_T_149; // @[CSR.scala:899:{93,111}]
wire _io_decode_0_read_illegal_T = ~csr_addr_legal; // @[CSR.scala:920:60, :923:28]
wire _io_decode_0_read_illegal_T_1 = ~csr_exists; // @[CSR.scala:899:111, :924:7]
wire _io_decode_0_read_illegal_T_2 = _io_decode_0_read_illegal_T | _io_decode_0_read_illegal_T_1; // @[CSR.scala:923:{28,44}, :924:7]
wire _io_decode_0_read_illegal_T_4 = addr == 12'h680; // @[CSR.scala:897:27, :925:38]
wire _io_decode_0_read_illegal_T_5 = _io_decode_0_read_illegal_T_3 | _io_decode_0_read_illegal_T_4; // @[CSR.scala:925:{14,30,38}]
wire _io_decode_0_read_illegal_T_6 = ~allow_sfence_vma; // @[CSR.scala:907:70, :925:59]
wire _io_decode_0_read_illegal_T_7 = _io_decode_0_read_illegal_T_5 & _io_decode_0_read_illegal_T_6; // @[CSR.scala:925:{30,56,59}]
wire _io_decode_0_read_illegal_T_8 = _io_decode_0_read_illegal_T_2 | _io_decode_0_read_illegal_T_7; // @[CSR.scala:923:44, :924:19, :925:56]
wire _io_decode_0_read_illegal_T_9 = ~allow_counter; // @[CSR.scala:913:91, :926:21]
wire _io_decode_0_read_illegal_T_10 = is_counter & _io_decode_0_read_illegal_T_9; // @[CSR.scala:904:81, :926:{18,21}]
wire _io_decode_0_read_illegal_T_11 = _io_decode_0_read_illegal_T_8 | _io_decode_0_read_illegal_T_10; // @[CSR.scala:924:19, :925:78, :926:18]
wire [11:0] io_decode_0_read_illegal_invInputs = ~io_decode_0_read_illegal_plaInput; // @[pla.scala:77:22, :78:21]
wire io_decode_0_read_illegal_invMatrixOutputs; // @[pla.scala:124:31]
wire io_decode_0_read_illegal_plaOutput; // @[pla.scala:81:23]
wire _io_decode_0_read_illegal_T_12 = io_decode_0_read_illegal_plaOutput; // @[pla.scala:81:23]
wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0 = io_decode_0_read_illegal_plaInput[4]; // @[pla.scala:77:22, :90:45]
wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1 = io_decode_0_read_illegal_plaInput[5]; // @[pla.scala:77:22, :90:45]
wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2 = io_decode_0_read_illegal_invInputs[6]; // @[pla.scala:78:21, :91:29]
wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3 = io_decode_0_read_illegal_plaInput[7]; // @[pla.scala:77:22, :90:45]
wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4 = io_decode_0_read_illegal_plaInput[8]; // @[pla.scala:77:22, :90:45]
wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5 = io_decode_0_read_illegal_plaInput[9]; // @[pla.scala:77:22, :90:45]
wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6 = io_decode_0_read_illegal_plaInput[10]; // @[pla.scala:77:22, :90:45]
wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7 = io_decode_0_read_illegal_invInputs[11]; // @[pla.scala:78:21, :91:29]
wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_lo_lo = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_lo_hi = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :98:53]
wire [3:0] io_decode_0_read_illegal_andMatrixOutputs_lo = {io_decode_0_read_illegal_andMatrixOutputs_lo_hi, io_decode_0_read_illegal_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53]
wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_hi_lo = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:90:45, :91:29, :98:53]
wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_hi_hi = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53]
wire [3:0] io_decode_0_read_illegal_andMatrixOutputs_hi = {io_decode_0_read_illegal_andMatrixOutputs_hi_hi, io_decode_0_read_illegal_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53]
wire [7:0] _io_decode_0_read_illegal_andMatrixOutputs_T = {io_decode_0_read_illegal_andMatrixOutputs_hi, io_decode_0_read_illegal_andMatrixOutputs_lo}; // @[pla.scala:98:53]
wire io_decode_0_read_illegal_andMatrixOutputs_0_2 = &_io_decode_0_read_illegal_andMatrixOutputs_T; // @[pla.scala:98:{53,70}]
wire io_decode_0_read_illegal_orMatrixOutputs = io_decode_0_read_illegal_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36]
assign io_decode_0_read_illegal_invMatrixOutputs = io_decode_0_read_illegal_orMatrixOutputs; // @[pla.scala:114:36, :124:31]
assign io_decode_0_read_illegal_plaOutput = io_decode_0_read_illegal_invMatrixOutputs; // @[pla.scala:81:23, :124:31]
wire _io_decode_0_read_illegal_T_13 = ~reg_debug; // @[CSR.scala:482:26, :927:45]
wire _io_decode_0_read_illegal_T_14 = _io_decode_0_read_illegal_T_12 & _io_decode_0_read_illegal_T_13; // @[Decode.scala:55:116]
wire _io_decode_0_read_illegal_T_15 = _io_decode_0_read_illegal_T_11 | _io_decode_0_read_illegal_T_14; // @[CSR.scala:925:78, :926:36, :927:42]
wire _io_decode_0_read_illegal_T_18 = _io_decode_0_read_illegal_T_15; // @[CSR.scala:926:36, :927:56]
wire [11:0] io_decode_0_read_illegal_invInputs_1 = ~io_decode_0_read_illegal_plaInput_1; // @[pla.scala:77:22, :78:21]
wire _io_decode_0_read_illegal_T_19 = io_decode_0_fp_csr_0 & io_decode_0_fp_illegal_0; // @[CSR.scala:377:7, :929:21]
assign _io_decode_0_read_illegal_T_20 = _io_decode_0_read_illegal_T_18 | _io_decode_0_read_illegal_T_19; // @[CSR.scala:927:56, :928:68, :929:21]
assign io_decode_0_read_illegal_0 = _io_decode_0_read_illegal_T_20; // @[CSR.scala:377:7, :928:68]
wire [1:0] _io_decode_0_write_illegal_T = addr[11:10]; // @[CSR.scala:897:27, :930:33]
assign _io_decode_0_write_illegal_T_1 = &_io_decode_0_write_illegal_T; // @[CSR.scala:930:{33,41}]
assign io_decode_0_write_illegal_0 = _io_decode_0_write_illegal_T_1; // @[CSR.scala:377:7, :930:41]
wire [11:0] io_decode_0_write_flush_addr_m = {_io_decode_0_write_illegal_T, addr[9:0] | 10'h300}; // @[CSR.scala:897:27, :930:33, :932:25]
wire _io_decode_0_write_flush_T = io_decode_0_write_flush_addr_m > 12'h33F; // @[CSR.scala:932:25, :933:16]
wire _io_decode_0_write_flush_T_1 = io_decode_0_write_flush_addr_m < 12'h344; // @[CSR.scala:932:25, :933:45]
wire _io_decode_0_write_flush_T_2 = _io_decode_0_write_flush_T & _io_decode_0_write_flush_T_1; // @[CSR.scala:933:{16,35,45}]
assign _io_decode_0_write_flush_T_3 = ~_io_decode_0_write_flush_T_2; // @[CSR.scala:933:{7,35}]
assign io_decode_0_write_flush_0 = _io_decode_0_write_flush_T_3; // @[CSR.scala:377:7, :933:7]
wire _io_decode_0_system_illegal_T = ~csr_addr_legal; // @[CSR.scala:920:60, :923:28, :935:30]
wire _io_decode_0_system_illegal_T_1 = ~is_hlsv; // @[CSR.scala:903:82, :935:49]
wire _io_decode_0_system_illegal_T_2 = _io_decode_0_system_illegal_T & _io_decode_0_system_illegal_T_1; // @[CSR.scala:935:{30,46,49}]
wire _io_decode_0_system_illegal_T_3 = ~allow_wfi; // @[CSR.scala:906:71, :936:17]
wire _io_decode_0_system_illegal_T_4 = is_wfi & _io_decode_0_system_illegal_T_3; // @[CSR.scala:903:82, :936:{14,17}]
wire _io_decode_0_system_illegal_T_5 = _io_decode_0_system_illegal_T_2 | _io_decode_0_system_illegal_T_4; // @[CSR.scala:935:{46,58}, :936:14]
wire _io_decode_0_system_illegal_T_6 = ~allow_sret; // @[CSR.scala:910:72, :937:17]
wire _io_decode_0_system_illegal_T_7 = is_ret & _io_decode_0_system_illegal_T_6; // @[CSR.scala:903:82, :937:{14,17}]
wire _io_decode_0_system_illegal_T_8 = _io_decode_0_system_illegal_T_5 | _io_decode_0_system_illegal_T_7; // @[CSR.scala:935:58, :936:28, :937:14]
wire _io_decode_0_system_illegal_T_9 = addr[10]; // @[CSR.scala:897:27, :938:21]
wire _io_decode_0_system_illegal_T_10 = is_ret & _io_decode_0_system_illegal_T_9; // @[CSR.scala:903:82, :938:{14,21}]
wire _io_decode_0_system_illegal_T_11 = addr[7]; // @[CSR.scala:897:27, :938:33]
wire _io_decode_0_system_illegal_T_12 = _io_decode_0_system_illegal_T_10 & _io_decode_0_system_illegal_T_11; // @[CSR.scala:938:{14,26,33}]
wire _io_decode_0_system_illegal_T_13 = ~reg_debug; // @[CSR.scala:482:26, :927:45, :938:40]
wire _io_decode_0_system_illegal_T_14 = _io_decode_0_system_illegal_T_12 & _io_decode_0_system_illegal_T_13; // @[CSR.scala:938:{26,37,40}]
wire _io_decode_0_system_illegal_T_15 = _io_decode_0_system_illegal_T_8 | _io_decode_0_system_illegal_T_14; // @[CSR.scala:936:28, :937:29, :938:37]
wire _io_decode_0_system_illegal_T_16 = is_sfence | is_hfence_gvma; // @[CSR.scala:903:82, :939:18]
wire _io_decode_0_system_illegal_T_17 = ~allow_sfence_vma; // @[CSR.scala:907:70, :925:59, :939:40]
wire _io_decode_0_system_illegal_T_18 = _io_decode_0_system_illegal_T_16 & _io_decode_0_system_illegal_T_17; // @[CSR.scala:939:{18,37,40}]
wire _io_decode_0_system_illegal_T_19 = _io_decode_0_system_illegal_T_15 | _io_decode_0_system_illegal_T_18; // @[CSR.scala:937:29, :938:51, :939:37]
wire _io_decode_0_system_illegal_T_22 = _io_decode_0_system_illegal_T_19; // @[CSR.scala:938:51, :939:58]
assign _io_decode_0_system_illegal_T_25 = _io_decode_0_system_illegal_T_22; // @[CSR.scala:939:58, :940:44]
assign io_decode_0_system_illegal_0 = _io_decode_0_system_illegal_T_25; // @[CSR.scala:377:7, :940:44]
wire _io_decode_0_virtual_access_illegal_T = reg_mstatus_v & csr_exists; // @[CSR.scala:395:28, :899:111, :943:52]
wire _io_decode_0_virtual_access_illegal_T_2 = _io_decode_0_virtual_access_illegal_T_1 == 2'h2; // @[CSR.scala:190:36, :944:22]
wire _io_decode_0_virtual_access_illegal_T_4 = _io_decode_0_virtual_access_illegal_T_3[0]; // @[CSR.scala:945:36]
wire _io_decode_0_virtual_access_illegal_T_5 = is_counter & _io_decode_0_virtual_access_illegal_T_4; // @[CSR.scala:904:81, :945:{18,36}]
wire _io_decode_0_virtual_access_illegal_T_7 = _io_decode_0_virtual_access_illegal_T_6[0]; // @[CSR.scala:945:71]
wire _io_decode_0_virtual_access_illegal_T_8 = ~_io_decode_0_virtual_access_illegal_T_7; // @[CSR.scala:945:{55,71}]
wire _io_decode_0_virtual_access_illegal_T_9 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105]
wire _io_decode_0_virtual_access_illegal_T_20 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :946:53]
wire _io_decode_0_virtual_access_illegal_T_25 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :947:46]
wire _io_decode_0_virtual_system_illegal_T_2 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :953:34]
wire _io_decode_0_virtual_system_illegal_T_12 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :954:64]
wire _io_decode_0_virtual_system_illegal_T_17 = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :955:37]
wire _cause_T = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :959:61]
wire _reg_hstatus_spvp_T = reg_mstatus_prv[0]; // @[CSR.scala:395:28, :945:105, :1067:61]
wire _io_decode_0_virtual_access_illegal_T_10 = ~_io_decode_0_virtual_access_illegal_T_9; // @[CSR.scala:945:{89,105}]
wire _io_decode_0_virtual_access_illegal_T_12 = _io_decode_0_virtual_access_illegal_T_11[0]; // @[CSR.scala:945:128]
wire _io_decode_0_virtual_access_illegal_T_13 = ~_io_decode_0_virtual_access_illegal_T_12; // @[CSR.scala:945:{112,128}]
wire _io_decode_0_virtual_access_illegal_T_14 = _io_decode_0_virtual_access_illegal_T_10 & _io_decode_0_virtual_access_illegal_T_13; // @[CSR.scala:945:{89,109,112}]
wire _io_decode_0_virtual_access_illegal_T_15 = _io_decode_0_virtual_access_illegal_T_8 | _io_decode_0_virtual_access_illegal_T_14; // @[CSR.scala:945:{55,86,109}]
wire _io_decode_0_virtual_access_illegal_T_16 = _io_decode_0_virtual_access_illegal_T_5 & _io_decode_0_virtual_access_illegal_T_15; // @[CSR.scala:945:{18,51,86}]
wire _io_decode_0_virtual_access_illegal_T_17 = _io_decode_0_virtual_access_illegal_T_2 | _io_decode_0_virtual_access_illegal_T_16; // @[CSR.scala:944:{22,34}, :945:51]
wire _io_decode_0_virtual_access_illegal_T_19 = _io_decode_0_virtual_access_illegal_T_18 == 2'h1; // @[CSR.scala:190:36, :946:22]
wire _io_decode_0_virtual_access_illegal_T_21 = ~_io_decode_0_virtual_access_illegal_T_20; // @[CSR.scala:946:{37,53}]
wire _io_decode_0_virtual_access_illegal_T_22 = _io_decode_0_virtual_access_illegal_T_19 & _io_decode_0_virtual_access_illegal_T_21; // @[CSR.scala:946:{22,34,37}]
wire _io_decode_0_virtual_access_illegal_T_23 = _io_decode_0_virtual_access_illegal_T_17 | _io_decode_0_virtual_access_illegal_T_22; // @[CSR.scala:944:34, :945:144, :946:34]
wire _io_decode_0_virtual_access_illegal_T_28 = _io_decode_0_virtual_access_illegal_T_23; // @[CSR.scala:945:144, :946:57]
wire _io_decode_0_virtual_access_illegal_T_26 = _io_decode_0_virtual_access_illegal_T_24 & _io_decode_0_virtual_access_illegal_T_25; // @[CSR.scala:947:{12,28,46}]
assign _io_decode_0_virtual_access_illegal_T_29 = _io_decode_0_virtual_access_illegal_T & _io_decode_0_virtual_access_illegal_T_28; // @[CSR.scala:943:{52,66}, :946:57]
assign io_decode_0_virtual_access_illegal_0 = _io_decode_0_virtual_access_illegal_T_29; // @[CSR.scala:377:7, :943:66]
wire _io_decode_0_virtual_system_illegal_T = is_hfence_vvma | is_hfence_gvma; // @[CSR.scala:903:82, :950:22]
wire _io_decode_0_virtual_system_illegal_T_1 = _io_decode_0_virtual_system_illegal_T | is_hlsv; // @[CSR.scala:903:82, :950:22, :951:22]
wire _io_decode_0_virtual_system_illegal_T_3 = ~_io_decode_0_virtual_system_illegal_T_2; // @[CSR.scala:953:{18,34}]
wire _io_decode_0_virtual_system_illegal_T_6 = _io_decode_0_virtual_system_illegal_T_3; // @[CSR.scala:953:{18,38}]
wire _io_decode_0_virtual_system_illegal_T_4 = ~reg_mstatus_tw; // @[CSR.scala:395:28, :906:74, :953:41]
wire _io_decode_0_virtual_system_illegal_T_7 = is_wfi & _io_decode_0_virtual_system_illegal_T_6; // @[CSR.scala:903:82, :953:{14,38}]
wire _io_decode_0_virtual_system_illegal_T_8 = _io_decode_0_virtual_system_illegal_T_1 | _io_decode_0_virtual_system_illegal_T_7; // @[CSR.scala:951:22, :952:15, :953:14]
wire _io_decode_0_virtual_system_illegal_T_10 = _io_decode_0_virtual_system_illegal_T_9 == 2'h1; // @[CSR.scala:190:36, :954:32]
wire _io_decode_0_virtual_system_illegal_T_11 = is_ret & _io_decode_0_virtual_system_illegal_T_10; // @[CSR.scala:903:82, :954:{14,32}]
wire _io_decode_0_virtual_system_illegal_T_13 = ~_io_decode_0_virtual_system_illegal_T_12; // @[CSR.scala:954:{48,64}]
wire _io_decode_0_virtual_system_illegal_T_14 = _io_decode_0_virtual_system_illegal_T_13; // @[CSR.scala:954:{48,68}]
wire _io_decode_0_virtual_system_illegal_T_15 = _io_decode_0_virtual_system_illegal_T_11 & _io_decode_0_virtual_system_illegal_T_14; // @[CSR.scala:954:{14,44,68}]
wire _io_decode_0_virtual_system_illegal_T_16 = _io_decode_0_virtual_system_illegal_T_8 | _io_decode_0_virtual_system_illegal_T_15; // @[CSR.scala:952:15, :953:77, :954:44]
wire _io_decode_0_virtual_system_illegal_T_18 = ~_io_decode_0_virtual_system_illegal_T_17; // @[CSR.scala:955:{21,37}]
wire _io_decode_0_virtual_system_illegal_T_19 = _io_decode_0_virtual_system_illegal_T_18; // @[CSR.scala:955:{21,41}]
wire _io_decode_0_virtual_system_illegal_T_20 = is_sfence & _io_decode_0_virtual_system_illegal_T_19; // @[CSR.scala:903:82, :955:{17,41}]
wire _io_decode_0_virtual_system_illegal_T_21 = _io_decode_0_virtual_system_illegal_T_16 | _io_decode_0_virtual_system_illegal_T_20; // @[CSR.scala:953:77, :954:89, :955:17]
assign _io_decode_0_virtual_system_illegal_T_22 = reg_mstatus_v & _io_decode_0_virtual_system_illegal_T_21; // @[CSR.scala:395:28, :949:52, :954:89]
assign io_decode_0_virtual_system_illegal_0 = _io_decode_0_virtual_system_illegal_T_22; // @[CSR.scala:377:7, :949:52]
wire _cause_T_1 = _cause_T & reg_mstatus_v; // @[CSR.scala:395:28, :959:{61,65}]
wire [1:0] _cause_T_2 = _cause_T_1 ? 2'h2 : reg_mstatus_prv; // @[CSR.scala:395:28, :959:{45,65}]
wire [4:0] _cause_T_3 = {3'h0, _cause_T_2} + 5'h8; // @[CSR.scala:959:{40,45}]
wire [3:0] _cause_T_4 = _cause_T_3[3:0]; // @[CSR.scala:959:40]
wire [63:0] _cause_T_5 = insn_break ? 64'h3 : io_cause_0; // @[CSR.scala:377:7, :893:83, :960:14]
assign cause = insn_call ? {60'h0, _cause_T_4} : _cause_T_5; // @[CSR.scala:893:83, :959:{8,40}, :960:14]
assign io_trace_0_cause_0 = cause; // @[CSR.scala:377:7, :959:8]
wire [7:0] cause_lsbs = cause[7:0]; // @[CSR.scala:959:8, :961:25]
wire [5:0] cause_deleg_lsbs = cause[5:0]; // @[CSR.scala:959:8, :962:31]
wire [5:0] _notDebugTVec_interruptOffset_T = cause[5:0]; // @[CSR.scala:959:8, :962:31, :979:32]
wire _causeIsDebugInt_T = cause[63]; // @[CSR.scala:959:8, :963:30]
wire _causeIsDebugTrigger_T = cause[63]; // @[CSR.scala:959:8, :963:30, :964:35]
wire _causeIsDebugBreak_T = cause[63]; // @[CSR.scala:959:8, :963:30, :965:33]
wire _delegate_T_2 = cause[63]; // @[CSR.scala:959:8, :963:30, :970:78]
wire _delegateVS_T_1 = cause[63]; // @[CSR.scala:959:8, :963:30, :971:58]
wire _notDebugTVec_doVector_T_1 = cause[63]; // @[CSR.scala:959:8, :963:30, :981:36]
wire _causeIsRnmiInt_T = cause[63]; // @[CSR.scala:959:8, :963:30, :985:29]
wire _causeIsRnmiBEU_T = cause[63]; // @[CSR.scala:959:8, :963:30, :986:29]
wire _reg_vscause_T = cause[63]; // @[CSR.scala:959:8, :963:30, :1060:31]
assign _io_trace_0_interrupt_T = cause[63]; // @[CSR.scala:959:8, :963:30, :1626:25]
wire _GEN_15 = cause_lsbs == 8'hE; // @[CSR.scala:961:25, :963:53]
wire _causeIsDebugInt_T_1; // @[CSR.scala:963:53]
assign _causeIsDebugInt_T_1 = _GEN_15; // @[CSR.scala:963:53]
wire _causeIsDebugTrigger_T_2; // @[CSR.scala:964:58]
assign _causeIsDebugTrigger_T_2 = _GEN_15; // @[CSR.scala:963:53, :964:58]
wire causeIsDebugInt = _causeIsDebugInt_T & _causeIsDebugInt_T_1; // @[CSR.scala:963:{30,39,53}]
wire _causeIsDebugTrigger_T_1 = ~_causeIsDebugTrigger_T; // @[CSR.scala:964:{29,35}]
wire causeIsDebugTrigger = _causeIsDebugTrigger_T_1 & _causeIsDebugTrigger_T_2; // @[CSR.scala:964:{29,44,58}]
wire _causeIsDebugBreak_T_1 = ~_causeIsDebugBreak_T; // @[CSR.scala:965:{27,33}]
wire _causeIsDebugBreak_T_2 = _causeIsDebugBreak_T_1 & insn_break; // @[CSR.scala:893:83, :965:{27,42}]
wire [1:0] causeIsDebugBreak_lo = {reg_dcsr_ebreaks, reg_dcsr_ebreaku}; // @[CSR.scala:403:25, :965:62]
wire [1:0] causeIsDebugBreak_hi = {reg_dcsr_ebreakm, 1'h0}; // @[CSR.scala:403:25, :965:62]
wire [3:0] _causeIsDebugBreak_T_3 = {causeIsDebugBreak_hi, causeIsDebugBreak_lo}; // @[CSR.scala:965:62]
wire [3:0] _causeIsDebugBreak_T_4 = _causeIsDebugBreak_T_3 >> reg_mstatus_prv; // @[CSR.scala:395:28, :965:{62,134}]
wire _causeIsDebugBreak_T_5 = _causeIsDebugBreak_T_4[0]; // @[CSR.scala:965:134]
wire causeIsDebugBreak = _causeIsDebugBreak_T_2 & _causeIsDebugBreak_T_5; // @[CSR.scala:965:{42,56,134}]
wire _trapToDebug_T = reg_singleStepped | causeIsDebugInt; // @[CSR.scala:486:30, :963:39, :966:56]
wire _trapToDebug_T_1 = _trapToDebug_T | causeIsDebugTrigger; // @[CSR.scala:964:44, :966:{56,75}]
wire _trapToDebug_T_2 = _trapToDebug_T_1 | causeIsDebugBreak; // @[CSR.scala:965:56, :966:{75,98}]
wire _trapToDebug_T_3 = _trapToDebug_T_2 | reg_debug; // @[CSR.scala:482:26, :966:{98,119}]
wire trapToDebug = _trapToDebug_T_3; // @[CSR.scala:966:{34,119}]
wire [11:0] _debugTVec_T = {8'h80, ~insn_break, 3'h0}; // @[CSR.scala:893:83, :969:37]
wire [11:0] debugTVec = reg_debug ? _debugTVec_T : 12'h800; // @[CSR.scala:482:26, :969:{22,37}]
wire _delegate_T = ~(reg_mstatus_prv[1]); // @[CSR.scala:395:28, :620:51, :970:55]
wire _delegate_T_1 = _delegate_T; // @[CSR.scala:970:{36,55}]
wire [63:0] _GEN_16 = {58'h0, cause_deleg_lsbs}; // @[CSR.scala:962:31, :970:100]
wire [63:0] _delegate_T_3 = read_mideleg >> _GEN_16; // @[CSR.scala:498:14, :970:100]
wire _delegate_T_4 = _delegate_T_3[0]; // @[CSR.scala:970:100]
wire [63:0] _delegate_T_5 = read_medeleg >> _GEN_16; // @[CSR.scala:502:14, :970:{100,132}]
wire _delegate_T_6 = _delegate_T_5[0]; // @[CSR.scala:970:132]
wire _delegate_T_7 = _delegate_T_2 ? _delegate_T_4 : _delegate_T_6; // @[CSR.scala:970:{72,78,100,132}]
wire delegate = _delegate_T_1 & _delegate_T_7; // @[CSR.scala:970:{36,66,72}]
wire _delegateVS_T = reg_mstatus_v & delegate; // @[CSR.scala:395:28, :970:66, :971:34]
wire [63:0] _GEN_17 = 64'h0 >> _GEN_16; // @[CSR.scala:970:100, :971:80]
wire [63:0] _delegateVS_T_2; // @[CSR.scala:971:80]
assign _delegateVS_T_2 = _GEN_17; // @[CSR.scala:971:80]
wire [63:0] _delegateVS_T_4; // @[CSR.scala:971:112]
assign _delegateVS_T_4 = _GEN_17; // @[CSR.scala:971:{80,112}]
wire _delegateVS_T_3 = _delegateVS_T_2[0]; // @[CSR.scala:971:80]
wire _delegateVS_T_5 = _delegateVS_T_4[0]; // @[CSR.scala:971:112]
wire _delegateVS_T_6 = _delegateVS_T_1 ? _delegateVS_T_3 : _delegateVS_T_5; // @[CSR.scala:971:{52,58,80,112}]
wire delegateVS = _delegateVS_T & _delegateVS_T_6; // @[CSR.scala:971:{34,46,52}]
wire [63:0] _notDebugTVec_base_T = delegateVS ? read_vstvec : read_stvec; // @[package.scala:132:15]
wire [63:0] notDebugTVec_base = delegate ? _notDebugTVec_base_T : read_mtvec; // @[package.scala:138:15]
wire [7:0] notDebugTVec_interruptOffset = {_notDebugTVec_interruptOffset_T, 2'h0}; // @[CSR.scala:979:{32,59}]
wire [55:0] _notDebugTVec_interruptVec_T = notDebugTVec_base[63:8]; // @[CSR.scala:978:19, :980:33]
wire [63:0] notDebugTVec_interruptVec = {_notDebugTVec_interruptVec_T, notDebugTVec_interruptOffset}; // @[CSR.scala:979:59, :980:{27,33}]
wire _notDebugTVec_doVector_T = notDebugTVec_base[0]; // @[CSR.scala:978:19, :981:24]
wire _notDebugTVec_doVector_T_2 = _notDebugTVec_doVector_T & _notDebugTVec_doVector_T_1; // @[CSR.scala:981:{24,28,36}]
wire [1:0] _notDebugTVec_doVector_T_3 = cause_lsbs[7:6]; // @[CSR.scala:961:25, :981:70]
wire _notDebugTVec_doVector_T_4 = _notDebugTVec_doVector_T_3 == 2'h0; // @[CSR.scala:981:{70,94}]
wire notDebugTVec_doVector = _notDebugTVec_doVector_T_2 & _notDebugTVec_doVector_T_4; // @[CSR.scala:981:{28,55,94}]
wire [61:0] _notDebugTVec_T = notDebugTVec_base[63:2]; // @[CSR.scala:978:19, :982:38]
wire [63:0] _notDebugTVec_T_1 = {_notDebugTVec_T, 2'h0}; // @[CSR.scala:982:{38,56}]
wire [63:0] notDebugTVec = notDebugTVec_doVector ? notDebugTVec_interruptVec : _notDebugTVec_T_1; // @[CSR.scala:980:27, :981:55, :982:{8,56}]
wire [63:0] _tvec_T = notDebugTVec; // @[CSR.scala:982:8, :995:45]
wire _causeIsRnmiInt_T_1 = cause[62]; // @[CSR.scala:959:8, :985:46]
wire _causeIsRnmiBEU_T_1 = cause[62]; // @[CSR.scala:959:8, :985:46, :986:46]
wire _causeIsRnmiInt_T_2 = _causeIsRnmiInt_T & _causeIsRnmiInt_T_1; // @[CSR.scala:985:{29,38,46}]
wire _causeIsRnmiInt_T_3 = cause_lsbs == 8'hD; // @[CSR.scala:961:25, :985:70]
wire _GEN_18 = cause_lsbs == 8'hC; // @[CSR.scala:961:25, :985:107]
wire _causeIsRnmiInt_T_4; // @[CSR.scala:985:107]
assign _causeIsRnmiInt_T_4 = _GEN_18; // @[CSR.scala:985:107]
wire _causeIsRnmiBEU_T_3; // @[CSR.scala:986:69]
assign _causeIsRnmiBEU_T_3 = _GEN_18; // @[CSR.scala:985:107, :986:69]
wire _causeIsRnmiInt_T_5 = _causeIsRnmiInt_T_3 | _causeIsRnmiInt_T_4; // @[CSR.scala:985:{70,93,107}]
wire causeIsRnmiInt = _causeIsRnmiInt_T_2 & _causeIsRnmiInt_T_5; // @[CSR.scala:985:{38,55,93}]
wire _causeIsRnmiBEU_T_2 = _causeIsRnmiBEU_T & _causeIsRnmiBEU_T_1; // @[CSR.scala:986:{29,38,46}]
wire causeIsRnmiBEU = _causeIsRnmiBEU_T_2 & _causeIsRnmiBEU_T_3; // @[CSR.scala:986:{38,55,69}]
wire [63:0] tvec = trapToDebug ? {52'h0, debugTVec} : _tvec_T; // @[CSR.scala:966:34, :969:22, :995:{17,45}]
wire _GEN_19 = insn_call | insn_break; // @[CSR.scala:893:83, :1000:24]
wire _io_eret_T; // @[CSR.scala:1000:24]
assign _io_eret_T = _GEN_19; // @[CSR.scala:1000:24]
wire _exception_T; // @[CSR.scala:1020:29]
assign _exception_T = _GEN_19; // @[CSR.scala:1000:24, :1020:29]
assign _io_eret_T_1 = _io_eret_T | insn_ret; // @[CSR.scala:893:83, :1000:{24,38}]
assign io_eret_0 = _io_eret_T_1; // @[CSR.scala:377:7, :1000:38]
wire _io_singleStep_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1001:37]
assign _io_singleStep_T_1 = reg_dcsr_step & _io_singleStep_T; // @[CSR.scala:403:25, :1001:{34,37}]
assign io_singleStep_0 = _io_singleStep_T_1; // @[CSR.scala:377:7, :1001:34]
wire _io_status_sd_T = &io_status_fs_0; // @[CSR.scala:377:7, :1003:32]
assign io_status_isa_0 = reg_misa[31:0]; // @[CSR.scala:377:7, :648:25, :1005:17]
wire _io_status_dprv_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1008:45]
wire _io_status_dprv_T_1 = reg_mstatus_mprv & _io_status_dprv_T; // @[CSR.scala:395:28, :1008:{42,45}]
assign _io_status_dprv_T_2 = _io_status_dprv_T_1 ? reg_mstatus_mpp : reg_mstatus_prv; // @[CSR.scala:395:28, :1008:{24,42}]
assign io_status_dprv_0 = _io_status_dprv_T_2; // @[CSR.scala:377:7, :1008:24]
wire _io_status_dv_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1009:60]
wire _io_status_dv_T_1 = reg_mstatus_mprv & _io_status_dv_T; // @[CSR.scala:395:28, :1009:{57,60}]
wire _io_status_dv_T_2 = _io_status_dv_T_1 & reg_mstatus_mpv; // @[CSR.scala:395:28, :1009:{39,57}]
assign _io_status_dv_T_3 = reg_mstatus_v | _io_status_dv_T_2; // @[CSR.scala:395:28, :1009:{33,39}]
assign io_status_dv_0 = _io_status_dv_T_3; // @[CSR.scala:377:7, :1009:33]
wire _io_gstatus_sd_T = &io_gstatus_fs_0; // @[CSR.scala:377:7, :1016:34]
wire _io_gstatus_sd_T_3 = &io_gstatus_vs_0; // @[CSR.scala:377:7, :1016:78]
wire exception = _exception_T | io_exception_0; // @[CSR.scala:377:7, :1020:{29,43}]
wire _en_T_8 = exception; // @[CSR.scala:1020:43, :1096:24]
wire _en_T_20 = exception; // @[CSR.scala:1020:43, :1096:24]
wire _en_T_32 = exception; // @[CSR.scala:1020:43, :1096:24]
wire _en_T_44 = exception; // @[CSR.scala:1020:43, :1096:24]
wire _en_T_56 = exception; // @[CSR.scala:1020:43, :1096:24]
wire _en_T_68 = exception; // @[CSR.scala:1020:43, :1096:24]
wire _en_T_80 = exception; // @[CSR.scala:1020:43, :1096:24]
assign _io_trace_0_exception_T_1 = exception; // @[CSR.scala:1020:43, :1620:37] |
Generate the Verilog code corresponding to this FIRRTL code module MacUnit_70 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<8>, flip in_c : SInt<32>, out_d : SInt<20>}
node _io_out_d_T = mul(io.in_a, io.in_b)
node _io_out_d_T_1 = add(_io_out_d_T, io.in_c)
node _io_out_d_T_2 = tail(_io_out_d_T_1, 1)
node _io_out_d_T_3 = asSInt(_io_out_d_T_2)
connect io.out_d, _io_out_d_T_3 | module MacUnit_70( // @[PE.scala:14:7]
input clock, // @[PE.scala:14:7]
input reset, // @[PE.scala:14:7]
input [7:0] io_in_a, // @[PE.scala:16:14]
input [7:0] io_in_b, // @[PE.scala:16:14]
input [31:0] io_in_c, // @[PE.scala:16:14]
output [19:0] io_out_d // @[PE.scala:16:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:14:7]
wire [7:0] io_in_b_0 = io_in_b; // @[PE.scala:14:7]
wire [31:0] io_in_c_0 = io_in_c; // @[PE.scala:14:7]
wire [19:0] io_out_d_0; // @[PE.scala:14:7]
wire [15:0] _io_out_d_T = {{8{io_in_a_0[7]}}, io_in_a_0} * {{8{io_in_b_0[7]}}, io_in_b_0}; // @[PE.scala:14:7]
wire [32:0] _io_out_d_T_1 = {{17{_io_out_d_T[15]}}, _io_out_d_T} + {io_in_c_0[31], io_in_c_0}; // @[PE.scala:14:7]
wire [31:0] _io_out_d_T_2 = _io_out_d_T_1[31:0]; // @[Arithmetic.scala:93:54]
wire [31:0] _io_out_d_T_3 = _io_out_d_T_2; // @[Arithmetic.scala:93:54]
assign io_out_d_0 = _io_out_d_T_3[19:0]; // @[PE.scala:14:7, :23:12]
assign io_out_d = io_out_d_0; // @[PE.scala:14:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module BasicDispatcher :
input clock : Clock
input reset : Reset
output io : { flip ren_uops : { flip ready : UInt<1>, valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}[3], dis_uops : { `3` : { flip ready : UInt<1>, valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}[3], `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}[3], `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}[3], `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<3>, iw_p2_speculative_child : UInt<3>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<3>, br_mask : UInt<16>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}[3]}}
wire _ren_readys_WIRE : UInt<1>[3]
connect _ren_readys_WIRE[0], io.dis_uops.`0`[0].ready
connect _ren_readys_WIRE[1], io.dis_uops.`0`[1].ready
connect _ren_readys_WIRE[2], io.dis_uops.`0`[2].ready
node ren_readys_hi = cat(_ren_readys_WIRE[2], _ren_readys_WIRE[1])
node _ren_readys_T = cat(ren_readys_hi, _ren_readys_WIRE[0])
wire _ren_readys_WIRE_1 : UInt<1>[3]
connect _ren_readys_WIRE_1[0], io.dis_uops.`1`[0].ready
connect _ren_readys_WIRE_1[1], io.dis_uops.`1`[1].ready
connect _ren_readys_WIRE_1[2], io.dis_uops.`1`[2].ready
node ren_readys_hi_1 = cat(_ren_readys_WIRE_1[2], _ren_readys_WIRE_1[1])
node _ren_readys_T_1 = cat(ren_readys_hi_1, _ren_readys_WIRE_1[0])
wire _ren_readys_WIRE_2 : UInt<1>[3]
connect _ren_readys_WIRE_2[0], io.dis_uops.`2`[0].ready
connect _ren_readys_WIRE_2[1], io.dis_uops.`2`[1].ready
connect _ren_readys_WIRE_2[2], io.dis_uops.`2`[2].ready
node ren_readys_hi_2 = cat(_ren_readys_WIRE_2[2], _ren_readys_WIRE_2[1])
node _ren_readys_T_2 = cat(ren_readys_hi_2, _ren_readys_WIRE_2[0])
wire _ren_readys_WIRE_3 : UInt<1>[3]
connect _ren_readys_WIRE_3[0], io.dis_uops.`3`[0].ready
connect _ren_readys_WIRE_3[1], io.dis_uops.`3`[1].ready
connect _ren_readys_WIRE_3[2], io.dis_uops.`3`[2].ready
node ren_readys_hi_3 = cat(_ren_readys_WIRE_3[2], _ren_readys_WIRE_3[1])
node _ren_readys_T_3 = cat(ren_readys_hi_3, _ren_readys_WIRE_3[0])
node _ren_readys_T_4 = and(_ren_readys_T, _ren_readys_T_1)
node _ren_readys_T_5 = and(_ren_readys_T_4, _ren_readys_T_2)
node ren_readys = and(_ren_readys_T_5, _ren_readys_T_3)
node _io_ren_uops_0_ready_T = bits(ren_readys, 0, 0)
connect io.ren_uops[0].ready, _io_ren_uops_0_ready_T
node _io_ren_uops_1_ready_T = bits(ren_readys, 1, 1)
connect io.ren_uops[1].ready, _io_ren_uops_1_ready_T
node _io_ren_uops_2_ready_T = bits(ren_readys, 2, 2)
connect io.ren_uops[2].ready, _io_ren_uops_2_ready_T
node _io_dis_uops_0_0_valid_T = and(io.ren_uops[0].valid, io.ren_uops[0].bits.iq_type[0])
connect io.dis_uops.`0`[0].valid, _io_dis_uops_0_0_valid_T
connect io.dis_uops.`0`[0].bits, io.ren_uops[0].bits
node _io_dis_uops_0_1_valid_T = and(io.ren_uops[1].valid, io.ren_uops[1].bits.iq_type[0])
connect io.dis_uops.`0`[1].valid, _io_dis_uops_0_1_valid_T
connect io.dis_uops.`0`[1].bits, io.ren_uops[1].bits
node _io_dis_uops_0_2_valid_T = and(io.ren_uops[2].valid, io.ren_uops[2].bits.iq_type[0])
connect io.dis_uops.`0`[2].valid, _io_dis_uops_0_2_valid_T
connect io.dis_uops.`0`[2].bits, io.ren_uops[2].bits
node _io_dis_uops_1_0_valid_T = and(io.ren_uops[0].valid, io.ren_uops[0].bits.iq_type[1])
connect io.dis_uops.`1`[0].valid, _io_dis_uops_1_0_valid_T
connect io.dis_uops.`1`[0].bits, io.ren_uops[0].bits
node _io_dis_uops_1_1_valid_T = and(io.ren_uops[1].valid, io.ren_uops[1].bits.iq_type[1])
connect io.dis_uops.`1`[1].valid, _io_dis_uops_1_1_valid_T
connect io.dis_uops.`1`[1].bits, io.ren_uops[1].bits
node _io_dis_uops_1_2_valid_T = and(io.ren_uops[2].valid, io.ren_uops[2].bits.iq_type[1])
connect io.dis_uops.`1`[2].valid, _io_dis_uops_1_2_valid_T
connect io.dis_uops.`1`[2].bits, io.ren_uops[2].bits
node _io_dis_uops_2_0_valid_T = and(io.ren_uops[0].valid, io.ren_uops[0].bits.iq_type[2])
connect io.dis_uops.`2`[0].valid, _io_dis_uops_2_0_valid_T
connect io.dis_uops.`2`[0].bits, io.ren_uops[0].bits
node _io_dis_uops_2_1_valid_T = and(io.ren_uops[1].valid, io.ren_uops[1].bits.iq_type[2])
connect io.dis_uops.`2`[1].valid, _io_dis_uops_2_1_valid_T
connect io.dis_uops.`2`[1].bits, io.ren_uops[1].bits
node _io_dis_uops_2_2_valid_T = and(io.ren_uops[2].valid, io.ren_uops[2].bits.iq_type[2])
connect io.dis_uops.`2`[2].valid, _io_dis_uops_2_2_valid_T
connect io.dis_uops.`2`[2].bits, io.ren_uops[2].bits
node _io_dis_uops_3_0_valid_T = and(io.ren_uops[0].valid, io.ren_uops[0].bits.iq_type[3])
connect io.dis_uops.`3`[0].valid, _io_dis_uops_3_0_valid_T
connect io.dis_uops.`3`[0].bits, io.ren_uops[0].bits
node _io_dis_uops_3_1_valid_T = and(io.ren_uops[1].valid, io.ren_uops[1].bits.iq_type[3])
connect io.dis_uops.`3`[1].valid, _io_dis_uops_3_1_valid_T
connect io.dis_uops.`3`[1].bits, io.ren_uops[1].bits
node _io_dis_uops_3_2_valid_T = and(io.ren_uops[2].valid, io.ren_uops[2].bits.iq_type[3])
connect io.dis_uops.`3`[2].valid, _io_dis_uops_3_2_valid_T
connect io.dis_uops.`3`[2].bits, io.ren_uops[2].bits | module BasicDispatcher( // @[dispatch.scala:43:7]
input clock, // @[dispatch.scala:43:7]
input reset, // @[dispatch.scala:43:7]
output io_ren_uops_0_ready, // @[dispatch.scala:36:14]
input io_ren_uops_0_valid, // @[dispatch.scala:36:14]
input [31:0] io_ren_uops_0_bits_inst, // @[dispatch.scala:36:14]
input [31:0] io_ren_uops_0_bits_debug_inst, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_is_rvc, // @[dispatch.scala:36:14]
input [39:0] io_ren_uops_0_bits_debug_pc, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_iq_type_0, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_iq_type_1, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_iq_type_2, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_iq_type_3, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_fu_code_0, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_fu_code_1, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_fu_code_2, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_fu_code_3, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_fu_code_4, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_fu_code_5, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_fu_code_6, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_fu_code_7, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_fu_code_8, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_fu_code_9, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_iw_issued, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_iw_issued_partial_agen, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_iw_issued_partial_dgen, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_0_bits_iw_p1_speculative_child, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_0_bits_iw_p2_speculative_child, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_iw_p1_bypass_hint, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_iw_p2_bypass_hint, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_iw_p3_bypass_hint, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_0_bits_dis_col_sel, // @[dispatch.scala:36:14]
input [15:0] io_ren_uops_0_bits_br_mask, // @[dispatch.scala:36:14]
input [3:0] io_ren_uops_0_bits_br_tag, // @[dispatch.scala:36:14]
input [3:0] io_ren_uops_0_bits_br_type, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_is_sfb, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_is_fence, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_is_fencei, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_is_sfence, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_is_amo, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_is_eret, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_is_sys_pc2epc, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_is_rocc, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_is_mov, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_0_bits_ftq_idx, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_edge_inst, // @[dispatch.scala:36:14]
input [5:0] io_ren_uops_0_bits_pc_lob, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_taken, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_imm_rename, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_0_bits_imm_sel, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_0_bits_pimm, // @[dispatch.scala:36:14]
input [19:0] io_ren_uops_0_bits_imm_packed, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_0_bits_op1_sel, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_0_bits_op2_sel, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_fp_ctrl_ldst, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_fp_ctrl_wen, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_fp_ctrl_ren1, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_fp_ctrl_ren2, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_fp_ctrl_ren3, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_fp_ctrl_swap12, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_fp_ctrl_swap23, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_0_bits_fp_ctrl_typeTagIn, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_0_bits_fp_ctrl_typeTagOut, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_fp_ctrl_fromint, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_fp_ctrl_toint, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_fp_ctrl_fastpipe, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_fp_ctrl_fma, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_fp_ctrl_div, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_fp_ctrl_sqrt, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_fp_ctrl_wflags, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_fp_ctrl_vec, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_0_bits_rob_idx, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_0_bits_ldq_idx, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_0_bits_stq_idx, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_0_bits_rxq_idx, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_0_bits_pdst, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_0_bits_prs1, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_0_bits_prs2, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_0_bits_prs3, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_0_bits_ppred, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_prs1_busy, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_prs2_busy, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_prs3_busy, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_ppred_busy, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_0_bits_stale_pdst, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_exception, // @[dispatch.scala:36:14]
input [63:0] io_ren_uops_0_bits_exc_cause, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_0_bits_mem_cmd, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_0_bits_mem_size, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_mem_signed, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_uses_ldq, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_uses_stq, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_is_unique, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_flush_on_commit, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_0_bits_csr_cmd, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_ldst_is_rs1, // @[dispatch.scala:36:14]
input [5:0] io_ren_uops_0_bits_ldst, // @[dispatch.scala:36:14]
input [5:0] io_ren_uops_0_bits_lrs1, // @[dispatch.scala:36:14]
input [5:0] io_ren_uops_0_bits_lrs2, // @[dispatch.scala:36:14]
input [5:0] io_ren_uops_0_bits_lrs3, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_0_bits_dst_rtype, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_0_bits_lrs1_rtype, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_0_bits_lrs2_rtype, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_frs3_en, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_fcn_dw, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_0_bits_fcn_op, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_fp_val, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_0_bits_fp_rm, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_0_bits_fp_typ, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_xcpt_pf_if, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_xcpt_ae_if, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_xcpt_ma_if, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_bp_debug_if, // @[dispatch.scala:36:14]
input io_ren_uops_0_bits_bp_xcpt_if, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_0_bits_debug_fsrc, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_0_bits_debug_tsrc, // @[dispatch.scala:36:14]
output io_ren_uops_1_ready, // @[dispatch.scala:36:14]
input io_ren_uops_1_valid, // @[dispatch.scala:36:14]
input [31:0] io_ren_uops_1_bits_inst, // @[dispatch.scala:36:14]
input [31:0] io_ren_uops_1_bits_debug_inst, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_is_rvc, // @[dispatch.scala:36:14]
input [39:0] io_ren_uops_1_bits_debug_pc, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_iq_type_0, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_iq_type_1, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_iq_type_2, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_iq_type_3, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_fu_code_0, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_fu_code_1, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_fu_code_2, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_fu_code_3, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_fu_code_4, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_fu_code_5, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_fu_code_6, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_fu_code_7, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_fu_code_8, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_fu_code_9, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_iw_issued, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_iw_issued_partial_agen, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_iw_issued_partial_dgen, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_1_bits_iw_p1_speculative_child, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_1_bits_iw_p2_speculative_child, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_iw_p1_bypass_hint, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_iw_p2_bypass_hint, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_iw_p3_bypass_hint, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_1_bits_dis_col_sel, // @[dispatch.scala:36:14]
input [15:0] io_ren_uops_1_bits_br_mask, // @[dispatch.scala:36:14]
input [3:0] io_ren_uops_1_bits_br_tag, // @[dispatch.scala:36:14]
input [3:0] io_ren_uops_1_bits_br_type, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_is_sfb, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_is_fence, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_is_fencei, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_is_sfence, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_is_amo, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_is_eret, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_is_sys_pc2epc, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_is_rocc, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_is_mov, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_1_bits_ftq_idx, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_edge_inst, // @[dispatch.scala:36:14]
input [5:0] io_ren_uops_1_bits_pc_lob, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_taken, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_imm_rename, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_1_bits_imm_sel, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_1_bits_pimm, // @[dispatch.scala:36:14]
input [19:0] io_ren_uops_1_bits_imm_packed, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_1_bits_op1_sel, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_1_bits_op2_sel, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_fp_ctrl_ldst, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_fp_ctrl_wen, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_fp_ctrl_ren1, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_fp_ctrl_ren2, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_fp_ctrl_ren3, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_fp_ctrl_swap12, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_fp_ctrl_swap23, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_1_bits_fp_ctrl_typeTagIn, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_1_bits_fp_ctrl_typeTagOut, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_fp_ctrl_fromint, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_fp_ctrl_toint, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_fp_ctrl_fastpipe, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_fp_ctrl_fma, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_fp_ctrl_div, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_fp_ctrl_sqrt, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_fp_ctrl_wflags, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_fp_ctrl_vec, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_1_bits_rob_idx, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_1_bits_ldq_idx, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_1_bits_stq_idx, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_1_bits_rxq_idx, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_1_bits_pdst, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_1_bits_prs1, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_1_bits_prs2, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_1_bits_prs3, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_1_bits_ppred, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_prs1_busy, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_prs2_busy, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_prs3_busy, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_ppred_busy, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_1_bits_stale_pdst, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_exception, // @[dispatch.scala:36:14]
input [63:0] io_ren_uops_1_bits_exc_cause, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_1_bits_mem_cmd, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_1_bits_mem_size, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_mem_signed, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_uses_ldq, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_uses_stq, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_is_unique, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_flush_on_commit, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_1_bits_csr_cmd, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_ldst_is_rs1, // @[dispatch.scala:36:14]
input [5:0] io_ren_uops_1_bits_ldst, // @[dispatch.scala:36:14]
input [5:0] io_ren_uops_1_bits_lrs1, // @[dispatch.scala:36:14]
input [5:0] io_ren_uops_1_bits_lrs2, // @[dispatch.scala:36:14]
input [5:0] io_ren_uops_1_bits_lrs3, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_1_bits_dst_rtype, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_1_bits_lrs1_rtype, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_1_bits_lrs2_rtype, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_frs3_en, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_fcn_dw, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_1_bits_fcn_op, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_fp_val, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_1_bits_fp_rm, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_1_bits_fp_typ, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_xcpt_pf_if, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_xcpt_ae_if, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_xcpt_ma_if, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_bp_debug_if, // @[dispatch.scala:36:14]
input io_ren_uops_1_bits_bp_xcpt_if, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_1_bits_debug_fsrc, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_1_bits_debug_tsrc, // @[dispatch.scala:36:14]
output io_ren_uops_2_ready, // @[dispatch.scala:36:14]
input io_ren_uops_2_valid, // @[dispatch.scala:36:14]
input [31:0] io_ren_uops_2_bits_inst, // @[dispatch.scala:36:14]
input [31:0] io_ren_uops_2_bits_debug_inst, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_is_rvc, // @[dispatch.scala:36:14]
input [39:0] io_ren_uops_2_bits_debug_pc, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_iq_type_0, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_iq_type_1, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_iq_type_2, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_iq_type_3, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_fu_code_0, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_fu_code_1, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_fu_code_2, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_fu_code_3, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_fu_code_4, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_fu_code_5, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_fu_code_6, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_fu_code_7, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_fu_code_8, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_fu_code_9, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_iw_issued, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_iw_issued_partial_agen, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_iw_issued_partial_dgen, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_2_bits_iw_p1_speculative_child, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_2_bits_iw_p2_speculative_child, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_iw_p1_bypass_hint, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_iw_p2_bypass_hint, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_iw_p3_bypass_hint, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_2_bits_dis_col_sel, // @[dispatch.scala:36:14]
input [15:0] io_ren_uops_2_bits_br_mask, // @[dispatch.scala:36:14]
input [3:0] io_ren_uops_2_bits_br_tag, // @[dispatch.scala:36:14]
input [3:0] io_ren_uops_2_bits_br_type, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_is_sfb, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_is_fence, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_is_fencei, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_is_sfence, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_is_amo, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_is_eret, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_is_sys_pc2epc, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_is_rocc, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_is_mov, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_2_bits_ftq_idx, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_edge_inst, // @[dispatch.scala:36:14]
input [5:0] io_ren_uops_2_bits_pc_lob, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_taken, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_imm_rename, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_2_bits_imm_sel, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_2_bits_pimm, // @[dispatch.scala:36:14]
input [19:0] io_ren_uops_2_bits_imm_packed, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_2_bits_op1_sel, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_2_bits_op2_sel, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_fp_ctrl_ldst, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_fp_ctrl_wen, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_fp_ctrl_ren1, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_fp_ctrl_ren2, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_fp_ctrl_ren3, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_fp_ctrl_swap12, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_fp_ctrl_swap23, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_2_bits_fp_ctrl_typeTagIn, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_2_bits_fp_ctrl_typeTagOut, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_fp_ctrl_fromint, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_fp_ctrl_toint, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_fp_ctrl_fastpipe, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_fp_ctrl_fma, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_fp_ctrl_div, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_fp_ctrl_sqrt, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_fp_ctrl_wflags, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_fp_ctrl_vec, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_2_bits_rob_idx, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_2_bits_ldq_idx, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_2_bits_stq_idx, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_2_bits_rxq_idx, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_2_bits_pdst, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_2_bits_prs1, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_2_bits_prs2, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_2_bits_prs3, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_2_bits_ppred, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_prs1_busy, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_prs2_busy, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_prs3_busy, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_ppred_busy, // @[dispatch.scala:36:14]
input [6:0] io_ren_uops_2_bits_stale_pdst, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_exception, // @[dispatch.scala:36:14]
input [63:0] io_ren_uops_2_bits_exc_cause, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_2_bits_mem_cmd, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_2_bits_mem_size, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_mem_signed, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_uses_ldq, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_uses_stq, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_is_unique, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_flush_on_commit, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_2_bits_csr_cmd, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_ldst_is_rs1, // @[dispatch.scala:36:14]
input [5:0] io_ren_uops_2_bits_ldst, // @[dispatch.scala:36:14]
input [5:0] io_ren_uops_2_bits_lrs1, // @[dispatch.scala:36:14]
input [5:0] io_ren_uops_2_bits_lrs2, // @[dispatch.scala:36:14]
input [5:0] io_ren_uops_2_bits_lrs3, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_2_bits_dst_rtype, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_2_bits_lrs1_rtype, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_2_bits_lrs2_rtype, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_frs3_en, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_fcn_dw, // @[dispatch.scala:36:14]
input [4:0] io_ren_uops_2_bits_fcn_op, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_fp_val, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_2_bits_fp_rm, // @[dispatch.scala:36:14]
input [1:0] io_ren_uops_2_bits_fp_typ, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_xcpt_pf_if, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_xcpt_ae_if, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_xcpt_ma_if, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_bp_debug_if, // @[dispatch.scala:36:14]
input io_ren_uops_2_bits_bp_xcpt_if, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_2_bits_debug_fsrc, // @[dispatch.scala:36:14]
input [2:0] io_ren_uops_2_bits_debug_tsrc, // @[dispatch.scala:36:14]
input io_dis_uops_3_0_ready, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_valid, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_3_0_bits_inst, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_3_0_bits_debug_inst, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_is_rvc, // @[dispatch.scala:36:14]
output [39:0] io_dis_uops_3_0_bits_debug_pc, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_iq_type_0, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_iq_type_1, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_iq_type_2, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_iq_type_3, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_fu_code_0, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_fu_code_1, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_fu_code_2, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_fu_code_3, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_fu_code_4, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_fu_code_5, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_fu_code_6, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_fu_code_7, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_fu_code_8, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_fu_code_9, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_iw_issued, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_iw_issued_partial_agen, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_iw_issued_partial_dgen, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_3_0_bits_iw_p1_speculative_child, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_3_0_bits_iw_p2_speculative_child, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_iw_p1_bypass_hint, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_iw_p2_bypass_hint, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_iw_p3_bypass_hint, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_3_0_bits_dis_col_sel, // @[dispatch.scala:36:14]
output [15:0] io_dis_uops_3_0_bits_br_mask, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_3_0_bits_br_tag, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_3_0_bits_br_type, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_is_sfb, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_is_fence, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_is_fencei, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_is_sfence, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_is_amo, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_is_eret, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_is_sys_pc2epc, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_is_rocc, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_is_mov, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_3_0_bits_ftq_idx, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_edge_inst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_3_0_bits_pc_lob, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_taken, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_imm_rename, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_3_0_bits_imm_sel, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_3_0_bits_pimm, // @[dispatch.scala:36:14]
output [19:0] io_dis_uops_3_0_bits_imm_packed, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_3_0_bits_op1_sel, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_3_0_bits_op2_sel, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_fp_ctrl_ldst, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_fp_ctrl_wen, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_fp_ctrl_ren1, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_fp_ctrl_ren2, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_fp_ctrl_ren3, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_fp_ctrl_swap12, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_fp_ctrl_swap23, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_3_0_bits_fp_ctrl_typeTagIn, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_3_0_bits_fp_ctrl_typeTagOut, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_fp_ctrl_fromint, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_fp_ctrl_toint, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_fp_ctrl_fastpipe, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_fp_ctrl_fma, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_fp_ctrl_div, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_fp_ctrl_sqrt, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_fp_ctrl_wflags, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_fp_ctrl_vec, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_3_0_bits_rob_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_3_0_bits_ldq_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_3_0_bits_stq_idx, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_3_0_bits_rxq_idx, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_3_0_bits_pdst, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_3_0_bits_prs1, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_3_0_bits_prs2, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_3_0_bits_prs3, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_3_0_bits_ppred, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_prs1_busy, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_prs2_busy, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_prs3_busy, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_ppred_busy, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_3_0_bits_stale_pdst, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_exception, // @[dispatch.scala:36:14]
output [63:0] io_dis_uops_3_0_bits_exc_cause, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_3_0_bits_mem_cmd, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_3_0_bits_mem_size, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_mem_signed, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_uses_ldq, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_uses_stq, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_is_unique, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_flush_on_commit, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_3_0_bits_csr_cmd, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_ldst_is_rs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_3_0_bits_ldst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_3_0_bits_lrs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_3_0_bits_lrs2, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_3_0_bits_lrs3, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_3_0_bits_dst_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_3_0_bits_lrs1_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_3_0_bits_lrs2_rtype, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_frs3_en, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_fcn_dw, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_3_0_bits_fcn_op, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_fp_val, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_3_0_bits_fp_rm, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_3_0_bits_fp_typ, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_xcpt_pf_if, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_xcpt_ae_if, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_xcpt_ma_if, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_bp_debug_if, // @[dispatch.scala:36:14]
output io_dis_uops_3_0_bits_bp_xcpt_if, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_3_0_bits_debug_fsrc, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_3_0_bits_debug_tsrc, // @[dispatch.scala:36:14]
input io_dis_uops_3_1_ready, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_valid, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_3_1_bits_inst, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_3_1_bits_debug_inst, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_is_rvc, // @[dispatch.scala:36:14]
output [39:0] io_dis_uops_3_1_bits_debug_pc, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_iq_type_0, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_iq_type_1, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_iq_type_2, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_iq_type_3, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_fu_code_0, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_fu_code_1, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_fu_code_2, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_fu_code_3, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_fu_code_4, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_fu_code_5, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_fu_code_6, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_fu_code_7, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_fu_code_8, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_fu_code_9, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_iw_issued, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_iw_issued_partial_agen, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_iw_issued_partial_dgen, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_3_1_bits_iw_p1_speculative_child, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_3_1_bits_iw_p2_speculative_child, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_iw_p1_bypass_hint, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_iw_p2_bypass_hint, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_iw_p3_bypass_hint, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_3_1_bits_dis_col_sel, // @[dispatch.scala:36:14]
output [15:0] io_dis_uops_3_1_bits_br_mask, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_3_1_bits_br_tag, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_3_1_bits_br_type, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_is_sfb, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_is_fence, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_is_fencei, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_is_sfence, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_is_amo, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_is_eret, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_is_sys_pc2epc, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_is_rocc, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_is_mov, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_3_1_bits_ftq_idx, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_edge_inst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_3_1_bits_pc_lob, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_taken, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_imm_rename, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_3_1_bits_imm_sel, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_3_1_bits_pimm, // @[dispatch.scala:36:14]
output [19:0] io_dis_uops_3_1_bits_imm_packed, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_3_1_bits_op1_sel, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_3_1_bits_op2_sel, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_fp_ctrl_ldst, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_fp_ctrl_wen, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_fp_ctrl_ren1, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_fp_ctrl_ren2, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_fp_ctrl_ren3, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_fp_ctrl_swap12, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_fp_ctrl_swap23, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_3_1_bits_fp_ctrl_typeTagIn, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_3_1_bits_fp_ctrl_typeTagOut, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_fp_ctrl_fromint, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_fp_ctrl_toint, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_fp_ctrl_fastpipe, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_fp_ctrl_fma, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_fp_ctrl_div, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_fp_ctrl_sqrt, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_fp_ctrl_wflags, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_fp_ctrl_vec, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_3_1_bits_rob_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_3_1_bits_ldq_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_3_1_bits_stq_idx, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_3_1_bits_rxq_idx, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_3_1_bits_pdst, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_3_1_bits_prs1, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_3_1_bits_prs2, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_3_1_bits_prs3, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_3_1_bits_ppred, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_prs1_busy, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_prs2_busy, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_prs3_busy, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_ppred_busy, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_3_1_bits_stale_pdst, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_exception, // @[dispatch.scala:36:14]
output [63:0] io_dis_uops_3_1_bits_exc_cause, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_3_1_bits_mem_cmd, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_3_1_bits_mem_size, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_mem_signed, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_uses_ldq, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_uses_stq, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_is_unique, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_flush_on_commit, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_3_1_bits_csr_cmd, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_ldst_is_rs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_3_1_bits_ldst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_3_1_bits_lrs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_3_1_bits_lrs2, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_3_1_bits_lrs3, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_3_1_bits_dst_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_3_1_bits_lrs1_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_3_1_bits_lrs2_rtype, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_frs3_en, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_fcn_dw, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_3_1_bits_fcn_op, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_fp_val, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_3_1_bits_fp_rm, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_3_1_bits_fp_typ, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_xcpt_pf_if, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_xcpt_ae_if, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_xcpt_ma_if, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_bp_debug_if, // @[dispatch.scala:36:14]
output io_dis_uops_3_1_bits_bp_xcpt_if, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_3_1_bits_debug_fsrc, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_3_1_bits_debug_tsrc, // @[dispatch.scala:36:14]
input io_dis_uops_3_2_ready, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_valid, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_3_2_bits_inst, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_3_2_bits_debug_inst, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_is_rvc, // @[dispatch.scala:36:14]
output [39:0] io_dis_uops_3_2_bits_debug_pc, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_iq_type_0, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_iq_type_1, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_iq_type_2, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_iq_type_3, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_fu_code_0, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_fu_code_1, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_fu_code_2, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_fu_code_3, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_fu_code_4, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_fu_code_5, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_fu_code_6, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_fu_code_7, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_fu_code_8, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_fu_code_9, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_iw_issued, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_iw_issued_partial_agen, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_iw_issued_partial_dgen, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_3_2_bits_iw_p1_speculative_child, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_3_2_bits_iw_p2_speculative_child, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_iw_p1_bypass_hint, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_iw_p2_bypass_hint, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_iw_p3_bypass_hint, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_3_2_bits_dis_col_sel, // @[dispatch.scala:36:14]
output [15:0] io_dis_uops_3_2_bits_br_mask, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_3_2_bits_br_tag, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_3_2_bits_br_type, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_is_sfb, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_is_fence, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_is_fencei, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_is_sfence, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_is_amo, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_is_eret, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_is_sys_pc2epc, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_is_rocc, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_is_mov, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_3_2_bits_ftq_idx, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_edge_inst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_3_2_bits_pc_lob, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_taken, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_imm_rename, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_3_2_bits_imm_sel, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_3_2_bits_pimm, // @[dispatch.scala:36:14]
output [19:0] io_dis_uops_3_2_bits_imm_packed, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_3_2_bits_op1_sel, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_3_2_bits_op2_sel, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_fp_ctrl_ldst, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_fp_ctrl_wen, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_fp_ctrl_ren1, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_fp_ctrl_ren2, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_fp_ctrl_ren3, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_fp_ctrl_swap12, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_fp_ctrl_swap23, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_3_2_bits_fp_ctrl_typeTagIn, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_3_2_bits_fp_ctrl_typeTagOut, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_fp_ctrl_fromint, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_fp_ctrl_toint, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_fp_ctrl_fastpipe, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_fp_ctrl_fma, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_fp_ctrl_div, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_fp_ctrl_sqrt, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_fp_ctrl_wflags, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_fp_ctrl_vec, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_3_2_bits_rob_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_3_2_bits_ldq_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_3_2_bits_stq_idx, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_3_2_bits_rxq_idx, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_3_2_bits_pdst, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_3_2_bits_prs1, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_3_2_bits_prs2, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_3_2_bits_prs3, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_3_2_bits_ppred, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_prs1_busy, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_prs2_busy, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_prs3_busy, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_ppred_busy, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_3_2_bits_stale_pdst, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_exception, // @[dispatch.scala:36:14]
output [63:0] io_dis_uops_3_2_bits_exc_cause, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_3_2_bits_mem_cmd, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_3_2_bits_mem_size, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_mem_signed, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_uses_ldq, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_uses_stq, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_is_unique, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_flush_on_commit, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_3_2_bits_csr_cmd, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_ldst_is_rs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_3_2_bits_ldst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_3_2_bits_lrs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_3_2_bits_lrs2, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_3_2_bits_lrs3, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_3_2_bits_dst_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_3_2_bits_lrs1_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_3_2_bits_lrs2_rtype, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_frs3_en, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_fcn_dw, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_3_2_bits_fcn_op, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_fp_val, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_3_2_bits_fp_rm, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_3_2_bits_fp_typ, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_xcpt_pf_if, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_xcpt_ae_if, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_xcpt_ma_if, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_bp_debug_if, // @[dispatch.scala:36:14]
output io_dis_uops_3_2_bits_bp_xcpt_if, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_3_2_bits_debug_fsrc, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_3_2_bits_debug_tsrc, // @[dispatch.scala:36:14]
input io_dis_uops_2_0_ready, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_valid, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_2_0_bits_inst, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_2_0_bits_debug_inst, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_is_rvc, // @[dispatch.scala:36:14]
output [39:0] io_dis_uops_2_0_bits_debug_pc, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_iq_type_0, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_iq_type_1, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_iq_type_2, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_iq_type_3, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_fu_code_0, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_fu_code_1, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_fu_code_2, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_fu_code_3, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_fu_code_4, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_fu_code_5, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_fu_code_6, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_fu_code_7, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_fu_code_8, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_fu_code_9, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_iw_issued, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_iw_issued_partial_agen, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_iw_issued_partial_dgen, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_0_bits_iw_p1_speculative_child, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_0_bits_iw_p2_speculative_child, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_iw_p1_bypass_hint, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_iw_p2_bypass_hint, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_iw_p3_bypass_hint, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_0_bits_dis_col_sel, // @[dispatch.scala:36:14]
output [15:0] io_dis_uops_2_0_bits_br_mask, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_2_0_bits_br_tag, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_2_0_bits_br_type, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_is_sfb, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_is_fence, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_is_fencei, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_is_sfence, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_is_amo, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_is_eret, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_is_sys_pc2epc, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_is_rocc, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_is_mov, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_0_bits_ftq_idx, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_edge_inst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_2_0_bits_pc_lob, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_taken, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_imm_rename, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_0_bits_imm_sel, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_0_bits_pimm, // @[dispatch.scala:36:14]
output [19:0] io_dis_uops_2_0_bits_imm_packed, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_0_bits_op1_sel, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_0_bits_op2_sel, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_fp_ctrl_ldst, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_fp_ctrl_wen, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_fp_ctrl_ren1, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_fp_ctrl_ren2, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_fp_ctrl_ren3, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_fp_ctrl_swap12, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_fp_ctrl_swap23, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_0_bits_fp_ctrl_typeTagIn, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_0_bits_fp_ctrl_typeTagOut, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_fp_ctrl_fromint, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_fp_ctrl_toint, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_fp_ctrl_fastpipe, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_fp_ctrl_fma, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_fp_ctrl_div, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_fp_ctrl_sqrt, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_fp_ctrl_wflags, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_fp_ctrl_vec, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_0_bits_rob_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_0_bits_ldq_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_0_bits_stq_idx, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_0_bits_rxq_idx, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_0_bits_pdst, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_0_bits_prs1, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_0_bits_prs2, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_0_bits_prs3, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_0_bits_ppred, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_prs1_busy, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_prs2_busy, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_prs3_busy, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_ppred_busy, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_0_bits_stale_pdst, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_exception, // @[dispatch.scala:36:14]
output [63:0] io_dis_uops_2_0_bits_exc_cause, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_0_bits_mem_cmd, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_0_bits_mem_size, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_mem_signed, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_uses_ldq, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_uses_stq, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_is_unique, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_flush_on_commit, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_0_bits_csr_cmd, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_ldst_is_rs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_2_0_bits_ldst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_2_0_bits_lrs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_2_0_bits_lrs2, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_2_0_bits_lrs3, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_0_bits_dst_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_0_bits_lrs1_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_0_bits_lrs2_rtype, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_frs3_en, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_fcn_dw, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_0_bits_fcn_op, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_fp_val, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_0_bits_fp_rm, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_0_bits_fp_typ, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_xcpt_pf_if, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_xcpt_ae_if, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_xcpt_ma_if, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_bp_debug_if, // @[dispatch.scala:36:14]
output io_dis_uops_2_0_bits_bp_xcpt_if, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_0_bits_debug_fsrc, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_0_bits_debug_tsrc, // @[dispatch.scala:36:14]
input io_dis_uops_2_1_ready, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_valid, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_2_1_bits_inst, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_2_1_bits_debug_inst, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_is_rvc, // @[dispatch.scala:36:14]
output [39:0] io_dis_uops_2_1_bits_debug_pc, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_iq_type_0, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_iq_type_1, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_iq_type_2, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_iq_type_3, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_fu_code_0, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_fu_code_1, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_fu_code_2, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_fu_code_3, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_fu_code_4, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_fu_code_5, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_fu_code_6, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_fu_code_7, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_fu_code_8, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_fu_code_9, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_iw_issued, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_iw_issued_partial_agen, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_iw_issued_partial_dgen, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_1_bits_iw_p1_speculative_child, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_1_bits_iw_p2_speculative_child, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_iw_p1_bypass_hint, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_iw_p2_bypass_hint, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_iw_p3_bypass_hint, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_1_bits_dis_col_sel, // @[dispatch.scala:36:14]
output [15:0] io_dis_uops_2_1_bits_br_mask, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_2_1_bits_br_tag, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_2_1_bits_br_type, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_is_sfb, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_is_fence, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_is_fencei, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_is_sfence, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_is_amo, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_is_eret, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_is_sys_pc2epc, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_is_rocc, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_is_mov, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_1_bits_ftq_idx, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_edge_inst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_2_1_bits_pc_lob, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_taken, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_imm_rename, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_1_bits_imm_sel, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_1_bits_pimm, // @[dispatch.scala:36:14]
output [19:0] io_dis_uops_2_1_bits_imm_packed, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_1_bits_op1_sel, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_1_bits_op2_sel, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_fp_ctrl_ldst, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_fp_ctrl_wen, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_fp_ctrl_ren1, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_fp_ctrl_ren2, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_fp_ctrl_ren3, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_fp_ctrl_swap12, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_fp_ctrl_swap23, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_1_bits_fp_ctrl_typeTagIn, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_1_bits_fp_ctrl_typeTagOut, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_fp_ctrl_fromint, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_fp_ctrl_toint, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_fp_ctrl_fastpipe, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_fp_ctrl_fma, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_fp_ctrl_div, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_fp_ctrl_sqrt, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_fp_ctrl_wflags, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_fp_ctrl_vec, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_1_bits_rob_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_1_bits_ldq_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_1_bits_stq_idx, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_1_bits_rxq_idx, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_1_bits_pdst, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_1_bits_prs1, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_1_bits_prs2, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_1_bits_prs3, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_1_bits_ppred, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_prs1_busy, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_prs2_busy, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_prs3_busy, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_ppred_busy, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_1_bits_stale_pdst, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_exception, // @[dispatch.scala:36:14]
output [63:0] io_dis_uops_2_1_bits_exc_cause, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_1_bits_mem_cmd, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_1_bits_mem_size, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_mem_signed, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_uses_ldq, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_uses_stq, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_is_unique, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_flush_on_commit, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_1_bits_csr_cmd, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_ldst_is_rs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_2_1_bits_ldst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_2_1_bits_lrs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_2_1_bits_lrs2, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_2_1_bits_lrs3, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_1_bits_dst_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_1_bits_lrs1_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_1_bits_lrs2_rtype, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_frs3_en, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_fcn_dw, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_1_bits_fcn_op, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_fp_val, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_1_bits_fp_rm, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_1_bits_fp_typ, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_xcpt_pf_if, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_xcpt_ae_if, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_xcpt_ma_if, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_bp_debug_if, // @[dispatch.scala:36:14]
output io_dis_uops_2_1_bits_bp_xcpt_if, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_1_bits_debug_fsrc, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_1_bits_debug_tsrc, // @[dispatch.scala:36:14]
input io_dis_uops_2_2_ready, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_valid, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_2_2_bits_inst, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_2_2_bits_debug_inst, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_is_rvc, // @[dispatch.scala:36:14]
output [39:0] io_dis_uops_2_2_bits_debug_pc, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_iq_type_0, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_iq_type_1, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_iq_type_2, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_iq_type_3, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_fu_code_0, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_fu_code_1, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_fu_code_2, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_fu_code_3, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_fu_code_4, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_fu_code_5, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_fu_code_6, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_fu_code_7, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_fu_code_8, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_fu_code_9, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_iw_issued, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_iw_issued_partial_agen, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_iw_issued_partial_dgen, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_2_bits_iw_p1_speculative_child, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_2_bits_iw_p2_speculative_child, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_iw_p1_bypass_hint, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_iw_p2_bypass_hint, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_iw_p3_bypass_hint, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_2_bits_dis_col_sel, // @[dispatch.scala:36:14]
output [15:0] io_dis_uops_2_2_bits_br_mask, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_2_2_bits_br_tag, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_2_2_bits_br_type, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_is_sfb, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_is_fence, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_is_fencei, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_is_sfence, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_is_amo, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_is_eret, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_is_sys_pc2epc, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_is_rocc, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_is_mov, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_2_bits_ftq_idx, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_edge_inst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_2_2_bits_pc_lob, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_taken, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_imm_rename, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_2_bits_imm_sel, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_2_bits_pimm, // @[dispatch.scala:36:14]
output [19:0] io_dis_uops_2_2_bits_imm_packed, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_2_bits_op1_sel, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_2_bits_op2_sel, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_fp_ctrl_ldst, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_fp_ctrl_wen, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_fp_ctrl_ren1, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_fp_ctrl_ren2, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_fp_ctrl_ren3, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_fp_ctrl_swap12, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_fp_ctrl_swap23, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_2_bits_fp_ctrl_typeTagIn, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_2_bits_fp_ctrl_typeTagOut, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_fp_ctrl_fromint, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_fp_ctrl_toint, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_fp_ctrl_fastpipe, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_fp_ctrl_fma, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_fp_ctrl_div, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_fp_ctrl_sqrt, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_fp_ctrl_wflags, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_fp_ctrl_vec, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_2_bits_rob_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_2_bits_ldq_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_2_bits_stq_idx, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_2_bits_rxq_idx, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_2_bits_pdst, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_2_bits_prs1, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_2_bits_prs2, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_2_bits_prs3, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_2_bits_ppred, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_prs1_busy, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_prs2_busy, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_prs3_busy, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_ppred_busy, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_2_2_bits_stale_pdst, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_exception, // @[dispatch.scala:36:14]
output [63:0] io_dis_uops_2_2_bits_exc_cause, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_2_bits_mem_cmd, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_2_bits_mem_size, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_mem_signed, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_uses_ldq, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_uses_stq, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_is_unique, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_flush_on_commit, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_2_bits_csr_cmd, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_ldst_is_rs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_2_2_bits_ldst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_2_2_bits_lrs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_2_2_bits_lrs2, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_2_2_bits_lrs3, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_2_bits_dst_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_2_bits_lrs1_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_2_bits_lrs2_rtype, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_frs3_en, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_fcn_dw, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_2_2_bits_fcn_op, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_fp_val, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_2_bits_fp_rm, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_2_2_bits_fp_typ, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_xcpt_pf_if, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_xcpt_ae_if, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_xcpt_ma_if, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_bp_debug_if, // @[dispatch.scala:36:14]
output io_dis_uops_2_2_bits_bp_xcpt_if, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_2_bits_debug_fsrc, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_2_2_bits_debug_tsrc, // @[dispatch.scala:36:14]
input io_dis_uops_1_0_ready, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_valid, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_1_0_bits_inst, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_1_0_bits_debug_inst, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_is_rvc, // @[dispatch.scala:36:14]
output [39:0] io_dis_uops_1_0_bits_debug_pc, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_iq_type_0, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_iq_type_1, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_iq_type_2, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_iq_type_3, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_fu_code_0, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_fu_code_1, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_fu_code_2, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_fu_code_3, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_fu_code_4, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_fu_code_5, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_fu_code_6, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_fu_code_7, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_fu_code_8, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_fu_code_9, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_iw_issued, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_iw_issued_partial_agen, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_iw_issued_partial_dgen, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_0_bits_iw_p1_speculative_child, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_0_bits_iw_p2_speculative_child, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_iw_p1_bypass_hint, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_iw_p2_bypass_hint, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_iw_p3_bypass_hint, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_0_bits_dis_col_sel, // @[dispatch.scala:36:14]
output [15:0] io_dis_uops_1_0_bits_br_mask, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_1_0_bits_br_tag, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_1_0_bits_br_type, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_is_sfb, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_is_fence, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_is_fencei, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_is_sfence, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_is_amo, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_is_eret, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_is_sys_pc2epc, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_is_rocc, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_is_mov, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_0_bits_ftq_idx, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_edge_inst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_1_0_bits_pc_lob, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_taken, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_imm_rename, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_0_bits_imm_sel, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_0_bits_pimm, // @[dispatch.scala:36:14]
output [19:0] io_dis_uops_1_0_bits_imm_packed, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_0_bits_op1_sel, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_0_bits_op2_sel, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_fp_ctrl_ldst, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_fp_ctrl_wen, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_fp_ctrl_ren1, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_fp_ctrl_ren2, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_fp_ctrl_ren3, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_fp_ctrl_swap12, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_fp_ctrl_swap23, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_0_bits_fp_ctrl_typeTagIn, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_0_bits_fp_ctrl_typeTagOut, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_fp_ctrl_fromint, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_fp_ctrl_toint, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_fp_ctrl_fastpipe, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_fp_ctrl_fma, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_fp_ctrl_div, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_fp_ctrl_sqrt, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_fp_ctrl_wflags, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_fp_ctrl_vec, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_0_bits_rob_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_0_bits_ldq_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_0_bits_stq_idx, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_0_bits_rxq_idx, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_0_bits_pdst, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_0_bits_prs1, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_0_bits_prs2, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_0_bits_prs3, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_0_bits_ppred, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_prs1_busy, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_prs2_busy, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_prs3_busy, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_ppred_busy, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_0_bits_stale_pdst, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_exception, // @[dispatch.scala:36:14]
output [63:0] io_dis_uops_1_0_bits_exc_cause, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_0_bits_mem_cmd, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_0_bits_mem_size, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_mem_signed, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_uses_ldq, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_uses_stq, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_is_unique, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_flush_on_commit, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_0_bits_csr_cmd, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_ldst_is_rs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_1_0_bits_ldst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_1_0_bits_lrs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_1_0_bits_lrs2, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_1_0_bits_lrs3, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_0_bits_dst_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_0_bits_lrs1_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_0_bits_lrs2_rtype, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_frs3_en, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_fcn_dw, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_0_bits_fcn_op, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_fp_val, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_0_bits_fp_rm, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_0_bits_fp_typ, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_xcpt_pf_if, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_xcpt_ae_if, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_xcpt_ma_if, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_bp_debug_if, // @[dispatch.scala:36:14]
output io_dis_uops_1_0_bits_bp_xcpt_if, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_0_bits_debug_fsrc, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_0_bits_debug_tsrc, // @[dispatch.scala:36:14]
input io_dis_uops_1_1_ready, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_valid, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_1_1_bits_inst, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_1_1_bits_debug_inst, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_is_rvc, // @[dispatch.scala:36:14]
output [39:0] io_dis_uops_1_1_bits_debug_pc, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_iq_type_0, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_iq_type_1, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_iq_type_2, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_iq_type_3, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_fu_code_0, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_fu_code_1, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_fu_code_2, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_fu_code_3, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_fu_code_4, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_fu_code_5, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_fu_code_6, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_fu_code_7, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_fu_code_8, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_fu_code_9, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_iw_issued, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_iw_issued_partial_agen, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_iw_issued_partial_dgen, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_1_bits_iw_p1_speculative_child, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_1_bits_iw_p2_speculative_child, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_iw_p1_bypass_hint, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_iw_p2_bypass_hint, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_iw_p3_bypass_hint, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_1_bits_dis_col_sel, // @[dispatch.scala:36:14]
output [15:0] io_dis_uops_1_1_bits_br_mask, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_1_1_bits_br_tag, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_1_1_bits_br_type, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_is_sfb, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_is_fence, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_is_fencei, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_is_sfence, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_is_amo, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_is_eret, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_is_sys_pc2epc, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_is_rocc, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_is_mov, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_1_bits_ftq_idx, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_edge_inst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_1_1_bits_pc_lob, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_taken, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_imm_rename, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_1_bits_imm_sel, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_1_bits_pimm, // @[dispatch.scala:36:14]
output [19:0] io_dis_uops_1_1_bits_imm_packed, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_1_bits_op1_sel, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_1_bits_op2_sel, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_fp_ctrl_ldst, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_fp_ctrl_wen, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_fp_ctrl_ren1, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_fp_ctrl_ren2, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_fp_ctrl_ren3, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_fp_ctrl_swap12, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_fp_ctrl_swap23, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_1_bits_fp_ctrl_typeTagIn, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_1_bits_fp_ctrl_typeTagOut, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_fp_ctrl_fromint, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_fp_ctrl_toint, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_fp_ctrl_fastpipe, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_fp_ctrl_fma, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_fp_ctrl_div, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_fp_ctrl_sqrt, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_fp_ctrl_wflags, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_fp_ctrl_vec, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_1_bits_rob_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_1_bits_ldq_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_1_bits_stq_idx, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_1_bits_rxq_idx, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_1_bits_pdst, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_1_bits_prs1, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_1_bits_prs2, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_1_bits_prs3, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_1_bits_ppred, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_prs1_busy, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_prs2_busy, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_prs3_busy, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_ppred_busy, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_1_bits_stale_pdst, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_exception, // @[dispatch.scala:36:14]
output [63:0] io_dis_uops_1_1_bits_exc_cause, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_1_bits_mem_cmd, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_1_bits_mem_size, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_mem_signed, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_uses_ldq, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_uses_stq, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_is_unique, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_flush_on_commit, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_1_bits_csr_cmd, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_ldst_is_rs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_1_1_bits_ldst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_1_1_bits_lrs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_1_1_bits_lrs2, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_1_1_bits_lrs3, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_1_bits_dst_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_1_bits_lrs1_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_1_bits_lrs2_rtype, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_frs3_en, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_fcn_dw, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_1_bits_fcn_op, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_fp_val, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_1_bits_fp_rm, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_1_bits_fp_typ, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_xcpt_pf_if, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_xcpt_ae_if, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_xcpt_ma_if, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_bp_debug_if, // @[dispatch.scala:36:14]
output io_dis_uops_1_1_bits_bp_xcpt_if, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_1_bits_debug_fsrc, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_1_bits_debug_tsrc, // @[dispatch.scala:36:14]
input io_dis_uops_1_2_ready, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_valid, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_1_2_bits_inst, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_1_2_bits_debug_inst, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_is_rvc, // @[dispatch.scala:36:14]
output [39:0] io_dis_uops_1_2_bits_debug_pc, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_iq_type_0, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_iq_type_1, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_iq_type_2, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_iq_type_3, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_fu_code_0, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_fu_code_1, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_fu_code_2, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_fu_code_3, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_fu_code_4, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_fu_code_5, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_fu_code_6, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_fu_code_7, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_fu_code_8, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_fu_code_9, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_iw_issued, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_iw_issued_partial_agen, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_iw_issued_partial_dgen, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_2_bits_iw_p1_speculative_child, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_2_bits_iw_p2_speculative_child, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_iw_p1_bypass_hint, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_iw_p2_bypass_hint, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_iw_p3_bypass_hint, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_2_bits_dis_col_sel, // @[dispatch.scala:36:14]
output [15:0] io_dis_uops_1_2_bits_br_mask, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_1_2_bits_br_tag, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_1_2_bits_br_type, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_is_sfb, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_is_fence, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_is_fencei, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_is_sfence, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_is_amo, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_is_eret, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_is_sys_pc2epc, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_is_rocc, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_is_mov, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_2_bits_ftq_idx, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_edge_inst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_1_2_bits_pc_lob, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_taken, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_imm_rename, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_2_bits_imm_sel, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_2_bits_pimm, // @[dispatch.scala:36:14]
output [19:0] io_dis_uops_1_2_bits_imm_packed, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_2_bits_op1_sel, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_2_bits_op2_sel, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_fp_ctrl_ldst, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_fp_ctrl_wen, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_fp_ctrl_ren1, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_fp_ctrl_ren2, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_fp_ctrl_ren3, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_fp_ctrl_swap12, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_fp_ctrl_swap23, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_2_bits_fp_ctrl_typeTagIn, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_2_bits_fp_ctrl_typeTagOut, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_fp_ctrl_fromint, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_fp_ctrl_toint, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_fp_ctrl_fastpipe, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_fp_ctrl_fma, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_fp_ctrl_div, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_fp_ctrl_sqrt, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_fp_ctrl_wflags, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_fp_ctrl_vec, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_2_bits_rob_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_2_bits_ldq_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_2_bits_stq_idx, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_2_bits_rxq_idx, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_2_bits_pdst, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_2_bits_prs1, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_2_bits_prs2, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_2_bits_prs3, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_2_bits_ppred, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_prs1_busy, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_prs2_busy, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_prs3_busy, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_ppred_busy, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_1_2_bits_stale_pdst, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_exception, // @[dispatch.scala:36:14]
output [63:0] io_dis_uops_1_2_bits_exc_cause, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_2_bits_mem_cmd, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_2_bits_mem_size, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_mem_signed, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_uses_ldq, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_uses_stq, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_is_unique, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_flush_on_commit, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_2_bits_csr_cmd, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_ldst_is_rs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_1_2_bits_ldst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_1_2_bits_lrs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_1_2_bits_lrs2, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_1_2_bits_lrs3, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_2_bits_dst_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_2_bits_lrs1_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_2_bits_lrs2_rtype, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_frs3_en, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_fcn_dw, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_1_2_bits_fcn_op, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_fp_val, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_2_bits_fp_rm, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_1_2_bits_fp_typ, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_xcpt_pf_if, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_xcpt_ae_if, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_xcpt_ma_if, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_bp_debug_if, // @[dispatch.scala:36:14]
output io_dis_uops_1_2_bits_bp_xcpt_if, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_2_bits_debug_fsrc, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_1_2_bits_debug_tsrc, // @[dispatch.scala:36:14]
input io_dis_uops_0_0_ready, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_valid, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_0_0_bits_inst, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_0_0_bits_debug_inst, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_is_rvc, // @[dispatch.scala:36:14]
output [39:0] io_dis_uops_0_0_bits_debug_pc, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_iq_type_0, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_iq_type_1, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_iq_type_2, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_iq_type_3, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_fu_code_0, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_fu_code_1, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_fu_code_2, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_fu_code_3, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_fu_code_4, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_fu_code_5, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_fu_code_6, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_fu_code_7, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_fu_code_8, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_fu_code_9, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_iw_issued, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_iw_issued_partial_agen, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_iw_issued_partial_dgen, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_0_bits_iw_p1_speculative_child, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_0_bits_iw_p2_speculative_child, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_iw_p1_bypass_hint, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_iw_p2_bypass_hint, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_iw_p3_bypass_hint, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_0_bits_dis_col_sel, // @[dispatch.scala:36:14]
output [15:0] io_dis_uops_0_0_bits_br_mask, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_0_0_bits_br_tag, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_0_0_bits_br_type, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_is_sfb, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_is_fence, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_is_fencei, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_is_sfence, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_is_amo, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_is_eret, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_is_sys_pc2epc, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_is_rocc, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_is_mov, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_0_bits_ftq_idx, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_edge_inst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_0_0_bits_pc_lob, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_taken, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_imm_rename, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_0_bits_imm_sel, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_0_bits_pimm, // @[dispatch.scala:36:14]
output [19:0] io_dis_uops_0_0_bits_imm_packed, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_0_bits_op1_sel, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_0_bits_op2_sel, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_fp_ctrl_ldst, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_fp_ctrl_wen, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_fp_ctrl_ren1, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_fp_ctrl_ren2, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_fp_ctrl_ren3, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_fp_ctrl_swap12, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_fp_ctrl_swap23, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_0_bits_fp_ctrl_typeTagIn, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_0_bits_fp_ctrl_typeTagOut, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_fp_ctrl_fromint, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_fp_ctrl_toint, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_fp_ctrl_fastpipe, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_fp_ctrl_fma, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_fp_ctrl_div, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_fp_ctrl_sqrt, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_fp_ctrl_wflags, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_fp_ctrl_vec, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_0_bits_rob_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_0_bits_ldq_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_0_bits_stq_idx, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_0_bits_rxq_idx, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_0_bits_pdst, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_0_bits_prs1, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_0_bits_prs2, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_0_bits_prs3, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_0_bits_ppred, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_prs1_busy, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_prs2_busy, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_prs3_busy, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_ppred_busy, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_0_bits_stale_pdst, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_exception, // @[dispatch.scala:36:14]
output [63:0] io_dis_uops_0_0_bits_exc_cause, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_0_bits_mem_cmd, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_0_bits_mem_size, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_mem_signed, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_uses_ldq, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_uses_stq, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_is_unique, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_flush_on_commit, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_0_bits_csr_cmd, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_ldst_is_rs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_0_0_bits_ldst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_0_0_bits_lrs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_0_0_bits_lrs2, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_0_0_bits_lrs3, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_0_bits_dst_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_0_bits_lrs1_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_0_bits_lrs2_rtype, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_frs3_en, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_fcn_dw, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_0_bits_fcn_op, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_fp_val, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_0_bits_fp_rm, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_0_bits_fp_typ, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_xcpt_pf_if, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_xcpt_ae_if, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_xcpt_ma_if, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_bp_debug_if, // @[dispatch.scala:36:14]
output io_dis_uops_0_0_bits_bp_xcpt_if, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_0_bits_debug_fsrc, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_0_bits_debug_tsrc, // @[dispatch.scala:36:14]
input io_dis_uops_0_1_ready, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_valid, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_0_1_bits_inst, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_0_1_bits_debug_inst, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_is_rvc, // @[dispatch.scala:36:14]
output [39:0] io_dis_uops_0_1_bits_debug_pc, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_iq_type_0, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_iq_type_1, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_iq_type_2, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_iq_type_3, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_fu_code_0, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_fu_code_1, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_fu_code_2, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_fu_code_3, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_fu_code_4, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_fu_code_5, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_fu_code_6, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_fu_code_7, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_fu_code_8, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_fu_code_9, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_iw_issued, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_iw_issued_partial_agen, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_iw_issued_partial_dgen, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_1_bits_iw_p1_speculative_child, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_1_bits_iw_p2_speculative_child, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_iw_p1_bypass_hint, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_iw_p2_bypass_hint, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_iw_p3_bypass_hint, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_1_bits_dis_col_sel, // @[dispatch.scala:36:14]
output [15:0] io_dis_uops_0_1_bits_br_mask, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_0_1_bits_br_tag, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_0_1_bits_br_type, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_is_sfb, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_is_fence, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_is_fencei, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_is_sfence, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_is_amo, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_is_eret, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_is_sys_pc2epc, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_is_rocc, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_is_mov, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_1_bits_ftq_idx, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_edge_inst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_0_1_bits_pc_lob, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_taken, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_imm_rename, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_1_bits_imm_sel, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_1_bits_pimm, // @[dispatch.scala:36:14]
output [19:0] io_dis_uops_0_1_bits_imm_packed, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_1_bits_op1_sel, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_1_bits_op2_sel, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_fp_ctrl_ldst, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_fp_ctrl_wen, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_fp_ctrl_ren1, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_fp_ctrl_ren2, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_fp_ctrl_ren3, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_fp_ctrl_swap12, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_fp_ctrl_swap23, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_1_bits_fp_ctrl_typeTagIn, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_1_bits_fp_ctrl_typeTagOut, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_fp_ctrl_fromint, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_fp_ctrl_toint, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_fp_ctrl_fastpipe, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_fp_ctrl_fma, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_fp_ctrl_div, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_fp_ctrl_sqrt, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_fp_ctrl_wflags, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_fp_ctrl_vec, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_1_bits_rob_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_1_bits_ldq_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_1_bits_stq_idx, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_1_bits_rxq_idx, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_1_bits_pdst, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_1_bits_prs1, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_1_bits_prs2, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_1_bits_prs3, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_1_bits_ppred, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_prs1_busy, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_prs2_busy, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_prs3_busy, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_ppred_busy, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_1_bits_stale_pdst, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_exception, // @[dispatch.scala:36:14]
output [63:0] io_dis_uops_0_1_bits_exc_cause, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_1_bits_mem_cmd, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_1_bits_mem_size, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_mem_signed, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_uses_ldq, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_uses_stq, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_is_unique, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_flush_on_commit, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_1_bits_csr_cmd, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_ldst_is_rs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_0_1_bits_ldst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_0_1_bits_lrs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_0_1_bits_lrs2, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_0_1_bits_lrs3, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_1_bits_dst_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_1_bits_lrs1_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_1_bits_lrs2_rtype, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_frs3_en, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_fcn_dw, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_1_bits_fcn_op, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_fp_val, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_1_bits_fp_rm, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_1_bits_fp_typ, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_xcpt_pf_if, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_xcpt_ae_if, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_xcpt_ma_if, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_bp_debug_if, // @[dispatch.scala:36:14]
output io_dis_uops_0_1_bits_bp_xcpt_if, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_1_bits_debug_fsrc, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_1_bits_debug_tsrc, // @[dispatch.scala:36:14]
input io_dis_uops_0_2_ready, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_valid, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_0_2_bits_inst, // @[dispatch.scala:36:14]
output [31:0] io_dis_uops_0_2_bits_debug_inst, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_is_rvc, // @[dispatch.scala:36:14]
output [39:0] io_dis_uops_0_2_bits_debug_pc, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_iq_type_0, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_iq_type_1, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_iq_type_2, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_iq_type_3, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_fu_code_0, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_fu_code_1, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_fu_code_2, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_fu_code_3, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_fu_code_4, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_fu_code_5, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_fu_code_6, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_fu_code_7, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_fu_code_8, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_fu_code_9, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_iw_issued, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_iw_issued_partial_agen, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_iw_issued_partial_dgen, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_2_bits_iw_p1_speculative_child, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_2_bits_iw_p2_speculative_child, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_iw_p1_bypass_hint, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_iw_p2_bypass_hint, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_iw_p3_bypass_hint, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_2_bits_dis_col_sel, // @[dispatch.scala:36:14]
output [15:0] io_dis_uops_0_2_bits_br_mask, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_0_2_bits_br_tag, // @[dispatch.scala:36:14]
output [3:0] io_dis_uops_0_2_bits_br_type, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_is_sfb, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_is_fence, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_is_fencei, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_is_sfence, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_is_amo, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_is_eret, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_is_sys_pc2epc, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_is_rocc, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_is_mov, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_2_bits_ftq_idx, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_edge_inst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_0_2_bits_pc_lob, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_taken, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_imm_rename, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_2_bits_imm_sel, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_2_bits_pimm, // @[dispatch.scala:36:14]
output [19:0] io_dis_uops_0_2_bits_imm_packed, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_2_bits_op1_sel, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_2_bits_op2_sel, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_fp_ctrl_ldst, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_fp_ctrl_wen, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_fp_ctrl_ren1, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_fp_ctrl_ren2, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_fp_ctrl_ren3, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_fp_ctrl_swap12, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_fp_ctrl_swap23, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_2_bits_fp_ctrl_typeTagIn, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_2_bits_fp_ctrl_typeTagOut, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_fp_ctrl_fromint, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_fp_ctrl_toint, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_fp_ctrl_fastpipe, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_fp_ctrl_fma, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_fp_ctrl_div, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_fp_ctrl_sqrt, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_fp_ctrl_wflags, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_fp_ctrl_vec, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_2_bits_rob_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_2_bits_ldq_idx, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_2_bits_stq_idx, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_2_bits_rxq_idx, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_2_bits_pdst, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_2_bits_prs1, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_2_bits_prs2, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_2_bits_prs3, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_2_bits_ppred, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_prs1_busy, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_prs2_busy, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_prs3_busy, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_ppred_busy, // @[dispatch.scala:36:14]
output [6:0] io_dis_uops_0_2_bits_stale_pdst, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_exception, // @[dispatch.scala:36:14]
output [63:0] io_dis_uops_0_2_bits_exc_cause, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_2_bits_mem_cmd, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_2_bits_mem_size, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_mem_signed, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_uses_ldq, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_uses_stq, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_is_unique, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_flush_on_commit, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_2_bits_csr_cmd, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_ldst_is_rs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_0_2_bits_ldst, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_0_2_bits_lrs1, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_0_2_bits_lrs2, // @[dispatch.scala:36:14]
output [5:0] io_dis_uops_0_2_bits_lrs3, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_2_bits_dst_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_2_bits_lrs1_rtype, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_2_bits_lrs2_rtype, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_frs3_en, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_fcn_dw, // @[dispatch.scala:36:14]
output [4:0] io_dis_uops_0_2_bits_fcn_op, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_fp_val, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_2_bits_fp_rm, // @[dispatch.scala:36:14]
output [1:0] io_dis_uops_0_2_bits_fp_typ, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_xcpt_pf_if, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_xcpt_ae_if, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_xcpt_ma_if, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_bp_debug_if, // @[dispatch.scala:36:14]
output io_dis_uops_0_2_bits_bp_xcpt_if, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_2_bits_debug_fsrc, // @[dispatch.scala:36:14]
output [2:0] io_dis_uops_0_2_bits_debug_tsrc // @[dispatch.scala:36:14]
);
wire io_ren_uops_0_valid_0 = io_ren_uops_0_valid; // @[dispatch.scala:43:7]
wire [31:0] io_ren_uops_0_bits_inst_0 = io_ren_uops_0_bits_inst; // @[dispatch.scala:43:7]
wire [31:0] io_ren_uops_0_bits_debug_inst_0 = io_ren_uops_0_bits_debug_inst; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_is_rvc_0 = io_ren_uops_0_bits_is_rvc; // @[dispatch.scala:43:7]
wire [39:0] io_ren_uops_0_bits_debug_pc_0 = io_ren_uops_0_bits_debug_pc; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_iq_type_0_0 = io_ren_uops_0_bits_iq_type_0; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_iq_type_1_0 = io_ren_uops_0_bits_iq_type_1; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_iq_type_2_0 = io_ren_uops_0_bits_iq_type_2; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_iq_type_3_0 = io_ren_uops_0_bits_iq_type_3; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_fu_code_0_0 = io_ren_uops_0_bits_fu_code_0; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_fu_code_1_0 = io_ren_uops_0_bits_fu_code_1; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_fu_code_2_0 = io_ren_uops_0_bits_fu_code_2; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_fu_code_3_0 = io_ren_uops_0_bits_fu_code_3; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_fu_code_4_0 = io_ren_uops_0_bits_fu_code_4; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_fu_code_5_0 = io_ren_uops_0_bits_fu_code_5; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_fu_code_6_0 = io_ren_uops_0_bits_fu_code_6; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_fu_code_7_0 = io_ren_uops_0_bits_fu_code_7; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_fu_code_8_0 = io_ren_uops_0_bits_fu_code_8; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_fu_code_9_0 = io_ren_uops_0_bits_fu_code_9; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_iw_issued_0 = io_ren_uops_0_bits_iw_issued; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_iw_issued_partial_agen_0 = io_ren_uops_0_bits_iw_issued_partial_agen; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_iw_issued_partial_dgen_0 = io_ren_uops_0_bits_iw_issued_partial_dgen; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_0_bits_iw_p1_speculative_child_0 = io_ren_uops_0_bits_iw_p1_speculative_child; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_0_bits_iw_p2_speculative_child_0 = io_ren_uops_0_bits_iw_p2_speculative_child; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_iw_p1_bypass_hint_0 = io_ren_uops_0_bits_iw_p1_bypass_hint; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_iw_p2_bypass_hint_0 = io_ren_uops_0_bits_iw_p2_bypass_hint; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_iw_p3_bypass_hint_0 = io_ren_uops_0_bits_iw_p3_bypass_hint; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_0_bits_dis_col_sel_0 = io_ren_uops_0_bits_dis_col_sel; // @[dispatch.scala:43:7]
wire [15:0] io_ren_uops_0_bits_br_mask_0 = io_ren_uops_0_bits_br_mask; // @[dispatch.scala:43:7]
wire [3:0] io_ren_uops_0_bits_br_tag_0 = io_ren_uops_0_bits_br_tag; // @[dispatch.scala:43:7]
wire [3:0] io_ren_uops_0_bits_br_type_0 = io_ren_uops_0_bits_br_type; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_is_sfb_0 = io_ren_uops_0_bits_is_sfb; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_is_fence_0 = io_ren_uops_0_bits_is_fence; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_is_fencei_0 = io_ren_uops_0_bits_is_fencei; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_is_sfence_0 = io_ren_uops_0_bits_is_sfence; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_is_amo_0 = io_ren_uops_0_bits_is_amo; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_is_eret_0 = io_ren_uops_0_bits_is_eret; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_is_sys_pc2epc_0 = io_ren_uops_0_bits_is_sys_pc2epc; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_is_rocc_0 = io_ren_uops_0_bits_is_rocc; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_is_mov_0 = io_ren_uops_0_bits_is_mov; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_0_bits_ftq_idx_0 = io_ren_uops_0_bits_ftq_idx; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_edge_inst_0 = io_ren_uops_0_bits_edge_inst; // @[dispatch.scala:43:7]
wire [5:0] io_ren_uops_0_bits_pc_lob_0 = io_ren_uops_0_bits_pc_lob; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_taken_0 = io_ren_uops_0_bits_taken; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_imm_rename_0 = io_ren_uops_0_bits_imm_rename; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_0_bits_imm_sel_0 = io_ren_uops_0_bits_imm_sel; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_0_bits_pimm_0 = io_ren_uops_0_bits_pimm; // @[dispatch.scala:43:7]
wire [19:0] io_ren_uops_0_bits_imm_packed_0 = io_ren_uops_0_bits_imm_packed; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_0_bits_op1_sel_0 = io_ren_uops_0_bits_op1_sel; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_0_bits_op2_sel_0 = io_ren_uops_0_bits_op2_sel; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_fp_ctrl_ldst_0 = io_ren_uops_0_bits_fp_ctrl_ldst; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_fp_ctrl_wen_0 = io_ren_uops_0_bits_fp_ctrl_wen; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_fp_ctrl_ren1_0 = io_ren_uops_0_bits_fp_ctrl_ren1; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_fp_ctrl_ren2_0 = io_ren_uops_0_bits_fp_ctrl_ren2; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_fp_ctrl_ren3_0 = io_ren_uops_0_bits_fp_ctrl_ren3; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_fp_ctrl_swap12_0 = io_ren_uops_0_bits_fp_ctrl_swap12; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_fp_ctrl_swap23_0 = io_ren_uops_0_bits_fp_ctrl_swap23; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_0_bits_fp_ctrl_typeTagIn_0 = io_ren_uops_0_bits_fp_ctrl_typeTagIn; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_0_bits_fp_ctrl_typeTagOut_0 = io_ren_uops_0_bits_fp_ctrl_typeTagOut; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_fp_ctrl_fromint_0 = io_ren_uops_0_bits_fp_ctrl_fromint; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_fp_ctrl_toint_0 = io_ren_uops_0_bits_fp_ctrl_toint; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_fp_ctrl_fastpipe_0 = io_ren_uops_0_bits_fp_ctrl_fastpipe; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_fp_ctrl_fma_0 = io_ren_uops_0_bits_fp_ctrl_fma; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_fp_ctrl_div_0 = io_ren_uops_0_bits_fp_ctrl_div; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_fp_ctrl_sqrt_0 = io_ren_uops_0_bits_fp_ctrl_sqrt; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_fp_ctrl_wflags_0 = io_ren_uops_0_bits_fp_ctrl_wflags; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_fp_ctrl_vec_0 = io_ren_uops_0_bits_fp_ctrl_vec; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_0_bits_rob_idx_0 = io_ren_uops_0_bits_rob_idx; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_0_bits_ldq_idx_0 = io_ren_uops_0_bits_ldq_idx; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_0_bits_stq_idx_0 = io_ren_uops_0_bits_stq_idx; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_0_bits_rxq_idx_0 = io_ren_uops_0_bits_rxq_idx; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_0_bits_pdst_0 = io_ren_uops_0_bits_pdst; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_0_bits_prs1_0 = io_ren_uops_0_bits_prs1; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_0_bits_prs2_0 = io_ren_uops_0_bits_prs2; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_0_bits_prs3_0 = io_ren_uops_0_bits_prs3; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_0_bits_ppred_0 = io_ren_uops_0_bits_ppred; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_prs1_busy_0 = io_ren_uops_0_bits_prs1_busy; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_prs2_busy_0 = io_ren_uops_0_bits_prs2_busy; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_prs3_busy_0 = io_ren_uops_0_bits_prs3_busy; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_ppred_busy_0 = io_ren_uops_0_bits_ppred_busy; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_0_bits_stale_pdst_0 = io_ren_uops_0_bits_stale_pdst; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_exception_0 = io_ren_uops_0_bits_exception; // @[dispatch.scala:43:7]
wire [63:0] io_ren_uops_0_bits_exc_cause_0 = io_ren_uops_0_bits_exc_cause; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_0_bits_mem_cmd_0 = io_ren_uops_0_bits_mem_cmd; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_0_bits_mem_size_0 = io_ren_uops_0_bits_mem_size; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_mem_signed_0 = io_ren_uops_0_bits_mem_signed; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_uses_ldq_0 = io_ren_uops_0_bits_uses_ldq; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_uses_stq_0 = io_ren_uops_0_bits_uses_stq; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_is_unique_0 = io_ren_uops_0_bits_is_unique; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_flush_on_commit_0 = io_ren_uops_0_bits_flush_on_commit; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_0_bits_csr_cmd_0 = io_ren_uops_0_bits_csr_cmd; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_ldst_is_rs1_0 = io_ren_uops_0_bits_ldst_is_rs1; // @[dispatch.scala:43:7]
wire [5:0] io_ren_uops_0_bits_ldst_0 = io_ren_uops_0_bits_ldst; // @[dispatch.scala:43:7]
wire [5:0] io_ren_uops_0_bits_lrs1_0 = io_ren_uops_0_bits_lrs1; // @[dispatch.scala:43:7]
wire [5:0] io_ren_uops_0_bits_lrs2_0 = io_ren_uops_0_bits_lrs2; // @[dispatch.scala:43:7]
wire [5:0] io_ren_uops_0_bits_lrs3_0 = io_ren_uops_0_bits_lrs3; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_0_bits_dst_rtype_0 = io_ren_uops_0_bits_dst_rtype; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_0_bits_lrs1_rtype_0 = io_ren_uops_0_bits_lrs1_rtype; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_0_bits_lrs2_rtype_0 = io_ren_uops_0_bits_lrs2_rtype; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_frs3_en_0 = io_ren_uops_0_bits_frs3_en; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_fcn_dw_0 = io_ren_uops_0_bits_fcn_dw; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_0_bits_fcn_op_0 = io_ren_uops_0_bits_fcn_op; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_fp_val_0 = io_ren_uops_0_bits_fp_val; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_0_bits_fp_rm_0 = io_ren_uops_0_bits_fp_rm; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_0_bits_fp_typ_0 = io_ren_uops_0_bits_fp_typ; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_xcpt_pf_if_0 = io_ren_uops_0_bits_xcpt_pf_if; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_xcpt_ae_if_0 = io_ren_uops_0_bits_xcpt_ae_if; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_xcpt_ma_if_0 = io_ren_uops_0_bits_xcpt_ma_if; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_bp_debug_if_0 = io_ren_uops_0_bits_bp_debug_if; // @[dispatch.scala:43:7]
wire io_ren_uops_0_bits_bp_xcpt_if_0 = io_ren_uops_0_bits_bp_xcpt_if; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_0_bits_debug_fsrc_0 = io_ren_uops_0_bits_debug_fsrc; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_0_bits_debug_tsrc_0 = io_ren_uops_0_bits_debug_tsrc; // @[dispatch.scala:43:7]
wire io_ren_uops_1_valid_0 = io_ren_uops_1_valid; // @[dispatch.scala:43:7]
wire [31:0] io_ren_uops_1_bits_inst_0 = io_ren_uops_1_bits_inst; // @[dispatch.scala:43:7]
wire [31:0] io_ren_uops_1_bits_debug_inst_0 = io_ren_uops_1_bits_debug_inst; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_is_rvc_0 = io_ren_uops_1_bits_is_rvc; // @[dispatch.scala:43:7]
wire [39:0] io_ren_uops_1_bits_debug_pc_0 = io_ren_uops_1_bits_debug_pc; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_iq_type_0_0 = io_ren_uops_1_bits_iq_type_0; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_iq_type_1_0 = io_ren_uops_1_bits_iq_type_1; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_iq_type_2_0 = io_ren_uops_1_bits_iq_type_2; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_iq_type_3_0 = io_ren_uops_1_bits_iq_type_3; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_fu_code_0_0 = io_ren_uops_1_bits_fu_code_0; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_fu_code_1_0 = io_ren_uops_1_bits_fu_code_1; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_fu_code_2_0 = io_ren_uops_1_bits_fu_code_2; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_fu_code_3_0 = io_ren_uops_1_bits_fu_code_3; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_fu_code_4_0 = io_ren_uops_1_bits_fu_code_4; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_fu_code_5_0 = io_ren_uops_1_bits_fu_code_5; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_fu_code_6_0 = io_ren_uops_1_bits_fu_code_6; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_fu_code_7_0 = io_ren_uops_1_bits_fu_code_7; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_fu_code_8_0 = io_ren_uops_1_bits_fu_code_8; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_fu_code_9_0 = io_ren_uops_1_bits_fu_code_9; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_iw_issued_0 = io_ren_uops_1_bits_iw_issued; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_iw_issued_partial_agen_0 = io_ren_uops_1_bits_iw_issued_partial_agen; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_iw_issued_partial_dgen_0 = io_ren_uops_1_bits_iw_issued_partial_dgen; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_1_bits_iw_p1_speculative_child_0 = io_ren_uops_1_bits_iw_p1_speculative_child; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_1_bits_iw_p2_speculative_child_0 = io_ren_uops_1_bits_iw_p2_speculative_child; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_iw_p1_bypass_hint_0 = io_ren_uops_1_bits_iw_p1_bypass_hint; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_iw_p2_bypass_hint_0 = io_ren_uops_1_bits_iw_p2_bypass_hint; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_iw_p3_bypass_hint_0 = io_ren_uops_1_bits_iw_p3_bypass_hint; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_1_bits_dis_col_sel_0 = io_ren_uops_1_bits_dis_col_sel; // @[dispatch.scala:43:7]
wire [15:0] io_ren_uops_1_bits_br_mask_0 = io_ren_uops_1_bits_br_mask; // @[dispatch.scala:43:7]
wire [3:0] io_ren_uops_1_bits_br_tag_0 = io_ren_uops_1_bits_br_tag; // @[dispatch.scala:43:7]
wire [3:0] io_ren_uops_1_bits_br_type_0 = io_ren_uops_1_bits_br_type; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_is_sfb_0 = io_ren_uops_1_bits_is_sfb; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_is_fence_0 = io_ren_uops_1_bits_is_fence; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_is_fencei_0 = io_ren_uops_1_bits_is_fencei; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_is_sfence_0 = io_ren_uops_1_bits_is_sfence; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_is_amo_0 = io_ren_uops_1_bits_is_amo; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_is_eret_0 = io_ren_uops_1_bits_is_eret; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_is_sys_pc2epc_0 = io_ren_uops_1_bits_is_sys_pc2epc; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_is_rocc_0 = io_ren_uops_1_bits_is_rocc; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_is_mov_0 = io_ren_uops_1_bits_is_mov; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_1_bits_ftq_idx_0 = io_ren_uops_1_bits_ftq_idx; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_edge_inst_0 = io_ren_uops_1_bits_edge_inst; // @[dispatch.scala:43:7]
wire [5:0] io_ren_uops_1_bits_pc_lob_0 = io_ren_uops_1_bits_pc_lob; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_taken_0 = io_ren_uops_1_bits_taken; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_imm_rename_0 = io_ren_uops_1_bits_imm_rename; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_1_bits_imm_sel_0 = io_ren_uops_1_bits_imm_sel; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_1_bits_pimm_0 = io_ren_uops_1_bits_pimm; // @[dispatch.scala:43:7]
wire [19:0] io_ren_uops_1_bits_imm_packed_0 = io_ren_uops_1_bits_imm_packed; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_1_bits_op1_sel_0 = io_ren_uops_1_bits_op1_sel; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_1_bits_op2_sel_0 = io_ren_uops_1_bits_op2_sel; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_fp_ctrl_ldst_0 = io_ren_uops_1_bits_fp_ctrl_ldst; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_fp_ctrl_wen_0 = io_ren_uops_1_bits_fp_ctrl_wen; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_fp_ctrl_ren1_0 = io_ren_uops_1_bits_fp_ctrl_ren1; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_fp_ctrl_ren2_0 = io_ren_uops_1_bits_fp_ctrl_ren2; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_fp_ctrl_ren3_0 = io_ren_uops_1_bits_fp_ctrl_ren3; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_fp_ctrl_swap12_0 = io_ren_uops_1_bits_fp_ctrl_swap12; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_fp_ctrl_swap23_0 = io_ren_uops_1_bits_fp_ctrl_swap23; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_1_bits_fp_ctrl_typeTagIn_0 = io_ren_uops_1_bits_fp_ctrl_typeTagIn; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_1_bits_fp_ctrl_typeTagOut_0 = io_ren_uops_1_bits_fp_ctrl_typeTagOut; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_fp_ctrl_fromint_0 = io_ren_uops_1_bits_fp_ctrl_fromint; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_fp_ctrl_toint_0 = io_ren_uops_1_bits_fp_ctrl_toint; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_fp_ctrl_fastpipe_0 = io_ren_uops_1_bits_fp_ctrl_fastpipe; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_fp_ctrl_fma_0 = io_ren_uops_1_bits_fp_ctrl_fma; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_fp_ctrl_div_0 = io_ren_uops_1_bits_fp_ctrl_div; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_fp_ctrl_sqrt_0 = io_ren_uops_1_bits_fp_ctrl_sqrt; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_fp_ctrl_wflags_0 = io_ren_uops_1_bits_fp_ctrl_wflags; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_fp_ctrl_vec_0 = io_ren_uops_1_bits_fp_ctrl_vec; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_1_bits_rob_idx_0 = io_ren_uops_1_bits_rob_idx; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_1_bits_ldq_idx_0 = io_ren_uops_1_bits_ldq_idx; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_1_bits_stq_idx_0 = io_ren_uops_1_bits_stq_idx; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_1_bits_rxq_idx_0 = io_ren_uops_1_bits_rxq_idx; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_1_bits_pdst_0 = io_ren_uops_1_bits_pdst; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_1_bits_prs1_0 = io_ren_uops_1_bits_prs1; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_1_bits_prs2_0 = io_ren_uops_1_bits_prs2; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_1_bits_prs3_0 = io_ren_uops_1_bits_prs3; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_1_bits_ppred_0 = io_ren_uops_1_bits_ppred; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_prs1_busy_0 = io_ren_uops_1_bits_prs1_busy; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_prs2_busy_0 = io_ren_uops_1_bits_prs2_busy; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_prs3_busy_0 = io_ren_uops_1_bits_prs3_busy; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_ppred_busy_0 = io_ren_uops_1_bits_ppred_busy; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_1_bits_stale_pdst_0 = io_ren_uops_1_bits_stale_pdst; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_exception_0 = io_ren_uops_1_bits_exception; // @[dispatch.scala:43:7]
wire [63:0] io_ren_uops_1_bits_exc_cause_0 = io_ren_uops_1_bits_exc_cause; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_1_bits_mem_cmd_0 = io_ren_uops_1_bits_mem_cmd; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_1_bits_mem_size_0 = io_ren_uops_1_bits_mem_size; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_mem_signed_0 = io_ren_uops_1_bits_mem_signed; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_uses_ldq_0 = io_ren_uops_1_bits_uses_ldq; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_uses_stq_0 = io_ren_uops_1_bits_uses_stq; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_is_unique_0 = io_ren_uops_1_bits_is_unique; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_flush_on_commit_0 = io_ren_uops_1_bits_flush_on_commit; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_1_bits_csr_cmd_0 = io_ren_uops_1_bits_csr_cmd; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_ldst_is_rs1_0 = io_ren_uops_1_bits_ldst_is_rs1; // @[dispatch.scala:43:7]
wire [5:0] io_ren_uops_1_bits_ldst_0 = io_ren_uops_1_bits_ldst; // @[dispatch.scala:43:7]
wire [5:0] io_ren_uops_1_bits_lrs1_0 = io_ren_uops_1_bits_lrs1; // @[dispatch.scala:43:7]
wire [5:0] io_ren_uops_1_bits_lrs2_0 = io_ren_uops_1_bits_lrs2; // @[dispatch.scala:43:7]
wire [5:0] io_ren_uops_1_bits_lrs3_0 = io_ren_uops_1_bits_lrs3; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_1_bits_dst_rtype_0 = io_ren_uops_1_bits_dst_rtype; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_1_bits_lrs1_rtype_0 = io_ren_uops_1_bits_lrs1_rtype; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_1_bits_lrs2_rtype_0 = io_ren_uops_1_bits_lrs2_rtype; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_frs3_en_0 = io_ren_uops_1_bits_frs3_en; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_fcn_dw_0 = io_ren_uops_1_bits_fcn_dw; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_1_bits_fcn_op_0 = io_ren_uops_1_bits_fcn_op; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_fp_val_0 = io_ren_uops_1_bits_fp_val; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_1_bits_fp_rm_0 = io_ren_uops_1_bits_fp_rm; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_1_bits_fp_typ_0 = io_ren_uops_1_bits_fp_typ; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_xcpt_pf_if_0 = io_ren_uops_1_bits_xcpt_pf_if; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_xcpt_ae_if_0 = io_ren_uops_1_bits_xcpt_ae_if; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_xcpt_ma_if_0 = io_ren_uops_1_bits_xcpt_ma_if; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_bp_debug_if_0 = io_ren_uops_1_bits_bp_debug_if; // @[dispatch.scala:43:7]
wire io_ren_uops_1_bits_bp_xcpt_if_0 = io_ren_uops_1_bits_bp_xcpt_if; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_1_bits_debug_fsrc_0 = io_ren_uops_1_bits_debug_fsrc; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_1_bits_debug_tsrc_0 = io_ren_uops_1_bits_debug_tsrc; // @[dispatch.scala:43:7]
wire io_ren_uops_2_valid_0 = io_ren_uops_2_valid; // @[dispatch.scala:43:7]
wire [31:0] io_ren_uops_2_bits_inst_0 = io_ren_uops_2_bits_inst; // @[dispatch.scala:43:7]
wire [31:0] io_ren_uops_2_bits_debug_inst_0 = io_ren_uops_2_bits_debug_inst; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_is_rvc_0 = io_ren_uops_2_bits_is_rvc; // @[dispatch.scala:43:7]
wire [39:0] io_ren_uops_2_bits_debug_pc_0 = io_ren_uops_2_bits_debug_pc; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_iq_type_0_0 = io_ren_uops_2_bits_iq_type_0; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_iq_type_1_0 = io_ren_uops_2_bits_iq_type_1; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_iq_type_2_0 = io_ren_uops_2_bits_iq_type_2; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_iq_type_3_0 = io_ren_uops_2_bits_iq_type_3; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_fu_code_0_0 = io_ren_uops_2_bits_fu_code_0; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_fu_code_1_0 = io_ren_uops_2_bits_fu_code_1; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_fu_code_2_0 = io_ren_uops_2_bits_fu_code_2; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_fu_code_3_0 = io_ren_uops_2_bits_fu_code_3; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_fu_code_4_0 = io_ren_uops_2_bits_fu_code_4; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_fu_code_5_0 = io_ren_uops_2_bits_fu_code_5; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_fu_code_6_0 = io_ren_uops_2_bits_fu_code_6; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_fu_code_7_0 = io_ren_uops_2_bits_fu_code_7; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_fu_code_8_0 = io_ren_uops_2_bits_fu_code_8; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_fu_code_9_0 = io_ren_uops_2_bits_fu_code_9; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_iw_issued_0 = io_ren_uops_2_bits_iw_issued; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_iw_issued_partial_agen_0 = io_ren_uops_2_bits_iw_issued_partial_agen; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_iw_issued_partial_dgen_0 = io_ren_uops_2_bits_iw_issued_partial_dgen; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_2_bits_iw_p1_speculative_child_0 = io_ren_uops_2_bits_iw_p1_speculative_child; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_2_bits_iw_p2_speculative_child_0 = io_ren_uops_2_bits_iw_p2_speculative_child; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_iw_p1_bypass_hint_0 = io_ren_uops_2_bits_iw_p1_bypass_hint; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_iw_p2_bypass_hint_0 = io_ren_uops_2_bits_iw_p2_bypass_hint; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_iw_p3_bypass_hint_0 = io_ren_uops_2_bits_iw_p3_bypass_hint; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_2_bits_dis_col_sel_0 = io_ren_uops_2_bits_dis_col_sel; // @[dispatch.scala:43:7]
wire [15:0] io_ren_uops_2_bits_br_mask_0 = io_ren_uops_2_bits_br_mask; // @[dispatch.scala:43:7]
wire [3:0] io_ren_uops_2_bits_br_tag_0 = io_ren_uops_2_bits_br_tag; // @[dispatch.scala:43:7]
wire [3:0] io_ren_uops_2_bits_br_type_0 = io_ren_uops_2_bits_br_type; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_is_sfb_0 = io_ren_uops_2_bits_is_sfb; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_is_fence_0 = io_ren_uops_2_bits_is_fence; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_is_fencei_0 = io_ren_uops_2_bits_is_fencei; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_is_sfence_0 = io_ren_uops_2_bits_is_sfence; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_is_amo_0 = io_ren_uops_2_bits_is_amo; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_is_eret_0 = io_ren_uops_2_bits_is_eret; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_is_sys_pc2epc_0 = io_ren_uops_2_bits_is_sys_pc2epc; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_is_rocc_0 = io_ren_uops_2_bits_is_rocc; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_is_mov_0 = io_ren_uops_2_bits_is_mov; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_2_bits_ftq_idx_0 = io_ren_uops_2_bits_ftq_idx; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_edge_inst_0 = io_ren_uops_2_bits_edge_inst; // @[dispatch.scala:43:7]
wire [5:0] io_ren_uops_2_bits_pc_lob_0 = io_ren_uops_2_bits_pc_lob; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_taken_0 = io_ren_uops_2_bits_taken; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_imm_rename_0 = io_ren_uops_2_bits_imm_rename; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_2_bits_imm_sel_0 = io_ren_uops_2_bits_imm_sel; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_2_bits_pimm_0 = io_ren_uops_2_bits_pimm; // @[dispatch.scala:43:7]
wire [19:0] io_ren_uops_2_bits_imm_packed_0 = io_ren_uops_2_bits_imm_packed; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_2_bits_op1_sel_0 = io_ren_uops_2_bits_op1_sel; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_2_bits_op2_sel_0 = io_ren_uops_2_bits_op2_sel; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_fp_ctrl_ldst_0 = io_ren_uops_2_bits_fp_ctrl_ldst; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_fp_ctrl_wen_0 = io_ren_uops_2_bits_fp_ctrl_wen; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_fp_ctrl_ren1_0 = io_ren_uops_2_bits_fp_ctrl_ren1; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_fp_ctrl_ren2_0 = io_ren_uops_2_bits_fp_ctrl_ren2; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_fp_ctrl_ren3_0 = io_ren_uops_2_bits_fp_ctrl_ren3; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_fp_ctrl_swap12_0 = io_ren_uops_2_bits_fp_ctrl_swap12; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_fp_ctrl_swap23_0 = io_ren_uops_2_bits_fp_ctrl_swap23; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_2_bits_fp_ctrl_typeTagIn_0 = io_ren_uops_2_bits_fp_ctrl_typeTagIn; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_2_bits_fp_ctrl_typeTagOut_0 = io_ren_uops_2_bits_fp_ctrl_typeTagOut; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_fp_ctrl_fromint_0 = io_ren_uops_2_bits_fp_ctrl_fromint; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_fp_ctrl_toint_0 = io_ren_uops_2_bits_fp_ctrl_toint; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_fp_ctrl_fastpipe_0 = io_ren_uops_2_bits_fp_ctrl_fastpipe; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_fp_ctrl_fma_0 = io_ren_uops_2_bits_fp_ctrl_fma; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_fp_ctrl_div_0 = io_ren_uops_2_bits_fp_ctrl_div; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_fp_ctrl_sqrt_0 = io_ren_uops_2_bits_fp_ctrl_sqrt; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_fp_ctrl_wflags_0 = io_ren_uops_2_bits_fp_ctrl_wflags; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_fp_ctrl_vec_0 = io_ren_uops_2_bits_fp_ctrl_vec; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_2_bits_rob_idx_0 = io_ren_uops_2_bits_rob_idx; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_2_bits_ldq_idx_0 = io_ren_uops_2_bits_ldq_idx; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_2_bits_stq_idx_0 = io_ren_uops_2_bits_stq_idx; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_2_bits_rxq_idx_0 = io_ren_uops_2_bits_rxq_idx; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_2_bits_pdst_0 = io_ren_uops_2_bits_pdst; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_2_bits_prs1_0 = io_ren_uops_2_bits_prs1; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_2_bits_prs2_0 = io_ren_uops_2_bits_prs2; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_2_bits_prs3_0 = io_ren_uops_2_bits_prs3; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_2_bits_ppred_0 = io_ren_uops_2_bits_ppred; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_prs1_busy_0 = io_ren_uops_2_bits_prs1_busy; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_prs2_busy_0 = io_ren_uops_2_bits_prs2_busy; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_prs3_busy_0 = io_ren_uops_2_bits_prs3_busy; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_ppred_busy_0 = io_ren_uops_2_bits_ppred_busy; // @[dispatch.scala:43:7]
wire [6:0] io_ren_uops_2_bits_stale_pdst_0 = io_ren_uops_2_bits_stale_pdst; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_exception_0 = io_ren_uops_2_bits_exception; // @[dispatch.scala:43:7]
wire [63:0] io_ren_uops_2_bits_exc_cause_0 = io_ren_uops_2_bits_exc_cause; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_2_bits_mem_cmd_0 = io_ren_uops_2_bits_mem_cmd; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_2_bits_mem_size_0 = io_ren_uops_2_bits_mem_size; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_mem_signed_0 = io_ren_uops_2_bits_mem_signed; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_uses_ldq_0 = io_ren_uops_2_bits_uses_ldq; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_uses_stq_0 = io_ren_uops_2_bits_uses_stq; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_is_unique_0 = io_ren_uops_2_bits_is_unique; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_flush_on_commit_0 = io_ren_uops_2_bits_flush_on_commit; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_2_bits_csr_cmd_0 = io_ren_uops_2_bits_csr_cmd; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_ldst_is_rs1_0 = io_ren_uops_2_bits_ldst_is_rs1; // @[dispatch.scala:43:7]
wire [5:0] io_ren_uops_2_bits_ldst_0 = io_ren_uops_2_bits_ldst; // @[dispatch.scala:43:7]
wire [5:0] io_ren_uops_2_bits_lrs1_0 = io_ren_uops_2_bits_lrs1; // @[dispatch.scala:43:7]
wire [5:0] io_ren_uops_2_bits_lrs2_0 = io_ren_uops_2_bits_lrs2; // @[dispatch.scala:43:7]
wire [5:0] io_ren_uops_2_bits_lrs3_0 = io_ren_uops_2_bits_lrs3; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_2_bits_dst_rtype_0 = io_ren_uops_2_bits_dst_rtype; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_2_bits_lrs1_rtype_0 = io_ren_uops_2_bits_lrs1_rtype; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_2_bits_lrs2_rtype_0 = io_ren_uops_2_bits_lrs2_rtype; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_frs3_en_0 = io_ren_uops_2_bits_frs3_en; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_fcn_dw_0 = io_ren_uops_2_bits_fcn_dw; // @[dispatch.scala:43:7]
wire [4:0] io_ren_uops_2_bits_fcn_op_0 = io_ren_uops_2_bits_fcn_op; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_fp_val_0 = io_ren_uops_2_bits_fp_val; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_2_bits_fp_rm_0 = io_ren_uops_2_bits_fp_rm; // @[dispatch.scala:43:7]
wire [1:0] io_ren_uops_2_bits_fp_typ_0 = io_ren_uops_2_bits_fp_typ; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_xcpt_pf_if_0 = io_ren_uops_2_bits_xcpt_pf_if; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_xcpt_ae_if_0 = io_ren_uops_2_bits_xcpt_ae_if; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_xcpt_ma_if_0 = io_ren_uops_2_bits_xcpt_ma_if; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_bp_debug_if_0 = io_ren_uops_2_bits_bp_debug_if; // @[dispatch.scala:43:7]
wire io_ren_uops_2_bits_bp_xcpt_if_0 = io_ren_uops_2_bits_bp_xcpt_if; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_2_bits_debug_fsrc_0 = io_ren_uops_2_bits_debug_fsrc; // @[dispatch.scala:43:7]
wire [2:0] io_ren_uops_2_bits_debug_tsrc_0 = io_ren_uops_2_bits_debug_tsrc; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_ready_0 = io_dis_uops_3_0_ready; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_ready_0 = io_dis_uops_3_1_ready; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_ready_0 = io_dis_uops_3_2_ready; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_ready_0 = io_dis_uops_2_0_ready; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_ready_0 = io_dis_uops_2_1_ready; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_ready_0 = io_dis_uops_2_2_ready; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_ready_0 = io_dis_uops_1_0_ready; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_ready_0 = io_dis_uops_1_1_ready; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_ready_0 = io_dis_uops_1_2_ready; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_ready_0 = io_dis_uops_0_0_ready; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_ready_0 = io_dis_uops_0_1_ready; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_ready_0 = io_dis_uops_0_2_ready; // @[dispatch.scala:43:7]
wire _io_ren_uops_0_ready_T; // @[dispatch.scala:50:39]
wire [31:0] io_dis_uops_3_0_bits_inst_0 = io_ren_uops_0_bits_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_2_0_bits_inst_0 = io_ren_uops_0_bits_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_1_0_bits_inst_0 = io_ren_uops_0_bits_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_0_0_bits_inst_0 = io_ren_uops_0_bits_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_3_0_bits_debug_inst_0 = io_ren_uops_0_bits_debug_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_2_0_bits_debug_inst_0 = io_ren_uops_0_bits_debug_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_1_0_bits_debug_inst_0 = io_ren_uops_0_bits_debug_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_0_0_bits_debug_inst_0 = io_ren_uops_0_bits_debug_inst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_is_rvc_0 = io_ren_uops_0_bits_is_rvc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_is_rvc_0 = io_ren_uops_0_bits_is_rvc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_is_rvc_0 = io_ren_uops_0_bits_is_rvc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_is_rvc_0 = io_ren_uops_0_bits_is_rvc_0; // @[dispatch.scala:43:7]
wire [39:0] io_dis_uops_3_0_bits_debug_pc_0 = io_ren_uops_0_bits_debug_pc_0; // @[dispatch.scala:43:7]
wire [39:0] io_dis_uops_2_0_bits_debug_pc_0 = io_ren_uops_0_bits_debug_pc_0; // @[dispatch.scala:43:7]
wire [39:0] io_dis_uops_1_0_bits_debug_pc_0 = io_ren_uops_0_bits_debug_pc_0; // @[dispatch.scala:43:7]
wire [39:0] io_dis_uops_0_0_bits_debug_pc_0 = io_ren_uops_0_bits_debug_pc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_iq_type_0_0 = io_ren_uops_0_bits_iq_type_0_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_iq_type_0_0 = io_ren_uops_0_bits_iq_type_0_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_iq_type_0_0 = io_ren_uops_0_bits_iq_type_0_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_iq_type_0_0 = io_ren_uops_0_bits_iq_type_0_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_iq_type_1_0 = io_ren_uops_0_bits_iq_type_1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_iq_type_1_0 = io_ren_uops_0_bits_iq_type_1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_iq_type_1_0 = io_ren_uops_0_bits_iq_type_1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_iq_type_1_0 = io_ren_uops_0_bits_iq_type_1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_iq_type_2_0 = io_ren_uops_0_bits_iq_type_2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_iq_type_2_0 = io_ren_uops_0_bits_iq_type_2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_iq_type_2_0 = io_ren_uops_0_bits_iq_type_2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_iq_type_2_0 = io_ren_uops_0_bits_iq_type_2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_iq_type_3_0 = io_ren_uops_0_bits_iq_type_3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_iq_type_3_0 = io_ren_uops_0_bits_iq_type_3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_iq_type_3_0 = io_ren_uops_0_bits_iq_type_3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_iq_type_3_0 = io_ren_uops_0_bits_iq_type_3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_fu_code_0_0 = io_ren_uops_0_bits_fu_code_0_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_fu_code_0_0 = io_ren_uops_0_bits_fu_code_0_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_fu_code_0_0 = io_ren_uops_0_bits_fu_code_0_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_fu_code_0_0 = io_ren_uops_0_bits_fu_code_0_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_fu_code_1_0 = io_ren_uops_0_bits_fu_code_1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_fu_code_1_0 = io_ren_uops_0_bits_fu_code_1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_fu_code_1_0 = io_ren_uops_0_bits_fu_code_1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_fu_code_1_0 = io_ren_uops_0_bits_fu_code_1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_fu_code_2_0 = io_ren_uops_0_bits_fu_code_2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_fu_code_2_0 = io_ren_uops_0_bits_fu_code_2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_fu_code_2_0 = io_ren_uops_0_bits_fu_code_2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_fu_code_2_0 = io_ren_uops_0_bits_fu_code_2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_fu_code_3_0 = io_ren_uops_0_bits_fu_code_3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_fu_code_3_0 = io_ren_uops_0_bits_fu_code_3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_fu_code_3_0 = io_ren_uops_0_bits_fu_code_3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_fu_code_3_0 = io_ren_uops_0_bits_fu_code_3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_fu_code_4_0 = io_ren_uops_0_bits_fu_code_4_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_fu_code_4_0 = io_ren_uops_0_bits_fu_code_4_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_fu_code_4_0 = io_ren_uops_0_bits_fu_code_4_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_fu_code_4_0 = io_ren_uops_0_bits_fu_code_4_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_fu_code_5_0 = io_ren_uops_0_bits_fu_code_5_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_fu_code_5_0 = io_ren_uops_0_bits_fu_code_5_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_fu_code_5_0 = io_ren_uops_0_bits_fu_code_5_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_fu_code_5_0 = io_ren_uops_0_bits_fu_code_5_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_fu_code_6_0 = io_ren_uops_0_bits_fu_code_6_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_fu_code_6_0 = io_ren_uops_0_bits_fu_code_6_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_fu_code_6_0 = io_ren_uops_0_bits_fu_code_6_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_fu_code_6_0 = io_ren_uops_0_bits_fu_code_6_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_fu_code_7_0 = io_ren_uops_0_bits_fu_code_7_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_fu_code_7_0 = io_ren_uops_0_bits_fu_code_7_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_fu_code_7_0 = io_ren_uops_0_bits_fu_code_7_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_fu_code_7_0 = io_ren_uops_0_bits_fu_code_7_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_fu_code_8_0 = io_ren_uops_0_bits_fu_code_8_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_fu_code_8_0 = io_ren_uops_0_bits_fu_code_8_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_fu_code_8_0 = io_ren_uops_0_bits_fu_code_8_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_fu_code_8_0 = io_ren_uops_0_bits_fu_code_8_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_fu_code_9_0 = io_ren_uops_0_bits_fu_code_9_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_fu_code_9_0 = io_ren_uops_0_bits_fu_code_9_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_fu_code_9_0 = io_ren_uops_0_bits_fu_code_9_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_fu_code_9_0 = io_ren_uops_0_bits_fu_code_9_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_iw_issued_0 = io_ren_uops_0_bits_iw_issued_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_iw_issued_0 = io_ren_uops_0_bits_iw_issued_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_iw_issued_0 = io_ren_uops_0_bits_iw_issued_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_iw_issued_0 = io_ren_uops_0_bits_iw_issued_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_iw_issued_partial_agen_0 = io_ren_uops_0_bits_iw_issued_partial_agen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_iw_issued_partial_agen_0 = io_ren_uops_0_bits_iw_issued_partial_agen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_iw_issued_partial_agen_0 = io_ren_uops_0_bits_iw_issued_partial_agen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_iw_issued_partial_agen_0 = io_ren_uops_0_bits_iw_issued_partial_agen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_iw_issued_partial_dgen_0 = io_ren_uops_0_bits_iw_issued_partial_dgen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_iw_issued_partial_dgen_0 = io_ren_uops_0_bits_iw_issued_partial_dgen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_iw_issued_partial_dgen_0 = io_ren_uops_0_bits_iw_issued_partial_dgen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_iw_issued_partial_dgen_0 = io_ren_uops_0_bits_iw_issued_partial_dgen_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_3_0_bits_iw_p1_speculative_child_0 = io_ren_uops_0_bits_iw_p1_speculative_child_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_0_bits_iw_p1_speculative_child_0 = io_ren_uops_0_bits_iw_p1_speculative_child_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_0_bits_iw_p1_speculative_child_0 = io_ren_uops_0_bits_iw_p1_speculative_child_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_0_bits_iw_p1_speculative_child_0 = io_ren_uops_0_bits_iw_p1_speculative_child_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_3_0_bits_iw_p2_speculative_child_0 = io_ren_uops_0_bits_iw_p2_speculative_child_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_0_bits_iw_p2_speculative_child_0 = io_ren_uops_0_bits_iw_p2_speculative_child_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_0_bits_iw_p2_speculative_child_0 = io_ren_uops_0_bits_iw_p2_speculative_child_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_0_bits_iw_p2_speculative_child_0 = io_ren_uops_0_bits_iw_p2_speculative_child_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_iw_p1_bypass_hint_0 = io_ren_uops_0_bits_iw_p1_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_iw_p1_bypass_hint_0 = io_ren_uops_0_bits_iw_p1_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_iw_p1_bypass_hint_0 = io_ren_uops_0_bits_iw_p1_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_iw_p1_bypass_hint_0 = io_ren_uops_0_bits_iw_p1_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_iw_p2_bypass_hint_0 = io_ren_uops_0_bits_iw_p2_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_iw_p2_bypass_hint_0 = io_ren_uops_0_bits_iw_p2_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_iw_p2_bypass_hint_0 = io_ren_uops_0_bits_iw_p2_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_iw_p2_bypass_hint_0 = io_ren_uops_0_bits_iw_p2_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_iw_p3_bypass_hint_0 = io_ren_uops_0_bits_iw_p3_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_iw_p3_bypass_hint_0 = io_ren_uops_0_bits_iw_p3_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_iw_p3_bypass_hint_0 = io_ren_uops_0_bits_iw_p3_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_iw_p3_bypass_hint_0 = io_ren_uops_0_bits_iw_p3_bypass_hint_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_3_0_bits_dis_col_sel_0 = io_ren_uops_0_bits_dis_col_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_0_bits_dis_col_sel_0 = io_ren_uops_0_bits_dis_col_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_0_bits_dis_col_sel_0 = io_ren_uops_0_bits_dis_col_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_0_bits_dis_col_sel_0 = io_ren_uops_0_bits_dis_col_sel_0; // @[dispatch.scala:43:7]
wire [15:0] io_dis_uops_3_0_bits_br_mask_0 = io_ren_uops_0_bits_br_mask_0; // @[dispatch.scala:43:7]
wire [15:0] io_dis_uops_2_0_bits_br_mask_0 = io_ren_uops_0_bits_br_mask_0; // @[dispatch.scala:43:7]
wire [15:0] io_dis_uops_1_0_bits_br_mask_0 = io_ren_uops_0_bits_br_mask_0; // @[dispatch.scala:43:7]
wire [15:0] io_dis_uops_0_0_bits_br_mask_0 = io_ren_uops_0_bits_br_mask_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_3_0_bits_br_tag_0 = io_ren_uops_0_bits_br_tag_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_2_0_bits_br_tag_0 = io_ren_uops_0_bits_br_tag_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_1_0_bits_br_tag_0 = io_ren_uops_0_bits_br_tag_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_0_0_bits_br_tag_0 = io_ren_uops_0_bits_br_tag_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_3_0_bits_br_type_0 = io_ren_uops_0_bits_br_type_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_2_0_bits_br_type_0 = io_ren_uops_0_bits_br_type_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_1_0_bits_br_type_0 = io_ren_uops_0_bits_br_type_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_0_0_bits_br_type_0 = io_ren_uops_0_bits_br_type_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_is_sfb_0 = io_ren_uops_0_bits_is_sfb_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_is_sfb_0 = io_ren_uops_0_bits_is_sfb_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_is_sfb_0 = io_ren_uops_0_bits_is_sfb_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_is_sfb_0 = io_ren_uops_0_bits_is_sfb_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_is_fence_0 = io_ren_uops_0_bits_is_fence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_is_fence_0 = io_ren_uops_0_bits_is_fence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_is_fence_0 = io_ren_uops_0_bits_is_fence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_is_fence_0 = io_ren_uops_0_bits_is_fence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_is_fencei_0 = io_ren_uops_0_bits_is_fencei_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_is_fencei_0 = io_ren_uops_0_bits_is_fencei_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_is_fencei_0 = io_ren_uops_0_bits_is_fencei_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_is_fencei_0 = io_ren_uops_0_bits_is_fencei_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_is_sfence_0 = io_ren_uops_0_bits_is_sfence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_is_sfence_0 = io_ren_uops_0_bits_is_sfence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_is_sfence_0 = io_ren_uops_0_bits_is_sfence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_is_sfence_0 = io_ren_uops_0_bits_is_sfence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_is_amo_0 = io_ren_uops_0_bits_is_amo_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_is_amo_0 = io_ren_uops_0_bits_is_amo_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_is_amo_0 = io_ren_uops_0_bits_is_amo_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_is_amo_0 = io_ren_uops_0_bits_is_amo_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_is_eret_0 = io_ren_uops_0_bits_is_eret_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_is_eret_0 = io_ren_uops_0_bits_is_eret_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_is_eret_0 = io_ren_uops_0_bits_is_eret_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_is_eret_0 = io_ren_uops_0_bits_is_eret_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_is_sys_pc2epc_0 = io_ren_uops_0_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_is_sys_pc2epc_0 = io_ren_uops_0_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_is_sys_pc2epc_0 = io_ren_uops_0_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_is_sys_pc2epc_0 = io_ren_uops_0_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_is_rocc_0 = io_ren_uops_0_bits_is_rocc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_is_rocc_0 = io_ren_uops_0_bits_is_rocc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_is_rocc_0 = io_ren_uops_0_bits_is_rocc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_is_rocc_0 = io_ren_uops_0_bits_is_rocc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_is_mov_0 = io_ren_uops_0_bits_is_mov_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_is_mov_0 = io_ren_uops_0_bits_is_mov_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_is_mov_0 = io_ren_uops_0_bits_is_mov_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_is_mov_0 = io_ren_uops_0_bits_is_mov_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_3_0_bits_ftq_idx_0 = io_ren_uops_0_bits_ftq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_0_bits_ftq_idx_0 = io_ren_uops_0_bits_ftq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_0_bits_ftq_idx_0 = io_ren_uops_0_bits_ftq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_0_bits_ftq_idx_0 = io_ren_uops_0_bits_ftq_idx_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_edge_inst_0 = io_ren_uops_0_bits_edge_inst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_edge_inst_0 = io_ren_uops_0_bits_edge_inst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_edge_inst_0 = io_ren_uops_0_bits_edge_inst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_edge_inst_0 = io_ren_uops_0_bits_edge_inst_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_3_0_bits_pc_lob_0 = io_ren_uops_0_bits_pc_lob_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_2_0_bits_pc_lob_0 = io_ren_uops_0_bits_pc_lob_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_1_0_bits_pc_lob_0 = io_ren_uops_0_bits_pc_lob_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_0_0_bits_pc_lob_0 = io_ren_uops_0_bits_pc_lob_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_taken_0 = io_ren_uops_0_bits_taken_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_taken_0 = io_ren_uops_0_bits_taken_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_taken_0 = io_ren_uops_0_bits_taken_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_taken_0 = io_ren_uops_0_bits_taken_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_imm_rename_0 = io_ren_uops_0_bits_imm_rename_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_imm_rename_0 = io_ren_uops_0_bits_imm_rename_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_imm_rename_0 = io_ren_uops_0_bits_imm_rename_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_imm_rename_0 = io_ren_uops_0_bits_imm_rename_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_3_0_bits_imm_sel_0 = io_ren_uops_0_bits_imm_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_0_bits_imm_sel_0 = io_ren_uops_0_bits_imm_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_0_bits_imm_sel_0 = io_ren_uops_0_bits_imm_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_0_bits_imm_sel_0 = io_ren_uops_0_bits_imm_sel_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_3_0_bits_pimm_0 = io_ren_uops_0_bits_pimm_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_0_bits_pimm_0 = io_ren_uops_0_bits_pimm_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_0_bits_pimm_0 = io_ren_uops_0_bits_pimm_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_0_bits_pimm_0 = io_ren_uops_0_bits_pimm_0; // @[dispatch.scala:43:7]
wire [19:0] io_dis_uops_3_0_bits_imm_packed_0 = io_ren_uops_0_bits_imm_packed_0; // @[dispatch.scala:43:7]
wire [19:0] io_dis_uops_2_0_bits_imm_packed_0 = io_ren_uops_0_bits_imm_packed_0; // @[dispatch.scala:43:7]
wire [19:0] io_dis_uops_1_0_bits_imm_packed_0 = io_ren_uops_0_bits_imm_packed_0; // @[dispatch.scala:43:7]
wire [19:0] io_dis_uops_0_0_bits_imm_packed_0 = io_ren_uops_0_bits_imm_packed_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_3_0_bits_op1_sel_0 = io_ren_uops_0_bits_op1_sel_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_0_bits_op1_sel_0 = io_ren_uops_0_bits_op1_sel_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_0_bits_op1_sel_0 = io_ren_uops_0_bits_op1_sel_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_0_bits_op1_sel_0 = io_ren_uops_0_bits_op1_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_3_0_bits_op2_sel_0 = io_ren_uops_0_bits_op2_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_0_bits_op2_sel_0 = io_ren_uops_0_bits_op2_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_0_bits_op2_sel_0 = io_ren_uops_0_bits_op2_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_0_bits_op2_sel_0 = io_ren_uops_0_bits_op2_sel_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_fp_ctrl_ldst_0 = io_ren_uops_0_bits_fp_ctrl_ldst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_fp_ctrl_ldst_0 = io_ren_uops_0_bits_fp_ctrl_ldst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_fp_ctrl_ldst_0 = io_ren_uops_0_bits_fp_ctrl_ldst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_fp_ctrl_ldst_0 = io_ren_uops_0_bits_fp_ctrl_ldst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_fp_ctrl_wen_0 = io_ren_uops_0_bits_fp_ctrl_wen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_fp_ctrl_wen_0 = io_ren_uops_0_bits_fp_ctrl_wen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_fp_ctrl_wen_0 = io_ren_uops_0_bits_fp_ctrl_wen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_fp_ctrl_wen_0 = io_ren_uops_0_bits_fp_ctrl_wen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_fp_ctrl_ren1_0 = io_ren_uops_0_bits_fp_ctrl_ren1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_fp_ctrl_ren1_0 = io_ren_uops_0_bits_fp_ctrl_ren1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_fp_ctrl_ren1_0 = io_ren_uops_0_bits_fp_ctrl_ren1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_fp_ctrl_ren1_0 = io_ren_uops_0_bits_fp_ctrl_ren1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_fp_ctrl_ren2_0 = io_ren_uops_0_bits_fp_ctrl_ren2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_fp_ctrl_ren2_0 = io_ren_uops_0_bits_fp_ctrl_ren2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_fp_ctrl_ren2_0 = io_ren_uops_0_bits_fp_ctrl_ren2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_fp_ctrl_ren2_0 = io_ren_uops_0_bits_fp_ctrl_ren2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_fp_ctrl_ren3_0 = io_ren_uops_0_bits_fp_ctrl_ren3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_fp_ctrl_ren3_0 = io_ren_uops_0_bits_fp_ctrl_ren3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_fp_ctrl_ren3_0 = io_ren_uops_0_bits_fp_ctrl_ren3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_fp_ctrl_ren3_0 = io_ren_uops_0_bits_fp_ctrl_ren3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_fp_ctrl_swap12_0 = io_ren_uops_0_bits_fp_ctrl_swap12_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_fp_ctrl_swap12_0 = io_ren_uops_0_bits_fp_ctrl_swap12_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_fp_ctrl_swap12_0 = io_ren_uops_0_bits_fp_ctrl_swap12_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_fp_ctrl_swap12_0 = io_ren_uops_0_bits_fp_ctrl_swap12_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_fp_ctrl_swap23_0 = io_ren_uops_0_bits_fp_ctrl_swap23_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_fp_ctrl_swap23_0 = io_ren_uops_0_bits_fp_ctrl_swap23_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_fp_ctrl_swap23_0 = io_ren_uops_0_bits_fp_ctrl_swap23_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_fp_ctrl_swap23_0 = io_ren_uops_0_bits_fp_ctrl_swap23_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_3_0_bits_fp_ctrl_typeTagIn_0 = io_ren_uops_0_bits_fp_ctrl_typeTagIn_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_0_bits_fp_ctrl_typeTagIn_0 = io_ren_uops_0_bits_fp_ctrl_typeTagIn_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_0_bits_fp_ctrl_typeTagIn_0 = io_ren_uops_0_bits_fp_ctrl_typeTagIn_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_0_bits_fp_ctrl_typeTagIn_0 = io_ren_uops_0_bits_fp_ctrl_typeTagIn_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_3_0_bits_fp_ctrl_typeTagOut_0 = io_ren_uops_0_bits_fp_ctrl_typeTagOut_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_0_bits_fp_ctrl_typeTagOut_0 = io_ren_uops_0_bits_fp_ctrl_typeTagOut_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_0_bits_fp_ctrl_typeTagOut_0 = io_ren_uops_0_bits_fp_ctrl_typeTagOut_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_0_bits_fp_ctrl_typeTagOut_0 = io_ren_uops_0_bits_fp_ctrl_typeTagOut_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_fp_ctrl_fromint_0 = io_ren_uops_0_bits_fp_ctrl_fromint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_fp_ctrl_fromint_0 = io_ren_uops_0_bits_fp_ctrl_fromint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_fp_ctrl_fromint_0 = io_ren_uops_0_bits_fp_ctrl_fromint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_fp_ctrl_fromint_0 = io_ren_uops_0_bits_fp_ctrl_fromint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_fp_ctrl_toint_0 = io_ren_uops_0_bits_fp_ctrl_toint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_fp_ctrl_toint_0 = io_ren_uops_0_bits_fp_ctrl_toint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_fp_ctrl_toint_0 = io_ren_uops_0_bits_fp_ctrl_toint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_fp_ctrl_toint_0 = io_ren_uops_0_bits_fp_ctrl_toint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_fp_ctrl_fastpipe_0 = io_ren_uops_0_bits_fp_ctrl_fastpipe_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_fp_ctrl_fastpipe_0 = io_ren_uops_0_bits_fp_ctrl_fastpipe_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_fp_ctrl_fastpipe_0 = io_ren_uops_0_bits_fp_ctrl_fastpipe_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_fp_ctrl_fastpipe_0 = io_ren_uops_0_bits_fp_ctrl_fastpipe_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_fp_ctrl_fma_0 = io_ren_uops_0_bits_fp_ctrl_fma_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_fp_ctrl_fma_0 = io_ren_uops_0_bits_fp_ctrl_fma_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_fp_ctrl_fma_0 = io_ren_uops_0_bits_fp_ctrl_fma_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_fp_ctrl_fma_0 = io_ren_uops_0_bits_fp_ctrl_fma_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_fp_ctrl_div_0 = io_ren_uops_0_bits_fp_ctrl_div_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_fp_ctrl_div_0 = io_ren_uops_0_bits_fp_ctrl_div_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_fp_ctrl_div_0 = io_ren_uops_0_bits_fp_ctrl_div_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_fp_ctrl_div_0 = io_ren_uops_0_bits_fp_ctrl_div_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_fp_ctrl_sqrt_0 = io_ren_uops_0_bits_fp_ctrl_sqrt_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_fp_ctrl_sqrt_0 = io_ren_uops_0_bits_fp_ctrl_sqrt_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_fp_ctrl_sqrt_0 = io_ren_uops_0_bits_fp_ctrl_sqrt_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_fp_ctrl_sqrt_0 = io_ren_uops_0_bits_fp_ctrl_sqrt_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_fp_ctrl_wflags_0 = io_ren_uops_0_bits_fp_ctrl_wflags_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_fp_ctrl_wflags_0 = io_ren_uops_0_bits_fp_ctrl_wflags_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_fp_ctrl_wflags_0 = io_ren_uops_0_bits_fp_ctrl_wflags_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_fp_ctrl_wflags_0 = io_ren_uops_0_bits_fp_ctrl_wflags_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_fp_ctrl_vec_0 = io_ren_uops_0_bits_fp_ctrl_vec_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_fp_ctrl_vec_0 = io_ren_uops_0_bits_fp_ctrl_vec_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_fp_ctrl_vec_0 = io_ren_uops_0_bits_fp_ctrl_vec_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_fp_ctrl_vec_0 = io_ren_uops_0_bits_fp_ctrl_vec_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_3_0_bits_rob_idx_0 = io_ren_uops_0_bits_rob_idx_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_0_bits_rob_idx_0 = io_ren_uops_0_bits_rob_idx_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_0_bits_rob_idx_0 = io_ren_uops_0_bits_rob_idx_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_0_bits_rob_idx_0 = io_ren_uops_0_bits_rob_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_3_0_bits_ldq_idx_0 = io_ren_uops_0_bits_ldq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_0_bits_ldq_idx_0 = io_ren_uops_0_bits_ldq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_0_bits_ldq_idx_0 = io_ren_uops_0_bits_ldq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_0_bits_ldq_idx_0 = io_ren_uops_0_bits_ldq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_3_0_bits_stq_idx_0 = io_ren_uops_0_bits_stq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_0_bits_stq_idx_0 = io_ren_uops_0_bits_stq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_0_bits_stq_idx_0 = io_ren_uops_0_bits_stq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_0_bits_stq_idx_0 = io_ren_uops_0_bits_stq_idx_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_3_0_bits_rxq_idx_0 = io_ren_uops_0_bits_rxq_idx_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_0_bits_rxq_idx_0 = io_ren_uops_0_bits_rxq_idx_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_0_bits_rxq_idx_0 = io_ren_uops_0_bits_rxq_idx_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_0_bits_rxq_idx_0 = io_ren_uops_0_bits_rxq_idx_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_3_0_bits_pdst_0 = io_ren_uops_0_bits_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_0_bits_pdst_0 = io_ren_uops_0_bits_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_0_bits_pdst_0 = io_ren_uops_0_bits_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_0_bits_pdst_0 = io_ren_uops_0_bits_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_3_0_bits_prs1_0 = io_ren_uops_0_bits_prs1_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_0_bits_prs1_0 = io_ren_uops_0_bits_prs1_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_0_bits_prs1_0 = io_ren_uops_0_bits_prs1_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_0_bits_prs1_0 = io_ren_uops_0_bits_prs1_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_3_0_bits_prs2_0 = io_ren_uops_0_bits_prs2_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_0_bits_prs2_0 = io_ren_uops_0_bits_prs2_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_0_bits_prs2_0 = io_ren_uops_0_bits_prs2_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_0_bits_prs2_0 = io_ren_uops_0_bits_prs2_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_3_0_bits_prs3_0 = io_ren_uops_0_bits_prs3_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_0_bits_prs3_0 = io_ren_uops_0_bits_prs3_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_0_bits_prs3_0 = io_ren_uops_0_bits_prs3_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_0_bits_prs3_0 = io_ren_uops_0_bits_prs3_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_3_0_bits_ppred_0 = io_ren_uops_0_bits_ppred_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_0_bits_ppred_0 = io_ren_uops_0_bits_ppred_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_0_bits_ppred_0 = io_ren_uops_0_bits_ppred_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_0_bits_ppred_0 = io_ren_uops_0_bits_ppred_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_prs1_busy_0 = io_ren_uops_0_bits_prs1_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_prs1_busy_0 = io_ren_uops_0_bits_prs1_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_prs1_busy_0 = io_ren_uops_0_bits_prs1_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_prs1_busy_0 = io_ren_uops_0_bits_prs1_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_prs2_busy_0 = io_ren_uops_0_bits_prs2_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_prs2_busy_0 = io_ren_uops_0_bits_prs2_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_prs2_busy_0 = io_ren_uops_0_bits_prs2_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_prs2_busy_0 = io_ren_uops_0_bits_prs2_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_prs3_busy_0 = io_ren_uops_0_bits_prs3_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_prs3_busy_0 = io_ren_uops_0_bits_prs3_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_prs3_busy_0 = io_ren_uops_0_bits_prs3_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_prs3_busy_0 = io_ren_uops_0_bits_prs3_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_ppred_busy_0 = io_ren_uops_0_bits_ppred_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_ppred_busy_0 = io_ren_uops_0_bits_ppred_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_ppred_busy_0 = io_ren_uops_0_bits_ppred_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_ppred_busy_0 = io_ren_uops_0_bits_ppred_busy_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_3_0_bits_stale_pdst_0 = io_ren_uops_0_bits_stale_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_0_bits_stale_pdst_0 = io_ren_uops_0_bits_stale_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_0_bits_stale_pdst_0 = io_ren_uops_0_bits_stale_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_0_bits_stale_pdst_0 = io_ren_uops_0_bits_stale_pdst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_exception_0 = io_ren_uops_0_bits_exception_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_exception_0 = io_ren_uops_0_bits_exception_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_exception_0 = io_ren_uops_0_bits_exception_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_exception_0 = io_ren_uops_0_bits_exception_0; // @[dispatch.scala:43:7]
wire [63:0] io_dis_uops_3_0_bits_exc_cause_0 = io_ren_uops_0_bits_exc_cause_0; // @[dispatch.scala:43:7]
wire [63:0] io_dis_uops_2_0_bits_exc_cause_0 = io_ren_uops_0_bits_exc_cause_0; // @[dispatch.scala:43:7]
wire [63:0] io_dis_uops_1_0_bits_exc_cause_0 = io_ren_uops_0_bits_exc_cause_0; // @[dispatch.scala:43:7]
wire [63:0] io_dis_uops_0_0_bits_exc_cause_0 = io_ren_uops_0_bits_exc_cause_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_3_0_bits_mem_cmd_0 = io_ren_uops_0_bits_mem_cmd_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_0_bits_mem_cmd_0 = io_ren_uops_0_bits_mem_cmd_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_0_bits_mem_cmd_0 = io_ren_uops_0_bits_mem_cmd_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_0_bits_mem_cmd_0 = io_ren_uops_0_bits_mem_cmd_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_3_0_bits_mem_size_0 = io_ren_uops_0_bits_mem_size_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_0_bits_mem_size_0 = io_ren_uops_0_bits_mem_size_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_0_bits_mem_size_0 = io_ren_uops_0_bits_mem_size_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_0_bits_mem_size_0 = io_ren_uops_0_bits_mem_size_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_mem_signed_0 = io_ren_uops_0_bits_mem_signed_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_mem_signed_0 = io_ren_uops_0_bits_mem_signed_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_mem_signed_0 = io_ren_uops_0_bits_mem_signed_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_mem_signed_0 = io_ren_uops_0_bits_mem_signed_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_uses_ldq_0 = io_ren_uops_0_bits_uses_ldq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_uses_ldq_0 = io_ren_uops_0_bits_uses_ldq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_uses_ldq_0 = io_ren_uops_0_bits_uses_ldq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_uses_ldq_0 = io_ren_uops_0_bits_uses_ldq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_uses_stq_0 = io_ren_uops_0_bits_uses_stq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_uses_stq_0 = io_ren_uops_0_bits_uses_stq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_uses_stq_0 = io_ren_uops_0_bits_uses_stq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_uses_stq_0 = io_ren_uops_0_bits_uses_stq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_is_unique_0 = io_ren_uops_0_bits_is_unique_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_is_unique_0 = io_ren_uops_0_bits_is_unique_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_is_unique_0 = io_ren_uops_0_bits_is_unique_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_is_unique_0 = io_ren_uops_0_bits_is_unique_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_flush_on_commit_0 = io_ren_uops_0_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_flush_on_commit_0 = io_ren_uops_0_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_flush_on_commit_0 = io_ren_uops_0_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_flush_on_commit_0 = io_ren_uops_0_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_3_0_bits_csr_cmd_0 = io_ren_uops_0_bits_csr_cmd_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_0_bits_csr_cmd_0 = io_ren_uops_0_bits_csr_cmd_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_0_bits_csr_cmd_0 = io_ren_uops_0_bits_csr_cmd_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_0_bits_csr_cmd_0 = io_ren_uops_0_bits_csr_cmd_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_ldst_is_rs1_0 = io_ren_uops_0_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_ldst_is_rs1_0 = io_ren_uops_0_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_ldst_is_rs1_0 = io_ren_uops_0_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_ldst_is_rs1_0 = io_ren_uops_0_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_3_0_bits_ldst_0 = io_ren_uops_0_bits_ldst_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_2_0_bits_ldst_0 = io_ren_uops_0_bits_ldst_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_1_0_bits_ldst_0 = io_ren_uops_0_bits_ldst_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_0_0_bits_ldst_0 = io_ren_uops_0_bits_ldst_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_3_0_bits_lrs1_0 = io_ren_uops_0_bits_lrs1_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_2_0_bits_lrs1_0 = io_ren_uops_0_bits_lrs1_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_1_0_bits_lrs1_0 = io_ren_uops_0_bits_lrs1_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_0_0_bits_lrs1_0 = io_ren_uops_0_bits_lrs1_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_3_0_bits_lrs2_0 = io_ren_uops_0_bits_lrs2_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_2_0_bits_lrs2_0 = io_ren_uops_0_bits_lrs2_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_1_0_bits_lrs2_0 = io_ren_uops_0_bits_lrs2_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_0_0_bits_lrs2_0 = io_ren_uops_0_bits_lrs2_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_3_0_bits_lrs3_0 = io_ren_uops_0_bits_lrs3_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_2_0_bits_lrs3_0 = io_ren_uops_0_bits_lrs3_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_1_0_bits_lrs3_0 = io_ren_uops_0_bits_lrs3_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_0_0_bits_lrs3_0 = io_ren_uops_0_bits_lrs3_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_3_0_bits_dst_rtype_0 = io_ren_uops_0_bits_dst_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_0_bits_dst_rtype_0 = io_ren_uops_0_bits_dst_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_0_bits_dst_rtype_0 = io_ren_uops_0_bits_dst_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_0_bits_dst_rtype_0 = io_ren_uops_0_bits_dst_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_3_0_bits_lrs1_rtype_0 = io_ren_uops_0_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_0_bits_lrs1_rtype_0 = io_ren_uops_0_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_0_bits_lrs1_rtype_0 = io_ren_uops_0_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_0_bits_lrs1_rtype_0 = io_ren_uops_0_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_3_0_bits_lrs2_rtype_0 = io_ren_uops_0_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_0_bits_lrs2_rtype_0 = io_ren_uops_0_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_0_bits_lrs2_rtype_0 = io_ren_uops_0_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_0_bits_lrs2_rtype_0 = io_ren_uops_0_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_frs3_en_0 = io_ren_uops_0_bits_frs3_en_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_frs3_en_0 = io_ren_uops_0_bits_frs3_en_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_frs3_en_0 = io_ren_uops_0_bits_frs3_en_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_frs3_en_0 = io_ren_uops_0_bits_frs3_en_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_fcn_dw_0 = io_ren_uops_0_bits_fcn_dw_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_fcn_dw_0 = io_ren_uops_0_bits_fcn_dw_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_fcn_dw_0 = io_ren_uops_0_bits_fcn_dw_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_fcn_dw_0 = io_ren_uops_0_bits_fcn_dw_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_3_0_bits_fcn_op_0 = io_ren_uops_0_bits_fcn_op_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_0_bits_fcn_op_0 = io_ren_uops_0_bits_fcn_op_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_0_bits_fcn_op_0 = io_ren_uops_0_bits_fcn_op_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_0_bits_fcn_op_0 = io_ren_uops_0_bits_fcn_op_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_fp_val_0 = io_ren_uops_0_bits_fp_val_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_fp_val_0 = io_ren_uops_0_bits_fp_val_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_fp_val_0 = io_ren_uops_0_bits_fp_val_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_fp_val_0 = io_ren_uops_0_bits_fp_val_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_3_0_bits_fp_rm_0 = io_ren_uops_0_bits_fp_rm_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_0_bits_fp_rm_0 = io_ren_uops_0_bits_fp_rm_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_0_bits_fp_rm_0 = io_ren_uops_0_bits_fp_rm_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_0_bits_fp_rm_0 = io_ren_uops_0_bits_fp_rm_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_3_0_bits_fp_typ_0 = io_ren_uops_0_bits_fp_typ_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_0_bits_fp_typ_0 = io_ren_uops_0_bits_fp_typ_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_0_bits_fp_typ_0 = io_ren_uops_0_bits_fp_typ_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_0_bits_fp_typ_0 = io_ren_uops_0_bits_fp_typ_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_xcpt_pf_if_0 = io_ren_uops_0_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_xcpt_pf_if_0 = io_ren_uops_0_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_xcpt_pf_if_0 = io_ren_uops_0_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_xcpt_pf_if_0 = io_ren_uops_0_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_xcpt_ae_if_0 = io_ren_uops_0_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_xcpt_ae_if_0 = io_ren_uops_0_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_xcpt_ae_if_0 = io_ren_uops_0_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_xcpt_ae_if_0 = io_ren_uops_0_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_xcpt_ma_if_0 = io_ren_uops_0_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_xcpt_ma_if_0 = io_ren_uops_0_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_xcpt_ma_if_0 = io_ren_uops_0_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_xcpt_ma_if_0 = io_ren_uops_0_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_bp_debug_if_0 = io_ren_uops_0_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_bp_debug_if_0 = io_ren_uops_0_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_bp_debug_if_0 = io_ren_uops_0_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_bp_debug_if_0 = io_ren_uops_0_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_bits_bp_xcpt_if_0 = io_ren_uops_0_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_bits_bp_xcpt_if_0 = io_ren_uops_0_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_bits_bp_xcpt_if_0 = io_ren_uops_0_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_bits_bp_xcpt_if_0 = io_ren_uops_0_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_3_0_bits_debug_fsrc_0 = io_ren_uops_0_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_0_bits_debug_fsrc_0 = io_ren_uops_0_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_0_bits_debug_fsrc_0 = io_ren_uops_0_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_0_bits_debug_fsrc_0 = io_ren_uops_0_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_3_0_bits_debug_tsrc_0 = io_ren_uops_0_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_0_bits_debug_tsrc_0 = io_ren_uops_0_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_0_bits_debug_tsrc_0 = io_ren_uops_0_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_0_bits_debug_tsrc_0 = io_ren_uops_0_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
wire _io_ren_uops_1_ready_T; // @[dispatch.scala:50:39]
wire [31:0] io_dis_uops_3_1_bits_inst_0 = io_ren_uops_1_bits_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_2_1_bits_inst_0 = io_ren_uops_1_bits_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_1_1_bits_inst_0 = io_ren_uops_1_bits_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_0_1_bits_inst_0 = io_ren_uops_1_bits_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_3_1_bits_debug_inst_0 = io_ren_uops_1_bits_debug_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_2_1_bits_debug_inst_0 = io_ren_uops_1_bits_debug_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_1_1_bits_debug_inst_0 = io_ren_uops_1_bits_debug_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_0_1_bits_debug_inst_0 = io_ren_uops_1_bits_debug_inst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_is_rvc_0 = io_ren_uops_1_bits_is_rvc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_is_rvc_0 = io_ren_uops_1_bits_is_rvc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_is_rvc_0 = io_ren_uops_1_bits_is_rvc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_is_rvc_0 = io_ren_uops_1_bits_is_rvc_0; // @[dispatch.scala:43:7]
wire [39:0] io_dis_uops_3_1_bits_debug_pc_0 = io_ren_uops_1_bits_debug_pc_0; // @[dispatch.scala:43:7]
wire [39:0] io_dis_uops_2_1_bits_debug_pc_0 = io_ren_uops_1_bits_debug_pc_0; // @[dispatch.scala:43:7]
wire [39:0] io_dis_uops_1_1_bits_debug_pc_0 = io_ren_uops_1_bits_debug_pc_0; // @[dispatch.scala:43:7]
wire [39:0] io_dis_uops_0_1_bits_debug_pc_0 = io_ren_uops_1_bits_debug_pc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_iq_type_0_0 = io_ren_uops_1_bits_iq_type_0_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_iq_type_0_0 = io_ren_uops_1_bits_iq_type_0_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_iq_type_0_0 = io_ren_uops_1_bits_iq_type_0_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_iq_type_0_0 = io_ren_uops_1_bits_iq_type_0_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_iq_type_1_0 = io_ren_uops_1_bits_iq_type_1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_iq_type_1_0 = io_ren_uops_1_bits_iq_type_1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_iq_type_1_0 = io_ren_uops_1_bits_iq_type_1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_iq_type_1_0 = io_ren_uops_1_bits_iq_type_1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_iq_type_2_0 = io_ren_uops_1_bits_iq_type_2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_iq_type_2_0 = io_ren_uops_1_bits_iq_type_2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_iq_type_2_0 = io_ren_uops_1_bits_iq_type_2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_iq_type_2_0 = io_ren_uops_1_bits_iq_type_2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_iq_type_3_0 = io_ren_uops_1_bits_iq_type_3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_iq_type_3_0 = io_ren_uops_1_bits_iq_type_3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_iq_type_3_0 = io_ren_uops_1_bits_iq_type_3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_iq_type_3_0 = io_ren_uops_1_bits_iq_type_3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_fu_code_0_0 = io_ren_uops_1_bits_fu_code_0_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_fu_code_0_0 = io_ren_uops_1_bits_fu_code_0_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_fu_code_0_0 = io_ren_uops_1_bits_fu_code_0_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_fu_code_0_0 = io_ren_uops_1_bits_fu_code_0_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_fu_code_1_0 = io_ren_uops_1_bits_fu_code_1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_fu_code_1_0 = io_ren_uops_1_bits_fu_code_1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_fu_code_1_0 = io_ren_uops_1_bits_fu_code_1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_fu_code_1_0 = io_ren_uops_1_bits_fu_code_1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_fu_code_2_0 = io_ren_uops_1_bits_fu_code_2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_fu_code_2_0 = io_ren_uops_1_bits_fu_code_2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_fu_code_2_0 = io_ren_uops_1_bits_fu_code_2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_fu_code_2_0 = io_ren_uops_1_bits_fu_code_2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_fu_code_3_0 = io_ren_uops_1_bits_fu_code_3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_fu_code_3_0 = io_ren_uops_1_bits_fu_code_3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_fu_code_3_0 = io_ren_uops_1_bits_fu_code_3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_fu_code_3_0 = io_ren_uops_1_bits_fu_code_3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_fu_code_4_0 = io_ren_uops_1_bits_fu_code_4_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_fu_code_4_0 = io_ren_uops_1_bits_fu_code_4_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_fu_code_4_0 = io_ren_uops_1_bits_fu_code_4_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_fu_code_4_0 = io_ren_uops_1_bits_fu_code_4_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_fu_code_5_0 = io_ren_uops_1_bits_fu_code_5_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_fu_code_5_0 = io_ren_uops_1_bits_fu_code_5_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_fu_code_5_0 = io_ren_uops_1_bits_fu_code_5_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_fu_code_5_0 = io_ren_uops_1_bits_fu_code_5_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_fu_code_6_0 = io_ren_uops_1_bits_fu_code_6_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_fu_code_6_0 = io_ren_uops_1_bits_fu_code_6_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_fu_code_6_0 = io_ren_uops_1_bits_fu_code_6_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_fu_code_6_0 = io_ren_uops_1_bits_fu_code_6_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_fu_code_7_0 = io_ren_uops_1_bits_fu_code_7_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_fu_code_7_0 = io_ren_uops_1_bits_fu_code_7_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_fu_code_7_0 = io_ren_uops_1_bits_fu_code_7_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_fu_code_7_0 = io_ren_uops_1_bits_fu_code_7_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_fu_code_8_0 = io_ren_uops_1_bits_fu_code_8_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_fu_code_8_0 = io_ren_uops_1_bits_fu_code_8_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_fu_code_8_0 = io_ren_uops_1_bits_fu_code_8_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_fu_code_8_0 = io_ren_uops_1_bits_fu_code_8_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_fu_code_9_0 = io_ren_uops_1_bits_fu_code_9_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_fu_code_9_0 = io_ren_uops_1_bits_fu_code_9_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_fu_code_9_0 = io_ren_uops_1_bits_fu_code_9_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_fu_code_9_0 = io_ren_uops_1_bits_fu_code_9_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_iw_issued_0 = io_ren_uops_1_bits_iw_issued_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_iw_issued_0 = io_ren_uops_1_bits_iw_issued_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_iw_issued_0 = io_ren_uops_1_bits_iw_issued_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_iw_issued_0 = io_ren_uops_1_bits_iw_issued_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_iw_issued_partial_agen_0 = io_ren_uops_1_bits_iw_issued_partial_agen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_iw_issued_partial_agen_0 = io_ren_uops_1_bits_iw_issued_partial_agen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_iw_issued_partial_agen_0 = io_ren_uops_1_bits_iw_issued_partial_agen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_iw_issued_partial_agen_0 = io_ren_uops_1_bits_iw_issued_partial_agen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_iw_issued_partial_dgen_0 = io_ren_uops_1_bits_iw_issued_partial_dgen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_iw_issued_partial_dgen_0 = io_ren_uops_1_bits_iw_issued_partial_dgen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_iw_issued_partial_dgen_0 = io_ren_uops_1_bits_iw_issued_partial_dgen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_iw_issued_partial_dgen_0 = io_ren_uops_1_bits_iw_issued_partial_dgen_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_3_1_bits_iw_p1_speculative_child_0 = io_ren_uops_1_bits_iw_p1_speculative_child_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_1_bits_iw_p1_speculative_child_0 = io_ren_uops_1_bits_iw_p1_speculative_child_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_1_bits_iw_p1_speculative_child_0 = io_ren_uops_1_bits_iw_p1_speculative_child_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_1_bits_iw_p1_speculative_child_0 = io_ren_uops_1_bits_iw_p1_speculative_child_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_3_1_bits_iw_p2_speculative_child_0 = io_ren_uops_1_bits_iw_p2_speculative_child_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_1_bits_iw_p2_speculative_child_0 = io_ren_uops_1_bits_iw_p2_speculative_child_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_1_bits_iw_p2_speculative_child_0 = io_ren_uops_1_bits_iw_p2_speculative_child_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_1_bits_iw_p2_speculative_child_0 = io_ren_uops_1_bits_iw_p2_speculative_child_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_iw_p1_bypass_hint_0 = io_ren_uops_1_bits_iw_p1_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_iw_p1_bypass_hint_0 = io_ren_uops_1_bits_iw_p1_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_iw_p1_bypass_hint_0 = io_ren_uops_1_bits_iw_p1_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_iw_p1_bypass_hint_0 = io_ren_uops_1_bits_iw_p1_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_iw_p2_bypass_hint_0 = io_ren_uops_1_bits_iw_p2_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_iw_p2_bypass_hint_0 = io_ren_uops_1_bits_iw_p2_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_iw_p2_bypass_hint_0 = io_ren_uops_1_bits_iw_p2_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_iw_p2_bypass_hint_0 = io_ren_uops_1_bits_iw_p2_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_iw_p3_bypass_hint_0 = io_ren_uops_1_bits_iw_p3_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_iw_p3_bypass_hint_0 = io_ren_uops_1_bits_iw_p3_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_iw_p3_bypass_hint_0 = io_ren_uops_1_bits_iw_p3_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_iw_p3_bypass_hint_0 = io_ren_uops_1_bits_iw_p3_bypass_hint_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_3_1_bits_dis_col_sel_0 = io_ren_uops_1_bits_dis_col_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_1_bits_dis_col_sel_0 = io_ren_uops_1_bits_dis_col_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_1_bits_dis_col_sel_0 = io_ren_uops_1_bits_dis_col_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_1_bits_dis_col_sel_0 = io_ren_uops_1_bits_dis_col_sel_0; // @[dispatch.scala:43:7]
wire [15:0] io_dis_uops_3_1_bits_br_mask_0 = io_ren_uops_1_bits_br_mask_0; // @[dispatch.scala:43:7]
wire [15:0] io_dis_uops_2_1_bits_br_mask_0 = io_ren_uops_1_bits_br_mask_0; // @[dispatch.scala:43:7]
wire [15:0] io_dis_uops_1_1_bits_br_mask_0 = io_ren_uops_1_bits_br_mask_0; // @[dispatch.scala:43:7]
wire [15:0] io_dis_uops_0_1_bits_br_mask_0 = io_ren_uops_1_bits_br_mask_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_3_1_bits_br_tag_0 = io_ren_uops_1_bits_br_tag_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_2_1_bits_br_tag_0 = io_ren_uops_1_bits_br_tag_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_1_1_bits_br_tag_0 = io_ren_uops_1_bits_br_tag_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_0_1_bits_br_tag_0 = io_ren_uops_1_bits_br_tag_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_3_1_bits_br_type_0 = io_ren_uops_1_bits_br_type_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_2_1_bits_br_type_0 = io_ren_uops_1_bits_br_type_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_1_1_bits_br_type_0 = io_ren_uops_1_bits_br_type_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_0_1_bits_br_type_0 = io_ren_uops_1_bits_br_type_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_is_sfb_0 = io_ren_uops_1_bits_is_sfb_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_is_sfb_0 = io_ren_uops_1_bits_is_sfb_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_is_sfb_0 = io_ren_uops_1_bits_is_sfb_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_is_sfb_0 = io_ren_uops_1_bits_is_sfb_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_is_fence_0 = io_ren_uops_1_bits_is_fence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_is_fence_0 = io_ren_uops_1_bits_is_fence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_is_fence_0 = io_ren_uops_1_bits_is_fence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_is_fence_0 = io_ren_uops_1_bits_is_fence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_is_fencei_0 = io_ren_uops_1_bits_is_fencei_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_is_fencei_0 = io_ren_uops_1_bits_is_fencei_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_is_fencei_0 = io_ren_uops_1_bits_is_fencei_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_is_fencei_0 = io_ren_uops_1_bits_is_fencei_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_is_sfence_0 = io_ren_uops_1_bits_is_sfence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_is_sfence_0 = io_ren_uops_1_bits_is_sfence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_is_sfence_0 = io_ren_uops_1_bits_is_sfence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_is_sfence_0 = io_ren_uops_1_bits_is_sfence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_is_amo_0 = io_ren_uops_1_bits_is_amo_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_is_amo_0 = io_ren_uops_1_bits_is_amo_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_is_amo_0 = io_ren_uops_1_bits_is_amo_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_is_amo_0 = io_ren_uops_1_bits_is_amo_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_is_eret_0 = io_ren_uops_1_bits_is_eret_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_is_eret_0 = io_ren_uops_1_bits_is_eret_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_is_eret_0 = io_ren_uops_1_bits_is_eret_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_is_eret_0 = io_ren_uops_1_bits_is_eret_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_is_sys_pc2epc_0 = io_ren_uops_1_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_is_sys_pc2epc_0 = io_ren_uops_1_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_is_sys_pc2epc_0 = io_ren_uops_1_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_is_sys_pc2epc_0 = io_ren_uops_1_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_is_rocc_0 = io_ren_uops_1_bits_is_rocc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_is_rocc_0 = io_ren_uops_1_bits_is_rocc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_is_rocc_0 = io_ren_uops_1_bits_is_rocc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_is_rocc_0 = io_ren_uops_1_bits_is_rocc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_is_mov_0 = io_ren_uops_1_bits_is_mov_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_is_mov_0 = io_ren_uops_1_bits_is_mov_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_is_mov_0 = io_ren_uops_1_bits_is_mov_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_is_mov_0 = io_ren_uops_1_bits_is_mov_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_3_1_bits_ftq_idx_0 = io_ren_uops_1_bits_ftq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_1_bits_ftq_idx_0 = io_ren_uops_1_bits_ftq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_1_bits_ftq_idx_0 = io_ren_uops_1_bits_ftq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_1_bits_ftq_idx_0 = io_ren_uops_1_bits_ftq_idx_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_edge_inst_0 = io_ren_uops_1_bits_edge_inst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_edge_inst_0 = io_ren_uops_1_bits_edge_inst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_edge_inst_0 = io_ren_uops_1_bits_edge_inst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_edge_inst_0 = io_ren_uops_1_bits_edge_inst_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_3_1_bits_pc_lob_0 = io_ren_uops_1_bits_pc_lob_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_2_1_bits_pc_lob_0 = io_ren_uops_1_bits_pc_lob_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_1_1_bits_pc_lob_0 = io_ren_uops_1_bits_pc_lob_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_0_1_bits_pc_lob_0 = io_ren_uops_1_bits_pc_lob_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_taken_0 = io_ren_uops_1_bits_taken_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_taken_0 = io_ren_uops_1_bits_taken_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_taken_0 = io_ren_uops_1_bits_taken_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_taken_0 = io_ren_uops_1_bits_taken_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_imm_rename_0 = io_ren_uops_1_bits_imm_rename_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_imm_rename_0 = io_ren_uops_1_bits_imm_rename_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_imm_rename_0 = io_ren_uops_1_bits_imm_rename_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_imm_rename_0 = io_ren_uops_1_bits_imm_rename_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_3_1_bits_imm_sel_0 = io_ren_uops_1_bits_imm_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_1_bits_imm_sel_0 = io_ren_uops_1_bits_imm_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_1_bits_imm_sel_0 = io_ren_uops_1_bits_imm_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_1_bits_imm_sel_0 = io_ren_uops_1_bits_imm_sel_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_3_1_bits_pimm_0 = io_ren_uops_1_bits_pimm_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_1_bits_pimm_0 = io_ren_uops_1_bits_pimm_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_1_bits_pimm_0 = io_ren_uops_1_bits_pimm_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_1_bits_pimm_0 = io_ren_uops_1_bits_pimm_0; // @[dispatch.scala:43:7]
wire [19:0] io_dis_uops_3_1_bits_imm_packed_0 = io_ren_uops_1_bits_imm_packed_0; // @[dispatch.scala:43:7]
wire [19:0] io_dis_uops_2_1_bits_imm_packed_0 = io_ren_uops_1_bits_imm_packed_0; // @[dispatch.scala:43:7]
wire [19:0] io_dis_uops_1_1_bits_imm_packed_0 = io_ren_uops_1_bits_imm_packed_0; // @[dispatch.scala:43:7]
wire [19:0] io_dis_uops_0_1_bits_imm_packed_0 = io_ren_uops_1_bits_imm_packed_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_3_1_bits_op1_sel_0 = io_ren_uops_1_bits_op1_sel_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_1_bits_op1_sel_0 = io_ren_uops_1_bits_op1_sel_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_1_bits_op1_sel_0 = io_ren_uops_1_bits_op1_sel_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_1_bits_op1_sel_0 = io_ren_uops_1_bits_op1_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_3_1_bits_op2_sel_0 = io_ren_uops_1_bits_op2_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_1_bits_op2_sel_0 = io_ren_uops_1_bits_op2_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_1_bits_op2_sel_0 = io_ren_uops_1_bits_op2_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_1_bits_op2_sel_0 = io_ren_uops_1_bits_op2_sel_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_fp_ctrl_ldst_0 = io_ren_uops_1_bits_fp_ctrl_ldst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_fp_ctrl_ldst_0 = io_ren_uops_1_bits_fp_ctrl_ldst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_fp_ctrl_ldst_0 = io_ren_uops_1_bits_fp_ctrl_ldst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_fp_ctrl_ldst_0 = io_ren_uops_1_bits_fp_ctrl_ldst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_fp_ctrl_wen_0 = io_ren_uops_1_bits_fp_ctrl_wen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_fp_ctrl_wen_0 = io_ren_uops_1_bits_fp_ctrl_wen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_fp_ctrl_wen_0 = io_ren_uops_1_bits_fp_ctrl_wen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_fp_ctrl_wen_0 = io_ren_uops_1_bits_fp_ctrl_wen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_fp_ctrl_ren1_0 = io_ren_uops_1_bits_fp_ctrl_ren1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_fp_ctrl_ren1_0 = io_ren_uops_1_bits_fp_ctrl_ren1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_fp_ctrl_ren1_0 = io_ren_uops_1_bits_fp_ctrl_ren1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_fp_ctrl_ren1_0 = io_ren_uops_1_bits_fp_ctrl_ren1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_fp_ctrl_ren2_0 = io_ren_uops_1_bits_fp_ctrl_ren2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_fp_ctrl_ren2_0 = io_ren_uops_1_bits_fp_ctrl_ren2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_fp_ctrl_ren2_0 = io_ren_uops_1_bits_fp_ctrl_ren2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_fp_ctrl_ren2_0 = io_ren_uops_1_bits_fp_ctrl_ren2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_fp_ctrl_ren3_0 = io_ren_uops_1_bits_fp_ctrl_ren3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_fp_ctrl_ren3_0 = io_ren_uops_1_bits_fp_ctrl_ren3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_fp_ctrl_ren3_0 = io_ren_uops_1_bits_fp_ctrl_ren3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_fp_ctrl_ren3_0 = io_ren_uops_1_bits_fp_ctrl_ren3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_fp_ctrl_swap12_0 = io_ren_uops_1_bits_fp_ctrl_swap12_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_fp_ctrl_swap12_0 = io_ren_uops_1_bits_fp_ctrl_swap12_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_fp_ctrl_swap12_0 = io_ren_uops_1_bits_fp_ctrl_swap12_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_fp_ctrl_swap12_0 = io_ren_uops_1_bits_fp_ctrl_swap12_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_fp_ctrl_swap23_0 = io_ren_uops_1_bits_fp_ctrl_swap23_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_fp_ctrl_swap23_0 = io_ren_uops_1_bits_fp_ctrl_swap23_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_fp_ctrl_swap23_0 = io_ren_uops_1_bits_fp_ctrl_swap23_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_fp_ctrl_swap23_0 = io_ren_uops_1_bits_fp_ctrl_swap23_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_3_1_bits_fp_ctrl_typeTagIn_0 = io_ren_uops_1_bits_fp_ctrl_typeTagIn_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_1_bits_fp_ctrl_typeTagIn_0 = io_ren_uops_1_bits_fp_ctrl_typeTagIn_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_1_bits_fp_ctrl_typeTagIn_0 = io_ren_uops_1_bits_fp_ctrl_typeTagIn_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_1_bits_fp_ctrl_typeTagIn_0 = io_ren_uops_1_bits_fp_ctrl_typeTagIn_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_3_1_bits_fp_ctrl_typeTagOut_0 = io_ren_uops_1_bits_fp_ctrl_typeTagOut_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_1_bits_fp_ctrl_typeTagOut_0 = io_ren_uops_1_bits_fp_ctrl_typeTagOut_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_1_bits_fp_ctrl_typeTagOut_0 = io_ren_uops_1_bits_fp_ctrl_typeTagOut_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_1_bits_fp_ctrl_typeTagOut_0 = io_ren_uops_1_bits_fp_ctrl_typeTagOut_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_fp_ctrl_fromint_0 = io_ren_uops_1_bits_fp_ctrl_fromint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_fp_ctrl_fromint_0 = io_ren_uops_1_bits_fp_ctrl_fromint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_fp_ctrl_fromint_0 = io_ren_uops_1_bits_fp_ctrl_fromint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_fp_ctrl_fromint_0 = io_ren_uops_1_bits_fp_ctrl_fromint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_fp_ctrl_toint_0 = io_ren_uops_1_bits_fp_ctrl_toint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_fp_ctrl_toint_0 = io_ren_uops_1_bits_fp_ctrl_toint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_fp_ctrl_toint_0 = io_ren_uops_1_bits_fp_ctrl_toint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_fp_ctrl_toint_0 = io_ren_uops_1_bits_fp_ctrl_toint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_fp_ctrl_fastpipe_0 = io_ren_uops_1_bits_fp_ctrl_fastpipe_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_fp_ctrl_fastpipe_0 = io_ren_uops_1_bits_fp_ctrl_fastpipe_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_fp_ctrl_fastpipe_0 = io_ren_uops_1_bits_fp_ctrl_fastpipe_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_fp_ctrl_fastpipe_0 = io_ren_uops_1_bits_fp_ctrl_fastpipe_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_fp_ctrl_fma_0 = io_ren_uops_1_bits_fp_ctrl_fma_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_fp_ctrl_fma_0 = io_ren_uops_1_bits_fp_ctrl_fma_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_fp_ctrl_fma_0 = io_ren_uops_1_bits_fp_ctrl_fma_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_fp_ctrl_fma_0 = io_ren_uops_1_bits_fp_ctrl_fma_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_fp_ctrl_div_0 = io_ren_uops_1_bits_fp_ctrl_div_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_fp_ctrl_div_0 = io_ren_uops_1_bits_fp_ctrl_div_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_fp_ctrl_div_0 = io_ren_uops_1_bits_fp_ctrl_div_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_fp_ctrl_div_0 = io_ren_uops_1_bits_fp_ctrl_div_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_fp_ctrl_sqrt_0 = io_ren_uops_1_bits_fp_ctrl_sqrt_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_fp_ctrl_sqrt_0 = io_ren_uops_1_bits_fp_ctrl_sqrt_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_fp_ctrl_sqrt_0 = io_ren_uops_1_bits_fp_ctrl_sqrt_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_fp_ctrl_sqrt_0 = io_ren_uops_1_bits_fp_ctrl_sqrt_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_fp_ctrl_wflags_0 = io_ren_uops_1_bits_fp_ctrl_wflags_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_fp_ctrl_wflags_0 = io_ren_uops_1_bits_fp_ctrl_wflags_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_fp_ctrl_wflags_0 = io_ren_uops_1_bits_fp_ctrl_wflags_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_fp_ctrl_wflags_0 = io_ren_uops_1_bits_fp_ctrl_wflags_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_fp_ctrl_vec_0 = io_ren_uops_1_bits_fp_ctrl_vec_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_fp_ctrl_vec_0 = io_ren_uops_1_bits_fp_ctrl_vec_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_fp_ctrl_vec_0 = io_ren_uops_1_bits_fp_ctrl_vec_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_fp_ctrl_vec_0 = io_ren_uops_1_bits_fp_ctrl_vec_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_3_1_bits_rob_idx_0 = io_ren_uops_1_bits_rob_idx_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_1_bits_rob_idx_0 = io_ren_uops_1_bits_rob_idx_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_1_bits_rob_idx_0 = io_ren_uops_1_bits_rob_idx_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_1_bits_rob_idx_0 = io_ren_uops_1_bits_rob_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_3_1_bits_ldq_idx_0 = io_ren_uops_1_bits_ldq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_1_bits_ldq_idx_0 = io_ren_uops_1_bits_ldq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_1_bits_ldq_idx_0 = io_ren_uops_1_bits_ldq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_1_bits_ldq_idx_0 = io_ren_uops_1_bits_ldq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_3_1_bits_stq_idx_0 = io_ren_uops_1_bits_stq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_1_bits_stq_idx_0 = io_ren_uops_1_bits_stq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_1_bits_stq_idx_0 = io_ren_uops_1_bits_stq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_1_bits_stq_idx_0 = io_ren_uops_1_bits_stq_idx_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_3_1_bits_rxq_idx_0 = io_ren_uops_1_bits_rxq_idx_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_1_bits_rxq_idx_0 = io_ren_uops_1_bits_rxq_idx_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_1_bits_rxq_idx_0 = io_ren_uops_1_bits_rxq_idx_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_1_bits_rxq_idx_0 = io_ren_uops_1_bits_rxq_idx_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_3_1_bits_pdst_0 = io_ren_uops_1_bits_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_1_bits_pdst_0 = io_ren_uops_1_bits_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_1_bits_pdst_0 = io_ren_uops_1_bits_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_1_bits_pdst_0 = io_ren_uops_1_bits_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_3_1_bits_prs1_0 = io_ren_uops_1_bits_prs1_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_1_bits_prs1_0 = io_ren_uops_1_bits_prs1_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_1_bits_prs1_0 = io_ren_uops_1_bits_prs1_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_1_bits_prs1_0 = io_ren_uops_1_bits_prs1_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_3_1_bits_prs2_0 = io_ren_uops_1_bits_prs2_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_1_bits_prs2_0 = io_ren_uops_1_bits_prs2_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_1_bits_prs2_0 = io_ren_uops_1_bits_prs2_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_1_bits_prs2_0 = io_ren_uops_1_bits_prs2_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_3_1_bits_prs3_0 = io_ren_uops_1_bits_prs3_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_1_bits_prs3_0 = io_ren_uops_1_bits_prs3_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_1_bits_prs3_0 = io_ren_uops_1_bits_prs3_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_1_bits_prs3_0 = io_ren_uops_1_bits_prs3_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_3_1_bits_ppred_0 = io_ren_uops_1_bits_ppred_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_1_bits_ppred_0 = io_ren_uops_1_bits_ppred_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_1_bits_ppred_0 = io_ren_uops_1_bits_ppred_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_1_bits_ppred_0 = io_ren_uops_1_bits_ppred_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_prs1_busy_0 = io_ren_uops_1_bits_prs1_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_prs1_busy_0 = io_ren_uops_1_bits_prs1_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_prs1_busy_0 = io_ren_uops_1_bits_prs1_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_prs1_busy_0 = io_ren_uops_1_bits_prs1_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_prs2_busy_0 = io_ren_uops_1_bits_prs2_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_prs2_busy_0 = io_ren_uops_1_bits_prs2_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_prs2_busy_0 = io_ren_uops_1_bits_prs2_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_prs2_busy_0 = io_ren_uops_1_bits_prs2_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_prs3_busy_0 = io_ren_uops_1_bits_prs3_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_prs3_busy_0 = io_ren_uops_1_bits_prs3_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_prs3_busy_0 = io_ren_uops_1_bits_prs3_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_prs3_busy_0 = io_ren_uops_1_bits_prs3_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_ppred_busy_0 = io_ren_uops_1_bits_ppred_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_ppred_busy_0 = io_ren_uops_1_bits_ppred_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_ppred_busy_0 = io_ren_uops_1_bits_ppred_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_ppred_busy_0 = io_ren_uops_1_bits_ppred_busy_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_3_1_bits_stale_pdst_0 = io_ren_uops_1_bits_stale_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_1_bits_stale_pdst_0 = io_ren_uops_1_bits_stale_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_1_bits_stale_pdst_0 = io_ren_uops_1_bits_stale_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_1_bits_stale_pdst_0 = io_ren_uops_1_bits_stale_pdst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_exception_0 = io_ren_uops_1_bits_exception_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_exception_0 = io_ren_uops_1_bits_exception_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_exception_0 = io_ren_uops_1_bits_exception_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_exception_0 = io_ren_uops_1_bits_exception_0; // @[dispatch.scala:43:7]
wire [63:0] io_dis_uops_3_1_bits_exc_cause_0 = io_ren_uops_1_bits_exc_cause_0; // @[dispatch.scala:43:7]
wire [63:0] io_dis_uops_2_1_bits_exc_cause_0 = io_ren_uops_1_bits_exc_cause_0; // @[dispatch.scala:43:7]
wire [63:0] io_dis_uops_1_1_bits_exc_cause_0 = io_ren_uops_1_bits_exc_cause_0; // @[dispatch.scala:43:7]
wire [63:0] io_dis_uops_0_1_bits_exc_cause_0 = io_ren_uops_1_bits_exc_cause_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_3_1_bits_mem_cmd_0 = io_ren_uops_1_bits_mem_cmd_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_1_bits_mem_cmd_0 = io_ren_uops_1_bits_mem_cmd_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_1_bits_mem_cmd_0 = io_ren_uops_1_bits_mem_cmd_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_1_bits_mem_cmd_0 = io_ren_uops_1_bits_mem_cmd_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_3_1_bits_mem_size_0 = io_ren_uops_1_bits_mem_size_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_1_bits_mem_size_0 = io_ren_uops_1_bits_mem_size_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_1_bits_mem_size_0 = io_ren_uops_1_bits_mem_size_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_1_bits_mem_size_0 = io_ren_uops_1_bits_mem_size_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_mem_signed_0 = io_ren_uops_1_bits_mem_signed_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_mem_signed_0 = io_ren_uops_1_bits_mem_signed_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_mem_signed_0 = io_ren_uops_1_bits_mem_signed_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_mem_signed_0 = io_ren_uops_1_bits_mem_signed_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_uses_ldq_0 = io_ren_uops_1_bits_uses_ldq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_uses_ldq_0 = io_ren_uops_1_bits_uses_ldq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_uses_ldq_0 = io_ren_uops_1_bits_uses_ldq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_uses_ldq_0 = io_ren_uops_1_bits_uses_ldq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_uses_stq_0 = io_ren_uops_1_bits_uses_stq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_uses_stq_0 = io_ren_uops_1_bits_uses_stq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_uses_stq_0 = io_ren_uops_1_bits_uses_stq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_uses_stq_0 = io_ren_uops_1_bits_uses_stq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_is_unique_0 = io_ren_uops_1_bits_is_unique_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_is_unique_0 = io_ren_uops_1_bits_is_unique_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_is_unique_0 = io_ren_uops_1_bits_is_unique_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_is_unique_0 = io_ren_uops_1_bits_is_unique_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_flush_on_commit_0 = io_ren_uops_1_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_flush_on_commit_0 = io_ren_uops_1_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_flush_on_commit_0 = io_ren_uops_1_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_flush_on_commit_0 = io_ren_uops_1_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_3_1_bits_csr_cmd_0 = io_ren_uops_1_bits_csr_cmd_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_1_bits_csr_cmd_0 = io_ren_uops_1_bits_csr_cmd_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_1_bits_csr_cmd_0 = io_ren_uops_1_bits_csr_cmd_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_1_bits_csr_cmd_0 = io_ren_uops_1_bits_csr_cmd_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_ldst_is_rs1_0 = io_ren_uops_1_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_ldst_is_rs1_0 = io_ren_uops_1_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_ldst_is_rs1_0 = io_ren_uops_1_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_ldst_is_rs1_0 = io_ren_uops_1_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_3_1_bits_ldst_0 = io_ren_uops_1_bits_ldst_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_2_1_bits_ldst_0 = io_ren_uops_1_bits_ldst_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_1_1_bits_ldst_0 = io_ren_uops_1_bits_ldst_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_0_1_bits_ldst_0 = io_ren_uops_1_bits_ldst_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_3_1_bits_lrs1_0 = io_ren_uops_1_bits_lrs1_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_2_1_bits_lrs1_0 = io_ren_uops_1_bits_lrs1_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_1_1_bits_lrs1_0 = io_ren_uops_1_bits_lrs1_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_0_1_bits_lrs1_0 = io_ren_uops_1_bits_lrs1_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_3_1_bits_lrs2_0 = io_ren_uops_1_bits_lrs2_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_2_1_bits_lrs2_0 = io_ren_uops_1_bits_lrs2_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_1_1_bits_lrs2_0 = io_ren_uops_1_bits_lrs2_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_0_1_bits_lrs2_0 = io_ren_uops_1_bits_lrs2_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_3_1_bits_lrs3_0 = io_ren_uops_1_bits_lrs3_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_2_1_bits_lrs3_0 = io_ren_uops_1_bits_lrs3_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_1_1_bits_lrs3_0 = io_ren_uops_1_bits_lrs3_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_0_1_bits_lrs3_0 = io_ren_uops_1_bits_lrs3_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_3_1_bits_dst_rtype_0 = io_ren_uops_1_bits_dst_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_1_bits_dst_rtype_0 = io_ren_uops_1_bits_dst_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_1_bits_dst_rtype_0 = io_ren_uops_1_bits_dst_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_1_bits_dst_rtype_0 = io_ren_uops_1_bits_dst_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_3_1_bits_lrs1_rtype_0 = io_ren_uops_1_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_1_bits_lrs1_rtype_0 = io_ren_uops_1_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_1_bits_lrs1_rtype_0 = io_ren_uops_1_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_1_bits_lrs1_rtype_0 = io_ren_uops_1_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_3_1_bits_lrs2_rtype_0 = io_ren_uops_1_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_1_bits_lrs2_rtype_0 = io_ren_uops_1_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_1_bits_lrs2_rtype_0 = io_ren_uops_1_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_1_bits_lrs2_rtype_0 = io_ren_uops_1_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_frs3_en_0 = io_ren_uops_1_bits_frs3_en_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_frs3_en_0 = io_ren_uops_1_bits_frs3_en_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_frs3_en_0 = io_ren_uops_1_bits_frs3_en_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_frs3_en_0 = io_ren_uops_1_bits_frs3_en_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_fcn_dw_0 = io_ren_uops_1_bits_fcn_dw_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_fcn_dw_0 = io_ren_uops_1_bits_fcn_dw_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_fcn_dw_0 = io_ren_uops_1_bits_fcn_dw_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_fcn_dw_0 = io_ren_uops_1_bits_fcn_dw_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_3_1_bits_fcn_op_0 = io_ren_uops_1_bits_fcn_op_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_1_bits_fcn_op_0 = io_ren_uops_1_bits_fcn_op_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_1_bits_fcn_op_0 = io_ren_uops_1_bits_fcn_op_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_1_bits_fcn_op_0 = io_ren_uops_1_bits_fcn_op_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_fp_val_0 = io_ren_uops_1_bits_fp_val_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_fp_val_0 = io_ren_uops_1_bits_fp_val_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_fp_val_0 = io_ren_uops_1_bits_fp_val_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_fp_val_0 = io_ren_uops_1_bits_fp_val_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_3_1_bits_fp_rm_0 = io_ren_uops_1_bits_fp_rm_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_1_bits_fp_rm_0 = io_ren_uops_1_bits_fp_rm_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_1_bits_fp_rm_0 = io_ren_uops_1_bits_fp_rm_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_1_bits_fp_rm_0 = io_ren_uops_1_bits_fp_rm_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_3_1_bits_fp_typ_0 = io_ren_uops_1_bits_fp_typ_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_1_bits_fp_typ_0 = io_ren_uops_1_bits_fp_typ_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_1_bits_fp_typ_0 = io_ren_uops_1_bits_fp_typ_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_1_bits_fp_typ_0 = io_ren_uops_1_bits_fp_typ_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_xcpt_pf_if_0 = io_ren_uops_1_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_xcpt_pf_if_0 = io_ren_uops_1_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_xcpt_pf_if_0 = io_ren_uops_1_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_xcpt_pf_if_0 = io_ren_uops_1_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_xcpt_ae_if_0 = io_ren_uops_1_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_xcpt_ae_if_0 = io_ren_uops_1_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_xcpt_ae_if_0 = io_ren_uops_1_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_xcpt_ae_if_0 = io_ren_uops_1_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_xcpt_ma_if_0 = io_ren_uops_1_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_xcpt_ma_if_0 = io_ren_uops_1_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_xcpt_ma_if_0 = io_ren_uops_1_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_xcpt_ma_if_0 = io_ren_uops_1_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_bp_debug_if_0 = io_ren_uops_1_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_bp_debug_if_0 = io_ren_uops_1_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_bp_debug_if_0 = io_ren_uops_1_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_bp_debug_if_0 = io_ren_uops_1_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_bits_bp_xcpt_if_0 = io_ren_uops_1_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_bits_bp_xcpt_if_0 = io_ren_uops_1_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_bits_bp_xcpt_if_0 = io_ren_uops_1_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_bits_bp_xcpt_if_0 = io_ren_uops_1_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_3_1_bits_debug_fsrc_0 = io_ren_uops_1_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_1_bits_debug_fsrc_0 = io_ren_uops_1_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_1_bits_debug_fsrc_0 = io_ren_uops_1_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_1_bits_debug_fsrc_0 = io_ren_uops_1_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_3_1_bits_debug_tsrc_0 = io_ren_uops_1_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_1_bits_debug_tsrc_0 = io_ren_uops_1_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_1_bits_debug_tsrc_0 = io_ren_uops_1_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_1_bits_debug_tsrc_0 = io_ren_uops_1_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
wire _io_ren_uops_2_ready_T; // @[dispatch.scala:50:39]
wire [31:0] io_dis_uops_3_2_bits_inst_0 = io_ren_uops_2_bits_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_2_2_bits_inst_0 = io_ren_uops_2_bits_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_1_2_bits_inst_0 = io_ren_uops_2_bits_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_0_2_bits_inst_0 = io_ren_uops_2_bits_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_3_2_bits_debug_inst_0 = io_ren_uops_2_bits_debug_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_2_2_bits_debug_inst_0 = io_ren_uops_2_bits_debug_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_1_2_bits_debug_inst_0 = io_ren_uops_2_bits_debug_inst_0; // @[dispatch.scala:43:7]
wire [31:0] io_dis_uops_0_2_bits_debug_inst_0 = io_ren_uops_2_bits_debug_inst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_is_rvc_0 = io_ren_uops_2_bits_is_rvc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_is_rvc_0 = io_ren_uops_2_bits_is_rvc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_is_rvc_0 = io_ren_uops_2_bits_is_rvc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_is_rvc_0 = io_ren_uops_2_bits_is_rvc_0; // @[dispatch.scala:43:7]
wire [39:0] io_dis_uops_3_2_bits_debug_pc_0 = io_ren_uops_2_bits_debug_pc_0; // @[dispatch.scala:43:7]
wire [39:0] io_dis_uops_2_2_bits_debug_pc_0 = io_ren_uops_2_bits_debug_pc_0; // @[dispatch.scala:43:7]
wire [39:0] io_dis_uops_1_2_bits_debug_pc_0 = io_ren_uops_2_bits_debug_pc_0; // @[dispatch.scala:43:7]
wire [39:0] io_dis_uops_0_2_bits_debug_pc_0 = io_ren_uops_2_bits_debug_pc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_iq_type_0_0 = io_ren_uops_2_bits_iq_type_0_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_iq_type_0_0 = io_ren_uops_2_bits_iq_type_0_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_iq_type_0_0 = io_ren_uops_2_bits_iq_type_0_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_iq_type_0_0 = io_ren_uops_2_bits_iq_type_0_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_iq_type_1_0 = io_ren_uops_2_bits_iq_type_1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_iq_type_1_0 = io_ren_uops_2_bits_iq_type_1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_iq_type_1_0 = io_ren_uops_2_bits_iq_type_1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_iq_type_1_0 = io_ren_uops_2_bits_iq_type_1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_iq_type_2_0 = io_ren_uops_2_bits_iq_type_2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_iq_type_2_0 = io_ren_uops_2_bits_iq_type_2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_iq_type_2_0 = io_ren_uops_2_bits_iq_type_2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_iq_type_2_0 = io_ren_uops_2_bits_iq_type_2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_iq_type_3_0 = io_ren_uops_2_bits_iq_type_3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_iq_type_3_0 = io_ren_uops_2_bits_iq_type_3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_iq_type_3_0 = io_ren_uops_2_bits_iq_type_3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_iq_type_3_0 = io_ren_uops_2_bits_iq_type_3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_fu_code_0_0 = io_ren_uops_2_bits_fu_code_0_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_fu_code_0_0 = io_ren_uops_2_bits_fu_code_0_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_fu_code_0_0 = io_ren_uops_2_bits_fu_code_0_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_fu_code_0_0 = io_ren_uops_2_bits_fu_code_0_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_fu_code_1_0 = io_ren_uops_2_bits_fu_code_1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_fu_code_1_0 = io_ren_uops_2_bits_fu_code_1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_fu_code_1_0 = io_ren_uops_2_bits_fu_code_1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_fu_code_1_0 = io_ren_uops_2_bits_fu_code_1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_fu_code_2_0 = io_ren_uops_2_bits_fu_code_2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_fu_code_2_0 = io_ren_uops_2_bits_fu_code_2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_fu_code_2_0 = io_ren_uops_2_bits_fu_code_2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_fu_code_2_0 = io_ren_uops_2_bits_fu_code_2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_fu_code_3_0 = io_ren_uops_2_bits_fu_code_3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_fu_code_3_0 = io_ren_uops_2_bits_fu_code_3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_fu_code_3_0 = io_ren_uops_2_bits_fu_code_3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_fu_code_3_0 = io_ren_uops_2_bits_fu_code_3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_fu_code_4_0 = io_ren_uops_2_bits_fu_code_4_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_fu_code_4_0 = io_ren_uops_2_bits_fu_code_4_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_fu_code_4_0 = io_ren_uops_2_bits_fu_code_4_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_fu_code_4_0 = io_ren_uops_2_bits_fu_code_4_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_fu_code_5_0 = io_ren_uops_2_bits_fu_code_5_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_fu_code_5_0 = io_ren_uops_2_bits_fu_code_5_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_fu_code_5_0 = io_ren_uops_2_bits_fu_code_5_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_fu_code_5_0 = io_ren_uops_2_bits_fu_code_5_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_fu_code_6_0 = io_ren_uops_2_bits_fu_code_6_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_fu_code_6_0 = io_ren_uops_2_bits_fu_code_6_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_fu_code_6_0 = io_ren_uops_2_bits_fu_code_6_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_fu_code_6_0 = io_ren_uops_2_bits_fu_code_6_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_fu_code_7_0 = io_ren_uops_2_bits_fu_code_7_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_fu_code_7_0 = io_ren_uops_2_bits_fu_code_7_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_fu_code_7_0 = io_ren_uops_2_bits_fu_code_7_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_fu_code_7_0 = io_ren_uops_2_bits_fu_code_7_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_fu_code_8_0 = io_ren_uops_2_bits_fu_code_8_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_fu_code_8_0 = io_ren_uops_2_bits_fu_code_8_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_fu_code_8_0 = io_ren_uops_2_bits_fu_code_8_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_fu_code_8_0 = io_ren_uops_2_bits_fu_code_8_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_fu_code_9_0 = io_ren_uops_2_bits_fu_code_9_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_fu_code_9_0 = io_ren_uops_2_bits_fu_code_9_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_fu_code_9_0 = io_ren_uops_2_bits_fu_code_9_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_fu_code_9_0 = io_ren_uops_2_bits_fu_code_9_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_iw_issued_0 = io_ren_uops_2_bits_iw_issued_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_iw_issued_0 = io_ren_uops_2_bits_iw_issued_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_iw_issued_0 = io_ren_uops_2_bits_iw_issued_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_iw_issued_0 = io_ren_uops_2_bits_iw_issued_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_iw_issued_partial_agen_0 = io_ren_uops_2_bits_iw_issued_partial_agen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_iw_issued_partial_agen_0 = io_ren_uops_2_bits_iw_issued_partial_agen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_iw_issued_partial_agen_0 = io_ren_uops_2_bits_iw_issued_partial_agen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_iw_issued_partial_agen_0 = io_ren_uops_2_bits_iw_issued_partial_agen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_iw_issued_partial_dgen_0 = io_ren_uops_2_bits_iw_issued_partial_dgen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_iw_issued_partial_dgen_0 = io_ren_uops_2_bits_iw_issued_partial_dgen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_iw_issued_partial_dgen_0 = io_ren_uops_2_bits_iw_issued_partial_dgen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_iw_issued_partial_dgen_0 = io_ren_uops_2_bits_iw_issued_partial_dgen_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_3_2_bits_iw_p1_speculative_child_0 = io_ren_uops_2_bits_iw_p1_speculative_child_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_2_bits_iw_p1_speculative_child_0 = io_ren_uops_2_bits_iw_p1_speculative_child_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_2_bits_iw_p1_speculative_child_0 = io_ren_uops_2_bits_iw_p1_speculative_child_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_2_bits_iw_p1_speculative_child_0 = io_ren_uops_2_bits_iw_p1_speculative_child_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_3_2_bits_iw_p2_speculative_child_0 = io_ren_uops_2_bits_iw_p2_speculative_child_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_2_bits_iw_p2_speculative_child_0 = io_ren_uops_2_bits_iw_p2_speculative_child_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_2_bits_iw_p2_speculative_child_0 = io_ren_uops_2_bits_iw_p2_speculative_child_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_2_bits_iw_p2_speculative_child_0 = io_ren_uops_2_bits_iw_p2_speculative_child_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_iw_p1_bypass_hint_0 = io_ren_uops_2_bits_iw_p1_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_iw_p1_bypass_hint_0 = io_ren_uops_2_bits_iw_p1_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_iw_p1_bypass_hint_0 = io_ren_uops_2_bits_iw_p1_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_iw_p1_bypass_hint_0 = io_ren_uops_2_bits_iw_p1_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_iw_p2_bypass_hint_0 = io_ren_uops_2_bits_iw_p2_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_iw_p2_bypass_hint_0 = io_ren_uops_2_bits_iw_p2_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_iw_p2_bypass_hint_0 = io_ren_uops_2_bits_iw_p2_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_iw_p2_bypass_hint_0 = io_ren_uops_2_bits_iw_p2_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_iw_p3_bypass_hint_0 = io_ren_uops_2_bits_iw_p3_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_iw_p3_bypass_hint_0 = io_ren_uops_2_bits_iw_p3_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_iw_p3_bypass_hint_0 = io_ren_uops_2_bits_iw_p3_bypass_hint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_iw_p3_bypass_hint_0 = io_ren_uops_2_bits_iw_p3_bypass_hint_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_3_2_bits_dis_col_sel_0 = io_ren_uops_2_bits_dis_col_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_2_bits_dis_col_sel_0 = io_ren_uops_2_bits_dis_col_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_2_bits_dis_col_sel_0 = io_ren_uops_2_bits_dis_col_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_2_bits_dis_col_sel_0 = io_ren_uops_2_bits_dis_col_sel_0; // @[dispatch.scala:43:7]
wire [15:0] io_dis_uops_3_2_bits_br_mask_0 = io_ren_uops_2_bits_br_mask_0; // @[dispatch.scala:43:7]
wire [15:0] io_dis_uops_2_2_bits_br_mask_0 = io_ren_uops_2_bits_br_mask_0; // @[dispatch.scala:43:7]
wire [15:0] io_dis_uops_1_2_bits_br_mask_0 = io_ren_uops_2_bits_br_mask_0; // @[dispatch.scala:43:7]
wire [15:0] io_dis_uops_0_2_bits_br_mask_0 = io_ren_uops_2_bits_br_mask_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_3_2_bits_br_tag_0 = io_ren_uops_2_bits_br_tag_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_2_2_bits_br_tag_0 = io_ren_uops_2_bits_br_tag_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_1_2_bits_br_tag_0 = io_ren_uops_2_bits_br_tag_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_0_2_bits_br_tag_0 = io_ren_uops_2_bits_br_tag_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_3_2_bits_br_type_0 = io_ren_uops_2_bits_br_type_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_2_2_bits_br_type_0 = io_ren_uops_2_bits_br_type_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_1_2_bits_br_type_0 = io_ren_uops_2_bits_br_type_0; // @[dispatch.scala:43:7]
wire [3:0] io_dis_uops_0_2_bits_br_type_0 = io_ren_uops_2_bits_br_type_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_is_sfb_0 = io_ren_uops_2_bits_is_sfb_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_is_sfb_0 = io_ren_uops_2_bits_is_sfb_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_is_sfb_0 = io_ren_uops_2_bits_is_sfb_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_is_sfb_0 = io_ren_uops_2_bits_is_sfb_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_is_fence_0 = io_ren_uops_2_bits_is_fence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_is_fence_0 = io_ren_uops_2_bits_is_fence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_is_fence_0 = io_ren_uops_2_bits_is_fence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_is_fence_0 = io_ren_uops_2_bits_is_fence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_is_fencei_0 = io_ren_uops_2_bits_is_fencei_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_is_fencei_0 = io_ren_uops_2_bits_is_fencei_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_is_fencei_0 = io_ren_uops_2_bits_is_fencei_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_is_fencei_0 = io_ren_uops_2_bits_is_fencei_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_is_sfence_0 = io_ren_uops_2_bits_is_sfence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_is_sfence_0 = io_ren_uops_2_bits_is_sfence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_is_sfence_0 = io_ren_uops_2_bits_is_sfence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_is_sfence_0 = io_ren_uops_2_bits_is_sfence_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_is_amo_0 = io_ren_uops_2_bits_is_amo_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_is_amo_0 = io_ren_uops_2_bits_is_amo_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_is_amo_0 = io_ren_uops_2_bits_is_amo_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_is_amo_0 = io_ren_uops_2_bits_is_amo_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_is_eret_0 = io_ren_uops_2_bits_is_eret_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_is_eret_0 = io_ren_uops_2_bits_is_eret_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_is_eret_0 = io_ren_uops_2_bits_is_eret_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_is_eret_0 = io_ren_uops_2_bits_is_eret_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_is_sys_pc2epc_0 = io_ren_uops_2_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_is_sys_pc2epc_0 = io_ren_uops_2_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_is_sys_pc2epc_0 = io_ren_uops_2_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_is_sys_pc2epc_0 = io_ren_uops_2_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_is_rocc_0 = io_ren_uops_2_bits_is_rocc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_is_rocc_0 = io_ren_uops_2_bits_is_rocc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_is_rocc_0 = io_ren_uops_2_bits_is_rocc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_is_rocc_0 = io_ren_uops_2_bits_is_rocc_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_is_mov_0 = io_ren_uops_2_bits_is_mov_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_is_mov_0 = io_ren_uops_2_bits_is_mov_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_is_mov_0 = io_ren_uops_2_bits_is_mov_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_is_mov_0 = io_ren_uops_2_bits_is_mov_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_3_2_bits_ftq_idx_0 = io_ren_uops_2_bits_ftq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_2_bits_ftq_idx_0 = io_ren_uops_2_bits_ftq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_2_bits_ftq_idx_0 = io_ren_uops_2_bits_ftq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_2_bits_ftq_idx_0 = io_ren_uops_2_bits_ftq_idx_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_edge_inst_0 = io_ren_uops_2_bits_edge_inst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_edge_inst_0 = io_ren_uops_2_bits_edge_inst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_edge_inst_0 = io_ren_uops_2_bits_edge_inst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_edge_inst_0 = io_ren_uops_2_bits_edge_inst_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_3_2_bits_pc_lob_0 = io_ren_uops_2_bits_pc_lob_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_2_2_bits_pc_lob_0 = io_ren_uops_2_bits_pc_lob_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_1_2_bits_pc_lob_0 = io_ren_uops_2_bits_pc_lob_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_0_2_bits_pc_lob_0 = io_ren_uops_2_bits_pc_lob_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_taken_0 = io_ren_uops_2_bits_taken_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_taken_0 = io_ren_uops_2_bits_taken_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_taken_0 = io_ren_uops_2_bits_taken_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_taken_0 = io_ren_uops_2_bits_taken_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_imm_rename_0 = io_ren_uops_2_bits_imm_rename_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_imm_rename_0 = io_ren_uops_2_bits_imm_rename_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_imm_rename_0 = io_ren_uops_2_bits_imm_rename_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_imm_rename_0 = io_ren_uops_2_bits_imm_rename_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_3_2_bits_imm_sel_0 = io_ren_uops_2_bits_imm_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_2_bits_imm_sel_0 = io_ren_uops_2_bits_imm_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_2_bits_imm_sel_0 = io_ren_uops_2_bits_imm_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_2_bits_imm_sel_0 = io_ren_uops_2_bits_imm_sel_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_3_2_bits_pimm_0 = io_ren_uops_2_bits_pimm_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_2_bits_pimm_0 = io_ren_uops_2_bits_pimm_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_2_bits_pimm_0 = io_ren_uops_2_bits_pimm_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_2_bits_pimm_0 = io_ren_uops_2_bits_pimm_0; // @[dispatch.scala:43:7]
wire [19:0] io_dis_uops_3_2_bits_imm_packed_0 = io_ren_uops_2_bits_imm_packed_0; // @[dispatch.scala:43:7]
wire [19:0] io_dis_uops_2_2_bits_imm_packed_0 = io_ren_uops_2_bits_imm_packed_0; // @[dispatch.scala:43:7]
wire [19:0] io_dis_uops_1_2_bits_imm_packed_0 = io_ren_uops_2_bits_imm_packed_0; // @[dispatch.scala:43:7]
wire [19:0] io_dis_uops_0_2_bits_imm_packed_0 = io_ren_uops_2_bits_imm_packed_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_3_2_bits_op1_sel_0 = io_ren_uops_2_bits_op1_sel_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_2_bits_op1_sel_0 = io_ren_uops_2_bits_op1_sel_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_2_bits_op1_sel_0 = io_ren_uops_2_bits_op1_sel_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_2_bits_op1_sel_0 = io_ren_uops_2_bits_op1_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_3_2_bits_op2_sel_0 = io_ren_uops_2_bits_op2_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_2_bits_op2_sel_0 = io_ren_uops_2_bits_op2_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_2_bits_op2_sel_0 = io_ren_uops_2_bits_op2_sel_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_2_bits_op2_sel_0 = io_ren_uops_2_bits_op2_sel_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_fp_ctrl_ldst_0 = io_ren_uops_2_bits_fp_ctrl_ldst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_fp_ctrl_ldst_0 = io_ren_uops_2_bits_fp_ctrl_ldst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_fp_ctrl_ldst_0 = io_ren_uops_2_bits_fp_ctrl_ldst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_fp_ctrl_ldst_0 = io_ren_uops_2_bits_fp_ctrl_ldst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_fp_ctrl_wen_0 = io_ren_uops_2_bits_fp_ctrl_wen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_fp_ctrl_wen_0 = io_ren_uops_2_bits_fp_ctrl_wen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_fp_ctrl_wen_0 = io_ren_uops_2_bits_fp_ctrl_wen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_fp_ctrl_wen_0 = io_ren_uops_2_bits_fp_ctrl_wen_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_fp_ctrl_ren1_0 = io_ren_uops_2_bits_fp_ctrl_ren1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_fp_ctrl_ren1_0 = io_ren_uops_2_bits_fp_ctrl_ren1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_fp_ctrl_ren1_0 = io_ren_uops_2_bits_fp_ctrl_ren1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_fp_ctrl_ren1_0 = io_ren_uops_2_bits_fp_ctrl_ren1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_fp_ctrl_ren2_0 = io_ren_uops_2_bits_fp_ctrl_ren2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_fp_ctrl_ren2_0 = io_ren_uops_2_bits_fp_ctrl_ren2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_fp_ctrl_ren2_0 = io_ren_uops_2_bits_fp_ctrl_ren2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_fp_ctrl_ren2_0 = io_ren_uops_2_bits_fp_ctrl_ren2_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_fp_ctrl_ren3_0 = io_ren_uops_2_bits_fp_ctrl_ren3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_fp_ctrl_ren3_0 = io_ren_uops_2_bits_fp_ctrl_ren3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_fp_ctrl_ren3_0 = io_ren_uops_2_bits_fp_ctrl_ren3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_fp_ctrl_ren3_0 = io_ren_uops_2_bits_fp_ctrl_ren3_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_fp_ctrl_swap12_0 = io_ren_uops_2_bits_fp_ctrl_swap12_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_fp_ctrl_swap12_0 = io_ren_uops_2_bits_fp_ctrl_swap12_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_fp_ctrl_swap12_0 = io_ren_uops_2_bits_fp_ctrl_swap12_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_fp_ctrl_swap12_0 = io_ren_uops_2_bits_fp_ctrl_swap12_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_fp_ctrl_swap23_0 = io_ren_uops_2_bits_fp_ctrl_swap23_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_fp_ctrl_swap23_0 = io_ren_uops_2_bits_fp_ctrl_swap23_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_fp_ctrl_swap23_0 = io_ren_uops_2_bits_fp_ctrl_swap23_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_fp_ctrl_swap23_0 = io_ren_uops_2_bits_fp_ctrl_swap23_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_3_2_bits_fp_ctrl_typeTagIn_0 = io_ren_uops_2_bits_fp_ctrl_typeTagIn_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_2_bits_fp_ctrl_typeTagIn_0 = io_ren_uops_2_bits_fp_ctrl_typeTagIn_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_2_bits_fp_ctrl_typeTagIn_0 = io_ren_uops_2_bits_fp_ctrl_typeTagIn_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_2_bits_fp_ctrl_typeTagIn_0 = io_ren_uops_2_bits_fp_ctrl_typeTagIn_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_3_2_bits_fp_ctrl_typeTagOut_0 = io_ren_uops_2_bits_fp_ctrl_typeTagOut_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_2_bits_fp_ctrl_typeTagOut_0 = io_ren_uops_2_bits_fp_ctrl_typeTagOut_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_2_bits_fp_ctrl_typeTagOut_0 = io_ren_uops_2_bits_fp_ctrl_typeTagOut_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_2_bits_fp_ctrl_typeTagOut_0 = io_ren_uops_2_bits_fp_ctrl_typeTagOut_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_fp_ctrl_fromint_0 = io_ren_uops_2_bits_fp_ctrl_fromint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_fp_ctrl_fromint_0 = io_ren_uops_2_bits_fp_ctrl_fromint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_fp_ctrl_fromint_0 = io_ren_uops_2_bits_fp_ctrl_fromint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_fp_ctrl_fromint_0 = io_ren_uops_2_bits_fp_ctrl_fromint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_fp_ctrl_toint_0 = io_ren_uops_2_bits_fp_ctrl_toint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_fp_ctrl_toint_0 = io_ren_uops_2_bits_fp_ctrl_toint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_fp_ctrl_toint_0 = io_ren_uops_2_bits_fp_ctrl_toint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_fp_ctrl_toint_0 = io_ren_uops_2_bits_fp_ctrl_toint_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_fp_ctrl_fastpipe_0 = io_ren_uops_2_bits_fp_ctrl_fastpipe_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_fp_ctrl_fastpipe_0 = io_ren_uops_2_bits_fp_ctrl_fastpipe_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_fp_ctrl_fastpipe_0 = io_ren_uops_2_bits_fp_ctrl_fastpipe_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_fp_ctrl_fastpipe_0 = io_ren_uops_2_bits_fp_ctrl_fastpipe_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_fp_ctrl_fma_0 = io_ren_uops_2_bits_fp_ctrl_fma_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_fp_ctrl_fma_0 = io_ren_uops_2_bits_fp_ctrl_fma_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_fp_ctrl_fma_0 = io_ren_uops_2_bits_fp_ctrl_fma_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_fp_ctrl_fma_0 = io_ren_uops_2_bits_fp_ctrl_fma_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_fp_ctrl_div_0 = io_ren_uops_2_bits_fp_ctrl_div_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_fp_ctrl_div_0 = io_ren_uops_2_bits_fp_ctrl_div_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_fp_ctrl_div_0 = io_ren_uops_2_bits_fp_ctrl_div_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_fp_ctrl_div_0 = io_ren_uops_2_bits_fp_ctrl_div_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_fp_ctrl_sqrt_0 = io_ren_uops_2_bits_fp_ctrl_sqrt_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_fp_ctrl_sqrt_0 = io_ren_uops_2_bits_fp_ctrl_sqrt_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_fp_ctrl_sqrt_0 = io_ren_uops_2_bits_fp_ctrl_sqrt_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_fp_ctrl_sqrt_0 = io_ren_uops_2_bits_fp_ctrl_sqrt_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_fp_ctrl_wflags_0 = io_ren_uops_2_bits_fp_ctrl_wflags_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_fp_ctrl_wflags_0 = io_ren_uops_2_bits_fp_ctrl_wflags_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_fp_ctrl_wflags_0 = io_ren_uops_2_bits_fp_ctrl_wflags_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_fp_ctrl_wflags_0 = io_ren_uops_2_bits_fp_ctrl_wflags_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_fp_ctrl_vec_0 = io_ren_uops_2_bits_fp_ctrl_vec_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_fp_ctrl_vec_0 = io_ren_uops_2_bits_fp_ctrl_vec_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_fp_ctrl_vec_0 = io_ren_uops_2_bits_fp_ctrl_vec_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_fp_ctrl_vec_0 = io_ren_uops_2_bits_fp_ctrl_vec_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_3_2_bits_rob_idx_0 = io_ren_uops_2_bits_rob_idx_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_2_bits_rob_idx_0 = io_ren_uops_2_bits_rob_idx_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_2_bits_rob_idx_0 = io_ren_uops_2_bits_rob_idx_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_2_bits_rob_idx_0 = io_ren_uops_2_bits_rob_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_3_2_bits_ldq_idx_0 = io_ren_uops_2_bits_ldq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_2_bits_ldq_idx_0 = io_ren_uops_2_bits_ldq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_2_bits_ldq_idx_0 = io_ren_uops_2_bits_ldq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_2_bits_ldq_idx_0 = io_ren_uops_2_bits_ldq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_3_2_bits_stq_idx_0 = io_ren_uops_2_bits_stq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_2_bits_stq_idx_0 = io_ren_uops_2_bits_stq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_2_bits_stq_idx_0 = io_ren_uops_2_bits_stq_idx_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_2_bits_stq_idx_0 = io_ren_uops_2_bits_stq_idx_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_3_2_bits_rxq_idx_0 = io_ren_uops_2_bits_rxq_idx_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_2_bits_rxq_idx_0 = io_ren_uops_2_bits_rxq_idx_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_2_bits_rxq_idx_0 = io_ren_uops_2_bits_rxq_idx_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_2_bits_rxq_idx_0 = io_ren_uops_2_bits_rxq_idx_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_3_2_bits_pdst_0 = io_ren_uops_2_bits_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_2_bits_pdst_0 = io_ren_uops_2_bits_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_2_bits_pdst_0 = io_ren_uops_2_bits_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_2_bits_pdst_0 = io_ren_uops_2_bits_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_3_2_bits_prs1_0 = io_ren_uops_2_bits_prs1_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_2_bits_prs1_0 = io_ren_uops_2_bits_prs1_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_2_bits_prs1_0 = io_ren_uops_2_bits_prs1_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_2_bits_prs1_0 = io_ren_uops_2_bits_prs1_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_3_2_bits_prs2_0 = io_ren_uops_2_bits_prs2_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_2_bits_prs2_0 = io_ren_uops_2_bits_prs2_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_2_bits_prs2_0 = io_ren_uops_2_bits_prs2_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_2_bits_prs2_0 = io_ren_uops_2_bits_prs2_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_3_2_bits_prs3_0 = io_ren_uops_2_bits_prs3_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_2_bits_prs3_0 = io_ren_uops_2_bits_prs3_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_2_bits_prs3_0 = io_ren_uops_2_bits_prs3_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_2_bits_prs3_0 = io_ren_uops_2_bits_prs3_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_3_2_bits_ppred_0 = io_ren_uops_2_bits_ppred_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_2_bits_ppred_0 = io_ren_uops_2_bits_ppred_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_2_bits_ppred_0 = io_ren_uops_2_bits_ppred_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_2_bits_ppred_0 = io_ren_uops_2_bits_ppred_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_prs1_busy_0 = io_ren_uops_2_bits_prs1_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_prs1_busy_0 = io_ren_uops_2_bits_prs1_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_prs1_busy_0 = io_ren_uops_2_bits_prs1_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_prs1_busy_0 = io_ren_uops_2_bits_prs1_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_prs2_busy_0 = io_ren_uops_2_bits_prs2_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_prs2_busy_0 = io_ren_uops_2_bits_prs2_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_prs2_busy_0 = io_ren_uops_2_bits_prs2_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_prs2_busy_0 = io_ren_uops_2_bits_prs2_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_prs3_busy_0 = io_ren_uops_2_bits_prs3_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_prs3_busy_0 = io_ren_uops_2_bits_prs3_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_prs3_busy_0 = io_ren_uops_2_bits_prs3_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_prs3_busy_0 = io_ren_uops_2_bits_prs3_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_ppred_busy_0 = io_ren_uops_2_bits_ppred_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_ppred_busy_0 = io_ren_uops_2_bits_ppred_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_ppred_busy_0 = io_ren_uops_2_bits_ppred_busy_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_ppred_busy_0 = io_ren_uops_2_bits_ppred_busy_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_3_2_bits_stale_pdst_0 = io_ren_uops_2_bits_stale_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_2_2_bits_stale_pdst_0 = io_ren_uops_2_bits_stale_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_1_2_bits_stale_pdst_0 = io_ren_uops_2_bits_stale_pdst_0; // @[dispatch.scala:43:7]
wire [6:0] io_dis_uops_0_2_bits_stale_pdst_0 = io_ren_uops_2_bits_stale_pdst_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_exception_0 = io_ren_uops_2_bits_exception_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_exception_0 = io_ren_uops_2_bits_exception_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_exception_0 = io_ren_uops_2_bits_exception_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_exception_0 = io_ren_uops_2_bits_exception_0; // @[dispatch.scala:43:7]
wire [63:0] io_dis_uops_3_2_bits_exc_cause_0 = io_ren_uops_2_bits_exc_cause_0; // @[dispatch.scala:43:7]
wire [63:0] io_dis_uops_2_2_bits_exc_cause_0 = io_ren_uops_2_bits_exc_cause_0; // @[dispatch.scala:43:7]
wire [63:0] io_dis_uops_1_2_bits_exc_cause_0 = io_ren_uops_2_bits_exc_cause_0; // @[dispatch.scala:43:7]
wire [63:0] io_dis_uops_0_2_bits_exc_cause_0 = io_ren_uops_2_bits_exc_cause_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_3_2_bits_mem_cmd_0 = io_ren_uops_2_bits_mem_cmd_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_2_bits_mem_cmd_0 = io_ren_uops_2_bits_mem_cmd_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_2_bits_mem_cmd_0 = io_ren_uops_2_bits_mem_cmd_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_2_bits_mem_cmd_0 = io_ren_uops_2_bits_mem_cmd_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_3_2_bits_mem_size_0 = io_ren_uops_2_bits_mem_size_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_2_bits_mem_size_0 = io_ren_uops_2_bits_mem_size_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_2_bits_mem_size_0 = io_ren_uops_2_bits_mem_size_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_2_bits_mem_size_0 = io_ren_uops_2_bits_mem_size_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_mem_signed_0 = io_ren_uops_2_bits_mem_signed_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_mem_signed_0 = io_ren_uops_2_bits_mem_signed_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_mem_signed_0 = io_ren_uops_2_bits_mem_signed_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_mem_signed_0 = io_ren_uops_2_bits_mem_signed_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_uses_ldq_0 = io_ren_uops_2_bits_uses_ldq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_uses_ldq_0 = io_ren_uops_2_bits_uses_ldq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_uses_ldq_0 = io_ren_uops_2_bits_uses_ldq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_uses_ldq_0 = io_ren_uops_2_bits_uses_ldq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_uses_stq_0 = io_ren_uops_2_bits_uses_stq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_uses_stq_0 = io_ren_uops_2_bits_uses_stq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_uses_stq_0 = io_ren_uops_2_bits_uses_stq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_uses_stq_0 = io_ren_uops_2_bits_uses_stq_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_is_unique_0 = io_ren_uops_2_bits_is_unique_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_is_unique_0 = io_ren_uops_2_bits_is_unique_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_is_unique_0 = io_ren_uops_2_bits_is_unique_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_is_unique_0 = io_ren_uops_2_bits_is_unique_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_flush_on_commit_0 = io_ren_uops_2_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_flush_on_commit_0 = io_ren_uops_2_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_flush_on_commit_0 = io_ren_uops_2_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_flush_on_commit_0 = io_ren_uops_2_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_3_2_bits_csr_cmd_0 = io_ren_uops_2_bits_csr_cmd_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_2_bits_csr_cmd_0 = io_ren_uops_2_bits_csr_cmd_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_2_bits_csr_cmd_0 = io_ren_uops_2_bits_csr_cmd_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_2_bits_csr_cmd_0 = io_ren_uops_2_bits_csr_cmd_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_ldst_is_rs1_0 = io_ren_uops_2_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_ldst_is_rs1_0 = io_ren_uops_2_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_ldst_is_rs1_0 = io_ren_uops_2_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_ldst_is_rs1_0 = io_ren_uops_2_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_3_2_bits_ldst_0 = io_ren_uops_2_bits_ldst_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_2_2_bits_ldst_0 = io_ren_uops_2_bits_ldst_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_1_2_bits_ldst_0 = io_ren_uops_2_bits_ldst_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_0_2_bits_ldst_0 = io_ren_uops_2_bits_ldst_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_3_2_bits_lrs1_0 = io_ren_uops_2_bits_lrs1_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_2_2_bits_lrs1_0 = io_ren_uops_2_bits_lrs1_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_1_2_bits_lrs1_0 = io_ren_uops_2_bits_lrs1_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_0_2_bits_lrs1_0 = io_ren_uops_2_bits_lrs1_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_3_2_bits_lrs2_0 = io_ren_uops_2_bits_lrs2_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_2_2_bits_lrs2_0 = io_ren_uops_2_bits_lrs2_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_1_2_bits_lrs2_0 = io_ren_uops_2_bits_lrs2_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_0_2_bits_lrs2_0 = io_ren_uops_2_bits_lrs2_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_3_2_bits_lrs3_0 = io_ren_uops_2_bits_lrs3_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_2_2_bits_lrs3_0 = io_ren_uops_2_bits_lrs3_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_1_2_bits_lrs3_0 = io_ren_uops_2_bits_lrs3_0; // @[dispatch.scala:43:7]
wire [5:0] io_dis_uops_0_2_bits_lrs3_0 = io_ren_uops_2_bits_lrs3_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_3_2_bits_dst_rtype_0 = io_ren_uops_2_bits_dst_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_2_bits_dst_rtype_0 = io_ren_uops_2_bits_dst_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_2_bits_dst_rtype_0 = io_ren_uops_2_bits_dst_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_2_bits_dst_rtype_0 = io_ren_uops_2_bits_dst_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_3_2_bits_lrs1_rtype_0 = io_ren_uops_2_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_2_bits_lrs1_rtype_0 = io_ren_uops_2_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_2_bits_lrs1_rtype_0 = io_ren_uops_2_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_2_bits_lrs1_rtype_0 = io_ren_uops_2_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_3_2_bits_lrs2_rtype_0 = io_ren_uops_2_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_2_bits_lrs2_rtype_0 = io_ren_uops_2_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_2_bits_lrs2_rtype_0 = io_ren_uops_2_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_2_bits_lrs2_rtype_0 = io_ren_uops_2_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_frs3_en_0 = io_ren_uops_2_bits_frs3_en_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_frs3_en_0 = io_ren_uops_2_bits_frs3_en_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_frs3_en_0 = io_ren_uops_2_bits_frs3_en_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_frs3_en_0 = io_ren_uops_2_bits_frs3_en_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_fcn_dw_0 = io_ren_uops_2_bits_fcn_dw_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_fcn_dw_0 = io_ren_uops_2_bits_fcn_dw_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_fcn_dw_0 = io_ren_uops_2_bits_fcn_dw_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_fcn_dw_0 = io_ren_uops_2_bits_fcn_dw_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_3_2_bits_fcn_op_0 = io_ren_uops_2_bits_fcn_op_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_2_2_bits_fcn_op_0 = io_ren_uops_2_bits_fcn_op_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_1_2_bits_fcn_op_0 = io_ren_uops_2_bits_fcn_op_0; // @[dispatch.scala:43:7]
wire [4:0] io_dis_uops_0_2_bits_fcn_op_0 = io_ren_uops_2_bits_fcn_op_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_fp_val_0 = io_ren_uops_2_bits_fp_val_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_fp_val_0 = io_ren_uops_2_bits_fp_val_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_fp_val_0 = io_ren_uops_2_bits_fp_val_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_fp_val_0 = io_ren_uops_2_bits_fp_val_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_3_2_bits_fp_rm_0 = io_ren_uops_2_bits_fp_rm_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_2_bits_fp_rm_0 = io_ren_uops_2_bits_fp_rm_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_2_bits_fp_rm_0 = io_ren_uops_2_bits_fp_rm_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_2_bits_fp_rm_0 = io_ren_uops_2_bits_fp_rm_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_3_2_bits_fp_typ_0 = io_ren_uops_2_bits_fp_typ_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_2_2_bits_fp_typ_0 = io_ren_uops_2_bits_fp_typ_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_1_2_bits_fp_typ_0 = io_ren_uops_2_bits_fp_typ_0; // @[dispatch.scala:43:7]
wire [1:0] io_dis_uops_0_2_bits_fp_typ_0 = io_ren_uops_2_bits_fp_typ_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_xcpt_pf_if_0 = io_ren_uops_2_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_xcpt_pf_if_0 = io_ren_uops_2_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_xcpt_pf_if_0 = io_ren_uops_2_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_xcpt_pf_if_0 = io_ren_uops_2_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_xcpt_ae_if_0 = io_ren_uops_2_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_xcpt_ae_if_0 = io_ren_uops_2_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_xcpt_ae_if_0 = io_ren_uops_2_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_xcpt_ae_if_0 = io_ren_uops_2_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_xcpt_ma_if_0 = io_ren_uops_2_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_xcpt_ma_if_0 = io_ren_uops_2_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_xcpt_ma_if_0 = io_ren_uops_2_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_xcpt_ma_if_0 = io_ren_uops_2_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_bp_debug_if_0 = io_ren_uops_2_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_bp_debug_if_0 = io_ren_uops_2_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_bp_debug_if_0 = io_ren_uops_2_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_bp_debug_if_0 = io_ren_uops_2_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_bits_bp_xcpt_if_0 = io_ren_uops_2_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_bits_bp_xcpt_if_0 = io_ren_uops_2_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_bits_bp_xcpt_if_0 = io_ren_uops_2_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_bits_bp_xcpt_if_0 = io_ren_uops_2_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_3_2_bits_debug_fsrc_0 = io_ren_uops_2_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_2_bits_debug_fsrc_0 = io_ren_uops_2_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_2_bits_debug_fsrc_0 = io_ren_uops_2_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_2_bits_debug_fsrc_0 = io_ren_uops_2_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_3_2_bits_debug_tsrc_0 = io_ren_uops_2_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_2_2_bits_debug_tsrc_0 = io_ren_uops_2_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_1_2_bits_debug_tsrc_0 = io_ren_uops_2_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
wire [2:0] io_dis_uops_0_2_bits_debug_tsrc_0 = io_ren_uops_2_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
wire _ren_readys_WIRE_3_0 = io_dis_uops_3_0_ready_0; // @[dispatch.scala:43:7, :47:46]
wire _io_dis_uops_3_0_valid_T; // @[dispatch.scala:58:42]
wire _ren_readys_WIRE_3_1 = io_dis_uops_3_1_ready_0; // @[dispatch.scala:43:7, :47:46]
wire _io_dis_uops_3_1_valid_T; // @[dispatch.scala:58:42]
wire _ren_readys_WIRE_3_2 = io_dis_uops_3_2_ready_0; // @[dispatch.scala:43:7, :47:46]
wire _io_dis_uops_3_2_valid_T; // @[dispatch.scala:58:42]
wire _ren_readys_WIRE_2_0 = io_dis_uops_2_0_ready_0; // @[dispatch.scala:43:7, :47:46]
wire _io_dis_uops_2_0_valid_T; // @[dispatch.scala:58:42]
wire _ren_readys_WIRE_2_1 = io_dis_uops_2_1_ready_0; // @[dispatch.scala:43:7, :47:46]
wire _io_dis_uops_2_1_valid_T; // @[dispatch.scala:58:42]
wire _ren_readys_WIRE_2_2 = io_dis_uops_2_2_ready_0; // @[dispatch.scala:43:7, :47:46]
wire _io_dis_uops_2_2_valid_T; // @[dispatch.scala:58:42]
wire _ren_readys_WIRE_1_0 = io_dis_uops_1_0_ready_0; // @[dispatch.scala:43:7, :47:46]
wire _io_dis_uops_1_0_valid_T; // @[dispatch.scala:58:42]
wire _ren_readys_WIRE_1_1 = io_dis_uops_1_1_ready_0; // @[dispatch.scala:43:7, :47:46]
wire _io_dis_uops_1_1_valid_T; // @[dispatch.scala:58:42]
wire _ren_readys_WIRE_1_2 = io_dis_uops_1_2_ready_0; // @[dispatch.scala:43:7, :47:46]
wire _io_dis_uops_1_2_valid_T; // @[dispatch.scala:58:42]
wire _ren_readys_WIRE_0 = io_dis_uops_0_0_ready_0; // @[dispatch.scala:43:7, :47:46]
wire _io_dis_uops_0_0_valid_T; // @[dispatch.scala:58:42]
wire _ren_readys_WIRE_1 = io_dis_uops_0_1_ready_0; // @[dispatch.scala:43:7, :47:46]
wire _io_dis_uops_0_1_valid_T; // @[dispatch.scala:58:42]
wire _ren_readys_WIRE_2 = io_dis_uops_0_2_ready_0; // @[dispatch.scala:43:7, :47:46]
wire _io_dis_uops_0_2_valid_T; // @[dispatch.scala:58:42]
wire io_ren_uops_0_ready_0; // @[dispatch.scala:43:7]
wire io_ren_uops_1_ready_0; // @[dispatch.scala:43:7]
wire io_ren_uops_2_ready_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_0_valid_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_1_valid_0; // @[dispatch.scala:43:7]
wire io_dis_uops_3_2_valid_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_0_valid_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_1_valid_0; // @[dispatch.scala:43:7]
wire io_dis_uops_2_2_valid_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_0_valid_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_1_valid_0; // @[dispatch.scala:43:7]
wire io_dis_uops_1_2_valid_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_0_valid_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_1_valid_0; // @[dispatch.scala:43:7]
wire io_dis_uops_0_2_valid_0; // @[dispatch.scala:43:7]
wire [1:0] ren_readys_hi = {_ren_readys_WIRE_2, _ren_readys_WIRE_1}; // @[dispatch.scala:47:{46,63}]
wire [2:0] _ren_readys_T = {ren_readys_hi, _ren_readys_WIRE_0}; // @[dispatch.scala:47:{46,63}]
wire [1:0] ren_readys_hi_1 = {_ren_readys_WIRE_1_2, _ren_readys_WIRE_1_1}; // @[dispatch.scala:47:{46,63}]
wire [2:0] _ren_readys_T_1 = {ren_readys_hi_1, _ren_readys_WIRE_1_0}; // @[dispatch.scala:47:{46,63}]
wire [1:0] ren_readys_hi_2 = {_ren_readys_WIRE_2_2, _ren_readys_WIRE_2_1}; // @[dispatch.scala:47:{46,63}]
wire [2:0] _ren_readys_T_2 = {ren_readys_hi_2, _ren_readys_WIRE_2_0}; // @[dispatch.scala:47:{46,63}]
wire [1:0] ren_readys_hi_3 = {_ren_readys_WIRE_3_2, _ren_readys_WIRE_3_1}; // @[dispatch.scala:47:{46,63}]
wire [2:0] _ren_readys_T_3 = {ren_readys_hi_3, _ren_readys_WIRE_3_0}; // @[dispatch.scala:47:{46,63}]
wire [2:0] _ren_readys_T_4 = _ren_readys_T & _ren_readys_T_1; // @[dispatch.scala:47:{63,79}]
wire [2:0] _ren_readys_T_5 = _ren_readys_T_4 & _ren_readys_T_2; // @[dispatch.scala:47:{63,79}]
wire [2:0] ren_readys = _ren_readys_T_5 & _ren_readys_T_3; // @[dispatch.scala:47:{63,79}]
assign _io_ren_uops_0_ready_T = ren_readys[0]; // @[dispatch.scala:47:79, :50:39]
assign io_ren_uops_0_ready_0 = _io_ren_uops_0_ready_T; // @[dispatch.scala:43:7, :50:39]
assign _io_ren_uops_1_ready_T = ren_readys[1]; // @[dispatch.scala:47:79, :50:39]
assign io_ren_uops_1_ready_0 = _io_ren_uops_1_ready_T; // @[dispatch.scala:43:7, :50:39]
assign _io_ren_uops_2_ready_T = ren_readys[2]; // @[dispatch.scala:47:79, :50:39]
assign io_ren_uops_2_ready_0 = _io_ren_uops_2_ready_T; // @[dispatch.scala:43:7, :50:39]
assign _io_dis_uops_0_0_valid_T = io_ren_uops_0_valid_0 & io_ren_uops_0_bits_iq_type_0_0; // @[dispatch.scala:43:7, :58:42]
assign io_dis_uops_0_0_valid_0 = _io_dis_uops_0_0_valid_T; // @[dispatch.scala:43:7, :58:42]
assign _io_dis_uops_0_1_valid_T = io_ren_uops_1_valid_0 & io_ren_uops_1_bits_iq_type_0_0; // @[dispatch.scala:43:7, :58:42]
assign io_dis_uops_0_1_valid_0 = _io_dis_uops_0_1_valid_T; // @[dispatch.scala:43:7, :58:42]
assign _io_dis_uops_0_2_valid_T = io_ren_uops_2_valid_0 & io_ren_uops_2_bits_iq_type_0_0; // @[dispatch.scala:43:7, :58:42]
assign io_dis_uops_0_2_valid_0 = _io_dis_uops_0_2_valid_T; // @[dispatch.scala:43:7, :58:42]
assign _io_dis_uops_1_0_valid_T = io_ren_uops_0_valid_0 & io_ren_uops_0_bits_iq_type_1_0; // @[dispatch.scala:43:7, :58:42]
assign io_dis_uops_1_0_valid_0 = _io_dis_uops_1_0_valid_T; // @[dispatch.scala:43:7, :58:42]
assign _io_dis_uops_1_1_valid_T = io_ren_uops_1_valid_0 & io_ren_uops_1_bits_iq_type_1_0; // @[dispatch.scala:43:7, :58:42]
assign io_dis_uops_1_1_valid_0 = _io_dis_uops_1_1_valid_T; // @[dispatch.scala:43:7, :58:42]
assign _io_dis_uops_1_2_valid_T = io_ren_uops_2_valid_0 & io_ren_uops_2_bits_iq_type_1_0; // @[dispatch.scala:43:7, :58:42]
assign io_dis_uops_1_2_valid_0 = _io_dis_uops_1_2_valid_T; // @[dispatch.scala:43:7, :58:42]
assign _io_dis_uops_2_0_valid_T = io_ren_uops_0_valid_0 & io_ren_uops_0_bits_iq_type_2_0; // @[dispatch.scala:43:7, :58:42]
assign io_dis_uops_2_0_valid_0 = _io_dis_uops_2_0_valid_T; // @[dispatch.scala:43:7, :58:42]
assign _io_dis_uops_2_1_valid_T = io_ren_uops_1_valid_0 & io_ren_uops_1_bits_iq_type_2_0; // @[dispatch.scala:43:7, :58:42]
assign io_dis_uops_2_1_valid_0 = _io_dis_uops_2_1_valid_T; // @[dispatch.scala:43:7, :58:42]
assign _io_dis_uops_2_2_valid_T = io_ren_uops_2_valid_0 & io_ren_uops_2_bits_iq_type_2_0; // @[dispatch.scala:43:7, :58:42]
assign io_dis_uops_2_2_valid_0 = _io_dis_uops_2_2_valid_T; // @[dispatch.scala:43:7, :58:42]
assign _io_dis_uops_3_0_valid_T = io_ren_uops_0_valid_0 & io_ren_uops_0_bits_iq_type_3_0; // @[dispatch.scala:43:7, :58:42]
assign io_dis_uops_3_0_valid_0 = _io_dis_uops_3_0_valid_T; // @[dispatch.scala:43:7, :58:42]
assign _io_dis_uops_3_1_valid_T = io_ren_uops_1_valid_0 & io_ren_uops_1_bits_iq_type_3_0; // @[dispatch.scala:43:7, :58:42]
assign io_dis_uops_3_1_valid_0 = _io_dis_uops_3_1_valid_T; // @[dispatch.scala:43:7, :58:42]
assign _io_dis_uops_3_2_valid_T = io_ren_uops_2_valid_0 & io_ren_uops_2_bits_iq_type_3_0; // @[dispatch.scala:43:7, :58:42]
assign io_dis_uops_3_2_valid_0 = _io_dis_uops_3_2_valid_T; // @[dispatch.scala:43:7, :58:42]
assign io_ren_uops_0_ready = io_ren_uops_0_ready_0; // @[dispatch.scala:43:7]
assign io_ren_uops_1_ready = io_ren_uops_1_ready_0; // @[dispatch.scala:43:7]
assign io_ren_uops_2_ready = io_ren_uops_2_ready_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_valid = io_dis_uops_3_0_valid_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_inst = io_dis_uops_3_0_bits_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_debug_inst = io_dis_uops_3_0_bits_debug_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_is_rvc = io_dis_uops_3_0_bits_is_rvc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_debug_pc = io_dis_uops_3_0_bits_debug_pc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_iq_type_0 = io_dis_uops_3_0_bits_iq_type_0_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_iq_type_1 = io_dis_uops_3_0_bits_iq_type_1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_iq_type_2 = io_dis_uops_3_0_bits_iq_type_2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_iq_type_3 = io_dis_uops_3_0_bits_iq_type_3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_fu_code_0 = io_dis_uops_3_0_bits_fu_code_0_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_fu_code_1 = io_dis_uops_3_0_bits_fu_code_1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_fu_code_2 = io_dis_uops_3_0_bits_fu_code_2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_fu_code_3 = io_dis_uops_3_0_bits_fu_code_3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_fu_code_4 = io_dis_uops_3_0_bits_fu_code_4_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_fu_code_5 = io_dis_uops_3_0_bits_fu_code_5_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_fu_code_6 = io_dis_uops_3_0_bits_fu_code_6_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_fu_code_7 = io_dis_uops_3_0_bits_fu_code_7_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_fu_code_8 = io_dis_uops_3_0_bits_fu_code_8_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_fu_code_9 = io_dis_uops_3_0_bits_fu_code_9_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_iw_issued = io_dis_uops_3_0_bits_iw_issued_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_iw_issued_partial_agen = io_dis_uops_3_0_bits_iw_issued_partial_agen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_iw_issued_partial_dgen = io_dis_uops_3_0_bits_iw_issued_partial_dgen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_iw_p1_speculative_child = io_dis_uops_3_0_bits_iw_p1_speculative_child_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_iw_p2_speculative_child = io_dis_uops_3_0_bits_iw_p2_speculative_child_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_iw_p1_bypass_hint = io_dis_uops_3_0_bits_iw_p1_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_iw_p2_bypass_hint = io_dis_uops_3_0_bits_iw_p2_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_iw_p3_bypass_hint = io_dis_uops_3_0_bits_iw_p3_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_dis_col_sel = io_dis_uops_3_0_bits_dis_col_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_br_mask = io_dis_uops_3_0_bits_br_mask_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_br_tag = io_dis_uops_3_0_bits_br_tag_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_br_type = io_dis_uops_3_0_bits_br_type_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_is_sfb = io_dis_uops_3_0_bits_is_sfb_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_is_fence = io_dis_uops_3_0_bits_is_fence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_is_fencei = io_dis_uops_3_0_bits_is_fencei_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_is_sfence = io_dis_uops_3_0_bits_is_sfence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_is_amo = io_dis_uops_3_0_bits_is_amo_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_is_eret = io_dis_uops_3_0_bits_is_eret_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_is_sys_pc2epc = io_dis_uops_3_0_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_is_rocc = io_dis_uops_3_0_bits_is_rocc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_is_mov = io_dis_uops_3_0_bits_is_mov_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_ftq_idx = io_dis_uops_3_0_bits_ftq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_edge_inst = io_dis_uops_3_0_bits_edge_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_pc_lob = io_dis_uops_3_0_bits_pc_lob_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_taken = io_dis_uops_3_0_bits_taken_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_imm_rename = io_dis_uops_3_0_bits_imm_rename_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_imm_sel = io_dis_uops_3_0_bits_imm_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_pimm = io_dis_uops_3_0_bits_pimm_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_imm_packed = io_dis_uops_3_0_bits_imm_packed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_op1_sel = io_dis_uops_3_0_bits_op1_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_op2_sel = io_dis_uops_3_0_bits_op2_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_fp_ctrl_ldst = io_dis_uops_3_0_bits_fp_ctrl_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_fp_ctrl_wen = io_dis_uops_3_0_bits_fp_ctrl_wen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_fp_ctrl_ren1 = io_dis_uops_3_0_bits_fp_ctrl_ren1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_fp_ctrl_ren2 = io_dis_uops_3_0_bits_fp_ctrl_ren2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_fp_ctrl_ren3 = io_dis_uops_3_0_bits_fp_ctrl_ren3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_fp_ctrl_swap12 = io_dis_uops_3_0_bits_fp_ctrl_swap12_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_fp_ctrl_swap23 = io_dis_uops_3_0_bits_fp_ctrl_swap23_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_fp_ctrl_typeTagIn = io_dis_uops_3_0_bits_fp_ctrl_typeTagIn_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_fp_ctrl_typeTagOut = io_dis_uops_3_0_bits_fp_ctrl_typeTagOut_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_fp_ctrl_fromint = io_dis_uops_3_0_bits_fp_ctrl_fromint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_fp_ctrl_toint = io_dis_uops_3_0_bits_fp_ctrl_toint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_fp_ctrl_fastpipe = io_dis_uops_3_0_bits_fp_ctrl_fastpipe_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_fp_ctrl_fma = io_dis_uops_3_0_bits_fp_ctrl_fma_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_fp_ctrl_div = io_dis_uops_3_0_bits_fp_ctrl_div_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_fp_ctrl_sqrt = io_dis_uops_3_0_bits_fp_ctrl_sqrt_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_fp_ctrl_wflags = io_dis_uops_3_0_bits_fp_ctrl_wflags_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_fp_ctrl_vec = io_dis_uops_3_0_bits_fp_ctrl_vec_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_rob_idx = io_dis_uops_3_0_bits_rob_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_ldq_idx = io_dis_uops_3_0_bits_ldq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_stq_idx = io_dis_uops_3_0_bits_stq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_rxq_idx = io_dis_uops_3_0_bits_rxq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_pdst = io_dis_uops_3_0_bits_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_prs1 = io_dis_uops_3_0_bits_prs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_prs2 = io_dis_uops_3_0_bits_prs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_prs3 = io_dis_uops_3_0_bits_prs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_ppred = io_dis_uops_3_0_bits_ppred_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_prs1_busy = io_dis_uops_3_0_bits_prs1_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_prs2_busy = io_dis_uops_3_0_bits_prs2_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_prs3_busy = io_dis_uops_3_0_bits_prs3_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_ppred_busy = io_dis_uops_3_0_bits_ppred_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_stale_pdst = io_dis_uops_3_0_bits_stale_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_exception = io_dis_uops_3_0_bits_exception_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_exc_cause = io_dis_uops_3_0_bits_exc_cause_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_mem_cmd = io_dis_uops_3_0_bits_mem_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_mem_size = io_dis_uops_3_0_bits_mem_size_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_mem_signed = io_dis_uops_3_0_bits_mem_signed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_uses_ldq = io_dis_uops_3_0_bits_uses_ldq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_uses_stq = io_dis_uops_3_0_bits_uses_stq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_is_unique = io_dis_uops_3_0_bits_is_unique_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_flush_on_commit = io_dis_uops_3_0_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_csr_cmd = io_dis_uops_3_0_bits_csr_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_ldst_is_rs1 = io_dis_uops_3_0_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_ldst = io_dis_uops_3_0_bits_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_lrs1 = io_dis_uops_3_0_bits_lrs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_lrs2 = io_dis_uops_3_0_bits_lrs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_lrs3 = io_dis_uops_3_0_bits_lrs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_dst_rtype = io_dis_uops_3_0_bits_dst_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_lrs1_rtype = io_dis_uops_3_0_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_lrs2_rtype = io_dis_uops_3_0_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_frs3_en = io_dis_uops_3_0_bits_frs3_en_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_fcn_dw = io_dis_uops_3_0_bits_fcn_dw_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_fcn_op = io_dis_uops_3_0_bits_fcn_op_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_fp_val = io_dis_uops_3_0_bits_fp_val_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_fp_rm = io_dis_uops_3_0_bits_fp_rm_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_fp_typ = io_dis_uops_3_0_bits_fp_typ_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_xcpt_pf_if = io_dis_uops_3_0_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_xcpt_ae_if = io_dis_uops_3_0_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_xcpt_ma_if = io_dis_uops_3_0_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_bp_debug_if = io_dis_uops_3_0_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_bp_xcpt_if = io_dis_uops_3_0_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_debug_fsrc = io_dis_uops_3_0_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_0_bits_debug_tsrc = io_dis_uops_3_0_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_valid = io_dis_uops_3_1_valid_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_inst = io_dis_uops_3_1_bits_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_debug_inst = io_dis_uops_3_1_bits_debug_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_is_rvc = io_dis_uops_3_1_bits_is_rvc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_debug_pc = io_dis_uops_3_1_bits_debug_pc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_iq_type_0 = io_dis_uops_3_1_bits_iq_type_0_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_iq_type_1 = io_dis_uops_3_1_bits_iq_type_1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_iq_type_2 = io_dis_uops_3_1_bits_iq_type_2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_iq_type_3 = io_dis_uops_3_1_bits_iq_type_3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_fu_code_0 = io_dis_uops_3_1_bits_fu_code_0_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_fu_code_1 = io_dis_uops_3_1_bits_fu_code_1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_fu_code_2 = io_dis_uops_3_1_bits_fu_code_2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_fu_code_3 = io_dis_uops_3_1_bits_fu_code_3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_fu_code_4 = io_dis_uops_3_1_bits_fu_code_4_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_fu_code_5 = io_dis_uops_3_1_bits_fu_code_5_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_fu_code_6 = io_dis_uops_3_1_bits_fu_code_6_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_fu_code_7 = io_dis_uops_3_1_bits_fu_code_7_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_fu_code_8 = io_dis_uops_3_1_bits_fu_code_8_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_fu_code_9 = io_dis_uops_3_1_bits_fu_code_9_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_iw_issued = io_dis_uops_3_1_bits_iw_issued_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_iw_issued_partial_agen = io_dis_uops_3_1_bits_iw_issued_partial_agen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_iw_issued_partial_dgen = io_dis_uops_3_1_bits_iw_issued_partial_dgen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_iw_p1_speculative_child = io_dis_uops_3_1_bits_iw_p1_speculative_child_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_iw_p2_speculative_child = io_dis_uops_3_1_bits_iw_p2_speculative_child_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_iw_p1_bypass_hint = io_dis_uops_3_1_bits_iw_p1_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_iw_p2_bypass_hint = io_dis_uops_3_1_bits_iw_p2_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_iw_p3_bypass_hint = io_dis_uops_3_1_bits_iw_p3_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_dis_col_sel = io_dis_uops_3_1_bits_dis_col_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_br_mask = io_dis_uops_3_1_bits_br_mask_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_br_tag = io_dis_uops_3_1_bits_br_tag_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_br_type = io_dis_uops_3_1_bits_br_type_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_is_sfb = io_dis_uops_3_1_bits_is_sfb_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_is_fence = io_dis_uops_3_1_bits_is_fence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_is_fencei = io_dis_uops_3_1_bits_is_fencei_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_is_sfence = io_dis_uops_3_1_bits_is_sfence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_is_amo = io_dis_uops_3_1_bits_is_amo_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_is_eret = io_dis_uops_3_1_bits_is_eret_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_is_sys_pc2epc = io_dis_uops_3_1_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_is_rocc = io_dis_uops_3_1_bits_is_rocc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_is_mov = io_dis_uops_3_1_bits_is_mov_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_ftq_idx = io_dis_uops_3_1_bits_ftq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_edge_inst = io_dis_uops_3_1_bits_edge_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_pc_lob = io_dis_uops_3_1_bits_pc_lob_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_taken = io_dis_uops_3_1_bits_taken_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_imm_rename = io_dis_uops_3_1_bits_imm_rename_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_imm_sel = io_dis_uops_3_1_bits_imm_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_pimm = io_dis_uops_3_1_bits_pimm_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_imm_packed = io_dis_uops_3_1_bits_imm_packed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_op1_sel = io_dis_uops_3_1_bits_op1_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_op2_sel = io_dis_uops_3_1_bits_op2_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_fp_ctrl_ldst = io_dis_uops_3_1_bits_fp_ctrl_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_fp_ctrl_wen = io_dis_uops_3_1_bits_fp_ctrl_wen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_fp_ctrl_ren1 = io_dis_uops_3_1_bits_fp_ctrl_ren1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_fp_ctrl_ren2 = io_dis_uops_3_1_bits_fp_ctrl_ren2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_fp_ctrl_ren3 = io_dis_uops_3_1_bits_fp_ctrl_ren3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_fp_ctrl_swap12 = io_dis_uops_3_1_bits_fp_ctrl_swap12_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_fp_ctrl_swap23 = io_dis_uops_3_1_bits_fp_ctrl_swap23_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_fp_ctrl_typeTagIn = io_dis_uops_3_1_bits_fp_ctrl_typeTagIn_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_fp_ctrl_typeTagOut = io_dis_uops_3_1_bits_fp_ctrl_typeTagOut_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_fp_ctrl_fromint = io_dis_uops_3_1_bits_fp_ctrl_fromint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_fp_ctrl_toint = io_dis_uops_3_1_bits_fp_ctrl_toint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_fp_ctrl_fastpipe = io_dis_uops_3_1_bits_fp_ctrl_fastpipe_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_fp_ctrl_fma = io_dis_uops_3_1_bits_fp_ctrl_fma_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_fp_ctrl_div = io_dis_uops_3_1_bits_fp_ctrl_div_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_fp_ctrl_sqrt = io_dis_uops_3_1_bits_fp_ctrl_sqrt_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_fp_ctrl_wflags = io_dis_uops_3_1_bits_fp_ctrl_wflags_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_fp_ctrl_vec = io_dis_uops_3_1_bits_fp_ctrl_vec_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_rob_idx = io_dis_uops_3_1_bits_rob_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_ldq_idx = io_dis_uops_3_1_bits_ldq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_stq_idx = io_dis_uops_3_1_bits_stq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_rxq_idx = io_dis_uops_3_1_bits_rxq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_pdst = io_dis_uops_3_1_bits_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_prs1 = io_dis_uops_3_1_bits_prs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_prs2 = io_dis_uops_3_1_bits_prs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_prs3 = io_dis_uops_3_1_bits_prs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_ppred = io_dis_uops_3_1_bits_ppred_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_prs1_busy = io_dis_uops_3_1_bits_prs1_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_prs2_busy = io_dis_uops_3_1_bits_prs2_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_prs3_busy = io_dis_uops_3_1_bits_prs3_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_ppred_busy = io_dis_uops_3_1_bits_ppred_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_stale_pdst = io_dis_uops_3_1_bits_stale_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_exception = io_dis_uops_3_1_bits_exception_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_exc_cause = io_dis_uops_3_1_bits_exc_cause_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_mem_cmd = io_dis_uops_3_1_bits_mem_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_mem_size = io_dis_uops_3_1_bits_mem_size_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_mem_signed = io_dis_uops_3_1_bits_mem_signed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_uses_ldq = io_dis_uops_3_1_bits_uses_ldq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_uses_stq = io_dis_uops_3_1_bits_uses_stq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_is_unique = io_dis_uops_3_1_bits_is_unique_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_flush_on_commit = io_dis_uops_3_1_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_csr_cmd = io_dis_uops_3_1_bits_csr_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_ldst_is_rs1 = io_dis_uops_3_1_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_ldst = io_dis_uops_3_1_bits_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_lrs1 = io_dis_uops_3_1_bits_lrs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_lrs2 = io_dis_uops_3_1_bits_lrs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_lrs3 = io_dis_uops_3_1_bits_lrs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_dst_rtype = io_dis_uops_3_1_bits_dst_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_lrs1_rtype = io_dis_uops_3_1_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_lrs2_rtype = io_dis_uops_3_1_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_frs3_en = io_dis_uops_3_1_bits_frs3_en_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_fcn_dw = io_dis_uops_3_1_bits_fcn_dw_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_fcn_op = io_dis_uops_3_1_bits_fcn_op_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_fp_val = io_dis_uops_3_1_bits_fp_val_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_fp_rm = io_dis_uops_3_1_bits_fp_rm_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_fp_typ = io_dis_uops_3_1_bits_fp_typ_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_xcpt_pf_if = io_dis_uops_3_1_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_xcpt_ae_if = io_dis_uops_3_1_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_xcpt_ma_if = io_dis_uops_3_1_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_bp_debug_if = io_dis_uops_3_1_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_bp_xcpt_if = io_dis_uops_3_1_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_debug_fsrc = io_dis_uops_3_1_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_1_bits_debug_tsrc = io_dis_uops_3_1_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_valid = io_dis_uops_3_2_valid_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_inst = io_dis_uops_3_2_bits_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_debug_inst = io_dis_uops_3_2_bits_debug_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_is_rvc = io_dis_uops_3_2_bits_is_rvc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_debug_pc = io_dis_uops_3_2_bits_debug_pc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_iq_type_0 = io_dis_uops_3_2_bits_iq_type_0_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_iq_type_1 = io_dis_uops_3_2_bits_iq_type_1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_iq_type_2 = io_dis_uops_3_2_bits_iq_type_2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_iq_type_3 = io_dis_uops_3_2_bits_iq_type_3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_fu_code_0 = io_dis_uops_3_2_bits_fu_code_0_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_fu_code_1 = io_dis_uops_3_2_bits_fu_code_1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_fu_code_2 = io_dis_uops_3_2_bits_fu_code_2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_fu_code_3 = io_dis_uops_3_2_bits_fu_code_3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_fu_code_4 = io_dis_uops_3_2_bits_fu_code_4_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_fu_code_5 = io_dis_uops_3_2_bits_fu_code_5_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_fu_code_6 = io_dis_uops_3_2_bits_fu_code_6_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_fu_code_7 = io_dis_uops_3_2_bits_fu_code_7_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_fu_code_8 = io_dis_uops_3_2_bits_fu_code_8_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_fu_code_9 = io_dis_uops_3_2_bits_fu_code_9_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_iw_issued = io_dis_uops_3_2_bits_iw_issued_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_iw_issued_partial_agen = io_dis_uops_3_2_bits_iw_issued_partial_agen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_iw_issued_partial_dgen = io_dis_uops_3_2_bits_iw_issued_partial_dgen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_iw_p1_speculative_child = io_dis_uops_3_2_bits_iw_p1_speculative_child_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_iw_p2_speculative_child = io_dis_uops_3_2_bits_iw_p2_speculative_child_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_iw_p1_bypass_hint = io_dis_uops_3_2_bits_iw_p1_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_iw_p2_bypass_hint = io_dis_uops_3_2_bits_iw_p2_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_iw_p3_bypass_hint = io_dis_uops_3_2_bits_iw_p3_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_dis_col_sel = io_dis_uops_3_2_bits_dis_col_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_br_mask = io_dis_uops_3_2_bits_br_mask_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_br_tag = io_dis_uops_3_2_bits_br_tag_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_br_type = io_dis_uops_3_2_bits_br_type_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_is_sfb = io_dis_uops_3_2_bits_is_sfb_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_is_fence = io_dis_uops_3_2_bits_is_fence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_is_fencei = io_dis_uops_3_2_bits_is_fencei_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_is_sfence = io_dis_uops_3_2_bits_is_sfence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_is_amo = io_dis_uops_3_2_bits_is_amo_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_is_eret = io_dis_uops_3_2_bits_is_eret_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_is_sys_pc2epc = io_dis_uops_3_2_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_is_rocc = io_dis_uops_3_2_bits_is_rocc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_is_mov = io_dis_uops_3_2_bits_is_mov_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_ftq_idx = io_dis_uops_3_2_bits_ftq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_edge_inst = io_dis_uops_3_2_bits_edge_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_pc_lob = io_dis_uops_3_2_bits_pc_lob_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_taken = io_dis_uops_3_2_bits_taken_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_imm_rename = io_dis_uops_3_2_bits_imm_rename_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_imm_sel = io_dis_uops_3_2_bits_imm_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_pimm = io_dis_uops_3_2_bits_pimm_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_imm_packed = io_dis_uops_3_2_bits_imm_packed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_op1_sel = io_dis_uops_3_2_bits_op1_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_op2_sel = io_dis_uops_3_2_bits_op2_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_fp_ctrl_ldst = io_dis_uops_3_2_bits_fp_ctrl_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_fp_ctrl_wen = io_dis_uops_3_2_bits_fp_ctrl_wen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_fp_ctrl_ren1 = io_dis_uops_3_2_bits_fp_ctrl_ren1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_fp_ctrl_ren2 = io_dis_uops_3_2_bits_fp_ctrl_ren2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_fp_ctrl_ren3 = io_dis_uops_3_2_bits_fp_ctrl_ren3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_fp_ctrl_swap12 = io_dis_uops_3_2_bits_fp_ctrl_swap12_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_fp_ctrl_swap23 = io_dis_uops_3_2_bits_fp_ctrl_swap23_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_fp_ctrl_typeTagIn = io_dis_uops_3_2_bits_fp_ctrl_typeTagIn_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_fp_ctrl_typeTagOut = io_dis_uops_3_2_bits_fp_ctrl_typeTagOut_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_fp_ctrl_fromint = io_dis_uops_3_2_bits_fp_ctrl_fromint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_fp_ctrl_toint = io_dis_uops_3_2_bits_fp_ctrl_toint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_fp_ctrl_fastpipe = io_dis_uops_3_2_bits_fp_ctrl_fastpipe_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_fp_ctrl_fma = io_dis_uops_3_2_bits_fp_ctrl_fma_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_fp_ctrl_div = io_dis_uops_3_2_bits_fp_ctrl_div_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_fp_ctrl_sqrt = io_dis_uops_3_2_bits_fp_ctrl_sqrt_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_fp_ctrl_wflags = io_dis_uops_3_2_bits_fp_ctrl_wflags_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_fp_ctrl_vec = io_dis_uops_3_2_bits_fp_ctrl_vec_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_rob_idx = io_dis_uops_3_2_bits_rob_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_ldq_idx = io_dis_uops_3_2_bits_ldq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_stq_idx = io_dis_uops_3_2_bits_stq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_rxq_idx = io_dis_uops_3_2_bits_rxq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_pdst = io_dis_uops_3_2_bits_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_prs1 = io_dis_uops_3_2_bits_prs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_prs2 = io_dis_uops_3_2_bits_prs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_prs3 = io_dis_uops_3_2_bits_prs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_ppred = io_dis_uops_3_2_bits_ppred_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_prs1_busy = io_dis_uops_3_2_bits_prs1_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_prs2_busy = io_dis_uops_3_2_bits_prs2_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_prs3_busy = io_dis_uops_3_2_bits_prs3_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_ppred_busy = io_dis_uops_3_2_bits_ppred_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_stale_pdst = io_dis_uops_3_2_bits_stale_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_exception = io_dis_uops_3_2_bits_exception_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_exc_cause = io_dis_uops_3_2_bits_exc_cause_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_mem_cmd = io_dis_uops_3_2_bits_mem_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_mem_size = io_dis_uops_3_2_bits_mem_size_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_mem_signed = io_dis_uops_3_2_bits_mem_signed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_uses_ldq = io_dis_uops_3_2_bits_uses_ldq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_uses_stq = io_dis_uops_3_2_bits_uses_stq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_is_unique = io_dis_uops_3_2_bits_is_unique_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_flush_on_commit = io_dis_uops_3_2_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_csr_cmd = io_dis_uops_3_2_bits_csr_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_ldst_is_rs1 = io_dis_uops_3_2_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_ldst = io_dis_uops_3_2_bits_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_lrs1 = io_dis_uops_3_2_bits_lrs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_lrs2 = io_dis_uops_3_2_bits_lrs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_lrs3 = io_dis_uops_3_2_bits_lrs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_dst_rtype = io_dis_uops_3_2_bits_dst_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_lrs1_rtype = io_dis_uops_3_2_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_lrs2_rtype = io_dis_uops_3_2_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_frs3_en = io_dis_uops_3_2_bits_frs3_en_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_fcn_dw = io_dis_uops_3_2_bits_fcn_dw_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_fcn_op = io_dis_uops_3_2_bits_fcn_op_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_fp_val = io_dis_uops_3_2_bits_fp_val_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_fp_rm = io_dis_uops_3_2_bits_fp_rm_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_fp_typ = io_dis_uops_3_2_bits_fp_typ_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_xcpt_pf_if = io_dis_uops_3_2_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_xcpt_ae_if = io_dis_uops_3_2_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_xcpt_ma_if = io_dis_uops_3_2_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_bp_debug_if = io_dis_uops_3_2_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_bp_xcpt_if = io_dis_uops_3_2_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_debug_fsrc = io_dis_uops_3_2_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_3_2_bits_debug_tsrc = io_dis_uops_3_2_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_valid = io_dis_uops_2_0_valid_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_inst = io_dis_uops_2_0_bits_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_debug_inst = io_dis_uops_2_0_bits_debug_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_is_rvc = io_dis_uops_2_0_bits_is_rvc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_debug_pc = io_dis_uops_2_0_bits_debug_pc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_iq_type_0 = io_dis_uops_2_0_bits_iq_type_0_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_iq_type_1 = io_dis_uops_2_0_bits_iq_type_1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_iq_type_2 = io_dis_uops_2_0_bits_iq_type_2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_iq_type_3 = io_dis_uops_2_0_bits_iq_type_3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fu_code_0 = io_dis_uops_2_0_bits_fu_code_0_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fu_code_1 = io_dis_uops_2_0_bits_fu_code_1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fu_code_2 = io_dis_uops_2_0_bits_fu_code_2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fu_code_3 = io_dis_uops_2_0_bits_fu_code_3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fu_code_4 = io_dis_uops_2_0_bits_fu_code_4_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fu_code_5 = io_dis_uops_2_0_bits_fu_code_5_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fu_code_6 = io_dis_uops_2_0_bits_fu_code_6_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fu_code_7 = io_dis_uops_2_0_bits_fu_code_7_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fu_code_8 = io_dis_uops_2_0_bits_fu_code_8_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fu_code_9 = io_dis_uops_2_0_bits_fu_code_9_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_iw_issued = io_dis_uops_2_0_bits_iw_issued_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_iw_issued_partial_agen = io_dis_uops_2_0_bits_iw_issued_partial_agen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_iw_issued_partial_dgen = io_dis_uops_2_0_bits_iw_issued_partial_dgen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_iw_p1_speculative_child = io_dis_uops_2_0_bits_iw_p1_speculative_child_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_iw_p2_speculative_child = io_dis_uops_2_0_bits_iw_p2_speculative_child_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_iw_p1_bypass_hint = io_dis_uops_2_0_bits_iw_p1_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_iw_p2_bypass_hint = io_dis_uops_2_0_bits_iw_p2_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_iw_p3_bypass_hint = io_dis_uops_2_0_bits_iw_p3_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_dis_col_sel = io_dis_uops_2_0_bits_dis_col_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_br_mask = io_dis_uops_2_0_bits_br_mask_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_br_tag = io_dis_uops_2_0_bits_br_tag_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_br_type = io_dis_uops_2_0_bits_br_type_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_is_sfb = io_dis_uops_2_0_bits_is_sfb_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_is_fence = io_dis_uops_2_0_bits_is_fence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_is_fencei = io_dis_uops_2_0_bits_is_fencei_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_is_sfence = io_dis_uops_2_0_bits_is_sfence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_is_amo = io_dis_uops_2_0_bits_is_amo_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_is_eret = io_dis_uops_2_0_bits_is_eret_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_is_sys_pc2epc = io_dis_uops_2_0_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_is_rocc = io_dis_uops_2_0_bits_is_rocc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_is_mov = io_dis_uops_2_0_bits_is_mov_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_ftq_idx = io_dis_uops_2_0_bits_ftq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_edge_inst = io_dis_uops_2_0_bits_edge_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_pc_lob = io_dis_uops_2_0_bits_pc_lob_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_taken = io_dis_uops_2_0_bits_taken_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_imm_rename = io_dis_uops_2_0_bits_imm_rename_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_imm_sel = io_dis_uops_2_0_bits_imm_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_pimm = io_dis_uops_2_0_bits_pimm_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_imm_packed = io_dis_uops_2_0_bits_imm_packed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_op1_sel = io_dis_uops_2_0_bits_op1_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_op2_sel = io_dis_uops_2_0_bits_op2_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fp_ctrl_ldst = io_dis_uops_2_0_bits_fp_ctrl_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fp_ctrl_wen = io_dis_uops_2_0_bits_fp_ctrl_wen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fp_ctrl_ren1 = io_dis_uops_2_0_bits_fp_ctrl_ren1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fp_ctrl_ren2 = io_dis_uops_2_0_bits_fp_ctrl_ren2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fp_ctrl_ren3 = io_dis_uops_2_0_bits_fp_ctrl_ren3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fp_ctrl_swap12 = io_dis_uops_2_0_bits_fp_ctrl_swap12_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fp_ctrl_swap23 = io_dis_uops_2_0_bits_fp_ctrl_swap23_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fp_ctrl_typeTagIn = io_dis_uops_2_0_bits_fp_ctrl_typeTagIn_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fp_ctrl_typeTagOut = io_dis_uops_2_0_bits_fp_ctrl_typeTagOut_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fp_ctrl_fromint = io_dis_uops_2_0_bits_fp_ctrl_fromint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fp_ctrl_toint = io_dis_uops_2_0_bits_fp_ctrl_toint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fp_ctrl_fastpipe = io_dis_uops_2_0_bits_fp_ctrl_fastpipe_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fp_ctrl_fma = io_dis_uops_2_0_bits_fp_ctrl_fma_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fp_ctrl_div = io_dis_uops_2_0_bits_fp_ctrl_div_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fp_ctrl_sqrt = io_dis_uops_2_0_bits_fp_ctrl_sqrt_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fp_ctrl_wflags = io_dis_uops_2_0_bits_fp_ctrl_wflags_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fp_ctrl_vec = io_dis_uops_2_0_bits_fp_ctrl_vec_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_rob_idx = io_dis_uops_2_0_bits_rob_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_ldq_idx = io_dis_uops_2_0_bits_ldq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_stq_idx = io_dis_uops_2_0_bits_stq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_rxq_idx = io_dis_uops_2_0_bits_rxq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_pdst = io_dis_uops_2_0_bits_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_prs1 = io_dis_uops_2_0_bits_prs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_prs2 = io_dis_uops_2_0_bits_prs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_prs3 = io_dis_uops_2_0_bits_prs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_ppred = io_dis_uops_2_0_bits_ppred_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_prs1_busy = io_dis_uops_2_0_bits_prs1_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_prs2_busy = io_dis_uops_2_0_bits_prs2_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_prs3_busy = io_dis_uops_2_0_bits_prs3_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_ppred_busy = io_dis_uops_2_0_bits_ppred_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_stale_pdst = io_dis_uops_2_0_bits_stale_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_exception = io_dis_uops_2_0_bits_exception_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_exc_cause = io_dis_uops_2_0_bits_exc_cause_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_mem_cmd = io_dis_uops_2_0_bits_mem_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_mem_size = io_dis_uops_2_0_bits_mem_size_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_mem_signed = io_dis_uops_2_0_bits_mem_signed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_uses_ldq = io_dis_uops_2_0_bits_uses_ldq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_uses_stq = io_dis_uops_2_0_bits_uses_stq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_is_unique = io_dis_uops_2_0_bits_is_unique_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_flush_on_commit = io_dis_uops_2_0_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_csr_cmd = io_dis_uops_2_0_bits_csr_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_ldst_is_rs1 = io_dis_uops_2_0_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_ldst = io_dis_uops_2_0_bits_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_lrs1 = io_dis_uops_2_0_bits_lrs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_lrs2 = io_dis_uops_2_0_bits_lrs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_lrs3 = io_dis_uops_2_0_bits_lrs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_dst_rtype = io_dis_uops_2_0_bits_dst_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_lrs1_rtype = io_dis_uops_2_0_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_lrs2_rtype = io_dis_uops_2_0_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_frs3_en = io_dis_uops_2_0_bits_frs3_en_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fcn_dw = io_dis_uops_2_0_bits_fcn_dw_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fcn_op = io_dis_uops_2_0_bits_fcn_op_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fp_val = io_dis_uops_2_0_bits_fp_val_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fp_rm = io_dis_uops_2_0_bits_fp_rm_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_fp_typ = io_dis_uops_2_0_bits_fp_typ_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_xcpt_pf_if = io_dis_uops_2_0_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_xcpt_ae_if = io_dis_uops_2_0_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_xcpt_ma_if = io_dis_uops_2_0_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_bp_debug_if = io_dis_uops_2_0_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_bp_xcpt_if = io_dis_uops_2_0_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_debug_fsrc = io_dis_uops_2_0_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_0_bits_debug_tsrc = io_dis_uops_2_0_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_valid = io_dis_uops_2_1_valid_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_inst = io_dis_uops_2_1_bits_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_debug_inst = io_dis_uops_2_1_bits_debug_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_is_rvc = io_dis_uops_2_1_bits_is_rvc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_debug_pc = io_dis_uops_2_1_bits_debug_pc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_iq_type_0 = io_dis_uops_2_1_bits_iq_type_0_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_iq_type_1 = io_dis_uops_2_1_bits_iq_type_1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_iq_type_2 = io_dis_uops_2_1_bits_iq_type_2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_iq_type_3 = io_dis_uops_2_1_bits_iq_type_3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fu_code_0 = io_dis_uops_2_1_bits_fu_code_0_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fu_code_1 = io_dis_uops_2_1_bits_fu_code_1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fu_code_2 = io_dis_uops_2_1_bits_fu_code_2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fu_code_3 = io_dis_uops_2_1_bits_fu_code_3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fu_code_4 = io_dis_uops_2_1_bits_fu_code_4_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fu_code_5 = io_dis_uops_2_1_bits_fu_code_5_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fu_code_6 = io_dis_uops_2_1_bits_fu_code_6_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fu_code_7 = io_dis_uops_2_1_bits_fu_code_7_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fu_code_8 = io_dis_uops_2_1_bits_fu_code_8_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fu_code_9 = io_dis_uops_2_1_bits_fu_code_9_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_iw_issued = io_dis_uops_2_1_bits_iw_issued_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_iw_issued_partial_agen = io_dis_uops_2_1_bits_iw_issued_partial_agen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_iw_issued_partial_dgen = io_dis_uops_2_1_bits_iw_issued_partial_dgen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_iw_p1_speculative_child = io_dis_uops_2_1_bits_iw_p1_speculative_child_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_iw_p2_speculative_child = io_dis_uops_2_1_bits_iw_p2_speculative_child_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_iw_p1_bypass_hint = io_dis_uops_2_1_bits_iw_p1_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_iw_p2_bypass_hint = io_dis_uops_2_1_bits_iw_p2_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_iw_p3_bypass_hint = io_dis_uops_2_1_bits_iw_p3_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_dis_col_sel = io_dis_uops_2_1_bits_dis_col_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_br_mask = io_dis_uops_2_1_bits_br_mask_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_br_tag = io_dis_uops_2_1_bits_br_tag_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_br_type = io_dis_uops_2_1_bits_br_type_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_is_sfb = io_dis_uops_2_1_bits_is_sfb_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_is_fence = io_dis_uops_2_1_bits_is_fence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_is_fencei = io_dis_uops_2_1_bits_is_fencei_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_is_sfence = io_dis_uops_2_1_bits_is_sfence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_is_amo = io_dis_uops_2_1_bits_is_amo_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_is_eret = io_dis_uops_2_1_bits_is_eret_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_is_sys_pc2epc = io_dis_uops_2_1_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_is_rocc = io_dis_uops_2_1_bits_is_rocc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_is_mov = io_dis_uops_2_1_bits_is_mov_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_ftq_idx = io_dis_uops_2_1_bits_ftq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_edge_inst = io_dis_uops_2_1_bits_edge_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_pc_lob = io_dis_uops_2_1_bits_pc_lob_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_taken = io_dis_uops_2_1_bits_taken_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_imm_rename = io_dis_uops_2_1_bits_imm_rename_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_imm_sel = io_dis_uops_2_1_bits_imm_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_pimm = io_dis_uops_2_1_bits_pimm_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_imm_packed = io_dis_uops_2_1_bits_imm_packed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_op1_sel = io_dis_uops_2_1_bits_op1_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_op2_sel = io_dis_uops_2_1_bits_op2_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fp_ctrl_ldst = io_dis_uops_2_1_bits_fp_ctrl_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fp_ctrl_wen = io_dis_uops_2_1_bits_fp_ctrl_wen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fp_ctrl_ren1 = io_dis_uops_2_1_bits_fp_ctrl_ren1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fp_ctrl_ren2 = io_dis_uops_2_1_bits_fp_ctrl_ren2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fp_ctrl_ren3 = io_dis_uops_2_1_bits_fp_ctrl_ren3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fp_ctrl_swap12 = io_dis_uops_2_1_bits_fp_ctrl_swap12_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fp_ctrl_swap23 = io_dis_uops_2_1_bits_fp_ctrl_swap23_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fp_ctrl_typeTagIn = io_dis_uops_2_1_bits_fp_ctrl_typeTagIn_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fp_ctrl_typeTagOut = io_dis_uops_2_1_bits_fp_ctrl_typeTagOut_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fp_ctrl_fromint = io_dis_uops_2_1_bits_fp_ctrl_fromint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fp_ctrl_toint = io_dis_uops_2_1_bits_fp_ctrl_toint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fp_ctrl_fastpipe = io_dis_uops_2_1_bits_fp_ctrl_fastpipe_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fp_ctrl_fma = io_dis_uops_2_1_bits_fp_ctrl_fma_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fp_ctrl_div = io_dis_uops_2_1_bits_fp_ctrl_div_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fp_ctrl_sqrt = io_dis_uops_2_1_bits_fp_ctrl_sqrt_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fp_ctrl_wflags = io_dis_uops_2_1_bits_fp_ctrl_wflags_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fp_ctrl_vec = io_dis_uops_2_1_bits_fp_ctrl_vec_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_rob_idx = io_dis_uops_2_1_bits_rob_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_ldq_idx = io_dis_uops_2_1_bits_ldq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_stq_idx = io_dis_uops_2_1_bits_stq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_rxq_idx = io_dis_uops_2_1_bits_rxq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_pdst = io_dis_uops_2_1_bits_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_prs1 = io_dis_uops_2_1_bits_prs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_prs2 = io_dis_uops_2_1_bits_prs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_prs3 = io_dis_uops_2_1_bits_prs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_ppred = io_dis_uops_2_1_bits_ppred_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_prs1_busy = io_dis_uops_2_1_bits_prs1_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_prs2_busy = io_dis_uops_2_1_bits_prs2_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_prs3_busy = io_dis_uops_2_1_bits_prs3_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_ppred_busy = io_dis_uops_2_1_bits_ppred_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_stale_pdst = io_dis_uops_2_1_bits_stale_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_exception = io_dis_uops_2_1_bits_exception_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_exc_cause = io_dis_uops_2_1_bits_exc_cause_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_mem_cmd = io_dis_uops_2_1_bits_mem_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_mem_size = io_dis_uops_2_1_bits_mem_size_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_mem_signed = io_dis_uops_2_1_bits_mem_signed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_uses_ldq = io_dis_uops_2_1_bits_uses_ldq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_uses_stq = io_dis_uops_2_1_bits_uses_stq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_is_unique = io_dis_uops_2_1_bits_is_unique_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_flush_on_commit = io_dis_uops_2_1_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_csr_cmd = io_dis_uops_2_1_bits_csr_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_ldst_is_rs1 = io_dis_uops_2_1_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_ldst = io_dis_uops_2_1_bits_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_lrs1 = io_dis_uops_2_1_bits_lrs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_lrs2 = io_dis_uops_2_1_bits_lrs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_lrs3 = io_dis_uops_2_1_bits_lrs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_dst_rtype = io_dis_uops_2_1_bits_dst_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_lrs1_rtype = io_dis_uops_2_1_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_lrs2_rtype = io_dis_uops_2_1_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_frs3_en = io_dis_uops_2_1_bits_frs3_en_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fcn_dw = io_dis_uops_2_1_bits_fcn_dw_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fcn_op = io_dis_uops_2_1_bits_fcn_op_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fp_val = io_dis_uops_2_1_bits_fp_val_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fp_rm = io_dis_uops_2_1_bits_fp_rm_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_fp_typ = io_dis_uops_2_1_bits_fp_typ_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_xcpt_pf_if = io_dis_uops_2_1_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_xcpt_ae_if = io_dis_uops_2_1_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_xcpt_ma_if = io_dis_uops_2_1_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_bp_debug_if = io_dis_uops_2_1_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_bp_xcpt_if = io_dis_uops_2_1_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_debug_fsrc = io_dis_uops_2_1_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_1_bits_debug_tsrc = io_dis_uops_2_1_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_valid = io_dis_uops_2_2_valid_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_inst = io_dis_uops_2_2_bits_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_debug_inst = io_dis_uops_2_2_bits_debug_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_is_rvc = io_dis_uops_2_2_bits_is_rvc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_debug_pc = io_dis_uops_2_2_bits_debug_pc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_iq_type_0 = io_dis_uops_2_2_bits_iq_type_0_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_iq_type_1 = io_dis_uops_2_2_bits_iq_type_1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_iq_type_2 = io_dis_uops_2_2_bits_iq_type_2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_iq_type_3 = io_dis_uops_2_2_bits_iq_type_3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fu_code_0 = io_dis_uops_2_2_bits_fu_code_0_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fu_code_1 = io_dis_uops_2_2_bits_fu_code_1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fu_code_2 = io_dis_uops_2_2_bits_fu_code_2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fu_code_3 = io_dis_uops_2_2_bits_fu_code_3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fu_code_4 = io_dis_uops_2_2_bits_fu_code_4_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fu_code_5 = io_dis_uops_2_2_bits_fu_code_5_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fu_code_6 = io_dis_uops_2_2_bits_fu_code_6_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fu_code_7 = io_dis_uops_2_2_bits_fu_code_7_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fu_code_8 = io_dis_uops_2_2_bits_fu_code_8_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fu_code_9 = io_dis_uops_2_2_bits_fu_code_9_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_iw_issued = io_dis_uops_2_2_bits_iw_issued_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_iw_issued_partial_agen = io_dis_uops_2_2_bits_iw_issued_partial_agen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_iw_issued_partial_dgen = io_dis_uops_2_2_bits_iw_issued_partial_dgen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_iw_p1_speculative_child = io_dis_uops_2_2_bits_iw_p1_speculative_child_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_iw_p2_speculative_child = io_dis_uops_2_2_bits_iw_p2_speculative_child_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_iw_p1_bypass_hint = io_dis_uops_2_2_bits_iw_p1_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_iw_p2_bypass_hint = io_dis_uops_2_2_bits_iw_p2_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_iw_p3_bypass_hint = io_dis_uops_2_2_bits_iw_p3_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_dis_col_sel = io_dis_uops_2_2_bits_dis_col_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_br_mask = io_dis_uops_2_2_bits_br_mask_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_br_tag = io_dis_uops_2_2_bits_br_tag_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_br_type = io_dis_uops_2_2_bits_br_type_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_is_sfb = io_dis_uops_2_2_bits_is_sfb_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_is_fence = io_dis_uops_2_2_bits_is_fence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_is_fencei = io_dis_uops_2_2_bits_is_fencei_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_is_sfence = io_dis_uops_2_2_bits_is_sfence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_is_amo = io_dis_uops_2_2_bits_is_amo_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_is_eret = io_dis_uops_2_2_bits_is_eret_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_is_sys_pc2epc = io_dis_uops_2_2_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_is_rocc = io_dis_uops_2_2_bits_is_rocc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_is_mov = io_dis_uops_2_2_bits_is_mov_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_ftq_idx = io_dis_uops_2_2_bits_ftq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_edge_inst = io_dis_uops_2_2_bits_edge_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_pc_lob = io_dis_uops_2_2_bits_pc_lob_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_taken = io_dis_uops_2_2_bits_taken_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_imm_rename = io_dis_uops_2_2_bits_imm_rename_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_imm_sel = io_dis_uops_2_2_bits_imm_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_pimm = io_dis_uops_2_2_bits_pimm_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_imm_packed = io_dis_uops_2_2_bits_imm_packed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_op1_sel = io_dis_uops_2_2_bits_op1_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_op2_sel = io_dis_uops_2_2_bits_op2_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fp_ctrl_ldst = io_dis_uops_2_2_bits_fp_ctrl_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fp_ctrl_wen = io_dis_uops_2_2_bits_fp_ctrl_wen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fp_ctrl_ren1 = io_dis_uops_2_2_bits_fp_ctrl_ren1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fp_ctrl_ren2 = io_dis_uops_2_2_bits_fp_ctrl_ren2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fp_ctrl_ren3 = io_dis_uops_2_2_bits_fp_ctrl_ren3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fp_ctrl_swap12 = io_dis_uops_2_2_bits_fp_ctrl_swap12_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fp_ctrl_swap23 = io_dis_uops_2_2_bits_fp_ctrl_swap23_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fp_ctrl_typeTagIn = io_dis_uops_2_2_bits_fp_ctrl_typeTagIn_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fp_ctrl_typeTagOut = io_dis_uops_2_2_bits_fp_ctrl_typeTagOut_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fp_ctrl_fromint = io_dis_uops_2_2_bits_fp_ctrl_fromint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fp_ctrl_toint = io_dis_uops_2_2_bits_fp_ctrl_toint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fp_ctrl_fastpipe = io_dis_uops_2_2_bits_fp_ctrl_fastpipe_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fp_ctrl_fma = io_dis_uops_2_2_bits_fp_ctrl_fma_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fp_ctrl_div = io_dis_uops_2_2_bits_fp_ctrl_div_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fp_ctrl_sqrt = io_dis_uops_2_2_bits_fp_ctrl_sqrt_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fp_ctrl_wflags = io_dis_uops_2_2_bits_fp_ctrl_wflags_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fp_ctrl_vec = io_dis_uops_2_2_bits_fp_ctrl_vec_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_rob_idx = io_dis_uops_2_2_bits_rob_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_ldq_idx = io_dis_uops_2_2_bits_ldq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_stq_idx = io_dis_uops_2_2_bits_stq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_rxq_idx = io_dis_uops_2_2_bits_rxq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_pdst = io_dis_uops_2_2_bits_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_prs1 = io_dis_uops_2_2_bits_prs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_prs2 = io_dis_uops_2_2_bits_prs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_prs3 = io_dis_uops_2_2_bits_prs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_ppred = io_dis_uops_2_2_bits_ppred_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_prs1_busy = io_dis_uops_2_2_bits_prs1_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_prs2_busy = io_dis_uops_2_2_bits_prs2_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_prs3_busy = io_dis_uops_2_2_bits_prs3_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_ppred_busy = io_dis_uops_2_2_bits_ppred_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_stale_pdst = io_dis_uops_2_2_bits_stale_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_exception = io_dis_uops_2_2_bits_exception_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_exc_cause = io_dis_uops_2_2_bits_exc_cause_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_mem_cmd = io_dis_uops_2_2_bits_mem_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_mem_size = io_dis_uops_2_2_bits_mem_size_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_mem_signed = io_dis_uops_2_2_bits_mem_signed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_uses_ldq = io_dis_uops_2_2_bits_uses_ldq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_uses_stq = io_dis_uops_2_2_bits_uses_stq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_is_unique = io_dis_uops_2_2_bits_is_unique_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_flush_on_commit = io_dis_uops_2_2_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_csr_cmd = io_dis_uops_2_2_bits_csr_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_ldst_is_rs1 = io_dis_uops_2_2_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_ldst = io_dis_uops_2_2_bits_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_lrs1 = io_dis_uops_2_2_bits_lrs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_lrs2 = io_dis_uops_2_2_bits_lrs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_lrs3 = io_dis_uops_2_2_bits_lrs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_dst_rtype = io_dis_uops_2_2_bits_dst_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_lrs1_rtype = io_dis_uops_2_2_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_lrs2_rtype = io_dis_uops_2_2_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_frs3_en = io_dis_uops_2_2_bits_frs3_en_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fcn_dw = io_dis_uops_2_2_bits_fcn_dw_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fcn_op = io_dis_uops_2_2_bits_fcn_op_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fp_val = io_dis_uops_2_2_bits_fp_val_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fp_rm = io_dis_uops_2_2_bits_fp_rm_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_fp_typ = io_dis_uops_2_2_bits_fp_typ_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_xcpt_pf_if = io_dis_uops_2_2_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_xcpt_ae_if = io_dis_uops_2_2_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_xcpt_ma_if = io_dis_uops_2_2_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_bp_debug_if = io_dis_uops_2_2_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_bp_xcpt_if = io_dis_uops_2_2_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_debug_fsrc = io_dis_uops_2_2_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_2_2_bits_debug_tsrc = io_dis_uops_2_2_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_valid = io_dis_uops_1_0_valid_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_inst = io_dis_uops_1_0_bits_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_debug_inst = io_dis_uops_1_0_bits_debug_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_is_rvc = io_dis_uops_1_0_bits_is_rvc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_debug_pc = io_dis_uops_1_0_bits_debug_pc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_iq_type_0 = io_dis_uops_1_0_bits_iq_type_0_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_iq_type_1 = io_dis_uops_1_0_bits_iq_type_1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_iq_type_2 = io_dis_uops_1_0_bits_iq_type_2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_iq_type_3 = io_dis_uops_1_0_bits_iq_type_3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fu_code_0 = io_dis_uops_1_0_bits_fu_code_0_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fu_code_1 = io_dis_uops_1_0_bits_fu_code_1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fu_code_2 = io_dis_uops_1_0_bits_fu_code_2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fu_code_3 = io_dis_uops_1_0_bits_fu_code_3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fu_code_4 = io_dis_uops_1_0_bits_fu_code_4_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fu_code_5 = io_dis_uops_1_0_bits_fu_code_5_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fu_code_6 = io_dis_uops_1_0_bits_fu_code_6_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fu_code_7 = io_dis_uops_1_0_bits_fu_code_7_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fu_code_8 = io_dis_uops_1_0_bits_fu_code_8_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fu_code_9 = io_dis_uops_1_0_bits_fu_code_9_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_iw_issued = io_dis_uops_1_0_bits_iw_issued_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_iw_issued_partial_agen = io_dis_uops_1_0_bits_iw_issued_partial_agen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_iw_issued_partial_dgen = io_dis_uops_1_0_bits_iw_issued_partial_dgen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_iw_p1_speculative_child = io_dis_uops_1_0_bits_iw_p1_speculative_child_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_iw_p2_speculative_child = io_dis_uops_1_0_bits_iw_p2_speculative_child_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_iw_p1_bypass_hint = io_dis_uops_1_0_bits_iw_p1_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_iw_p2_bypass_hint = io_dis_uops_1_0_bits_iw_p2_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_iw_p3_bypass_hint = io_dis_uops_1_0_bits_iw_p3_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_dis_col_sel = io_dis_uops_1_0_bits_dis_col_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_br_mask = io_dis_uops_1_0_bits_br_mask_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_br_tag = io_dis_uops_1_0_bits_br_tag_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_br_type = io_dis_uops_1_0_bits_br_type_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_is_sfb = io_dis_uops_1_0_bits_is_sfb_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_is_fence = io_dis_uops_1_0_bits_is_fence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_is_fencei = io_dis_uops_1_0_bits_is_fencei_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_is_sfence = io_dis_uops_1_0_bits_is_sfence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_is_amo = io_dis_uops_1_0_bits_is_amo_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_is_eret = io_dis_uops_1_0_bits_is_eret_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_is_sys_pc2epc = io_dis_uops_1_0_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_is_rocc = io_dis_uops_1_0_bits_is_rocc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_is_mov = io_dis_uops_1_0_bits_is_mov_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_ftq_idx = io_dis_uops_1_0_bits_ftq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_edge_inst = io_dis_uops_1_0_bits_edge_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_pc_lob = io_dis_uops_1_0_bits_pc_lob_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_taken = io_dis_uops_1_0_bits_taken_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_imm_rename = io_dis_uops_1_0_bits_imm_rename_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_imm_sel = io_dis_uops_1_0_bits_imm_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_pimm = io_dis_uops_1_0_bits_pimm_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_imm_packed = io_dis_uops_1_0_bits_imm_packed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_op1_sel = io_dis_uops_1_0_bits_op1_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_op2_sel = io_dis_uops_1_0_bits_op2_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fp_ctrl_ldst = io_dis_uops_1_0_bits_fp_ctrl_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fp_ctrl_wen = io_dis_uops_1_0_bits_fp_ctrl_wen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fp_ctrl_ren1 = io_dis_uops_1_0_bits_fp_ctrl_ren1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fp_ctrl_ren2 = io_dis_uops_1_0_bits_fp_ctrl_ren2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fp_ctrl_ren3 = io_dis_uops_1_0_bits_fp_ctrl_ren3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fp_ctrl_swap12 = io_dis_uops_1_0_bits_fp_ctrl_swap12_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fp_ctrl_swap23 = io_dis_uops_1_0_bits_fp_ctrl_swap23_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fp_ctrl_typeTagIn = io_dis_uops_1_0_bits_fp_ctrl_typeTagIn_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fp_ctrl_typeTagOut = io_dis_uops_1_0_bits_fp_ctrl_typeTagOut_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fp_ctrl_fromint = io_dis_uops_1_0_bits_fp_ctrl_fromint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fp_ctrl_toint = io_dis_uops_1_0_bits_fp_ctrl_toint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fp_ctrl_fastpipe = io_dis_uops_1_0_bits_fp_ctrl_fastpipe_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fp_ctrl_fma = io_dis_uops_1_0_bits_fp_ctrl_fma_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fp_ctrl_div = io_dis_uops_1_0_bits_fp_ctrl_div_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fp_ctrl_sqrt = io_dis_uops_1_0_bits_fp_ctrl_sqrt_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fp_ctrl_wflags = io_dis_uops_1_0_bits_fp_ctrl_wflags_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fp_ctrl_vec = io_dis_uops_1_0_bits_fp_ctrl_vec_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_rob_idx = io_dis_uops_1_0_bits_rob_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_ldq_idx = io_dis_uops_1_0_bits_ldq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_stq_idx = io_dis_uops_1_0_bits_stq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_rxq_idx = io_dis_uops_1_0_bits_rxq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_pdst = io_dis_uops_1_0_bits_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_prs1 = io_dis_uops_1_0_bits_prs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_prs2 = io_dis_uops_1_0_bits_prs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_prs3 = io_dis_uops_1_0_bits_prs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_ppred = io_dis_uops_1_0_bits_ppred_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_prs1_busy = io_dis_uops_1_0_bits_prs1_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_prs2_busy = io_dis_uops_1_0_bits_prs2_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_prs3_busy = io_dis_uops_1_0_bits_prs3_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_ppred_busy = io_dis_uops_1_0_bits_ppred_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_stale_pdst = io_dis_uops_1_0_bits_stale_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_exception = io_dis_uops_1_0_bits_exception_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_exc_cause = io_dis_uops_1_0_bits_exc_cause_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_mem_cmd = io_dis_uops_1_0_bits_mem_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_mem_size = io_dis_uops_1_0_bits_mem_size_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_mem_signed = io_dis_uops_1_0_bits_mem_signed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_uses_ldq = io_dis_uops_1_0_bits_uses_ldq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_uses_stq = io_dis_uops_1_0_bits_uses_stq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_is_unique = io_dis_uops_1_0_bits_is_unique_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_flush_on_commit = io_dis_uops_1_0_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_csr_cmd = io_dis_uops_1_0_bits_csr_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_ldst_is_rs1 = io_dis_uops_1_0_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_ldst = io_dis_uops_1_0_bits_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_lrs1 = io_dis_uops_1_0_bits_lrs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_lrs2 = io_dis_uops_1_0_bits_lrs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_lrs3 = io_dis_uops_1_0_bits_lrs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_dst_rtype = io_dis_uops_1_0_bits_dst_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_lrs1_rtype = io_dis_uops_1_0_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_lrs2_rtype = io_dis_uops_1_0_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_frs3_en = io_dis_uops_1_0_bits_frs3_en_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fcn_dw = io_dis_uops_1_0_bits_fcn_dw_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fcn_op = io_dis_uops_1_0_bits_fcn_op_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fp_val = io_dis_uops_1_0_bits_fp_val_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fp_rm = io_dis_uops_1_0_bits_fp_rm_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_fp_typ = io_dis_uops_1_0_bits_fp_typ_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_xcpt_pf_if = io_dis_uops_1_0_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_xcpt_ae_if = io_dis_uops_1_0_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_xcpt_ma_if = io_dis_uops_1_0_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_bp_debug_if = io_dis_uops_1_0_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_bp_xcpt_if = io_dis_uops_1_0_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_debug_fsrc = io_dis_uops_1_0_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_0_bits_debug_tsrc = io_dis_uops_1_0_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_valid = io_dis_uops_1_1_valid_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_inst = io_dis_uops_1_1_bits_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_debug_inst = io_dis_uops_1_1_bits_debug_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_is_rvc = io_dis_uops_1_1_bits_is_rvc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_debug_pc = io_dis_uops_1_1_bits_debug_pc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_iq_type_0 = io_dis_uops_1_1_bits_iq_type_0_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_iq_type_1 = io_dis_uops_1_1_bits_iq_type_1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_iq_type_2 = io_dis_uops_1_1_bits_iq_type_2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_iq_type_3 = io_dis_uops_1_1_bits_iq_type_3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fu_code_0 = io_dis_uops_1_1_bits_fu_code_0_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fu_code_1 = io_dis_uops_1_1_bits_fu_code_1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fu_code_2 = io_dis_uops_1_1_bits_fu_code_2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fu_code_3 = io_dis_uops_1_1_bits_fu_code_3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fu_code_4 = io_dis_uops_1_1_bits_fu_code_4_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fu_code_5 = io_dis_uops_1_1_bits_fu_code_5_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fu_code_6 = io_dis_uops_1_1_bits_fu_code_6_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fu_code_7 = io_dis_uops_1_1_bits_fu_code_7_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fu_code_8 = io_dis_uops_1_1_bits_fu_code_8_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fu_code_9 = io_dis_uops_1_1_bits_fu_code_9_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_iw_issued = io_dis_uops_1_1_bits_iw_issued_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_iw_issued_partial_agen = io_dis_uops_1_1_bits_iw_issued_partial_agen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_iw_issued_partial_dgen = io_dis_uops_1_1_bits_iw_issued_partial_dgen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_iw_p1_speculative_child = io_dis_uops_1_1_bits_iw_p1_speculative_child_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_iw_p2_speculative_child = io_dis_uops_1_1_bits_iw_p2_speculative_child_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_iw_p1_bypass_hint = io_dis_uops_1_1_bits_iw_p1_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_iw_p2_bypass_hint = io_dis_uops_1_1_bits_iw_p2_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_iw_p3_bypass_hint = io_dis_uops_1_1_bits_iw_p3_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_dis_col_sel = io_dis_uops_1_1_bits_dis_col_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_br_mask = io_dis_uops_1_1_bits_br_mask_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_br_tag = io_dis_uops_1_1_bits_br_tag_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_br_type = io_dis_uops_1_1_bits_br_type_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_is_sfb = io_dis_uops_1_1_bits_is_sfb_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_is_fence = io_dis_uops_1_1_bits_is_fence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_is_fencei = io_dis_uops_1_1_bits_is_fencei_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_is_sfence = io_dis_uops_1_1_bits_is_sfence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_is_amo = io_dis_uops_1_1_bits_is_amo_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_is_eret = io_dis_uops_1_1_bits_is_eret_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_is_sys_pc2epc = io_dis_uops_1_1_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_is_rocc = io_dis_uops_1_1_bits_is_rocc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_is_mov = io_dis_uops_1_1_bits_is_mov_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_ftq_idx = io_dis_uops_1_1_bits_ftq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_edge_inst = io_dis_uops_1_1_bits_edge_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_pc_lob = io_dis_uops_1_1_bits_pc_lob_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_taken = io_dis_uops_1_1_bits_taken_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_imm_rename = io_dis_uops_1_1_bits_imm_rename_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_imm_sel = io_dis_uops_1_1_bits_imm_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_pimm = io_dis_uops_1_1_bits_pimm_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_imm_packed = io_dis_uops_1_1_bits_imm_packed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_op1_sel = io_dis_uops_1_1_bits_op1_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_op2_sel = io_dis_uops_1_1_bits_op2_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fp_ctrl_ldst = io_dis_uops_1_1_bits_fp_ctrl_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fp_ctrl_wen = io_dis_uops_1_1_bits_fp_ctrl_wen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fp_ctrl_ren1 = io_dis_uops_1_1_bits_fp_ctrl_ren1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fp_ctrl_ren2 = io_dis_uops_1_1_bits_fp_ctrl_ren2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fp_ctrl_ren3 = io_dis_uops_1_1_bits_fp_ctrl_ren3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fp_ctrl_swap12 = io_dis_uops_1_1_bits_fp_ctrl_swap12_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fp_ctrl_swap23 = io_dis_uops_1_1_bits_fp_ctrl_swap23_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fp_ctrl_typeTagIn = io_dis_uops_1_1_bits_fp_ctrl_typeTagIn_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fp_ctrl_typeTagOut = io_dis_uops_1_1_bits_fp_ctrl_typeTagOut_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fp_ctrl_fromint = io_dis_uops_1_1_bits_fp_ctrl_fromint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fp_ctrl_toint = io_dis_uops_1_1_bits_fp_ctrl_toint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fp_ctrl_fastpipe = io_dis_uops_1_1_bits_fp_ctrl_fastpipe_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fp_ctrl_fma = io_dis_uops_1_1_bits_fp_ctrl_fma_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fp_ctrl_div = io_dis_uops_1_1_bits_fp_ctrl_div_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fp_ctrl_sqrt = io_dis_uops_1_1_bits_fp_ctrl_sqrt_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fp_ctrl_wflags = io_dis_uops_1_1_bits_fp_ctrl_wflags_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fp_ctrl_vec = io_dis_uops_1_1_bits_fp_ctrl_vec_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_rob_idx = io_dis_uops_1_1_bits_rob_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_ldq_idx = io_dis_uops_1_1_bits_ldq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_stq_idx = io_dis_uops_1_1_bits_stq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_rxq_idx = io_dis_uops_1_1_bits_rxq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_pdst = io_dis_uops_1_1_bits_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_prs1 = io_dis_uops_1_1_bits_prs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_prs2 = io_dis_uops_1_1_bits_prs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_prs3 = io_dis_uops_1_1_bits_prs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_ppred = io_dis_uops_1_1_bits_ppred_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_prs1_busy = io_dis_uops_1_1_bits_prs1_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_prs2_busy = io_dis_uops_1_1_bits_prs2_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_prs3_busy = io_dis_uops_1_1_bits_prs3_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_ppred_busy = io_dis_uops_1_1_bits_ppred_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_stale_pdst = io_dis_uops_1_1_bits_stale_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_exception = io_dis_uops_1_1_bits_exception_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_exc_cause = io_dis_uops_1_1_bits_exc_cause_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_mem_cmd = io_dis_uops_1_1_bits_mem_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_mem_size = io_dis_uops_1_1_bits_mem_size_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_mem_signed = io_dis_uops_1_1_bits_mem_signed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_uses_ldq = io_dis_uops_1_1_bits_uses_ldq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_uses_stq = io_dis_uops_1_1_bits_uses_stq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_is_unique = io_dis_uops_1_1_bits_is_unique_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_flush_on_commit = io_dis_uops_1_1_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_csr_cmd = io_dis_uops_1_1_bits_csr_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_ldst_is_rs1 = io_dis_uops_1_1_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_ldst = io_dis_uops_1_1_bits_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_lrs1 = io_dis_uops_1_1_bits_lrs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_lrs2 = io_dis_uops_1_1_bits_lrs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_lrs3 = io_dis_uops_1_1_bits_lrs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_dst_rtype = io_dis_uops_1_1_bits_dst_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_lrs1_rtype = io_dis_uops_1_1_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_lrs2_rtype = io_dis_uops_1_1_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_frs3_en = io_dis_uops_1_1_bits_frs3_en_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fcn_dw = io_dis_uops_1_1_bits_fcn_dw_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fcn_op = io_dis_uops_1_1_bits_fcn_op_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fp_val = io_dis_uops_1_1_bits_fp_val_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fp_rm = io_dis_uops_1_1_bits_fp_rm_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_fp_typ = io_dis_uops_1_1_bits_fp_typ_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_xcpt_pf_if = io_dis_uops_1_1_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_xcpt_ae_if = io_dis_uops_1_1_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_xcpt_ma_if = io_dis_uops_1_1_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_bp_debug_if = io_dis_uops_1_1_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_bp_xcpt_if = io_dis_uops_1_1_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_debug_fsrc = io_dis_uops_1_1_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_1_bits_debug_tsrc = io_dis_uops_1_1_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_valid = io_dis_uops_1_2_valid_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_inst = io_dis_uops_1_2_bits_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_debug_inst = io_dis_uops_1_2_bits_debug_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_is_rvc = io_dis_uops_1_2_bits_is_rvc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_debug_pc = io_dis_uops_1_2_bits_debug_pc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_iq_type_0 = io_dis_uops_1_2_bits_iq_type_0_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_iq_type_1 = io_dis_uops_1_2_bits_iq_type_1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_iq_type_2 = io_dis_uops_1_2_bits_iq_type_2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_iq_type_3 = io_dis_uops_1_2_bits_iq_type_3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fu_code_0 = io_dis_uops_1_2_bits_fu_code_0_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fu_code_1 = io_dis_uops_1_2_bits_fu_code_1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fu_code_2 = io_dis_uops_1_2_bits_fu_code_2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fu_code_3 = io_dis_uops_1_2_bits_fu_code_3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fu_code_4 = io_dis_uops_1_2_bits_fu_code_4_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fu_code_5 = io_dis_uops_1_2_bits_fu_code_5_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fu_code_6 = io_dis_uops_1_2_bits_fu_code_6_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fu_code_7 = io_dis_uops_1_2_bits_fu_code_7_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fu_code_8 = io_dis_uops_1_2_bits_fu_code_8_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fu_code_9 = io_dis_uops_1_2_bits_fu_code_9_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_iw_issued = io_dis_uops_1_2_bits_iw_issued_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_iw_issued_partial_agen = io_dis_uops_1_2_bits_iw_issued_partial_agen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_iw_issued_partial_dgen = io_dis_uops_1_2_bits_iw_issued_partial_dgen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_iw_p1_speculative_child = io_dis_uops_1_2_bits_iw_p1_speculative_child_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_iw_p2_speculative_child = io_dis_uops_1_2_bits_iw_p2_speculative_child_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_iw_p1_bypass_hint = io_dis_uops_1_2_bits_iw_p1_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_iw_p2_bypass_hint = io_dis_uops_1_2_bits_iw_p2_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_iw_p3_bypass_hint = io_dis_uops_1_2_bits_iw_p3_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_dis_col_sel = io_dis_uops_1_2_bits_dis_col_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_br_mask = io_dis_uops_1_2_bits_br_mask_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_br_tag = io_dis_uops_1_2_bits_br_tag_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_br_type = io_dis_uops_1_2_bits_br_type_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_is_sfb = io_dis_uops_1_2_bits_is_sfb_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_is_fence = io_dis_uops_1_2_bits_is_fence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_is_fencei = io_dis_uops_1_2_bits_is_fencei_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_is_sfence = io_dis_uops_1_2_bits_is_sfence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_is_amo = io_dis_uops_1_2_bits_is_amo_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_is_eret = io_dis_uops_1_2_bits_is_eret_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_is_sys_pc2epc = io_dis_uops_1_2_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_is_rocc = io_dis_uops_1_2_bits_is_rocc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_is_mov = io_dis_uops_1_2_bits_is_mov_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_ftq_idx = io_dis_uops_1_2_bits_ftq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_edge_inst = io_dis_uops_1_2_bits_edge_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_pc_lob = io_dis_uops_1_2_bits_pc_lob_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_taken = io_dis_uops_1_2_bits_taken_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_imm_rename = io_dis_uops_1_2_bits_imm_rename_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_imm_sel = io_dis_uops_1_2_bits_imm_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_pimm = io_dis_uops_1_2_bits_pimm_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_imm_packed = io_dis_uops_1_2_bits_imm_packed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_op1_sel = io_dis_uops_1_2_bits_op1_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_op2_sel = io_dis_uops_1_2_bits_op2_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fp_ctrl_ldst = io_dis_uops_1_2_bits_fp_ctrl_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fp_ctrl_wen = io_dis_uops_1_2_bits_fp_ctrl_wen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fp_ctrl_ren1 = io_dis_uops_1_2_bits_fp_ctrl_ren1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fp_ctrl_ren2 = io_dis_uops_1_2_bits_fp_ctrl_ren2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fp_ctrl_ren3 = io_dis_uops_1_2_bits_fp_ctrl_ren3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fp_ctrl_swap12 = io_dis_uops_1_2_bits_fp_ctrl_swap12_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fp_ctrl_swap23 = io_dis_uops_1_2_bits_fp_ctrl_swap23_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fp_ctrl_typeTagIn = io_dis_uops_1_2_bits_fp_ctrl_typeTagIn_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fp_ctrl_typeTagOut = io_dis_uops_1_2_bits_fp_ctrl_typeTagOut_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fp_ctrl_fromint = io_dis_uops_1_2_bits_fp_ctrl_fromint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fp_ctrl_toint = io_dis_uops_1_2_bits_fp_ctrl_toint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fp_ctrl_fastpipe = io_dis_uops_1_2_bits_fp_ctrl_fastpipe_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fp_ctrl_fma = io_dis_uops_1_2_bits_fp_ctrl_fma_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fp_ctrl_div = io_dis_uops_1_2_bits_fp_ctrl_div_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fp_ctrl_sqrt = io_dis_uops_1_2_bits_fp_ctrl_sqrt_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fp_ctrl_wflags = io_dis_uops_1_2_bits_fp_ctrl_wflags_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fp_ctrl_vec = io_dis_uops_1_2_bits_fp_ctrl_vec_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_rob_idx = io_dis_uops_1_2_bits_rob_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_ldq_idx = io_dis_uops_1_2_bits_ldq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_stq_idx = io_dis_uops_1_2_bits_stq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_rxq_idx = io_dis_uops_1_2_bits_rxq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_pdst = io_dis_uops_1_2_bits_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_prs1 = io_dis_uops_1_2_bits_prs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_prs2 = io_dis_uops_1_2_bits_prs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_prs3 = io_dis_uops_1_2_bits_prs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_ppred = io_dis_uops_1_2_bits_ppred_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_prs1_busy = io_dis_uops_1_2_bits_prs1_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_prs2_busy = io_dis_uops_1_2_bits_prs2_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_prs3_busy = io_dis_uops_1_2_bits_prs3_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_ppred_busy = io_dis_uops_1_2_bits_ppred_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_stale_pdst = io_dis_uops_1_2_bits_stale_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_exception = io_dis_uops_1_2_bits_exception_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_exc_cause = io_dis_uops_1_2_bits_exc_cause_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_mem_cmd = io_dis_uops_1_2_bits_mem_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_mem_size = io_dis_uops_1_2_bits_mem_size_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_mem_signed = io_dis_uops_1_2_bits_mem_signed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_uses_ldq = io_dis_uops_1_2_bits_uses_ldq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_uses_stq = io_dis_uops_1_2_bits_uses_stq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_is_unique = io_dis_uops_1_2_bits_is_unique_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_flush_on_commit = io_dis_uops_1_2_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_csr_cmd = io_dis_uops_1_2_bits_csr_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_ldst_is_rs1 = io_dis_uops_1_2_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_ldst = io_dis_uops_1_2_bits_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_lrs1 = io_dis_uops_1_2_bits_lrs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_lrs2 = io_dis_uops_1_2_bits_lrs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_lrs3 = io_dis_uops_1_2_bits_lrs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_dst_rtype = io_dis_uops_1_2_bits_dst_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_lrs1_rtype = io_dis_uops_1_2_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_lrs2_rtype = io_dis_uops_1_2_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_frs3_en = io_dis_uops_1_2_bits_frs3_en_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fcn_dw = io_dis_uops_1_2_bits_fcn_dw_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fcn_op = io_dis_uops_1_2_bits_fcn_op_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fp_val = io_dis_uops_1_2_bits_fp_val_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fp_rm = io_dis_uops_1_2_bits_fp_rm_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_fp_typ = io_dis_uops_1_2_bits_fp_typ_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_xcpt_pf_if = io_dis_uops_1_2_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_xcpt_ae_if = io_dis_uops_1_2_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_xcpt_ma_if = io_dis_uops_1_2_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_bp_debug_if = io_dis_uops_1_2_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_bp_xcpt_if = io_dis_uops_1_2_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_debug_fsrc = io_dis_uops_1_2_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_1_2_bits_debug_tsrc = io_dis_uops_1_2_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_valid = io_dis_uops_0_0_valid_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_inst = io_dis_uops_0_0_bits_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_debug_inst = io_dis_uops_0_0_bits_debug_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_is_rvc = io_dis_uops_0_0_bits_is_rvc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_debug_pc = io_dis_uops_0_0_bits_debug_pc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_iq_type_0 = io_dis_uops_0_0_bits_iq_type_0_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_iq_type_1 = io_dis_uops_0_0_bits_iq_type_1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_iq_type_2 = io_dis_uops_0_0_bits_iq_type_2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_iq_type_3 = io_dis_uops_0_0_bits_iq_type_3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fu_code_0 = io_dis_uops_0_0_bits_fu_code_0_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fu_code_1 = io_dis_uops_0_0_bits_fu_code_1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fu_code_2 = io_dis_uops_0_0_bits_fu_code_2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fu_code_3 = io_dis_uops_0_0_bits_fu_code_3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fu_code_4 = io_dis_uops_0_0_bits_fu_code_4_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fu_code_5 = io_dis_uops_0_0_bits_fu_code_5_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fu_code_6 = io_dis_uops_0_0_bits_fu_code_6_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fu_code_7 = io_dis_uops_0_0_bits_fu_code_7_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fu_code_8 = io_dis_uops_0_0_bits_fu_code_8_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fu_code_9 = io_dis_uops_0_0_bits_fu_code_9_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_iw_issued = io_dis_uops_0_0_bits_iw_issued_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_iw_issued_partial_agen = io_dis_uops_0_0_bits_iw_issued_partial_agen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_iw_issued_partial_dgen = io_dis_uops_0_0_bits_iw_issued_partial_dgen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_iw_p1_speculative_child = io_dis_uops_0_0_bits_iw_p1_speculative_child_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_iw_p2_speculative_child = io_dis_uops_0_0_bits_iw_p2_speculative_child_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_iw_p1_bypass_hint = io_dis_uops_0_0_bits_iw_p1_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_iw_p2_bypass_hint = io_dis_uops_0_0_bits_iw_p2_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_iw_p3_bypass_hint = io_dis_uops_0_0_bits_iw_p3_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_dis_col_sel = io_dis_uops_0_0_bits_dis_col_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_br_mask = io_dis_uops_0_0_bits_br_mask_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_br_tag = io_dis_uops_0_0_bits_br_tag_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_br_type = io_dis_uops_0_0_bits_br_type_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_is_sfb = io_dis_uops_0_0_bits_is_sfb_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_is_fence = io_dis_uops_0_0_bits_is_fence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_is_fencei = io_dis_uops_0_0_bits_is_fencei_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_is_sfence = io_dis_uops_0_0_bits_is_sfence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_is_amo = io_dis_uops_0_0_bits_is_amo_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_is_eret = io_dis_uops_0_0_bits_is_eret_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_is_sys_pc2epc = io_dis_uops_0_0_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_is_rocc = io_dis_uops_0_0_bits_is_rocc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_is_mov = io_dis_uops_0_0_bits_is_mov_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_ftq_idx = io_dis_uops_0_0_bits_ftq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_edge_inst = io_dis_uops_0_0_bits_edge_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_pc_lob = io_dis_uops_0_0_bits_pc_lob_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_taken = io_dis_uops_0_0_bits_taken_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_imm_rename = io_dis_uops_0_0_bits_imm_rename_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_imm_sel = io_dis_uops_0_0_bits_imm_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_pimm = io_dis_uops_0_0_bits_pimm_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_imm_packed = io_dis_uops_0_0_bits_imm_packed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_op1_sel = io_dis_uops_0_0_bits_op1_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_op2_sel = io_dis_uops_0_0_bits_op2_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fp_ctrl_ldst = io_dis_uops_0_0_bits_fp_ctrl_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fp_ctrl_wen = io_dis_uops_0_0_bits_fp_ctrl_wen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fp_ctrl_ren1 = io_dis_uops_0_0_bits_fp_ctrl_ren1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fp_ctrl_ren2 = io_dis_uops_0_0_bits_fp_ctrl_ren2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fp_ctrl_ren3 = io_dis_uops_0_0_bits_fp_ctrl_ren3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fp_ctrl_swap12 = io_dis_uops_0_0_bits_fp_ctrl_swap12_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fp_ctrl_swap23 = io_dis_uops_0_0_bits_fp_ctrl_swap23_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fp_ctrl_typeTagIn = io_dis_uops_0_0_bits_fp_ctrl_typeTagIn_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fp_ctrl_typeTagOut = io_dis_uops_0_0_bits_fp_ctrl_typeTagOut_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fp_ctrl_fromint = io_dis_uops_0_0_bits_fp_ctrl_fromint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fp_ctrl_toint = io_dis_uops_0_0_bits_fp_ctrl_toint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fp_ctrl_fastpipe = io_dis_uops_0_0_bits_fp_ctrl_fastpipe_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fp_ctrl_fma = io_dis_uops_0_0_bits_fp_ctrl_fma_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fp_ctrl_div = io_dis_uops_0_0_bits_fp_ctrl_div_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fp_ctrl_sqrt = io_dis_uops_0_0_bits_fp_ctrl_sqrt_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fp_ctrl_wflags = io_dis_uops_0_0_bits_fp_ctrl_wflags_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fp_ctrl_vec = io_dis_uops_0_0_bits_fp_ctrl_vec_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_rob_idx = io_dis_uops_0_0_bits_rob_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_ldq_idx = io_dis_uops_0_0_bits_ldq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_stq_idx = io_dis_uops_0_0_bits_stq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_rxq_idx = io_dis_uops_0_0_bits_rxq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_pdst = io_dis_uops_0_0_bits_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_prs1 = io_dis_uops_0_0_bits_prs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_prs2 = io_dis_uops_0_0_bits_prs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_prs3 = io_dis_uops_0_0_bits_prs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_ppred = io_dis_uops_0_0_bits_ppred_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_prs1_busy = io_dis_uops_0_0_bits_prs1_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_prs2_busy = io_dis_uops_0_0_bits_prs2_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_prs3_busy = io_dis_uops_0_0_bits_prs3_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_ppred_busy = io_dis_uops_0_0_bits_ppred_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_stale_pdst = io_dis_uops_0_0_bits_stale_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_exception = io_dis_uops_0_0_bits_exception_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_exc_cause = io_dis_uops_0_0_bits_exc_cause_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_mem_cmd = io_dis_uops_0_0_bits_mem_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_mem_size = io_dis_uops_0_0_bits_mem_size_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_mem_signed = io_dis_uops_0_0_bits_mem_signed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_uses_ldq = io_dis_uops_0_0_bits_uses_ldq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_uses_stq = io_dis_uops_0_0_bits_uses_stq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_is_unique = io_dis_uops_0_0_bits_is_unique_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_flush_on_commit = io_dis_uops_0_0_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_csr_cmd = io_dis_uops_0_0_bits_csr_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_ldst_is_rs1 = io_dis_uops_0_0_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_ldst = io_dis_uops_0_0_bits_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_lrs1 = io_dis_uops_0_0_bits_lrs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_lrs2 = io_dis_uops_0_0_bits_lrs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_lrs3 = io_dis_uops_0_0_bits_lrs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_dst_rtype = io_dis_uops_0_0_bits_dst_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_lrs1_rtype = io_dis_uops_0_0_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_lrs2_rtype = io_dis_uops_0_0_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_frs3_en = io_dis_uops_0_0_bits_frs3_en_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fcn_dw = io_dis_uops_0_0_bits_fcn_dw_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fcn_op = io_dis_uops_0_0_bits_fcn_op_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fp_val = io_dis_uops_0_0_bits_fp_val_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fp_rm = io_dis_uops_0_0_bits_fp_rm_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_fp_typ = io_dis_uops_0_0_bits_fp_typ_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_xcpt_pf_if = io_dis_uops_0_0_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_xcpt_ae_if = io_dis_uops_0_0_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_xcpt_ma_if = io_dis_uops_0_0_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_bp_debug_if = io_dis_uops_0_0_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_bp_xcpt_if = io_dis_uops_0_0_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_debug_fsrc = io_dis_uops_0_0_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_0_bits_debug_tsrc = io_dis_uops_0_0_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_valid = io_dis_uops_0_1_valid_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_inst = io_dis_uops_0_1_bits_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_debug_inst = io_dis_uops_0_1_bits_debug_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_is_rvc = io_dis_uops_0_1_bits_is_rvc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_debug_pc = io_dis_uops_0_1_bits_debug_pc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_iq_type_0 = io_dis_uops_0_1_bits_iq_type_0_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_iq_type_1 = io_dis_uops_0_1_bits_iq_type_1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_iq_type_2 = io_dis_uops_0_1_bits_iq_type_2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_iq_type_3 = io_dis_uops_0_1_bits_iq_type_3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fu_code_0 = io_dis_uops_0_1_bits_fu_code_0_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fu_code_1 = io_dis_uops_0_1_bits_fu_code_1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fu_code_2 = io_dis_uops_0_1_bits_fu_code_2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fu_code_3 = io_dis_uops_0_1_bits_fu_code_3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fu_code_4 = io_dis_uops_0_1_bits_fu_code_4_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fu_code_5 = io_dis_uops_0_1_bits_fu_code_5_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fu_code_6 = io_dis_uops_0_1_bits_fu_code_6_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fu_code_7 = io_dis_uops_0_1_bits_fu_code_7_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fu_code_8 = io_dis_uops_0_1_bits_fu_code_8_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fu_code_9 = io_dis_uops_0_1_bits_fu_code_9_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_iw_issued = io_dis_uops_0_1_bits_iw_issued_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_iw_issued_partial_agen = io_dis_uops_0_1_bits_iw_issued_partial_agen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_iw_issued_partial_dgen = io_dis_uops_0_1_bits_iw_issued_partial_dgen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_iw_p1_speculative_child = io_dis_uops_0_1_bits_iw_p1_speculative_child_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_iw_p2_speculative_child = io_dis_uops_0_1_bits_iw_p2_speculative_child_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_iw_p1_bypass_hint = io_dis_uops_0_1_bits_iw_p1_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_iw_p2_bypass_hint = io_dis_uops_0_1_bits_iw_p2_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_iw_p3_bypass_hint = io_dis_uops_0_1_bits_iw_p3_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_dis_col_sel = io_dis_uops_0_1_bits_dis_col_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_br_mask = io_dis_uops_0_1_bits_br_mask_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_br_tag = io_dis_uops_0_1_bits_br_tag_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_br_type = io_dis_uops_0_1_bits_br_type_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_is_sfb = io_dis_uops_0_1_bits_is_sfb_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_is_fence = io_dis_uops_0_1_bits_is_fence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_is_fencei = io_dis_uops_0_1_bits_is_fencei_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_is_sfence = io_dis_uops_0_1_bits_is_sfence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_is_amo = io_dis_uops_0_1_bits_is_amo_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_is_eret = io_dis_uops_0_1_bits_is_eret_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_is_sys_pc2epc = io_dis_uops_0_1_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_is_rocc = io_dis_uops_0_1_bits_is_rocc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_is_mov = io_dis_uops_0_1_bits_is_mov_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_ftq_idx = io_dis_uops_0_1_bits_ftq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_edge_inst = io_dis_uops_0_1_bits_edge_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_pc_lob = io_dis_uops_0_1_bits_pc_lob_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_taken = io_dis_uops_0_1_bits_taken_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_imm_rename = io_dis_uops_0_1_bits_imm_rename_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_imm_sel = io_dis_uops_0_1_bits_imm_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_pimm = io_dis_uops_0_1_bits_pimm_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_imm_packed = io_dis_uops_0_1_bits_imm_packed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_op1_sel = io_dis_uops_0_1_bits_op1_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_op2_sel = io_dis_uops_0_1_bits_op2_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fp_ctrl_ldst = io_dis_uops_0_1_bits_fp_ctrl_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fp_ctrl_wen = io_dis_uops_0_1_bits_fp_ctrl_wen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fp_ctrl_ren1 = io_dis_uops_0_1_bits_fp_ctrl_ren1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fp_ctrl_ren2 = io_dis_uops_0_1_bits_fp_ctrl_ren2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fp_ctrl_ren3 = io_dis_uops_0_1_bits_fp_ctrl_ren3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fp_ctrl_swap12 = io_dis_uops_0_1_bits_fp_ctrl_swap12_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fp_ctrl_swap23 = io_dis_uops_0_1_bits_fp_ctrl_swap23_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fp_ctrl_typeTagIn = io_dis_uops_0_1_bits_fp_ctrl_typeTagIn_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fp_ctrl_typeTagOut = io_dis_uops_0_1_bits_fp_ctrl_typeTagOut_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fp_ctrl_fromint = io_dis_uops_0_1_bits_fp_ctrl_fromint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fp_ctrl_toint = io_dis_uops_0_1_bits_fp_ctrl_toint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fp_ctrl_fastpipe = io_dis_uops_0_1_bits_fp_ctrl_fastpipe_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fp_ctrl_fma = io_dis_uops_0_1_bits_fp_ctrl_fma_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fp_ctrl_div = io_dis_uops_0_1_bits_fp_ctrl_div_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fp_ctrl_sqrt = io_dis_uops_0_1_bits_fp_ctrl_sqrt_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fp_ctrl_wflags = io_dis_uops_0_1_bits_fp_ctrl_wflags_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fp_ctrl_vec = io_dis_uops_0_1_bits_fp_ctrl_vec_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_rob_idx = io_dis_uops_0_1_bits_rob_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_ldq_idx = io_dis_uops_0_1_bits_ldq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_stq_idx = io_dis_uops_0_1_bits_stq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_rxq_idx = io_dis_uops_0_1_bits_rxq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_pdst = io_dis_uops_0_1_bits_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_prs1 = io_dis_uops_0_1_bits_prs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_prs2 = io_dis_uops_0_1_bits_prs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_prs3 = io_dis_uops_0_1_bits_prs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_ppred = io_dis_uops_0_1_bits_ppred_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_prs1_busy = io_dis_uops_0_1_bits_prs1_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_prs2_busy = io_dis_uops_0_1_bits_prs2_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_prs3_busy = io_dis_uops_0_1_bits_prs3_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_ppred_busy = io_dis_uops_0_1_bits_ppred_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_stale_pdst = io_dis_uops_0_1_bits_stale_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_exception = io_dis_uops_0_1_bits_exception_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_exc_cause = io_dis_uops_0_1_bits_exc_cause_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_mem_cmd = io_dis_uops_0_1_bits_mem_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_mem_size = io_dis_uops_0_1_bits_mem_size_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_mem_signed = io_dis_uops_0_1_bits_mem_signed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_uses_ldq = io_dis_uops_0_1_bits_uses_ldq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_uses_stq = io_dis_uops_0_1_bits_uses_stq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_is_unique = io_dis_uops_0_1_bits_is_unique_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_flush_on_commit = io_dis_uops_0_1_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_csr_cmd = io_dis_uops_0_1_bits_csr_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_ldst_is_rs1 = io_dis_uops_0_1_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_ldst = io_dis_uops_0_1_bits_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_lrs1 = io_dis_uops_0_1_bits_lrs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_lrs2 = io_dis_uops_0_1_bits_lrs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_lrs3 = io_dis_uops_0_1_bits_lrs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_dst_rtype = io_dis_uops_0_1_bits_dst_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_lrs1_rtype = io_dis_uops_0_1_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_lrs2_rtype = io_dis_uops_0_1_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_frs3_en = io_dis_uops_0_1_bits_frs3_en_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fcn_dw = io_dis_uops_0_1_bits_fcn_dw_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fcn_op = io_dis_uops_0_1_bits_fcn_op_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fp_val = io_dis_uops_0_1_bits_fp_val_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fp_rm = io_dis_uops_0_1_bits_fp_rm_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_fp_typ = io_dis_uops_0_1_bits_fp_typ_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_xcpt_pf_if = io_dis_uops_0_1_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_xcpt_ae_if = io_dis_uops_0_1_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_xcpt_ma_if = io_dis_uops_0_1_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_bp_debug_if = io_dis_uops_0_1_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_bp_xcpt_if = io_dis_uops_0_1_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_debug_fsrc = io_dis_uops_0_1_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_1_bits_debug_tsrc = io_dis_uops_0_1_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_valid = io_dis_uops_0_2_valid_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_inst = io_dis_uops_0_2_bits_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_debug_inst = io_dis_uops_0_2_bits_debug_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_is_rvc = io_dis_uops_0_2_bits_is_rvc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_debug_pc = io_dis_uops_0_2_bits_debug_pc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_iq_type_0 = io_dis_uops_0_2_bits_iq_type_0_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_iq_type_1 = io_dis_uops_0_2_bits_iq_type_1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_iq_type_2 = io_dis_uops_0_2_bits_iq_type_2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_iq_type_3 = io_dis_uops_0_2_bits_iq_type_3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fu_code_0 = io_dis_uops_0_2_bits_fu_code_0_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fu_code_1 = io_dis_uops_0_2_bits_fu_code_1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fu_code_2 = io_dis_uops_0_2_bits_fu_code_2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fu_code_3 = io_dis_uops_0_2_bits_fu_code_3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fu_code_4 = io_dis_uops_0_2_bits_fu_code_4_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fu_code_5 = io_dis_uops_0_2_bits_fu_code_5_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fu_code_6 = io_dis_uops_0_2_bits_fu_code_6_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fu_code_7 = io_dis_uops_0_2_bits_fu_code_7_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fu_code_8 = io_dis_uops_0_2_bits_fu_code_8_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fu_code_9 = io_dis_uops_0_2_bits_fu_code_9_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_iw_issued = io_dis_uops_0_2_bits_iw_issued_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_iw_issued_partial_agen = io_dis_uops_0_2_bits_iw_issued_partial_agen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_iw_issued_partial_dgen = io_dis_uops_0_2_bits_iw_issued_partial_dgen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_iw_p1_speculative_child = io_dis_uops_0_2_bits_iw_p1_speculative_child_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_iw_p2_speculative_child = io_dis_uops_0_2_bits_iw_p2_speculative_child_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_iw_p1_bypass_hint = io_dis_uops_0_2_bits_iw_p1_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_iw_p2_bypass_hint = io_dis_uops_0_2_bits_iw_p2_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_iw_p3_bypass_hint = io_dis_uops_0_2_bits_iw_p3_bypass_hint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_dis_col_sel = io_dis_uops_0_2_bits_dis_col_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_br_mask = io_dis_uops_0_2_bits_br_mask_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_br_tag = io_dis_uops_0_2_bits_br_tag_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_br_type = io_dis_uops_0_2_bits_br_type_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_is_sfb = io_dis_uops_0_2_bits_is_sfb_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_is_fence = io_dis_uops_0_2_bits_is_fence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_is_fencei = io_dis_uops_0_2_bits_is_fencei_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_is_sfence = io_dis_uops_0_2_bits_is_sfence_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_is_amo = io_dis_uops_0_2_bits_is_amo_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_is_eret = io_dis_uops_0_2_bits_is_eret_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_is_sys_pc2epc = io_dis_uops_0_2_bits_is_sys_pc2epc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_is_rocc = io_dis_uops_0_2_bits_is_rocc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_is_mov = io_dis_uops_0_2_bits_is_mov_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_ftq_idx = io_dis_uops_0_2_bits_ftq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_edge_inst = io_dis_uops_0_2_bits_edge_inst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_pc_lob = io_dis_uops_0_2_bits_pc_lob_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_taken = io_dis_uops_0_2_bits_taken_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_imm_rename = io_dis_uops_0_2_bits_imm_rename_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_imm_sel = io_dis_uops_0_2_bits_imm_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_pimm = io_dis_uops_0_2_bits_pimm_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_imm_packed = io_dis_uops_0_2_bits_imm_packed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_op1_sel = io_dis_uops_0_2_bits_op1_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_op2_sel = io_dis_uops_0_2_bits_op2_sel_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fp_ctrl_ldst = io_dis_uops_0_2_bits_fp_ctrl_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fp_ctrl_wen = io_dis_uops_0_2_bits_fp_ctrl_wen_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fp_ctrl_ren1 = io_dis_uops_0_2_bits_fp_ctrl_ren1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fp_ctrl_ren2 = io_dis_uops_0_2_bits_fp_ctrl_ren2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fp_ctrl_ren3 = io_dis_uops_0_2_bits_fp_ctrl_ren3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fp_ctrl_swap12 = io_dis_uops_0_2_bits_fp_ctrl_swap12_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fp_ctrl_swap23 = io_dis_uops_0_2_bits_fp_ctrl_swap23_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fp_ctrl_typeTagIn = io_dis_uops_0_2_bits_fp_ctrl_typeTagIn_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fp_ctrl_typeTagOut = io_dis_uops_0_2_bits_fp_ctrl_typeTagOut_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fp_ctrl_fromint = io_dis_uops_0_2_bits_fp_ctrl_fromint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fp_ctrl_toint = io_dis_uops_0_2_bits_fp_ctrl_toint_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fp_ctrl_fastpipe = io_dis_uops_0_2_bits_fp_ctrl_fastpipe_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fp_ctrl_fma = io_dis_uops_0_2_bits_fp_ctrl_fma_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fp_ctrl_div = io_dis_uops_0_2_bits_fp_ctrl_div_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fp_ctrl_sqrt = io_dis_uops_0_2_bits_fp_ctrl_sqrt_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fp_ctrl_wflags = io_dis_uops_0_2_bits_fp_ctrl_wflags_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fp_ctrl_vec = io_dis_uops_0_2_bits_fp_ctrl_vec_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_rob_idx = io_dis_uops_0_2_bits_rob_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_ldq_idx = io_dis_uops_0_2_bits_ldq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_stq_idx = io_dis_uops_0_2_bits_stq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_rxq_idx = io_dis_uops_0_2_bits_rxq_idx_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_pdst = io_dis_uops_0_2_bits_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_prs1 = io_dis_uops_0_2_bits_prs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_prs2 = io_dis_uops_0_2_bits_prs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_prs3 = io_dis_uops_0_2_bits_prs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_ppred = io_dis_uops_0_2_bits_ppred_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_prs1_busy = io_dis_uops_0_2_bits_prs1_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_prs2_busy = io_dis_uops_0_2_bits_prs2_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_prs3_busy = io_dis_uops_0_2_bits_prs3_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_ppred_busy = io_dis_uops_0_2_bits_ppred_busy_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_stale_pdst = io_dis_uops_0_2_bits_stale_pdst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_exception = io_dis_uops_0_2_bits_exception_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_exc_cause = io_dis_uops_0_2_bits_exc_cause_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_mem_cmd = io_dis_uops_0_2_bits_mem_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_mem_size = io_dis_uops_0_2_bits_mem_size_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_mem_signed = io_dis_uops_0_2_bits_mem_signed_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_uses_ldq = io_dis_uops_0_2_bits_uses_ldq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_uses_stq = io_dis_uops_0_2_bits_uses_stq_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_is_unique = io_dis_uops_0_2_bits_is_unique_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_flush_on_commit = io_dis_uops_0_2_bits_flush_on_commit_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_csr_cmd = io_dis_uops_0_2_bits_csr_cmd_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_ldst_is_rs1 = io_dis_uops_0_2_bits_ldst_is_rs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_ldst = io_dis_uops_0_2_bits_ldst_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_lrs1 = io_dis_uops_0_2_bits_lrs1_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_lrs2 = io_dis_uops_0_2_bits_lrs2_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_lrs3 = io_dis_uops_0_2_bits_lrs3_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_dst_rtype = io_dis_uops_0_2_bits_dst_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_lrs1_rtype = io_dis_uops_0_2_bits_lrs1_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_lrs2_rtype = io_dis_uops_0_2_bits_lrs2_rtype_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_frs3_en = io_dis_uops_0_2_bits_frs3_en_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fcn_dw = io_dis_uops_0_2_bits_fcn_dw_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fcn_op = io_dis_uops_0_2_bits_fcn_op_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fp_val = io_dis_uops_0_2_bits_fp_val_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fp_rm = io_dis_uops_0_2_bits_fp_rm_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_fp_typ = io_dis_uops_0_2_bits_fp_typ_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_xcpt_pf_if = io_dis_uops_0_2_bits_xcpt_pf_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_xcpt_ae_if = io_dis_uops_0_2_bits_xcpt_ae_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_xcpt_ma_if = io_dis_uops_0_2_bits_xcpt_ma_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_bp_debug_if = io_dis_uops_0_2_bits_bp_debug_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_bp_xcpt_if = io_dis_uops_0_2_bits_bp_xcpt_if_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_debug_fsrc = io_dis_uops_0_2_bits_debug_fsrc_0; // @[dispatch.scala:43:7]
assign io_dis_uops_0_2_bits_debug_tsrc = io_dis_uops_0_2_bits_debug_tsrc_0; // @[dispatch.scala:43:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ReRoCCBuffer_4 :
input clock : Clock
input reset : Reset
output auto : { flip in : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}}, out : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}}}
wire nodeIn : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}}
invalidate nodeIn.resp.bits.data
invalidate nodeIn.resp.bits.manager_id
invalidate nodeIn.resp.bits.client_id
invalidate nodeIn.resp.bits.opcode
invalidate nodeIn.resp.valid
invalidate nodeIn.resp.ready
invalidate nodeIn.req.bits.data
invalidate nodeIn.req.bits.manager_id
invalidate nodeIn.req.bits.client_id
invalidate nodeIn.req.bits.opcode
invalidate nodeIn.req.valid
invalidate nodeIn.req.ready
wire nodeOut : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}}
invalidate nodeOut.resp.bits.data
invalidate nodeOut.resp.bits.manager_id
invalidate nodeOut.resp.bits.client_id
invalidate nodeOut.resp.bits.opcode
invalidate nodeOut.resp.valid
invalidate nodeOut.resp.ready
invalidate nodeOut.req.bits.data
invalidate nodeOut.req.bits.manager_id
invalidate nodeOut.req.bits.client_id
invalidate nodeOut.req.bits.opcode
invalidate nodeOut.req.valid
invalidate nodeOut.req.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_req_q of Queue2_ReRoCCMsgBundle_12
connect nodeOut_req_q.clock, clock
connect nodeOut_req_q.reset, reset
connect nodeOut_req_q.io.enq.valid, nodeIn.req.valid
connect nodeOut_req_q.io.enq.bits.data, nodeIn.req.bits.data
connect nodeOut_req_q.io.enq.bits.manager_id, nodeIn.req.bits.manager_id
connect nodeOut_req_q.io.enq.bits.client_id, nodeIn.req.bits.client_id
connect nodeOut_req_q.io.enq.bits.opcode, nodeIn.req.bits.opcode
connect nodeIn.req.ready, nodeOut_req_q.io.enq.ready
connect nodeOut.req.bits, nodeOut_req_q.io.deq.bits
connect nodeOut.req.valid, nodeOut_req_q.io.deq.valid
connect nodeOut_req_q.io.deq.ready, nodeOut.req.ready
inst nodeIn_resp_q of Queue2_ReRoCCMsgBundle_13
connect nodeIn_resp_q.clock, clock
connect nodeIn_resp_q.reset, reset
connect nodeIn_resp_q.io.enq.valid, nodeOut.resp.valid
connect nodeIn_resp_q.io.enq.bits.data, nodeOut.resp.bits.data
connect nodeIn_resp_q.io.enq.bits.manager_id, nodeOut.resp.bits.manager_id
connect nodeIn_resp_q.io.enq.bits.client_id, nodeOut.resp.bits.client_id
connect nodeIn_resp_q.io.enq.bits.opcode, nodeOut.resp.bits.opcode
connect nodeOut.resp.ready, nodeIn_resp_q.io.enq.ready
connect nodeIn.resp.bits, nodeIn_resp_q.io.deq.bits
connect nodeIn.resp.valid, nodeIn_resp_q.io.deq.valid
connect nodeIn_resp_q.io.deq.ready, nodeIn.resp.ready | module ReRoCCBuffer_4( // @[Protocol.scala:124:25]
input clock, // @[Protocol.scala:124:25]
input reset, // @[Protocol.scala:124:25]
output auto_in_req_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_req_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_req_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_req_bits_client_id, // @[LazyModuleImp.scala:107:25]
input auto_in_req_bits_manager_id, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_req_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_resp_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_resp_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_resp_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_resp_bits_client_id, // @[LazyModuleImp.scala:107:25]
output auto_in_resp_bits_manager_id, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_resp_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_req_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_req_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_req_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_req_bits_client_id, // @[LazyModuleImp.scala:107:25]
output auto_out_req_bits_manager_id, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_req_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_resp_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_resp_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_resp_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_resp_bits_client_id, // @[LazyModuleImp.scala:107:25]
input auto_out_resp_bits_manager_id, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_resp_bits_data // @[LazyModuleImp.scala:107:25]
);
wire auto_in_req_valid_0 = auto_in_req_valid; // @[Protocol.scala:124:25]
wire [2:0] auto_in_req_bits_opcode_0 = auto_in_req_bits_opcode; // @[Protocol.scala:124:25]
wire [3:0] auto_in_req_bits_client_id_0 = auto_in_req_bits_client_id; // @[Protocol.scala:124:25]
wire auto_in_req_bits_manager_id_0 = auto_in_req_bits_manager_id; // @[Protocol.scala:124:25]
wire [63:0] auto_in_req_bits_data_0 = auto_in_req_bits_data; // @[Protocol.scala:124:25]
wire auto_in_resp_ready_0 = auto_in_resp_ready; // @[Protocol.scala:124:25]
wire auto_out_req_ready_0 = auto_out_req_ready; // @[Protocol.scala:124:25]
wire auto_out_resp_valid_0 = auto_out_resp_valid; // @[Protocol.scala:124:25]
wire [2:0] auto_out_resp_bits_opcode_0 = auto_out_resp_bits_opcode; // @[Protocol.scala:124:25]
wire [3:0] auto_out_resp_bits_client_id_0 = auto_out_resp_bits_client_id; // @[Protocol.scala:124:25]
wire auto_out_resp_bits_manager_id_0 = auto_out_resp_bits_manager_id; // @[Protocol.scala:124:25]
wire [63:0] auto_out_resp_bits_data_0 = auto_out_resp_bits_data; // @[Protocol.scala:124:25]
wire nodeIn_req_ready; // @[MixedNode.scala:551:17]
wire nodeIn_req_valid = auto_in_req_valid_0; // @[Protocol.scala:124:25]
wire [2:0] nodeIn_req_bits_opcode = auto_in_req_bits_opcode_0; // @[Protocol.scala:124:25]
wire [3:0] nodeIn_req_bits_client_id = auto_in_req_bits_client_id_0; // @[Protocol.scala:124:25]
wire nodeIn_req_bits_manager_id = auto_in_req_bits_manager_id_0; // @[Protocol.scala:124:25]
wire [63:0] nodeIn_req_bits_data = auto_in_req_bits_data_0; // @[Protocol.scala:124:25]
wire nodeIn_resp_ready = auto_in_resp_ready_0; // @[Protocol.scala:124:25]
wire nodeIn_resp_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_resp_bits_opcode; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_resp_bits_client_id; // @[MixedNode.scala:551:17]
wire nodeIn_resp_bits_manager_id; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_resp_bits_data; // @[MixedNode.scala:551:17]
wire nodeOut_req_ready = auto_out_req_ready_0; // @[Protocol.scala:124:25]
wire nodeOut_req_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_req_bits_opcode; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_req_bits_client_id; // @[MixedNode.scala:542:17]
wire nodeOut_req_bits_manager_id; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_req_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_resp_ready; // @[MixedNode.scala:542:17]
wire nodeOut_resp_valid = auto_out_resp_valid_0; // @[Protocol.scala:124:25]
wire [2:0] nodeOut_resp_bits_opcode = auto_out_resp_bits_opcode_0; // @[Protocol.scala:124:25]
wire [3:0] nodeOut_resp_bits_client_id = auto_out_resp_bits_client_id_0; // @[Protocol.scala:124:25]
wire nodeOut_resp_bits_manager_id = auto_out_resp_bits_manager_id_0; // @[Protocol.scala:124:25]
wire [63:0] nodeOut_resp_bits_data = auto_out_resp_bits_data_0; // @[Protocol.scala:124:25]
wire auto_in_req_ready_0; // @[Protocol.scala:124:25]
wire [2:0] auto_in_resp_bits_opcode_0; // @[Protocol.scala:124:25]
wire [3:0] auto_in_resp_bits_client_id_0; // @[Protocol.scala:124:25]
wire auto_in_resp_bits_manager_id_0; // @[Protocol.scala:124:25]
wire [63:0] auto_in_resp_bits_data_0; // @[Protocol.scala:124:25]
wire auto_in_resp_valid_0; // @[Protocol.scala:124:25]
wire [2:0] auto_out_req_bits_opcode_0; // @[Protocol.scala:124:25]
wire [3:0] auto_out_req_bits_client_id_0; // @[Protocol.scala:124:25]
wire auto_out_req_bits_manager_id_0; // @[Protocol.scala:124:25]
wire [63:0] auto_out_req_bits_data_0; // @[Protocol.scala:124:25]
wire auto_out_req_valid_0; // @[Protocol.scala:124:25]
wire auto_out_resp_ready_0; // @[Protocol.scala:124:25]
assign auto_in_req_ready_0 = nodeIn_req_ready; // @[Protocol.scala:124:25]
assign auto_in_resp_valid_0 = nodeIn_resp_valid; // @[Protocol.scala:124:25]
assign auto_in_resp_bits_opcode_0 = nodeIn_resp_bits_opcode; // @[Protocol.scala:124:25]
assign auto_in_resp_bits_client_id_0 = nodeIn_resp_bits_client_id; // @[Protocol.scala:124:25]
assign auto_in_resp_bits_manager_id_0 = nodeIn_resp_bits_manager_id; // @[Protocol.scala:124:25]
assign auto_in_resp_bits_data_0 = nodeIn_resp_bits_data; // @[Protocol.scala:124:25]
assign auto_out_req_valid_0 = nodeOut_req_valid; // @[Protocol.scala:124:25]
assign auto_out_req_bits_opcode_0 = nodeOut_req_bits_opcode; // @[Protocol.scala:124:25]
assign auto_out_req_bits_client_id_0 = nodeOut_req_bits_client_id; // @[Protocol.scala:124:25]
assign auto_out_req_bits_manager_id_0 = nodeOut_req_bits_manager_id; // @[Protocol.scala:124:25]
assign auto_out_req_bits_data_0 = nodeOut_req_bits_data; // @[Protocol.scala:124:25]
assign auto_out_resp_ready_0 = nodeOut_resp_ready; // @[Protocol.scala:124:25]
Queue2_ReRoCCMsgBundle_12 nodeOut_req_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_req_ready),
.io_enq_valid (nodeIn_req_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_req_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_client_id (nodeIn_req_bits_client_id), // @[MixedNode.scala:551:17]
.io_enq_bits_manager_id (nodeIn_req_bits_manager_id), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_req_bits_data), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_req_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_req_valid),
.io_deq_bits_opcode (nodeOut_req_bits_opcode),
.io_deq_bits_client_id (nodeOut_req_bits_client_id),
.io_deq_bits_manager_id (nodeOut_req_bits_manager_id),
.io_deq_bits_data (nodeOut_req_bits_data)
); // @[Decoupled.scala:362:21]
Queue2_ReRoCCMsgBundle_13 nodeIn_resp_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_resp_ready),
.io_enq_valid (nodeOut_resp_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_resp_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_client_id (nodeOut_resp_bits_client_id), // @[MixedNode.scala:542:17]
.io_enq_bits_manager_id (nodeOut_resp_bits_manager_id), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_resp_bits_data), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_resp_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_resp_valid),
.io_deq_bits_opcode (nodeIn_resp_bits_opcode),
.io_deq_bits_client_id (nodeIn_resp_bits_client_id),
.io_deq_bits_manager_id (nodeIn_resp_bits_manager_id),
.io_deq_bits_data (nodeIn_resp_bits_data)
); // @[Decoupled.scala:362:21]
assign auto_in_req_ready = auto_in_req_ready_0; // @[Protocol.scala:124:25]
assign auto_in_resp_valid = auto_in_resp_valid_0; // @[Protocol.scala:124:25]
assign auto_in_resp_bits_opcode = auto_in_resp_bits_opcode_0; // @[Protocol.scala:124:25]
assign auto_in_resp_bits_client_id = auto_in_resp_bits_client_id_0; // @[Protocol.scala:124:25]
assign auto_in_resp_bits_manager_id = auto_in_resp_bits_manager_id_0; // @[Protocol.scala:124:25]
assign auto_in_resp_bits_data = auto_in_resp_bits_data_0; // @[Protocol.scala:124:25]
assign auto_out_req_valid = auto_out_req_valid_0; // @[Protocol.scala:124:25]
assign auto_out_req_bits_opcode = auto_out_req_bits_opcode_0; // @[Protocol.scala:124:25]
assign auto_out_req_bits_client_id = auto_out_req_bits_client_id_0; // @[Protocol.scala:124:25]
assign auto_out_req_bits_manager_id = auto_out_req_bits_manager_id_0; // @[Protocol.scala:124:25]
assign auto_out_req_bits_data = auto_out_req_bits_data_0; // @[Protocol.scala:124:25]
assign auto_out_resp_ready = auto_out_resp_ready_0; // @[Protocol.scala:124:25]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_EntryData_71 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_EntryData_71( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_g, // @[package.scala:268:18]
output io_y_ae, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c, // @[package.scala:268:18]
output io_y_fragmented_superpage // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_0 = io_x_ae; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g_0 = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_0 = io_x_ae_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage_0 = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_g = io_y_g_0; // @[package.scala:267:30]
assign io_y_ae = io_y_ae_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
assign io_y_fragmented_superpage = io_y_fragmented_superpage_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLCToNoC_2 :
input clock : Clock
input reset : Reset
output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<129>, egress_id : UInt}}}
inst q of Queue1_TLBundleC_a32d128s7k6z4c_2
connect q.clock, clock
connect q.reset, reset
wire has_body : UInt<1>
node _head_T = and(q.io.deq.ready, q.io.deq.valid)
node _head_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size)
node _head_beats1_decode_T_1 = bits(_head_beats1_decode_T, 11, 0)
node _head_beats1_decode_T_2 = not(_head_beats1_decode_T_1)
node head_beats1_decode = shr(_head_beats1_decode_T_2, 4)
node head_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0)
node head_beats1 = mux(head_beats1_opdata, head_beats1_decode, UInt<1>(0h0))
regreset head_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _head_counter1_T = sub(head_counter, UInt<1>(0h1))
node head_counter1 = tail(_head_counter1_T, 1)
node head = eq(head_counter, UInt<1>(0h0))
node _head_last_T = eq(head_counter, UInt<1>(0h1))
node _head_last_T_1 = eq(head_beats1, UInt<1>(0h0))
node head_last = or(_head_last_T, _head_last_T_1)
node head_done = and(head_last, _head_T)
node _head_count_T = not(head_counter1)
node head_count = and(head_beats1, _head_count_T)
when _head_T :
node _head_counter_T = mux(head, head_beats1, head_counter1)
connect head_counter, _head_counter_T
node _tail_T = and(q.io.deq.ready, q.io.deq.valid)
node _tail_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size)
node _tail_beats1_decode_T_1 = bits(_tail_beats1_decode_T, 11, 0)
node _tail_beats1_decode_T_2 = not(_tail_beats1_decode_T_1)
node tail_beats1_decode = shr(_tail_beats1_decode_T_2, 4)
node tail_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0)
node tail_beats1 = mux(tail_beats1_opdata, tail_beats1_decode, UInt<1>(0h0))
regreset tail_counter : UInt<8>, clock, reset, UInt<8>(0h0)
node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1))
node tail_counter1 = tail(_tail_counter1_T, 1)
node tail_first = eq(tail_counter, UInt<1>(0h0))
node _tail_last_T = eq(tail_counter, UInt<1>(0h1))
node _tail_last_T_1 = eq(tail_beats1, UInt<1>(0h0))
node tail = or(_tail_last_T, _tail_last_T_1)
node tail_done = and(tail, _tail_T)
node _tail_count_T = not(tail_counter1)
node tail_count = and(tail_beats1, _tail_count_T)
when _tail_T :
node _tail_counter_T = mux(tail_first, tail_beats1, tail_counter1)
connect tail_counter, _tail_counter_T
node body = cat(q.io.deq.bits.data, q.io.deq.bits.corrupt)
node const_lo = cat(q.io.deq.bits.source, q.io.deq.bits.address)
node const_hi_hi = cat(q.io.deq.bits.opcode, q.io.deq.bits.param)
node const_hi = cat(const_hi_hi, q.io.deq.bits.size)
node const = cat(const_hi, const_lo)
regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0)
connect io.flit.valid, q.io.deq.valid
node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0))
node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T)
node _q_io_deq_ready_T_2 = and(io.flit.ready, _q_io_deq_ready_T_1)
connect q.io.deq.ready, _q_io_deq_ready_T_2
node _io_flit_bits_head_T = eq(is_body, UInt<1>(0h0))
node _io_flit_bits_head_T_1 = and(head, _io_flit_bits_head_T)
connect io.flit.bits.head, _io_flit_bits_head_T_1
node _io_flit_bits_tail_T = eq(has_body, UInt<1>(0h0))
node _io_flit_bits_tail_T_1 = or(is_body, _io_flit_bits_tail_T)
node _io_flit_bits_tail_T_2 = and(tail, _io_flit_bits_tail_T_1)
connect io.flit.bits.tail, _io_flit_bits_tail_T_2
node _io_flit_bits_egress_id_requestOH_T = xor(q.io.deq.bits.address, UInt<1>(0h0))
node _io_flit_bits_egress_id_requestOH_T_1 = cvt(_io_flit_bits_egress_id_requestOH_T)
node _io_flit_bits_egress_id_requestOH_T_2 = and(_io_flit_bits_egress_id_requestOH_T_1, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_3 = asSInt(_io_flit_bits_egress_id_requestOH_T_2)
node _io_flit_bits_egress_id_requestOH_T_4 = eq(_io_flit_bits_egress_id_requestOH_T_3, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_5 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_4)
node io_flit_bits_egress_id_requestOH_0 = and(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_5)
node _io_flit_bits_egress_id_requestOH_T_6 = xor(q.io.deq.bits.address, UInt<1>(0h0))
node _io_flit_bits_egress_id_requestOH_T_7 = cvt(_io_flit_bits_egress_id_requestOH_T_6)
node _io_flit_bits_egress_id_requestOH_T_8 = and(_io_flit_bits_egress_id_requestOH_T_7, asSInt(UInt<9>(0hc0)))
node _io_flit_bits_egress_id_requestOH_T_9 = asSInt(_io_flit_bits_egress_id_requestOH_T_8)
node _io_flit_bits_egress_id_requestOH_T_10 = eq(_io_flit_bits_egress_id_requestOH_T_9, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_11 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_10)
node io_flit_bits_egress_id_requestOH_1 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_11)
node _io_flit_bits_egress_id_requestOH_T_12 = xor(q.io.deq.bits.address, UInt<7>(0h40))
node _io_flit_bits_egress_id_requestOH_T_13 = cvt(_io_flit_bits_egress_id_requestOH_T_12)
node _io_flit_bits_egress_id_requestOH_T_14 = and(_io_flit_bits_egress_id_requestOH_T_13, asSInt(UInt<9>(0hc0)))
node _io_flit_bits_egress_id_requestOH_T_15 = asSInt(_io_flit_bits_egress_id_requestOH_T_14)
node _io_flit_bits_egress_id_requestOH_T_16 = eq(_io_flit_bits_egress_id_requestOH_T_15, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_17 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_16)
node io_flit_bits_egress_id_requestOH_2 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_17)
node _io_flit_bits_egress_id_requestOH_T_18 = xor(q.io.deq.bits.address, UInt<8>(0h80))
node _io_flit_bits_egress_id_requestOH_T_19 = cvt(_io_flit_bits_egress_id_requestOH_T_18)
node _io_flit_bits_egress_id_requestOH_T_20 = and(_io_flit_bits_egress_id_requestOH_T_19, asSInt(UInt<9>(0hc0)))
node _io_flit_bits_egress_id_requestOH_T_21 = asSInt(_io_flit_bits_egress_id_requestOH_T_20)
node _io_flit_bits_egress_id_requestOH_T_22 = eq(_io_flit_bits_egress_id_requestOH_T_21, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_23 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_22)
node io_flit_bits_egress_id_requestOH_3 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_23)
node _io_flit_bits_egress_id_requestOH_T_24 = xor(q.io.deq.bits.address, UInt<8>(0hc0))
node _io_flit_bits_egress_id_requestOH_T_25 = cvt(_io_flit_bits_egress_id_requestOH_T_24)
node _io_flit_bits_egress_id_requestOH_T_26 = and(_io_flit_bits_egress_id_requestOH_T_25, asSInt(UInt<9>(0hc0)))
node _io_flit_bits_egress_id_requestOH_T_27 = asSInt(_io_flit_bits_egress_id_requestOH_T_26)
node _io_flit_bits_egress_id_requestOH_T_28 = eq(_io_flit_bits_egress_id_requestOH_T_27, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_29 = or(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_28)
node io_flit_bits_egress_id_requestOH_4 = and(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_29)
node _io_flit_bits_egress_id_T = mux(io_flit_bits_egress_id_requestOH_0, UInt<4>(0he), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_1 = mux(io_flit_bits_egress_id_requestOH_1, UInt<5>(0h10), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_2 = mux(io_flit_bits_egress_id_requestOH_2, UInt<5>(0h12), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_3 = mux(io_flit_bits_egress_id_requestOH_3, UInt<5>(0h14), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_4 = mux(io_flit_bits_egress_id_requestOH_4, UInt<5>(0h16), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_5 = or(_io_flit_bits_egress_id_T, _io_flit_bits_egress_id_T_1)
node _io_flit_bits_egress_id_T_6 = or(_io_flit_bits_egress_id_T_5, _io_flit_bits_egress_id_T_2)
node _io_flit_bits_egress_id_T_7 = or(_io_flit_bits_egress_id_T_6, _io_flit_bits_egress_id_T_3)
node _io_flit_bits_egress_id_T_8 = or(_io_flit_bits_egress_id_T_7, _io_flit_bits_egress_id_T_4)
wire _io_flit_bits_egress_id_WIRE : UInt<5>
connect _io_flit_bits_egress_id_WIRE, _io_flit_bits_egress_id_T_8
connect io.flit.bits.egress_id, _io_flit_bits_egress_id_WIRE
node _io_flit_bits_payload_T = mux(is_body, body, const)
connect io.flit.bits.payload, _io_flit_bits_payload_T
node _T = and(io.flit.ready, io.flit.valid)
node _T_1 = and(_T, io.flit.bits.head)
when _T_1 :
connect is_body, UInt<1>(0h1)
node _T_2 = and(io.flit.ready, io.flit.valid)
node _T_3 = and(_T_2, io.flit.bits.tail)
when _T_3 :
connect is_body, UInt<1>(0h0)
node has_body_opdata = bits(q.io.deq.bits.opcode, 0, 0)
connect has_body, has_body_opdata
connect q.io.enq, io.protocol
node _q_io_enq_bits_source_T = or(io.protocol.bits.source, UInt<7>(0h48))
connect q.io.enq.bits.source, _q_io_enq_bits_source_T | module TLCToNoC_2( // @[TilelinkAdapters.scala:151:7]
input clock, // @[TilelinkAdapters.scala:151:7]
input reset, // @[TilelinkAdapters.scala:151:7]
output io_protocol_ready, // @[TilelinkAdapters.scala:19:14]
input io_protocol_valid, // @[TilelinkAdapters.scala:19:14]
input [2:0] io_protocol_bits_opcode, // @[TilelinkAdapters.scala:19:14]
input [2:0] io_protocol_bits_param, // @[TilelinkAdapters.scala:19:14]
input [3:0] io_protocol_bits_size, // @[TilelinkAdapters.scala:19:14]
input [6:0] io_protocol_bits_source, // @[TilelinkAdapters.scala:19:14]
input [31:0] io_protocol_bits_address, // @[TilelinkAdapters.scala:19:14]
input [127:0] io_protocol_bits_data, // @[TilelinkAdapters.scala:19:14]
input io_protocol_bits_corrupt, // @[TilelinkAdapters.scala:19:14]
input io_flit_ready, // @[TilelinkAdapters.scala:19:14]
output io_flit_valid, // @[TilelinkAdapters.scala:19:14]
output io_flit_bits_head, // @[TilelinkAdapters.scala:19:14]
output io_flit_bits_tail, // @[TilelinkAdapters.scala:19:14]
output [128:0] io_flit_bits_payload, // @[TilelinkAdapters.scala:19:14]
output [4:0] io_flit_bits_egress_id // @[TilelinkAdapters.scala:19:14]
);
wire _q_io_deq_valid; // @[TilelinkAdapters.scala:26:17]
wire [2:0] _q_io_deq_bits_opcode; // @[TilelinkAdapters.scala:26:17]
wire [2:0] _q_io_deq_bits_param; // @[TilelinkAdapters.scala:26:17]
wire [3:0] _q_io_deq_bits_size; // @[TilelinkAdapters.scala:26:17]
wire [6:0] _q_io_deq_bits_source; // @[TilelinkAdapters.scala:26:17]
wire [31:0] _q_io_deq_bits_address; // @[TilelinkAdapters.scala:26:17]
wire [127:0] _q_io_deq_bits_data; // @[TilelinkAdapters.scala:26:17]
wire _q_io_deq_bits_corrupt; // @[TilelinkAdapters.scala:26:17]
wire [26:0] _tail_beats1_decode_T = 27'hFFF << _q_io_deq_bits_size; // @[package.scala:243:71]
reg [7:0] head_counter; // @[Edges.scala:229:27]
wire head = head_counter == 8'h0; // @[Edges.scala:229:27, :231:25]
wire [7:0] tail_beats1 = _q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:4]) : 8'h0; // @[package.scala:243:{46,71,76}]
reg [7:0] tail_counter; // @[Edges.scala:229:27]
reg is_body; // @[TilelinkAdapters.scala:39:24]
wire q_io_deq_ready = io_flit_ready & (is_body | ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36]
wire io_flit_bits_head_0 = head & ~is_body; // @[Edges.scala:231:25]
wire io_flit_bits_tail_0 = (tail_counter == 8'h1 | tail_beats1 == 8'h0) & (is_body | ~(_q_io_deq_bits_opcode[0])); // @[Edges.scala:102:36, :221:14, :229:27, :232:{25,33,43}]
wire _GEN = io_flit_ready & _q_io_deq_valid; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[TilelinkAdapters.scala:151:7]
if (reset) begin // @[TilelinkAdapters.scala:151:7]
head_counter <= 8'h0; // @[Edges.scala:229:27]
tail_counter <= 8'h0; // @[Edges.scala:229:27]
is_body <= 1'h0; // @[TilelinkAdapters.scala:39:24, :151:7]
end
else begin // @[TilelinkAdapters.scala:151:7]
if (q_io_deq_ready & _q_io_deq_valid) begin // @[Decoupled.scala:51:35]
head_counter <= head ? (_q_io_deq_bits_opcode[0] ? ~(_tail_beats1_decode_T[11:4]) : 8'h0) : head_counter - 8'h1; // @[package.scala:243:{46,71,76}]
tail_counter <= tail_counter == 8'h0 ? tail_beats1 : tail_counter - 8'h1; // @[Edges.scala:221:14, :229:27, :230:28, :231:25, :236:21]
end
is_body <= ~(_GEN & io_flit_bits_tail_0) & (_GEN & io_flit_bits_head_0 | is_body); // @[Decoupled.scala:51:35]
end
always @(posedge) |
Generate the Verilog code corresponding to this FIRRTL code module Tile_204 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_460
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_204( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_460 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module LoopBranchPredictorColumn_15 :
input clock : Clock
input reset : Reset
output io : { flip f2_req_valid : UInt<1>, flip f2_req_idx : UInt, flip f3_req_fire : UInt<1>, flip f3_pred_in : UInt<1>, f3_pred : UInt<1>, f3_meta : { s_cnt : UInt<10>}, flip update_mispredict : UInt<1>, flip update_repair : UInt<1>, flip update_idx : UInt, flip update_resolve_dir : UInt<1>, flip update_meta : { s_cnt : UInt<10>}}
regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1)
regreset reset_idx : UInt<4>, clock, reset, UInt<4>(0h0)
node _reset_idx_T = add(reset_idx, doing_reset)
node _reset_idx_T_1 = tail(_reset_idx_T, 1)
connect reset_idx, _reset_idx_T_1
node _T = eq(reset_idx, UInt<4>(0hf))
when _T :
connect doing_reset, UInt<1>(0h0)
reg entries : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}[16], clock
node _f2_entry_T = or(io.f2_req_idx, UInt<4>(0h0))
node _f2_entry_T_1 = bits(_f2_entry_T, 3, 0)
wire f2_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}
connect f2_entry, entries[_f2_entry_T_1]
node _T_1 = eq(io.update_idx, io.f2_req_idx)
node _T_2 = and(io.update_repair, _T_1)
when _T_2 :
connect f2_entry.s_cnt, io.update_meta.s_cnt
else :
node _T_3 = eq(io.update_idx, io.f2_req_idx)
node _T_4 = and(io.update_mispredict, _T_3)
when _T_4 :
connect f2_entry.s_cnt, UInt<1>(0h0)
reg f3_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}, clock
connect f3_entry, f2_entry
reg f3_scnt_REG : UInt, clock
connect f3_scnt_REG, io.f2_req_idx
node _f3_scnt_T = eq(io.update_idx, f3_scnt_REG)
node _f3_scnt_T_1 = and(io.update_repair, _f3_scnt_T)
node f3_scnt = mux(_f3_scnt_T_1, io.update_meta.s_cnt, f3_entry.s_cnt)
node _f3_tag_T = bits(io.f2_req_idx, 13, 4)
reg f3_tag : UInt, clock
connect f3_tag, _f3_tag_T
connect io.f3_pred, io.f3_pred_in
connect io.f3_meta.s_cnt, f3_scnt
node _T_5 = eq(f3_entry.tag, f3_tag)
when _T_5 :
node _T_6 = eq(f3_scnt, f3_entry.p_cnt)
node _T_7 = eq(f3_entry.conf, UInt<3>(0h7))
node _T_8 = and(_T_6, _T_7)
when _T_8 :
node _io_f3_pred_T = eq(io.f3_pred_in, UInt<1>(0h0))
connect io.f3_pred, _io_f3_pred_T
reg f4_fire : UInt<1>, clock
connect f4_fire, io.f3_req_fire
reg f4_entry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}, clock
connect f4_entry, f3_entry
reg f4_tag : UInt, clock
connect f4_tag, f3_tag
reg f4_scnt : UInt, clock
connect f4_scnt, f3_scnt
reg f4_idx_REG : UInt, clock
connect f4_idx_REG, io.f2_req_idx
reg f4_idx : UInt, clock
connect f4_idx, f4_idx_REG
when f4_fire :
node _T_9 = eq(f4_entry.tag, f4_tag)
when _T_9 :
node _T_10 = eq(f4_scnt, f4_entry.p_cnt)
node _T_11 = eq(f4_entry.conf, UInt<3>(0h7))
node _T_12 = and(_T_10, _T_11)
when _T_12 :
node _T_13 = or(f4_idx, UInt<4>(0h0))
node _T_14 = bits(_T_13, 3, 0)
connect entries[_T_14].age, UInt<3>(0h7)
node _T_15 = or(f4_idx, UInt<4>(0h0))
node _T_16 = bits(_T_15, 3, 0)
connect entries[_T_16].s_cnt, UInt<1>(0h0)
else :
node _T_17 = or(f4_idx, UInt<4>(0h0))
node _T_18 = bits(_T_17, 3, 0)
node _entries_s_cnt_T = add(f4_scnt, UInt<1>(0h1))
node _entries_s_cnt_T_1 = tail(_entries_s_cnt_T, 1)
connect entries[_T_18].s_cnt, _entries_s_cnt_T_1
node _T_19 = or(f4_idx, UInt<4>(0h0))
node _T_20 = bits(_T_19, 3, 0)
node _entries_age_T = eq(f4_entry.age, UInt<3>(0h7))
node _entries_age_T_1 = add(f4_entry.age, UInt<1>(0h1))
node _entries_age_T_2 = tail(_entries_age_T_1, 1)
node _entries_age_T_3 = mux(_entries_age_T, UInt<3>(0h7), _entries_age_T_2)
connect entries[_T_20].age, _entries_age_T_3
node _entry_T = or(io.update_idx, UInt<4>(0h0))
node _entry_T_1 = bits(_entry_T, 3, 0)
node tag = bits(io.update_idx, 13, 4)
node tag_match = eq(entries[_entry_T_1].tag, tag)
node ctr_match = eq(entries[_entry_T_1].p_cnt, io.update_meta.s_cnt)
wire wentry : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}
connect wentry, entries[_entry_T_1]
node _T_21 = eq(doing_reset, UInt<1>(0h0))
node _T_22 = and(io.update_mispredict, _T_21)
when _T_22 :
node _T_23 = eq(entries[_entry_T_1].conf, UInt<3>(0h7))
node _T_24 = and(_T_23, tag_match)
when _T_24 :
connect wentry.s_cnt, UInt<1>(0h0)
connect wentry.conf, UInt<1>(0h0)
else :
node _T_25 = eq(entries[_entry_T_1].conf, UInt<3>(0h7))
node _T_26 = eq(tag_match, UInt<1>(0h0))
node _T_27 = and(_T_25, _T_26)
when _T_27 :
skip
else :
node _T_28 = neq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_29 = and(_T_28, tag_match)
node _T_30 = and(_T_29, ctr_match)
when _T_30 :
node _wentry_conf_T = add(entries[_entry_T_1].conf, UInt<1>(0h1))
node _wentry_conf_T_1 = tail(_wentry_conf_T, 1)
connect wentry.conf, _wentry_conf_T_1
connect wentry.s_cnt, UInt<1>(0h0)
else :
node _T_31 = neq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_32 = and(_T_31, tag_match)
node _T_33 = eq(ctr_match, UInt<1>(0h0))
node _T_34 = and(_T_32, _T_33)
when _T_34 :
connect wentry.conf, UInt<1>(0h0)
connect wentry.s_cnt, UInt<1>(0h0)
connect wentry.p_cnt, io.update_meta.s_cnt
else :
node _T_35 = neq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_36 = eq(tag_match, UInt<1>(0h0))
node _T_37 = and(_T_35, _T_36)
node _T_38 = eq(entries[_entry_T_1].age, UInt<1>(0h0))
node _T_39 = and(_T_37, _T_38)
when _T_39 :
connect wentry.tag, tag
connect wentry.conf, UInt<1>(0h1)
connect wentry.s_cnt, UInt<1>(0h0)
connect wentry.p_cnt, io.update_meta.s_cnt
else :
node _T_40 = neq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_41 = eq(tag_match, UInt<1>(0h0))
node _T_42 = and(_T_40, _T_41)
node _T_43 = neq(entries[_entry_T_1].age, UInt<1>(0h0))
node _T_44 = and(_T_42, _T_43)
when _T_44 :
node _wentry_age_T = sub(entries[_entry_T_1].age, UInt<1>(0h1))
node _wentry_age_T_1 = tail(_wentry_age_T, 1)
connect wentry.age, _wentry_age_T_1
else :
node _T_45 = eq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_46 = and(_T_45, tag_match)
node _T_47 = and(_T_46, ctr_match)
when _T_47 :
connect wentry.conf, UInt<1>(0h1)
connect wentry.age, UInt<3>(0h7)
connect wentry.s_cnt, UInt<1>(0h0)
else :
node _T_48 = eq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_49 = and(_T_48, tag_match)
node _T_50 = eq(ctr_match, UInt<1>(0h0))
node _T_51 = and(_T_49, _T_50)
when _T_51 :
connect wentry.p_cnt, io.update_meta.s_cnt
connect wentry.age, UInt<3>(0h7)
connect wentry.s_cnt, UInt<1>(0h0)
else :
node _T_52 = eq(entries[_entry_T_1].conf, UInt<1>(0h0))
node _T_53 = eq(tag_match, UInt<1>(0h0))
node _T_54 = and(_T_52, _T_53)
when _T_54 :
connect wentry.tag, tag
connect wentry.conf, UInt<1>(0h1)
connect wentry.age, UInt<3>(0h7)
connect wentry.s_cnt, UInt<1>(0h0)
connect wentry.p_cnt, io.update_meta.s_cnt
node _T_55 = or(io.update_idx, UInt<4>(0h0))
node _T_56 = bits(_T_55, 3, 0)
connect entries[_T_56], wentry
else :
node _T_57 = eq(doing_reset, UInt<1>(0h0))
node _T_58 = and(io.update_repair, _T_57)
when _T_58 :
node _T_59 = eq(io.update_idx, f4_idx)
node _T_60 = and(f4_fire, _T_59)
node _T_61 = eq(_T_60, UInt<1>(0h0))
node _T_62 = and(tag_match, _T_61)
when _T_62 :
connect wentry.s_cnt, io.update_meta.s_cnt
node _T_63 = or(io.update_idx, UInt<4>(0h0))
node _T_64 = bits(_T_63, 3, 0)
connect entries[_T_64], wentry
when doing_reset :
wire _entries_WIRE : { tag : UInt<10>, conf : UInt<3>, age : UInt<3>, p_cnt : UInt<10>, s_cnt : UInt<10>}
connect _entries_WIRE.s_cnt, UInt<10>(0h0)
connect _entries_WIRE.p_cnt, UInt<10>(0h0)
connect _entries_WIRE.age, UInt<3>(0h0)
connect _entries_WIRE.conf, UInt<3>(0h0)
connect _entries_WIRE.tag, UInt<10>(0h0)
connect entries[reset_idx], _entries_WIRE | module LoopBranchPredictorColumn_15( // @[loop.scala:39:9]
input clock, // @[loop.scala:39:9]
input reset, // @[loop.scala:39:9]
input io_f2_req_valid, // @[loop.scala:43:16]
input [35:0] io_f2_req_idx, // @[loop.scala:43:16]
input io_f3_req_fire, // @[loop.scala:43:16]
input io_f3_pred_in, // @[loop.scala:43:16]
output io_f3_pred, // @[loop.scala:43:16]
output [9:0] io_f3_meta_s_cnt, // @[loop.scala:43:16]
input io_update_mispredict, // @[loop.scala:43:16]
input io_update_repair, // @[loop.scala:43:16]
input [35:0] io_update_idx, // @[loop.scala:43:16]
input io_update_resolve_dir, // @[loop.scala:43:16]
input [9:0] io_update_meta_s_cnt // @[loop.scala:43:16]
);
wire io_f2_req_valid_0 = io_f2_req_valid; // @[loop.scala:39:9]
wire [35:0] io_f2_req_idx_0 = io_f2_req_idx; // @[loop.scala:39:9]
wire io_f3_req_fire_0 = io_f3_req_fire; // @[loop.scala:39:9]
wire io_f3_pred_in_0 = io_f3_pred_in; // @[loop.scala:39:9]
wire io_update_mispredict_0 = io_update_mispredict; // @[loop.scala:39:9]
wire io_update_repair_0 = io_update_repair; // @[loop.scala:39:9]
wire [35:0] io_update_idx_0 = io_update_idx; // @[loop.scala:39:9]
wire io_update_resolve_dir_0 = io_update_resolve_dir; // @[loop.scala:39:9]
wire [9:0] io_update_meta_s_cnt_0 = io_update_meta_s_cnt; // @[loop.scala:39:9]
wire [2:0] _entries_WIRE_conf = 3'h0; // @[loop.scala:176:43]
wire [2:0] _entries_WIRE_age = 3'h0; // @[loop.scala:176:43]
wire [9:0] _entries_WIRE_tag = 10'h0; // @[loop.scala:176:43]
wire [9:0] _entries_WIRE_p_cnt = 10'h0; // @[loop.scala:176:43]
wire [9:0] _entries_WIRE_s_cnt = 10'h0; // @[loop.scala:176:43]
wire [35:0] _f2_entry_T = io_f2_req_idx_0; // @[loop.scala:39:9]
wire [9:0] f3_scnt; // @[loop.scala:73:23]
wire [35:0] _entry_T = io_update_idx_0; // @[loop.scala:39:9]
wire [9:0] io_f3_meta_s_cnt_0; // @[loop.scala:39:9]
wire io_f3_pred_0; // @[loop.scala:39:9]
reg doing_reset; // @[loop.scala:59:30]
reg [3:0] reset_idx; // @[loop.scala:60:28]
wire [4:0] _reset_idx_T = {1'h0, reset_idx} + {4'h0, doing_reset}; // @[loop.scala:59:30, :60:28, :61:28]
wire [3:0] _reset_idx_T_1 = _reset_idx_T[3:0]; // @[loop.scala:61:28]
reg [9:0] entries_0_tag; // @[loop.scala:65:22]
reg [2:0] entries_0_conf; // @[loop.scala:65:22]
reg [2:0] entries_0_age; // @[loop.scala:65:22]
reg [9:0] entries_0_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_0_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_1_tag; // @[loop.scala:65:22]
reg [2:0] entries_1_conf; // @[loop.scala:65:22]
reg [2:0] entries_1_age; // @[loop.scala:65:22]
reg [9:0] entries_1_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_1_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_2_tag; // @[loop.scala:65:22]
reg [2:0] entries_2_conf; // @[loop.scala:65:22]
reg [2:0] entries_2_age; // @[loop.scala:65:22]
reg [9:0] entries_2_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_2_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_3_tag; // @[loop.scala:65:22]
reg [2:0] entries_3_conf; // @[loop.scala:65:22]
reg [2:0] entries_3_age; // @[loop.scala:65:22]
reg [9:0] entries_3_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_3_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_4_tag; // @[loop.scala:65:22]
reg [2:0] entries_4_conf; // @[loop.scala:65:22]
reg [2:0] entries_4_age; // @[loop.scala:65:22]
reg [9:0] entries_4_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_4_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_5_tag; // @[loop.scala:65:22]
reg [2:0] entries_5_conf; // @[loop.scala:65:22]
reg [2:0] entries_5_age; // @[loop.scala:65:22]
reg [9:0] entries_5_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_5_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_6_tag; // @[loop.scala:65:22]
reg [2:0] entries_6_conf; // @[loop.scala:65:22]
reg [2:0] entries_6_age; // @[loop.scala:65:22]
reg [9:0] entries_6_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_6_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_7_tag; // @[loop.scala:65:22]
reg [2:0] entries_7_conf; // @[loop.scala:65:22]
reg [2:0] entries_7_age; // @[loop.scala:65:22]
reg [9:0] entries_7_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_7_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_8_tag; // @[loop.scala:65:22]
reg [2:0] entries_8_conf; // @[loop.scala:65:22]
reg [2:0] entries_8_age; // @[loop.scala:65:22]
reg [9:0] entries_8_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_8_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_9_tag; // @[loop.scala:65:22]
reg [2:0] entries_9_conf; // @[loop.scala:65:22]
reg [2:0] entries_9_age; // @[loop.scala:65:22]
reg [9:0] entries_9_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_9_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_10_tag; // @[loop.scala:65:22]
reg [2:0] entries_10_conf; // @[loop.scala:65:22]
reg [2:0] entries_10_age; // @[loop.scala:65:22]
reg [9:0] entries_10_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_10_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_11_tag; // @[loop.scala:65:22]
reg [2:0] entries_11_conf; // @[loop.scala:65:22]
reg [2:0] entries_11_age; // @[loop.scala:65:22]
reg [9:0] entries_11_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_11_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_12_tag; // @[loop.scala:65:22]
reg [2:0] entries_12_conf; // @[loop.scala:65:22]
reg [2:0] entries_12_age; // @[loop.scala:65:22]
reg [9:0] entries_12_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_12_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_13_tag; // @[loop.scala:65:22]
reg [2:0] entries_13_conf; // @[loop.scala:65:22]
reg [2:0] entries_13_age; // @[loop.scala:65:22]
reg [9:0] entries_13_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_13_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_14_tag; // @[loop.scala:65:22]
reg [2:0] entries_14_conf; // @[loop.scala:65:22]
reg [2:0] entries_14_age; // @[loop.scala:65:22]
reg [9:0] entries_14_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_14_s_cnt; // @[loop.scala:65:22]
reg [9:0] entries_15_tag; // @[loop.scala:65:22]
reg [2:0] entries_15_conf; // @[loop.scala:65:22]
reg [2:0] entries_15_age; // @[loop.scala:65:22]
reg [9:0] entries_15_p_cnt; // @[loop.scala:65:22]
reg [9:0] entries_15_s_cnt; // @[loop.scala:65:22]
wire [3:0] _f2_entry_T_1 = _f2_entry_T[3:0];
wire [9:0] f2_entry_tag; // @[loop.scala:66:28]
wire [2:0] f2_entry_conf; // @[loop.scala:66:28]
wire [2:0] f2_entry_age; // @[loop.scala:66:28]
wire [9:0] f2_entry_p_cnt; // @[loop.scala:66:28]
wire [9:0] f2_entry_s_cnt; // @[loop.scala:66:28]
wire [15:0][9:0] _GEN = {{entries_15_tag}, {entries_14_tag}, {entries_13_tag}, {entries_12_tag}, {entries_11_tag}, {entries_10_tag}, {entries_9_tag}, {entries_8_tag}, {entries_7_tag}, {entries_6_tag}, {entries_5_tag}, {entries_4_tag}, {entries_3_tag}, {entries_2_tag}, {entries_1_tag}, {entries_0_tag}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_tag = _GEN[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][2:0] _GEN_0 = {{entries_15_conf}, {entries_14_conf}, {entries_13_conf}, {entries_12_conf}, {entries_11_conf}, {entries_10_conf}, {entries_9_conf}, {entries_8_conf}, {entries_7_conf}, {entries_6_conf}, {entries_5_conf}, {entries_4_conf}, {entries_3_conf}, {entries_2_conf}, {entries_1_conf}, {entries_0_conf}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_conf = _GEN_0[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][2:0] _GEN_1 = {{entries_15_age}, {entries_14_age}, {entries_13_age}, {entries_12_age}, {entries_11_age}, {entries_10_age}, {entries_9_age}, {entries_8_age}, {entries_7_age}, {entries_6_age}, {entries_5_age}, {entries_4_age}, {entries_3_age}, {entries_2_age}, {entries_1_age}, {entries_0_age}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_age = _GEN_1[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][9:0] _GEN_2 = {{entries_15_p_cnt}, {entries_14_p_cnt}, {entries_13_p_cnt}, {entries_12_p_cnt}, {entries_11_p_cnt}, {entries_10_p_cnt}, {entries_9_p_cnt}, {entries_8_p_cnt}, {entries_7_p_cnt}, {entries_6_p_cnt}, {entries_5_p_cnt}, {entries_4_p_cnt}, {entries_3_p_cnt}, {entries_2_p_cnt}, {entries_1_p_cnt}, {entries_0_p_cnt}}; // @[loop.scala:65:22, :66:28]
assign f2_entry_p_cnt = _GEN_2[_f2_entry_T_1]; // @[loop.scala:66:28]
wire [15:0][9:0] _GEN_3 = {{entries_15_s_cnt}, {entries_14_s_cnt}, {entries_13_s_cnt}, {entries_12_s_cnt}, {entries_11_s_cnt}, {entries_10_s_cnt}, {entries_9_s_cnt}, {entries_8_s_cnt}, {entries_7_s_cnt}, {entries_6_s_cnt}, {entries_5_s_cnt}, {entries_4_s_cnt}, {entries_3_s_cnt}, {entries_2_s_cnt}, {entries_1_s_cnt}, {entries_0_s_cnt}}; // @[loop.scala:65:22, :66:28]
wire _T_3 = io_update_idx_0 == io_f2_req_idx_0; // @[loop.scala:39:9, :67:45]
assign f2_entry_s_cnt = io_update_repair_0 & _T_3 ? io_update_meta_s_cnt_0 : io_update_mispredict_0 & _T_3 ? 10'h0 : _GEN_3[_f2_entry_T_1]; // @[loop.scala:39:9, :66:28, :67:{28,45,64}, :68:22, :69:{39,75}, :70:22]
reg [9:0] f3_entry_tag; // @[loop.scala:72:27]
reg [2:0] f3_entry_conf; // @[loop.scala:72:27]
reg [2:0] f3_entry_age; // @[loop.scala:72:27]
reg [9:0] f3_entry_p_cnt; // @[loop.scala:72:27]
reg [9:0] f3_entry_s_cnt; // @[loop.scala:72:27]
reg [35:0] f3_scnt_REG; // @[loop.scala:73:69]
wire _f3_scnt_T = io_update_idx_0 == f3_scnt_REG; // @[loop.scala:39:9, :73:{58,69}]
wire _f3_scnt_T_1 = io_update_repair_0 & _f3_scnt_T; // @[loop.scala:39:9, :73:{41,58}]
assign f3_scnt = _f3_scnt_T_1 ? io_update_meta_s_cnt_0 : f3_entry_s_cnt; // @[loop.scala:39:9, :72:27, :73:{23,41}]
assign io_f3_meta_s_cnt_0 = f3_scnt; // @[loop.scala:39:9, :73:23]
wire [9:0] _f3_tag_T = io_f2_req_idx_0[13:4]; // @[loop.scala:39:9, :76:41]
reg [9:0] f3_tag; // @[loop.scala:76:27]
wire _io_f3_pred_T = ~io_f3_pred_in_0; // @[loop.scala:39:9, :83:23]
assign io_f3_pred_0 = f3_entry_tag == f3_tag & f3_scnt == f3_entry_p_cnt & (&f3_entry_conf) ? _io_f3_pred_T : io_f3_pred_in_0; // @[loop.scala:39:9, :72:27, :73:23, :76:27, :78:16, :81:{24,36}, :82:{21,40,57,66}, :83:{20,23}]
reg f4_fire; // @[loop.scala:88:27]
reg [9:0] f4_entry_tag; // @[loop.scala:89:27]
reg [2:0] f4_entry_conf; // @[loop.scala:89:27]
reg [2:0] f4_entry_age; // @[loop.scala:89:27]
reg [9:0] f4_entry_p_cnt; // @[loop.scala:89:27]
reg [9:0] f4_entry_s_cnt; // @[loop.scala:89:27]
reg [9:0] f4_tag; // @[loop.scala:90:27]
reg [9:0] f4_scnt; // @[loop.scala:91:27]
reg [35:0] f4_idx_REG; // @[loop.scala:92:35]
reg [35:0] f4_idx; // @[loop.scala:92:27]
wire [10:0] _entries_s_cnt_T = {1'h0, f4_scnt} + 11'h1; // @[loop.scala:91:27, :101:44]
wire [9:0] _entries_s_cnt_T_1 = _entries_s_cnt_T[9:0]; // @[loop.scala:101:44]
wire _entries_age_T = &f4_entry_age; // @[loop.scala:89:27, :102:53]
wire [3:0] _entries_age_T_1 = {1'h0, f4_entry_age} + 4'h1; // @[loop.scala:89:27, :102:80]
wire [2:0] _entries_age_T_2 = _entries_age_T_1[2:0]; // @[loop.scala:102:80]
wire [2:0] _entries_age_T_3 = _entries_age_T ? 3'h7 : _entries_age_T_2; // @[loop.scala:102:{39,53,80}]
wire [3:0] _entry_T_1 = _entry_T[3:0];
wire [9:0] tag = io_update_idx_0[13:4]; // @[loop.scala:39:9, :109:28]
wire tag_match = _GEN[_entry_T_1] == tag; // @[loop.scala:66:28, :109:28, :110:31]
wire ctr_match = _GEN_2[_entry_T_1] == io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :111:33]
wire [9:0] wentry_tag; // @[loop.scala:112:26]
wire [2:0] wentry_conf; // @[loop.scala:112:26]
wire [2:0] wentry_age; // @[loop.scala:112:26]
wire [9:0] wentry_p_cnt; // @[loop.scala:112:26]
wire [9:0] wentry_s_cnt; // @[loop.scala:112:26]
wire _T_22 = io_update_mispredict_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:{32,35}]
wire _T_24 = (&_GEN_0[_entry_T_1]) & tag_match; // @[loop.scala:66:28, :110:31, :117:{24,32}]
wire _T_27 = (&_GEN_0[_entry_T_1]) & ~tag_match; // @[loop.scala:66:28, :110:31, :117:24, :122:{39,42}]
wire _T_30 = (|_GEN_0[_entry_T_1]) & tag_match & ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:{31,39,52}]
wire [3:0] _wentry_conf_T = {1'h0, _GEN_0[_entry_T_1]} + 4'h1; // @[loop.scala:66:28, :102:80, :110:31, :126:36]
wire [2:0] _wentry_conf_T_1 = _wentry_conf_T[2:0]; // @[loop.scala:126:36]
wire _T_34 = (|_GEN_0[_entry_T_1]) & tag_match & ~ctr_match; // @[loop.scala:66:28, :110:31, :111:33, :125:31, :130:{39,52,55}]
wire _T_39 = (|_GEN_0[_entry_T_1]) & ~tag_match & _GEN_1[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :122:42, :125:31, :136:{39,53,66}]
wire _T_44 = (|_GEN_0[_entry_T_1]) & ~tag_match & (|_GEN_1[_entry_T_1]); // @[loop.scala:66:28, :110:31, :122:42, :125:31, :143:{39,53,66}]
wire [3:0] _wentry_age_T = {1'h0, _GEN_1[_entry_T_1]} - 4'h1; // @[loop.scala:66:28, :110:31, :144:33]
wire [2:0] _wentry_age_T_1 = _wentry_age_T[2:0]; // @[loop.scala:144:33]
wire _T_52 = _GEN_0[_entry_T_1] == 3'h0; // @[loop.scala:66:28, :110:31, :147:31]
wire _T_47 = _T_52 & tag_match & ctr_match; // @[loop.scala:110:31, :111:33, :147:{31,39,52}]
wire _T_51 = _T_52 & tag_match & ~ctr_match; // @[loop.scala:110:31, :111:33, :130:55, :147:31, :153:{39,52}]
wire _T_54 = _T_52 & ~tag_match; // @[loop.scala:110:31, :122:42, :147:31, :159:39]
wire _GEN_4 = _T_47 | _T_51; // @[loop.scala:112:26, :147:{39,52,66}, :153:{39,52,67}, :159:54]
wire _GEN_5 = _T_30 | _T_34; // @[loop.scala:112:26, :125:{39,52,66}, :130:{39,52,67}, :136:75]
assign wentry_tag = ~_T_22 | _T_24 | _T_27 | _GEN_5 | ~(_T_39 | ~(_T_44 | _GEN_4 | ~_T_54)) ? _GEN[_entry_T_1] : tag; // @[loop.scala:66:28, :109:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:66, :130:67, :136:{39,53,75}, :137:22, :143:{39,53,75}, :147:66, :153:67, :159:{39,54}]
assign wentry_conf = _T_22 ? (_T_24 ? 3'h0 : _T_27 ? _GEN_0[_entry_T_1] : _T_30 ? _wentry_conf_T_1 : _T_34 ? 3'h0 : _T_39 | ~(_T_44 | ~(_T_47 | ~(_T_51 | ~_T_54))) ? 3'h1 : _GEN_0[_entry_T_1]) : _GEN_0[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :119:22, :122:{39,54}, :125:{39,52,66}, :126:{22,36}, :130:{39,52,67}, :131:22, :136:{39,53,75}, :138:22, :143:{39,53,75}, :147:{39,52,66}, :148:22, :153:{39,52,67}, :159:{39,54}]
wire _GEN_6 = _T_51 | _T_54; // @[loop.scala:112:26, :153:{39,52,67}, :155:22, :159:{39,54}, :162:22]
wire _GEN_7 = _T_34 | _T_39; // @[loop.scala:112:26, :130:{39,52,67}, :136:{39,53,75}, :143:75]
assign wentry_age = ~_T_22 | _T_24 | _T_27 | _T_30 | _GEN_7 ? _GEN_1[_entry_T_1] : _T_44 ? _wentry_age_T_1 : _T_47 | _GEN_6 ? 3'h7 : _GEN_1[_entry_T_1]; // @[loop.scala:66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :136:75, :143:{39,53,75}, :144:{20,33}, :147:{39,52,66}, :149:22, :153:67, :155:22, :159:54, :162:22]
assign wentry_p_cnt = ~_T_22 | _T_24 | _T_27 | _T_30 | ~(_GEN_7 | ~(_T_44 | _T_47 | ~_GEN_6)) ? _GEN_2[_entry_T_1] : io_update_meta_s_cnt_0; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :122:{39,54}, :125:{39,52,66}, :130:67, :133:22, :136:75, :140:22, :143:{39,53,75}, :147:{39,52,66}, :153:67, :155:22, :159:54, :162:22]
wire _T_58 = io_update_repair_0 & ~doing_reset; // @[loop.scala:39:9, :59:30, :114:35, :168:35]
wire _T_62 = tag_match & ~(f4_fire & io_update_idx_0 == f4_idx); // @[loop.scala:39:9, :88:27, :92:27, :110:31, :169:{23,26,36,53}]
assign wentry_s_cnt = _T_22 ? (_T_24 | ~(_T_27 | ~(_GEN_5 | _T_39 | ~(_T_44 | ~(_GEN_4 | _T_54)))) ? 10'h0 : _GEN_3[_entry_T_1]) : _T_58 & _T_62 ? io_update_meta_s_cnt_0 : _GEN_3[_entry_T_1]; // @[loop.scala:39:9, :66:28, :110:31, :112:26, :114:{32,49}, :117:{32,46}, :118:22, :122:{39,54}, :125:66, :127:22, :130:67, :132:22, :136:{39,53,75}, :139:22, :143:{39,53,75}, :147:66, :150:22, :153:67, :156:22, :159:{39,54}, :163:22, :168:{35,52}, :169:{23,66}, :170:22]
wire _T_12 = f4_scnt == f4_entry_p_cnt & (&f4_entry_conf); // @[loop.scala:89:27, :91:27, :97:{23,42,59}]
wire _GEN_8 = f4_fire & f4_entry_tag == f4_tag; // @[loop.scala:65:22, :88:27, :89:27, :90:27, :95:20, :96:{26,38}, :97:68]
always @(posedge clock) begin // @[loop.scala:39:9]
if (reset) begin // @[loop.scala:39:9]
doing_reset <= 1'h1; // @[loop.scala:59:30]
reset_idx <= 4'h0; // @[loop.scala:60:28]
end
else begin // @[loop.scala:39:9]
doing_reset <= reset_idx != 4'hF & doing_reset; // @[loop.scala:59:30, :60:28, :62:{21,38,52}]
reset_idx <= _reset_idx_T_1; // @[loop.scala:60:28, :61:28]
end
if (doing_reset & reset_idx == 4'h0) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_0_tag <= 10'h0; // @[loop.scala:65:22]
entries_0_conf <= 3'h0; // @[loop.scala:65:22]
entries_0_age <= 3'h0; // @[loop.scala:65:22]
entries_0_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h0 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h0) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_0_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_0_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_0_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_0_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_0_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :98:33]
entries_0_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :99:33]
entries_0_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :102:33]
entries_0_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h0) // @[loop.scala:92:27, :101:33]
entries_0_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h1) begin // @[loop.scala:59:30, :60:28, :102:80, :114:49, :175:24, :176:26]
entries_1_tag <= 10'h0; // @[loop.scala:65:22]
entries_1_conf <= 3'h0; // @[loop.scala:65:22]
entries_1_age <= 3'h0; // @[loop.scala:65:22]
entries_1_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h1 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h1) begin // @[loop.scala:39:9, :65:22, :95:20, :102:80, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_1_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_1_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_1_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_1_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_1_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :98:33, :102:80]
entries_1_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :99:33, :102:80]
entries_1_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :102:{33,80}]
entries_1_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h1) // @[loop.scala:92:27, :101:33, :102:80]
entries_1_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h2) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_2_tag <= 10'h0; // @[loop.scala:65:22]
entries_2_conf <= 3'h0; // @[loop.scala:65:22]
entries_2_age <= 3'h0; // @[loop.scala:65:22]
entries_2_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h2 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h2) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_2_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_2_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_2_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_2_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_2_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :98:33]
entries_2_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :99:33]
entries_2_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :102:33]
entries_2_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h2) // @[loop.scala:92:27, :101:33]
entries_2_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h3) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_3_tag <= 10'h0; // @[loop.scala:65:22]
entries_3_conf <= 3'h0; // @[loop.scala:65:22]
entries_3_age <= 3'h0; // @[loop.scala:65:22]
entries_3_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h3 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h3) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_3_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_3_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_3_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_3_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_3_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :98:33]
entries_3_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :99:33]
entries_3_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :102:33]
entries_3_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h3) // @[loop.scala:92:27, :101:33]
entries_3_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h4) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_4_tag <= 10'h0; // @[loop.scala:65:22]
entries_4_conf <= 3'h0; // @[loop.scala:65:22]
entries_4_age <= 3'h0; // @[loop.scala:65:22]
entries_4_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h4 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h4) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_4_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_4_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_4_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_4_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_4_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :98:33]
entries_4_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :99:33]
entries_4_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :102:33]
entries_4_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h4) // @[loop.scala:92:27, :101:33]
entries_4_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h5) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_5_tag <= 10'h0; // @[loop.scala:65:22]
entries_5_conf <= 3'h0; // @[loop.scala:65:22]
entries_5_age <= 3'h0; // @[loop.scala:65:22]
entries_5_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h5 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h5) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_5_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_5_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_5_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_5_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_5_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :98:33]
entries_5_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :99:33]
entries_5_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :102:33]
entries_5_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h5) // @[loop.scala:92:27, :101:33]
entries_5_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h6) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_6_tag <= 10'h0; // @[loop.scala:65:22]
entries_6_conf <= 3'h0; // @[loop.scala:65:22]
entries_6_age <= 3'h0; // @[loop.scala:65:22]
entries_6_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h6 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h6) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_6_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_6_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_6_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_6_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_6_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :98:33]
entries_6_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :99:33]
entries_6_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :102:33]
entries_6_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h6) // @[loop.scala:92:27, :101:33]
entries_6_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h7) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_7_tag <= 10'h0; // @[loop.scala:65:22]
entries_7_conf <= 3'h0; // @[loop.scala:65:22]
entries_7_age <= 3'h0; // @[loop.scala:65:22]
entries_7_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h7 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h7) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_7_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_7_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_7_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_7_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_7_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :98:33]
entries_7_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :99:33]
entries_7_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :102:33]
entries_7_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h7) // @[loop.scala:92:27, :101:33]
entries_7_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h8) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_8_tag <= 10'h0; // @[loop.scala:65:22]
entries_8_conf <= 3'h0; // @[loop.scala:65:22]
entries_8_age <= 3'h0; // @[loop.scala:65:22]
entries_8_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h8 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h8) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_8_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_8_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_8_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_8_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_8_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :98:33]
entries_8_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :99:33]
entries_8_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :102:33]
entries_8_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h8) // @[loop.scala:92:27, :101:33]
entries_8_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'h9) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_9_tag <= 10'h0; // @[loop.scala:65:22]
entries_9_conf <= 3'h0; // @[loop.scala:65:22]
entries_9_age <= 3'h0; // @[loop.scala:65:22]
entries_9_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'h9 : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'h9) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_9_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_9_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_9_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_9_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_9_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :98:33]
entries_9_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :99:33]
entries_9_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :102:33]
entries_9_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'h9) // @[loop.scala:92:27, :101:33]
entries_9_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hA) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_10_tag <= 10'h0; // @[loop.scala:65:22]
entries_10_conf <= 3'h0; // @[loop.scala:65:22]
entries_10_age <= 3'h0; // @[loop.scala:65:22]
entries_10_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hA : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hA) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_10_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_10_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_10_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_10_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_10_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :98:33]
entries_10_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :99:33]
entries_10_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :102:33]
entries_10_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hA) // @[loop.scala:92:27, :101:33]
entries_10_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hB) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_11_tag <= 10'h0; // @[loop.scala:65:22]
entries_11_conf <= 3'h0; // @[loop.scala:65:22]
entries_11_age <= 3'h0; // @[loop.scala:65:22]
entries_11_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hB : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hB) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_11_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_11_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_11_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_11_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_11_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :98:33]
entries_11_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :99:33]
entries_11_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :102:33]
entries_11_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hB) // @[loop.scala:92:27, :101:33]
entries_11_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hC) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_12_tag <= 10'h0; // @[loop.scala:65:22]
entries_12_conf <= 3'h0; // @[loop.scala:65:22]
entries_12_age <= 3'h0; // @[loop.scala:65:22]
entries_12_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hC : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hC) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_12_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_12_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_12_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_12_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_12_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :98:33]
entries_12_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :99:33]
entries_12_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :102:33]
entries_12_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hC) // @[loop.scala:92:27, :101:33]
entries_12_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hD) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_13_tag <= 10'h0; // @[loop.scala:65:22]
entries_13_conf <= 3'h0; // @[loop.scala:65:22]
entries_13_age <= 3'h0; // @[loop.scala:65:22]
entries_13_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hD : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hD) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_13_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_13_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_13_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_13_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_13_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :98:33]
entries_13_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :99:33]
entries_13_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :102:33]
entries_13_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hD) // @[loop.scala:92:27, :101:33]
entries_13_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & reset_idx == 4'hE) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_14_tag <= 10'h0; // @[loop.scala:65:22]
entries_14_conf <= 3'h0; // @[loop.scala:65:22]
entries_14_age <= 3'h0; // @[loop.scala:65:22]
entries_14_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? io_update_idx_0[3:0] == 4'hE : _T_58 & _T_62 & io_update_idx_0[3:0] == 4'hE) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_14_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_14_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_14_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_14_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_14_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :98:33]
entries_14_age <= 3'h7; // @[loop.scala:65:22]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :99:33]
entries_14_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :102:33]
entries_14_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (f4_idx[3:0] == 4'hE) // @[loop.scala:92:27, :101:33]
entries_14_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
if (doing_reset & (&reset_idx)) begin // @[loop.scala:59:30, :60:28, :114:49, :175:24, :176:26]
entries_15_tag <= 10'h0; // @[loop.scala:65:22]
entries_15_conf <= 3'h0; // @[loop.scala:65:22]
entries_15_age <= 3'h0; // @[loop.scala:65:22]
entries_15_p_cnt <= 10'h0; // @[loop.scala:65:22]
entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else if (_T_22 ? (&(io_update_idx_0[3:0])) : _T_58 & _T_62 & (&(io_update_idx_0[3:0]))) begin // @[loop.scala:39:9, :65:22, :95:20, :114:{32,49}, :167:30, :168:{35,52}, :169:{23,66}, :171:32]
entries_15_tag <= wentry_tag; // @[loop.scala:65:22, :112:26]
entries_15_conf <= wentry_conf; // @[loop.scala:65:22, :112:26]
entries_15_age <= wentry_age; // @[loop.scala:65:22, :112:26]
entries_15_p_cnt <= wentry_p_cnt; // @[loop.scala:65:22, :112:26]
entries_15_s_cnt <= wentry_s_cnt; // @[loop.scala:65:22, :112:26]
end
else if (_GEN_8) begin // @[loop.scala:65:22, :95:20, :96:38, :97:68]
if (_T_12) begin // @[loop.scala:97:42]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :98:33]
entries_15_age <= 3'h7; // @[loop.scala:65:22]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :99:33]
entries_15_s_cnt <= 10'h0; // @[loop.scala:65:22]
end
else begin // @[loop.scala:97:42]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :102:33]
entries_15_age <= _entries_age_T_3; // @[loop.scala:65:22, :102:39]
if (&(f4_idx[3:0])) // @[loop.scala:92:27, :101:33]
entries_15_s_cnt <= _entries_s_cnt_T_1; // @[loop.scala:65:22, :101:44]
end
end
f3_entry_tag <= f2_entry_tag; // @[loop.scala:66:28, :72:27]
f3_entry_conf <= f2_entry_conf; // @[loop.scala:66:28, :72:27]
f3_entry_age <= f2_entry_age; // @[loop.scala:66:28, :72:27]
f3_entry_p_cnt <= f2_entry_p_cnt; // @[loop.scala:66:28, :72:27]
f3_entry_s_cnt <= f2_entry_s_cnt; // @[loop.scala:66:28, :72:27]
f3_scnt_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :73:69]
f3_tag <= _f3_tag_T; // @[loop.scala:76:{27,41}]
f4_fire <= io_f3_req_fire_0; // @[loop.scala:39:9, :88:27]
f4_entry_tag <= f3_entry_tag; // @[loop.scala:72:27, :89:27]
f4_entry_conf <= f3_entry_conf; // @[loop.scala:72:27, :89:27]
f4_entry_age <= f3_entry_age; // @[loop.scala:72:27, :89:27]
f4_entry_p_cnt <= f3_entry_p_cnt; // @[loop.scala:72:27, :89:27]
f4_entry_s_cnt <= f3_entry_s_cnt; // @[loop.scala:72:27, :89:27]
f4_tag <= f3_tag; // @[loop.scala:76:27, :90:27]
f4_scnt <= f3_scnt; // @[loop.scala:73:23, :91:27]
f4_idx_REG <= io_f2_req_idx_0; // @[loop.scala:39:9, :92:35]
f4_idx <= f4_idx_REG; // @[loop.scala:92:{27,35}]
always @(posedge)
assign io_f3_pred = io_f3_pred_0; // @[loop.scala:39:9]
assign io_f3_meta_s_cnt = io_f3_meta_s_cnt_0; // @[loop.scala:39:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_156 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_sink_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_170
connect io_out_sink_valid_0.clock, clock
connect io_out_sink_valid_0.reset, reset
connect io_out_sink_valid_0.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_sink_valid_0.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_156( // @[AsyncQueue.scala:58:7]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in = 1'h1; // @[ShiftReg.scala:45:23]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_170 io_out_sink_valid_0 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module DCache :
input clock : Clock
input reset : Reset
output auto : { flip mmio_address_prefix_sink_in : UInt<1>, flip hart_id_sink_in : UInt<1>, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
output io : { flip cpu : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<34>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<21>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<33>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, errors : { bus : { valid : UInt<1>, bits : UInt<32>}}, tlb_port : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<34>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}, s1_resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<34>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, flip s2_kill : UInt<1>}}
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.user.amba_prot.fetch
invalidate nodeOut.a.bits.user.amba_prot.secure
invalidate nodeOut.a.bits.user.amba_prot.privileged
invalidate nodeOut.a.bits.user.amba_prot.writealloc
invalidate nodeOut.a.bits.user.amba_prot.readalloc
invalidate nodeOut.a.bits.user.amba_prot.modifiable
invalidate nodeOut.a.bits.user.amba_prot.bufferable
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
wire hartIdSinkNodeOptIn : UInt<1>
invalidate hartIdSinkNodeOptIn
wire mmioAddressPrefixSinkNodeOptIn : UInt<1>
invalidate mmioAddressPrefixSinkNodeOptIn
connect auto.out, nodeOut
connect hartIdSinkNodeOptIn, auto.hart_id_sink_in
connect mmioAddressPrefixSinkNodeOptIn, auto.mmio_address_prefix_sink_in
reg clock_en_reg : UInt<1>, clock
connect io.cpu.clock_enabled, clock_en_reg
inst tlb of DTLB
connect tlb.clock, clock
connect tlb.reset, reset
inst pma_checker of DTLB_1
connect pma_checker.clock, clock
connect pma_checker.reset, reset
wire replace : UInt<1>
connect replace, UInt<1>(0h0)
inst lfsr_prng of MaxPeriodFibonacciLFSR
connect lfsr_prng.clock, clock
connect lfsr_prng.reset, reset
connect lfsr_prng.io.seed.valid, UInt<1>(0h0)
invalidate lfsr_prng.io.seed.bits[0]
invalidate lfsr_prng.io.seed.bits[1]
invalidate lfsr_prng.io.seed.bits[2]
invalidate lfsr_prng.io.seed.bits[3]
invalidate lfsr_prng.io.seed.bits[4]
invalidate lfsr_prng.io.seed.bits[5]
invalidate lfsr_prng.io.seed.bits[6]
invalidate lfsr_prng.io.seed.bits[7]
invalidate lfsr_prng.io.seed.bits[8]
invalidate lfsr_prng.io.seed.bits[9]
invalidate lfsr_prng.io.seed.bits[10]
invalidate lfsr_prng.io.seed.bits[11]
invalidate lfsr_prng.io.seed.bits[12]
invalidate lfsr_prng.io.seed.bits[13]
invalidate lfsr_prng.io.seed.bits[14]
invalidate lfsr_prng.io.seed.bits[15]
connect lfsr_prng.io.increment, replace
node lfsr_lo_lo_lo = cat(lfsr_prng.io.out[1], lfsr_prng.io.out[0])
node lfsr_lo_lo_hi = cat(lfsr_prng.io.out[3], lfsr_prng.io.out[2])
node lfsr_lo_lo = cat(lfsr_lo_lo_hi, lfsr_lo_lo_lo)
node lfsr_lo_hi_lo = cat(lfsr_prng.io.out[5], lfsr_prng.io.out[4])
node lfsr_lo_hi_hi = cat(lfsr_prng.io.out[7], lfsr_prng.io.out[6])
node lfsr_lo_hi = cat(lfsr_lo_hi_hi, lfsr_lo_hi_lo)
node lfsr_lo = cat(lfsr_lo_hi, lfsr_lo_lo)
node lfsr_hi_lo_lo = cat(lfsr_prng.io.out[9], lfsr_prng.io.out[8])
node lfsr_hi_lo_hi = cat(lfsr_prng.io.out[11], lfsr_prng.io.out[10])
node lfsr_hi_lo = cat(lfsr_hi_lo_hi, lfsr_hi_lo_lo)
node lfsr_hi_hi_lo = cat(lfsr_prng.io.out[13], lfsr_prng.io.out[12])
node lfsr_hi_hi_hi = cat(lfsr_prng.io.out[15], lfsr_prng.io.out[14])
node lfsr_hi_hi = cat(lfsr_hi_hi_hi, lfsr_hi_hi_lo)
node lfsr_hi = cat(lfsr_hi_hi, lfsr_hi_lo)
node lfsr = cat(lfsr_hi, lfsr_lo)
inst metaArb of Arbiter8_DCacheMetadataReq
connect metaArb.clock, clock
connect metaArb.reset, reset
smem rockettile_dcache_tag_array : UInt<20>[1] [256]
inst data of DCacheDataArray
connect data.clock, clock
connect data.reset, reset
inst dataArb of Arbiter4_DCacheDataReq
connect dataArb.clock, clock
connect dataArb.reset, reset
connect dataArb.io.in[1].bits.wdata, dataArb.io.in[0].bits.wdata
connect dataArb.io.in[2].bits.wdata, dataArb.io.in[0].bits.wdata
connect dataArb.io.in[3].bits.wdata, dataArb.io.in[0].bits.wdata
connect data.io.req.bits, dataArb.io.out.bits
connect data.io.req.valid, dataArb.io.out.valid
connect dataArb.io.out.ready, UInt<1>(0h1)
connect metaArb.io.out.ready, clock_en_reg
wire tl_out_a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
wire nodeOut_a_deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect nodeOut_a_deq.valid, tl_out_a.valid
connect nodeOut_a_deq.bits, tl_out_a.bits
connect tl_out_a.ready, nodeOut_a_deq.ready
connect nodeOut.a, nodeOut_a_deq
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect _WIRE.bits.user.amba_prot.secure, UInt<1>(0h0)
connect _WIRE.bits.user.amba_prot.privileged, UInt<1>(0h0)
connect _WIRE.bits.user.amba_prot.writealloc, UInt<1>(0h0)
connect _WIRE.bits.user.amba_prot.readalloc, UInt<1>(0h0)
connect _WIRE.bits.user.amba_prot.modifiable, UInt<1>(0h0)
connect _WIRE.bits.user.amba_prot.bufferable, UInt<1>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<3>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire tl_out_c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect tl_out_c.bits, _WIRE.bits
connect tl_out_c.valid, _WIRE.valid
connect tl_out_c.ready, _WIRE.ready
node _s1_valid_T = and(io.cpu.req.ready, io.cpu.req.valid)
regreset s1_valid : UInt<1>, clock, reset, UInt<1>(0h0)
connect s1_valid, _s1_valid_T
wire _s1_probe_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _s1_probe_WIRE.bits.corrupt, UInt<1>(0h0)
connect _s1_probe_WIRE.bits.data, UInt<64>(0h0)
connect _s1_probe_WIRE.bits.mask, UInt<8>(0h0)
connect _s1_probe_WIRE.bits.address, UInt<32>(0h0)
connect _s1_probe_WIRE.bits.source, UInt<1>(0h0)
connect _s1_probe_WIRE.bits.size, UInt<4>(0h0)
connect _s1_probe_WIRE.bits.param, UInt<2>(0h0)
connect _s1_probe_WIRE.bits.opcode, UInt<3>(0h0)
connect _s1_probe_WIRE.valid, UInt<1>(0h0)
connect _s1_probe_WIRE.ready, UInt<1>(0h0)
wire _s1_probe_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _s1_probe_WIRE_1.bits, _s1_probe_WIRE.bits
connect _s1_probe_WIRE_1.valid, _s1_probe_WIRE.valid
connect _s1_probe_WIRE_1.ready, _s1_probe_WIRE.ready
node _s1_probe_T = and(_s1_probe_WIRE_1.ready, _s1_probe_WIRE_1.valid)
regreset s1_probe : UInt<1>, clock, reset, UInt<1>(0h0)
connect s1_probe, _s1_probe_T
wire _probe_bits_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _probe_bits_WIRE.bits.corrupt, UInt<1>(0h0)
connect _probe_bits_WIRE.bits.data, UInt<64>(0h0)
connect _probe_bits_WIRE.bits.mask, UInt<8>(0h0)
connect _probe_bits_WIRE.bits.address, UInt<32>(0h0)
connect _probe_bits_WIRE.bits.source, UInt<1>(0h0)
connect _probe_bits_WIRE.bits.size, UInt<4>(0h0)
connect _probe_bits_WIRE.bits.param, UInt<2>(0h0)
connect _probe_bits_WIRE.bits.opcode, UInt<3>(0h0)
connect _probe_bits_WIRE.valid, UInt<1>(0h0)
connect _probe_bits_WIRE.ready, UInt<1>(0h0)
wire _probe_bits_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _probe_bits_WIRE_1.bits, _probe_bits_WIRE.bits
connect _probe_bits_WIRE_1.valid, _probe_bits_WIRE.valid
connect _probe_bits_WIRE_1.ready, _probe_bits_WIRE.ready
wire _probe_bits_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _probe_bits_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _probe_bits_WIRE_2.bits.data, UInt<64>(0h0)
connect _probe_bits_WIRE_2.bits.mask, UInt<8>(0h0)
connect _probe_bits_WIRE_2.bits.address, UInt<32>(0h0)
connect _probe_bits_WIRE_2.bits.source, UInt<1>(0h0)
connect _probe_bits_WIRE_2.bits.size, UInt<4>(0h0)
connect _probe_bits_WIRE_2.bits.param, UInt<2>(0h0)
connect _probe_bits_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _probe_bits_WIRE_2.valid, UInt<1>(0h0)
connect _probe_bits_WIRE_2.ready, UInt<1>(0h0)
wire _probe_bits_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _probe_bits_WIRE_3.bits, _probe_bits_WIRE_2.bits
connect _probe_bits_WIRE_3.valid, _probe_bits_WIRE_2.valid
connect _probe_bits_WIRE_3.ready, _probe_bits_WIRE_2.ready
node _probe_bits_T = and(_probe_bits_WIRE_3.ready, _probe_bits_WIRE_3.valid)
reg probe_bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock
when _probe_bits_T :
connect probe_bits, _probe_bits_WIRE_1.bits
wire s1_nack : UInt<1>
connect s1_nack, UInt<1>(0h0)
node _s1_valid_masked_T = eq(io.cpu.s1_kill, UInt<1>(0h0))
node s1_valid_masked = and(s1_valid, _s1_valid_masked_T)
node _s1_valid_not_nacked_T = eq(s1_nack, UInt<1>(0h0))
node s1_valid_not_nacked = and(s1_valid, _s1_valid_not_nacked_T)
node _s1_tlb_req_valid_T = and(io.tlb_port.req.ready, io.tlb_port.req.valid)
regreset s1_tlb_req_valid : UInt<1>, clock, reset, UInt<1>(0h0)
connect s1_tlb_req_valid, _s1_tlb_req_valid_T
regreset s2_tlb_req_valid : UInt<1>, clock, reset, UInt<1>(0h0)
connect s2_tlb_req_valid, s1_tlb_req_valid
node _s0_clk_en_T = eq(metaArb.io.out.bits.write, UInt<1>(0h0))
node s0_clk_en = and(metaArb.io.out.valid, _s0_clk_en_T)
wire s0_req : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}
connect s0_req, io.cpu.req.bits
node _s0_req_addr_T = shr(metaArb.io.out.bits.addr, 6)
node _s0_req_addr_T_1 = bits(io.cpu.req.bits.addr, 5, 0)
node _s0_req_addr_T_2 = cat(_s0_req_addr_T, _s0_req_addr_T_1)
connect s0_req.addr, _s0_req_addr_T_2
node _T = eq(metaArb.io.in[7].ready, UInt<1>(0h0))
when _T :
connect s0_req.phys, UInt<1>(0h1)
reg s1_req : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}, clock
when s0_clk_en :
connect s1_req, s0_req
node _s1_vaddr_T = shr(s1_req.addr, 14)
node _s1_vaddr_T_1 = bits(s1_req.addr, 13, 0)
node s1_vaddr = cat(_s1_vaddr_T, _s1_vaddr_T_1)
wire s0_tlb_req : { vaddr : UInt<34>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}
connect s0_tlb_req, io.tlb_port.req.bits
node _T_1 = and(io.tlb_port.req.ready, io.tlb_port.req.valid)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
connect s0_tlb_req.passthrough, s0_req.phys
connect s0_tlb_req.vaddr, s0_req.addr
connect s0_tlb_req.size, s0_req.size
connect s0_tlb_req.cmd, s0_req.cmd
connect s0_tlb_req.prv, s0_req.dprv
connect s0_tlb_req.v, s0_req.dv
node _s1_tlb_req_T = or(s0_clk_en, io.tlb_port.req.valid)
reg s1_tlb_req : { vaddr : UInt<34>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}, clock
when _s1_tlb_req_T :
connect s1_tlb_req, s0_tlb_req
node _s1_read_T = eq(s1_req.cmd, UInt<1>(0h0))
node _s1_read_T_1 = eq(s1_req.cmd, UInt<5>(0h10))
node _s1_read_T_2 = eq(s1_req.cmd, UInt<3>(0h6))
node _s1_read_T_3 = eq(s1_req.cmd, UInt<3>(0h7))
node _s1_read_T_4 = or(_s1_read_T, _s1_read_T_1)
node _s1_read_T_5 = or(_s1_read_T_4, _s1_read_T_2)
node _s1_read_T_6 = or(_s1_read_T_5, _s1_read_T_3)
node _s1_read_T_7 = eq(s1_req.cmd, UInt<3>(0h4))
node _s1_read_T_8 = eq(s1_req.cmd, UInt<4>(0h9))
node _s1_read_T_9 = eq(s1_req.cmd, UInt<4>(0ha))
node _s1_read_T_10 = eq(s1_req.cmd, UInt<4>(0hb))
node _s1_read_T_11 = or(_s1_read_T_7, _s1_read_T_8)
node _s1_read_T_12 = or(_s1_read_T_11, _s1_read_T_9)
node _s1_read_T_13 = or(_s1_read_T_12, _s1_read_T_10)
node _s1_read_T_14 = eq(s1_req.cmd, UInt<4>(0h8))
node _s1_read_T_15 = eq(s1_req.cmd, UInt<4>(0hc))
node _s1_read_T_16 = eq(s1_req.cmd, UInt<4>(0hd))
node _s1_read_T_17 = eq(s1_req.cmd, UInt<4>(0he))
node _s1_read_T_18 = eq(s1_req.cmd, UInt<4>(0hf))
node _s1_read_T_19 = or(_s1_read_T_14, _s1_read_T_15)
node _s1_read_T_20 = or(_s1_read_T_19, _s1_read_T_16)
node _s1_read_T_21 = or(_s1_read_T_20, _s1_read_T_17)
node _s1_read_T_22 = or(_s1_read_T_21, _s1_read_T_18)
node _s1_read_T_23 = or(_s1_read_T_13, _s1_read_T_22)
node s1_read = or(_s1_read_T_6, _s1_read_T_23)
node _s1_write_T = eq(s1_req.cmd, UInt<1>(0h1))
node _s1_write_T_1 = eq(s1_req.cmd, UInt<5>(0h11))
node _s1_write_T_2 = or(_s1_write_T, _s1_write_T_1)
node _s1_write_T_3 = eq(s1_req.cmd, UInt<3>(0h7))
node _s1_write_T_4 = or(_s1_write_T_2, _s1_write_T_3)
node _s1_write_T_5 = eq(s1_req.cmd, UInt<3>(0h4))
node _s1_write_T_6 = eq(s1_req.cmd, UInt<4>(0h9))
node _s1_write_T_7 = eq(s1_req.cmd, UInt<4>(0ha))
node _s1_write_T_8 = eq(s1_req.cmd, UInt<4>(0hb))
node _s1_write_T_9 = or(_s1_write_T_5, _s1_write_T_6)
node _s1_write_T_10 = or(_s1_write_T_9, _s1_write_T_7)
node _s1_write_T_11 = or(_s1_write_T_10, _s1_write_T_8)
node _s1_write_T_12 = eq(s1_req.cmd, UInt<4>(0h8))
node _s1_write_T_13 = eq(s1_req.cmd, UInt<4>(0hc))
node _s1_write_T_14 = eq(s1_req.cmd, UInt<4>(0hd))
node _s1_write_T_15 = eq(s1_req.cmd, UInt<4>(0he))
node _s1_write_T_16 = eq(s1_req.cmd, UInt<4>(0hf))
node _s1_write_T_17 = or(_s1_write_T_12, _s1_write_T_13)
node _s1_write_T_18 = or(_s1_write_T_17, _s1_write_T_14)
node _s1_write_T_19 = or(_s1_write_T_18, _s1_write_T_15)
node _s1_write_T_20 = or(_s1_write_T_19, _s1_write_T_16)
node _s1_write_T_21 = or(_s1_write_T_11, _s1_write_T_20)
node s1_write = or(_s1_write_T_4, _s1_write_T_21)
node s1_readwrite = or(s1_read, s1_write)
node _s1_sfence_T = eq(s1_req.cmd, UInt<5>(0h14))
node _s1_sfence_T_1 = eq(s1_req.cmd, UInt<5>(0h15))
node _s1_sfence_T_2 = or(_s1_sfence_T, _s1_sfence_T_1)
node _s1_sfence_T_3 = eq(s1_req.cmd, UInt<5>(0h16))
node s1_sfence = or(_s1_sfence_T_2, _s1_sfence_T_3)
node _s1_flush_line_T = eq(s1_req.cmd, UInt<3>(0h5))
node _s1_flush_line_T_1 = bits(s1_req.size, 0, 0)
node s1_flush_line = and(_s1_flush_line_T, _s1_flush_line_T_1)
reg s1_flush_valid : UInt<1>, clock
wire s1_waw_hazard : UInt<1>
regreset flushed : UInt<1>, clock, reset, UInt<1>(0h1)
regreset flushing : UInt<1>, clock, reset, UInt<1>(0h0)
reg flushing_req : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}, clock
regreset cached_grant_wait : UInt<1>, clock, reset, UInt<1>(0h0)
regreset resetting : UInt<1>, clock, reset, UInt<1>(0h0)
regreset flushCounter : UInt<8>, clock, reset, UInt<8>(0h0)
regreset release_ack_wait : UInt<1>, clock, reset, UInt<1>(0h0)
reg release_ack_addr : UInt<32>, clock
regreset release_state : UInt<4>, clock, reset, UInt<4>(0h0)
reg refill_way : UInt, clock
wire any_pstore_valid : UInt<1>
node _inWriteback_T = eq(release_state, UInt<4>(0h1))
node _inWriteback_T_1 = eq(release_state, UInt<4>(0h2))
node inWriteback = or(_inWriteback_T, _inWriteback_T_1)
wire releaseWay : UInt
node _io_cpu_req_ready_T = eq(release_state, UInt<4>(0h0))
node _io_cpu_req_ready_T_1 = eq(cached_grant_wait, UInt<1>(0h0))
node _io_cpu_req_ready_T_2 = and(_io_cpu_req_ready_T, _io_cpu_req_ready_T_1)
node _io_cpu_req_ready_T_3 = eq(s1_nack, UInt<1>(0h0))
node _io_cpu_req_ready_T_4 = and(_io_cpu_req_ready_T_2, _io_cpu_req_ready_T_3)
connect io.cpu.req.ready, _io_cpu_req_ready_T_4
wire _uncachedInFlight_WIRE : UInt<1>[1]
connect _uncachedInFlight_WIRE[0], UInt<1>(0h0)
regreset uncachedInFlight : UInt<1>[1], clock, reset, _uncachedInFlight_WIRE
reg uncachedReqs : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}[1], clock
wire uncachedResp : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}
invalidate uncachedResp.mask
invalidate uncachedResp.data
invalidate uncachedResp.no_xcpt
invalidate uncachedResp.no_alloc
invalidate uncachedResp.no_resp
invalidate uncachedResp.phys
invalidate uncachedResp.dv
invalidate uncachedResp.dprv
invalidate uncachedResp.signed
invalidate uncachedResp.size
invalidate uncachedResp.cmd
invalidate uncachedResp.tag
invalidate uncachedResp.addr
node _s0_read_T = eq(io.cpu.req.bits.cmd, UInt<1>(0h0))
node _s0_read_T_1 = eq(io.cpu.req.bits.cmd, UInt<5>(0h10))
node _s0_read_T_2 = eq(io.cpu.req.bits.cmd, UInt<3>(0h6))
node _s0_read_T_3 = eq(io.cpu.req.bits.cmd, UInt<3>(0h7))
node _s0_read_T_4 = or(_s0_read_T, _s0_read_T_1)
node _s0_read_T_5 = or(_s0_read_T_4, _s0_read_T_2)
node _s0_read_T_6 = or(_s0_read_T_5, _s0_read_T_3)
node _s0_read_T_7 = eq(io.cpu.req.bits.cmd, UInt<3>(0h4))
node _s0_read_T_8 = eq(io.cpu.req.bits.cmd, UInt<4>(0h9))
node _s0_read_T_9 = eq(io.cpu.req.bits.cmd, UInt<4>(0ha))
node _s0_read_T_10 = eq(io.cpu.req.bits.cmd, UInt<4>(0hb))
node _s0_read_T_11 = or(_s0_read_T_7, _s0_read_T_8)
node _s0_read_T_12 = or(_s0_read_T_11, _s0_read_T_9)
node _s0_read_T_13 = or(_s0_read_T_12, _s0_read_T_10)
node _s0_read_T_14 = eq(io.cpu.req.bits.cmd, UInt<4>(0h8))
node _s0_read_T_15 = eq(io.cpu.req.bits.cmd, UInt<4>(0hc))
node _s0_read_T_16 = eq(io.cpu.req.bits.cmd, UInt<4>(0hd))
node _s0_read_T_17 = eq(io.cpu.req.bits.cmd, UInt<4>(0he))
node _s0_read_T_18 = eq(io.cpu.req.bits.cmd, UInt<4>(0hf))
node _s0_read_T_19 = or(_s0_read_T_14, _s0_read_T_15)
node _s0_read_T_20 = or(_s0_read_T_19, _s0_read_T_16)
node _s0_read_T_21 = or(_s0_read_T_20, _s0_read_T_17)
node _s0_read_T_22 = or(_s0_read_T_21, _s0_read_T_18)
node _s0_read_T_23 = or(_s0_read_T_13, _s0_read_T_22)
node s0_read = or(_s0_read_T_6, _s0_read_T_23)
node _dataArb_io_in_3_valid_res_T = eq(io.cpu.req.bits.cmd, UInt<1>(0h1))
node _dataArb_io_in_3_valid_res_T_1 = eq(io.cpu.req.bits.cmd, UInt<2>(0h3))
node _dataArb_io_in_3_valid_res_T_2 = or(_dataArb_io_in_3_valid_res_T, _dataArb_io_in_3_valid_res_T_1)
node _dataArb_io_in_3_valid_res_T_3 = eq(_dataArb_io_in_3_valid_res_T_2, UInt<1>(0h0))
node _dataArb_io_in_3_valid_res_T_4 = lt(io.cpu.req.bits.size, UInt<1>(0h0))
node dataArb_io_in_3_valid_res = or(_dataArb_io_in_3_valid_res_T_3, _dataArb_io_in_3_valid_res_T_4)
node _dataArb_io_in_3_valid_T = eq(io.cpu.req.bits.cmd, UInt<1>(0h0))
node _dataArb_io_in_3_valid_T_1 = eq(io.cpu.req.bits.cmd, UInt<5>(0h10))
node _dataArb_io_in_3_valid_T_2 = eq(io.cpu.req.bits.cmd, UInt<3>(0h6))
node _dataArb_io_in_3_valid_T_3 = eq(io.cpu.req.bits.cmd, UInt<3>(0h7))
node _dataArb_io_in_3_valid_T_4 = or(_dataArb_io_in_3_valid_T, _dataArb_io_in_3_valid_T_1)
node _dataArb_io_in_3_valid_T_5 = or(_dataArb_io_in_3_valid_T_4, _dataArb_io_in_3_valid_T_2)
node _dataArb_io_in_3_valid_T_6 = or(_dataArb_io_in_3_valid_T_5, _dataArb_io_in_3_valid_T_3)
node _dataArb_io_in_3_valid_T_7 = eq(io.cpu.req.bits.cmd, UInt<3>(0h4))
node _dataArb_io_in_3_valid_T_8 = eq(io.cpu.req.bits.cmd, UInt<4>(0h9))
node _dataArb_io_in_3_valid_T_9 = eq(io.cpu.req.bits.cmd, UInt<4>(0ha))
node _dataArb_io_in_3_valid_T_10 = eq(io.cpu.req.bits.cmd, UInt<4>(0hb))
node _dataArb_io_in_3_valid_T_11 = or(_dataArb_io_in_3_valid_T_7, _dataArb_io_in_3_valid_T_8)
node _dataArb_io_in_3_valid_T_12 = or(_dataArb_io_in_3_valid_T_11, _dataArb_io_in_3_valid_T_9)
node _dataArb_io_in_3_valid_T_13 = or(_dataArb_io_in_3_valid_T_12, _dataArb_io_in_3_valid_T_10)
node _dataArb_io_in_3_valid_T_14 = eq(io.cpu.req.bits.cmd, UInt<4>(0h8))
node _dataArb_io_in_3_valid_T_15 = eq(io.cpu.req.bits.cmd, UInt<4>(0hc))
node _dataArb_io_in_3_valid_T_16 = eq(io.cpu.req.bits.cmd, UInt<4>(0hd))
node _dataArb_io_in_3_valid_T_17 = eq(io.cpu.req.bits.cmd, UInt<4>(0he))
node _dataArb_io_in_3_valid_T_18 = eq(io.cpu.req.bits.cmd, UInt<4>(0hf))
node _dataArb_io_in_3_valid_T_19 = or(_dataArb_io_in_3_valid_T_14, _dataArb_io_in_3_valid_T_15)
node _dataArb_io_in_3_valid_T_20 = or(_dataArb_io_in_3_valid_T_19, _dataArb_io_in_3_valid_T_16)
node _dataArb_io_in_3_valid_T_21 = or(_dataArb_io_in_3_valid_T_20, _dataArb_io_in_3_valid_T_17)
node _dataArb_io_in_3_valid_T_22 = or(_dataArb_io_in_3_valid_T_21, _dataArb_io_in_3_valid_T_18)
node _dataArb_io_in_3_valid_T_23 = or(_dataArb_io_in_3_valid_T_13, _dataArb_io_in_3_valid_T_22)
node _dataArb_io_in_3_valid_T_24 = or(_dataArb_io_in_3_valid_T_6, _dataArb_io_in_3_valid_T_23)
node _dataArb_io_in_3_valid_T_25 = eq(io.cpu.req.bits.cmd, UInt<1>(0h1))
node _dataArb_io_in_3_valid_T_26 = eq(io.cpu.req.bits.cmd, UInt<5>(0h11))
node _dataArb_io_in_3_valid_T_27 = or(_dataArb_io_in_3_valid_T_25, _dataArb_io_in_3_valid_T_26)
node _dataArb_io_in_3_valid_T_28 = eq(io.cpu.req.bits.cmd, UInt<3>(0h7))
node _dataArb_io_in_3_valid_T_29 = or(_dataArb_io_in_3_valid_T_27, _dataArb_io_in_3_valid_T_28)
node _dataArb_io_in_3_valid_T_30 = eq(io.cpu.req.bits.cmd, UInt<3>(0h4))
node _dataArb_io_in_3_valid_T_31 = eq(io.cpu.req.bits.cmd, UInt<4>(0h9))
node _dataArb_io_in_3_valid_T_32 = eq(io.cpu.req.bits.cmd, UInt<4>(0ha))
node _dataArb_io_in_3_valid_T_33 = eq(io.cpu.req.bits.cmd, UInt<4>(0hb))
node _dataArb_io_in_3_valid_T_34 = or(_dataArb_io_in_3_valid_T_30, _dataArb_io_in_3_valid_T_31)
node _dataArb_io_in_3_valid_T_35 = or(_dataArb_io_in_3_valid_T_34, _dataArb_io_in_3_valid_T_32)
node _dataArb_io_in_3_valid_T_36 = or(_dataArb_io_in_3_valid_T_35, _dataArb_io_in_3_valid_T_33)
node _dataArb_io_in_3_valid_T_37 = eq(io.cpu.req.bits.cmd, UInt<4>(0h8))
node _dataArb_io_in_3_valid_T_38 = eq(io.cpu.req.bits.cmd, UInt<4>(0hc))
node _dataArb_io_in_3_valid_T_39 = eq(io.cpu.req.bits.cmd, UInt<4>(0hd))
node _dataArb_io_in_3_valid_T_40 = eq(io.cpu.req.bits.cmd, UInt<4>(0he))
node _dataArb_io_in_3_valid_T_41 = eq(io.cpu.req.bits.cmd, UInt<4>(0hf))
node _dataArb_io_in_3_valid_T_42 = or(_dataArb_io_in_3_valid_T_37, _dataArb_io_in_3_valid_T_38)
node _dataArb_io_in_3_valid_T_43 = or(_dataArb_io_in_3_valid_T_42, _dataArb_io_in_3_valid_T_39)
node _dataArb_io_in_3_valid_T_44 = or(_dataArb_io_in_3_valid_T_43, _dataArb_io_in_3_valid_T_40)
node _dataArb_io_in_3_valid_T_45 = or(_dataArb_io_in_3_valid_T_44, _dataArb_io_in_3_valid_T_41)
node _dataArb_io_in_3_valid_T_46 = or(_dataArb_io_in_3_valid_T_36, _dataArb_io_in_3_valid_T_45)
node _dataArb_io_in_3_valid_T_47 = or(_dataArb_io_in_3_valid_T_29, _dataArb_io_in_3_valid_T_46)
node _dataArb_io_in_3_valid_T_48 = eq(io.cpu.req.bits.cmd, UInt<5>(0h11))
node _dataArb_io_in_3_valid_T_49 = lt(io.cpu.req.bits.size, UInt<1>(0h0))
node _dataArb_io_in_3_valid_T_50 = or(_dataArb_io_in_3_valid_T_48, _dataArb_io_in_3_valid_T_49)
node _dataArb_io_in_3_valid_T_51 = and(_dataArb_io_in_3_valid_T_47, _dataArb_io_in_3_valid_T_50)
node _dataArb_io_in_3_valid_T_52 = or(_dataArb_io_in_3_valid_T_24, _dataArb_io_in_3_valid_T_51)
node _dataArb_io_in_3_valid_T_53 = eq(_dataArb_io_in_3_valid_T_52, UInt<1>(0h0))
node _dataArb_io_in_3_valid_T_54 = or(_dataArb_io_in_3_valid_T_53, dataArb_io_in_3_valid_res)
node _dataArb_io_in_3_valid_T_55 = asUInt(reset)
node _dataArb_io_in_3_valid_T_56 = eq(_dataArb_io_in_3_valid_T_55, UInt<1>(0h0))
when _dataArb_io_in_3_valid_T_56 :
node _dataArb_io_in_3_valid_T_57 = eq(_dataArb_io_in_3_valid_T_54, UInt<1>(0h0))
when _dataArb_io_in_3_valid_T_57 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at DCache.scala:1186 assert(!needsRead(req) || res)\n") : dataArb_io_in_3_valid_printf
assert(clock, _dataArb_io_in_3_valid_T_54, UInt<1>(0h1), "") : dataArb_io_in_3_valid_assert
node _dataArb_io_in_3_valid_T_58 = and(io.cpu.req.valid, dataArb_io_in_3_valid_res)
connect dataArb.io.in[3].valid, _dataArb_io_in_3_valid_T_58
connect dataArb.io.in[3].bits.way_en, dataArb.io.in[1].bits.way_en
connect dataArb.io.in[3].bits.eccMask, dataArb.io.in[1].bits.eccMask
connect dataArb.io.in[3].bits.wordMask, dataArb.io.in[1].bits.wordMask
connect dataArb.io.in[3].bits.wdata, dataArb.io.in[1].bits.wdata
connect dataArb.io.in[3].bits.write, dataArb.io.in[1].bits.write
connect dataArb.io.in[3].bits.addr, dataArb.io.in[1].bits.addr
connect dataArb.io.in[3].bits.write, UInt<1>(0h0)
node _dataArb_io_in_3_bits_addr_T = shr(io.cpu.req.bits.addr, 14)
node _dataArb_io_in_3_bits_addr_T_1 = bits(io.cpu.req.bits.addr, 13, 0)
node _dataArb_io_in_3_bits_addr_T_2 = cat(_dataArb_io_in_3_bits_addr_T, _dataArb_io_in_3_bits_addr_T_1)
connect dataArb.io.in[3].bits.addr, _dataArb_io_in_3_bits_addr_T_2
node _dataArb_io_in_3_bits_wordMask_T = mux(UInt<1>(0h1), UInt<8>(0hff), UInt<8>(0h0))
connect dataArb.io.in[3].bits.wordMask, _dataArb_io_in_3_bits_wordMask_T
node _dataArb_io_in_3_bits_eccMask_T = not(UInt<8>(0h0))
connect dataArb.io.in[3].bits.eccMask, _dataArb_io_in_3_bits_eccMask_T
node _dataArb_io_in_3_bits_way_en_T = not(UInt<1>(0h0))
connect dataArb.io.in[3].bits.way_en, _dataArb_io_in_3_bits_way_en_T
node _T_3 = eq(dataArb.io.in[3].ready, UInt<1>(0h0))
node _T_4 = and(_T_3, s0_read)
when _T_4 :
connect io.cpu.req.ready, UInt<1>(0h0)
node _s1_did_read_T = eq(io.cpu.req.bits.cmd, UInt<1>(0h0))
node _s1_did_read_T_1 = eq(io.cpu.req.bits.cmd, UInt<5>(0h10))
node _s1_did_read_T_2 = eq(io.cpu.req.bits.cmd, UInt<3>(0h6))
node _s1_did_read_T_3 = eq(io.cpu.req.bits.cmd, UInt<3>(0h7))
node _s1_did_read_T_4 = or(_s1_did_read_T, _s1_did_read_T_1)
node _s1_did_read_T_5 = or(_s1_did_read_T_4, _s1_did_read_T_2)
node _s1_did_read_T_6 = or(_s1_did_read_T_5, _s1_did_read_T_3)
node _s1_did_read_T_7 = eq(io.cpu.req.bits.cmd, UInt<3>(0h4))
node _s1_did_read_T_8 = eq(io.cpu.req.bits.cmd, UInt<4>(0h9))
node _s1_did_read_T_9 = eq(io.cpu.req.bits.cmd, UInt<4>(0ha))
node _s1_did_read_T_10 = eq(io.cpu.req.bits.cmd, UInt<4>(0hb))
node _s1_did_read_T_11 = or(_s1_did_read_T_7, _s1_did_read_T_8)
node _s1_did_read_T_12 = or(_s1_did_read_T_11, _s1_did_read_T_9)
node _s1_did_read_T_13 = or(_s1_did_read_T_12, _s1_did_read_T_10)
node _s1_did_read_T_14 = eq(io.cpu.req.bits.cmd, UInt<4>(0h8))
node _s1_did_read_T_15 = eq(io.cpu.req.bits.cmd, UInt<4>(0hc))
node _s1_did_read_T_16 = eq(io.cpu.req.bits.cmd, UInt<4>(0hd))
node _s1_did_read_T_17 = eq(io.cpu.req.bits.cmd, UInt<4>(0he))
node _s1_did_read_T_18 = eq(io.cpu.req.bits.cmd, UInt<4>(0hf))
node _s1_did_read_T_19 = or(_s1_did_read_T_14, _s1_did_read_T_15)
node _s1_did_read_T_20 = or(_s1_did_read_T_19, _s1_did_read_T_16)
node _s1_did_read_T_21 = or(_s1_did_read_T_20, _s1_did_read_T_17)
node _s1_did_read_T_22 = or(_s1_did_read_T_21, _s1_did_read_T_18)
node _s1_did_read_T_23 = or(_s1_did_read_T_13, _s1_did_read_T_22)
node _s1_did_read_T_24 = or(_s1_did_read_T_6, _s1_did_read_T_23)
node _s1_did_read_T_25 = eq(io.cpu.req.bits.cmd, UInt<1>(0h1))
node _s1_did_read_T_26 = eq(io.cpu.req.bits.cmd, UInt<5>(0h11))
node _s1_did_read_T_27 = or(_s1_did_read_T_25, _s1_did_read_T_26)
node _s1_did_read_T_28 = eq(io.cpu.req.bits.cmd, UInt<3>(0h7))
node _s1_did_read_T_29 = or(_s1_did_read_T_27, _s1_did_read_T_28)
node _s1_did_read_T_30 = eq(io.cpu.req.bits.cmd, UInt<3>(0h4))
node _s1_did_read_T_31 = eq(io.cpu.req.bits.cmd, UInt<4>(0h9))
node _s1_did_read_T_32 = eq(io.cpu.req.bits.cmd, UInt<4>(0ha))
node _s1_did_read_T_33 = eq(io.cpu.req.bits.cmd, UInt<4>(0hb))
node _s1_did_read_T_34 = or(_s1_did_read_T_30, _s1_did_read_T_31)
node _s1_did_read_T_35 = or(_s1_did_read_T_34, _s1_did_read_T_32)
node _s1_did_read_T_36 = or(_s1_did_read_T_35, _s1_did_read_T_33)
node _s1_did_read_T_37 = eq(io.cpu.req.bits.cmd, UInt<4>(0h8))
node _s1_did_read_T_38 = eq(io.cpu.req.bits.cmd, UInt<4>(0hc))
node _s1_did_read_T_39 = eq(io.cpu.req.bits.cmd, UInt<4>(0hd))
node _s1_did_read_T_40 = eq(io.cpu.req.bits.cmd, UInt<4>(0he))
node _s1_did_read_T_41 = eq(io.cpu.req.bits.cmd, UInt<4>(0hf))
node _s1_did_read_T_42 = or(_s1_did_read_T_37, _s1_did_read_T_38)
node _s1_did_read_T_43 = or(_s1_did_read_T_42, _s1_did_read_T_39)
node _s1_did_read_T_44 = or(_s1_did_read_T_43, _s1_did_read_T_40)
node _s1_did_read_T_45 = or(_s1_did_read_T_44, _s1_did_read_T_41)
node _s1_did_read_T_46 = or(_s1_did_read_T_36, _s1_did_read_T_45)
node _s1_did_read_T_47 = or(_s1_did_read_T_29, _s1_did_read_T_46)
node _s1_did_read_T_48 = eq(io.cpu.req.bits.cmd, UInt<5>(0h11))
node _s1_did_read_T_49 = lt(io.cpu.req.bits.size, UInt<1>(0h0))
node _s1_did_read_T_50 = or(_s1_did_read_T_48, _s1_did_read_T_49)
node _s1_did_read_T_51 = and(_s1_did_read_T_47, _s1_did_read_T_50)
node _s1_did_read_T_52 = or(_s1_did_read_T_24, _s1_did_read_T_51)
node _s1_did_read_T_53 = and(io.cpu.req.valid, _s1_did_read_T_52)
node _s1_did_read_T_54 = and(dataArb.io.in[3].ready, _s1_did_read_T_53)
reg s1_did_read : UInt<1>, clock
when s0_clk_en :
connect s1_did_read, _s1_did_read_T_54
reg s1_read_mask : UInt<1>, clock
when s0_clk_en :
connect s1_read_mask, dataArb.io.in[3].bits.wordMask
connect metaArb.io.in[7].valid, io.cpu.req.valid
connect metaArb.io.in[7].bits.write, UInt<1>(0h0)
node _metaArb_io_in_7_bits_idx_T = bits(dataArb.io.in[3].bits.addr, 13, 6)
connect metaArb.io.in[7].bits.idx, _metaArb_io_in_7_bits_idx_T
connect metaArb.io.in[7].bits.addr, io.cpu.req.bits.addr
connect metaArb.io.in[7].bits.way_en, metaArb.io.in[4].bits.way_en
connect metaArb.io.in[7].bits.data, metaArb.io.in[4].bits.data
node _T_5 = eq(metaArb.io.in[7].ready, UInt<1>(0h0))
when _T_5 :
connect io.cpu.req.ready, UInt<1>(0h0)
node _s1_cmd_uses_tlb_T = or(s1_readwrite, s1_flush_line)
node _s1_cmd_uses_tlb_T_1 = eq(s1_req.cmd, UInt<5>(0h17))
node s1_cmd_uses_tlb = or(_s1_cmd_uses_tlb_T, _s1_cmd_uses_tlb_T_1)
connect tlb.io.ptw.customCSRs, io.ptw.customCSRs
connect tlb.io.ptw.pmp[0], io.ptw.pmp[0]
connect tlb.io.ptw.pmp[1], io.ptw.pmp[1]
connect tlb.io.ptw.pmp[2], io.ptw.pmp[2]
connect tlb.io.ptw.pmp[3], io.ptw.pmp[3]
connect tlb.io.ptw.pmp[4], io.ptw.pmp[4]
connect tlb.io.ptw.pmp[5], io.ptw.pmp[5]
connect tlb.io.ptw.pmp[6], io.ptw.pmp[6]
connect tlb.io.ptw.pmp[7], io.ptw.pmp[7]
connect tlb.io.ptw.gstatus, io.ptw.gstatus
connect tlb.io.ptw.hstatus, io.ptw.hstatus
connect tlb.io.ptw.status, io.ptw.status
connect tlb.io.ptw.vsatp, io.ptw.vsatp
connect tlb.io.ptw.hgatp, io.ptw.hgatp
connect tlb.io.ptw.ptbr, io.ptw.ptbr
connect tlb.io.ptw.resp, io.ptw.resp
connect io.ptw.req.bits, tlb.io.ptw.req.bits
connect io.ptw.req.valid, tlb.io.ptw.req.valid
connect tlb.io.ptw.req.ready, io.ptw.req.ready
node _tlb_io_kill_T = and(s2_tlb_req_valid, io.tlb_port.s2_kill)
node _tlb_io_kill_T_1 = or(io.cpu.s2_kill, _tlb_io_kill_T)
connect tlb.io.kill, _tlb_io_kill_T_1
node _tlb_io_req_valid_T = eq(io.cpu.s1_kill, UInt<1>(0h0))
node _tlb_io_req_valid_T_1 = and(s1_valid, _tlb_io_req_valid_T)
node _tlb_io_req_valid_T_2 = and(_tlb_io_req_valid_T_1, s1_cmd_uses_tlb)
node _tlb_io_req_valid_T_3 = or(s1_tlb_req_valid, _tlb_io_req_valid_T_2)
connect tlb.io.req.valid, _tlb_io_req_valid_T_3
connect tlb.io.req.bits.v, s1_tlb_req.v
connect tlb.io.req.bits.prv, s1_tlb_req.prv
connect tlb.io.req.bits.cmd, s1_tlb_req.cmd
connect tlb.io.req.bits.size, s1_tlb_req.size
connect tlb.io.req.bits.passthrough, s1_tlb_req.passthrough
connect tlb.io.req.bits.vaddr, s1_tlb_req.vaddr
node _T_6 = eq(tlb.io.req.ready, UInt<1>(0h0))
node _T_7 = eq(tlb.io.ptw.resp.valid, UInt<1>(0h0))
node _T_8 = and(_T_6, _T_7)
node _T_9 = eq(io.cpu.req.bits.phys, UInt<1>(0h0))
node _T_10 = and(_T_8, _T_9)
when _T_10 :
connect io.cpu.req.ready, UInt<1>(0h0)
node _T_11 = eq(s1_tlb_req_valid, UInt<1>(0h0))
node _T_12 = and(_T_11, s1_valid)
node _T_13 = and(_T_12, s1_cmd_uses_tlb)
node _T_14 = and(_T_13, tlb.io.resp.miss)
when _T_14 :
connect s1_nack, UInt<1>(0h1)
node _tlb_io_sfence_valid_T = eq(io.cpu.s1_kill, UInt<1>(0h0))
node _tlb_io_sfence_valid_T_1 = and(s1_valid, _tlb_io_sfence_valid_T)
node _tlb_io_sfence_valid_T_2 = and(_tlb_io_sfence_valid_T_1, s1_sfence)
connect tlb.io.sfence.valid, _tlb_io_sfence_valid_T_2
node _tlb_io_sfence_bits_rs1_T = bits(s1_req.size, 0, 0)
connect tlb.io.sfence.bits.rs1, _tlb_io_sfence_bits_rs1_T
node _tlb_io_sfence_bits_rs2_T = bits(s1_req.size, 1, 1)
connect tlb.io.sfence.bits.rs2, _tlb_io_sfence_bits_rs2_T
connect tlb.io.sfence.bits.asid, io.cpu.s1_data.data
connect tlb.io.sfence.bits.addr, s1_req.addr
node _tlb_io_sfence_bits_hv_T = eq(s1_req.cmd, UInt<5>(0h15))
connect tlb.io.sfence.bits.hv, _tlb_io_sfence_bits_hv_T
node _tlb_io_sfence_bits_hg_T = eq(s1_req.cmd, UInt<5>(0h16))
connect tlb.io.sfence.bits.hg, _tlb_io_sfence_bits_hg_T
connect io.tlb_port.req.ready, clock_en_reg
connect io.tlb_port.s1_resp, tlb.io.resp
node _T_15 = and(s1_tlb_req_valid, s1_valid)
node _T_16 = and(s1_req.phys, s1_req.no_xcpt)
node _T_17 = eq(_T_16, UInt<1>(0h0))
node _T_18 = and(_T_15, _T_17)
when _T_18 :
connect s1_nack, UInt<1>(0h1)
invalidate pma_checker.io.kill
invalidate pma_checker.io.ptw.customCSRs.csrs[0].sdata
invalidate pma_checker.io.ptw.customCSRs.csrs[0].set
invalidate pma_checker.io.ptw.customCSRs.csrs[0].stall
invalidate pma_checker.io.ptw.customCSRs.csrs[0].value
invalidate pma_checker.io.ptw.customCSRs.csrs[0].wdata
invalidate pma_checker.io.ptw.customCSRs.csrs[0].wen
invalidate pma_checker.io.ptw.customCSRs.csrs[0].ren
invalidate pma_checker.io.ptw.customCSRs.csrs[1].sdata
invalidate pma_checker.io.ptw.customCSRs.csrs[1].set
invalidate pma_checker.io.ptw.customCSRs.csrs[1].stall
invalidate pma_checker.io.ptw.customCSRs.csrs[1].value
invalidate pma_checker.io.ptw.customCSRs.csrs[1].wdata
invalidate pma_checker.io.ptw.customCSRs.csrs[1].wen
invalidate pma_checker.io.ptw.customCSRs.csrs[1].ren
invalidate pma_checker.io.ptw.customCSRs.csrs[2].sdata
invalidate pma_checker.io.ptw.customCSRs.csrs[2].set
invalidate pma_checker.io.ptw.customCSRs.csrs[2].stall
invalidate pma_checker.io.ptw.customCSRs.csrs[2].value
invalidate pma_checker.io.ptw.customCSRs.csrs[2].wdata
invalidate pma_checker.io.ptw.customCSRs.csrs[2].wen
invalidate pma_checker.io.ptw.customCSRs.csrs[2].ren
invalidate pma_checker.io.ptw.customCSRs.csrs[3].sdata
invalidate pma_checker.io.ptw.customCSRs.csrs[3].set
invalidate pma_checker.io.ptw.customCSRs.csrs[3].stall
invalidate pma_checker.io.ptw.customCSRs.csrs[3].value
invalidate pma_checker.io.ptw.customCSRs.csrs[3].wdata
invalidate pma_checker.io.ptw.customCSRs.csrs[3].wen
invalidate pma_checker.io.ptw.customCSRs.csrs[3].ren
invalidate pma_checker.io.ptw.pmp[0].mask
invalidate pma_checker.io.ptw.pmp[0].addr
invalidate pma_checker.io.ptw.pmp[0].cfg.r
invalidate pma_checker.io.ptw.pmp[0].cfg.w
invalidate pma_checker.io.ptw.pmp[0].cfg.x
invalidate pma_checker.io.ptw.pmp[0].cfg.a
invalidate pma_checker.io.ptw.pmp[0].cfg.res
invalidate pma_checker.io.ptw.pmp[0].cfg.l
invalidate pma_checker.io.ptw.pmp[1].mask
invalidate pma_checker.io.ptw.pmp[1].addr
invalidate pma_checker.io.ptw.pmp[1].cfg.r
invalidate pma_checker.io.ptw.pmp[1].cfg.w
invalidate pma_checker.io.ptw.pmp[1].cfg.x
invalidate pma_checker.io.ptw.pmp[1].cfg.a
invalidate pma_checker.io.ptw.pmp[1].cfg.res
invalidate pma_checker.io.ptw.pmp[1].cfg.l
invalidate pma_checker.io.ptw.pmp[2].mask
invalidate pma_checker.io.ptw.pmp[2].addr
invalidate pma_checker.io.ptw.pmp[2].cfg.r
invalidate pma_checker.io.ptw.pmp[2].cfg.w
invalidate pma_checker.io.ptw.pmp[2].cfg.x
invalidate pma_checker.io.ptw.pmp[2].cfg.a
invalidate pma_checker.io.ptw.pmp[2].cfg.res
invalidate pma_checker.io.ptw.pmp[2].cfg.l
invalidate pma_checker.io.ptw.pmp[3].mask
invalidate pma_checker.io.ptw.pmp[3].addr
invalidate pma_checker.io.ptw.pmp[3].cfg.r
invalidate pma_checker.io.ptw.pmp[3].cfg.w
invalidate pma_checker.io.ptw.pmp[3].cfg.x
invalidate pma_checker.io.ptw.pmp[3].cfg.a
invalidate pma_checker.io.ptw.pmp[3].cfg.res
invalidate pma_checker.io.ptw.pmp[3].cfg.l
invalidate pma_checker.io.ptw.pmp[4].mask
invalidate pma_checker.io.ptw.pmp[4].addr
invalidate pma_checker.io.ptw.pmp[4].cfg.r
invalidate pma_checker.io.ptw.pmp[4].cfg.w
invalidate pma_checker.io.ptw.pmp[4].cfg.x
invalidate pma_checker.io.ptw.pmp[4].cfg.a
invalidate pma_checker.io.ptw.pmp[4].cfg.res
invalidate pma_checker.io.ptw.pmp[4].cfg.l
invalidate pma_checker.io.ptw.pmp[5].mask
invalidate pma_checker.io.ptw.pmp[5].addr
invalidate pma_checker.io.ptw.pmp[5].cfg.r
invalidate pma_checker.io.ptw.pmp[5].cfg.w
invalidate pma_checker.io.ptw.pmp[5].cfg.x
invalidate pma_checker.io.ptw.pmp[5].cfg.a
invalidate pma_checker.io.ptw.pmp[5].cfg.res
invalidate pma_checker.io.ptw.pmp[5].cfg.l
invalidate pma_checker.io.ptw.pmp[6].mask
invalidate pma_checker.io.ptw.pmp[6].addr
invalidate pma_checker.io.ptw.pmp[6].cfg.r
invalidate pma_checker.io.ptw.pmp[6].cfg.w
invalidate pma_checker.io.ptw.pmp[6].cfg.x
invalidate pma_checker.io.ptw.pmp[6].cfg.a
invalidate pma_checker.io.ptw.pmp[6].cfg.res
invalidate pma_checker.io.ptw.pmp[6].cfg.l
invalidate pma_checker.io.ptw.pmp[7].mask
invalidate pma_checker.io.ptw.pmp[7].addr
invalidate pma_checker.io.ptw.pmp[7].cfg.r
invalidate pma_checker.io.ptw.pmp[7].cfg.w
invalidate pma_checker.io.ptw.pmp[7].cfg.x
invalidate pma_checker.io.ptw.pmp[7].cfg.a
invalidate pma_checker.io.ptw.pmp[7].cfg.res
invalidate pma_checker.io.ptw.pmp[7].cfg.l
invalidate pma_checker.io.ptw.gstatus.uie
invalidate pma_checker.io.ptw.gstatus.sie
invalidate pma_checker.io.ptw.gstatus.hie
invalidate pma_checker.io.ptw.gstatus.mie
invalidate pma_checker.io.ptw.gstatus.upie
invalidate pma_checker.io.ptw.gstatus.spie
invalidate pma_checker.io.ptw.gstatus.ube
invalidate pma_checker.io.ptw.gstatus.mpie
invalidate pma_checker.io.ptw.gstatus.spp
invalidate pma_checker.io.ptw.gstatus.vs
invalidate pma_checker.io.ptw.gstatus.mpp
invalidate pma_checker.io.ptw.gstatus.fs
invalidate pma_checker.io.ptw.gstatus.xs
invalidate pma_checker.io.ptw.gstatus.mprv
invalidate pma_checker.io.ptw.gstatus.sum
invalidate pma_checker.io.ptw.gstatus.mxr
invalidate pma_checker.io.ptw.gstatus.tvm
invalidate pma_checker.io.ptw.gstatus.tw
invalidate pma_checker.io.ptw.gstatus.tsr
invalidate pma_checker.io.ptw.gstatus.zero1
invalidate pma_checker.io.ptw.gstatus.sd_rv32
invalidate pma_checker.io.ptw.gstatus.uxl
invalidate pma_checker.io.ptw.gstatus.sxl
invalidate pma_checker.io.ptw.gstatus.sbe
invalidate pma_checker.io.ptw.gstatus.mbe
invalidate pma_checker.io.ptw.gstatus.gva
invalidate pma_checker.io.ptw.gstatus.mpv
invalidate pma_checker.io.ptw.gstatus.zero2
invalidate pma_checker.io.ptw.gstatus.sd
invalidate pma_checker.io.ptw.gstatus.v
invalidate pma_checker.io.ptw.gstatus.prv
invalidate pma_checker.io.ptw.gstatus.dv
invalidate pma_checker.io.ptw.gstatus.dprv
invalidate pma_checker.io.ptw.gstatus.isa
invalidate pma_checker.io.ptw.gstatus.wfi
invalidate pma_checker.io.ptw.gstatus.cease
invalidate pma_checker.io.ptw.gstatus.debug
invalidate pma_checker.io.ptw.hstatus.zero1
invalidate pma_checker.io.ptw.hstatus.vsbe
invalidate pma_checker.io.ptw.hstatus.gva
invalidate pma_checker.io.ptw.hstatus.spv
invalidate pma_checker.io.ptw.hstatus.spvp
invalidate pma_checker.io.ptw.hstatus.hu
invalidate pma_checker.io.ptw.hstatus.zero2
invalidate pma_checker.io.ptw.hstatus.vgein
invalidate pma_checker.io.ptw.hstatus.zero3
invalidate pma_checker.io.ptw.hstatus.vtvm
invalidate pma_checker.io.ptw.hstatus.vtw
invalidate pma_checker.io.ptw.hstatus.vtsr
invalidate pma_checker.io.ptw.hstatus.zero5
invalidate pma_checker.io.ptw.hstatus.vsxl
invalidate pma_checker.io.ptw.hstatus.zero6
invalidate pma_checker.io.ptw.status.uie
invalidate pma_checker.io.ptw.status.sie
invalidate pma_checker.io.ptw.status.hie
invalidate pma_checker.io.ptw.status.mie
invalidate pma_checker.io.ptw.status.upie
invalidate pma_checker.io.ptw.status.spie
invalidate pma_checker.io.ptw.status.ube
invalidate pma_checker.io.ptw.status.mpie
invalidate pma_checker.io.ptw.status.spp
invalidate pma_checker.io.ptw.status.vs
invalidate pma_checker.io.ptw.status.mpp
invalidate pma_checker.io.ptw.status.fs
invalidate pma_checker.io.ptw.status.xs
invalidate pma_checker.io.ptw.status.mprv
invalidate pma_checker.io.ptw.status.sum
invalidate pma_checker.io.ptw.status.mxr
invalidate pma_checker.io.ptw.status.tvm
invalidate pma_checker.io.ptw.status.tw
invalidate pma_checker.io.ptw.status.tsr
invalidate pma_checker.io.ptw.status.zero1
invalidate pma_checker.io.ptw.status.sd_rv32
invalidate pma_checker.io.ptw.status.uxl
invalidate pma_checker.io.ptw.status.sxl
invalidate pma_checker.io.ptw.status.sbe
invalidate pma_checker.io.ptw.status.mbe
invalidate pma_checker.io.ptw.status.gva
invalidate pma_checker.io.ptw.status.mpv
invalidate pma_checker.io.ptw.status.zero2
invalidate pma_checker.io.ptw.status.sd
invalidate pma_checker.io.ptw.status.v
invalidate pma_checker.io.ptw.status.prv
invalidate pma_checker.io.ptw.status.dv
invalidate pma_checker.io.ptw.status.dprv
invalidate pma_checker.io.ptw.status.isa
invalidate pma_checker.io.ptw.status.wfi
invalidate pma_checker.io.ptw.status.cease
invalidate pma_checker.io.ptw.status.debug
invalidate pma_checker.io.ptw.vsatp.ppn
invalidate pma_checker.io.ptw.vsatp.asid
invalidate pma_checker.io.ptw.vsatp.mode
invalidate pma_checker.io.ptw.hgatp.ppn
invalidate pma_checker.io.ptw.hgatp.asid
invalidate pma_checker.io.ptw.hgatp.mode
invalidate pma_checker.io.ptw.ptbr.ppn
invalidate pma_checker.io.ptw.ptbr.asid
invalidate pma_checker.io.ptw.ptbr.mode
invalidate pma_checker.io.ptw.resp.bits.gpa_is_pte
invalidate pma_checker.io.ptw.resp.bits.gpa.bits
invalidate pma_checker.io.ptw.resp.bits.gpa.valid
invalidate pma_checker.io.ptw.resp.bits.homogeneous
invalidate pma_checker.io.ptw.resp.bits.fragmented_superpage
invalidate pma_checker.io.ptw.resp.bits.level
invalidate pma_checker.io.ptw.resp.bits.pte.v
invalidate pma_checker.io.ptw.resp.bits.pte.r
invalidate pma_checker.io.ptw.resp.bits.pte.w
invalidate pma_checker.io.ptw.resp.bits.pte.x
invalidate pma_checker.io.ptw.resp.bits.pte.u
invalidate pma_checker.io.ptw.resp.bits.pte.g
invalidate pma_checker.io.ptw.resp.bits.pte.a
invalidate pma_checker.io.ptw.resp.bits.pte.d
invalidate pma_checker.io.ptw.resp.bits.pte.reserved_for_software
invalidate pma_checker.io.ptw.resp.bits.pte.ppn
invalidate pma_checker.io.ptw.resp.bits.pte.reserved_for_future
invalidate pma_checker.io.ptw.resp.bits.hx
invalidate pma_checker.io.ptw.resp.bits.hw
invalidate pma_checker.io.ptw.resp.bits.hr
invalidate pma_checker.io.ptw.resp.bits.gf
invalidate pma_checker.io.ptw.resp.bits.pf
invalidate pma_checker.io.ptw.resp.bits.ae_final
invalidate pma_checker.io.ptw.resp.bits.ae_ptw
invalidate pma_checker.io.ptw.resp.valid
invalidate pma_checker.io.ptw.req.bits.bits.stage2
invalidate pma_checker.io.ptw.req.bits.bits.vstage1
invalidate pma_checker.io.ptw.req.bits.bits.need_gpa
invalidate pma_checker.io.ptw.req.bits.bits.addr
invalidate pma_checker.io.ptw.req.bits.valid
invalidate pma_checker.io.ptw.req.valid
invalidate pma_checker.io.ptw.req.ready
invalidate pma_checker.io.sfence.bits.hg
invalidate pma_checker.io.sfence.bits.hv
invalidate pma_checker.io.sfence.bits.asid
invalidate pma_checker.io.sfence.bits.addr
invalidate pma_checker.io.sfence.bits.rs2
invalidate pma_checker.io.sfence.bits.rs1
invalidate pma_checker.io.sfence.valid
invalidate pma_checker.io.resp.cmd
invalidate pma_checker.io.resp.size
invalidate pma_checker.io.resp.prefetchable
invalidate pma_checker.io.resp.must_alloc
invalidate pma_checker.io.resp.cacheable
invalidate pma_checker.io.resp.ma.inst
invalidate pma_checker.io.resp.ma.st
invalidate pma_checker.io.resp.ma.ld
invalidate pma_checker.io.resp.ae.inst
invalidate pma_checker.io.resp.ae.st
invalidate pma_checker.io.resp.ae.ld
invalidate pma_checker.io.resp.gf.inst
invalidate pma_checker.io.resp.gf.st
invalidate pma_checker.io.resp.gf.ld
invalidate pma_checker.io.resp.pf.inst
invalidate pma_checker.io.resp.pf.st
invalidate pma_checker.io.resp.pf.ld
invalidate pma_checker.io.resp.gpa_is_pte
invalidate pma_checker.io.resp.gpa
invalidate pma_checker.io.resp.paddr
invalidate pma_checker.io.resp.miss
invalidate pma_checker.io.req.bits.v
invalidate pma_checker.io.req.bits.prv
invalidate pma_checker.io.req.bits.cmd
invalidate pma_checker.io.req.bits.size
invalidate pma_checker.io.req.bits.passthrough
invalidate pma_checker.io.req.bits.vaddr
invalidate pma_checker.io.req.valid
invalidate pma_checker.io.req.ready
connect pma_checker.io.req.bits.passthrough, UInt<1>(0h1)
connect pma_checker.io.req.bits.vaddr, s1_req.addr
connect pma_checker.io.req.bits.size, s1_req.size
connect pma_checker.io.req.bits.cmd, s1_req.cmd
connect pma_checker.io.req.bits.prv, s1_req.dprv
connect pma_checker.io.req.bits.v, s1_req.dv
node _s1_paddr_T = bits(s1_req.addr, 31, 12)
node _s1_paddr_T_1 = shr(tlb.io.resp.paddr, 12)
node _s1_paddr_T_2 = mux(s1_tlb_req_valid, _s1_paddr_T, _s1_paddr_T_1)
node _s1_paddr_T_3 = bits(s1_req.addr, 11, 0)
node s1_paddr = cat(_s1_paddr_T_2, _s1_paddr_T_3)
wire s1_victim_way : UInt
node _baseAddr_T = eq(UInt<1>(0h0), hartIdSinkNodeOptIn)
node baseAddr = or(UInt<32>(0h80000000), mmioAddressPrefixSinkNodeOptIn)
node _inScratchpad_T = geq(s1_paddr, baseAddr)
node _inScratchpad_T_1 = add(baseAddr, UInt<15>(0h4000))
node _inScratchpad_T_2 = tail(_inScratchpad_T_1, 1)
node _inScratchpad_T_3 = lt(s1_paddr, _inScratchpad_T_2)
node s1_hit_way = and(_inScratchpad_T, _inScratchpad_T_3)
wire hitState_meta : { state : UInt<2>}
connect hitState_meta.state, UInt<2>(0h3)
wire hitState_meta_1 : { state : UInt<2>}
connect hitState_meta_1.state, UInt<2>(0h0)
node s1_hit_state = mux(s1_hit_way, hitState_meta, hitState_meta_1)
wire dummyMeta_meta : { state : UInt<2>}
connect dummyMeta_meta.state, UInt<2>(0h0)
wire dummyMeta : { coh : { state : UInt<2>}, tag : UInt<18>}
connect dummyMeta.tag, UInt<1>(0h0)
connect dummyMeta.coh, dummyMeta_meta
node s1_meta_0 = cat(dummyMeta.coh.state, dummyMeta.tag)
wire s1_data_way : UInt
connect s1_data_way, UInt<1>(0h1)
node _tl_d_data_encoded_T = bits(nodeOut.d.bits.data, 7, 0)
node _tl_d_data_encoded_T_1 = bits(nodeOut.d.bits.data, 15, 8)
node _tl_d_data_encoded_T_2 = bits(nodeOut.d.bits.data, 23, 16)
node _tl_d_data_encoded_T_3 = bits(nodeOut.d.bits.data, 31, 24)
node _tl_d_data_encoded_T_4 = bits(nodeOut.d.bits.data, 39, 32)
node _tl_d_data_encoded_T_5 = bits(nodeOut.d.bits.data, 47, 40)
node _tl_d_data_encoded_T_6 = bits(nodeOut.d.bits.data, 55, 48)
node _tl_d_data_encoded_T_7 = bits(nodeOut.d.bits.data, 63, 56)
node tl_d_data_encoded_lo_lo = cat(_tl_d_data_encoded_T_1, _tl_d_data_encoded_T)
node tl_d_data_encoded_lo_hi = cat(_tl_d_data_encoded_T_3, _tl_d_data_encoded_T_2)
node tl_d_data_encoded_lo = cat(tl_d_data_encoded_lo_hi, tl_d_data_encoded_lo_lo)
node tl_d_data_encoded_hi_lo = cat(_tl_d_data_encoded_T_5, _tl_d_data_encoded_T_4)
node tl_d_data_encoded_hi_hi = cat(_tl_d_data_encoded_T_7, _tl_d_data_encoded_T_6)
node tl_d_data_encoded_hi = cat(tl_d_data_encoded_hi_hi, tl_d_data_encoded_hi_lo)
node _tl_d_data_encoded_T_8 = cat(tl_d_data_encoded_hi, tl_d_data_encoded_lo)
wire tl_d_data_encoded : UInt<64>
wire s1_all_data_ways : UInt<64>[2]
connect s1_all_data_ways[0], data.io.resp[0]
connect s1_all_data_ways[1], tl_d_data_encoded
wire s1_mask_xwr_size : UInt<2>
connect s1_mask_xwr_size, s1_req.size
node _s1_mask_xwr_upper_T = bits(s1_req.addr, 0, 0)
node _s1_mask_xwr_upper_T_1 = mux(_s1_mask_xwr_upper_T, UInt<1>(0h1), UInt<1>(0h0))
node _s1_mask_xwr_upper_T_2 = geq(s1_mask_xwr_size, UInt<1>(0h1))
node _s1_mask_xwr_upper_T_3 = mux(_s1_mask_xwr_upper_T_2, UInt<1>(0h1), UInt<1>(0h0))
node s1_mask_xwr_upper = or(_s1_mask_xwr_upper_T_1, _s1_mask_xwr_upper_T_3)
node _s1_mask_xwr_lower_T = bits(s1_req.addr, 0, 0)
node s1_mask_xwr_lower = mux(_s1_mask_xwr_lower_T, UInt<1>(0h0), UInt<1>(0h1))
node _s1_mask_xwr_T = cat(s1_mask_xwr_upper, s1_mask_xwr_lower)
node _s1_mask_xwr_upper_T_4 = bits(s1_req.addr, 1, 1)
node _s1_mask_xwr_upper_T_5 = mux(_s1_mask_xwr_upper_T_4, _s1_mask_xwr_T, UInt<1>(0h0))
node _s1_mask_xwr_upper_T_6 = geq(s1_mask_xwr_size, UInt<2>(0h2))
node _s1_mask_xwr_upper_T_7 = mux(_s1_mask_xwr_upper_T_6, UInt<2>(0h3), UInt<1>(0h0))
node s1_mask_xwr_upper_1 = or(_s1_mask_xwr_upper_T_5, _s1_mask_xwr_upper_T_7)
node _s1_mask_xwr_lower_T_1 = bits(s1_req.addr, 1, 1)
node s1_mask_xwr_lower_1 = mux(_s1_mask_xwr_lower_T_1, UInt<1>(0h0), _s1_mask_xwr_T)
node _s1_mask_xwr_T_1 = cat(s1_mask_xwr_upper_1, s1_mask_xwr_lower_1)
node _s1_mask_xwr_upper_T_8 = bits(s1_req.addr, 2, 2)
node _s1_mask_xwr_upper_T_9 = mux(_s1_mask_xwr_upper_T_8, _s1_mask_xwr_T_1, UInt<1>(0h0))
node _s1_mask_xwr_upper_T_10 = geq(s1_mask_xwr_size, UInt<2>(0h3))
node _s1_mask_xwr_upper_T_11 = mux(_s1_mask_xwr_upper_T_10, UInt<4>(0hf), UInt<1>(0h0))
node s1_mask_xwr_upper_2 = or(_s1_mask_xwr_upper_T_9, _s1_mask_xwr_upper_T_11)
node _s1_mask_xwr_lower_T_2 = bits(s1_req.addr, 2, 2)
node s1_mask_xwr_lower_2 = mux(_s1_mask_xwr_lower_T_2, UInt<1>(0h0), _s1_mask_xwr_T_1)
node s1_mask_xwr = cat(s1_mask_xwr_upper_2, s1_mask_xwr_lower_2)
node _s1_mask_T = eq(s1_req.cmd, UInt<5>(0h11))
node s1_mask = mux(_s1_mask_T, io.cpu.s1_data.mask, s1_mask_xwr)
node _T_19 = eq(s1_req.cmd, UInt<5>(0h11))
node _T_20 = and(s1_valid_masked, _T_19)
node _T_21 = eq(_T_20, UInt<1>(0h0))
node _T_22 = not(io.cpu.s1_data.mask)
node _T_23 = or(s1_mask_xwr, _T_22)
node _T_24 = andr(_T_23)
node _T_25 = or(_T_21, _T_24)
node _T_26 = asUInt(reset)
node _T_27 = eq(_T_26, UInt<1>(0h0))
when _T_27 :
node _T_28 = eq(_T_25, UInt<1>(0h0))
when _T_28 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at DCache.scala:329 assert(!(s1_valid_masked && s1_req.cmd === M_PWR) || (s1_mask_xwr | ~io.cpu.s1_data.mask).andR)\n") : printf
assert(clock, _T_25, UInt<1>(0h1), "") : assert
node _s2_valid_T = eq(s1_sfence, UInt<1>(0h0))
node _s2_valid_T_1 = and(s1_valid_masked, _s2_valid_T)
regreset s2_valid : UInt<1>, clock, reset, UInt<1>(0h0)
connect s2_valid, _s2_valid_T_1
node _s2_valid_no_xcpt_T = cat(io.cpu.s2_xcpt.ae.ld, io.cpu.s2_xcpt.ae.st)
node _s2_valid_no_xcpt_T_1 = cat(io.cpu.s2_xcpt.gf.ld, io.cpu.s2_xcpt.gf.st)
node _s2_valid_no_xcpt_T_2 = cat(io.cpu.s2_xcpt.pf.ld, io.cpu.s2_xcpt.pf.st)
node _s2_valid_no_xcpt_T_3 = cat(io.cpu.s2_xcpt.ma.ld, io.cpu.s2_xcpt.ma.st)
node s2_valid_no_xcpt_lo = cat(_s2_valid_no_xcpt_T_1, _s2_valid_no_xcpt_T)
node s2_valid_no_xcpt_hi = cat(_s2_valid_no_xcpt_T_3, _s2_valid_no_xcpt_T_2)
node _s2_valid_no_xcpt_T_4 = cat(s2_valid_no_xcpt_hi, s2_valid_no_xcpt_lo)
node _s2_valid_no_xcpt_T_5 = orr(_s2_valid_no_xcpt_T_4)
node _s2_valid_no_xcpt_T_6 = eq(_s2_valid_no_xcpt_T_5, UInt<1>(0h0))
node s2_valid_no_xcpt = and(s2_valid, _s2_valid_no_xcpt_T_6)
regreset s2_probe : UInt<1>, clock, reset, UInt<1>(0h0)
connect s2_probe, s1_probe
node _releaseInFlight_T = or(s1_probe, s2_probe)
node _releaseInFlight_T_1 = neq(release_state, UInt<4>(0h0))
node releaseInFlight = or(_releaseInFlight_T, _releaseInFlight_T_1)
node _s2_not_nacked_in_s1_T = eq(s1_nack, UInt<1>(0h0))
reg s2_not_nacked_in_s1 : UInt<1>, clock
connect s2_not_nacked_in_s1, _s2_not_nacked_in_s1_T
node s2_valid_not_nacked_in_s1 = and(s2_valid, s2_not_nacked_in_s1)
node s2_valid_masked = and(s2_valid_no_xcpt, s2_not_nacked_in_s1)
node _s2_valid_not_killed_T = eq(io.cpu.s2_kill, UInt<1>(0h0))
node s2_valid_not_killed = and(s2_valid_masked, _s2_valid_not_killed_T)
reg s2_req : { addr : UInt<34>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}, clock
node _s2_cmd_flush_all_T = eq(s2_req.cmd, UInt<3>(0h5))
node _s2_cmd_flush_all_T_1 = bits(s2_req.size, 0, 0)
node _s2_cmd_flush_all_T_2 = eq(_s2_cmd_flush_all_T_1, UInt<1>(0h0))
node s2_cmd_flush_all = and(_s2_cmd_flush_all_T, _s2_cmd_flush_all_T_2)
node _s2_cmd_flush_line_T = eq(s2_req.cmd, UInt<3>(0h5))
node _s2_cmd_flush_line_T_1 = bits(s2_req.size, 0, 0)
node s2_cmd_flush_line = and(_s2_cmd_flush_line_T, _s2_cmd_flush_line_T_1)
reg s2_tlb_xcpt : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<34>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, clock
reg s2_pma : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<34>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, clock
reg s2_uncached_resp_addr : UInt<34>, clock
node _T_29 = or(s1_valid_not_nacked, s1_flush_valid)
when _T_29 :
connect s2_req, s1_req
connect s2_req.addr, s1_paddr
connect s2_tlb_xcpt, tlb.io.resp
node _s2_pma_T = mux(s1_tlb_req_valid, pma_checker.io.resp, tlb.io.resp)
connect s2_pma, _s2_pma_T
node _s2_vaddr_T = or(s1_valid_not_nacked, s1_flush_valid)
reg s2_vaddr_r : UInt<34>, clock
when _s2_vaddr_T :
connect s2_vaddr_r, s1_vaddr
node _s2_vaddr_T_1 = shr(s2_vaddr_r, 14)
node _s2_vaddr_T_2 = bits(s2_req.addr, 13, 0)
node s2_vaddr = cat(_s2_vaddr_T_1, _s2_vaddr_T_2)
node _s2_read_T = eq(s2_req.cmd, UInt<1>(0h0))
node _s2_read_T_1 = eq(s2_req.cmd, UInt<5>(0h10))
node _s2_read_T_2 = eq(s2_req.cmd, UInt<3>(0h6))
node _s2_read_T_3 = eq(s2_req.cmd, UInt<3>(0h7))
node _s2_read_T_4 = or(_s2_read_T, _s2_read_T_1)
node _s2_read_T_5 = or(_s2_read_T_4, _s2_read_T_2)
node _s2_read_T_6 = or(_s2_read_T_5, _s2_read_T_3)
node _s2_read_T_7 = eq(s2_req.cmd, UInt<3>(0h4))
node _s2_read_T_8 = eq(s2_req.cmd, UInt<4>(0h9))
node _s2_read_T_9 = eq(s2_req.cmd, UInt<4>(0ha))
node _s2_read_T_10 = eq(s2_req.cmd, UInt<4>(0hb))
node _s2_read_T_11 = or(_s2_read_T_7, _s2_read_T_8)
node _s2_read_T_12 = or(_s2_read_T_11, _s2_read_T_9)
node _s2_read_T_13 = or(_s2_read_T_12, _s2_read_T_10)
node _s2_read_T_14 = eq(s2_req.cmd, UInt<4>(0h8))
node _s2_read_T_15 = eq(s2_req.cmd, UInt<4>(0hc))
node _s2_read_T_16 = eq(s2_req.cmd, UInt<4>(0hd))
node _s2_read_T_17 = eq(s2_req.cmd, UInt<4>(0he))
node _s2_read_T_18 = eq(s2_req.cmd, UInt<4>(0hf))
node _s2_read_T_19 = or(_s2_read_T_14, _s2_read_T_15)
node _s2_read_T_20 = or(_s2_read_T_19, _s2_read_T_16)
node _s2_read_T_21 = or(_s2_read_T_20, _s2_read_T_17)
node _s2_read_T_22 = or(_s2_read_T_21, _s2_read_T_18)
node _s2_read_T_23 = or(_s2_read_T_13, _s2_read_T_22)
node s2_read = or(_s2_read_T_6, _s2_read_T_23)
node _s2_write_T = eq(s2_req.cmd, UInt<1>(0h1))
node _s2_write_T_1 = eq(s2_req.cmd, UInt<5>(0h11))
node _s2_write_T_2 = or(_s2_write_T, _s2_write_T_1)
node _s2_write_T_3 = eq(s2_req.cmd, UInt<3>(0h7))
node _s2_write_T_4 = or(_s2_write_T_2, _s2_write_T_3)
node _s2_write_T_5 = eq(s2_req.cmd, UInt<3>(0h4))
node _s2_write_T_6 = eq(s2_req.cmd, UInt<4>(0h9))
node _s2_write_T_7 = eq(s2_req.cmd, UInt<4>(0ha))
node _s2_write_T_8 = eq(s2_req.cmd, UInt<4>(0hb))
node _s2_write_T_9 = or(_s2_write_T_5, _s2_write_T_6)
node _s2_write_T_10 = or(_s2_write_T_9, _s2_write_T_7)
node _s2_write_T_11 = or(_s2_write_T_10, _s2_write_T_8)
node _s2_write_T_12 = eq(s2_req.cmd, UInt<4>(0h8))
node _s2_write_T_13 = eq(s2_req.cmd, UInt<4>(0hc))
node _s2_write_T_14 = eq(s2_req.cmd, UInt<4>(0hd))
node _s2_write_T_15 = eq(s2_req.cmd, UInt<4>(0he))
node _s2_write_T_16 = eq(s2_req.cmd, UInt<4>(0hf))
node _s2_write_T_17 = or(_s2_write_T_12, _s2_write_T_13)
node _s2_write_T_18 = or(_s2_write_T_17, _s2_write_T_14)
node _s2_write_T_19 = or(_s2_write_T_18, _s2_write_T_15)
node _s2_write_T_20 = or(_s2_write_T_19, _s2_write_T_16)
node _s2_write_T_21 = or(_s2_write_T_11, _s2_write_T_20)
node s2_write = or(_s2_write_T_4, _s2_write_T_21)
node s2_readwrite = or(s2_read, s2_write)
reg s2_flush_valid_pre_tag_ecc : UInt<1>, clock
connect s2_flush_valid_pre_tag_ecc, s1_flush_valid
node _s1_meta_clk_en_T = or(s1_valid_not_nacked, s1_flush_valid)
node s1_meta_clk_en = or(_s1_meta_clk_en_T, s1_probe)
reg s2_meta_correctable_errors : UInt<1>, clock
when s1_meta_clk_en :
connect s2_meta_correctable_errors, UInt<1>(0h0)
reg s2_meta_uncorrectable_errors : UInt<1>, clock
when s1_meta_clk_en :
connect s2_meta_uncorrectable_errors, UInt<1>(0h0)
node s2_meta_error_uncorrectable = orr(s2_meta_uncorrectable_errors)
reg s2_meta_corrected_r : UInt<20>, clock
when s1_meta_clk_en :
connect s2_meta_corrected_r, s1_meta_0
wire s2_meta_corrected_0 : { coh : { state : UInt<2>}, tag : UInt<18>}
wire _s2_meta_corrected_WIRE : UInt<20>
connect _s2_meta_corrected_WIRE, s2_meta_corrected_r
node _s2_meta_corrected_T = bits(_s2_meta_corrected_WIRE, 17, 0)
connect s2_meta_corrected_0.tag, _s2_meta_corrected_T
node _s2_meta_corrected_T_1 = bits(_s2_meta_corrected_WIRE, 19, 18)
connect s2_meta_corrected_0.coh.state, _s2_meta_corrected_T_1
node _s2_meta_error_T = or(s2_meta_uncorrectable_errors, s2_meta_correctable_errors)
node s2_meta_error = orr(_s2_meta_error_T)
node _s2_flush_valid_T = eq(s2_meta_error, UInt<1>(0h0))
node s2_flush_valid = and(s2_flush_valid_pre_tag_ecc, _s2_flush_valid_T)
node _s2_data_en_T = or(s1_valid, inWriteback)
node s2_data_en = or(_s2_data_en_T, io.cpu.replay_next)
node _s2_data_word_en_T = mux(s1_did_read, s1_read_mask, UInt<1>(0h0))
node s2_data_word_en = mux(inWriteback, UInt<1>(0h1), _s2_data_word_en_T)
node s2_data_s1_way_words_0_0 = bits(s1_all_data_ways[0], 63, 0)
node s2_data_s1_way_words_1_0 = bits(s1_all_data_ways[1], 63, 0)
node _s2_data_s1_word_en_T = eq(io.cpu.replay_next, UInt<1>(0h0))
node s2_data_s1_word_en = mux(_s2_data_s1_word_en_T, s2_data_word_en, UInt<1>(0h1))
node _s2_data_T = bits(s2_data_s1_word_en, 0, 0)
node _s2_data_T_1 = mux(_s2_data_T, s1_data_way, UInt<1>(0h0))
node _s2_data_T_2 = bits(_s2_data_T_1, 0, 0)
node _s2_data_T_3 = bits(_s2_data_T_1, 1, 1)
node _s2_data_T_4 = mux(_s2_data_T_2, s2_data_s1_way_words_0_0, UInt<1>(0h0))
node _s2_data_T_5 = mux(_s2_data_T_3, s2_data_s1_way_words_1_0, UInt<1>(0h0))
node _s2_data_T_6 = or(_s2_data_T_4, _s2_data_T_5)
wire _s2_data_WIRE : UInt<64>
connect _s2_data_WIRE, _s2_data_T_6
reg s2_data : UInt<64>, clock
when s2_data_en :
connect s2_data, _s2_data_WIRE
reg s2_probe_way : UInt<1>, clock
when s1_probe :
connect s2_probe_way, s1_hit_way
reg s2_probe_state : { state : UInt<2>}, clock
when s1_probe :
connect s2_probe_state, s1_hit_state
reg s2_hit_way : UInt<1>, clock
when s1_valid_not_nacked :
connect s2_hit_way, s1_hit_way
node _s2_hit_state_T = or(s1_valid_not_nacked, s1_flush_valid)
reg s2_hit_state : { state : UInt<2>}, clock
when _s2_hit_state_T :
connect s2_hit_state, s1_hit_state
reg s2_waw_hazard : UInt<1>, clock
when s1_valid_not_nacked :
connect s2_waw_hazard, s1_waw_hazard
wire s2_store_merge : UInt<1>
node s2_hit_valid = gt(s2_hit_state.state, UInt<2>(0h0))
node _r_c_cat_T = eq(s2_req.cmd, UInt<1>(0h1))
node _r_c_cat_T_1 = eq(s2_req.cmd, UInt<5>(0h11))
node _r_c_cat_T_2 = or(_r_c_cat_T, _r_c_cat_T_1)
node _r_c_cat_T_3 = eq(s2_req.cmd, UInt<3>(0h7))
node _r_c_cat_T_4 = or(_r_c_cat_T_2, _r_c_cat_T_3)
node _r_c_cat_T_5 = eq(s2_req.cmd, UInt<3>(0h4))
node _r_c_cat_T_6 = eq(s2_req.cmd, UInt<4>(0h9))
node _r_c_cat_T_7 = eq(s2_req.cmd, UInt<4>(0ha))
node _r_c_cat_T_8 = eq(s2_req.cmd, UInt<4>(0hb))
node _r_c_cat_T_9 = or(_r_c_cat_T_5, _r_c_cat_T_6)
node _r_c_cat_T_10 = or(_r_c_cat_T_9, _r_c_cat_T_7)
node _r_c_cat_T_11 = or(_r_c_cat_T_10, _r_c_cat_T_8)
node _r_c_cat_T_12 = eq(s2_req.cmd, UInt<4>(0h8))
node _r_c_cat_T_13 = eq(s2_req.cmd, UInt<4>(0hc))
node _r_c_cat_T_14 = eq(s2_req.cmd, UInt<4>(0hd))
node _r_c_cat_T_15 = eq(s2_req.cmd, UInt<4>(0he))
node _r_c_cat_T_16 = eq(s2_req.cmd, UInt<4>(0hf))
node _r_c_cat_T_17 = or(_r_c_cat_T_12, _r_c_cat_T_13)
node _r_c_cat_T_18 = or(_r_c_cat_T_17, _r_c_cat_T_14)
node _r_c_cat_T_19 = or(_r_c_cat_T_18, _r_c_cat_T_15)
node _r_c_cat_T_20 = or(_r_c_cat_T_19, _r_c_cat_T_16)
node _r_c_cat_T_21 = or(_r_c_cat_T_11, _r_c_cat_T_20)
node _r_c_cat_T_22 = or(_r_c_cat_T_4, _r_c_cat_T_21)
node _r_c_cat_T_23 = eq(s2_req.cmd, UInt<1>(0h1))
node _r_c_cat_T_24 = eq(s2_req.cmd, UInt<5>(0h11))
node _r_c_cat_T_25 = or(_r_c_cat_T_23, _r_c_cat_T_24)
node _r_c_cat_T_26 = eq(s2_req.cmd, UInt<3>(0h7))
node _r_c_cat_T_27 = or(_r_c_cat_T_25, _r_c_cat_T_26)
node _r_c_cat_T_28 = eq(s2_req.cmd, UInt<3>(0h4))
node _r_c_cat_T_29 = eq(s2_req.cmd, UInt<4>(0h9))
node _r_c_cat_T_30 = eq(s2_req.cmd, UInt<4>(0ha))
node _r_c_cat_T_31 = eq(s2_req.cmd, UInt<4>(0hb))
node _r_c_cat_T_32 = or(_r_c_cat_T_28, _r_c_cat_T_29)
node _r_c_cat_T_33 = or(_r_c_cat_T_32, _r_c_cat_T_30)
node _r_c_cat_T_34 = or(_r_c_cat_T_33, _r_c_cat_T_31)
node _r_c_cat_T_35 = eq(s2_req.cmd, UInt<4>(0h8))
node _r_c_cat_T_36 = eq(s2_req.cmd, UInt<4>(0hc))
node _r_c_cat_T_37 = eq(s2_req.cmd, UInt<4>(0hd))
node _r_c_cat_T_38 = eq(s2_req.cmd, UInt<4>(0he))
node _r_c_cat_T_39 = eq(s2_req.cmd, UInt<4>(0hf))
node _r_c_cat_T_40 = or(_r_c_cat_T_35, _r_c_cat_T_36)
node _r_c_cat_T_41 = or(_r_c_cat_T_40, _r_c_cat_T_37)
node _r_c_cat_T_42 = or(_r_c_cat_T_41, _r_c_cat_T_38)
node _r_c_cat_T_43 = or(_r_c_cat_T_42, _r_c_cat_T_39)
node _r_c_cat_T_44 = or(_r_c_cat_T_34, _r_c_cat_T_43)
node _r_c_cat_T_45 = or(_r_c_cat_T_27, _r_c_cat_T_44)
node _r_c_cat_T_46 = eq(s2_req.cmd, UInt<2>(0h3))
node _r_c_cat_T_47 = or(_r_c_cat_T_45, _r_c_cat_T_46)
node _r_c_cat_T_48 = eq(s2_req.cmd, UInt<3>(0h6))
node _r_c_cat_T_49 = or(_r_c_cat_T_47, _r_c_cat_T_48)
node r_c = cat(_r_c_cat_T_22, _r_c_cat_T_49)
node _r_T = cat(r_c, s2_hit_state.state)
node _r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_2 = cat(_r_T_1, UInt<2>(0h3))
node _r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_4 = cat(_r_T_3, UInt<2>(0h2))
node _r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_6 = cat(_r_T_5, UInt<2>(0h1))
node _r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_8 = cat(_r_T_7, UInt<2>(0h3))
node _r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_10 = cat(_r_T_9, UInt<2>(0h2))
node _r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_12 = cat(_r_T_11, UInt<2>(0h3))
node _r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_14 = cat(_r_T_13, UInt<2>(0h2))
node _r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_16 = cat(_r_T_15, UInt<2>(0h0))
node _r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_18 = cat(_r_T_17, UInt<2>(0h1))
node _r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_20 = cat(_r_T_19, UInt<2>(0h0))
node _r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_22 = cat(_r_T_21, UInt<2>(0h1))
node _r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_24 = cat(_r_T_23, UInt<2>(0h0))
node _r_T_25 = eq(_r_T_24, _r_T)
node _r_T_26 = mux(_r_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_27 = mux(_r_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _r_T_28 = eq(_r_T_22, _r_T)
node _r_T_29 = mux(_r_T_28, UInt<1>(0h0), _r_T_26)
node _r_T_30 = mux(_r_T_28, UInt<2>(0h2), _r_T_27)
node _r_T_31 = eq(_r_T_20, _r_T)
node _r_T_32 = mux(_r_T_31, UInt<1>(0h0), _r_T_29)
node _r_T_33 = mux(_r_T_31, UInt<2>(0h1), _r_T_30)
node _r_T_34 = eq(_r_T_18, _r_T)
node _r_T_35 = mux(_r_T_34, UInt<1>(0h0), _r_T_32)
node _r_T_36 = mux(_r_T_34, UInt<2>(0h2), _r_T_33)
node _r_T_37 = eq(_r_T_16, _r_T)
node _r_T_38 = mux(_r_T_37, UInt<1>(0h0), _r_T_35)
node _r_T_39 = mux(_r_T_37, UInt<2>(0h0), _r_T_36)
node _r_T_40 = eq(_r_T_14, _r_T)
node _r_T_41 = mux(_r_T_40, UInt<1>(0h1), _r_T_38)
node _r_T_42 = mux(_r_T_40, UInt<2>(0h3), _r_T_39)
node _r_T_43 = eq(_r_T_12, _r_T)
node _r_T_44 = mux(_r_T_43, UInt<1>(0h1), _r_T_41)
node _r_T_45 = mux(_r_T_43, UInt<2>(0h3), _r_T_42)
node _r_T_46 = eq(_r_T_10, _r_T)
node _r_T_47 = mux(_r_T_46, UInt<1>(0h1), _r_T_44)
node _r_T_48 = mux(_r_T_46, UInt<2>(0h2), _r_T_45)
node _r_T_49 = eq(_r_T_8, _r_T)
node _r_T_50 = mux(_r_T_49, UInt<1>(0h1), _r_T_47)
node _r_T_51 = mux(_r_T_49, UInt<2>(0h3), _r_T_48)
node _r_T_52 = eq(_r_T_6, _r_T)
node _r_T_53 = mux(_r_T_52, UInt<1>(0h1), _r_T_50)
node _r_T_54 = mux(_r_T_52, UInt<2>(0h1), _r_T_51)
node _r_T_55 = eq(_r_T_4, _r_T)
node _r_T_56 = mux(_r_T_55, UInt<1>(0h1), _r_T_53)
node _r_T_57 = mux(_r_T_55, UInt<2>(0h2), _r_T_54)
node _r_T_58 = eq(_r_T_2, _r_T)
node s2_hit = mux(_r_T_58, UInt<1>(0h1), _r_T_56)
node s2_grow_param = mux(_r_T_58, UInt<2>(0h3), _r_T_57)
wire s2_new_hit_state : { state : UInt<2>}
connect s2_new_hit_state.state, s2_grow_param
node _T_30 = bits(s2_data, 7, 0)
node _T_31 = bits(s2_data, 15, 8)
node _T_32 = bits(s2_data, 23, 16)
node _T_33 = bits(s2_data, 31, 24)
node _T_34 = bits(s2_data, 39, 32)
node _T_35 = bits(s2_data, 47, 40)
node _T_36 = bits(s2_data, 55, 48)
node _T_37 = bits(s2_data, 63, 56)
node _s2_data_error_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _s2_data_error_T_1 = or(UInt<1>(0h0), UInt<1>(0h0))
node _s2_data_error_T_2 = or(UInt<1>(0h0), UInt<1>(0h0))
node _s2_data_error_T_3 = or(UInt<1>(0h0), UInt<1>(0h0))
node _s2_data_error_T_4 = or(UInt<1>(0h0), UInt<1>(0h0))
node _s2_data_error_T_5 = or(UInt<1>(0h0), UInt<1>(0h0))
node _s2_data_error_T_6 = or(UInt<1>(0h0), UInt<1>(0h0))
node _s2_data_error_T_7 = or(UInt<1>(0h0), UInt<1>(0h0))
node _s2_data_error_T_8 = or(_s2_data_error_T, _s2_data_error_T_1)
node _s2_data_error_T_9 = or(_s2_data_error_T_8, _s2_data_error_T_2)
node _s2_data_error_T_10 = or(_s2_data_error_T_9, _s2_data_error_T_3)
node _s2_data_error_T_11 = or(_s2_data_error_T_10, _s2_data_error_T_4)
node _s2_data_error_T_12 = or(_s2_data_error_T_11, _s2_data_error_T_5)
node _s2_data_error_T_13 = or(_s2_data_error_T_12, _s2_data_error_T_6)
node s2_data_error = or(_s2_data_error_T_13, _s2_data_error_T_7)
node _s2_data_error_uncorrectable_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _s2_data_error_uncorrectable_T_1 = or(_s2_data_error_uncorrectable_T, UInt<1>(0h0))
node _s2_data_error_uncorrectable_T_2 = or(_s2_data_error_uncorrectable_T_1, UInt<1>(0h0))
node _s2_data_error_uncorrectable_T_3 = or(_s2_data_error_uncorrectable_T_2, UInt<1>(0h0))
node _s2_data_error_uncorrectable_T_4 = or(_s2_data_error_uncorrectable_T_3, UInt<1>(0h0))
node _s2_data_error_uncorrectable_T_5 = or(_s2_data_error_uncorrectable_T_4, UInt<1>(0h0))
node s2_data_error_uncorrectable = or(_s2_data_error_uncorrectable_T_5, UInt<1>(0h0))
node s2_data_corrected_lo_lo = cat(_T_31, _T_30)
node s2_data_corrected_lo_hi = cat(_T_33, _T_32)
node s2_data_corrected_lo = cat(s2_data_corrected_lo_hi, s2_data_corrected_lo_lo)
node s2_data_corrected_hi_lo = cat(_T_35, _T_34)
node s2_data_corrected_hi_hi = cat(_T_37, _T_36)
node s2_data_corrected_hi = cat(s2_data_corrected_hi_hi, s2_data_corrected_hi_lo)
node s2_data_corrected = cat(s2_data_corrected_hi, s2_data_corrected_lo)
node s2_data_uncorrected_lo_lo = cat(_T_31, _T_30)
node s2_data_uncorrected_lo_hi = cat(_T_33, _T_32)
node s2_data_uncorrected_lo = cat(s2_data_uncorrected_lo_hi, s2_data_uncorrected_lo_lo)
node s2_data_uncorrected_hi_lo = cat(_T_35, _T_34)
node s2_data_uncorrected_hi_hi = cat(_T_37, _T_36)
node s2_data_uncorrected_hi = cat(s2_data_uncorrected_hi_hi, s2_data_uncorrected_hi_lo)
node s2_data_uncorrected = cat(s2_data_uncorrected_hi, s2_data_uncorrected_lo)
node _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T = eq(s2_meta_error, UInt<1>(0h0))
node _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T_1 = and(s2_valid_masked, _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T)
node s2_valid_hit_maybe_flush_pre_data_ecc_and_waw = and(_s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T_1, s2_hit)
node _s2_valid_hit_pre_data_ecc_and_waw_T = and(s2_valid_hit_maybe_flush_pre_data_ecc_and_waw, s2_readwrite)
node _s2_valid_hit_pre_data_ecc_and_waw_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0))
node s2_valid_hit_pre_data_ecc_and_waw = and(_s2_valid_hit_pre_data_ecc_and_waw_T, _s2_valid_hit_pre_data_ecc_and_waw_T_1)
node s2_valid_flush_line = and(s2_valid_hit_maybe_flush_pre_data_ecc_and_waw, s2_cmd_flush_line)
node _s2_valid_hit_pre_data_ecc_T = eq(s2_waw_hazard, UInt<1>(0h0))
node _s2_valid_hit_pre_data_ecc_T_1 = or(_s2_valid_hit_pre_data_ecc_T, s2_store_merge)
node s2_valid_hit_pre_data_ecc = and(s2_valid_hit_pre_data_ecc_and_waw, _s2_valid_hit_pre_data_ecc_T_1)
node s2_valid_data_error = and(s2_valid_hit_pre_data_ecc_and_waw, s2_data_error)
node _s2_valid_hit_T = eq(s2_data_error, UInt<1>(0h0))
node s2_valid_hit = and(s2_valid_hit_pre_data_ecc, _s2_valid_hit_T)
node _s2_valid_miss_T = and(s2_valid_masked, s2_readwrite)
node _s2_valid_miss_T_1 = eq(s2_meta_error, UInt<1>(0h0))
node _s2_valid_miss_T_2 = and(_s2_valid_miss_T, _s2_valid_miss_T_1)
node _s2_valid_miss_T_3 = eq(s2_hit, UInt<1>(0h0))
node s2_valid_miss = and(_s2_valid_miss_T_2, _s2_valid_miss_T_3)
node _s2_uncached_T = eq(s2_pma.cacheable, UInt<1>(0h0))
node _s2_uncached_T_1 = eq(s2_pma.must_alloc, UInt<1>(0h0))
node _s2_uncached_T_2 = and(s2_req.no_alloc, _s2_uncached_T_1)
node _s2_uncached_T_3 = eq(s2_hit_valid, UInt<1>(0h0))
node _s2_uncached_T_4 = and(_s2_uncached_T_2, _s2_uncached_T_3)
node s2_uncached = or(_s2_uncached_T, _s2_uncached_T_4)
node _s2_valid_cached_miss_T = eq(s2_uncached, UInt<1>(0h0))
node _s2_valid_cached_miss_T_1 = and(s2_valid_miss, _s2_valid_cached_miss_T)
node _s2_valid_cached_miss_T_2 = orr(uncachedInFlight[0])
node _s2_valid_cached_miss_T_3 = eq(_s2_valid_cached_miss_T_2, UInt<1>(0h0))
node s2_valid_cached_miss = and(_s2_valid_cached_miss_T_1, _s2_valid_cached_miss_T_3)
node _s2_want_victimize_T = or(s2_valid_cached_miss, s2_valid_flush_line)
node _s2_want_victimize_T_1 = or(_s2_want_victimize_T, s2_valid_data_error)
node _s2_want_victimize_T_2 = or(_s2_want_victimize_T_1, s2_flush_valid)
node s2_want_victimize = and(UInt<1>(0h0), _s2_want_victimize_T_2)
node _s2_cannot_victimize_T = eq(s2_flush_valid, UInt<1>(0h0))
node s2_cannot_victimize = and(_s2_cannot_victimize_T, io.cpu.s2_kill)
node _s2_victimize_T = eq(s2_cannot_victimize, UInt<1>(0h0))
node s2_victimize = and(s2_want_victimize, _s2_victimize_T)
node _s2_valid_uncached_pending_T = and(s2_valid_miss, s2_uncached)
node _s2_valid_uncached_pending_T_1 = andr(uncachedInFlight[0])
node _s2_valid_uncached_pending_T_2 = eq(_s2_valid_uncached_pending_T_1, UInt<1>(0h0))
node s2_valid_uncached_pending = and(_s2_valid_uncached_pending_T, _s2_valid_uncached_pending_T_2)
node _s2_victim_way_T = or(s1_valid_not_nacked, s1_flush_valid)
reg s2_victim_way_r : UInt, clock
when _s2_victim_way_T :
connect s2_victim_way_r, s1_victim_way
node s2_victim_way = dshl(UInt<1>(0h1), s2_victim_way_r)
node s2_victim_or_hit_way = mux(s2_hit_valid, s2_hit_way, s2_victim_way)
node _s2_victim_tag_T = or(s2_valid_data_error, s2_valid_flush_line)
node _s2_victim_tag_T_1 = bits(s2_req.addr, 31, 14)
node _s2_victim_tag_T_2 = bits(s2_victim_way, 0, 0)
node s2_victim_tag = mux(_s2_victim_tag_T, _s2_victim_tag_T_1, s2_meta_corrected_0.tag)
node _s2_victim_state_T = bits(s2_victim_way, 0, 0)
node s2_victim_state = mux(s2_hit_valid, s2_hit_state, s2_meta_corrected_0.coh)
node _r_T_59 = cat(probe_bits.param, s2_probe_state.state)
node _r_T_60 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _r_T_61 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _r_T_62 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _r_T_63 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _r_T_64 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _r_T_65 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _r_T_66 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _r_T_67 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _r_T_68 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _r_T_69 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _r_T_70 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _r_T_71 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _r_T_72 = eq(_r_T_71, _r_T_59)
node _r_T_73 = mux(_r_T_72, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_74 = mux(_r_T_72, UInt<3>(0h5), UInt<1>(0h0))
node _r_T_75 = mux(_r_T_72, UInt<2>(0h0), UInt<1>(0h0))
node _r_T_76 = eq(_r_T_70, _r_T_59)
node _r_T_77 = mux(_r_T_76, UInt<1>(0h0), _r_T_73)
node _r_T_78 = mux(_r_T_76, UInt<3>(0h2), _r_T_74)
node _r_T_79 = mux(_r_T_76, UInt<2>(0h0), _r_T_75)
node _r_T_80 = eq(_r_T_69, _r_T_59)
node _r_T_81 = mux(_r_T_80, UInt<1>(0h0), _r_T_77)
node _r_T_82 = mux(_r_T_80, UInt<3>(0h1), _r_T_78)
node _r_T_83 = mux(_r_T_80, UInt<2>(0h0), _r_T_79)
node _r_T_84 = eq(_r_T_68, _r_T_59)
node _r_T_85 = mux(_r_T_84, UInt<1>(0h1), _r_T_81)
node _r_T_86 = mux(_r_T_84, UInt<3>(0h1), _r_T_82)
node _r_T_87 = mux(_r_T_84, UInt<2>(0h0), _r_T_83)
node _r_T_88 = eq(_r_T_67, _r_T_59)
node _r_T_89 = mux(_r_T_88, UInt<1>(0h0), _r_T_85)
node _r_T_90 = mux(_r_T_88, UInt<3>(0h5), _r_T_86)
node _r_T_91 = mux(_r_T_88, UInt<2>(0h0), _r_T_87)
node _r_T_92 = eq(_r_T_66, _r_T_59)
node _r_T_93 = mux(_r_T_92, UInt<1>(0h0), _r_T_89)
node _r_T_94 = mux(_r_T_92, UInt<3>(0h4), _r_T_90)
node _r_T_95 = mux(_r_T_92, UInt<2>(0h1), _r_T_91)
node _r_T_96 = eq(_r_T_65, _r_T_59)
node _r_T_97 = mux(_r_T_96, UInt<1>(0h0), _r_T_93)
node _r_T_98 = mux(_r_T_96, UInt<3>(0h0), _r_T_94)
node _r_T_99 = mux(_r_T_96, UInt<2>(0h1), _r_T_95)
node _r_T_100 = eq(_r_T_64, _r_T_59)
node _r_T_101 = mux(_r_T_100, UInt<1>(0h1), _r_T_97)
node _r_T_102 = mux(_r_T_100, UInt<3>(0h0), _r_T_98)
node _r_T_103 = mux(_r_T_100, UInt<2>(0h1), _r_T_99)
node _r_T_104 = eq(_r_T_63, _r_T_59)
node _r_T_105 = mux(_r_T_104, UInt<1>(0h0), _r_T_101)
node _r_T_106 = mux(_r_T_104, UInt<3>(0h5), _r_T_102)
node _r_T_107 = mux(_r_T_104, UInt<2>(0h0), _r_T_103)
node _r_T_108 = eq(_r_T_62, _r_T_59)
node _r_T_109 = mux(_r_T_108, UInt<1>(0h0), _r_T_105)
node _r_T_110 = mux(_r_T_108, UInt<3>(0h4), _r_T_106)
node _r_T_111 = mux(_r_T_108, UInt<2>(0h1), _r_T_107)
node _r_T_112 = eq(_r_T_61, _r_T_59)
node _r_T_113 = mux(_r_T_112, UInt<1>(0h0), _r_T_109)
node _r_T_114 = mux(_r_T_112, UInt<3>(0h3), _r_T_110)
node _r_T_115 = mux(_r_T_112, UInt<2>(0h2), _r_T_111)
node _r_T_116 = eq(_r_T_60, _r_T_59)
node s2_prb_ack_data = mux(_r_T_116, UInt<1>(0h1), _r_T_113)
node s2_report_param = mux(_r_T_116, UInt<3>(0h3), _r_T_114)
node r_3 = mux(_r_T_116, UInt<2>(0h2), _r_T_115)
wire probeNewCoh : { state : UInt<2>}
connect probeNewCoh.state, r_3
node _r_T_117 = eq(UInt<5>(0h10), UInt<5>(0h10))
node _r_T_118 = mux(_r_T_117, UInt<2>(0h2), UInt<2>(0h2))
node _r_T_119 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _r_T_120 = mux(_r_T_119, UInt<2>(0h1), _r_T_118)
node _r_T_121 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _r_T_122 = mux(_r_T_121, UInt<2>(0h0), _r_T_120)
node _r_T_123 = cat(_r_T_122, s2_victim_state.state)
node _r_T_124 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _r_T_125 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _r_T_126 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _r_T_127 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _r_T_128 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _r_T_129 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _r_T_130 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _r_T_131 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _r_T_132 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _r_T_133 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _r_T_134 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _r_T_135 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _r_T_136 = eq(_r_T_135, _r_T_123)
node _r_T_137 = mux(_r_T_136, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_138 = mux(_r_T_136, UInt<3>(0h5), UInt<1>(0h0))
node _r_T_139 = mux(_r_T_136, UInt<2>(0h0), UInt<1>(0h0))
node _r_T_140 = eq(_r_T_134, _r_T_123)
node _r_T_141 = mux(_r_T_140, UInt<1>(0h0), _r_T_137)
node _r_T_142 = mux(_r_T_140, UInt<3>(0h2), _r_T_138)
node _r_T_143 = mux(_r_T_140, UInt<2>(0h0), _r_T_139)
node _r_T_144 = eq(_r_T_133, _r_T_123)
node _r_T_145 = mux(_r_T_144, UInt<1>(0h0), _r_T_141)
node _r_T_146 = mux(_r_T_144, UInt<3>(0h1), _r_T_142)
node _r_T_147 = mux(_r_T_144, UInt<2>(0h0), _r_T_143)
node _r_T_148 = eq(_r_T_132, _r_T_123)
node _r_T_149 = mux(_r_T_148, UInt<1>(0h1), _r_T_145)
node _r_T_150 = mux(_r_T_148, UInt<3>(0h1), _r_T_146)
node _r_T_151 = mux(_r_T_148, UInt<2>(0h0), _r_T_147)
node _r_T_152 = eq(_r_T_131, _r_T_123)
node _r_T_153 = mux(_r_T_152, UInt<1>(0h0), _r_T_149)
node _r_T_154 = mux(_r_T_152, UInt<3>(0h5), _r_T_150)
node _r_T_155 = mux(_r_T_152, UInt<2>(0h0), _r_T_151)
node _r_T_156 = eq(_r_T_130, _r_T_123)
node _r_T_157 = mux(_r_T_156, UInt<1>(0h0), _r_T_153)
node _r_T_158 = mux(_r_T_156, UInt<3>(0h4), _r_T_154)
node _r_T_159 = mux(_r_T_156, UInt<2>(0h1), _r_T_155)
node _r_T_160 = eq(_r_T_129, _r_T_123)
node _r_T_161 = mux(_r_T_160, UInt<1>(0h0), _r_T_157)
node _r_T_162 = mux(_r_T_160, UInt<3>(0h0), _r_T_158)
node _r_T_163 = mux(_r_T_160, UInt<2>(0h1), _r_T_159)
node _r_T_164 = eq(_r_T_128, _r_T_123)
node _r_T_165 = mux(_r_T_164, UInt<1>(0h1), _r_T_161)
node _r_T_166 = mux(_r_T_164, UInt<3>(0h0), _r_T_162)
node _r_T_167 = mux(_r_T_164, UInt<2>(0h1), _r_T_163)
node _r_T_168 = eq(_r_T_127, _r_T_123)
node _r_T_169 = mux(_r_T_168, UInt<1>(0h0), _r_T_165)
node _r_T_170 = mux(_r_T_168, UInt<3>(0h5), _r_T_166)
node _r_T_171 = mux(_r_T_168, UInt<2>(0h0), _r_T_167)
node _r_T_172 = eq(_r_T_126, _r_T_123)
node _r_T_173 = mux(_r_T_172, UInt<1>(0h0), _r_T_169)
node _r_T_174 = mux(_r_T_172, UInt<3>(0h4), _r_T_170)
node _r_T_175 = mux(_r_T_172, UInt<2>(0h1), _r_T_171)
node _r_T_176 = eq(_r_T_125, _r_T_123)
node _r_T_177 = mux(_r_T_176, UInt<1>(0h0), _r_T_173)
node _r_T_178 = mux(_r_T_176, UInt<3>(0h3), _r_T_174)
node _r_T_179 = mux(_r_T_176, UInt<2>(0h2), _r_T_175)
node _r_T_180 = eq(_r_T_124, _r_T_123)
node s2_victim_dirty = mux(_r_T_180, UInt<1>(0h1), _r_T_177)
node s2_shrink_param = mux(_r_T_180, UInt<3>(0h3), _r_T_178)
node r_3_1 = mux(_r_T_180, UInt<2>(0h2), _r_T_179)
wire voluntaryNewCoh : { state : UInt<2>}
connect voluntaryNewCoh.state, r_3_1
node _s2_update_meta_T = eq(s2_hit_state.state, s2_new_hit_state.state)
node s2_update_meta = eq(_s2_update_meta_T, UInt<1>(0h0))
node s2_dont_nack_uncached = and(s2_valid_uncached_pending, tl_out_a.ready)
node _s2_dont_nack_misc_T = eq(s2_meta_error, UInt<1>(0h0))
node _s2_dont_nack_misc_T_1 = and(s2_valid_masked, _s2_dont_nack_misc_T)
node _s2_dont_nack_misc_T_2 = and(UInt<1>(0h0), s2_cmd_flush_all)
node _s2_dont_nack_misc_T_3 = and(_s2_dont_nack_misc_T_2, flushed)
node _s2_dont_nack_misc_T_4 = eq(flushing, UInt<1>(0h0))
node _s2_dont_nack_misc_T_5 = and(_s2_dont_nack_misc_T_3, _s2_dont_nack_misc_T_4)
node _s2_dont_nack_misc_T_6 = and(UInt<1>(0h0), s2_cmd_flush_line)
node _s2_dont_nack_misc_T_7 = eq(s2_hit, UInt<1>(0h0))
node _s2_dont_nack_misc_T_8 = and(_s2_dont_nack_misc_T_6, _s2_dont_nack_misc_T_7)
node _s2_dont_nack_misc_T_9 = or(_s2_dont_nack_misc_T_5, _s2_dont_nack_misc_T_8)
node _s2_dont_nack_misc_T_10 = eq(s2_req.cmd, UInt<5>(0h17))
node _s2_dont_nack_misc_T_11 = or(_s2_dont_nack_misc_T_9, _s2_dont_nack_misc_T_10)
node s2_dont_nack_misc = and(_s2_dont_nack_misc_T_1, _s2_dont_nack_misc_T_11)
node _io_cpu_s2_nack_T = eq(s2_dont_nack_uncached, UInt<1>(0h0))
node _io_cpu_s2_nack_T_1 = and(s2_valid_no_xcpt, _io_cpu_s2_nack_T)
node _io_cpu_s2_nack_T_2 = eq(s2_dont_nack_misc, UInt<1>(0h0))
node _io_cpu_s2_nack_T_3 = and(_io_cpu_s2_nack_T_1, _io_cpu_s2_nack_T_2)
node _io_cpu_s2_nack_T_4 = eq(s2_valid_hit, UInt<1>(0h0))
node _io_cpu_s2_nack_T_5 = and(_io_cpu_s2_nack_T_3, _io_cpu_s2_nack_T_4)
connect io.cpu.s2_nack, _io_cpu_s2_nack_T_5
node _T_38 = and(s2_valid_hit_pre_data_ecc_and_waw, s2_update_meta)
node _T_39 = or(io.cpu.s2_nack, _T_38)
when _T_39 :
connect s1_nack, UInt<1>(0h1)
node _s2_first_meta_corrected_T = bits(s2_meta_correctable_errors, 0, 0)
node _metaArb_io_in_1_valid_T = or(s2_valid_masked, s2_flush_valid_pre_tag_ecc)
node _metaArb_io_in_1_valid_T_1 = or(_metaArb_io_in_1_valid_T, s2_probe)
node _metaArb_io_in_1_valid_T_2 = and(s2_meta_error, _metaArb_io_in_1_valid_T_1)
connect metaArb.io.in[1].valid, _metaArb_io_in_1_valid_T_2
connect metaArb.io.in[1].bits.write, UInt<1>(0h1)
node _metaArb_io_in_1_bits_way_en_T = bits(s2_meta_correctable_errors, 0, 0)
node _metaArb_io_in_1_bits_way_en_T_1 = mux(_metaArb_io_in_1_bits_way_en_T, UInt<1>(0h1), UInt<1>(0h0))
node _metaArb_io_in_1_bits_way_en_T_2 = mux(s2_meta_error_uncorrectable, UInt<1>(0h0), _metaArb_io_in_1_bits_way_en_T_1)
node _metaArb_io_in_1_bits_way_en_T_3 = or(s2_meta_uncorrectable_errors, _metaArb_io_in_1_bits_way_en_T_2)
connect metaArb.io.in[1].bits.way_en, _metaArb_io_in_1_bits_way_en_T_3
node _metaArb_io_in_1_bits_idx_T = bits(probe_bits.address, 13, 6)
node _metaArb_io_in_1_bits_idx_T_1 = bits(s2_vaddr, 13, 6)
node _metaArb_io_in_1_bits_idx_T_2 = mux(s2_probe, _metaArb_io_in_1_bits_idx_T, _metaArb_io_in_1_bits_idx_T_1)
connect metaArb.io.in[1].bits.idx, _metaArb_io_in_1_bits_idx_T_2
node _metaArb_io_in_1_bits_addr_T = shr(io.cpu.req.bits.addr, 14)
node _metaArb_io_in_1_bits_addr_T_1 = shl(metaArb.io.in[1].bits.idx, 6)
node _metaArb_io_in_1_bits_addr_T_2 = cat(_metaArb_io_in_1_bits_addr_T, _metaArb_io_in_1_bits_addr_T_1)
connect metaArb.io.in[1].bits.addr, _metaArb_io_in_1_bits_addr_T_2
wire metaArb_io_in_1_bits_data_new_meta : { coh : { state : UInt<2>}, tag : UInt<18>}
connect metaArb_io_in_1_bits_data_new_meta, s2_meta_corrected_0
when s2_meta_error_uncorrectable :
wire metaArb_io_in_1_bits_data_new_meta_coh_meta : { state : UInt<2>}
connect metaArb_io_in_1_bits_data_new_meta_coh_meta.state, UInt<2>(0h0)
connect metaArb_io_in_1_bits_data_new_meta.coh, metaArb_io_in_1_bits_data_new_meta_coh_meta
node _metaArb_io_in_1_bits_data_T = cat(metaArb_io_in_1_bits_data_new_meta.coh.state, metaArb_io_in_1_bits_data_new_meta.tag)
connect metaArb.io.in[1].bits.data, _metaArb_io_in_1_bits_data_T
node _metaArb_io_in_2_valid_T = and(s2_valid_hit_pre_data_ecc_and_waw, s2_update_meta)
connect metaArb.io.in[2].valid, _metaArb_io_in_2_valid_T
node _metaArb_io_in_2_bits_write_T = eq(io.cpu.s2_kill, UInt<1>(0h0))
connect metaArb.io.in[2].bits.write, _metaArb_io_in_2_bits_write_T
connect metaArb.io.in[2].bits.way_en, s2_victim_or_hit_way
node _metaArb_io_in_2_bits_idx_T = bits(s2_vaddr, 13, 6)
connect metaArb.io.in[2].bits.idx, _metaArb_io_in_2_bits_idx_T
node _metaArb_io_in_2_bits_addr_T = shr(io.cpu.req.bits.addr, 14)
node _metaArb_io_in_2_bits_addr_T_1 = bits(s2_vaddr, 13, 0)
node _metaArb_io_in_2_bits_addr_T_2 = cat(_metaArb_io_in_2_bits_addr_T, _metaArb_io_in_2_bits_addr_T_1)
connect metaArb.io.in[2].bits.addr, _metaArb_io_in_2_bits_addr_T_2
node _metaArb_io_in_2_bits_data_T = shr(s2_req.addr, 14)
wire metaArb_io_in_2_bits_data_meta : { coh : { state : UInt<2>}, tag : UInt<18>}
connect metaArb_io_in_2_bits_data_meta.tag, _metaArb_io_in_2_bits_data_T
connect metaArb_io_in_2_bits_data_meta.coh, s2_new_hit_state
node _metaArb_io_in_2_bits_data_T_1 = cat(metaArb_io_in_2_bits_data_meta.coh.state, metaArb_io_in_2_bits_data_meta.tag)
connect metaArb.io.in[2].bits.data, _metaArb_io_in_2_bits_data_T_1
node _s2_lr_T = eq(s2_req.cmd, UInt<3>(0h6))
node s2_lr = and(UInt<1>(0h0), _s2_lr_T)
node _s2_sc_T = eq(s2_req.cmd, UInt<3>(0h7))
node s2_sc = and(UInt<1>(0h0), _s2_sc_T)
regreset lrscCount : UInt, clock, reset, UInt<1>(0h0)
node lrscValid = gt(lrscCount, UInt<2>(0h3))
node _lrscBackingOff_T = gt(lrscCount, UInt<1>(0h0))
node _lrscBackingOff_T_1 = eq(lrscValid, UInt<1>(0h0))
node lrscBackingOff = and(_lrscBackingOff_T, _lrscBackingOff_T_1)
reg lrscAddr : UInt, clock
node _lrscAddrMatch_T = shr(s2_req.addr, 6)
node lrscAddrMatch = eq(lrscAddr, _lrscAddrMatch_T)
node _s2_sc_fail_T = and(lrscValid, lrscAddrMatch)
node _s2_sc_fail_T_1 = eq(_s2_sc_fail_T, UInt<1>(0h0))
node s2_sc_fail = and(s2_sc, _s2_sc_fail_T_1)
node _T_40 = and(s2_valid_hit, s2_lr)
node _T_41 = eq(cached_grant_wait, UInt<1>(0h0))
node _T_42 = and(_T_40, _T_41)
node _T_43 = or(_T_42, s2_valid_cached_miss)
node _T_44 = eq(io.cpu.s2_kill, UInt<1>(0h0))
node _T_45 = and(_T_43, _T_44)
when _T_45 :
node _lrscCount_T = mux(s2_hit, UInt<7>(0h4f), UInt<1>(0h0))
connect lrscCount, _lrscCount_T
node _lrscAddr_T = shr(s2_req.addr, 6)
connect lrscAddr, _lrscAddr_T
node _T_46 = gt(lrscCount, UInt<1>(0h0))
when _T_46 :
node _lrscCount_T_1 = sub(lrscCount, UInt<1>(0h1))
node _lrscCount_T_2 = tail(_lrscCount_T_1, 1)
connect lrscCount, _lrscCount_T_2
node _T_47 = and(s2_valid_not_killed, lrscValid)
when _T_47 :
connect lrscCount, UInt<2>(0h3)
when s1_probe :
connect lrscCount, UInt<1>(0h0)
node _s2_correct_T = eq(any_pstore_valid, UInt<1>(0h0))
node _s2_correct_T_1 = and(s2_data_error, _s2_correct_T)
node _s2_correct_T_2 = or(any_pstore_valid, s2_valid)
reg s2_correct_REG : UInt<1>, clock
connect s2_correct_REG, _s2_correct_T_2
node _s2_correct_T_3 = eq(s2_correct_REG, UInt<1>(0h0))
node _s2_correct_T_4 = and(_s2_correct_T_1, _s2_correct_T_3)
node s2_correct = and(_s2_correct_T_4, UInt<1>(0h1))
node _s2_valid_correct_T = and(s2_valid_hit_pre_data_ecc_and_waw, s2_correct)
node _s2_valid_correct_T_1 = eq(io.cpu.s2_kill, UInt<1>(0h0))
node s2_valid_correct = and(_s2_valid_correct_T, _s2_valid_correct_T_1)
node _pstore1_cmd_T = and(s1_valid_not_nacked, s1_write)
reg pstore1_cmd : UInt<5>, clock
when _pstore1_cmd_T :
connect pstore1_cmd, s1_req.cmd
node _pstore1_addr_T = and(s1_valid_not_nacked, s1_write)
reg pstore1_addr : UInt<34>, clock
when _pstore1_addr_T :
connect pstore1_addr, s1_vaddr
node _pstore1_data_T = and(s1_valid_not_nacked, s1_write)
reg pstore1_data : UInt<64>, clock
when _pstore1_data_T :
connect pstore1_data, io.cpu.s1_data.data
node _pstore1_way_T = and(s1_valid_not_nacked, s1_write)
reg pstore1_way : UInt<1>, clock
when _pstore1_way_T :
connect pstore1_way, s1_hit_way
node _pstore1_mask_T = and(s1_valid_not_nacked, s1_write)
reg pstore1_mask : UInt<8>, clock
when _pstore1_mask_T :
connect pstore1_mask, s1_mask
wire pstore1_storegen_data : UInt
connect pstore1_storegen_data, pstore1_data
node _pstore1_rmw_T = eq(s1_req.cmd, UInt<1>(0h0))
node _pstore1_rmw_T_1 = eq(s1_req.cmd, UInt<5>(0h10))
node _pstore1_rmw_T_2 = eq(s1_req.cmd, UInt<3>(0h6))
node _pstore1_rmw_T_3 = eq(s1_req.cmd, UInt<3>(0h7))
node _pstore1_rmw_T_4 = or(_pstore1_rmw_T, _pstore1_rmw_T_1)
node _pstore1_rmw_T_5 = or(_pstore1_rmw_T_4, _pstore1_rmw_T_2)
node _pstore1_rmw_T_6 = or(_pstore1_rmw_T_5, _pstore1_rmw_T_3)
node _pstore1_rmw_T_7 = eq(s1_req.cmd, UInt<3>(0h4))
node _pstore1_rmw_T_8 = eq(s1_req.cmd, UInt<4>(0h9))
node _pstore1_rmw_T_9 = eq(s1_req.cmd, UInt<4>(0ha))
node _pstore1_rmw_T_10 = eq(s1_req.cmd, UInt<4>(0hb))
node _pstore1_rmw_T_11 = or(_pstore1_rmw_T_7, _pstore1_rmw_T_8)
node _pstore1_rmw_T_12 = or(_pstore1_rmw_T_11, _pstore1_rmw_T_9)
node _pstore1_rmw_T_13 = or(_pstore1_rmw_T_12, _pstore1_rmw_T_10)
node _pstore1_rmw_T_14 = eq(s1_req.cmd, UInt<4>(0h8))
node _pstore1_rmw_T_15 = eq(s1_req.cmd, UInt<4>(0hc))
node _pstore1_rmw_T_16 = eq(s1_req.cmd, UInt<4>(0hd))
node _pstore1_rmw_T_17 = eq(s1_req.cmd, UInt<4>(0he))
node _pstore1_rmw_T_18 = eq(s1_req.cmd, UInt<4>(0hf))
node _pstore1_rmw_T_19 = or(_pstore1_rmw_T_14, _pstore1_rmw_T_15)
node _pstore1_rmw_T_20 = or(_pstore1_rmw_T_19, _pstore1_rmw_T_16)
node _pstore1_rmw_T_21 = or(_pstore1_rmw_T_20, _pstore1_rmw_T_17)
node _pstore1_rmw_T_22 = or(_pstore1_rmw_T_21, _pstore1_rmw_T_18)
node _pstore1_rmw_T_23 = or(_pstore1_rmw_T_13, _pstore1_rmw_T_22)
node _pstore1_rmw_T_24 = or(_pstore1_rmw_T_6, _pstore1_rmw_T_23)
node _pstore1_rmw_T_25 = eq(s1_req.cmd, UInt<1>(0h1))
node _pstore1_rmw_T_26 = eq(s1_req.cmd, UInt<5>(0h11))
node _pstore1_rmw_T_27 = or(_pstore1_rmw_T_25, _pstore1_rmw_T_26)
node _pstore1_rmw_T_28 = eq(s1_req.cmd, UInt<3>(0h7))
node _pstore1_rmw_T_29 = or(_pstore1_rmw_T_27, _pstore1_rmw_T_28)
node _pstore1_rmw_T_30 = eq(s1_req.cmd, UInt<3>(0h4))
node _pstore1_rmw_T_31 = eq(s1_req.cmd, UInt<4>(0h9))
node _pstore1_rmw_T_32 = eq(s1_req.cmd, UInt<4>(0ha))
node _pstore1_rmw_T_33 = eq(s1_req.cmd, UInt<4>(0hb))
node _pstore1_rmw_T_34 = or(_pstore1_rmw_T_30, _pstore1_rmw_T_31)
node _pstore1_rmw_T_35 = or(_pstore1_rmw_T_34, _pstore1_rmw_T_32)
node _pstore1_rmw_T_36 = or(_pstore1_rmw_T_35, _pstore1_rmw_T_33)
node _pstore1_rmw_T_37 = eq(s1_req.cmd, UInt<4>(0h8))
node _pstore1_rmw_T_38 = eq(s1_req.cmd, UInt<4>(0hc))
node _pstore1_rmw_T_39 = eq(s1_req.cmd, UInt<4>(0hd))
node _pstore1_rmw_T_40 = eq(s1_req.cmd, UInt<4>(0he))
node _pstore1_rmw_T_41 = eq(s1_req.cmd, UInt<4>(0hf))
node _pstore1_rmw_T_42 = or(_pstore1_rmw_T_37, _pstore1_rmw_T_38)
node _pstore1_rmw_T_43 = or(_pstore1_rmw_T_42, _pstore1_rmw_T_39)
node _pstore1_rmw_T_44 = or(_pstore1_rmw_T_43, _pstore1_rmw_T_40)
node _pstore1_rmw_T_45 = or(_pstore1_rmw_T_44, _pstore1_rmw_T_41)
node _pstore1_rmw_T_46 = or(_pstore1_rmw_T_36, _pstore1_rmw_T_45)
node _pstore1_rmw_T_47 = or(_pstore1_rmw_T_29, _pstore1_rmw_T_46)
node _pstore1_rmw_T_48 = eq(s1_req.cmd, UInt<5>(0h11))
node _pstore1_rmw_T_49 = lt(s1_req.size, UInt<1>(0h0))
node _pstore1_rmw_T_50 = or(_pstore1_rmw_T_48, _pstore1_rmw_T_49)
node _pstore1_rmw_T_51 = and(_pstore1_rmw_T_47, _pstore1_rmw_T_50)
node _pstore1_rmw_T_52 = or(_pstore1_rmw_T_24, _pstore1_rmw_T_51)
node _pstore1_rmw_T_53 = and(s1_valid_not_nacked, s1_write)
reg pstore1_rmw_r : UInt<1>, clock
when _pstore1_rmw_T_53 :
connect pstore1_rmw_r, _pstore1_rmw_T_52
node pstore1_rmw = and(UInt<1>(0h1), pstore1_rmw_r)
node _pstore1_merge_likely_T = and(s2_valid_not_nacked_in_s1, s2_write)
node pstore1_merge_likely = and(_pstore1_merge_likely_T, s2_store_merge)
node _pstore1_merge_T = and(s2_valid_hit, s2_write)
node _pstore1_merge_T_1 = eq(s2_sc_fail, UInt<1>(0h0))
node _pstore1_merge_T_2 = and(_pstore1_merge_T, _pstore1_merge_T_1)
node _pstore1_merge_T_3 = eq(io.cpu.s2_kill, UInt<1>(0h0))
node _pstore1_merge_T_4 = and(_pstore1_merge_T_2, _pstore1_merge_T_3)
node pstore1_merge = and(_pstore1_merge_T_4, s2_store_merge)
regreset pstore2_valid : UInt<1>, clock, reset, UInt<1>(0h0)
node _pstore_drain_opportunistic_res_T = eq(io.cpu.req.bits.cmd, UInt<1>(0h1))
node _pstore_drain_opportunistic_res_T_1 = eq(io.cpu.req.bits.cmd, UInt<2>(0h3))
node _pstore_drain_opportunistic_res_T_2 = or(_pstore_drain_opportunistic_res_T, _pstore_drain_opportunistic_res_T_1)
node _pstore_drain_opportunistic_res_T_3 = eq(_pstore_drain_opportunistic_res_T_2, UInt<1>(0h0))
node _pstore_drain_opportunistic_res_T_4 = lt(io.cpu.req.bits.size, UInt<1>(0h0))
node pstore_drain_opportunistic_res = or(_pstore_drain_opportunistic_res_T_3, _pstore_drain_opportunistic_res_T_4)
node _pstore_drain_opportunistic_T = eq(io.cpu.req.bits.cmd, UInt<1>(0h0))
node _pstore_drain_opportunistic_T_1 = eq(io.cpu.req.bits.cmd, UInt<5>(0h10))
node _pstore_drain_opportunistic_T_2 = eq(io.cpu.req.bits.cmd, UInt<3>(0h6))
node _pstore_drain_opportunistic_T_3 = eq(io.cpu.req.bits.cmd, UInt<3>(0h7))
node _pstore_drain_opportunistic_T_4 = or(_pstore_drain_opportunistic_T, _pstore_drain_opportunistic_T_1)
node _pstore_drain_opportunistic_T_5 = or(_pstore_drain_opportunistic_T_4, _pstore_drain_opportunistic_T_2)
node _pstore_drain_opportunistic_T_6 = or(_pstore_drain_opportunistic_T_5, _pstore_drain_opportunistic_T_3)
node _pstore_drain_opportunistic_T_7 = eq(io.cpu.req.bits.cmd, UInt<3>(0h4))
node _pstore_drain_opportunistic_T_8 = eq(io.cpu.req.bits.cmd, UInt<4>(0h9))
node _pstore_drain_opportunistic_T_9 = eq(io.cpu.req.bits.cmd, UInt<4>(0ha))
node _pstore_drain_opportunistic_T_10 = eq(io.cpu.req.bits.cmd, UInt<4>(0hb))
node _pstore_drain_opportunistic_T_11 = or(_pstore_drain_opportunistic_T_7, _pstore_drain_opportunistic_T_8)
node _pstore_drain_opportunistic_T_12 = or(_pstore_drain_opportunistic_T_11, _pstore_drain_opportunistic_T_9)
node _pstore_drain_opportunistic_T_13 = or(_pstore_drain_opportunistic_T_12, _pstore_drain_opportunistic_T_10)
node _pstore_drain_opportunistic_T_14 = eq(io.cpu.req.bits.cmd, UInt<4>(0h8))
node _pstore_drain_opportunistic_T_15 = eq(io.cpu.req.bits.cmd, UInt<4>(0hc))
node _pstore_drain_opportunistic_T_16 = eq(io.cpu.req.bits.cmd, UInt<4>(0hd))
node _pstore_drain_opportunistic_T_17 = eq(io.cpu.req.bits.cmd, UInt<4>(0he))
node _pstore_drain_opportunistic_T_18 = eq(io.cpu.req.bits.cmd, UInt<4>(0hf))
node _pstore_drain_opportunistic_T_19 = or(_pstore_drain_opportunistic_T_14, _pstore_drain_opportunistic_T_15)
node _pstore_drain_opportunistic_T_20 = or(_pstore_drain_opportunistic_T_19, _pstore_drain_opportunistic_T_16)
node _pstore_drain_opportunistic_T_21 = or(_pstore_drain_opportunistic_T_20, _pstore_drain_opportunistic_T_17)
node _pstore_drain_opportunistic_T_22 = or(_pstore_drain_opportunistic_T_21, _pstore_drain_opportunistic_T_18)
node _pstore_drain_opportunistic_T_23 = or(_pstore_drain_opportunistic_T_13, _pstore_drain_opportunistic_T_22)
node _pstore_drain_opportunistic_T_24 = or(_pstore_drain_opportunistic_T_6, _pstore_drain_opportunistic_T_23)
node _pstore_drain_opportunistic_T_25 = eq(io.cpu.req.bits.cmd, UInt<1>(0h1))
node _pstore_drain_opportunistic_T_26 = eq(io.cpu.req.bits.cmd, UInt<5>(0h11))
node _pstore_drain_opportunistic_T_27 = or(_pstore_drain_opportunistic_T_25, _pstore_drain_opportunistic_T_26)
node _pstore_drain_opportunistic_T_28 = eq(io.cpu.req.bits.cmd, UInt<3>(0h7))
node _pstore_drain_opportunistic_T_29 = or(_pstore_drain_opportunistic_T_27, _pstore_drain_opportunistic_T_28)
node _pstore_drain_opportunistic_T_30 = eq(io.cpu.req.bits.cmd, UInt<3>(0h4))
node _pstore_drain_opportunistic_T_31 = eq(io.cpu.req.bits.cmd, UInt<4>(0h9))
node _pstore_drain_opportunistic_T_32 = eq(io.cpu.req.bits.cmd, UInt<4>(0ha))
node _pstore_drain_opportunistic_T_33 = eq(io.cpu.req.bits.cmd, UInt<4>(0hb))
node _pstore_drain_opportunistic_T_34 = or(_pstore_drain_opportunistic_T_30, _pstore_drain_opportunistic_T_31)
node _pstore_drain_opportunistic_T_35 = or(_pstore_drain_opportunistic_T_34, _pstore_drain_opportunistic_T_32)
node _pstore_drain_opportunistic_T_36 = or(_pstore_drain_opportunistic_T_35, _pstore_drain_opportunistic_T_33)
node _pstore_drain_opportunistic_T_37 = eq(io.cpu.req.bits.cmd, UInt<4>(0h8))
node _pstore_drain_opportunistic_T_38 = eq(io.cpu.req.bits.cmd, UInt<4>(0hc))
node _pstore_drain_opportunistic_T_39 = eq(io.cpu.req.bits.cmd, UInt<4>(0hd))
node _pstore_drain_opportunistic_T_40 = eq(io.cpu.req.bits.cmd, UInt<4>(0he))
node _pstore_drain_opportunistic_T_41 = eq(io.cpu.req.bits.cmd, UInt<4>(0hf))
node _pstore_drain_opportunistic_T_42 = or(_pstore_drain_opportunistic_T_37, _pstore_drain_opportunistic_T_38)
node _pstore_drain_opportunistic_T_43 = or(_pstore_drain_opportunistic_T_42, _pstore_drain_opportunistic_T_39)
node _pstore_drain_opportunistic_T_44 = or(_pstore_drain_opportunistic_T_43, _pstore_drain_opportunistic_T_40)
node _pstore_drain_opportunistic_T_45 = or(_pstore_drain_opportunistic_T_44, _pstore_drain_opportunistic_T_41)
node _pstore_drain_opportunistic_T_46 = or(_pstore_drain_opportunistic_T_36, _pstore_drain_opportunistic_T_45)
node _pstore_drain_opportunistic_T_47 = or(_pstore_drain_opportunistic_T_29, _pstore_drain_opportunistic_T_46)
node _pstore_drain_opportunistic_T_48 = eq(io.cpu.req.bits.cmd, UInt<5>(0h11))
node _pstore_drain_opportunistic_T_49 = lt(io.cpu.req.bits.size, UInt<1>(0h0))
node _pstore_drain_opportunistic_T_50 = or(_pstore_drain_opportunistic_T_48, _pstore_drain_opportunistic_T_49)
node _pstore_drain_opportunistic_T_51 = and(_pstore_drain_opportunistic_T_47, _pstore_drain_opportunistic_T_50)
node _pstore_drain_opportunistic_T_52 = or(_pstore_drain_opportunistic_T_24, _pstore_drain_opportunistic_T_51)
node _pstore_drain_opportunistic_T_53 = eq(_pstore_drain_opportunistic_T_52, UInt<1>(0h0))
node _pstore_drain_opportunistic_T_54 = or(_pstore_drain_opportunistic_T_53, pstore_drain_opportunistic_res)
node _pstore_drain_opportunistic_T_55 = asUInt(reset)
node _pstore_drain_opportunistic_T_56 = eq(_pstore_drain_opportunistic_T_55, UInt<1>(0h0))
when _pstore_drain_opportunistic_T_56 :
node _pstore_drain_opportunistic_T_57 = eq(_pstore_drain_opportunistic_T_54, UInt<1>(0h0))
when _pstore_drain_opportunistic_T_57 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at DCache.scala:1186 assert(!needsRead(req) || res)\n") : pstore_drain_opportunistic_printf
assert(clock, _pstore_drain_opportunistic_T_54, UInt<1>(0h1), "") : pstore_drain_opportunistic_assert
node _pstore_drain_opportunistic_T_58 = and(io.cpu.req.valid, pstore_drain_opportunistic_res)
node _pstore_drain_opportunistic_T_59 = eq(_pstore_drain_opportunistic_T_58, UInt<1>(0h0))
node _pstore_drain_opportunistic_T_60 = and(s1_valid, s1_waw_hazard)
node _pstore_drain_opportunistic_T_61 = eq(_pstore_drain_opportunistic_T_60, UInt<1>(0h0))
node pstore_drain_opportunistic = and(_pstore_drain_opportunistic_T_59, _pstore_drain_opportunistic_T_61)
reg pstore_drain_on_miss_REG : UInt<1>, clock
connect pstore_drain_on_miss_REG, io.cpu.s2_nack
node pstore_drain_on_miss = or(releaseInFlight, pstore_drain_on_miss_REG)
regreset pstore1_held : UInt<1>, clock, reset, UInt<1>(0h0)
node _pstore1_valid_likely_T = and(s2_valid, s2_write)
node pstore1_valid_likely = or(_pstore1_valid_likely_T, pstore1_held)
node _pstore1_valid_T = and(s2_valid_hit, s2_write)
node _pstore1_valid_T_1 = eq(s2_sc_fail, UInt<1>(0h0))
node _pstore1_valid_T_2 = and(_pstore1_valid_T, _pstore1_valid_T_1)
node _pstore1_valid_T_3 = eq(io.cpu.s2_kill, UInt<1>(0h0))
node _pstore1_valid_T_4 = and(_pstore1_valid_T_2, _pstore1_valid_T_3)
node pstore1_valid = or(_pstore1_valid_T_4, pstore1_held)
node _any_pstore_valid_T = or(pstore1_held, pstore2_valid)
connect any_pstore_valid, _any_pstore_valid_T
node _pstore_drain_structural_T = and(pstore1_valid_likely, pstore2_valid)
node _pstore_drain_structural_T_1 = and(s1_valid, s1_write)
node _pstore_drain_structural_T_2 = or(_pstore_drain_structural_T_1, pstore1_rmw)
node pstore_drain_structural = and(_pstore_drain_structural_T, _pstore_drain_structural_T_2)
node _T_48 = and(s2_valid_hit_pre_data_ecc, s2_write)
node _T_49 = eq(io.cpu.s2_kill, UInt<1>(0h0))
node _T_50 = and(_T_48, _T_49)
node _T_51 = or(_T_50, pstore1_held)
node _T_52 = eq(_T_51, pstore1_valid)
node _T_53 = or(pstore1_rmw, _T_52)
node _T_54 = asUInt(reset)
node _T_55 = eq(_T_54, UInt<1>(0h0))
when _T_55 :
node _T_56 = eq(_T_53, UInt<1>(0h0))
when _T_56 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at DCache.scala:510 assert(pstore1_rmw || pstore1_valid_not_rmw(io.cpu.s2_kill) === pstore1_valid)\n") : printf_1
assert(clock, _T_53, UInt<1>(0h1), "") : assert_1
node _T_57 = and(pstore1_valid, pstore_drain_on_miss)
node _T_58 = and(s1_valid_not_nacked, s1_waw_hazard)
node pstore_drain_s2_kill = and(UInt<1>(0h1), io.cpu.s2_kill)
node _pstore_drain_T = eq(pstore1_merge_likely, UInt<1>(0h0))
node _pstore_drain_T_1 = and(UInt<1>(0h1), pstore_drain_structural)
node _pstore_drain_T_2 = and(s2_valid_hit_pre_data_ecc, s2_write)
node _pstore_drain_T_3 = eq(pstore_drain_s2_kill, UInt<1>(0h0))
node _pstore_drain_T_4 = and(_pstore_drain_T_2, _pstore_drain_T_3)
node _pstore_drain_T_5 = or(_pstore_drain_T_4, pstore1_held)
node _pstore_drain_T_6 = eq(pstore1_rmw, UInt<1>(0h0))
node _pstore_drain_T_7 = and(_pstore_drain_T_5, _pstore_drain_T_6)
node _pstore_drain_T_8 = or(_pstore_drain_T_7, pstore2_valid)
node _pstore_drain_T_9 = or(pstore_drain_opportunistic, pstore_drain_on_miss)
node _pstore_drain_T_10 = and(_pstore_drain_T_8, _pstore_drain_T_9)
node _pstore_drain_T_11 = or(_pstore_drain_T_1, _pstore_drain_T_10)
node pstore_drain = and(_pstore_drain_T, _pstore_drain_T_11)
node _pstore1_held_T = and(s2_valid_hit, s2_write)
node _pstore1_held_T_1 = eq(s2_sc_fail, UInt<1>(0h0))
node _pstore1_held_T_2 = and(_pstore1_held_T, _pstore1_held_T_1)
node _pstore1_held_T_3 = eq(io.cpu.s2_kill, UInt<1>(0h0))
node _pstore1_held_T_4 = and(_pstore1_held_T_2, _pstore1_held_T_3)
node _pstore1_held_T_5 = eq(s2_store_merge, UInt<1>(0h0))
node _pstore1_held_T_6 = and(_pstore1_held_T_4, _pstore1_held_T_5)
node _pstore1_held_T_7 = or(_pstore1_held_T_6, pstore1_held)
node _pstore1_held_T_8 = and(_pstore1_held_T_7, pstore2_valid)
node _pstore1_held_T_9 = eq(pstore_drain, UInt<1>(0h0))
node _pstore1_held_T_10 = and(_pstore1_held_T_8, _pstore1_held_T_9)
connect pstore1_held, _pstore1_held_T_10
node _advance_pstore1_T = or(pstore1_valid, s2_valid_correct)
node _advance_pstore1_T_1 = eq(pstore2_valid, pstore_drain)
node advance_pstore1 = and(_advance_pstore1_T, _advance_pstore1_T_1)
node _pstore2_valid_T = eq(pstore_drain, UInt<1>(0h0))
node _pstore2_valid_T_1 = and(pstore2_valid, _pstore2_valid_T)
node _pstore2_valid_T_2 = or(_pstore2_valid_T_1, advance_pstore1)
connect pstore2_valid, _pstore2_valid_T_2
node _pstore2_addr_T = mux(s2_correct, s2_vaddr, pstore1_addr)
reg pstore2_addr : UInt<34>, clock
when advance_pstore1 :
connect pstore2_addr, _pstore2_addr_T
node _pstore2_way_T = mux(s2_correct, s2_hit_way, pstore1_way)
reg pstore2_way : UInt<1>, clock
when advance_pstore1 :
connect pstore2_way, _pstore2_way_T
node _pstore2_storegen_data_T = bits(pstore1_storegen_data, 7, 0)
node _pstore2_storegen_data_T_1 = bits(pstore1_mask, 0, 0)
node _pstore2_storegen_data_T_2 = and(pstore1_merge, _pstore2_storegen_data_T_1)
node _pstore2_storegen_data_T_3 = or(advance_pstore1, _pstore2_storegen_data_T_2)
reg pstore2_storegen_data_r : UInt<8>, clock
when _pstore2_storegen_data_T_3 :
connect pstore2_storegen_data_r, _pstore2_storegen_data_T
node _pstore2_storegen_data_T_4 = bits(pstore1_storegen_data, 15, 8)
node _pstore2_storegen_data_T_5 = bits(pstore1_mask, 1, 1)
node _pstore2_storegen_data_T_6 = and(pstore1_merge, _pstore2_storegen_data_T_5)
node _pstore2_storegen_data_T_7 = or(advance_pstore1, _pstore2_storegen_data_T_6)
reg pstore2_storegen_data_r_1 : UInt<8>, clock
when _pstore2_storegen_data_T_7 :
connect pstore2_storegen_data_r_1, _pstore2_storegen_data_T_4
node _pstore2_storegen_data_T_8 = bits(pstore1_storegen_data, 23, 16)
node _pstore2_storegen_data_T_9 = bits(pstore1_mask, 2, 2)
node _pstore2_storegen_data_T_10 = and(pstore1_merge, _pstore2_storegen_data_T_9)
node _pstore2_storegen_data_T_11 = or(advance_pstore1, _pstore2_storegen_data_T_10)
reg pstore2_storegen_data_r_2 : UInt<8>, clock
when _pstore2_storegen_data_T_11 :
connect pstore2_storegen_data_r_2, _pstore2_storegen_data_T_8
node _pstore2_storegen_data_T_12 = bits(pstore1_storegen_data, 31, 24)
node _pstore2_storegen_data_T_13 = bits(pstore1_mask, 3, 3)
node _pstore2_storegen_data_T_14 = and(pstore1_merge, _pstore2_storegen_data_T_13)
node _pstore2_storegen_data_T_15 = or(advance_pstore1, _pstore2_storegen_data_T_14)
reg pstore2_storegen_data_r_3 : UInt<8>, clock
when _pstore2_storegen_data_T_15 :
connect pstore2_storegen_data_r_3, _pstore2_storegen_data_T_12
node _pstore2_storegen_data_T_16 = bits(pstore1_storegen_data, 39, 32)
node _pstore2_storegen_data_T_17 = bits(pstore1_mask, 4, 4)
node _pstore2_storegen_data_T_18 = and(pstore1_merge, _pstore2_storegen_data_T_17)
node _pstore2_storegen_data_T_19 = or(advance_pstore1, _pstore2_storegen_data_T_18)
reg pstore2_storegen_data_r_4 : UInt<8>, clock
when _pstore2_storegen_data_T_19 :
connect pstore2_storegen_data_r_4, _pstore2_storegen_data_T_16
node _pstore2_storegen_data_T_20 = bits(pstore1_storegen_data, 47, 40)
node _pstore2_storegen_data_T_21 = bits(pstore1_mask, 5, 5)
node _pstore2_storegen_data_T_22 = and(pstore1_merge, _pstore2_storegen_data_T_21)
node _pstore2_storegen_data_T_23 = or(advance_pstore1, _pstore2_storegen_data_T_22)
reg pstore2_storegen_data_r_5 : UInt<8>, clock
when _pstore2_storegen_data_T_23 :
connect pstore2_storegen_data_r_5, _pstore2_storegen_data_T_20
node _pstore2_storegen_data_T_24 = bits(pstore1_storegen_data, 55, 48)
node _pstore2_storegen_data_T_25 = bits(pstore1_mask, 6, 6)
node _pstore2_storegen_data_T_26 = and(pstore1_merge, _pstore2_storegen_data_T_25)
node _pstore2_storegen_data_T_27 = or(advance_pstore1, _pstore2_storegen_data_T_26)
reg pstore2_storegen_data_r_6 : UInt<8>, clock
when _pstore2_storegen_data_T_27 :
connect pstore2_storegen_data_r_6, _pstore2_storegen_data_T_24
node _pstore2_storegen_data_T_28 = bits(pstore1_storegen_data, 63, 56)
node _pstore2_storegen_data_T_29 = bits(pstore1_mask, 7, 7)
node _pstore2_storegen_data_T_30 = and(pstore1_merge, _pstore2_storegen_data_T_29)
node _pstore2_storegen_data_T_31 = or(advance_pstore1, _pstore2_storegen_data_T_30)
reg pstore2_storegen_data_r_7 : UInt<8>, clock
when _pstore2_storegen_data_T_31 :
connect pstore2_storegen_data_r_7, _pstore2_storegen_data_T_28
node pstore2_storegen_data_lo_lo = cat(pstore2_storegen_data_r_1, pstore2_storegen_data_r)
node pstore2_storegen_data_lo_hi = cat(pstore2_storegen_data_r_3, pstore2_storegen_data_r_2)
node pstore2_storegen_data_lo = cat(pstore2_storegen_data_lo_hi, pstore2_storegen_data_lo_lo)
node pstore2_storegen_data_hi_lo = cat(pstore2_storegen_data_r_5, pstore2_storegen_data_r_4)
node pstore2_storegen_data_hi_hi = cat(pstore2_storegen_data_r_7, pstore2_storegen_data_r_6)
node pstore2_storegen_data_hi = cat(pstore2_storegen_data_hi_hi, pstore2_storegen_data_hi_lo)
node pstore2_storegen_data = cat(pstore2_storegen_data_hi, pstore2_storegen_data_lo)
reg pstore2_storegen_mask : UInt<8>, clock
node _pstore2_storegen_mask_T = or(advance_pstore1, pstore1_merge)
when _pstore2_storegen_mask_T :
node _pstore2_storegen_mask_mergedMask_T = mux(pstore1_merge, pstore2_storegen_mask, UInt<1>(0h0))
node pstore2_storegen_mask_mergedMask = or(pstore1_mask, _pstore2_storegen_mask_mergedMask_T)
node _pstore2_storegen_mask_mask_T = not(pstore2_storegen_mask_mergedMask)
node _pstore2_storegen_mask_mask_T_1 = mux(s2_correct, UInt<1>(0h0), _pstore2_storegen_mask_mask_T)
node _pstore2_storegen_mask_mask_T_2 = not(_pstore2_storegen_mask_mask_T_1)
connect pstore2_storegen_mask, _pstore2_storegen_mask_mask_T_2
connect s2_store_merge, UInt<1>(0h0)
node dataArb_io_in_0_valid_s2_kill = and(UInt<1>(0h0), io.cpu.s2_kill)
node _dataArb_io_in_0_valid_T = eq(pstore1_merge_likely, UInt<1>(0h0))
node _dataArb_io_in_0_valid_T_1 = and(UInt<1>(0h1), pstore_drain_structural)
node _dataArb_io_in_0_valid_T_2 = and(s2_valid_hit_pre_data_ecc, s2_write)
node _dataArb_io_in_0_valid_T_3 = eq(dataArb_io_in_0_valid_s2_kill, UInt<1>(0h0))
node _dataArb_io_in_0_valid_T_4 = and(_dataArb_io_in_0_valid_T_2, _dataArb_io_in_0_valid_T_3)
node _dataArb_io_in_0_valid_T_5 = or(_dataArb_io_in_0_valid_T_4, pstore1_held)
node _dataArb_io_in_0_valid_T_6 = eq(pstore1_rmw, UInt<1>(0h0))
node _dataArb_io_in_0_valid_T_7 = and(_dataArb_io_in_0_valid_T_5, _dataArb_io_in_0_valid_T_6)
node _dataArb_io_in_0_valid_T_8 = or(_dataArb_io_in_0_valid_T_7, pstore2_valid)
node _dataArb_io_in_0_valid_T_9 = or(pstore_drain_opportunistic, pstore_drain_on_miss)
node _dataArb_io_in_0_valid_T_10 = and(_dataArb_io_in_0_valid_T_8, _dataArb_io_in_0_valid_T_9)
node _dataArb_io_in_0_valid_T_11 = or(_dataArb_io_in_0_valid_T_1, _dataArb_io_in_0_valid_T_10)
node _dataArb_io_in_0_valid_T_12 = and(_dataArb_io_in_0_valid_T, _dataArb_io_in_0_valid_T_11)
connect dataArb.io.in[0].valid, _dataArb_io_in_0_valid_T_12
connect dataArb.io.in[0].bits.write, pstore_drain
node _dataArb_io_in_0_bits_addr_T = mux(pstore2_valid, pstore2_addr, pstore1_addr)
connect dataArb.io.in[0].bits.addr, _dataArb_io_in_0_bits_addr_T
node _dataArb_io_in_0_bits_way_en_T = mux(pstore2_valid, pstore2_way, pstore1_way)
connect dataArb.io.in[0].bits.way_en, _dataArb_io_in_0_bits_way_en_T
node _dataArb_io_in_0_bits_wdata_T = mux(pstore2_valid, pstore2_storegen_data, pstore1_data)
node _dataArb_io_in_0_bits_wdata_T_1 = bits(_dataArb_io_in_0_bits_wdata_T, 7, 0)
node _dataArb_io_in_0_bits_wdata_T_2 = bits(_dataArb_io_in_0_bits_wdata_T, 15, 8)
node _dataArb_io_in_0_bits_wdata_T_3 = bits(_dataArb_io_in_0_bits_wdata_T, 23, 16)
node _dataArb_io_in_0_bits_wdata_T_4 = bits(_dataArb_io_in_0_bits_wdata_T, 31, 24)
node _dataArb_io_in_0_bits_wdata_T_5 = bits(_dataArb_io_in_0_bits_wdata_T, 39, 32)
node _dataArb_io_in_0_bits_wdata_T_6 = bits(_dataArb_io_in_0_bits_wdata_T, 47, 40)
node _dataArb_io_in_0_bits_wdata_T_7 = bits(_dataArb_io_in_0_bits_wdata_T, 55, 48)
node _dataArb_io_in_0_bits_wdata_T_8 = bits(_dataArb_io_in_0_bits_wdata_T, 63, 56)
node dataArb_io_in_0_bits_wdata_lo_lo = cat(_dataArb_io_in_0_bits_wdata_T_2, _dataArb_io_in_0_bits_wdata_T_1)
node dataArb_io_in_0_bits_wdata_lo_hi = cat(_dataArb_io_in_0_bits_wdata_T_4, _dataArb_io_in_0_bits_wdata_T_3)
node dataArb_io_in_0_bits_wdata_lo = cat(dataArb_io_in_0_bits_wdata_lo_hi, dataArb_io_in_0_bits_wdata_lo_lo)
node dataArb_io_in_0_bits_wdata_hi_lo = cat(_dataArb_io_in_0_bits_wdata_T_6, _dataArb_io_in_0_bits_wdata_T_5)
node dataArb_io_in_0_bits_wdata_hi_hi = cat(_dataArb_io_in_0_bits_wdata_T_8, _dataArb_io_in_0_bits_wdata_T_7)
node dataArb_io_in_0_bits_wdata_hi = cat(dataArb_io_in_0_bits_wdata_hi_hi, dataArb_io_in_0_bits_wdata_hi_lo)
node _dataArb_io_in_0_bits_wdata_T_9 = cat(dataArb_io_in_0_bits_wdata_hi, dataArb_io_in_0_bits_wdata_lo)
connect dataArb.io.in[0].bits.wdata, _dataArb_io_in_0_bits_wdata_T_9
node _dataArb_io_in_0_bits_wordMask_eccMask_T = bits(dataArb.io.in[0].bits.eccMask, 0, 0)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_1 = bits(dataArb.io.in[0].bits.eccMask, 1, 1)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_2 = bits(dataArb.io.in[0].bits.eccMask, 2, 2)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_3 = bits(dataArb.io.in[0].bits.eccMask, 3, 3)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_4 = bits(dataArb.io.in[0].bits.eccMask, 4, 4)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_5 = bits(dataArb.io.in[0].bits.eccMask, 5, 5)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_6 = bits(dataArb.io.in[0].bits.eccMask, 6, 6)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_7 = bits(dataArb.io.in[0].bits.eccMask, 7, 7)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_8 = or(_dataArb_io_in_0_bits_wordMask_eccMask_T, _dataArb_io_in_0_bits_wordMask_eccMask_T_1)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_9 = or(_dataArb_io_in_0_bits_wordMask_eccMask_T_8, _dataArb_io_in_0_bits_wordMask_eccMask_T_2)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_10 = or(_dataArb_io_in_0_bits_wordMask_eccMask_T_9, _dataArb_io_in_0_bits_wordMask_eccMask_T_3)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_11 = or(_dataArb_io_in_0_bits_wordMask_eccMask_T_10, _dataArb_io_in_0_bits_wordMask_eccMask_T_4)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_12 = or(_dataArb_io_in_0_bits_wordMask_eccMask_T_11, _dataArb_io_in_0_bits_wordMask_eccMask_T_5)
node _dataArb_io_in_0_bits_wordMask_eccMask_T_13 = or(_dataArb_io_in_0_bits_wordMask_eccMask_T_12, _dataArb_io_in_0_bits_wordMask_eccMask_T_6)
node dataArb_io_in_0_bits_wordMask_eccMask = or(_dataArb_io_in_0_bits_wordMask_eccMask_T_13, _dataArb_io_in_0_bits_wordMask_eccMask_T_7)
node _dataArb_io_in_0_bits_wordMask_wordMask_T = mux(pstore2_valid, pstore2_addr, pstore1_addr)
node dataArb_io_in_0_bits_wordMask_wordMask = dshl(UInt<1>(0h1), UInt<1>(0h0))
node _dataArb_io_in_0_bits_wordMask_T = bits(dataArb_io_in_0_bits_wordMask_wordMask, 0, 0)
node _dataArb_io_in_0_bits_wordMask_T_1 = bits(dataArb_io_in_0_bits_wordMask_wordMask, 1, 1)
node _dataArb_io_in_0_bits_wordMask_T_2 = cat(_dataArb_io_in_0_bits_wordMask_T_1, _dataArb_io_in_0_bits_wordMask_T)
node _dataArb_io_in_0_bits_wordMask_T_3 = and(_dataArb_io_in_0_bits_wordMask_T_2, dataArb_io_in_0_bits_wordMask_eccMask)
connect dataArb.io.in[0].bits.wordMask, _dataArb_io_in_0_bits_wordMask_T_3
node _dataArb_io_in_0_bits_eccMask_T = mux(pstore2_valid, pstore2_storegen_mask, pstore1_mask)
node _dataArb_io_in_0_bits_eccMask_T_1 = bits(_dataArb_io_in_0_bits_eccMask_T, 0, 0)
node _dataArb_io_in_0_bits_eccMask_T_2 = bits(_dataArb_io_in_0_bits_eccMask_T, 1, 1)
node _dataArb_io_in_0_bits_eccMask_T_3 = bits(_dataArb_io_in_0_bits_eccMask_T, 2, 2)
node _dataArb_io_in_0_bits_eccMask_T_4 = bits(_dataArb_io_in_0_bits_eccMask_T, 3, 3)
node _dataArb_io_in_0_bits_eccMask_T_5 = bits(_dataArb_io_in_0_bits_eccMask_T, 4, 4)
node _dataArb_io_in_0_bits_eccMask_T_6 = bits(_dataArb_io_in_0_bits_eccMask_T, 5, 5)
node _dataArb_io_in_0_bits_eccMask_T_7 = bits(_dataArb_io_in_0_bits_eccMask_T, 6, 6)
node _dataArb_io_in_0_bits_eccMask_T_8 = bits(_dataArb_io_in_0_bits_eccMask_T, 7, 7)
node _dataArb_io_in_0_bits_eccMask_T_9 = orr(_dataArb_io_in_0_bits_eccMask_T_1)
node _dataArb_io_in_0_bits_eccMask_T_10 = orr(_dataArb_io_in_0_bits_eccMask_T_2)
node _dataArb_io_in_0_bits_eccMask_T_11 = orr(_dataArb_io_in_0_bits_eccMask_T_3)
node _dataArb_io_in_0_bits_eccMask_T_12 = orr(_dataArb_io_in_0_bits_eccMask_T_4)
node _dataArb_io_in_0_bits_eccMask_T_13 = orr(_dataArb_io_in_0_bits_eccMask_T_5)
node _dataArb_io_in_0_bits_eccMask_T_14 = orr(_dataArb_io_in_0_bits_eccMask_T_6)
node _dataArb_io_in_0_bits_eccMask_T_15 = orr(_dataArb_io_in_0_bits_eccMask_T_7)
node _dataArb_io_in_0_bits_eccMask_T_16 = orr(_dataArb_io_in_0_bits_eccMask_T_8)
node dataArb_io_in_0_bits_eccMask_lo_lo = cat(_dataArb_io_in_0_bits_eccMask_T_10, _dataArb_io_in_0_bits_eccMask_T_9)
node dataArb_io_in_0_bits_eccMask_lo_hi = cat(_dataArb_io_in_0_bits_eccMask_T_12, _dataArb_io_in_0_bits_eccMask_T_11)
node dataArb_io_in_0_bits_eccMask_lo = cat(dataArb_io_in_0_bits_eccMask_lo_hi, dataArb_io_in_0_bits_eccMask_lo_lo)
node dataArb_io_in_0_bits_eccMask_hi_lo = cat(_dataArb_io_in_0_bits_eccMask_T_14, _dataArb_io_in_0_bits_eccMask_T_13)
node dataArb_io_in_0_bits_eccMask_hi_hi = cat(_dataArb_io_in_0_bits_eccMask_T_16, _dataArb_io_in_0_bits_eccMask_T_15)
node dataArb_io_in_0_bits_eccMask_hi = cat(dataArb_io_in_0_bits_eccMask_hi_hi, dataArb_io_in_0_bits_eccMask_hi_lo)
node _dataArb_io_in_0_bits_eccMask_T_17 = cat(dataArb_io_in_0_bits_eccMask_hi, dataArb_io_in_0_bits_eccMask_lo)
connect dataArb.io.in[0].bits.eccMask, _dataArb_io_in_0_bits_eccMask_T_17
node _s1_hazard_T = bits(pstore1_addr, 13, 3)
node _s1_hazard_T_1 = bits(s1_vaddr, 13, 3)
node _s1_hazard_T_2 = eq(_s1_hazard_T, _s1_hazard_T_1)
node _s1_hazard_T_3 = bits(pstore1_mask, 0, 0)
node _s1_hazard_T_4 = bits(pstore1_mask, 1, 1)
node _s1_hazard_T_5 = bits(pstore1_mask, 2, 2)
node _s1_hazard_T_6 = bits(pstore1_mask, 3, 3)
node _s1_hazard_T_7 = bits(pstore1_mask, 4, 4)
node _s1_hazard_T_8 = bits(pstore1_mask, 5, 5)
node _s1_hazard_T_9 = bits(pstore1_mask, 6, 6)
node _s1_hazard_T_10 = bits(pstore1_mask, 7, 7)
node _s1_hazard_T_11 = orr(_s1_hazard_T_3)
node _s1_hazard_T_12 = orr(_s1_hazard_T_4)
node _s1_hazard_T_13 = orr(_s1_hazard_T_5)
node _s1_hazard_T_14 = orr(_s1_hazard_T_6)
node _s1_hazard_T_15 = orr(_s1_hazard_T_7)
node _s1_hazard_T_16 = orr(_s1_hazard_T_8)
node _s1_hazard_T_17 = orr(_s1_hazard_T_9)
node _s1_hazard_T_18 = orr(_s1_hazard_T_10)
node s1_hazard_lo_lo = cat(_s1_hazard_T_12, _s1_hazard_T_11)
node s1_hazard_lo_hi = cat(_s1_hazard_T_14, _s1_hazard_T_13)
node s1_hazard_lo = cat(s1_hazard_lo_hi, s1_hazard_lo_lo)
node s1_hazard_hi_lo = cat(_s1_hazard_T_16, _s1_hazard_T_15)
node s1_hazard_hi_hi = cat(_s1_hazard_T_18, _s1_hazard_T_17)
node s1_hazard_hi = cat(s1_hazard_hi_hi, s1_hazard_hi_lo)
node _s1_hazard_T_19 = cat(s1_hazard_hi, s1_hazard_lo)
node _s1_hazard_T_20 = bits(_s1_hazard_T_19, 0, 0)
node _s1_hazard_T_21 = bits(_s1_hazard_T_19, 1, 1)
node _s1_hazard_T_22 = bits(_s1_hazard_T_19, 2, 2)
node _s1_hazard_T_23 = bits(_s1_hazard_T_19, 3, 3)
node _s1_hazard_T_24 = bits(_s1_hazard_T_19, 4, 4)
node _s1_hazard_T_25 = bits(_s1_hazard_T_19, 5, 5)
node _s1_hazard_T_26 = bits(_s1_hazard_T_19, 6, 6)
node _s1_hazard_T_27 = bits(_s1_hazard_T_19, 7, 7)
node s1_hazard_lo_lo_1 = cat(_s1_hazard_T_21, _s1_hazard_T_20)
node s1_hazard_lo_hi_1 = cat(_s1_hazard_T_23, _s1_hazard_T_22)
node s1_hazard_lo_1 = cat(s1_hazard_lo_hi_1, s1_hazard_lo_lo_1)
node s1_hazard_hi_lo_1 = cat(_s1_hazard_T_25, _s1_hazard_T_24)
node s1_hazard_hi_hi_1 = cat(_s1_hazard_T_27, _s1_hazard_T_26)
node s1_hazard_hi_1 = cat(s1_hazard_hi_hi_1, s1_hazard_hi_lo_1)
node _s1_hazard_T_28 = cat(s1_hazard_hi_1, s1_hazard_lo_1)
node _s1_hazard_T_29 = bits(s1_mask_xwr, 0, 0)
node _s1_hazard_T_30 = bits(s1_mask_xwr, 1, 1)
node _s1_hazard_T_31 = bits(s1_mask_xwr, 2, 2)
node _s1_hazard_T_32 = bits(s1_mask_xwr, 3, 3)
node _s1_hazard_T_33 = bits(s1_mask_xwr, 4, 4)
node _s1_hazard_T_34 = bits(s1_mask_xwr, 5, 5)
node _s1_hazard_T_35 = bits(s1_mask_xwr, 6, 6)
node _s1_hazard_T_36 = bits(s1_mask_xwr, 7, 7)
node _s1_hazard_T_37 = orr(_s1_hazard_T_29)
node _s1_hazard_T_38 = orr(_s1_hazard_T_30)
node _s1_hazard_T_39 = orr(_s1_hazard_T_31)
node _s1_hazard_T_40 = orr(_s1_hazard_T_32)
node _s1_hazard_T_41 = orr(_s1_hazard_T_33)
node _s1_hazard_T_42 = orr(_s1_hazard_T_34)
node _s1_hazard_T_43 = orr(_s1_hazard_T_35)
node _s1_hazard_T_44 = orr(_s1_hazard_T_36)
node s1_hazard_lo_lo_2 = cat(_s1_hazard_T_38, _s1_hazard_T_37)
node s1_hazard_lo_hi_2 = cat(_s1_hazard_T_40, _s1_hazard_T_39)
node s1_hazard_lo_2 = cat(s1_hazard_lo_hi_2, s1_hazard_lo_lo_2)
node s1_hazard_hi_lo_2 = cat(_s1_hazard_T_42, _s1_hazard_T_41)
node s1_hazard_hi_hi_2 = cat(_s1_hazard_T_44, _s1_hazard_T_43)
node s1_hazard_hi_2 = cat(s1_hazard_hi_hi_2, s1_hazard_hi_lo_2)
node _s1_hazard_T_45 = cat(s1_hazard_hi_2, s1_hazard_lo_2)
node _s1_hazard_T_46 = bits(_s1_hazard_T_45, 0, 0)
node _s1_hazard_T_47 = bits(_s1_hazard_T_45, 1, 1)
node _s1_hazard_T_48 = bits(_s1_hazard_T_45, 2, 2)
node _s1_hazard_T_49 = bits(_s1_hazard_T_45, 3, 3)
node _s1_hazard_T_50 = bits(_s1_hazard_T_45, 4, 4)
node _s1_hazard_T_51 = bits(_s1_hazard_T_45, 5, 5)
node _s1_hazard_T_52 = bits(_s1_hazard_T_45, 6, 6)
node _s1_hazard_T_53 = bits(_s1_hazard_T_45, 7, 7)
node s1_hazard_lo_lo_3 = cat(_s1_hazard_T_47, _s1_hazard_T_46)
node s1_hazard_lo_hi_3 = cat(_s1_hazard_T_49, _s1_hazard_T_48)
node s1_hazard_lo_3 = cat(s1_hazard_lo_hi_3, s1_hazard_lo_lo_3)
node s1_hazard_hi_lo_3 = cat(_s1_hazard_T_51, _s1_hazard_T_50)
node s1_hazard_hi_hi_3 = cat(_s1_hazard_T_53, _s1_hazard_T_52)
node s1_hazard_hi_3 = cat(s1_hazard_hi_hi_3, s1_hazard_hi_lo_3)
node _s1_hazard_T_54 = cat(s1_hazard_hi_3, s1_hazard_lo_3)
node _s1_hazard_T_55 = and(_s1_hazard_T_28, _s1_hazard_T_54)
node _s1_hazard_T_56 = orr(_s1_hazard_T_55)
node _s1_hazard_T_57 = and(pstore1_mask, s1_mask_xwr)
node _s1_hazard_T_58 = orr(_s1_hazard_T_57)
node _s1_hazard_T_59 = mux(s1_write, _s1_hazard_T_56, _s1_hazard_T_58)
node _s1_hazard_T_60 = and(_s1_hazard_T_2, _s1_hazard_T_59)
node _s1_hazard_T_61 = and(pstore1_valid_likely, _s1_hazard_T_60)
node _s1_hazard_T_62 = bits(pstore2_addr, 13, 3)
node _s1_hazard_T_63 = bits(s1_vaddr, 13, 3)
node _s1_hazard_T_64 = eq(_s1_hazard_T_62, _s1_hazard_T_63)
node _s1_hazard_T_65 = bits(pstore2_storegen_mask, 0, 0)
node _s1_hazard_T_66 = bits(pstore2_storegen_mask, 1, 1)
node _s1_hazard_T_67 = bits(pstore2_storegen_mask, 2, 2)
node _s1_hazard_T_68 = bits(pstore2_storegen_mask, 3, 3)
node _s1_hazard_T_69 = bits(pstore2_storegen_mask, 4, 4)
node _s1_hazard_T_70 = bits(pstore2_storegen_mask, 5, 5)
node _s1_hazard_T_71 = bits(pstore2_storegen_mask, 6, 6)
node _s1_hazard_T_72 = bits(pstore2_storegen_mask, 7, 7)
node _s1_hazard_T_73 = orr(_s1_hazard_T_65)
node _s1_hazard_T_74 = orr(_s1_hazard_T_66)
node _s1_hazard_T_75 = orr(_s1_hazard_T_67)
node _s1_hazard_T_76 = orr(_s1_hazard_T_68)
node _s1_hazard_T_77 = orr(_s1_hazard_T_69)
node _s1_hazard_T_78 = orr(_s1_hazard_T_70)
node _s1_hazard_T_79 = orr(_s1_hazard_T_71)
node _s1_hazard_T_80 = orr(_s1_hazard_T_72)
node s1_hazard_lo_lo_4 = cat(_s1_hazard_T_74, _s1_hazard_T_73)
node s1_hazard_lo_hi_4 = cat(_s1_hazard_T_76, _s1_hazard_T_75)
node s1_hazard_lo_4 = cat(s1_hazard_lo_hi_4, s1_hazard_lo_lo_4)
node s1_hazard_hi_lo_4 = cat(_s1_hazard_T_78, _s1_hazard_T_77)
node s1_hazard_hi_hi_4 = cat(_s1_hazard_T_80, _s1_hazard_T_79)
node s1_hazard_hi_4 = cat(s1_hazard_hi_hi_4, s1_hazard_hi_lo_4)
node _s1_hazard_T_81 = cat(s1_hazard_hi_4, s1_hazard_lo_4)
node _s1_hazard_T_82 = bits(_s1_hazard_T_81, 0, 0)
node _s1_hazard_T_83 = bits(_s1_hazard_T_81, 1, 1)
node _s1_hazard_T_84 = bits(_s1_hazard_T_81, 2, 2)
node _s1_hazard_T_85 = bits(_s1_hazard_T_81, 3, 3)
node _s1_hazard_T_86 = bits(_s1_hazard_T_81, 4, 4)
node _s1_hazard_T_87 = bits(_s1_hazard_T_81, 5, 5)
node _s1_hazard_T_88 = bits(_s1_hazard_T_81, 6, 6)
node _s1_hazard_T_89 = bits(_s1_hazard_T_81, 7, 7)
node s1_hazard_lo_lo_5 = cat(_s1_hazard_T_83, _s1_hazard_T_82)
node s1_hazard_lo_hi_5 = cat(_s1_hazard_T_85, _s1_hazard_T_84)
node s1_hazard_lo_5 = cat(s1_hazard_lo_hi_5, s1_hazard_lo_lo_5)
node s1_hazard_hi_lo_5 = cat(_s1_hazard_T_87, _s1_hazard_T_86)
node s1_hazard_hi_hi_5 = cat(_s1_hazard_T_89, _s1_hazard_T_88)
node s1_hazard_hi_5 = cat(s1_hazard_hi_hi_5, s1_hazard_hi_lo_5)
node _s1_hazard_T_90 = cat(s1_hazard_hi_5, s1_hazard_lo_5)
node _s1_hazard_T_91 = bits(s1_mask_xwr, 0, 0)
node _s1_hazard_T_92 = bits(s1_mask_xwr, 1, 1)
node _s1_hazard_T_93 = bits(s1_mask_xwr, 2, 2)
node _s1_hazard_T_94 = bits(s1_mask_xwr, 3, 3)
node _s1_hazard_T_95 = bits(s1_mask_xwr, 4, 4)
node _s1_hazard_T_96 = bits(s1_mask_xwr, 5, 5)
node _s1_hazard_T_97 = bits(s1_mask_xwr, 6, 6)
node _s1_hazard_T_98 = bits(s1_mask_xwr, 7, 7)
node _s1_hazard_T_99 = orr(_s1_hazard_T_91)
node _s1_hazard_T_100 = orr(_s1_hazard_T_92)
node _s1_hazard_T_101 = orr(_s1_hazard_T_93)
node _s1_hazard_T_102 = orr(_s1_hazard_T_94)
node _s1_hazard_T_103 = orr(_s1_hazard_T_95)
node _s1_hazard_T_104 = orr(_s1_hazard_T_96)
node _s1_hazard_T_105 = orr(_s1_hazard_T_97)
node _s1_hazard_T_106 = orr(_s1_hazard_T_98)
node s1_hazard_lo_lo_6 = cat(_s1_hazard_T_100, _s1_hazard_T_99)
node s1_hazard_lo_hi_6 = cat(_s1_hazard_T_102, _s1_hazard_T_101)
node s1_hazard_lo_6 = cat(s1_hazard_lo_hi_6, s1_hazard_lo_lo_6)
node s1_hazard_hi_lo_6 = cat(_s1_hazard_T_104, _s1_hazard_T_103)
node s1_hazard_hi_hi_6 = cat(_s1_hazard_T_106, _s1_hazard_T_105)
node s1_hazard_hi_6 = cat(s1_hazard_hi_hi_6, s1_hazard_hi_lo_6)
node _s1_hazard_T_107 = cat(s1_hazard_hi_6, s1_hazard_lo_6)
node _s1_hazard_T_108 = bits(_s1_hazard_T_107, 0, 0)
node _s1_hazard_T_109 = bits(_s1_hazard_T_107, 1, 1)
node _s1_hazard_T_110 = bits(_s1_hazard_T_107, 2, 2)
node _s1_hazard_T_111 = bits(_s1_hazard_T_107, 3, 3)
node _s1_hazard_T_112 = bits(_s1_hazard_T_107, 4, 4)
node _s1_hazard_T_113 = bits(_s1_hazard_T_107, 5, 5)
node _s1_hazard_T_114 = bits(_s1_hazard_T_107, 6, 6)
node _s1_hazard_T_115 = bits(_s1_hazard_T_107, 7, 7)
node s1_hazard_lo_lo_7 = cat(_s1_hazard_T_109, _s1_hazard_T_108)
node s1_hazard_lo_hi_7 = cat(_s1_hazard_T_111, _s1_hazard_T_110)
node s1_hazard_lo_7 = cat(s1_hazard_lo_hi_7, s1_hazard_lo_lo_7)
node s1_hazard_hi_lo_7 = cat(_s1_hazard_T_113, _s1_hazard_T_112)
node s1_hazard_hi_hi_7 = cat(_s1_hazard_T_115, _s1_hazard_T_114)
node s1_hazard_hi_7 = cat(s1_hazard_hi_hi_7, s1_hazard_hi_lo_7)
node _s1_hazard_T_116 = cat(s1_hazard_hi_7, s1_hazard_lo_7)
node _s1_hazard_T_117 = and(_s1_hazard_T_90, _s1_hazard_T_116)
node _s1_hazard_T_118 = orr(_s1_hazard_T_117)
node _s1_hazard_T_119 = and(pstore2_storegen_mask, s1_mask_xwr)
node _s1_hazard_T_120 = orr(_s1_hazard_T_119)
node _s1_hazard_T_121 = mux(s1_write, _s1_hazard_T_118, _s1_hazard_T_120)
node _s1_hazard_T_122 = and(_s1_hazard_T_64, _s1_hazard_T_121)
node _s1_hazard_T_123 = and(pstore2_valid, _s1_hazard_T_122)
node s1_hazard = or(_s1_hazard_T_61, _s1_hazard_T_123)
node s1_raw_hazard = and(s1_read, s1_hazard)
connect s1_waw_hazard, UInt<1>(0h0)
node _T_59 = and(s1_valid, s1_raw_hazard)
when _T_59 :
connect s1_nack, UInt<1>(0h1)
reg io_cpu_s2_nack_cause_raw_REG : UInt<1>, clock
connect io_cpu_s2_nack_cause_raw_REG, s1_raw_hazard
node _io_cpu_s2_nack_cause_raw_T = eq(s2_waw_hazard, UInt<1>(0h0))
node _io_cpu_s2_nack_cause_raw_T_1 = or(_io_cpu_s2_nack_cause_raw_T, s2_store_merge)
node _io_cpu_s2_nack_cause_raw_T_2 = eq(_io_cpu_s2_nack_cause_raw_T_1, UInt<1>(0h0))
node _io_cpu_s2_nack_cause_raw_T_3 = or(io_cpu_s2_nack_cause_raw_REG, _io_cpu_s2_nack_cause_raw_T_2)
connect io.cpu.s2_nack_cause_raw, _io_cpu_s2_nack_cause_raw_T_3
node _a_source_T = not(uncachedInFlight[0])
node _a_source_T_1 = shl(_a_source_T, 0)
node _a_source_T_2 = bits(_a_source_T_1, 0, 0)
node _acquire_address_T = shr(s2_req.addr, 6)
node acquire_address = shl(_acquire_address_T, 6)
node _a_mask_T = shl(UInt<1>(0h0), 3)
node a_mask = dshl(pstore1_mask, _a_mask_T)
node _get_legal_T = leq(UInt<1>(0h0), s2_req.size)
node _get_legal_T_1 = leq(s2_req.size, UInt<4>(0hc))
node _get_legal_T_2 = and(_get_legal_T, _get_legal_T_1)
node _get_legal_T_3 = or(UInt<1>(0h0), _get_legal_T_2)
node _get_legal_T_4 = xor(s2_req.addr, UInt<14>(0h3000))
node _get_legal_T_5 = cvt(_get_legal_T_4)
node _get_legal_T_6 = and(_get_legal_T_5, asSInt(UInt<33>(0hca113000)))
node _get_legal_T_7 = asSInt(_get_legal_T_6)
node _get_legal_T_8 = eq(_get_legal_T_7, asSInt(UInt<1>(0h0)))
node _get_legal_T_9 = and(_get_legal_T_3, _get_legal_T_8)
node _get_legal_T_10 = leq(UInt<1>(0h0), s2_req.size)
node _get_legal_T_11 = leq(s2_req.size, UInt<3>(0h6))
node _get_legal_T_12 = and(_get_legal_T_10, _get_legal_T_11)
node _get_legal_T_13 = or(UInt<1>(0h0), _get_legal_T_12)
node _get_legal_T_14 = xor(s2_req.addr, UInt<1>(0h0))
node _get_legal_T_15 = cvt(_get_legal_T_14)
node _get_legal_T_16 = and(_get_legal_T_15, asSInt(UInt<33>(0hca112000)))
node _get_legal_T_17 = asSInt(_get_legal_T_16)
node _get_legal_T_18 = eq(_get_legal_T_17, asSInt(UInt<1>(0h0)))
node _get_legal_T_19 = xor(s2_req.addr, UInt<17>(0h10000))
node _get_legal_T_20 = cvt(_get_legal_T_19)
node _get_legal_T_21 = and(_get_legal_T_20, asSInt(UInt<33>(0hca110000)))
node _get_legal_T_22 = asSInt(_get_legal_T_21)
node _get_legal_T_23 = eq(_get_legal_T_22, asSInt(UInt<1>(0h0)))
node _get_legal_T_24 = xor(s2_req.addr, UInt<21>(0h100000))
node _get_legal_T_25 = cvt(_get_legal_T_24)
node _get_legal_T_26 = and(_get_legal_T_25, asSInt(UInt<33>(0hca103000)))
node _get_legal_T_27 = asSInt(_get_legal_T_26)
node _get_legal_T_28 = eq(_get_legal_T_27, asSInt(UInt<1>(0h0)))
node _get_legal_T_29 = xor(s2_req.addr, UInt<26>(0h2000000))
node _get_legal_T_30 = cvt(_get_legal_T_29)
node _get_legal_T_31 = and(_get_legal_T_30, asSInt(UInt<33>(0hca110000)))
node _get_legal_T_32 = asSInt(_get_legal_T_31)
node _get_legal_T_33 = eq(_get_legal_T_32, asSInt(UInt<1>(0h0)))
node _get_legal_T_34 = xor(s2_req.addr, UInt<28>(0h8000000))
node _get_legal_T_35 = cvt(_get_legal_T_34)
node _get_legal_T_36 = and(_get_legal_T_35, asSInt(UInt<33>(0hc8000000)))
node _get_legal_T_37 = asSInt(_get_legal_T_36)
node _get_legal_T_38 = eq(_get_legal_T_37, asSInt(UInt<1>(0h0)))
node _get_legal_T_39 = xor(s2_req.addr, UInt<31>(0h40000000))
node _get_legal_T_40 = cvt(_get_legal_T_39)
node _get_legal_T_41 = and(_get_legal_T_40, asSInt(UInt<33>(0hc0000000)))
node _get_legal_T_42 = asSInt(_get_legal_T_41)
node _get_legal_T_43 = eq(_get_legal_T_42, asSInt(UInt<1>(0h0)))
node _get_legal_T_44 = xor(s2_req.addr, UInt<32>(0h80000000))
node _get_legal_T_45 = cvt(_get_legal_T_44)
node _get_legal_T_46 = and(_get_legal_T_45, asSInt(UInt<33>(0hca110000)))
node _get_legal_T_47 = asSInt(_get_legal_T_46)
node _get_legal_T_48 = eq(_get_legal_T_47, asSInt(UInt<1>(0h0)))
node _get_legal_T_49 = or(_get_legal_T_18, _get_legal_T_23)
node _get_legal_T_50 = or(_get_legal_T_49, _get_legal_T_28)
node _get_legal_T_51 = or(_get_legal_T_50, _get_legal_T_33)
node _get_legal_T_52 = or(_get_legal_T_51, _get_legal_T_38)
node _get_legal_T_53 = or(_get_legal_T_52, _get_legal_T_43)
node _get_legal_T_54 = or(_get_legal_T_53, _get_legal_T_48)
node _get_legal_T_55 = and(_get_legal_T_13, _get_legal_T_54)
node _get_legal_T_56 = or(UInt<1>(0h0), _get_legal_T_9)
node get_legal = or(_get_legal_T_56, _get_legal_T_55)
wire get : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect get.opcode, UInt<3>(0h4)
connect get.param, UInt<1>(0h0)
connect get.size, s2_req.size
connect get.source, UInt<1>(0h0)
connect get.address, s2_req.addr
invalidate get.user.amba_prot.fetch
invalidate get.user.amba_prot.secure
invalidate get.user.amba_prot.privileged
invalidate get.user.amba_prot.writealloc
invalidate get.user.amba_prot.readalloc
invalidate get.user.amba_prot.modifiable
invalidate get.user.amba_prot.bufferable
node _get_a_mask_sizeOH_T = or(s2_req.size, UInt<3>(0h0))
node get_a_mask_sizeOH_shiftAmount = bits(_get_a_mask_sizeOH_T, 1, 0)
node _get_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), get_a_mask_sizeOH_shiftAmount)
node _get_a_mask_sizeOH_T_2 = bits(_get_a_mask_sizeOH_T_1, 2, 0)
node get_a_mask_sizeOH = or(_get_a_mask_sizeOH_T_2, UInt<1>(0h1))
node get_a_mask_sub_sub_sub_0_1 = geq(s2_req.size, UInt<2>(0h3))
node get_a_mask_sub_sub_size = bits(get_a_mask_sizeOH, 2, 2)
node get_a_mask_sub_sub_bit = bits(s2_req.addr, 2, 2)
node get_a_mask_sub_sub_nbit = eq(get_a_mask_sub_sub_bit, UInt<1>(0h0))
node get_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), get_a_mask_sub_sub_nbit)
node _get_a_mask_sub_sub_acc_T = and(get_a_mask_sub_sub_size, get_a_mask_sub_sub_0_2)
node get_a_mask_sub_sub_0_1 = or(get_a_mask_sub_sub_sub_0_1, _get_a_mask_sub_sub_acc_T)
node get_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), get_a_mask_sub_sub_bit)
node _get_a_mask_sub_sub_acc_T_1 = and(get_a_mask_sub_sub_size, get_a_mask_sub_sub_1_2)
node get_a_mask_sub_sub_1_1 = or(get_a_mask_sub_sub_sub_0_1, _get_a_mask_sub_sub_acc_T_1)
node get_a_mask_sub_size = bits(get_a_mask_sizeOH, 1, 1)
node get_a_mask_sub_bit = bits(s2_req.addr, 1, 1)
node get_a_mask_sub_nbit = eq(get_a_mask_sub_bit, UInt<1>(0h0))
node get_a_mask_sub_0_2 = and(get_a_mask_sub_sub_0_2, get_a_mask_sub_nbit)
node _get_a_mask_sub_acc_T = and(get_a_mask_sub_size, get_a_mask_sub_0_2)
node get_a_mask_sub_0_1 = or(get_a_mask_sub_sub_0_1, _get_a_mask_sub_acc_T)
node get_a_mask_sub_1_2 = and(get_a_mask_sub_sub_0_2, get_a_mask_sub_bit)
node _get_a_mask_sub_acc_T_1 = and(get_a_mask_sub_size, get_a_mask_sub_1_2)
node get_a_mask_sub_1_1 = or(get_a_mask_sub_sub_0_1, _get_a_mask_sub_acc_T_1)
node get_a_mask_sub_2_2 = and(get_a_mask_sub_sub_1_2, get_a_mask_sub_nbit)
node _get_a_mask_sub_acc_T_2 = and(get_a_mask_sub_size, get_a_mask_sub_2_2)
node get_a_mask_sub_2_1 = or(get_a_mask_sub_sub_1_1, _get_a_mask_sub_acc_T_2)
node get_a_mask_sub_3_2 = and(get_a_mask_sub_sub_1_2, get_a_mask_sub_bit)
node _get_a_mask_sub_acc_T_3 = and(get_a_mask_sub_size, get_a_mask_sub_3_2)
node get_a_mask_sub_3_1 = or(get_a_mask_sub_sub_1_1, _get_a_mask_sub_acc_T_3)
node get_a_mask_size = bits(get_a_mask_sizeOH, 0, 0)
node get_a_mask_bit = bits(s2_req.addr, 0, 0)
node get_a_mask_nbit = eq(get_a_mask_bit, UInt<1>(0h0))
node get_a_mask_eq = and(get_a_mask_sub_0_2, get_a_mask_nbit)
node _get_a_mask_acc_T = and(get_a_mask_size, get_a_mask_eq)
node get_a_mask_acc = or(get_a_mask_sub_0_1, _get_a_mask_acc_T)
node get_a_mask_eq_1 = and(get_a_mask_sub_0_2, get_a_mask_bit)
node _get_a_mask_acc_T_1 = and(get_a_mask_size, get_a_mask_eq_1)
node get_a_mask_acc_1 = or(get_a_mask_sub_0_1, _get_a_mask_acc_T_1)
node get_a_mask_eq_2 = and(get_a_mask_sub_1_2, get_a_mask_nbit)
node _get_a_mask_acc_T_2 = and(get_a_mask_size, get_a_mask_eq_2)
node get_a_mask_acc_2 = or(get_a_mask_sub_1_1, _get_a_mask_acc_T_2)
node get_a_mask_eq_3 = and(get_a_mask_sub_1_2, get_a_mask_bit)
node _get_a_mask_acc_T_3 = and(get_a_mask_size, get_a_mask_eq_3)
node get_a_mask_acc_3 = or(get_a_mask_sub_1_1, _get_a_mask_acc_T_3)
node get_a_mask_eq_4 = and(get_a_mask_sub_2_2, get_a_mask_nbit)
node _get_a_mask_acc_T_4 = and(get_a_mask_size, get_a_mask_eq_4)
node get_a_mask_acc_4 = or(get_a_mask_sub_2_1, _get_a_mask_acc_T_4)
node get_a_mask_eq_5 = and(get_a_mask_sub_2_2, get_a_mask_bit)
node _get_a_mask_acc_T_5 = and(get_a_mask_size, get_a_mask_eq_5)
node get_a_mask_acc_5 = or(get_a_mask_sub_2_1, _get_a_mask_acc_T_5)
node get_a_mask_eq_6 = and(get_a_mask_sub_3_2, get_a_mask_nbit)
node _get_a_mask_acc_T_6 = and(get_a_mask_size, get_a_mask_eq_6)
node get_a_mask_acc_6 = or(get_a_mask_sub_3_1, _get_a_mask_acc_T_6)
node get_a_mask_eq_7 = and(get_a_mask_sub_3_2, get_a_mask_bit)
node _get_a_mask_acc_T_7 = and(get_a_mask_size, get_a_mask_eq_7)
node get_a_mask_acc_7 = or(get_a_mask_sub_3_1, _get_a_mask_acc_T_7)
node get_a_mask_lo_lo = cat(get_a_mask_acc_1, get_a_mask_acc)
node get_a_mask_lo_hi = cat(get_a_mask_acc_3, get_a_mask_acc_2)
node get_a_mask_lo = cat(get_a_mask_lo_hi, get_a_mask_lo_lo)
node get_a_mask_hi_lo = cat(get_a_mask_acc_5, get_a_mask_acc_4)
node get_a_mask_hi_hi = cat(get_a_mask_acc_7, get_a_mask_acc_6)
node get_a_mask_hi = cat(get_a_mask_hi_hi, get_a_mask_hi_lo)
node _get_a_mask_T = cat(get_a_mask_hi, get_a_mask_lo)
connect get.mask, _get_a_mask_T
invalidate get.data
connect get.corrupt, UInt<1>(0h0)
node _put_legal_T = leq(UInt<1>(0h0), s2_req.size)
node _put_legal_T_1 = leq(s2_req.size, UInt<4>(0hc))
node _put_legal_T_2 = and(_put_legal_T, _put_legal_T_1)
node _put_legal_T_3 = or(UInt<1>(0h0), _put_legal_T_2)
node _put_legal_T_4 = xor(s2_req.addr, UInt<14>(0h3000))
node _put_legal_T_5 = cvt(_put_legal_T_4)
node _put_legal_T_6 = and(_put_legal_T_5, asSInt(UInt<33>(0hca113000)))
node _put_legal_T_7 = asSInt(_put_legal_T_6)
node _put_legal_T_8 = eq(_put_legal_T_7, asSInt(UInt<1>(0h0)))
node _put_legal_T_9 = and(_put_legal_T_3, _put_legal_T_8)
node _put_legal_T_10 = leq(UInt<1>(0h0), s2_req.size)
node _put_legal_T_11 = leq(s2_req.size, UInt<3>(0h6))
node _put_legal_T_12 = and(_put_legal_T_10, _put_legal_T_11)
node _put_legal_T_13 = or(UInt<1>(0h0), _put_legal_T_12)
node _put_legal_T_14 = xor(s2_req.addr, UInt<1>(0h0))
node _put_legal_T_15 = cvt(_put_legal_T_14)
node _put_legal_T_16 = and(_put_legal_T_15, asSInt(UInt<33>(0hca112000)))
node _put_legal_T_17 = asSInt(_put_legal_T_16)
node _put_legal_T_18 = eq(_put_legal_T_17, asSInt(UInt<1>(0h0)))
node _put_legal_T_19 = xor(s2_req.addr, UInt<21>(0h100000))
node _put_legal_T_20 = cvt(_put_legal_T_19)
node _put_legal_T_21 = and(_put_legal_T_20, asSInt(UInt<33>(0hca103000)))
node _put_legal_T_22 = asSInt(_put_legal_T_21)
node _put_legal_T_23 = eq(_put_legal_T_22, asSInt(UInt<1>(0h0)))
node _put_legal_T_24 = xor(s2_req.addr, UInt<26>(0h2000000))
node _put_legal_T_25 = cvt(_put_legal_T_24)
node _put_legal_T_26 = and(_put_legal_T_25, asSInt(UInt<33>(0hca110000)))
node _put_legal_T_27 = asSInt(_put_legal_T_26)
node _put_legal_T_28 = eq(_put_legal_T_27, asSInt(UInt<1>(0h0)))
node _put_legal_T_29 = xor(s2_req.addr, UInt<28>(0h8000000))
node _put_legal_T_30 = cvt(_put_legal_T_29)
node _put_legal_T_31 = and(_put_legal_T_30, asSInt(UInt<33>(0hc8000000)))
node _put_legal_T_32 = asSInt(_put_legal_T_31)
node _put_legal_T_33 = eq(_put_legal_T_32, asSInt(UInt<1>(0h0)))
node _put_legal_T_34 = xor(s2_req.addr, UInt<32>(0h80000000))
node _put_legal_T_35 = cvt(_put_legal_T_34)
node _put_legal_T_36 = and(_put_legal_T_35, asSInt(UInt<33>(0hca110000)))
node _put_legal_T_37 = asSInt(_put_legal_T_36)
node _put_legal_T_38 = eq(_put_legal_T_37, asSInt(UInt<1>(0h0)))
node _put_legal_T_39 = or(_put_legal_T_18, _put_legal_T_23)
node _put_legal_T_40 = or(_put_legal_T_39, _put_legal_T_28)
node _put_legal_T_41 = or(_put_legal_T_40, _put_legal_T_33)
node _put_legal_T_42 = or(_put_legal_T_41, _put_legal_T_38)
node _put_legal_T_43 = and(_put_legal_T_13, _put_legal_T_42)
node _put_legal_T_44 = or(UInt<1>(0h0), UInt<1>(0h0))
node _put_legal_T_45 = xor(s2_req.addr, UInt<17>(0h10000))
node _put_legal_T_46 = cvt(_put_legal_T_45)
node _put_legal_T_47 = and(_put_legal_T_46, asSInt(UInt<33>(0hca110000)))
node _put_legal_T_48 = asSInt(_put_legal_T_47)
node _put_legal_T_49 = eq(_put_legal_T_48, asSInt(UInt<1>(0h0)))
node _put_legal_T_50 = and(_put_legal_T_44, _put_legal_T_49)
node _put_legal_T_51 = leq(UInt<1>(0h0), s2_req.size)
node _put_legal_T_52 = leq(s2_req.size, UInt<4>(0h8))
node _put_legal_T_53 = and(_put_legal_T_51, _put_legal_T_52)
node _put_legal_T_54 = or(UInt<1>(0h0), _put_legal_T_53)
node _put_legal_T_55 = xor(s2_req.addr, UInt<31>(0h40000000))
node _put_legal_T_56 = cvt(_put_legal_T_55)
node _put_legal_T_57 = and(_put_legal_T_56, asSInt(UInt<33>(0hc0000000)))
node _put_legal_T_58 = asSInt(_put_legal_T_57)
node _put_legal_T_59 = eq(_put_legal_T_58, asSInt(UInt<1>(0h0)))
node _put_legal_T_60 = and(_put_legal_T_54, _put_legal_T_59)
node _put_legal_T_61 = or(UInt<1>(0h0), _put_legal_T_9)
node _put_legal_T_62 = or(_put_legal_T_61, _put_legal_T_43)
node _put_legal_T_63 = or(_put_legal_T_62, _put_legal_T_50)
node put_legal = or(_put_legal_T_63, _put_legal_T_60)
wire put : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect put.opcode, UInt<1>(0h0)
connect put.param, UInt<1>(0h0)
connect put.size, s2_req.size
connect put.source, UInt<1>(0h0)
connect put.address, s2_req.addr
invalidate put.user.amba_prot.fetch
invalidate put.user.amba_prot.secure
invalidate put.user.amba_prot.privileged
invalidate put.user.amba_prot.writealloc
invalidate put.user.amba_prot.readalloc
invalidate put.user.amba_prot.modifiable
invalidate put.user.amba_prot.bufferable
node _put_a_mask_sizeOH_T = or(s2_req.size, UInt<3>(0h0))
node put_a_mask_sizeOH_shiftAmount = bits(_put_a_mask_sizeOH_T, 1, 0)
node _put_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), put_a_mask_sizeOH_shiftAmount)
node _put_a_mask_sizeOH_T_2 = bits(_put_a_mask_sizeOH_T_1, 2, 0)
node put_a_mask_sizeOH = or(_put_a_mask_sizeOH_T_2, UInt<1>(0h1))
node put_a_mask_sub_sub_sub_0_1 = geq(s2_req.size, UInt<2>(0h3))
node put_a_mask_sub_sub_size = bits(put_a_mask_sizeOH, 2, 2)
node put_a_mask_sub_sub_bit = bits(s2_req.addr, 2, 2)
node put_a_mask_sub_sub_nbit = eq(put_a_mask_sub_sub_bit, UInt<1>(0h0))
node put_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), put_a_mask_sub_sub_nbit)
node _put_a_mask_sub_sub_acc_T = and(put_a_mask_sub_sub_size, put_a_mask_sub_sub_0_2)
node put_a_mask_sub_sub_0_1 = or(put_a_mask_sub_sub_sub_0_1, _put_a_mask_sub_sub_acc_T)
node put_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), put_a_mask_sub_sub_bit)
node _put_a_mask_sub_sub_acc_T_1 = and(put_a_mask_sub_sub_size, put_a_mask_sub_sub_1_2)
node put_a_mask_sub_sub_1_1 = or(put_a_mask_sub_sub_sub_0_1, _put_a_mask_sub_sub_acc_T_1)
node put_a_mask_sub_size = bits(put_a_mask_sizeOH, 1, 1)
node put_a_mask_sub_bit = bits(s2_req.addr, 1, 1)
node put_a_mask_sub_nbit = eq(put_a_mask_sub_bit, UInt<1>(0h0))
node put_a_mask_sub_0_2 = and(put_a_mask_sub_sub_0_2, put_a_mask_sub_nbit)
node _put_a_mask_sub_acc_T = and(put_a_mask_sub_size, put_a_mask_sub_0_2)
node put_a_mask_sub_0_1 = or(put_a_mask_sub_sub_0_1, _put_a_mask_sub_acc_T)
node put_a_mask_sub_1_2 = and(put_a_mask_sub_sub_0_2, put_a_mask_sub_bit)
node _put_a_mask_sub_acc_T_1 = and(put_a_mask_sub_size, put_a_mask_sub_1_2)
node put_a_mask_sub_1_1 = or(put_a_mask_sub_sub_0_1, _put_a_mask_sub_acc_T_1)
node put_a_mask_sub_2_2 = and(put_a_mask_sub_sub_1_2, put_a_mask_sub_nbit)
node _put_a_mask_sub_acc_T_2 = and(put_a_mask_sub_size, put_a_mask_sub_2_2)
node put_a_mask_sub_2_1 = or(put_a_mask_sub_sub_1_1, _put_a_mask_sub_acc_T_2)
node put_a_mask_sub_3_2 = and(put_a_mask_sub_sub_1_2, put_a_mask_sub_bit)
node _put_a_mask_sub_acc_T_3 = and(put_a_mask_sub_size, put_a_mask_sub_3_2)
node put_a_mask_sub_3_1 = or(put_a_mask_sub_sub_1_1, _put_a_mask_sub_acc_T_3)
node put_a_mask_size = bits(put_a_mask_sizeOH, 0, 0)
node put_a_mask_bit = bits(s2_req.addr, 0, 0)
node put_a_mask_nbit = eq(put_a_mask_bit, UInt<1>(0h0))
node put_a_mask_eq = and(put_a_mask_sub_0_2, put_a_mask_nbit)
node _put_a_mask_acc_T = and(put_a_mask_size, put_a_mask_eq)
node put_a_mask_acc = or(put_a_mask_sub_0_1, _put_a_mask_acc_T)
node put_a_mask_eq_1 = and(put_a_mask_sub_0_2, put_a_mask_bit)
node _put_a_mask_acc_T_1 = and(put_a_mask_size, put_a_mask_eq_1)
node put_a_mask_acc_1 = or(put_a_mask_sub_0_1, _put_a_mask_acc_T_1)
node put_a_mask_eq_2 = and(put_a_mask_sub_1_2, put_a_mask_nbit)
node _put_a_mask_acc_T_2 = and(put_a_mask_size, put_a_mask_eq_2)
node put_a_mask_acc_2 = or(put_a_mask_sub_1_1, _put_a_mask_acc_T_2)
node put_a_mask_eq_3 = and(put_a_mask_sub_1_2, put_a_mask_bit)
node _put_a_mask_acc_T_3 = and(put_a_mask_size, put_a_mask_eq_3)
node put_a_mask_acc_3 = or(put_a_mask_sub_1_1, _put_a_mask_acc_T_3)
node put_a_mask_eq_4 = and(put_a_mask_sub_2_2, put_a_mask_nbit)
node _put_a_mask_acc_T_4 = and(put_a_mask_size, put_a_mask_eq_4)
node put_a_mask_acc_4 = or(put_a_mask_sub_2_1, _put_a_mask_acc_T_4)
node put_a_mask_eq_5 = and(put_a_mask_sub_2_2, put_a_mask_bit)
node _put_a_mask_acc_T_5 = and(put_a_mask_size, put_a_mask_eq_5)
node put_a_mask_acc_5 = or(put_a_mask_sub_2_1, _put_a_mask_acc_T_5)
node put_a_mask_eq_6 = and(put_a_mask_sub_3_2, put_a_mask_nbit)
node _put_a_mask_acc_T_6 = and(put_a_mask_size, put_a_mask_eq_6)
node put_a_mask_acc_6 = or(put_a_mask_sub_3_1, _put_a_mask_acc_T_6)
node put_a_mask_eq_7 = and(put_a_mask_sub_3_2, put_a_mask_bit)
node _put_a_mask_acc_T_7 = and(put_a_mask_size, put_a_mask_eq_7)
node put_a_mask_acc_7 = or(put_a_mask_sub_3_1, _put_a_mask_acc_T_7)
node put_a_mask_lo_lo = cat(put_a_mask_acc_1, put_a_mask_acc)
node put_a_mask_lo_hi = cat(put_a_mask_acc_3, put_a_mask_acc_2)
node put_a_mask_lo = cat(put_a_mask_lo_hi, put_a_mask_lo_lo)
node put_a_mask_hi_lo = cat(put_a_mask_acc_5, put_a_mask_acc_4)
node put_a_mask_hi_hi = cat(put_a_mask_acc_7, put_a_mask_acc_6)
node put_a_mask_hi = cat(put_a_mask_hi_hi, put_a_mask_hi_lo)
node _put_a_mask_T = cat(put_a_mask_hi, put_a_mask_lo)
connect put.mask, _put_a_mask_T
connect put.data, pstore1_data
connect put.corrupt, UInt<1>(0h0)
node _putpartial_legal_T = leq(UInt<1>(0h0), s2_req.size)
node _putpartial_legal_T_1 = leq(s2_req.size, UInt<4>(0hc))
node _putpartial_legal_T_2 = and(_putpartial_legal_T, _putpartial_legal_T_1)
node _putpartial_legal_T_3 = or(UInt<1>(0h0), _putpartial_legal_T_2)
node _putpartial_legal_T_4 = xor(s2_req.addr, UInt<14>(0h3000))
node _putpartial_legal_T_5 = cvt(_putpartial_legal_T_4)
node _putpartial_legal_T_6 = and(_putpartial_legal_T_5, asSInt(UInt<33>(0hca113000)))
node _putpartial_legal_T_7 = asSInt(_putpartial_legal_T_6)
node _putpartial_legal_T_8 = eq(_putpartial_legal_T_7, asSInt(UInt<1>(0h0)))
node _putpartial_legal_T_9 = and(_putpartial_legal_T_3, _putpartial_legal_T_8)
node _putpartial_legal_T_10 = leq(UInt<1>(0h0), s2_req.size)
node _putpartial_legal_T_11 = leq(s2_req.size, UInt<3>(0h6))
node _putpartial_legal_T_12 = and(_putpartial_legal_T_10, _putpartial_legal_T_11)
node _putpartial_legal_T_13 = or(UInt<1>(0h0), _putpartial_legal_T_12)
node _putpartial_legal_T_14 = xor(s2_req.addr, UInt<1>(0h0))
node _putpartial_legal_T_15 = cvt(_putpartial_legal_T_14)
node _putpartial_legal_T_16 = and(_putpartial_legal_T_15, asSInt(UInt<33>(0hca112000)))
node _putpartial_legal_T_17 = asSInt(_putpartial_legal_T_16)
node _putpartial_legal_T_18 = eq(_putpartial_legal_T_17, asSInt(UInt<1>(0h0)))
node _putpartial_legal_T_19 = xor(s2_req.addr, UInt<21>(0h100000))
node _putpartial_legal_T_20 = cvt(_putpartial_legal_T_19)
node _putpartial_legal_T_21 = and(_putpartial_legal_T_20, asSInt(UInt<33>(0hca103000)))
node _putpartial_legal_T_22 = asSInt(_putpartial_legal_T_21)
node _putpartial_legal_T_23 = eq(_putpartial_legal_T_22, asSInt(UInt<1>(0h0)))
node _putpartial_legal_T_24 = xor(s2_req.addr, UInt<26>(0h2000000))
node _putpartial_legal_T_25 = cvt(_putpartial_legal_T_24)
node _putpartial_legal_T_26 = and(_putpartial_legal_T_25, asSInt(UInt<33>(0hca110000)))
node _putpartial_legal_T_27 = asSInt(_putpartial_legal_T_26)
node _putpartial_legal_T_28 = eq(_putpartial_legal_T_27, asSInt(UInt<1>(0h0)))
node _putpartial_legal_T_29 = xor(s2_req.addr, UInt<28>(0h8000000))
node _putpartial_legal_T_30 = cvt(_putpartial_legal_T_29)
node _putpartial_legal_T_31 = and(_putpartial_legal_T_30, asSInt(UInt<33>(0hc8000000)))
node _putpartial_legal_T_32 = asSInt(_putpartial_legal_T_31)
node _putpartial_legal_T_33 = eq(_putpartial_legal_T_32, asSInt(UInt<1>(0h0)))
node _putpartial_legal_T_34 = xor(s2_req.addr, UInt<32>(0h80000000))
node _putpartial_legal_T_35 = cvt(_putpartial_legal_T_34)
node _putpartial_legal_T_36 = and(_putpartial_legal_T_35, asSInt(UInt<33>(0hca110000)))
node _putpartial_legal_T_37 = asSInt(_putpartial_legal_T_36)
node _putpartial_legal_T_38 = eq(_putpartial_legal_T_37, asSInt(UInt<1>(0h0)))
node _putpartial_legal_T_39 = or(_putpartial_legal_T_18, _putpartial_legal_T_23)
node _putpartial_legal_T_40 = or(_putpartial_legal_T_39, _putpartial_legal_T_28)
node _putpartial_legal_T_41 = or(_putpartial_legal_T_40, _putpartial_legal_T_33)
node _putpartial_legal_T_42 = or(_putpartial_legal_T_41, _putpartial_legal_T_38)
node _putpartial_legal_T_43 = and(_putpartial_legal_T_13, _putpartial_legal_T_42)
node _putpartial_legal_T_44 = or(UInt<1>(0h0), UInt<1>(0h0))
node _putpartial_legal_T_45 = xor(s2_req.addr, UInt<17>(0h10000))
node _putpartial_legal_T_46 = cvt(_putpartial_legal_T_45)
node _putpartial_legal_T_47 = and(_putpartial_legal_T_46, asSInt(UInt<33>(0hca110000)))
node _putpartial_legal_T_48 = asSInt(_putpartial_legal_T_47)
node _putpartial_legal_T_49 = eq(_putpartial_legal_T_48, asSInt(UInt<1>(0h0)))
node _putpartial_legal_T_50 = and(_putpartial_legal_T_44, _putpartial_legal_T_49)
node _putpartial_legal_T_51 = leq(UInt<1>(0h0), s2_req.size)
node _putpartial_legal_T_52 = leq(s2_req.size, UInt<4>(0h8))
node _putpartial_legal_T_53 = and(_putpartial_legal_T_51, _putpartial_legal_T_52)
node _putpartial_legal_T_54 = or(UInt<1>(0h0), _putpartial_legal_T_53)
node _putpartial_legal_T_55 = xor(s2_req.addr, UInt<31>(0h40000000))
node _putpartial_legal_T_56 = cvt(_putpartial_legal_T_55)
node _putpartial_legal_T_57 = and(_putpartial_legal_T_56, asSInt(UInt<33>(0hc0000000)))
node _putpartial_legal_T_58 = asSInt(_putpartial_legal_T_57)
node _putpartial_legal_T_59 = eq(_putpartial_legal_T_58, asSInt(UInt<1>(0h0)))
node _putpartial_legal_T_60 = and(_putpartial_legal_T_54, _putpartial_legal_T_59)
node _putpartial_legal_T_61 = or(UInt<1>(0h0), _putpartial_legal_T_9)
node _putpartial_legal_T_62 = or(_putpartial_legal_T_61, _putpartial_legal_T_43)
node _putpartial_legal_T_63 = or(_putpartial_legal_T_62, _putpartial_legal_T_50)
node putpartial_legal = or(_putpartial_legal_T_63, _putpartial_legal_T_60)
wire putpartial : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect putpartial.opcode, UInt<1>(0h1)
connect putpartial.param, UInt<1>(0h0)
connect putpartial.size, s2_req.size
connect putpartial.source, UInt<1>(0h0)
connect putpartial.address, s2_req.addr
invalidate putpartial.user.amba_prot.fetch
invalidate putpartial.user.amba_prot.secure
invalidate putpartial.user.amba_prot.privileged
invalidate putpartial.user.amba_prot.writealloc
invalidate putpartial.user.amba_prot.readalloc
invalidate putpartial.user.amba_prot.modifiable
invalidate putpartial.user.amba_prot.bufferable
connect putpartial.mask, a_mask
connect putpartial.data, pstore1_data
connect putpartial.corrupt, UInt<1>(0h0)
wire _atomics_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect _atomics_WIRE.corrupt, UInt<1>(0h0)
connect _atomics_WIRE.data, UInt<64>(0h0)
connect _atomics_WIRE.mask, UInt<8>(0h0)
connect _atomics_WIRE.user.amba_prot.fetch, UInt<1>(0h0)
connect _atomics_WIRE.user.amba_prot.secure, UInt<1>(0h0)
connect _atomics_WIRE.user.amba_prot.privileged, UInt<1>(0h0)
connect _atomics_WIRE.user.amba_prot.writealloc, UInt<1>(0h0)
connect _atomics_WIRE.user.amba_prot.readalloc, UInt<1>(0h0)
connect _atomics_WIRE.user.amba_prot.modifiable, UInt<1>(0h0)
connect _atomics_WIRE.user.amba_prot.bufferable, UInt<1>(0h0)
connect _atomics_WIRE.address, UInt<32>(0h0)
connect _atomics_WIRE.source, UInt<1>(0h0)
connect _atomics_WIRE.size, UInt<4>(0h0)
connect _atomics_WIRE.param, UInt<3>(0h0)
connect _atomics_WIRE.opcode, UInt<3>(0h0)
wire _atomics_WIRE_1 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect _atomics_WIRE_1.corrupt, _atomics_WIRE.corrupt
connect _atomics_WIRE_1.data, _atomics_WIRE.data
connect _atomics_WIRE_1.mask, _atomics_WIRE.mask
connect _atomics_WIRE_1.user, _atomics_WIRE.user
connect _atomics_WIRE_1.address, _atomics_WIRE.address
connect _atomics_WIRE_1.source, _atomics_WIRE.source
connect _atomics_WIRE_1.size, _atomics_WIRE.size
connect _atomics_WIRE_1.param, _atomics_WIRE.param
connect _atomics_WIRE_1.opcode, _atomics_WIRE.opcode
node _atomics_legal_T = leq(UInt<1>(0h0), s2_req.size)
node _atomics_legal_T_1 = leq(s2_req.size, UInt<2>(0h3))
node _atomics_legal_T_2 = and(_atomics_legal_T, _atomics_legal_T_1)
node _atomics_legal_T_3 = or(UInt<1>(0h0), _atomics_legal_T_2)
node _atomics_legal_T_4 = xor(s2_req.addr, UInt<1>(0h0))
node _atomics_legal_T_5 = cvt(_atomics_legal_T_4)
node _atomics_legal_T_6 = and(_atomics_legal_T_5, asSInt(UInt<32>(0h48110000)))
node _atomics_legal_T_7 = asSInt(_atomics_legal_T_6)
node _atomics_legal_T_8 = eq(_atomics_legal_T_7, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_9 = xor(s2_req.addr, UInt<21>(0h100000))
node _atomics_legal_T_10 = cvt(_atomics_legal_T_9)
node _atomics_legal_T_11 = and(_atomics_legal_T_10, asSInt(UInt<32>(0h48101000)))
node _atomics_legal_T_12 = asSInt(_atomics_legal_T_11)
node _atomics_legal_T_13 = eq(_atomics_legal_T_12, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_14 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_15 = cvt(_atomics_legal_T_14)
node _atomics_legal_T_16 = and(_atomics_legal_T_15, asSInt(UInt<32>(0h48000000)))
node _atomics_legal_T_17 = asSInt(_atomics_legal_T_16)
node _atomics_legal_T_18 = eq(_atomics_legal_T_17, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_19 = or(_atomics_legal_T_8, _atomics_legal_T_13)
node _atomics_legal_T_20 = or(_atomics_legal_T_19, _atomics_legal_T_18)
node _atomics_legal_T_21 = and(_atomics_legal_T_3, _atomics_legal_T_20)
node _atomics_legal_T_22 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_23 = xor(s2_req.addr, UInt<17>(0h10000))
node _atomics_legal_T_24 = cvt(_atomics_legal_T_23)
node _atomics_legal_T_25 = and(_atomics_legal_T_24, asSInt(UInt<32>(0h48110000)))
node _atomics_legal_T_26 = asSInt(_atomics_legal_T_25)
node _atomics_legal_T_27 = eq(_atomics_legal_T_26, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_28 = xor(s2_req.addr, UInt<31>(0h40000000))
node _atomics_legal_T_29 = cvt(_atomics_legal_T_28)
node _atomics_legal_T_30 = and(_atomics_legal_T_29, asSInt(UInt<32>(0h40000000)))
node _atomics_legal_T_31 = asSInt(_atomics_legal_T_30)
node _atomics_legal_T_32 = eq(_atomics_legal_T_31, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_33 = or(_atomics_legal_T_27, _atomics_legal_T_32)
node _atomics_legal_T_34 = and(_atomics_legal_T_22, _atomics_legal_T_33)
node _atomics_legal_T_35 = or(UInt<1>(0h0), _atomics_legal_T_21)
node atomics_legal = or(_atomics_legal_T_35, _atomics_legal_T_34)
wire atomics_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a.opcode, UInt<2>(0h3)
connect atomics_a.param, UInt<3>(0h3)
connect atomics_a.size, s2_req.size
connect atomics_a.source, UInt<1>(0h0)
connect atomics_a.address, s2_req.addr
invalidate atomics_a.user.amba_prot.fetch
invalidate atomics_a.user.amba_prot.secure
invalidate atomics_a.user.amba_prot.privileged
invalidate atomics_a.user.amba_prot.writealloc
invalidate atomics_a.user.amba_prot.readalloc
invalidate atomics_a.user.amba_prot.modifiable
invalidate atomics_a.user.amba_prot.bufferable
node _atomics_a_mask_sizeOH_T = or(s2_req.size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount = bits(_atomics_a_mask_sizeOH_T, 1, 0)
node _atomics_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount)
node _atomics_a_mask_sizeOH_T_2 = bits(_atomics_a_mask_sizeOH_T_1, 2, 0)
node atomics_a_mask_sizeOH = or(_atomics_a_mask_sizeOH_T_2, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1 = geq(s2_req.size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size = bits(atomics_a_mask_sizeOH, 2, 2)
node atomics_a_mask_sub_sub_bit = bits(s2_req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit = eq(atomics_a_mask_sub_sub_bit, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit)
node _atomics_a_mask_sub_sub_acc_T = and(atomics_a_mask_sub_sub_size, atomics_a_mask_sub_sub_0_2)
node atomics_a_mask_sub_sub_0_1 = or(atomics_a_mask_sub_sub_sub_0_1, _atomics_a_mask_sub_sub_acc_T)
node atomics_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit)
node _atomics_a_mask_sub_sub_acc_T_1 = and(atomics_a_mask_sub_sub_size, atomics_a_mask_sub_sub_1_2)
node atomics_a_mask_sub_sub_1_1 = or(atomics_a_mask_sub_sub_sub_0_1, _atomics_a_mask_sub_sub_acc_T_1)
node atomics_a_mask_sub_size = bits(atomics_a_mask_sizeOH, 1, 1)
node atomics_a_mask_sub_bit = bits(s2_req.addr, 1, 1)
node atomics_a_mask_sub_nbit = eq(atomics_a_mask_sub_bit, UInt<1>(0h0))
node atomics_a_mask_sub_0_2 = and(atomics_a_mask_sub_sub_0_2, atomics_a_mask_sub_nbit)
node _atomics_a_mask_sub_acc_T = and(atomics_a_mask_sub_size, atomics_a_mask_sub_0_2)
node atomics_a_mask_sub_0_1 = or(atomics_a_mask_sub_sub_0_1, _atomics_a_mask_sub_acc_T)
node atomics_a_mask_sub_1_2 = and(atomics_a_mask_sub_sub_0_2, atomics_a_mask_sub_bit)
node _atomics_a_mask_sub_acc_T_1 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_1_2)
node atomics_a_mask_sub_1_1 = or(atomics_a_mask_sub_sub_0_1, _atomics_a_mask_sub_acc_T_1)
node atomics_a_mask_sub_2_2 = and(atomics_a_mask_sub_sub_1_2, atomics_a_mask_sub_nbit)
node _atomics_a_mask_sub_acc_T_2 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_2_2)
node atomics_a_mask_sub_2_1 = or(atomics_a_mask_sub_sub_1_1, _atomics_a_mask_sub_acc_T_2)
node atomics_a_mask_sub_3_2 = and(atomics_a_mask_sub_sub_1_2, atomics_a_mask_sub_bit)
node _atomics_a_mask_sub_acc_T_3 = and(atomics_a_mask_sub_size, atomics_a_mask_sub_3_2)
node atomics_a_mask_sub_3_1 = or(atomics_a_mask_sub_sub_1_1, _atomics_a_mask_sub_acc_T_3)
node atomics_a_mask_size = bits(atomics_a_mask_sizeOH, 0, 0)
node atomics_a_mask_bit = bits(s2_req.addr, 0, 0)
node atomics_a_mask_nbit = eq(atomics_a_mask_bit, UInt<1>(0h0))
node atomics_a_mask_eq = and(atomics_a_mask_sub_0_2, atomics_a_mask_nbit)
node _atomics_a_mask_acc_T = and(atomics_a_mask_size, atomics_a_mask_eq)
node atomics_a_mask_acc = or(atomics_a_mask_sub_0_1, _atomics_a_mask_acc_T)
node atomics_a_mask_eq_1 = and(atomics_a_mask_sub_0_2, atomics_a_mask_bit)
node _atomics_a_mask_acc_T_1 = and(atomics_a_mask_size, atomics_a_mask_eq_1)
node atomics_a_mask_acc_1 = or(atomics_a_mask_sub_0_1, _atomics_a_mask_acc_T_1)
node atomics_a_mask_eq_2 = and(atomics_a_mask_sub_1_2, atomics_a_mask_nbit)
node _atomics_a_mask_acc_T_2 = and(atomics_a_mask_size, atomics_a_mask_eq_2)
node atomics_a_mask_acc_2 = or(atomics_a_mask_sub_1_1, _atomics_a_mask_acc_T_2)
node atomics_a_mask_eq_3 = and(atomics_a_mask_sub_1_2, atomics_a_mask_bit)
node _atomics_a_mask_acc_T_3 = and(atomics_a_mask_size, atomics_a_mask_eq_3)
node atomics_a_mask_acc_3 = or(atomics_a_mask_sub_1_1, _atomics_a_mask_acc_T_3)
node atomics_a_mask_eq_4 = and(atomics_a_mask_sub_2_2, atomics_a_mask_nbit)
node _atomics_a_mask_acc_T_4 = and(atomics_a_mask_size, atomics_a_mask_eq_4)
node atomics_a_mask_acc_4 = or(atomics_a_mask_sub_2_1, _atomics_a_mask_acc_T_4)
node atomics_a_mask_eq_5 = and(atomics_a_mask_sub_2_2, atomics_a_mask_bit)
node _atomics_a_mask_acc_T_5 = and(atomics_a_mask_size, atomics_a_mask_eq_5)
node atomics_a_mask_acc_5 = or(atomics_a_mask_sub_2_1, _atomics_a_mask_acc_T_5)
node atomics_a_mask_eq_6 = and(atomics_a_mask_sub_3_2, atomics_a_mask_nbit)
node _atomics_a_mask_acc_T_6 = and(atomics_a_mask_size, atomics_a_mask_eq_6)
node atomics_a_mask_acc_6 = or(atomics_a_mask_sub_3_1, _atomics_a_mask_acc_T_6)
node atomics_a_mask_eq_7 = and(atomics_a_mask_sub_3_2, atomics_a_mask_bit)
node _atomics_a_mask_acc_T_7 = and(atomics_a_mask_size, atomics_a_mask_eq_7)
node atomics_a_mask_acc_7 = or(atomics_a_mask_sub_3_1, _atomics_a_mask_acc_T_7)
node atomics_a_mask_lo_lo = cat(atomics_a_mask_acc_1, atomics_a_mask_acc)
node atomics_a_mask_lo_hi = cat(atomics_a_mask_acc_3, atomics_a_mask_acc_2)
node atomics_a_mask_lo = cat(atomics_a_mask_lo_hi, atomics_a_mask_lo_lo)
node atomics_a_mask_hi_lo = cat(atomics_a_mask_acc_5, atomics_a_mask_acc_4)
node atomics_a_mask_hi_hi = cat(atomics_a_mask_acc_7, atomics_a_mask_acc_6)
node atomics_a_mask_hi = cat(atomics_a_mask_hi_hi, atomics_a_mask_hi_lo)
node _atomics_a_mask_T = cat(atomics_a_mask_hi, atomics_a_mask_lo)
connect atomics_a.mask, _atomics_a_mask_T
connect atomics_a.data, pstore1_data
connect atomics_a.corrupt, UInt<1>(0h0)
node _atomics_legal_T_36 = leq(UInt<1>(0h0), s2_req.size)
node _atomics_legal_T_37 = leq(s2_req.size, UInt<2>(0h3))
node _atomics_legal_T_38 = and(_atomics_legal_T_36, _atomics_legal_T_37)
node _atomics_legal_T_39 = or(UInt<1>(0h0), _atomics_legal_T_38)
node _atomics_legal_T_40 = xor(s2_req.addr, UInt<1>(0h0))
node _atomics_legal_T_41 = cvt(_atomics_legal_T_40)
node _atomics_legal_T_42 = and(_atomics_legal_T_41, asSInt(UInt<32>(0h48110000)))
node _atomics_legal_T_43 = asSInt(_atomics_legal_T_42)
node _atomics_legal_T_44 = eq(_atomics_legal_T_43, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_45 = xor(s2_req.addr, UInt<21>(0h100000))
node _atomics_legal_T_46 = cvt(_atomics_legal_T_45)
node _atomics_legal_T_47 = and(_atomics_legal_T_46, asSInt(UInt<32>(0h48101000)))
node _atomics_legal_T_48 = asSInt(_atomics_legal_T_47)
node _atomics_legal_T_49 = eq(_atomics_legal_T_48, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_50 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_51 = cvt(_atomics_legal_T_50)
node _atomics_legal_T_52 = and(_atomics_legal_T_51, asSInt(UInt<32>(0h48000000)))
node _atomics_legal_T_53 = asSInt(_atomics_legal_T_52)
node _atomics_legal_T_54 = eq(_atomics_legal_T_53, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_55 = or(_atomics_legal_T_44, _atomics_legal_T_49)
node _atomics_legal_T_56 = or(_atomics_legal_T_55, _atomics_legal_T_54)
node _atomics_legal_T_57 = and(_atomics_legal_T_39, _atomics_legal_T_56)
node _atomics_legal_T_58 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_59 = xor(s2_req.addr, UInt<17>(0h10000))
node _atomics_legal_T_60 = cvt(_atomics_legal_T_59)
node _atomics_legal_T_61 = and(_atomics_legal_T_60, asSInt(UInt<32>(0h48110000)))
node _atomics_legal_T_62 = asSInt(_atomics_legal_T_61)
node _atomics_legal_T_63 = eq(_atomics_legal_T_62, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_64 = xor(s2_req.addr, UInt<31>(0h40000000))
node _atomics_legal_T_65 = cvt(_atomics_legal_T_64)
node _atomics_legal_T_66 = and(_atomics_legal_T_65, asSInt(UInt<32>(0h40000000)))
node _atomics_legal_T_67 = asSInt(_atomics_legal_T_66)
node _atomics_legal_T_68 = eq(_atomics_legal_T_67, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_69 = or(_atomics_legal_T_63, _atomics_legal_T_68)
node _atomics_legal_T_70 = and(_atomics_legal_T_58, _atomics_legal_T_69)
node _atomics_legal_T_71 = or(UInt<1>(0h0), _atomics_legal_T_57)
node atomics_legal_1 = or(_atomics_legal_T_71, _atomics_legal_T_70)
wire atomics_a_1 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_1.opcode, UInt<2>(0h3)
connect atomics_a_1.param, UInt<3>(0h0)
connect atomics_a_1.size, s2_req.size
connect atomics_a_1.source, UInt<1>(0h0)
connect atomics_a_1.address, s2_req.addr
invalidate atomics_a_1.user.amba_prot.fetch
invalidate atomics_a_1.user.amba_prot.secure
invalidate atomics_a_1.user.amba_prot.privileged
invalidate atomics_a_1.user.amba_prot.writealloc
invalidate atomics_a_1.user.amba_prot.readalloc
invalidate atomics_a_1.user.amba_prot.modifiable
invalidate atomics_a_1.user.amba_prot.bufferable
node _atomics_a_mask_sizeOH_T_3 = or(s2_req.size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_1 = bits(_atomics_a_mask_sizeOH_T_3, 1, 0)
node _atomics_a_mask_sizeOH_T_4 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_1)
node _atomics_a_mask_sizeOH_T_5 = bits(_atomics_a_mask_sizeOH_T_4, 2, 0)
node atomics_a_mask_sizeOH_1 = or(_atomics_a_mask_sizeOH_T_5, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_1 = geq(s2_req.size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_1 = bits(atomics_a_mask_sizeOH_1, 2, 2)
node atomics_a_mask_sub_sub_bit_1 = bits(s2_req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_1 = eq(atomics_a_mask_sub_sub_bit_1, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_1 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_1)
node _atomics_a_mask_sub_sub_acc_T_2 = and(atomics_a_mask_sub_sub_size_1, atomics_a_mask_sub_sub_0_2_1)
node atomics_a_mask_sub_sub_0_1_1 = or(atomics_a_mask_sub_sub_sub_0_1_1, _atomics_a_mask_sub_sub_acc_T_2)
node atomics_a_mask_sub_sub_1_2_1 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_1)
node _atomics_a_mask_sub_sub_acc_T_3 = and(atomics_a_mask_sub_sub_size_1, atomics_a_mask_sub_sub_1_2_1)
node atomics_a_mask_sub_sub_1_1_1 = or(atomics_a_mask_sub_sub_sub_0_1_1, _atomics_a_mask_sub_sub_acc_T_3)
node atomics_a_mask_sub_size_1 = bits(atomics_a_mask_sizeOH_1, 1, 1)
node atomics_a_mask_sub_bit_1 = bits(s2_req.addr, 1, 1)
node atomics_a_mask_sub_nbit_1 = eq(atomics_a_mask_sub_bit_1, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_1 = and(atomics_a_mask_sub_sub_0_2_1, atomics_a_mask_sub_nbit_1)
node _atomics_a_mask_sub_acc_T_4 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_0_2_1)
node atomics_a_mask_sub_0_1_1 = or(atomics_a_mask_sub_sub_0_1_1, _atomics_a_mask_sub_acc_T_4)
node atomics_a_mask_sub_1_2_1 = and(atomics_a_mask_sub_sub_0_2_1, atomics_a_mask_sub_bit_1)
node _atomics_a_mask_sub_acc_T_5 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_1_2_1)
node atomics_a_mask_sub_1_1_1 = or(atomics_a_mask_sub_sub_0_1_1, _atomics_a_mask_sub_acc_T_5)
node atomics_a_mask_sub_2_2_1 = and(atomics_a_mask_sub_sub_1_2_1, atomics_a_mask_sub_nbit_1)
node _atomics_a_mask_sub_acc_T_6 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_2_2_1)
node atomics_a_mask_sub_2_1_1 = or(atomics_a_mask_sub_sub_1_1_1, _atomics_a_mask_sub_acc_T_6)
node atomics_a_mask_sub_3_2_1 = and(atomics_a_mask_sub_sub_1_2_1, atomics_a_mask_sub_bit_1)
node _atomics_a_mask_sub_acc_T_7 = and(atomics_a_mask_sub_size_1, atomics_a_mask_sub_3_2_1)
node atomics_a_mask_sub_3_1_1 = or(atomics_a_mask_sub_sub_1_1_1, _atomics_a_mask_sub_acc_T_7)
node atomics_a_mask_size_1 = bits(atomics_a_mask_sizeOH_1, 0, 0)
node atomics_a_mask_bit_1 = bits(s2_req.addr, 0, 0)
node atomics_a_mask_nbit_1 = eq(atomics_a_mask_bit_1, UInt<1>(0h0))
node atomics_a_mask_eq_8 = and(atomics_a_mask_sub_0_2_1, atomics_a_mask_nbit_1)
node _atomics_a_mask_acc_T_8 = and(atomics_a_mask_size_1, atomics_a_mask_eq_8)
node atomics_a_mask_acc_8 = or(atomics_a_mask_sub_0_1_1, _atomics_a_mask_acc_T_8)
node atomics_a_mask_eq_9 = and(atomics_a_mask_sub_0_2_1, atomics_a_mask_bit_1)
node _atomics_a_mask_acc_T_9 = and(atomics_a_mask_size_1, atomics_a_mask_eq_9)
node atomics_a_mask_acc_9 = or(atomics_a_mask_sub_0_1_1, _atomics_a_mask_acc_T_9)
node atomics_a_mask_eq_10 = and(atomics_a_mask_sub_1_2_1, atomics_a_mask_nbit_1)
node _atomics_a_mask_acc_T_10 = and(atomics_a_mask_size_1, atomics_a_mask_eq_10)
node atomics_a_mask_acc_10 = or(atomics_a_mask_sub_1_1_1, _atomics_a_mask_acc_T_10)
node atomics_a_mask_eq_11 = and(atomics_a_mask_sub_1_2_1, atomics_a_mask_bit_1)
node _atomics_a_mask_acc_T_11 = and(atomics_a_mask_size_1, atomics_a_mask_eq_11)
node atomics_a_mask_acc_11 = or(atomics_a_mask_sub_1_1_1, _atomics_a_mask_acc_T_11)
node atomics_a_mask_eq_12 = and(atomics_a_mask_sub_2_2_1, atomics_a_mask_nbit_1)
node _atomics_a_mask_acc_T_12 = and(atomics_a_mask_size_1, atomics_a_mask_eq_12)
node atomics_a_mask_acc_12 = or(atomics_a_mask_sub_2_1_1, _atomics_a_mask_acc_T_12)
node atomics_a_mask_eq_13 = and(atomics_a_mask_sub_2_2_1, atomics_a_mask_bit_1)
node _atomics_a_mask_acc_T_13 = and(atomics_a_mask_size_1, atomics_a_mask_eq_13)
node atomics_a_mask_acc_13 = or(atomics_a_mask_sub_2_1_1, _atomics_a_mask_acc_T_13)
node atomics_a_mask_eq_14 = and(atomics_a_mask_sub_3_2_1, atomics_a_mask_nbit_1)
node _atomics_a_mask_acc_T_14 = and(atomics_a_mask_size_1, atomics_a_mask_eq_14)
node atomics_a_mask_acc_14 = or(atomics_a_mask_sub_3_1_1, _atomics_a_mask_acc_T_14)
node atomics_a_mask_eq_15 = and(atomics_a_mask_sub_3_2_1, atomics_a_mask_bit_1)
node _atomics_a_mask_acc_T_15 = and(atomics_a_mask_size_1, atomics_a_mask_eq_15)
node atomics_a_mask_acc_15 = or(atomics_a_mask_sub_3_1_1, _atomics_a_mask_acc_T_15)
node atomics_a_mask_lo_lo_1 = cat(atomics_a_mask_acc_9, atomics_a_mask_acc_8)
node atomics_a_mask_lo_hi_1 = cat(atomics_a_mask_acc_11, atomics_a_mask_acc_10)
node atomics_a_mask_lo_1 = cat(atomics_a_mask_lo_hi_1, atomics_a_mask_lo_lo_1)
node atomics_a_mask_hi_lo_1 = cat(atomics_a_mask_acc_13, atomics_a_mask_acc_12)
node atomics_a_mask_hi_hi_1 = cat(atomics_a_mask_acc_15, atomics_a_mask_acc_14)
node atomics_a_mask_hi_1 = cat(atomics_a_mask_hi_hi_1, atomics_a_mask_hi_lo_1)
node _atomics_a_mask_T_1 = cat(atomics_a_mask_hi_1, atomics_a_mask_lo_1)
connect atomics_a_1.mask, _atomics_a_mask_T_1
connect atomics_a_1.data, pstore1_data
connect atomics_a_1.corrupt, UInt<1>(0h0)
node _atomics_legal_T_72 = leq(UInt<1>(0h0), s2_req.size)
node _atomics_legal_T_73 = leq(s2_req.size, UInt<2>(0h3))
node _atomics_legal_T_74 = and(_atomics_legal_T_72, _atomics_legal_T_73)
node _atomics_legal_T_75 = or(UInt<1>(0h0), _atomics_legal_T_74)
node _atomics_legal_T_76 = xor(s2_req.addr, UInt<1>(0h0))
node _atomics_legal_T_77 = cvt(_atomics_legal_T_76)
node _atomics_legal_T_78 = and(_atomics_legal_T_77, asSInt(UInt<32>(0h48110000)))
node _atomics_legal_T_79 = asSInt(_atomics_legal_T_78)
node _atomics_legal_T_80 = eq(_atomics_legal_T_79, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_81 = xor(s2_req.addr, UInt<21>(0h100000))
node _atomics_legal_T_82 = cvt(_atomics_legal_T_81)
node _atomics_legal_T_83 = and(_atomics_legal_T_82, asSInt(UInt<32>(0h48101000)))
node _atomics_legal_T_84 = asSInt(_atomics_legal_T_83)
node _atomics_legal_T_85 = eq(_atomics_legal_T_84, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_86 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_87 = cvt(_atomics_legal_T_86)
node _atomics_legal_T_88 = and(_atomics_legal_T_87, asSInt(UInt<32>(0h48000000)))
node _atomics_legal_T_89 = asSInt(_atomics_legal_T_88)
node _atomics_legal_T_90 = eq(_atomics_legal_T_89, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_91 = or(_atomics_legal_T_80, _atomics_legal_T_85)
node _atomics_legal_T_92 = or(_atomics_legal_T_91, _atomics_legal_T_90)
node _atomics_legal_T_93 = and(_atomics_legal_T_75, _atomics_legal_T_92)
node _atomics_legal_T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_95 = xor(s2_req.addr, UInt<17>(0h10000))
node _atomics_legal_T_96 = cvt(_atomics_legal_T_95)
node _atomics_legal_T_97 = and(_atomics_legal_T_96, asSInt(UInt<32>(0h48110000)))
node _atomics_legal_T_98 = asSInt(_atomics_legal_T_97)
node _atomics_legal_T_99 = eq(_atomics_legal_T_98, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_100 = xor(s2_req.addr, UInt<31>(0h40000000))
node _atomics_legal_T_101 = cvt(_atomics_legal_T_100)
node _atomics_legal_T_102 = and(_atomics_legal_T_101, asSInt(UInt<32>(0h40000000)))
node _atomics_legal_T_103 = asSInt(_atomics_legal_T_102)
node _atomics_legal_T_104 = eq(_atomics_legal_T_103, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_105 = or(_atomics_legal_T_99, _atomics_legal_T_104)
node _atomics_legal_T_106 = and(_atomics_legal_T_94, _atomics_legal_T_105)
node _atomics_legal_T_107 = or(UInt<1>(0h0), _atomics_legal_T_93)
node atomics_legal_2 = or(_atomics_legal_T_107, _atomics_legal_T_106)
wire atomics_a_2 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_2.opcode, UInt<2>(0h3)
connect atomics_a_2.param, UInt<3>(0h1)
connect atomics_a_2.size, s2_req.size
connect atomics_a_2.source, UInt<1>(0h0)
connect atomics_a_2.address, s2_req.addr
invalidate atomics_a_2.user.amba_prot.fetch
invalidate atomics_a_2.user.amba_prot.secure
invalidate atomics_a_2.user.amba_prot.privileged
invalidate atomics_a_2.user.amba_prot.writealloc
invalidate atomics_a_2.user.amba_prot.readalloc
invalidate atomics_a_2.user.amba_prot.modifiable
invalidate atomics_a_2.user.amba_prot.bufferable
node _atomics_a_mask_sizeOH_T_6 = or(s2_req.size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_2 = bits(_atomics_a_mask_sizeOH_T_6, 1, 0)
node _atomics_a_mask_sizeOH_T_7 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_2)
node _atomics_a_mask_sizeOH_T_8 = bits(_atomics_a_mask_sizeOH_T_7, 2, 0)
node atomics_a_mask_sizeOH_2 = or(_atomics_a_mask_sizeOH_T_8, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_2 = geq(s2_req.size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_2 = bits(atomics_a_mask_sizeOH_2, 2, 2)
node atomics_a_mask_sub_sub_bit_2 = bits(s2_req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_2 = eq(atomics_a_mask_sub_sub_bit_2, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_2)
node _atomics_a_mask_sub_sub_acc_T_4 = and(atomics_a_mask_sub_sub_size_2, atomics_a_mask_sub_sub_0_2_2)
node atomics_a_mask_sub_sub_0_1_2 = or(atomics_a_mask_sub_sub_sub_0_1_2, _atomics_a_mask_sub_sub_acc_T_4)
node atomics_a_mask_sub_sub_1_2_2 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_2)
node _atomics_a_mask_sub_sub_acc_T_5 = and(atomics_a_mask_sub_sub_size_2, atomics_a_mask_sub_sub_1_2_2)
node atomics_a_mask_sub_sub_1_1_2 = or(atomics_a_mask_sub_sub_sub_0_1_2, _atomics_a_mask_sub_sub_acc_T_5)
node atomics_a_mask_sub_size_2 = bits(atomics_a_mask_sizeOH_2, 1, 1)
node atomics_a_mask_sub_bit_2 = bits(s2_req.addr, 1, 1)
node atomics_a_mask_sub_nbit_2 = eq(atomics_a_mask_sub_bit_2, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_2 = and(atomics_a_mask_sub_sub_0_2_2, atomics_a_mask_sub_nbit_2)
node _atomics_a_mask_sub_acc_T_8 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_0_2_2)
node atomics_a_mask_sub_0_1_2 = or(atomics_a_mask_sub_sub_0_1_2, _atomics_a_mask_sub_acc_T_8)
node atomics_a_mask_sub_1_2_2 = and(atomics_a_mask_sub_sub_0_2_2, atomics_a_mask_sub_bit_2)
node _atomics_a_mask_sub_acc_T_9 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_1_2_2)
node atomics_a_mask_sub_1_1_2 = or(atomics_a_mask_sub_sub_0_1_2, _atomics_a_mask_sub_acc_T_9)
node atomics_a_mask_sub_2_2_2 = and(atomics_a_mask_sub_sub_1_2_2, atomics_a_mask_sub_nbit_2)
node _atomics_a_mask_sub_acc_T_10 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_2_2_2)
node atomics_a_mask_sub_2_1_2 = or(atomics_a_mask_sub_sub_1_1_2, _atomics_a_mask_sub_acc_T_10)
node atomics_a_mask_sub_3_2_2 = and(atomics_a_mask_sub_sub_1_2_2, atomics_a_mask_sub_bit_2)
node _atomics_a_mask_sub_acc_T_11 = and(atomics_a_mask_sub_size_2, atomics_a_mask_sub_3_2_2)
node atomics_a_mask_sub_3_1_2 = or(atomics_a_mask_sub_sub_1_1_2, _atomics_a_mask_sub_acc_T_11)
node atomics_a_mask_size_2 = bits(atomics_a_mask_sizeOH_2, 0, 0)
node atomics_a_mask_bit_2 = bits(s2_req.addr, 0, 0)
node atomics_a_mask_nbit_2 = eq(atomics_a_mask_bit_2, UInt<1>(0h0))
node atomics_a_mask_eq_16 = and(atomics_a_mask_sub_0_2_2, atomics_a_mask_nbit_2)
node _atomics_a_mask_acc_T_16 = and(atomics_a_mask_size_2, atomics_a_mask_eq_16)
node atomics_a_mask_acc_16 = or(atomics_a_mask_sub_0_1_2, _atomics_a_mask_acc_T_16)
node atomics_a_mask_eq_17 = and(atomics_a_mask_sub_0_2_2, atomics_a_mask_bit_2)
node _atomics_a_mask_acc_T_17 = and(atomics_a_mask_size_2, atomics_a_mask_eq_17)
node atomics_a_mask_acc_17 = or(atomics_a_mask_sub_0_1_2, _atomics_a_mask_acc_T_17)
node atomics_a_mask_eq_18 = and(atomics_a_mask_sub_1_2_2, atomics_a_mask_nbit_2)
node _atomics_a_mask_acc_T_18 = and(atomics_a_mask_size_2, atomics_a_mask_eq_18)
node atomics_a_mask_acc_18 = or(atomics_a_mask_sub_1_1_2, _atomics_a_mask_acc_T_18)
node atomics_a_mask_eq_19 = and(atomics_a_mask_sub_1_2_2, atomics_a_mask_bit_2)
node _atomics_a_mask_acc_T_19 = and(atomics_a_mask_size_2, atomics_a_mask_eq_19)
node atomics_a_mask_acc_19 = or(atomics_a_mask_sub_1_1_2, _atomics_a_mask_acc_T_19)
node atomics_a_mask_eq_20 = and(atomics_a_mask_sub_2_2_2, atomics_a_mask_nbit_2)
node _atomics_a_mask_acc_T_20 = and(atomics_a_mask_size_2, atomics_a_mask_eq_20)
node atomics_a_mask_acc_20 = or(atomics_a_mask_sub_2_1_2, _atomics_a_mask_acc_T_20)
node atomics_a_mask_eq_21 = and(atomics_a_mask_sub_2_2_2, atomics_a_mask_bit_2)
node _atomics_a_mask_acc_T_21 = and(atomics_a_mask_size_2, atomics_a_mask_eq_21)
node atomics_a_mask_acc_21 = or(atomics_a_mask_sub_2_1_2, _atomics_a_mask_acc_T_21)
node atomics_a_mask_eq_22 = and(atomics_a_mask_sub_3_2_2, atomics_a_mask_nbit_2)
node _atomics_a_mask_acc_T_22 = and(atomics_a_mask_size_2, atomics_a_mask_eq_22)
node atomics_a_mask_acc_22 = or(atomics_a_mask_sub_3_1_2, _atomics_a_mask_acc_T_22)
node atomics_a_mask_eq_23 = and(atomics_a_mask_sub_3_2_2, atomics_a_mask_bit_2)
node _atomics_a_mask_acc_T_23 = and(atomics_a_mask_size_2, atomics_a_mask_eq_23)
node atomics_a_mask_acc_23 = or(atomics_a_mask_sub_3_1_2, _atomics_a_mask_acc_T_23)
node atomics_a_mask_lo_lo_2 = cat(atomics_a_mask_acc_17, atomics_a_mask_acc_16)
node atomics_a_mask_lo_hi_2 = cat(atomics_a_mask_acc_19, atomics_a_mask_acc_18)
node atomics_a_mask_lo_2 = cat(atomics_a_mask_lo_hi_2, atomics_a_mask_lo_lo_2)
node atomics_a_mask_hi_lo_2 = cat(atomics_a_mask_acc_21, atomics_a_mask_acc_20)
node atomics_a_mask_hi_hi_2 = cat(atomics_a_mask_acc_23, atomics_a_mask_acc_22)
node atomics_a_mask_hi_2 = cat(atomics_a_mask_hi_hi_2, atomics_a_mask_hi_lo_2)
node _atomics_a_mask_T_2 = cat(atomics_a_mask_hi_2, atomics_a_mask_lo_2)
connect atomics_a_2.mask, _atomics_a_mask_T_2
connect atomics_a_2.data, pstore1_data
connect atomics_a_2.corrupt, UInt<1>(0h0)
node _atomics_legal_T_108 = leq(UInt<1>(0h0), s2_req.size)
node _atomics_legal_T_109 = leq(s2_req.size, UInt<2>(0h3))
node _atomics_legal_T_110 = and(_atomics_legal_T_108, _atomics_legal_T_109)
node _atomics_legal_T_111 = or(UInt<1>(0h0), _atomics_legal_T_110)
node _atomics_legal_T_112 = xor(s2_req.addr, UInt<1>(0h0))
node _atomics_legal_T_113 = cvt(_atomics_legal_T_112)
node _atomics_legal_T_114 = and(_atomics_legal_T_113, asSInt(UInt<32>(0h48110000)))
node _atomics_legal_T_115 = asSInt(_atomics_legal_T_114)
node _atomics_legal_T_116 = eq(_atomics_legal_T_115, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_117 = xor(s2_req.addr, UInt<21>(0h100000))
node _atomics_legal_T_118 = cvt(_atomics_legal_T_117)
node _atomics_legal_T_119 = and(_atomics_legal_T_118, asSInt(UInt<32>(0h48101000)))
node _atomics_legal_T_120 = asSInt(_atomics_legal_T_119)
node _atomics_legal_T_121 = eq(_atomics_legal_T_120, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_122 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_123 = cvt(_atomics_legal_T_122)
node _atomics_legal_T_124 = and(_atomics_legal_T_123, asSInt(UInt<32>(0h48000000)))
node _atomics_legal_T_125 = asSInt(_atomics_legal_T_124)
node _atomics_legal_T_126 = eq(_atomics_legal_T_125, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_127 = or(_atomics_legal_T_116, _atomics_legal_T_121)
node _atomics_legal_T_128 = or(_atomics_legal_T_127, _atomics_legal_T_126)
node _atomics_legal_T_129 = and(_atomics_legal_T_111, _atomics_legal_T_128)
node _atomics_legal_T_130 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_131 = xor(s2_req.addr, UInt<17>(0h10000))
node _atomics_legal_T_132 = cvt(_atomics_legal_T_131)
node _atomics_legal_T_133 = and(_atomics_legal_T_132, asSInt(UInt<32>(0h48110000)))
node _atomics_legal_T_134 = asSInt(_atomics_legal_T_133)
node _atomics_legal_T_135 = eq(_atomics_legal_T_134, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_136 = xor(s2_req.addr, UInt<31>(0h40000000))
node _atomics_legal_T_137 = cvt(_atomics_legal_T_136)
node _atomics_legal_T_138 = and(_atomics_legal_T_137, asSInt(UInt<32>(0h40000000)))
node _atomics_legal_T_139 = asSInt(_atomics_legal_T_138)
node _atomics_legal_T_140 = eq(_atomics_legal_T_139, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_141 = or(_atomics_legal_T_135, _atomics_legal_T_140)
node _atomics_legal_T_142 = and(_atomics_legal_T_130, _atomics_legal_T_141)
node _atomics_legal_T_143 = or(UInt<1>(0h0), _atomics_legal_T_129)
node atomics_legal_3 = or(_atomics_legal_T_143, _atomics_legal_T_142)
wire atomics_a_3 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_3.opcode, UInt<2>(0h3)
connect atomics_a_3.param, UInt<3>(0h2)
connect atomics_a_3.size, s2_req.size
connect atomics_a_3.source, UInt<1>(0h0)
connect atomics_a_3.address, s2_req.addr
invalidate atomics_a_3.user.amba_prot.fetch
invalidate atomics_a_3.user.amba_prot.secure
invalidate atomics_a_3.user.amba_prot.privileged
invalidate atomics_a_3.user.amba_prot.writealloc
invalidate atomics_a_3.user.amba_prot.readalloc
invalidate atomics_a_3.user.amba_prot.modifiable
invalidate atomics_a_3.user.amba_prot.bufferable
node _atomics_a_mask_sizeOH_T_9 = or(s2_req.size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_3 = bits(_atomics_a_mask_sizeOH_T_9, 1, 0)
node _atomics_a_mask_sizeOH_T_10 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_3)
node _atomics_a_mask_sizeOH_T_11 = bits(_atomics_a_mask_sizeOH_T_10, 2, 0)
node atomics_a_mask_sizeOH_3 = or(_atomics_a_mask_sizeOH_T_11, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_3 = geq(s2_req.size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_3 = bits(atomics_a_mask_sizeOH_3, 2, 2)
node atomics_a_mask_sub_sub_bit_3 = bits(s2_req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_3 = eq(atomics_a_mask_sub_sub_bit_3, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_3 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_3)
node _atomics_a_mask_sub_sub_acc_T_6 = and(atomics_a_mask_sub_sub_size_3, atomics_a_mask_sub_sub_0_2_3)
node atomics_a_mask_sub_sub_0_1_3 = or(atomics_a_mask_sub_sub_sub_0_1_3, _atomics_a_mask_sub_sub_acc_T_6)
node atomics_a_mask_sub_sub_1_2_3 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_3)
node _atomics_a_mask_sub_sub_acc_T_7 = and(atomics_a_mask_sub_sub_size_3, atomics_a_mask_sub_sub_1_2_3)
node atomics_a_mask_sub_sub_1_1_3 = or(atomics_a_mask_sub_sub_sub_0_1_3, _atomics_a_mask_sub_sub_acc_T_7)
node atomics_a_mask_sub_size_3 = bits(atomics_a_mask_sizeOH_3, 1, 1)
node atomics_a_mask_sub_bit_3 = bits(s2_req.addr, 1, 1)
node atomics_a_mask_sub_nbit_3 = eq(atomics_a_mask_sub_bit_3, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_3 = and(atomics_a_mask_sub_sub_0_2_3, atomics_a_mask_sub_nbit_3)
node _atomics_a_mask_sub_acc_T_12 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_0_2_3)
node atomics_a_mask_sub_0_1_3 = or(atomics_a_mask_sub_sub_0_1_3, _atomics_a_mask_sub_acc_T_12)
node atomics_a_mask_sub_1_2_3 = and(atomics_a_mask_sub_sub_0_2_3, atomics_a_mask_sub_bit_3)
node _atomics_a_mask_sub_acc_T_13 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_1_2_3)
node atomics_a_mask_sub_1_1_3 = or(atomics_a_mask_sub_sub_0_1_3, _atomics_a_mask_sub_acc_T_13)
node atomics_a_mask_sub_2_2_3 = and(atomics_a_mask_sub_sub_1_2_3, atomics_a_mask_sub_nbit_3)
node _atomics_a_mask_sub_acc_T_14 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_2_2_3)
node atomics_a_mask_sub_2_1_3 = or(atomics_a_mask_sub_sub_1_1_3, _atomics_a_mask_sub_acc_T_14)
node atomics_a_mask_sub_3_2_3 = and(atomics_a_mask_sub_sub_1_2_3, atomics_a_mask_sub_bit_3)
node _atomics_a_mask_sub_acc_T_15 = and(atomics_a_mask_sub_size_3, atomics_a_mask_sub_3_2_3)
node atomics_a_mask_sub_3_1_3 = or(atomics_a_mask_sub_sub_1_1_3, _atomics_a_mask_sub_acc_T_15)
node atomics_a_mask_size_3 = bits(atomics_a_mask_sizeOH_3, 0, 0)
node atomics_a_mask_bit_3 = bits(s2_req.addr, 0, 0)
node atomics_a_mask_nbit_3 = eq(atomics_a_mask_bit_3, UInt<1>(0h0))
node atomics_a_mask_eq_24 = and(atomics_a_mask_sub_0_2_3, atomics_a_mask_nbit_3)
node _atomics_a_mask_acc_T_24 = and(atomics_a_mask_size_3, atomics_a_mask_eq_24)
node atomics_a_mask_acc_24 = or(atomics_a_mask_sub_0_1_3, _atomics_a_mask_acc_T_24)
node atomics_a_mask_eq_25 = and(atomics_a_mask_sub_0_2_3, atomics_a_mask_bit_3)
node _atomics_a_mask_acc_T_25 = and(atomics_a_mask_size_3, atomics_a_mask_eq_25)
node atomics_a_mask_acc_25 = or(atomics_a_mask_sub_0_1_3, _atomics_a_mask_acc_T_25)
node atomics_a_mask_eq_26 = and(atomics_a_mask_sub_1_2_3, atomics_a_mask_nbit_3)
node _atomics_a_mask_acc_T_26 = and(atomics_a_mask_size_3, atomics_a_mask_eq_26)
node atomics_a_mask_acc_26 = or(atomics_a_mask_sub_1_1_3, _atomics_a_mask_acc_T_26)
node atomics_a_mask_eq_27 = and(atomics_a_mask_sub_1_2_3, atomics_a_mask_bit_3)
node _atomics_a_mask_acc_T_27 = and(atomics_a_mask_size_3, atomics_a_mask_eq_27)
node atomics_a_mask_acc_27 = or(atomics_a_mask_sub_1_1_3, _atomics_a_mask_acc_T_27)
node atomics_a_mask_eq_28 = and(atomics_a_mask_sub_2_2_3, atomics_a_mask_nbit_3)
node _atomics_a_mask_acc_T_28 = and(atomics_a_mask_size_3, atomics_a_mask_eq_28)
node atomics_a_mask_acc_28 = or(atomics_a_mask_sub_2_1_3, _atomics_a_mask_acc_T_28)
node atomics_a_mask_eq_29 = and(atomics_a_mask_sub_2_2_3, atomics_a_mask_bit_3)
node _atomics_a_mask_acc_T_29 = and(atomics_a_mask_size_3, atomics_a_mask_eq_29)
node atomics_a_mask_acc_29 = or(atomics_a_mask_sub_2_1_3, _atomics_a_mask_acc_T_29)
node atomics_a_mask_eq_30 = and(atomics_a_mask_sub_3_2_3, atomics_a_mask_nbit_3)
node _atomics_a_mask_acc_T_30 = and(atomics_a_mask_size_3, atomics_a_mask_eq_30)
node atomics_a_mask_acc_30 = or(atomics_a_mask_sub_3_1_3, _atomics_a_mask_acc_T_30)
node atomics_a_mask_eq_31 = and(atomics_a_mask_sub_3_2_3, atomics_a_mask_bit_3)
node _atomics_a_mask_acc_T_31 = and(atomics_a_mask_size_3, atomics_a_mask_eq_31)
node atomics_a_mask_acc_31 = or(atomics_a_mask_sub_3_1_3, _atomics_a_mask_acc_T_31)
node atomics_a_mask_lo_lo_3 = cat(atomics_a_mask_acc_25, atomics_a_mask_acc_24)
node atomics_a_mask_lo_hi_3 = cat(atomics_a_mask_acc_27, atomics_a_mask_acc_26)
node atomics_a_mask_lo_3 = cat(atomics_a_mask_lo_hi_3, atomics_a_mask_lo_lo_3)
node atomics_a_mask_hi_lo_3 = cat(atomics_a_mask_acc_29, atomics_a_mask_acc_28)
node atomics_a_mask_hi_hi_3 = cat(atomics_a_mask_acc_31, atomics_a_mask_acc_30)
node atomics_a_mask_hi_3 = cat(atomics_a_mask_hi_hi_3, atomics_a_mask_hi_lo_3)
node _atomics_a_mask_T_3 = cat(atomics_a_mask_hi_3, atomics_a_mask_lo_3)
connect atomics_a_3.mask, _atomics_a_mask_T_3
connect atomics_a_3.data, pstore1_data
connect atomics_a_3.corrupt, UInt<1>(0h0)
node _atomics_legal_T_144 = leq(UInt<1>(0h0), s2_req.size)
node _atomics_legal_T_145 = leq(s2_req.size, UInt<2>(0h3))
node _atomics_legal_T_146 = and(_atomics_legal_T_144, _atomics_legal_T_145)
node _atomics_legal_T_147 = or(UInt<1>(0h0), _atomics_legal_T_146)
node _atomics_legal_T_148 = xor(s2_req.addr, UInt<1>(0h0))
node _atomics_legal_T_149 = cvt(_atomics_legal_T_148)
node _atomics_legal_T_150 = and(_atomics_legal_T_149, asSInt(UInt<32>(0h48110000)))
node _atomics_legal_T_151 = asSInt(_atomics_legal_T_150)
node _atomics_legal_T_152 = eq(_atomics_legal_T_151, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_153 = xor(s2_req.addr, UInt<21>(0h100000))
node _atomics_legal_T_154 = cvt(_atomics_legal_T_153)
node _atomics_legal_T_155 = and(_atomics_legal_T_154, asSInt(UInt<32>(0h48101000)))
node _atomics_legal_T_156 = asSInt(_atomics_legal_T_155)
node _atomics_legal_T_157 = eq(_atomics_legal_T_156, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_158 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_159 = cvt(_atomics_legal_T_158)
node _atomics_legal_T_160 = and(_atomics_legal_T_159, asSInt(UInt<32>(0h48000000)))
node _atomics_legal_T_161 = asSInt(_atomics_legal_T_160)
node _atomics_legal_T_162 = eq(_atomics_legal_T_161, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_163 = or(_atomics_legal_T_152, _atomics_legal_T_157)
node _atomics_legal_T_164 = or(_atomics_legal_T_163, _atomics_legal_T_162)
node _atomics_legal_T_165 = and(_atomics_legal_T_147, _atomics_legal_T_164)
node _atomics_legal_T_166 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_167 = xor(s2_req.addr, UInt<17>(0h10000))
node _atomics_legal_T_168 = cvt(_atomics_legal_T_167)
node _atomics_legal_T_169 = and(_atomics_legal_T_168, asSInt(UInt<32>(0h48110000)))
node _atomics_legal_T_170 = asSInt(_atomics_legal_T_169)
node _atomics_legal_T_171 = eq(_atomics_legal_T_170, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_172 = xor(s2_req.addr, UInt<31>(0h40000000))
node _atomics_legal_T_173 = cvt(_atomics_legal_T_172)
node _atomics_legal_T_174 = and(_atomics_legal_T_173, asSInt(UInt<32>(0h40000000)))
node _atomics_legal_T_175 = asSInt(_atomics_legal_T_174)
node _atomics_legal_T_176 = eq(_atomics_legal_T_175, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_177 = or(_atomics_legal_T_171, _atomics_legal_T_176)
node _atomics_legal_T_178 = and(_atomics_legal_T_166, _atomics_legal_T_177)
node _atomics_legal_T_179 = or(UInt<1>(0h0), _atomics_legal_T_165)
node atomics_legal_4 = or(_atomics_legal_T_179, _atomics_legal_T_178)
wire atomics_a_4 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_4.opcode, UInt<2>(0h2)
connect atomics_a_4.param, UInt<3>(0h4)
connect atomics_a_4.size, s2_req.size
connect atomics_a_4.source, UInt<1>(0h0)
connect atomics_a_4.address, s2_req.addr
invalidate atomics_a_4.user.amba_prot.fetch
invalidate atomics_a_4.user.amba_prot.secure
invalidate atomics_a_4.user.amba_prot.privileged
invalidate atomics_a_4.user.amba_prot.writealloc
invalidate atomics_a_4.user.amba_prot.readalloc
invalidate atomics_a_4.user.amba_prot.modifiable
invalidate atomics_a_4.user.amba_prot.bufferable
node _atomics_a_mask_sizeOH_T_12 = or(s2_req.size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_4 = bits(_atomics_a_mask_sizeOH_T_12, 1, 0)
node _atomics_a_mask_sizeOH_T_13 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_4)
node _atomics_a_mask_sizeOH_T_14 = bits(_atomics_a_mask_sizeOH_T_13, 2, 0)
node atomics_a_mask_sizeOH_4 = or(_atomics_a_mask_sizeOH_T_14, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_4 = geq(s2_req.size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_4 = bits(atomics_a_mask_sizeOH_4, 2, 2)
node atomics_a_mask_sub_sub_bit_4 = bits(s2_req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_4 = eq(atomics_a_mask_sub_sub_bit_4, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_4 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_4)
node _atomics_a_mask_sub_sub_acc_T_8 = and(atomics_a_mask_sub_sub_size_4, atomics_a_mask_sub_sub_0_2_4)
node atomics_a_mask_sub_sub_0_1_4 = or(atomics_a_mask_sub_sub_sub_0_1_4, _atomics_a_mask_sub_sub_acc_T_8)
node atomics_a_mask_sub_sub_1_2_4 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_4)
node _atomics_a_mask_sub_sub_acc_T_9 = and(atomics_a_mask_sub_sub_size_4, atomics_a_mask_sub_sub_1_2_4)
node atomics_a_mask_sub_sub_1_1_4 = or(atomics_a_mask_sub_sub_sub_0_1_4, _atomics_a_mask_sub_sub_acc_T_9)
node atomics_a_mask_sub_size_4 = bits(atomics_a_mask_sizeOH_4, 1, 1)
node atomics_a_mask_sub_bit_4 = bits(s2_req.addr, 1, 1)
node atomics_a_mask_sub_nbit_4 = eq(atomics_a_mask_sub_bit_4, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_4 = and(atomics_a_mask_sub_sub_0_2_4, atomics_a_mask_sub_nbit_4)
node _atomics_a_mask_sub_acc_T_16 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_0_2_4)
node atomics_a_mask_sub_0_1_4 = or(atomics_a_mask_sub_sub_0_1_4, _atomics_a_mask_sub_acc_T_16)
node atomics_a_mask_sub_1_2_4 = and(atomics_a_mask_sub_sub_0_2_4, atomics_a_mask_sub_bit_4)
node _atomics_a_mask_sub_acc_T_17 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_1_2_4)
node atomics_a_mask_sub_1_1_4 = or(atomics_a_mask_sub_sub_0_1_4, _atomics_a_mask_sub_acc_T_17)
node atomics_a_mask_sub_2_2_4 = and(atomics_a_mask_sub_sub_1_2_4, atomics_a_mask_sub_nbit_4)
node _atomics_a_mask_sub_acc_T_18 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_2_2_4)
node atomics_a_mask_sub_2_1_4 = or(atomics_a_mask_sub_sub_1_1_4, _atomics_a_mask_sub_acc_T_18)
node atomics_a_mask_sub_3_2_4 = and(atomics_a_mask_sub_sub_1_2_4, atomics_a_mask_sub_bit_4)
node _atomics_a_mask_sub_acc_T_19 = and(atomics_a_mask_sub_size_4, atomics_a_mask_sub_3_2_4)
node atomics_a_mask_sub_3_1_4 = or(atomics_a_mask_sub_sub_1_1_4, _atomics_a_mask_sub_acc_T_19)
node atomics_a_mask_size_4 = bits(atomics_a_mask_sizeOH_4, 0, 0)
node atomics_a_mask_bit_4 = bits(s2_req.addr, 0, 0)
node atomics_a_mask_nbit_4 = eq(atomics_a_mask_bit_4, UInt<1>(0h0))
node atomics_a_mask_eq_32 = and(atomics_a_mask_sub_0_2_4, atomics_a_mask_nbit_4)
node _atomics_a_mask_acc_T_32 = and(atomics_a_mask_size_4, atomics_a_mask_eq_32)
node atomics_a_mask_acc_32 = or(atomics_a_mask_sub_0_1_4, _atomics_a_mask_acc_T_32)
node atomics_a_mask_eq_33 = and(atomics_a_mask_sub_0_2_4, atomics_a_mask_bit_4)
node _atomics_a_mask_acc_T_33 = and(atomics_a_mask_size_4, atomics_a_mask_eq_33)
node atomics_a_mask_acc_33 = or(atomics_a_mask_sub_0_1_4, _atomics_a_mask_acc_T_33)
node atomics_a_mask_eq_34 = and(atomics_a_mask_sub_1_2_4, atomics_a_mask_nbit_4)
node _atomics_a_mask_acc_T_34 = and(atomics_a_mask_size_4, atomics_a_mask_eq_34)
node atomics_a_mask_acc_34 = or(atomics_a_mask_sub_1_1_4, _atomics_a_mask_acc_T_34)
node atomics_a_mask_eq_35 = and(atomics_a_mask_sub_1_2_4, atomics_a_mask_bit_4)
node _atomics_a_mask_acc_T_35 = and(atomics_a_mask_size_4, atomics_a_mask_eq_35)
node atomics_a_mask_acc_35 = or(atomics_a_mask_sub_1_1_4, _atomics_a_mask_acc_T_35)
node atomics_a_mask_eq_36 = and(atomics_a_mask_sub_2_2_4, atomics_a_mask_nbit_4)
node _atomics_a_mask_acc_T_36 = and(atomics_a_mask_size_4, atomics_a_mask_eq_36)
node atomics_a_mask_acc_36 = or(atomics_a_mask_sub_2_1_4, _atomics_a_mask_acc_T_36)
node atomics_a_mask_eq_37 = and(atomics_a_mask_sub_2_2_4, atomics_a_mask_bit_4)
node _atomics_a_mask_acc_T_37 = and(atomics_a_mask_size_4, atomics_a_mask_eq_37)
node atomics_a_mask_acc_37 = or(atomics_a_mask_sub_2_1_4, _atomics_a_mask_acc_T_37)
node atomics_a_mask_eq_38 = and(atomics_a_mask_sub_3_2_4, atomics_a_mask_nbit_4)
node _atomics_a_mask_acc_T_38 = and(atomics_a_mask_size_4, atomics_a_mask_eq_38)
node atomics_a_mask_acc_38 = or(atomics_a_mask_sub_3_1_4, _atomics_a_mask_acc_T_38)
node atomics_a_mask_eq_39 = and(atomics_a_mask_sub_3_2_4, atomics_a_mask_bit_4)
node _atomics_a_mask_acc_T_39 = and(atomics_a_mask_size_4, atomics_a_mask_eq_39)
node atomics_a_mask_acc_39 = or(atomics_a_mask_sub_3_1_4, _atomics_a_mask_acc_T_39)
node atomics_a_mask_lo_lo_4 = cat(atomics_a_mask_acc_33, atomics_a_mask_acc_32)
node atomics_a_mask_lo_hi_4 = cat(atomics_a_mask_acc_35, atomics_a_mask_acc_34)
node atomics_a_mask_lo_4 = cat(atomics_a_mask_lo_hi_4, atomics_a_mask_lo_lo_4)
node atomics_a_mask_hi_lo_4 = cat(atomics_a_mask_acc_37, atomics_a_mask_acc_36)
node atomics_a_mask_hi_hi_4 = cat(atomics_a_mask_acc_39, atomics_a_mask_acc_38)
node atomics_a_mask_hi_4 = cat(atomics_a_mask_hi_hi_4, atomics_a_mask_hi_lo_4)
node _atomics_a_mask_T_4 = cat(atomics_a_mask_hi_4, atomics_a_mask_lo_4)
connect atomics_a_4.mask, _atomics_a_mask_T_4
connect atomics_a_4.data, pstore1_data
connect atomics_a_4.corrupt, UInt<1>(0h0)
node _atomics_legal_T_180 = leq(UInt<1>(0h0), s2_req.size)
node _atomics_legal_T_181 = leq(s2_req.size, UInt<2>(0h3))
node _atomics_legal_T_182 = and(_atomics_legal_T_180, _atomics_legal_T_181)
node _atomics_legal_T_183 = or(UInt<1>(0h0), _atomics_legal_T_182)
node _atomics_legal_T_184 = xor(s2_req.addr, UInt<1>(0h0))
node _atomics_legal_T_185 = cvt(_atomics_legal_T_184)
node _atomics_legal_T_186 = and(_atomics_legal_T_185, asSInt(UInt<32>(0h48110000)))
node _atomics_legal_T_187 = asSInt(_atomics_legal_T_186)
node _atomics_legal_T_188 = eq(_atomics_legal_T_187, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_189 = xor(s2_req.addr, UInt<21>(0h100000))
node _atomics_legal_T_190 = cvt(_atomics_legal_T_189)
node _atomics_legal_T_191 = and(_atomics_legal_T_190, asSInt(UInt<32>(0h48101000)))
node _atomics_legal_T_192 = asSInt(_atomics_legal_T_191)
node _atomics_legal_T_193 = eq(_atomics_legal_T_192, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_194 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_195 = cvt(_atomics_legal_T_194)
node _atomics_legal_T_196 = and(_atomics_legal_T_195, asSInt(UInt<32>(0h48000000)))
node _atomics_legal_T_197 = asSInt(_atomics_legal_T_196)
node _atomics_legal_T_198 = eq(_atomics_legal_T_197, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_199 = or(_atomics_legal_T_188, _atomics_legal_T_193)
node _atomics_legal_T_200 = or(_atomics_legal_T_199, _atomics_legal_T_198)
node _atomics_legal_T_201 = and(_atomics_legal_T_183, _atomics_legal_T_200)
node _atomics_legal_T_202 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_203 = xor(s2_req.addr, UInt<17>(0h10000))
node _atomics_legal_T_204 = cvt(_atomics_legal_T_203)
node _atomics_legal_T_205 = and(_atomics_legal_T_204, asSInt(UInt<32>(0h48110000)))
node _atomics_legal_T_206 = asSInt(_atomics_legal_T_205)
node _atomics_legal_T_207 = eq(_atomics_legal_T_206, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_208 = xor(s2_req.addr, UInt<31>(0h40000000))
node _atomics_legal_T_209 = cvt(_atomics_legal_T_208)
node _atomics_legal_T_210 = and(_atomics_legal_T_209, asSInt(UInt<32>(0h40000000)))
node _atomics_legal_T_211 = asSInt(_atomics_legal_T_210)
node _atomics_legal_T_212 = eq(_atomics_legal_T_211, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_213 = or(_atomics_legal_T_207, _atomics_legal_T_212)
node _atomics_legal_T_214 = and(_atomics_legal_T_202, _atomics_legal_T_213)
node _atomics_legal_T_215 = or(UInt<1>(0h0), _atomics_legal_T_201)
node atomics_legal_5 = or(_atomics_legal_T_215, _atomics_legal_T_214)
wire atomics_a_5 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_5.opcode, UInt<2>(0h2)
connect atomics_a_5.param, UInt<3>(0h0)
connect atomics_a_5.size, s2_req.size
connect atomics_a_5.source, UInt<1>(0h0)
connect atomics_a_5.address, s2_req.addr
invalidate atomics_a_5.user.amba_prot.fetch
invalidate atomics_a_5.user.amba_prot.secure
invalidate atomics_a_5.user.amba_prot.privileged
invalidate atomics_a_5.user.amba_prot.writealloc
invalidate atomics_a_5.user.amba_prot.readalloc
invalidate atomics_a_5.user.amba_prot.modifiable
invalidate atomics_a_5.user.amba_prot.bufferable
node _atomics_a_mask_sizeOH_T_15 = or(s2_req.size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_5 = bits(_atomics_a_mask_sizeOH_T_15, 1, 0)
node _atomics_a_mask_sizeOH_T_16 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_5)
node _atomics_a_mask_sizeOH_T_17 = bits(_atomics_a_mask_sizeOH_T_16, 2, 0)
node atomics_a_mask_sizeOH_5 = or(_atomics_a_mask_sizeOH_T_17, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_5 = geq(s2_req.size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_5 = bits(atomics_a_mask_sizeOH_5, 2, 2)
node atomics_a_mask_sub_sub_bit_5 = bits(s2_req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_5 = eq(atomics_a_mask_sub_sub_bit_5, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_5 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_5)
node _atomics_a_mask_sub_sub_acc_T_10 = and(atomics_a_mask_sub_sub_size_5, atomics_a_mask_sub_sub_0_2_5)
node atomics_a_mask_sub_sub_0_1_5 = or(atomics_a_mask_sub_sub_sub_0_1_5, _atomics_a_mask_sub_sub_acc_T_10)
node atomics_a_mask_sub_sub_1_2_5 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_5)
node _atomics_a_mask_sub_sub_acc_T_11 = and(atomics_a_mask_sub_sub_size_5, atomics_a_mask_sub_sub_1_2_5)
node atomics_a_mask_sub_sub_1_1_5 = or(atomics_a_mask_sub_sub_sub_0_1_5, _atomics_a_mask_sub_sub_acc_T_11)
node atomics_a_mask_sub_size_5 = bits(atomics_a_mask_sizeOH_5, 1, 1)
node atomics_a_mask_sub_bit_5 = bits(s2_req.addr, 1, 1)
node atomics_a_mask_sub_nbit_5 = eq(atomics_a_mask_sub_bit_5, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_5 = and(atomics_a_mask_sub_sub_0_2_5, atomics_a_mask_sub_nbit_5)
node _atomics_a_mask_sub_acc_T_20 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_0_2_5)
node atomics_a_mask_sub_0_1_5 = or(atomics_a_mask_sub_sub_0_1_5, _atomics_a_mask_sub_acc_T_20)
node atomics_a_mask_sub_1_2_5 = and(atomics_a_mask_sub_sub_0_2_5, atomics_a_mask_sub_bit_5)
node _atomics_a_mask_sub_acc_T_21 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_1_2_5)
node atomics_a_mask_sub_1_1_5 = or(atomics_a_mask_sub_sub_0_1_5, _atomics_a_mask_sub_acc_T_21)
node atomics_a_mask_sub_2_2_5 = and(atomics_a_mask_sub_sub_1_2_5, atomics_a_mask_sub_nbit_5)
node _atomics_a_mask_sub_acc_T_22 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_2_2_5)
node atomics_a_mask_sub_2_1_5 = or(atomics_a_mask_sub_sub_1_1_5, _atomics_a_mask_sub_acc_T_22)
node atomics_a_mask_sub_3_2_5 = and(atomics_a_mask_sub_sub_1_2_5, atomics_a_mask_sub_bit_5)
node _atomics_a_mask_sub_acc_T_23 = and(atomics_a_mask_sub_size_5, atomics_a_mask_sub_3_2_5)
node atomics_a_mask_sub_3_1_5 = or(atomics_a_mask_sub_sub_1_1_5, _atomics_a_mask_sub_acc_T_23)
node atomics_a_mask_size_5 = bits(atomics_a_mask_sizeOH_5, 0, 0)
node atomics_a_mask_bit_5 = bits(s2_req.addr, 0, 0)
node atomics_a_mask_nbit_5 = eq(atomics_a_mask_bit_5, UInt<1>(0h0))
node atomics_a_mask_eq_40 = and(atomics_a_mask_sub_0_2_5, atomics_a_mask_nbit_5)
node _atomics_a_mask_acc_T_40 = and(atomics_a_mask_size_5, atomics_a_mask_eq_40)
node atomics_a_mask_acc_40 = or(atomics_a_mask_sub_0_1_5, _atomics_a_mask_acc_T_40)
node atomics_a_mask_eq_41 = and(atomics_a_mask_sub_0_2_5, atomics_a_mask_bit_5)
node _atomics_a_mask_acc_T_41 = and(atomics_a_mask_size_5, atomics_a_mask_eq_41)
node atomics_a_mask_acc_41 = or(atomics_a_mask_sub_0_1_5, _atomics_a_mask_acc_T_41)
node atomics_a_mask_eq_42 = and(atomics_a_mask_sub_1_2_5, atomics_a_mask_nbit_5)
node _atomics_a_mask_acc_T_42 = and(atomics_a_mask_size_5, atomics_a_mask_eq_42)
node atomics_a_mask_acc_42 = or(atomics_a_mask_sub_1_1_5, _atomics_a_mask_acc_T_42)
node atomics_a_mask_eq_43 = and(atomics_a_mask_sub_1_2_5, atomics_a_mask_bit_5)
node _atomics_a_mask_acc_T_43 = and(atomics_a_mask_size_5, atomics_a_mask_eq_43)
node atomics_a_mask_acc_43 = or(atomics_a_mask_sub_1_1_5, _atomics_a_mask_acc_T_43)
node atomics_a_mask_eq_44 = and(atomics_a_mask_sub_2_2_5, atomics_a_mask_nbit_5)
node _atomics_a_mask_acc_T_44 = and(atomics_a_mask_size_5, atomics_a_mask_eq_44)
node atomics_a_mask_acc_44 = or(atomics_a_mask_sub_2_1_5, _atomics_a_mask_acc_T_44)
node atomics_a_mask_eq_45 = and(atomics_a_mask_sub_2_2_5, atomics_a_mask_bit_5)
node _atomics_a_mask_acc_T_45 = and(atomics_a_mask_size_5, atomics_a_mask_eq_45)
node atomics_a_mask_acc_45 = or(atomics_a_mask_sub_2_1_5, _atomics_a_mask_acc_T_45)
node atomics_a_mask_eq_46 = and(atomics_a_mask_sub_3_2_5, atomics_a_mask_nbit_5)
node _atomics_a_mask_acc_T_46 = and(atomics_a_mask_size_5, atomics_a_mask_eq_46)
node atomics_a_mask_acc_46 = or(atomics_a_mask_sub_3_1_5, _atomics_a_mask_acc_T_46)
node atomics_a_mask_eq_47 = and(atomics_a_mask_sub_3_2_5, atomics_a_mask_bit_5)
node _atomics_a_mask_acc_T_47 = and(atomics_a_mask_size_5, atomics_a_mask_eq_47)
node atomics_a_mask_acc_47 = or(atomics_a_mask_sub_3_1_5, _atomics_a_mask_acc_T_47)
node atomics_a_mask_lo_lo_5 = cat(atomics_a_mask_acc_41, atomics_a_mask_acc_40)
node atomics_a_mask_lo_hi_5 = cat(atomics_a_mask_acc_43, atomics_a_mask_acc_42)
node atomics_a_mask_lo_5 = cat(atomics_a_mask_lo_hi_5, atomics_a_mask_lo_lo_5)
node atomics_a_mask_hi_lo_5 = cat(atomics_a_mask_acc_45, atomics_a_mask_acc_44)
node atomics_a_mask_hi_hi_5 = cat(atomics_a_mask_acc_47, atomics_a_mask_acc_46)
node atomics_a_mask_hi_5 = cat(atomics_a_mask_hi_hi_5, atomics_a_mask_hi_lo_5)
node _atomics_a_mask_T_5 = cat(atomics_a_mask_hi_5, atomics_a_mask_lo_5)
connect atomics_a_5.mask, _atomics_a_mask_T_5
connect atomics_a_5.data, pstore1_data
connect atomics_a_5.corrupt, UInt<1>(0h0)
node _atomics_legal_T_216 = leq(UInt<1>(0h0), s2_req.size)
node _atomics_legal_T_217 = leq(s2_req.size, UInt<2>(0h3))
node _atomics_legal_T_218 = and(_atomics_legal_T_216, _atomics_legal_T_217)
node _atomics_legal_T_219 = or(UInt<1>(0h0), _atomics_legal_T_218)
node _atomics_legal_T_220 = xor(s2_req.addr, UInt<1>(0h0))
node _atomics_legal_T_221 = cvt(_atomics_legal_T_220)
node _atomics_legal_T_222 = and(_atomics_legal_T_221, asSInt(UInt<32>(0h48110000)))
node _atomics_legal_T_223 = asSInt(_atomics_legal_T_222)
node _atomics_legal_T_224 = eq(_atomics_legal_T_223, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_225 = xor(s2_req.addr, UInt<21>(0h100000))
node _atomics_legal_T_226 = cvt(_atomics_legal_T_225)
node _atomics_legal_T_227 = and(_atomics_legal_T_226, asSInt(UInt<32>(0h48101000)))
node _atomics_legal_T_228 = asSInt(_atomics_legal_T_227)
node _atomics_legal_T_229 = eq(_atomics_legal_T_228, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_230 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_231 = cvt(_atomics_legal_T_230)
node _atomics_legal_T_232 = and(_atomics_legal_T_231, asSInt(UInt<32>(0h48000000)))
node _atomics_legal_T_233 = asSInt(_atomics_legal_T_232)
node _atomics_legal_T_234 = eq(_atomics_legal_T_233, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_235 = or(_atomics_legal_T_224, _atomics_legal_T_229)
node _atomics_legal_T_236 = or(_atomics_legal_T_235, _atomics_legal_T_234)
node _atomics_legal_T_237 = and(_atomics_legal_T_219, _atomics_legal_T_236)
node _atomics_legal_T_238 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_239 = xor(s2_req.addr, UInt<17>(0h10000))
node _atomics_legal_T_240 = cvt(_atomics_legal_T_239)
node _atomics_legal_T_241 = and(_atomics_legal_T_240, asSInt(UInt<32>(0h48110000)))
node _atomics_legal_T_242 = asSInt(_atomics_legal_T_241)
node _atomics_legal_T_243 = eq(_atomics_legal_T_242, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_244 = xor(s2_req.addr, UInt<31>(0h40000000))
node _atomics_legal_T_245 = cvt(_atomics_legal_T_244)
node _atomics_legal_T_246 = and(_atomics_legal_T_245, asSInt(UInt<32>(0h40000000)))
node _atomics_legal_T_247 = asSInt(_atomics_legal_T_246)
node _atomics_legal_T_248 = eq(_atomics_legal_T_247, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_249 = or(_atomics_legal_T_243, _atomics_legal_T_248)
node _atomics_legal_T_250 = and(_atomics_legal_T_238, _atomics_legal_T_249)
node _atomics_legal_T_251 = or(UInt<1>(0h0), _atomics_legal_T_237)
node atomics_legal_6 = or(_atomics_legal_T_251, _atomics_legal_T_250)
wire atomics_a_6 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_6.opcode, UInt<2>(0h2)
connect atomics_a_6.param, UInt<3>(0h1)
connect atomics_a_6.size, s2_req.size
connect atomics_a_6.source, UInt<1>(0h0)
connect atomics_a_6.address, s2_req.addr
invalidate atomics_a_6.user.amba_prot.fetch
invalidate atomics_a_6.user.amba_prot.secure
invalidate atomics_a_6.user.amba_prot.privileged
invalidate atomics_a_6.user.amba_prot.writealloc
invalidate atomics_a_6.user.amba_prot.readalloc
invalidate atomics_a_6.user.amba_prot.modifiable
invalidate atomics_a_6.user.amba_prot.bufferable
node _atomics_a_mask_sizeOH_T_18 = or(s2_req.size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_6 = bits(_atomics_a_mask_sizeOH_T_18, 1, 0)
node _atomics_a_mask_sizeOH_T_19 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_6)
node _atomics_a_mask_sizeOH_T_20 = bits(_atomics_a_mask_sizeOH_T_19, 2, 0)
node atomics_a_mask_sizeOH_6 = or(_atomics_a_mask_sizeOH_T_20, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_6 = geq(s2_req.size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_6 = bits(atomics_a_mask_sizeOH_6, 2, 2)
node atomics_a_mask_sub_sub_bit_6 = bits(s2_req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_6 = eq(atomics_a_mask_sub_sub_bit_6, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_6 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_6)
node _atomics_a_mask_sub_sub_acc_T_12 = and(atomics_a_mask_sub_sub_size_6, atomics_a_mask_sub_sub_0_2_6)
node atomics_a_mask_sub_sub_0_1_6 = or(atomics_a_mask_sub_sub_sub_0_1_6, _atomics_a_mask_sub_sub_acc_T_12)
node atomics_a_mask_sub_sub_1_2_6 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_6)
node _atomics_a_mask_sub_sub_acc_T_13 = and(atomics_a_mask_sub_sub_size_6, atomics_a_mask_sub_sub_1_2_6)
node atomics_a_mask_sub_sub_1_1_6 = or(atomics_a_mask_sub_sub_sub_0_1_6, _atomics_a_mask_sub_sub_acc_T_13)
node atomics_a_mask_sub_size_6 = bits(atomics_a_mask_sizeOH_6, 1, 1)
node atomics_a_mask_sub_bit_6 = bits(s2_req.addr, 1, 1)
node atomics_a_mask_sub_nbit_6 = eq(atomics_a_mask_sub_bit_6, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_6 = and(atomics_a_mask_sub_sub_0_2_6, atomics_a_mask_sub_nbit_6)
node _atomics_a_mask_sub_acc_T_24 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_0_2_6)
node atomics_a_mask_sub_0_1_6 = or(atomics_a_mask_sub_sub_0_1_6, _atomics_a_mask_sub_acc_T_24)
node atomics_a_mask_sub_1_2_6 = and(atomics_a_mask_sub_sub_0_2_6, atomics_a_mask_sub_bit_6)
node _atomics_a_mask_sub_acc_T_25 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_1_2_6)
node atomics_a_mask_sub_1_1_6 = or(atomics_a_mask_sub_sub_0_1_6, _atomics_a_mask_sub_acc_T_25)
node atomics_a_mask_sub_2_2_6 = and(atomics_a_mask_sub_sub_1_2_6, atomics_a_mask_sub_nbit_6)
node _atomics_a_mask_sub_acc_T_26 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_2_2_6)
node atomics_a_mask_sub_2_1_6 = or(atomics_a_mask_sub_sub_1_1_6, _atomics_a_mask_sub_acc_T_26)
node atomics_a_mask_sub_3_2_6 = and(atomics_a_mask_sub_sub_1_2_6, atomics_a_mask_sub_bit_6)
node _atomics_a_mask_sub_acc_T_27 = and(atomics_a_mask_sub_size_6, atomics_a_mask_sub_3_2_6)
node atomics_a_mask_sub_3_1_6 = or(atomics_a_mask_sub_sub_1_1_6, _atomics_a_mask_sub_acc_T_27)
node atomics_a_mask_size_6 = bits(atomics_a_mask_sizeOH_6, 0, 0)
node atomics_a_mask_bit_6 = bits(s2_req.addr, 0, 0)
node atomics_a_mask_nbit_6 = eq(atomics_a_mask_bit_6, UInt<1>(0h0))
node atomics_a_mask_eq_48 = and(atomics_a_mask_sub_0_2_6, atomics_a_mask_nbit_6)
node _atomics_a_mask_acc_T_48 = and(atomics_a_mask_size_6, atomics_a_mask_eq_48)
node atomics_a_mask_acc_48 = or(atomics_a_mask_sub_0_1_6, _atomics_a_mask_acc_T_48)
node atomics_a_mask_eq_49 = and(atomics_a_mask_sub_0_2_6, atomics_a_mask_bit_6)
node _atomics_a_mask_acc_T_49 = and(atomics_a_mask_size_6, atomics_a_mask_eq_49)
node atomics_a_mask_acc_49 = or(atomics_a_mask_sub_0_1_6, _atomics_a_mask_acc_T_49)
node atomics_a_mask_eq_50 = and(atomics_a_mask_sub_1_2_6, atomics_a_mask_nbit_6)
node _atomics_a_mask_acc_T_50 = and(atomics_a_mask_size_6, atomics_a_mask_eq_50)
node atomics_a_mask_acc_50 = or(atomics_a_mask_sub_1_1_6, _atomics_a_mask_acc_T_50)
node atomics_a_mask_eq_51 = and(atomics_a_mask_sub_1_2_6, atomics_a_mask_bit_6)
node _atomics_a_mask_acc_T_51 = and(atomics_a_mask_size_6, atomics_a_mask_eq_51)
node atomics_a_mask_acc_51 = or(atomics_a_mask_sub_1_1_6, _atomics_a_mask_acc_T_51)
node atomics_a_mask_eq_52 = and(atomics_a_mask_sub_2_2_6, atomics_a_mask_nbit_6)
node _atomics_a_mask_acc_T_52 = and(atomics_a_mask_size_6, atomics_a_mask_eq_52)
node atomics_a_mask_acc_52 = or(atomics_a_mask_sub_2_1_6, _atomics_a_mask_acc_T_52)
node atomics_a_mask_eq_53 = and(atomics_a_mask_sub_2_2_6, atomics_a_mask_bit_6)
node _atomics_a_mask_acc_T_53 = and(atomics_a_mask_size_6, atomics_a_mask_eq_53)
node atomics_a_mask_acc_53 = or(atomics_a_mask_sub_2_1_6, _atomics_a_mask_acc_T_53)
node atomics_a_mask_eq_54 = and(atomics_a_mask_sub_3_2_6, atomics_a_mask_nbit_6)
node _atomics_a_mask_acc_T_54 = and(atomics_a_mask_size_6, atomics_a_mask_eq_54)
node atomics_a_mask_acc_54 = or(atomics_a_mask_sub_3_1_6, _atomics_a_mask_acc_T_54)
node atomics_a_mask_eq_55 = and(atomics_a_mask_sub_3_2_6, atomics_a_mask_bit_6)
node _atomics_a_mask_acc_T_55 = and(atomics_a_mask_size_6, atomics_a_mask_eq_55)
node atomics_a_mask_acc_55 = or(atomics_a_mask_sub_3_1_6, _atomics_a_mask_acc_T_55)
node atomics_a_mask_lo_lo_6 = cat(atomics_a_mask_acc_49, atomics_a_mask_acc_48)
node atomics_a_mask_lo_hi_6 = cat(atomics_a_mask_acc_51, atomics_a_mask_acc_50)
node atomics_a_mask_lo_6 = cat(atomics_a_mask_lo_hi_6, atomics_a_mask_lo_lo_6)
node atomics_a_mask_hi_lo_6 = cat(atomics_a_mask_acc_53, atomics_a_mask_acc_52)
node atomics_a_mask_hi_hi_6 = cat(atomics_a_mask_acc_55, atomics_a_mask_acc_54)
node atomics_a_mask_hi_6 = cat(atomics_a_mask_hi_hi_6, atomics_a_mask_hi_lo_6)
node _atomics_a_mask_T_6 = cat(atomics_a_mask_hi_6, atomics_a_mask_lo_6)
connect atomics_a_6.mask, _atomics_a_mask_T_6
connect atomics_a_6.data, pstore1_data
connect atomics_a_6.corrupt, UInt<1>(0h0)
node _atomics_legal_T_252 = leq(UInt<1>(0h0), s2_req.size)
node _atomics_legal_T_253 = leq(s2_req.size, UInt<2>(0h3))
node _atomics_legal_T_254 = and(_atomics_legal_T_252, _atomics_legal_T_253)
node _atomics_legal_T_255 = or(UInt<1>(0h0), _atomics_legal_T_254)
node _atomics_legal_T_256 = xor(s2_req.addr, UInt<1>(0h0))
node _atomics_legal_T_257 = cvt(_atomics_legal_T_256)
node _atomics_legal_T_258 = and(_atomics_legal_T_257, asSInt(UInt<32>(0h48110000)))
node _atomics_legal_T_259 = asSInt(_atomics_legal_T_258)
node _atomics_legal_T_260 = eq(_atomics_legal_T_259, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_261 = xor(s2_req.addr, UInt<21>(0h100000))
node _atomics_legal_T_262 = cvt(_atomics_legal_T_261)
node _atomics_legal_T_263 = and(_atomics_legal_T_262, asSInt(UInt<32>(0h48101000)))
node _atomics_legal_T_264 = asSInt(_atomics_legal_T_263)
node _atomics_legal_T_265 = eq(_atomics_legal_T_264, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_266 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_267 = cvt(_atomics_legal_T_266)
node _atomics_legal_T_268 = and(_atomics_legal_T_267, asSInt(UInt<32>(0h48000000)))
node _atomics_legal_T_269 = asSInt(_atomics_legal_T_268)
node _atomics_legal_T_270 = eq(_atomics_legal_T_269, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_271 = or(_atomics_legal_T_260, _atomics_legal_T_265)
node _atomics_legal_T_272 = or(_atomics_legal_T_271, _atomics_legal_T_270)
node _atomics_legal_T_273 = and(_atomics_legal_T_255, _atomics_legal_T_272)
node _atomics_legal_T_274 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_275 = xor(s2_req.addr, UInt<17>(0h10000))
node _atomics_legal_T_276 = cvt(_atomics_legal_T_275)
node _atomics_legal_T_277 = and(_atomics_legal_T_276, asSInt(UInt<32>(0h48110000)))
node _atomics_legal_T_278 = asSInt(_atomics_legal_T_277)
node _atomics_legal_T_279 = eq(_atomics_legal_T_278, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_280 = xor(s2_req.addr, UInt<31>(0h40000000))
node _atomics_legal_T_281 = cvt(_atomics_legal_T_280)
node _atomics_legal_T_282 = and(_atomics_legal_T_281, asSInt(UInt<32>(0h40000000)))
node _atomics_legal_T_283 = asSInt(_atomics_legal_T_282)
node _atomics_legal_T_284 = eq(_atomics_legal_T_283, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_285 = or(_atomics_legal_T_279, _atomics_legal_T_284)
node _atomics_legal_T_286 = and(_atomics_legal_T_274, _atomics_legal_T_285)
node _atomics_legal_T_287 = or(UInt<1>(0h0), _atomics_legal_T_273)
node atomics_legal_7 = or(_atomics_legal_T_287, _atomics_legal_T_286)
wire atomics_a_7 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_7.opcode, UInt<2>(0h2)
connect atomics_a_7.param, UInt<3>(0h2)
connect atomics_a_7.size, s2_req.size
connect atomics_a_7.source, UInt<1>(0h0)
connect atomics_a_7.address, s2_req.addr
invalidate atomics_a_7.user.amba_prot.fetch
invalidate atomics_a_7.user.amba_prot.secure
invalidate atomics_a_7.user.amba_prot.privileged
invalidate atomics_a_7.user.amba_prot.writealloc
invalidate atomics_a_7.user.amba_prot.readalloc
invalidate atomics_a_7.user.amba_prot.modifiable
invalidate atomics_a_7.user.amba_prot.bufferable
node _atomics_a_mask_sizeOH_T_21 = or(s2_req.size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_7 = bits(_atomics_a_mask_sizeOH_T_21, 1, 0)
node _atomics_a_mask_sizeOH_T_22 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_7)
node _atomics_a_mask_sizeOH_T_23 = bits(_atomics_a_mask_sizeOH_T_22, 2, 0)
node atomics_a_mask_sizeOH_7 = or(_atomics_a_mask_sizeOH_T_23, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_7 = geq(s2_req.size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_7 = bits(atomics_a_mask_sizeOH_7, 2, 2)
node atomics_a_mask_sub_sub_bit_7 = bits(s2_req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_7 = eq(atomics_a_mask_sub_sub_bit_7, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_7 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_7)
node _atomics_a_mask_sub_sub_acc_T_14 = and(atomics_a_mask_sub_sub_size_7, atomics_a_mask_sub_sub_0_2_7)
node atomics_a_mask_sub_sub_0_1_7 = or(atomics_a_mask_sub_sub_sub_0_1_7, _atomics_a_mask_sub_sub_acc_T_14)
node atomics_a_mask_sub_sub_1_2_7 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_7)
node _atomics_a_mask_sub_sub_acc_T_15 = and(atomics_a_mask_sub_sub_size_7, atomics_a_mask_sub_sub_1_2_7)
node atomics_a_mask_sub_sub_1_1_7 = or(atomics_a_mask_sub_sub_sub_0_1_7, _atomics_a_mask_sub_sub_acc_T_15)
node atomics_a_mask_sub_size_7 = bits(atomics_a_mask_sizeOH_7, 1, 1)
node atomics_a_mask_sub_bit_7 = bits(s2_req.addr, 1, 1)
node atomics_a_mask_sub_nbit_7 = eq(atomics_a_mask_sub_bit_7, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_7 = and(atomics_a_mask_sub_sub_0_2_7, atomics_a_mask_sub_nbit_7)
node _atomics_a_mask_sub_acc_T_28 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_0_2_7)
node atomics_a_mask_sub_0_1_7 = or(atomics_a_mask_sub_sub_0_1_7, _atomics_a_mask_sub_acc_T_28)
node atomics_a_mask_sub_1_2_7 = and(atomics_a_mask_sub_sub_0_2_7, atomics_a_mask_sub_bit_7)
node _atomics_a_mask_sub_acc_T_29 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_1_2_7)
node atomics_a_mask_sub_1_1_7 = or(atomics_a_mask_sub_sub_0_1_7, _atomics_a_mask_sub_acc_T_29)
node atomics_a_mask_sub_2_2_7 = and(atomics_a_mask_sub_sub_1_2_7, atomics_a_mask_sub_nbit_7)
node _atomics_a_mask_sub_acc_T_30 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_2_2_7)
node atomics_a_mask_sub_2_1_7 = or(atomics_a_mask_sub_sub_1_1_7, _atomics_a_mask_sub_acc_T_30)
node atomics_a_mask_sub_3_2_7 = and(atomics_a_mask_sub_sub_1_2_7, atomics_a_mask_sub_bit_7)
node _atomics_a_mask_sub_acc_T_31 = and(atomics_a_mask_sub_size_7, atomics_a_mask_sub_3_2_7)
node atomics_a_mask_sub_3_1_7 = or(atomics_a_mask_sub_sub_1_1_7, _atomics_a_mask_sub_acc_T_31)
node atomics_a_mask_size_7 = bits(atomics_a_mask_sizeOH_7, 0, 0)
node atomics_a_mask_bit_7 = bits(s2_req.addr, 0, 0)
node atomics_a_mask_nbit_7 = eq(atomics_a_mask_bit_7, UInt<1>(0h0))
node atomics_a_mask_eq_56 = and(atomics_a_mask_sub_0_2_7, atomics_a_mask_nbit_7)
node _atomics_a_mask_acc_T_56 = and(atomics_a_mask_size_7, atomics_a_mask_eq_56)
node atomics_a_mask_acc_56 = or(atomics_a_mask_sub_0_1_7, _atomics_a_mask_acc_T_56)
node atomics_a_mask_eq_57 = and(atomics_a_mask_sub_0_2_7, atomics_a_mask_bit_7)
node _atomics_a_mask_acc_T_57 = and(atomics_a_mask_size_7, atomics_a_mask_eq_57)
node atomics_a_mask_acc_57 = or(atomics_a_mask_sub_0_1_7, _atomics_a_mask_acc_T_57)
node atomics_a_mask_eq_58 = and(atomics_a_mask_sub_1_2_7, atomics_a_mask_nbit_7)
node _atomics_a_mask_acc_T_58 = and(atomics_a_mask_size_7, atomics_a_mask_eq_58)
node atomics_a_mask_acc_58 = or(atomics_a_mask_sub_1_1_7, _atomics_a_mask_acc_T_58)
node atomics_a_mask_eq_59 = and(atomics_a_mask_sub_1_2_7, atomics_a_mask_bit_7)
node _atomics_a_mask_acc_T_59 = and(atomics_a_mask_size_7, atomics_a_mask_eq_59)
node atomics_a_mask_acc_59 = or(atomics_a_mask_sub_1_1_7, _atomics_a_mask_acc_T_59)
node atomics_a_mask_eq_60 = and(atomics_a_mask_sub_2_2_7, atomics_a_mask_nbit_7)
node _atomics_a_mask_acc_T_60 = and(atomics_a_mask_size_7, atomics_a_mask_eq_60)
node atomics_a_mask_acc_60 = or(atomics_a_mask_sub_2_1_7, _atomics_a_mask_acc_T_60)
node atomics_a_mask_eq_61 = and(atomics_a_mask_sub_2_2_7, atomics_a_mask_bit_7)
node _atomics_a_mask_acc_T_61 = and(atomics_a_mask_size_7, atomics_a_mask_eq_61)
node atomics_a_mask_acc_61 = or(atomics_a_mask_sub_2_1_7, _atomics_a_mask_acc_T_61)
node atomics_a_mask_eq_62 = and(atomics_a_mask_sub_3_2_7, atomics_a_mask_nbit_7)
node _atomics_a_mask_acc_T_62 = and(atomics_a_mask_size_7, atomics_a_mask_eq_62)
node atomics_a_mask_acc_62 = or(atomics_a_mask_sub_3_1_7, _atomics_a_mask_acc_T_62)
node atomics_a_mask_eq_63 = and(atomics_a_mask_sub_3_2_7, atomics_a_mask_bit_7)
node _atomics_a_mask_acc_T_63 = and(atomics_a_mask_size_7, atomics_a_mask_eq_63)
node atomics_a_mask_acc_63 = or(atomics_a_mask_sub_3_1_7, _atomics_a_mask_acc_T_63)
node atomics_a_mask_lo_lo_7 = cat(atomics_a_mask_acc_57, atomics_a_mask_acc_56)
node atomics_a_mask_lo_hi_7 = cat(atomics_a_mask_acc_59, atomics_a_mask_acc_58)
node atomics_a_mask_lo_7 = cat(atomics_a_mask_lo_hi_7, atomics_a_mask_lo_lo_7)
node atomics_a_mask_hi_lo_7 = cat(atomics_a_mask_acc_61, atomics_a_mask_acc_60)
node atomics_a_mask_hi_hi_7 = cat(atomics_a_mask_acc_63, atomics_a_mask_acc_62)
node atomics_a_mask_hi_7 = cat(atomics_a_mask_hi_hi_7, atomics_a_mask_hi_lo_7)
node _atomics_a_mask_T_7 = cat(atomics_a_mask_hi_7, atomics_a_mask_lo_7)
connect atomics_a_7.mask, _atomics_a_mask_T_7
connect atomics_a_7.data, pstore1_data
connect atomics_a_7.corrupt, UInt<1>(0h0)
node _atomics_legal_T_288 = leq(UInt<1>(0h0), s2_req.size)
node _atomics_legal_T_289 = leq(s2_req.size, UInt<2>(0h3))
node _atomics_legal_T_290 = and(_atomics_legal_T_288, _atomics_legal_T_289)
node _atomics_legal_T_291 = or(UInt<1>(0h0), _atomics_legal_T_290)
node _atomics_legal_T_292 = xor(s2_req.addr, UInt<1>(0h0))
node _atomics_legal_T_293 = cvt(_atomics_legal_T_292)
node _atomics_legal_T_294 = and(_atomics_legal_T_293, asSInt(UInt<32>(0h48110000)))
node _atomics_legal_T_295 = asSInt(_atomics_legal_T_294)
node _atomics_legal_T_296 = eq(_atomics_legal_T_295, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_297 = xor(s2_req.addr, UInt<21>(0h100000))
node _atomics_legal_T_298 = cvt(_atomics_legal_T_297)
node _atomics_legal_T_299 = and(_atomics_legal_T_298, asSInt(UInt<32>(0h48101000)))
node _atomics_legal_T_300 = asSInt(_atomics_legal_T_299)
node _atomics_legal_T_301 = eq(_atomics_legal_T_300, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_302 = xor(s2_req.addr, UInt<28>(0h8000000))
node _atomics_legal_T_303 = cvt(_atomics_legal_T_302)
node _atomics_legal_T_304 = and(_atomics_legal_T_303, asSInt(UInt<32>(0h48000000)))
node _atomics_legal_T_305 = asSInt(_atomics_legal_T_304)
node _atomics_legal_T_306 = eq(_atomics_legal_T_305, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_307 = or(_atomics_legal_T_296, _atomics_legal_T_301)
node _atomics_legal_T_308 = or(_atomics_legal_T_307, _atomics_legal_T_306)
node _atomics_legal_T_309 = and(_atomics_legal_T_291, _atomics_legal_T_308)
node _atomics_legal_T_310 = or(UInt<1>(0h0), UInt<1>(0h0))
node _atomics_legal_T_311 = xor(s2_req.addr, UInt<17>(0h10000))
node _atomics_legal_T_312 = cvt(_atomics_legal_T_311)
node _atomics_legal_T_313 = and(_atomics_legal_T_312, asSInt(UInt<32>(0h48110000)))
node _atomics_legal_T_314 = asSInt(_atomics_legal_T_313)
node _atomics_legal_T_315 = eq(_atomics_legal_T_314, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_316 = xor(s2_req.addr, UInt<31>(0h40000000))
node _atomics_legal_T_317 = cvt(_atomics_legal_T_316)
node _atomics_legal_T_318 = and(_atomics_legal_T_317, asSInt(UInt<32>(0h40000000)))
node _atomics_legal_T_319 = asSInt(_atomics_legal_T_318)
node _atomics_legal_T_320 = eq(_atomics_legal_T_319, asSInt(UInt<1>(0h0)))
node _atomics_legal_T_321 = or(_atomics_legal_T_315, _atomics_legal_T_320)
node _atomics_legal_T_322 = and(_atomics_legal_T_310, _atomics_legal_T_321)
node _atomics_legal_T_323 = or(UInt<1>(0h0), _atomics_legal_T_309)
node atomics_legal_8 = or(_atomics_legal_T_323, _atomics_legal_T_322)
wire atomics_a_8 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect atomics_a_8.opcode, UInt<2>(0h2)
connect atomics_a_8.param, UInt<3>(0h3)
connect atomics_a_8.size, s2_req.size
connect atomics_a_8.source, UInt<1>(0h0)
connect atomics_a_8.address, s2_req.addr
invalidate atomics_a_8.user.amba_prot.fetch
invalidate atomics_a_8.user.amba_prot.secure
invalidate atomics_a_8.user.amba_prot.privileged
invalidate atomics_a_8.user.amba_prot.writealloc
invalidate atomics_a_8.user.amba_prot.readalloc
invalidate atomics_a_8.user.amba_prot.modifiable
invalidate atomics_a_8.user.amba_prot.bufferable
node _atomics_a_mask_sizeOH_T_24 = or(s2_req.size, UInt<3>(0h0))
node atomics_a_mask_sizeOH_shiftAmount_8 = bits(_atomics_a_mask_sizeOH_T_24, 1, 0)
node _atomics_a_mask_sizeOH_T_25 = dshl(UInt<1>(0h1), atomics_a_mask_sizeOH_shiftAmount_8)
node _atomics_a_mask_sizeOH_T_26 = bits(_atomics_a_mask_sizeOH_T_25, 2, 0)
node atomics_a_mask_sizeOH_8 = or(_atomics_a_mask_sizeOH_T_26, UInt<1>(0h1))
node atomics_a_mask_sub_sub_sub_0_1_8 = geq(s2_req.size, UInt<2>(0h3))
node atomics_a_mask_sub_sub_size_8 = bits(atomics_a_mask_sizeOH_8, 2, 2)
node atomics_a_mask_sub_sub_bit_8 = bits(s2_req.addr, 2, 2)
node atomics_a_mask_sub_sub_nbit_8 = eq(atomics_a_mask_sub_sub_bit_8, UInt<1>(0h0))
node atomics_a_mask_sub_sub_0_2_8 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_nbit_8)
node _atomics_a_mask_sub_sub_acc_T_16 = and(atomics_a_mask_sub_sub_size_8, atomics_a_mask_sub_sub_0_2_8)
node atomics_a_mask_sub_sub_0_1_8 = or(atomics_a_mask_sub_sub_sub_0_1_8, _atomics_a_mask_sub_sub_acc_T_16)
node atomics_a_mask_sub_sub_1_2_8 = and(UInt<1>(0h1), atomics_a_mask_sub_sub_bit_8)
node _atomics_a_mask_sub_sub_acc_T_17 = and(atomics_a_mask_sub_sub_size_8, atomics_a_mask_sub_sub_1_2_8)
node atomics_a_mask_sub_sub_1_1_8 = or(atomics_a_mask_sub_sub_sub_0_1_8, _atomics_a_mask_sub_sub_acc_T_17)
node atomics_a_mask_sub_size_8 = bits(atomics_a_mask_sizeOH_8, 1, 1)
node atomics_a_mask_sub_bit_8 = bits(s2_req.addr, 1, 1)
node atomics_a_mask_sub_nbit_8 = eq(atomics_a_mask_sub_bit_8, UInt<1>(0h0))
node atomics_a_mask_sub_0_2_8 = and(atomics_a_mask_sub_sub_0_2_8, atomics_a_mask_sub_nbit_8)
node _atomics_a_mask_sub_acc_T_32 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_0_2_8)
node atomics_a_mask_sub_0_1_8 = or(atomics_a_mask_sub_sub_0_1_8, _atomics_a_mask_sub_acc_T_32)
node atomics_a_mask_sub_1_2_8 = and(atomics_a_mask_sub_sub_0_2_8, atomics_a_mask_sub_bit_8)
node _atomics_a_mask_sub_acc_T_33 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_1_2_8)
node atomics_a_mask_sub_1_1_8 = or(atomics_a_mask_sub_sub_0_1_8, _atomics_a_mask_sub_acc_T_33)
node atomics_a_mask_sub_2_2_8 = and(atomics_a_mask_sub_sub_1_2_8, atomics_a_mask_sub_nbit_8)
node _atomics_a_mask_sub_acc_T_34 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_2_2_8)
node atomics_a_mask_sub_2_1_8 = or(atomics_a_mask_sub_sub_1_1_8, _atomics_a_mask_sub_acc_T_34)
node atomics_a_mask_sub_3_2_8 = and(atomics_a_mask_sub_sub_1_2_8, atomics_a_mask_sub_bit_8)
node _atomics_a_mask_sub_acc_T_35 = and(atomics_a_mask_sub_size_8, atomics_a_mask_sub_3_2_8)
node atomics_a_mask_sub_3_1_8 = or(atomics_a_mask_sub_sub_1_1_8, _atomics_a_mask_sub_acc_T_35)
node atomics_a_mask_size_8 = bits(atomics_a_mask_sizeOH_8, 0, 0)
node atomics_a_mask_bit_8 = bits(s2_req.addr, 0, 0)
node atomics_a_mask_nbit_8 = eq(atomics_a_mask_bit_8, UInt<1>(0h0))
node atomics_a_mask_eq_64 = and(atomics_a_mask_sub_0_2_8, atomics_a_mask_nbit_8)
node _atomics_a_mask_acc_T_64 = and(atomics_a_mask_size_8, atomics_a_mask_eq_64)
node atomics_a_mask_acc_64 = or(atomics_a_mask_sub_0_1_8, _atomics_a_mask_acc_T_64)
node atomics_a_mask_eq_65 = and(atomics_a_mask_sub_0_2_8, atomics_a_mask_bit_8)
node _atomics_a_mask_acc_T_65 = and(atomics_a_mask_size_8, atomics_a_mask_eq_65)
node atomics_a_mask_acc_65 = or(atomics_a_mask_sub_0_1_8, _atomics_a_mask_acc_T_65)
node atomics_a_mask_eq_66 = and(atomics_a_mask_sub_1_2_8, atomics_a_mask_nbit_8)
node _atomics_a_mask_acc_T_66 = and(atomics_a_mask_size_8, atomics_a_mask_eq_66)
node atomics_a_mask_acc_66 = or(atomics_a_mask_sub_1_1_8, _atomics_a_mask_acc_T_66)
node atomics_a_mask_eq_67 = and(atomics_a_mask_sub_1_2_8, atomics_a_mask_bit_8)
node _atomics_a_mask_acc_T_67 = and(atomics_a_mask_size_8, atomics_a_mask_eq_67)
node atomics_a_mask_acc_67 = or(atomics_a_mask_sub_1_1_8, _atomics_a_mask_acc_T_67)
node atomics_a_mask_eq_68 = and(atomics_a_mask_sub_2_2_8, atomics_a_mask_nbit_8)
node _atomics_a_mask_acc_T_68 = and(atomics_a_mask_size_8, atomics_a_mask_eq_68)
node atomics_a_mask_acc_68 = or(atomics_a_mask_sub_2_1_8, _atomics_a_mask_acc_T_68)
node atomics_a_mask_eq_69 = and(atomics_a_mask_sub_2_2_8, atomics_a_mask_bit_8)
node _atomics_a_mask_acc_T_69 = and(atomics_a_mask_size_8, atomics_a_mask_eq_69)
node atomics_a_mask_acc_69 = or(atomics_a_mask_sub_2_1_8, _atomics_a_mask_acc_T_69)
node atomics_a_mask_eq_70 = and(atomics_a_mask_sub_3_2_8, atomics_a_mask_nbit_8)
node _atomics_a_mask_acc_T_70 = and(atomics_a_mask_size_8, atomics_a_mask_eq_70)
node atomics_a_mask_acc_70 = or(atomics_a_mask_sub_3_1_8, _atomics_a_mask_acc_T_70)
node atomics_a_mask_eq_71 = and(atomics_a_mask_sub_3_2_8, atomics_a_mask_bit_8)
node _atomics_a_mask_acc_T_71 = and(atomics_a_mask_size_8, atomics_a_mask_eq_71)
node atomics_a_mask_acc_71 = or(atomics_a_mask_sub_3_1_8, _atomics_a_mask_acc_T_71)
node atomics_a_mask_lo_lo_8 = cat(atomics_a_mask_acc_65, atomics_a_mask_acc_64)
node atomics_a_mask_lo_hi_8 = cat(atomics_a_mask_acc_67, atomics_a_mask_acc_66)
node atomics_a_mask_lo_8 = cat(atomics_a_mask_lo_hi_8, atomics_a_mask_lo_lo_8)
node atomics_a_mask_hi_lo_8 = cat(atomics_a_mask_acc_69, atomics_a_mask_acc_68)
node atomics_a_mask_hi_hi_8 = cat(atomics_a_mask_acc_71, atomics_a_mask_acc_70)
node atomics_a_mask_hi_8 = cat(atomics_a_mask_hi_hi_8, atomics_a_mask_hi_lo_8)
node _atomics_a_mask_T_8 = cat(atomics_a_mask_hi_8, atomics_a_mask_lo_8)
connect atomics_a_8.mask, _atomics_a_mask_T_8
connect atomics_a_8.data, pstore1_data
connect atomics_a_8.corrupt, UInt<1>(0h0)
node _atomics_T = eq(UInt<3>(0h4), s2_req.cmd)
node _atomics_T_1 = mux(_atomics_T, atomics_a, _atomics_WIRE_1)
node _atomics_T_2 = eq(UInt<4>(0h9), s2_req.cmd)
node _atomics_T_3 = mux(_atomics_T_2, atomics_a_1, _atomics_T_1)
node _atomics_T_4 = eq(UInt<4>(0ha), s2_req.cmd)
node _atomics_T_5 = mux(_atomics_T_4, atomics_a_2, _atomics_T_3)
node _atomics_T_6 = eq(UInt<4>(0hb), s2_req.cmd)
node _atomics_T_7 = mux(_atomics_T_6, atomics_a_3, _atomics_T_5)
node _atomics_T_8 = eq(UInt<4>(0h8), s2_req.cmd)
node _atomics_T_9 = mux(_atomics_T_8, atomics_a_4, _atomics_T_7)
node _atomics_T_10 = eq(UInt<4>(0hc), s2_req.cmd)
node _atomics_T_11 = mux(_atomics_T_10, atomics_a_5, _atomics_T_9)
node _atomics_T_12 = eq(UInt<4>(0hd), s2_req.cmd)
node _atomics_T_13 = mux(_atomics_T_12, atomics_a_6, _atomics_T_11)
node _atomics_T_14 = eq(UInt<4>(0he), s2_req.cmd)
node _atomics_T_15 = mux(_atomics_T_14, atomics_a_7, _atomics_T_13)
node _atomics_T_16 = eq(UInt<4>(0hf), s2_req.cmd)
node atomics = mux(_atomics_T_16, atomics_a_8, _atomics_T_15)
node _tl_out_a_valid_T = eq(io.cpu.s2_kill, UInt<1>(0h0))
node _tl_out_a_valid_T_1 = xor(s2_req.addr, release_ack_addr)
node _tl_out_a_valid_T_2 = bits(_tl_out_a_valid_T_1, 20, 6)
node _tl_out_a_valid_T_3 = eq(_tl_out_a_valid_T_2, UInt<1>(0h0))
node _tl_out_a_valid_T_4 = and(release_ack_wait, _tl_out_a_valid_T_3)
node _tl_out_a_valid_T_5 = eq(_tl_out_a_valid_T_4, UInt<1>(0h0))
node _tl_out_a_valid_T_6 = and(s2_valid_cached_miss, _tl_out_a_valid_T_5)
node _tl_out_a_valid_T_7 = eq(release_ack_wait, UInt<1>(0h0))
node _tl_out_a_valid_T_8 = and(UInt<1>(0h0), _tl_out_a_valid_T_7)
node _tl_out_a_valid_T_9 = and(_tl_out_a_valid_T_8, UInt<1>(0h1))
node _tl_out_a_valid_T_10 = eq(s2_victim_dirty, UInt<1>(0h0))
node _tl_out_a_valid_T_11 = or(_tl_out_a_valid_T_9, _tl_out_a_valid_T_10)
node _tl_out_a_valid_T_12 = and(_tl_out_a_valid_T_6, _tl_out_a_valid_T_11)
node _tl_out_a_valid_T_13 = or(s2_valid_uncached_pending, _tl_out_a_valid_T_12)
node _tl_out_a_valid_T_14 = and(_tl_out_a_valid_T, _tl_out_a_valid_T_13)
connect tl_out_a.valid, _tl_out_a_valid_T_14
node _tl_out_a_bits_T = eq(s2_uncached, UInt<1>(0h0))
wire _tl_out_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect _tl_out_a_bits_WIRE.corrupt, UInt<1>(0h0)
connect _tl_out_a_bits_WIRE.data, UInt<64>(0h0)
connect _tl_out_a_bits_WIRE.mask, UInt<8>(0h0)
connect _tl_out_a_bits_WIRE.user.amba_prot.fetch, UInt<1>(0h0)
connect _tl_out_a_bits_WIRE.user.amba_prot.secure, UInt<1>(0h0)
connect _tl_out_a_bits_WIRE.user.amba_prot.privileged, UInt<1>(0h0)
connect _tl_out_a_bits_WIRE.user.amba_prot.writealloc, UInt<1>(0h0)
connect _tl_out_a_bits_WIRE.user.amba_prot.readalloc, UInt<1>(0h0)
connect _tl_out_a_bits_WIRE.user.amba_prot.modifiable, UInt<1>(0h0)
connect _tl_out_a_bits_WIRE.user.amba_prot.bufferable, UInt<1>(0h0)
connect _tl_out_a_bits_WIRE.address, UInt<32>(0h0)
connect _tl_out_a_bits_WIRE.source, UInt<1>(0h0)
connect _tl_out_a_bits_WIRE.size, UInt<4>(0h0)
connect _tl_out_a_bits_WIRE.param, UInt<3>(0h0)
connect _tl_out_a_bits_WIRE.opcode, UInt<3>(0h0)
wire _tl_out_a_bits_WIRE_1 : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect _tl_out_a_bits_WIRE_1.corrupt, _tl_out_a_bits_WIRE.corrupt
connect _tl_out_a_bits_WIRE_1.data, _tl_out_a_bits_WIRE.data
connect _tl_out_a_bits_WIRE_1.mask, _tl_out_a_bits_WIRE.mask
connect _tl_out_a_bits_WIRE_1.user, _tl_out_a_bits_WIRE.user
connect _tl_out_a_bits_WIRE_1.address, _tl_out_a_bits_WIRE.address
connect _tl_out_a_bits_WIRE_1.source, _tl_out_a_bits_WIRE.source
connect _tl_out_a_bits_WIRE_1.size, _tl_out_a_bits_WIRE.size
connect _tl_out_a_bits_WIRE_1.param, _tl_out_a_bits_WIRE.param
connect _tl_out_a_bits_WIRE_1.opcode, _tl_out_a_bits_WIRE.opcode
node _tl_out_a_bits_T_1 = eq(s2_write, UInt<1>(0h0))
node _tl_out_a_bits_T_2 = eq(s2_req.cmd, UInt<5>(0h11))
node _tl_out_a_bits_T_3 = eq(s2_read, UInt<1>(0h0))
node _tl_out_a_bits_T_4 = mux(_tl_out_a_bits_T_3, put, atomics)
node _tl_out_a_bits_T_5 = mux(_tl_out_a_bits_T_2, putpartial, _tl_out_a_bits_T_4)
node _tl_out_a_bits_T_6 = mux(_tl_out_a_bits_T_1, get, _tl_out_a_bits_T_5)
node _tl_out_a_bits_T_7 = mux(_tl_out_a_bits_T, _tl_out_a_bits_WIRE_1, _tl_out_a_bits_T_6)
connect tl_out_a.bits, _tl_out_a_bits_T_7
node _tl_out_a_bits_user_amba_prot_privileged_T = eq(s2_req.dprv, UInt<2>(0h3))
node _tl_out_a_bits_user_amba_prot_privileged_T_1 = or(_tl_out_a_bits_user_amba_prot_privileged_T, s2_pma.cacheable)
connect tl_out_a.bits.user.amba_prot.privileged, _tl_out_a_bits_user_amba_prot_privileged_T_1
connect tl_out_a.bits.user.amba_prot.bufferable, s2_pma.cacheable
connect tl_out_a.bits.user.amba_prot.modifiable, s2_pma.cacheable
connect tl_out_a.bits.user.amba_prot.readalloc, s2_pma.cacheable
connect tl_out_a.bits.user.amba_prot.writealloc, s2_pma.cacheable
connect tl_out_a.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect tl_out_a.bits.user.amba_prot.secure, UInt<1>(0h1)
node a_sel = shr(UInt<1>(0h1), 0)
node _T_60 = and(tl_out_a.ready, tl_out_a.valid)
when _T_60 :
when s2_uncached :
node _T_61 = bits(a_sel, 0, 0)
when _T_61 :
connect uncachedInFlight[0], UInt<1>(0h1)
connect uncachedReqs[0], s2_req
node _uncachedReqs_0_cmd_T = eq(s2_req.cmd, UInt<5>(0h11))
node _uncachedReqs_0_cmd_T_1 = mux(_uncachedReqs_0_cmd_T, UInt<5>(0h11), UInt<1>(0h1))
node _uncachedReqs_0_cmd_T_2 = mux(s2_write, _uncachedReqs_0_cmd_T_1, UInt<1>(0h0))
connect uncachedReqs[0].cmd, _uncachedReqs_0_cmd_T_2
else :
connect cached_grant_wait, UInt<1>(0h1)
connect refill_way, s2_victim_or_hit_way
node _T_62 = and(nodeOut.d.ready, nodeOut.d.valid)
node _r_beats1_decode_T = dshl(UInt<12>(0hfff), nodeOut.d.bits.size)
node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0)
node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1)
node r_beats1_decode = shr(_r_beats1_decode_T_2, 3)
node r_beats1_opdata = bits(nodeOut.d.bits.opcode, 0, 0)
node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0))
regreset r_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _r_counter1_T = sub(r_counter, UInt<1>(0h1))
node r_counter1 = tail(_r_counter1_T, 1)
node d_first = eq(r_counter, UInt<1>(0h0))
node _r_last_T = eq(r_counter, UInt<1>(0h1))
node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0))
node d_last = or(_r_last_T, _r_last_T_1)
node d_done = and(d_last, _T_62)
node _r_count_T = not(r_counter1)
node r_4 = and(r_beats1, _r_count_T)
when _T_62 :
node _r_counter_T = mux(d_first, r_beats1, r_counter1)
connect r_counter, _r_counter_T
node d_address_inc = shl(r_4, 3)
node _T_63 = eq(nodeOut.d.valid, UInt<1>(0h0))
node _T_64 = eq(nodeOut.d.bits.opcode, UInt<1>(0h1))
node _T_65 = eq(nodeOut.d.bits.opcode, UInt<1>(0h0))
node _T_66 = eq(nodeOut.d.bits.opcode, UInt<2>(0h2))
node _T_67 = or(_T_64, _T_65)
node _T_68 = or(_T_67, _T_66)
node _T_69 = or(_T_63, _T_68)
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at DCache.scala:654 assert(!tl_out.d.valid || whole_opc.isOneOf(uncachedGrantOpcodes))\n") : printf_2
assert(clock, _T_69, UInt<1>(0h1), "") : assert_2
node d_opc = bits(nodeOut.d.bits.opcode, 1, 0)
wire data_plaInput : UInt<2>
node data_invInputs = not(data_plaInput)
wire data_plaOutput : UInt<1>
node data_andMatrixOutputs_andMatrixInput_0 = bits(data_plaInput, 0, 0)
node data_andMatrixOutputs_andMatrixInput_1 = bits(data_invInputs, 1, 1)
node _data_andMatrixOutputs_T = cat(data_andMatrixOutputs_andMatrixInput_0, data_andMatrixOutputs_andMatrixInput_1)
node data_andMatrixOutputs_0_2 = andr(_data_andMatrixOutputs_T)
node data_orMatrixOutputs = orr(data_andMatrixOutputs_0_2)
node data_invMatrixOutputs = bits(data_orMatrixOutputs, 0, 0)
connect data_plaOutput, data_invMatrixOutputs
connect data_plaInput, d_opc
node grantIsUncachedData = bits(data_plaOutput, 0, 0)
node _tl_d_data_encoded_T_9 = bits(io.ptw.customCSRs.csrs[0].value, 9, 9)
node _tl_d_data_encoded_T_10 = eq(_tl_d_data_encoded_T_9, UInt<1>(0h0))
node _tl_d_data_encoded_T_11 = and(nodeOut.d.bits.corrupt, _tl_d_data_encoded_T_10)
node _tl_d_data_encoded_T_12 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _tl_d_data_encoded_T_13 = and(_tl_d_data_encoded_T_11, _tl_d_data_encoded_T_12)
node _tl_d_data_encoded_T_14 = bits(nodeOut.d.bits.data, 7, 0)
node _tl_d_data_encoded_T_15 = bits(nodeOut.d.bits.data, 15, 8)
node _tl_d_data_encoded_T_16 = bits(nodeOut.d.bits.data, 23, 16)
node _tl_d_data_encoded_T_17 = bits(nodeOut.d.bits.data, 31, 24)
node _tl_d_data_encoded_T_18 = bits(nodeOut.d.bits.data, 39, 32)
node _tl_d_data_encoded_T_19 = bits(nodeOut.d.bits.data, 47, 40)
node _tl_d_data_encoded_T_20 = bits(nodeOut.d.bits.data, 55, 48)
node _tl_d_data_encoded_T_21 = bits(nodeOut.d.bits.data, 63, 56)
node tl_d_data_encoded_lo_lo_1 = cat(_tl_d_data_encoded_T_15, _tl_d_data_encoded_T_14)
node tl_d_data_encoded_lo_hi_1 = cat(_tl_d_data_encoded_T_17, _tl_d_data_encoded_T_16)
node tl_d_data_encoded_lo_1 = cat(tl_d_data_encoded_lo_hi_1, tl_d_data_encoded_lo_lo_1)
node tl_d_data_encoded_hi_lo_1 = cat(_tl_d_data_encoded_T_19, _tl_d_data_encoded_T_18)
node tl_d_data_encoded_hi_hi_1 = cat(_tl_d_data_encoded_T_21, _tl_d_data_encoded_T_20)
node tl_d_data_encoded_hi_1 = cat(tl_d_data_encoded_hi_hi_1, tl_d_data_encoded_hi_lo_1)
node _tl_d_data_encoded_T_22 = cat(tl_d_data_encoded_hi_1, tl_d_data_encoded_lo_1)
connect tl_d_data_encoded, _tl_d_data_encoded_T_22
node _grantIsCached_T = eq(d_opc, UInt<3>(0h4))
node _grantIsCached_T_1 = eq(d_opc, UInt<3>(0h5))
node grantIsCached = or(_grantIsCached_T, _grantIsCached_T_1)
node grantIsVoluntary = eq(d_opc, UInt<3>(0h6))
node grantIsRefill = eq(d_opc, UInt<3>(0h5))
regreset grantInProgress : UInt<1>, clock, reset, UInt<1>(0h0)
regreset blockProbeAfterGrantCount : UInt, clock, reset, UInt<1>(0h0)
node _T_73 = gt(blockProbeAfterGrantCount, UInt<1>(0h0))
when _T_73 :
node _blockProbeAfterGrantCount_T = sub(blockProbeAfterGrantCount, UInt<1>(0h1))
node _blockProbeAfterGrantCount_T_1 = tail(_blockProbeAfterGrantCount_T, 1)
connect blockProbeAfterGrantCount, _blockProbeAfterGrantCount_T_1
node _canAcceptCachedGrant_T = eq(release_state, UInt<4>(0h1))
node _canAcceptCachedGrant_T_1 = eq(release_state, UInt<4>(0h6))
node _canAcceptCachedGrant_T_2 = eq(release_state, UInt<4>(0h9))
node _canAcceptCachedGrant_T_3 = or(_canAcceptCachedGrant_T, _canAcceptCachedGrant_T_1)
node _canAcceptCachedGrant_T_4 = or(_canAcceptCachedGrant_T_3, _canAcceptCachedGrant_T_2)
node canAcceptCachedGrant = eq(_canAcceptCachedGrant_T_4, UInt<1>(0h0))
node _nodeOut_d_ready_T = eq(d_first, UInt<1>(0h0))
wire _nodeOut_d_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _nodeOut_d_ready_WIRE.bits.sink, UInt<1>(0h0)
connect _nodeOut_d_ready_WIRE.valid, UInt<1>(0h0)
connect _nodeOut_d_ready_WIRE.ready, UInt<1>(0h0)
wire _nodeOut_d_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _nodeOut_d_ready_WIRE_1.bits, _nodeOut_d_ready_WIRE.bits
connect _nodeOut_d_ready_WIRE_1.valid, _nodeOut_d_ready_WIRE.valid
connect _nodeOut_d_ready_WIRE_1.ready, _nodeOut_d_ready_WIRE.ready
node _nodeOut_d_ready_T_1 = or(_nodeOut_d_ready_T, _nodeOut_d_ready_WIRE_1.ready)
node _nodeOut_d_ready_T_2 = and(_nodeOut_d_ready_T_1, canAcceptCachedGrant)
node _nodeOut_d_ready_T_3 = mux(grantIsCached, _nodeOut_d_ready_T_2, UInt<1>(0h1))
connect nodeOut.d.ready, _nodeOut_d_ready_T_3
node uncachedRespIdxOH = shr(UInt<1>(0h1), 0)
node _uncachedResp_T = bits(uncachedRespIdxOH, 0, 0)
connect uncachedResp, uncachedReqs[0]
node _T_74 = and(nodeOut.d.ready, nodeOut.d.valid)
when _T_74 :
when grantIsCached :
connect grantInProgress, UInt<1>(0h1)
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(cached_grant_wait, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: A GrantData was unexpected by the dcache.\n at DCache.scala:677 assert(cached_grant_wait, \"A GrantData was unexpected by the dcache.\")\n") : printf_3
assert(clock, cached_grant_wait, UInt<1>(0h1), "") : assert_3
when d_last :
connect cached_grant_wait, UInt<1>(0h0)
connect grantInProgress, UInt<1>(0h0)
connect blockProbeAfterGrantCount, UInt<3>(0h7)
connect replace, UInt<1>(0h1)
else :
when UInt<1>(0h1) :
node _T_78 = bits(uncachedRespIdxOH, 0, 0)
node _T_79 = and(_T_78, d_last)
when _T_79 :
node _T_80 = asUInt(reset)
node _T_81 = eq(_T_80, UInt<1>(0h0))
when _T_81 :
node _T_82 = eq(uncachedInFlight[0], UInt<1>(0h0))
when _T_82 :
printf(clock, UInt<1>(0h1), "Assertion failed: An AccessAck was unexpected by the dcache.\n at DCache.scala:687 assert(f, \"An AccessAck was unexpected by the dcache.\") // TODO must handle Ack coming back on same cycle!\n") : printf_4
assert(clock, uncachedInFlight[0], UInt<1>(0h1), "") : assert_4
connect uncachedInFlight[0], UInt<1>(0h0)
when grantIsUncachedData :
node _s1_data_way_T = shl(UInt<1>(0h1), 1)
connect s1_data_way, _s1_data_way_T
connect s2_req.cmd, UInt<1>(0h0)
connect s2_req.size, uncachedResp.size
connect s2_req.signed, uncachedResp.signed
connect s2_req.tag, uncachedResp.tag
node _s2_req_addr_dontCareBits_T = shr(s1_paddr, 3)
node s2_req_addr_dontCareBits = shl(_s2_req_addr_dontCareBits_T, 3)
node _s2_req_addr_T = bits(uncachedResp.addr, 2, 0)
node _s2_req_addr_T_1 = or(s2_req_addr_dontCareBits, _s2_req_addr_T)
connect s2_req.addr, _s2_req_addr_T_1
connect s2_uncached_resp_addr, uncachedResp.addr
else :
when grantIsVoluntary :
node _T_83 = asUInt(reset)
node _T_84 = eq(_T_83, UInt<1>(0h0))
when _T_84 :
node _T_85 = eq(release_ack_wait, UInt<1>(0h0))
when _T_85 :
printf(clock, UInt<1>(0h1), "Assertion failed: A ReleaseAck was unexpected by the dcache.\n at DCache.scala:708 assert(release_ack_wait, \"A ReleaseAck was unexpected by the dcache.\") // TODO should handle Ack coming back on same cycle!\n") : printf_5
assert(clock, release_ack_wait, UInt<1>(0h1), "") : assert_5
connect release_ack_wait, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_1.bits.sink, UInt<1>(0h0)
connect _WIRE_1.valid, UInt<1>(0h0)
connect _WIRE_1.ready, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_2.bits, _WIRE_1.bits
connect _WIRE_2.valid, _WIRE_1.valid
connect _WIRE_2.ready, _WIRE_1.ready
node _T_86 = and(nodeOut.d.valid, d_first)
node _T_87 = and(_T_86, grantIsCached)
node _T_88 = and(_T_87, canAcceptCachedGrant)
connect _WIRE_2.valid, _T_88
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_3.bits.sink, UInt<1>(0h0)
connect _WIRE_3.valid, UInt<1>(0h0)
connect _WIRE_3.ready, UInt<1>(0h0)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits, _WIRE_3.bits
connect _WIRE_4.valid, _WIRE_3.valid
connect _WIRE_4.ready, _WIRE_3.ready
wire e : { sink : UInt<1>}
connect e.sink, nodeOut.d.bits.sink
connect _WIRE_4.bits, e
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits.sink, UInt<1>(0h0)
connect _WIRE_5.valid, UInt<1>(0h0)
connect _WIRE_5.ready, UInt<1>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_6.bits, _WIRE_5.bits
connect _WIRE_6.valid, _WIRE_5.valid
connect _WIRE_6.ready, _WIRE_5.ready
node _T_89 = and(_WIRE_6.ready, _WIRE_6.valid)
node _T_90 = and(nodeOut.d.ready, nodeOut.d.valid)
node _T_91 = and(_T_90, d_first)
node _T_92 = and(_T_91, grantIsCached)
node _T_93 = eq(_T_89, _T_92)
node _T_94 = asUInt(reset)
node _T_95 = eq(_T_94, UInt<1>(0h0))
when _T_95 :
node _T_96 = eq(_T_93, UInt<1>(0h0))
when _T_96 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at DCache.scala:716 assert(tl_out.e.fire === (tl_out.d.fire && d_first && grantIsCached))\n") : printf_6
assert(clock, _T_93, UInt<1>(0h1), "") : assert_6
node _dataArb_io_in_1_valid_T = and(nodeOut.d.valid, grantIsRefill)
node _dataArb_io_in_1_valid_T_1 = and(_dataArb_io_in_1_valid_T, canAcceptCachedGrant)
connect dataArb.io.in[1].valid, _dataArb_io_in_1_valid_T_1
node _T_97 = eq(dataArb.io.in[1].ready, UInt<1>(0h0))
node _T_98 = and(grantIsRefill, _T_97)
when _T_98 :
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_7.bits.sink, UInt<1>(0h0)
connect _WIRE_7.valid, UInt<1>(0h0)
connect _WIRE_7.ready, UInt<1>(0h0)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits, _WIRE_7.bits
connect _WIRE_8.valid, _WIRE_7.valid
connect _WIRE_8.ready, _WIRE_7.ready
connect _WIRE_8.valid, UInt<1>(0h0)
connect nodeOut.d.ready, UInt<1>(0h0)
connect dataArb.io.in[1].bits.way_en, dataArb.io.in[0].bits.way_en
connect dataArb.io.in[1].bits.eccMask, dataArb.io.in[0].bits.eccMask
connect dataArb.io.in[1].bits.wordMask, dataArb.io.in[0].bits.wordMask
connect dataArb.io.in[1].bits.wdata, dataArb.io.in[0].bits.wdata
connect dataArb.io.in[1].bits.write, dataArb.io.in[0].bits.write
connect dataArb.io.in[1].bits.addr, dataArb.io.in[0].bits.addr
node _metaArb_io_in_3_valid_T = and(grantIsCached, d_done)
node _metaArb_io_in_3_valid_T_1 = eq(nodeOut.d.bits.denied, UInt<1>(0h0))
node _metaArb_io_in_3_valid_T_2 = and(_metaArb_io_in_3_valid_T, _metaArb_io_in_3_valid_T_1)
connect metaArb.io.in[3].valid, _metaArb_io_in_3_valid_T_2
connect metaArb.io.in[3].bits.write, UInt<1>(0h1)
connect metaArb.io.in[3].bits.way_en, refill_way
node _metaArb_io_in_3_bits_idx_T = bits(s2_vaddr, 13, 6)
connect metaArb.io.in[3].bits.idx, _metaArb_io_in_3_bits_idx_T
node _metaArb_io_in_3_bits_addr_T = shr(io.cpu.req.bits.addr, 14)
node _metaArb_io_in_3_bits_addr_T_1 = bits(s2_vaddr, 13, 0)
node _metaArb_io_in_3_bits_addr_T_2 = cat(_metaArb_io_in_3_bits_addr_T, _metaArb_io_in_3_bits_addr_T_1)
connect metaArb.io.in[3].bits.addr, _metaArb_io_in_3_bits_addr_T_2
node _metaArb_io_in_3_bits_data_T = shr(s2_req.addr, 14)
node _metaArb_io_in_3_bits_data_c_cat_T = eq(s2_req.cmd, UInt<1>(0h1))
node _metaArb_io_in_3_bits_data_c_cat_T_1 = eq(s2_req.cmd, UInt<5>(0h11))
node _metaArb_io_in_3_bits_data_c_cat_T_2 = or(_metaArb_io_in_3_bits_data_c_cat_T, _metaArb_io_in_3_bits_data_c_cat_T_1)
node _metaArb_io_in_3_bits_data_c_cat_T_3 = eq(s2_req.cmd, UInt<3>(0h7))
node _metaArb_io_in_3_bits_data_c_cat_T_4 = or(_metaArb_io_in_3_bits_data_c_cat_T_2, _metaArb_io_in_3_bits_data_c_cat_T_3)
node _metaArb_io_in_3_bits_data_c_cat_T_5 = eq(s2_req.cmd, UInt<3>(0h4))
node _metaArb_io_in_3_bits_data_c_cat_T_6 = eq(s2_req.cmd, UInt<4>(0h9))
node _metaArb_io_in_3_bits_data_c_cat_T_7 = eq(s2_req.cmd, UInt<4>(0ha))
node _metaArb_io_in_3_bits_data_c_cat_T_8 = eq(s2_req.cmd, UInt<4>(0hb))
node _metaArb_io_in_3_bits_data_c_cat_T_9 = or(_metaArb_io_in_3_bits_data_c_cat_T_5, _metaArb_io_in_3_bits_data_c_cat_T_6)
node _metaArb_io_in_3_bits_data_c_cat_T_10 = or(_metaArb_io_in_3_bits_data_c_cat_T_9, _metaArb_io_in_3_bits_data_c_cat_T_7)
node _metaArb_io_in_3_bits_data_c_cat_T_11 = or(_metaArb_io_in_3_bits_data_c_cat_T_10, _metaArb_io_in_3_bits_data_c_cat_T_8)
node _metaArb_io_in_3_bits_data_c_cat_T_12 = eq(s2_req.cmd, UInt<4>(0h8))
node _metaArb_io_in_3_bits_data_c_cat_T_13 = eq(s2_req.cmd, UInt<4>(0hc))
node _metaArb_io_in_3_bits_data_c_cat_T_14 = eq(s2_req.cmd, UInt<4>(0hd))
node _metaArb_io_in_3_bits_data_c_cat_T_15 = eq(s2_req.cmd, UInt<4>(0he))
node _metaArb_io_in_3_bits_data_c_cat_T_16 = eq(s2_req.cmd, UInt<4>(0hf))
node _metaArb_io_in_3_bits_data_c_cat_T_17 = or(_metaArb_io_in_3_bits_data_c_cat_T_12, _metaArb_io_in_3_bits_data_c_cat_T_13)
node _metaArb_io_in_3_bits_data_c_cat_T_18 = or(_metaArb_io_in_3_bits_data_c_cat_T_17, _metaArb_io_in_3_bits_data_c_cat_T_14)
node _metaArb_io_in_3_bits_data_c_cat_T_19 = or(_metaArb_io_in_3_bits_data_c_cat_T_18, _metaArb_io_in_3_bits_data_c_cat_T_15)
node _metaArb_io_in_3_bits_data_c_cat_T_20 = or(_metaArb_io_in_3_bits_data_c_cat_T_19, _metaArb_io_in_3_bits_data_c_cat_T_16)
node _metaArb_io_in_3_bits_data_c_cat_T_21 = or(_metaArb_io_in_3_bits_data_c_cat_T_11, _metaArb_io_in_3_bits_data_c_cat_T_20)
node _metaArb_io_in_3_bits_data_c_cat_T_22 = or(_metaArb_io_in_3_bits_data_c_cat_T_4, _metaArb_io_in_3_bits_data_c_cat_T_21)
node _metaArb_io_in_3_bits_data_c_cat_T_23 = eq(s2_req.cmd, UInt<1>(0h1))
node _metaArb_io_in_3_bits_data_c_cat_T_24 = eq(s2_req.cmd, UInt<5>(0h11))
node _metaArb_io_in_3_bits_data_c_cat_T_25 = or(_metaArb_io_in_3_bits_data_c_cat_T_23, _metaArb_io_in_3_bits_data_c_cat_T_24)
node _metaArb_io_in_3_bits_data_c_cat_T_26 = eq(s2_req.cmd, UInt<3>(0h7))
node _metaArb_io_in_3_bits_data_c_cat_T_27 = or(_metaArb_io_in_3_bits_data_c_cat_T_25, _metaArb_io_in_3_bits_data_c_cat_T_26)
node _metaArb_io_in_3_bits_data_c_cat_T_28 = eq(s2_req.cmd, UInt<3>(0h4))
node _metaArb_io_in_3_bits_data_c_cat_T_29 = eq(s2_req.cmd, UInt<4>(0h9))
node _metaArb_io_in_3_bits_data_c_cat_T_30 = eq(s2_req.cmd, UInt<4>(0ha))
node _metaArb_io_in_3_bits_data_c_cat_T_31 = eq(s2_req.cmd, UInt<4>(0hb))
node _metaArb_io_in_3_bits_data_c_cat_T_32 = or(_metaArb_io_in_3_bits_data_c_cat_T_28, _metaArb_io_in_3_bits_data_c_cat_T_29)
node _metaArb_io_in_3_bits_data_c_cat_T_33 = or(_metaArb_io_in_3_bits_data_c_cat_T_32, _metaArb_io_in_3_bits_data_c_cat_T_30)
node _metaArb_io_in_3_bits_data_c_cat_T_34 = or(_metaArb_io_in_3_bits_data_c_cat_T_33, _metaArb_io_in_3_bits_data_c_cat_T_31)
node _metaArb_io_in_3_bits_data_c_cat_T_35 = eq(s2_req.cmd, UInt<4>(0h8))
node _metaArb_io_in_3_bits_data_c_cat_T_36 = eq(s2_req.cmd, UInt<4>(0hc))
node _metaArb_io_in_3_bits_data_c_cat_T_37 = eq(s2_req.cmd, UInt<4>(0hd))
node _metaArb_io_in_3_bits_data_c_cat_T_38 = eq(s2_req.cmd, UInt<4>(0he))
node _metaArb_io_in_3_bits_data_c_cat_T_39 = eq(s2_req.cmd, UInt<4>(0hf))
node _metaArb_io_in_3_bits_data_c_cat_T_40 = or(_metaArb_io_in_3_bits_data_c_cat_T_35, _metaArb_io_in_3_bits_data_c_cat_T_36)
node _metaArb_io_in_3_bits_data_c_cat_T_41 = or(_metaArb_io_in_3_bits_data_c_cat_T_40, _metaArb_io_in_3_bits_data_c_cat_T_37)
node _metaArb_io_in_3_bits_data_c_cat_T_42 = or(_metaArb_io_in_3_bits_data_c_cat_T_41, _metaArb_io_in_3_bits_data_c_cat_T_38)
node _metaArb_io_in_3_bits_data_c_cat_T_43 = or(_metaArb_io_in_3_bits_data_c_cat_T_42, _metaArb_io_in_3_bits_data_c_cat_T_39)
node _metaArb_io_in_3_bits_data_c_cat_T_44 = or(_metaArb_io_in_3_bits_data_c_cat_T_34, _metaArb_io_in_3_bits_data_c_cat_T_43)
node _metaArb_io_in_3_bits_data_c_cat_T_45 = or(_metaArb_io_in_3_bits_data_c_cat_T_27, _metaArb_io_in_3_bits_data_c_cat_T_44)
node _metaArb_io_in_3_bits_data_c_cat_T_46 = eq(s2_req.cmd, UInt<2>(0h3))
node _metaArb_io_in_3_bits_data_c_cat_T_47 = or(_metaArb_io_in_3_bits_data_c_cat_T_45, _metaArb_io_in_3_bits_data_c_cat_T_46)
node _metaArb_io_in_3_bits_data_c_cat_T_48 = eq(s2_req.cmd, UInt<3>(0h6))
node _metaArb_io_in_3_bits_data_c_cat_T_49 = or(_metaArb_io_in_3_bits_data_c_cat_T_47, _metaArb_io_in_3_bits_data_c_cat_T_48)
node metaArb_io_in_3_bits_data_c = cat(_metaArb_io_in_3_bits_data_c_cat_T_22, _metaArb_io_in_3_bits_data_c_cat_T_49)
node _metaArb_io_in_3_bits_data_T_1 = cat(metaArb_io_in_3_bits_data_c, nodeOut.d.bits.param)
node _metaArb_io_in_3_bits_data_T_2 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _metaArb_io_in_3_bits_data_T_3 = cat(_metaArb_io_in_3_bits_data_T_2, UInt<2>(0h1))
node _metaArb_io_in_3_bits_data_T_4 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _metaArb_io_in_3_bits_data_T_5 = cat(_metaArb_io_in_3_bits_data_T_4, UInt<2>(0h0))
node _metaArb_io_in_3_bits_data_T_6 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _metaArb_io_in_3_bits_data_T_7 = cat(_metaArb_io_in_3_bits_data_T_6, UInt<2>(0h0))
node _metaArb_io_in_3_bits_data_T_8 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _metaArb_io_in_3_bits_data_T_9 = cat(_metaArb_io_in_3_bits_data_T_8, UInt<2>(0h0))
node _metaArb_io_in_3_bits_data_T_10 = eq(_metaArb_io_in_3_bits_data_T_3, _metaArb_io_in_3_bits_data_T_1)
node _metaArb_io_in_3_bits_data_T_11 = mux(_metaArb_io_in_3_bits_data_T_10, UInt<2>(0h1), UInt<2>(0h0))
node _metaArb_io_in_3_bits_data_T_12 = eq(_metaArb_io_in_3_bits_data_T_5, _metaArb_io_in_3_bits_data_T_1)
node _metaArb_io_in_3_bits_data_T_13 = mux(_metaArb_io_in_3_bits_data_T_12, UInt<2>(0h2), _metaArb_io_in_3_bits_data_T_11)
node _metaArb_io_in_3_bits_data_T_14 = eq(_metaArb_io_in_3_bits_data_T_7, _metaArb_io_in_3_bits_data_T_1)
node _metaArb_io_in_3_bits_data_T_15 = mux(_metaArb_io_in_3_bits_data_T_14, UInt<2>(0h2), _metaArb_io_in_3_bits_data_T_13)
node _metaArb_io_in_3_bits_data_T_16 = eq(_metaArb_io_in_3_bits_data_T_9, _metaArb_io_in_3_bits_data_T_1)
node _metaArb_io_in_3_bits_data_T_17 = mux(_metaArb_io_in_3_bits_data_T_16, UInt<2>(0h3), _metaArb_io_in_3_bits_data_T_15)
wire metaArb_io_in_3_bits_data_meta : { state : UInt<2>}
connect metaArb_io_in_3_bits_data_meta.state, _metaArb_io_in_3_bits_data_T_17
wire metaArb_io_in_3_bits_data_meta_1 : { coh : { state : UInt<2>}, tag : UInt<18>}
connect metaArb_io_in_3_bits_data_meta_1.tag, _metaArb_io_in_3_bits_data_T
connect metaArb_io_in_3_bits_data_meta_1.coh, metaArb_io_in_3_bits_data_meta
node _metaArb_io_in_3_bits_data_T_18 = cat(metaArb_io_in_3_bits_data_meta_1.coh.state, metaArb_io_in_3_bits_data_meta_1.tag)
connect metaArb.io.in[3].bits.data, _metaArb_io_in_3_bits_data_T_18
reg blockUncachedGrant : UInt<1>, clock
connect blockUncachedGrant, dataArb.io.out.valid
node _T_99 = or(blockUncachedGrant, s1_valid)
node _T_100 = and(grantIsUncachedData, _T_99)
when _T_100 :
connect nodeOut.d.ready, UInt<1>(0h0)
when nodeOut.d.valid :
connect io.cpu.req.ready, UInt<1>(0h0)
connect dataArb.io.in[1].valid, UInt<1>(0h1)
connect dataArb.io.in[1].bits.write, UInt<1>(0h0)
node _blockUncachedGrant_T = eq(dataArb.io.in[1].ready, UInt<1>(0h0))
connect blockUncachedGrant, _blockUncachedGrant_T
node _T_101 = eq(nodeOut.d.ready, UInt<1>(0h0))
node _T_102 = and(nodeOut.d.valid, _T_101)
node _block_probe_for_core_progress_T = gt(blockProbeAfterGrantCount, UInt<1>(0h0))
node block_probe_for_core_progress = or(_block_probe_for_core_progress_T, lrscValid)
wire _block_probe_for_pending_release_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _block_probe_for_pending_release_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _block_probe_for_pending_release_ack_WIRE.bits.data, UInt<64>(0h0)
connect _block_probe_for_pending_release_ack_WIRE.bits.mask, UInt<8>(0h0)
connect _block_probe_for_pending_release_ack_WIRE.bits.address, UInt<32>(0h0)
connect _block_probe_for_pending_release_ack_WIRE.bits.source, UInt<1>(0h0)
connect _block_probe_for_pending_release_ack_WIRE.bits.size, UInt<4>(0h0)
connect _block_probe_for_pending_release_ack_WIRE.bits.param, UInt<2>(0h0)
connect _block_probe_for_pending_release_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _block_probe_for_pending_release_ack_WIRE.valid, UInt<1>(0h0)
connect _block_probe_for_pending_release_ack_WIRE.ready, UInt<1>(0h0)
wire _block_probe_for_pending_release_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _block_probe_for_pending_release_ack_WIRE_1.bits, _block_probe_for_pending_release_ack_WIRE.bits
connect _block_probe_for_pending_release_ack_WIRE_1.valid, _block_probe_for_pending_release_ack_WIRE.valid
connect _block_probe_for_pending_release_ack_WIRE_1.ready, _block_probe_for_pending_release_ack_WIRE.ready
node _block_probe_for_pending_release_ack_T = xor(_block_probe_for_pending_release_ack_WIRE_1.bits.address, release_ack_addr)
node _block_probe_for_pending_release_ack_T_1 = bits(_block_probe_for_pending_release_ack_T, 20, 6)
node _block_probe_for_pending_release_ack_T_2 = eq(_block_probe_for_pending_release_ack_T_1, UInt<1>(0h0))
node block_probe_for_pending_release_ack = and(release_ack_wait, _block_probe_for_pending_release_ack_T_2)
node _block_probe_for_ordering_T = or(releaseInFlight, block_probe_for_pending_release_ack)
node block_probe_for_ordering = or(_block_probe_for_ordering_T, grantInProgress)
wire _metaArb_io_in_6_valid_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _metaArb_io_in_6_valid_WIRE.bits.corrupt, UInt<1>(0h0)
connect _metaArb_io_in_6_valid_WIRE.bits.data, UInt<64>(0h0)
connect _metaArb_io_in_6_valid_WIRE.bits.mask, UInt<8>(0h0)
connect _metaArb_io_in_6_valid_WIRE.bits.address, UInt<32>(0h0)
connect _metaArb_io_in_6_valid_WIRE.bits.source, UInt<1>(0h0)
connect _metaArb_io_in_6_valid_WIRE.bits.size, UInt<4>(0h0)
connect _metaArb_io_in_6_valid_WIRE.bits.param, UInt<2>(0h0)
connect _metaArb_io_in_6_valid_WIRE.bits.opcode, UInt<3>(0h0)
connect _metaArb_io_in_6_valid_WIRE.valid, UInt<1>(0h0)
connect _metaArb_io_in_6_valid_WIRE.ready, UInt<1>(0h0)
wire _metaArb_io_in_6_valid_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _metaArb_io_in_6_valid_WIRE_1.bits, _metaArb_io_in_6_valid_WIRE.bits
connect _metaArb_io_in_6_valid_WIRE_1.valid, _metaArb_io_in_6_valid_WIRE.valid
connect _metaArb_io_in_6_valid_WIRE_1.ready, _metaArb_io_in_6_valid_WIRE.ready
node _metaArb_io_in_6_valid_T = eq(block_probe_for_core_progress, UInt<1>(0h0))
node _metaArb_io_in_6_valid_T_1 = or(_metaArb_io_in_6_valid_T, lrscBackingOff)
node _metaArb_io_in_6_valid_T_2 = and(_metaArb_io_in_6_valid_WIRE_1.valid, _metaArb_io_in_6_valid_T_1)
connect metaArb.io.in[6].valid, _metaArb_io_in_6_valid_T_2
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits.corrupt, UInt<1>(0h0)
connect _WIRE_9.bits.data, UInt<64>(0h0)
connect _WIRE_9.bits.mask, UInt<8>(0h0)
connect _WIRE_9.bits.address, UInt<32>(0h0)
connect _WIRE_9.bits.source, UInt<1>(0h0)
connect _WIRE_9.bits.size, UInt<4>(0h0)
connect _WIRE_9.bits.param, UInt<2>(0h0)
connect _WIRE_9.bits.opcode, UInt<3>(0h0)
connect _WIRE_9.valid, UInt<1>(0h0)
connect _WIRE_9.ready, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits, _WIRE_9.bits
connect _WIRE_10.valid, _WIRE_9.valid
connect _WIRE_10.ready, _WIRE_9.ready
node _T_103 = or(block_probe_for_core_progress, block_probe_for_ordering)
node _T_104 = or(_T_103, s1_valid)
node _T_105 = or(_T_104, s2_valid)
node _T_106 = eq(_T_105, UInt<1>(0h0))
node _T_107 = and(metaArb.io.in[6].ready, _T_106)
connect _WIRE_10.ready, _T_107
connect metaArb.io.in[6].bits.write, UInt<1>(0h0)
wire _metaArb_io_in_6_bits_idx_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _metaArb_io_in_6_bits_idx_WIRE.bits.corrupt, UInt<1>(0h0)
connect _metaArb_io_in_6_bits_idx_WIRE.bits.data, UInt<64>(0h0)
connect _metaArb_io_in_6_bits_idx_WIRE.bits.mask, UInt<8>(0h0)
connect _metaArb_io_in_6_bits_idx_WIRE.bits.address, UInt<32>(0h0)
connect _metaArb_io_in_6_bits_idx_WIRE.bits.source, UInt<1>(0h0)
connect _metaArb_io_in_6_bits_idx_WIRE.bits.size, UInt<4>(0h0)
connect _metaArb_io_in_6_bits_idx_WIRE.bits.param, UInt<2>(0h0)
connect _metaArb_io_in_6_bits_idx_WIRE.bits.opcode, UInt<3>(0h0)
connect _metaArb_io_in_6_bits_idx_WIRE.valid, UInt<1>(0h0)
connect _metaArb_io_in_6_bits_idx_WIRE.ready, UInt<1>(0h0)
wire _metaArb_io_in_6_bits_idx_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _metaArb_io_in_6_bits_idx_WIRE_1.bits, _metaArb_io_in_6_bits_idx_WIRE.bits
connect _metaArb_io_in_6_bits_idx_WIRE_1.valid, _metaArb_io_in_6_bits_idx_WIRE.valid
connect _metaArb_io_in_6_bits_idx_WIRE_1.ready, _metaArb_io_in_6_bits_idx_WIRE.ready
node _metaArb_io_in_6_bits_idx_T = bits(_metaArb_io_in_6_bits_idx_WIRE_1.bits.address, 13, 6)
connect metaArb.io.in[6].bits.idx, _metaArb_io_in_6_bits_idx_T
node _metaArb_io_in_6_bits_addr_T = shr(io.cpu.req.bits.addr, 32)
wire _metaArb_io_in_6_bits_addr_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _metaArb_io_in_6_bits_addr_WIRE.bits.corrupt, UInt<1>(0h0)
connect _metaArb_io_in_6_bits_addr_WIRE.bits.data, UInt<64>(0h0)
connect _metaArb_io_in_6_bits_addr_WIRE.bits.mask, UInt<8>(0h0)
connect _metaArb_io_in_6_bits_addr_WIRE.bits.address, UInt<32>(0h0)
connect _metaArb_io_in_6_bits_addr_WIRE.bits.source, UInt<1>(0h0)
connect _metaArb_io_in_6_bits_addr_WIRE.bits.size, UInt<4>(0h0)
connect _metaArb_io_in_6_bits_addr_WIRE.bits.param, UInt<2>(0h0)
connect _metaArb_io_in_6_bits_addr_WIRE.bits.opcode, UInt<3>(0h0)
connect _metaArb_io_in_6_bits_addr_WIRE.valid, UInt<1>(0h0)
connect _metaArb_io_in_6_bits_addr_WIRE.ready, UInt<1>(0h0)
wire _metaArb_io_in_6_bits_addr_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _metaArb_io_in_6_bits_addr_WIRE_1.bits, _metaArb_io_in_6_bits_addr_WIRE.bits
connect _metaArb_io_in_6_bits_addr_WIRE_1.valid, _metaArb_io_in_6_bits_addr_WIRE.valid
connect _metaArb_io_in_6_bits_addr_WIRE_1.ready, _metaArb_io_in_6_bits_addr_WIRE.ready
node _metaArb_io_in_6_bits_addr_T_1 = cat(_metaArb_io_in_6_bits_addr_T, _metaArb_io_in_6_bits_addr_WIRE_1.bits.address)
connect metaArb.io.in[6].bits.addr, _metaArb_io_in_6_bits_addr_T_1
connect metaArb.io.in[6].bits.way_en, metaArb.io.in[4].bits.way_en
connect metaArb.io.in[6].bits.data, metaArb.io.in[4].bits.data
connect s1_victim_way, UInt<1>(0h0)
node _T_108 = and(tl_out_c.ready, tl_out_c.valid)
node _r_beats1_decode_T_3 = dshl(UInt<12>(0hfff), tl_out_c.bits.size)
node _r_beats1_decode_T_4 = bits(_r_beats1_decode_T_3, 11, 0)
node _r_beats1_decode_T_5 = not(_r_beats1_decode_T_4)
node r_beats1_decode_1 = shr(_r_beats1_decode_T_5, 3)
node r_beats1_opdata_1 = bits(tl_out_c.bits.opcode, 0, 0)
node r_beats1_1 = mux(UInt<1>(0h0), r_beats1_decode_1, UInt<1>(0h0))
regreset r_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _r_counter1_T_1 = sub(r_counter_1, UInt<1>(0h1))
node r_counter1_1 = tail(_r_counter1_T_1, 1)
node c_first = eq(r_counter_1, UInt<1>(0h0))
node _r_last_T_2 = eq(r_counter_1, UInt<1>(0h1))
node _r_last_T_3 = eq(r_beats1_1, UInt<1>(0h0))
node c_last = or(_r_last_T_2, _r_last_T_3)
node releaseDone = and(c_last, _T_108)
node _r_count_T_1 = not(r_counter1_1)
node c_count = and(r_beats1_1, _r_count_T_1)
when _T_108 :
node _r_counter_T_1 = mux(c_first, r_beats1_1, r_counter1_1)
connect r_counter_1, _r_counter_T_1
wire releaseRejected : UInt<1>
node _s1_release_data_valid_T = and(dataArb.io.in[2].ready, dataArb.io.in[2].valid)
reg s1_release_data_valid : UInt<1>, clock
connect s1_release_data_valid, _s1_release_data_valid_T
node _s2_release_data_valid_T = eq(releaseRejected, UInt<1>(0h0))
node _s2_release_data_valid_T_1 = and(s1_release_data_valid, _s2_release_data_valid_T)
reg s2_release_data_valid : UInt<1>, clock
connect s2_release_data_valid, _s2_release_data_valid_T_1
node _releaseRejected_T = and(tl_out_c.ready, tl_out_c.valid)
node _releaseRejected_T_1 = eq(_releaseRejected_T, UInt<1>(0h0))
node _releaseRejected_T_2 = and(s2_release_data_valid, _releaseRejected_T_1)
connect releaseRejected, _releaseRejected_T_2
node _releaseDataBeat_T = cat(UInt<1>(0h0), c_count)
node _releaseDataBeat_T_1 = cat(UInt<1>(0h0), s2_release_data_valid)
node _releaseDataBeat_T_2 = add(s1_release_data_valid, _releaseDataBeat_T_1)
node _releaseDataBeat_T_3 = tail(_releaseDataBeat_T_2, 1)
node _releaseDataBeat_T_4 = mux(releaseRejected, UInt<1>(0h0), _releaseDataBeat_T_3)
node _releaseDataBeat_T_5 = add(_releaseDataBeat_T, _releaseDataBeat_T_4)
node releaseDataBeat = tail(_releaseDataBeat_T_5, 1)
wire nackResponseMessage : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect nackResponseMessage.opcode, UInt<3>(0h4)
connect nackResponseMessage.param, UInt<3>(0h5)
connect nackResponseMessage.size, probe_bits.size
connect nackResponseMessage.source, probe_bits.source
connect nackResponseMessage.address, probe_bits.address
invalidate nackResponseMessage.user.amba_prot.fetch
invalidate nackResponseMessage.user.amba_prot.secure
invalidate nackResponseMessage.user.amba_prot.privileged
invalidate nackResponseMessage.user.amba_prot.writealloc
invalidate nackResponseMessage.user.amba_prot.readalloc
invalidate nackResponseMessage.user.amba_prot.modifiable
invalidate nackResponseMessage.user.amba_prot.bufferable
invalidate nackResponseMessage.data
connect nackResponseMessage.corrupt, UInt<1>(0h0)
wire cleanReleaseMessage : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect cleanReleaseMessage.opcode, UInt<3>(0h4)
connect cleanReleaseMessage.param, s2_report_param
connect cleanReleaseMessage.size, probe_bits.size
connect cleanReleaseMessage.source, probe_bits.source
connect cleanReleaseMessage.address, probe_bits.address
invalidate cleanReleaseMessage.user.amba_prot.fetch
invalidate cleanReleaseMessage.user.amba_prot.secure
invalidate cleanReleaseMessage.user.amba_prot.privileged
invalidate cleanReleaseMessage.user.amba_prot.writealloc
invalidate cleanReleaseMessage.user.amba_prot.readalloc
invalidate cleanReleaseMessage.user.amba_prot.modifiable
invalidate cleanReleaseMessage.user.amba_prot.bufferable
invalidate cleanReleaseMessage.data
connect cleanReleaseMessage.corrupt, UInt<1>(0h0)
wire dirtyReleaseMessage : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<64>, corrupt : UInt<1>}
connect dirtyReleaseMessage.opcode, UInt<3>(0h5)
connect dirtyReleaseMessage.param, s2_report_param
connect dirtyReleaseMessage.size, probe_bits.size
connect dirtyReleaseMessage.source, probe_bits.source
connect dirtyReleaseMessage.address, probe_bits.address
invalidate dirtyReleaseMessage.user.amba_prot.fetch
invalidate dirtyReleaseMessage.user.amba_prot.secure
invalidate dirtyReleaseMessage.user.amba_prot.privileged
invalidate dirtyReleaseMessage.user.amba_prot.writealloc
invalidate dirtyReleaseMessage.user.amba_prot.readalloc
invalidate dirtyReleaseMessage.user.amba_prot.modifiable
invalidate dirtyReleaseMessage.user.amba_prot.bufferable
connect dirtyReleaseMessage.data, UInt<1>(0h0)
connect dirtyReleaseMessage.corrupt, UInt<1>(0h0)
node _tl_out_c_valid_T = eq(UInt<1>(0h1), UInt<1>(0h0))
node _tl_out_c_valid_T_1 = eq(release_state, UInt<4>(0h9))
node _tl_out_c_valid_T_2 = and(_tl_out_c_valid_T, _tl_out_c_valid_T_1)
node _tl_out_c_valid_T_3 = or(s2_release_data_valid, _tl_out_c_valid_T_2)
node _tl_out_c_valid_T_4 = and(c_first, release_ack_wait)
node _tl_out_c_valid_T_5 = eq(_tl_out_c_valid_T_4, UInt<1>(0h0))
node _tl_out_c_valid_T_6 = and(_tl_out_c_valid_T_3, _tl_out_c_valid_T_5)
connect tl_out_c.valid, _tl_out_c_valid_T_6
connect tl_out_c.bits, nackResponseMessage
wire newCoh : { state : UInt<2>}
connect newCoh, probeNewCoh
connect releaseWay, s2_probe_way
connect tl_out_c.bits.user.amba_prot.fetch, UInt<1>(0h0)
connect tl_out_c.bits.user.amba_prot.secure, UInt<1>(0h1)
connect tl_out_c.bits.user.amba_prot.privileged, UInt<1>(0h1)
connect tl_out_c.bits.user.amba_prot.bufferable, UInt<1>(0h1)
connect tl_out_c.bits.user.amba_prot.modifiable, UInt<1>(0h1)
connect tl_out_c.bits.user.amba_prot.readalloc, UInt<1>(0h1)
connect tl_out_c.bits.user.amba_prot.writealloc, UInt<1>(0h1)
node _dataArb_io_in_2_valid_T = lt(releaseDataBeat, UInt<4>(0h8))
node _dataArb_io_in_2_valid_T_1 = and(inWriteback, _dataArb_io_in_2_valid_T)
connect dataArb.io.in[2].valid, _dataArb_io_in_2_valid_T_1
connect dataArb.io.in[2].bits.way_en, dataArb.io.in[1].bits.way_en
connect dataArb.io.in[2].bits.eccMask, dataArb.io.in[1].bits.eccMask
connect dataArb.io.in[2].bits.wordMask, dataArb.io.in[1].bits.wordMask
connect dataArb.io.in[2].bits.wdata, dataArb.io.in[1].bits.wdata
connect dataArb.io.in[2].bits.write, dataArb.io.in[1].bits.write
connect dataArb.io.in[2].bits.addr, dataArb.io.in[1].bits.addr
connect dataArb.io.in[2].bits.write, UInt<1>(0h0)
node _dataArb_io_in_2_bits_addr_T = bits(probe_bits.address, 13, 6)
node _dataArb_io_in_2_bits_addr_T_1 = shl(_dataArb_io_in_2_bits_addr_T, 6)
node _dataArb_io_in_2_bits_addr_T_2 = bits(releaseDataBeat, 2, 0)
node _dataArb_io_in_2_bits_addr_T_3 = shl(_dataArb_io_in_2_bits_addr_T_2, 3)
node _dataArb_io_in_2_bits_addr_T_4 = or(_dataArb_io_in_2_bits_addr_T_1, _dataArb_io_in_2_bits_addr_T_3)
connect dataArb.io.in[2].bits.addr, _dataArb_io_in_2_bits_addr_T_4
node _dataArb_io_in_2_bits_wordMask_T = not(UInt<1>(0h0))
connect dataArb.io.in[2].bits.wordMask, _dataArb_io_in_2_bits_wordMask_T
node _dataArb_io_in_2_bits_eccMask_T = not(UInt<8>(0h0))
connect dataArb.io.in[2].bits.eccMask, _dataArb_io_in_2_bits_eccMask_T
node _dataArb_io_in_2_bits_way_en_T = not(UInt<1>(0h0))
connect dataArb.io.in[2].bits.way_en, _dataArb_io_in_2_bits_way_en_T
node _metaArb_io_in_4_valid_T = eq(release_state, UInt<4>(0h6))
node _metaArb_io_in_4_valid_T_1 = eq(release_state, UInt<4>(0h7))
node _metaArb_io_in_4_valid_T_2 = or(_metaArb_io_in_4_valid_T, _metaArb_io_in_4_valid_T_1)
connect metaArb.io.in[4].valid, _metaArb_io_in_4_valid_T_2
connect metaArb.io.in[4].bits.write, UInt<1>(0h1)
connect metaArb.io.in[4].bits.way_en, releaseWay
node _metaArb_io_in_4_bits_idx_T = bits(probe_bits.address, 13, 6)
connect metaArb.io.in[4].bits.idx, _metaArb_io_in_4_bits_idx_T
node _metaArb_io_in_4_bits_addr_T = shr(io.cpu.req.bits.addr, 14)
node _metaArb_io_in_4_bits_addr_T_1 = bits(probe_bits.address, 13, 0)
node _metaArb_io_in_4_bits_addr_T_2 = cat(_metaArb_io_in_4_bits_addr_T, _metaArb_io_in_4_bits_addr_T_1)
connect metaArb.io.in[4].bits.addr, _metaArb_io_in_4_bits_addr_T_2
node _metaArb_io_in_4_bits_data_T = shr(tl_out_c.bits.address, 14)
wire metaArb_io_in_4_bits_data_meta : { coh : { state : UInt<2>}, tag : UInt<18>}
connect metaArb_io_in_4_bits_data_meta.tag, _metaArb_io_in_4_bits_data_T
connect metaArb_io_in_4_bits_data_meta.coh, newCoh
node _metaArb_io_in_4_bits_data_T_1 = cat(metaArb_io_in_4_bits_data_meta.coh.state, metaArb_io_in_4_bits_data_meta.tag)
connect metaArb.io.in[4].bits.data, _metaArb_io_in_4_bits_data_T_1
node _T_109 = and(metaArb.io.in[4].ready, metaArb.io.in[4].valid)
when _T_109 :
connect release_state, UInt<4>(0h0)
connect io.cpu.resp.bits.mask, s2_req.mask
connect io.cpu.resp.bits.data, s2_req.data
connect io.cpu.resp.bits.dv, s2_req.dv
connect io.cpu.resp.bits.dprv, s2_req.dprv
connect io.cpu.resp.bits.signed, s2_req.signed
connect io.cpu.resp.bits.size, s2_req.size
connect io.cpu.resp.bits.cmd, s2_req.cmd
connect io.cpu.resp.bits.tag, s2_req.tag
connect io.cpu.resp.bits.addr, s2_req.addr
connect io.cpu.resp.bits.has_data, s2_read
connect io.cpu.resp.bits.replay, UInt<1>(0h0)
node _io_cpu_s2_uncached_T = eq(s2_hit, UInt<1>(0h0))
node _io_cpu_s2_uncached_T_1 = and(s2_uncached, _io_cpu_s2_uncached_T)
connect io.cpu.s2_uncached, _io_cpu_s2_uncached_T_1
connect io.cpu.s2_paddr, s2_req.addr
connect io.cpu.s2_gpa, s2_tlb_xcpt.gpa
connect io.cpu.s2_gpa_is_pte, s2_tlb_xcpt.gpa_is_pte
node _io_cpu_ordered_T = eq(s1_req.no_xcpt, UInt<1>(0h0))
node _io_cpu_ordered_T_1 = and(s1_valid, _io_cpu_ordered_T)
node _io_cpu_ordered_T_2 = eq(s2_req.no_xcpt, UInt<1>(0h0))
node _io_cpu_ordered_T_3 = and(s2_valid, _io_cpu_ordered_T_2)
node _io_cpu_ordered_T_4 = or(_io_cpu_ordered_T_1, _io_cpu_ordered_T_3)
node _io_cpu_ordered_T_5 = or(_io_cpu_ordered_T_4, cached_grant_wait)
node _io_cpu_ordered_T_6 = orr(uncachedInFlight[0])
node _io_cpu_ordered_T_7 = or(_io_cpu_ordered_T_5, _io_cpu_ordered_T_6)
node _io_cpu_ordered_T_8 = eq(_io_cpu_ordered_T_7, UInt<1>(0h0))
connect io.cpu.ordered, _io_cpu_ordered_T_8
node _io_cpu_store_pending_T = eq(s2_req.cmd, UInt<1>(0h1))
node _io_cpu_store_pending_T_1 = eq(s2_req.cmd, UInt<5>(0h11))
node _io_cpu_store_pending_T_2 = or(_io_cpu_store_pending_T, _io_cpu_store_pending_T_1)
node _io_cpu_store_pending_T_3 = eq(s2_req.cmd, UInt<3>(0h7))
node _io_cpu_store_pending_T_4 = or(_io_cpu_store_pending_T_2, _io_cpu_store_pending_T_3)
node _io_cpu_store_pending_T_5 = eq(s2_req.cmd, UInt<3>(0h4))
node _io_cpu_store_pending_T_6 = eq(s2_req.cmd, UInt<4>(0h9))
node _io_cpu_store_pending_T_7 = eq(s2_req.cmd, UInt<4>(0ha))
node _io_cpu_store_pending_T_8 = eq(s2_req.cmd, UInt<4>(0hb))
node _io_cpu_store_pending_T_9 = or(_io_cpu_store_pending_T_5, _io_cpu_store_pending_T_6)
node _io_cpu_store_pending_T_10 = or(_io_cpu_store_pending_T_9, _io_cpu_store_pending_T_7)
node _io_cpu_store_pending_T_11 = or(_io_cpu_store_pending_T_10, _io_cpu_store_pending_T_8)
node _io_cpu_store_pending_T_12 = eq(s2_req.cmd, UInt<4>(0h8))
node _io_cpu_store_pending_T_13 = eq(s2_req.cmd, UInt<4>(0hc))
node _io_cpu_store_pending_T_14 = eq(s2_req.cmd, UInt<4>(0hd))
node _io_cpu_store_pending_T_15 = eq(s2_req.cmd, UInt<4>(0he))
node _io_cpu_store_pending_T_16 = eq(s2_req.cmd, UInt<4>(0hf))
node _io_cpu_store_pending_T_17 = or(_io_cpu_store_pending_T_12, _io_cpu_store_pending_T_13)
node _io_cpu_store_pending_T_18 = or(_io_cpu_store_pending_T_17, _io_cpu_store_pending_T_14)
node _io_cpu_store_pending_T_19 = or(_io_cpu_store_pending_T_18, _io_cpu_store_pending_T_15)
node _io_cpu_store_pending_T_20 = or(_io_cpu_store_pending_T_19, _io_cpu_store_pending_T_16)
node _io_cpu_store_pending_T_21 = or(_io_cpu_store_pending_T_11, _io_cpu_store_pending_T_20)
node _io_cpu_store_pending_T_22 = or(_io_cpu_store_pending_T_4, _io_cpu_store_pending_T_21)
node _io_cpu_store_pending_T_23 = and(cached_grant_wait, _io_cpu_store_pending_T_22)
node _io_cpu_store_pending_T_24 = orr(uncachedInFlight[0])
node _io_cpu_store_pending_T_25 = or(_io_cpu_store_pending_T_23, _io_cpu_store_pending_T_24)
connect io.cpu.store_pending, _io_cpu_store_pending_T_25
node _s1_xcpt_valid_T = eq(s1_req.no_xcpt, UInt<1>(0h0))
node _s1_xcpt_valid_T_1 = and(tlb.io.req.valid, _s1_xcpt_valid_T)
node _s1_xcpt_valid_T_2 = eq(s1_nack, UInt<1>(0h0))
node s1_xcpt_valid = and(_s1_xcpt_valid_T_1, _s1_xcpt_valid_T_2)
reg io_cpu_s2_xcpt_REG : UInt<1>, clock
connect io_cpu_s2_xcpt_REG, s1_xcpt_valid
wire _io_cpu_s2_xcpt_WIRE : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<34>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}
connect _io_cpu_s2_xcpt_WIRE.cmd, UInt<5>(0h0)
connect _io_cpu_s2_xcpt_WIRE.size, UInt<2>(0h0)
connect _io_cpu_s2_xcpt_WIRE.prefetchable, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.must_alloc, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.cacheable, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.ma.inst, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.ma.st, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.ma.ld, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.ae.inst, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.ae.st, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.ae.ld, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.gf.inst, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.gf.st, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.gf.ld, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.pf.inst, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.pf.st, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.pf.ld, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.gpa_is_pte, UInt<1>(0h0)
connect _io_cpu_s2_xcpt_WIRE.gpa, UInt<34>(0h0)
connect _io_cpu_s2_xcpt_WIRE.paddr, UInt<32>(0h0)
connect _io_cpu_s2_xcpt_WIRE.miss, UInt<1>(0h0)
node _io_cpu_s2_xcpt_T = mux(io_cpu_s2_xcpt_REG, s2_tlb_xcpt, _io_cpu_s2_xcpt_WIRE)
connect io.cpu.s2_xcpt.ae.st, _io_cpu_s2_xcpt_T.ae.st
connect io.cpu.s2_xcpt.ae.ld, _io_cpu_s2_xcpt_T.ae.ld
connect io.cpu.s2_xcpt.gf.st, _io_cpu_s2_xcpt_T.gf.st
connect io.cpu.s2_xcpt.gf.ld, _io_cpu_s2_xcpt_T.gf.ld
connect io.cpu.s2_xcpt.pf.st, _io_cpu_s2_xcpt_T.pf.st
connect io.cpu.s2_xcpt.pf.ld, _io_cpu_s2_xcpt_T.pf.ld
connect io.cpu.s2_xcpt.ma.st, _io_cpu_s2_xcpt_T.ma.st
connect io.cpu.s2_xcpt.ma.ld, _io_cpu_s2_xcpt_T.ma.ld
node _T_110 = eq(s2_req.cmd, UInt<3>(0h6))
node _T_111 = eq(s2_req.cmd, UInt<3>(0h7))
node _T_112 = or(_T_110, _T_111)
node _T_113 = and(s2_valid_masked, _T_112)
node _T_114 = eq(_T_113, UInt<1>(0h0))
node _T_115 = asUInt(reset)
node _T_116 = eq(_T_115, UInt<1>(0h0))
when _T_116 :
node _T_117 = eq(_T_114, UInt<1>(0h0))
when _T_117 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at DCache.scala:936 assert(!(s2_valid_masked && s2_req.cmd.isOneOf(M_XLR, M_XSC)))\n") : printf_7
assert(clock, _T_114, UInt<1>(0h1), "") : assert_7
node s1_uncached_data_word = bits(nodeOut.d.bits.data, 63, 0)
reg s2_uncached_data_word : UInt<64>, clock
when io.cpu.replay_next :
connect s2_uncached_data_word, s1_uncached_data_word
reg doUncachedResp : UInt<1>, clock
connect doUncachedResp, io.cpu.replay_next
node _io_cpu_resp_valid_T = or(s2_valid_hit_pre_data_ecc, doUncachedResp)
node _io_cpu_resp_valid_T_1 = eq(s2_data_error, UInt<1>(0h0))
node _io_cpu_resp_valid_T_2 = and(_io_cpu_resp_valid_T, _io_cpu_resp_valid_T_1)
connect io.cpu.resp.valid, _io_cpu_resp_valid_T_2
node _io_cpu_replay_next_T = and(nodeOut.d.ready, nodeOut.d.valid)
node _io_cpu_replay_next_T_1 = and(_io_cpu_replay_next_T, grantIsUncachedData)
node _io_cpu_replay_next_T_2 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _io_cpu_replay_next_T_3 = and(_io_cpu_replay_next_T_1, _io_cpu_replay_next_T_2)
connect io.cpu.replay_next, _io_cpu_replay_next_T_3
when doUncachedResp :
node _T_118 = eq(s2_valid_hit, UInt<1>(0h0))
node _T_119 = asUInt(reset)
node _T_120 = eq(_T_119, UInt<1>(0h0))
when _T_120 :
node _T_121 = eq(_T_118, UInt<1>(0h0))
when _T_121 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at DCache.scala:952 assert(!s2_valid_hit)\n") : printf_8
assert(clock, _T_118, UInt<1>(0h1), "") : assert_8
connect io.cpu.resp.bits.replay, UInt<1>(0h1)
connect io.cpu.resp.bits.addr, s2_uncached_resp_addr
node s2_data_word = bits(s2_data_uncorrected, 63, 0)
node s2_data_word_corrected = bits(s2_data_corrected, 63, 0)
node _s2_data_word_possibly_uncached_T = and(UInt<1>(0h0), doUncachedResp)
node _s2_data_word_possibly_uncached_T_1 = mux(_s2_data_word_possibly_uncached_T, s2_uncached_data_word, UInt<1>(0h0))
node s2_data_word_possibly_uncached = or(_s2_data_word_possibly_uncached_T_1, s2_data_word)
wire size : UInt<2>
connect size, s2_req.size
node _io_cpu_resp_bits_data_shifted_T = bits(s2_req.addr, 2, 2)
node _io_cpu_resp_bits_data_shifted_T_1 = bits(s2_data_word_possibly_uncached, 63, 32)
node _io_cpu_resp_bits_data_shifted_T_2 = bits(s2_data_word_possibly_uncached, 31, 0)
node io_cpu_resp_bits_data_shifted = mux(_io_cpu_resp_bits_data_shifted_T, _io_cpu_resp_bits_data_shifted_T_1, _io_cpu_resp_bits_data_shifted_T_2)
node io_cpu_resp_bits_data_doZero = and(UInt<1>(0h0), s2_sc)
node io_cpu_resp_bits_data_zeroed = mux(io_cpu_resp_bits_data_doZero, UInt<1>(0h0), io_cpu_resp_bits_data_shifted)
node _io_cpu_resp_bits_data_T = eq(size, UInt<2>(0h2))
node _io_cpu_resp_bits_data_T_1 = or(_io_cpu_resp_bits_data_T, io_cpu_resp_bits_data_doZero)
node _io_cpu_resp_bits_data_T_2 = bits(io_cpu_resp_bits_data_zeroed, 31, 31)
node _io_cpu_resp_bits_data_T_3 = and(s2_req.signed, _io_cpu_resp_bits_data_T_2)
node _io_cpu_resp_bits_data_T_4 = mux(_io_cpu_resp_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0))
node _io_cpu_resp_bits_data_T_5 = bits(s2_data_word_possibly_uncached, 63, 32)
node _io_cpu_resp_bits_data_T_6 = mux(_io_cpu_resp_bits_data_T_1, _io_cpu_resp_bits_data_T_4, _io_cpu_resp_bits_data_T_5)
node _io_cpu_resp_bits_data_T_7 = cat(_io_cpu_resp_bits_data_T_6, io_cpu_resp_bits_data_zeroed)
node _io_cpu_resp_bits_data_shifted_T_3 = bits(s2_req.addr, 1, 1)
node _io_cpu_resp_bits_data_shifted_T_4 = bits(_io_cpu_resp_bits_data_T_7, 31, 16)
node _io_cpu_resp_bits_data_shifted_T_5 = bits(_io_cpu_resp_bits_data_T_7, 15, 0)
node io_cpu_resp_bits_data_shifted_1 = mux(_io_cpu_resp_bits_data_shifted_T_3, _io_cpu_resp_bits_data_shifted_T_4, _io_cpu_resp_bits_data_shifted_T_5)
node io_cpu_resp_bits_data_doZero_1 = and(UInt<1>(0h0), s2_sc)
node io_cpu_resp_bits_data_zeroed_1 = mux(io_cpu_resp_bits_data_doZero_1, UInt<1>(0h0), io_cpu_resp_bits_data_shifted_1)
node _io_cpu_resp_bits_data_T_8 = eq(size, UInt<1>(0h1))
node _io_cpu_resp_bits_data_T_9 = or(_io_cpu_resp_bits_data_T_8, io_cpu_resp_bits_data_doZero_1)
node _io_cpu_resp_bits_data_T_10 = bits(io_cpu_resp_bits_data_zeroed_1, 15, 15)
node _io_cpu_resp_bits_data_T_11 = and(s2_req.signed, _io_cpu_resp_bits_data_T_10)
node _io_cpu_resp_bits_data_T_12 = mux(_io_cpu_resp_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0))
node _io_cpu_resp_bits_data_T_13 = bits(_io_cpu_resp_bits_data_T_7, 63, 16)
node _io_cpu_resp_bits_data_T_14 = mux(_io_cpu_resp_bits_data_T_9, _io_cpu_resp_bits_data_T_12, _io_cpu_resp_bits_data_T_13)
node _io_cpu_resp_bits_data_T_15 = cat(_io_cpu_resp_bits_data_T_14, io_cpu_resp_bits_data_zeroed_1)
node _io_cpu_resp_bits_data_shifted_T_6 = bits(s2_req.addr, 0, 0)
node _io_cpu_resp_bits_data_shifted_T_7 = bits(_io_cpu_resp_bits_data_T_15, 15, 8)
node _io_cpu_resp_bits_data_shifted_T_8 = bits(_io_cpu_resp_bits_data_T_15, 7, 0)
node io_cpu_resp_bits_data_shifted_2 = mux(_io_cpu_resp_bits_data_shifted_T_6, _io_cpu_resp_bits_data_shifted_T_7, _io_cpu_resp_bits_data_shifted_T_8)
node io_cpu_resp_bits_data_doZero_2 = and(UInt<1>(0h1), s2_sc)
node io_cpu_resp_bits_data_zeroed_2 = mux(io_cpu_resp_bits_data_doZero_2, UInt<1>(0h0), io_cpu_resp_bits_data_shifted_2)
node _io_cpu_resp_bits_data_T_16 = eq(size, UInt<1>(0h0))
node _io_cpu_resp_bits_data_T_17 = or(_io_cpu_resp_bits_data_T_16, io_cpu_resp_bits_data_doZero_2)
node _io_cpu_resp_bits_data_T_18 = bits(io_cpu_resp_bits_data_zeroed_2, 7, 7)
node _io_cpu_resp_bits_data_T_19 = and(s2_req.signed, _io_cpu_resp_bits_data_T_18)
node _io_cpu_resp_bits_data_T_20 = mux(_io_cpu_resp_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0))
node _io_cpu_resp_bits_data_T_21 = bits(_io_cpu_resp_bits_data_T_15, 63, 8)
node _io_cpu_resp_bits_data_T_22 = mux(_io_cpu_resp_bits_data_T_17, _io_cpu_resp_bits_data_T_20, _io_cpu_resp_bits_data_T_21)
node _io_cpu_resp_bits_data_T_23 = cat(_io_cpu_resp_bits_data_T_22, io_cpu_resp_bits_data_zeroed_2)
node _io_cpu_resp_bits_data_T_24 = or(_io_cpu_resp_bits_data_T_23, s2_sc_fail)
connect io.cpu.resp.bits.data, _io_cpu_resp_bits_data_T_24
node _io_cpu_resp_bits_data_word_bypass_shifted_T = bits(s2_req.addr, 2, 2)
node _io_cpu_resp_bits_data_word_bypass_shifted_T_1 = bits(s2_data_word_possibly_uncached, 63, 32)
node _io_cpu_resp_bits_data_word_bypass_shifted_T_2 = bits(s2_data_word_possibly_uncached, 31, 0)
node io_cpu_resp_bits_data_word_bypass_shifted = mux(_io_cpu_resp_bits_data_word_bypass_shifted_T, _io_cpu_resp_bits_data_word_bypass_shifted_T_1, _io_cpu_resp_bits_data_word_bypass_shifted_T_2)
node io_cpu_resp_bits_data_word_bypass_doZero = and(UInt<1>(0h0), s2_sc)
node io_cpu_resp_bits_data_word_bypass_zeroed = mux(io_cpu_resp_bits_data_word_bypass_doZero, UInt<1>(0h0), io_cpu_resp_bits_data_word_bypass_shifted)
node _io_cpu_resp_bits_data_word_bypass_T = eq(size, UInt<2>(0h2))
node _io_cpu_resp_bits_data_word_bypass_T_1 = or(_io_cpu_resp_bits_data_word_bypass_T, io_cpu_resp_bits_data_word_bypass_doZero)
node _io_cpu_resp_bits_data_word_bypass_T_2 = bits(io_cpu_resp_bits_data_word_bypass_zeroed, 31, 31)
node _io_cpu_resp_bits_data_word_bypass_T_3 = and(s2_req.signed, _io_cpu_resp_bits_data_word_bypass_T_2)
node _io_cpu_resp_bits_data_word_bypass_T_4 = mux(_io_cpu_resp_bits_data_word_bypass_T_3, UInt<32>(0hffffffff), UInt<32>(0h0))
node _io_cpu_resp_bits_data_word_bypass_T_5 = bits(s2_data_word_possibly_uncached, 63, 32)
node _io_cpu_resp_bits_data_word_bypass_T_6 = mux(_io_cpu_resp_bits_data_word_bypass_T_1, _io_cpu_resp_bits_data_word_bypass_T_4, _io_cpu_resp_bits_data_word_bypass_T_5)
node _io_cpu_resp_bits_data_word_bypass_T_7 = cat(_io_cpu_resp_bits_data_word_bypass_T_6, io_cpu_resp_bits_data_word_bypass_zeroed)
connect io.cpu.resp.bits.data_word_bypass, _io_cpu_resp_bits_data_word_bypass_T_7
connect io.cpu.resp.bits.data_raw, s2_data_word
connect io.cpu.resp.bits.store_data, pstore1_data
inst amoalus_0 of AMOALU
connect amoalus_0.clock, clock
connect amoalus_0.reset, reset
node _amoalu_io_mask_T = shr(pstore1_mask, 0)
connect amoalus_0.io.mask, _amoalu_io_mask_T
connect amoalus_0.io.cmd, pstore1_cmd
node _amoalu_io_lhs_T = shr(s2_data_word, 0)
connect amoalus_0.io.lhs, _amoalu_io_lhs_T
node _amoalu_io_rhs_T = shr(pstore1_data, 0)
connect amoalus_0.io.rhs, _amoalu_io_rhs_T
node _pstore1_storegen_data_mask_T = mux(s2_correct, UInt<1>(0h0), pstore1_mask)
node _pstore1_storegen_data_mask_T_1 = bits(_pstore1_storegen_data_mask_T, 0, 0)
node _pstore1_storegen_data_mask_T_2 = bits(_pstore1_storegen_data_mask_T, 1, 1)
node _pstore1_storegen_data_mask_T_3 = bits(_pstore1_storegen_data_mask_T, 2, 2)
node _pstore1_storegen_data_mask_T_4 = bits(_pstore1_storegen_data_mask_T, 3, 3)
node _pstore1_storegen_data_mask_T_5 = bits(_pstore1_storegen_data_mask_T, 4, 4)
node _pstore1_storegen_data_mask_T_6 = bits(_pstore1_storegen_data_mask_T, 5, 5)
node _pstore1_storegen_data_mask_T_7 = bits(_pstore1_storegen_data_mask_T, 6, 6)
node _pstore1_storegen_data_mask_T_8 = bits(_pstore1_storegen_data_mask_T, 7, 7)
node _pstore1_storegen_data_mask_T_9 = mux(_pstore1_storegen_data_mask_T_1, UInt<8>(0hff), UInt<8>(0h0))
node _pstore1_storegen_data_mask_T_10 = mux(_pstore1_storegen_data_mask_T_2, UInt<8>(0hff), UInt<8>(0h0))
node _pstore1_storegen_data_mask_T_11 = mux(_pstore1_storegen_data_mask_T_3, UInt<8>(0hff), UInt<8>(0h0))
node _pstore1_storegen_data_mask_T_12 = mux(_pstore1_storegen_data_mask_T_4, UInt<8>(0hff), UInt<8>(0h0))
node _pstore1_storegen_data_mask_T_13 = mux(_pstore1_storegen_data_mask_T_5, UInt<8>(0hff), UInt<8>(0h0))
node _pstore1_storegen_data_mask_T_14 = mux(_pstore1_storegen_data_mask_T_6, UInt<8>(0hff), UInt<8>(0h0))
node _pstore1_storegen_data_mask_T_15 = mux(_pstore1_storegen_data_mask_T_7, UInt<8>(0hff), UInt<8>(0h0))
node _pstore1_storegen_data_mask_T_16 = mux(_pstore1_storegen_data_mask_T_8, UInt<8>(0hff), UInt<8>(0h0))
node pstore1_storegen_data_mask_lo_lo = cat(_pstore1_storegen_data_mask_T_10, _pstore1_storegen_data_mask_T_9)
node pstore1_storegen_data_mask_lo_hi = cat(_pstore1_storegen_data_mask_T_12, _pstore1_storegen_data_mask_T_11)
node pstore1_storegen_data_mask_lo = cat(pstore1_storegen_data_mask_lo_hi, pstore1_storegen_data_mask_lo_lo)
node pstore1_storegen_data_mask_hi_lo = cat(_pstore1_storegen_data_mask_T_14, _pstore1_storegen_data_mask_T_13)
node pstore1_storegen_data_mask_hi_hi = cat(_pstore1_storegen_data_mask_T_16, _pstore1_storegen_data_mask_T_15)
node pstore1_storegen_data_mask_hi = cat(pstore1_storegen_data_mask_hi_hi, pstore1_storegen_data_mask_hi_lo)
node pstore1_storegen_data_mask = cat(pstore1_storegen_data_mask_hi, pstore1_storegen_data_mask_lo)
node _pstore1_storegen_data_T = and(amoalus_0.io.out_unmasked, pstore1_storegen_data_mask)
node _pstore1_storegen_data_T_1 = not(pstore1_storegen_data_mask)
node _pstore1_storegen_data_T_2 = and(s2_data_word_corrected, _pstore1_storegen_data_T_1)
node _pstore1_storegen_data_T_3 = or(_pstore1_storegen_data_T, _pstore1_storegen_data_T_2)
connect pstore1_storegen_data, _pstore1_storegen_data_T_3
node flushCounterNext = add(flushCounter, UInt<1>(0h1))
node _flushDone_T = shr(flushCounterNext, 8)
node flushDone = eq(_flushDone_T, UInt<1>(0h1))
node flushCounterWrap = bits(flushCounterNext, 7, 0)
node _T_122 = and(s2_valid_masked, s2_cmd_flush_all)
node _T_123 = and(_T_122, s2_meta_error)
node _T_124 = and(s2_valid_masked, s2_cmd_flush_all)
node _T_125 = and(_T_124, s2_data_error)
node _s1_flush_valid_T = and(metaArb.io.in[5].ready, metaArb.io.in[5].valid)
node _s1_flush_valid_T_1 = eq(s1_flush_valid, UInt<1>(0h0))
node _s1_flush_valid_T_2 = and(_s1_flush_valid_T, _s1_flush_valid_T_1)
node _s1_flush_valid_T_3 = eq(s2_flush_valid_pre_tag_ecc, UInt<1>(0h0))
node _s1_flush_valid_T_4 = and(_s1_flush_valid_T_2, _s1_flush_valid_T_3)
node _s1_flush_valid_T_5 = eq(release_state, UInt<4>(0h0))
node _s1_flush_valid_T_6 = and(_s1_flush_valid_T_4, _s1_flush_valid_T_5)
node _s1_flush_valid_T_7 = eq(release_ack_wait, UInt<1>(0h0))
node _s1_flush_valid_T_8 = and(_s1_flush_valid_T_6, _s1_flush_valid_T_7)
connect s1_flush_valid, _s1_flush_valid_T_8
node _metaArb_io_in_5_valid_T = eq(flushed, UInt<1>(0h0))
node _metaArb_io_in_5_valid_T_1 = and(flushing, _metaArb_io_in_5_valid_T)
connect metaArb.io.in[5].valid, _metaArb_io_in_5_valid_T_1
connect metaArb.io.in[5].bits.write, UInt<1>(0h0)
node _metaArb_io_in_5_bits_idx_T = bits(flushCounter, 7, 0)
connect metaArb.io.in[5].bits.idx, _metaArb_io_in_5_bits_idx_T
node _metaArb_io_in_5_bits_addr_T = shr(io.cpu.req.bits.addr, 14)
node _metaArb_io_in_5_bits_addr_T_1 = shl(metaArb.io.in[5].bits.idx, 6)
node _metaArb_io_in_5_bits_addr_T_2 = cat(_metaArb_io_in_5_bits_addr_T, _metaArb_io_in_5_bits_addr_T_1)
connect metaArb.io.in[5].bits.addr, _metaArb_io_in_5_bits_addr_T_2
connect metaArb.io.in[5].bits.way_en, metaArb.io.in[4].bits.way_en
connect metaArb.io.in[5].bits.data, metaArb.io.in[4].bits.data
connect metaArb.io.in[0].valid, resetting
connect metaArb.io.in[0].bits.data, metaArb.io.in[5].bits.data
connect metaArb.io.in[0].bits.way_en, metaArb.io.in[5].bits.way_en
connect metaArb.io.in[0].bits.idx, metaArb.io.in[5].bits.idx
connect metaArb.io.in[0].bits.addr, metaArb.io.in[5].bits.addr
connect metaArb.io.in[0].bits.write, metaArb.io.in[5].bits.write
connect metaArb.io.in[0].bits.write, UInt<1>(0h1)
node _metaArb_io_in_0_bits_way_en_T = not(UInt<1>(0h0))
connect metaArb.io.in[0].bits.way_en, _metaArb_io_in_0_bits_way_en_T
wire metaArb_io_in_0_bits_data_meta : { state : UInt<2>}
connect metaArb_io_in_0_bits_data_meta.state, UInt<2>(0h0)
wire metaArb_io_in_0_bits_data_meta_1 : { coh : { state : UInt<2>}, tag : UInt<18>}
connect metaArb_io_in_0_bits_data_meta_1.tag, UInt<1>(0h0)
connect metaArb_io_in_0_bits_data_meta_1.coh, metaArb_io_in_0_bits_data_meta
node _metaArb_io_in_0_bits_data_T = cat(metaArb_io_in_0_bits_data_meta_1.coh.state, metaArb_io_in_0_bits_data_meta_1.tag)
connect metaArb.io.in[0].bits.data, _metaArb_io_in_0_bits_data_T
when resetting :
connect flushCounter, flushCounterNext
when flushDone :
connect resetting, UInt<1>(0h0)
node _clock_en_reg_T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _clock_en_reg_T_1 = bits(io.ptw.customCSRs.csrs[0].value, 0, 0)
node _clock_en_reg_T_2 = or(_clock_en_reg_T, _clock_en_reg_T_1)
node _clock_en_reg_T_3 = or(_clock_en_reg_T_2, io.cpu.keep_clock_enabled)
node _clock_en_reg_T_4 = or(_clock_en_reg_T_3, metaArb.io.out.valid)
node _clock_en_reg_T_5 = or(_clock_en_reg_T_4, s1_probe)
node _clock_en_reg_T_6 = or(_clock_en_reg_T_5, s2_probe)
node _clock_en_reg_T_7 = or(_clock_en_reg_T_6, s1_valid)
node _clock_en_reg_T_8 = or(_clock_en_reg_T_7, s2_valid)
node _clock_en_reg_T_9 = or(_clock_en_reg_T_8, io.tlb_port.req.valid)
node _clock_en_reg_T_10 = or(_clock_en_reg_T_9, s1_tlb_req_valid)
node _clock_en_reg_T_11 = or(_clock_en_reg_T_10, s2_tlb_req_valid)
node _clock_en_reg_T_12 = or(_clock_en_reg_T_11, pstore1_held)
node _clock_en_reg_T_13 = or(_clock_en_reg_T_12, pstore2_valid)
node _clock_en_reg_T_14 = neq(release_state, UInt<4>(0h0))
node _clock_en_reg_T_15 = or(_clock_en_reg_T_13, _clock_en_reg_T_14)
node _clock_en_reg_T_16 = or(_clock_en_reg_T_15, release_ack_wait)
node _clock_en_reg_T_17 = eq(UInt<1>(0h1), UInt<1>(0h0))
node _clock_en_reg_T_18 = or(_clock_en_reg_T_16, _clock_en_reg_T_17)
node _clock_en_reg_T_19 = eq(tlb.io.req.ready, UInt<1>(0h0))
node _clock_en_reg_T_20 = or(_clock_en_reg_T_18, _clock_en_reg_T_19)
node _clock_en_reg_T_21 = or(_clock_en_reg_T_20, cached_grant_wait)
node _clock_en_reg_T_22 = orr(uncachedInFlight[0])
node _clock_en_reg_T_23 = or(_clock_en_reg_T_21, _clock_en_reg_T_22)
node _clock_en_reg_T_24 = gt(lrscCount, UInt<1>(0h0))
node _clock_en_reg_T_25 = or(_clock_en_reg_T_23, _clock_en_reg_T_24)
node _clock_en_reg_T_26 = gt(blockProbeAfterGrantCount, UInt<1>(0h0))
node _clock_en_reg_T_27 = or(_clock_en_reg_T_25, _clock_en_reg_T_26)
connect clock_en_reg, _clock_en_reg_T_27
node _io_cpu_perf_acquire_T = and(tl_out_a.ready, tl_out_a.valid)
node _io_cpu_perf_acquire_beats1_decode_T = dshl(UInt<12>(0hfff), tl_out_a.bits.size)
node _io_cpu_perf_acquire_beats1_decode_T_1 = bits(_io_cpu_perf_acquire_beats1_decode_T, 11, 0)
node _io_cpu_perf_acquire_beats1_decode_T_2 = not(_io_cpu_perf_acquire_beats1_decode_T_1)
node io_cpu_perf_acquire_beats1_decode = shr(_io_cpu_perf_acquire_beats1_decode_T_2, 3)
node _io_cpu_perf_acquire_beats1_opdata_T = bits(tl_out_a.bits.opcode, 2, 2)
node io_cpu_perf_acquire_beats1_opdata = eq(_io_cpu_perf_acquire_beats1_opdata_T, UInt<1>(0h0))
node io_cpu_perf_acquire_beats1 = mux(io_cpu_perf_acquire_beats1_opdata, io_cpu_perf_acquire_beats1_decode, UInt<1>(0h0))
regreset io_cpu_perf_acquire_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _io_cpu_perf_acquire_counter1_T = sub(io_cpu_perf_acquire_counter, UInt<1>(0h1))
node io_cpu_perf_acquire_counter1 = tail(_io_cpu_perf_acquire_counter1_T, 1)
node io_cpu_perf_acquire_first = eq(io_cpu_perf_acquire_counter, UInt<1>(0h0))
node _io_cpu_perf_acquire_last_T = eq(io_cpu_perf_acquire_counter, UInt<1>(0h1))
node _io_cpu_perf_acquire_last_T_1 = eq(io_cpu_perf_acquire_beats1, UInt<1>(0h0))
node io_cpu_perf_acquire_last = or(_io_cpu_perf_acquire_last_T, _io_cpu_perf_acquire_last_T_1)
node io_cpu_perf_acquire_done = and(io_cpu_perf_acquire_last, _io_cpu_perf_acquire_T)
node _io_cpu_perf_acquire_count_T = not(io_cpu_perf_acquire_counter1)
node io_cpu_perf_acquire_count = and(io_cpu_perf_acquire_beats1, _io_cpu_perf_acquire_count_T)
when _io_cpu_perf_acquire_T :
node _io_cpu_perf_acquire_counter_T = mux(io_cpu_perf_acquire_first, io_cpu_perf_acquire_beats1, io_cpu_perf_acquire_counter1)
connect io_cpu_perf_acquire_counter, _io_cpu_perf_acquire_counter_T
connect io.cpu.perf.acquire, io_cpu_perf_acquire_done
node _io_cpu_perf_release_T = and(tl_out_c.ready, tl_out_c.valid)
node _io_cpu_perf_release_beats1_decode_T = dshl(UInt<12>(0hfff), tl_out_c.bits.size)
node _io_cpu_perf_release_beats1_decode_T_1 = bits(_io_cpu_perf_release_beats1_decode_T, 11, 0)
node _io_cpu_perf_release_beats1_decode_T_2 = not(_io_cpu_perf_release_beats1_decode_T_1)
node io_cpu_perf_release_beats1_decode = shr(_io_cpu_perf_release_beats1_decode_T_2, 3)
node io_cpu_perf_release_beats1_opdata = bits(tl_out_c.bits.opcode, 0, 0)
node io_cpu_perf_release_beats1 = mux(UInt<1>(0h0), io_cpu_perf_release_beats1_decode, UInt<1>(0h0))
regreset io_cpu_perf_release_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _io_cpu_perf_release_counter1_T = sub(io_cpu_perf_release_counter, UInt<1>(0h1))
node io_cpu_perf_release_counter1 = tail(_io_cpu_perf_release_counter1_T, 1)
node io_cpu_perf_release_first = eq(io_cpu_perf_release_counter, UInt<1>(0h0))
node _io_cpu_perf_release_last_T = eq(io_cpu_perf_release_counter, UInt<1>(0h1))
node _io_cpu_perf_release_last_T_1 = eq(io_cpu_perf_release_beats1, UInt<1>(0h0))
node io_cpu_perf_release_last = or(_io_cpu_perf_release_last_T, _io_cpu_perf_release_last_T_1)
node io_cpu_perf_release_done = and(io_cpu_perf_release_last, _io_cpu_perf_release_T)
node _io_cpu_perf_release_count_T = not(io_cpu_perf_release_counter1)
node io_cpu_perf_release_count = and(io_cpu_perf_release_beats1, _io_cpu_perf_release_count_T)
when _io_cpu_perf_release_T :
node _io_cpu_perf_release_counter_T = mux(io_cpu_perf_release_first, io_cpu_perf_release_beats1, io_cpu_perf_release_counter1)
connect io_cpu_perf_release_counter, _io_cpu_perf_release_counter_T
connect io.cpu.perf.release, io_cpu_perf_release_done
node _io_cpu_perf_grant_T = and(nodeOut.d.valid, d_last)
connect io.cpu.perf.grant, _io_cpu_perf_grant_T
node _io_cpu_perf_tlbMiss_T = and(io.ptw.req.ready, io.ptw.req.valid)
connect io.cpu.perf.tlbMiss, _io_cpu_perf_tlbMiss_T
node _io_cpu_perf_storeBufferEmptyAfterLoad_T = and(s1_valid, s1_write)
node _io_cpu_perf_storeBufferEmptyAfterLoad_T_1 = and(s2_valid, s2_write)
node _io_cpu_perf_storeBufferEmptyAfterLoad_T_2 = eq(s2_waw_hazard, UInt<1>(0h0))
node _io_cpu_perf_storeBufferEmptyAfterLoad_T_3 = and(_io_cpu_perf_storeBufferEmptyAfterLoad_T_1, _io_cpu_perf_storeBufferEmptyAfterLoad_T_2)
node _io_cpu_perf_storeBufferEmptyAfterLoad_T_4 = or(_io_cpu_perf_storeBufferEmptyAfterLoad_T_3, pstore1_held)
node _io_cpu_perf_storeBufferEmptyAfterLoad_T_5 = or(_io_cpu_perf_storeBufferEmptyAfterLoad_T, _io_cpu_perf_storeBufferEmptyAfterLoad_T_4)
node _io_cpu_perf_storeBufferEmptyAfterLoad_T_6 = or(_io_cpu_perf_storeBufferEmptyAfterLoad_T_5, pstore2_valid)
node _io_cpu_perf_storeBufferEmptyAfterLoad_T_7 = eq(_io_cpu_perf_storeBufferEmptyAfterLoad_T_6, UInt<1>(0h0))
connect io.cpu.perf.storeBufferEmptyAfterLoad, _io_cpu_perf_storeBufferEmptyAfterLoad_T_7
node _io_cpu_perf_storeBufferEmptyAfterStore_T = and(s1_valid, s1_write)
node _io_cpu_perf_storeBufferEmptyAfterStore_T_1 = and(s2_valid, s2_write)
node _io_cpu_perf_storeBufferEmptyAfterStore_T_2 = and(_io_cpu_perf_storeBufferEmptyAfterStore_T_1, pstore1_rmw)
node _io_cpu_perf_storeBufferEmptyAfterStore_T_3 = or(_io_cpu_perf_storeBufferEmptyAfterStore_T, _io_cpu_perf_storeBufferEmptyAfterStore_T_2)
node _io_cpu_perf_storeBufferEmptyAfterStore_T_4 = and(s2_valid, s2_write)
node _io_cpu_perf_storeBufferEmptyAfterStore_T_5 = eq(s2_waw_hazard, UInt<1>(0h0))
node _io_cpu_perf_storeBufferEmptyAfterStore_T_6 = and(_io_cpu_perf_storeBufferEmptyAfterStore_T_4, _io_cpu_perf_storeBufferEmptyAfterStore_T_5)
node _io_cpu_perf_storeBufferEmptyAfterStore_T_7 = or(_io_cpu_perf_storeBufferEmptyAfterStore_T_6, pstore1_held)
node _io_cpu_perf_storeBufferEmptyAfterStore_T_8 = and(_io_cpu_perf_storeBufferEmptyAfterStore_T_7, pstore2_valid)
node _io_cpu_perf_storeBufferEmptyAfterStore_T_9 = or(_io_cpu_perf_storeBufferEmptyAfterStore_T_3, _io_cpu_perf_storeBufferEmptyAfterStore_T_8)
node _io_cpu_perf_storeBufferEmptyAfterStore_T_10 = eq(_io_cpu_perf_storeBufferEmptyAfterStore_T_9, UInt<1>(0h0))
connect io.cpu.perf.storeBufferEmptyAfterStore, _io_cpu_perf_storeBufferEmptyAfterStore_T_10
node _io_cpu_perf_canAcceptStoreThenLoad_T = and(s2_valid, s2_write)
node _io_cpu_perf_canAcceptStoreThenLoad_T_1 = and(_io_cpu_perf_canAcceptStoreThenLoad_T, pstore1_rmw)
node _io_cpu_perf_canAcceptStoreThenLoad_T_2 = and(s1_valid, s1_write)
node _io_cpu_perf_canAcceptStoreThenLoad_T_3 = eq(s1_waw_hazard, UInt<1>(0h0))
node _io_cpu_perf_canAcceptStoreThenLoad_T_4 = and(_io_cpu_perf_canAcceptStoreThenLoad_T_2, _io_cpu_perf_canAcceptStoreThenLoad_T_3)
node _io_cpu_perf_canAcceptStoreThenLoad_T_5 = and(_io_cpu_perf_canAcceptStoreThenLoad_T_1, _io_cpu_perf_canAcceptStoreThenLoad_T_4)
node _io_cpu_perf_canAcceptStoreThenLoad_T_6 = and(pstore2_valid, pstore1_valid_likely)
node _io_cpu_perf_canAcceptStoreThenLoad_T_7 = and(s1_valid, s1_write)
node _io_cpu_perf_canAcceptStoreThenLoad_T_8 = and(_io_cpu_perf_canAcceptStoreThenLoad_T_6, _io_cpu_perf_canAcceptStoreThenLoad_T_7)
node _io_cpu_perf_canAcceptStoreThenLoad_T_9 = or(_io_cpu_perf_canAcceptStoreThenLoad_T_5, _io_cpu_perf_canAcceptStoreThenLoad_T_8)
node _io_cpu_perf_canAcceptStoreThenLoad_T_10 = eq(_io_cpu_perf_canAcceptStoreThenLoad_T_9, UInt<1>(0h0))
connect io.cpu.perf.canAcceptStoreThenLoad, _io_cpu_perf_canAcceptStoreThenLoad_T_10
node _io_cpu_perf_canAcceptStoreThenRMW_T = eq(pstore2_valid, UInt<1>(0h0))
node _io_cpu_perf_canAcceptStoreThenRMW_T_1 = and(io.cpu.perf.canAcceptStoreThenLoad, _io_cpu_perf_canAcceptStoreThenRMW_T)
connect io.cpu.perf.canAcceptStoreThenRMW, _io_cpu_perf_canAcceptStoreThenRMW_T_1
node _io_cpu_perf_canAcceptLoadThenLoad_T = and(s1_valid, s1_write)
node _io_cpu_perf_canAcceptLoadThenLoad_T_1 = eq(s1_req.cmd, UInt<1>(0h0))
node _io_cpu_perf_canAcceptLoadThenLoad_T_2 = eq(s1_req.cmd, UInt<5>(0h10))
node _io_cpu_perf_canAcceptLoadThenLoad_T_3 = eq(s1_req.cmd, UInt<3>(0h6))
node _io_cpu_perf_canAcceptLoadThenLoad_T_4 = eq(s1_req.cmd, UInt<3>(0h7))
node _io_cpu_perf_canAcceptLoadThenLoad_T_5 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_1, _io_cpu_perf_canAcceptLoadThenLoad_T_2)
node _io_cpu_perf_canAcceptLoadThenLoad_T_6 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_5, _io_cpu_perf_canAcceptLoadThenLoad_T_3)
node _io_cpu_perf_canAcceptLoadThenLoad_T_7 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_6, _io_cpu_perf_canAcceptLoadThenLoad_T_4)
node _io_cpu_perf_canAcceptLoadThenLoad_T_8 = eq(s1_req.cmd, UInt<3>(0h4))
node _io_cpu_perf_canAcceptLoadThenLoad_T_9 = eq(s1_req.cmd, UInt<4>(0h9))
node _io_cpu_perf_canAcceptLoadThenLoad_T_10 = eq(s1_req.cmd, UInt<4>(0ha))
node _io_cpu_perf_canAcceptLoadThenLoad_T_11 = eq(s1_req.cmd, UInt<4>(0hb))
node _io_cpu_perf_canAcceptLoadThenLoad_T_12 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_8, _io_cpu_perf_canAcceptLoadThenLoad_T_9)
node _io_cpu_perf_canAcceptLoadThenLoad_T_13 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_12, _io_cpu_perf_canAcceptLoadThenLoad_T_10)
node _io_cpu_perf_canAcceptLoadThenLoad_T_14 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_13, _io_cpu_perf_canAcceptLoadThenLoad_T_11)
node _io_cpu_perf_canAcceptLoadThenLoad_T_15 = eq(s1_req.cmd, UInt<4>(0h8))
node _io_cpu_perf_canAcceptLoadThenLoad_T_16 = eq(s1_req.cmd, UInt<4>(0hc))
node _io_cpu_perf_canAcceptLoadThenLoad_T_17 = eq(s1_req.cmd, UInt<4>(0hd))
node _io_cpu_perf_canAcceptLoadThenLoad_T_18 = eq(s1_req.cmd, UInt<4>(0he))
node _io_cpu_perf_canAcceptLoadThenLoad_T_19 = eq(s1_req.cmd, UInt<4>(0hf))
node _io_cpu_perf_canAcceptLoadThenLoad_T_20 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_15, _io_cpu_perf_canAcceptLoadThenLoad_T_16)
node _io_cpu_perf_canAcceptLoadThenLoad_T_21 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_20, _io_cpu_perf_canAcceptLoadThenLoad_T_17)
node _io_cpu_perf_canAcceptLoadThenLoad_T_22 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_21, _io_cpu_perf_canAcceptLoadThenLoad_T_18)
node _io_cpu_perf_canAcceptLoadThenLoad_T_23 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_22, _io_cpu_perf_canAcceptLoadThenLoad_T_19)
node _io_cpu_perf_canAcceptLoadThenLoad_T_24 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_14, _io_cpu_perf_canAcceptLoadThenLoad_T_23)
node _io_cpu_perf_canAcceptLoadThenLoad_T_25 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_7, _io_cpu_perf_canAcceptLoadThenLoad_T_24)
node _io_cpu_perf_canAcceptLoadThenLoad_T_26 = eq(s1_req.cmd, UInt<1>(0h1))
node _io_cpu_perf_canAcceptLoadThenLoad_T_27 = eq(s1_req.cmd, UInt<5>(0h11))
node _io_cpu_perf_canAcceptLoadThenLoad_T_28 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_26, _io_cpu_perf_canAcceptLoadThenLoad_T_27)
node _io_cpu_perf_canAcceptLoadThenLoad_T_29 = eq(s1_req.cmd, UInt<3>(0h7))
node _io_cpu_perf_canAcceptLoadThenLoad_T_30 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_28, _io_cpu_perf_canAcceptLoadThenLoad_T_29)
node _io_cpu_perf_canAcceptLoadThenLoad_T_31 = eq(s1_req.cmd, UInt<3>(0h4))
node _io_cpu_perf_canAcceptLoadThenLoad_T_32 = eq(s1_req.cmd, UInt<4>(0h9))
node _io_cpu_perf_canAcceptLoadThenLoad_T_33 = eq(s1_req.cmd, UInt<4>(0ha))
node _io_cpu_perf_canAcceptLoadThenLoad_T_34 = eq(s1_req.cmd, UInt<4>(0hb))
node _io_cpu_perf_canAcceptLoadThenLoad_T_35 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_31, _io_cpu_perf_canAcceptLoadThenLoad_T_32)
node _io_cpu_perf_canAcceptLoadThenLoad_T_36 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_35, _io_cpu_perf_canAcceptLoadThenLoad_T_33)
node _io_cpu_perf_canAcceptLoadThenLoad_T_37 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_36, _io_cpu_perf_canAcceptLoadThenLoad_T_34)
node _io_cpu_perf_canAcceptLoadThenLoad_T_38 = eq(s1_req.cmd, UInt<4>(0h8))
node _io_cpu_perf_canAcceptLoadThenLoad_T_39 = eq(s1_req.cmd, UInt<4>(0hc))
node _io_cpu_perf_canAcceptLoadThenLoad_T_40 = eq(s1_req.cmd, UInt<4>(0hd))
node _io_cpu_perf_canAcceptLoadThenLoad_T_41 = eq(s1_req.cmd, UInt<4>(0he))
node _io_cpu_perf_canAcceptLoadThenLoad_T_42 = eq(s1_req.cmd, UInt<4>(0hf))
node _io_cpu_perf_canAcceptLoadThenLoad_T_43 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_38, _io_cpu_perf_canAcceptLoadThenLoad_T_39)
node _io_cpu_perf_canAcceptLoadThenLoad_T_44 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_43, _io_cpu_perf_canAcceptLoadThenLoad_T_40)
node _io_cpu_perf_canAcceptLoadThenLoad_T_45 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_44, _io_cpu_perf_canAcceptLoadThenLoad_T_41)
node _io_cpu_perf_canAcceptLoadThenLoad_T_46 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_45, _io_cpu_perf_canAcceptLoadThenLoad_T_42)
node _io_cpu_perf_canAcceptLoadThenLoad_T_47 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_37, _io_cpu_perf_canAcceptLoadThenLoad_T_46)
node _io_cpu_perf_canAcceptLoadThenLoad_T_48 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_30, _io_cpu_perf_canAcceptLoadThenLoad_T_47)
node _io_cpu_perf_canAcceptLoadThenLoad_T_49 = eq(s1_req.cmd, UInt<5>(0h11))
node _io_cpu_perf_canAcceptLoadThenLoad_T_50 = lt(s1_req.size, UInt<1>(0h0))
node _io_cpu_perf_canAcceptLoadThenLoad_T_51 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_49, _io_cpu_perf_canAcceptLoadThenLoad_T_50)
node _io_cpu_perf_canAcceptLoadThenLoad_T_52 = and(_io_cpu_perf_canAcceptLoadThenLoad_T_48, _io_cpu_perf_canAcceptLoadThenLoad_T_51)
node _io_cpu_perf_canAcceptLoadThenLoad_T_53 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_25, _io_cpu_perf_canAcceptLoadThenLoad_T_52)
node _io_cpu_perf_canAcceptLoadThenLoad_T_54 = and(_io_cpu_perf_canAcceptLoadThenLoad_T, _io_cpu_perf_canAcceptLoadThenLoad_T_53)
node _io_cpu_perf_canAcceptLoadThenLoad_T_55 = and(s2_valid, s2_write)
node _io_cpu_perf_canAcceptLoadThenLoad_T_56 = eq(s2_waw_hazard, UInt<1>(0h0))
node _io_cpu_perf_canAcceptLoadThenLoad_T_57 = and(_io_cpu_perf_canAcceptLoadThenLoad_T_55, _io_cpu_perf_canAcceptLoadThenLoad_T_56)
node _io_cpu_perf_canAcceptLoadThenLoad_T_58 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_57, pstore1_held)
node _io_cpu_perf_canAcceptLoadThenLoad_T_59 = or(_io_cpu_perf_canAcceptLoadThenLoad_T_58, pstore2_valid)
node _io_cpu_perf_canAcceptLoadThenLoad_T_60 = and(_io_cpu_perf_canAcceptLoadThenLoad_T_54, _io_cpu_perf_canAcceptLoadThenLoad_T_59)
node _io_cpu_perf_canAcceptLoadThenLoad_T_61 = eq(_io_cpu_perf_canAcceptLoadThenLoad_T_60, UInt<1>(0h0))
connect io.cpu.perf.canAcceptLoadThenLoad, _io_cpu_perf_canAcceptLoadThenLoad_T_61
regreset io_cpu_perf_blocked_near_end_of_refill_refill_count : UInt<3>, clock, reset, UInt<3>(0h0)
node _io_cpu_perf_blocked_near_end_of_refill_T = and(nodeOut.d.ready, nodeOut.d.valid)
node _io_cpu_perf_blocked_near_end_of_refill_T_1 = and(_io_cpu_perf_blocked_near_end_of_refill_T, grantIsRefill)
when _io_cpu_perf_blocked_near_end_of_refill_T_1 :
node _io_cpu_perf_blocked_near_end_of_refill_refill_count_T = add(io_cpu_perf_blocked_near_end_of_refill_refill_count, UInt<1>(0h1))
node _io_cpu_perf_blocked_near_end_of_refill_refill_count_T_1 = tail(_io_cpu_perf_blocked_near_end_of_refill_refill_count_T, 1)
connect io_cpu_perf_blocked_near_end_of_refill_refill_count, _io_cpu_perf_blocked_near_end_of_refill_refill_count_T_1
node io_cpu_perf_blocked_near_end_of_refill = geq(io_cpu_perf_blocked_near_end_of_refill_refill_count, UInt<3>(0h6))
node _io_cpu_perf_blocked_T = eq(io_cpu_perf_blocked_near_end_of_refill, UInt<1>(0h0))
node _io_cpu_perf_blocked_T_1 = and(cached_grant_wait, _io_cpu_perf_blocked_T)
connect io.cpu.perf.blocked, _io_cpu_perf_blocked_T_1
node _error_addr_T = bits(metaArb.io.in[1].bits.addr, 13, 6)
node _error_addr_T_1 = cat(s2_meta_corrected_0.tag, _error_addr_T)
node _error_addr_T_2 = shr(s2_req.addr, 6)
node _error_addr_T_3 = mux(metaArb.io.in[1].valid, _error_addr_T_1, _error_addr_T_2)
node error_addr = shl(_error_addr_T_3, 6)
node _io_errors_bus_valid_T = and(nodeOut.d.ready, nodeOut.d.valid)
node _io_errors_bus_valid_T_1 = or(nodeOut.d.bits.denied, nodeOut.d.bits.corrupt)
node _io_errors_bus_valid_T_2 = and(_io_errors_bus_valid_T, _io_errors_bus_valid_T_1)
connect io.errors.bus.valid, _io_errors_bus_valid_T_2
node _io_errors_bus_bits_T = shr(s2_req.addr, 6)
node _io_errors_bus_bits_T_1 = shl(_io_errors_bus_bits_T, 6)
node _io_errors_bus_bits_T_2 = mux(grantIsCached, _io_errors_bus_bits_T_1, UInt<1>(0h0))
connect io.errors.bus.bits, _io_errors_bus_bits_T_2
node _T_126 = and(io.errors.bus.valid, grantIsCached)
node _T_127 = eq(grantIsCached, UInt<1>(0h0))
node _T_128 = and(io.errors.bus.valid, _T_127)
node _T_129 = eq(s2_valid_data_error, UInt<1>(0h0))
node _T_130 = eq(s2_data_error_uncorrectable, UInt<1>(0h0))
node _T_131 = and(s2_valid_data_error, _T_130)
node _T_132 = and(s2_valid_data_error, s2_data_error_uncorrectable)
node _T_133 = eq(s2_req.no_xcpt, UInt<1>(0h0))
node _T_134 = and(_T_129, s2_req.no_xcpt)
node _T_135 = and(_T_129, _T_133)
node _T_136 = and(_T_131, s2_req.no_xcpt)
node _T_137 = and(_T_131, _T_133)
node _T_138 = and(_T_132, s2_req.no_xcpt)
node _T_139 = and(_T_132, _T_133) | module DCache( // @[DCache.scala:101:7]
input clock, // @[DCache.scala:101:7]
input reset, // @[DCache.scala:101:7]
input auto_hart_id_sink_in, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_user_amba_prot_bufferable, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_user_amba_prot_modifiable, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_user_amba_prot_readalloc, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_user_amba_prot_writealloc, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_user_amba_prot_privileged, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output io_cpu_req_ready, // @[HellaCache.scala:243:14]
input io_cpu_req_valid, // @[HellaCache.scala:243:14]
input [33:0] io_cpu_req_bits_addr, // @[HellaCache.scala:243:14]
input [6:0] io_cpu_req_bits_tag, // @[HellaCache.scala:243:14]
input [4:0] io_cpu_req_bits_cmd, // @[HellaCache.scala:243:14]
input [1:0] io_cpu_req_bits_size, // @[HellaCache.scala:243:14]
input io_cpu_req_bits_signed, // @[HellaCache.scala:243:14]
input [1:0] io_cpu_req_bits_dprv, // @[HellaCache.scala:243:14]
input io_cpu_req_bits_dv, // @[HellaCache.scala:243:14]
input io_cpu_req_bits_phys, // @[HellaCache.scala:243:14]
input io_cpu_req_bits_no_resp, // @[HellaCache.scala:243:14]
input io_cpu_req_bits_no_xcpt, // @[HellaCache.scala:243:14]
input io_cpu_s1_kill, // @[HellaCache.scala:243:14]
input [63:0] io_cpu_s1_data_data, // @[HellaCache.scala:243:14]
input [7:0] io_cpu_s1_data_mask, // @[HellaCache.scala:243:14]
output io_cpu_s2_nack, // @[HellaCache.scala:243:14]
output io_cpu_s2_nack_cause_raw, // @[HellaCache.scala:243:14]
output io_cpu_s2_uncached, // @[HellaCache.scala:243:14]
output [31:0] io_cpu_s2_paddr, // @[HellaCache.scala:243:14]
output io_cpu_resp_valid, // @[HellaCache.scala:243:14]
output [33:0] io_cpu_resp_bits_addr, // @[HellaCache.scala:243:14]
output [6:0] io_cpu_resp_bits_tag, // @[HellaCache.scala:243:14]
output [4:0] io_cpu_resp_bits_cmd, // @[HellaCache.scala:243:14]
output [1:0] io_cpu_resp_bits_size, // @[HellaCache.scala:243:14]
output io_cpu_resp_bits_signed, // @[HellaCache.scala:243:14]
output [1:0] io_cpu_resp_bits_dprv, // @[HellaCache.scala:243:14]
output io_cpu_resp_bits_dv, // @[HellaCache.scala:243:14]
output [63:0] io_cpu_resp_bits_data, // @[HellaCache.scala:243:14]
output [7:0] io_cpu_resp_bits_mask, // @[HellaCache.scala:243:14]
output io_cpu_resp_bits_replay, // @[HellaCache.scala:243:14]
output io_cpu_resp_bits_has_data, // @[HellaCache.scala:243:14]
output [63:0] io_cpu_resp_bits_data_word_bypass, // @[HellaCache.scala:243:14]
output [63:0] io_cpu_resp_bits_data_raw, // @[HellaCache.scala:243:14]
output [63:0] io_cpu_resp_bits_store_data, // @[HellaCache.scala:243:14]
output io_cpu_replay_next, // @[HellaCache.scala:243:14]
output io_cpu_s2_xcpt_ma_ld, // @[HellaCache.scala:243:14]
output io_cpu_s2_xcpt_ma_st, // @[HellaCache.scala:243:14]
output io_cpu_s2_xcpt_pf_ld, // @[HellaCache.scala:243:14]
output io_cpu_s2_xcpt_pf_st, // @[HellaCache.scala:243:14]
output io_cpu_s2_xcpt_ae_ld, // @[HellaCache.scala:243:14]
output io_cpu_s2_xcpt_ae_st, // @[HellaCache.scala:243:14]
output [33:0] io_cpu_s2_gpa, // @[HellaCache.scala:243:14]
output io_cpu_ordered, // @[HellaCache.scala:243:14]
output io_cpu_store_pending, // @[HellaCache.scala:243:14]
output io_cpu_perf_acquire, // @[HellaCache.scala:243:14]
output io_cpu_perf_grant, // @[HellaCache.scala:243:14]
output io_cpu_perf_blocked, // @[HellaCache.scala:243:14]
output io_cpu_perf_canAcceptStoreThenLoad, // @[HellaCache.scala:243:14]
output io_cpu_perf_canAcceptStoreThenRMW, // @[HellaCache.scala:243:14]
output io_cpu_perf_canAcceptLoadThenLoad, // @[HellaCache.scala:243:14]
output io_cpu_perf_storeBufferEmptyAfterLoad, // @[HellaCache.scala:243:14]
output io_cpu_perf_storeBufferEmptyAfterStore, // @[HellaCache.scala:243:14]
input io_cpu_keep_clock_enabled, // @[HellaCache.scala:243:14]
input io_ptw_req_ready, // @[HellaCache.scala:243:14]
output [20:0] io_ptw_req_bits_bits_addr, // @[HellaCache.scala:243:14]
output io_ptw_req_bits_bits_need_gpa, // @[HellaCache.scala:243:14]
output io_ptw_req_bits_bits_vstage1, // @[HellaCache.scala:243:14]
output io_ptw_req_bits_bits_stage2, // @[HellaCache.scala:243:14]
input io_ptw_resp_valid, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_ae_ptw, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_ae_final, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_pf, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_gf, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_hr, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_hw, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_hx, // @[HellaCache.scala:243:14]
input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[HellaCache.scala:243:14]
input [43:0] io_ptw_resp_bits_pte_ppn, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_pte_d, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_pte_a, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_pte_g, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_pte_u, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_pte_x, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_pte_w, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_pte_r, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_pte_v, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_resp_bits_level, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_homogeneous, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_gpa_valid, // @[HellaCache.scala:243:14]
input [32:0] io_ptw_resp_bits_gpa_bits, // @[HellaCache.scala:243:14]
input io_ptw_resp_bits_gpa_is_pte, // @[HellaCache.scala:243:14]
input io_ptw_status_debug, // @[HellaCache.scala:243:14]
input io_ptw_status_cease, // @[HellaCache.scala:243:14]
input io_ptw_status_wfi, // @[HellaCache.scala:243:14]
input [31:0] io_ptw_status_isa, // @[HellaCache.scala:243:14]
input io_ptw_status_dv, // @[HellaCache.scala:243:14]
input io_ptw_status_v, // @[HellaCache.scala:243:14]
input io_ptw_status_sd, // @[HellaCache.scala:243:14]
input io_ptw_status_mpv, // @[HellaCache.scala:243:14]
input io_ptw_status_gva, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_status_fs, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_status_mpp, // @[HellaCache.scala:243:14]
input io_ptw_status_mpie, // @[HellaCache.scala:243:14]
input io_ptw_status_mie, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_debug, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_cease, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_wfi, // @[HellaCache.scala:243:14]
input [31:0] io_ptw_gstatus_isa, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_gstatus_dprv, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_dv, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_gstatus_prv, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_v, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_sd, // @[HellaCache.scala:243:14]
input [22:0] io_ptw_gstatus_zero2, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_mpv, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_gva, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_mbe, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_sbe, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_gstatus_sxl, // @[HellaCache.scala:243:14]
input [7:0] io_ptw_gstatus_zero1, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_tsr, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_tw, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_tvm, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_mxr, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_sum, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_mprv, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_gstatus_fs, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_gstatus_mpp, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_gstatus_vs, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_spp, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_mpie, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_ube, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_spie, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_upie, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_mie, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_hie, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_sie, // @[HellaCache.scala:243:14]
input io_ptw_gstatus_uie, // @[HellaCache.scala:243:14]
input io_ptw_pmp_0_cfg_l, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_pmp_0_cfg_a, // @[HellaCache.scala:243:14]
input io_ptw_pmp_0_cfg_x, // @[HellaCache.scala:243:14]
input io_ptw_pmp_0_cfg_w, // @[HellaCache.scala:243:14]
input io_ptw_pmp_0_cfg_r, // @[HellaCache.scala:243:14]
input [29:0] io_ptw_pmp_0_addr, // @[HellaCache.scala:243:14]
input [31:0] io_ptw_pmp_0_mask, // @[HellaCache.scala:243:14]
input io_ptw_pmp_1_cfg_l, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_pmp_1_cfg_a, // @[HellaCache.scala:243:14]
input io_ptw_pmp_1_cfg_x, // @[HellaCache.scala:243:14]
input io_ptw_pmp_1_cfg_w, // @[HellaCache.scala:243:14]
input io_ptw_pmp_1_cfg_r, // @[HellaCache.scala:243:14]
input [29:0] io_ptw_pmp_1_addr, // @[HellaCache.scala:243:14]
input [31:0] io_ptw_pmp_1_mask, // @[HellaCache.scala:243:14]
input io_ptw_pmp_2_cfg_l, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_pmp_2_cfg_a, // @[HellaCache.scala:243:14]
input io_ptw_pmp_2_cfg_x, // @[HellaCache.scala:243:14]
input io_ptw_pmp_2_cfg_w, // @[HellaCache.scala:243:14]
input io_ptw_pmp_2_cfg_r, // @[HellaCache.scala:243:14]
input [29:0] io_ptw_pmp_2_addr, // @[HellaCache.scala:243:14]
input [31:0] io_ptw_pmp_2_mask, // @[HellaCache.scala:243:14]
input io_ptw_pmp_3_cfg_l, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_pmp_3_cfg_a, // @[HellaCache.scala:243:14]
input io_ptw_pmp_3_cfg_x, // @[HellaCache.scala:243:14]
input io_ptw_pmp_3_cfg_w, // @[HellaCache.scala:243:14]
input io_ptw_pmp_3_cfg_r, // @[HellaCache.scala:243:14]
input [29:0] io_ptw_pmp_3_addr, // @[HellaCache.scala:243:14]
input [31:0] io_ptw_pmp_3_mask, // @[HellaCache.scala:243:14]
input io_ptw_pmp_4_cfg_l, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_pmp_4_cfg_a, // @[HellaCache.scala:243:14]
input io_ptw_pmp_4_cfg_x, // @[HellaCache.scala:243:14]
input io_ptw_pmp_4_cfg_w, // @[HellaCache.scala:243:14]
input io_ptw_pmp_4_cfg_r, // @[HellaCache.scala:243:14]
input [29:0] io_ptw_pmp_4_addr, // @[HellaCache.scala:243:14]
input [31:0] io_ptw_pmp_4_mask, // @[HellaCache.scala:243:14]
input io_ptw_pmp_5_cfg_l, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_pmp_5_cfg_a, // @[HellaCache.scala:243:14]
input io_ptw_pmp_5_cfg_x, // @[HellaCache.scala:243:14]
input io_ptw_pmp_5_cfg_w, // @[HellaCache.scala:243:14]
input io_ptw_pmp_5_cfg_r, // @[HellaCache.scala:243:14]
input [29:0] io_ptw_pmp_5_addr, // @[HellaCache.scala:243:14]
input [31:0] io_ptw_pmp_5_mask, // @[HellaCache.scala:243:14]
input io_ptw_pmp_6_cfg_l, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_pmp_6_cfg_a, // @[HellaCache.scala:243:14]
input io_ptw_pmp_6_cfg_x, // @[HellaCache.scala:243:14]
input io_ptw_pmp_6_cfg_w, // @[HellaCache.scala:243:14]
input io_ptw_pmp_6_cfg_r, // @[HellaCache.scala:243:14]
input [29:0] io_ptw_pmp_6_addr, // @[HellaCache.scala:243:14]
input [31:0] io_ptw_pmp_6_mask, // @[HellaCache.scala:243:14]
input io_ptw_pmp_7_cfg_l, // @[HellaCache.scala:243:14]
input [1:0] io_ptw_pmp_7_cfg_a, // @[HellaCache.scala:243:14]
input io_ptw_pmp_7_cfg_x, // @[HellaCache.scala:243:14]
input io_ptw_pmp_7_cfg_w, // @[HellaCache.scala:243:14]
input io_ptw_pmp_7_cfg_r, // @[HellaCache.scala:243:14]
input [29:0] io_ptw_pmp_7_addr, // @[HellaCache.scala:243:14]
input [31:0] io_ptw_pmp_7_mask, // @[HellaCache.scala:243:14]
input io_ptw_customCSRs_csrs_0_ren, // @[HellaCache.scala:243:14]
input io_ptw_customCSRs_csrs_0_wen, // @[HellaCache.scala:243:14]
input [63:0] io_ptw_customCSRs_csrs_0_wdata, // @[HellaCache.scala:243:14]
input [63:0] io_ptw_customCSRs_csrs_0_value, // @[HellaCache.scala:243:14]
input io_ptw_customCSRs_csrs_1_ren, // @[HellaCache.scala:243:14]
input io_ptw_customCSRs_csrs_1_wen, // @[HellaCache.scala:243:14]
input [63:0] io_ptw_customCSRs_csrs_1_wdata, // @[HellaCache.scala:243:14]
input [63:0] io_ptw_customCSRs_csrs_1_value, // @[HellaCache.scala:243:14]
input io_ptw_customCSRs_csrs_2_ren, // @[HellaCache.scala:243:14]
input io_ptw_customCSRs_csrs_2_wen, // @[HellaCache.scala:243:14]
input [63:0] io_ptw_customCSRs_csrs_2_wdata, // @[HellaCache.scala:243:14]
input [63:0] io_ptw_customCSRs_csrs_2_value, // @[HellaCache.scala:243:14]
input io_ptw_customCSRs_csrs_3_ren, // @[HellaCache.scala:243:14]
input io_ptw_customCSRs_csrs_3_wen, // @[HellaCache.scala:243:14]
input [63:0] io_ptw_customCSRs_csrs_3_wdata, // @[HellaCache.scala:243:14]
input [63:0] io_ptw_customCSRs_csrs_3_value // @[HellaCache.scala:243:14]
);
wire [63:0] s1_all_data_ways_0; // @[DCache.scala:325:33]
wire s0_req_phys; // @[DCache.scala:192:24]
wire [33:0] s0_req_addr; // @[DCache.scala:192:24]
wire tl_out_a_valid; // @[DCache.scala:159:22]
wire [63:0] tl_out_a_bits_data; // @[DCache.scala:159:22]
wire [7:0] tl_out_a_bits_mask; // @[DCache.scala:159:22]
wire [31:0] tl_out_a_bits_address; // @[DCache.scala:159:22]
wire [3:0] tl_out_a_bits_size; // @[DCache.scala:159:22]
wire [2:0] tl_out_a_bits_param; // @[DCache.scala:159:22]
wire [2:0] tl_out_a_bits_opcode; // @[DCache.scala:159:22]
wire tl_out_a_bits_user_amba_prot_privileged; // @[DCache.scala:159:22]
wire tl_out_a_bits_user_amba_prot_writealloc; // @[DCache.scala:159:22]
wire tl_out_a_bits_user_amba_prot_readalloc; // @[DCache.scala:159:22]
wire tl_out_a_bits_user_amba_prot_modifiable; // @[DCache.scala:159:22]
wire tl_out_a_bits_user_amba_prot_bufferable; // @[DCache.scala:159:22]
wire metaArb_io_in_2_valid; // @[DCache.scala:135:28]
wire [4:0] pma_checker_io_req_bits_cmd; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_req_bits_size; // @[DCache.scala:120:32]
wire [63:0] _amoalus_0_io_out_unmasked; // @[DCache.scala:982:26]
wire _lfsr_prng_io_out_0; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_1; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_2; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_3; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_4; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_5; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_6; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_7; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_8; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_9; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_10; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_11; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_12; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_13; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_14; // @[PRNG.scala:91:22]
wire _lfsr_prng_io_out_15; // @[PRNG.scala:91:22]
wire _pma_checker_entries_barrier_12_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_12_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_11_io_y_c; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_10_io_y_c; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_9_io_y_c; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_8_io_y_c; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_7_io_y_c; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_6_io_y_c; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_5_io_y_c; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_4_io_y_c; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_3_io_y_c; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_2_io_y_c; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_1_io_y_c; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_u; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_ae_ptw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_ae_final; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_ae_stage2; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_pf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_gf; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_sw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_sx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_sr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_hw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_hx; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_hr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_pw; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_px; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_pr; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_ppp; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_pal; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_paa; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_eff; // @[package.scala:267:25]
wire _pma_checker_entries_barrier_io_y_c; // @[package.scala:267:25]
wire _pma_checker_pma_io_resp_r; // @[TLB.scala:422:19]
wire _pma_checker_pma_io_resp_w; // @[TLB.scala:422:19]
wire _pma_checker_pma_io_resp_pp; // @[TLB.scala:422:19]
wire _pma_checker_pma_io_resp_al; // @[TLB.scala:422:19]
wire _pma_checker_pma_io_resp_aa; // @[TLB.scala:422:19]
wire _pma_checker_pma_io_resp_x; // @[TLB.scala:422:19]
wire _pma_checker_pma_io_resp_eff; // @[TLB.scala:422:19]
wire _pma_checker_pmp_io_r; // @[TLB.scala:416:19]
wire _pma_checker_pmp_io_w; // @[TLB.scala:416:19]
wire _pma_checker_pmp_io_x; // @[TLB.scala:416:19]
wire [31:0] _tlb_io_resp_paddr; // @[DCache.scala:119:19]
wire [33:0] _tlb_io_resp_gpa; // @[DCache.scala:119:19]
wire _tlb_io_resp_pf_ld; // @[DCache.scala:119:19]
wire _tlb_io_resp_pf_st; // @[DCache.scala:119:19]
wire _tlb_io_resp_pf_inst; // @[DCache.scala:119:19]
wire _tlb_io_resp_ae_ld; // @[DCache.scala:119:19]
wire _tlb_io_resp_ae_st; // @[DCache.scala:119:19]
wire _tlb_io_resp_ae_inst; // @[DCache.scala:119:19]
wire _tlb_io_resp_ma_ld; // @[DCache.scala:119:19]
wire _tlb_io_resp_ma_st; // @[DCache.scala:119:19]
wire _tlb_io_resp_cacheable; // @[DCache.scala:119:19]
wire _tlb_io_resp_must_alloc; // @[DCache.scala:119:19]
wire _tlb_io_resp_prefetchable; // @[DCache.scala:119:19]
wire [1:0] _tlb_io_resp_size; // @[DCache.scala:119:19]
wire [4:0] _tlb_io_resp_cmd; // @[DCache.scala:119:19]
wire auto_hart_id_sink_in_0 = auto_hart_id_sink_in; // @[DCache.scala:101:7]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[DCache.scala:101:7]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[DCache.scala:101:7]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[DCache.scala:101:7]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[DCache.scala:101:7]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[DCache.scala:101:7]
wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[DCache.scala:101:7]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[DCache.scala:101:7]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[DCache.scala:101:7]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[DCache.scala:101:7]
wire io_cpu_req_valid_0 = io_cpu_req_valid; // @[DCache.scala:101:7]
wire [33:0] io_cpu_req_bits_addr_0 = io_cpu_req_bits_addr; // @[DCache.scala:101:7]
wire [6:0] io_cpu_req_bits_tag_0 = io_cpu_req_bits_tag; // @[DCache.scala:101:7]
wire [4:0] io_cpu_req_bits_cmd_0 = io_cpu_req_bits_cmd; // @[DCache.scala:101:7]
wire [1:0] io_cpu_req_bits_size_0 = io_cpu_req_bits_size; // @[DCache.scala:101:7]
wire io_cpu_req_bits_signed_0 = io_cpu_req_bits_signed; // @[DCache.scala:101:7]
wire [1:0] io_cpu_req_bits_dprv_0 = io_cpu_req_bits_dprv; // @[DCache.scala:101:7]
wire io_cpu_req_bits_dv_0 = io_cpu_req_bits_dv; // @[DCache.scala:101:7]
wire io_cpu_req_bits_phys_0 = io_cpu_req_bits_phys; // @[DCache.scala:101:7]
wire io_cpu_req_bits_no_resp_0 = io_cpu_req_bits_no_resp; // @[DCache.scala:101:7]
wire io_cpu_req_bits_no_xcpt_0 = io_cpu_req_bits_no_xcpt; // @[DCache.scala:101:7]
wire io_cpu_s1_kill_0 = io_cpu_s1_kill; // @[DCache.scala:101:7]
wire [63:0] io_cpu_s1_data_data_0 = io_cpu_s1_data_data; // @[DCache.scala:101:7]
wire [7:0] io_cpu_s1_data_mask_0 = io_cpu_s1_data_mask; // @[DCache.scala:101:7]
wire io_cpu_keep_clock_enabled_0 = io_cpu_keep_clock_enabled; // @[DCache.scala:101:7]
wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[DCache.scala:101:7]
wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[DCache.scala:101:7]
wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[DCache.scala:101:7]
wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[DCache.scala:101:7]
wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[DCache.scala:101:7]
wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[DCache.scala:101:7]
wire [32:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[DCache.scala:101:7]
wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[DCache.scala:101:7]
wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[DCache.scala:101:7]
wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[DCache.scala:101:7]
wire [31:0] io_ptw_status_isa_0 = io_ptw_status_isa; // @[DCache.scala:101:7]
wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[DCache.scala:101:7]
wire io_ptw_status_v_0 = io_ptw_status_v; // @[DCache.scala:101:7]
wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[DCache.scala:101:7]
wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[DCache.scala:101:7]
wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[DCache.scala:101:7]
wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[DCache.scala:101:7]
wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[DCache.scala:101:7]
wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[DCache.scala:101:7]
wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[DCache.scala:101:7]
wire io_ptw_gstatus_debug_0 = io_ptw_gstatus_debug; // @[DCache.scala:101:7]
wire io_ptw_gstatus_cease_0 = io_ptw_gstatus_cease; // @[DCache.scala:101:7]
wire io_ptw_gstatus_wfi_0 = io_ptw_gstatus_wfi; // @[DCache.scala:101:7]
wire [31:0] io_ptw_gstatus_isa_0 = io_ptw_gstatus_isa; // @[DCache.scala:101:7]
wire [1:0] io_ptw_gstatus_dprv_0 = io_ptw_gstatus_dprv; // @[DCache.scala:101:7]
wire io_ptw_gstatus_dv_0 = io_ptw_gstatus_dv; // @[DCache.scala:101:7]
wire [1:0] io_ptw_gstatus_prv_0 = io_ptw_gstatus_prv; // @[DCache.scala:101:7]
wire io_ptw_gstatus_v_0 = io_ptw_gstatus_v; // @[DCache.scala:101:7]
wire io_ptw_gstatus_sd_0 = io_ptw_gstatus_sd; // @[DCache.scala:101:7]
wire [22:0] io_ptw_gstatus_zero2_0 = io_ptw_gstatus_zero2; // @[DCache.scala:101:7]
wire io_ptw_gstatus_mpv_0 = io_ptw_gstatus_mpv; // @[DCache.scala:101:7]
wire io_ptw_gstatus_gva_0 = io_ptw_gstatus_gva; // @[DCache.scala:101:7]
wire io_ptw_gstatus_mbe_0 = io_ptw_gstatus_mbe; // @[DCache.scala:101:7]
wire io_ptw_gstatus_sbe_0 = io_ptw_gstatus_sbe; // @[DCache.scala:101:7]
wire [1:0] io_ptw_gstatus_sxl_0 = io_ptw_gstatus_sxl; // @[DCache.scala:101:7]
wire [7:0] io_ptw_gstatus_zero1_0 = io_ptw_gstatus_zero1; // @[DCache.scala:101:7]
wire io_ptw_gstatus_tsr_0 = io_ptw_gstatus_tsr; // @[DCache.scala:101:7]
wire io_ptw_gstatus_tw_0 = io_ptw_gstatus_tw; // @[DCache.scala:101:7]
wire io_ptw_gstatus_tvm_0 = io_ptw_gstatus_tvm; // @[DCache.scala:101:7]
wire io_ptw_gstatus_mxr_0 = io_ptw_gstatus_mxr; // @[DCache.scala:101:7]
wire io_ptw_gstatus_sum_0 = io_ptw_gstatus_sum; // @[DCache.scala:101:7]
wire io_ptw_gstatus_mprv_0 = io_ptw_gstatus_mprv; // @[DCache.scala:101:7]
wire [1:0] io_ptw_gstatus_fs_0 = io_ptw_gstatus_fs; // @[DCache.scala:101:7]
wire [1:0] io_ptw_gstatus_mpp_0 = io_ptw_gstatus_mpp; // @[DCache.scala:101:7]
wire [1:0] io_ptw_gstatus_vs_0 = io_ptw_gstatus_vs; // @[DCache.scala:101:7]
wire io_ptw_gstatus_spp_0 = io_ptw_gstatus_spp; // @[DCache.scala:101:7]
wire io_ptw_gstatus_mpie_0 = io_ptw_gstatus_mpie; // @[DCache.scala:101:7]
wire io_ptw_gstatus_ube_0 = io_ptw_gstatus_ube; // @[DCache.scala:101:7]
wire io_ptw_gstatus_spie_0 = io_ptw_gstatus_spie; // @[DCache.scala:101:7]
wire io_ptw_gstatus_upie_0 = io_ptw_gstatus_upie; // @[DCache.scala:101:7]
wire io_ptw_gstatus_mie_0 = io_ptw_gstatus_mie; // @[DCache.scala:101:7]
wire io_ptw_gstatus_hie_0 = io_ptw_gstatus_hie; // @[DCache.scala:101:7]
wire io_ptw_gstatus_sie_0 = io_ptw_gstatus_sie; // @[DCache.scala:101:7]
wire io_ptw_gstatus_uie_0 = io_ptw_gstatus_uie; // @[DCache.scala:101:7]
wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[DCache.scala:101:7]
wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[DCache.scala:101:7]
wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[DCache.scala:101:7]
wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[DCache.scala:101:7]
wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[DCache.scala:101:7]
wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[DCache.scala:101:7]
wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[DCache.scala:101:7]
wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[DCache.scala:101:7]
wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[DCache.scala:101:7]
wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[DCache.scala:101:7]
wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[DCache.scala:101:7]
wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[DCache.scala:101:7]
wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[DCache.scala:101:7]
wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[DCache.scala:101:7]
wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[DCache.scala:101:7]
wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[DCache.scala:101:7]
wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[DCache.scala:101:7]
wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[DCache.scala:101:7]
wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[DCache.scala:101:7]
wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[DCache.scala:101:7]
wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[DCache.scala:101:7]
wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[DCache.scala:101:7]
wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[DCache.scala:101:7]
wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[DCache.scala:101:7]
wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[DCache.scala:101:7]
wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[DCache.scala:101:7]
wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[DCache.scala:101:7]
wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[DCache.scala:101:7]
wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[DCache.scala:101:7]
wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[DCache.scala:101:7]
wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[DCache.scala:101:7]
wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[DCache.scala:101:7]
wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[DCache.scala:101:7]
wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[DCache.scala:101:7]
wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[DCache.scala:101:7]
wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[DCache.scala:101:7]
wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[DCache.scala:101:7]
wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[DCache.scala:101:7]
wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[DCache.scala:101:7]
wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[DCache.scala:101:7]
wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[DCache.scala:101:7]
wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[DCache.scala:101:7]
wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[DCache.scala:101:7]
wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[DCache.scala:101:7]
wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[DCache.scala:101:7]
wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[DCache.scala:101:7]
wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[DCache.scala:101:7]
wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[DCache.scala:101:7]
wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[DCache.scala:101:7]
wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[DCache.scala:101:7]
wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[DCache.scala:101:7]
wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[DCache.scala:101:7]
wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[DCache.scala:101:7]
wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[DCache.scala:101:7]
wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[DCache.scala:101:7]
wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[DCache.scala:101:7]
wire io_ptw_customCSRs_csrs_0_ren_0 = io_ptw_customCSRs_csrs_0_ren; // @[DCache.scala:101:7]
wire io_ptw_customCSRs_csrs_0_wen_0 = io_ptw_customCSRs_csrs_0_wen; // @[DCache.scala:101:7]
wire [63:0] io_ptw_customCSRs_csrs_0_wdata_0 = io_ptw_customCSRs_csrs_0_wdata; // @[DCache.scala:101:7]
wire [63:0] io_ptw_customCSRs_csrs_0_value_0 = io_ptw_customCSRs_csrs_0_value; // @[DCache.scala:101:7]
wire io_ptw_customCSRs_csrs_1_ren_0 = io_ptw_customCSRs_csrs_1_ren; // @[DCache.scala:101:7]
wire io_ptw_customCSRs_csrs_1_wen_0 = io_ptw_customCSRs_csrs_1_wen; // @[DCache.scala:101:7]
wire [63:0] io_ptw_customCSRs_csrs_1_wdata_0 = io_ptw_customCSRs_csrs_1_wdata; // @[DCache.scala:101:7]
wire [63:0] io_ptw_customCSRs_csrs_1_value_0 = io_ptw_customCSRs_csrs_1_value; // @[DCache.scala:101:7]
wire io_ptw_customCSRs_csrs_2_ren_0 = io_ptw_customCSRs_csrs_2_ren; // @[DCache.scala:101:7]
wire io_ptw_customCSRs_csrs_2_wen_0 = io_ptw_customCSRs_csrs_2_wen; // @[DCache.scala:101:7]
wire [63:0] io_ptw_customCSRs_csrs_2_wdata_0 = io_ptw_customCSRs_csrs_2_wdata; // @[DCache.scala:101:7]
wire [63:0] io_ptw_customCSRs_csrs_2_value_0 = io_ptw_customCSRs_csrs_2_value; // @[DCache.scala:101:7]
wire io_ptw_customCSRs_csrs_3_ren_0 = io_ptw_customCSRs_csrs_3_ren; // @[DCache.scala:101:7]
wire io_ptw_customCSRs_csrs_3_wen_0 = io_ptw_customCSRs_csrs_3_wen; // @[DCache.scala:101:7]
wire [63:0] io_ptw_customCSRs_csrs_3_wdata_0 = io_ptw_customCSRs_csrs_3_wdata; // @[DCache.scala:101:7]
wire [63:0] io_ptw_customCSRs_csrs_3_value_0 = io_ptw_customCSRs_csrs_3_value; // @[DCache.scala:101:7]
wire _dataArb_io_in_3_valid_T_55 = reset; // @[DCache.scala:1186:11]
wire _pstore_drain_opportunistic_T_55 = reset; // @[DCache.scala:1186:11]
wire auto_mmio_address_prefix_sink_in = 1'h0; // @[DCache.scala:101:7]
wire auto_out_a_bits_source = 1'h0; // @[DCache.scala:101:7]
wire auto_out_a_bits_user_amba_prot_fetch = 1'h0; // @[DCache.scala:101:7]
wire auto_out_a_bits_corrupt = 1'h0; // @[DCache.scala:101:7]
wire auto_out_d_bits_source = 1'h0; // @[DCache.scala:101:7]
wire io_cpu_req_bits_no_alloc = 1'h0; // @[DCache.scala:101:7]
wire io_cpu_s2_kill = 1'h0; // @[DCache.scala:101:7]
wire io_cpu_s2_xcpt_gf_ld = 1'h0; // @[DCache.scala:101:7]
wire io_cpu_s2_xcpt_gf_st = 1'h0; // @[DCache.scala:101:7]
wire io_cpu_s2_gpa_is_pte = 1'h0; // @[DCache.scala:101:7]
wire io_cpu_perf_release = 1'h0; // @[DCache.scala:101:7]
wire io_cpu_perf_tlbMiss = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_req_valid = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_status_mbe = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_status_sbe = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_status_sd_rv32 = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_status_tsr = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_status_tw = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_status_tvm = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_status_mxr = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_status_sum = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_status_mprv = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_status_spp = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_status_ube = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_status_spie = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_status_upie = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_status_hie = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_status_sie = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_status_uie = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_hstatus_vtsr = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_hstatus_vtw = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_hstatus_vtvm = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_hstatus_hu = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_hstatus_spvp = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_hstatus_spv = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_hstatus_gva = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_hstatus_vsbe = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[DCache.scala:101:7]
wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[DCache.scala:101:7]
wire io_tlb_port_req_valid = 1'h0; // @[DCache.scala:101:7]
wire io_tlb_port_req_bits_passthrough = 1'h0; // @[DCache.scala:101:7]
wire io_tlb_port_req_bits_v = 1'h0; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_miss = 1'h0; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_gpa_is_pte = 1'h0; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_gf_ld = 1'h0; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_gf_st = 1'h0; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_gf_inst = 1'h0; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_ma_inst = 1'h0; // @[DCache.scala:101:7]
wire io_tlb_port_s2_kill = 1'h0; // @[DCache.scala:101:7]
wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_user_amba_prot_fetch = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire mmioAddressPrefixSinkNodeOptIn = 1'h0; // @[MixedNode.scala:551:17]
wire pma_checker_io_req_valid = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_resp_miss = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_resp_gpa_is_pte = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_resp_gf_ld = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_resp_gf_st = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_resp_gf_inst = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_resp_ma_inst = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_sfence_valid = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_sfence_bits_rs1 = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_sfence_bits_rs2 = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_sfence_bits_asid = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_sfence_bits_hv = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_sfence_bits_hg = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_req_ready = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_req_valid = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_req_bits_bits_need_gpa = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_req_bits_bits_vstage1 = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_req_bits_bits_stage2 = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_valid = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_ae_ptw = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_ae_final = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_pf = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_gf = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_hr = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_hw = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_hx = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_pte_d = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_pte_a = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_pte_g = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_pte_u = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_pte_x = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_pte_w = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_pte_r = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_pte_v = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_homogeneous = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_gpa_valid = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_resp_bits_gpa_is_pte = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_debug = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_cease = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_wfi = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_dv = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_v = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_sd = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_mpv = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_gva = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_mbe = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_sbe = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_sd_rv32 = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_tsr = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_tw = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_tvm = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_mxr = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_sum = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_mprv = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_spp = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_mpie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_ube = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_spie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_upie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_mie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_hie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_sie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_status_uie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_hstatus_vtsr = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_hstatus_vtw = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_hstatus_vtvm = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_hstatus_hu = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_hstatus_spvp = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_hstatus_spv = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_hstatus_gva = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_hstatus_vsbe = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_debug = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_cease = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_wfi = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_dv = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_v = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_sd = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_mpv = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_gva = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_mbe = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_sbe = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_sd_rv32 = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_tsr = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_tw = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_tvm = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_mxr = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_sum = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_mprv = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_spp = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_mpie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_ube = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_spie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_upie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_mie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_hie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_sie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_gstatus_uie = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_0_cfg_l = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_0_cfg_x = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_0_cfg_w = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_0_cfg_r = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_1_cfg_l = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_1_cfg_x = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_1_cfg_w = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_1_cfg_r = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_2_cfg_l = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_2_cfg_x = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_2_cfg_w = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_2_cfg_r = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_3_cfg_l = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_3_cfg_x = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_3_cfg_w = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_3_cfg_r = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_4_cfg_l = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_4_cfg_x = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_4_cfg_w = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_4_cfg_r = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_5_cfg_l = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_5_cfg_x = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_5_cfg_w = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_5_cfg_r = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_6_cfg_l = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_6_cfg_x = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_6_cfg_w = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_6_cfg_r = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_7_cfg_l = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_7_cfg_x = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_7_cfg_w = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_pmp_7_cfg_r = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_customCSRs_csrs_0_set = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_customCSRs_csrs_1_set = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_customCSRs_csrs_2_ren = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_customCSRs_csrs_2_wen = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_customCSRs_csrs_2_set = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_customCSRs_csrs_3_ren = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_customCSRs_csrs_3_wen = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_customCSRs_csrs_3_set = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_io_kill = 1'h0; // @[DCache.scala:120:32]
wire pma_checker_priv_v = 1'h0; // @[TLB.scala:369:34]
wire pma_checker__stage1_en_T = 1'h0; // @[TLB.scala:374:41]
wire pma_checker_stage1_en = 1'h0; // @[TLB.scala:374:29]
wire pma_checker__vstage1_en_T = 1'h0; // @[TLB.scala:376:38]
wire pma_checker__vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68]
wire pma_checker_vstage1_en = 1'h0; // @[TLB.scala:376:48]
wire pma_checker__stage2_en_T = 1'h0; // @[TLB.scala:378:38]
wire pma_checker__stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68]
wire pma_checker_stage2_en = 1'h0; // @[TLB.scala:378:48]
wire pma_checker__vm_enabled_T = 1'h0; // @[TLB.scala:399:31]
wire pma_checker__vm_enabled_T_1 = 1'h0; // @[TLB.scala:399:45]
wire pma_checker__vm_enabled_T_2 = 1'h0; // @[TLB.scala:399:64]
wire pma_checker_vm_enabled = 1'h0; // @[TLB.scala:399:61]
wire pma_checker__vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52]
wire pma_checker__vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37]
wire pma_checker__vsatp_mode_mismatch_T_2 = 1'h0; // @[TLB.scala:403:81]
wire pma_checker_vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78]
wire pma_checker_do_refill = 1'h0; // @[TLB.scala:408:29]
wire pma_checker__invalidate_refill_T = 1'h0; // @[package.scala:16:47]
wire pma_checker__invalidate_refill_T_1 = 1'h0; // @[package.scala:16:47]
wire pma_checker__invalidate_refill_T_2 = 1'h0; // @[package.scala:81:59]
wire pma_checker_invalidate_refill = 1'h0; // @[TLB.scala:410:88]
wire pma_checker__mpu_ppn_T = 1'h0; // @[TLB.scala:413:32]
wire pma_checker__mpu_priv_T_1 = 1'h0; // @[TLB.scala:415:38]
wire pma_checker_cacheable = 1'h0; // @[TLB.scala:425:41]
wire pma_checker__sector_hits_T = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_8 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_16 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_24 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_32 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_40 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_48 = 1'h0; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_56 = 1'h0; // @[package.scala:81:59]
wire pma_checker_superpage_hits_0 = 1'h0; // @[TLB.scala:188:18]
wire pma_checker_superpage_hits_1 = 1'h0; // @[TLB.scala:188:18]
wire pma_checker_superpage_hits_2 = 1'h0; // @[TLB.scala:188:18]
wire pma_checker_superpage_hits_3 = 1'h0; // @[TLB.scala:188:18]
wire pma_checker__hitsVec_T_5 = 1'h0; // @[TLB.scala:188:18]
wire pma_checker_hitsVec_0 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker__hitsVec_T_11 = 1'h0; // @[TLB.scala:188:18]
wire pma_checker_hitsVec_1 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker__hitsVec_T_17 = 1'h0; // @[TLB.scala:188:18]
wire pma_checker_hitsVec_2 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker__hitsVec_T_23 = 1'h0; // @[TLB.scala:188:18]
wire pma_checker_hitsVec_3 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker__hitsVec_T_29 = 1'h0; // @[TLB.scala:188:18]
wire pma_checker_hitsVec_4 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker__hitsVec_T_35 = 1'h0; // @[TLB.scala:188:18]
wire pma_checker_hitsVec_5 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker__hitsVec_T_41 = 1'h0; // @[TLB.scala:188:18]
wire pma_checker_hitsVec_6 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker__hitsVec_T_47 = 1'h0; // @[TLB.scala:188:18]
wire pma_checker_hitsVec_7 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker__hitsVec_T_53 = 1'h0; // @[TLB.scala:188:18]
wire pma_checker_hitsVec_8 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker__hitsVec_T_59 = 1'h0; // @[TLB.scala:188:18]
wire pma_checker_hitsVec_9 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker__hitsVec_T_65 = 1'h0; // @[TLB.scala:188:18]
wire pma_checker_hitsVec_10 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker__hitsVec_T_71 = 1'h0; // @[TLB.scala:188:18]
wire pma_checker_hitsVec_11 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker_hitsVec_12 = 1'h0; // @[TLB.scala:440:44]
wire pma_checker_refill_v = 1'h0; // @[TLB.scala:448:33]
wire pma_checker_newEntry_u = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_g = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_ae_ptw = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_ae_final = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_pf = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_gf = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_sw = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_sx = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_sr = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_hw = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_hx = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_hr = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_c = 1'h0; // @[TLB.scala:449:24]
wire pma_checker_newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24]
wire pma_checker__newEntry_g_T = 1'h0; // @[TLB.scala:453:25]
wire pma_checker__newEntry_ae_stage2_T = 1'h0; // @[TLB.scala:456:53]
wire pma_checker__newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84]
wire pma_checker__newEntry_sr_T_1 = 1'h0; // @[PTW.scala:141:44]
wire pma_checker__newEntry_sr_T_2 = 1'h0; // @[PTW.scala:141:38]
wire pma_checker__newEntry_sr_T_3 = 1'h0; // @[PTW.scala:141:32]
wire pma_checker__newEntry_sr_T_4 = 1'h0; // @[PTW.scala:141:52]
wire pma_checker__newEntry_sr_T_5 = 1'h0; // @[PTW.scala:149:35]
wire pma_checker__newEntry_sw_T_1 = 1'h0; // @[PTW.scala:141:44]
wire pma_checker__newEntry_sw_T_2 = 1'h0; // @[PTW.scala:141:38]
wire pma_checker__newEntry_sw_T_3 = 1'h0; // @[PTW.scala:141:32]
wire pma_checker__newEntry_sw_T_4 = 1'h0; // @[PTW.scala:141:52]
wire pma_checker__newEntry_sw_T_5 = 1'h0; // @[PTW.scala:151:35]
wire pma_checker__newEntry_sw_T_6 = 1'h0; // @[PTW.scala:151:40]
wire pma_checker__newEntry_sx_T_1 = 1'h0; // @[PTW.scala:141:44]
wire pma_checker__newEntry_sx_T_2 = 1'h0; // @[PTW.scala:141:38]
wire pma_checker__newEntry_sx_T_3 = 1'h0; // @[PTW.scala:141:32]
wire pma_checker__newEntry_sx_T_4 = 1'h0; // @[PTW.scala:141:52]
wire pma_checker__newEntry_sx_T_5 = 1'h0; // @[PTW.scala:153:35]
wire pma_checker__waddr_T = 1'h0; // @[TLB.scala:477:45]
wire pma_checker__superpage_entries_0_level_T = 1'h0; // @[package.scala:163:13]
wire pma_checker__superpage_entries_1_level_T = 1'h0; // @[package.scala:163:13]
wire pma_checker__superpage_entries_2_level_T = 1'h0; // @[package.scala:163:13]
wire pma_checker__superpage_entries_3_level_T = 1'h0; // @[package.scala:163:13]
wire pma_checker_sum = 1'h0; // @[TLB.scala:510:16]
wire pma_checker__mxr_T = 1'h0; // @[TLB.scala:518:36]
wire pma_checker_mxr = 1'h0; // @[TLB.scala:518:31]
wire pma_checker__prefetchable_array_T = 1'h0; // @[TLB.scala:547:43]
wire pma_checker_cmd_readx = 1'h0; // @[TLB.scala:575:37]
wire pma_checker__gf_ld_array_T = 1'h0; // @[TLB.scala:600:32]
wire pma_checker__gf_st_array_T = 1'h0; // @[TLB.scala:601:32]
wire pma_checker__gpa_hits_hit_mask_T_1 = 1'h0; // @[TLB.scala:606:60]
wire pma_checker_tlb_hit_if_not_gpa_miss = 1'h0; // @[TLB.scala:610:43]
wire pma_checker_tlb_hit = 1'h0; // @[TLB.scala:611:40]
wire pma_checker__tlb_miss_T_1 = 1'h0; // @[TLB.scala:613:29]
wire pma_checker__tlb_miss_T_3 = 1'h0; // @[TLB.scala:613:53]
wire pma_checker_tlb_miss = 1'h0; // @[TLB.scala:613:64]
wire pma_checker_state_vec_0_left_subtree_state_1 = 1'h0; // @[package.scala:163:13]
wire pma_checker_state_vec_0_right_subtree_state_1 = 1'h0; // @[Replacement.scala:198:38]
wire pma_checker_state_vec_0_left_subtree_state_2 = 1'h0; // @[package.scala:163:13]
wire pma_checker_state_vec_0_right_subtree_state_2 = 1'h0; // @[Replacement.scala:198:38]
wire pma_checker_state_reg_left_subtree_state = 1'h0; // @[package.scala:163:13]
wire pma_checker_state_reg_right_subtree_state = 1'h0; // @[Replacement.scala:198:38]
wire pma_checker__multipleHits_T_2 = 1'h0; // @[Misc.scala:181:37]
wire pma_checker_multipleHits_leftOne = 1'h0; // @[Misc.scala:178:18]
wire pma_checker__multipleHits_T_4 = 1'h0; // @[Misc.scala:181:37]
wire pma_checker_multipleHits_leftOne_1 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker__multipleHits_T_5 = 1'h0; // @[Misc.scala:182:39]
wire pma_checker_multipleHits_rightOne = 1'h0; // @[Misc.scala:178:18]
wire pma_checker_multipleHits_rightOne_1 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_6 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_7 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_rightTwo = 1'h0; // @[Misc.scala:183:49]
wire pma_checker_multipleHits_leftOne_2 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_8 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_9 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_leftTwo = 1'h0; // @[Misc.scala:183:49]
wire pma_checker__multipleHits_T_11 = 1'h0; // @[Misc.scala:181:37]
wire pma_checker_multipleHits_leftOne_3 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker__multipleHits_T_13 = 1'h0; // @[Misc.scala:181:37]
wire pma_checker_multipleHits_leftOne_4 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker__multipleHits_T_14 = 1'h0; // @[Misc.scala:182:39]
wire pma_checker_multipleHits_rightOne_2 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker_multipleHits_rightOne_3 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_15 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_16 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_rightTwo_1 = 1'h0; // @[Misc.scala:183:49]
wire pma_checker_multipleHits_rightOne_4 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_17 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_18 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_rightTwo_2 = 1'h0; // @[Misc.scala:183:49]
wire pma_checker_multipleHits_leftOne_5 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_19 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_20 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_leftTwo_1 = 1'h0; // @[Misc.scala:183:49]
wire pma_checker__multipleHits_T_23 = 1'h0; // @[Misc.scala:181:37]
wire pma_checker_multipleHits_leftOne_6 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker__multipleHits_T_25 = 1'h0; // @[Misc.scala:181:37]
wire pma_checker_multipleHits_leftOne_7 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker__multipleHits_T_26 = 1'h0; // @[Misc.scala:182:39]
wire pma_checker_multipleHits_rightOne_5 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker_multipleHits_rightOne_6 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_27 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_28 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_rightTwo_3 = 1'h0; // @[Misc.scala:183:49]
wire pma_checker_multipleHits_leftOne_8 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_29 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_30 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_leftTwo_2 = 1'h0; // @[Misc.scala:183:49]
wire pma_checker__multipleHits_T_33 = 1'h0; // @[Misc.scala:181:37]
wire pma_checker_multipleHits_leftOne_9 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker__multipleHits_T_34 = 1'h0; // @[Misc.scala:182:39]
wire pma_checker_multipleHits_rightOne_7 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker_multipleHits_leftOne_10 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_35 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_36 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_leftTwo_3 = 1'h0; // @[Misc.scala:183:49]
wire pma_checker__multipleHits_T_38 = 1'h0; // @[Misc.scala:181:37]
wire pma_checker_multipleHits_leftOne_11 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker__multipleHits_T_39 = 1'h0; // @[Misc.scala:182:39]
wire pma_checker_multipleHits_rightOne_8 = 1'h0; // @[Misc.scala:178:18]
wire pma_checker_multipleHits_rightOne_9 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_40 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_41 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_rightTwo_4 = 1'h0; // @[Misc.scala:183:49]
wire pma_checker_multipleHits_rightOne_10 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_42 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_43 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_rightTwo_5 = 1'h0; // @[Misc.scala:183:49]
wire pma_checker_multipleHits_rightOne_11 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_44 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_45 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits_rightTwo_6 = 1'h0; // @[Misc.scala:183:49]
wire pma_checker__multipleHits_T_46 = 1'h0; // @[Misc.scala:183:16]
wire pma_checker__multipleHits_T_47 = 1'h0; // @[Misc.scala:183:37]
wire pma_checker__multipleHits_T_48 = 1'h0; // @[Misc.scala:183:61]
wire pma_checker_multipleHits = 1'h0; // @[Misc.scala:183:49]
wire pma_checker__io_resp_pf_ld_T = 1'h0; // @[TLB.scala:633:28]
wire pma_checker__io_resp_pf_st_T = 1'h0; // @[TLB.scala:634:28]
wire pma_checker__io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29]
wire pma_checker__io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66]
wire pma_checker__io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42]
wire pma_checker__io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29]
wire pma_checker__io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73]
wire pma_checker__io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49]
wire pma_checker__io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56]
wire pma_checker__io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30]
wire pma_checker__io_resp_miss_T = 1'h0; // @[TLB.scala:651:29]
wire pma_checker__io_resp_miss_T_1 = 1'h0; // @[TLB.scala:651:52]
wire pma_checker__io_resp_miss_T_2 = 1'h0; // @[TLB.scala:651:64]
wire pma_checker__io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36]
wire pma_checker__io_ptw_req_valid_T = 1'h0; // @[TLB.scala:662:29]
wire metaArb_io_in_0_valid = 1'h0; // @[DCache.scala:135:28]
wire metaArb_io_in_1_valid = 1'h0; // @[DCache.scala:135:28]
wire metaArb_io_in_1_bits_way_en = 1'h0; // @[DCache.scala:135:28]
wire metaArb_io_in_4_valid = 1'h0; // @[DCache.scala:135:28]
wire metaArb_io_in_5_valid = 1'h0; // @[DCache.scala:135:28]
wire metaArb_io_in_5_bits_write = 1'h0; // @[DCache.scala:135:28]
wire metaArb_io_in_6_valid = 1'h0; // @[DCache.scala:135:28]
wire metaArb_io_in_6_bits_write = 1'h0; // @[DCache.scala:135:28]
wire metaArb_io_in_7_bits_write = 1'h0; // @[DCache.scala:135:28]
wire metaArb__grant_T = 1'h0; // @[Arbiter.scala:45:68]
wire dataArb_io_in_2_valid = 1'h0; // @[DCache.scala:152:28]
wire dataArb_io_in_2_bits_write = 1'h0; // @[DCache.scala:152:28]
wire dataArb_io_in_3_bits_write = 1'h0; // @[DCache.scala:152:28]
wire tl_out_a_bits_source = 1'h0; // @[DCache.scala:159:22]
wire tl_out_a_bits_user_amba_prot_fetch = 1'h0; // @[DCache.scala:159:22]
wire tl_out_a_bits_corrupt = 1'h0; // @[DCache.scala:159:22]
wire nodeOut_a_deq_bits_source = 1'h0; // @[Decoupled.scala:356:21]
wire nodeOut_a_deq_bits_user_amba_prot_fetch = 1'h0; // @[Decoupled.scala:356:21]
wire nodeOut_a_deq_bits_corrupt = 1'h0; // @[Decoupled.scala:356:21]
wire tl_out_c_ready = 1'h0; // @[Bundles.scala:265:61]
wire tl_out_c_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire tl_out_c_bits_user_amba_prot_fetch = 1'h0; // @[Bundles.scala:265:61]
wire tl_out_c_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _s1_probe_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _s1_probe_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _s1_probe_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74]
wire _s1_probe_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _s1_probe_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _s1_probe_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _s1_probe_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61]
wire _s1_probe_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _s1_probe_T = 1'h0; // @[Decoupled.scala:51:35]
wire _probe_bits_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _probe_bits_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _probe_bits_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74]
wire _probe_bits_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _probe_bits_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _probe_bits_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _probe_bits_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61]
wire _probe_bits_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _probe_bits_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74]
wire _probe_bits_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74]
wire _probe_bits_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:264:74]
wire _probe_bits_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _probe_bits_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61]
wire _probe_bits_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61]
wire _probe_bits_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:264:61]
wire _probe_bits_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _probe_bits_T = 1'h0; // @[Decoupled.scala:51:35]
wire _s1_tlb_req_valid_T = 1'h0; // @[Decoupled.scala:51:35]
wire s0_req_no_alloc = 1'h0; // @[DCache.scala:192:24]
wire s1_waw_hazard = 1'h0; // @[DCache.scala:216:27]
wire _inWriteback_T = 1'h0; // @[package.scala:16:47]
wire _inWriteback_T_1 = 1'h0; // @[package.scala:16:47]
wire inWriteback = 1'h0; // @[package.scala:81:59]
wire _uncachedInFlight_WIRE_0 = 1'h0; // @[DCache.scala:236:41]
wire _dataArb_io_in_3_valid_res_T_4 = 1'h0; // @[DCache.scala:1185:58]
wire _dataArb_io_in_3_valid_T_49 = 1'h0; // @[DCache.scala:1191:57]
wire _s1_did_read_T_49 = 1'h0; // @[DCache.scala:1191:57]
wire _tlb_io_kill_T = 1'h0; // @[DCache.scala:272:53]
wire _tlb_io_kill_T_1 = 1'h0; // @[DCache.scala:272:33]
wire s1_victim_way = 1'h0; // @[DCache.scala:299:27]
wire _releaseInFlight_T = 1'h0; // @[DCache.scala:334:34]
wire _releaseInFlight_T_1 = 1'h0; // @[DCache.scala:334:63]
wire releaseInFlight = 1'h0; // @[DCache.scala:334:46]
wire _s2_pma_T_miss = 1'h0; // @[DCache.scala:349:18]
wire _s2_pma_T_gpa_is_pte = 1'h0; // @[DCache.scala:349:18]
wire _s2_pma_T_gf_ld = 1'h0; // @[DCache.scala:349:18]
wire _s2_pma_T_gf_st = 1'h0; // @[DCache.scala:349:18]
wire _s2_pma_T_gf_inst = 1'h0; // @[DCache.scala:349:18]
wire _s2_pma_T_ma_inst = 1'h0; // @[DCache.scala:349:18]
wire s2_meta_error_uncorrectable = 1'h0; // @[DCache.scala:360:66]
wire _s2_meta_error_T = 1'h0; // @[DCache.scala:362:53]
wire s2_meta_error = 1'h0; // @[DCache.scala:362:83]
wire s2_store_merge = 1'h0; // @[DCache.scala:388:28]
wire _r_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _s2_data_error_T = 1'h0; // @[ECC.scala:15:27]
wire _s2_data_error_T_1 = 1'h0; // @[ECC.scala:15:27]
wire _s2_data_error_T_2 = 1'h0; // @[ECC.scala:15:27]
wire _s2_data_error_T_3 = 1'h0; // @[ECC.scala:15:27]
wire _s2_data_error_T_4 = 1'h0; // @[ECC.scala:15:27]
wire _s2_data_error_T_5 = 1'h0; // @[ECC.scala:15:27]
wire _s2_data_error_T_6 = 1'h0; // @[ECC.scala:15:27]
wire _s2_data_error_T_7 = 1'h0; // @[ECC.scala:15:27]
wire _s2_data_error_T_8 = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_T_9 = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_T_10 = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_T_11 = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_T_12 = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_T_13 = 1'h0; // @[package.scala:81:59]
wire s2_data_error = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_uncorrectable_T = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_uncorrectable_T_1 = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_uncorrectable_T_2 = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_uncorrectable_T_3 = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_uncorrectable_T_4 = 1'h0; // @[package.scala:81:59]
wire _s2_data_error_uncorrectable_T_5 = 1'h0; // @[package.scala:81:59]
wire s2_data_error_uncorrectable = 1'h0; // @[package.scala:81:59]
wire s2_valid_data_error = 1'h0; // @[DCache.scala:421:63]
wire s2_want_victimize = 1'h0; // @[DCache.scala:427:52]
wire s2_cannot_victimize = 1'h0; // @[DCache.scala:428:45]
wire s2_victimize = 1'h0; // @[DCache.scala:429:40]
wire _r_T_73 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_77 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_81 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_119 = 1'h0; // @[Metadata.scala:140:24]
wire _r_T_121 = 1'h0; // @[Metadata.scala:140:24]
wire _r_T_137 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_141 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_145 = 1'h0; // @[Misc.scala:38:9]
wire _s2_dont_nack_misc_T_2 = 1'h0; // @[DCache.scala:442:23]
wire _s2_dont_nack_misc_T_3 = 1'h0; // @[DCache.scala:442:43]
wire _s2_dont_nack_misc_T_5 = 1'h0; // @[DCache.scala:442:54]
wire _s2_dont_nack_misc_T_6 = 1'h0; // @[DCache.scala:443:23]
wire _s2_dont_nack_misc_T_8 = 1'h0; // @[DCache.scala:443:44]
wire _s2_dont_nack_misc_T_9 = 1'h0; // @[DCache.scala:442:67]
wire _s2_first_meta_corrected_T = 1'h0; // @[Mux.scala:52:83]
wire _metaArb_io_in_1_valid_T_2 = 1'h0; // @[DCache.scala:450:43]
wire _metaArb_io_in_1_bits_way_en_T = 1'h0; // @[OneHot.scala:85:71]
wire _metaArb_io_in_1_bits_way_en_T_1 = 1'h0; // @[Mux.scala:50:70]
wire _metaArb_io_in_1_bits_way_en_T_2 = 1'h0; // @[DCache.scala:452:69]
wire _metaArb_io_in_1_bits_way_en_T_3 = 1'h0; // @[DCache.scala:452:64]
wire s2_lr = 1'h0; // @[DCache.scala:470:56]
wire s2_sc = 1'h0; // @[DCache.scala:471:56]
wire s2_sc_fail = 1'h0; // @[DCache.scala:477:26]
wire _s2_correct_T_1 = 1'h0; // @[DCache.scala:487:34]
wire _s2_correct_T_4 = 1'h0; // @[DCache.scala:487:55]
wire s2_correct = 1'h0; // @[DCache.scala:487:97]
wire _s2_valid_correct_T = 1'h0; // @[DCache.scala:489:60]
wire s2_valid_correct = 1'h0; // @[DCache.scala:489:74]
wire _pstore1_rmw_T_49 = 1'h0; // @[DCache.scala:1191:57]
wire pstore1_merge_likely = 1'h0; // @[DCache.scala:499:68]
wire pstore1_merge = 1'h0; // @[DCache.scala:500:38]
wire _pstore_drain_opportunistic_res_T_4 = 1'h0; // @[DCache.scala:1185:58]
wire _pstore_drain_opportunistic_T_49 = 1'h0; // @[DCache.scala:1191:57]
wire _pstore_drain_opportunistic_T_60 = 1'h0; // @[DCache.scala:502:106]
wire pstore_drain_s2_kill = 1'h0; // @[DCache.scala:515:25]
wire _pstore2_storegen_data_T_2 = 1'h0; // @[DCache.scala:528:95]
wire _pstore2_storegen_data_T_6 = 1'h0; // @[DCache.scala:528:95]
wire _pstore2_storegen_data_T_10 = 1'h0; // @[DCache.scala:528:95]
wire _pstore2_storegen_data_T_14 = 1'h0; // @[DCache.scala:528:95]
wire _pstore2_storegen_data_T_18 = 1'h0; // @[DCache.scala:528:95]
wire _pstore2_storegen_data_T_22 = 1'h0; // @[DCache.scala:528:95]
wire _pstore2_storegen_data_T_26 = 1'h0; // @[DCache.scala:528:95]
wire _pstore2_storegen_data_T_30 = 1'h0; // @[DCache.scala:528:95]
wire dataArb_io_in_0_valid_s2_kill = 1'h0; // @[DCache.scala:515:25]
wire _dataArb_io_in_0_bits_wordMask_T_1 = 1'h0; // @[DCache.scala:555:20]
wire _io_cpu_s2_nack_cause_raw_T_2 = 1'h0; // @[DCache.scala:574:57]
wire get_source = 1'h0; // @[Edges.scala:460:17]
wire get_user_amba_prot_bufferable = 1'h0; // @[Edges.scala:460:17]
wire get_user_amba_prot_modifiable = 1'h0; // @[Edges.scala:460:17]
wire get_user_amba_prot_readalloc = 1'h0; // @[Edges.scala:460:17]
wire get_user_amba_prot_writealloc = 1'h0; // @[Edges.scala:460:17]
wire get_user_amba_prot_privileged = 1'h0; // @[Edges.scala:460:17]
wire get_user_amba_prot_secure = 1'h0; // @[Edges.scala:460:17]
wire get_user_amba_prot_fetch = 1'h0; // @[Edges.scala:460:17]
wire get_corrupt = 1'h0; // @[Edges.scala:460:17]
wire _put_legal_T_44 = 1'h0; // @[Parameters.scala:684:29]
wire _put_legal_T_50 = 1'h0; // @[Parameters.scala:684:54]
wire put_source = 1'h0; // @[Edges.scala:480:17]
wire put_user_amba_prot_bufferable = 1'h0; // @[Edges.scala:480:17]
wire put_user_amba_prot_modifiable = 1'h0; // @[Edges.scala:480:17]
wire put_user_amba_prot_readalloc = 1'h0; // @[Edges.scala:480:17]
wire put_user_amba_prot_writealloc = 1'h0; // @[Edges.scala:480:17]
wire put_user_amba_prot_privileged = 1'h0; // @[Edges.scala:480:17]
wire put_user_amba_prot_secure = 1'h0; // @[Edges.scala:480:17]
wire put_user_amba_prot_fetch = 1'h0; // @[Edges.scala:480:17]
wire put_corrupt = 1'h0; // @[Edges.scala:480:17]
wire _putpartial_legal_T_44 = 1'h0; // @[Parameters.scala:684:29]
wire _putpartial_legal_T_50 = 1'h0; // @[Parameters.scala:684:54]
wire putpartial_source = 1'h0; // @[Edges.scala:500:17]
wire putpartial_user_amba_prot_bufferable = 1'h0; // @[Edges.scala:500:17]
wire putpartial_user_amba_prot_modifiable = 1'h0; // @[Edges.scala:500:17]
wire putpartial_user_amba_prot_readalloc = 1'h0; // @[Edges.scala:500:17]
wire putpartial_user_amba_prot_writealloc = 1'h0; // @[Edges.scala:500:17]
wire putpartial_user_amba_prot_privileged = 1'h0; // @[Edges.scala:500:17]
wire putpartial_user_amba_prot_secure = 1'h0; // @[Edges.scala:500:17]
wire putpartial_user_amba_prot_fetch = 1'h0; // @[Edges.scala:500:17]
wire putpartial_corrupt = 1'h0; // @[Edges.scala:500:17]
wire _atomics_WIRE_source = 1'h0; // @[DCache.scala:587:51]
wire _atomics_WIRE_user_amba_prot_bufferable = 1'h0; // @[DCache.scala:587:51]
wire _atomics_WIRE_user_amba_prot_modifiable = 1'h0; // @[DCache.scala:587:51]
wire _atomics_WIRE_user_amba_prot_readalloc = 1'h0; // @[DCache.scala:587:51]
wire _atomics_WIRE_user_amba_prot_writealloc = 1'h0; // @[DCache.scala:587:51]
wire _atomics_WIRE_user_amba_prot_privileged = 1'h0; // @[DCache.scala:587:51]
wire _atomics_WIRE_user_amba_prot_secure = 1'h0; // @[DCache.scala:587:51]
wire _atomics_WIRE_user_amba_prot_fetch = 1'h0; // @[DCache.scala:587:51]
wire _atomics_WIRE_corrupt = 1'h0; // @[DCache.scala:587:51]
wire _atomics_WIRE_1_source = 1'h0; // @[DCache.scala:587:38]
wire _atomics_WIRE_1_user_amba_prot_bufferable = 1'h0; // @[DCache.scala:587:38]
wire _atomics_WIRE_1_user_amba_prot_modifiable = 1'h0; // @[DCache.scala:587:38]
wire _atomics_WIRE_1_user_amba_prot_readalloc = 1'h0; // @[DCache.scala:587:38]
wire _atomics_WIRE_1_user_amba_prot_writealloc = 1'h0; // @[DCache.scala:587:38]
wire _atomics_WIRE_1_user_amba_prot_privileged = 1'h0; // @[DCache.scala:587:38]
wire _atomics_WIRE_1_user_amba_prot_secure = 1'h0; // @[DCache.scala:587:38]
wire _atomics_WIRE_1_user_amba_prot_fetch = 1'h0; // @[DCache.scala:587:38]
wire _atomics_WIRE_1_corrupt = 1'h0; // @[DCache.scala:587:38]
wire _atomics_legal_T_22 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_34 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_source = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_user_amba_prot_bufferable = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_user_amba_prot_modifiable = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_user_amba_prot_readalloc = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_user_amba_prot_writealloc = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_user_amba_prot_privileged = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_user_amba_prot_secure = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_user_amba_prot_fetch = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_corrupt = 1'h0; // @[Edges.scala:534:17]
wire _atomics_legal_T_58 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_70 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_1_source = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_1_user_amba_prot_bufferable = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_1_user_amba_prot_modifiable = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_1_user_amba_prot_readalloc = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_1_user_amba_prot_writealloc = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_1_user_amba_prot_privileged = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_1_user_amba_prot_secure = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_1_user_amba_prot_fetch = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_1_corrupt = 1'h0; // @[Edges.scala:534:17]
wire _atomics_legal_T_94 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_106 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_2_source = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_2_user_amba_prot_bufferable = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_2_user_amba_prot_modifiable = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_2_user_amba_prot_readalloc = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_2_user_amba_prot_writealloc = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_2_user_amba_prot_privileged = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_2_user_amba_prot_secure = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_2_user_amba_prot_fetch = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_2_corrupt = 1'h0; // @[Edges.scala:534:17]
wire _atomics_legal_T_130 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_142 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_3_source = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_3_user_amba_prot_bufferable = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_3_user_amba_prot_modifiable = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_3_user_amba_prot_readalloc = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_3_user_amba_prot_writealloc = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_3_user_amba_prot_privileged = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_3_user_amba_prot_secure = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_3_user_amba_prot_fetch = 1'h0; // @[Edges.scala:534:17]
wire atomics_a_3_corrupt = 1'h0; // @[Edges.scala:534:17]
wire _atomics_legal_T_166 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_178 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_4_source = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_4_user_amba_prot_bufferable = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_4_user_amba_prot_modifiable = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_4_user_amba_prot_readalloc = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_4_user_amba_prot_writealloc = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_4_user_amba_prot_privileged = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_4_user_amba_prot_secure = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_4_user_amba_prot_fetch = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_4_corrupt = 1'h0; // @[Edges.scala:517:17]
wire _atomics_legal_T_202 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_214 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_5_source = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_5_user_amba_prot_bufferable = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_5_user_amba_prot_modifiable = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_5_user_amba_prot_readalloc = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_5_user_amba_prot_writealloc = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_5_user_amba_prot_privileged = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_5_user_amba_prot_secure = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_5_user_amba_prot_fetch = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_5_corrupt = 1'h0; // @[Edges.scala:517:17]
wire _atomics_legal_T_238 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_250 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_6_source = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_6_user_amba_prot_bufferable = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_6_user_amba_prot_modifiable = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_6_user_amba_prot_readalloc = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_6_user_amba_prot_writealloc = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_6_user_amba_prot_privileged = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_6_user_amba_prot_secure = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_6_user_amba_prot_fetch = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_6_corrupt = 1'h0; // @[Edges.scala:517:17]
wire _atomics_legal_T_274 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_286 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_7_source = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_7_user_amba_prot_bufferable = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_7_user_amba_prot_modifiable = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_7_user_amba_prot_readalloc = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_7_user_amba_prot_writealloc = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_7_user_amba_prot_privileged = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_7_user_amba_prot_secure = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_7_user_amba_prot_fetch = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_7_corrupt = 1'h0; // @[Edges.scala:517:17]
wire _atomics_legal_T_310 = 1'h0; // @[Parameters.scala:684:29]
wire _atomics_legal_T_322 = 1'h0; // @[Parameters.scala:684:54]
wire atomics_a_8_source = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_8_user_amba_prot_bufferable = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_8_user_amba_prot_modifiable = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_8_user_amba_prot_readalloc = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_8_user_amba_prot_writealloc = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_8_user_amba_prot_privileged = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_8_user_amba_prot_secure = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_8_user_amba_prot_fetch = 1'h0; // @[Edges.scala:517:17]
wire atomics_a_8_corrupt = 1'h0; // @[Edges.scala:517:17]
wire _atomics_T_1_source = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_1_user_amba_prot_bufferable = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_1_user_amba_prot_modifiable = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_1_user_amba_prot_readalloc = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_1_user_amba_prot_writealloc = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_1_user_amba_prot_privileged = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_1_user_amba_prot_secure = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_1_user_amba_prot_fetch = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_1_corrupt = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_3_source = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_3_user_amba_prot_bufferable = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_3_user_amba_prot_modifiable = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_3_user_amba_prot_readalloc = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_3_user_amba_prot_writealloc = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_3_user_amba_prot_privileged = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_3_user_amba_prot_secure = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_3_user_amba_prot_fetch = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_3_corrupt = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_5_source = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_5_user_amba_prot_bufferable = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_5_user_amba_prot_modifiable = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_5_user_amba_prot_readalloc = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_5_user_amba_prot_writealloc = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_5_user_amba_prot_privileged = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_5_user_amba_prot_secure = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_5_user_amba_prot_fetch = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_5_corrupt = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_7_source = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_7_user_amba_prot_bufferable = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_7_user_amba_prot_modifiable = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_7_user_amba_prot_readalloc = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_7_user_amba_prot_writealloc = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_7_user_amba_prot_privileged = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_7_user_amba_prot_secure = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_7_user_amba_prot_fetch = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_7_corrupt = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_9_source = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_9_user_amba_prot_bufferable = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_9_user_amba_prot_modifiable = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_9_user_amba_prot_readalloc = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_9_user_amba_prot_writealloc = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_9_user_amba_prot_privileged = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_9_user_amba_prot_secure = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_9_user_amba_prot_fetch = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_9_corrupt = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_11_source = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_11_user_amba_prot_bufferable = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_11_user_amba_prot_modifiable = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_11_user_amba_prot_readalloc = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_11_user_amba_prot_writealloc = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_11_user_amba_prot_privileged = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_11_user_amba_prot_secure = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_11_user_amba_prot_fetch = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_11_corrupt = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_13_source = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_13_user_amba_prot_bufferable = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_13_user_amba_prot_modifiable = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_13_user_amba_prot_readalloc = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_13_user_amba_prot_writealloc = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_13_user_amba_prot_privileged = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_13_user_amba_prot_secure = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_13_user_amba_prot_fetch = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_13_corrupt = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_15_source = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_15_user_amba_prot_bufferable = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_15_user_amba_prot_modifiable = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_15_user_amba_prot_readalloc = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_15_user_amba_prot_writealloc = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_15_user_amba_prot_privileged = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_15_user_amba_prot_secure = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_15_user_amba_prot_fetch = 1'h0; // @[DCache.scala:587:81]
wire _atomics_T_15_corrupt = 1'h0; // @[DCache.scala:587:81]
wire atomics_source = 1'h0; // @[DCache.scala:587:81]
wire atomics_user_amba_prot_bufferable = 1'h0; // @[DCache.scala:587:81]
wire atomics_user_amba_prot_modifiable = 1'h0; // @[DCache.scala:587:81]
wire atomics_user_amba_prot_readalloc = 1'h0; // @[DCache.scala:587:81]
wire atomics_user_amba_prot_writealloc = 1'h0; // @[DCache.scala:587:81]
wire atomics_user_amba_prot_privileged = 1'h0; // @[DCache.scala:587:81]
wire atomics_user_amba_prot_secure = 1'h0; // @[DCache.scala:587:81]
wire atomics_user_amba_prot_fetch = 1'h0; // @[DCache.scala:587:81]
wire atomics_corrupt = 1'h0; // @[DCache.scala:587:81]
wire _tl_out_a_valid_T_4 = 1'h0; // @[DCache.scala:606:27]
wire _tl_out_a_valid_T_8 = 1'h0; // @[DCache.scala:607:44]
wire _tl_out_a_valid_T_9 = 1'h0; // @[DCache.scala:607:65]
wire _tl_out_a_bits_WIRE_source = 1'h0; // @[DCache.scala:1209:67]
wire _tl_out_a_bits_WIRE_user_amba_prot_bufferable = 1'h0; // @[DCache.scala:1209:67]
wire _tl_out_a_bits_WIRE_user_amba_prot_modifiable = 1'h0; // @[DCache.scala:1209:67]
wire _tl_out_a_bits_WIRE_user_amba_prot_readalloc = 1'h0; // @[DCache.scala:1209:67]
wire _tl_out_a_bits_WIRE_user_amba_prot_writealloc = 1'h0; // @[DCache.scala:1209:67]
wire _tl_out_a_bits_WIRE_user_amba_prot_privileged = 1'h0; // @[DCache.scala:1209:67]
wire _tl_out_a_bits_WIRE_user_amba_prot_secure = 1'h0; // @[DCache.scala:1209:67]
wire _tl_out_a_bits_WIRE_user_amba_prot_fetch = 1'h0; // @[DCache.scala:1209:67]
wire _tl_out_a_bits_WIRE_corrupt = 1'h0; // @[DCache.scala:1209:67]
wire _tl_out_a_bits_WIRE_1_source = 1'h0; // @[DCache.scala:1209:54]
wire _tl_out_a_bits_WIRE_1_user_amba_prot_bufferable = 1'h0; // @[DCache.scala:1209:54]
wire _tl_out_a_bits_WIRE_1_user_amba_prot_modifiable = 1'h0; // @[DCache.scala:1209:54]
wire _tl_out_a_bits_WIRE_1_user_amba_prot_readalloc = 1'h0; // @[DCache.scala:1209:54]
wire _tl_out_a_bits_WIRE_1_user_amba_prot_writealloc = 1'h0; // @[DCache.scala:1209:54]
wire _tl_out_a_bits_WIRE_1_user_amba_prot_privileged = 1'h0; // @[DCache.scala:1209:54]
wire _tl_out_a_bits_WIRE_1_user_amba_prot_secure = 1'h0; // @[DCache.scala:1209:54]
wire _tl_out_a_bits_WIRE_1_user_amba_prot_fetch = 1'h0; // @[DCache.scala:1209:54]
wire _tl_out_a_bits_WIRE_1_corrupt = 1'h0; // @[DCache.scala:1209:54]
wire _tl_out_a_bits_T_4_source = 1'h0; // @[DCache.scala:611:8]
wire _tl_out_a_bits_T_4_user_amba_prot_bufferable = 1'h0; // @[DCache.scala:611:8]
wire _tl_out_a_bits_T_4_user_amba_prot_modifiable = 1'h0; // @[DCache.scala:611:8]
wire _tl_out_a_bits_T_4_user_amba_prot_readalloc = 1'h0; // @[DCache.scala:611:8]
wire _tl_out_a_bits_T_4_user_amba_prot_writealloc = 1'h0; // @[DCache.scala:611:8]
wire _tl_out_a_bits_T_4_user_amba_prot_privileged = 1'h0; // @[DCache.scala:611:8]
wire _tl_out_a_bits_T_4_user_amba_prot_secure = 1'h0; // @[DCache.scala:611:8]
wire _tl_out_a_bits_T_4_user_amba_prot_fetch = 1'h0; // @[DCache.scala:611:8]
wire _tl_out_a_bits_T_4_corrupt = 1'h0; // @[DCache.scala:611:8]
wire _tl_out_a_bits_T_5_source = 1'h0; // @[DCache.scala:610:8]
wire _tl_out_a_bits_T_5_user_amba_prot_bufferable = 1'h0; // @[DCache.scala:610:8]
wire _tl_out_a_bits_T_5_user_amba_prot_modifiable = 1'h0; // @[DCache.scala:610:8]
wire _tl_out_a_bits_T_5_user_amba_prot_readalloc = 1'h0; // @[DCache.scala:610:8]
wire _tl_out_a_bits_T_5_user_amba_prot_writealloc = 1'h0; // @[DCache.scala:610:8]
wire _tl_out_a_bits_T_5_user_amba_prot_privileged = 1'h0; // @[DCache.scala:610:8]
wire _tl_out_a_bits_T_5_user_amba_prot_secure = 1'h0; // @[DCache.scala:610:8]
wire _tl_out_a_bits_T_5_user_amba_prot_fetch = 1'h0; // @[DCache.scala:610:8]
wire _tl_out_a_bits_T_5_corrupt = 1'h0; // @[DCache.scala:610:8]
wire _tl_out_a_bits_T_6_source = 1'h0; // @[DCache.scala:609:8]
wire _tl_out_a_bits_T_6_user_amba_prot_bufferable = 1'h0; // @[DCache.scala:609:8]
wire _tl_out_a_bits_T_6_user_amba_prot_modifiable = 1'h0; // @[DCache.scala:609:8]
wire _tl_out_a_bits_T_6_user_amba_prot_readalloc = 1'h0; // @[DCache.scala:609:8]
wire _tl_out_a_bits_T_6_user_amba_prot_writealloc = 1'h0; // @[DCache.scala:609:8]
wire _tl_out_a_bits_T_6_user_amba_prot_privileged = 1'h0; // @[DCache.scala:609:8]
wire _tl_out_a_bits_T_6_user_amba_prot_secure = 1'h0; // @[DCache.scala:609:8]
wire _tl_out_a_bits_T_6_user_amba_prot_fetch = 1'h0; // @[DCache.scala:609:8]
wire _tl_out_a_bits_T_6_corrupt = 1'h0; // @[DCache.scala:609:8]
wire _tl_out_a_bits_T_7_source = 1'h0; // @[DCache.scala:608:23]
wire _tl_out_a_bits_T_7_user_amba_prot_bufferable = 1'h0; // @[DCache.scala:608:23]
wire _tl_out_a_bits_T_7_user_amba_prot_modifiable = 1'h0; // @[DCache.scala:608:23]
wire _tl_out_a_bits_T_7_user_amba_prot_readalloc = 1'h0; // @[DCache.scala:608:23]
wire _tl_out_a_bits_T_7_user_amba_prot_writealloc = 1'h0; // @[DCache.scala:608:23]
wire _tl_out_a_bits_T_7_user_amba_prot_privileged = 1'h0; // @[DCache.scala:608:23]
wire _tl_out_a_bits_T_7_user_amba_prot_secure = 1'h0; // @[DCache.scala:608:23]
wire _tl_out_a_bits_T_7_user_amba_prot_fetch = 1'h0; // @[DCache.scala:608:23]
wire _tl_out_a_bits_T_7_corrupt = 1'h0; // @[DCache.scala:608:23]
wire _tl_d_data_encoded_T_12 = 1'h0; // @[DCache.scala:663:129]
wire _tl_d_data_encoded_T_13 = 1'h0; // @[DCache.scala:663:126]
wire _grantIsCached_T = 1'h0; // @[package.scala:16:47]
wire _grantIsCached_T_1 = 1'h0; // @[package.scala:16:47]
wire grantIsVoluntary = 1'h0; // @[DCache.scala:665:32]
wire grantIsRefill = 1'h0; // @[DCache.scala:666:29]
wire _canAcceptCachedGrant_T = 1'h0; // @[package.scala:16:47]
wire _canAcceptCachedGrant_T_1 = 1'h0; // @[package.scala:16:47]
wire _canAcceptCachedGrant_T_2 = 1'h0; // @[package.scala:16:47]
wire _canAcceptCachedGrant_T_3 = 1'h0; // @[package.scala:81:59]
wire _canAcceptCachedGrant_T_4 = 1'h0; // @[package.scala:81:59]
wire _nodeOut_d_ready_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _nodeOut_d_ready_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _nodeOut_d_ready_WIRE_bits_sink = 1'h0; // @[Bundles.scala:267:74]
wire _nodeOut_d_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _nodeOut_d_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _nodeOut_d_ready_WIRE_1_bits_sink = 1'h0; // @[Bundles.scala:267:61]
wire _block_probe_for_pending_release_ack_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _block_probe_for_pending_release_ack_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _block_probe_for_pending_release_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74]
wire _block_probe_for_pending_release_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _block_probe_for_pending_release_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _block_probe_for_pending_release_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _block_probe_for_pending_release_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61]
wire _block_probe_for_pending_release_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire block_probe_for_pending_release_ack = 1'h0; // @[DCache.scala:767:62]
wire _block_probe_for_ordering_T = 1'h0; // @[DCache.scala:768:50]
wire _metaArb_io_in_6_valid_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _metaArb_io_in_6_valid_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _metaArb_io_in_6_valid_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74]
wire _metaArb_io_in_6_valid_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _metaArb_io_in_6_valid_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _metaArb_io_in_6_valid_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _metaArb_io_in_6_valid_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61]
wire _metaArb_io_in_6_valid_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _metaArb_io_in_6_valid_T_2 = 1'h0; // @[DCache.scala:769:44]
wire _metaArb_io_in_6_bits_idx_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _metaArb_io_in_6_bits_idx_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _metaArb_io_in_6_bits_idx_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74]
wire _metaArb_io_in_6_bits_idx_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _metaArb_io_in_6_bits_idx_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _metaArb_io_in_6_bits_idx_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _metaArb_io_in_6_bits_idx_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61]
wire _metaArb_io_in_6_bits_idx_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _metaArb_io_in_6_bits_addr_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _metaArb_io_in_6_bits_addr_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _metaArb_io_in_6_bits_addr_WIRE_bits_source = 1'h0; // @[Bundles.scala:264:74]
wire _metaArb_io_in_6_bits_addr_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _metaArb_io_in_6_bits_addr_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _metaArb_io_in_6_bits_addr_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _metaArb_io_in_6_bits_addr_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:264:61]
wire _metaArb_io_in_6_bits_addr_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire r_beats1_opdata_1 = 1'h0; // @[Edges.scala:102:36]
wire _r_last_T_2 = 1'h0; // @[Edges.scala:232:25]
wire releaseDone = 1'h0; // @[Edges.scala:233:22]
wire _s1_release_data_valid_T = 1'h0; // @[Decoupled.scala:51:35]
wire _s2_release_data_valid_T_1 = 1'h0; // @[DCache.scala:802:61]
wire _releaseRejected_T = 1'h0; // @[Decoupled.scala:51:35]
wire nackResponseMessage_source = 1'h0; // @[Edges.scala:416:17]
wire nackResponseMessage_user_amba_prot_bufferable = 1'h0; // @[Edges.scala:416:17]
wire nackResponseMessage_user_amba_prot_modifiable = 1'h0; // @[Edges.scala:416:17]
wire nackResponseMessage_user_amba_prot_readalloc = 1'h0; // @[Edges.scala:416:17]
wire nackResponseMessage_user_amba_prot_writealloc = 1'h0; // @[Edges.scala:416:17]
wire nackResponseMessage_user_amba_prot_privileged = 1'h0; // @[Edges.scala:416:17]
wire nackResponseMessage_user_amba_prot_secure = 1'h0; // @[Edges.scala:416:17]
wire nackResponseMessage_user_amba_prot_fetch = 1'h0; // @[Edges.scala:416:17]
wire nackResponseMessage_corrupt = 1'h0; // @[Edges.scala:416:17]
wire cleanReleaseMessage_source = 1'h0; // @[Edges.scala:416:17]
wire cleanReleaseMessage_user_amba_prot_bufferable = 1'h0; // @[Edges.scala:416:17]
wire cleanReleaseMessage_user_amba_prot_modifiable = 1'h0; // @[Edges.scala:416:17]
wire cleanReleaseMessage_user_amba_prot_readalloc = 1'h0; // @[Edges.scala:416:17]
wire cleanReleaseMessage_user_amba_prot_writealloc = 1'h0; // @[Edges.scala:416:17]
wire cleanReleaseMessage_user_amba_prot_privileged = 1'h0; // @[Edges.scala:416:17]
wire cleanReleaseMessage_user_amba_prot_secure = 1'h0; // @[Edges.scala:416:17]
wire cleanReleaseMessage_user_amba_prot_fetch = 1'h0; // @[Edges.scala:416:17]
wire cleanReleaseMessage_corrupt = 1'h0; // @[Edges.scala:416:17]
wire dirtyReleaseMessage_source = 1'h0; // @[Edges.scala:433:17]
wire dirtyReleaseMessage_user_amba_prot_bufferable = 1'h0; // @[Edges.scala:433:17]
wire dirtyReleaseMessage_user_amba_prot_modifiable = 1'h0; // @[Edges.scala:433:17]
wire dirtyReleaseMessage_user_amba_prot_readalloc = 1'h0; // @[Edges.scala:433:17]
wire dirtyReleaseMessage_user_amba_prot_writealloc = 1'h0; // @[Edges.scala:433:17]
wire dirtyReleaseMessage_user_amba_prot_privileged = 1'h0; // @[Edges.scala:433:17]
wire dirtyReleaseMessage_user_amba_prot_secure = 1'h0; // @[Edges.scala:433:17]
wire dirtyReleaseMessage_user_amba_prot_fetch = 1'h0; // @[Edges.scala:433:17]
wire dirtyReleaseMessage_corrupt = 1'h0; // @[Edges.scala:433:17]
wire _tl_out_c_valid_T = 1'h0; // @[DCache.scala:810:48]
wire _tl_out_c_valid_T_1 = 1'h0; // @[DCache.scala:810:91]
wire _tl_out_c_valid_T_2 = 1'h0; // @[DCache.scala:810:74]
wire _tl_out_c_valid_T_4 = 1'h0; // @[DCache.scala:810:130]
wire _dataArb_io_in_2_valid_T_1 = 1'h0; // @[DCache.scala:900:41]
wire _metaArb_io_in_4_valid_T = 1'h0; // @[package.scala:16:47]
wire _metaArb_io_in_4_valid_T_1 = 1'h0; // @[package.scala:16:47]
wire _metaArb_io_in_4_valid_T_2 = 1'h0; // @[package.scala:81:59]
wire _io_cpu_s2_xcpt_WIRE_miss = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_gpa_is_pte = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_pf_ld = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_pf_st = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_pf_inst = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_gf_ld = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_gf_st = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_gf_inst = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_ae_ld = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_ae_st = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_ae_inst = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_ma_ld = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_ma_st = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_ma_inst = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_cacheable = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_must_alloc = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_WIRE_prefetchable = 1'h0; // @[DCache.scala:933:74]
wire _io_cpu_s2_xcpt_T_miss = 1'h0; // @[DCache.scala:933:24]
wire _io_cpu_s2_xcpt_T_gpa_is_pte = 1'h0; // @[DCache.scala:933:24]
wire _io_cpu_s2_xcpt_T_gf_ld = 1'h0; // @[DCache.scala:933:24]
wire _io_cpu_s2_xcpt_T_gf_st = 1'h0; // @[DCache.scala:933:24]
wire _io_cpu_s2_xcpt_T_gf_inst = 1'h0; // @[DCache.scala:933:24]
wire _io_cpu_s2_xcpt_T_ma_inst = 1'h0; // @[DCache.scala:933:24]
wire _s2_data_word_possibly_uncached_T = 1'h0; // @[DCache.scala:972:73]
wire io_cpu_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31]
wire io_cpu_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31]
wire io_cpu_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31]
wire io_cpu_resp_bits_data_word_bypass_doZero = 1'h0; // @[AMOALU.scala:43:31]
wire _flushDone_T = 1'h0; // @[DCache.scala:1010:37]
wire flushDone = 1'h0; // @[DCache.scala:1010:57]
wire _s1_flush_valid_T = 1'h0; // @[Decoupled.scala:51:35]
wire _s1_flush_valid_T_2 = 1'h0; // @[DCache.scala:1014:43]
wire _s1_flush_valid_T_4 = 1'h0; // @[DCache.scala:1014:62]
wire _s1_flush_valid_T_6 = 1'h0; // @[DCache.scala:1014:93]
wire _s1_flush_valid_T_8 = 1'h0; // @[DCache.scala:1014:122]
wire _metaArb_io_in_5_valid_T = 1'h0; // @[DCache.scala:1015:41]
wire _metaArb_io_in_5_valid_T_1 = 1'h0; // @[DCache.scala:1015:38]
wire _clock_en_reg_T_14 = 1'h0; // @[DCache.scala:1069:19]
wire _clock_en_reg_T_17 = 1'h0; // @[DCache.scala:1070:25]
wire _clock_en_reg_T_19 = 1'h0; // @[DCache.scala:1071:5]
wire _io_cpu_perf_release_T = 1'h0; // @[Decoupled.scala:51:35]
wire io_cpu_perf_release_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _io_cpu_perf_release_last_T = 1'h0; // @[Edges.scala:232:25]
wire io_cpu_perf_release_done = 1'h0; // @[Edges.scala:233:22]
wire _io_cpu_perf_tlbMiss_T = 1'h0; // @[Decoupled.scala:51:35]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_50 = 1'h0; // @[DCache.scala:1191:57]
wire auto_out_a_bits_user_amba_prot_secure = 1'h1; // @[DCache.scala:101:7]
wire io_cpu_clock_enabled = 1'h1; // @[DCache.scala:101:7]
wire io_ptw_req_bits_valid = 1'h1; // @[DCache.scala:101:7]
wire io_tlb_port_req_ready = 1'h1; // @[DCache.scala:101:7]
wire nodeOut_a_bits_user_amba_prot_secure = 1'h1; // @[MixedNode.scala:542:17]
wire pma_checker_io_req_ready = 1'h1; // @[DCache.scala:120:32]
wire pma_checker_io_req_bits_passthrough = 1'h1; // @[DCache.scala:120:32]
wire pma_checker_io_ptw_req_bits_valid = 1'h1; // @[DCache.scala:120:32]
wire pma_checker__mpu_priv_T = 1'h1; // @[TLB.scala:415:52]
wire pma_checker__homogeneous_T_53 = 1'h1; // @[TLBPermissions.scala:87:22]
wire pma_checker__sector_hits_T_6 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__sector_hits_T_14 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__sector_hits_T_22 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__sector_hits_T_30 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__sector_hits_T_38 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__sector_hits_T_46 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__sector_hits_T_54 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__sector_hits_T_62 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__superpage_hits_T_3 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__superpage_hits_T_8 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__superpage_hits_T_13 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__superpage_hits_T_18 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__hitsVec_T_3 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__hitsVec_T_9 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__hitsVec_T_15 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__hitsVec_T_21 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__hitsVec_T_27 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__hitsVec_T_33 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__hitsVec_T_39 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__hitsVec_T_45 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__hitsVec_T_51 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__hitsVec_T_57 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__hitsVec_T_63 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__hitsVec_T_69 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__hitsVec_T_75 = 1'h1; // @[TLB.scala:174:105]
wire pma_checker__hits_T = 1'h1; // @[TLB.scala:442:18]
wire pma_checker__newEntry_sr_T = 1'h1; // @[PTW.scala:141:47]
wire pma_checker__newEntry_sw_T = 1'h1; // @[PTW.scala:141:47]
wire pma_checker__newEntry_sx_T = 1'h1; // @[PTW.scala:141:47]
wire pma_checker__ppn_T = 1'h1; // @[TLB.scala:502:30]
wire pma_checker__stage1_bypass_T_1 = 1'h1; // @[TLB.scala:517:83]
wire pma_checker__stage2_bypass_T = 1'h1; // @[TLB.scala:523:42]
wire pma_checker__gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107]
wire pma_checker__tlb_miss_T = 1'h1; // @[TLB.scala:613:32]
wire pma_checker__tlb_miss_T_2 = 1'h1; // @[TLB.scala:613:56]
wire pma_checker__tlb_miss_T_4 = 1'h1; // @[TLB.scala:613:67]
wire pma_checker__io_req_ready_T = 1'h1; // @[TLB.scala:631:25]
wire pma_checker__io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20]
wire pma_checker__io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28]
wire metaArb_io_in_0_ready = 1'h1; // @[DCache.scala:135:28]
wire metaArb_io_in_0_bits_write = 1'h1; // @[DCache.scala:135:28]
wire metaArb_io_in_0_bits_way_en = 1'h1; // @[DCache.scala:135:28]
wire metaArb_io_in_1_ready = 1'h1; // @[DCache.scala:135:28]
wire metaArb_io_in_1_bits_write = 1'h1; // @[DCache.scala:135:28]
wire metaArb_io_in_2_ready = 1'h1; // @[DCache.scala:135:28]
wire metaArb_io_in_2_bits_write = 1'h1; // @[DCache.scala:135:28]
wire metaArb_io_in_3_bits_write = 1'h1; // @[DCache.scala:135:28]
wire metaArb_io_in_4_bits_write = 1'h1; // @[DCache.scala:135:28]
wire metaArb_io_out_ready = 1'h1; // @[DCache.scala:135:28]
wire metaArb_grant_1 = 1'h1; // @[Arbiter.scala:45:78]
wire metaArb_grant_2 = 1'h1; // @[Arbiter.scala:45:78]
wire metaArb__io_in_0_ready_T = 1'h1; // @[Arbiter.scala:153:19]
wire metaArb__io_in_1_ready_T = 1'h1; // @[Arbiter.scala:153:19]
wire metaArb__io_in_2_ready_T = 1'h1; // @[Arbiter.scala:153:19]
wire dataArb_io_in_0_ready = 1'h1; // @[DCache.scala:152:28]
wire dataArb_io_in_2_bits_wordMask = 1'h1; // @[DCache.scala:152:28]
wire dataArb_io_in_2_bits_way_en = 1'h1; // @[DCache.scala:152:28]
wire dataArb_io_in_3_bits_wordMask = 1'h1; // @[DCache.scala:152:28]
wire dataArb_io_in_3_bits_way_en = 1'h1; // @[DCache.scala:152:28]
wire dataArb_io_out_ready = 1'h1; // @[DCache.scala:152:28]
wire dataArb__io_in_0_ready_T = 1'h1; // @[Arbiter.scala:153:19]
wire tl_out_a_bits_user_amba_prot_secure = 1'h1; // @[DCache.scala:159:22]
wire nodeOut_a_deq_bits_user_amba_prot_secure = 1'h1; // @[Decoupled.scala:356:21]
wire tl_out_c_bits_user_amba_prot_bufferable = 1'h1; // @[Bundles.scala:265:61]
wire tl_out_c_bits_user_amba_prot_modifiable = 1'h1; // @[Bundles.scala:265:61]
wire tl_out_c_bits_user_amba_prot_readalloc = 1'h1; // @[Bundles.scala:265:61]
wire tl_out_c_bits_user_amba_prot_writealloc = 1'h1; // @[Bundles.scala:265:61]
wire tl_out_c_bits_user_amba_prot_privileged = 1'h1; // @[Bundles.scala:265:61]
wire tl_out_c_bits_user_amba_prot_secure = 1'h1; // @[Bundles.scala:265:61]
wire _io_cpu_req_ready_T = 1'h1; // @[DCache.scala:233:38]
wire _dataArb_io_in_3_bits_way_en_T = 1'h1; // @[DCache.scala:257:35]
wire _s2_valid_not_killed_T = 1'h1; // @[DCache.scala:338:48]
wire _s2_flush_valid_T = 1'h1; // @[DCache.scala:363:54]
wire _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T = 1'h1; // @[DCache.scala:397:74]
wire _s2_valid_hit_pre_data_ecc_and_waw_T_1 = 1'h1; // @[DCache.scala:418:108]
wire _s2_valid_hit_pre_data_ecc_T = 1'h1; // @[DCache.scala:420:73]
wire _s2_valid_hit_pre_data_ecc_T_1 = 1'h1; // @[DCache.scala:420:88]
wire _s2_valid_hit_T = 1'h1; // @[DCache.scala:422:51]
wire _s2_valid_miss_T_1 = 1'h1; // @[DCache.scala:423:58]
wire _s2_victimize_T = 1'h1; // @[DCache.scala:429:43]
wire _s2_victim_tag_T_2 = 1'h1; // @[Mux.scala:32:36]
wire _s2_victim_state_T = 1'h1; // @[Mux.scala:32:36]
wire _r_T_117 = 1'h1; // @[Metadata.scala:140:24]
wire _s2_dont_nack_misc_T = 1'h1; // @[DCache.scala:441:46]
wire _s2_dont_nack_misc_T_4 = 1'h1; // @[DCache.scala:442:57]
wire _metaArb_io_in_2_bits_write_T = 1'h1; // @[DCache.scala:463:34]
wire _s2_valid_correct_T_1 = 1'h1; // @[DCache.scala:489:77]
wire _pstore1_merge_T_1 = 1'h1; // @[DCache.scala:490:61]
wire _pstore1_merge_T_3 = 1'h1; // @[DCache.scala:491:51]
wire _pstore_drain_opportunistic_T_61 = 1'h1; // @[DCache.scala:502:95]
wire _pstore1_valid_T_1 = 1'h1; // @[DCache.scala:490:61]
wire _pstore1_valid_T_3 = 1'h1; // @[DCache.scala:491:51]
wire _pstore_drain_T = 1'h1; // @[DCache.scala:516:5]
wire _pstore_drain_T_3 = 1'h1; // @[DCache.scala:506:87]
wire _pstore1_held_T_1 = 1'h1; // @[DCache.scala:490:61]
wire _pstore1_held_T_3 = 1'h1; // @[DCache.scala:491:51]
wire _pstore1_held_T_5 = 1'h1; // @[DCache.scala:521:38]
wire _dataArb_io_in_0_valid_T = 1'h1; // @[DCache.scala:516:5]
wire _dataArb_io_in_0_valid_T_3 = 1'h1; // @[DCache.scala:506:87]
wire _dataArb_io_in_0_bits_wordMask_T = 1'h1; // @[DCache.scala:555:20]
wire _io_cpu_s2_nack_cause_raw_T = 1'h1; // @[DCache.scala:574:59]
wire _io_cpu_s2_nack_cause_raw_T_1 = 1'h1; // @[DCache.scala:574:74]
wire _get_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _get_legal_T_1 = 1'h1; // @[Parameters.scala:92:38]
wire _get_legal_T_2 = 1'h1; // @[Parameters.scala:92:33]
wire _get_legal_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _get_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _get_legal_T_11 = 1'h1; // @[Parameters.scala:92:38]
wire _get_legal_T_12 = 1'h1; // @[Parameters.scala:92:33]
wire _get_legal_T_13 = 1'h1; // @[Parameters.scala:684:29]
wire _put_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _put_legal_T_1 = 1'h1; // @[Parameters.scala:92:38]
wire _put_legal_T_2 = 1'h1; // @[Parameters.scala:92:33]
wire _put_legal_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _put_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _put_legal_T_11 = 1'h1; // @[Parameters.scala:92:38]
wire _put_legal_T_12 = 1'h1; // @[Parameters.scala:92:33]
wire _put_legal_T_13 = 1'h1; // @[Parameters.scala:684:29]
wire _put_legal_T_51 = 1'h1; // @[Parameters.scala:92:28]
wire _put_legal_T_52 = 1'h1; // @[Parameters.scala:92:38]
wire _put_legal_T_53 = 1'h1; // @[Parameters.scala:92:33]
wire _put_legal_T_54 = 1'h1; // @[Parameters.scala:684:29]
wire _putpartial_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _putpartial_legal_T_1 = 1'h1; // @[Parameters.scala:92:38]
wire _putpartial_legal_T_2 = 1'h1; // @[Parameters.scala:92:33]
wire _putpartial_legal_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _putpartial_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire _putpartial_legal_T_11 = 1'h1; // @[Parameters.scala:92:38]
wire _putpartial_legal_T_12 = 1'h1; // @[Parameters.scala:92:33]
wire _putpartial_legal_T_13 = 1'h1; // @[Parameters.scala:684:29]
wire _putpartial_legal_T_51 = 1'h1; // @[Parameters.scala:92:28]
wire _putpartial_legal_T_52 = 1'h1; // @[Parameters.scala:92:38]
wire _putpartial_legal_T_53 = 1'h1; // @[Parameters.scala:92:33]
wire _putpartial_legal_T_54 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_1 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_2 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_36 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_37 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_38 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_39 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_72 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_73 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_74 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_75 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_108 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_109 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_110 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_111 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_144 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_145 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_146 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_147 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_180 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_181 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_182 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_183 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_216 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_217 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_218 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_219 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_252 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_253 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_254 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_255 = 1'h1; // @[Parameters.scala:684:29]
wire _atomics_legal_T_288 = 1'h1; // @[Parameters.scala:92:28]
wire _atomics_legal_T_289 = 1'h1; // @[Parameters.scala:92:38]
wire _atomics_legal_T_290 = 1'h1; // @[Parameters.scala:92:33]
wire _atomics_legal_T_291 = 1'h1; // @[Parameters.scala:684:29]
wire _tl_out_a_valid_T = 1'h1; // @[DCache.scala:603:21]
wire _tl_out_a_valid_T_5 = 1'h1; // @[DCache.scala:606:8]
wire _tl_out_a_valid_T_7 = 1'h1; // @[DCache.scala:607:47]
wire a_sel = 1'h1; // @[DCache.scala:630:66]
wire canAcceptCachedGrant = 1'h1; // @[DCache.scala:670:30]
wire uncachedRespIdxOH = 1'h1; // @[DCache.scala:672:90]
wire _uncachedResp_T = 1'h1; // @[Mux.scala:32:36]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _r_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire c_last = 1'h1; // @[Edges.scala:232:33]
wire _releaseRejected_T_1 = 1'h1; // @[DCache.scala:803:47]
wire _tl_out_c_valid_T_5 = 1'h1; // @[DCache.scala:810:120]
wire _dataArb_io_in_2_bits_wordMask_T = 1'h1; // @[DCache.scala:904:37]
wire _dataArb_io_in_2_bits_way_en_T = 1'h1; // @[DCache.scala:906:35]
wire _io_cpu_resp_valid_T_1 = 1'h1; // @[DCache.scala:949:73]
wire _io_cpu_replay_next_T_2 = 1'h1; // @[DCache.scala:950:65]
wire _s1_flush_valid_T_5 = 1'h1; // @[DCache.scala:1014:110]
wire _s1_flush_valid_T_7 = 1'h1; // @[DCache.scala:1014:125]
wire _metaArb_io_in_0_bits_way_en_T = 1'h1; // @[DCache.scala:1049:35]
wire _clock_en_reg_T = 1'h1; // @[DCache.scala:1060:19]
wire _clock_en_reg_T_2 = 1'h1; // @[DCache.scala:1060:44]
wire _clock_en_reg_T_3 = 1'h1; // @[DCache.scala:1061:46]
wire _clock_en_reg_T_4 = 1'h1; // @[DCache.scala:1062:31]
wire _clock_en_reg_T_5 = 1'h1; // @[DCache.scala:1063:26]
wire _clock_en_reg_T_6 = 1'h1; // @[DCache.scala:1064:14]
wire _clock_en_reg_T_7 = 1'h1; // @[DCache.scala:1064:26]
wire _clock_en_reg_T_8 = 1'h1; // @[DCache.scala:1065:14]
wire _clock_en_reg_T_9 = 1'h1; // @[DCache.scala:1065:26]
wire _clock_en_reg_T_10 = 1'h1; // @[DCache.scala:1066:27]
wire _clock_en_reg_T_11 = 1'h1; // @[DCache.scala:1067:22]
wire _clock_en_reg_T_12 = 1'h1; // @[DCache.scala:1067:42]
wire _clock_en_reg_T_13 = 1'h1; // @[DCache.scala:1068:18]
wire _clock_en_reg_T_15 = 1'h1; // @[DCache.scala:1068:35]
wire _clock_en_reg_T_16 = 1'h1; // @[DCache.scala:1069:31]
wire _clock_en_reg_T_18 = 1'h1; // @[DCache.scala:1070:22]
wire _clock_en_reg_T_20 = 1'h1; // @[DCache.scala:1070:46]
wire _clock_en_reg_T_21 = 1'h1; // @[DCache.scala:1071:23]
wire _clock_en_reg_T_23 = 1'h1; // @[DCache.scala:1072:23]
wire _clock_en_reg_T_25 = 1'h1; // @[DCache.scala:1072:54]
wire _clock_en_reg_T_27 = 1'h1; // @[DCache.scala:1073:21]
wire io_cpu_perf_release_first = 1'h1; // @[Edges.scala:231:25]
wire _io_cpu_perf_release_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire io_cpu_perf_release_last = 1'h1; // @[Edges.scala:232:33]
wire _io_cpu_perf_storeBufferEmptyAfterLoad_T_2 = 1'h1; // @[DCache.scala:1082:31]
wire _io_cpu_perf_storeBufferEmptyAfterStore_T_5 = 1'h1; // @[DCache.scala:1087:31]
wire _io_cpu_perf_canAcceptStoreThenLoad_T_3 = 1'h1; // @[DCache.scala:1089:72]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_56 = 1'h1; // @[DCache.scala:1092:115]
wire [3:0] io_ptw_ptbr_mode = 4'h0; // @[DCache.scala:101:7]
wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[DCache.scala:101:7]
wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[DCache.scala:101:7]
wire [3:0] pma_checker_io_ptw_ptbr_mode = 4'h0; // @[DCache.scala:120:32]
wire [3:0] pma_checker_io_ptw_hgatp_mode = 4'h0; // @[DCache.scala:120:32]
wire [3:0] pma_checker_io_ptw_vsatp_mode = 4'h0; // @[DCache.scala:120:32]
wire [3:0] pma_checker_satp_mode = 4'h0; // @[TLB.scala:373:17]
wire [3:0] pma_checker_real_hits_hi_hi = 4'h0; // @[package.scala:45:27]
wire [3:0] pma_checker__multipleHits_T_31 = 4'h0; // @[Misc.scala:182:39]
wire [3:0] tl_out_c_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _s1_probe_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _s1_probe_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _probe_bits_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _probe_bits_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _probe_bits_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _probe_bits_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _r_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _r_T_63 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _r_T_127 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _a_mask_T = 4'h0; // @[DCache.scala:582:90]
wire [3:0] _atomics_WIRE_size = 4'h0; // @[DCache.scala:587:51]
wire [3:0] _atomics_WIRE_1_size = 4'h0; // @[DCache.scala:587:38]
wire [3:0] _tl_out_a_bits_WIRE_size = 4'h0; // @[DCache.scala:1209:67]
wire [3:0] _tl_out_a_bits_WIRE_1_size = 4'h0; // @[DCache.scala:1209:54]
wire [3:0] _metaArb_io_in_3_bits_data_T_5 = 4'h0; // @[Metadata.scala:87:10]
wire [3:0] _block_probe_for_pending_release_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _block_probe_for_pending_release_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _metaArb_io_in_6_valid_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _metaArb_io_in_6_valid_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _metaArb_io_in_6_bits_idx_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _metaArb_io_in_6_bits_idx_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _metaArb_io_in_6_bits_addr_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _metaArb_io_in_6_bits_addr_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] nackResponseMessage_size = 4'h0; // @[Edges.scala:416:17]
wire [3:0] cleanReleaseMessage_size = 4'h0; // @[Edges.scala:416:17]
wire [3:0] dirtyReleaseMessage_size = 4'h0; // @[Edges.scala:433:17]
wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[DCache.scala:101:7]
wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[DCache.scala:101:7]
wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[DCache.scala:101:7]
wire [15:0] pma_checker_io_ptw_ptbr_asid = 16'h0; // @[DCache.scala:120:32]
wire [15:0] pma_checker_io_ptw_hgatp_asid = 16'h0; // @[DCache.scala:120:32]
wire [15:0] pma_checker_io_ptw_vsatp_asid = 16'h0; // @[DCache.scala:120:32]
wire [15:0] pma_checker_satp_asid = 16'h0; // @[TLB.scala:373:17]
wire [43:0] io_ptw_ptbr_ppn = 44'h0; // @[DCache.scala:101:7]
wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[DCache.scala:101:7]
wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[DCache.scala:101:7]
wire [43:0] pma_checker_io_ptw_resp_bits_pte_ppn = 44'h0; // @[DCache.scala:120:32]
wire [43:0] pma_checker_io_ptw_ptbr_ppn = 44'h0; // @[DCache.scala:120:32]
wire [43:0] pma_checker_io_ptw_hgatp_ppn = 44'h0; // @[DCache.scala:120:32]
wire [43:0] pma_checker_io_ptw_vsatp_ppn = 44'h0; // @[DCache.scala:120:32]
wire [43:0] pma_checker_satp_ppn = 44'h0; // @[TLB.scala:373:17]
wire [1:0] io_ptw_status_dprv = 2'h3; // @[DCache.scala:101:7]
wire [1:0] io_ptw_status_prv = 2'h3; // @[DCache.scala:101:7]
wire [1:0] hitState_meta_state = 2'h3; // @[Metadata.scala:160:20]
wire [1:0] _r_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _metaArb_io_in_3_bits_data_T_8 = 2'h3; // @[Metadata.scala:24:15]
wire [22:0] io_ptw_status_zero2 = 23'h0; // @[DCache.scala:101:7]
wire [22:0] pma_checker_io_ptw_status_zero2 = 23'h0; // @[DCache.scala:120:32]
wire [22:0] pma_checker_io_ptw_gstatus_zero2 = 23'h0; // @[DCache.scala:120:32]
wire [7:0] io_cpu_req_bits_mask = 8'h0; // @[DCache.scala:101:7]
wire [7:0] io_ptw_status_zero1 = 8'h0; // @[DCache.scala:101:7]
wire [7:0] pma_checker_io_ptw_status_zero1 = 8'h0; // @[DCache.scala:120:32]
wire [7:0] pma_checker_io_ptw_gstatus_zero1 = 8'h0; // @[DCache.scala:120:32]
wire [7:0] metaArb_io_in_0_bits_idx = 8'h0; // @[DCache.scala:135:28]
wire [7:0] metaArb_io_in_4_bits_idx = 8'h0; // @[DCache.scala:135:28]
wire [7:0] metaArb_io_in_5_bits_idx = 8'h0; // @[DCache.scala:135:28]
wire [7:0] metaArb_io_in_6_bits_idx = 8'h0; // @[DCache.scala:135:28]
wire [7:0] _s1_probe_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _s1_probe_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _probe_bits_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _probe_bits_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _probe_bits_WIRE_2_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _probe_bits_WIRE_3_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] s0_req_mask = 8'h0; // @[DCache.scala:192:24]
wire [7:0] _metaArb_io_in_1_bits_idx_T = 8'h0; // @[DCache.scala:1200:47]
wire [7:0] _pstore2_storegen_mask_mergedMask_T = 8'h0; // @[DCache.scala:533:42]
wire [7:0] _atomics_WIRE_mask = 8'h0; // @[DCache.scala:587:51]
wire [7:0] _atomics_WIRE_1_mask = 8'h0; // @[DCache.scala:587:38]
wire [7:0] _tl_out_a_bits_WIRE_mask = 8'h0; // @[DCache.scala:1209:67]
wire [7:0] _tl_out_a_bits_WIRE_1_mask = 8'h0; // @[DCache.scala:1209:54]
wire [7:0] _block_probe_for_pending_release_ack_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _block_probe_for_pending_release_ack_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _metaArb_io_in_6_valid_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _metaArb_io_in_6_valid_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _metaArb_io_in_6_bits_idx_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _metaArb_io_in_6_bits_idx_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _metaArb_io_in_6_bits_idx_T = 8'h0; // @[DCache.scala:1200:47]
wire [7:0] _metaArb_io_in_6_bits_addr_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74]
wire [7:0] _metaArb_io_in_6_bits_addr_WIRE_1_bits_mask = 8'h0; // @[Bundles.scala:264:61]
wire [7:0] _dataArb_io_in_2_bits_addr_T = 8'h0; // @[DCache.scala:1200:47]
wire [7:0] _metaArb_io_in_4_bits_idx_T = 8'h0; // @[DCache.scala:1200:47]
wire [7:0] _metaArb_io_in_5_bits_idx_T = 8'h0; // @[DCache.scala:1017:44]
wire [1:0] io_ptw_status_sxl = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_status_uxl = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_status_xs = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_status_vs = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_tlb_port_req_bits_size = 2'h0; // @[DCache.scala:101:7]
wire [1:0] io_tlb_port_req_bits_prv = 2'h0; // @[DCache.scala:101:7]
wire [1:0] pma_checker_io_ptw_resp_bits_pte_reserved_for_software = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_resp_bits_level = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_status_dprv = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_status_prv = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_status_sxl = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_status_uxl = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_status_xs = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_status_fs = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_status_mpp = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_status_vs = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_hstatus_vsxl = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_hstatus_zero3 = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_hstatus_zero2 = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_gstatus_dprv = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_gstatus_prv = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_gstatus_sxl = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_gstatus_uxl = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_gstatus_xs = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_gstatus_fs = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_gstatus_mpp = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_gstatus_vs = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_pmp_0_cfg_res = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_pmp_0_cfg_a = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_pmp_1_cfg_res = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_pmp_1_cfg_a = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_pmp_2_cfg_res = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_pmp_2_cfg_a = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_pmp_3_cfg_res = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_pmp_3_cfg_a = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_pmp_4_cfg_res = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_pmp_4_cfg_a = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_pmp_5_cfg_res = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_pmp_5_cfg_a = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_pmp_6_cfg_res = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_pmp_6_cfg_a = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_pmp_7_cfg_res = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_ptw_pmp_7_cfg_a = 2'h0; // @[DCache.scala:120:32]
wire [1:0] pma_checker_real_hits_lo_lo_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] pma_checker_real_hits_lo_hi_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] pma_checker_real_hits_hi_lo_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] pma_checker_real_hits_hi_hi_lo = 2'h0; // @[package.scala:45:27]
wire [1:0] pma_checker_real_hits_hi_hi_hi = 2'h0; // @[package.scala:45:27]
wire [1:0] pma_checker__special_entry_level_T = 2'h0; // @[package.scala:163:13]
wire [1:0] pma_checker_special_entry_data_0_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_special_entry_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_special_entry_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_special_entry_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_special_entry_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_waddr = 2'h0; // @[TLB.scala:477:22]
wire [1:0] pma_checker_superpage_entries_0_data_0_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_0_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_0_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_0_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_0_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_1_data_0_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_1_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_1_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_1_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_1_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_2_data_0_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_2_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_2_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_2_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_2_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_3_data_0_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_3_data_0_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_3_data_0_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_3_data_0_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_3_data_0_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_idx = 2'h0; // @[package.scala:163:13]
wire [1:0] pma_checker_sectored_entries_0_0_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_0_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_0_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_0_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_0_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_idx_1 = 2'h0; // @[package.scala:163:13]
wire [1:0] pma_checker_sectored_entries_0_1_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_1_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_1_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_1_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_1_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_idx_2 = 2'h0; // @[package.scala:163:13]
wire [1:0] pma_checker_sectored_entries_0_2_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_2_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_2_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_2_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_2_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_idx_3 = 2'h0; // @[package.scala:163:13]
wire [1:0] pma_checker_sectored_entries_0_3_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_3_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_3_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_3_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_3_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_idx_4 = 2'h0; // @[package.scala:163:13]
wire [1:0] pma_checker_sectored_entries_0_4_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_4_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_4_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_4_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_4_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_idx_5 = 2'h0; // @[package.scala:163:13]
wire [1:0] pma_checker_sectored_entries_0_5_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_5_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_5_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_5_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_5_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_idx_6 = 2'h0; // @[package.scala:163:13]
wire [1:0] pma_checker_sectored_entries_0_6_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_6_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_6_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_6_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_6_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_idx_7 = 2'h0; // @[package.scala:163:13]
wire [1:0] pma_checker_sectored_entries_0_7_data_lo_lo_lo = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_7_data_lo_hi_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_7_data_hi_lo_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_7_data_hi_lo_hi_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_7_data_hi_hi_lo_hi = 2'h0; // @[TLB.scala:217:24]
wire [1:0] pma_checker__c_array_T = 2'h0; // @[TLB.scala:537:25]
wire [1:0] pma_checker__prefetchable_array_T_1 = 2'h0; // @[TLB.scala:547:59]
wire [1:0] pma_checker__multipleHits_T_3 = 2'h0; // @[Misc.scala:182:39]
wire [1:0] pma_checker__multipleHits_T_12 = 2'h0; // @[Misc.scala:182:39]
wire [1:0] pma_checker__multipleHits_T_24 = 2'h0; // @[Misc.scala:182:39]
wire [1:0] pma_checker__multipleHits_T_32 = 2'h0; // @[Misc.scala:181:37]
wire [1:0] pma_checker__multipleHits_T_37 = 2'h0; // @[Misc.scala:182:39]
wire [1:0] _s1_probe_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _s1_probe_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _probe_bits_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _probe_bits_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _probe_bits_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _probe_bits_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] hitState_meta_1_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] dummyMeta_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] dummyMeta_coh_state = 2'h0; // @[HellaCache.scala:305:20]
wire [1:0] _s2_valid_no_xcpt_T_1 = 2'h0; // @[DCache.scala:332:54]
wire [1:0] s2_meta_corrected_0_coh_state = 2'h0; // @[DCache.scala:361:99]
wire [1:0] _s2_meta_corrected_T_1 = 2'h0; // @[DCache.scala:361:99]
wire [1:0] _r_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_75 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_79 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_83 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_87 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_91 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_139 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_143 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_147 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_151 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_155 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] metaArb_io_in_1_bits_data_new_meta_coh_state = 2'h0; // @[DCache.scala:456:31]
wire [1:0] metaArb_io_in_1_bits_data_new_meta_coh_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _metaArb_io_in_3_bits_data_T_2 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _metaArb_io_in_3_bits_data_T_4 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _block_probe_for_pending_release_ack_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _block_probe_for_pending_release_ack_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _metaArb_io_in_6_valid_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _metaArb_io_in_6_valid_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _metaArb_io_in_6_bits_idx_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _metaArb_io_in_6_bits_idx_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _metaArb_io_in_6_bits_addr_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _metaArb_io_in_6_bits_addr_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _io_cpu_s2_xcpt_WIRE_size = 2'h0; // @[DCache.scala:933:74]
wire [1:0] metaArb_io_in_0_bits_data_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] metaArb_io_in_0_bits_data_meta_1_coh_state = 2'h0; // @[HellaCache.scala:305:20]
wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[DCache.scala:101:7]
wire [29:0] pma_checker_io_ptw_hstatus_zero6 = 30'h0; // @[DCache.scala:120:32]
wire [29:0] pma_checker_io_ptw_pmp_0_addr = 30'h0; // @[DCache.scala:120:32]
wire [29:0] pma_checker_io_ptw_pmp_1_addr = 30'h0; // @[DCache.scala:120:32]
wire [29:0] pma_checker_io_ptw_pmp_2_addr = 30'h0; // @[DCache.scala:120:32]
wire [29:0] pma_checker_io_ptw_pmp_3_addr = 30'h0; // @[DCache.scala:120:32]
wire [29:0] pma_checker_io_ptw_pmp_4_addr = 30'h0; // @[DCache.scala:120:32]
wire [29:0] pma_checker_io_ptw_pmp_5_addr = 30'h0; // @[DCache.scala:120:32]
wire [29:0] pma_checker_io_ptw_pmp_6_addr = 30'h0; // @[DCache.scala:120:32]
wire [29:0] pma_checker_io_ptw_pmp_7_addr = 30'h0; // @[DCache.scala:120:32]
wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[DCache.scala:101:7]
wire [8:0] pma_checker_io_ptw_hstatus_zero5 = 9'h0; // @[DCache.scala:120:32]
wire [8:0] r_beats1_decode_1 = 9'h0; // @[Edges.scala:220:59]
wire [8:0] r_beats1_1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _r_count_T_1 = 9'h0; // @[Edges.scala:234:27]
wire [8:0] c_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _r_counter_T_1 = 9'h0; // @[Edges.scala:236:21]
wire [8:0] io_cpu_perf_release_beats1_decode = 9'h0; // @[Edges.scala:220:59]
wire [8:0] io_cpu_perf_release_beats1 = 9'h0; // @[Edges.scala:221:14]
wire [8:0] _io_cpu_perf_release_count_T = 9'h0; // @[Edges.scala:234:27]
wire [8:0] io_cpu_perf_release_count = 9'h0; // @[Edges.scala:234:25]
wire [8:0] _io_cpu_perf_release_counter_T = 9'h0; // @[Edges.scala:236:21]
wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[DCache.scala:101:7]
wire [5:0] pma_checker_io_ptw_hstatus_vgein = 6'h0; // @[DCache.scala:120:32]
wire [5:0] pma_checker_real_hits_lo = 6'h0; // @[package.scala:45:27]
wire [5:0] pma_checker_special_entry_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_superpage_entries_0_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_superpage_entries_1_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_superpage_entries_2_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_superpage_entries_3_data_0_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_sectored_entries_0_0_data_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_sectored_entries_0_1_data_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_sectored_entries_0_2_data_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_sectored_entries_0_3_data_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_sectored_entries_0_4_data_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_sectored_entries_0_5_data_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_sectored_entries_0_6_data_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker_sectored_entries_0_7_data_hi_lo = 6'h0; // @[TLB.scala:217:24]
wire [5:0] pma_checker__multipleHits_T = 6'h0; // @[Misc.scala:181:37]
wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[DCache.scala:101:7]
wire [4:0] io_tlb_port_req_bits_cmd = 5'h0; // @[DCache.scala:101:7]
wire [4:0] pma_checker_io_ptw_hstatus_zero1 = 5'h0; // @[DCache.scala:120:32]
wire [4:0] _io_cpu_s2_xcpt_WIRE_cmd = 5'h0; // @[DCache.scala:933:74]
wire [8:0] r_counter1_1 = 9'h1FF; // @[Edges.scala:230:28]
wire [8:0] io_cpu_perf_release_counter1 = 9'h1FF; // @[Edges.scala:230:28]
wire [9:0] _r_counter1_T_1 = 10'h3FF; // @[Edges.scala:230:28]
wire [9:0] _io_cpu_perf_release_counter1_T = 10'h3FF; // @[Edges.scala:230:28]
wire [11:0] pma_checker__gpa_hits_hit_mask_T_2 = 12'h0; // @[TLB.scala:606:24]
wire [11:0] pma_checker__io_resp_gpa_offset_T = 12'h0; // @[TLB.scala:658:47]
wire [11:0] _r_beats1_decode_T_5 = 12'h0; // @[package.scala:243:46]
wire [11:0] _io_cpu_perf_release_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _r_beats1_decode_T_4 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _io_cpu_perf_release_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _r_beats1_decode_T_3 = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _io_cpu_perf_release_beats1_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [19:0] pma_checker_refill_ppn = 20'h0; // @[TLB.scala:406:44]
wire [19:0] pma_checker_newEntry_ppn = 20'h0; // @[TLB.scala:449:24]
wire [19:0] pma_checker__ppn_T_2 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_3 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_4 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_5 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_6 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_7 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_8 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_9 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_10 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_11 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_12 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_13 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_14 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_16 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_17 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_18 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_19 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_20 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_21 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_22 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_23 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_24 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_25 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_26 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_27 = 20'h0; // @[Mux.scala:30:73]
wire [19:0] metaArb_io_in_0_bits_data = 20'h0; // @[DCache.scala:135:28]
wire [19:0] metaArb_io_in_1_bits_data = 20'h0; // @[DCache.scala:135:28]
wire [19:0] s1_meta_0 = 20'h0; // @[DCache.scala:306:58]
wire [19:0] _s2_meta_corrected_WIRE = 20'h0; // @[DCache.scala:361:99]
wire [19:0] _metaArb_io_in_1_bits_data_T = 20'h0; // @[DCache.scala:458:14]
wire [19:0] _metaArb_io_in_0_bits_data_T = 20'h0; // @[DCache.scala:1050:85]
wire [17:0] dummyMeta_tag = 18'h0; // @[HellaCache.scala:305:20]
wire [17:0] s2_meta_corrected_0_tag = 18'h0; // @[DCache.scala:361:99]
wire [17:0] _s2_meta_corrected_T = 18'h0; // @[DCache.scala:361:99]
wire [17:0] metaArb_io_in_1_bits_data_new_meta_tag = 18'h0; // @[DCache.scala:456:31]
wire [17:0] _metaArb_io_in_4_bits_data_T = 18'h0; // @[DCache.scala:913:78]
wire [17:0] metaArb_io_in_4_bits_data_meta_tag = 18'h0; // @[HellaCache.scala:305:20]
wire [17:0] metaArb_io_in_0_bits_data_meta_1_tag = 18'h0; // @[HellaCache.scala:305:20]
wire [13:0] pma_checker_lrscAllowed = 14'h0; // @[TLB.scala:580:24]
wire [13:0] pma_checker__gf_ld_array_T_2 = 14'h0; // @[TLB.scala:600:46]
wire [13:0] pma_checker_gf_ld_array = 14'h0; // @[TLB.scala:600:24]
wire [13:0] pma_checker__gf_st_array_T_1 = 14'h0; // @[TLB.scala:601:53]
wire [13:0] pma_checker_gf_st_array = 14'h0; // @[TLB.scala:601:24]
wire [13:0] pma_checker__gf_inst_array_T = 14'h0; // @[TLB.scala:602:36]
wire [13:0] pma_checker_gf_inst_array = 14'h0; // @[TLB.scala:602:26]
wire [13:0] pma_checker_gpa_hits_need_gpa_mask = 14'h0; // @[TLB.scala:605:73]
wire [13:0] pma_checker__io_resp_gf_ld_T_1 = 14'h0; // @[TLB.scala:637:58]
wire [13:0] pma_checker__io_resp_gf_st_T_1 = 14'h0; // @[TLB.scala:638:65]
wire [13:0] pma_checker__io_resp_gf_inst_T = 14'h0; // @[TLB.scala:639:48]
wire [13:0] _dataArb_io_in_2_bits_addr_T_1 = 14'h0; // @[DCache.scala:903:55]
wire [13:0] _metaArb_io_in_4_bits_addr_T_1 = 14'h0; // @[DCache.scala:912:90]
wire [13:0] _metaArb_io_in_5_bits_addr_T_1 = 14'h0; // @[DCache.scala:1018:98]
wire [7:0] flushCounterWrap = 8'h1; // @[DCache.scala:1011:42]
wire [8:0] flushCounterNext = 9'h1; // @[DCache.scala:1009:39]
wire [31:0] pma_checker_io_ptw_status_isa = 32'h0; // @[DCache.scala:120:32]
wire [31:0] pma_checker_io_ptw_gstatus_isa = 32'h0; // @[DCache.scala:120:32]
wire [31:0] pma_checker_io_ptw_pmp_0_mask = 32'h0; // @[DCache.scala:120:32]
wire [31:0] pma_checker_io_ptw_pmp_1_mask = 32'h0; // @[DCache.scala:120:32]
wire [31:0] pma_checker_io_ptw_pmp_2_mask = 32'h0; // @[DCache.scala:120:32]
wire [31:0] pma_checker_io_ptw_pmp_3_mask = 32'h0; // @[DCache.scala:120:32]
wire [31:0] pma_checker_io_ptw_pmp_4_mask = 32'h0; // @[DCache.scala:120:32]
wire [31:0] pma_checker_io_ptw_pmp_5_mask = 32'h0; // @[DCache.scala:120:32]
wire [31:0] pma_checker_io_ptw_pmp_6_mask = 32'h0; // @[DCache.scala:120:32]
wire [31:0] pma_checker_io_ptw_pmp_7_mask = 32'h0; // @[DCache.scala:120:32]
wire [31:0] tl_out_c_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _s1_probe_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _s1_probe_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _probe_bits_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _probe_bits_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _probe_bits_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _probe_bits_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _atomics_WIRE_address = 32'h0; // @[DCache.scala:587:51]
wire [31:0] _atomics_WIRE_1_address = 32'h0; // @[DCache.scala:587:38]
wire [31:0] _tl_out_a_bits_WIRE_address = 32'h0; // @[DCache.scala:1209:67]
wire [31:0] _tl_out_a_bits_WIRE_1_address = 32'h0; // @[DCache.scala:1209:54]
wire [31:0] _block_probe_for_pending_release_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _block_probe_for_pending_release_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _block_probe_for_pending_release_ack_T = 32'h0; // @[DCache.scala:767:88]
wire [31:0] _metaArb_io_in_6_valid_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _metaArb_io_in_6_valid_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _metaArb_io_in_6_bits_idx_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _metaArb_io_in_6_bits_idx_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _metaArb_io_in_6_bits_addr_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _metaArb_io_in_6_bits_addr_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] nackResponseMessage_address = 32'h0; // @[Edges.scala:416:17]
wire [31:0] cleanReleaseMessage_address = 32'h0; // @[Edges.scala:416:17]
wire [31:0] dirtyReleaseMessage_address = 32'h0; // @[Edges.scala:433:17]
wire [31:0] _io_cpu_s2_xcpt_WIRE_paddr = 32'h0; // @[DCache.scala:933:74]
wire [2:0] pma_checker_real_hits_lo_lo = 3'h0; // @[package.scala:45:27]
wire [2:0] pma_checker_real_hits_lo_hi = 3'h0; // @[package.scala:45:27]
wire [2:0] pma_checker_real_hits_hi_lo = 3'h0; // @[package.scala:45:27]
wire [2:0] pma_checker_special_entry_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_special_entry_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_special_entry_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_0_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_0_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_0_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_1_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_1_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_1_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_2_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_2_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_2_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_3_data_0_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_3_data_0_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_3_data_0_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_waddr_1 = 3'h0; // @[TLB.scala:485:22]
wire [2:0] pma_checker_sectored_entries_0_0_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_0_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_0_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_1_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_1_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_1_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_2_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_2_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_2_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_3_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_3_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_3_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_4_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_4_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_4_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_5_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_5_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_5_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_6_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_6_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_6_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_7_data_hi_lo_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_7_data_hi_lo_hi = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_7_data_hi_hi_lo = 3'h0; // @[TLB.scala:217:24]
wire [2:0] pma_checker_state_vec_0_left_subtree_state = 3'h0; // @[package.scala:163:13]
wire [2:0] pma_checker_state_vec_0_right_subtree_state = 3'h0; // @[Replacement.scala:198:38]
wire [2:0] pma_checker__multipleHits_T_1 = 3'h0; // @[Misc.scala:181:37]
wire [2:0] pma_checker__multipleHits_T_10 = 3'h0; // @[Misc.scala:182:39]
wire [2:0] pma_checker__multipleHits_T_22 = 3'h0; // @[Misc.scala:181:37]
wire [2:0] _s1_probe_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _s1_probe_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _probe_bits_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _probe_bits_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _probe_bits_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _probe_bits_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] get_param = 3'h0; // @[Edges.scala:460:17]
wire [2:0] put_opcode = 3'h0; // @[Edges.scala:480:17]
wire [2:0] put_param = 3'h0; // @[Edges.scala:480:17]
wire [2:0] putpartial_param = 3'h0; // @[Edges.scala:500:17]
wire [2:0] _atomics_WIRE_opcode = 3'h0; // @[DCache.scala:587:51]
wire [2:0] _atomics_WIRE_param = 3'h0; // @[DCache.scala:587:51]
wire [2:0] _atomics_WIRE_1_opcode = 3'h0; // @[DCache.scala:587:38]
wire [2:0] _atomics_WIRE_1_param = 3'h0; // @[DCache.scala:587:38]
wire [2:0] atomics_a_1_param = 3'h0; // @[Edges.scala:534:17]
wire [2:0] atomics_a_5_param = 3'h0; // @[Edges.scala:517:17]
wire [2:0] _tl_out_a_bits_WIRE_opcode = 3'h0; // @[DCache.scala:1209:67]
wire [2:0] _tl_out_a_bits_WIRE_param = 3'h0; // @[DCache.scala:1209:67]
wire [2:0] _tl_out_a_bits_WIRE_1_opcode = 3'h0; // @[DCache.scala:1209:54]
wire [2:0] _tl_out_a_bits_WIRE_1_param = 3'h0; // @[DCache.scala:1209:54]
wire [2:0] _block_probe_for_pending_release_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _block_probe_for_pending_release_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _metaArb_io_in_6_valid_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _metaArb_io_in_6_valid_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _metaArb_io_in_6_bits_idx_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _metaArb_io_in_6_bits_idx_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _metaArb_io_in_6_bits_addr_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _metaArb_io_in_6_bits_addr_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [1:0] _r_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] s2_victim_way = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] dataArb_io_in_0_bits_wordMask_wordMask = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _dataArb_io_in_0_bits_wordMask_T_2 = 2'h1; // @[DCache.scala:555:20]
wire [1:0] _metaArb_io_in_3_bits_data_T_6 = 2'h1; // @[Metadata.scala:25:15]
wire [20:0] pma_checker_io_ptw_req_bits_bits_addr = 21'h0; // @[DCache.scala:120:32]
wire [20:0] pma_checker_special_entry_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_superpage_entries_0_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_superpage_entries_1_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_superpage_entries_2_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_superpage_entries_3_data_0_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_sectored_entries_0_0_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_sectored_entries_0_1_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_sectored_entries_0_2_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_sectored_entries_0_3_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_sectored_entries_0_4_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_sectored_entries_0_5_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_sectored_entries_0_6_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker_sectored_entries_0_7_data_hi_hi_hi_hi = 21'h0; // @[TLB.scala:217:24]
wire [20:0] pma_checker__io_resp_gpa_page_T_2 = 21'h0; // @[TLB.scala:657:58]
wire [63:0] io_cpu_req_bits_data = 64'h0; // @[DCache.scala:101:7]
wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[DCache.scala:101:7]
wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[DCache.scala:101:7]
wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[DCache.scala:101:7]
wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[DCache.scala:101:7]
wire [63:0] pma_checker_io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[DCache.scala:120:32]
wire [63:0] pma_checker_io_ptw_customCSRs_csrs_0_value = 64'h0; // @[DCache.scala:120:32]
wire [63:0] pma_checker_io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[DCache.scala:120:32]
wire [63:0] pma_checker_io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[DCache.scala:120:32]
wire [63:0] pma_checker_io_ptw_customCSRs_csrs_1_value = 64'h0; // @[DCache.scala:120:32]
wire [63:0] pma_checker_io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[DCache.scala:120:32]
wire [63:0] pma_checker_io_ptw_customCSRs_csrs_2_wdata = 64'h0; // @[DCache.scala:120:32]
wire [63:0] pma_checker_io_ptw_customCSRs_csrs_2_value = 64'h0; // @[DCache.scala:120:32]
wire [63:0] pma_checker_io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[DCache.scala:120:32]
wire [63:0] pma_checker_io_ptw_customCSRs_csrs_3_wdata = 64'h0; // @[DCache.scala:120:32]
wire [63:0] pma_checker_io_ptw_customCSRs_csrs_3_value = 64'h0; // @[DCache.scala:120:32]
wire [63:0] pma_checker_io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[DCache.scala:120:32]
wire [63:0] tl_out_c_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _s1_probe_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _s1_probe_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _probe_bits_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _probe_bits_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _probe_bits_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _probe_bits_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] s0_req_data = 64'h0; // @[DCache.scala:192:24]
wire [63:0] get_data = 64'h0; // @[Edges.scala:460:17]
wire [63:0] _atomics_WIRE_data = 64'h0; // @[DCache.scala:587:51]
wire [63:0] _atomics_WIRE_1_data = 64'h0; // @[DCache.scala:587:38]
wire [63:0] _tl_out_a_bits_WIRE_data = 64'h0; // @[DCache.scala:1209:67]
wire [63:0] _tl_out_a_bits_WIRE_1_data = 64'h0; // @[DCache.scala:1209:54]
wire [63:0] _block_probe_for_pending_release_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _block_probe_for_pending_release_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _metaArb_io_in_6_valid_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _metaArb_io_in_6_valid_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _metaArb_io_in_6_bits_idx_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _metaArb_io_in_6_bits_idx_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] _metaArb_io_in_6_bits_addr_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74]
wire [63:0] _metaArb_io_in_6_bits_addr_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:264:61]
wire [63:0] nackResponseMessage_data = 64'h0; // @[Edges.scala:416:17]
wire [63:0] cleanReleaseMessage_data = 64'h0; // @[Edges.scala:416:17]
wire [63:0] dirtyReleaseMessage_data = 64'h0; // @[Edges.scala:433:17]
wire [63:0] _s2_data_word_possibly_uncached_T_1 = 64'h0; // @[DCache.scala:972:43]
wire [32:0] pma_checker_io_sfence_bits_addr = 33'h0; // @[DCache.scala:120:32]
wire [32:0] pma_checker_io_ptw_resp_bits_gpa_bits = 33'h0; // @[DCache.scala:120:32]
wire [33:0] io_tlb_port_req_bits_vaddr = 34'h0; // @[DCache.scala:101:7]
wire [33:0] _io_cpu_s2_xcpt_WIRE_gpa = 34'h0; // @[DCache.scala:933:74]
wire [7:0] dataArb_io_in_2_bits_eccMask = 8'hFF; // @[DCache.scala:152:28]
wire [7:0] dataArb_io_in_3_bits_eccMask = 8'hFF; // @[DCache.scala:152:28]
wire [7:0] _dataArb_io_in_3_bits_wordMask_T = 8'hFF; // @[DCache.scala:254:9]
wire [7:0] _dataArb_io_in_3_bits_eccMask_T = 8'hFF; // @[DCache.scala:256:36]
wire [7:0] _dataArb_io_in_2_bits_eccMask_T = 8'hFF; // @[DCache.scala:905:36]
wire [2:0] tl_out_c_bits_param = 3'h5; // @[Bundles.scala:265:61]
wire [2:0] nackResponseMessage_param = 3'h5; // @[Edges.scala:416:17]
wire [2:0] dirtyReleaseMessage_opcode = 3'h5; // @[Edges.scala:433:17]
wire [2:0] tl_out_c_bits_opcode = 3'h4; // @[Bundles.scala:265:61]
wire [2:0] get_opcode = 3'h4; // @[Edges.scala:460:17]
wire [2:0] atomics_a_4_param = 3'h4; // @[Edges.scala:517:17]
wire [2:0] nackResponseMessage_opcode = 3'h4; // @[Edges.scala:416:17]
wire [2:0] cleanReleaseMessage_opcode = 3'h4; // @[Edges.scala:416:17]
wire [9:0] pma_checker_io_ptw_resp_bits_pte_reserved_for_future = 10'h0; // @[DCache.scala:120:32]
wire [9:0] _releaseDataBeat_T = 10'h0; // @[DCache.scala:804:28]
wire [3:0] _r_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _metaArb_io_in_3_bits_data_T_9 = 4'hC; // @[Metadata.scala:89:10]
wire [3:0] _r_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r_T_67 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _r_T_131 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _metaArb_io_in_3_bits_data_T_7 = 4'h4; // @[Metadata.scala:88:10]
wire [3:0] _r_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r_T_62 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _r_T_126 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _metaArb_io_in_3_bits_data_T_3 = 4'h1; // @[Metadata.scala:86:10]
wire [1:0] _r_T_118 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _r_T_120 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _r_T_122 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _s1_data_way_T = 2'h2; // @[DCache.scala:694:32]
wire [2:0] atomics_a_opcode = 3'h3; // @[Edges.scala:534:17]
wire [2:0] atomics_a_param = 3'h3; // @[Edges.scala:534:17]
wire [2:0] atomics_a_1_opcode = 3'h3; // @[Edges.scala:534:17]
wire [2:0] atomics_a_2_opcode = 3'h3; // @[Edges.scala:534:17]
wire [2:0] atomics_a_3_opcode = 3'h3; // @[Edges.scala:534:17]
wire [2:0] atomics_a_8_param = 3'h3; // @[Edges.scala:517:17]
wire [2:0] atomics_a_3_param = 3'h2; // @[Edges.scala:534:17]
wire [2:0] atomics_a_4_opcode = 3'h2; // @[Edges.scala:517:17]
wire [2:0] atomics_a_5_opcode = 3'h2; // @[Edges.scala:517:17]
wire [2:0] atomics_a_6_opcode = 3'h2; // @[Edges.scala:517:17]
wire [2:0] atomics_a_7_opcode = 3'h2; // @[Edges.scala:517:17]
wire [2:0] atomics_a_7_param = 3'h2; // @[Edges.scala:517:17]
wire [2:0] atomics_a_8_opcode = 3'h2; // @[Edges.scala:517:17]
wire [2:0] putpartial_opcode = 3'h1; // @[Edges.scala:500:17]
wire [2:0] atomics_a_2_param = 3'h1; // @[Edges.scala:534:17]
wire [2:0] atomics_a_6_param = 3'h1; // @[Edges.scala:517:17]
wire [3:0] _r_T_71 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _r_T_135 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _r_T_70 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _r_T_134 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _r_T_69 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _r_T_133 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _r_T_68 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _r_T_132 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _r_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r_T_66 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _r_T_130 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _r_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r_T_65 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _r_T_129 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _r_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r_T_64 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _r_T_128 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _r_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r_T_61 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _r_T_125 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _r_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r_T_60 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _r_T_124 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _r_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [31:0] _inScratchpad_T_2 = 32'h80004000; // @[DCache.scala:303:70]
wire [32:0] _inScratchpad_T_1 = 33'h80004000; // @[DCache.scala:303:70]
wire [31:0] baseAddr = 32'h80000000; // @[DCache.scala:302:93]
wire [6:0] pma_checker_real_hits_hi = 7'h0; // @[package.scala:45:27]
wire [6:0] pma_checker__state_vec_WIRE_0 = 7'h0; // @[Replacement.scala:305:25]
wire [6:0] pma_checker__multipleHits_T_21 = 7'h0; // @[Misc.scala:182:39]
wire [12:0] pma_checker_real_hits = 13'h0; // @[package.scala:45:27]
wire [12:0] pma_checker__stage1_bypass_T = 13'h0; // @[TLB.scala:517:27]
wire [12:0] pma_checker_stage1_bypass = 13'h0; // @[TLB.scala:517:61]
wire [12:0] pma_checker__r_array_T_2 = 13'h0; // @[TLB.scala:520:74]
wire [12:0] pma_checker__hr_array_T_2 = 13'h0; // @[TLB.scala:524:60]
wire [12:0] pma_checker__gpa_hits_T = 13'h0; // @[TLB.scala:607:30]
wire [12:0] pma_checker__tlb_hit_T = 13'h0; // @[TLB.scala:611:28]
wire [12:0] pma_checker__stage1_bypass_T_2 = 13'h1FFF; // @[TLB.scala:517:68]
wire [12:0] pma_checker__stage1_bypass_T_4 = 13'h1FFF; // @[TLB.scala:517:95]
wire [12:0] pma_checker_stage2_bypass = 13'h1FFF; // @[TLB.scala:523:27]
wire [12:0] pma_checker__hr_array_T_4 = 13'h1FFF; // @[TLB.scala:524:111]
wire [12:0] pma_checker__hw_array_T_1 = 13'h1FFF; // @[TLB.scala:525:55]
wire [12:0] pma_checker__hx_array_T_1 = 13'h1FFF; // @[TLB.scala:526:55]
wire [12:0] pma_checker__gpa_hits_hit_mask_T_4 = 13'h1FFF; // @[TLB.scala:606:88]
wire [12:0] pma_checker_gpa_hits_hit_mask = 13'h1FFF; // @[TLB.scala:606:82]
wire [12:0] pma_checker__gpa_hits_T_1 = 13'h1FFF; // @[TLB.scala:607:16]
wire [12:0] pma_checker_gpa_hits = 13'h1FFF; // @[TLB.scala:607:14]
wire [13:0] pma_checker_hr_array = 14'h3FFF; // @[TLB.scala:524:21]
wire [13:0] pma_checker_hw_array = 14'h3FFF; // @[TLB.scala:525:21]
wire [13:0] pma_checker_hx_array = 14'h3FFF; // @[TLB.scala:526:21]
wire [13:0] pma_checker__ae_array_T_1 = 14'h3FFF; // @[TLB.scala:583:19]
wire [13:0] pma_checker__must_alloc_array_T_8 = 14'h3FFF; // @[TLB.scala:596:19]
wire [13:0] pma_checker__gf_ld_array_T_1 = 14'h3FFF; // @[TLB.scala:600:50]
wire [30:0] pma_checker_special_entry_data_0_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_superpage_entries_0_data_0_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_superpage_entries_1_data_0_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_superpage_entries_2_data_0_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_superpage_entries_3_data_0_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_sectored_entries_0_0_data_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_sectored_entries_0_1_data_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_sectored_entries_0_2_data_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_sectored_entries_0_3_data_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_sectored_entries_0_4_data_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_sectored_entries_0_5_data_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_sectored_entries_0_6_data_hi = 31'h0; // @[TLB.scala:217:24]
wire [30:0] pma_checker_sectored_entries_0_7_data_hi = 31'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_special_entry_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_superpage_entries_0_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_superpage_entries_1_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_superpage_entries_2_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_superpage_entries_3_data_0_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_sectored_entries_0_0_data_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_sectored_entries_0_1_data_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_sectored_entries_0_2_data_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_sectored_entries_0_3_data_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_sectored_entries_0_4_data_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_sectored_entries_0_5_data_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_sectored_entries_0_6_data_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [24:0] pma_checker_sectored_entries_0_7_data_hi_hi = 25'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_special_entry_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_superpage_entries_0_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_superpage_entries_1_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_superpage_entries_2_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_superpage_entries_3_data_0_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_sectored_entries_0_0_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_sectored_entries_0_1_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_sectored_entries_0_2_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_sectored_entries_0_3_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_sectored_entries_0_4_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_sectored_entries_0_5_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_sectored_entries_0_6_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [21:0] pma_checker_sectored_entries_0_7_data_hi_hi_hi = 22'h0; // @[TLB.scala:217:24]
wire [13:0] pma_checker_hits = 14'h2000; // @[TLB.scala:442:17]
wire [41:0] pma_checker__mpu_ppn_WIRE_1 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_1 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_3 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_5 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_7 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_9 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_11 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_13 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_15 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_17 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_19 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_21 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_23 = 42'h0; // @[TLB.scala:170:77]
wire [41:0] pma_checker__entries_WIRE_25 = 42'h0; // @[TLB.scala:170:77]
wire hartIdSinkNodeOptIn = auto_hart_id_sink_in_0; // @[DCache.scala:101:7]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[DCache.scala:101:7]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_user_amba_prot_bufferable; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_user_amba_prot_modifiable; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_user_amba_prot_readalloc; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_user_amba_prot_writealloc; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_user_amba_prot_privileged; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[DCache.scala:101:7]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[DCache.scala:101:7]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[DCache.scala:101:7]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[DCache.scala:101:7]
wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[DCache.scala:101:7]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[DCache.scala:101:7]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[DCache.scala:101:7]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[DCache.scala:101:7]
wire metaArb_io_in_7_valid = io_cpu_req_valid_0; // @[DCache.scala:101:7, :135:28]
wire [33:0] metaArb_io_in_7_bits_addr = io_cpu_req_bits_addr_0; // @[DCache.scala:101:7, :135:28]
wire [6:0] s0_req_tag = io_cpu_req_bits_tag_0; // @[DCache.scala:101:7, :192:24]
wire [4:0] s0_req_cmd = io_cpu_req_bits_cmd_0; // @[DCache.scala:101:7, :192:24]
wire [1:0] s0_req_size = io_cpu_req_bits_size_0; // @[DCache.scala:101:7, :192:24]
wire s0_req_signed = io_cpu_req_bits_signed_0; // @[DCache.scala:101:7, :192:24]
wire [1:0] s0_req_dprv = io_cpu_req_bits_dprv_0; // @[DCache.scala:101:7, :192:24]
wire s0_req_dv = io_cpu_req_bits_dv_0; // @[DCache.scala:101:7, :192:24]
wire s0_req_no_resp = io_cpu_req_bits_no_resp_0; // @[DCache.scala:101:7, :192:24]
wire s0_req_no_xcpt = io_cpu_req_bits_no_xcpt_0; // @[DCache.scala:101:7, :192:24]
wire _io_cpu_s2_nack_T_5; // @[DCache.scala:445:86]
wire _io_cpu_s2_nack_cause_raw_T_3; // @[DCache.scala:574:54]
wire _io_cpu_s2_uncached_T_1; // @[DCache.scala:920:37]
wire _io_cpu_resp_valid_T_2; // @[DCache.scala:949:70]
wire [63:0] _io_cpu_resp_bits_data_T_24; // @[DCache.scala:974:41]
wire s2_read; // @[Consts.scala:89:68]
wire [63:0] _io_cpu_resp_bits_data_word_bypass_T_7; // @[AMOALU.scala:45:16]
wire [63:0] s2_data_word; // @[DCache.scala:970:80]
wire _io_cpu_replay_next_T_3; // @[DCache.scala:950:62]
wire _io_cpu_s2_xcpt_T_ma_ld; // @[DCache.scala:933:24]
wire _io_cpu_s2_xcpt_T_ma_st; // @[DCache.scala:933:24]
wire _io_cpu_s2_xcpt_T_pf_ld; // @[DCache.scala:933:24]
wire _io_cpu_s2_xcpt_T_pf_st; // @[DCache.scala:933:24]
wire _io_cpu_s2_xcpt_T_ae_ld; // @[DCache.scala:933:24]
wire _io_cpu_s2_xcpt_T_ae_st; // @[DCache.scala:933:24]
wire _io_cpu_ordered_T_8; // @[DCache.scala:929:21]
wire _io_cpu_store_pending_T_25; // @[DCache.scala:930:70]
wire io_cpu_perf_acquire_done; // @[Edges.scala:233:22]
wire _io_cpu_perf_grant_T; // @[DCache.scala:1078:39]
wire _io_cpu_perf_blocked_T_1; // @[DCache.scala:1106:23]
wire _io_cpu_perf_canAcceptStoreThenLoad_T_10; // @[DCache.scala:1088:41]
wire _io_cpu_perf_canAcceptStoreThenRMW_T_1; // @[DCache.scala:1091:75]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_61; // @[DCache.scala:1092:40]
wire _io_cpu_perf_storeBufferEmptyAfterLoad_T_7; // @[DCache.scala:1080:44]
wire _io_cpu_perf_storeBufferEmptyAfterStore_T_10; // @[DCache.scala:1084:45]
wire _io_errors_bus_valid_T_2; // @[DCache.scala:1129:42]
wire auto_out_a_bits_user_amba_prot_bufferable_0; // @[DCache.scala:101:7]
wire auto_out_a_bits_user_amba_prot_modifiable_0; // @[DCache.scala:101:7]
wire auto_out_a_bits_user_amba_prot_readalloc_0; // @[DCache.scala:101:7]
wire auto_out_a_bits_user_amba_prot_writealloc_0; // @[DCache.scala:101:7]
wire auto_out_a_bits_user_amba_prot_privileged_0; // @[DCache.scala:101:7]
wire [2:0] auto_out_a_bits_opcode_0; // @[DCache.scala:101:7]
wire [2:0] auto_out_a_bits_param_0; // @[DCache.scala:101:7]
wire [3:0] auto_out_a_bits_size_0; // @[DCache.scala:101:7]
wire [31:0] auto_out_a_bits_address_0; // @[DCache.scala:101:7]
wire [7:0] auto_out_a_bits_mask_0; // @[DCache.scala:101:7]
wire [63:0] auto_out_a_bits_data_0; // @[DCache.scala:101:7]
wire auto_out_a_valid_0; // @[DCache.scala:101:7]
wire auto_out_d_ready_0; // @[DCache.scala:101:7]
wire io_cpu_req_ready_0; // @[DCache.scala:101:7]
wire [33:0] io_cpu_resp_bits_addr_0; // @[DCache.scala:101:7]
wire [6:0] io_cpu_resp_bits_tag_0; // @[DCache.scala:101:7]
wire [4:0] io_cpu_resp_bits_cmd_0; // @[DCache.scala:101:7]
wire [1:0] io_cpu_resp_bits_size_0; // @[DCache.scala:101:7]
wire io_cpu_resp_bits_signed_0; // @[DCache.scala:101:7]
wire [1:0] io_cpu_resp_bits_dprv_0; // @[DCache.scala:101:7]
wire io_cpu_resp_bits_dv_0; // @[DCache.scala:101:7]
wire [63:0] io_cpu_resp_bits_data_0; // @[DCache.scala:101:7]
wire [7:0] io_cpu_resp_bits_mask_0; // @[DCache.scala:101:7]
wire io_cpu_resp_bits_replay_0; // @[DCache.scala:101:7]
wire io_cpu_resp_bits_has_data_0; // @[DCache.scala:101:7]
wire [63:0] io_cpu_resp_bits_data_word_bypass_0; // @[DCache.scala:101:7]
wire [63:0] io_cpu_resp_bits_data_raw_0; // @[DCache.scala:101:7]
wire [63:0] io_cpu_resp_bits_store_data_0; // @[DCache.scala:101:7]
wire io_cpu_resp_valid_0; // @[DCache.scala:101:7]
wire io_cpu_s2_xcpt_ma_ld_0; // @[DCache.scala:101:7]
wire io_cpu_s2_xcpt_ma_st_0; // @[DCache.scala:101:7]
wire io_cpu_s2_xcpt_pf_ld_0; // @[DCache.scala:101:7]
wire io_cpu_s2_xcpt_pf_st_0; // @[DCache.scala:101:7]
wire io_cpu_s2_xcpt_ae_ld_0; // @[DCache.scala:101:7]
wire io_cpu_s2_xcpt_ae_st_0; // @[DCache.scala:101:7]
wire io_cpu_perf_acquire_0; // @[DCache.scala:101:7]
wire io_cpu_perf_grant_0; // @[DCache.scala:101:7]
wire io_cpu_perf_blocked_0; // @[DCache.scala:101:7]
wire io_cpu_perf_canAcceptStoreThenLoad_0; // @[DCache.scala:101:7]
wire io_cpu_perf_canAcceptStoreThenRMW_0; // @[DCache.scala:101:7]
wire io_cpu_perf_canAcceptLoadThenLoad_0; // @[DCache.scala:101:7]
wire io_cpu_perf_storeBufferEmptyAfterLoad_0; // @[DCache.scala:101:7]
wire io_cpu_perf_storeBufferEmptyAfterStore_0; // @[DCache.scala:101:7]
wire io_cpu_s2_nack_0; // @[DCache.scala:101:7]
wire io_cpu_s2_nack_cause_raw_0; // @[DCache.scala:101:7]
wire io_cpu_s2_uncached_0; // @[DCache.scala:101:7]
wire [31:0] io_cpu_s2_paddr_0; // @[DCache.scala:101:7]
wire io_cpu_replay_next_0; // @[DCache.scala:101:7]
wire [33:0] io_cpu_s2_gpa_0; // @[DCache.scala:101:7]
wire io_cpu_ordered_0; // @[DCache.scala:101:7]
wire io_cpu_store_pending_0; // @[DCache.scala:101:7]
wire [20:0] io_ptw_req_bits_bits_addr_0; // @[DCache.scala:101:7]
wire io_ptw_req_bits_bits_need_gpa_0; // @[DCache.scala:101:7]
wire io_ptw_req_bits_bits_vstage1_0; // @[DCache.scala:101:7]
wire io_ptw_req_bits_bits_stage2_0; // @[DCache.scala:101:7]
wire io_errors_bus_valid; // @[DCache.scala:101:7]
wire [31:0] io_errors_bus_bits; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_pf_ld; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_pf_st; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_pf_inst; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_ae_ld; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_ae_st; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_ae_inst; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_ma_ld; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_ma_st; // @[DCache.scala:101:7]
wire [31:0] io_tlb_port_s1_resp_paddr; // @[DCache.scala:101:7]
wire [33:0] io_tlb_port_s1_resp_gpa; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_cacheable; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_must_alloc; // @[DCache.scala:101:7]
wire io_tlb_port_s1_resp_prefetchable; // @[DCache.scala:101:7]
wire [1:0] io_tlb_port_s1_resp_size; // @[DCache.scala:101:7]
wire [4:0] io_tlb_port_s1_resp_cmd; // @[DCache.scala:101:7]
wire nodeOut_a_deq_ready = nodeOut_a_ready; // @[Decoupled.scala:356:21]
wire nodeOut_a_deq_valid; // @[Decoupled.scala:356:21]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[DCache.scala:101:7]
wire [2:0] nodeOut_a_deq_bits_opcode; // @[Decoupled.scala:356:21]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[DCache.scala:101:7]
wire [2:0] nodeOut_a_deq_bits_param; // @[Decoupled.scala:356:21]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[DCache.scala:101:7]
wire [3:0] nodeOut_a_deq_bits_size; // @[Decoupled.scala:356:21]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[DCache.scala:101:7]
wire [31:0] nodeOut_a_deq_bits_address; // @[Decoupled.scala:356:21]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[DCache.scala:101:7]
wire nodeOut_a_deq_bits_user_amba_prot_bufferable; // @[Decoupled.scala:356:21]
assign auto_out_a_bits_user_amba_prot_bufferable_0 = nodeOut_a_bits_user_amba_prot_bufferable; // @[DCache.scala:101:7]
wire nodeOut_a_deq_bits_user_amba_prot_modifiable; // @[Decoupled.scala:356:21]
assign auto_out_a_bits_user_amba_prot_modifiable_0 = nodeOut_a_bits_user_amba_prot_modifiable; // @[DCache.scala:101:7]
wire nodeOut_a_deq_bits_user_amba_prot_readalloc; // @[Decoupled.scala:356:21]
assign auto_out_a_bits_user_amba_prot_readalloc_0 = nodeOut_a_bits_user_amba_prot_readalloc; // @[DCache.scala:101:7]
wire nodeOut_a_deq_bits_user_amba_prot_writealloc; // @[Decoupled.scala:356:21]
assign auto_out_a_bits_user_amba_prot_writealloc_0 = nodeOut_a_bits_user_amba_prot_writealloc; // @[DCache.scala:101:7]
wire nodeOut_a_deq_bits_user_amba_prot_privileged; // @[Decoupled.scala:356:21]
assign auto_out_a_bits_user_amba_prot_privileged_0 = nodeOut_a_bits_user_amba_prot_privileged; // @[DCache.scala:101:7]
wire [7:0] nodeOut_a_deq_bits_mask; // @[Decoupled.scala:356:21]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[DCache.scala:101:7]
wire [63:0] nodeOut_a_deq_bits_data; // @[Decoupled.scala:356:21]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[DCache.scala:101:7]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[DCache.scala:101:7]
wire e_sink = nodeOut_d_bits_sink; // @[Edges.scala:451:17]
wire [63:0] s1_uncached_data_word = nodeOut_d_bits_data; // @[package.scala:211:50]
wire [1:0] pma_checker_io_resp_size = pma_checker_io_req_bits_size; // @[DCache.scala:120:32]
wire [4:0] pma_checker_io_resp_cmd = pma_checker_io_req_bits_cmd; // @[DCache.scala:120:32]
wire [31:0] pma_checker__io_resp_paddr_T_1; // @[TLB.scala:652:23]
wire [33:0] pma_checker__io_resp_gpa_T; // @[TLB.scala:659:8]
wire pma_checker__io_resp_pf_ld_T_3; // @[TLB.scala:633:41]
wire pma_checker__io_resp_pf_st_T_3; // @[TLB.scala:634:48]
wire pma_checker__io_resp_pf_inst_T_2; // @[TLB.scala:635:29]
wire pma_checker__io_resp_ae_ld_T_1; // @[TLB.scala:641:41]
wire pma_checker__io_resp_ae_st_T_1; // @[TLB.scala:642:41]
wire pma_checker__io_resp_ae_inst_T_2; // @[TLB.scala:643:41]
wire pma_checker__io_resp_ma_ld_T; // @[TLB.scala:645:31]
wire pma_checker__io_resp_ma_st_T; // @[TLB.scala:646:31]
wire pma_checker__io_resp_cacheable_T_1; // @[TLB.scala:648:41]
wire pma_checker__io_resp_must_alloc_T_1; // @[TLB.scala:649:51]
wire pma_checker__io_resp_prefetchable_T_2; // @[TLB.scala:650:59]
wire [33:0] pma_checker_io_req_bits_vaddr; // @[DCache.scala:120:32]
wire [1:0] pma_checker_io_req_bits_prv; // @[DCache.scala:120:32]
wire pma_checker_io_req_bits_v; // @[DCache.scala:120:32]
wire pma_checker_io_resp_pf_ld; // @[DCache.scala:120:32]
wire pma_checker_io_resp_pf_st; // @[DCache.scala:120:32]
wire pma_checker_io_resp_pf_inst; // @[DCache.scala:120:32]
wire pma_checker_io_resp_ae_ld; // @[DCache.scala:120:32]
wire pma_checker_io_resp_ae_st; // @[DCache.scala:120:32]
wire pma_checker_io_resp_ae_inst; // @[DCache.scala:120:32]
wire pma_checker_io_resp_ma_ld; // @[DCache.scala:120:32]
wire pma_checker_io_resp_ma_st; // @[DCache.scala:120:32]
wire [31:0] pma_checker_io_resp_paddr; // @[DCache.scala:120:32]
wire [33:0] pma_checker_io_resp_gpa; // @[DCache.scala:120:32]
wire pma_checker_io_resp_cacheable; // @[DCache.scala:120:32]
wire pma_checker_io_resp_must_alloc; // @[DCache.scala:120:32]
wire pma_checker_io_resp_prefetchable; // @[DCache.scala:120:32]
wire [20:0] pma_checker_vpn = pma_checker_io_req_bits_vaddr[32:12]; // @[TLB.scala:335:30]
wire [20:0] pma_checker__sector_hits_T_3 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] pma_checker__sector_hits_T_11 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] pma_checker__sector_hits_T_19 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] pma_checker__sector_hits_T_27 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] pma_checker__sector_hits_T_35 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] pma_checker__sector_hits_T_43 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] pma_checker__sector_hits_T_51 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] pma_checker__sector_hits_T_59 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] pma_checker__superpage_hits_T = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] pma_checker__superpage_hits_T_5 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] pma_checker__superpage_hits_T_10 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] pma_checker__superpage_hits_T_15 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] pma_checker__hitsVec_T = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] pma_checker__hitsVec_T_6 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] pma_checker__hitsVec_T_12 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] pma_checker__hitsVec_T_18 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] pma_checker__hitsVec_T_24 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] pma_checker__hitsVec_T_30 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] pma_checker__hitsVec_T_36 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] pma_checker__hitsVec_T_42 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] pma_checker__hitsVec_T_48 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] pma_checker__hitsVec_T_54 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] pma_checker__hitsVec_T_60 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] pma_checker__hitsVec_T_66 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire [20:0] pma_checker__hitsVec_T_72 = pma_checker_vpn; // @[TLB.scala:174:61, :335:30]
wire pma_checker_priv_s = pma_checker_io_req_bits_prv[0]; // @[TLB.scala:370:20]
wire pma_checker_priv_uses_vm = ~(pma_checker_io_req_bits_prv[1]); // @[TLB.scala:372:27]
wire [19:0] pma_checker__mpu_ppn_T_23; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_22; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_21; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_20; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_19; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_18; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_17; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_16; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_15; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_14; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_13; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_12; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_11; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_10; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_9; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_8; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_7; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_6; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_5; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_4; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_3; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_2; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_T_1; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_1 = pma_checker__mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_fragmented_superpage = pma_checker__mpu_ppn_T_1; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_2 = pma_checker__mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_c = pma_checker__mpu_ppn_T_2; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_3 = pma_checker__mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_eff = pma_checker__mpu_ppn_T_3; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_4 = pma_checker__mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_paa = pma_checker__mpu_ppn_T_4; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_5 = pma_checker__mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_pal = pma_checker__mpu_ppn_T_5; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_6 = pma_checker__mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_ppp = pma_checker__mpu_ppn_T_6; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_7 = pma_checker__mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_pr = pma_checker__mpu_ppn_T_7; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_8 = pma_checker__mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_px = pma_checker__mpu_ppn_T_8; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_9 = pma_checker__mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_pw = pma_checker__mpu_ppn_T_9; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_10 = pma_checker__mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_hr = pma_checker__mpu_ppn_T_10; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_11 = pma_checker__mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_hx = pma_checker__mpu_ppn_T_11; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_12 = pma_checker__mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_hw = pma_checker__mpu_ppn_T_12; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_13 = pma_checker__mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_sr = pma_checker__mpu_ppn_T_13; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_14 = pma_checker__mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_sx = pma_checker__mpu_ppn_T_14; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_15 = pma_checker__mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_sw = pma_checker__mpu_ppn_T_15; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_16 = pma_checker__mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_gf = pma_checker__mpu_ppn_T_16; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_17 = pma_checker__mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_pf = pma_checker__mpu_ppn_T_17; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_18 = pma_checker__mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_ae_stage2 = pma_checker__mpu_ppn_T_18; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_19 = pma_checker__mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_ae_final = pma_checker__mpu_ppn_T_19; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_20 = pma_checker__mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_ae_ptw = pma_checker__mpu_ppn_T_20; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_21 = pma_checker__mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_g = pma_checker__mpu_ppn_T_21; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_22 = pma_checker__mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77]
wire pma_checker__mpu_ppn_WIRE_u = pma_checker__mpu_ppn_T_22; // @[TLB.scala:170:77]
assign pma_checker__mpu_ppn_T_23 = pma_checker__mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__mpu_ppn_WIRE_ppn = pma_checker__mpu_ppn_T_23; // @[TLB.scala:170:77]
wire [21:0] pma_checker__mpu_ppn_T_24 = pma_checker_io_req_bits_vaddr[33:12]; // @[TLB.scala:413:146]
wire [21:0] pma_checker__mpu_ppn_T_25 = pma_checker__mpu_ppn_T_24; // @[TLB.scala:413:{20,146}]
wire [21:0] pma_checker_mpu_ppn = pma_checker__mpu_ppn_T_25; // @[TLB.scala:412:20, :413:20]
wire [11:0] pma_checker__mpu_physaddr_T = pma_checker_io_req_bits_vaddr[11:0]; // @[TLB.scala:414:52]
wire [11:0] pma_checker__io_resp_paddr_T = pma_checker_io_req_bits_vaddr[11:0]; // @[TLB.scala:414:52, :652:46]
wire [11:0] pma_checker__io_resp_gpa_offset_T_1 = pma_checker_io_req_bits_vaddr[11:0]; // @[TLB.scala:414:52, :658:82]
wire [33:0] pma_checker_mpu_physaddr = {pma_checker_mpu_ppn, pma_checker__mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}]
wire [33:0] pma_checker__homogeneous_T = pma_checker_mpu_physaddr; // @[TLB.scala:414:25]
wire [33:0] pma_checker__deny_access_to_debug_T_1 = pma_checker_mpu_physaddr; // @[TLB.scala:414:25]
wire [2:0] pma_checker__mpu_priv_T_2 = {1'h0, pma_checker_io_req_bits_prv}; // @[TLB.scala:415:103]
wire [2:0] pma_checker_mpu_priv = pma_checker__mpu_priv_T_2; // @[TLB.scala:415:{27,103}]
wire [34:0] pma_checker__homogeneous_T_1 = {1'h0, pma_checker__homogeneous_T}; // @[Parameters.scala:137:{31,41}]
wire [34:0] pma_checker__homogeneous_T_2 = pma_checker__homogeneous_T_1 & 35'h7FFFFE000; // @[Parameters.scala:137:{41,46}]
wire [34:0] pma_checker__homogeneous_T_3 = pma_checker__homogeneous_T_2; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_4 = pma_checker__homogeneous_T_3 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire pma_checker__homogeneous_T_45 = pma_checker__homogeneous_T_4; // @[TLBPermissions.scala:101:65]
wire [33:0] pma_checker__homogeneous_T_5 = {pma_checker_mpu_physaddr[33:14], pma_checker_mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25]
wire [34:0] pma_checker__homogeneous_T_6 = {1'h0, pma_checker__homogeneous_T_5}; // @[Parameters.scala:137:{31,41}]
wire [34:0] pma_checker__homogeneous_T_7 = pma_checker__homogeneous_T_6 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [34:0] pma_checker__homogeneous_T_8 = pma_checker__homogeneous_T_7; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_9 = pma_checker__homogeneous_T_8 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] _GEN = {pma_checker_mpu_physaddr[33:17], pma_checker_mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25]
wire [33:0] pma_checker__homogeneous_T_10; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_10 = _GEN; // @[Parameters.scala:137:31]
wire [33:0] pma_checker__homogeneous_T_54; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_54 = _GEN; // @[Parameters.scala:137:31]
wire [33:0] pma_checker__homogeneous_T_92; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_92 = _GEN; // @[Parameters.scala:137:31]
wire [33:0] pma_checker__homogeneous_T_105; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_105 = _GEN; // @[Parameters.scala:137:31]
wire [34:0] pma_checker__homogeneous_T_11 = {1'h0, pma_checker__homogeneous_T_10}; // @[Parameters.scala:137:{31,41}]
wire [34:0] pma_checker__homogeneous_T_12 = pma_checker__homogeneous_T_11 & 35'h7FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [34:0] pma_checker__homogeneous_T_13 = pma_checker__homogeneous_T_12; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_14 = pma_checker__homogeneous_T_13 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] _GEN_0 = {pma_checker_mpu_physaddr[33:21], pma_checker_mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25]
wire [33:0] pma_checker__homogeneous_T_15; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_15 = _GEN_0; // @[Parameters.scala:137:31]
wire [33:0] pma_checker__homogeneous_T_66; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_66 = _GEN_0; // @[Parameters.scala:137:31]
wire [34:0] pma_checker__homogeneous_T_16 = {1'h0, pma_checker__homogeneous_T_15}; // @[Parameters.scala:137:{31,41}]
wire [34:0] pma_checker__homogeneous_T_17 = pma_checker__homogeneous_T_16 & 35'h7FFFEF000; // @[Parameters.scala:137:{41,46}]
wire [34:0] pma_checker__homogeneous_T_18 = pma_checker__homogeneous_T_17; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_19 = pma_checker__homogeneous_T_18 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] _GEN_1 = {pma_checker_mpu_physaddr[33:26], pma_checker_mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25]
wire [33:0] pma_checker__homogeneous_T_20; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_20 = _GEN_1; // @[Parameters.scala:137:31]
wire [33:0] pma_checker__homogeneous_T_71; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_71 = _GEN_1; // @[Parameters.scala:137:31]
wire [34:0] pma_checker__homogeneous_T_21 = {1'h0, pma_checker__homogeneous_T_20}; // @[Parameters.scala:137:{31,41}]
wire [34:0] pma_checker__homogeneous_T_22 = pma_checker__homogeneous_T_21 & 35'h7FFFF0000; // @[Parameters.scala:137:{41,46}]
wire [34:0] pma_checker__homogeneous_T_23 = pma_checker__homogeneous_T_22; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_24 = pma_checker__homogeneous_T_23 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] pma_checker__homogeneous_T_25 = {pma_checker_mpu_physaddr[33:28], pma_checker_mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25]
wire [34:0] pma_checker__homogeneous_T_26 = {1'h0, pma_checker__homogeneous_T_25}; // @[Parameters.scala:137:{31,41}]
wire [34:0] pma_checker__homogeneous_T_27 = pma_checker__homogeneous_T_26 & 35'h7FC000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] pma_checker__homogeneous_T_28 = pma_checker__homogeneous_T_27; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_29 = pma_checker__homogeneous_T_28 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] pma_checker__homogeneous_T_30 = {pma_checker_mpu_physaddr[33:29], pma_checker_mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25]
wire [34:0] pma_checker__homogeneous_T_31 = {1'h0, pma_checker__homogeneous_T_30}; // @[Parameters.scala:137:{31,41}]
wire [34:0] pma_checker__homogeneous_T_32 = pma_checker__homogeneous_T_31 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [34:0] pma_checker__homogeneous_T_33 = pma_checker__homogeneous_T_32; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_34 = pma_checker__homogeneous_T_33 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] pma_checker__homogeneous_T_35 = {pma_checker_mpu_physaddr[33:31], pma_checker_mpu_physaddr[30:0] ^ 31'h60000000}; // @[TLB.scala:414:25]
wire [34:0] pma_checker__homogeneous_T_36 = {1'h0, pma_checker__homogeneous_T_35}; // @[Parameters.scala:137:{31,41}]
wire [34:0] pma_checker__homogeneous_T_37 = pma_checker__homogeneous_T_36 & 35'h7E0000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] pma_checker__homogeneous_T_38 = pma_checker__homogeneous_T_37; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_39 = pma_checker__homogeneous_T_38 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] pma_checker__homogeneous_T_40 = {pma_checker_mpu_physaddr[33:32], pma_checker_mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15]
wire [34:0] pma_checker__homogeneous_T_41 = {1'h0, pma_checker__homogeneous_T_40}; // @[Parameters.scala:137:{31,41}]
wire [34:0] pma_checker__homogeneous_T_42 = pma_checker__homogeneous_T_41 & 35'h7FFFFC000; // @[Parameters.scala:137:{41,46}]
wire [34:0] pma_checker__homogeneous_T_43 = pma_checker__homogeneous_T_42; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_44 = pma_checker__homogeneous_T_43 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire pma_checker__homogeneous_T_46 = pma_checker__homogeneous_T_45 | pma_checker__homogeneous_T_9; // @[TLBPermissions.scala:101:65]
wire pma_checker__homogeneous_T_47 = pma_checker__homogeneous_T_46 | pma_checker__homogeneous_T_14; // @[TLBPermissions.scala:101:65]
wire pma_checker__homogeneous_T_48 = pma_checker__homogeneous_T_47 | pma_checker__homogeneous_T_19; // @[TLBPermissions.scala:101:65]
wire pma_checker__homogeneous_T_49 = pma_checker__homogeneous_T_48 | pma_checker__homogeneous_T_24; // @[TLBPermissions.scala:101:65]
wire pma_checker__homogeneous_T_50 = pma_checker__homogeneous_T_49 | pma_checker__homogeneous_T_29; // @[TLBPermissions.scala:101:65]
wire pma_checker__homogeneous_T_51 = pma_checker__homogeneous_T_50 | pma_checker__homogeneous_T_34; // @[TLBPermissions.scala:101:65]
wire pma_checker__homogeneous_T_52 = pma_checker__homogeneous_T_51 | pma_checker__homogeneous_T_39; // @[TLBPermissions.scala:101:65]
wire pma_checker_homogeneous = pma_checker__homogeneous_T_52 | pma_checker__homogeneous_T_44; // @[TLBPermissions.scala:101:65]
wire [34:0] pma_checker__homogeneous_T_55 = {1'h0, pma_checker__homogeneous_T_54}; // @[Parameters.scala:137:{31,41}]
wire [34:0] pma_checker__homogeneous_T_56 = pma_checker__homogeneous_T_55 & 35'hD8110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] pma_checker__homogeneous_T_57 = pma_checker__homogeneous_T_56; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_58 = pma_checker__homogeneous_T_57 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire pma_checker__homogeneous_T_59 = pma_checker__homogeneous_T_58; // @[TLBPermissions.scala:87:66]
wire pma_checker__homogeneous_T_60 = ~pma_checker__homogeneous_T_59; // @[TLBPermissions.scala:87:{22,66}]
wire [33:0] pma_checker__homogeneous_T_61 = {pma_checker_mpu_physaddr[33:13], pma_checker_mpu_physaddr[12:0] ^ 13'h1000}; // @[TLB.scala:414:25]
wire [34:0] pma_checker__homogeneous_T_62 = {1'h0, pma_checker__homogeneous_T_61}; // @[Parameters.scala:137:{31,41}]
wire [34:0] pma_checker__homogeneous_T_63 = pma_checker__homogeneous_T_62 & 35'hDA113000; // @[Parameters.scala:137:{41,46}]
wire [34:0] pma_checker__homogeneous_T_64 = pma_checker__homogeneous_T_63; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_65 = pma_checker__homogeneous_T_64 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire pma_checker__homogeneous_T_86 = pma_checker__homogeneous_T_65; // @[TLBPermissions.scala:87:66]
wire [34:0] pma_checker__homogeneous_T_67 = {1'h0, pma_checker__homogeneous_T_66}; // @[Parameters.scala:137:{31,41}]
wire [34:0] pma_checker__homogeneous_T_68 = pma_checker__homogeneous_T_67 & 35'hDA103000; // @[Parameters.scala:137:{41,46}]
wire [34:0] pma_checker__homogeneous_T_69 = pma_checker__homogeneous_T_68; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_70 = pma_checker__homogeneous_T_69 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] pma_checker__homogeneous_T_72 = {1'h0, pma_checker__homogeneous_T_71}; // @[Parameters.scala:137:{31,41}]
wire [34:0] pma_checker__homogeneous_T_73 = pma_checker__homogeneous_T_72 & 35'hDA110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] pma_checker__homogeneous_T_74 = pma_checker__homogeneous_T_73; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_75 = pma_checker__homogeneous_T_74 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] pma_checker__homogeneous_T_76 = {pma_checker_mpu_physaddr[33:28], pma_checker_mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25]
wire [34:0] pma_checker__homogeneous_T_77 = {1'h0, pma_checker__homogeneous_T_76}; // @[Parameters.scala:137:{31,41}]
wire [34:0] pma_checker__homogeneous_T_78 = pma_checker__homogeneous_T_77 & 35'hD8000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] pma_checker__homogeneous_T_79 = pma_checker__homogeneous_T_78; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_80 = pma_checker__homogeneous_T_79 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] pma_checker__homogeneous_T_81 = {pma_checker_mpu_physaddr[33:29], pma_checker_mpu_physaddr[28:0] ^ 29'h10000000}; // @[TLB.scala:414:25]
wire [34:0] pma_checker__homogeneous_T_82 = {1'h0, pma_checker__homogeneous_T_81}; // @[Parameters.scala:137:{31,41}]
wire [34:0] pma_checker__homogeneous_T_83 = pma_checker__homogeneous_T_82 & 35'hDA113000; // @[Parameters.scala:137:{41,46}]
wire [34:0] pma_checker__homogeneous_T_84 = pma_checker__homogeneous_T_83; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_85 = pma_checker__homogeneous_T_84 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire pma_checker__homogeneous_T_87 = pma_checker__homogeneous_T_86 | pma_checker__homogeneous_T_70; // @[TLBPermissions.scala:87:66]
wire pma_checker__homogeneous_T_88 = pma_checker__homogeneous_T_87 | pma_checker__homogeneous_T_75; // @[TLBPermissions.scala:87:66]
wire pma_checker__homogeneous_T_89 = pma_checker__homogeneous_T_88 | pma_checker__homogeneous_T_80; // @[TLBPermissions.scala:87:66]
wire pma_checker__homogeneous_T_90 = pma_checker__homogeneous_T_89 | pma_checker__homogeneous_T_85; // @[TLBPermissions.scala:87:66]
wire pma_checker__homogeneous_T_91 = ~pma_checker__homogeneous_T_90; // @[TLBPermissions.scala:87:{22,66}]
wire [34:0] pma_checker__homogeneous_T_93 = {1'h0, pma_checker__homogeneous_T_92}; // @[Parameters.scala:137:{31,41}]
wire [34:0] pma_checker__homogeneous_T_94 = pma_checker__homogeneous_T_93 & 35'hD8110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] pma_checker__homogeneous_T_95 = pma_checker__homogeneous_T_94; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_96 = pma_checker__homogeneous_T_95 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire pma_checker__homogeneous_T_102 = pma_checker__homogeneous_T_96; // @[TLBPermissions.scala:87:66]
wire [33:0] _GEN_2 = {pma_checker_mpu_physaddr[33:31], pma_checker_mpu_physaddr[30:0] ^ 31'h40000000}; // @[TLB.scala:414:25]
wire [33:0] pma_checker__homogeneous_T_97; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_97 = _GEN_2; // @[Parameters.scala:137:31]
wire [33:0] pma_checker__homogeneous_T_110; // @[Parameters.scala:137:31]
assign pma_checker__homogeneous_T_110 = _GEN_2; // @[Parameters.scala:137:31]
wire [34:0] pma_checker__homogeneous_T_98 = {1'h0, pma_checker__homogeneous_T_97}; // @[Parameters.scala:137:{31,41}]
wire [34:0] pma_checker__homogeneous_T_99 = pma_checker__homogeneous_T_98 & 35'hC0000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] pma_checker__homogeneous_T_100 = pma_checker__homogeneous_T_99; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_101 = pma_checker__homogeneous_T_100 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire pma_checker__homogeneous_T_103 = pma_checker__homogeneous_T_102 | pma_checker__homogeneous_T_101; // @[TLBPermissions.scala:87:66]
wire pma_checker__homogeneous_T_104 = ~pma_checker__homogeneous_T_103; // @[TLBPermissions.scala:87:{22,66}]
wire [34:0] pma_checker__homogeneous_T_106 = {1'h0, pma_checker__homogeneous_T_105}; // @[Parameters.scala:137:{31,41}]
wire [34:0] pma_checker__homogeneous_T_107 = pma_checker__homogeneous_T_106 & 35'hD8110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] pma_checker__homogeneous_T_108 = pma_checker__homogeneous_T_107; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_109 = pma_checker__homogeneous_T_108 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire pma_checker__homogeneous_T_115 = pma_checker__homogeneous_T_109; // @[TLBPermissions.scala:87:66]
wire [34:0] pma_checker__homogeneous_T_111 = {1'h0, pma_checker__homogeneous_T_110}; // @[Parameters.scala:137:{31,41}]
wire [34:0] pma_checker__homogeneous_T_112 = pma_checker__homogeneous_T_111 & 35'hC0000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] pma_checker__homogeneous_T_113 = pma_checker__homogeneous_T_112; // @[Parameters.scala:137:46]
wire pma_checker__homogeneous_T_114 = pma_checker__homogeneous_T_113 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire pma_checker__homogeneous_T_116 = pma_checker__homogeneous_T_115 | pma_checker__homogeneous_T_114; // @[TLBPermissions.scala:87:66]
wire pma_checker__homogeneous_T_117 = ~pma_checker__homogeneous_T_116; // @[TLBPermissions.scala:87:{22,66}]
wire pma_checker__deny_access_to_debug_T = ~(pma_checker_mpu_priv[2]); // @[TLB.scala:415:27, :428:39]
wire [34:0] pma_checker__deny_access_to_debug_T_2 = {1'h0, pma_checker__deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}]
wire [34:0] pma_checker__deny_access_to_debug_T_3 = pma_checker__deny_access_to_debug_T_2 & 35'h7FFFFF000; // @[Parameters.scala:137:{41,46}]
wire [34:0] pma_checker__deny_access_to_debug_T_4 = pma_checker__deny_access_to_debug_T_3; // @[Parameters.scala:137:46]
wire pma_checker__deny_access_to_debug_T_5 = pma_checker__deny_access_to_debug_T_4 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire pma_checker_deny_access_to_debug = pma_checker__deny_access_to_debug_T & pma_checker__deny_access_to_debug_T_5; // @[TLB.scala:428:{39,50}]
wire pma_checker__prot_r_T = ~pma_checker_deny_access_to_debug; // @[TLB.scala:428:50, :429:33]
wire pma_checker__prot_r_T_1 = _pma_checker_pma_io_resp_r & pma_checker__prot_r_T; // @[TLB.scala:422:19, :429:{30,33}]
wire pma_checker_prot_r = pma_checker__prot_r_T_1 & _pma_checker_pmp_io_r; // @[TLB.scala:416:19, :429:{30,55}]
wire pma_checker_newEntry_pr = pma_checker_prot_r; // @[TLB.scala:429:55, :449:24]
wire pma_checker__prot_w_T = ~pma_checker_deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33]
wire pma_checker__prot_w_T_1 = _pma_checker_pma_io_resp_w & pma_checker__prot_w_T; // @[TLB.scala:422:19, :430:{30,33}]
wire pma_checker_prot_w = pma_checker__prot_w_T_1 & _pma_checker_pmp_io_w; // @[TLB.scala:416:19, :430:{30,55}]
wire pma_checker_newEntry_pw = pma_checker_prot_w; // @[TLB.scala:430:55, :449:24]
wire pma_checker__prot_x_T = ~pma_checker_deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33]
wire pma_checker__prot_x_T_1 = _pma_checker_pma_io_resp_x & pma_checker__prot_x_T; // @[TLB.scala:422:19, :434:{30,33}]
wire pma_checker_prot_x = pma_checker__prot_x_T_1 & _pma_checker_pmp_io_x; // @[TLB.scala:416:19, :434:{30,55}]
wire pma_checker_newEntry_px = pma_checker_prot_x; // @[TLB.scala:434:55, :449:24]
wire pma_checker__sector_hits_T_1 = pma_checker__sector_hits_T; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_2 = pma_checker__sector_hits_T_1; // @[package.scala:81:59]
wire [18:0] pma_checker__sector_hits_T_4 = pma_checker__sector_hits_T_3[20:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__sector_hits_T_5 = pma_checker__sector_hits_T_4 == 19'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__sector_hits_T_7 = pma_checker__sector_hits_T_5 & pma_checker__sector_hits_T_6; // @[TLB.scala:174:{86,95,105}]
wire pma_checker_sector_hits_0 = pma_checker__sector_hits_T_2 & pma_checker__sector_hits_T_7; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_9 = pma_checker__sector_hits_T_8; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_10 = pma_checker__sector_hits_T_9; // @[package.scala:81:59]
wire [18:0] pma_checker__sector_hits_T_12 = pma_checker__sector_hits_T_11[20:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__sector_hits_T_13 = pma_checker__sector_hits_T_12 == 19'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__sector_hits_T_15 = pma_checker__sector_hits_T_13 & pma_checker__sector_hits_T_14; // @[TLB.scala:174:{86,95,105}]
wire pma_checker_sector_hits_1 = pma_checker__sector_hits_T_10 & pma_checker__sector_hits_T_15; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_17 = pma_checker__sector_hits_T_16; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_18 = pma_checker__sector_hits_T_17; // @[package.scala:81:59]
wire [18:0] pma_checker__sector_hits_T_20 = pma_checker__sector_hits_T_19[20:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__sector_hits_T_21 = pma_checker__sector_hits_T_20 == 19'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__sector_hits_T_23 = pma_checker__sector_hits_T_21 & pma_checker__sector_hits_T_22; // @[TLB.scala:174:{86,95,105}]
wire pma_checker_sector_hits_2 = pma_checker__sector_hits_T_18 & pma_checker__sector_hits_T_23; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_25 = pma_checker__sector_hits_T_24; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_26 = pma_checker__sector_hits_T_25; // @[package.scala:81:59]
wire [18:0] pma_checker__sector_hits_T_28 = pma_checker__sector_hits_T_27[20:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__sector_hits_T_29 = pma_checker__sector_hits_T_28 == 19'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__sector_hits_T_31 = pma_checker__sector_hits_T_29 & pma_checker__sector_hits_T_30; // @[TLB.scala:174:{86,95,105}]
wire pma_checker_sector_hits_3 = pma_checker__sector_hits_T_26 & pma_checker__sector_hits_T_31; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_33 = pma_checker__sector_hits_T_32; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_34 = pma_checker__sector_hits_T_33; // @[package.scala:81:59]
wire [18:0] pma_checker__sector_hits_T_36 = pma_checker__sector_hits_T_35[20:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__sector_hits_T_37 = pma_checker__sector_hits_T_36 == 19'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__sector_hits_T_39 = pma_checker__sector_hits_T_37 & pma_checker__sector_hits_T_38; // @[TLB.scala:174:{86,95,105}]
wire pma_checker_sector_hits_4 = pma_checker__sector_hits_T_34 & pma_checker__sector_hits_T_39; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_41 = pma_checker__sector_hits_T_40; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_42 = pma_checker__sector_hits_T_41; // @[package.scala:81:59]
wire [18:0] pma_checker__sector_hits_T_44 = pma_checker__sector_hits_T_43[20:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__sector_hits_T_45 = pma_checker__sector_hits_T_44 == 19'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__sector_hits_T_47 = pma_checker__sector_hits_T_45 & pma_checker__sector_hits_T_46; // @[TLB.scala:174:{86,95,105}]
wire pma_checker_sector_hits_5 = pma_checker__sector_hits_T_42 & pma_checker__sector_hits_T_47; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_49 = pma_checker__sector_hits_T_48; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_50 = pma_checker__sector_hits_T_49; // @[package.scala:81:59]
wire [18:0] pma_checker__sector_hits_T_52 = pma_checker__sector_hits_T_51[20:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__sector_hits_T_53 = pma_checker__sector_hits_T_52 == 19'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__sector_hits_T_55 = pma_checker__sector_hits_T_53 & pma_checker__sector_hits_T_54; // @[TLB.scala:174:{86,95,105}]
wire pma_checker_sector_hits_6 = pma_checker__sector_hits_T_50 & pma_checker__sector_hits_T_55; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_57 = pma_checker__sector_hits_T_56; // @[package.scala:81:59]
wire pma_checker__sector_hits_T_58 = pma_checker__sector_hits_T_57; // @[package.scala:81:59]
wire [18:0] pma_checker__sector_hits_T_60 = pma_checker__sector_hits_T_59[20:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__sector_hits_T_61 = pma_checker__sector_hits_T_60 == 19'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__sector_hits_T_63 = pma_checker__sector_hits_T_61 & pma_checker__sector_hits_T_62; // @[TLB.scala:174:{86,95,105}]
wire pma_checker_sector_hits_7 = pma_checker__sector_hits_T_58 & pma_checker__sector_hits_T_63; // @[package.scala:81:59]
wire [20:0] pma_checker__superpage_hits_T_1 = pma_checker__superpage_hits_T; // @[TLB.scala:174:{61,68}]
wire pma_checker__superpage_hits_T_2 = pma_checker__superpage_hits_T_1 == 21'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__superpage_hits_T_4 = pma_checker__superpage_hits_T_2 & pma_checker__superpage_hits_T_3; // @[TLB.scala:174:{86,95,105}]
wire [20:0] pma_checker__superpage_hits_T_6 = pma_checker__superpage_hits_T_5; // @[TLB.scala:174:{61,68}]
wire pma_checker__superpage_hits_T_7 = pma_checker__superpage_hits_T_6 == 21'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__superpage_hits_T_9 = pma_checker__superpage_hits_T_7 & pma_checker__superpage_hits_T_8; // @[TLB.scala:174:{86,95,105}]
wire [20:0] pma_checker__superpage_hits_T_11 = pma_checker__superpage_hits_T_10; // @[TLB.scala:174:{61,68}]
wire pma_checker__superpage_hits_T_12 = pma_checker__superpage_hits_T_11 == 21'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__superpage_hits_T_14 = pma_checker__superpage_hits_T_12 & pma_checker__superpage_hits_T_13; // @[TLB.scala:174:{86,95,105}]
wire [20:0] pma_checker__superpage_hits_T_16 = pma_checker__superpage_hits_T_15; // @[TLB.scala:174:{61,68}]
wire pma_checker__superpage_hits_T_17 = pma_checker__superpage_hits_T_16 == 21'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__superpage_hits_T_19 = pma_checker__superpage_hits_T_17 & pma_checker__superpage_hits_T_18; // @[TLB.scala:174:{86,95,105}]
wire [1:0] pma_checker_hitsVec_idx = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker_hitsVec_idx_1 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker_hitsVec_idx_2 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker_hitsVec_idx_3 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker_hitsVec_idx_4 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker_hitsVec_idx_5 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker_hitsVec_idx_6 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker_hitsVec_idx_7 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker__entries_T = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker__entries_T_24 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker__entries_T_48 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker__entries_T_72 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker__entries_T_96 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker__entries_T_120 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker__entries_T_144 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker__entries_T_168 = pma_checker_vpn[1:0]; // @[package.scala:163:13]
wire [18:0] pma_checker__hitsVec_T_1 = pma_checker__hitsVec_T[20:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__hitsVec_T_2 = pma_checker__hitsVec_T_1 == 19'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__hitsVec_T_4 = pma_checker__hitsVec_T_2 & pma_checker__hitsVec_T_3; // @[TLB.scala:174:{86,95,105}]
wire [18:0] pma_checker__hitsVec_T_7 = pma_checker__hitsVec_T_6[20:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__hitsVec_T_8 = pma_checker__hitsVec_T_7 == 19'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__hitsVec_T_10 = pma_checker__hitsVec_T_8 & pma_checker__hitsVec_T_9; // @[TLB.scala:174:{86,95,105}]
wire [18:0] pma_checker__hitsVec_T_13 = pma_checker__hitsVec_T_12[20:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__hitsVec_T_14 = pma_checker__hitsVec_T_13 == 19'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__hitsVec_T_16 = pma_checker__hitsVec_T_14 & pma_checker__hitsVec_T_15; // @[TLB.scala:174:{86,95,105}]
wire [18:0] pma_checker__hitsVec_T_19 = pma_checker__hitsVec_T_18[20:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__hitsVec_T_20 = pma_checker__hitsVec_T_19 == 19'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__hitsVec_T_22 = pma_checker__hitsVec_T_20 & pma_checker__hitsVec_T_21; // @[TLB.scala:174:{86,95,105}]
wire [18:0] pma_checker__hitsVec_T_25 = pma_checker__hitsVec_T_24[20:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__hitsVec_T_26 = pma_checker__hitsVec_T_25 == 19'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__hitsVec_T_28 = pma_checker__hitsVec_T_26 & pma_checker__hitsVec_T_27; // @[TLB.scala:174:{86,95,105}]
wire [18:0] pma_checker__hitsVec_T_31 = pma_checker__hitsVec_T_30[20:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__hitsVec_T_32 = pma_checker__hitsVec_T_31 == 19'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__hitsVec_T_34 = pma_checker__hitsVec_T_32 & pma_checker__hitsVec_T_33; // @[TLB.scala:174:{86,95,105}]
wire [18:0] pma_checker__hitsVec_T_37 = pma_checker__hitsVec_T_36[20:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__hitsVec_T_38 = pma_checker__hitsVec_T_37 == 19'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__hitsVec_T_40 = pma_checker__hitsVec_T_38 & pma_checker__hitsVec_T_39; // @[TLB.scala:174:{86,95,105}]
wire [18:0] pma_checker__hitsVec_T_43 = pma_checker__hitsVec_T_42[20:2]; // @[TLB.scala:174:{61,68}]
wire pma_checker__hitsVec_T_44 = pma_checker__hitsVec_T_43 == 19'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__hitsVec_T_46 = pma_checker__hitsVec_T_44 & pma_checker__hitsVec_T_45; // @[TLB.scala:174:{86,95,105}]
wire [20:0] pma_checker__hitsVec_T_49 = pma_checker__hitsVec_T_48; // @[TLB.scala:174:{61,68}]
wire pma_checker__hitsVec_T_50 = pma_checker__hitsVec_T_49 == 21'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__hitsVec_T_52 = pma_checker__hitsVec_T_50 & pma_checker__hitsVec_T_51; // @[TLB.scala:174:{86,95,105}]
wire [20:0] pma_checker__hitsVec_T_55 = pma_checker__hitsVec_T_54; // @[TLB.scala:174:{61,68}]
wire pma_checker__hitsVec_T_56 = pma_checker__hitsVec_T_55 == 21'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__hitsVec_T_58 = pma_checker__hitsVec_T_56 & pma_checker__hitsVec_T_57; // @[TLB.scala:174:{86,95,105}]
wire [20:0] pma_checker__hitsVec_T_61 = pma_checker__hitsVec_T_60; // @[TLB.scala:174:{61,68}]
wire pma_checker__hitsVec_T_62 = pma_checker__hitsVec_T_61 == 21'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__hitsVec_T_64 = pma_checker__hitsVec_T_62 & pma_checker__hitsVec_T_63; // @[TLB.scala:174:{86,95,105}]
wire [20:0] pma_checker__hitsVec_T_67 = pma_checker__hitsVec_T_66; // @[TLB.scala:174:{61,68}]
wire pma_checker__hitsVec_T_68 = pma_checker__hitsVec_T_67 == 21'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__hitsVec_T_70 = pma_checker__hitsVec_T_68 & pma_checker__hitsVec_T_69; // @[TLB.scala:174:{86,95,105}]
wire [20:0] pma_checker__hitsVec_T_73 = pma_checker__hitsVec_T_72; // @[TLB.scala:174:{61,68}]
wire pma_checker__hitsVec_T_74 = pma_checker__hitsVec_T_73 == 21'h0; // @[TLB.scala:174:{68,86}]
wire pma_checker__hitsVec_T_76 = pma_checker__hitsVec_T_74 & pma_checker__hitsVec_T_75; // @[TLB.scala:174:{86,95,105}]
wire pma_checker__hitsVec_T_77 = pma_checker__hitsVec_T_76; // @[TLB.scala:174:95, :188:18]
wire pma_checker_newEntry_ppp; // @[TLB.scala:449:24]
wire pma_checker_newEntry_pal; // @[TLB.scala:449:24]
wire pma_checker_newEntry_paa; // @[TLB.scala:449:24]
wire pma_checker_newEntry_eff; // @[TLB.scala:449:24]
wire [1:0] _GEN_3 = {pma_checker_newEntry_pal, pma_checker_newEntry_paa}; // @[TLB.scala:217:24, :449:24]
wire [1:0] pma_checker_special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_special_entry_data_0_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_1_data_0_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_2_data_0_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_3_data_0_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_0_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_0_data_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_1_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_1_data_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_2_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_2_data_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_3_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_3_data_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_4_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_4_data_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_5_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_5_data_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_6_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_6_data_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_7_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_7_data_lo_lo_hi_hi = _GEN_3; // @[TLB.scala:217:24]
wire [2:0] pma_checker_special_entry_data_0_lo_lo_hi = {pma_checker_special_entry_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_special_entry_data_0_lo_lo = {pma_checker_special_entry_data_0_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [1:0] _GEN_4 = {pma_checker_newEntry_px, pma_checker_newEntry_pr}; // @[TLB.scala:217:24, :449:24]
wire [1:0] pma_checker_special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign pma_checker_special_entry_data_0_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_1_data_0_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_2_data_0_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] pma_checker_superpage_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_3_data_0_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_0_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_0_data_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_1_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_1_data_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_2_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_2_data_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_3_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_3_data_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_4_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_4_data_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_5_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_5_data_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_6_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_6_data_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [1:0] pma_checker_sectored_entries_0_7_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_7_data_lo_hi_lo_hi = _GEN_4; // @[TLB.scala:217:24]
wire [2:0] pma_checker_special_entry_data_0_lo_hi_lo = {pma_checker_special_entry_data_0_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] _GEN_5 = {2'h0, pma_checker_newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] pma_checker_special_entry_data_0_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_special_entry_data_0_lo_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_0_data_0_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_0_data_0_lo_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_1_data_0_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_1_data_0_lo_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_2_data_0_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_2_data_0_lo_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_3_data_0_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_superpage_entries_3_data_0_lo_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_0_data_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_0_data_lo_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_1_data_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_1_data_lo_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_2_data_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_2_data_lo_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_3_data_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_3_data_lo_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_4_data_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_4_data_lo_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_5_data_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_5_data_lo_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_6_data_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_6_data_lo_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_7_data_lo_hi_hi; // @[TLB.scala:217:24]
assign pma_checker_sectored_entries_0_7_data_lo_hi_hi = _GEN_5; // @[TLB.scala:217:24]
wire [5:0] pma_checker_special_entry_data_0_lo_hi = {pma_checker_special_entry_data_0_lo_hi_hi, pma_checker_special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_special_entry_data_0_lo = {pma_checker_special_entry_data_0_lo_hi, pma_checker_special_entry_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__special_entry_data_0_T = {31'h0, pma_checker_special_entry_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_0_data_0_lo_lo_hi = {pma_checker_superpage_entries_0_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_superpage_entries_0_data_0_lo_lo = {pma_checker_superpage_entries_0_data_0_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_0_data_0_lo_hi_lo = {pma_checker_superpage_entries_0_data_0_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [5:0] pma_checker_superpage_entries_0_data_0_lo_hi = {pma_checker_superpage_entries_0_data_0_lo_hi_hi, pma_checker_superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_superpage_entries_0_data_0_lo = {pma_checker_superpage_entries_0_data_0_lo_hi, pma_checker_superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__superpage_entries_0_data_0_T = {31'h0, pma_checker_superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_1_data_0_lo_lo_hi = {pma_checker_superpage_entries_1_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_superpage_entries_1_data_0_lo_lo = {pma_checker_superpage_entries_1_data_0_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_1_data_0_lo_hi_lo = {pma_checker_superpage_entries_1_data_0_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [5:0] pma_checker_superpage_entries_1_data_0_lo_hi = {pma_checker_superpage_entries_1_data_0_lo_hi_hi, pma_checker_superpage_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_superpage_entries_1_data_0_lo = {pma_checker_superpage_entries_1_data_0_lo_hi, pma_checker_superpage_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__superpage_entries_1_data_0_T = {31'h0, pma_checker_superpage_entries_1_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_2_data_0_lo_lo_hi = {pma_checker_superpage_entries_2_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_superpage_entries_2_data_0_lo_lo = {pma_checker_superpage_entries_2_data_0_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_2_data_0_lo_hi_lo = {pma_checker_superpage_entries_2_data_0_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [5:0] pma_checker_superpage_entries_2_data_0_lo_hi = {pma_checker_superpage_entries_2_data_0_lo_hi_hi, pma_checker_superpage_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_superpage_entries_2_data_0_lo = {pma_checker_superpage_entries_2_data_0_lo_hi, pma_checker_superpage_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__superpage_entries_2_data_0_T = {31'h0, pma_checker_superpage_entries_2_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_3_data_0_lo_lo_hi = {pma_checker_superpage_entries_3_data_0_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_superpage_entries_3_data_0_lo_lo = {pma_checker_superpage_entries_3_data_0_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_superpage_entries_3_data_0_lo_hi_lo = {pma_checker_superpage_entries_3_data_0_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [5:0] pma_checker_superpage_entries_3_data_0_lo_hi = {pma_checker_superpage_entries_3_data_0_lo_hi_hi, pma_checker_superpage_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_superpage_entries_3_data_0_lo = {pma_checker_superpage_entries_3_data_0_lo_hi, pma_checker_superpage_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__superpage_entries_3_data_0_T = {31'h0, pma_checker_superpage_entries_3_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_0_data_lo_lo_hi = {pma_checker_sectored_entries_0_0_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_sectored_entries_0_0_data_lo_lo = {pma_checker_sectored_entries_0_0_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_0_data_lo_hi_lo = {pma_checker_sectored_entries_0_0_data_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [5:0] pma_checker_sectored_entries_0_0_data_lo_hi = {pma_checker_sectored_entries_0_0_data_lo_hi_hi, pma_checker_sectored_entries_0_0_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_sectored_entries_0_0_data_lo = {pma_checker_sectored_entries_0_0_data_lo_hi, pma_checker_sectored_entries_0_0_data_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__sectored_entries_0_0_data_T = {31'h0, pma_checker_sectored_entries_0_0_data_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_1_data_lo_lo_hi = {pma_checker_sectored_entries_0_1_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_sectored_entries_0_1_data_lo_lo = {pma_checker_sectored_entries_0_1_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_1_data_lo_hi_lo = {pma_checker_sectored_entries_0_1_data_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [5:0] pma_checker_sectored_entries_0_1_data_lo_hi = {pma_checker_sectored_entries_0_1_data_lo_hi_hi, pma_checker_sectored_entries_0_1_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_sectored_entries_0_1_data_lo = {pma_checker_sectored_entries_0_1_data_lo_hi, pma_checker_sectored_entries_0_1_data_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__sectored_entries_0_1_data_T = {31'h0, pma_checker_sectored_entries_0_1_data_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_2_data_lo_lo_hi = {pma_checker_sectored_entries_0_2_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_sectored_entries_0_2_data_lo_lo = {pma_checker_sectored_entries_0_2_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_2_data_lo_hi_lo = {pma_checker_sectored_entries_0_2_data_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [5:0] pma_checker_sectored_entries_0_2_data_lo_hi = {pma_checker_sectored_entries_0_2_data_lo_hi_hi, pma_checker_sectored_entries_0_2_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_sectored_entries_0_2_data_lo = {pma_checker_sectored_entries_0_2_data_lo_hi, pma_checker_sectored_entries_0_2_data_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__sectored_entries_0_2_data_T = {31'h0, pma_checker_sectored_entries_0_2_data_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_3_data_lo_lo_hi = {pma_checker_sectored_entries_0_3_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_sectored_entries_0_3_data_lo_lo = {pma_checker_sectored_entries_0_3_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_3_data_lo_hi_lo = {pma_checker_sectored_entries_0_3_data_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [5:0] pma_checker_sectored_entries_0_3_data_lo_hi = {pma_checker_sectored_entries_0_3_data_lo_hi_hi, pma_checker_sectored_entries_0_3_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_sectored_entries_0_3_data_lo = {pma_checker_sectored_entries_0_3_data_lo_hi, pma_checker_sectored_entries_0_3_data_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__sectored_entries_0_3_data_T = {31'h0, pma_checker_sectored_entries_0_3_data_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_4_data_lo_lo_hi = {pma_checker_sectored_entries_0_4_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_sectored_entries_0_4_data_lo_lo = {pma_checker_sectored_entries_0_4_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_4_data_lo_hi_lo = {pma_checker_sectored_entries_0_4_data_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [5:0] pma_checker_sectored_entries_0_4_data_lo_hi = {pma_checker_sectored_entries_0_4_data_lo_hi_hi, pma_checker_sectored_entries_0_4_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_sectored_entries_0_4_data_lo = {pma_checker_sectored_entries_0_4_data_lo_hi, pma_checker_sectored_entries_0_4_data_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__sectored_entries_0_4_data_T = {31'h0, pma_checker_sectored_entries_0_4_data_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_5_data_lo_lo_hi = {pma_checker_sectored_entries_0_5_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_sectored_entries_0_5_data_lo_lo = {pma_checker_sectored_entries_0_5_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_5_data_lo_hi_lo = {pma_checker_sectored_entries_0_5_data_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [5:0] pma_checker_sectored_entries_0_5_data_lo_hi = {pma_checker_sectored_entries_0_5_data_lo_hi_hi, pma_checker_sectored_entries_0_5_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_sectored_entries_0_5_data_lo = {pma_checker_sectored_entries_0_5_data_lo_hi, pma_checker_sectored_entries_0_5_data_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__sectored_entries_0_5_data_T = {31'h0, pma_checker_sectored_entries_0_5_data_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_6_data_lo_lo_hi = {pma_checker_sectored_entries_0_6_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_sectored_entries_0_6_data_lo_lo = {pma_checker_sectored_entries_0_6_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_6_data_lo_hi_lo = {pma_checker_sectored_entries_0_6_data_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [5:0] pma_checker_sectored_entries_0_6_data_lo_hi = {pma_checker_sectored_entries_0_6_data_lo_hi_hi, pma_checker_sectored_entries_0_6_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_sectored_entries_0_6_data_lo = {pma_checker_sectored_entries_0_6_data_lo_hi, pma_checker_sectored_entries_0_6_data_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__sectored_entries_0_6_data_T = {31'h0, pma_checker_sectored_entries_0_6_data_lo}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_7_data_lo_lo_hi = {pma_checker_sectored_entries_0_7_data_lo_lo_hi_hi, pma_checker_newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] pma_checker_sectored_entries_0_7_data_lo_lo = {pma_checker_sectored_entries_0_7_data_lo_lo_hi, 2'h0}; // @[TLB.scala:217:24]
wire [2:0] pma_checker_sectored_entries_0_7_data_lo_hi_lo = {pma_checker_sectored_entries_0_7_data_lo_hi_lo_hi, pma_checker_newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [5:0] pma_checker_sectored_entries_0_7_data_lo_hi = {pma_checker_sectored_entries_0_7_data_lo_hi_hi, pma_checker_sectored_entries_0_7_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] pma_checker_sectored_entries_0_7_data_lo = {pma_checker_sectored_entries_0_7_data_lo_hi, pma_checker_sectored_entries_0_7_data_lo_lo}; // @[TLB.scala:217:24]
wire [41:0] pma_checker__sectored_entries_0_7_data_T = {31'h0, pma_checker_sectored_entries_0_7_data_lo}; // @[TLB.scala:217:24]
wire [19:0] pma_checker__entries_T_23; // @[TLB.scala:170:77]
wire pma_checker__entries_T_22; // @[TLB.scala:170:77]
wire pma_checker__entries_T_21; // @[TLB.scala:170:77]
wire pma_checker__entries_T_20; // @[TLB.scala:170:77]
wire pma_checker__entries_T_19; // @[TLB.scala:170:77]
wire pma_checker__entries_T_18; // @[TLB.scala:170:77]
wire pma_checker__entries_T_17; // @[TLB.scala:170:77]
wire pma_checker__entries_T_16; // @[TLB.scala:170:77]
wire pma_checker__entries_T_15; // @[TLB.scala:170:77]
wire pma_checker__entries_T_14; // @[TLB.scala:170:77]
wire pma_checker__entries_T_13; // @[TLB.scala:170:77]
wire pma_checker__entries_T_12; // @[TLB.scala:170:77]
wire pma_checker__entries_T_11; // @[TLB.scala:170:77]
wire pma_checker__entries_T_10; // @[TLB.scala:170:77]
wire pma_checker__entries_T_9; // @[TLB.scala:170:77]
wire pma_checker__entries_T_8; // @[TLB.scala:170:77]
wire pma_checker__entries_T_7; // @[TLB.scala:170:77]
wire pma_checker__entries_T_6; // @[TLB.scala:170:77]
wire pma_checker__entries_T_5; // @[TLB.scala:170:77]
wire pma_checker__entries_T_4; // @[TLB.scala:170:77]
wire pma_checker__entries_T_3; // @[TLB.scala:170:77]
wire pma_checker__entries_T_2; // @[TLB.scala:170:77]
wire pma_checker__entries_T_1; // @[TLB.scala:170:77]
assign pma_checker__entries_T_1 = pma_checker__entries_WIRE_1[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_fragmented_superpage = pma_checker__entries_T_1; // @[TLB.scala:170:77]
assign pma_checker__entries_T_2 = pma_checker__entries_WIRE_1[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_c = pma_checker__entries_T_2; // @[TLB.scala:170:77]
assign pma_checker__entries_T_3 = pma_checker__entries_WIRE_1[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_eff = pma_checker__entries_T_3; // @[TLB.scala:170:77]
assign pma_checker__entries_T_4 = pma_checker__entries_WIRE_1[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_paa = pma_checker__entries_T_4; // @[TLB.scala:170:77]
assign pma_checker__entries_T_5 = pma_checker__entries_WIRE_1[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_pal = pma_checker__entries_T_5; // @[TLB.scala:170:77]
assign pma_checker__entries_T_6 = pma_checker__entries_WIRE_1[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_ppp = pma_checker__entries_T_6; // @[TLB.scala:170:77]
assign pma_checker__entries_T_7 = pma_checker__entries_WIRE_1[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_pr = pma_checker__entries_T_7; // @[TLB.scala:170:77]
assign pma_checker__entries_T_8 = pma_checker__entries_WIRE_1[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_px = pma_checker__entries_T_8; // @[TLB.scala:170:77]
assign pma_checker__entries_T_9 = pma_checker__entries_WIRE_1[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_pw = pma_checker__entries_T_9; // @[TLB.scala:170:77]
assign pma_checker__entries_T_10 = pma_checker__entries_WIRE_1[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_hr = pma_checker__entries_T_10; // @[TLB.scala:170:77]
assign pma_checker__entries_T_11 = pma_checker__entries_WIRE_1[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_hx = pma_checker__entries_T_11; // @[TLB.scala:170:77]
assign pma_checker__entries_T_12 = pma_checker__entries_WIRE_1[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_hw = pma_checker__entries_T_12; // @[TLB.scala:170:77]
assign pma_checker__entries_T_13 = pma_checker__entries_WIRE_1[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_sr = pma_checker__entries_T_13; // @[TLB.scala:170:77]
assign pma_checker__entries_T_14 = pma_checker__entries_WIRE_1[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_sx = pma_checker__entries_T_14; // @[TLB.scala:170:77]
assign pma_checker__entries_T_15 = pma_checker__entries_WIRE_1[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_sw = pma_checker__entries_T_15; // @[TLB.scala:170:77]
assign pma_checker__entries_T_16 = pma_checker__entries_WIRE_1[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_gf = pma_checker__entries_T_16; // @[TLB.scala:170:77]
assign pma_checker__entries_T_17 = pma_checker__entries_WIRE_1[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_pf = pma_checker__entries_T_17; // @[TLB.scala:170:77]
assign pma_checker__entries_T_18 = pma_checker__entries_WIRE_1[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_ae_stage2 = pma_checker__entries_T_18; // @[TLB.scala:170:77]
assign pma_checker__entries_T_19 = pma_checker__entries_WIRE_1[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_ae_final = pma_checker__entries_T_19; // @[TLB.scala:170:77]
assign pma_checker__entries_T_20 = pma_checker__entries_WIRE_1[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_ae_ptw = pma_checker__entries_T_20; // @[TLB.scala:170:77]
assign pma_checker__entries_T_21 = pma_checker__entries_WIRE_1[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_g = pma_checker__entries_T_21; // @[TLB.scala:170:77]
assign pma_checker__entries_T_22 = pma_checker__entries_WIRE_1[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_u = pma_checker__entries_T_22; // @[TLB.scala:170:77]
assign pma_checker__entries_T_23 = pma_checker__entries_WIRE_1[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_ppn = pma_checker__entries_T_23; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_47; // @[TLB.scala:170:77]
wire pma_checker__entries_T_46; // @[TLB.scala:170:77]
wire pma_checker__entries_T_45; // @[TLB.scala:170:77]
wire pma_checker__entries_T_44; // @[TLB.scala:170:77]
wire pma_checker__entries_T_43; // @[TLB.scala:170:77]
wire pma_checker__entries_T_42; // @[TLB.scala:170:77]
wire pma_checker__entries_T_41; // @[TLB.scala:170:77]
wire pma_checker__entries_T_40; // @[TLB.scala:170:77]
wire pma_checker__entries_T_39; // @[TLB.scala:170:77]
wire pma_checker__entries_T_38; // @[TLB.scala:170:77]
wire pma_checker__entries_T_37; // @[TLB.scala:170:77]
wire pma_checker__entries_T_36; // @[TLB.scala:170:77]
wire pma_checker__entries_T_35; // @[TLB.scala:170:77]
wire pma_checker__entries_T_34; // @[TLB.scala:170:77]
wire pma_checker__entries_T_33; // @[TLB.scala:170:77]
wire pma_checker__entries_T_32; // @[TLB.scala:170:77]
wire pma_checker__entries_T_31; // @[TLB.scala:170:77]
wire pma_checker__entries_T_30; // @[TLB.scala:170:77]
wire pma_checker__entries_T_29; // @[TLB.scala:170:77]
wire pma_checker__entries_T_28; // @[TLB.scala:170:77]
wire pma_checker__entries_T_27; // @[TLB.scala:170:77]
wire pma_checker__entries_T_26; // @[TLB.scala:170:77]
wire pma_checker__entries_T_25; // @[TLB.scala:170:77]
assign pma_checker__entries_T_25 = pma_checker__entries_WIRE_3[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_fragmented_superpage = pma_checker__entries_T_25; // @[TLB.scala:170:77]
assign pma_checker__entries_T_26 = pma_checker__entries_WIRE_3[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_c = pma_checker__entries_T_26; // @[TLB.scala:170:77]
assign pma_checker__entries_T_27 = pma_checker__entries_WIRE_3[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_eff = pma_checker__entries_T_27; // @[TLB.scala:170:77]
assign pma_checker__entries_T_28 = pma_checker__entries_WIRE_3[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_paa = pma_checker__entries_T_28; // @[TLB.scala:170:77]
assign pma_checker__entries_T_29 = pma_checker__entries_WIRE_3[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_pal = pma_checker__entries_T_29; // @[TLB.scala:170:77]
assign pma_checker__entries_T_30 = pma_checker__entries_WIRE_3[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_ppp = pma_checker__entries_T_30; // @[TLB.scala:170:77]
assign pma_checker__entries_T_31 = pma_checker__entries_WIRE_3[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_pr = pma_checker__entries_T_31; // @[TLB.scala:170:77]
assign pma_checker__entries_T_32 = pma_checker__entries_WIRE_3[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_px = pma_checker__entries_T_32; // @[TLB.scala:170:77]
assign pma_checker__entries_T_33 = pma_checker__entries_WIRE_3[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_pw = pma_checker__entries_T_33; // @[TLB.scala:170:77]
assign pma_checker__entries_T_34 = pma_checker__entries_WIRE_3[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_hr = pma_checker__entries_T_34; // @[TLB.scala:170:77]
assign pma_checker__entries_T_35 = pma_checker__entries_WIRE_3[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_hx = pma_checker__entries_T_35; // @[TLB.scala:170:77]
assign pma_checker__entries_T_36 = pma_checker__entries_WIRE_3[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_hw = pma_checker__entries_T_36; // @[TLB.scala:170:77]
assign pma_checker__entries_T_37 = pma_checker__entries_WIRE_3[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_sr = pma_checker__entries_T_37; // @[TLB.scala:170:77]
assign pma_checker__entries_T_38 = pma_checker__entries_WIRE_3[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_sx = pma_checker__entries_T_38; // @[TLB.scala:170:77]
assign pma_checker__entries_T_39 = pma_checker__entries_WIRE_3[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_sw = pma_checker__entries_T_39; // @[TLB.scala:170:77]
assign pma_checker__entries_T_40 = pma_checker__entries_WIRE_3[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_gf = pma_checker__entries_T_40; // @[TLB.scala:170:77]
assign pma_checker__entries_T_41 = pma_checker__entries_WIRE_3[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_pf = pma_checker__entries_T_41; // @[TLB.scala:170:77]
assign pma_checker__entries_T_42 = pma_checker__entries_WIRE_3[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_ae_stage2 = pma_checker__entries_T_42; // @[TLB.scala:170:77]
assign pma_checker__entries_T_43 = pma_checker__entries_WIRE_3[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_ae_final = pma_checker__entries_T_43; // @[TLB.scala:170:77]
assign pma_checker__entries_T_44 = pma_checker__entries_WIRE_3[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_ae_ptw = pma_checker__entries_T_44; // @[TLB.scala:170:77]
assign pma_checker__entries_T_45 = pma_checker__entries_WIRE_3[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_g = pma_checker__entries_T_45; // @[TLB.scala:170:77]
assign pma_checker__entries_T_46 = pma_checker__entries_WIRE_3[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_2_u = pma_checker__entries_T_46; // @[TLB.scala:170:77]
assign pma_checker__entries_T_47 = pma_checker__entries_WIRE_3[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_2_ppn = pma_checker__entries_T_47; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_71; // @[TLB.scala:170:77]
wire pma_checker__entries_T_70; // @[TLB.scala:170:77]
wire pma_checker__entries_T_69; // @[TLB.scala:170:77]
wire pma_checker__entries_T_68; // @[TLB.scala:170:77]
wire pma_checker__entries_T_67; // @[TLB.scala:170:77]
wire pma_checker__entries_T_66; // @[TLB.scala:170:77]
wire pma_checker__entries_T_65; // @[TLB.scala:170:77]
wire pma_checker__entries_T_64; // @[TLB.scala:170:77]
wire pma_checker__entries_T_63; // @[TLB.scala:170:77]
wire pma_checker__entries_T_62; // @[TLB.scala:170:77]
wire pma_checker__entries_T_61; // @[TLB.scala:170:77]
wire pma_checker__entries_T_60; // @[TLB.scala:170:77]
wire pma_checker__entries_T_59; // @[TLB.scala:170:77]
wire pma_checker__entries_T_58; // @[TLB.scala:170:77]
wire pma_checker__entries_T_57; // @[TLB.scala:170:77]
wire pma_checker__entries_T_56; // @[TLB.scala:170:77]
wire pma_checker__entries_T_55; // @[TLB.scala:170:77]
wire pma_checker__entries_T_54; // @[TLB.scala:170:77]
wire pma_checker__entries_T_53; // @[TLB.scala:170:77]
wire pma_checker__entries_T_52; // @[TLB.scala:170:77]
wire pma_checker__entries_T_51; // @[TLB.scala:170:77]
wire pma_checker__entries_T_50; // @[TLB.scala:170:77]
wire pma_checker__entries_T_49; // @[TLB.scala:170:77]
assign pma_checker__entries_T_49 = pma_checker__entries_WIRE_5[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_fragmented_superpage = pma_checker__entries_T_49; // @[TLB.scala:170:77]
assign pma_checker__entries_T_50 = pma_checker__entries_WIRE_5[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_c = pma_checker__entries_T_50; // @[TLB.scala:170:77]
assign pma_checker__entries_T_51 = pma_checker__entries_WIRE_5[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_eff = pma_checker__entries_T_51; // @[TLB.scala:170:77]
assign pma_checker__entries_T_52 = pma_checker__entries_WIRE_5[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_paa = pma_checker__entries_T_52; // @[TLB.scala:170:77]
assign pma_checker__entries_T_53 = pma_checker__entries_WIRE_5[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_pal = pma_checker__entries_T_53; // @[TLB.scala:170:77]
assign pma_checker__entries_T_54 = pma_checker__entries_WIRE_5[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_ppp = pma_checker__entries_T_54; // @[TLB.scala:170:77]
assign pma_checker__entries_T_55 = pma_checker__entries_WIRE_5[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_pr = pma_checker__entries_T_55; // @[TLB.scala:170:77]
assign pma_checker__entries_T_56 = pma_checker__entries_WIRE_5[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_px = pma_checker__entries_T_56; // @[TLB.scala:170:77]
assign pma_checker__entries_T_57 = pma_checker__entries_WIRE_5[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_pw = pma_checker__entries_T_57; // @[TLB.scala:170:77]
assign pma_checker__entries_T_58 = pma_checker__entries_WIRE_5[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_hr = pma_checker__entries_T_58; // @[TLB.scala:170:77]
assign pma_checker__entries_T_59 = pma_checker__entries_WIRE_5[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_hx = pma_checker__entries_T_59; // @[TLB.scala:170:77]
assign pma_checker__entries_T_60 = pma_checker__entries_WIRE_5[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_hw = pma_checker__entries_T_60; // @[TLB.scala:170:77]
assign pma_checker__entries_T_61 = pma_checker__entries_WIRE_5[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_sr = pma_checker__entries_T_61; // @[TLB.scala:170:77]
assign pma_checker__entries_T_62 = pma_checker__entries_WIRE_5[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_sx = pma_checker__entries_T_62; // @[TLB.scala:170:77]
assign pma_checker__entries_T_63 = pma_checker__entries_WIRE_5[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_sw = pma_checker__entries_T_63; // @[TLB.scala:170:77]
assign pma_checker__entries_T_64 = pma_checker__entries_WIRE_5[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_gf = pma_checker__entries_T_64; // @[TLB.scala:170:77]
assign pma_checker__entries_T_65 = pma_checker__entries_WIRE_5[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_pf = pma_checker__entries_T_65; // @[TLB.scala:170:77]
assign pma_checker__entries_T_66 = pma_checker__entries_WIRE_5[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_ae_stage2 = pma_checker__entries_T_66; // @[TLB.scala:170:77]
assign pma_checker__entries_T_67 = pma_checker__entries_WIRE_5[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_ae_final = pma_checker__entries_T_67; // @[TLB.scala:170:77]
assign pma_checker__entries_T_68 = pma_checker__entries_WIRE_5[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_ae_ptw = pma_checker__entries_T_68; // @[TLB.scala:170:77]
assign pma_checker__entries_T_69 = pma_checker__entries_WIRE_5[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_g = pma_checker__entries_T_69; // @[TLB.scala:170:77]
assign pma_checker__entries_T_70 = pma_checker__entries_WIRE_5[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_4_u = pma_checker__entries_T_70; // @[TLB.scala:170:77]
assign pma_checker__entries_T_71 = pma_checker__entries_WIRE_5[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_4_ppn = pma_checker__entries_T_71; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_95; // @[TLB.scala:170:77]
wire pma_checker__entries_T_94; // @[TLB.scala:170:77]
wire pma_checker__entries_T_93; // @[TLB.scala:170:77]
wire pma_checker__entries_T_92; // @[TLB.scala:170:77]
wire pma_checker__entries_T_91; // @[TLB.scala:170:77]
wire pma_checker__entries_T_90; // @[TLB.scala:170:77]
wire pma_checker__entries_T_89; // @[TLB.scala:170:77]
wire pma_checker__entries_T_88; // @[TLB.scala:170:77]
wire pma_checker__entries_T_87; // @[TLB.scala:170:77]
wire pma_checker__entries_T_86; // @[TLB.scala:170:77]
wire pma_checker__entries_T_85; // @[TLB.scala:170:77]
wire pma_checker__entries_T_84; // @[TLB.scala:170:77]
wire pma_checker__entries_T_83; // @[TLB.scala:170:77]
wire pma_checker__entries_T_82; // @[TLB.scala:170:77]
wire pma_checker__entries_T_81; // @[TLB.scala:170:77]
wire pma_checker__entries_T_80; // @[TLB.scala:170:77]
wire pma_checker__entries_T_79; // @[TLB.scala:170:77]
wire pma_checker__entries_T_78; // @[TLB.scala:170:77]
wire pma_checker__entries_T_77; // @[TLB.scala:170:77]
wire pma_checker__entries_T_76; // @[TLB.scala:170:77]
wire pma_checker__entries_T_75; // @[TLB.scala:170:77]
wire pma_checker__entries_T_74; // @[TLB.scala:170:77]
wire pma_checker__entries_T_73; // @[TLB.scala:170:77]
assign pma_checker__entries_T_73 = pma_checker__entries_WIRE_7[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_fragmented_superpage = pma_checker__entries_T_73; // @[TLB.scala:170:77]
assign pma_checker__entries_T_74 = pma_checker__entries_WIRE_7[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_c = pma_checker__entries_T_74; // @[TLB.scala:170:77]
assign pma_checker__entries_T_75 = pma_checker__entries_WIRE_7[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_eff = pma_checker__entries_T_75; // @[TLB.scala:170:77]
assign pma_checker__entries_T_76 = pma_checker__entries_WIRE_7[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_paa = pma_checker__entries_T_76; // @[TLB.scala:170:77]
assign pma_checker__entries_T_77 = pma_checker__entries_WIRE_7[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_pal = pma_checker__entries_T_77; // @[TLB.scala:170:77]
assign pma_checker__entries_T_78 = pma_checker__entries_WIRE_7[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_ppp = pma_checker__entries_T_78; // @[TLB.scala:170:77]
assign pma_checker__entries_T_79 = pma_checker__entries_WIRE_7[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_pr = pma_checker__entries_T_79; // @[TLB.scala:170:77]
assign pma_checker__entries_T_80 = pma_checker__entries_WIRE_7[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_px = pma_checker__entries_T_80; // @[TLB.scala:170:77]
assign pma_checker__entries_T_81 = pma_checker__entries_WIRE_7[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_pw = pma_checker__entries_T_81; // @[TLB.scala:170:77]
assign pma_checker__entries_T_82 = pma_checker__entries_WIRE_7[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_hr = pma_checker__entries_T_82; // @[TLB.scala:170:77]
assign pma_checker__entries_T_83 = pma_checker__entries_WIRE_7[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_hx = pma_checker__entries_T_83; // @[TLB.scala:170:77]
assign pma_checker__entries_T_84 = pma_checker__entries_WIRE_7[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_hw = pma_checker__entries_T_84; // @[TLB.scala:170:77]
assign pma_checker__entries_T_85 = pma_checker__entries_WIRE_7[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_sr = pma_checker__entries_T_85; // @[TLB.scala:170:77]
assign pma_checker__entries_T_86 = pma_checker__entries_WIRE_7[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_sx = pma_checker__entries_T_86; // @[TLB.scala:170:77]
assign pma_checker__entries_T_87 = pma_checker__entries_WIRE_7[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_sw = pma_checker__entries_T_87; // @[TLB.scala:170:77]
assign pma_checker__entries_T_88 = pma_checker__entries_WIRE_7[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_gf = pma_checker__entries_T_88; // @[TLB.scala:170:77]
assign pma_checker__entries_T_89 = pma_checker__entries_WIRE_7[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_pf = pma_checker__entries_T_89; // @[TLB.scala:170:77]
assign pma_checker__entries_T_90 = pma_checker__entries_WIRE_7[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_ae_stage2 = pma_checker__entries_T_90; // @[TLB.scala:170:77]
assign pma_checker__entries_T_91 = pma_checker__entries_WIRE_7[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_ae_final = pma_checker__entries_T_91; // @[TLB.scala:170:77]
assign pma_checker__entries_T_92 = pma_checker__entries_WIRE_7[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_ae_ptw = pma_checker__entries_T_92; // @[TLB.scala:170:77]
assign pma_checker__entries_T_93 = pma_checker__entries_WIRE_7[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_g = pma_checker__entries_T_93; // @[TLB.scala:170:77]
assign pma_checker__entries_T_94 = pma_checker__entries_WIRE_7[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_6_u = pma_checker__entries_T_94; // @[TLB.scala:170:77]
assign pma_checker__entries_T_95 = pma_checker__entries_WIRE_7[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_6_ppn = pma_checker__entries_T_95; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_119; // @[TLB.scala:170:77]
wire pma_checker__entries_T_118; // @[TLB.scala:170:77]
wire pma_checker__entries_T_117; // @[TLB.scala:170:77]
wire pma_checker__entries_T_116; // @[TLB.scala:170:77]
wire pma_checker__entries_T_115; // @[TLB.scala:170:77]
wire pma_checker__entries_T_114; // @[TLB.scala:170:77]
wire pma_checker__entries_T_113; // @[TLB.scala:170:77]
wire pma_checker__entries_T_112; // @[TLB.scala:170:77]
wire pma_checker__entries_T_111; // @[TLB.scala:170:77]
wire pma_checker__entries_T_110; // @[TLB.scala:170:77]
wire pma_checker__entries_T_109; // @[TLB.scala:170:77]
wire pma_checker__entries_T_108; // @[TLB.scala:170:77]
wire pma_checker__entries_T_107; // @[TLB.scala:170:77]
wire pma_checker__entries_T_106; // @[TLB.scala:170:77]
wire pma_checker__entries_T_105; // @[TLB.scala:170:77]
wire pma_checker__entries_T_104; // @[TLB.scala:170:77]
wire pma_checker__entries_T_103; // @[TLB.scala:170:77]
wire pma_checker__entries_T_102; // @[TLB.scala:170:77]
wire pma_checker__entries_T_101; // @[TLB.scala:170:77]
wire pma_checker__entries_T_100; // @[TLB.scala:170:77]
wire pma_checker__entries_T_99; // @[TLB.scala:170:77]
wire pma_checker__entries_T_98; // @[TLB.scala:170:77]
wire pma_checker__entries_T_97; // @[TLB.scala:170:77]
assign pma_checker__entries_T_97 = pma_checker__entries_WIRE_9[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_fragmented_superpage = pma_checker__entries_T_97; // @[TLB.scala:170:77]
assign pma_checker__entries_T_98 = pma_checker__entries_WIRE_9[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_c = pma_checker__entries_T_98; // @[TLB.scala:170:77]
assign pma_checker__entries_T_99 = pma_checker__entries_WIRE_9[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_eff = pma_checker__entries_T_99; // @[TLB.scala:170:77]
assign pma_checker__entries_T_100 = pma_checker__entries_WIRE_9[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_paa = pma_checker__entries_T_100; // @[TLB.scala:170:77]
assign pma_checker__entries_T_101 = pma_checker__entries_WIRE_9[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_pal = pma_checker__entries_T_101; // @[TLB.scala:170:77]
assign pma_checker__entries_T_102 = pma_checker__entries_WIRE_9[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_ppp = pma_checker__entries_T_102; // @[TLB.scala:170:77]
assign pma_checker__entries_T_103 = pma_checker__entries_WIRE_9[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_pr = pma_checker__entries_T_103; // @[TLB.scala:170:77]
assign pma_checker__entries_T_104 = pma_checker__entries_WIRE_9[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_px = pma_checker__entries_T_104; // @[TLB.scala:170:77]
assign pma_checker__entries_T_105 = pma_checker__entries_WIRE_9[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_pw = pma_checker__entries_T_105; // @[TLB.scala:170:77]
assign pma_checker__entries_T_106 = pma_checker__entries_WIRE_9[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_hr = pma_checker__entries_T_106; // @[TLB.scala:170:77]
assign pma_checker__entries_T_107 = pma_checker__entries_WIRE_9[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_hx = pma_checker__entries_T_107; // @[TLB.scala:170:77]
assign pma_checker__entries_T_108 = pma_checker__entries_WIRE_9[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_hw = pma_checker__entries_T_108; // @[TLB.scala:170:77]
assign pma_checker__entries_T_109 = pma_checker__entries_WIRE_9[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_sr = pma_checker__entries_T_109; // @[TLB.scala:170:77]
assign pma_checker__entries_T_110 = pma_checker__entries_WIRE_9[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_sx = pma_checker__entries_T_110; // @[TLB.scala:170:77]
assign pma_checker__entries_T_111 = pma_checker__entries_WIRE_9[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_sw = pma_checker__entries_T_111; // @[TLB.scala:170:77]
assign pma_checker__entries_T_112 = pma_checker__entries_WIRE_9[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_gf = pma_checker__entries_T_112; // @[TLB.scala:170:77]
assign pma_checker__entries_T_113 = pma_checker__entries_WIRE_9[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_pf = pma_checker__entries_T_113; // @[TLB.scala:170:77]
assign pma_checker__entries_T_114 = pma_checker__entries_WIRE_9[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_ae_stage2 = pma_checker__entries_T_114; // @[TLB.scala:170:77]
assign pma_checker__entries_T_115 = pma_checker__entries_WIRE_9[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_ae_final = pma_checker__entries_T_115; // @[TLB.scala:170:77]
assign pma_checker__entries_T_116 = pma_checker__entries_WIRE_9[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_ae_ptw = pma_checker__entries_T_116; // @[TLB.scala:170:77]
assign pma_checker__entries_T_117 = pma_checker__entries_WIRE_9[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_g = pma_checker__entries_T_117; // @[TLB.scala:170:77]
assign pma_checker__entries_T_118 = pma_checker__entries_WIRE_9[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_8_u = pma_checker__entries_T_118; // @[TLB.scala:170:77]
assign pma_checker__entries_T_119 = pma_checker__entries_WIRE_9[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_8_ppn = pma_checker__entries_T_119; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_143; // @[TLB.scala:170:77]
wire pma_checker__entries_T_142; // @[TLB.scala:170:77]
wire pma_checker__entries_T_141; // @[TLB.scala:170:77]
wire pma_checker__entries_T_140; // @[TLB.scala:170:77]
wire pma_checker__entries_T_139; // @[TLB.scala:170:77]
wire pma_checker__entries_T_138; // @[TLB.scala:170:77]
wire pma_checker__entries_T_137; // @[TLB.scala:170:77]
wire pma_checker__entries_T_136; // @[TLB.scala:170:77]
wire pma_checker__entries_T_135; // @[TLB.scala:170:77]
wire pma_checker__entries_T_134; // @[TLB.scala:170:77]
wire pma_checker__entries_T_133; // @[TLB.scala:170:77]
wire pma_checker__entries_T_132; // @[TLB.scala:170:77]
wire pma_checker__entries_T_131; // @[TLB.scala:170:77]
wire pma_checker__entries_T_130; // @[TLB.scala:170:77]
wire pma_checker__entries_T_129; // @[TLB.scala:170:77]
wire pma_checker__entries_T_128; // @[TLB.scala:170:77]
wire pma_checker__entries_T_127; // @[TLB.scala:170:77]
wire pma_checker__entries_T_126; // @[TLB.scala:170:77]
wire pma_checker__entries_T_125; // @[TLB.scala:170:77]
wire pma_checker__entries_T_124; // @[TLB.scala:170:77]
wire pma_checker__entries_T_123; // @[TLB.scala:170:77]
wire pma_checker__entries_T_122; // @[TLB.scala:170:77]
wire pma_checker__entries_T_121; // @[TLB.scala:170:77]
assign pma_checker__entries_T_121 = pma_checker__entries_WIRE_11[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_fragmented_superpage = pma_checker__entries_T_121; // @[TLB.scala:170:77]
assign pma_checker__entries_T_122 = pma_checker__entries_WIRE_11[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_c = pma_checker__entries_T_122; // @[TLB.scala:170:77]
assign pma_checker__entries_T_123 = pma_checker__entries_WIRE_11[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_eff = pma_checker__entries_T_123; // @[TLB.scala:170:77]
assign pma_checker__entries_T_124 = pma_checker__entries_WIRE_11[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_paa = pma_checker__entries_T_124; // @[TLB.scala:170:77]
assign pma_checker__entries_T_125 = pma_checker__entries_WIRE_11[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_pal = pma_checker__entries_T_125; // @[TLB.scala:170:77]
assign pma_checker__entries_T_126 = pma_checker__entries_WIRE_11[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_ppp = pma_checker__entries_T_126; // @[TLB.scala:170:77]
assign pma_checker__entries_T_127 = pma_checker__entries_WIRE_11[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_pr = pma_checker__entries_T_127; // @[TLB.scala:170:77]
assign pma_checker__entries_T_128 = pma_checker__entries_WIRE_11[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_px = pma_checker__entries_T_128; // @[TLB.scala:170:77]
assign pma_checker__entries_T_129 = pma_checker__entries_WIRE_11[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_pw = pma_checker__entries_T_129; // @[TLB.scala:170:77]
assign pma_checker__entries_T_130 = pma_checker__entries_WIRE_11[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_hr = pma_checker__entries_T_130; // @[TLB.scala:170:77]
assign pma_checker__entries_T_131 = pma_checker__entries_WIRE_11[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_hx = pma_checker__entries_T_131; // @[TLB.scala:170:77]
assign pma_checker__entries_T_132 = pma_checker__entries_WIRE_11[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_hw = pma_checker__entries_T_132; // @[TLB.scala:170:77]
assign pma_checker__entries_T_133 = pma_checker__entries_WIRE_11[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_sr = pma_checker__entries_T_133; // @[TLB.scala:170:77]
assign pma_checker__entries_T_134 = pma_checker__entries_WIRE_11[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_sx = pma_checker__entries_T_134; // @[TLB.scala:170:77]
assign pma_checker__entries_T_135 = pma_checker__entries_WIRE_11[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_sw = pma_checker__entries_T_135; // @[TLB.scala:170:77]
assign pma_checker__entries_T_136 = pma_checker__entries_WIRE_11[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_gf = pma_checker__entries_T_136; // @[TLB.scala:170:77]
assign pma_checker__entries_T_137 = pma_checker__entries_WIRE_11[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_pf = pma_checker__entries_T_137; // @[TLB.scala:170:77]
assign pma_checker__entries_T_138 = pma_checker__entries_WIRE_11[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_ae_stage2 = pma_checker__entries_T_138; // @[TLB.scala:170:77]
assign pma_checker__entries_T_139 = pma_checker__entries_WIRE_11[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_ae_final = pma_checker__entries_T_139; // @[TLB.scala:170:77]
assign pma_checker__entries_T_140 = pma_checker__entries_WIRE_11[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_ae_ptw = pma_checker__entries_T_140; // @[TLB.scala:170:77]
assign pma_checker__entries_T_141 = pma_checker__entries_WIRE_11[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_g = pma_checker__entries_T_141; // @[TLB.scala:170:77]
assign pma_checker__entries_T_142 = pma_checker__entries_WIRE_11[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_10_u = pma_checker__entries_T_142; // @[TLB.scala:170:77]
assign pma_checker__entries_T_143 = pma_checker__entries_WIRE_11[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_10_ppn = pma_checker__entries_T_143; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_167; // @[TLB.scala:170:77]
wire pma_checker__entries_T_166; // @[TLB.scala:170:77]
wire pma_checker__entries_T_165; // @[TLB.scala:170:77]
wire pma_checker__entries_T_164; // @[TLB.scala:170:77]
wire pma_checker__entries_T_163; // @[TLB.scala:170:77]
wire pma_checker__entries_T_162; // @[TLB.scala:170:77]
wire pma_checker__entries_T_161; // @[TLB.scala:170:77]
wire pma_checker__entries_T_160; // @[TLB.scala:170:77]
wire pma_checker__entries_T_159; // @[TLB.scala:170:77]
wire pma_checker__entries_T_158; // @[TLB.scala:170:77]
wire pma_checker__entries_T_157; // @[TLB.scala:170:77]
wire pma_checker__entries_T_156; // @[TLB.scala:170:77]
wire pma_checker__entries_T_155; // @[TLB.scala:170:77]
wire pma_checker__entries_T_154; // @[TLB.scala:170:77]
wire pma_checker__entries_T_153; // @[TLB.scala:170:77]
wire pma_checker__entries_T_152; // @[TLB.scala:170:77]
wire pma_checker__entries_T_151; // @[TLB.scala:170:77]
wire pma_checker__entries_T_150; // @[TLB.scala:170:77]
wire pma_checker__entries_T_149; // @[TLB.scala:170:77]
wire pma_checker__entries_T_148; // @[TLB.scala:170:77]
wire pma_checker__entries_T_147; // @[TLB.scala:170:77]
wire pma_checker__entries_T_146; // @[TLB.scala:170:77]
wire pma_checker__entries_T_145; // @[TLB.scala:170:77]
assign pma_checker__entries_T_145 = pma_checker__entries_WIRE_13[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_fragmented_superpage = pma_checker__entries_T_145; // @[TLB.scala:170:77]
assign pma_checker__entries_T_146 = pma_checker__entries_WIRE_13[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_c = pma_checker__entries_T_146; // @[TLB.scala:170:77]
assign pma_checker__entries_T_147 = pma_checker__entries_WIRE_13[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_eff = pma_checker__entries_T_147; // @[TLB.scala:170:77]
assign pma_checker__entries_T_148 = pma_checker__entries_WIRE_13[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_paa = pma_checker__entries_T_148; // @[TLB.scala:170:77]
assign pma_checker__entries_T_149 = pma_checker__entries_WIRE_13[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_pal = pma_checker__entries_T_149; // @[TLB.scala:170:77]
assign pma_checker__entries_T_150 = pma_checker__entries_WIRE_13[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_ppp = pma_checker__entries_T_150; // @[TLB.scala:170:77]
assign pma_checker__entries_T_151 = pma_checker__entries_WIRE_13[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_pr = pma_checker__entries_T_151; // @[TLB.scala:170:77]
assign pma_checker__entries_T_152 = pma_checker__entries_WIRE_13[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_px = pma_checker__entries_T_152; // @[TLB.scala:170:77]
assign pma_checker__entries_T_153 = pma_checker__entries_WIRE_13[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_pw = pma_checker__entries_T_153; // @[TLB.scala:170:77]
assign pma_checker__entries_T_154 = pma_checker__entries_WIRE_13[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_hr = pma_checker__entries_T_154; // @[TLB.scala:170:77]
assign pma_checker__entries_T_155 = pma_checker__entries_WIRE_13[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_hx = pma_checker__entries_T_155; // @[TLB.scala:170:77]
assign pma_checker__entries_T_156 = pma_checker__entries_WIRE_13[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_hw = pma_checker__entries_T_156; // @[TLB.scala:170:77]
assign pma_checker__entries_T_157 = pma_checker__entries_WIRE_13[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_sr = pma_checker__entries_T_157; // @[TLB.scala:170:77]
assign pma_checker__entries_T_158 = pma_checker__entries_WIRE_13[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_sx = pma_checker__entries_T_158; // @[TLB.scala:170:77]
assign pma_checker__entries_T_159 = pma_checker__entries_WIRE_13[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_sw = pma_checker__entries_T_159; // @[TLB.scala:170:77]
assign pma_checker__entries_T_160 = pma_checker__entries_WIRE_13[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_gf = pma_checker__entries_T_160; // @[TLB.scala:170:77]
assign pma_checker__entries_T_161 = pma_checker__entries_WIRE_13[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_pf = pma_checker__entries_T_161; // @[TLB.scala:170:77]
assign pma_checker__entries_T_162 = pma_checker__entries_WIRE_13[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_ae_stage2 = pma_checker__entries_T_162; // @[TLB.scala:170:77]
assign pma_checker__entries_T_163 = pma_checker__entries_WIRE_13[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_ae_final = pma_checker__entries_T_163; // @[TLB.scala:170:77]
assign pma_checker__entries_T_164 = pma_checker__entries_WIRE_13[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_ae_ptw = pma_checker__entries_T_164; // @[TLB.scala:170:77]
assign pma_checker__entries_T_165 = pma_checker__entries_WIRE_13[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_g = pma_checker__entries_T_165; // @[TLB.scala:170:77]
assign pma_checker__entries_T_166 = pma_checker__entries_WIRE_13[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_12_u = pma_checker__entries_T_166; // @[TLB.scala:170:77]
assign pma_checker__entries_T_167 = pma_checker__entries_WIRE_13[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_12_ppn = pma_checker__entries_T_167; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_191; // @[TLB.scala:170:77]
wire pma_checker__entries_T_190; // @[TLB.scala:170:77]
wire pma_checker__entries_T_189; // @[TLB.scala:170:77]
wire pma_checker__entries_T_188; // @[TLB.scala:170:77]
wire pma_checker__entries_T_187; // @[TLB.scala:170:77]
wire pma_checker__entries_T_186; // @[TLB.scala:170:77]
wire pma_checker__entries_T_185; // @[TLB.scala:170:77]
wire pma_checker__entries_T_184; // @[TLB.scala:170:77]
wire pma_checker__entries_T_183; // @[TLB.scala:170:77]
wire pma_checker__entries_T_182; // @[TLB.scala:170:77]
wire pma_checker__entries_T_181; // @[TLB.scala:170:77]
wire pma_checker__entries_T_180; // @[TLB.scala:170:77]
wire pma_checker__entries_T_179; // @[TLB.scala:170:77]
wire pma_checker__entries_T_178; // @[TLB.scala:170:77]
wire pma_checker__entries_T_177; // @[TLB.scala:170:77]
wire pma_checker__entries_T_176; // @[TLB.scala:170:77]
wire pma_checker__entries_T_175; // @[TLB.scala:170:77]
wire pma_checker__entries_T_174; // @[TLB.scala:170:77]
wire pma_checker__entries_T_173; // @[TLB.scala:170:77]
wire pma_checker__entries_T_172; // @[TLB.scala:170:77]
wire pma_checker__entries_T_171; // @[TLB.scala:170:77]
wire pma_checker__entries_T_170; // @[TLB.scala:170:77]
wire pma_checker__entries_T_169; // @[TLB.scala:170:77]
assign pma_checker__entries_T_169 = pma_checker__entries_WIRE_15[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_fragmented_superpage = pma_checker__entries_T_169; // @[TLB.scala:170:77]
assign pma_checker__entries_T_170 = pma_checker__entries_WIRE_15[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_c = pma_checker__entries_T_170; // @[TLB.scala:170:77]
assign pma_checker__entries_T_171 = pma_checker__entries_WIRE_15[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_eff = pma_checker__entries_T_171; // @[TLB.scala:170:77]
assign pma_checker__entries_T_172 = pma_checker__entries_WIRE_15[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_paa = pma_checker__entries_T_172; // @[TLB.scala:170:77]
assign pma_checker__entries_T_173 = pma_checker__entries_WIRE_15[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_pal = pma_checker__entries_T_173; // @[TLB.scala:170:77]
assign pma_checker__entries_T_174 = pma_checker__entries_WIRE_15[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_ppp = pma_checker__entries_T_174; // @[TLB.scala:170:77]
assign pma_checker__entries_T_175 = pma_checker__entries_WIRE_15[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_pr = pma_checker__entries_T_175; // @[TLB.scala:170:77]
assign pma_checker__entries_T_176 = pma_checker__entries_WIRE_15[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_px = pma_checker__entries_T_176; // @[TLB.scala:170:77]
assign pma_checker__entries_T_177 = pma_checker__entries_WIRE_15[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_pw = pma_checker__entries_T_177; // @[TLB.scala:170:77]
assign pma_checker__entries_T_178 = pma_checker__entries_WIRE_15[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_hr = pma_checker__entries_T_178; // @[TLB.scala:170:77]
assign pma_checker__entries_T_179 = pma_checker__entries_WIRE_15[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_hx = pma_checker__entries_T_179; // @[TLB.scala:170:77]
assign pma_checker__entries_T_180 = pma_checker__entries_WIRE_15[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_hw = pma_checker__entries_T_180; // @[TLB.scala:170:77]
assign pma_checker__entries_T_181 = pma_checker__entries_WIRE_15[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_sr = pma_checker__entries_T_181; // @[TLB.scala:170:77]
assign pma_checker__entries_T_182 = pma_checker__entries_WIRE_15[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_sx = pma_checker__entries_T_182; // @[TLB.scala:170:77]
assign pma_checker__entries_T_183 = pma_checker__entries_WIRE_15[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_sw = pma_checker__entries_T_183; // @[TLB.scala:170:77]
assign pma_checker__entries_T_184 = pma_checker__entries_WIRE_15[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_gf = pma_checker__entries_T_184; // @[TLB.scala:170:77]
assign pma_checker__entries_T_185 = pma_checker__entries_WIRE_15[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_pf = pma_checker__entries_T_185; // @[TLB.scala:170:77]
assign pma_checker__entries_T_186 = pma_checker__entries_WIRE_15[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_ae_stage2 = pma_checker__entries_T_186; // @[TLB.scala:170:77]
assign pma_checker__entries_T_187 = pma_checker__entries_WIRE_15[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_ae_final = pma_checker__entries_T_187; // @[TLB.scala:170:77]
assign pma_checker__entries_T_188 = pma_checker__entries_WIRE_15[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_ae_ptw = pma_checker__entries_T_188; // @[TLB.scala:170:77]
assign pma_checker__entries_T_189 = pma_checker__entries_WIRE_15[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_g = pma_checker__entries_T_189; // @[TLB.scala:170:77]
assign pma_checker__entries_T_190 = pma_checker__entries_WIRE_15[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_14_u = pma_checker__entries_T_190; // @[TLB.scala:170:77]
assign pma_checker__entries_T_191 = pma_checker__entries_WIRE_15[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_14_ppn = pma_checker__entries_T_191; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_214; // @[TLB.scala:170:77]
wire pma_checker__entries_T_213; // @[TLB.scala:170:77]
wire pma_checker__entries_T_212; // @[TLB.scala:170:77]
wire pma_checker__entries_T_211; // @[TLB.scala:170:77]
wire pma_checker__entries_T_210; // @[TLB.scala:170:77]
wire pma_checker__entries_T_209; // @[TLB.scala:170:77]
wire pma_checker__entries_T_208; // @[TLB.scala:170:77]
wire pma_checker__entries_T_207; // @[TLB.scala:170:77]
wire pma_checker__entries_T_206; // @[TLB.scala:170:77]
wire pma_checker__entries_T_205; // @[TLB.scala:170:77]
wire pma_checker__entries_T_204; // @[TLB.scala:170:77]
wire pma_checker__entries_T_203; // @[TLB.scala:170:77]
wire pma_checker__entries_T_202; // @[TLB.scala:170:77]
wire pma_checker__entries_T_201; // @[TLB.scala:170:77]
wire pma_checker__entries_T_200; // @[TLB.scala:170:77]
wire pma_checker__entries_T_199; // @[TLB.scala:170:77]
wire pma_checker__entries_T_198; // @[TLB.scala:170:77]
wire pma_checker__entries_T_197; // @[TLB.scala:170:77]
wire pma_checker__entries_T_196; // @[TLB.scala:170:77]
wire pma_checker__entries_T_195; // @[TLB.scala:170:77]
wire pma_checker__entries_T_194; // @[TLB.scala:170:77]
wire pma_checker__entries_T_193; // @[TLB.scala:170:77]
wire pma_checker__entries_T_192; // @[TLB.scala:170:77]
assign pma_checker__entries_T_192 = pma_checker__entries_WIRE_17[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_fragmented_superpage = pma_checker__entries_T_192; // @[TLB.scala:170:77]
assign pma_checker__entries_T_193 = pma_checker__entries_WIRE_17[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_c = pma_checker__entries_T_193; // @[TLB.scala:170:77]
assign pma_checker__entries_T_194 = pma_checker__entries_WIRE_17[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_eff = pma_checker__entries_T_194; // @[TLB.scala:170:77]
assign pma_checker__entries_T_195 = pma_checker__entries_WIRE_17[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_paa = pma_checker__entries_T_195; // @[TLB.scala:170:77]
assign pma_checker__entries_T_196 = pma_checker__entries_WIRE_17[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_pal = pma_checker__entries_T_196; // @[TLB.scala:170:77]
assign pma_checker__entries_T_197 = pma_checker__entries_WIRE_17[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_ppp = pma_checker__entries_T_197; // @[TLB.scala:170:77]
assign pma_checker__entries_T_198 = pma_checker__entries_WIRE_17[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_pr = pma_checker__entries_T_198; // @[TLB.scala:170:77]
assign pma_checker__entries_T_199 = pma_checker__entries_WIRE_17[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_px = pma_checker__entries_T_199; // @[TLB.scala:170:77]
assign pma_checker__entries_T_200 = pma_checker__entries_WIRE_17[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_pw = pma_checker__entries_T_200; // @[TLB.scala:170:77]
assign pma_checker__entries_T_201 = pma_checker__entries_WIRE_17[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_hr = pma_checker__entries_T_201; // @[TLB.scala:170:77]
assign pma_checker__entries_T_202 = pma_checker__entries_WIRE_17[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_hx = pma_checker__entries_T_202; // @[TLB.scala:170:77]
assign pma_checker__entries_T_203 = pma_checker__entries_WIRE_17[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_hw = pma_checker__entries_T_203; // @[TLB.scala:170:77]
assign pma_checker__entries_T_204 = pma_checker__entries_WIRE_17[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_sr = pma_checker__entries_T_204; // @[TLB.scala:170:77]
assign pma_checker__entries_T_205 = pma_checker__entries_WIRE_17[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_sx = pma_checker__entries_T_205; // @[TLB.scala:170:77]
assign pma_checker__entries_T_206 = pma_checker__entries_WIRE_17[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_sw = pma_checker__entries_T_206; // @[TLB.scala:170:77]
assign pma_checker__entries_T_207 = pma_checker__entries_WIRE_17[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_gf = pma_checker__entries_T_207; // @[TLB.scala:170:77]
assign pma_checker__entries_T_208 = pma_checker__entries_WIRE_17[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_pf = pma_checker__entries_T_208; // @[TLB.scala:170:77]
assign pma_checker__entries_T_209 = pma_checker__entries_WIRE_17[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_ae_stage2 = pma_checker__entries_T_209; // @[TLB.scala:170:77]
assign pma_checker__entries_T_210 = pma_checker__entries_WIRE_17[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_ae_final = pma_checker__entries_T_210; // @[TLB.scala:170:77]
assign pma_checker__entries_T_211 = pma_checker__entries_WIRE_17[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_ae_ptw = pma_checker__entries_T_211; // @[TLB.scala:170:77]
assign pma_checker__entries_T_212 = pma_checker__entries_WIRE_17[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_g = pma_checker__entries_T_212; // @[TLB.scala:170:77]
assign pma_checker__entries_T_213 = pma_checker__entries_WIRE_17[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_16_u = pma_checker__entries_T_213; // @[TLB.scala:170:77]
assign pma_checker__entries_T_214 = pma_checker__entries_WIRE_17[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_16_ppn = pma_checker__entries_T_214; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_237; // @[TLB.scala:170:77]
wire pma_checker__entries_T_236; // @[TLB.scala:170:77]
wire pma_checker__entries_T_235; // @[TLB.scala:170:77]
wire pma_checker__entries_T_234; // @[TLB.scala:170:77]
wire pma_checker__entries_T_233; // @[TLB.scala:170:77]
wire pma_checker__entries_T_232; // @[TLB.scala:170:77]
wire pma_checker__entries_T_231; // @[TLB.scala:170:77]
wire pma_checker__entries_T_230; // @[TLB.scala:170:77]
wire pma_checker__entries_T_229; // @[TLB.scala:170:77]
wire pma_checker__entries_T_228; // @[TLB.scala:170:77]
wire pma_checker__entries_T_227; // @[TLB.scala:170:77]
wire pma_checker__entries_T_226; // @[TLB.scala:170:77]
wire pma_checker__entries_T_225; // @[TLB.scala:170:77]
wire pma_checker__entries_T_224; // @[TLB.scala:170:77]
wire pma_checker__entries_T_223; // @[TLB.scala:170:77]
wire pma_checker__entries_T_222; // @[TLB.scala:170:77]
wire pma_checker__entries_T_221; // @[TLB.scala:170:77]
wire pma_checker__entries_T_220; // @[TLB.scala:170:77]
wire pma_checker__entries_T_219; // @[TLB.scala:170:77]
wire pma_checker__entries_T_218; // @[TLB.scala:170:77]
wire pma_checker__entries_T_217; // @[TLB.scala:170:77]
wire pma_checker__entries_T_216; // @[TLB.scala:170:77]
wire pma_checker__entries_T_215; // @[TLB.scala:170:77]
assign pma_checker__entries_T_215 = pma_checker__entries_WIRE_19[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_fragmented_superpage = pma_checker__entries_T_215; // @[TLB.scala:170:77]
assign pma_checker__entries_T_216 = pma_checker__entries_WIRE_19[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_c = pma_checker__entries_T_216; // @[TLB.scala:170:77]
assign pma_checker__entries_T_217 = pma_checker__entries_WIRE_19[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_eff = pma_checker__entries_T_217; // @[TLB.scala:170:77]
assign pma_checker__entries_T_218 = pma_checker__entries_WIRE_19[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_paa = pma_checker__entries_T_218; // @[TLB.scala:170:77]
assign pma_checker__entries_T_219 = pma_checker__entries_WIRE_19[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_pal = pma_checker__entries_T_219; // @[TLB.scala:170:77]
assign pma_checker__entries_T_220 = pma_checker__entries_WIRE_19[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_ppp = pma_checker__entries_T_220; // @[TLB.scala:170:77]
assign pma_checker__entries_T_221 = pma_checker__entries_WIRE_19[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_pr = pma_checker__entries_T_221; // @[TLB.scala:170:77]
assign pma_checker__entries_T_222 = pma_checker__entries_WIRE_19[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_px = pma_checker__entries_T_222; // @[TLB.scala:170:77]
assign pma_checker__entries_T_223 = pma_checker__entries_WIRE_19[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_pw = pma_checker__entries_T_223; // @[TLB.scala:170:77]
assign pma_checker__entries_T_224 = pma_checker__entries_WIRE_19[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_hr = pma_checker__entries_T_224; // @[TLB.scala:170:77]
assign pma_checker__entries_T_225 = pma_checker__entries_WIRE_19[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_hx = pma_checker__entries_T_225; // @[TLB.scala:170:77]
assign pma_checker__entries_T_226 = pma_checker__entries_WIRE_19[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_hw = pma_checker__entries_T_226; // @[TLB.scala:170:77]
assign pma_checker__entries_T_227 = pma_checker__entries_WIRE_19[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_sr = pma_checker__entries_T_227; // @[TLB.scala:170:77]
assign pma_checker__entries_T_228 = pma_checker__entries_WIRE_19[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_sx = pma_checker__entries_T_228; // @[TLB.scala:170:77]
assign pma_checker__entries_T_229 = pma_checker__entries_WIRE_19[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_sw = pma_checker__entries_T_229; // @[TLB.scala:170:77]
assign pma_checker__entries_T_230 = pma_checker__entries_WIRE_19[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_gf = pma_checker__entries_T_230; // @[TLB.scala:170:77]
assign pma_checker__entries_T_231 = pma_checker__entries_WIRE_19[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_pf = pma_checker__entries_T_231; // @[TLB.scala:170:77]
assign pma_checker__entries_T_232 = pma_checker__entries_WIRE_19[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_ae_stage2 = pma_checker__entries_T_232; // @[TLB.scala:170:77]
assign pma_checker__entries_T_233 = pma_checker__entries_WIRE_19[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_ae_final = pma_checker__entries_T_233; // @[TLB.scala:170:77]
assign pma_checker__entries_T_234 = pma_checker__entries_WIRE_19[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_ae_ptw = pma_checker__entries_T_234; // @[TLB.scala:170:77]
assign pma_checker__entries_T_235 = pma_checker__entries_WIRE_19[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_g = pma_checker__entries_T_235; // @[TLB.scala:170:77]
assign pma_checker__entries_T_236 = pma_checker__entries_WIRE_19[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_18_u = pma_checker__entries_T_236; // @[TLB.scala:170:77]
assign pma_checker__entries_T_237 = pma_checker__entries_WIRE_19[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_18_ppn = pma_checker__entries_T_237; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_260; // @[TLB.scala:170:77]
wire pma_checker__entries_T_259; // @[TLB.scala:170:77]
wire pma_checker__entries_T_258; // @[TLB.scala:170:77]
wire pma_checker__entries_T_257; // @[TLB.scala:170:77]
wire pma_checker__entries_T_256; // @[TLB.scala:170:77]
wire pma_checker__entries_T_255; // @[TLB.scala:170:77]
wire pma_checker__entries_T_254; // @[TLB.scala:170:77]
wire pma_checker__entries_T_253; // @[TLB.scala:170:77]
wire pma_checker__entries_T_252; // @[TLB.scala:170:77]
wire pma_checker__entries_T_251; // @[TLB.scala:170:77]
wire pma_checker__entries_T_250; // @[TLB.scala:170:77]
wire pma_checker__entries_T_249; // @[TLB.scala:170:77]
wire pma_checker__entries_T_248; // @[TLB.scala:170:77]
wire pma_checker__entries_T_247; // @[TLB.scala:170:77]
wire pma_checker__entries_T_246; // @[TLB.scala:170:77]
wire pma_checker__entries_T_245; // @[TLB.scala:170:77]
wire pma_checker__entries_T_244; // @[TLB.scala:170:77]
wire pma_checker__entries_T_243; // @[TLB.scala:170:77]
wire pma_checker__entries_T_242; // @[TLB.scala:170:77]
wire pma_checker__entries_T_241; // @[TLB.scala:170:77]
wire pma_checker__entries_T_240; // @[TLB.scala:170:77]
wire pma_checker__entries_T_239; // @[TLB.scala:170:77]
wire pma_checker__entries_T_238; // @[TLB.scala:170:77]
assign pma_checker__entries_T_238 = pma_checker__entries_WIRE_21[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_fragmented_superpage = pma_checker__entries_T_238; // @[TLB.scala:170:77]
assign pma_checker__entries_T_239 = pma_checker__entries_WIRE_21[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_c = pma_checker__entries_T_239; // @[TLB.scala:170:77]
assign pma_checker__entries_T_240 = pma_checker__entries_WIRE_21[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_eff = pma_checker__entries_T_240; // @[TLB.scala:170:77]
assign pma_checker__entries_T_241 = pma_checker__entries_WIRE_21[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_paa = pma_checker__entries_T_241; // @[TLB.scala:170:77]
assign pma_checker__entries_T_242 = pma_checker__entries_WIRE_21[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_pal = pma_checker__entries_T_242; // @[TLB.scala:170:77]
assign pma_checker__entries_T_243 = pma_checker__entries_WIRE_21[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_ppp = pma_checker__entries_T_243; // @[TLB.scala:170:77]
assign pma_checker__entries_T_244 = pma_checker__entries_WIRE_21[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_pr = pma_checker__entries_T_244; // @[TLB.scala:170:77]
assign pma_checker__entries_T_245 = pma_checker__entries_WIRE_21[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_px = pma_checker__entries_T_245; // @[TLB.scala:170:77]
assign pma_checker__entries_T_246 = pma_checker__entries_WIRE_21[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_pw = pma_checker__entries_T_246; // @[TLB.scala:170:77]
assign pma_checker__entries_T_247 = pma_checker__entries_WIRE_21[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_hr = pma_checker__entries_T_247; // @[TLB.scala:170:77]
assign pma_checker__entries_T_248 = pma_checker__entries_WIRE_21[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_hx = pma_checker__entries_T_248; // @[TLB.scala:170:77]
assign pma_checker__entries_T_249 = pma_checker__entries_WIRE_21[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_hw = pma_checker__entries_T_249; // @[TLB.scala:170:77]
assign pma_checker__entries_T_250 = pma_checker__entries_WIRE_21[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_sr = pma_checker__entries_T_250; // @[TLB.scala:170:77]
assign pma_checker__entries_T_251 = pma_checker__entries_WIRE_21[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_sx = pma_checker__entries_T_251; // @[TLB.scala:170:77]
assign pma_checker__entries_T_252 = pma_checker__entries_WIRE_21[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_sw = pma_checker__entries_T_252; // @[TLB.scala:170:77]
assign pma_checker__entries_T_253 = pma_checker__entries_WIRE_21[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_gf = pma_checker__entries_T_253; // @[TLB.scala:170:77]
assign pma_checker__entries_T_254 = pma_checker__entries_WIRE_21[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_pf = pma_checker__entries_T_254; // @[TLB.scala:170:77]
assign pma_checker__entries_T_255 = pma_checker__entries_WIRE_21[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_ae_stage2 = pma_checker__entries_T_255; // @[TLB.scala:170:77]
assign pma_checker__entries_T_256 = pma_checker__entries_WIRE_21[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_ae_final = pma_checker__entries_T_256; // @[TLB.scala:170:77]
assign pma_checker__entries_T_257 = pma_checker__entries_WIRE_21[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_ae_ptw = pma_checker__entries_T_257; // @[TLB.scala:170:77]
assign pma_checker__entries_T_258 = pma_checker__entries_WIRE_21[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_g = pma_checker__entries_T_258; // @[TLB.scala:170:77]
assign pma_checker__entries_T_259 = pma_checker__entries_WIRE_21[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_20_u = pma_checker__entries_T_259; // @[TLB.scala:170:77]
assign pma_checker__entries_T_260 = pma_checker__entries_WIRE_21[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_20_ppn = pma_checker__entries_T_260; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_283; // @[TLB.scala:170:77]
wire pma_checker__entries_T_282; // @[TLB.scala:170:77]
wire pma_checker__entries_T_281; // @[TLB.scala:170:77]
wire pma_checker__entries_T_280; // @[TLB.scala:170:77]
wire pma_checker__entries_T_279; // @[TLB.scala:170:77]
wire pma_checker__entries_T_278; // @[TLB.scala:170:77]
wire pma_checker__entries_T_277; // @[TLB.scala:170:77]
wire pma_checker__entries_T_276; // @[TLB.scala:170:77]
wire pma_checker__entries_T_275; // @[TLB.scala:170:77]
wire pma_checker__entries_T_274; // @[TLB.scala:170:77]
wire pma_checker__entries_T_273; // @[TLB.scala:170:77]
wire pma_checker__entries_T_272; // @[TLB.scala:170:77]
wire pma_checker__entries_T_271; // @[TLB.scala:170:77]
wire pma_checker__entries_T_270; // @[TLB.scala:170:77]
wire pma_checker__entries_T_269; // @[TLB.scala:170:77]
wire pma_checker__entries_T_268; // @[TLB.scala:170:77]
wire pma_checker__entries_T_267; // @[TLB.scala:170:77]
wire pma_checker__entries_T_266; // @[TLB.scala:170:77]
wire pma_checker__entries_T_265; // @[TLB.scala:170:77]
wire pma_checker__entries_T_264; // @[TLB.scala:170:77]
wire pma_checker__entries_T_263; // @[TLB.scala:170:77]
wire pma_checker__entries_T_262; // @[TLB.scala:170:77]
wire pma_checker__entries_T_261; // @[TLB.scala:170:77]
assign pma_checker__entries_T_261 = pma_checker__entries_WIRE_23[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_fragmented_superpage = pma_checker__entries_T_261; // @[TLB.scala:170:77]
assign pma_checker__entries_T_262 = pma_checker__entries_WIRE_23[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_c = pma_checker__entries_T_262; // @[TLB.scala:170:77]
assign pma_checker__entries_T_263 = pma_checker__entries_WIRE_23[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_eff = pma_checker__entries_T_263; // @[TLB.scala:170:77]
assign pma_checker__entries_T_264 = pma_checker__entries_WIRE_23[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_paa = pma_checker__entries_T_264; // @[TLB.scala:170:77]
assign pma_checker__entries_T_265 = pma_checker__entries_WIRE_23[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_pal = pma_checker__entries_T_265; // @[TLB.scala:170:77]
assign pma_checker__entries_T_266 = pma_checker__entries_WIRE_23[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_ppp = pma_checker__entries_T_266; // @[TLB.scala:170:77]
assign pma_checker__entries_T_267 = pma_checker__entries_WIRE_23[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_pr = pma_checker__entries_T_267; // @[TLB.scala:170:77]
assign pma_checker__entries_T_268 = pma_checker__entries_WIRE_23[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_px = pma_checker__entries_T_268; // @[TLB.scala:170:77]
assign pma_checker__entries_T_269 = pma_checker__entries_WIRE_23[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_pw = pma_checker__entries_T_269; // @[TLB.scala:170:77]
assign pma_checker__entries_T_270 = pma_checker__entries_WIRE_23[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_hr = pma_checker__entries_T_270; // @[TLB.scala:170:77]
assign pma_checker__entries_T_271 = pma_checker__entries_WIRE_23[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_hx = pma_checker__entries_T_271; // @[TLB.scala:170:77]
assign pma_checker__entries_T_272 = pma_checker__entries_WIRE_23[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_hw = pma_checker__entries_T_272; // @[TLB.scala:170:77]
assign pma_checker__entries_T_273 = pma_checker__entries_WIRE_23[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_sr = pma_checker__entries_T_273; // @[TLB.scala:170:77]
assign pma_checker__entries_T_274 = pma_checker__entries_WIRE_23[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_sx = pma_checker__entries_T_274; // @[TLB.scala:170:77]
assign pma_checker__entries_T_275 = pma_checker__entries_WIRE_23[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_sw = pma_checker__entries_T_275; // @[TLB.scala:170:77]
assign pma_checker__entries_T_276 = pma_checker__entries_WIRE_23[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_gf = pma_checker__entries_T_276; // @[TLB.scala:170:77]
assign pma_checker__entries_T_277 = pma_checker__entries_WIRE_23[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_pf = pma_checker__entries_T_277; // @[TLB.scala:170:77]
assign pma_checker__entries_T_278 = pma_checker__entries_WIRE_23[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_ae_stage2 = pma_checker__entries_T_278; // @[TLB.scala:170:77]
assign pma_checker__entries_T_279 = pma_checker__entries_WIRE_23[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_ae_final = pma_checker__entries_T_279; // @[TLB.scala:170:77]
assign pma_checker__entries_T_280 = pma_checker__entries_WIRE_23[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_ae_ptw = pma_checker__entries_T_280; // @[TLB.scala:170:77]
assign pma_checker__entries_T_281 = pma_checker__entries_WIRE_23[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_g = pma_checker__entries_T_281; // @[TLB.scala:170:77]
assign pma_checker__entries_T_282 = pma_checker__entries_WIRE_23[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_22_u = pma_checker__entries_T_282; // @[TLB.scala:170:77]
assign pma_checker__entries_T_283 = pma_checker__entries_WIRE_23[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_22_ppn = pma_checker__entries_T_283; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_T_306; // @[TLB.scala:170:77]
wire pma_checker__entries_T_305; // @[TLB.scala:170:77]
wire pma_checker__entries_T_304; // @[TLB.scala:170:77]
wire pma_checker__entries_T_303; // @[TLB.scala:170:77]
wire pma_checker__entries_T_302; // @[TLB.scala:170:77]
wire pma_checker__entries_T_301; // @[TLB.scala:170:77]
wire pma_checker__entries_T_300; // @[TLB.scala:170:77]
wire pma_checker__entries_T_299; // @[TLB.scala:170:77]
wire pma_checker__entries_T_298; // @[TLB.scala:170:77]
wire pma_checker__entries_T_297; // @[TLB.scala:170:77]
wire pma_checker__entries_T_296; // @[TLB.scala:170:77]
wire pma_checker__entries_T_295; // @[TLB.scala:170:77]
wire pma_checker__entries_T_294; // @[TLB.scala:170:77]
wire pma_checker__entries_T_293; // @[TLB.scala:170:77]
wire pma_checker__entries_T_292; // @[TLB.scala:170:77]
wire pma_checker__entries_T_291; // @[TLB.scala:170:77]
wire pma_checker__entries_T_290; // @[TLB.scala:170:77]
wire pma_checker__entries_T_289; // @[TLB.scala:170:77]
wire pma_checker__entries_T_288; // @[TLB.scala:170:77]
wire pma_checker__entries_T_287; // @[TLB.scala:170:77]
wire pma_checker__entries_T_286; // @[TLB.scala:170:77]
wire pma_checker__entries_T_285; // @[TLB.scala:170:77]
wire pma_checker__entries_T_284; // @[TLB.scala:170:77]
assign pma_checker__entries_T_284 = pma_checker__entries_WIRE_25[0]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_fragmented_superpage = pma_checker__entries_T_284; // @[TLB.scala:170:77]
assign pma_checker__entries_T_285 = pma_checker__entries_WIRE_25[1]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_c = pma_checker__entries_T_285; // @[TLB.scala:170:77]
assign pma_checker__entries_T_286 = pma_checker__entries_WIRE_25[2]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_eff = pma_checker__entries_T_286; // @[TLB.scala:170:77]
assign pma_checker__entries_T_287 = pma_checker__entries_WIRE_25[3]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_paa = pma_checker__entries_T_287; // @[TLB.scala:170:77]
assign pma_checker__entries_T_288 = pma_checker__entries_WIRE_25[4]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_pal = pma_checker__entries_T_288; // @[TLB.scala:170:77]
assign pma_checker__entries_T_289 = pma_checker__entries_WIRE_25[5]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_ppp = pma_checker__entries_T_289; // @[TLB.scala:170:77]
assign pma_checker__entries_T_290 = pma_checker__entries_WIRE_25[6]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_pr = pma_checker__entries_T_290; // @[TLB.scala:170:77]
assign pma_checker__entries_T_291 = pma_checker__entries_WIRE_25[7]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_px = pma_checker__entries_T_291; // @[TLB.scala:170:77]
assign pma_checker__entries_T_292 = pma_checker__entries_WIRE_25[8]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_pw = pma_checker__entries_T_292; // @[TLB.scala:170:77]
assign pma_checker__entries_T_293 = pma_checker__entries_WIRE_25[9]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_hr = pma_checker__entries_T_293; // @[TLB.scala:170:77]
assign pma_checker__entries_T_294 = pma_checker__entries_WIRE_25[10]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_hx = pma_checker__entries_T_294; // @[TLB.scala:170:77]
assign pma_checker__entries_T_295 = pma_checker__entries_WIRE_25[11]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_hw = pma_checker__entries_T_295; // @[TLB.scala:170:77]
assign pma_checker__entries_T_296 = pma_checker__entries_WIRE_25[12]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_sr = pma_checker__entries_T_296; // @[TLB.scala:170:77]
assign pma_checker__entries_T_297 = pma_checker__entries_WIRE_25[13]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_sx = pma_checker__entries_T_297; // @[TLB.scala:170:77]
assign pma_checker__entries_T_298 = pma_checker__entries_WIRE_25[14]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_sw = pma_checker__entries_T_298; // @[TLB.scala:170:77]
assign pma_checker__entries_T_299 = pma_checker__entries_WIRE_25[15]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_gf = pma_checker__entries_T_299; // @[TLB.scala:170:77]
assign pma_checker__entries_T_300 = pma_checker__entries_WIRE_25[16]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_pf = pma_checker__entries_T_300; // @[TLB.scala:170:77]
assign pma_checker__entries_T_301 = pma_checker__entries_WIRE_25[17]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_ae_stage2 = pma_checker__entries_T_301; // @[TLB.scala:170:77]
assign pma_checker__entries_T_302 = pma_checker__entries_WIRE_25[18]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_ae_final = pma_checker__entries_T_302; // @[TLB.scala:170:77]
assign pma_checker__entries_T_303 = pma_checker__entries_WIRE_25[19]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_ae_ptw = pma_checker__entries_T_303; // @[TLB.scala:170:77]
assign pma_checker__entries_T_304 = pma_checker__entries_WIRE_25[20]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_g = pma_checker__entries_T_304; // @[TLB.scala:170:77]
assign pma_checker__entries_T_305 = pma_checker__entries_WIRE_25[21]; // @[TLB.scala:170:77]
wire pma_checker__entries_WIRE_24_u = pma_checker__entries_T_305; // @[TLB.scala:170:77]
assign pma_checker__entries_T_306 = pma_checker__entries_WIRE_25[41:22]; // @[TLB.scala:170:77]
wire [19:0] pma_checker__entries_WIRE_24_ppn = pma_checker__entries_T_306; // @[TLB.scala:170:77]
wire [19:0] pma_checker__ppn_T_1 = pma_checker_vpn[19:0]; // @[TLB.scala:335:30, :502:125]
wire [19:0] pma_checker__ppn_T_15 = pma_checker__ppn_T_1; // @[Mux.scala:30:73]
wire [19:0] pma_checker__ppn_T_28 = pma_checker__ppn_T_15; // @[Mux.scala:30:73]
wire [19:0] pma_checker_ppn = pma_checker__ppn_T_28; // @[Mux.scala:30:73]
wire [1:0] pma_checker_ptw_ae_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ae_ptw, _pma_checker_entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ptw_ae_array_lo_lo = {pma_checker_ptw_ae_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ptw_ae_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ae_ptw, _pma_checker_entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ptw_ae_array_lo_hi = {pma_checker_ptw_ae_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_ptw_ae_array_lo = {pma_checker_ptw_ae_array_lo_hi, pma_checker_ptw_ae_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_ptw_ae_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ae_ptw, _pma_checker_entries_barrier_7_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ptw_ae_array_hi_lo = {pma_checker_ptw_ae_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ptw_ae_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_ae_ptw, _pma_checker_entries_barrier_9_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ptw_ae_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_ae_ptw, _pma_checker_entries_barrier_11_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_ptw_ae_array_hi_hi = {pma_checker_ptw_ae_array_hi_hi_hi, pma_checker_ptw_ae_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_ptw_ae_array_hi = {pma_checker_ptw_ae_array_hi_hi, pma_checker_ptw_ae_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__ptw_ae_array_T = {pma_checker_ptw_ae_array_hi, pma_checker_ptw_ae_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker_ptw_ae_array = {1'h0, pma_checker__ptw_ae_array_T}; // @[package.scala:45:27]
wire [1:0] pma_checker_final_ae_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ae_final, _pma_checker_entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_final_ae_array_lo_lo = {pma_checker_final_ae_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_final_ae_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ae_final, _pma_checker_entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_final_ae_array_lo_hi = {pma_checker_final_ae_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_final_ae_array_lo = {pma_checker_final_ae_array_lo_hi, pma_checker_final_ae_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_final_ae_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ae_final, _pma_checker_entries_barrier_7_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_final_ae_array_hi_lo = {pma_checker_final_ae_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_final_ae_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_ae_final, _pma_checker_entries_barrier_9_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_final_ae_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_ae_final, _pma_checker_entries_barrier_11_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_final_ae_array_hi_hi = {pma_checker_final_ae_array_hi_hi_hi, pma_checker_final_ae_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_final_ae_array_hi = {pma_checker_final_ae_array_hi_hi, pma_checker_final_ae_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__final_ae_array_T = {pma_checker_final_ae_array_hi, pma_checker_final_ae_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker_final_ae_array = {1'h0, pma_checker__final_ae_array_T}; // @[package.scala:45:27]
wire [1:0] pma_checker_ptw_pf_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pf, _pma_checker_entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ptw_pf_array_lo_lo = {pma_checker_ptw_pf_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ptw_pf_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pf, _pma_checker_entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ptw_pf_array_lo_hi = {pma_checker_ptw_pf_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_ptw_pf_array_lo = {pma_checker_ptw_pf_array_lo_hi, pma_checker_ptw_pf_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_ptw_pf_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pf, _pma_checker_entries_barrier_7_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ptw_pf_array_hi_lo = {pma_checker_ptw_pf_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ptw_pf_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_pf, _pma_checker_entries_barrier_9_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ptw_pf_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_pf, _pma_checker_entries_barrier_11_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_ptw_pf_array_hi_hi = {pma_checker_ptw_pf_array_hi_hi_hi, pma_checker_ptw_pf_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_ptw_pf_array_hi = {pma_checker_ptw_pf_array_hi_hi, pma_checker_ptw_pf_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__ptw_pf_array_T = {pma_checker_ptw_pf_array_hi, pma_checker_ptw_pf_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker_ptw_pf_array = {1'h0, pma_checker__ptw_pf_array_T}; // @[package.scala:45:27]
wire [1:0] pma_checker_ptw_gf_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_gf, _pma_checker_entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ptw_gf_array_lo_lo = {pma_checker_ptw_gf_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ptw_gf_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_gf, _pma_checker_entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ptw_gf_array_lo_hi = {pma_checker_ptw_gf_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_ptw_gf_array_lo = {pma_checker_ptw_gf_array_lo_hi, pma_checker_ptw_gf_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_ptw_gf_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_gf, _pma_checker_entries_barrier_7_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ptw_gf_array_hi_lo = {pma_checker_ptw_gf_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ptw_gf_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_gf, _pma_checker_entries_barrier_9_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ptw_gf_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_gf, _pma_checker_entries_barrier_11_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_ptw_gf_array_hi_hi = {pma_checker_ptw_gf_array_hi_hi_hi, pma_checker_ptw_gf_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_ptw_gf_array_hi = {pma_checker_ptw_gf_array_hi_hi, pma_checker_ptw_gf_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__ptw_gf_array_T = {pma_checker_ptw_gf_array_hi, pma_checker_ptw_gf_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker_ptw_gf_array = {1'h0, pma_checker__ptw_gf_array_T}; // @[package.scala:45:27]
wire [13:0] pma_checker__gf_ld_array_T_3 = pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :600:82]
wire [13:0] pma_checker__gf_st_array_T_2 = pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :601:63]
wire [13:0] pma_checker__gf_inst_array_T_1 = pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :602:46]
wire pma_checker__priv_rw_ok_T = ~pma_checker_priv_s; // @[TLB.scala:370:20, :513:24]
wire pma_checker__priv_rw_ok_T_1 = pma_checker__priv_rw_ok_T; // @[TLB.scala:513:{24,32}]
wire [1:0] _GEN_6 = {_pma_checker_entries_barrier_2_io_y_u, _pma_checker_entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_priv_rw_ok_lo_lo_hi; // @[package.scala:45:27]
assign pma_checker_priv_rw_ok_lo_lo_hi = _GEN_6; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_rw_ok_lo_lo_hi_1; // @[package.scala:45:27]
assign pma_checker_priv_rw_ok_lo_lo_hi_1 = _GEN_6; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_x_ok_lo_lo_hi; // @[package.scala:45:27]
assign pma_checker_priv_x_ok_lo_lo_hi = _GEN_6; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_x_ok_lo_lo_hi_1; // @[package.scala:45:27]
assign pma_checker_priv_x_ok_lo_lo_hi_1 = _GEN_6; // @[package.scala:45:27]
wire [2:0] pma_checker_priv_rw_ok_lo_lo = {pma_checker_priv_rw_ok_lo_lo_hi, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_7 = {_pma_checker_entries_barrier_5_io_y_u, _pma_checker_entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_priv_rw_ok_lo_hi_hi; // @[package.scala:45:27]
assign pma_checker_priv_rw_ok_lo_hi_hi = _GEN_7; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_rw_ok_lo_hi_hi_1; // @[package.scala:45:27]
assign pma_checker_priv_rw_ok_lo_hi_hi_1 = _GEN_7; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_x_ok_lo_hi_hi; // @[package.scala:45:27]
assign pma_checker_priv_x_ok_lo_hi_hi = _GEN_7; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_x_ok_lo_hi_hi_1; // @[package.scala:45:27]
assign pma_checker_priv_x_ok_lo_hi_hi_1 = _GEN_7; // @[package.scala:45:27]
wire [2:0] pma_checker_priv_rw_ok_lo_hi = {pma_checker_priv_rw_ok_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_priv_rw_ok_lo = {pma_checker_priv_rw_ok_lo_hi, pma_checker_priv_rw_ok_lo_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_8 = {_pma_checker_entries_barrier_8_io_y_u, _pma_checker_entries_barrier_7_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_priv_rw_ok_hi_lo_hi; // @[package.scala:45:27]
assign pma_checker_priv_rw_ok_hi_lo_hi = _GEN_8; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_rw_ok_hi_lo_hi_1; // @[package.scala:45:27]
assign pma_checker_priv_rw_ok_hi_lo_hi_1 = _GEN_8; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_x_ok_hi_lo_hi; // @[package.scala:45:27]
assign pma_checker_priv_x_ok_hi_lo_hi = _GEN_8; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_x_ok_hi_lo_hi_1; // @[package.scala:45:27]
assign pma_checker_priv_x_ok_hi_lo_hi_1 = _GEN_8; // @[package.scala:45:27]
wire [2:0] pma_checker_priv_rw_ok_hi_lo = {pma_checker_priv_rw_ok_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_9 = {_pma_checker_entries_barrier_10_io_y_u, _pma_checker_entries_barrier_9_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_priv_rw_ok_hi_hi_lo; // @[package.scala:45:27]
assign pma_checker_priv_rw_ok_hi_hi_lo = _GEN_9; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_rw_ok_hi_hi_lo_1; // @[package.scala:45:27]
assign pma_checker_priv_rw_ok_hi_hi_lo_1 = _GEN_9; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_x_ok_hi_hi_lo; // @[package.scala:45:27]
assign pma_checker_priv_x_ok_hi_hi_lo = _GEN_9; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_x_ok_hi_hi_lo_1; // @[package.scala:45:27]
assign pma_checker_priv_x_ok_hi_hi_lo_1 = _GEN_9; // @[package.scala:45:27]
wire [1:0] _GEN_10 = {_pma_checker_entries_barrier_12_io_y_u, _pma_checker_entries_barrier_11_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_priv_rw_ok_hi_hi_hi; // @[package.scala:45:27]
assign pma_checker_priv_rw_ok_hi_hi_hi = _GEN_10; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_rw_ok_hi_hi_hi_1; // @[package.scala:45:27]
assign pma_checker_priv_rw_ok_hi_hi_hi_1 = _GEN_10; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_x_ok_hi_hi_hi; // @[package.scala:45:27]
assign pma_checker_priv_x_ok_hi_hi_hi = _GEN_10; // @[package.scala:45:27]
wire [1:0] pma_checker_priv_x_ok_hi_hi_hi_1; // @[package.scala:45:27]
assign pma_checker_priv_x_ok_hi_hi_hi_1 = _GEN_10; // @[package.scala:45:27]
wire [3:0] pma_checker_priv_rw_ok_hi_hi = {pma_checker_priv_rw_ok_hi_hi_hi, pma_checker_priv_rw_ok_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_priv_rw_ok_hi = {pma_checker_priv_rw_ok_hi_hi, pma_checker_priv_rw_ok_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__priv_rw_ok_T_2 = {pma_checker_priv_rw_ok_hi, pma_checker_priv_rw_ok_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__priv_rw_ok_T_3 = pma_checker__priv_rw_ok_T_1 ? pma_checker__priv_rw_ok_T_2 : 13'h0; // @[package.scala:45:27]
wire [2:0] pma_checker_priv_rw_ok_lo_lo_1 = {pma_checker_priv_rw_ok_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_priv_rw_ok_lo_hi_1 = {pma_checker_priv_rw_ok_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_priv_rw_ok_lo_1 = {pma_checker_priv_rw_ok_lo_hi_1, pma_checker_priv_rw_ok_lo_lo_1}; // @[package.scala:45:27]
wire [2:0] pma_checker_priv_rw_ok_hi_lo_1 = {pma_checker_priv_rw_ok_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_priv_rw_ok_hi_hi_1 = {pma_checker_priv_rw_ok_hi_hi_hi_1, pma_checker_priv_rw_ok_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] pma_checker_priv_rw_ok_hi_1 = {pma_checker_priv_rw_ok_hi_hi_1, pma_checker_priv_rw_ok_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] pma_checker__priv_rw_ok_T_4 = {pma_checker_priv_rw_ok_hi_1, pma_checker_priv_rw_ok_lo_1}; // @[package.scala:45:27]
wire [12:0] pma_checker__priv_rw_ok_T_5 = ~pma_checker__priv_rw_ok_T_4; // @[package.scala:45:27]
wire [12:0] pma_checker__priv_rw_ok_T_6 = pma_checker_priv_s ? pma_checker__priv_rw_ok_T_5 : 13'h0; // @[TLB.scala:370:20, :513:{75,84}]
wire [12:0] pma_checker_priv_rw_ok = pma_checker__priv_rw_ok_T_3 | pma_checker__priv_rw_ok_T_6; // @[TLB.scala:513:{23,70,75}]
wire [2:0] pma_checker_priv_x_ok_lo_lo = {pma_checker_priv_x_ok_lo_lo_hi, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_priv_x_ok_lo_hi = {pma_checker_priv_x_ok_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_priv_x_ok_lo = {pma_checker_priv_x_ok_lo_hi, pma_checker_priv_x_ok_lo_lo}; // @[package.scala:45:27]
wire [2:0] pma_checker_priv_x_ok_hi_lo = {pma_checker_priv_x_ok_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_priv_x_ok_hi_hi = {pma_checker_priv_x_ok_hi_hi_hi, pma_checker_priv_x_ok_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_priv_x_ok_hi = {pma_checker_priv_x_ok_hi_hi, pma_checker_priv_x_ok_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__priv_x_ok_T = {pma_checker_priv_x_ok_hi, pma_checker_priv_x_ok_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__priv_x_ok_T_1 = ~pma_checker__priv_x_ok_T; // @[package.scala:45:27]
wire [2:0] pma_checker_priv_x_ok_lo_lo_1 = {pma_checker_priv_x_ok_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_priv_x_ok_lo_hi_1 = {pma_checker_priv_x_ok_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_priv_x_ok_lo_1 = {pma_checker_priv_x_ok_lo_hi_1, pma_checker_priv_x_ok_lo_lo_1}; // @[package.scala:45:27]
wire [2:0] pma_checker_priv_x_ok_hi_lo_1 = {pma_checker_priv_x_ok_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_priv_x_ok_hi_hi_1 = {pma_checker_priv_x_ok_hi_hi_hi_1, pma_checker_priv_x_ok_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] pma_checker_priv_x_ok_hi_1 = {pma_checker_priv_x_ok_hi_hi_1, pma_checker_priv_x_ok_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] pma_checker__priv_x_ok_T_2 = {pma_checker_priv_x_ok_hi_1, pma_checker_priv_x_ok_lo_1}; // @[package.scala:45:27]
wire [12:0] pma_checker_priv_x_ok = pma_checker_priv_s ? pma_checker__priv_x_ok_T_1 : pma_checker__priv_x_ok_T_2; // @[package.scala:45:27]
wire [1:0] pma_checker_stage1_bypass_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ae_stage2, _pma_checker_entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_stage1_bypass_lo_lo = {pma_checker_stage1_bypass_lo_lo_hi, _pma_checker_entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_stage1_bypass_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ae_stage2, _pma_checker_entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_stage1_bypass_lo_hi = {pma_checker_stage1_bypass_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_stage1_bypass_lo = {pma_checker_stage1_bypass_lo_hi, pma_checker_stage1_bypass_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_stage1_bypass_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ae_stage2, _pma_checker_entries_barrier_7_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_stage1_bypass_hi_lo = {pma_checker_stage1_bypass_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_stage1_bypass_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_ae_stage2, _pma_checker_entries_barrier_9_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_stage1_bypass_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_ae_stage2, _pma_checker_entries_barrier_11_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_stage1_bypass_hi_hi = {pma_checker_stage1_bypass_hi_hi_hi, pma_checker_stage1_bypass_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_stage1_bypass_hi = {pma_checker_stage1_bypass_hi_hi, pma_checker_stage1_bypass_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__stage1_bypass_T_3 = {pma_checker_stage1_bypass_hi, pma_checker_stage1_bypass_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_r_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_sr, _pma_checker_entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_r_array_lo_lo = {pma_checker_r_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_r_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_sr, _pma_checker_entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_r_array_lo_hi = {pma_checker_r_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_r_array_lo = {pma_checker_r_array_lo_hi, pma_checker_r_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_r_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_sr, _pma_checker_entries_barrier_7_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_r_array_hi_lo = {pma_checker_r_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_r_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_sr, _pma_checker_entries_barrier_9_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_r_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_sr, _pma_checker_entries_barrier_11_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_r_array_hi_hi = {pma_checker_r_array_hi_hi_hi, pma_checker_r_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_r_array_hi = {pma_checker_r_array_hi_hi, pma_checker_r_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__r_array_T = {pma_checker_r_array_hi, pma_checker_r_array_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__r_array_T_3 = pma_checker__r_array_T; // @[package.scala:45:27]
wire [1:0] _GEN_11 = {_pma_checker_entries_barrier_2_io_y_sx, _pma_checker_entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_r_array_lo_lo_hi_1; // @[package.scala:45:27]
assign pma_checker_r_array_lo_lo_hi_1 = _GEN_11; // @[package.scala:45:27]
wire [1:0] pma_checker_x_array_lo_lo_hi; // @[package.scala:45:27]
assign pma_checker_x_array_lo_lo_hi = _GEN_11; // @[package.scala:45:27]
wire [2:0] pma_checker_r_array_lo_lo_1 = {pma_checker_r_array_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_12 = {_pma_checker_entries_barrier_5_io_y_sx, _pma_checker_entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_r_array_lo_hi_hi_1; // @[package.scala:45:27]
assign pma_checker_r_array_lo_hi_hi_1 = _GEN_12; // @[package.scala:45:27]
wire [1:0] pma_checker_x_array_lo_hi_hi; // @[package.scala:45:27]
assign pma_checker_x_array_lo_hi_hi = _GEN_12; // @[package.scala:45:27]
wire [2:0] pma_checker_r_array_lo_hi_1 = {pma_checker_r_array_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_r_array_lo_1 = {pma_checker_r_array_lo_hi_1, pma_checker_r_array_lo_lo_1}; // @[package.scala:45:27]
wire [1:0] _GEN_13 = {_pma_checker_entries_barrier_8_io_y_sx, _pma_checker_entries_barrier_7_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_r_array_hi_lo_hi_1; // @[package.scala:45:27]
assign pma_checker_r_array_hi_lo_hi_1 = _GEN_13; // @[package.scala:45:27]
wire [1:0] pma_checker_x_array_hi_lo_hi; // @[package.scala:45:27]
assign pma_checker_x_array_hi_lo_hi = _GEN_13; // @[package.scala:45:27]
wire [2:0] pma_checker_r_array_hi_lo_1 = {pma_checker_r_array_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_14 = {_pma_checker_entries_barrier_10_io_y_sx, _pma_checker_entries_barrier_9_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_r_array_hi_hi_lo_1; // @[package.scala:45:27]
assign pma_checker_r_array_hi_hi_lo_1 = _GEN_14; // @[package.scala:45:27]
wire [1:0] pma_checker_x_array_hi_hi_lo; // @[package.scala:45:27]
assign pma_checker_x_array_hi_hi_lo = _GEN_14; // @[package.scala:45:27]
wire [1:0] _GEN_15 = {_pma_checker_entries_barrier_12_io_y_sx, _pma_checker_entries_barrier_11_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_r_array_hi_hi_hi_1; // @[package.scala:45:27]
assign pma_checker_r_array_hi_hi_hi_1 = _GEN_15; // @[package.scala:45:27]
wire [1:0] pma_checker_x_array_hi_hi_hi; // @[package.scala:45:27]
assign pma_checker_x_array_hi_hi_hi = _GEN_15; // @[package.scala:45:27]
wire [3:0] pma_checker_r_array_hi_hi_1 = {pma_checker_r_array_hi_hi_hi_1, pma_checker_r_array_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] pma_checker_r_array_hi_1 = {pma_checker_r_array_hi_hi_1, pma_checker_r_array_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] pma_checker__r_array_T_1 = {pma_checker_r_array_hi_1, pma_checker_r_array_lo_1}; // @[package.scala:45:27]
wire [12:0] pma_checker__r_array_T_4 = pma_checker_priv_rw_ok & pma_checker__r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}]
wire [12:0] pma_checker__r_array_T_5 = pma_checker__r_array_T_4; // @[TLB.scala:520:{41,113}]
wire [13:0] pma_checker_r_array = {1'h1, pma_checker__r_array_T_5}; // @[TLB.scala:520:{20,113}]
wire [13:0] pma_checker__pf_ld_array_T = pma_checker_r_array; // @[TLB.scala:520:20, :597:41]
wire [1:0] pma_checker_w_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_sw, _pma_checker_entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_w_array_lo_lo = {pma_checker_w_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_w_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_sw, _pma_checker_entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_w_array_lo_hi = {pma_checker_w_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_w_array_lo = {pma_checker_w_array_lo_hi, pma_checker_w_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_w_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_sw, _pma_checker_entries_barrier_7_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_w_array_hi_lo = {pma_checker_w_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_w_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_sw, _pma_checker_entries_barrier_9_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_w_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_sw, _pma_checker_entries_barrier_11_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_w_array_hi_hi = {pma_checker_w_array_hi_hi_hi, pma_checker_w_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_w_array_hi = {pma_checker_w_array_hi_hi, pma_checker_w_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__w_array_T = {pma_checker_w_array_hi, pma_checker_w_array_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__w_array_T_1 = pma_checker_priv_rw_ok & pma_checker__w_array_T; // @[package.scala:45:27]
wire [12:0] pma_checker__w_array_T_2 = pma_checker__w_array_T_1; // @[TLB.scala:521:{41,69}]
wire [13:0] pma_checker_w_array = {1'h1, pma_checker__w_array_T_2}; // @[TLB.scala:521:{20,69}]
wire [2:0] pma_checker_x_array_lo_lo = {pma_checker_x_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_x_array_lo_hi = {pma_checker_x_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_x_array_lo = {pma_checker_x_array_lo_hi, pma_checker_x_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] pma_checker_x_array_hi_lo = {pma_checker_x_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_x_array_hi_hi = {pma_checker_x_array_hi_hi_hi, pma_checker_x_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_x_array_hi = {pma_checker_x_array_hi_hi, pma_checker_x_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__x_array_T = {pma_checker_x_array_hi, pma_checker_x_array_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__x_array_T_1 = pma_checker_priv_x_ok & pma_checker__x_array_T; // @[package.scala:45:27]
wire [12:0] pma_checker__x_array_T_2 = pma_checker__x_array_T_1; // @[TLB.scala:522:{40,68}]
wire [13:0] pma_checker_x_array = {1'h1, pma_checker__x_array_T_2}; // @[TLB.scala:522:{20,68}]
wire [1:0] pma_checker_hr_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_hr, _pma_checker_entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_hr_array_lo_lo = {pma_checker_hr_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hr_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_hr, _pma_checker_entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_hr_array_lo_hi = {pma_checker_hr_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_hr_array_lo = {pma_checker_hr_array_lo_hi, pma_checker_hr_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_hr_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_hr, _pma_checker_entries_barrier_7_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_hr_array_hi_lo = {pma_checker_hr_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hr_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_hr, _pma_checker_entries_barrier_9_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hr_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_hr, _pma_checker_entries_barrier_11_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_hr_array_hi_hi = {pma_checker_hr_array_hi_hi_hi, pma_checker_hr_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_hr_array_hi = {pma_checker_hr_array_hi_hi, pma_checker_hr_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__hr_array_T = {pma_checker_hr_array_hi, pma_checker_hr_array_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__hr_array_T_3 = pma_checker__hr_array_T; // @[package.scala:45:27]
wire [1:0] _GEN_16 = {_pma_checker_entries_barrier_2_io_y_hx, _pma_checker_entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hr_array_lo_lo_hi_1; // @[package.scala:45:27]
assign pma_checker_hr_array_lo_lo_hi_1 = _GEN_16; // @[package.scala:45:27]
wire [1:0] pma_checker_hx_array_lo_lo_hi; // @[package.scala:45:27]
assign pma_checker_hx_array_lo_lo_hi = _GEN_16; // @[package.scala:45:27]
wire [2:0] pma_checker_hr_array_lo_lo_1 = {pma_checker_hr_array_lo_lo_hi_1, _pma_checker_entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_17 = {_pma_checker_entries_barrier_5_io_y_hx, _pma_checker_entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hr_array_lo_hi_hi_1; // @[package.scala:45:27]
assign pma_checker_hr_array_lo_hi_hi_1 = _GEN_17; // @[package.scala:45:27]
wire [1:0] pma_checker_hx_array_lo_hi_hi; // @[package.scala:45:27]
assign pma_checker_hx_array_lo_hi_hi = _GEN_17; // @[package.scala:45:27]
wire [2:0] pma_checker_hr_array_lo_hi_1 = {pma_checker_hr_array_lo_hi_hi_1, _pma_checker_entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_hr_array_lo_1 = {pma_checker_hr_array_lo_hi_1, pma_checker_hr_array_lo_lo_1}; // @[package.scala:45:27]
wire [1:0] _GEN_18 = {_pma_checker_entries_barrier_8_io_y_hx, _pma_checker_entries_barrier_7_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hr_array_hi_lo_hi_1; // @[package.scala:45:27]
assign pma_checker_hr_array_hi_lo_hi_1 = _GEN_18; // @[package.scala:45:27]
wire [1:0] pma_checker_hx_array_hi_lo_hi; // @[package.scala:45:27]
assign pma_checker_hx_array_hi_lo_hi = _GEN_18; // @[package.scala:45:27]
wire [2:0] pma_checker_hr_array_hi_lo_1 = {pma_checker_hr_array_hi_lo_hi_1, _pma_checker_entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_19 = {_pma_checker_entries_barrier_10_io_y_hx, _pma_checker_entries_barrier_9_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hr_array_hi_hi_lo_1; // @[package.scala:45:27]
assign pma_checker_hr_array_hi_hi_lo_1 = _GEN_19; // @[package.scala:45:27]
wire [1:0] pma_checker_hx_array_hi_hi_lo; // @[package.scala:45:27]
assign pma_checker_hx_array_hi_hi_lo = _GEN_19; // @[package.scala:45:27]
wire [1:0] _GEN_20 = {_pma_checker_entries_barrier_12_io_y_hx, _pma_checker_entries_barrier_11_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hr_array_hi_hi_hi_1; // @[package.scala:45:27]
assign pma_checker_hr_array_hi_hi_hi_1 = _GEN_20; // @[package.scala:45:27]
wire [1:0] pma_checker_hx_array_hi_hi_hi; // @[package.scala:45:27]
assign pma_checker_hx_array_hi_hi_hi = _GEN_20; // @[package.scala:45:27]
wire [3:0] pma_checker_hr_array_hi_hi_1 = {pma_checker_hr_array_hi_hi_hi_1, pma_checker_hr_array_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] pma_checker_hr_array_hi_1 = {pma_checker_hr_array_hi_hi_1, pma_checker_hr_array_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] pma_checker__hr_array_T_1 = {pma_checker_hr_array_hi_1, pma_checker_hr_array_lo_1}; // @[package.scala:45:27]
wire [1:0] pma_checker_hw_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_hw, _pma_checker_entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_hw_array_lo_lo = {pma_checker_hw_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hw_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_hw, _pma_checker_entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_hw_array_lo_hi = {pma_checker_hw_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_hw_array_lo = {pma_checker_hw_array_lo_hi, pma_checker_hw_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_hw_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_hw, _pma_checker_entries_barrier_7_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_hw_array_hi_lo = {pma_checker_hw_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hw_array_hi_hi_lo = {_pma_checker_entries_barrier_10_io_y_hw, _pma_checker_entries_barrier_9_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_hw_array_hi_hi_hi = {_pma_checker_entries_barrier_12_io_y_hw, _pma_checker_entries_barrier_11_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_hw_array_hi_hi = {pma_checker_hw_array_hi_hi_hi, pma_checker_hw_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_hw_array_hi = {pma_checker_hw_array_hi_hi, pma_checker_hw_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__hw_array_T = {pma_checker_hw_array_hi, pma_checker_hw_array_lo}; // @[package.scala:45:27]
wire [2:0] pma_checker_hx_array_lo_lo = {pma_checker_hx_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_hx_array_lo_hi = {pma_checker_hx_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_hx_array_lo = {pma_checker_hx_array_lo_hi, pma_checker_hx_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] pma_checker_hx_array_hi_lo = {pma_checker_hx_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [3:0] pma_checker_hx_array_hi_hi = {pma_checker_hx_array_hi_hi_hi, pma_checker_hx_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] pma_checker_hx_array_hi = {pma_checker_hx_array_hi_hi, pma_checker_hx_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] pma_checker__hx_array_T = {pma_checker_hx_array_hi, pma_checker_hx_array_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker__pr_array_T = {2{pma_checker_prot_r}}; // @[TLB.scala:429:55, :529:26]
wire [1:0] pma_checker_pr_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pr, _pma_checker_entries_barrier_1_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pr_array_lo_lo = {pma_checker_pr_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_pr_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pr, _pma_checker_entries_barrier_4_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pr_array_lo_hi = {pma_checker_pr_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_pr_array_lo = {pma_checker_pr_array_lo_hi, pma_checker_pr_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_pr_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pr, _pma_checker_entries_barrier_7_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pr_array_hi_lo = {pma_checker_pr_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_pr_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_pr, _pma_checker_entries_barrier_10_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pr_array_hi_hi = {pma_checker_pr_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_pr_array_hi = {pma_checker_pr_array_hi_hi, pma_checker_pr_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] pma_checker__pr_array_T_1 = {pma_checker_pr_array_hi, pma_checker_pr_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker__pr_array_T_2 = {pma_checker__pr_array_T, pma_checker__pr_array_T_1}; // @[package.scala:45:27]
wire [13:0] _GEN_21 = pma_checker_ptw_ae_array | pma_checker_final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104]
wire [13:0] pma_checker__pr_array_T_3; // @[TLB.scala:529:104]
assign pma_checker__pr_array_T_3 = _GEN_21; // @[TLB.scala:529:104]
wire [13:0] pma_checker__pw_array_T_3; // @[TLB.scala:531:104]
assign pma_checker__pw_array_T_3 = _GEN_21; // @[TLB.scala:529:104, :531:104]
wire [13:0] pma_checker__px_array_T_3; // @[TLB.scala:533:104]
assign pma_checker__px_array_T_3 = _GEN_21; // @[TLB.scala:529:104, :533:104]
wire [13:0] pma_checker__pr_array_T_4 = ~pma_checker__pr_array_T_3; // @[TLB.scala:529:{89,104}]
wire [13:0] pma_checker_pr_array = pma_checker__pr_array_T_2 & pma_checker__pr_array_T_4; // @[TLB.scala:529:{21,87,89}]
wire [1:0] pma_checker__pw_array_T = {2{pma_checker_prot_w}}; // @[TLB.scala:430:55, :531:26]
wire [1:0] pma_checker_pw_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pw, _pma_checker_entries_barrier_1_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pw_array_lo_lo = {pma_checker_pw_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_pw_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pw, _pma_checker_entries_barrier_4_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pw_array_lo_hi = {pma_checker_pw_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_pw_array_lo = {pma_checker_pw_array_lo_hi, pma_checker_pw_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_pw_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pw, _pma_checker_entries_barrier_7_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pw_array_hi_lo = {pma_checker_pw_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_pw_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_pw, _pma_checker_entries_barrier_10_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pw_array_hi_hi = {pma_checker_pw_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_pw_array_hi = {pma_checker_pw_array_hi_hi, pma_checker_pw_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] pma_checker__pw_array_T_1 = {pma_checker_pw_array_hi, pma_checker_pw_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker__pw_array_T_2 = {pma_checker__pw_array_T, pma_checker__pw_array_T_1}; // @[package.scala:45:27]
wire [13:0] pma_checker__pw_array_T_4 = ~pma_checker__pw_array_T_3; // @[TLB.scala:531:{89,104}]
wire [13:0] pma_checker_pw_array = pma_checker__pw_array_T_2 & pma_checker__pw_array_T_4; // @[TLB.scala:531:{21,87,89}]
wire [1:0] pma_checker__px_array_T = {2{pma_checker_prot_x}}; // @[TLB.scala:434:55, :533:26]
wire [1:0] pma_checker_px_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_px, _pma_checker_entries_barrier_1_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_px_array_lo_lo = {pma_checker_px_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_px_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_px, _pma_checker_entries_barrier_4_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_px_array_lo_hi = {pma_checker_px_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_px_array_lo = {pma_checker_px_array_lo_hi, pma_checker_px_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_px_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_px, _pma_checker_entries_barrier_7_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_px_array_hi_lo = {pma_checker_px_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_px}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_px_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_px, _pma_checker_entries_barrier_10_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_px_array_hi_hi = {pma_checker_px_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_px}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_px_array_hi = {pma_checker_px_array_hi_hi, pma_checker_px_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] pma_checker__px_array_T_1 = {pma_checker_px_array_hi, pma_checker_px_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker__px_array_T_2 = {pma_checker__px_array_T, pma_checker__px_array_T_1}; // @[package.scala:45:27]
wire [13:0] pma_checker__px_array_T_4 = ~pma_checker__px_array_T_3; // @[TLB.scala:533:{89,104}]
wire [13:0] pma_checker_px_array = pma_checker__px_array_T_2 & pma_checker__px_array_T_4; // @[TLB.scala:533:{21,87,89}]
wire [1:0] pma_checker__eff_array_T = {2{_pma_checker_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27]
wire [1:0] pma_checker_eff_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_eff, _pma_checker_entries_barrier_1_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_eff_array_lo_lo = {pma_checker_eff_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_eff_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_eff, _pma_checker_entries_barrier_4_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_eff_array_lo_hi = {pma_checker_eff_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_eff_array_lo = {pma_checker_eff_array_lo_hi, pma_checker_eff_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_eff_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_eff, _pma_checker_entries_barrier_7_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_eff_array_hi_lo = {pma_checker_eff_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_eff_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_eff, _pma_checker_entries_barrier_10_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_eff_array_hi_hi = {pma_checker_eff_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_eff_array_hi = {pma_checker_eff_array_hi_hi, pma_checker_eff_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] pma_checker__eff_array_T_1 = {pma_checker_eff_array_hi, pma_checker_eff_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker_eff_array = {pma_checker__eff_array_T, pma_checker__eff_array_T_1}; // @[package.scala:45:27]
wire [1:0] _GEN_22 = {_pma_checker_entries_barrier_2_io_y_c, _pma_checker_entries_barrier_1_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_c_array_lo_lo_hi; // @[package.scala:45:27]
assign pma_checker_c_array_lo_lo_hi = _GEN_22; // @[package.scala:45:27]
wire [1:0] pma_checker_prefetchable_array_lo_lo_hi; // @[package.scala:45:27]
assign pma_checker_prefetchable_array_lo_lo_hi = _GEN_22; // @[package.scala:45:27]
wire [2:0] pma_checker_c_array_lo_lo = {pma_checker_c_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_23 = {_pma_checker_entries_barrier_5_io_y_c, _pma_checker_entries_barrier_4_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_c_array_lo_hi_hi; // @[package.scala:45:27]
assign pma_checker_c_array_lo_hi_hi = _GEN_23; // @[package.scala:45:27]
wire [1:0] pma_checker_prefetchable_array_lo_hi_hi; // @[package.scala:45:27]
assign pma_checker_prefetchable_array_lo_hi_hi = _GEN_23; // @[package.scala:45:27]
wire [2:0] pma_checker_c_array_lo_hi = {pma_checker_c_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_c_array_lo = {pma_checker_c_array_lo_hi, pma_checker_c_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_24 = {_pma_checker_entries_barrier_8_io_y_c, _pma_checker_entries_barrier_7_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_c_array_hi_lo_hi; // @[package.scala:45:27]
assign pma_checker_c_array_hi_lo_hi = _GEN_24; // @[package.scala:45:27]
wire [1:0] pma_checker_prefetchable_array_hi_lo_hi; // @[package.scala:45:27]
assign pma_checker_prefetchable_array_hi_lo_hi = _GEN_24; // @[package.scala:45:27]
wire [2:0] pma_checker_c_array_hi_lo = {pma_checker_c_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_25 = {_pma_checker_entries_barrier_11_io_y_c, _pma_checker_entries_barrier_10_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_c_array_hi_hi_hi; // @[package.scala:45:27]
assign pma_checker_c_array_hi_hi_hi = _GEN_25; // @[package.scala:45:27]
wire [1:0] pma_checker_prefetchable_array_hi_hi_hi; // @[package.scala:45:27]
assign pma_checker_prefetchable_array_hi_hi_hi = _GEN_25; // @[package.scala:45:27]
wire [2:0] pma_checker_c_array_hi_hi = {pma_checker_c_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_c_array_hi = {pma_checker_c_array_hi_hi, pma_checker_c_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] pma_checker__c_array_T_1 = {pma_checker_c_array_hi, pma_checker_c_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker_c_array = {2'h0, pma_checker__c_array_T_1}; // @[package.scala:45:27]
wire [1:0] pma_checker__ppp_array_T = {2{_pma_checker_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27]
wire [1:0] pma_checker_ppp_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_ppp, _pma_checker_entries_barrier_1_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ppp_array_lo_lo = {pma_checker_ppp_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ppp_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_ppp, _pma_checker_entries_barrier_4_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ppp_array_lo_hi = {pma_checker_ppp_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_ppp_array_lo = {pma_checker_ppp_array_lo_hi, pma_checker_ppp_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_ppp_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_ppp, _pma_checker_entries_barrier_7_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ppp_array_hi_lo = {pma_checker_ppp_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_ppp_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_ppp, _pma_checker_entries_barrier_10_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_ppp_array_hi_hi = {pma_checker_ppp_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_ppp_array_hi = {pma_checker_ppp_array_hi_hi, pma_checker_ppp_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] pma_checker__ppp_array_T_1 = {pma_checker_ppp_array_hi, pma_checker_ppp_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker_ppp_array = {pma_checker__ppp_array_T, pma_checker__ppp_array_T_1}; // @[package.scala:45:27]
wire [1:0] pma_checker__paa_array_T = {2{_pma_checker_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27]
wire [1:0] pma_checker_paa_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_paa, _pma_checker_entries_barrier_1_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_paa_array_lo_lo = {pma_checker_paa_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_paa_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_paa, _pma_checker_entries_barrier_4_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_paa_array_lo_hi = {pma_checker_paa_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_paa_array_lo = {pma_checker_paa_array_lo_hi, pma_checker_paa_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_paa_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_paa, _pma_checker_entries_barrier_7_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_paa_array_hi_lo = {pma_checker_paa_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_paa_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_paa, _pma_checker_entries_barrier_10_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_paa_array_hi_hi = {pma_checker_paa_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_paa_array_hi = {pma_checker_paa_array_hi_hi, pma_checker_paa_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] pma_checker__paa_array_T_1 = {pma_checker_paa_array_hi, pma_checker_paa_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker_paa_array = {pma_checker__paa_array_T, pma_checker__paa_array_T_1}; // @[package.scala:45:27]
wire [1:0] pma_checker__pal_array_T = {2{_pma_checker_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27]
wire [1:0] pma_checker_pal_array_lo_lo_hi = {_pma_checker_entries_barrier_2_io_y_pal, _pma_checker_entries_barrier_1_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pal_array_lo_lo = {pma_checker_pal_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_pal_array_lo_hi_hi = {_pma_checker_entries_barrier_5_io_y_pal, _pma_checker_entries_barrier_4_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pal_array_lo_hi = {pma_checker_pal_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_pal_array_lo = {pma_checker_pal_array_lo_hi, pma_checker_pal_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pma_checker_pal_array_hi_lo_hi = {_pma_checker_entries_barrier_8_io_y_pal, _pma_checker_entries_barrier_7_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pal_array_hi_lo = {pma_checker_pal_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [1:0] pma_checker_pal_array_hi_hi_hi = {_pma_checker_entries_barrier_11_io_y_pal, _pma_checker_entries_barrier_10_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_pal_array_hi_hi = {pma_checker_pal_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_pal_array_hi = {pma_checker_pal_array_hi_hi, pma_checker_pal_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] pma_checker__pal_array_T_1 = {pma_checker_pal_array_hi, pma_checker_pal_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker_pal_array = {pma_checker__pal_array_T, pma_checker__pal_array_T_1}; // @[package.scala:45:27]
wire [13:0] pma_checker_ppp_array_if_cached = pma_checker_ppp_array | pma_checker_c_array; // @[TLB.scala:537:20, :539:22, :544:39]
wire [13:0] pma_checker_paa_array_if_cached = pma_checker_paa_array | pma_checker_c_array; // @[TLB.scala:537:20, :541:22, :545:39]
wire [13:0] pma_checker_pal_array_if_cached = pma_checker_pal_array | pma_checker_c_array; // @[TLB.scala:537:20, :543:22, :546:39]
wire [2:0] pma_checker_prefetchable_array_lo_lo = {pma_checker_prefetchable_array_lo_lo_hi, _pma_checker_entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_prefetchable_array_lo_hi = {pma_checker_prefetchable_array_lo_hi_hi, _pma_checker_entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_prefetchable_array_lo = {pma_checker_prefetchable_array_lo_hi, pma_checker_prefetchable_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] pma_checker_prefetchable_array_hi_lo = {pma_checker_prefetchable_array_hi_lo_hi, _pma_checker_entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25]
wire [2:0] pma_checker_prefetchable_array_hi_hi = {pma_checker_prefetchable_array_hi_hi_hi, _pma_checker_entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] pma_checker_prefetchable_array_hi = {pma_checker_prefetchable_array_hi_hi, pma_checker_prefetchable_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] pma_checker__prefetchable_array_T_2 = {pma_checker_prefetchable_array_hi, pma_checker_prefetchable_array_lo}; // @[package.scala:45:27]
wire [13:0] pma_checker_prefetchable_array = {2'h0, pma_checker__prefetchable_array_T_2}; // @[package.scala:45:27]
wire [3:0] pma_checker__misaligned_T = 4'h1 << pma_checker_io_req_bits_size; // @[OneHot.scala:58:35]
wire [4:0] pma_checker__misaligned_T_1 = {1'h0, pma_checker__misaligned_T} - 5'h1; // @[OneHot.scala:58:35]
wire [3:0] pma_checker__misaligned_T_2 = pma_checker__misaligned_T_1[3:0]; // @[TLB.scala:550:69]
wire [33:0] pma_checker__misaligned_T_3 = {30'h0, pma_checker_io_req_bits_vaddr[3:0] & pma_checker__misaligned_T_2}; // @[TLB.scala:550:{39,69}]
wire pma_checker_misaligned = |pma_checker__misaligned_T_3; // @[TLB.scala:550:{39,77}]
wire _GEN_26 = pma_checker_io_req_bits_cmd == 5'h6; // @[package.scala:16:47]
wire pma_checker__cmd_lrsc_T; // @[package.scala:16:47]
assign pma_checker__cmd_lrsc_T = _GEN_26; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_2; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_2 = _GEN_26; // @[package.scala:16:47]
wire _GEN_27 = pma_checker_io_req_bits_cmd == 5'h7; // @[package.scala:16:47]
wire pma_checker__cmd_lrsc_T_1; // @[package.scala:16:47]
assign pma_checker__cmd_lrsc_T_1 = _GEN_27; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_3; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_3 = _GEN_27; // @[package.scala:16:47]
wire pma_checker__cmd_write_T_3; // @[Consts.scala:90:66]
assign pma_checker__cmd_write_T_3 = _GEN_27; // @[package.scala:16:47]
wire pma_checker__cmd_lrsc_T_2 = pma_checker__cmd_lrsc_T | pma_checker__cmd_lrsc_T_1; // @[package.scala:16:47, :81:59]
wire pma_checker_cmd_lrsc = pma_checker__cmd_lrsc_T_2; // @[package.scala:81:59]
wire _GEN_28 = pma_checker_io_req_bits_cmd == 5'h4; // @[package.scala:16:47]
wire pma_checker__cmd_amo_logical_T; // @[package.scala:16:47]
assign pma_checker__cmd_amo_logical_T = _GEN_28; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_7; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_7 = _GEN_28; // @[package.scala:16:47]
wire pma_checker__cmd_write_T_5; // @[package.scala:16:47]
assign pma_checker__cmd_write_T_5 = _GEN_28; // @[package.scala:16:47]
wire _GEN_29 = pma_checker_io_req_bits_cmd == 5'h9; // @[package.scala:16:47]
wire pma_checker__cmd_amo_logical_T_1; // @[package.scala:16:47]
assign pma_checker__cmd_amo_logical_T_1 = _GEN_29; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_8; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_8 = _GEN_29; // @[package.scala:16:47]
wire pma_checker__cmd_write_T_6; // @[package.scala:16:47]
assign pma_checker__cmd_write_T_6 = _GEN_29; // @[package.scala:16:47]
wire _GEN_30 = pma_checker_io_req_bits_cmd == 5'hA; // @[package.scala:16:47]
wire pma_checker__cmd_amo_logical_T_2; // @[package.scala:16:47]
assign pma_checker__cmd_amo_logical_T_2 = _GEN_30; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_9; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_9 = _GEN_30; // @[package.scala:16:47]
wire pma_checker__cmd_write_T_7; // @[package.scala:16:47]
assign pma_checker__cmd_write_T_7 = _GEN_30; // @[package.scala:16:47]
wire _GEN_31 = pma_checker_io_req_bits_cmd == 5'hB; // @[package.scala:16:47]
wire pma_checker__cmd_amo_logical_T_3; // @[package.scala:16:47]
assign pma_checker__cmd_amo_logical_T_3 = _GEN_31; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_10; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_10 = _GEN_31; // @[package.scala:16:47]
wire pma_checker__cmd_write_T_8; // @[package.scala:16:47]
assign pma_checker__cmd_write_T_8 = _GEN_31; // @[package.scala:16:47]
wire pma_checker__cmd_amo_logical_T_4 = pma_checker__cmd_amo_logical_T | pma_checker__cmd_amo_logical_T_1; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_amo_logical_T_5 = pma_checker__cmd_amo_logical_T_4 | pma_checker__cmd_amo_logical_T_2; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_amo_logical_T_6 = pma_checker__cmd_amo_logical_T_5 | pma_checker__cmd_amo_logical_T_3; // @[package.scala:16:47, :81:59]
wire pma_checker_cmd_amo_logical = pma_checker__cmd_amo_logical_T_6; // @[package.scala:81:59]
wire _GEN_32 = pma_checker_io_req_bits_cmd == 5'h8; // @[package.scala:16:47]
wire pma_checker__cmd_amo_arithmetic_T; // @[package.scala:16:47]
assign pma_checker__cmd_amo_arithmetic_T = _GEN_32; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_14; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_14 = _GEN_32; // @[package.scala:16:47]
wire pma_checker__cmd_write_T_12; // @[package.scala:16:47]
assign pma_checker__cmd_write_T_12 = _GEN_32; // @[package.scala:16:47]
wire _GEN_33 = pma_checker_io_req_bits_cmd == 5'hC; // @[package.scala:16:47]
wire pma_checker__cmd_amo_arithmetic_T_1; // @[package.scala:16:47]
assign pma_checker__cmd_amo_arithmetic_T_1 = _GEN_33; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_15; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_15 = _GEN_33; // @[package.scala:16:47]
wire pma_checker__cmd_write_T_13; // @[package.scala:16:47]
assign pma_checker__cmd_write_T_13 = _GEN_33; // @[package.scala:16:47]
wire _GEN_34 = pma_checker_io_req_bits_cmd == 5'hD; // @[package.scala:16:47]
wire pma_checker__cmd_amo_arithmetic_T_2; // @[package.scala:16:47]
assign pma_checker__cmd_amo_arithmetic_T_2 = _GEN_34; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_16; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_16 = _GEN_34; // @[package.scala:16:47]
wire pma_checker__cmd_write_T_14; // @[package.scala:16:47]
assign pma_checker__cmd_write_T_14 = _GEN_34; // @[package.scala:16:47]
wire _GEN_35 = pma_checker_io_req_bits_cmd == 5'hE; // @[package.scala:16:47]
wire pma_checker__cmd_amo_arithmetic_T_3; // @[package.scala:16:47]
assign pma_checker__cmd_amo_arithmetic_T_3 = _GEN_35; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_17; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_17 = _GEN_35; // @[package.scala:16:47]
wire pma_checker__cmd_write_T_15; // @[package.scala:16:47]
assign pma_checker__cmd_write_T_15 = _GEN_35; // @[package.scala:16:47]
wire _GEN_36 = pma_checker_io_req_bits_cmd == 5'hF; // @[package.scala:16:47]
wire pma_checker__cmd_amo_arithmetic_T_4; // @[package.scala:16:47]
assign pma_checker__cmd_amo_arithmetic_T_4 = _GEN_36; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_18; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_18 = _GEN_36; // @[package.scala:16:47]
wire pma_checker__cmd_write_T_16; // @[package.scala:16:47]
assign pma_checker__cmd_write_T_16 = _GEN_36; // @[package.scala:16:47]
wire pma_checker__cmd_amo_arithmetic_T_5 = pma_checker__cmd_amo_arithmetic_T | pma_checker__cmd_amo_arithmetic_T_1; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_amo_arithmetic_T_6 = pma_checker__cmd_amo_arithmetic_T_5 | pma_checker__cmd_amo_arithmetic_T_2; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_amo_arithmetic_T_7 = pma_checker__cmd_amo_arithmetic_T_6 | pma_checker__cmd_amo_arithmetic_T_3; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_amo_arithmetic_T_8 = pma_checker__cmd_amo_arithmetic_T_7 | pma_checker__cmd_amo_arithmetic_T_4; // @[package.scala:16:47, :81:59]
wire pma_checker_cmd_amo_arithmetic = pma_checker__cmd_amo_arithmetic_T_8; // @[package.scala:81:59]
wire _GEN_37 = pma_checker_io_req_bits_cmd == 5'h11; // @[TLB.scala:573:41]
wire pma_checker_cmd_put_partial; // @[TLB.scala:573:41]
assign pma_checker_cmd_put_partial = _GEN_37; // @[TLB.scala:573:41]
wire pma_checker__cmd_write_T_1; // @[Consts.scala:90:49]
assign pma_checker__cmd_write_T_1 = _GEN_37; // @[TLB.scala:573:41]
wire pma_checker__cmd_read_T = pma_checker_io_req_bits_cmd == 5'h0; // @[package.scala:16:47]
wire _GEN_38 = pma_checker_io_req_bits_cmd == 5'h10; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_1; // @[package.scala:16:47]
assign pma_checker__cmd_read_T_1 = _GEN_38; // @[package.scala:16:47]
wire pma_checker__cmd_readx_T; // @[TLB.scala:575:56]
assign pma_checker__cmd_readx_T = _GEN_38; // @[package.scala:16:47]
wire pma_checker__cmd_read_T_4 = pma_checker__cmd_read_T | pma_checker__cmd_read_T_1; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_read_T_5 = pma_checker__cmd_read_T_4 | pma_checker__cmd_read_T_2; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_read_T_6 = pma_checker__cmd_read_T_5 | pma_checker__cmd_read_T_3; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_read_T_11 = pma_checker__cmd_read_T_7 | pma_checker__cmd_read_T_8; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_read_T_12 = pma_checker__cmd_read_T_11 | pma_checker__cmd_read_T_9; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_read_T_13 = pma_checker__cmd_read_T_12 | pma_checker__cmd_read_T_10; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_read_T_19 = pma_checker__cmd_read_T_14 | pma_checker__cmd_read_T_15; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_read_T_20 = pma_checker__cmd_read_T_19 | pma_checker__cmd_read_T_16; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_read_T_21 = pma_checker__cmd_read_T_20 | pma_checker__cmd_read_T_17; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_read_T_22 = pma_checker__cmd_read_T_21 | pma_checker__cmd_read_T_18; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_read_T_23 = pma_checker__cmd_read_T_13 | pma_checker__cmd_read_T_22; // @[package.scala:81:59]
wire pma_checker_cmd_read = pma_checker__cmd_read_T_6 | pma_checker__cmd_read_T_23; // @[package.scala:81:59]
wire pma_checker__cmd_write_T = pma_checker_io_req_bits_cmd == 5'h1; // @[DCache.scala:120:32]
wire pma_checker__cmd_write_T_2 = pma_checker__cmd_write_T | pma_checker__cmd_write_T_1; // @[Consts.scala:90:{32,42,49}]
wire pma_checker__cmd_write_T_4 = pma_checker__cmd_write_T_2 | pma_checker__cmd_write_T_3; // @[Consts.scala:90:{42,59,66}]
wire pma_checker__cmd_write_T_9 = pma_checker__cmd_write_T_5 | pma_checker__cmd_write_T_6; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_write_T_10 = pma_checker__cmd_write_T_9 | pma_checker__cmd_write_T_7; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_write_T_11 = pma_checker__cmd_write_T_10 | pma_checker__cmd_write_T_8; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_write_T_17 = pma_checker__cmd_write_T_12 | pma_checker__cmd_write_T_13; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_write_T_18 = pma_checker__cmd_write_T_17 | pma_checker__cmd_write_T_14; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_write_T_19 = pma_checker__cmd_write_T_18 | pma_checker__cmd_write_T_15; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_write_T_20 = pma_checker__cmd_write_T_19 | pma_checker__cmd_write_T_16; // @[package.scala:16:47, :81:59]
wire pma_checker__cmd_write_T_21 = pma_checker__cmd_write_T_11 | pma_checker__cmd_write_T_20; // @[package.scala:81:59]
wire pma_checker_cmd_write = pma_checker__cmd_write_T_4 | pma_checker__cmd_write_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire pma_checker__cmd_write_perms_T = pma_checker_io_req_bits_cmd == 5'h5; // @[package.scala:16:47]
wire pma_checker__cmd_write_perms_T_1 = pma_checker_io_req_bits_cmd == 5'h17; // @[package.scala:16:47]
wire pma_checker__cmd_write_perms_T_2 = pma_checker__cmd_write_perms_T | pma_checker__cmd_write_perms_T_1; // @[package.scala:16:47, :81:59]
wire pma_checker_cmd_write_perms = pma_checker_cmd_write | pma_checker__cmd_write_perms_T_2; // @[package.scala:81:59]
wire [13:0] pma_checker__ae_array_T = pma_checker_misaligned ? pma_checker_eff_array : 14'h0; // @[TLB.scala:535:22, :550:77, :582:8]
wire [13:0] _GEN_39 = {14{pma_checker_cmd_lrsc}}; // @[TLB.scala:570:33, :583:8]
wire [13:0] pma_checker__ae_array_T_2; // @[TLB.scala:583:8]
assign pma_checker__ae_array_T_2 = _GEN_39; // @[TLB.scala:583:8]
wire [13:0] pma_checker__must_alloc_array_T_9; // @[TLB.scala:596:8]
assign pma_checker__must_alloc_array_T_9 = _GEN_39; // @[TLB.scala:583:8, :596:8]
wire [13:0] pma_checker_ae_array = pma_checker__ae_array_T | pma_checker__ae_array_T_2; // @[TLB.scala:582:{8,37}, :583:8]
wire [13:0] pma_checker__ae_ld_array_T = ~pma_checker_pr_array; // @[TLB.scala:529:87, :586:46]
wire [13:0] pma_checker__ae_ld_array_T_1 = pma_checker_ae_array | pma_checker__ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}]
wire [13:0] pma_checker_ae_ld_array = pma_checker_cmd_read ? pma_checker__ae_ld_array_T_1 : 14'h0; // @[TLB.scala:586:{24,44}]
wire [13:0] pma_checker__ae_st_array_T = ~pma_checker_pw_array; // @[TLB.scala:531:87, :588:37]
wire [13:0] pma_checker__ae_st_array_T_1 = pma_checker_ae_array | pma_checker__ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}]
wire [13:0] pma_checker__ae_st_array_T_2 = pma_checker_cmd_write_perms ? pma_checker__ae_st_array_T_1 : 14'h0; // @[TLB.scala:577:35, :588:{8,35}]
wire [13:0] pma_checker__ae_st_array_T_3 = ~pma_checker_ppp_array_if_cached; // @[TLB.scala:544:39, :589:26]
wire [13:0] pma_checker__ae_st_array_T_4 = pma_checker_cmd_put_partial ? pma_checker__ae_st_array_T_3 : 14'h0; // @[TLB.scala:573:41, :589:{8,26}]
wire [13:0] pma_checker__ae_st_array_T_5 = pma_checker__ae_st_array_T_2 | pma_checker__ae_st_array_T_4; // @[TLB.scala:588:{8,53}, :589:8]
wire [13:0] pma_checker__ae_st_array_T_6 = ~pma_checker_pal_array_if_cached; // @[TLB.scala:546:39, :590:26]
wire [13:0] pma_checker__ae_st_array_T_7 = pma_checker_cmd_amo_logical ? pma_checker__ae_st_array_T_6 : 14'h0; // @[TLB.scala:571:40, :590:{8,26}]
wire [13:0] pma_checker__ae_st_array_T_8 = pma_checker__ae_st_array_T_5 | pma_checker__ae_st_array_T_7; // @[TLB.scala:588:53, :589:53, :590:8]
wire [13:0] pma_checker__ae_st_array_T_9 = ~pma_checker_paa_array_if_cached; // @[TLB.scala:545:39, :591:29]
wire [13:0] pma_checker__ae_st_array_T_10 = pma_checker_cmd_amo_arithmetic ? pma_checker__ae_st_array_T_9 : 14'h0; // @[TLB.scala:572:43, :591:{8,29}]
wire [13:0] pma_checker_ae_st_array = pma_checker__ae_st_array_T_8 | pma_checker__ae_st_array_T_10; // @[TLB.scala:589:53, :590:53, :591:8]
wire [13:0] pma_checker__must_alloc_array_T = ~pma_checker_ppp_array; // @[TLB.scala:539:22, :593:26]
wire [13:0] pma_checker__must_alloc_array_T_1 = pma_checker_cmd_put_partial ? pma_checker__must_alloc_array_T : 14'h0; // @[TLB.scala:573:41, :593:{8,26}]
wire [13:0] pma_checker__must_alloc_array_T_2 = ~pma_checker_pal_array; // @[TLB.scala:543:22, :594:26]
wire [13:0] pma_checker__must_alloc_array_T_3 = pma_checker_cmd_amo_logical ? pma_checker__must_alloc_array_T_2 : 14'h0; // @[TLB.scala:571:40, :594:{8,26}]
wire [13:0] pma_checker__must_alloc_array_T_4 = pma_checker__must_alloc_array_T_1 | pma_checker__must_alloc_array_T_3; // @[TLB.scala:593:{8,43}, :594:8]
wire [13:0] pma_checker__must_alloc_array_T_5 = ~pma_checker_paa_array; // @[TLB.scala:541:22, :595:29]
wire [13:0] pma_checker__must_alloc_array_T_6 = pma_checker_cmd_amo_arithmetic ? pma_checker__must_alloc_array_T_5 : 14'h0; // @[TLB.scala:572:43, :595:{8,29}]
wire [13:0] pma_checker__must_alloc_array_T_7 = pma_checker__must_alloc_array_T_4 | pma_checker__must_alloc_array_T_6; // @[TLB.scala:593:43, :594:43, :595:8]
wire [13:0] pma_checker_must_alloc_array = pma_checker__must_alloc_array_T_7 | pma_checker__must_alloc_array_T_9; // @[TLB.scala:594:43, :595:46, :596:8]
wire [13:0] pma_checker__pf_ld_array_T_1 = ~pma_checker__pf_ld_array_T; // @[TLB.scala:597:{37,41}]
wire [13:0] pma_checker__pf_ld_array_T_2 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73]
wire [13:0] pma_checker__pf_ld_array_T_3 = pma_checker__pf_ld_array_T_1 & pma_checker__pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}]
wire [13:0] pma_checker__pf_ld_array_T_4 = pma_checker__pf_ld_array_T_3 | pma_checker_ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}]
wire [13:0] pma_checker__pf_ld_array_T_5 = ~pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :597:106]
wire [13:0] pma_checker__pf_ld_array_T_6 = pma_checker__pf_ld_array_T_4 & pma_checker__pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}]
wire [13:0] pma_checker_pf_ld_array = pma_checker_cmd_read ? pma_checker__pf_ld_array_T_6 : 14'h0; // @[TLB.scala:597:{24,104}]
wire [13:0] pma_checker__pf_st_array_T = ~pma_checker_w_array; // @[TLB.scala:521:20, :598:44]
wire [13:0] pma_checker__pf_st_array_T_1 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55]
wire [13:0] pma_checker__pf_st_array_T_2 = pma_checker__pf_st_array_T & pma_checker__pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}]
wire [13:0] pma_checker__pf_st_array_T_3 = pma_checker__pf_st_array_T_2 | pma_checker_ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}]
wire [13:0] pma_checker__pf_st_array_T_4 = ~pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88]
wire [13:0] pma_checker__pf_st_array_T_5 = pma_checker__pf_st_array_T_3 & pma_checker__pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}]
wire [13:0] pma_checker_pf_st_array = pma_checker_cmd_write_perms ? pma_checker__pf_st_array_T_5 : 14'h0; // @[TLB.scala:577:35, :598:{24,86}]
wire [13:0] pma_checker__pf_inst_array_T = ~pma_checker_x_array; // @[TLB.scala:522:20, :599:25]
wire [13:0] pma_checker__pf_inst_array_T_1 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36]
wire [13:0] pma_checker__pf_inst_array_T_2 = pma_checker__pf_inst_array_T & pma_checker__pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}]
wire [13:0] pma_checker__pf_inst_array_T_3 = pma_checker__pf_inst_array_T_2 | pma_checker_ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}]
wire [13:0] pma_checker__pf_inst_array_T_4 = ~pma_checker_ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69]
wire [13:0] pma_checker_pf_inst_array = pma_checker__pf_inst_array_T_3 & pma_checker__pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}]
wire [13:0] pma_checker__gf_ld_array_T_4 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100]
wire [13:0] pma_checker__gf_ld_array_T_5 = pma_checker__gf_ld_array_T_3 & pma_checker__gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}]
wire [13:0] pma_checker__gf_st_array_T_3 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81]
wire [13:0] pma_checker__gf_st_array_T_4 = pma_checker__gf_st_array_T_2 & pma_checker__gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}]
wire [13:0] pma_checker__gf_inst_array_T_2 = ~pma_checker_ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64]
wire [13:0] pma_checker__gf_inst_array_T_3 = pma_checker__gf_inst_array_T_1 & pma_checker__gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}]
wire pma_checker__gpa_hits_hit_mask_T = pma_checker_vpn == 21'h0; // @[TLB.scala:335:30, :606:73]
wire [1:0] pma_checker_lo_lo = {pma_checker_sector_hits_1, pma_checker_sector_hits_0}; // @[OneHot.scala:21:45]
wire [1:0] pma_checker_lo_hi = {pma_checker_sector_hits_3, pma_checker_sector_hits_2}; // @[OneHot.scala:21:45]
wire [3:0] pma_checker_lo = {pma_checker_lo_hi, pma_checker_lo_lo}; // @[OneHot.scala:21:45]
wire [3:0] pma_checker_lo_1 = pma_checker_lo; // @[OneHot.scala:21:45, :31:18]
wire [1:0] pma_checker_hi_lo = {pma_checker_sector_hits_5, pma_checker_sector_hits_4}; // @[OneHot.scala:21:45]
wire [1:0] pma_checker_hi_hi = {pma_checker_sector_hits_7, pma_checker_sector_hits_6}; // @[OneHot.scala:21:45]
wire [3:0] pma_checker_hi = {pma_checker_hi_hi, pma_checker_hi_lo}; // @[OneHot.scala:21:45]
wire [3:0] pma_checker_hi_1 = pma_checker_hi; // @[OneHot.scala:21:45, :30:18]
wire [3:0] pma_checker__T_33 = pma_checker_hi_1 | pma_checker_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] pma_checker_hi_2 = pma_checker__T_33[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] pma_checker_lo_2 = pma_checker__T_33[1:0]; // @[OneHot.scala:31:18, :32:28]
wire [2:0] pma_checker_state_vec_0_touch_way_sized = {|pma_checker_hi_1, |pma_checker_hi_2, pma_checker_hi_2[1] | pma_checker_lo_2[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire pma_checker__state_vec_0_set_left_older_T = pma_checker_state_vec_0_touch_way_sized[2]; // @[package.scala:163:13]
wire pma_checker_state_vec_0_set_left_older = ~pma_checker__state_vec_0_set_left_older_T; // @[Replacement.scala:196:{33,43}]
wire [1:0] pma_checker__state_vec_0_T = pma_checker_state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13]
wire [1:0] pma_checker__state_vec_0_T_11 = pma_checker_state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13]
wire pma_checker__state_vec_0_set_left_older_T_1 = pma_checker__state_vec_0_T[1]; // @[package.scala:163:13]
wire pma_checker_state_vec_0_set_left_older_1 = ~pma_checker__state_vec_0_set_left_older_T_1; // @[Replacement.scala:196:{33,43}]
wire pma_checker__state_vec_0_T_1 = pma_checker__state_vec_0_T[0]; // @[package.scala:163:13]
wire pma_checker__state_vec_0_T_5 = pma_checker__state_vec_0_T[0]; // @[package.scala:163:13]
wire pma_checker__state_vec_0_T_2 = pma_checker__state_vec_0_T_1; // @[package.scala:163:13]
wire pma_checker__state_vec_0_T_3 = ~pma_checker__state_vec_0_T_2; // @[Replacement.scala:218:{7,17}]
wire pma_checker__state_vec_0_T_4 = ~pma_checker_state_vec_0_set_left_older_1 & pma_checker__state_vec_0_T_3; // @[Replacement.scala:196:33, :203:16, :218:7]
wire pma_checker__state_vec_0_T_6 = pma_checker__state_vec_0_T_5; // @[Replacement.scala:207:62, :218:17]
wire pma_checker__state_vec_0_T_7 = ~pma_checker__state_vec_0_T_6; // @[Replacement.scala:218:{7,17}]
wire pma_checker__state_vec_0_T_8 = pma_checker_state_vec_0_set_left_older_1 & pma_checker__state_vec_0_T_7; // @[Replacement.scala:196:33, :206:16, :218:7]
wire [1:0] pma_checker_state_vec_0_hi = {pma_checker_state_vec_0_set_left_older_1, pma_checker__state_vec_0_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] pma_checker__state_vec_0_T_9 = {pma_checker_state_vec_0_hi, pma_checker__state_vec_0_T_8}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] pma_checker__state_vec_0_T_10 = pma_checker_state_vec_0_set_left_older ? 3'h0 : pma_checker__state_vec_0_T_9; // @[Replacement.scala:196:33, :202:12, :203:16]
wire pma_checker__state_vec_0_set_left_older_T_2 = pma_checker__state_vec_0_T_11[1]; // @[Replacement.scala:196:43, :207:62]
wire pma_checker_state_vec_0_set_left_older_2 = ~pma_checker__state_vec_0_set_left_older_T_2; // @[Replacement.scala:196:{33,43}]
wire pma_checker__state_vec_0_T_12 = pma_checker__state_vec_0_T_11[0]; // @[package.scala:163:13]
wire pma_checker__state_vec_0_T_16 = pma_checker__state_vec_0_T_11[0]; // @[package.scala:163:13]
wire pma_checker__state_vec_0_T_13 = pma_checker__state_vec_0_T_12; // @[package.scala:163:13]
wire pma_checker__state_vec_0_T_14 = ~pma_checker__state_vec_0_T_13; // @[Replacement.scala:218:{7,17}]
wire pma_checker__state_vec_0_T_15 = ~pma_checker_state_vec_0_set_left_older_2 & pma_checker__state_vec_0_T_14; // @[Replacement.scala:196:33, :203:16, :218:7]
wire pma_checker__state_vec_0_T_17 = pma_checker__state_vec_0_T_16; // @[Replacement.scala:207:62, :218:17]
wire pma_checker__state_vec_0_T_18 = ~pma_checker__state_vec_0_T_17; // @[Replacement.scala:218:{7,17}]
wire pma_checker__state_vec_0_T_19 = pma_checker_state_vec_0_set_left_older_2 & pma_checker__state_vec_0_T_18; // @[Replacement.scala:196:33, :206:16, :218:7]
wire [1:0] pma_checker_state_vec_0_hi_1 = {pma_checker_state_vec_0_set_left_older_2, pma_checker__state_vec_0_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] pma_checker__state_vec_0_T_20 = {pma_checker_state_vec_0_hi_1, pma_checker__state_vec_0_T_19}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] pma_checker__state_vec_0_T_21 = pma_checker_state_vec_0_set_left_older ? pma_checker__state_vec_0_T_20 : 3'h0; // @[Replacement.scala:196:33, :202:12, :206:16]
wire [3:0] pma_checker_state_vec_0_hi_2 = {pma_checker_state_vec_0_set_left_older, pma_checker__state_vec_0_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [6:0] pma_checker__state_vec_0_T_22 = {pma_checker_state_vec_0_hi_2, pma_checker__state_vec_0_T_21}; // @[Replacement.scala:202:12, :206:16]
wire [1:0] pma_checker_lo_3 = {pma_checker_superpage_hits_1, pma_checker_superpage_hits_0}; // @[OneHot.scala:21:45]
wire [1:0] pma_checker_lo_4 = pma_checker_lo_3; // @[OneHot.scala:21:45, :31:18]
wire [1:0] pma_checker_hi_3 = {pma_checker_superpage_hits_3, pma_checker_superpage_hits_2}; // @[OneHot.scala:21:45]
wire [1:0] pma_checker_hi_4 = pma_checker_hi_3; // @[OneHot.scala:21:45, :30:18]
wire [1:0] pma_checker_state_reg_touch_way_sized = {|pma_checker_hi_4, pma_checker_hi_4[1] | pma_checker_lo_4[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire pma_checker__state_reg_set_left_older_T = pma_checker_state_reg_touch_way_sized[1]; // @[package.scala:163:13]
wire pma_checker_state_reg_set_left_older = ~pma_checker__state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}]
wire pma_checker__state_reg_T = pma_checker_state_reg_touch_way_sized[0]; // @[package.scala:163:13]
wire pma_checker__state_reg_T_4 = pma_checker_state_reg_touch_way_sized[0]; // @[package.scala:163:13]
wire pma_checker__state_reg_T_1 = pma_checker__state_reg_T; // @[package.scala:163:13]
wire pma_checker__state_reg_T_2 = ~pma_checker__state_reg_T_1; // @[Replacement.scala:218:{7,17}]
wire pma_checker__state_reg_T_3 = ~pma_checker_state_reg_set_left_older & pma_checker__state_reg_T_2; // @[Replacement.scala:196:33, :203:16, :218:7]
wire pma_checker__state_reg_T_5 = pma_checker__state_reg_T_4; // @[Replacement.scala:207:62, :218:17]
wire pma_checker__state_reg_T_6 = ~pma_checker__state_reg_T_5; // @[Replacement.scala:218:{7,17}]
wire pma_checker__state_reg_T_7 = pma_checker_state_reg_set_left_older & pma_checker__state_reg_T_6; // @[Replacement.scala:196:33, :206:16, :218:7]
wire [1:0] pma_checker_state_reg_hi = {pma_checker_state_reg_set_left_older, pma_checker__state_reg_T_3}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] pma_checker__state_reg_T_8 = {pma_checker_state_reg_hi, pma_checker__state_reg_T_7}; // @[Replacement.scala:202:12, :206:16]
wire [13:0] pma_checker__io_resp_pf_ld_T_1 = pma_checker_pf_ld_array & 14'h2000; // @[TLB.scala:597:24, :633:57]
wire pma_checker__io_resp_pf_ld_T_2 = |pma_checker__io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}]
assign pma_checker__io_resp_pf_ld_T_3 = pma_checker__io_resp_pf_ld_T_2; // @[TLB.scala:633:{41,65}]
assign pma_checker_io_resp_pf_ld = pma_checker__io_resp_pf_ld_T_3; // @[TLB.scala:633:41]
wire [13:0] pma_checker__io_resp_pf_st_T_1 = pma_checker_pf_st_array & 14'h2000; // @[TLB.scala:598:24, :634:64]
wire pma_checker__io_resp_pf_st_T_2 = |pma_checker__io_resp_pf_st_T_1; // @[TLB.scala:634:{64,72}]
assign pma_checker__io_resp_pf_st_T_3 = pma_checker__io_resp_pf_st_T_2; // @[TLB.scala:634:{48,72}]
assign pma_checker_io_resp_pf_st = pma_checker__io_resp_pf_st_T_3; // @[TLB.scala:634:48]
wire [13:0] pma_checker__io_resp_pf_inst_T = pma_checker_pf_inst_array & 14'h2000; // @[TLB.scala:599:67, :635:47]
wire pma_checker__io_resp_pf_inst_T_1 = |pma_checker__io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}]
assign pma_checker__io_resp_pf_inst_T_2 = pma_checker__io_resp_pf_inst_T_1; // @[TLB.scala:635:{29,55}]
assign pma_checker_io_resp_pf_inst = pma_checker__io_resp_pf_inst_T_2; // @[TLB.scala:635:29]
wire [13:0] pma_checker__io_resp_ae_ld_T = pma_checker_ae_ld_array & 14'h2000; // @[TLB.scala:586:24, :641:33]
assign pma_checker__io_resp_ae_ld_T_1 = |pma_checker__io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}]
assign pma_checker_io_resp_ae_ld = pma_checker__io_resp_ae_ld_T_1; // @[TLB.scala:641:41]
wire [13:0] pma_checker__io_resp_ae_st_T = pma_checker_ae_st_array & 14'h2000; // @[TLB.scala:590:53, :642:33]
assign pma_checker__io_resp_ae_st_T_1 = |pma_checker__io_resp_ae_st_T; // @[TLB.scala:642:{33,41}]
assign pma_checker_io_resp_ae_st = pma_checker__io_resp_ae_st_T_1; // @[TLB.scala:642:41]
wire [13:0] pma_checker__io_resp_ae_inst_T = ~pma_checker_px_array; // @[TLB.scala:533:87, :643:23]
wire [13:0] pma_checker__io_resp_ae_inst_T_1 = pma_checker__io_resp_ae_inst_T & 14'h2000; // @[TLB.scala:643:{23,33}]
assign pma_checker__io_resp_ae_inst_T_2 = |pma_checker__io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}]
assign pma_checker_io_resp_ae_inst = pma_checker__io_resp_ae_inst_T_2; // @[TLB.scala:643:41]
assign pma_checker__io_resp_ma_ld_T = pma_checker_misaligned & pma_checker_cmd_read; // @[TLB.scala:550:77, :645:31]
assign pma_checker_io_resp_ma_ld = pma_checker__io_resp_ma_ld_T; // @[TLB.scala:645:31]
assign pma_checker__io_resp_ma_st_T = pma_checker_misaligned & pma_checker_cmd_write; // @[TLB.scala:550:77, :646:31]
assign pma_checker_io_resp_ma_st = pma_checker__io_resp_ma_st_T; // @[TLB.scala:646:31]
wire [13:0] pma_checker__io_resp_cacheable_T = pma_checker_c_array & 14'h2000; // @[TLB.scala:537:20, :648:33]
assign pma_checker__io_resp_cacheable_T_1 = |pma_checker__io_resp_cacheable_T; // @[TLB.scala:648:{33,41}]
assign pma_checker_io_resp_cacheable = pma_checker__io_resp_cacheable_T_1; // @[TLB.scala:648:41]
wire [13:0] pma_checker__io_resp_must_alloc_T = pma_checker_must_alloc_array & 14'h2000; // @[TLB.scala:595:46, :649:43]
assign pma_checker__io_resp_must_alloc_T_1 = |pma_checker__io_resp_must_alloc_T; // @[TLB.scala:649:{43,51}]
assign pma_checker_io_resp_must_alloc = pma_checker__io_resp_must_alloc_T_1; // @[TLB.scala:649:51]
wire [13:0] pma_checker__io_resp_prefetchable_T = pma_checker_prefetchable_array & 14'h2000; // @[TLB.scala:547:31, :650:47]
wire pma_checker__io_resp_prefetchable_T_1 = |pma_checker__io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}]
assign pma_checker__io_resp_prefetchable_T_2 = pma_checker__io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}]
assign pma_checker_io_resp_prefetchable = pma_checker__io_resp_prefetchable_T_2; // @[TLB.scala:650:59]
assign pma_checker__io_resp_paddr_T_1 = {pma_checker_ppn, pma_checker__io_resp_paddr_T}; // @[Mux.scala:30:73]
assign pma_checker_io_resp_paddr = pma_checker__io_resp_paddr_T_1; // @[TLB.scala:652:23]
wire [21:0] pma_checker__io_resp_gpa_page_T_1 = {1'h0, pma_checker_vpn}; // @[TLB.scala:335:30, :657:36]
wire [21:0] pma_checker_io_resp_gpa_page = pma_checker__io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}]
wire [11:0] pma_checker_io_resp_gpa_offset = pma_checker__io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}]
assign pma_checker__io_resp_gpa_T = {pma_checker_io_resp_gpa_page, pma_checker_io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8]
assign pma_checker_io_resp_gpa = pma_checker__io_resp_gpa_T; // @[TLB.scala:659:8]
wire replace; // @[Replacement.scala:37:29]
wire [1:0] lfsr_lo_lo_lo = {_lfsr_prng_io_out_1, _lfsr_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] lfsr_lo_lo_hi = {_lfsr_prng_io_out_3, _lfsr_prng_io_out_2}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] lfsr_lo_lo = {lfsr_lo_lo_hi, lfsr_lo_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] lfsr_lo_hi_lo = {_lfsr_prng_io_out_5, _lfsr_prng_io_out_4}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] lfsr_lo_hi_hi = {_lfsr_prng_io_out_7, _lfsr_prng_io_out_6}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] lfsr_lo_hi = {lfsr_lo_hi_hi, lfsr_lo_hi_lo}; // @[PRNG.scala:95:17]
wire [7:0] lfsr_lo = {lfsr_lo_hi, lfsr_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] lfsr_hi_lo_lo = {_lfsr_prng_io_out_9, _lfsr_prng_io_out_8}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] lfsr_hi_lo_hi = {_lfsr_prng_io_out_11, _lfsr_prng_io_out_10}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] lfsr_hi_lo = {lfsr_hi_lo_hi, lfsr_hi_lo_lo}; // @[PRNG.scala:95:17]
wire [1:0] lfsr_hi_hi_lo = {_lfsr_prng_io_out_13, _lfsr_prng_io_out_12}; // @[PRNG.scala:91:22, :95:17]
wire [1:0] lfsr_hi_hi_hi = {_lfsr_prng_io_out_15, _lfsr_prng_io_out_14}; // @[PRNG.scala:91:22, :95:17]
wire [3:0] lfsr_hi_hi = {lfsr_hi_hi_hi, lfsr_hi_hi_lo}; // @[PRNG.scala:95:17]
wire [7:0] lfsr_hi = {lfsr_hi_hi, lfsr_hi_lo}; // @[PRNG.scala:95:17]
wire [15:0] lfsr = {lfsr_hi, lfsr_lo}; // @[PRNG.scala:95:17]
wire [33:0] _metaArb_io_in_5_bits_addr_T_2; // @[DCache.scala:1018:36]
wire [33:0] _metaArb_io_in_1_bits_addr_T_2; // @[DCache.scala:454:36]
wire [7:0] _metaArb_io_in_1_bits_idx_T_2; // @[DCache.scala:453:35]
wire _metaArb_io_in_2_valid_T; // @[DCache.scala:462:63]
wire metaArb__grant_T_1 = metaArb_io_in_2_valid; // @[Arbiter.scala:45:68]
wire [33:0] _metaArb_io_in_2_bits_addr_T_2; // @[DCache.scala:466:36]
wire [7:0] _metaArb_io_in_2_bits_idx_T; // @[DCache.scala:465:40]
wire [19:0] _metaArb_io_in_2_bits_data_T_1; // @[DCache.scala:467:97]
wire metaArb__io_in_3_ready_T; // @[Arbiter.scala:153:19]
wire _metaArb_io_in_3_valid_T_2; // @[DCache.scala:741:53]
wire [33:0] _metaArb_io_in_3_bits_addr_T_2; // @[DCache.scala:745:36]
wire [7:0] _metaArb_io_in_3_bits_idx_T; // @[DCache.scala:744:40]
wire [19:0] _metaArb_io_in_3_bits_data_T_18; // @[DCache.scala:746:134]
wire metaArb__io_in_4_ready_T; // @[Arbiter.scala:153:19]
wire [33:0] _metaArb_io_in_4_bits_addr_T_2; // @[DCache.scala:912:36]
wire releaseWay; // @[DCache.scala:232:24]
wire [19:0] _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:913:97]
wire metaArb__io_in_5_ready_T; // @[Arbiter.scala:153:19]
wire metaArb__io_in_6_ready_T; // @[Arbiter.scala:153:19]
wire [33:0] _metaArb_io_in_6_bits_addr_T_1; // @[DCache.scala:773:36]
wire metaArb__io_in_7_ready_T; // @[Arbiter.scala:153:19]
wire [7:0] _metaArb_io_in_7_bits_idx_T; // @[DCache.scala:263:58]
wire metaArb__io_out_valid_T_1; // @[Arbiter.scala:154:31]
wire [33:0] metaArb_io_in_0_bits_addr; // @[DCache.scala:135:28]
wire [33:0] metaArb_io_in_1_bits_addr; // @[DCache.scala:135:28]
wire [7:0] metaArb_io_in_1_bits_idx; // @[DCache.scala:135:28]
wire [33:0] metaArb_io_in_2_bits_addr; // @[DCache.scala:135:28]
wire [7:0] metaArb_io_in_2_bits_idx; // @[DCache.scala:135:28]
wire metaArb_io_in_2_bits_way_en; // @[DCache.scala:135:28]
wire [19:0] metaArb_io_in_2_bits_data; // @[DCache.scala:135:28]
wire [33:0] metaArb_io_in_3_bits_addr; // @[DCache.scala:135:28]
wire [7:0] metaArb_io_in_3_bits_idx; // @[DCache.scala:135:28]
wire metaArb_io_in_3_bits_way_en; // @[DCache.scala:135:28]
wire [19:0] metaArb_io_in_3_bits_data; // @[DCache.scala:135:28]
wire metaArb_io_in_3_ready; // @[DCache.scala:135:28]
wire metaArb_io_in_3_valid; // @[DCache.scala:135:28]
wire [33:0] metaArb_io_in_4_bits_addr; // @[DCache.scala:135:28]
wire metaArb_io_in_4_bits_way_en; // @[DCache.scala:135:28]
wire [19:0] metaArb_io_in_4_bits_data; // @[DCache.scala:135:28]
wire metaArb_io_in_4_ready; // @[DCache.scala:135:28]
wire [33:0] metaArb_io_in_5_bits_addr; // @[DCache.scala:135:28]
wire metaArb_io_in_5_bits_way_en; // @[DCache.scala:135:28]
wire [19:0] metaArb_io_in_5_bits_data; // @[DCache.scala:135:28]
wire metaArb_io_in_5_ready; // @[DCache.scala:135:28]
wire [33:0] metaArb_io_in_6_bits_addr; // @[DCache.scala:135:28]
wire metaArb_io_in_6_bits_way_en; // @[DCache.scala:135:28]
wire [19:0] metaArb_io_in_6_bits_data; // @[DCache.scala:135:28]
wire metaArb_io_in_6_ready; // @[DCache.scala:135:28]
wire [7:0] metaArb_io_in_7_bits_idx; // @[DCache.scala:135:28]
wire metaArb_io_in_7_bits_way_en; // @[DCache.scala:135:28]
wire [19:0] metaArb_io_in_7_bits_data; // @[DCache.scala:135:28]
wire metaArb_io_in_7_ready; // @[DCache.scala:135:28]
wire metaArb_io_out_bits_write; // @[DCache.scala:135:28]
wire [33:0] metaArb_io_out_bits_addr; // @[DCache.scala:135:28]
wire [7:0] metaArb_io_out_bits_idx; // @[DCache.scala:135:28]
wire metaArb_io_out_bits_way_en; // @[DCache.scala:135:28]
wire [19:0] metaArb_io_out_bits_data; // @[DCache.scala:135:28]
wire metaArb_io_out_valid; // @[DCache.scala:135:28]
wire [2:0] metaArb_io_chosen; // @[DCache.scala:135:28]
assign metaArb_io_chosen = metaArb_io_in_2_valid ? 3'h2 : {~metaArb_io_in_3_valid, 2'h3}; // @[Arbiter.scala:145:26, :146:17]
assign metaArb_io_out_bits_addr = metaArb_io_in_2_valid ? metaArb_io_in_2_bits_addr : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_addr : metaArb_io_in_7_bits_addr; // @[Arbiter.scala:145:26, :147:19]
assign metaArb_io_out_bits_idx = metaArb_io_in_2_valid ? metaArb_io_in_2_bits_idx : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_idx : metaArb_io_in_7_bits_idx; // @[Arbiter.scala:145:26, :147:19]
assign metaArb_io_out_bits_way_en = metaArb_io_in_2_valid ? metaArb_io_in_2_bits_way_en : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_way_en : metaArb_io_in_7_bits_way_en; // @[Arbiter.scala:145:26, :147:19]
assign metaArb_io_out_bits_data = metaArb_io_in_2_valid ? metaArb_io_in_2_bits_data : metaArb_io_in_3_valid ? metaArb_io_in_3_bits_data : metaArb_io_in_7_bits_data; // @[Arbiter.scala:145:26, :147:19]
assign metaArb_io_out_bits_write = metaArb_io_in_2_valid | metaArb_io_in_3_valid; // @[Arbiter.scala:145:26, :147:19]
wire metaArb__grant_T_2 = metaArb__grant_T_1 | metaArb_io_in_3_valid; // @[Arbiter.scala:45:68]
wire metaArb__grant_T_3 = metaArb__grant_T_2; // @[Arbiter.scala:45:68]
wire metaArb__grant_T_4 = metaArb__grant_T_3; // @[Arbiter.scala:45:68]
wire metaArb__grant_T_5 = metaArb__grant_T_4; // @[Arbiter.scala:45:68]
wire metaArb_grant_3 = ~metaArb__grant_T_1; // @[Arbiter.scala:45:{68,78}]
assign metaArb__io_in_3_ready_T = metaArb_grant_3; // @[Arbiter.scala:45:78, :153:19]
wire metaArb_grant_4 = ~metaArb__grant_T_2; // @[Arbiter.scala:45:{68,78}]
assign metaArb__io_in_4_ready_T = metaArb_grant_4; // @[Arbiter.scala:45:78, :153:19]
wire metaArb_grant_5 = ~metaArb__grant_T_3; // @[Arbiter.scala:45:{68,78}]
assign metaArb__io_in_5_ready_T = metaArb_grant_5; // @[Arbiter.scala:45:78, :153:19]
wire metaArb_grant_6 = ~metaArb__grant_T_4; // @[Arbiter.scala:45:{68,78}]
assign metaArb__io_in_6_ready_T = metaArb_grant_6; // @[Arbiter.scala:45:78, :153:19]
wire metaArb_grant_7 = ~metaArb__grant_T_5; // @[Arbiter.scala:45:{68,78}]
assign metaArb__io_in_7_ready_T = metaArb_grant_7; // @[Arbiter.scala:45:78, :153:19]
assign metaArb_io_in_3_ready = metaArb__io_in_3_ready_T; // @[Arbiter.scala:153:19]
assign metaArb_io_in_4_ready = metaArb__io_in_4_ready_T; // @[Arbiter.scala:153:19]
assign metaArb_io_in_5_ready = metaArb__io_in_5_ready_T; // @[Arbiter.scala:153:19]
assign metaArb_io_in_6_ready = metaArb__io_in_6_ready_T; // @[Arbiter.scala:153:19]
assign metaArb_io_in_7_ready = metaArb__io_in_7_ready_T; // @[Arbiter.scala:153:19]
wire metaArb__io_out_valid_T = ~metaArb_grant_7; // @[Arbiter.scala:45:78, :154:19]
assign metaArb__io_out_valid_T_1 = metaArb__io_out_valid_T | metaArb_io_in_7_valid; // @[Arbiter.scala:154:{19,31}]
assign metaArb_io_out_valid = metaArb__io_out_valid_T_1; // @[Arbiter.scala:154:31]
wire _dataArb_io_in_0_valid_T_12; // @[DCache.scala:516:27]
wire pstore_drain; // @[DCache.scala:516:27]
wire [63:0] _dataArb_io_in_0_bits_wdata_T_9; // @[package.scala:45:27]
wire [7:0] _dataArb_io_in_0_bits_eccMask_T_17; // @[package.scala:45:27]
wire _dataArb_io_in_0_bits_way_en_T; // @[DCache.scala:550:38]
wire dataArb__io_in_1_ready_T; // @[Arbiter.scala:153:19]
wire dataArb__io_in_2_ready_T; // @[Arbiter.scala:153:19]
wire [13:0] _dataArb_io_in_2_bits_addr_T_4; // @[DCache.scala:903:72]
wire dataArb__io_in_3_ready_T; // @[Arbiter.scala:153:19]
wire _dataArb_io_in_3_valid_T_58; // @[DCache.scala:242:46]
wire dataArb__io_out_valid_T_1; // @[Arbiter.scala:154:31]
wire [13:0] dataArb_io_in_0_bits_addr; // @[DCache.scala:152:28]
wire dataArb_io_in_0_bits_write; // @[DCache.scala:152:28]
wire [63:0] dataArb_io_in_0_bits_wdata; // @[DCache.scala:152:28]
wire dataArb_io_in_0_bits_wordMask; // @[DCache.scala:152:28]
wire [7:0] dataArb_io_in_0_bits_eccMask; // @[DCache.scala:152:28]
wire dataArb_io_in_0_bits_way_en; // @[DCache.scala:152:28]
wire dataArb_io_in_0_valid; // @[DCache.scala:152:28]
wire [13:0] dataArb_io_in_1_bits_addr; // @[DCache.scala:152:28]
wire dataArb_io_in_1_bits_write; // @[DCache.scala:152:28]
wire [63:0] dataArb_io_in_1_bits_wdata; // @[DCache.scala:152:28]
wire dataArb_io_in_1_bits_wordMask; // @[DCache.scala:152:28]
wire [7:0] dataArb_io_in_1_bits_eccMask; // @[DCache.scala:152:28]
wire dataArb_io_in_1_bits_way_en; // @[DCache.scala:152:28]
wire dataArb_io_in_1_ready; // @[DCache.scala:152:28]
wire dataArb_io_in_1_valid; // @[DCache.scala:152:28]
wire [13:0] dataArb_io_in_2_bits_addr; // @[DCache.scala:152:28]
wire [63:0] dataArb_io_in_2_bits_wdata; // @[DCache.scala:152:28]
wire dataArb_io_in_2_ready; // @[DCache.scala:152:28]
wire [13:0] dataArb_io_in_3_bits_addr; // @[DCache.scala:152:28]
wire [63:0] dataArb_io_in_3_bits_wdata; // @[DCache.scala:152:28]
wire dataArb_io_in_3_ready; // @[DCache.scala:152:28]
wire dataArb_io_in_3_valid; // @[DCache.scala:152:28]
wire [13:0] dataArb_io_out_bits_addr; // @[DCache.scala:152:28]
wire dataArb_io_out_bits_write; // @[DCache.scala:152:28]
wire [63:0] dataArb_io_out_bits_wdata; // @[DCache.scala:152:28]
wire dataArb_io_out_bits_wordMask; // @[DCache.scala:152:28]
wire [7:0] dataArb_io_out_bits_eccMask; // @[DCache.scala:152:28]
wire dataArb_io_out_bits_way_en; // @[DCache.scala:152:28]
wire dataArb_io_out_valid; // @[DCache.scala:152:28]
wire [1:0] dataArb_io_chosen; // @[DCache.scala:152:28]
assign dataArb_io_chosen = dataArb_io_in_0_valid ? 2'h0 : {~dataArb_io_in_1_valid, 1'h1}; // @[Arbiter.scala:145:26, :146:17]
assign dataArb_io_out_bits_addr = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_addr : dataArb_io_in_1_valid ? dataArb_io_in_1_bits_addr : dataArb_io_in_3_bits_addr; // @[Arbiter.scala:145:26, :147:19]
assign dataArb_io_out_bits_write = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_write : dataArb_io_in_1_valid & dataArb_io_in_1_bits_write; // @[Arbiter.scala:145:26, :147:19]
assign dataArb_io_out_bits_wdata = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_wdata : dataArb_io_in_1_valid ? dataArb_io_in_1_bits_wdata : dataArb_io_in_3_bits_wdata; // @[Arbiter.scala:145:26, :147:19]
assign dataArb_io_out_bits_wordMask = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_wordMask : ~dataArb_io_in_1_valid | dataArb_io_in_1_bits_wordMask; // @[Arbiter.scala:145:26, :146:17, :147:19]
assign dataArb_io_out_bits_eccMask = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_eccMask : dataArb_io_in_1_valid ? dataArb_io_in_1_bits_eccMask : 8'hFF; // @[Arbiter.scala:145:26, :147:19]
assign dataArb_io_out_bits_way_en = dataArb_io_in_0_valid ? dataArb_io_in_0_bits_way_en : ~dataArb_io_in_1_valid | dataArb_io_in_1_bits_way_en; // @[Arbiter.scala:145:26, :146:17, :147:19]
wire dataArb__grant_T = dataArb_io_in_0_valid | dataArb_io_in_1_valid; // @[Arbiter.scala:45:68]
wire dataArb__grant_T_1 = dataArb__grant_T; // @[Arbiter.scala:45:68]
wire dataArb_grant_1 = ~dataArb_io_in_0_valid; // @[Arbiter.scala:45:78]
assign dataArb__io_in_1_ready_T = dataArb_grant_1; // @[Arbiter.scala:45:78, :153:19]
wire dataArb_grant_2 = ~dataArb__grant_T; // @[Arbiter.scala:45:{68,78}]
assign dataArb__io_in_2_ready_T = dataArb_grant_2; // @[Arbiter.scala:45:78, :153:19]
wire dataArb_grant_3 = ~dataArb__grant_T_1; // @[Arbiter.scala:45:{68,78}]
assign dataArb__io_in_3_ready_T = dataArb_grant_3; // @[Arbiter.scala:45:78, :153:19]
assign dataArb_io_in_1_ready = dataArb__io_in_1_ready_T; // @[Arbiter.scala:153:19]
assign dataArb_io_in_2_ready = dataArb__io_in_2_ready_T; // @[Arbiter.scala:153:19]
assign dataArb_io_in_3_ready = dataArb__io_in_3_ready_T; // @[Arbiter.scala:153:19]
wire dataArb__io_out_valid_T = ~dataArb_grant_3; // @[Arbiter.scala:45:78, :154:19]
assign dataArb__io_out_valid_T_1 = dataArb__io_out_valid_T | dataArb_io_in_3_valid; // @[Arbiter.scala:154:{19,31}]
assign dataArb_io_out_valid = dataArb__io_out_valid_T_1; // @[Arbiter.scala:154:31]
wire _tl_out_a_valid_T_14; // @[DCache.scala:603:37]
assign nodeOut_a_deq_valid = tl_out_a_valid; // @[Decoupled.scala:356:21]
wire [2:0] _tl_out_a_bits_T_7_opcode; // @[DCache.scala:608:23]
assign nodeOut_a_deq_bits_opcode = tl_out_a_bits_opcode; // @[Decoupled.scala:356:21]
wire [2:0] _tl_out_a_bits_T_7_param; // @[DCache.scala:608:23]
assign nodeOut_a_deq_bits_param = tl_out_a_bits_param; // @[Decoupled.scala:356:21]
wire [3:0] _tl_out_a_bits_T_7_size; // @[DCache.scala:608:23]
assign nodeOut_a_deq_bits_size = tl_out_a_bits_size; // @[Decoupled.scala:356:21]
wire [31:0] _tl_out_a_bits_T_7_address; // @[DCache.scala:608:23]
assign nodeOut_a_deq_bits_address = tl_out_a_bits_address; // @[Decoupled.scala:356:21]
assign nodeOut_a_deq_bits_user_amba_prot_bufferable = tl_out_a_bits_user_amba_prot_bufferable; // @[Decoupled.scala:356:21]
assign nodeOut_a_deq_bits_user_amba_prot_modifiable = tl_out_a_bits_user_amba_prot_modifiable; // @[Decoupled.scala:356:21]
assign nodeOut_a_deq_bits_user_amba_prot_readalloc = tl_out_a_bits_user_amba_prot_readalloc; // @[Decoupled.scala:356:21]
assign nodeOut_a_deq_bits_user_amba_prot_writealloc = tl_out_a_bits_user_amba_prot_writealloc; // @[Decoupled.scala:356:21]
wire _tl_out_a_bits_user_amba_prot_privileged_T_1; // @[DCache.scala:617:46]
assign nodeOut_a_deq_bits_user_amba_prot_privileged = tl_out_a_bits_user_amba_prot_privileged; // @[Decoupled.scala:356:21]
wire [7:0] _tl_out_a_bits_T_7_mask; // @[DCache.scala:608:23]
assign nodeOut_a_deq_bits_mask = tl_out_a_bits_mask; // @[Decoupled.scala:356:21]
wire [63:0] _tl_out_a_bits_T_7_data; // @[DCache.scala:608:23]
assign nodeOut_a_deq_bits_data = tl_out_a_bits_data; // @[Decoupled.scala:356:21]
wire tl_out_a_ready; // @[DCache.scala:159:22]
assign tl_out_a_ready = nodeOut_a_deq_ready; // @[Decoupled.scala:356:21]
assign nodeOut_a_valid = nodeOut_a_deq_valid; // @[Decoupled.scala:356:21]
assign nodeOut_a_bits_opcode = nodeOut_a_deq_bits_opcode; // @[Decoupled.scala:356:21]
assign nodeOut_a_bits_param = nodeOut_a_deq_bits_param; // @[Decoupled.scala:356:21]
assign nodeOut_a_bits_size = nodeOut_a_deq_bits_size; // @[Decoupled.scala:356:21]
assign nodeOut_a_bits_address = nodeOut_a_deq_bits_address; // @[Decoupled.scala:356:21]
assign nodeOut_a_bits_user_amba_prot_bufferable = nodeOut_a_deq_bits_user_amba_prot_bufferable; // @[Decoupled.scala:356:21]
assign nodeOut_a_bits_user_amba_prot_modifiable = nodeOut_a_deq_bits_user_amba_prot_modifiable; // @[Decoupled.scala:356:21]
assign nodeOut_a_bits_user_amba_prot_readalloc = nodeOut_a_deq_bits_user_amba_prot_readalloc; // @[Decoupled.scala:356:21]
assign nodeOut_a_bits_user_amba_prot_writealloc = nodeOut_a_deq_bits_user_amba_prot_writealloc; // @[Decoupled.scala:356:21]
assign nodeOut_a_bits_user_amba_prot_privileged = nodeOut_a_deq_bits_user_amba_prot_privileged; // @[Decoupled.scala:356:21]
assign nodeOut_a_bits_mask = nodeOut_a_deq_bits_mask; // @[Decoupled.scala:356:21]
assign nodeOut_a_bits_data = nodeOut_a_deq_bits_data; // @[Decoupled.scala:356:21]
wire _tl_out_c_valid_T_6; // @[DCache.scala:810:117]
wire tl_out_c_valid; // @[Bundles.scala:265:61]
wire _s1_valid_T = io_cpu_req_ready_0 & io_cpu_req_valid_0; // @[Decoupled.scala:51:35]
reg s1_valid; // @[DCache.scala:182:25]
wire _s2_data_en_T = s1_valid; // @[DCache.scala:182:25, :366:23]
wire s1_nack; // @[DCache.scala:185:28]
wire _s1_valid_masked_T = ~io_cpu_s1_kill_0; // @[DCache.scala:101:7, :186:37]
wire s1_valid_masked = s1_valid & _s1_valid_masked_T; // @[DCache.scala:182:25, :186:{34,37}]
wire _s1_valid_not_nacked_T = ~s1_nack; // @[DCache.scala:185:28, :187:41]
wire s1_valid_not_nacked = s1_valid & _s1_valid_not_nacked_T; // @[DCache.scala:182:25, :187:{38,41}]
wire _s0_clk_en_T = ~metaArb_io_out_bits_write; // @[DCache.scala:135:28, :190:43]
wire s0_clk_en = metaArb_io_out_valid & _s0_clk_en_T; // @[DCache.scala:135:28, :190:{40,43}]
wire _s1_tlb_req_T = s0_clk_en; // @[DCache.scala:190:40, :208:52]
wire [33:0] _s0_req_addr_T_2; // @[DCache.scala:193:21]
wire [33:0] s0_tlb_req_vaddr = s0_req_addr; // @[DCache.scala:192:24, :199:28]
wire [4:0] s0_tlb_req_cmd = s0_req_cmd; // @[DCache.scala:192:24, :199:28]
wire [1:0] s0_tlb_req_size = s0_req_size; // @[DCache.scala:192:24, :199:28]
wire [1:0] s0_tlb_req_prv = s0_req_dprv; // @[DCache.scala:192:24, :199:28]
wire s0_tlb_req_v = s0_req_dv; // @[DCache.scala:192:24, :199:28]
wire s0_tlb_req_passthrough = s0_req_phys; // @[DCache.scala:192:24, :199:28]
wire [27:0] _s0_req_addr_T = metaArb_io_out_bits_addr[33:6]; // @[DCache.scala:135:28, :193:47]
wire [5:0] _s0_req_addr_T_1 = io_cpu_req_bits_addr_0[5:0]; // @[DCache.scala:101:7, :193:84]
assign _s0_req_addr_T_2 = {_s0_req_addr_T, _s0_req_addr_T_1}; // @[DCache.scala:193:{21,47,84}]
assign s0_req_addr = _s0_req_addr_T_2; // @[DCache.scala:192:24, :193:21]
assign s0_req_phys = ~metaArb_io_in_7_ready | io_cpu_req_bits_phys_0; // @[DCache.scala:101:7, :135:28, :192:24, :195:{9,34,48}]
reg [33:0] s1_req_addr; // @[DCache.scala:196:25]
assign pma_checker_io_req_bits_vaddr = s1_req_addr; // @[DCache.scala:120:32, :196:25]
reg [6:0] s1_req_tag; // @[DCache.scala:196:25]
reg [4:0] s1_req_cmd; // @[DCache.scala:196:25]
assign pma_checker_io_req_bits_cmd = s1_req_cmd; // @[DCache.scala:120:32, :196:25]
reg [1:0] s1_req_size; // @[DCache.scala:196:25]
assign pma_checker_io_req_bits_size = s1_req_size; // @[DCache.scala:120:32, :196:25]
wire [1:0] s1_mask_xwr_size = s1_req_size; // @[DCache.scala:196:25]
reg s1_req_signed; // @[DCache.scala:196:25]
reg [1:0] s1_req_dprv; // @[DCache.scala:196:25]
assign pma_checker_io_req_bits_prv = s1_req_dprv; // @[DCache.scala:120:32, :196:25]
reg s1_req_dv; // @[DCache.scala:196:25]
assign pma_checker_io_req_bits_v = s1_req_dv; // @[DCache.scala:120:32, :196:25]
reg s1_req_phys; // @[DCache.scala:196:25]
reg s1_req_no_resp; // @[DCache.scala:196:25]
reg s1_req_no_xcpt; // @[DCache.scala:196:25]
wire [19:0] _s1_vaddr_T = s1_req_addr[33:14]; // @[DCache.scala:196:25, :197:56]
wire [13:0] _s1_vaddr_T_1 = s1_req_addr[13:0]; // @[DCache.scala:196:25, :197:78]
wire [33:0] s1_vaddr = {_s1_vaddr_T, _s1_vaddr_T_1}; // @[DCache.scala:197:{21,56,78}]
reg [33:0] s1_tlb_req_vaddr; // @[DCache.scala:208:29]
reg s1_tlb_req_passthrough; // @[DCache.scala:208:29]
reg [1:0] s1_tlb_req_size; // @[DCache.scala:208:29]
reg [4:0] s1_tlb_req_cmd; // @[DCache.scala:208:29]
reg [1:0] s1_tlb_req_prv; // @[DCache.scala:208:29]
reg s1_tlb_req_v; // @[DCache.scala:208:29]
wire _GEN_40 = s1_req_cmd == 5'h0; // @[package.scala:16:47]
wire _s1_read_T; // @[package.scala:16:47]
assign _s1_read_T = _GEN_40; // @[package.scala:16:47]
wire _pstore1_rmw_T; // @[package.scala:16:47]
assign _pstore1_rmw_T = _GEN_40; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_1; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_1 = _GEN_40; // @[package.scala:16:47]
wire _GEN_41 = s1_req_cmd == 5'h10; // @[package.scala:16:47]
wire _s1_read_T_1; // @[package.scala:16:47]
assign _s1_read_T_1 = _GEN_41; // @[package.scala:16:47]
wire _pstore1_rmw_T_1; // @[package.scala:16:47]
assign _pstore1_rmw_T_1 = _GEN_41; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_2; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_2 = _GEN_41; // @[package.scala:16:47]
wire _GEN_42 = s1_req_cmd == 5'h6; // @[package.scala:16:47]
wire _s1_read_T_2; // @[package.scala:16:47]
assign _s1_read_T_2 = _GEN_42; // @[package.scala:16:47]
wire _pstore1_rmw_T_2; // @[package.scala:16:47]
assign _pstore1_rmw_T_2 = _GEN_42; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_3; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_3 = _GEN_42; // @[package.scala:16:47]
wire _GEN_43 = s1_req_cmd == 5'h7; // @[package.scala:16:47]
wire _s1_read_T_3; // @[package.scala:16:47]
assign _s1_read_T_3 = _GEN_43; // @[package.scala:16:47]
wire _s1_write_T_3; // @[Consts.scala:90:66]
assign _s1_write_T_3 = _GEN_43; // @[package.scala:16:47]
wire _pstore1_rmw_T_3; // @[package.scala:16:47]
assign _pstore1_rmw_T_3 = _GEN_43; // @[package.scala:16:47]
wire _pstore1_rmw_T_28; // @[Consts.scala:90:66]
assign _pstore1_rmw_T_28 = _GEN_43; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_4; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_4 = _GEN_43; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_29; // @[Consts.scala:90:66]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_29 = _GEN_43; // @[package.scala:16:47]
wire _s1_read_T_4 = _s1_read_T | _s1_read_T_1; // @[package.scala:16:47, :81:59]
wire _s1_read_T_5 = _s1_read_T_4 | _s1_read_T_2; // @[package.scala:16:47, :81:59]
wire _s1_read_T_6 = _s1_read_T_5 | _s1_read_T_3; // @[package.scala:16:47, :81:59]
wire _GEN_44 = s1_req_cmd == 5'h4; // @[package.scala:16:47]
wire _s1_read_T_7; // @[package.scala:16:47]
assign _s1_read_T_7 = _GEN_44; // @[package.scala:16:47]
wire _s1_write_T_5; // @[package.scala:16:47]
assign _s1_write_T_5 = _GEN_44; // @[package.scala:16:47]
wire _pstore1_rmw_T_7; // @[package.scala:16:47]
assign _pstore1_rmw_T_7 = _GEN_44; // @[package.scala:16:47]
wire _pstore1_rmw_T_30; // @[package.scala:16:47]
assign _pstore1_rmw_T_30 = _GEN_44; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_8; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_8 = _GEN_44; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_31; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_31 = _GEN_44; // @[package.scala:16:47]
wire _GEN_45 = s1_req_cmd == 5'h9; // @[package.scala:16:47]
wire _s1_read_T_8; // @[package.scala:16:47]
assign _s1_read_T_8 = _GEN_45; // @[package.scala:16:47]
wire _s1_write_T_6; // @[package.scala:16:47]
assign _s1_write_T_6 = _GEN_45; // @[package.scala:16:47]
wire _pstore1_rmw_T_8; // @[package.scala:16:47]
assign _pstore1_rmw_T_8 = _GEN_45; // @[package.scala:16:47]
wire _pstore1_rmw_T_31; // @[package.scala:16:47]
assign _pstore1_rmw_T_31 = _GEN_45; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_9; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_9 = _GEN_45; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_32; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_32 = _GEN_45; // @[package.scala:16:47]
wire _GEN_46 = s1_req_cmd == 5'hA; // @[package.scala:16:47]
wire _s1_read_T_9; // @[package.scala:16:47]
assign _s1_read_T_9 = _GEN_46; // @[package.scala:16:47]
wire _s1_write_T_7; // @[package.scala:16:47]
assign _s1_write_T_7 = _GEN_46; // @[package.scala:16:47]
wire _pstore1_rmw_T_9; // @[package.scala:16:47]
assign _pstore1_rmw_T_9 = _GEN_46; // @[package.scala:16:47]
wire _pstore1_rmw_T_32; // @[package.scala:16:47]
assign _pstore1_rmw_T_32 = _GEN_46; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_10; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_10 = _GEN_46; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_33; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_33 = _GEN_46; // @[package.scala:16:47]
wire _GEN_47 = s1_req_cmd == 5'hB; // @[package.scala:16:47]
wire _s1_read_T_10; // @[package.scala:16:47]
assign _s1_read_T_10 = _GEN_47; // @[package.scala:16:47]
wire _s1_write_T_8; // @[package.scala:16:47]
assign _s1_write_T_8 = _GEN_47; // @[package.scala:16:47]
wire _pstore1_rmw_T_10; // @[package.scala:16:47]
assign _pstore1_rmw_T_10 = _GEN_47; // @[package.scala:16:47]
wire _pstore1_rmw_T_33; // @[package.scala:16:47]
assign _pstore1_rmw_T_33 = _GEN_47; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_11; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_11 = _GEN_47; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_34; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_34 = _GEN_47; // @[package.scala:16:47]
wire _s1_read_T_11 = _s1_read_T_7 | _s1_read_T_8; // @[package.scala:16:47, :81:59]
wire _s1_read_T_12 = _s1_read_T_11 | _s1_read_T_9; // @[package.scala:16:47, :81:59]
wire _s1_read_T_13 = _s1_read_T_12 | _s1_read_T_10; // @[package.scala:16:47, :81:59]
wire _GEN_48 = s1_req_cmd == 5'h8; // @[package.scala:16:47]
wire _s1_read_T_14; // @[package.scala:16:47]
assign _s1_read_T_14 = _GEN_48; // @[package.scala:16:47]
wire _s1_write_T_12; // @[package.scala:16:47]
assign _s1_write_T_12 = _GEN_48; // @[package.scala:16:47]
wire _pstore1_rmw_T_14; // @[package.scala:16:47]
assign _pstore1_rmw_T_14 = _GEN_48; // @[package.scala:16:47]
wire _pstore1_rmw_T_37; // @[package.scala:16:47]
assign _pstore1_rmw_T_37 = _GEN_48; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_15; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_15 = _GEN_48; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_38; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_38 = _GEN_48; // @[package.scala:16:47]
wire _GEN_49 = s1_req_cmd == 5'hC; // @[package.scala:16:47]
wire _s1_read_T_15; // @[package.scala:16:47]
assign _s1_read_T_15 = _GEN_49; // @[package.scala:16:47]
wire _s1_write_T_13; // @[package.scala:16:47]
assign _s1_write_T_13 = _GEN_49; // @[package.scala:16:47]
wire _pstore1_rmw_T_15; // @[package.scala:16:47]
assign _pstore1_rmw_T_15 = _GEN_49; // @[package.scala:16:47]
wire _pstore1_rmw_T_38; // @[package.scala:16:47]
assign _pstore1_rmw_T_38 = _GEN_49; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_16; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_16 = _GEN_49; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_39; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_39 = _GEN_49; // @[package.scala:16:47]
wire _GEN_50 = s1_req_cmd == 5'hD; // @[package.scala:16:47]
wire _s1_read_T_16; // @[package.scala:16:47]
assign _s1_read_T_16 = _GEN_50; // @[package.scala:16:47]
wire _s1_write_T_14; // @[package.scala:16:47]
assign _s1_write_T_14 = _GEN_50; // @[package.scala:16:47]
wire _pstore1_rmw_T_16; // @[package.scala:16:47]
assign _pstore1_rmw_T_16 = _GEN_50; // @[package.scala:16:47]
wire _pstore1_rmw_T_39; // @[package.scala:16:47]
assign _pstore1_rmw_T_39 = _GEN_50; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_17; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_17 = _GEN_50; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_40; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_40 = _GEN_50; // @[package.scala:16:47]
wire _GEN_51 = s1_req_cmd == 5'hE; // @[package.scala:16:47]
wire _s1_read_T_17; // @[package.scala:16:47]
assign _s1_read_T_17 = _GEN_51; // @[package.scala:16:47]
wire _s1_write_T_15; // @[package.scala:16:47]
assign _s1_write_T_15 = _GEN_51; // @[package.scala:16:47]
wire _pstore1_rmw_T_17; // @[package.scala:16:47]
assign _pstore1_rmw_T_17 = _GEN_51; // @[package.scala:16:47]
wire _pstore1_rmw_T_40; // @[package.scala:16:47]
assign _pstore1_rmw_T_40 = _GEN_51; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_18; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_18 = _GEN_51; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_41; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_41 = _GEN_51; // @[package.scala:16:47]
wire _GEN_52 = s1_req_cmd == 5'hF; // @[package.scala:16:47]
wire _s1_read_T_18; // @[package.scala:16:47]
assign _s1_read_T_18 = _GEN_52; // @[package.scala:16:47]
wire _s1_write_T_16; // @[package.scala:16:47]
assign _s1_write_T_16 = _GEN_52; // @[package.scala:16:47]
wire _pstore1_rmw_T_18; // @[package.scala:16:47]
assign _pstore1_rmw_T_18 = _GEN_52; // @[package.scala:16:47]
wire _pstore1_rmw_T_41; // @[package.scala:16:47]
assign _pstore1_rmw_T_41 = _GEN_52; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_19; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_19 = _GEN_52; // @[package.scala:16:47]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_42; // @[package.scala:16:47]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_42 = _GEN_52; // @[package.scala:16:47]
wire _s1_read_T_19 = _s1_read_T_14 | _s1_read_T_15; // @[package.scala:16:47, :81:59]
wire _s1_read_T_20 = _s1_read_T_19 | _s1_read_T_16; // @[package.scala:16:47, :81:59]
wire _s1_read_T_21 = _s1_read_T_20 | _s1_read_T_17; // @[package.scala:16:47, :81:59]
wire _s1_read_T_22 = _s1_read_T_21 | _s1_read_T_18; // @[package.scala:16:47, :81:59]
wire _s1_read_T_23 = _s1_read_T_13 | _s1_read_T_22; // @[package.scala:81:59]
wire s1_read = _s1_read_T_6 | _s1_read_T_23; // @[package.scala:81:59]
wire _GEN_53 = s1_req_cmd == 5'h1; // @[DCache.scala:196:25]
wire _s1_write_T; // @[Consts.scala:90:32]
assign _s1_write_T = _GEN_53; // @[Consts.scala:90:32]
wire _pstore1_rmw_T_25; // @[Consts.scala:90:32]
assign _pstore1_rmw_T_25 = _GEN_53; // @[Consts.scala:90:32]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_26; // @[Consts.scala:90:32]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_26 = _GEN_53; // @[Consts.scala:90:32]
wire _T_19 = s1_req_cmd == 5'h11; // @[DCache.scala:196:25]
wire _s1_write_T_1; // @[Consts.scala:90:49]
assign _s1_write_T_1 = _T_19; // @[Consts.scala:90:49]
wire _s1_mask_T; // @[DCache.scala:327:32]
assign _s1_mask_T = _T_19; // @[DCache.scala:327:32]
wire _pstore1_rmw_T_26; // @[Consts.scala:90:49]
assign _pstore1_rmw_T_26 = _T_19; // @[Consts.scala:90:49]
wire _pstore1_rmw_T_48; // @[DCache.scala:1191:35]
assign _pstore1_rmw_T_48 = _T_19; // @[DCache.scala:1191:35]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_27; // @[Consts.scala:90:49]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_27 = _T_19; // @[Consts.scala:90:49]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_49; // @[DCache.scala:1191:35]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_49 = _T_19; // @[DCache.scala:1191:35]
wire _s1_write_T_2 = _s1_write_T | _s1_write_T_1; // @[Consts.scala:90:{32,42,49}]
wire _s1_write_T_4 = _s1_write_T_2 | _s1_write_T_3; // @[Consts.scala:90:{42,59,66}]
wire _s1_write_T_9 = _s1_write_T_5 | _s1_write_T_6; // @[package.scala:16:47, :81:59]
wire _s1_write_T_10 = _s1_write_T_9 | _s1_write_T_7; // @[package.scala:16:47, :81:59]
wire _s1_write_T_11 = _s1_write_T_10 | _s1_write_T_8; // @[package.scala:16:47, :81:59]
wire _s1_write_T_17 = _s1_write_T_12 | _s1_write_T_13; // @[package.scala:16:47, :81:59]
wire _s1_write_T_18 = _s1_write_T_17 | _s1_write_T_14; // @[package.scala:16:47, :81:59]
wire _s1_write_T_19 = _s1_write_T_18 | _s1_write_T_15; // @[package.scala:16:47, :81:59]
wire _s1_write_T_20 = _s1_write_T_19 | _s1_write_T_16; // @[package.scala:16:47, :81:59]
wire _s1_write_T_21 = _s1_write_T_11 | _s1_write_T_20; // @[package.scala:81:59]
wire s1_write = _s1_write_T_4 | _s1_write_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire s1_readwrite = s1_read | s1_write; // @[DCache.scala:212:30]
wire _s1_sfence_T = s1_req_cmd == 5'h14; // @[DCache.scala:196:25, :213:30]
wire _GEN_54 = s1_req_cmd == 5'h15; // @[DCache.scala:196:25, :213:57]
wire _s1_sfence_T_1; // @[DCache.scala:213:57]
assign _s1_sfence_T_1 = _GEN_54; // @[DCache.scala:213:57]
wire _tlb_io_sfence_bits_hv_T; // @[DCache.scala:283:39]
assign _tlb_io_sfence_bits_hv_T = _GEN_54; // @[DCache.scala:213:57, :283:39]
wire _s1_sfence_T_2 = _s1_sfence_T | _s1_sfence_T_1; // @[DCache.scala:213:{30,43,57}]
wire _GEN_55 = s1_req_cmd == 5'h16; // @[DCache.scala:196:25, :213:85]
wire _s1_sfence_T_3; // @[DCache.scala:213:85]
assign _s1_sfence_T_3 = _GEN_55; // @[DCache.scala:213:85]
wire _tlb_io_sfence_bits_hg_T; // @[DCache.scala:284:39]
assign _tlb_io_sfence_bits_hg_T = _GEN_55; // @[DCache.scala:213:85, :284:39]
wire s1_sfence = _s1_sfence_T_2 | _s1_sfence_T_3; // @[DCache.scala:213:{43,71,85}]
wire _s1_flush_line_T = s1_req_cmd == 5'h5; // @[DCache.scala:196:25, :214:34]
wire _s1_flush_line_T_1 = s1_req_size[0]; // @[DCache.scala:196:25, :214:64]
wire _tlb_io_sfence_bits_rs1_T = s1_req_size[0]; // @[DCache.scala:196:25, :214:64, :279:40]
wire s1_flush_line = _s1_flush_line_T & _s1_flush_line_T_1; // @[DCache.scala:214:{34,50,64}]
reg s1_flush_valid; // @[DCache.scala:215:27]
reg cached_grant_wait; // @[DCache.scala:223:34]
reg [1:0] refill_way; // @[DCache.scala:229:23]
wire _any_pstore_valid_T; // @[DCache.scala:508:36]
wire any_pstore_valid; // @[DCache.scala:230:30]
assign metaArb_io_in_4_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24]
assign metaArb_io_in_5_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24]
assign metaArb_io_in_6_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24]
assign metaArb_io_in_7_bits_way_en = releaseWay; // @[DCache.scala:135:28, :232:24]
wire _io_cpu_req_ready_T_1 = ~cached_grant_wait; // @[DCache.scala:223:34, :233:54]
wire _io_cpu_req_ready_T_2 = _io_cpu_req_ready_T_1; // @[DCache.scala:233:{51,54}]
wire _io_cpu_req_ready_T_3 = ~s1_nack; // @[DCache.scala:185:28, :187:41, :233:76]
wire _io_cpu_req_ready_T_4 = _io_cpu_req_ready_T_2 & _io_cpu_req_ready_T_3; // @[DCache.scala:233:{51,73,76}]
reg uncachedInFlight_0; // @[DCache.scala:236:33]
wire _s2_valid_cached_miss_T_2 = uncachedInFlight_0; // @[DCache.scala:236:33, :425:88]
wire _s2_valid_uncached_pending_T_1 = uncachedInFlight_0; // @[DCache.scala:236:33, :430:92]
wire _io_cpu_ordered_T_6 = uncachedInFlight_0; // @[DCache.scala:236:33, :929:142]
wire _io_cpu_store_pending_T_24 = uncachedInFlight_0; // @[DCache.scala:236:33, :930:97]
wire _clock_en_reg_T_22 = uncachedInFlight_0; // @[DCache.scala:236:33, :1072:50]
reg [33:0] uncachedReqs_0_addr; // @[DCache.scala:237:25]
wire [33:0] uncachedResp_addr = uncachedReqs_0_addr; // @[DCache.scala:237:25, :238:30]
reg [6:0] uncachedReqs_0_tag; // @[DCache.scala:237:25]
wire [6:0] uncachedResp_tag = uncachedReqs_0_tag; // @[DCache.scala:237:25, :238:30]
reg [4:0] uncachedReqs_0_cmd; // @[DCache.scala:237:25]
wire [4:0] uncachedResp_cmd = uncachedReqs_0_cmd; // @[DCache.scala:237:25, :238:30]
reg [1:0] uncachedReqs_0_size; // @[DCache.scala:237:25]
wire [1:0] uncachedResp_size = uncachedReqs_0_size; // @[DCache.scala:237:25, :238:30]
reg uncachedReqs_0_signed; // @[DCache.scala:237:25]
wire uncachedResp_signed = uncachedReqs_0_signed; // @[DCache.scala:237:25, :238:30]
reg [1:0] uncachedReqs_0_dprv; // @[DCache.scala:237:25]
wire [1:0] uncachedResp_dprv = uncachedReqs_0_dprv; // @[DCache.scala:237:25, :238:30]
reg uncachedReqs_0_dv; // @[DCache.scala:237:25]
wire uncachedResp_dv = uncachedReqs_0_dv; // @[DCache.scala:237:25, :238:30]
reg uncachedReqs_0_phys; // @[DCache.scala:237:25]
wire uncachedResp_phys = uncachedReqs_0_phys; // @[DCache.scala:237:25, :238:30]
reg uncachedReqs_0_no_resp; // @[DCache.scala:237:25]
wire uncachedResp_no_resp = uncachedReqs_0_no_resp; // @[DCache.scala:237:25, :238:30]
reg uncachedReqs_0_no_alloc; // @[DCache.scala:237:25]
wire uncachedResp_no_alloc = uncachedReqs_0_no_alloc; // @[DCache.scala:237:25, :238:30]
reg uncachedReqs_0_no_xcpt; // @[DCache.scala:237:25]
wire uncachedResp_no_xcpt = uncachedReqs_0_no_xcpt; // @[DCache.scala:237:25, :238:30]
reg [63:0] uncachedReqs_0_data; // @[DCache.scala:237:25]
wire [63:0] uncachedResp_data = uncachedReqs_0_data; // @[DCache.scala:237:25, :238:30]
reg [7:0] uncachedReqs_0_mask; // @[DCache.scala:237:25]
wire [7:0] uncachedResp_mask = uncachedReqs_0_mask; // @[DCache.scala:237:25, :238:30]
wire _GEN_56 = io_cpu_req_bits_cmd_0 == 5'h0; // @[package.scala:16:47]
wire _s0_read_T; // @[package.scala:16:47]
assign _s0_read_T = _GEN_56; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T = _GEN_56; // @[package.scala:16:47]
wire _s1_did_read_T; // @[package.scala:16:47]
assign _s1_did_read_T = _GEN_56; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T = _GEN_56; // @[package.scala:16:47]
wire _GEN_57 = io_cpu_req_bits_cmd_0 == 5'h10; // @[package.scala:16:47]
wire _s0_read_T_1; // @[package.scala:16:47]
assign _s0_read_T_1 = _GEN_57; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_1; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_1 = _GEN_57; // @[package.scala:16:47]
wire _s1_did_read_T_1; // @[package.scala:16:47]
assign _s1_did_read_T_1 = _GEN_57; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_1; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_1 = _GEN_57; // @[package.scala:16:47]
wire _GEN_58 = io_cpu_req_bits_cmd_0 == 5'h6; // @[package.scala:16:47]
wire _s0_read_T_2; // @[package.scala:16:47]
assign _s0_read_T_2 = _GEN_58; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_2; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_2 = _GEN_58; // @[package.scala:16:47]
wire _s1_did_read_T_2; // @[package.scala:16:47]
assign _s1_did_read_T_2 = _GEN_58; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_2; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_2 = _GEN_58; // @[package.scala:16:47]
wire _GEN_59 = io_cpu_req_bits_cmd_0 == 5'h7; // @[package.scala:16:47]
wire _s0_read_T_3; // @[package.scala:16:47]
assign _s0_read_T_3 = _GEN_59; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_3; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_3 = _GEN_59; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_28; // @[Consts.scala:90:66]
assign _dataArb_io_in_3_valid_T_28 = _GEN_59; // @[package.scala:16:47]
wire _s1_did_read_T_3; // @[package.scala:16:47]
assign _s1_did_read_T_3 = _GEN_59; // @[package.scala:16:47]
wire _s1_did_read_T_28; // @[Consts.scala:90:66]
assign _s1_did_read_T_28 = _GEN_59; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_3; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_3 = _GEN_59; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_28; // @[Consts.scala:90:66]
assign _pstore_drain_opportunistic_T_28 = _GEN_59; // @[package.scala:16:47]
wire _s0_read_T_4 = _s0_read_T | _s0_read_T_1; // @[package.scala:16:47, :81:59]
wire _s0_read_T_5 = _s0_read_T_4 | _s0_read_T_2; // @[package.scala:16:47, :81:59]
wire _s0_read_T_6 = _s0_read_T_5 | _s0_read_T_3; // @[package.scala:16:47, :81:59]
wire _GEN_60 = io_cpu_req_bits_cmd_0 == 5'h4; // @[package.scala:16:47]
wire _s0_read_T_7; // @[package.scala:16:47]
assign _s0_read_T_7 = _GEN_60; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_7; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_7 = _GEN_60; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_30; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_30 = _GEN_60; // @[package.scala:16:47]
wire _s1_did_read_T_7; // @[package.scala:16:47]
assign _s1_did_read_T_7 = _GEN_60; // @[package.scala:16:47]
wire _s1_did_read_T_30; // @[package.scala:16:47]
assign _s1_did_read_T_30 = _GEN_60; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_7; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_7 = _GEN_60; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_30; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_30 = _GEN_60; // @[package.scala:16:47]
wire _GEN_61 = io_cpu_req_bits_cmd_0 == 5'h9; // @[package.scala:16:47]
wire _s0_read_T_8; // @[package.scala:16:47]
assign _s0_read_T_8 = _GEN_61; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_8; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_8 = _GEN_61; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_31; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_31 = _GEN_61; // @[package.scala:16:47]
wire _s1_did_read_T_8; // @[package.scala:16:47]
assign _s1_did_read_T_8 = _GEN_61; // @[package.scala:16:47]
wire _s1_did_read_T_31; // @[package.scala:16:47]
assign _s1_did_read_T_31 = _GEN_61; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_8; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_8 = _GEN_61; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_31; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_31 = _GEN_61; // @[package.scala:16:47]
wire _GEN_62 = io_cpu_req_bits_cmd_0 == 5'hA; // @[package.scala:16:47]
wire _s0_read_T_9; // @[package.scala:16:47]
assign _s0_read_T_9 = _GEN_62; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_9; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_9 = _GEN_62; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_32; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_32 = _GEN_62; // @[package.scala:16:47]
wire _s1_did_read_T_9; // @[package.scala:16:47]
assign _s1_did_read_T_9 = _GEN_62; // @[package.scala:16:47]
wire _s1_did_read_T_32; // @[package.scala:16:47]
assign _s1_did_read_T_32 = _GEN_62; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_9; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_9 = _GEN_62; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_32; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_32 = _GEN_62; // @[package.scala:16:47]
wire _GEN_63 = io_cpu_req_bits_cmd_0 == 5'hB; // @[package.scala:16:47]
wire _s0_read_T_10; // @[package.scala:16:47]
assign _s0_read_T_10 = _GEN_63; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_10; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_10 = _GEN_63; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_33; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_33 = _GEN_63; // @[package.scala:16:47]
wire _s1_did_read_T_10; // @[package.scala:16:47]
assign _s1_did_read_T_10 = _GEN_63; // @[package.scala:16:47]
wire _s1_did_read_T_33; // @[package.scala:16:47]
assign _s1_did_read_T_33 = _GEN_63; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_10; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_10 = _GEN_63; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_33; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_33 = _GEN_63; // @[package.scala:16:47]
wire _s0_read_T_11 = _s0_read_T_7 | _s0_read_T_8; // @[package.scala:16:47, :81:59]
wire _s0_read_T_12 = _s0_read_T_11 | _s0_read_T_9; // @[package.scala:16:47, :81:59]
wire _s0_read_T_13 = _s0_read_T_12 | _s0_read_T_10; // @[package.scala:16:47, :81:59]
wire _GEN_64 = io_cpu_req_bits_cmd_0 == 5'h8; // @[package.scala:16:47]
wire _s0_read_T_14; // @[package.scala:16:47]
assign _s0_read_T_14 = _GEN_64; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_14; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_14 = _GEN_64; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_37; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_37 = _GEN_64; // @[package.scala:16:47]
wire _s1_did_read_T_14; // @[package.scala:16:47]
assign _s1_did_read_T_14 = _GEN_64; // @[package.scala:16:47]
wire _s1_did_read_T_37; // @[package.scala:16:47]
assign _s1_did_read_T_37 = _GEN_64; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_14; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_14 = _GEN_64; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_37; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_37 = _GEN_64; // @[package.scala:16:47]
wire _GEN_65 = io_cpu_req_bits_cmd_0 == 5'hC; // @[package.scala:16:47]
wire _s0_read_T_15; // @[package.scala:16:47]
assign _s0_read_T_15 = _GEN_65; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_15; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_15 = _GEN_65; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_38; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_38 = _GEN_65; // @[package.scala:16:47]
wire _s1_did_read_T_15; // @[package.scala:16:47]
assign _s1_did_read_T_15 = _GEN_65; // @[package.scala:16:47]
wire _s1_did_read_T_38; // @[package.scala:16:47]
assign _s1_did_read_T_38 = _GEN_65; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_15; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_15 = _GEN_65; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_38; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_38 = _GEN_65; // @[package.scala:16:47]
wire _GEN_66 = io_cpu_req_bits_cmd_0 == 5'hD; // @[package.scala:16:47]
wire _s0_read_T_16; // @[package.scala:16:47]
assign _s0_read_T_16 = _GEN_66; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_16; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_16 = _GEN_66; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_39; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_39 = _GEN_66; // @[package.scala:16:47]
wire _s1_did_read_T_16; // @[package.scala:16:47]
assign _s1_did_read_T_16 = _GEN_66; // @[package.scala:16:47]
wire _s1_did_read_T_39; // @[package.scala:16:47]
assign _s1_did_read_T_39 = _GEN_66; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_16; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_16 = _GEN_66; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_39; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_39 = _GEN_66; // @[package.scala:16:47]
wire _GEN_67 = io_cpu_req_bits_cmd_0 == 5'hE; // @[package.scala:16:47]
wire _s0_read_T_17; // @[package.scala:16:47]
assign _s0_read_T_17 = _GEN_67; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_17; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_17 = _GEN_67; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_40; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_40 = _GEN_67; // @[package.scala:16:47]
wire _s1_did_read_T_17; // @[package.scala:16:47]
assign _s1_did_read_T_17 = _GEN_67; // @[package.scala:16:47]
wire _s1_did_read_T_40; // @[package.scala:16:47]
assign _s1_did_read_T_40 = _GEN_67; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_17; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_17 = _GEN_67; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_40; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_40 = _GEN_67; // @[package.scala:16:47]
wire _GEN_68 = io_cpu_req_bits_cmd_0 == 5'hF; // @[package.scala:16:47]
wire _s0_read_T_18; // @[package.scala:16:47]
assign _s0_read_T_18 = _GEN_68; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_18; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_18 = _GEN_68; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_41; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_T_41 = _GEN_68; // @[package.scala:16:47]
wire _s1_did_read_T_18; // @[package.scala:16:47]
assign _s1_did_read_T_18 = _GEN_68; // @[package.scala:16:47]
wire _s1_did_read_T_41; // @[package.scala:16:47]
assign _s1_did_read_T_41 = _GEN_68; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_18; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_18 = _GEN_68; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_41; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_T_41 = _GEN_68; // @[package.scala:16:47]
wire _s0_read_T_19 = _s0_read_T_14 | _s0_read_T_15; // @[package.scala:16:47, :81:59]
wire _s0_read_T_20 = _s0_read_T_19 | _s0_read_T_16; // @[package.scala:16:47, :81:59]
wire _s0_read_T_21 = _s0_read_T_20 | _s0_read_T_17; // @[package.scala:16:47, :81:59]
wire _s0_read_T_22 = _s0_read_T_21 | _s0_read_T_18; // @[package.scala:16:47, :81:59]
wire _s0_read_T_23 = _s0_read_T_13 | _s0_read_T_22; // @[package.scala:81:59]
wire s0_read = _s0_read_T_6 | _s0_read_T_23; // @[package.scala:81:59]
wire _GEN_69 = io_cpu_req_bits_cmd_0 == 5'h1; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_res_T; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_res_T = _GEN_69; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_T_25; // @[Consts.scala:90:32]
assign _dataArb_io_in_3_valid_T_25 = _GEN_69; // @[package.scala:16:47]
wire _s1_did_read_T_25; // @[Consts.scala:90:32]
assign _s1_did_read_T_25 = _GEN_69; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_res_T; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_res_T = _GEN_69; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_T_25; // @[Consts.scala:90:32]
assign _pstore_drain_opportunistic_T_25 = _GEN_69; // @[package.scala:16:47]
wire _GEN_70 = io_cpu_req_bits_cmd_0 == 5'h3; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_res_T_1; // @[package.scala:16:47]
assign _dataArb_io_in_3_valid_res_T_1 = _GEN_70; // @[package.scala:16:47]
wire _pstore_drain_opportunistic_res_T_1; // @[package.scala:16:47]
assign _pstore_drain_opportunistic_res_T_1 = _GEN_70; // @[package.scala:16:47]
wire _dataArb_io_in_3_valid_res_T_2 = _dataArb_io_in_3_valid_res_T | _dataArb_io_in_3_valid_res_T_1; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_res_T_3 = ~_dataArb_io_in_3_valid_res_T_2; // @[package.scala:81:59]
wire dataArb_io_in_3_valid_res = _dataArb_io_in_3_valid_res_T_3; // @[DCache.scala:1185:{15,46}]
wire _dataArb_io_in_3_valid_T_4 = _dataArb_io_in_3_valid_T | _dataArb_io_in_3_valid_T_1; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_5 = _dataArb_io_in_3_valid_T_4 | _dataArb_io_in_3_valid_T_2; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_6 = _dataArb_io_in_3_valid_T_5 | _dataArb_io_in_3_valid_T_3; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_11 = _dataArb_io_in_3_valid_T_7 | _dataArb_io_in_3_valid_T_8; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_12 = _dataArb_io_in_3_valid_T_11 | _dataArb_io_in_3_valid_T_9; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_13 = _dataArb_io_in_3_valid_T_12 | _dataArb_io_in_3_valid_T_10; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_19 = _dataArb_io_in_3_valid_T_14 | _dataArb_io_in_3_valid_T_15; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_20 = _dataArb_io_in_3_valid_T_19 | _dataArb_io_in_3_valid_T_16; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_21 = _dataArb_io_in_3_valid_T_20 | _dataArb_io_in_3_valid_T_17; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_22 = _dataArb_io_in_3_valid_T_21 | _dataArb_io_in_3_valid_T_18; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_23 = _dataArb_io_in_3_valid_T_13 | _dataArb_io_in_3_valid_T_22; // @[package.scala:81:59]
wire _dataArb_io_in_3_valid_T_24 = _dataArb_io_in_3_valid_T_6 | _dataArb_io_in_3_valid_T_23; // @[package.scala:81:59]
wire _GEN_71 = io_cpu_req_bits_cmd_0 == 5'h11; // @[DCache.scala:101:7]
wire _dataArb_io_in_3_valid_T_26; // @[Consts.scala:90:49]
assign _dataArb_io_in_3_valid_T_26 = _GEN_71; // @[Consts.scala:90:49]
wire _dataArb_io_in_3_valid_T_48; // @[DCache.scala:1191:35]
assign _dataArb_io_in_3_valid_T_48 = _GEN_71; // @[DCache.scala:1191:35]
wire _s1_did_read_T_26; // @[Consts.scala:90:49]
assign _s1_did_read_T_26 = _GEN_71; // @[Consts.scala:90:49]
wire _s1_did_read_T_48; // @[DCache.scala:1191:35]
assign _s1_did_read_T_48 = _GEN_71; // @[DCache.scala:1191:35]
wire _pstore_drain_opportunistic_T_26; // @[Consts.scala:90:49]
assign _pstore_drain_opportunistic_T_26 = _GEN_71; // @[Consts.scala:90:49]
wire _pstore_drain_opportunistic_T_48; // @[DCache.scala:1191:35]
assign _pstore_drain_opportunistic_T_48 = _GEN_71; // @[DCache.scala:1191:35]
wire _dataArb_io_in_3_valid_T_27 = _dataArb_io_in_3_valid_T_25 | _dataArb_io_in_3_valid_T_26; // @[Consts.scala:90:{32,42,49}]
wire _dataArb_io_in_3_valid_T_29 = _dataArb_io_in_3_valid_T_27 | _dataArb_io_in_3_valid_T_28; // @[Consts.scala:90:{42,59,66}]
wire _dataArb_io_in_3_valid_T_34 = _dataArb_io_in_3_valid_T_30 | _dataArb_io_in_3_valid_T_31; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_35 = _dataArb_io_in_3_valid_T_34 | _dataArb_io_in_3_valid_T_32; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_36 = _dataArb_io_in_3_valid_T_35 | _dataArb_io_in_3_valid_T_33; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_42 = _dataArb_io_in_3_valid_T_37 | _dataArb_io_in_3_valid_T_38; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_43 = _dataArb_io_in_3_valid_T_42 | _dataArb_io_in_3_valid_T_39; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_44 = _dataArb_io_in_3_valid_T_43 | _dataArb_io_in_3_valid_T_40; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_45 = _dataArb_io_in_3_valid_T_44 | _dataArb_io_in_3_valid_T_41; // @[package.scala:16:47, :81:59]
wire _dataArb_io_in_3_valid_T_46 = _dataArb_io_in_3_valid_T_36 | _dataArb_io_in_3_valid_T_45; // @[package.scala:81:59]
wire _dataArb_io_in_3_valid_T_47 = _dataArb_io_in_3_valid_T_29 | _dataArb_io_in_3_valid_T_46; // @[Consts.scala:87:44, :90:{59,76}]
wire _dataArb_io_in_3_valid_T_50 = _dataArb_io_in_3_valid_T_48; // @[DCache.scala:1191:{35,45}]
wire _dataArb_io_in_3_valid_T_51 = _dataArb_io_in_3_valid_T_47 & _dataArb_io_in_3_valid_T_50; // @[DCache.scala:1191:{23,45}]
wire _dataArb_io_in_3_valid_T_52 = _dataArb_io_in_3_valid_T_24 | _dataArb_io_in_3_valid_T_51; // @[DCache.scala:1190:21, :1191:23]
wire _dataArb_io_in_3_valid_T_53 = ~_dataArb_io_in_3_valid_T_52; // @[DCache.scala:1186:12, :1190:21]
wire _dataArb_io_in_3_valid_T_54 = _dataArb_io_in_3_valid_T_53 | dataArb_io_in_3_valid_res; // @[DCache.scala:1185:46, :1186:{12,28}]
wire _dataArb_io_in_3_valid_T_56 = ~_dataArb_io_in_3_valid_T_55; // @[DCache.scala:1186:11]
wire _dataArb_io_in_3_valid_T_57 = ~_dataArb_io_in_3_valid_T_54; // @[DCache.scala:1186:{11,28}]
assign _dataArb_io_in_3_valid_T_58 = io_cpu_req_valid_0 & dataArb_io_in_3_valid_res; // @[DCache.scala:101:7, :242:46, :1185:46]
assign dataArb_io_in_3_valid = _dataArb_io_in_3_valid_T_58; // @[DCache.scala:152:28, :242:46]
wire [19:0] _dataArb_io_in_3_bits_addr_T = io_cpu_req_bits_addr_0[33:14]; // @[DCache.scala:101:7, :245:89]
wire [19:0] _metaArb_io_in_1_bits_addr_T = io_cpu_req_bits_addr_0[33:14]; // @[DCache.scala:101:7, :245:89, :454:58]
wire [19:0] _metaArb_io_in_2_bits_addr_T = io_cpu_req_bits_addr_0[33:14]; // @[DCache.scala:101:7, :245:89, :466:58]
wire [19:0] _metaArb_io_in_3_bits_addr_T = io_cpu_req_bits_addr_0[33:14]; // @[DCache.scala:101:7, :245:89, :745:58]
wire [19:0] _metaArb_io_in_4_bits_addr_T = io_cpu_req_bits_addr_0[33:14]; // @[DCache.scala:101:7, :245:89, :912:58]
wire [19:0] _metaArb_io_in_5_bits_addr_T = io_cpu_req_bits_addr_0[33:14]; // @[DCache.scala:101:7, :245:89, :1018:58]
wire [13:0] _dataArb_io_in_3_bits_addr_T_1 = io_cpu_req_bits_addr_0[13:0]; // @[DCache.scala:101:7, :245:120]
wire [33:0] _dataArb_io_in_3_bits_addr_T_2 = {_dataArb_io_in_3_bits_addr_T, _dataArb_io_in_3_bits_addr_T_1}; // @[DCache.scala:245:{36,89,120}]
assign dataArb_io_in_3_bits_addr = _dataArb_io_in_3_bits_addr_T_2[13:0]; // @[DCache.scala:152:28, :245:{30,36}]
wire _T_4 = ~dataArb_io_in_3_ready & s0_read; // @[DCache.scala:152:28, :258:{9,33}]
wire _s1_did_read_T_4 = _s1_did_read_T | _s1_did_read_T_1; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_5 = _s1_did_read_T_4 | _s1_did_read_T_2; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_6 = _s1_did_read_T_5 | _s1_did_read_T_3; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_11 = _s1_did_read_T_7 | _s1_did_read_T_8; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_12 = _s1_did_read_T_11 | _s1_did_read_T_9; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_13 = _s1_did_read_T_12 | _s1_did_read_T_10; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_19 = _s1_did_read_T_14 | _s1_did_read_T_15; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_20 = _s1_did_read_T_19 | _s1_did_read_T_16; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_21 = _s1_did_read_T_20 | _s1_did_read_T_17; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_22 = _s1_did_read_T_21 | _s1_did_read_T_18; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_23 = _s1_did_read_T_13 | _s1_did_read_T_22; // @[package.scala:81:59]
wire _s1_did_read_T_24 = _s1_did_read_T_6 | _s1_did_read_T_23; // @[package.scala:81:59]
wire _s1_did_read_T_27 = _s1_did_read_T_25 | _s1_did_read_T_26; // @[Consts.scala:90:{32,42,49}]
wire _s1_did_read_T_29 = _s1_did_read_T_27 | _s1_did_read_T_28; // @[Consts.scala:90:{42,59,66}]
wire _s1_did_read_T_34 = _s1_did_read_T_30 | _s1_did_read_T_31; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_35 = _s1_did_read_T_34 | _s1_did_read_T_32; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_36 = _s1_did_read_T_35 | _s1_did_read_T_33; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_42 = _s1_did_read_T_37 | _s1_did_read_T_38; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_43 = _s1_did_read_T_42 | _s1_did_read_T_39; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_44 = _s1_did_read_T_43 | _s1_did_read_T_40; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_45 = _s1_did_read_T_44 | _s1_did_read_T_41; // @[package.scala:16:47, :81:59]
wire _s1_did_read_T_46 = _s1_did_read_T_36 | _s1_did_read_T_45; // @[package.scala:81:59]
wire _s1_did_read_T_47 = _s1_did_read_T_29 | _s1_did_read_T_46; // @[Consts.scala:87:44, :90:{59,76}]
wire _s1_did_read_T_50 = _s1_did_read_T_48; // @[DCache.scala:1191:{35,45}]
wire _s1_did_read_T_51 = _s1_did_read_T_47 & _s1_did_read_T_50; // @[DCache.scala:1191:{23,45}]
wire _s1_did_read_T_52 = _s1_did_read_T_24 | _s1_did_read_T_51; // @[DCache.scala:1190:21, :1191:23]
wire _s1_did_read_T_53 = io_cpu_req_valid_0 & _s1_did_read_T_52; // @[DCache.scala:101:7, :259:75, :1190:21]
wire _s1_did_read_T_54 = dataArb_io_in_3_ready & _s1_did_read_T_53; // @[DCache.scala:152:28, :259:{54,75}]
reg s1_did_read; // @[DCache.scala:259:30]
wire _s2_data_word_en_T = s1_did_read; // @[DCache.scala:259:30, :367:63]
assign _metaArb_io_in_7_bits_idx_T = _dataArb_io_in_3_bits_addr_T_2[13:6]; // @[DCache.scala:245:36, :263:58]
assign metaArb_io_in_7_bits_idx = _metaArb_io_in_7_bits_idx_T; // @[DCache.scala:135:28, :263:58]
wire _s1_cmd_uses_tlb_T = s1_readwrite | s1_flush_line; // @[DCache.scala:212:30, :214:50, :270:38]
wire _s1_cmd_uses_tlb_T_1 = s1_req_cmd == 5'h17; // @[DCache.scala:196:25, :270:69]
wire s1_cmd_uses_tlb = _s1_cmd_uses_tlb_T | _s1_cmd_uses_tlb_T_1; // @[DCache.scala:270:{38,55,69}]
wire _tlb_io_req_valid_T = ~io_cpu_s1_kill_0; // @[DCache.scala:101:7, :186:37, :273:55]
wire _tlb_io_req_valid_T_1 = s1_valid & _tlb_io_req_valid_T; // @[DCache.scala:182:25, :273:{52,55}]
wire _tlb_io_req_valid_T_2 = _tlb_io_req_valid_T_1 & s1_cmd_uses_tlb; // @[DCache.scala:270:55, :273:{52,71}]
wire _tlb_io_req_valid_T_3 = _tlb_io_req_valid_T_2; // @[DCache.scala:273:{40,71}]
wire _tlb_io_sfence_valid_T = ~io_cpu_s1_kill_0; // @[DCache.scala:101:7, :186:37, :278:38]
wire _tlb_io_sfence_valid_T_1 = s1_valid & _tlb_io_sfence_valid_T; // @[DCache.scala:182:25, :278:{35,38}]
wire _tlb_io_sfence_valid_T_2 = _tlb_io_sfence_valid_T_1 & s1_sfence; // @[DCache.scala:213:71, :278:{35,54}]
wire _tlb_io_sfence_bits_rs2_T = s1_req_size[1]; // @[DCache.scala:196:25, :280:40]
wire [19:0] _s1_paddr_T = s1_req_addr[31:12]; // @[DCache.scala:196:25, :298:55]
wire [19:0] _s1_paddr_T_1 = _tlb_io_resp_paddr[31:12]; // @[DCache.scala:119:19, :298:99]
wire [19:0] _s1_paddr_T_2 = _s1_paddr_T_1; // @[DCache.scala:298:{25,99}]
wire [11:0] _s1_paddr_T_3 = s1_req_addr[11:0]; // @[DCache.scala:196:25, :298:125]
wire [31:0] s1_paddr = {_s1_paddr_T_2, _s1_paddr_T_3}; // @[DCache.scala:298:{21,25,125}]
wire _baseAddr_T = ~hartIdSinkNodeOptIn; // @[LookupByHartId.scala:18:71]
wire _inScratchpad_T = s1_paddr[31]; // @[DCache.scala:298:21, :303:35]
wire _inScratchpad_T_3 = s1_paddr < 32'h80004000; // @[DCache.scala:298:21, :303:59]
wire s1_hit_way = _inScratchpad_T & _inScratchpad_T_3; // @[DCache.scala:303:{35,47,59}]
wire [1:0] s1_hit_state_state = {2{s1_hit_way}}; // @[DCache.scala:303:47, :304:25]
wire [1:0] s1_data_way; // @[DCache.scala:323:32]
wire [7:0] _tl_d_data_encoded_T = nodeOut_d_bits_data[7:0]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_14 = nodeOut_d_bits_data[7:0]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_1 = nodeOut_d_bits_data[15:8]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_15 = nodeOut_d_bits_data[15:8]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_2 = nodeOut_d_bits_data[23:16]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_16 = nodeOut_d_bits_data[23:16]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_3 = nodeOut_d_bits_data[31:24]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_17 = nodeOut_d_bits_data[31:24]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_4 = nodeOut_d_bits_data[39:32]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_18 = nodeOut_d_bits_data[39:32]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_5 = nodeOut_d_bits_data[47:40]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_19 = nodeOut_d_bits_data[47:40]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_6 = nodeOut_d_bits_data[55:48]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_20 = nodeOut_d_bits_data[55:48]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_7 = nodeOut_d_bits_data[63:56]; // @[package.scala:211:50]
wire [7:0] _tl_d_data_encoded_T_21 = nodeOut_d_bits_data[63:56]; // @[package.scala:211:50]
wire [15:0] tl_d_data_encoded_lo_lo = {_tl_d_data_encoded_T_1, _tl_d_data_encoded_T}; // @[package.scala:45:27, :211:50]
wire [15:0] tl_d_data_encoded_lo_hi = {_tl_d_data_encoded_T_3, _tl_d_data_encoded_T_2}; // @[package.scala:45:27, :211:50]
wire [31:0] tl_d_data_encoded_lo = {tl_d_data_encoded_lo_hi, tl_d_data_encoded_lo_lo}; // @[package.scala:45:27]
wire [15:0] tl_d_data_encoded_hi_lo = {_tl_d_data_encoded_T_5, _tl_d_data_encoded_T_4}; // @[package.scala:45:27, :211:50]
wire [15:0] tl_d_data_encoded_hi_hi = {_tl_d_data_encoded_T_7, _tl_d_data_encoded_T_6}; // @[package.scala:45:27, :211:50]
wire [31:0] tl_d_data_encoded_hi = {tl_d_data_encoded_hi_hi, tl_d_data_encoded_hi_lo}; // @[package.scala:45:27]
wire [63:0] _tl_d_data_encoded_T_8 = {tl_d_data_encoded_hi, tl_d_data_encoded_lo}; // @[package.scala:45:27]
wire [63:0] _tl_d_data_encoded_T_22; // @[package.scala:45:27]
wire [63:0] tl_d_data_encoded; // @[DCache.scala:324:31]
wire [63:0] s1_all_data_ways_1 = tl_d_data_encoded; // @[DCache.scala:324:31, :325:33]
wire [63:0] s2_data_s1_way_words_0_0 = s1_all_data_ways_0; // @[package.scala:211:50]
wire [63:0] s2_data_s1_way_words_1_0 = s1_all_data_ways_1; // @[package.scala:211:50]
wire _s1_mask_xwr_upper_T = s1_req_addr[0]; // @[DCache.scala:196:25]
wire _s1_mask_xwr_lower_T = s1_req_addr[0]; // @[DCache.scala:196:25]
wire _s1_mask_xwr_upper_T_1 = _s1_mask_xwr_upper_T; // @[AMOALU.scala:20:{22,27}]
wire _s1_mask_xwr_upper_T_2 = |s1_mask_xwr_size; // @[AMOALU.scala:11:18, :20:53]
wire _s1_mask_xwr_upper_T_3 = _s1_mask_xwr_upper_T_2; // @[AMOALU.scala:20:{47,53}]
wire s1_mask_xwr_upper = _s1_mask_xwr_upper_T_1 | _s1_mask_xwr_upper_T_3; // @[AMOALU.scala:20:{22,42,47}]
wire s1_mask_xwr_lower = ~_s1_mask_xwr_lower_T; // @[AMOALU.scala:21:{22,27}]
wire [1:0] _s1_mask_xwr_T = {s1_mask_xwr_upper, s1_mask_xwr_lower}; // @[AMOALU.scala:20:42, :21:22, :22:16]
wire _s1_mask_xwr_upper_T_4 = s1_req_addr[1]; // @[DCache.scala:196:25]
wire _s1_mask_xwr_lower_T_1 = s1_req_addr[1]; // @[DCache.scala:196:25]
wire [1:0] _s1_mask_xwr_upper_T_5 = _s1_mask_xwr_upper_T_4 ? _s1_mask_xwr_T : 2'h0; // @[AMOALU.scala:20:{22,27}, :22:16]
wire _s1_mask_xwr_upper_T_6 = s1_mask_xwr_size[1]; // @[AMOALU.scala:11:18, :20:53]
wire [1:0] _s1_mask_xwr_upper_T_7 = {2{_s1_mask_xwr_upper_T_6}}; // @[AMOALU.scala:20:{47,53}]
wire [1:0] s1_mask_xwr_upper_1 = _s1_mask_xwr_upper_T_5 | _s1_mask_xwr_upper_T_7; // @[AMOALU.scala:20:{22,42,47}]
wire [1:0] s1_mask_xwr_lower_1 = _s1_mask_xwr_lower_T_1 ? 2'h0 : _s1_mask_xwr_T; // @[AMOALU.scala:21:{22,27}, :22:16]
wire [3:0] _s1_mask_xwr_T_1 = {s1_mask_xwr_upper_1, s1_mask_xwr_lower_1}; // @[AMOALU.scala:20:42, :21:22, :22:16]
wire _s1_mask_xwr_upper_T_8 = s1_req_addr[2]; // @[DCache.scala:196:25]
wire _s1_mask_xwr_lower_T_2 = s1_req_addr[2]; // @[DCache.scala:196:25]
wire [3:0] _s1_mask_xwr_upper_T_9 = _s1_mask_xwr_upper_T_8 ? _s1_mask_xwr_T_1 : 4'h0; // @[AMOALU.scala:20:{22,27}, :22:16]
wire _s1_mask_xwr_upper_T_10 = &s1_mask_xwr_size; // @[AMOALU.scala:11:18, :20:53]
wire [3:0] _s1_mask_xwr_upper_T_11 = {4{_s1_mask_xwr_upper_T_10}}; // @[AMOALU.scala:20:{47,53}]
wire [3:0] s1_mask_xwr_upper_2 = _s1_mask_xwr_upper_T_9 | _s1_mask_xwr_upper_T_11; // @[AMOALU.scala:20:{22,42,47}]
wire [3:0] s1_mask_xwr_lower_2 = _s1_mask_xwr_lower_T_2 ? 4'h0 : _s1_mask_xwr_T_1; // @[AMOALU.scala:21:{22,27}, :22:16]
wire [7:0] s1_mask_xwr = {s1_mask_xwr_upper_2, s1_mask_xwr_lower_2}; // @[AMOALU.scala:20:42, :21:22, :22:16]
wire [7:0] s1_mask = _s1_mask_T ? io_cpu_s1_data_mask_0 : s1_mask_xwr; // @[DCache.scala:101:7, :327:{20,32}]
wire _s2_valid_T = ~s1_sfence; // @[DCache.scala:213:71, :331:45]
wire _s2_valid_T_1 = s1_valid_masked & _s2_valid_T; // @[DCache.scala:186:34, :331:{42,45}]
reg s2_valid; // @[DCache.scala:331:25]
wire [1:0] _s2_valid_no_xcpt_T = {io_cpu_s2_xcpt_ae_ld_0, io_cpu_s2_xcpt_ae_st_0}; // @[DCache.scala:101:7, :332:54]
wire [1:0] _s2_valid_no_xcpt_T_2 = {io_cpu_s2_xcpt_pf_ld_0, io_cpu_s2_xcpt_pf_st_0}; // @[DCache.scala:101:7, :332:54]
wire [1:0] _s2_valid_no_xcpt_T_3 = {io_cpu_s2_xcpt_ma_ld_0, io_cpu_s2_xcpt_ma_st_0}; // @[DCache.scala:101:7, :332:54]
wire [3:0] s2_valid_no_xcpt_lo = {2'h0, _s2_valid_no_xcpt_T}; // @[DCache.scala:332:54]
wire [3:0] s2_valid_no_xcpt_hi = {_s2_valid_no_xcpt_T_3, _s2_valid_no_xcpt_T_2}; // @[DCache.scala:332:54]
wire [7:0] _s2_valid_no_xcpt_T_4 = {s2_valid_no_xcpt_hi, s2_valid_no_xcpt_lo}; // @[DCache.scala:332:54]
wire _s2_valid_no_xcpt_T_5 = |_s2_valid_no_xcpt_T_4; // @[DCache.scala:332:{54,61}]
wire _s2_valid_no_xcpt_T_6 = ~_s2_valid_no_xcpt_T_5; // @[DCache.scala:332:{38,61}]
wire s2_valid_no_xcpt = s2_valid & _s2_valid_no_xcpt_T_6; // @[DCache.scala:331:25, :332:{35,38}]
wire _s2_not_nacked_in_s1_T = ~s1_nack; // @[DCache.scala:185:28, :187:41, :335:37]
reg s2_not_nacked_in_s1; // @[DCache.scala:335:36]
wire s2_valid_not_nacked_in_s1 = s2_valid & s2_not_nacked_in_s1; // @[DCache.scala:331:25, :335:36, :336:44]
wire s2_valid_masked = s2_valid_no_xcpt & s2_not_nacked_in_s1; // @[DCache.scala:332:35, :335:36, :337:42]
wire s2_valid_not_killed = s2_valid_masked; // @[DCache.scala:337:42, :338:45]
wire _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T_1 = s2_valid_masked; // @[DCache.scala:337:42, :397:71]
wire _s2_dont_nack_misc_T_1 = s2_valid_masked; // @[DCache.scala:337:42, :441:43]
reg [33:0] s2_req_addr; // @[DCache.scala:339:19]
wire [33:0] _get_legal_T_14 = s2_req_addr; // @[DCache.scala:339:19]
wire [33:0] _put_legal_T_14 = s2_req_addr; // @[DCache.scala:339:19]
wire [33:0] _putpartial_legal_T_14 = s2_req_addr; // @[DCache.scala:339:19]
wire [33:0] _atomics_legal_T_4 = s2_req_addr; // @[DCache.scala:339:19]
wire [33:0] _atomics_legal_T_40 = s2_req_addr; // @[DCache.scala:339:19]
wire [33:0] _atomics_legal_T_76 = s2_req_addr; // @[DCache.scala:339:19]
wire [33:0] _atomics_legal_T_112 = s2_req_addr; // @[DCache.scala:339:19]
wire [33:0] _atomics_legal_T_148 = s2_req_addr; // @[DCache.scala:339:19]
wire [33:0] _atomics_legal_T_184 = s2_req_addr; // @[DCache.scala:339:19]
wire [33:0] _atomics_legal_T_220 = s2_req_addr; // @[DCache.scala:339:19]
wire [33:0] _atomics_legal_T_256 = s2_req_addr; // @[DCache.scala:339:19]
wire [33:0] _atomics_legal_T_292 = s2_req_addr; // @[DCache.scala:339:19]
wire [33:0] _tl_out_a_valid_T_1 = s2_req_addr; // @[DCache.scala:339:19, :606:43]
reg [6:0] s2_req_tag; // @[DCache.scala:339:19]
assign io_cpu_resp_bits_tag_0 = s2_req_tag; // @[DCache.scala:101:7, :339:19]
reg [4:0] s2_req_cmd; // @[DCache.scala:339:19]
assign io_cpu_resp_bits_cmd_0 = s2_req_cmd; // @[DCache.scala:101:7, :339:19]
reg [1:0] s2_req_size; // @[DCache.scala:339:19]
assign io_cpu_resp_bits_size_0 = s2_req_size; // @[DCache.scala:101:7, :339:19]
wire [1:0] size = s2_req_size; // @[DCache.scala:339:19]
reg s2_req_signed; // @[DCache.scala:339:19]
assign io_cpu_resp_bits_signed_0 = s2_req_signed; // @[DCache.scala:101:7, :339:19]
reg [1:0] s2_req_dprv; // @[DCache.scala:339:19]
assign io_cpu_resp_bits_dprv_0 = s2_req_dprv; // @[DCache.scala:101:7, :339:19]
reg s2_req_dv; // @[DCache.scala:339:19]
assign io_cpu_resp_bits_dv_0 = s2_req_dv; // @[DCache.scala:101:7, :339:19]
reg s2_req_phys; // @[DCache.scala:339:19]
reg s2_req_no_resp; // @[DCache.scala:339:19]
reg s2_req_no_alloc; // @[DCache.scala:339:19]
reg s2_req_no_xcpt; // @[DCache.scala:339:19]
reg [63:0] s2_req_data; // @[DCache.scala:339:19]
reg [7:0] s2_req_mask; // @[DCache.scala:339:19]
assign io_cpu_resp_bits_mask_0 = s2_req_mask; // @[DCache.scala:101:7, :339:19]
wire _GEN_72 = s2_req_cmd == 5'h5; // @[DCache.scala:339:19, :340:37]
wire _s2_cmd_flush_all_T; // @[DCache.scala:340:37]
assign _s2_cmd_flush_all_T = _GEN_72; // @[DCache.scala:340:37]
wire _s2_cmd_flush_line_T; // @[DCache.scala:341:38]
assign _s2_cmd_flush_line_T = _GEN_72; // @[DCache.scala:340:37, :341:38]
wire _s2_cmd_flush_all_T_1 = s2_req_size[0]; // @[DCache.scala:339:19, :340:68]
wire _s2_cmd_flush_line_T_1 = s2_req_size[0]; // @[DCache.scala:339:19, :340:68, :341:68]
wire _s2_cmd_flush_all_T_2 = ~_s2_cmd_flush_all_T_1; // @[DCache.scala:340:{56,68}]
wire s2_cmd_flush_all = _s2_cmd_flush_all_T & _s2_cmd_flush_all_T_2; // @[DCache.scala:340:{37,53,56}]
wire s2_cmd_flush_line = _s2_cmd_flush_line_T & _s2_cmd_flush_line_T_1; // @[DCache.scala:341:{38,54,68}]
reg [31:0] s2_tlb_xcpt_paddr; // @[DCache.scala:342:24]
reg [33:0] s2_tlb_xcpt_gpa; // @[DCache.scala:342:24]
assign io_cpu_s2_gpa_0 = s2_tlb_xcpt_gpa; // @[DCache.scala:101:7, :342:24]
reg s2_tlb_xcpt_pf_ld; // @[DCache.scala:342:24]
reg s2_tlb_xcpt_pf_st; // @[DCache.scala:342:24]
reg s2_tlb_xcpt_pf_inst; // @[DCache.scala:342:24]
reg s2_tlb_xcpt_ae_ld; // @[DCache.scala:342:24]
reg s2_tlb_xcpt_ae_st; // @[DCache.scala:342:24]
reg s2_tlb_xcpt_ae_inst; // @[DCache.scala:342:24]
reg s2_tlb_xcpt_ma_ld; // @[DCache.scala:342:24]
reg s2_tlb_xcpt_ma_st; // @[DCache.scala:342:24]
reg s2_tlb_xcpt_cacheable; // @[DCache.scala:342:24]
reg s2_tlb_xcpt_must_alloc; // @[DCache.scala:342:24]
reg s2_tlb_xcpt_prefetchable; // @[DCache.scala:342:24]
reg [1:0] s2_tlb_xcpt_size; // @[DCache.scala:342:24]
reg [4:0] s2_tlb_xcpt_cmd; // @[DCache.scala:342:24]
reg [31:0] s2_pma_paddr; // @[DCache.scala:343:19]
reg [33:0] s2_pma_gpa; // @[DCache.scala:343:19]
reg s2_pma_pf_ld; // @[DCache.scala:343:19]
reg s2_pma_pf_st; // @[DCache.scala:343:19]
reg s2_pma_pf_inst; // @[DCache.scala:343:19]
reg s2_pma_ae_ld; // @[DCache.scala:343:19]
reg s2_pma_ae_st; // @[DCache.scala:343:19]
reg s2_pma_ae_inst; // @[DCache.scala:343:19]
reg s2_pma_ma_ld; // @[DCache.scala:343:19]
reg s2_pma_ma_st; // @[DCache.scala:343:19]
reg s2_pma_cacheable; // @[DCache.scala:343:19]
assign tl_out_a_bits_user_amba_prot_bufferable = s2_pma_cacheable; // @[DCache.scala:159:22, :343:19]
assign tl_out_a_bits_user_amba_prot_modifiable = s2_pma_cacheable; // @[DCache.scala:159:22, :343:19]
assign tl_out_a_bits_user_amba_prot_readalloc = s2_pma_cacheable; // @[DCache.scala:159:22, :343:19]
assign tl_out_a_bits_user_amba_prot_writealloc = s2_pma_cacheable; // @[DCache.scala:159:22, :343:19]
reg s2_pma_must_alloc; // @[DCache.scala:343:19]
reg s2_pma_prefetchable; // @[DCache.scala:343:19]
reg [1:0] s2_pma_size; // @[DCache.scala:343:19]
reg [4:0] s2_pma_cmd; // @[DCache.scala:343:19]
reg [33:0] s2_uncached_resp_addr; // @[DCache.scala:344:34]
wire _T_29 = s1_valid_not_nacked | s1_flush_valid; // @[DCache.scala:187:38, :215:27, :345:29]
wire _s2_vaddr_T; // @[DCache.scala:351:62]
assign _s2_vaddr_T = _T_29; // @[DCache.scala:345:29, :351:62]
wire _s1_meta_clk_en_T; // @[DCache.scala:357:44]
assign _s1_meta_clk_en_T = _T_29; // @[DCache.scala:345:29, :357:44]
wire _s2_hit_state_T; // @[DCache.scala:386:66]
assign _s2_hit_state_T = _T_29; // @[DCache.scala:345:29, :386:66]
wire _s2_victim_way_T; // @[DCache.scala:431:77]
assign _s2_victim_way_T = _T_29; // @[DCache.scala:345:29, :431:77]
reg [33:0] s2_vaddr_r; // @[DCache.scala:351:31]
wire [19:0] _s2_vaddr_T_1 = s2_vaddr_r[33:14]; // @[DCache.scala:351:{31,81}]
wire [13:0] _s2_vaddr_T_2 = s2_req_addr[13:0]; // @[DCache.scala:339:19, :351:103]
wire [33:0] s2_vaddr = {_s2_vaddr_T_1, _s2_vaddr_T_2}; // @[DCache.scala:351:{21,81,103}]
wire _s2_read_T = s2_req_cmd == 5'h0; // @[package.scala:16:47]
wire _s2_read_T_1 = s2_req_cmd == 5'h10; // @[package.scala:16:47]
wire _T_110 = s2_req_cmd == 5'h6; // @[package.scala:16:47]
wire _s2_read_T_2; // @[package.scala:16:47]
assign _s2_read_T_2 = _T_110; // @[package.scala:16:47]
wire _r_c_cat_T_48; // @[Consts.scala:91:71]
assign _r_c_cat_T_48 = _T_110; // @[package.scala:16:47]
wire _s2_lr_T; // @[DCache.scala:470:70]
assign _s2_lr_T = _T_110; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_48; // @[Consts.scala:91:71]
assign _metaArb_io_in_3_bits_data_c_cat_T_48 = _T_110; // @[package.scala:16:47]
wire _T_111 = s2_req_cmd == 5'h7; // @[package.scala:16:47]
wire _s2_read_T_3; // @[package.scala:16:47]
assign _s2_read_T_3 = _T_111; // @[package.scala:16:47]
wire _s2_write_T_3; // @[Consts.scala:90:66]
assign _s2_write_T_3 = _T_111; // @[package.scala:16:47]
wire _r_c_cat_T_3; // @[Consts.scala:90:66]
assign _r_c_cat_T_3 = _T_111; // @[package.scala:16:47]
wire _r_c_cat_T_26; // @[Consts.scala:90:66]
assign _r_c_cat_T_26 = _T_111; // @[package.scala:16:47]
wire _s2_sc_T; // @[DCache.scala:471:70]
assign _s2_sc_T = _T_111; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_3; // @[Consts.scala:90:66]
assign _metaArb_io_in_3_bits_data_c_cat_T_3 = _T_111; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_26; // @[Consts.scala:90:66]
assign _metaArb_io_in_3_bits_data_c_cat_T_26 = _T_111; // @[package.scala:16:47]
wire _io_cpu_store_pending_T_3; // @[Consts.scala:90:66]
assign _io_cpu_store_pending_T_3 = _T_111; // @[package.scala:16:47]
wire _s2_read_T_4 = _s2_read_T | _s2_read_T_1; // @[package.scala:16:47, :81:59]
wire _s2_read_T_5 = _s2_read_T_4 | _s2_read_T_2; // @[package.scala:16:47, :81:59]
wire _s2_read_T_6 = _s2_read_T_5 | _s2_read_T_3; // @[package.scala:16:47, :81:59]
wire _GEN_73 = s2_req_cmd == 5'h4; // @[package.scala:16:47]
wire _s2_read_T_7; // @[package.scala:16:47]
assign _s2_read_T_7 = _GEN_73; // @[package.scala:16:47]
wire _s2_write_T_5; // @[package.scala:16:47]
assign _s2_write_T_5 = _GEN_73; // @[package.scala:16:47]
wire _r_c_cat_T_5; // @[package.scala:16:47]
assign _r_c_cat_T_5 = _GEN_73; // @[package.scala:16:47]
wire _r_c_cat_T_28; // @[package.scala:16:47]
assign _r_c_cat_T_28 = _GEN_73; // @[package.scala:16:47]
wire _atomics_T; // @[DCache.scala:587:81]
assign _atomics_T = _GEN_73; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_5; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_5 = _GEN_73; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_28; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_28 = _GEN_73; // @[package.scala:16:47]
wire _io_cpu_store_pending_T_5; // @[package.scala:16:47]
assign _io_cpu_store_pending_T_5 = _GEN_73; // @[package.scala:16:47]
wire _GEN_74 = s2_req_cmd == 5'h9; // @[package.scala:16:47]
wire _s2_read_T_8; // @[package.scala:16:47]
assign _s2_read_T_8 = _GEN_74; // @[package.scala:16:47]
wire _s2_write_T_6; // @[package.scala:16:47]
assign _s2_write_T_6 = _GEN_74; // @[package.scala:16:47]
wire _r_c_cat_T_6; // @[package.scala:16:47]
assign _r_c_cat_T_6 = _GEN_74; // @[package.scala:16:47]
wire _r_c_cat_T_29; // @[package.scala:16:47]
assign _r_c_cat_T_29 = _GEN_74; // @[package.scala:16:47]
wire _atomics_T_2; // @[DCache.scala:587:81]
assign _atomics_T_2 = _GEN_74; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_6; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_6 = _GEN_74; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_29; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_29 = _GEN_74; // @[package.scala:16:47]
wire _io_cpu_store_pending_T_6; // @[package.scala:16:47]
assign _io_cpu_store_pending_T_6 = _GEN_74; // @[package.scala:16:47]
wire _GEN_75 = s2_req_cmd == 5'hA; // @[package.scala:16:47]
wire _s2_read_T_9; // @[package.scala:16:47]
assign _s2_read_T_9 = _GEN_75; // @[package.scala:16:47]
wire _s2_write_T_7; // @[package.scala:16:47]
assign _s2_write_T_7 = _GEN_75; // @[package.scala:16:47]
wire _r_c_cat_T_7; // @[package.scala:16:47]
assign _r_c_cat_T_7 = _GEN_75; // @[package.scala:16:47]
wire _r_c_cat_T_30; // @[package.scala:16:47]
assign _r_c_cat_T_30 = _GEN_75; // @[package.scala:16:47]
wire _atomics_T_4; // @[DCache.scala:587:81]
assign _atomics_T_4 = _GEN_75; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_7; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_7 = _GEN_75; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_30; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_30 = _GEN_75; // @[package.scala:16:47]
wire _io_cpu_store_pending_T_7; // @[package.scala:16:47]
assign _io_cpu_store_pending_T_7 = _GEN_75; // @[package.scala:16:47]
wire _GEN_76 = s2_req_cmd == 5'hB; // @[package.scala:16:47]
wire _s2_read_T_10; // @[package.scala:16:47]
assign _s2_read_T_10 = _GEN_76; // @[package.scala:16:47]
wire _s2_write_T_8; // @[package.scala:16:47]
assign _s2_write_T_8 = _GEN_76; // @[package.scala:16:47]
wire _r_c_cat_T_8; // @[package.scala:16:47]
assign _r_c_cat_T_8 = _GEN_76; // @[package.scala:16:47]
wire _r_c_cat_T_31; // @[package.scala:16:47]
assign _r_c_cat_T_31 = _GEN_76; // @[package.scala:16:47]
wire _atomics_T_6; // @[DCache.scala:587:81]
assign _atomics_T_6 = _GEN_76; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_8; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_8 = _GEN_76; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_31; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_31 = _GEN_76; // @[package.scala:16:47]
wire _io_cpu_store_pending_T_8; // @[package.scala:16:47]
assign _io_cpu_store_pending_T_8 = _GEN_76; // @[package.scala:16:47]
wire _s2_read_T_11 = _s2_read_T_7 | _s2_read_T_8; // @[package.scala:16:47, :81:59]
wire _s2_read_T_12 = _s2_read_T_11 | _s2_read_T_9; // @[package.scala:16:47, :81:59]
wire _s2_read_T_13 = _s2_read_T_12 | _s2_read_T_10; // @[package.scala:16:47, :81:59]
wire _GEN_77 = s2_req_cmd == 5'h8; // @[package.scala:16:47]
wire _s2_read_T_14; // @[package.scala:16:47]
assign _s2_read_T_14 = _GEN_77; // @[package.scala:16:47]
wire _s2_write_T_12; // @[package.scala:16:47]
assign _s2_write_T_12 = _GEN_77; // @[package.scala:16:47]
wire _r_c_cat_T_12; // @[package.scala:16:47]
assign _r_c_cat_T_12 = _GEN_77; // @[package.scala:16:47]
wire _r_c_cat_T_35; // @[package.scala:16:47]
assign _r_c_cat_T_35 = _GEN_77; // @[package.scala:16:47]
wire _atomics_T_8; // @[DCache.scala:587:81]
assign _atomics_T_8 = _GEN_77; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_12; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_12 = _GEN_77; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_35; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_35 = _GEN_77; // @[package.scala:16:47]
wire _io_cpu_store_pending_T_12; // @[package.scala:16:47]
assign _io_cpu_store_pending_T_12 = _GEN_77; // @[package.scala:16:47]
wire _GEN_78 = s2_req_cmd == 5'hC; // @[package.scala:16:47]
wire _s2_read_T_15; // @[package.scala:16:47]
assign _s2_read_T_15 = _GEN_78; // @[package.scala:16:47]
wire _s2_write_T_13; // @[package.scala:16:47]
assign _s2_write_T_13 = _GEN_78; // @[package.scala:16:47]
wire _r_c_cat_T_13; // @[package.scala:16:47]
assign _r_c_cat_T_13 = _GEN_78; // @[package.scala:16:47]
wire _r_c_cat_T_36; // @[package.scala:16:47]
assign _r_c_cat_T_36 = _GEN_78; // @[package.scala:16:47]
wire _atomics_T_10; // @[DCache.scala:587:81]
assign _atomics_T_10 = _GEN_78; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_13; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_13 = _GEN_78; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_36; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_36 = _GEN_78; // @[package.scala:16:47]
wire _io_cpu_store_pending_T_13; // @[package.scala:16:47]
assign _io_cpu_store_pending_T_13 = _GEN_78; // @[package.scala:16:47]
wire _GEN_79 = s2_req_cmd == 5'hD; // @[package.scala:16:47]
wire _s2_read_T_16; // @[package.scala:16:47]
assign _s2_read_T_16 = _GEN_79; // @[package.scala:16:47]
wire _s2_write_T_14; // @[package.scala:16:47]
assign _s2_write_T_14 = _GEN_79; // @[package.scala:16:47]
wire _r_c_cat_T_14; // @[package.scala:16:47]
assign _r_c_cat_T_14 = _GEN_79; // @[package.scala:16:47]
wire _r_c_cat_T_37; // @[package.scala:16:47]
assign _r_c_cat_T_37 = _GEN_79; // @[package.scala:16:47]
wire _atomics_T_12; // @[DCache.scala:587:81]
assign _atomics_T_12 = _GEN_79; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_14; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_14 = _GEN_79; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_37; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_37 = _GEN_79; // @[package.scala:16:47]
wire _io_cpu_store_pending_T_14; // @[package.scala:16:47]
assign _io_cpu_store_pending_T_14 = _GEN_79; // @[package.scala:16:47]
wire _GEN_80 = s2_req_cmd == 5'hE; // @[package.scala:16:47]
wire _s2_read_T_17; // @[package.scala:16:47]
assign _s2_read_T_17 = _GEN_80; // @[package.scala:16:47]
wire _s2_write_T_15; // @[package.scala:16:47]
assign _s2_write_T_15 = _GEN_80; // @[package.scala:16:47]
wire _r_c_cat_T_15; // @[package.scala:16:47]
assign _r_c_cat_T_15 = _GEN_80; // @[package.scala:16:47]
wire _r_c_cat_T_38; // @[package.scala:16:47]
assign _r_c_cat_T_38 = _GEN_80; // @[package.scala:16:47]
wire _atomics_T_14; // @[DCache.scala:587:81]
assign _atomics_T_14 = _GEN_80; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_15; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_15 = _GEN_80; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_38; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_38 = _GEN_80; // @[package.scala:16:47]
wire _io_cpu_store_pending_T_15; // @[package.scala:16:47]
assign _io_cpu_store_pending_T_15 = _GEN_80; // @[package.scala:16:47]
wire _GEN_81 = s2_req_cmd == 5'hF; // @[package.scala:16:47]
wire _s2_read_T_18; // @[package.scala:16:47]
assign _s2_read_T_18 = _GEN_81; // @[package.scala:16:47]
wire _s2_write_T_16; // @[package.scala:16:47]
assign _s2_write_T_16 = _GEN_81; // @[package.scala:16:47]
wire _r_c_cat_T_16; // @[package.scala:16:47]
assign _r_c_cat_T_16 = _GEN_81; // @[package.scala:16:47]
wire _r_c_cat_T_39; // @[package.scala:16:47]
assign _r_c_cat_T_39 = _GEN_81; // @[package.scala:16:47]
wire _atomics_T_16; // @[DCache.scala:587:81]
assign _atomics_T_16 = _GEN_81; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_16; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_16 = _GEN_81; // @[package.scala:16:47]
wire _metaArb_io_in_3_bits_data_c_cat_T_39; // @[package.scala:16:47]
assign _metaArb_io_in_3_bits_data_c_cat_T_39 = _GEN_81; // @[package.scala:16:47]
wire _io_cpu_store_pending_T_16; // @[package.scala:16:47]
assign _io_cpu_store_pending_T_16 = _GEN_81; // @[package.scala:16:47]
wire _s2_read_T_19 = _s2_read_T_14 | _s2_read_T_15; // @[package.scala:16:47, :81:59]
wire _s2_read_T_20 = _s2_read_T_19 | _s2_read_T_16; // @[package.scala:16:47, :81:59]
wire _s2_read_T_21 = _s2_read_T_20 | _s2_read_T_17; // @[package.scala:16:47, :81:59]
wire _s2_read_T_22 = _s2_read_T_21 | _s2_read_T_18; // @[package.scala:16:47, :81:59]
wire _s2_read_T_23 = _s2_read_T_13 | _s2_read_T_22; // @[package.scala:81:59]
assign s2_read = _s2_read_T_6 | _s2_read_T_23; // @[package.scala:81:59]
assign io_cpu_resp_bits_has_data_0 = s2_read; // @[DCache.scala:101:7]
wire _GEN_82 = s2_req_cmd == 5'h1; // @[DCache.scala:339:19]
wire _s2_write_T; // @[Consts.scala:90:32]
assign _s2_write_T = _GEN_82; // @[Consts.scala:90:32]
wire _r_c_cat_T; // @[Consts.scala:90:32]
assign _r_c_cat_T = _GEN_82; // @[Consts.scala:90:32]
wire _r_c_cat_T_23; // @[Consts.scala:90:32]
assign _r_c_cat_T_23 = _GEN_82; // @[Consts.scala:90:32]
wire _metaArb_io_in_3_bits_data_c_cat_T; // @[Consts.scala:90:32]
assign _metaArb_io_in_3_bits_data_c_cat_T = _GEN_82; // @[Consts.scala:90:32]
wire _metaArb_io_in_3_bits_data_c_cat_T_23; // @[Consts.scala:90:32]
assign _metaArb_io_in_3_bits_data_c_cat_T_23 = _GEN_82; // @[Consts.scala:90:32]
wire _io_cpu_store_pending_T; // @[Consts.scala:90:32]
assign _io_cpu_store_pending_T = _GEN_82; // @[Consts.scala:90:32]
wire _GEN_83 = s2_req_cmd == 5'h11; // @[DCache.scala:339:19]
wire _s2_write_T_1; // @[Consts.scala:90:49]
assign _s2_write_T_1 = _GEN_83; // @[Consts.scala:90:49]
wire _r_c_cat_T_1; // @[Consts.scala:90:49]
assign _r_c_cat_T_1 = _GEN_83; // @[Consts.scala:90:49]
wire _r_c_cat_T_24; // @[Consts.scala:90:49]
assign _r_c_cat_T_24 = _GEN_83; // @[Consts.scala:90:49]
wire _tl_out_a_bits_T_2; // @[DCache.scala:610:20]
assign _tl_out_a_bits_T_2 = _GEN_83; // @[DCache.scala:610:20]
wire _uncachedReqs_0_cmd_T; // @[DCache.scala:637:49]
assign _uncachedReqs_0_cmd_T = _GEN_83; // @[DCache.scala:637:49]
wire _metaArb_io_in_3_bits_data_c_cat_T_1; // @[Consts.scala:90:49]
assign _metaArb_io_in_3_bits_data_c_cat_T_1 = _GEN_83; // @[Consts.scala:90:49]
wire _metaArb_io_in_3_bits_data_c_cat_T_24; // @[Consts.scala:90:49]
assign _metaArb_io_in_3_bits_data_c_cat_T_24 = _GEN_83; // @[Consts.scala:90:49]
wire _io_cpu_store_pending_T_1; // @[Consts.scala:90:49]
assign _io_cpu_store_pending_T_1 = _GEN_83; // @[Consts.scala:90:49]
wire _s2_write_T_2 = _s2_write_T | _s2_write_T_1; // @[Consts.scala:90:{32,42,49}]
wire _s2_write_T_4 = _s2_write_T_2 | _s2_write_T_3; // @[Consts.scala:90:{42,59,66}]
wire _s2_write_T_9 = _s2_write_T_5 | _s2_write_T_6; // @[package.scala:16:47, :81:59]
wire _s2_write_T_10 = _s2_write_T_9 | _s2_write_T_7; // @[package.scala:16:47, :81:59]
wire _s2_write_T_11 = _s2_write_T_10 | _s2_write_T_8; // @[package.scala:16:47, :81:59]
wire _s2_write_T_17 = _s2_write_T_12 | _s2_write_T_13; // @[package.scala:16:47, :81:59]
wire _s2_write_T_18 = _s2_write_T_17 | _s2_write_T_14; // @[package.scala:16:47, :81:59]
wire _s2_write_T_19 = _s2_write_T_18 | _s2_write_T_15; // @[package.scala:16:47, :81:59]
wire _s2_write_T_20 = _s2_write_T_19 | _s2_write_T_16; // @[package.scala:16:47, :81:59]
wire _s2_write_T_21 = _s2_write_T_11 | _s2_write_T_20; // @[package.scala:81:59]
wire s2_write = _s2_write_T_4 | _s2_write_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire s2_readwrite = s2_read | s2_write; // @[DCache.scala:354:30]
reg s2_flush_valid_pre_tag_ecc; // @[DCache.scala:355:43]
wire s2_flush_valid = s2_flush_valid_pre_tag_ecc; // @[DCache.scala:355:43, :363:51]
wire s1_meta_clk_en = _s1_meta_clk_en_T; // @[DCache.scala:357:{44,62}]
wire s2_data_en = _s2_data_en_T | io_cpu_replay_next_0; // @[DCache.scala:101:7, :366:{23,38}]
wire s2_data_word_en = _s2_data_word_en_T; // @[DCache.scala:367:{22,63}]
wire _s2_data_s1_word_en_T = ~io_cpu_replay_next_0; // @[DCache.scala:101:7, :377:28]
wire s2_data_s1_word_en = ~_s2_data_s1_word_en_T | s2_data_word_en; // @[DCache.scala:367:22, :377:{27,28}]
wire _s2_data_T = s2_data_s1_word_en; // @[DCache.scala:377:27, :379:39]
wire [1:0] _s2_data_T_1 = _s2_data_T ? s1_data_way : 2'h0; // @[DCache.scala:323:32, :379:{28,39}]
wire _s2_data_T_2 = _s2_data_T_1[0]; // @[Mux.scala:32:36]
wire _s2_data_T_3 = _s2_data_T_1[1]; // @[Mux.scala:32:36]
wire [63:0] _s2_data_T_4 = _s2_data_T_2 ? s2_data_s1_way_words_0_0 : 64'h0; // @[Mux.scala:30:73, :32:36]
wire [63:0] _s2_data_T_5 = _s2_data_T_3 ? s2_data_s1_way_words_1_0 : 64'h0; // @[Mux.scala:30:73, :32:36]
wire [63:0] _s2_data_T_6 = _s2_data_T_4 | _s2_data_T_5; // @[Mux.scala:30:73]
wire [63:0] _s2_data_WIRE = _s2_data_T_6; // @[Mux.scala:30:73]
reg [63:0] s2_data; // @[DCache.scala:379:18]
reg s2_probe_way; // @[DCache.scala:383:31]
assign releaseWay = s2_probe_way; // @[DCache.scala:232:24, :383:31]
reg [1:0] s2_probe_state_state; // @[DCache.scala:384:33]
reg s2_hit_way; // @[DCache.scala:385:29]
reg [1:0] s2_hit_state_state; // @[DCache.scala:386:31]
wire s2_hit_valid = |s2_hit_state_state; // @[Metadata.scala:50:45]
wire _r_c_cat_T_2 = _r_c_cat_T | _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_4 = _r_c_cat_T_2 | _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_9 = _r_c_cat_T_5 | _r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_10 = _r_c_cat_T_9 | _r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_11 = _r_c_cat_T_10 | _r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_17 = _r_c_cat_T_12 | _r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_18 = _r_c_cat_T_17 | _r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_19 = _r_c_cat_T_18 | _r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_20 = _r_c_cat_T_19 | _r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_21 = _r_c_cat_T_11 | _r_c_cat_T_20; // @[package.scala:81:59]
wire _r_c_cat_T_22 = _r_c_cat_T_4 | _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_25 = _r_c_cat_T_23 | _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_27 = _r_c_cat_T_25 | _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_32 = _r_c_cat_T_28 | _r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_33 = _r_c_cat_T_32 | _r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_34 = _r_c_cat_T_33 | _r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_40 = _r_c_cat_T_35 | _r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_41 = _r_c_cat_T_40 | _r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_42 = _r_c_cat_T_41 | _r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_43 = _r_c_cat_T_42 | _r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_44 = _r_c_cat_T_34 | _r_c_cat_T_43; // @[package.scala:81:59]
wire _r_c_cat_T_45 = _r_c_cat_T_27 | _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _GEN_84 = s2_req_cmd == 5'h3; // @[DCache.scala:339:19]
wire _r_c_cat_T_46; // @[Consts.scala:91:54]
assign _r_c_cat_T_46 = _GEN_84; // @[Consts.scala:91:54]
wire _metaArb_io_in_3_bits_data_c_cat_T_46; // @[Consts.scala:91:54]
assign _metaArb_io_in_3_bits_data_c_cat_T_46 = _GEN_84; // @[Consts.scala:91:54]
wire _r_c_cat_T_47 = _r_c_cat_T_45 | _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _r_c_cat_T_49 = _r_c_cat_T_47 | _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r_T = {r_c, s2_hit_state_state}; // @[Metadata.scala:29:18, :58:19]
wire _r_T_25 = _r_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r_T_27 = {1'h0, _r_T_25}; // @[Misc.scala:35:36, :49:20]
wire _r_T_28 = _r_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r_T_30 = _r_T_28 ? 2'h2 : _r_T_27; // @[Misc.scala:35:36, :49:20]
wire _r_T_31 = _r_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r_T_33 = _r_T_31 ? 2'h1 : _r_T_30; // @[Misc.scala:35:36, :49:20]
wire _r_T_34 = _r_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r_T_36 = _r_T_34 ? 2'h2 : _r_T_33; // @[Misc.scala:35:36, :49:20]
wire _r_T_37 = _r_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r_T_39 = _r_T_37 ? 2'h0 : _r_T_36; // @[Misc.scala:35:36, :49:20]
wire _r_T_40 = _r_T == 4'hE; // @[Misc.scala:49:20]
wire _r_T_41 = _r_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_42 = _r_T_40 ? 2'h3 : _r_T_39; // @[Misc.scala:35:36, :49:20]
wire _r_T_43 = &_r_T; // @[Misc.scala:49:20]
wire _r_T_44 = _r_T_43 | _r_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_45 = _r_T_43 ? 2'h3 : _r_T_42; // @[Misc.scala:35:36, :49:20]
wire _r_T_46 = _r_T == 4'h6; // @[Misc.scala:49:20]
wire _r_T_47 = _r_T_46 | _r_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_48 = _r_T_46 ? 2'h2 : _r_T_45; // @[Misc.scala:35:36, :49:20]
wire _r_T_49 = _r_T == 4'h7; // @[Misc.scala:49:20]
wire _r_T_50 = _r_T_49 | _r_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_51 = _r_T_49 ? 2'h3 : _r_T_48; // @[Misc.scala:35:36, :49:20]
wire _r_T_52 = _r_T == 4'h1; // @[Misc.scala:49:20]
wire _r_T_53 = _r_T_52 | _r_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_54 = _r_T_52 ? 2'h1 : _r_T_51; // @[Misc.scala:35:36, :49:20]
wire _r_T_55 = _r_T == 4'h2; // @[Misc.scala:49:20]
wire _r_T_56 = _r_T_55 | _r_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_57 = _r_T_55 ? 2'h2 : _r_T_54; // @[Misc.scala:35:36, :49:20]
wire _r_T_58 = _r_T == 4'h3; // @[Misc.scala:49:20]
wire s2_hit = _r_T_58 | _r_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] s2_grow_param = _r_T_58 ? 2'h3 : _r_T_57; // @[Misc.scala:35:36, :49:20]
wire [1:0] s2_new_hit_state_state = s2_grow_param; // @[Misc.scala:35:36]
wire [1:0] metaArb_io_in_2_bits_data_meta_coh_state = s2_new_hit_state_state; // @[Metadata.scala:160:20]
wire [15:0] s2_data_corrected_lo_lo = s2_data[15:0]; // @[package.scala:45:27]
wire [15:0] s2_data_uncorrected_lo_lo = s2_data[15:0]; // @[package.scala:45:27]
wire [15:0] s2_data_corrected_lo_hi = s2_data[31:16]; // @[package.scala:45:27]
wire [15:0] s2_data_uncorrected_lo_hi = s2_data[31:16]; // @[package.scala:45:27]
wire [31:0] s2_data_corrected_lo = {s2_data_corrected_lo_hi, s2_data_corrected_lo_lo}; // @[package.scala:45:27]
wire [15:0] s2_data_corrected_hi_lo = s2_data[47:32]; // @[package.scala:45:27]
wire [15:0] s2_data_uncorrected_hi_lo = s2_data[47:32]; // @[package.scala:45:27]
wire [15:0] s2_data_corrected_hi_hi = s2_data[63:48]; // @[package.scala:45:27]
wire [15:0] s2_data_uncorrected_hi_hi = s2_data[63:48]; // @[package.scala:45:27]
wire [31:0] s2_data_corrected_hi = {s2_data_corrected_hi_hi, s2_data_corrected_hi_lo}; // @[package.scala:45:27]
wire [63:0] s2_data_corrected = {s2_data_corrected_hi, s2_data_corrected_lo}; // @[package.scala:45:27]
wire [63:0] s2_data_word_corrected = s2_data_corrected; // @[package.scala:45:27]
wire [31:0] s2_data_uncorrected_lo = {s2_data_uncorrected_lo_hi, s2_data_uncorrected_lo_lo}; // @[package.scala:45:27]
wire [31:0] s2_data_uncorrected_hi = {s2_data_uncorrected_hi_hi, s2_data_uncorrected_hi_lo}; // @[package.scala:45:27]
wire [63:0] s2_data_uncorrected = {s2_data_uncorrected_hi, s2_data_uncorrected_lo}; // @[package.scala:45:27]
assign s2_data_word = s2_data_uncorrected; // @[package.scala:45:27]
wire s2_valid_hit_maybe_flush_pre_data_ecc_and_waw = _s2_valid_hit_maybe_flush_pre_data_ecc_and_waw_T_1 & s2_hit; // @[Misc.scala:35:9]
wire _s2_valid_hit_pre_data_ecc_and_waw_T = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw & s2_readwrite; // @[DCache.scala:354:30, :397:89, :418:89]
wire s2_valid_hit_pre_data_ecc_and_waw = _s2_valid_hit_pre_data_ecc_and_waw_T; // @[DCache.scala:418:{89,105}]
wire s2_valid_hit_pre_data_ecc = s2_valid_hit_pre_data_ecc_and_waw; // @[DCache.scala:418:105, :420:69]
wire s2_valid_flush_line = s2_valid_hit_maybe_flush_pre_data_ecc_and_waw & s2_cmd_flush_line; // @[DCache.scala:341:54, :397:89, :419:75]
wire _s2_victim_tag_T = s2_valid_flush_line; // @[DCache.scala:419:75, :433:47]
wire s2_valid_hit = s2_valid_hit_pre_data_ecc; // @[DCache.scala:420:69, :422:48]
wire _s2_valid_miss_T = s2_valid_masked & s2_readwrite; // @[DCache.scala:337:42, :354:30, :423:39]
wire _s2_valid_miss_T_2 = _s2_valid_miss_T; // @[DCache.scala:423:{39,55}]
wire _s2_valid_miss_T_3 = ~s2_hit; // @[Misc.scala:35:9]
wire s2_valid_miss = _s2_valid_miss_T_2 & _s2_valid_miss_T_3; // @[DCache.scala:423:{55,73,76}]
wire _s2_uncached_T = ~s2_pma_cacheable; // @[DCache.scala:343:19, :424:21]
wire _s2_uncached_T_1 = ~s2_pma_must_alloc; // @[DCache.scala:343:19, :424:61]
wire _s2_uncached_T_2 = s2_req_no_alloc & _s2_uncached_T_1; // @[DCache.scala:339:19, :424:{58,61}]
wire _s2_uncached_T_3 = ~s2_hit_valid; // @[Metadata.scala:50:45]
wire _s2_uncached_T_4 = _s2_uncached_T_2 & _s2_uncached_T_3; // @[DCache.scala:424:{58,80,83}]
wire s2_uncached = _s2_uncached_T | _s2_uncached_T_4; // @[DCache.scala:424:{21,39,80}]
wire _s2_valid_cached_miss_T = ~s2_uncached; // @[DCache.scala:424:39, :425:47]
wire _s2_valid_cached_miss_T_1 = s2_valid_miss & _s2_valid_cached_miss_T; // @[DCache.scala:423:73, :425:{44,47}]
wire _s2_valid_cached_miss_T_3 = ~_s2_valid_cached_miss_T_2; // @[DCache.scala:425:{63,88}]
wire s2_valid_cached_miss = _s2_valid_cached_miss_T_1 & _s2_valid_cached_miss_T_3; // @[DCache.scala:425:{44,60,63}]
wire _tl_out_a_valid_T_6 = s2_valid_cached_miss; // @[DCache.scala:425:60, :605:29]
wire _s2_want_victimize_T = s2_valid_cached_miss | s2_valid_flush_line; // @[DCache.scala:419:75, :425:60, :427:77]
wire _s2_want_victimize_T_1 = _s2_want_victimize_T; // @[DCache.scala:427:{77,100}]
wire _s2_want_victimize_T_2 = _s2_want_victimize_T_1 | s2_flush_valid; // @[DCache.scala:363:51, :427:{100,123}]
wire _s2_cannot_victimize_T = ~s2_flush_valid; // @[DCache.scala:363:51, :428:29]
wire _s2_valid_uncached_pending_T = s2_valid_miss & s2_uncached; // @[DCache.scala:423:73, :424:39, :430:49]
wire _s2_valid_uncached_pending_T_2 = ~_s2_valid_uncached_pending_T_1; // @[DCache.scala:430:{67,92}]
wire s2_valid_uncached_pending = _s2_valid_uncached_pending_T & _s2_valid_uncached_pending_T_2; // @[DCache.scala:430:{49,64,67}]
wire [1:0] s2_victim_or_hit_way = s2_hit_valid ? {1'h0, s2_hit_way} : 2'h1; // @[Metadata.scala:50:45]
wire [17:0] _s2_victim_tag_T_1 = s2_req_addr[31:14]; // @[DCache.scala:339:19, :433:82]
wire [17:0] s2_victim_tag = _s2_victim_tag_T ? _s2_victim_tag_T_1 : 18'h0; // @[DCache.scala:433:{26,47,82}]
wire [1:0] s2_victim_state_state = s2_hit_valid ? s2_hit_state_state : 2'h0; // @[Metadata.scala:50:45]
wire [3:0] _r_T_59 = {2'h0, s2_probe_state_state}; // @[Metadata.scala:120:19]
wire _r_T_72 = _r_T_59 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _r_T_74 = _r_T_72 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _r_T_76 = _r_T_59 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _r_T_78 = _r_T_76 ? 3'h2 : _r_T_74; // @[Misc.scala:38:36, :56:20]
wire _r_T_80 = _r_T_59 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _r_T_82 = _r_T_80 ? 3'h1 : _r_T_78; // @[Misc.scala:38:36, :56:20]
wire _r_T_84 = _r_T_59 == 4'hB; // @[Misc.scala:56:20]
wire _r_T_85 = _r_T_84; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_86 = _r_T_84 ? 3'h1 : _r_T_82; // @[Misc.scala:38:36, :56:20]
wire _r_T_88 = _r_T_59 == 4'h4; // @[Misc.scala:56:20]
wire _r_T_89 = ~_r_T_88 & _r_T_85; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_90 = _r_T_88 ? 3'h5 : _r_T_86; // @[Misc.scala:38:36, :56:20]
wire _r_T_92 = _r_T_59 == 4'h5; // @[Misc.scala:56:20]
wire _r_T_93 = ~_r_T_92 & _r_T_89; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_94 = _r_T_92 ? 3'h4 : _r_T_90; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_95 = {1'h0, _r_T_92}; // @[Misc.scala:38:63, :56:20]
wire _r_T_96 = _r_T_59 == 4'h6; // @[Misc.scala:56:20]
wire _r_T_97 = ~_r_T_96 & _r_T_93; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_98 = _r_T_96 ? 3'h0 : _r_T_94; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_99 = _r_T_96 ? 2'h1 : _r_T_95; // @[Misc.scala:38:63, :56:20]
wire _r_T_100 = _r_T_59 == 4'h7; // @[Misc.scala:56:20]
wire _r_T_101 = _r_T_100 | _r_T_97; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_102 = _r_T_100 ? 3'h0 : _r_T_98; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_103 = _r_T_100 ? 2'h1 : _r_T_99; // @[Misc.scala:38:63, :56:20]
wire _r_T_104 = _r_T_59 == 4'h0; // @[Misc.scala:56:20]
wire _r_T_105 = ~_r_T_104 & _r_T_101; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_106 = _r_T_104 ? 3'h5 : _r_T_102; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_107 = _r_T_104 ? 2'h0 : _r_T_103; // @[Misc.scala:38:63, :56:20]
wire _r_T_108 = _r_T_59 == 4'h1; // @[Misc.scala:56:20]
wire _r_T_109 = ~_r_T_108 & _r_T_105; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_110 = _r_T_108 ? 3'h4 : _r_T_106; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_111 = _r_T_108 ? 2'h1 : _r_T_107; // @[Misc.scala:38:63, :56:20]
wire _r_T_112 = _r_T_59 == 4'h2; // @[Misc.scala:56:20]
wire _r_T_113 = ~_r_T_112 & _r_T_109; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_114 = _r_T_112 ? 3'h3 : _r_T_110; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_115 = _r_T_112 ? 2'h2 : _r_T_111; // @[Misc.scala:38:63, :56:20]
wire _r_T_116 = _r_T_59 == 4'h3; // @[Misc.scala:56:20]
wire s2_prb_ack_data = _r_T_116 | _r_T_113; // @[Misc.scala:38:9, :56:20]
wire [2:0] s2_report_param = _r_T_116 ? 3'h3 : _r_T_114; // @[Misc.scala:38:36, :56:20]
wire [2:0] cleanReleaseMessage_param = s2_report_param; // @[Misc.scala:38:36]
wire [2:0] dirtyReleaseMessage_param = s2_report_param; // @[Misc.scala:38:36]
wire [1:0] r_3 = _r_T_116 ? 2'h2 : _r_T_115; // @[Misc.scala:38:63, :56:20]
wire [1:0] probeNewCoh_state = r_3; // @[Misc.scala:38:63]
wire [1:0] newCoh_state = probeNewCoh_state; // @[Metadata.scala:160:20]
wire [3:0] _r_T_123 = {2'h2, s2_victim_state_state}; // @[Metadata.scala:120:19]
wire _r_T_136 = _r_T_123 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _r_T_138 = _r_T_136 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _r_T_140 = _r_T_123 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _r_T_142 = _r_T_140 ? 3'h2 : _r_T_138; // @[Misc.scala:38:36, :56:20]
wire _r_T_144 = _r_T_123 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _r_T_146 = _r_T_144 ? 3'h1 : _r_T_142; // @[Misc.scala:38:36, :56:20]
wire _r_T_148 = _r_T_123 == 4'hB; // @[Misc.scala:56:20]
wire _r_T_149 = _r_T_148; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_150 = _r_T_148 ? 3'h1 : _r_T_146; // @[Misc.scala:38:36, :56:20]
wire _r_T_152 = _r_T_123 == 4'h4; // @[Misc.scala:56:20]
wire _r_T_153 = ~_r_T_152 & _r_T_149; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_154 = _r_T_152 ? 3'h5 : _r_T_150; // @[Misc.scala:38:36, :56:20]
wire _r_T_156 = _r_T_123 == 4'h5; // @[Misc.scala:56:20]
wire _r_T_157 = ~_r_T_156 & _r_T_153; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_158 = _r_T_156 ? 3'h4 : _r_T_154; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_159 = {1'h0, _r_T_156}; // @[Misc.scala:38:63, :56:20]
wire _r_T_160 = _r_T_123 == 4'h6; // @[Misc.scala:56:20]
wire _r_T_161 = ~_r_T_160 & _r_T_157; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_162 = _r_T_160 ? 3'h0 : _r_T_158; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_163 = _r_T_160 ? 2'h1 : _r_T_159; // @[Misc.scala:38:63, :56:20]
wire _r_T_164 = _r_T_123 == 4'h7; // @[Misc.scala:56:20]
wire _r_T_165 = _r_T_164 | _r_T_161; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_166 = _r_T_164 ? 3'h0 : _r_T_162; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_167 = _r_T_164 ? 2'h1 : _r_T_163; // @[Misc.scala:38:63, :56:20]
wire _r_T_168 = _r_T_123 == 4'h0; // @[Misc.scala:56:20]
wire _r_T_169 = ~_r_T_168 & _r_T_165; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_170 = _r_T_168 ? 3'h5 : _r_T_166; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_171 = _r_T_168 ? 2'h0 : _r_T_167; // @[Misc.scala:38:63, :56:20]
wire _r_T_172 = _r_T_123 == 4'h1; // @[Misc.scala:56:20]
wire _r_T_173 = ~_r_T_172 & _r_T_169; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_174 = _r_T_172 ? 3'h4 : _r_T_170; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_175 = _r_T_172 ? 2'h1 : _r_T_171; // @[Misc.scala:38:63, :56:20]
wire _r_T_176 = _r_T_123 == 4'h2; // @[Misc.scala:56:20]
wire _r_T_177 = ~_r_T_176 & _r_T_173; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_178 = _r_T_176 ? 3'h3 : _r_T_174; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_179 = _r_T_176 ? 2'h2 : _r_T_175; // @[Misc.scala:38:63, :56:20]
wire _r_T_180 = _r_T_123 == 4'h3; // @[Misc.scala:56:20]
wire s2_victim_dirty = _r_T_180 | _r_T_177; // @[Misc.scala:38:9, :56:20]
wire [2:0] s2_shrink_param = _r_T_180 ? 3'h3 : _r_T_178; // @[Misc.scala:38:36, :56:20]
wire [1:0] r_3_1 = _r_T_180 ? 2'h2 : _r_T_179; // @[Misc.scala:38:63, :56:20]
wire [1:0] voluntaryNewCoh_state = r_3_1; // @[Misc.scala:38:63]
wire _s2_update_meta_T = s2_hit_state_state == s2_new_hit_state_state; // @[Metadata.scala:46:46, :160:20]
wire s2_update_meta = ~_s2_update_meta_T; // @[Metadata.scala:46:46, :47:40]
wire s2_dont_nack_uncached = s2_valid_uncached_pending & tl_out_a_ready; // @[DCache.scala:159:22, :430:64, :440:57]
wire _s2_dont_nack_misc_T_7 = ~s2_hit; // @[Misc.scala:35:9]
wire _s2_dont_nack_misc_T_10 = s2_req_cmd == 5'h17; // @[DCache.scala:339:19, :444:17]
wire _s2_dont_nack_misc_T_11 = _s2_dont_nack_misc_T_10; // @[DCache.scala:443:55, :444:17]
wire s2_dont_nack_misc = _s2_dont_nack_misc_T_1 & _s2_dont_nack_misc_T_11; // @[DCache.scala:441:{43,61}, :443:55]
wire _io_cpu_s2_nack_T = ~s2_dont_nack_uncached; // @[DCache.scala:440:57, :445:41]
wire _io_cpu_s2_nack_T_1 = s2_valid_no_xcpt & _io_cpu_s2_nack_T; // @[DCache.scala:332:35, :445:{38,41}]
wire _io_cpu_s2_nack_T_2 = ~s2_dont_nack_misc; // @[DCache.scala:441:61, :445:67]
wire _io_cpu_s2_nack_T_3 = _io_cpu_s2_nack_T_1 & _io_cpu_s2_nack_T_2; // @[DCache.scala:445:{38,64,67}]
wire _io_cpu_s2_nack_T_4 = ~s2_valid_hit; // @[DCache.scala:422:48, :445:89]
assign _io_cpu_s2_nack_T_5 = _io_cpu_s2_nack_T_3 & _io_cpu_s2_nack_T_4; // @[DCache.scala:445:{64,86,89}]
assign io_cpu_s2_nack_0 = _io_cpu_s2_nack_T_5; // @[DCache.scala:101:7, :445:86]
assign _metaArb_io_in_2_valid_T = s2_valid_hit_pre_data_ecc_and_waw & s2_update_meta; // @[Metadata.scala:47:40]
wire _metaArb_io_in_1_valid_T = s2_valid_masked | s2_flush_valid_pre_tag_ecc; // @[DCache.scala:337:42, :355:43, :450:63]
wire _metaArb_io_in_1_valid_T_1 = _metaArb_io_in_1_valid_T; // @[DCache.scala:450:{63,93}]
wire [7:0] _metaArb_io_in_1_bits_idx_T_1 = s2_vaddr[13:6]; // @[DCache.scala:351:21, :453:76]
assign _metaArb_io_in_2_bits_idx_T = s2_vaddr[13:6]; // @[DCache.scala:351:21, :453:76, :465:40]
assign _metaArb_io_in_3_bits_idx_T = s2_vaddr[13:6]; // @[DCache.scala:351:21, :453:76, :744:40]
assign _metaArb_io_in_1_bits_idx_T_2 = _metaArb_io_in_1_bits_idx_T_1; // @[DCache.scala:453:{35,76}]
assign metaArb_io_in_1_bits_idx = _metaArb_io_in_1_bits_idx_T_2; // @[DCache.scala:135:28, :453:35]
wire [13:0] _metaArb_io_in_1_bits_addr_T_1 = {_metaArb_io_in_1_bits_idx_T_2, 6'h0}; // @[DCache.scala:453:35, :454:98]
assign _metaArb_io_in_1_bits_addr_T_2 = {_metaArb_io_in_1_bits_addr_T, _metaArb_io_in_1_bits_addr_T_1}; // @[DCache.scala:454:{36,58,98}]
assign metaArb_io_in_1_bits_addr = _metaArb_io_in_1_bits_addr_T_2; // @[DCache.scala:135:28, :454:36]
assign metaArb_io_in_2_valid = _metaArb_io_in_2_valid_T; // @[DCache.scala:135:28, :462:63]
assign metaArb_io_in_2_bits_way_en = s2_victim_or_hit_way[0]; // @[DCache.scala:135:28, :432:33, :464:32]
assign metaArb_io_in_2_bits_idx = _metaArb_io_in_2_bits_idx_T; // @[DCache.scala:135:28, :465:40]
wire [13:0] _metaArb_io_in_2_bits_addr_T_1 = s2_vaddr[13:0]; // @[DCache.scala:351:21, :466:80]
wire [13:0] _metaArb_io_in_3_bits_addr_T_1 = s2_vaddr[13:0]; // @[DCache.scala:351:21, :466:80, :745:80]
assign _metaArb_io_in_2_bits_addr_T_2 = {_metaArb_io_in_2_bits_addr_T, _metaArb_io_in_2_bits_addr_T_1}; // @[DCache.scala:466:{36,58,80}]
assign metaArb_io_in_2_bits_addr = _metaArb_io_in_2_bits_addr_T_2; // @[DCache.scala:135:28, :466:36]
wire [19:0] _metaArb_io_in_2_bits_data_T = s2_req_addr[33:14]; // @[DCache.scala:339:19, :467:68]
wire [19:0] _metaArb_io_in_3_bits_data_T = s2_req_addr[33:14]; // @[DCache.scala:339:19, :467:68, :746:68]
wire [17:0] metaArb_io_in_2_bits_data_meta_tag; // @[HellaCache.scala:305:20]
assign metaArb_io_in_2_bits_data_meta_tag = _metaArb_io_in_2_bits_data_T[17:0]; // @[HellaCache.scala:305:20, :306:14]
assign _metaArb_io_in_2_bits_data_T_1 = {metaArb_io_in_2_bits_data_meta_coh_state, metaArb_io_in_2_bits_data_meta_tag}; // @[HellaCache.scala:305:20]
assign metaArb_io_in_2_bits_data = _metaArb_io_in_2_bits_data_T_1; // @[DCache.scala:135:28, :467:97]
reg [6:0] lrscCount; // @[DCache.scala:472:26]
wire lrscValid = |(lrscCount[6:2]); // @[DCache.scala:472:26, :473:29]
wire _lrscBackingOff_T = |lrscCount; // @[DCache.scala:472:26, :474:34]
wire _lrscBackingOff_T_1 = ~lrscValid; // @[DCache.scala:473:29, :474:43]
wire lrscBackingOff = _lrscBackingOff_T & _lrscBackingOff_T_1; // @[DCache.scala:474:{34,40,43}]
reg [27:0] lrscAddr; // @[DCache.scala:475:21]
wire [27:0] _lrscAddrMatch_T = s2_req_addr[33:6]; // @[DCache.scala:339:19, :476:49]
wire [27:0] _lrscAddr_T = s2_req_addr[33:6]; // @[DCache.scala:339:19, :476:49, :480:29]
wire [27:0] _acquire_address_T = s2_req_addr[33:6]; // @[DCache.scala:339:19, :476:49, :578:38]
wire [27:0] _error_addr_T_2 = s2_req_addr[33:6]; // @[DCache.scala:339:19, :476:49, :1119:27]
wire [27:0] _io_errors_bus_bits_T = s2_req_addr[33:6]; // @[DCache.scala:339:19, :476:49, :1130:58]
wire lrscAddrMatch = lrscAddr == _lrscAddrMatch_T; // @[DCache.scala:475:21, :476:{32,49}]
wire _s2_sc_fail_T = lrscValid & lrscAddrMatch; // @[DCache.scala:473:29, :476:32, :477:41]
wire _s2_sc_fail_T_1 = ~_s2_sc_fail_T; // @[DCache.scala:477:{29,41}]
wire [6:0] _lrscCount_T = s2_hit ? 7'h4F : 7'h0; // @[Misc.scala:35:9]
wire [7:0] _lrscCount_T_1 = {1'h0, lrscCount} - 8'h1; // @[DCache.scala:472:26, :482:51]
wire [6:0] _lrscCount_T_2 = _lrscCount_T_1[6:0]; // @[DCache.scala:482:51]
wire _s2_correct_T = ~any_pstore_valid; // @[DCache.scala:230:30, :487:37]
wire _s2_correct_T_2 = any_pstore_valid | s2_valid; // @[DCache.scala:230:30, :331:25, :487:84]
reg s2_correct_REG; // @[DCache.scala:487:66]
wire _s2_correct_T_3 = ~s2_correct_REG; // @[DCache.scala:487:{58,66}]
wire _GEN_85 = s1_valid_not_nacked & s1_write; // @[DCache.scala:187:38, :492:63]
wire _pstore1_cmd_T; // @[DCache.scala:492:63]
assign _pstore1_cmd_T = _GEN_85; // @[DCache.scala:492:63]
wire _pstore1_addr_T; // @[DCache.scala:493:62]
assign _pstore1_addr_T = _GEN_85; // @[DCache.scala:492:63, :493:62]
wire _pstore1_data_T; // @[DCache.scala:494:73]
assign _pstore1_data_T = _GEN_85; // @[DCache.scala:492:63, :494:73]
wire _pstore1_way_T; // @[DCache.scala:495:63]
assign _pstore1_way_T = _GEN_85; // @[DCache.scala:492:63, :495:63]
wire _pstore1_mask_T; // @[DCache.scala:496:61]
assign _pstore1_mask_T = _GEN_85; // @[DCache.scala:492:63, :496:61]
wire _pstore1_rmw_T_53; // @[DCache.scala:498:84]
assign _pstore1_rmw_T_53 = _GEN_85; // @[DCache.scala:492:63, :498:84]
reg [4:0] pstore1_cmd; // @[DCache.scala:492:30]
reg [33:0] pstore1_addr; // @[DCache.scala:493:31]
wire [33:0] _pstore2_addr_T = pstore1_addr; // @[DCache.scala:493:31, :524:35]
reg [63:0] pstore1_data; // @[DCache.scala:494:31]
assign io_cpu_resp_bits_store_data_0 = pstore1_data; // @[DCache.scala:101:7, :494:31]
wire [63:0] put_data = pstore1_data; // @[Edges.scala:480:17]
wire [63:0] putpartial_data = pstore1_data; // @[Edges.scala:500:17]
wire [63:0] atomics_a_data = pstore1_data; // @[Edges.scala:534:17]
wire [63:0] atomics_a_1_data = pstore1_data; // @[Edges.scala:534:17]
wire [63:0] atomics_a_2_data = pstore1_data; // @[Edges.scala:534:17]
wire [63:0] atomics_a_3_data = pstore1_data; // @[Edges.scala:534:17]
wire [63:0] atomics_a_4_data = pstore1_data; // @[Edges.scala:517:17]
wire [63:0] atomics_a_5_data = pstore1_data; // @[Edges.scala:517:17]
wire [63:0] atomics_a_6_data = pstore1_data; // @[Edges.scala:517:17]
wire [63:0] atomics_a_7_data = pstore1_data; // @[Edges.scala:517:17]
wire [63:0] atomics_a_8_data = pstore1_data; // @[Edges.scala:517:17]
wire [63:0] _amoalu_io_rhs_T = pstore1_data; // @[DCache.scala:494:31, :986:37]
reg pstore1_way; // @[DCache.scala:495:30]
wire _pstore2_way_T = pstore1_way; // @[DCache.scala:495:30, :525:34]
reg [7:0] pstore1_mask; // @[DCache.scala:496:31]
wire [7:0] pstore2_storegen_mask_mergedMask = pstore1_mask; // @[DCache.scala:496:31, :533:37]
wire [7:0] _amoalu_io_mask_T = pstore1_mask; // @[DCache.scala:496:31, :983:38]
wire [7:0] _pstore1_storegen_data_mask_T = pstore1_mask; // @[DCache.scala:496:31, :990:40]
wire [63:0] _pstore1_storegen_data_T_3; // @[DCache.scala:991:52]
wire [63:0] pstore1_storegen_data; // @[DCache.scala:497:42]
wire _pstore1_rmw_T_4 = _pstore1_rmw_T | _pstore1_rmw_T_1; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_5 = _pstore1_rmw_T_4 | _pstore1_rmw_T_2; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_6 = _pstore1_rmw_T_5 | _pstore1_rmw_T_3; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_11 = _pstore1_rmw_T_7 | _pstore1_rmw_T_8; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_12 = _pstore1_rmw_T_11 | _pstore1_rmw_T_9; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_13 = _pstore1_rmw_T_12 | _pstore1_rmw_T_10; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_19 = _pstore1_rmw_T_14 | _pstore1_rmw_T_15; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_20 = _pstore1_rmw_T_19 | _pstore1_rmw_T_16; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_21 = _pstore1_rmw_T_20 | _pstore1_rmw_T_17; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_22 = _pstore1_rmw_T_21 | _pstore1_rmw_T_18; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_23 = _pstore1_rmw_T_13 | _pstore1_rmw_T_22; // @[package.scala:81:59]
wire _pstore1_rmw_T_24 = _pstore1_rmw_T_6 | _pstore1_rmw_T_23; // @[package.scala:81:59]
wire _pstore1_rmw_T_27 = _pstore1_rmw_T_25 | _pstore1_rmw_T_26; // @[Consts.scala:90:{32,42,49}]
wire _pstore1_rmw_T_29 = _pstore1_rmw_T_27 | _pstore1_rmw_T_28; // @[Consts.scala:90:{42,59,66}]
wire _pstore1_rmw_T_34 = _pstore1_rmw_T_30 | _pstore1_rmw_T_31; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_35 = _pstore1_rmw_T_34 | _pstore1_rmw_T_32; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_36 = _pstore1_rmw_T_35 | _pstore1_rmw_T_33; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_42 = _pstore1_rmw_T_37 | _pstore1_rmw_T_38; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_43 = _pstore1_rmw_T_42 | _pstore1_rmw_T_39; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_44 = _pstore1_rmw_T_43 | _pstore1_rmw_T_40; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_45 = _pstore1_rmw_T_44 | _pstore1_rmw_T_41; // @[package.scala:16:47, :81:59]
wire _pstore1_rmw_T_46 = _pstore1_rmw_T_36 | _pstore1_rmw_T_45; // @[package.scala:81:59]
wire _pstore1_rmw_T_47 = _pstore1_rmw_T_29 | _pstore1_rmw_T_46; // @[Consts.scala:87:44, :90:{59,76}]
wire _pstore1_rmw_T_50 = _pstore1_rmw_T_48; // @[DCache.scala:1191:{35,45}]
wire _pstore1_rmw_T_51 = _pstore1_rmw_T_47 & _pstore1_rmw_T_50; // @[DCache.scala:1191:{23,45}]
wire _pstore1_rmw_T_52 = _pstore1_rmw_T_24 | _pstore1_rmw_T_51; // @[DCache.scala:1190:21, :1191:23]
reg pstore1_rmw_r; // @[DCache.scala:498:44]
wire pstore1_rmw = pstore1_rmw_r; // @[DCache.scala:498:{32,44}]
wire _pstore1_merge_likely_T = s2_valid_not_nacked_in_s1 & s2_write; // @[DCache.scala:336:44, :499:56]
wire _GEN_86 = s2_valid_hit & s2_write; // @[DCache.scala:422:48, :490:46]
wire _pstore1_merge_T; // @[DCache.scala:490:46]
assign _pstore1_merge_T = _GEN_86; // @[DCache.scala:490:46]
wire _pstore1_valid_T; // @[DCache.scala:490:46]
assign _pstore1_valid_T = _GEN_86; // @[DCache.scala:490:46]
wire _pstore1_held_T; // @[DCache.scala:490:46]
assign _pstore1_held_T = _GEN_86; // @[DCache.scala:490:46]
wire _pstore1_merge_T_2 = _pstore1_merge_T; // @[DCache.scala:490:{46,58}]
wire _pstore1_merge_T_4 = _pstore1_merge_T_2; // @[DCache.scala:490:58, :491:48]
reg pstore2_valid; // @[DCache.scala:501:30]
wire _pstore_drain_opportunistic_res_T_2 = _pstore_drain_opportunistic_res_T | _pstore_drain_opportunistic_res_T_1; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_res_T_3 = ~_pstore_drain_opportunistic_res_T_2; // @[package.scala:81:59]
wire pstore_drain_opportunistic_res = _pstore_drain_opportunistic_res_T_3; // @[DCache.scala:1185:{15,46}]
wire _pstore_drain_opportunistic_T_4 = _pstore_drain_opportunistic_T | _pstore_drain_opportunistic_T_1; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_5 = _pstore_drain_opportunistic_T_4 | _pstore_drain_opportunistic_T_2; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_6 = _pstore_drain_opportunistic_T_5 | _pstore_drain_opportunistic_T_3; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_11 = _pstore_drain_opportunistic_T_7 | _pstore_drain_opportunistic_T_8; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_12 = _pstore_drain_opportunistic_T_11 | _pstore_drain_opportunistic_T_9; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_13 = _pstore_drain_opportunistic_T_12 | _pstore_drain_opportunistic_T_10; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_19 = _pstore_drain_opportunistic_T_14 | _pstore_drain_opportunistic_T_15; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_20 = _pstore_drain_opportunistic_T_19 | _pstore_drain_opportunistic_T_16; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_21 = _pstore_drain_opportunistic_T_20 | _pstore_drain_opportunistic_T_17; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_22 = _pstore_drain_opportunistic_T_21 | _pstore_drain_opportunistic_T_18; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_23 = _pstore_drain_opportunistic_T_13 | _pstore_drain_opportunistic_T_22; // @[package.scala:81:59]
wire _pstore_drain_opportunistic_T_24 = _pstore_drain_opportunistic_T_6 | _pstore_drain_opportunistic_T_23; // @[package.scala:81:59]
wire _pstore_drain_opportunistic_T_27 = _pstore_drain_opportunistic_T_25 | _pstore_drain_opportunistic_T_26; // @[Consts.scala:90:{32,42,49}]
wire _pstore_drain_opportunistic_T_29 = _pstore_drain_opportunistic_T_27 | _pstore_drain_opportunistic_T_28; // @[Consts.scala:90:{42,59,66}]
wire _pstore_drain_opportunistic_T_34 = _pstore_drain_opportunistic_T_30 | _pstore_drain_opportunistic_T_31; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_35 = _pstore_drain_opportunistic_T_34 | _pstore_drain_opportunistic_T_32; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_36 = _pstore_drain_opportunistic_T_35 | _pstore_drain_opportunistic_T_33; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_42 = _pstore_drain_opportunistic_T_37 | _pstore_drain_opportunistic_T_38; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_43 = _pstore_drain_opportunistic_T_42 | _pstore_drain_opportunistic_T_39; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_44 = _pstore_drain_opportunistic_T_43 | _pstore_drain_opportunistic_T_40; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_45 = _pstore_drain_opportunistic_T_44 | _pstore_drain_opportunistic_T_41; // @[package.scala:16:47, :81:59]
wire _pstore_drain_opportunistic_T_46 = _pstore_drain_opportunistic_T_36 | _pstore_drain_opportunistic_T_45; // @[package.scala:81:59]
wire _pstore_drain_opportunistic_T_47 = _pstore_drain_opportunistic_T_29 | _pstore_drain_opportunistic_T_46; // @[Consts.scala:87:44, :90:{59,76}]
wire _pstore_drain_opportunistic_T_50 = _pstore_drain_opportunistic_T_48; // @[DCache.scala:1191:{35,45}]
wire _pstore_drain_opportunistic_T_51 = _pstore_drain_opportunistic_T_47 & _pstore_drain_opportunistic_T_50; // @[DCache.scala:1191:{23,45}]
wire _pstore_drain_opportunistic_T_52 = _pstore_drain_opportunistic_T_24 | _pstore_drain_opportunistic_T_51; // @[DCache.scala:1190:21, :1191:23]
wire _pstore_drain_opportunistic_T_53 = ~_pstore_drain_opportunistic_T_52; // @[DCache.scala:1186:12, :1190:21]
wire _pstore_drain_opportunistic_T_54 = _pstore_drain_opportunistic_T_53 | pstore_drain_opportunistic_res; // @[DCache.scala:1185:46, :1186:{12,28}]
wire _pstore_drain_opportunistic_T_56 = ~_pstore_drain_opportunistic_T_55; // @[DCache.scala:1186:11]
wire _pstore_drain_opportunistic_T_57 = ~_pstore_drain_opportunistic_T_54; // @[DCache.scala:1186:{11,28}]
wire _pstore_drain_opportunistic_T_58 = io_cpu_req_valid_0 & pstore_drain_opportunistic_res; // @[DCache.scala:101:7, :502:55, :1185:46]
wire _pstore_drain_opportunistic_T_59 = ~_pstore_drain_opportunistic_T_58; // @[DCache.scala:502:{36,55}]
wire pstore_drain_opportunistic = _pstore_drain_opportunistic_T_59; // @[DCache.scala:502:{36,92}]
reg pstore_drain_on_miss_REG; // @[DCache.scala:503:56]
wire pstore_drain_on_miss = pstore_drain_on_miss_REG; // @[DCache.scala:503:{46,56}]
reg pstore1_held; // @[DCache.scala:504:29]
wire _GEN_87 = s2_valid & s2_write; // @[DCache.scala:331:25, :505:39]
wire _pstore1_valid_likely_T; // @[DCache.scala:505:39]
assign _pstore1_valid_likely_T = _GEN_87; // @[DCache.scala:505:39]
wire _io_cpu_perf_storeBufferEmptyAfterLoad_T_1; // @[DCache.scala:1082:16]
assign _io_cpu_perf_storeBufferEmptyAfterLoad_T_1 = _GEN_87; // @[DCache.scala:505:39, :1082:16]
wire _io_cpu_perf_storeBufferEmptyAfterStore_T_1; // @[DCache.scala:1086:15]
assign _io_cpu_perf_storeBufferEmptyAfterStore_T_1 = _GEN_87; // @[DCache.scala:505:39, :1086:15]
wire _io_cpu_perf_storeBufferEmptyAfterStore_T_4; // @[DCache.scala:1087:16]
assign _io_cpu_perf_storeBufferEmptyAfterStore_T_4 = _GEN_87; // @[DCache.scala:505:39, :1087:16]
wire _io_cpu_perf_canAcceptStoreThenLoad_T; // @[DCache.scala:1089:16]
assign _io_cpu_perf_canAcceptStoreThenLoad_T = _GEN_87; // @[DCache.scala:505:39, :1089:16]
wire _io_cpu_perf_canAcceptLoadThenLoad_T_55; // @[DCache.scala:1092:100]
assign _io_cpu_perf_canAcceptLoadThenLoad_T_55 = _GEN_87; // @[DCache.scala:505:39, :1092:100]
wire pstore1_valid_likely = _pstore1_valid_likely_T | pstore1_held; // @[DCache.scala:504:29, :505:{39,51}]
wire _pstore1_valid_T_2 = _pstore1_valid_T; // @[DCache.scala:490:{46,58}]
wire _pstore1_valid_T_4 = _pstore1_valid_T_2; // @[DCache.scala:490:58, :491:48]
wire pstore1_valid = _pstore1_valid_T_4 | pstore1_held; // @[DCache.scala:491:48, :504:29, :507:38]
wire _advance_pstore1_T = pstore1_valid; // @[DCache.scala:507:38, :522:40]
assign _any_pstore_valid_T = pstore1_held | pstore2_valid; // @[DCache.scala:501:30, :504:29, :508:36]
assign any_pstore_valid = _any_pstore_valid_T; // @[DCache.scala:230:30, :508:36]
wire _GEN_88 = pstore1_valid_likely & pstore2_valid; // @[DCache.scala:501:30, :505:51, :509:54]
wire _pstore_drain_structural_T; // @[DCache.scala:509:54]
assign _pstore_drain_structural_T = _GEN_88; // @[DCache.scala:509:54]
wire _io_cpu_perf_canAcceptStoreThenLoad_T_6; // @[DCache.scala:1090:20]
assign _io_cpu_perf_canAcceptStoreThenLoad_T_6 = _GEN_88; // @[DCache.scala:509:54, :1090:20]
wire _GEN_89 = s1_valid & s1_write; // @[DCache.scala:182:25, :509:85]
wire _pstore_drain_structural_T_1; // @[DCache.scala:509:85]
assign _pstore_drain_structural_T_1 = _GEN_89; // @[DCache.scala:509:85]
wire _io_cpu_perf_storeBufferEmptyAfterLoad_T; // @[DCache.scala:1081:15]
assign _io_cpu_perf_storeBufferEmptyAfterLoad_T = _GEN_89; // @[DCache.scala:509:85, :1081:15]
wire _io_cpu_perf_storeBufferEmptyAfterStore_T; // @[DCache.scala:1085:15]
assign _io_cpu_perf_storeBufferEmptyAfterStore_T = _GEN_89; // @[DCache.scala:509:85, :1085:15]
wire _io_cpu_perf_canAcceptStoreThenLoad_T_2; // @[DCache.scala:1089:57]
assign _io_cpu_perf_canAcceptStoreThenLoad_T_2 = _GEN_89; // @[DCache.scala:509:85, :1089:57]
wire _io_cpu_perf_canAcceptStoreThenLoad_T_7; // @[DCache.scala:1090:57]
assign _io_cpu_perf_canAcceptStoreThenLoad_T_7 = _GEN_89; // @[DCache.scala:509:85, :1090:57]
wire _io_cpu_perf_canAcceptLoadThenLoad_T; // @[DCache.scala:1092:52]
assign _io_cpu_perf_canAcceptLoadThenLoad_T = _GEN_89; // @[DCache.scala:509:85, :1092:52]
wire _pstore_drain_structural_T_2 = _pstore_drain_structural_T_1 | pstore1_rmw; // @[DCache.scala:498:32, :509:{85,98}]
wire pstore_drain_structural = _pstore_drain_structural_T & _pstore_drain_structural_T_2; // @[DCache.scala:509:{54,71,98}]
wire _pstore_drain_T_1 = pstore_drain_structural; // @[DCache.scala:509:71, :517:17]
wire _dataArb_io_in_0_valid_T_1 = pstore_drain_structural; // @[DCache.scala:509:71, :517:17]
wire _T_48 = s2_valid_hit_pre_data_ecc & s2_write; // @[DCache.scala:420:69, :506:72]
wire _pstore_drain_T_2; // @[DCache.scala:506:72]
assign _pstore_drain_T_2 = _T_48; // @[DCache.scala:506:72]
wire _dataArb_io_in_0_valid_T_2; // @[DCache.scala:506:72]
assign _dataArb_io_in_0_valid_T_2 = _T_48; // @[DCache.scala:506:72]
wire _pstore_drain_T_4 = _pstore_drain_T_2; // @[DCache.scala:506:{72,84}]
wire _pstore_drain_T_5 = _pstore_drain_T_4 | pstore1_held; // @[DCache.scala:504:29, :506:{84,96}]
wire _pstore_drain_T_6 = ~pstore1_rmw; // @[DCache.scala:498:32, :518:44]
wire _pstore_drain_T_7 = _pstore_drain_T_5 & _pstore_drain_T_6; // @[DCache.scala:506:96, :518:{41,44}]
wire _pstore_drain_T_8 = _pstore_drain_T_7 | pstore2_valid; // @[DCache.scala:501:30, :518:{41,58}]
wire _GEN_90 = pstore_drain_opportunistic | pstore_drain_on_miss; // @[DCache.scala:502:92, :503:46, :518:107]
wire _pstore_drain_T_9; // @[DCache.scala:518:107]
assign _pstore_drain_T_9 = _GEN_90; // @[DCache.scala:518:107]
wire _dataArb_io_in_0_valid_T_9; // @[DCache.scala:518:107]
assign _dataArb_io_in_0_valid_T_9 = _GEN_90; // @[DCache.scala:518:107]
wire _pstore_drain_T_10 = _pstore_drain_T_8 & _pstore_drain_T_9; // @[DCache.scala:518:{58,76,107}]
wire _pstore_drain_T_11 = _pstore_drain_T_1 | _pstore_drain_T_10; // @[DCache.scala:517:{17,44}, :518:76]
assign pstore_drain = _pstore_drain_T_11; // @[DCache.scala:516:27, :517:44]
assign dataArb_io_in_0_bits_write = pstore_drain; // @[DCache.scala:152:28, :516:27]
wire _pstore1_held_T_2 = _pstore1_held_T; // @[DCache.scala:490:{46,58}]
wire _pstore1_held_T_4 = _pstore1_held_T_2; // @[DCache.scala:490:58, :491:48]
wire _pstore1_held_T_6 = _pstore1_held_T_4; // @[DCache.scala:491:48, :521:35]
wire _pstore1_held_T_7 = _pstore1_held_T_6 | pstore1_held; // @[DCache.scala:504:29, :521:{35,54}]
wire _pstore1_held_T_8 = _pstore1_held_T_7 & pstore2_valid; // @[DCache.scala:501:30, :521:{54,71}]
wire _pstore1_held_T_9 = ~pstore_drain; // @[DCache.scala:516:27, :521:91]
wire _pstore1_held_T_10 = _pstore1_held_T_8 & _pstore1_held_T_9; // @[DCache.scala:521:{71,88,91}]
wire _advance_pstore1_T_1 = pstore2_valid == pstore_drain; // @[DCache.scala:501:30, :516:27, :522:79]
wire advance_pstore1 = _advance_pstore1_T & _advance_pstore1_T_1; // @[DCache.scala:522:{40,61,79}]
wire _pstore2_storegen_data_T_3 = advance_pstore1; // @[DCache.scala:522:61, :528:78]
wire _pstore2_storegen_data_T_7 = advance_pstore1; // @[DCache.scala:522:61, :528:78]
wire _pstore2_storegen_data_T_11 = advance_pstore1; // @[DCache.scala:522:61, :528:78]
wire _pstore2_storegen_data_T_15 = advance_pstore1; // @[DCache.scala:522:61, :528:78]
wire _pstore2_storegen_data_T_19 = advance_pstore1; // @[DCache.scala:522:61, :528:78]
wire _pstore2_storegen_data_T_23 = advance_pstore1; // @[DCache.scala:522:61, :528:78]
wire _pstore2_storegen_data_T_27 = advance_pstore1; // @[DCache.scala:522:61, :528:78]
wire _pstore2_storegen_data_T_31 = advance_pstore1; // @[DCache.scala:522:61, :528:78]
wire _pstore2_storegen_mask_T = advance_pstore1; // @[DCache.scala:522:61, :532:27]
wire _pstore2_valid_T = ~pstore_drain; // @[DCache.scala:516:27, :521:91, :523:37]
wire _pstore2_valid_T_1 = pstore2_valid & _pstore2_valid_T; // @[DCache.scala:501:30, :523:{34,37}]
wire _pstore2_valid_T_2 = _pstore2_valid_T_1 | advance_pstore1; // @[DCache.scala:522:61, :523:{34,51}]
reg [33:0] pstore2_addr; // @[DCache.scala:524:31]
reg pstore2_way; // @[DCache.scala:525:30]
wire [7:0] _pstore2_storegen_data_T = pstore1_storegen_data[7:0]; // @[DCache.scala:497:42, :528:44]
wire _pstore2_storegen_data_T_1 = pstore1_mask[0]; // @[DCache.scala:496:31, :528:110]
wire _s1_hazard_T_3 = pstore1_mask[0]; // @[package.scala:211:50]
reg [7:0] pstore2_storegen_data_r; // @[DCache.scala:528:22]
wire [7:0] _pstore2_storegen_data_T_4 = pstore1_storegen_data[15:8]; // @[DCache.scala:497:42, :528:44]
wire _pstore2_storegen_data_T_5 = pstore1_mask[1]; // @[DCache.scala:496:31, :528:110]
wire _s1_hazard_T_4 = pstore1_mask[1]; // @[package.scala:211:50]
reg [7:0] pstore2_storegen_data_r_1; // @[DCache.scala:528:22]
wire [7:0] _pstore2_storegen_data_T_8 = pstore1_storegen_data[23:16]; // @[DCache.scala:497:42, :528:44]
wire _pstore2_storegen_data_T_9 = pstore1_mask[2]; // @[DCache.scala:496:31, :528:110]
wire _s1_hazard_T_5 = pstore1_mask[2]; // @[package.scala:211:50]
reg [7:0] pstore2_storegen_data_r_2; // @[DCache.scala:528:22]
wire [7:0] _pstore2_storegen_data_T_12 = pstore1_storegen_data[31:24]; // @[DCache.scala:497:42, :528:44]
wire _pstore2_storegen_data_T_13 = pstore1_mask[3]; // @[DCache.scala:496:31, :528:110]
wire _s1_hazard_T_6 = pstore1_mask[3]; // @[package.scala:211:50]
reg [7:0] pstore2_storegen_data_r_3; // @[DCache.scala:528:22]
wire [7:0] _pstore2_storegen_data_T_16 = pstore1_storegen_data[39:32]; // @[DCache.scala:497:42, :528:44]
wire _pstore2_storegen_data_T_17 = pstore1_mask[4]; // @[DCache.scala:496:31, :528:110]
wire _s1_hazard_T_7 = pstore1_mask[4]; // @[package.scala:211:50]
reg [7:0] pstore2_storegen_data_r_4; // @[DCache.scala:528:22]
wire [7:0] _pstore2_storegen_data_T_20 = pstore1_storegen_data[47:40]; // @[DCache.scala:497:42, :528:44]
wire _pstore2_storegen_data_T_21 = pstore1_mask[5]; // @[DCache.scala:496:31, :528:110]
wire _s1_hazard_T_8 = pstore1_mask[5]; // @[package.scala:211:50]
reg [7:0] pstore2_storegen_data_r_5; // @[DCache.scala:528:22]
wire [7:0] _pstore2_storegen_data_T_24 = pstore1_storegen_data[55:48]; // @[DCache.scala:497:42, :528:44]
wire _pstore2_storegen_data_T_25 = pstore1_mask[6]; // @[DCache.scala:496:31, :528:110]
wire _s1_hazard_T_9 = pstore1_mask[6]; // @[package.scala:211:50]
reg [7:0] pstore2_storegen_data_r_6; // @[DCache.scala:528:22]
wire [7:0] _pstore2_storegen_data_T_28 = pstore1_storegen_data[63:56]; // @[DCache.scala:497:42, :528:44]
wire _pstore2_storegen_data_T_29 = pstore1_mask[7]; // @[DCache.scala:496:31, :528:110]
wire _s1_hazard_T_10 = pstore1_mask[7]; // @[package.scala:211:50]
reg [7:0] pstore2_storegen_data_r_7; // @[DCache.scala:528:22]
wire [15:0] pstore2_storegen_data_lo_lo = {pstore2_storegen_data_r_1, pstore2_storegen_data_r}; // @[package.scala:45:27]
wire [15:0] pstore2_storegen_data_lo_hi = {pstore2_storegen_data_r_3, pstore2_storegen_data_r_2}; // @[package.scala:45:27]
wire [31:0] pstore2_storegen_data_lo = {pstore2_storegen_data_lo_hi, pstore2_storegen_data_lo_lo}; // @[package.scala:45:27]
wire [15:0] pstore2_storegen_data_hi_lo = {pstore2_storegen_data_r_5, pstore2_storegen_data_r_4}; // @[package.scala:45:27]
wire [15:0] pstore2_storegen_data_hi_hi = {pstore2_storegen_data_r_7, pstore2_storegen_data_r_6}; // @[package.scala:45:27]
wire [31:0] pstore2_storegen_data_hi = {pstore2_storegen_data_hi_hi, pstore2_storegen_data_hi_lo}; // @[package.scala:45:27]
wire [63:0] pstore2_storegen_data = {pstore2_storegen_data_hi, pstore2_storegen_data_lo}; // @[package.scala:45:27]
reg [7:0] pstore2_storegen_mask; // @[DCache.scala:531:19]
wire [7:0] _pstore2_storegen_mask_mask_T = ~pstore2_storegen_mask_mergedMask; // @[DCache.scala:533:37, :534:37]
wire [7:0] _pstore2_storegen_mask_mask_T_1 = _pstore2_storegen_mask_mask_T; // @[DCache.scala:534:{19,37}]
wire [7:0] _pstore2_storegen_mask_mask_T_2 = ~_pstore2_storegen_mask_mask_T_1; // @[DCache.scala:534:{15,19}]
wire _dataArb_io_in_0_valid_T_4 = _dataArb_io_in_0_valid_T_2; // @[DCache.scala:506:{72,84}]
wire _dataArb_io_in_0_valid_T_5 = _dataArb_io_in_0_valid_T_4 | pstore1_held; // @[DCache.scala:504:29, :506:{84,96}]
wire _dataArb_io_in_0_valid_T_6 = ~pstore1_rmw; // @[DCache.scala:498:32, :518:44]
wire _dataArb_io_in_0_valid_T_7 = _dataArb_io_in_0_valid_T_5 & _dataArb_io_in_0_valid_T_6; // @[DCache.scala:506:96, :518:{41,44}]
wire _dataArb_io_in_0_valid_T_8 = _dataArb_io_in_0_valid_T_7 | pstore2_valid; // @[DCache.scala:501:30, :518:{41,58}]
wire _dataArb_io_in_0_valid_T_10 = _dataArb_io_in_0_valid_T_8 & _dataArb_io_in_0_valid_T_9; // @[DCache.scala:518:{58,76,107}]
wire _dataArb_io_in_0_valid_T_11 = _dataArb_io_in_0_valid_T_1 | _dataArb_io_in_0_valid_T_10; // @[DCache.scala:517:{17,44}, :518:76]
assign _dataArb_io_in_0_valid_T_12 = _dataArb_io_in_0_valid_T_11; // @[DCache.scala:516:27, :517:44]
assign dataArb_io_in_0_valid = _dataArb_io_in_0_valid_T_12; // @[DCache.scala:152:28, :516:27]
wire [33:0] _GEN_91 = pstore2_valid ? pstore2_addr : pstore1_addr; // @[DCache.scala:493:31, :501:30, :524:31, :549:36]
wire [33:0] _dataArb_io_in_0_bits_addr_T; // @[DCache.scala:549:36]
assign _dataArb_io_in_0_bits_addr_T = _GEN_91; // @[DCache.scala:549:36]
wire [33:0] _dataArb_io_in_0_bits_wordMask_wordMask_T; // @[DCache.scala:554:32]
assign _dataArb_io_in_0_bits_wordMask_wordMask_T = _GEN_91; // @[DCache.scala:549:36, :554:32]
assign dataArb_io_in_0_bits_addr = _dataArb_io_in_0_bits_addr_T[13:0]; // @[DCache.scala:152:28, :549:{30,36}]
assign dataArb_io_in_1_bits_addr = _dataArb_io_in_0_bits_addr_T[13:0]; // @[DCache.scala:152:28, :549:{30,36}]
assign _dataArb_io_in_0_bits_way_en_T = pstore2_valid ? pstore2_way : pstore1_way; // @[DCache.scala:495:30, :501:30, :525:30, :550:38]
assign dataArb_io_in_0_bits_way_en = _dataArb_io_in_0_bits_way_en_T; // @[DCache.scala:152:28, :550:38]
assign dataArb_io_in_1_bits_way_en = _dataArb_io_in_0_bits_way_en_T; // @[DCache.scala:152:28, :550:38]
wire [63:0] _dataArb_io_in_0_bits_wdata_T = pstore2_valid ? pstore2_storegen_data : pstore1_data; // @[package.scala:45:27]
wire [7:0] _dataArb_io_in_0_bits_wdata_T_1 = _dataArb_io_in_0_bits_wdata_T[7:0]; // @[package.scala:211:50]
wire [7:0] _dataArb_io_in_0_bits_wdata_T_2 = _dataArb_io_in_0_bits_wdata_T[15:8]; // @[package.scala:211:50]
wire [7:0] _dataArb_io_in_0_bits_wdata_T_3 = _dataArb_io_in_0_bits_wdata_T[23:16]; // @[package.scala:211:50]
wire [7:0] _dataArb_io_in_0_bits_wdata_T_4 = _dataArb_io_in_0_bits_wdata_T[31:24]; // @[package.scala:211:50]
wire [7:0] _dataArb_io_in_0_bits_wdata_T_5 = _dataArb_io_in_0_bits_wdata_T[39:32]; // @[package.scala:211:50]
wire [7:0] _dataArb_io_in_0_bits_wdata_T_6 = _dataArb_io_in_0_bits_wdata_T[47:40]; // @[package.scala:211:50]
wire [7:0] _dataArb_io_in_0_bits_wdata_T_7 = _dataArb_io_in_0_bits_wdata_T[55:48]; // @[package.scala:211:50]
wire [7:0] _dataArb_io_in_0_bits_wdata_T_8 = _dataArb_io_in_0_bits_wdata_T[63:56]; // @[package.scala:211:50]
wire [15:0] dataArb_io_in_0_bits_wdata_lo_lo = {_dataArb_io_in_0_bits_wdata_T_2, _dataArb_io_in_0_bits_wdata_T_1}; // @[package.scala:45:27, :211:50]
wire [15:0] dataArb_io_in_0_bits_wdata_lo_hi = {_dataArb_io_in_0_bits_wdata_T_4, _dataArb_io_in_0_bits_wdata_T_3}; // @[package.scala:45:27, :211:50]
wire [31:0] dataArb_io_in_0_bits_wdata_lo = {dataArb_io_in_0_bits_wdata_lo_hi, dataArb_io_in_0_bits_wdata_lo_lo}; // @[package.scala:45:27]
wire [15:0] dataArb_io_in_0_bits_wdata_hi_lo = {_dataArb_io_in_0_bits_wdata_T_6, _dataArb_io_in_0_bits_wdata_T_5}; // @[package.scala:45:27, :211:50]
wire [15:0] dataArb_io_in_0_bits_wdata_hi_hi = {_dataArb_io_in_0_bits_wdata_T_8, _dataArb_io_in_0_bits_wdata_T_7}; // @[package.scala:45:27, :211:50]
wire [31:0] dataArb_io_in_0_bits_wdata_hi = {dataArb_io_in_0_bits_wdata_hi_hi, dataArb_io_in_0_bits_wdata_hi_lo}; // @[package.scala:45:27]
assign _dataArb_io_in_0_bits_wdata_T_9 = {dataArb_io_in_0_bits_wdata_hi, dataArb_io_in_0_bits_wdata_lo}; // @[package.scala:45:27]
assign dataArb_io_in_0_bits_wdata = _dataArb_io_in_0_bits_wdata_T_9; // @[package.scala:45:27]
assign dataArb_io_in_1_bits_wdata = _dataArb_io_in_0_bits_wdata_T_9; // @[package.scala:45:27]
assign dataArb_io_in_2_bits_wdata = _dataArb_io_in_0_bits_wdata_T_9; // @[package.scala:45:27]
assign dataArb_io_in_3_bits_wdata = _dataArb_io_in_0_bits_wdata_T_9; // @[package.scala:45:27]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T = _dataArb_io_in_0_bits_eccMask_T_17[0]; // @[package.scala:45:27]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_1 = _dataArb_io_in_0_bits_eccMask_T_17[1]; // @[package.scala:45:27]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_2 = _dataArb_io_in_0_bits_eccMask_T_17[2]; // @[package.scala:45:27]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_3 = _dataArb_io_in_0_bits_eccMask_T_17[3]; // @[package.scala:45:27]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_4 = _dataArb_io_in_0_bits_eccMask_T_17[4]; // @[package.scala:45:27]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_5 = _dataArb_io_in_0_bits_eccMask_T_17[5]; // @[package.scala:45:27]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_6 = _dataArb_io_in_0_bits_eccMask_T_17[6]; // @[package.scala:45:27]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_7 = _dataArb_io_in_0_bits_eccMask_T_17[7]; // @[package.scala:45:27]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_8 = _dataArb_io_in_0_bits_wordMask_eccMask_T | _dataArb_io_in_0_bits_wordMask_eccMask_T_1; // @[package.scala:81:59]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_9 = _dataArb_io_in_0_bits_wordMask_eccMask_T_8 | _dataArb_io_in_0_bits_wordMask_eccMask_T_2; // @[package.scala:81:59]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_10 = _dataArb_io_in_0_bits_wordMask_eccMask_T_9 | _dataArb_io_in_0_bits_wordMask_eccMask_T_3; // @[package.scala:81:59]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_11 = _dataArb_io_in_0_bits_wordMask_eccMask_T_10 | _dataArb_io_in_0_bits_wordMask_eccMask_T_4; // @[package.scala:81:59]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_12 = _dataArb_io_in_0_bits_wordMask_eccMask_T_11 | _dataArb_io_in_0_bits_wordMask_eccMask_T_5; // @[package.scala:81:59]
wire _dataArb_io_in_0_bits_wordMask_eccMask_T_13 = _dataArb_io_in_0_bits_wordMask_eccMask_T_12 | _dataArb_io_in_0_bits_wordMask_eccMask_T_6; // @[package.scala:81:59]
wire dataArb_io_in_0_bits_wordMask_eccMask = _dataArb_io_in_0_bits_wordMask_eccMask_T_13 | _dataArb_io_in_0_bits_wordMask_eccMask_T_7; // @[package.scala:81:59]
wire [1:0] _dataArb_io_in_0_bits_wordMask_T_3 = {1'h0, dataArb_io_in_0_bits_wordMask_eccMask}; // @[package.scala:81:59]
assign dataArb_io_in_0_bits_wordMask = _dataArb_io_in_0_bits_wordMask_T_3[0]; // @[DCache.scala:152:28, :552:34, :555:55]
assign dataArb_io_in_1_bits_wordMask = _dataArb_io_in_0_bits_wordMask_T_3[0]; // @[DCache.scala:152:28, :552:34, :555:55]
wire [7:0] _dataArb_io_in_0_bits_eccMask_T = pstore2_valid ? pstore2_storegen_mask : pstore1_mask; // @[DCache.scala:496:31, :501:30, :531:19, :557:47]
wire _dataArb_io_in_0_bits_eccMask_T_1 = _dataArb_io_in_0_bits_eccMask_T[0]; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_9 = _dataArb_io_in_0_bits_eccMask_T_1; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_2 = _dataArb_io_in_0_bits_eccMask_T[1]; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_10 = _dataArb_io_in_0_bits_eccMask_T_2; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_3 = _dataArb_io_in_0_bits_eccMask_T[2]; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_11 = _dataArb_io_in_0_bits_eccMask_T_3; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_4 = _dataArb_io_in_0_bits_eccMask_T[3]; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_12 = _dataArb_io_in_0_bits_eccMask_T_4; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_5 = _dataArb_io_in_0_bits_eccMask_T[4]; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_13 = _dataArb_io_in_0_bits_eccMask_T_5; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_6 = _dataArb_io_in_0_bits_eccMask_T[5]; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_14 = _dataArb_io_in_0_bits_eccMask_T_6; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_7 = _dataArb_io_in_0_bits_eccMask_T[6]; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_15 = _dataArb_io_in_0_bits_eccMask_T_7; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_8 = _dataArb_io_in_0_bits_eccMask_T[7]; // @[package.scala:211:50]
wire _dataArb_io_in_0_bits_eccMask_T_16 = _dataArb_io_in_0_bits_eccMask_T_8; // @[package.scala:211:50]
wire [1:0] dataArb_io_in_0_bits_eccMask_lo_lo = {_dataArb_io_in_0_bits_eccMask_T_10, _dataArb_io_in_0_bits_eccMask_T_9}; // @[package.scala:45:27]
wire [1:0] dataArb_io_in_0_bits_eccMask_lo_hi = {_dataArb_io_in_0_bits_eccMask_T_12, _dataArb_io_in_0_bits_eccMask_T_11}; // @[package.scala:45:27]
wire [3:0] dataArb_io_in_0_bits_eccMask_lo = {dataArb_io_in_0_bits_eccMask_lo_hi, dataArb_io_in_0_bits_eccMask_lo_lo}; // @[package.scala:45:27]
wire [1:0] dataArb_io_in_0_bits_eccMask_hi_lo = {_dataArb_io_in_0_bits_eccMask_T_14, _dataArb_io_in_0_bits_eccMask_T_13}; // @[package.scala:45:27]
wire [1:0] dataArb_io_in_0_bits_eccMask_hi_hi = {_dataArb_io_in_0_bits_eccMask_T_16, _dataArb_io_in_0_bits_eccMask_T_15}; // @[package.scala:45:27]
wire [3:0] dataArb_io_in_0_bits_eccMask_hi = {dataArb_io_in_0_bits_eccMask_hi_hi, dataArb_io_in_0_bits_eccMask_hi_lo}; // @[package.scala:45:27]
assign _dataArb_io_in_0_bits_eccMask_T_17 = {dataArb_io_in_0_bits_eccMask_hi, dataArb_io_in_0_bits_eccMask_lo}; // @[package.scala:45:27]
assign dataArb_io_in_0_bits_eccMask = _dataArb_io_in_0_bits_eccMask_T_17; // @[package.scala:45:27]
assign dataArb_io_in_1_bits_eccMask = _dataArb_io_in_0_bits_eccMask_T_17; // @[package.scala:45:27]
wire [10:0] _s1_hazard_T = pstore1_addr[13:3]; // @[DCache.scala:493:31, :561:9]
wire [10:0] _s1_hazard_T_1 = s1_vaddr[13:3]; // @[DCache.scala:197:21, :561:43]
wire [10:0] _s1_hazard_T_63 = s1_vaddr[13:3]; // @[DCache.scala:197:21, :561:43]
wire _s1_hazard_T_2 = _s1_hazard_T == _s1_hazard_T_1; // @[DCache.scala:561:{9,31,43}]
wire _s1_hazard_T_11 = _s1_hazard_T_3; // @[package.scala:211:50]
wire _s1_hazard_T_12 = _s1_hazard_T_4; // @[package.scala:211:50]
wire _s1_hazard_T_13 = _s1_hazard_T_5; // @[package.scala:211:50]
wire _s1_hazard_T_14 = _s1_hazard_T_6; // @[package.scala:211:50]
wire _s1_hazard_T_15 = _s1_hazard_T_7; // @[package.scala:211:50]
wire _s1_hazard_T_16 = _s1_hazard_T_8; // @[package.scala:211:50]
wire _s1_hazard_T_17 = _s1_hazard_T_9; // @[package.scala:211:50]
wire _s1_hazard_T_18 = _s1_hazard_T_10; // @[package.scala:211:50]
wire [1:0] s1_hazard_lo_lo = {_s1_hazard_T_12, _s1_hazard_T_11}; // @[package.scala:45:27]
wire [1:0] s1_hazard_lo_hi = {_s1_hazard_T_14, _s1_hazard_T_13}; // @[package.scala:45:27]
wire [3:0] s1_hazard_lo = {s1_hazard_lo_hi, s1_hazard_lo_lo}; // @[package.scala:45:27]
wire [1:0] s1_hazard_hi_lo = {_s1_hazard_T_16, _s1_hazard_T_15}; // @[package.scala:45:27]
wire [1:0] s1_hazard_hi_hi = {_s1_hazard_T_18, _s1_hazard_T_17}; // @[package.scala:45:27]
wire [3:0] s1_hazard_hi = {s1_hazard_hi_hi, s1_hazard_hi_lo}; // @[package.scala:45:27]
wire [7:0] _s1_hazard_T_19 = {s1_hazard_hi, s1_hazard_lo}; // @[package.scala:45:27]
wire _s1_hazard_T_20 = _s1_hazard_T_19[0]; // @[package.scala:45:27]
wire _s1_hazard_T_21 = _s1_hazard_T_19[1]; // @[package.scala:45:27]
wire _s1_hazard_T_22 = _s1_hazard_T_19[2]; // @[package.scala:45:27]
wire _s1_hazard_T_23 = _s1_hazard_T_19[3]; // @[package.scala:45:27]
wire _s1_hazard_T_24 = _s1_hazard_T_19[4]; // @[package.scala:45:27]
wire _s1_hazard_T_25 = _s1_hazard_T_19[5]; // @[package.scala:45:27]
wire _s1_hazard_T_26 = _s1_hazard_T_19[6]; // @[package.scala:45:27]
wire _s1_hazard_T_27 = _s1_hazard_T_19[7]; // @[package.scala:45:27]
wire [1:0] s1_hazard_lo_lo_1 = {_s1_hazard_T_21, _s1_hazard_T_20}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_lo_hi_1 = {_s1_hazard_T_23, _s1_hazard_T_22}; // @[DCache.scala:1182:52]
wire [3:0] s1_hazard_lo_1 = {s1_hazard_lo_hi_1, s1_hazard_lo_lo_1}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_hi_lo_1 = {_s1_hazard_T_25, _s1_hazard_T_24}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_hi_hi_1 = {_s1_hazard_T_27, _s1_hazard_T_26}; // @[DCache.scala:1182:52]
wire [3:0] s1_hazard_hi_1 = {s1_hazard_hi_hi_1, s1_hazard_hi_lo_1}; // @[DCache.scala:1182:52]
wire [7:0] _s1_hazard_T_28 = {s1_hazard_hi_1, s1_hazard_lo_1}; // @[DCache.scala:1182:52]
wire _s1_hazard_T_29 = s1_mask_xwr[0]; // @[package.scala:211:50]
wire _s1_hazard_T_91 = s1_mask_xwr[0]; // @[package.scala:211:50]
wire _s1_hazard_T_37 = _s1_hazard_T_29; // @[package.scala:211:50]
wire _s1_hazard_T_30 = s1_mask_xwr[1]; // @[package.scala:211:50]
wire _s1_hazard_T_92 = s1_mask_xwr[1]; // @[package.scala:211:50]
wire _s1_hazard_T_38 = _s1_hazard_T_30; // @[package.scala:211:50]
wire _s1_hazard_T_31 = s1_mask_xwr[2]; // @[package.scala:211:50]
wire _s1_hazard_T_93 = s1_mask_xwr[2]; // @[package.scala:211:50]
wire _s1_hazard_T_39 = _s1_hazard_T_31; // @[package.scala:211:50]
wire _s1_hazard_T_32 = s1_mask_xwr[3]; // @[package.scala:211:50]
wire _s1_hazard_T_94 = s1_mask_xwr[3]; // @[package.scala:211:50]
wire _s1_hazard_T_40 = _s1_hazard_T_32; // @[package.scala:211:50]
wire _s1_hazard_T_33 = s1_mask_xwr[4]; // @[package.scala:211:50]
wire _s1_hazard_T_95 = s1_mask_xwr[4]; // @[package.scala:211:50]
wire _s1_hazard_T_41 = _s1_hazard_T_33; // @[package.scala:211:50]
wire _s1_hazard_T_34 = s1_mask_xwr[5]; // @[package.scala:211:50]
wire _s1_hazard_T_96 = s1_mask_xwr[5]; // @[package.scala:211:50]
wire _s1_hazard_T_42 = _s1_hazard_T_34; // @[package.scala:211:50]
wire _s1_hazard_T_35 = s1_mask_xwr[6]; // @[package.scala:211:50]
wire _s1_hazard_T_97 = s1_mask_xwr[6]; // @[package.scala:211:50]
wire _s1_hazard_T_43 = _s1_hazard_T_35; // @[package.scala:211:50]
wire _s1_hazard_T_36 = s1_mask_xwr[7]; // @[package.scala:211:50]
wire _s1_hazard_T_98 = s1_mask_xwr[7]; // @[package.scala:211:50]
wire _s1_hazard_T_44 = _s1_hazard_T_36; // @[package.scala:211:50]
wire [1:0] s1_hazard_lo_lo_2 = {_s1_hazard_T_38, _s1_hazard_T_37}; // @[package.scala:45:27]
wire [1:0] s1_hazard_lo_hi_2 = {_s1_hazard_T_40, _s1_hazard_T_39}; // @[package.scala:45:27]
wire [3:0] s1_hazard_lo_2 = {s1_hazard_lo_hi_2, s1_hazard_lo_lo_2}; // @[package.scala:45:27]
wire [1:0] s1_hazard_hi_lo_2 = {_s1_hazard_T_42, _s1_hazard_T_41}; // @[package.scala:45:27]
wire [1:0] s1_hazard_hi_hi_2 = {_s1_hazard_T_44, _s1_hazard_T_43}; // @[package.scala:45:27]
wire [3:0] s1_hazard_hi_2 = {s1_hazard_hi_hi_2, s1_hazard_hi_lo_2}; // @[package.scala:45:27]
wire [7:0] _s1_hazard_T_45 = {s1_hazard_hi_2, s1_hazard_lo_2}; // @[package.scala:45:27]
wire _s1_hazard_T_46 = _s1_hazard_T_45[0]; // @[package.scala:45:27]
wire _s1_hazard_T_47 = _s1_hazard_T_45[1]; // @[package.scala:45:27]
wire _s1_hazard_T_48 = _s1_hazard_T_45[2]; // @[package.scala:45:27]
wire _s1_hazard_T_49 = _s1_hazard_T_45[3]; // @[package.scala:45:27]
wire _s1_hazard_T_50 = _s1_hazard_T_45[4]; // @[package.scala:45:27]
wire _s1_hazard_T_51 = _s1_hazard_T_45[5]; // @[package.scala:45:27]
wire _s1_hazard_T_52 = _s1_hazard_T_45[6]; // @[package.scala:45:27]
wire _s1_hazard_T_53 = _s1_hazard_T_45[7]; // @[package.scala:45:27]
wire [1:0] s1_hazard_lo_lo_3 = {_s1_hazard_T_47, _s1_hazard_T_46}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_lo_hi_3 = {_s1_hazard_T_49, _s1_hazard_T_48}; // @[DCache.scala:1182:52]
wire [3:0] s1_hazard_lo_3 = {s1_hazard_lo_hi_3, s1_hazard_lo_lo_3}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_hi_lo_3 = {_s1_hazard_T_51, _s1_hazard_T_50}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_hi_hi_3 = {_s1_hazard_T_53, _s1_hazard_T_52}; // @[DCache.scala:1182:52]
wire [3:0] s1_hazard_hi_3 = {s1_hazard_hi_hi_3, s1_hazard_hi_lo_3}; // @[DCache.scala:1182:52]
wire [7:0] _s1_hazard_T_54 = {s1_hazard_hi_3, s1_hazard_lo_3}; // @[DCache.scala:1182:52]
wire [7:0] _s1_hazard_T_55 = _s1_hazard_T_28 & _s1_hazard_T_54; // @[DCache.scala:562:38, :1182:52]
wire _s1_hazard_T_56 = |_s1_hazard_T_55; // @[DCache.scala:562:{38,66}]
wire [7:0] _s1_hazard_T_57 = pstore1_mask & s1_mask_xwr; // @[DCache.scala:496:31, :562:77]
wire _s1_hazard_T_58 = |_s1_hazard_T_57; // @[DCache.scala:562:{77,92}]
wire _s1_hazard_T_59 = s1_write ? _s1_hazard_T_56 : _s1_hazard_T_58; // @[DCache.scala:562:{8,66,92}]
wire _s1_hazard_T_60 = _s1_hazard_T_2 & _s1_hazard_T_59; // @[DCache.scala:561:{31,65}, :562:8]
wire _s1_hazard_T_61 = pstore1_valid_likely & _s1_hazard_T_60; // @[DCache.scala:505:51, :561:65, :564:27]
wire [10:0] _s1_hazard_T_62 = pstore2_addr[13:3]; // @[DCache.scala:524:31, :561:9]
wire _s1_hazard_T_64 = _s1_hazard_T_62 == _s1_hazard_T_63; // @[DCache.scala:561:{9,31,43}]
wire _s1_hazard_T_65 = pstore2_storegen_mask[0]; // @[package.scala:211:50]
wire _s1_hazard_T_73 = _s1_hazard_T_65; // @[package.scala:211:50]
wire _s1_hazard_T_66 = pstore2_storegen_mask[1]; // @[package.scala:211:50]
wire _s1_hazard_T_74 = _s1_hazard_T_66; // @[package.scala:211:50]
wire _s1_hazard_T_67 = pstore2_storegen_mask[2]; // @[package.scala:211:50]
wire _s1_hazard_T_75 = _s1_hazard_T_67; // @[package.scala:211:50]
wire _s1_hazard_T_68 = pstore2_storegen_mask[3]; // @[package.scala:211:50]
wire _s1_hazard_T_76 = _s1_hazard_T_68; // @[package.scala:211:50]
wire _s1_hazard_T_69 = pstore2_storegen_mask[4]; // @[package.scala:211:50]
wire _s1_hazard_T_77 = _s1_hazard_T_69; // @[package.scala:211:50]
wire _s1_hazard_T_70 = pstore2_storegen_mask[5]; // @[package.scala:211:50]
wire _s1_hazard_T_78 = _s1_hazard_T_70; // @[package.scala:211:50]
wire _s1_hazard_T_71 = pstore2_storegen_mask[6]; // @[package.scala:211:50]
wire _s1_hazard_T_79 = _s1_hazard_T_71; // @[package.scala:211:50]
wire _s1_hazard_T_72 = pstore2_storegen_mask[7]; // @[package.scala:211:50]
wire _s1_hazard_T_80 = _s1_hazard_T_72; // @[package.scala:211:50]
wire [1:0] s1_hazard_lo_lo_4 = {_s1_hazard_T_74, _s1_hazard_T_73}; // @[package.scala:45:27]
wire [1:0] s1_hazard_lo_hi_4 = {_s1_hazard_T_76, _s1_hazard_T_75}; // @[package.scala:45:27]
wire [3:0] s1_hazard_lo_4 = {s1_hazard_lo_hi_4, s1_hazard_lo_lo_4}; // @[package.scala:45:27]
wire [1:0] s1_hazard_hi_lo_4 = {_s1_hazard_T_78, _s1_hazard_T_77}; // @[package.scala:45:27]
wire [1:0] s1_hazard_hi_hi_4 = {_s1_hazard_T_80, _s1_hazard_T_79}; // @[package.scala:45:27]
wire [3:0] s1_hazard_hi_4 = {s1_hazard_hi_hi_4, s1_hazard_hi_lo_4}; // @[package.scala:45:27]
wire [7:0] _s1_hazard_T_81 = {s1_hazard_hi_4, s1_hazard_lo_4}; // @[package.scala:45:27]
wire _s1_hazard_T_82 = _s1_hazard_T_81[0]; // @[package.scala:45:27]
wire _s1_hazard_T_83 = _s1_hazard_T_81[1]; // @[package.scala:45:27]
wire _s1_hazard_T_84 = _s1_hazard_T_81[2]; // @[package.scala:45:27]
wire _s1_hazard_T_85 = _s1_hazard_T_81[3]; // @[package.scala:45:27]
wire _s1_hazard_T_86 = _s1_hazard_T_81[4]; // @[package.scala:45:27]
wire _s1_hazard_T_87 = _s1_hazard_T_81[5]; // @[package.scala:45:27]
wire _s1_hazard_T_88 = _s1_hazard_T_81[6]; // @[package.scala:45:27]
wire _s1_hazard_T_89 = _s1_hazard_T_81[7]; // @[package.scala:45:27]
wire [1:0] s1_hazard_lo_lo_5 = {_s1_hazard_T_83, _s1_hazard_T_82}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_lo_hi_5 = {_s1_hazard_T_85, _s1_hazard_T_84}; // @[DCache.scala:1182:52]
wire [3:0] s1_hazard_lo_5 = {s1_hazard_lo_hi_5, s1_hazard_lo_lo_5}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_hi_lo_5 = {_s1_hazard_T_87, _s1_hazard_T_86}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_hi_hi_5 = {_s1_hazard_T_89, _s1_hazard_T_88}; // @[DCache.scala:1182:52]
wire [3:0] s1_hazard_hi_5 = {s1_hazard_hi_hi_5, s1_hazard_hi_lo_5}; // @[DCache.scala:1182:52]
wire [7:0] _s1_hazard_T_90 = {s1_hazard_hi_5, s1_hazard_lo_5}; // @[DCache.scala:1182:52]
wire _s1_hazard_T_99 = _s1_hazard_T_91; // @[package.scala:211:50]
wire _s1_hazard_T_100 = _s1_hazard_T_92; // @[package.scala:211:50]
wire _s1_hazard_T_101 = _s1_hazard_T_93; // @[package.scala:211:50]
wire _s1_hazard_T_102 = _s1_hazard_T_94; // @[package.scala:211:50]
wire _s1_hazard_T_103 = _s1_hazard_T_95; // @[package.scala:211:50]
wire _s1_hazard_T_104 = _s1_hazard_T_96; // @[package.scala:211:50]
wire _s1_hazard_T_105 = _s1_hazard_T_97; // @[package.scala:211:50]
wire _s1_hazard_T_106 = _s1_hazard_T_98; // @[package.scala:211:50]
wire [1:0] s1_hazard_lo_lo_6 = {_s1_hazard_T_100, _s1_hazard_T_99}; // @[package.scala:45:27]
wire [1:0] s1_hazard_lo_hi_6 = {_s1_hazard_T_102, _s1_hazard_T_101}; // @[package.scala:45:27]
wire [3:0] s1_hazard_lo_6 = {s1_hazard_lo_hi_6, s1_hazard_lo_lo_6}; // @[package.scala:45:27]
wire [1:0] s1_hazard_hi_lo_6 = {_s1_hazard_T_104, _s1_hazard_T_103}; // @[package.scala:45:27]
wire [1:0] s1_hazard_hi_hi_6 = {_s1_hazard_T_106, _s1_hazard_T_105}; // @[package.scala:45:27]
wire [3:0] s1_hazard_hi_6 = {s1_hazard_hi_hi_6, s1_hazard_hi_lo_6}; // @[package.scala:45:27]
wire [7:0] _s1_hazard_T_107 = {s1_hazard_hi_6, s1_hazard_lo_6}; // @[package.scala:45:27]
wire _s1_hazard_T_108 = _s1_hazard_T_107[0]; // @[package.scala:45:27]
wire _s1_hazard_T_109 = _s1_hazard_T_107[1]; // @[package.scala:45:27]
wire _s1_hazard_T_110 = _s1_hazard_T_107[2]; // @[package.scala:45:27]
wire _s1_hazard_T_111 = _s1_hazard_T_107[3]; // @[package.scala:45:27]
wire _s1_hazard_T_112 = _s1_hazard_T_107[4]; // @[package.scala:45:27]
wire _s1_hazard_T_113 = _s1_hazard_T_107[5]; // @[package.scala:45:27]
wire _s1_hazard_T_114 = _s1_hazard_T_107[6]; // @[package.scala:45:27]
wire _s1_hazard_T_115 = _s1_hazard_T_107[7]; // @[package.scala:45:27]
wire [1:0] s1_hazard_lo_lo_7 = {_s1_hazard_T_109, _s1_hazard_T_108}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_lo_hi_7 = {_s1_hazard_T_111, _s1_hazard_T_110}; // @[DCache.scala:1182:52]
wire [3:0] s1_hazard_lo_7 = {s1_hazard_lo_hi_7, s1_hazard_lo_lo_7}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_hi_lo_7 = {_s1_hazard_T_113, _s1_hazard_T_112}; // @[DCache.scala:1182:52]
wire [1:0] s1_hazard_hi_hi_7 = {_s1_hazard_T_115, _s1_hazard_T_114}; // @[DCache.scala:1182:52]
wire [3:0] s1_hazard_hi_7 = {s1_hazard_hi_hi_7, s1_hazard_hi_lo_7}; // @[DCache.scala:1182:52]
wire [7:0] _s1_hazard_T_116 = {s1_hazard_hi_7, s1_hazard_lo_7}; // @[DCache.scala:1182:52]
wire [7:0] _s1_hazard_T_117 = _s1_hazard_T_90 & _s1_hazard_T_116; // @[DCache.scala:562:38, :1182:52]
wire _s1_hazard_T_118 = |_s1_hazard_T_117; // @[DCache.scala:562:{38,66}]
wire [7:0] _s1_hazard_T_119 = pstore2_storegen_mask & s1_mask_xwr; // @[DCache.scala:531:19, :562:77]
wire _s1_hazard_T_120 = |_s1_hazard_T_119; // @[DCache.scala:562:{77,92}]
wire _s1_hazard_T_121 = s1_write ? _s1_hazard_T_118 : _s1_hazard_T_120; // @[DCache.scala:562:{8,66,92}]
wire _s1_hazard_T_122 = _s1_hazard_T_64 & _s1_hazard_T_121; // @[DCache.scala:561:{31,65}, :562:8]
wire _s1_hazard_T_123 = pstore2_valid & _s1_hazard_T_122; // @[DCache.scala:501:30, :561:65, :565:21]
wire s1_hazard = _s1_hazard_T_61 | _s1_hazard_T_123; // @[DCache.scala:564:{27,69}, :565:21]
wire s1_raw_hazard = s1_read & s1_hazard; // @[DCache.scala:564:69, :566:31]
assign s1_nack = s1_valid & s1_raw_hazard | io_cpu_s2_nack_0 | _metaArb_io_in_2_valid_T; // @[DCache.scala:101:7, :182:25, :185:28, :288:75, :446:{24,82,92}, :462:63, :566:31, :571:{18,36,46}]
reg io_cpu_s2_nack_cause_raw_REG; // @[DCache.scala:574:38]
assign _io_cpu_s2_nack_cause_raw_T_3 = io_cpu_s2_nack_cause_raw_REG; // @[DCache.scala:574:{38,54}]
assign io_cpu_s2_nack_cause_raw_0 = _io_cpu_s2_nack_cause_raw_T_3; // @[DCache.scala:101:7, :574:54]
wire _a_source_T = ~uncachedInFlight_0; // @[DCache.scala:236:33, :577:34]
wire _a_source_T_1 = _a_source_T; // @[DCache.scala:577:{34,59}]
wire _a_source_T_2 = _a_source_T_1; // @[OneHot.scala:48:45]
wire [33:0] acquire_address = {_acquire_address_T, 6'h0}; // @[DCache.scala:578:{38,49}]
wire [22:0] a_mask = {15'h0, pstore1_mask}; // @[DCache.scala:496:31, :582:29]
wire [33:0] _GEN_92 = {s2_req_addr[33:14], _s2_vaddr_T_2 ^ 14'h3000}; // @[DCache.scala:339:19, :351:103, :467:68]
wire [33:0] _get_legal_T_4; // @[Parameters.scala:137:31]
assign _get_legal_T_4 = _GEN_92; // @[Parameters.scala:137:31]
wire [33:0] _put_legal_T_4; // @[Parameters.scala:137:31]
assign _put_legal_T_4 = _GEN_92; // @[Parameters.scala:137:31]
wire [33:0] _putpartial_legal_T_4; // @[Parameters.scala:137:31]
assign _putpartial_legal_T_4 = _GEN_92; // @[Parameters.scala:137:31]
wire [34:0] _get_legal_T_5 = {1'h0, _get_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _get_legal_T_6 = _get_legal_T_5 & 35'hCA113000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _get_legal_T_7 = _get_legal_T_6; // @[Parameters.scala:137:46]
wire _get_legal_T_8 = _get_legal_T_7 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _get_legal_T_9 = _get_legal_T_8; // @[Parameters.scala:684:54]
wire _get_legal_T_56 = _get_legal_T_9; // @[Parameters.scala:684:54, :686:26]
wire [34:0] _get_legal_T_15 = {1'h0, _get_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _get_legal_T_16 = _get_legal_T_15 & 35'hCA112000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _get_legal_T_17 = _get_legal_T_16; // @[Parameters.scala:137:46]
wire _get_legal_T_18 = _get_legal_T_17 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] _GEN_93 = {s2_req_addr[33:17], s2_req_addr[16:0] ^ 17'h10000}; // @[DCache.scala:339:19]
wire [33:0] _get_legal_T_19; // @[Parameters.scala:137:31]
assign _get_legal_T_19 = _GEN_93; // @[Parameters.scala:137:31]
wire [33:0] _put_legal_T_45; // @[Parameters.scala:137:31]
assign _put_legal_T_45 = _GEN_93; // @[Parameters.scala:137:31]
wire [33:0] _putpartial_legal_T_45; // @[Parameters.scala:137:31]
assign _putpartial_legal_T_45 = _GEN_93; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_23; // @[Parameters.scala:137:31]
assign _atomics_legal_T_23 = _GEN_93; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_59; // @[Parameters.scala:137:31]
assign _atomics_legal_T_59 = _GEN_93; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_95; // @[Parameters.scala:137:31]
assign _atomics_legal_T_95 = _GEN_93; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_131; // @[Parameters.scala:137:31]
assign _atomics_legal_T_131 = _GEN_93; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_167; // @[Parameters.scala:137:31]
assign _atomics_legal_T_167 = _GEN_93; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_203; // @[Parameters.scala:137:31]
assign _atomics_legal_T_203 = _GEN_93; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_239; // @[Parameters.scala:137:31]
assign _atomics_legal_T_239 = _GEN_93; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_275; // @[Parameters.scala:137:31]
assign _atomics_legal_T_275 = _GEN_93; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_311; // @[Parameters.scala:137:31]
assign _atomics_legal_T_311 = _GEN_93; // @[Parameters.scala:137:31]
wire [34:0] _get_legal_T_20 = {1'h0, _get_legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _get_legal_T_21 = _get_legal_T_20 & 35'hCA110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _get_legal_T_22 = _get_legal_T_21; // @[Parameters.scala:137:46]
wire _get_legal_T_23 = _get_legal_T_22 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] _GEN_94 = {s2_req_addr[33:21], s2_req_addr[20:0] ^ 21'h100000}; // @[DCache.scala:339:19]
wire [33:0] _get_legal_T_24; // @[Parameters.scala:137:31]
assign _get_legal_T_24 = _GEN_94; // @[Parameters.scala:137:31]
wire [33:0] _put_legal_T_19; // @[Parameters.scala:137:31]
assign _put_legal_T_19 = _GEN_94; // @[Parameters.scala:137:31]
wire [33:0] _putpartial_legal_T_19; // @[Parameters.scala:137:31]
assign _putpartial_legal_T_19 = _GEN_94; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_9; // @[Parameters.scala:137:31]
assign _atomics_legal_T_9 = _GEN_94; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_45; // @[Parameters.scala:137:31]
assign _atomics_legal_T_45 = _GEN_94; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_81; // @[Parameters.scala:137:31]
assign _atomics_legal_T_81 = _GEN_94; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_117; // @[Parameters.scala:137:31]
assign _atomics_legal_T_117 = _GEN_94; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_153; // @[Parameters.scala:137:31]
assign _atomics_legal_T_153 = _GEN_94; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_189; // @[Parameters.scala:137:31]
assign _atomics_legal_T_189 = _GEN_94; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_225; // @[Parameters.scala:137:31]
assign _atomics_legal_T_225 = _GEN_94; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_261; // @[Parameters.scala:137:31]
assign _atomics_legal_T_261 = _GEN_94; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_297; // @[Parameters.scala:137:31]
assign _atomics_legal_T_297 = _GEN_94; // @[Parameters.scala:137:31]
wire [34:0] _get_legal_T_25 = {1'h0, _get_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _get_legal_T_26 = _get_legal_T_25 & 35'hCA103000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _get_legal_T_27 = _get_legal_T_26; // @[Parameters.scala:137:46]
wire _get_legal_T_28 = _get_legal_T_27 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] _GEN_95 = {s2_req_addr[33:26], s2_req_addr[25:0] ^ 26'h2000000}; // @[DCache.scala:339:19]
wire [33:0] _get_legal_T_29; // @[Parameters.scala:137:31]
assign _get_legal_T_29 = _GEN_95; // @[Parameters.scala:137:31]
wire [33:0] _put_legal_T_24; // @[Parameters.scala:137:31]
assign _put_legal_T_24 = _GEN_95; // @[Parameters.scala:137:31]
wire [33:0] _putpartial_legal_T_24; // @[Parameters.scala:137:31]
assign _putpartial_legal_T_24 = _GEN_95; // @[Parameters.scala:137:31]
wire [34:0] _get_legal_T_30 = {1'h0, _get_legal_T_29}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _get_legal_T_31 = _get_legal_T_30 & 35'hCA110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _get_legal_T_32 = _get_legal_T_31; // @[Parameters.scala:137:46]
wire _get_legal_T_33 = _get_legal_T_32 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] _GEN_96 = {s2_req_addr[33:28], s2_req_addr[27:0] ^ 28'h8000000}; // @[DCache.scala:339:19]
wire [33:0] _get_legal_T_34; // @[Parameters.scala:137:31]
assign _get_legal_T_34 = _GEN_96; // @[Parameters.scala:137:31]
wire [33:0] _put_legal_T_29; // @[Parameters.scala:137:31]
assign _put_legal_T_29 = _GEN_96; // @[Parameters.scala:137:31]
wire [33:0] _putpartial_legal_T_29; // @[Parameters.scala:137:31]
assign _putpartial_legal_T_29 = _GEN_96; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_14; // @[Parameters.scala:137:31]
assign _atomics_legal_T_14 = _GEN_96; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_50; // @[Parameters.scala:137:31]
assign _atomics_legal_T_50 = _GEN_96; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_86; // @[Parameters.scala:137:31]
assign _atomics_legal_T_86 = _GEN_96; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_122; // @[Parameters.scala:137:31]
assign _atomics_legal_T_122 = _GEN_96; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_158; // @[Parameters.scala:137:31]
assign _atomics_legal_T_158 = _GEN_96; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_194; // @[Parameters.scala:137:31]
assign _atomics_legal_T_194 = _GEN_96; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_230; // @[Parameters.scala:137:31]
assign _atomics_legal_T_230 = _GEN_96; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_266; // @[Parameters.scala:137:31]
assign _atomics_legal_T_266 = _GEN_96; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_302; // @[Parameters.scala:137:31]
assign _atomics_legal_T_302 = _GEN_96; // @[Parameters.scala:137:31]
wire [34:0] _get_legal_T_35 = {1'h0, _get_legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _get_legal_T_36 = _get_legal_T_35 & 35'hC8000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _get_legal_T_37 = _get_legal_T_36; // @[Parameters.scala:137:46]
wire _get_legal_T_38 = _get_legal_T_37 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [33:0] _GEN_97 = {s2_req_addr[33:31], s2_req_addr[30:0] ^ 31'h40000000}; // @[DCache.scala:339:19]
wire [33:0] _get_legal_T_39; // @[Parameters.scala:137:31]
assign _get_legal_T_39 = _GEN_97; // @[Parameters.scala:137:31]
wire [33:0] _put_legal_T_55; // @[Parameters.scala:137:31]
assign _put_legal_T_55 = _GEN_97; // @[Parameters.scala:137:31]
wire [33:0] _putpartial_legal_T_55; // @[Parameters.scala:137:31]
assign _putpartial_legal_T_55 = _GEN_97; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_28; // @[Parameters.scala:137:31]
assign _atomics_legal_T_28 = _GEN_97; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_64; // @[Parameters.scala:137:31]
assign _atomics_legal_T_64 = _GEN_97; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_100; // @[Parameters.scala:137:31]
assign _atomics_legal_T_100 = _GEN_97; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_136; // @[Parameters.scala:137:31]
assign _atomics_legal_T_136 = _GEN_97; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_172; // @[Parameters.scala:137:31]
assign _atomics_legal_T_172 = _GEN_97; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_208; // @[Parameters.scala:137:31]
assign _atomics_legal_T_208 = _GEN_97; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_244; // @[Parameters.scala:137:31]
assign _atomics_legal_T_244 = _GEN_97; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_280; // @[Parameters.scala:137:31]
assign _atomics_legal_T_280 = _GEN_97; // @[Parameters.scala:137:31]
wire [33:0] _atomics_legal_T_316; // @[Parameters.scala:137:31]
assign _atomics_legal_T_316 = _GEN_97; // @[Parameters.scala:137:31]
wire [34:0] _get_legal_T_40 = {1'h0, _get_legal_T_39}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _get_legal_T_41 = _get_legal_T_40 & 35'hC0000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _get_legal_T_42 = _get_legal_T_41; // @[Parameters.scala:137:46]
wire _get_legal_T_43 = _get_legal_T_42 == 35'h0; // @[Parameters.scala:137:{46,59}]
assign io_cpu_s2_paddr_0 = s2_req_addr[31:0]; // @[DCache.scala:101:7, :339:19]
wire [31:0] get_address = s2_req_addr[31:0]; // @[Edges.scala:460:17]
wire [31:0] put_address = s2_req_addr[31:0]; // @[Edges.scala:480:17]
wire [31:0] putpartial_address = s2_req_addr[31:0]; // @[Edges.scala:500:17]
wire [31:0] atomics_a_address = s2_req_addr[31:0]; // @[Edges.scala:534:17]
wire [31:0] atomics_a_1_address = s2_req_addr[31:0]; // @[Edges.scala:534:17]
wire [31:0] atomics_a_2_address = s2_req_addr[31:0]; // @[Edges.scala:534:17]
wire [31:0] atomics_a_3_address = s2_req_addr[31:0]; // @[Edges.scala:534:17]
wire [31:0] atomics_a_4_address = s2_req_addr[31:0]; // @[Edges.scala:517:17]
wire [31:0] atomics_a_5_address = s2_req_addr[31:0]; // @[Edges.scala:517:17]
wire [31:0] atomics_a_6_address = s2_req_addr[31:0]; // @[Edges.scala:517:17]
wire [31:0] atomics_a_7_address = s2_req_addr[31:0]; // @[Edges.scala:517:17]
wire [31:0] atomics_a_8_address = s2_req_addr[31:0]; // @[Edges.scala:517:17]
wire [33:0] _GEN_98 = {s2_req_addr[33:32], s2_req_addr[31:0] ^ 32'h80000000}; // @[DCache.scala:339:19]
wire [33:0] _get_legal_T_44; // @[Parameters.scala:137:31]
assign _get_legal_T_44 = _GEN_98; // @[Parameters.scala:137:31]
wire [33:0] _put_legal_T_34; // @[Parameters.scala:137:31]
assign _put_legal_T_34 = _GEN_98; // @[Parameters.scala:137:31]
wire [33:0] _putpartial_legal_T_34; // @[Parameters.scala:137:31]
assign _putpartial_legal_T_34 = _GEN_98; // @[Parameters.scala:137:31]
wire [34:0] _get_legal_T_45 = {1'h0, _get_legal_T_44}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _get_legal_T_46 = _get_legal_T_45 & 35'hCA110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _get_legal_T_47 = _get_legal_T_46; // @[Parameters.scala:137:46]
wire _get_legal_T_48 = _get_legal_T_47 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _get_legal_T_49 = _get_legal_T_18 | _get_legal_T_23; // @[Parameters.scala:685:42]
wire _get_legal_T_50 = _get_legal_T_49 | _get_legal_T_28; // @[Parameters.scala:685:42]
wire _get_legal_T_51 = _get_legal_T_50 | _get_legal_T_33; // @[Parameters.scala:685:42]
wire _get_legal_T_52 = _get_legal_T_51 | _get_legal_T_38; // @[Parameters.scala:685:42]
wire _get_legal_T_53 = _get_legal_T_52 | _get_legal_T_43; // @[Parameters.scala:685:42]
wire _get_legal_T_54 = _get_legal_T_53 | _get_legal_T_48; // @[Parameters.scala:685:42]
wire _get_legal_T_55 = _get_legal_T_54; // @[Parameters.scala:684:54, :685:42]
wire get_legal = _get_legal_T_56 | _get_legal_T_55; // @[Parameters.scala:684:54, :686:26]
wire [7:0] _get_a_mask_T; // @[Misc.scala:222:10]
wire [3:0] get_size; // @[Edges.scala:460:17]
wire [7:0] get_mask; // @[Edges.scala:460:17]
wire [3:0] _GEN_99 = {2'h0, s2_req_size}; // @[Edges.scala:463:15]
assign get_size = _GEN_99; // @[Edges.scala:460:17, :463:15]
wire [3:0] put_size; // @[Edges.scala:480:17]
assign put_size = _GEN_99; // @[Edges.scala:463:15, :480:17]
wire [3:0] putpartial_size; // @[Edges.scala:500:17]
assign putpartial_size = _GEN_99; // @[Edges.scala:463:15, :500:17]
wire [3:0] atomics_a_size; // @[Edges.scala:534:17]
assign atomics_a_size = _GEN_99; // @[Edges.scala:463:15, :534:17]
wire [3:0] atomics_a_1_size; // @[Edges.scala:534:17]
assign atomics_a_1_size = _GEN_99; // @[Edges.scala:463:15, :534:17]
wire [3:0] atomics_a_2_size; // @[Edges.scala:534:17]
assign atomics_a_2_size = _GEN_99; // @[Edges.scala:463:15, :534:17]
wire [3:0] atomics_a_3_size; // @[Edges.scala:534:17]
assign atomics_a_3_size = _GEN_99; // @[Edges.scala:463:15, :534:17]
wire [3:0] atomics_a_4_size; // @[Edges.scala:517:17]
assign atomics_a_4_size = _GEN_99; // @[Edges.scala:463:15, :517:17]
wire [3:0] atomics_a_5_size; // @[Edges.scala:517:17]
assign atomics_a_5_size = _GEN_99; // @[Edges.scala:463:15, :517:17]
wire [3:0] atomics_a_6_size; // @[Edges.scala:517:17]
assign atomics_a_6_size = _GEN_99; // @[Edges.scala:463:15, :517:17]
wire [3:0] atomics_a_7_size; // @[Edges.scala:517:17]
assign atomics_a_7_size = _GEN_99; // @[Edges.scala:463:15, :517:17]
wire [3:0] atomics_a_8_size; // @[Edges.scala:517:17]
assign atomics_a_8_size = _GEN_99; // @[Edges.scala:463:15, :517:17]
wire [2:0] _GEN_100 = {1'h0, s2_req_size}; // @[Misc.scala:202:34]
wire [2:0] _get_a_mask_sizeOH_T; // @[Misc.scala:202:34]
assign _get_a_mask_sizeOH_T = _GEN_100; // @[Misc.scala:202:34]
wire [2:0] _put_a_mask_sizeOH_T; // @[Misc.scala:202:34]
assign _put_a_mask_sizeOH_T = _GEN_100; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T = _GEN_100; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_3; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_3 = _GEN_100; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_6; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_6 = _GEN_100; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_9; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_9 = _GEN_100; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_12; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_12 = _GEN_100; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_15; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_15 = _GEN_100; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_18; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_18 = _GEN_100; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_21; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_21 = _GEN_100; // @[Misc.scala:202:34]
wire [2:0] _atomics_a_mask_sizeOH_T_24; // @[Misc.scala:202:34]
assign _atomics_a_mask_sizeOH_T_24 = _GEN_100; // @[Misc.scala:202:34]
wire [1:0] get_a_mask_sizeOH_shiftAmount = _get_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _get_a_mask_sizeOH_T_1 = 4'h1 << get_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _get_a_mask_sizeOH_T_2 = _get_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] get_a_mask_sizeOH = {_get_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire get_a_mask_sub_sub_sub_0_1 = &s2_req_size; // @[Misc.scala:206:21]
wire get_a_mask_sub_sub_size = get_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire get_a_mask_sub_sub_bit = s2_req_addr[2]; // @[Misc.scala:210:26]
wire put_a_mask_sub_sub_bit = s2_req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit = s2_req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_1 = s2_req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_2 = s2_req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_3 = s2_req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_4 = s2_req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_5 = s2_req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_6 = s2_req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_7 = s2_req_addr[2]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_sub_bit_8 = s2_req_addr[2]; // @[Misc.scala:210:26]
wire _io_cpu_resp_bits_data_shifted_T = s2_req_addr[2]; // @[Misc.scala:210:26]
wire _io_cpu_resp_bits_data_word_bypass_shifted_T = s2_req_addr[2]; // @[Misc.scala:210:26]
wire get_a_mask_sub_sub_1_2 = get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire get_a_mask_sub_sub_nbit = ~get_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire get_a_mask_sub_sub_0_2 = get_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_sub_sub_acc_T = get_a_mask_sub_sub_size & get_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_sub_0_1 = get_a_mask_sub_sub_sub_0_1 | _get_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _get_a_mask_sub_sub_acc_T_1 = get_a_mask_sub_sub_size & get_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_sub_1_1 = get_a_mask_sub_sub_sub_0_1 | _get_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire get_a_mask_sub_size = get_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire get_a_mask_sub_bit = s2_req_addr[1]; // @[Misc.scala:210:26]
wire put_a_mask_sub_bit = s2_req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit = s2_req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_1 = s2_req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_2 = s2_req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_3 = s2_req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_4 = s2_req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_5 = s2_req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_6 = s2_req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_7 = s2_req_addr[1]; // @[Misc.scala:210:26]
wire atomics_a_mask_sub_bit_8 = s2_req_addr[1]; // @[Misc.scala:210:26]
wire _io_cpu_resp_bits_data_shifted_T_3 = s2_req_addr[1]; // @[Misc.scala:210:26]
wire get_a_mask_sub_nbit = ~get_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire get_a_mask_sub_0_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_sub_acc_T = get_a_mask_sub_size & get_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_0_1 = get_a_mask_sub_sub_0_1 | _get_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire get_a_mask_sub_1_2 = get_a_mask_sub_sub_0_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_sub_acc_T_1 = get_a_mask_sub_size & get_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_1_1 = get_a_mask_sub_sub_0_1 | _get_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire get_a_mask_sub_2_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_sub_acc_T_2 = get_a_mask_sub_size & get_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_2_1 = get_a_mask_sub_sub_1_1 | _get_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire get_a_mask_sub_3_2 = get_a_mask_sub_sub_1_2 & get_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_sub_acc_T_3 = get_a_mask_sub_size & get_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_sub_3_1 = get_a_mask_sub_sub_1_1 | _get_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire get_a_mask_size = get_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire get_a_mask_bit = s2_req_addr[0]; // @[Misc.scala:210:26]
wire put_a_mask_bit = s2_req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit = s2_req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_1 = s2_req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_2 = s2_req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_3 = s2_req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_4 = s2_req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_5 = s2_req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_6 = s2_req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_7 = s2_req_addr[0]; // @[Misc.scala:210:26]
wire atomics_a_mask_bit_8 = s2_req_addr[0]; // @[Misc.scala:210:26]
wire _io_cpu_resp_bits_data_shifted_T_6 = s2_req_addr[0]; // @[Misc.scala:210:26]
wire get_a_mask_nbit = ~get_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire get_a_mask_eq = get_a_mask_sub_0_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_acc_T = get_a_mask_size & get_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc = get_a_mask_sub_0_1 | _get_a_mask_acc_T; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_1 = get_a_mask_sub_0_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_acc_T_1 = get_a_mask_size & get_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_1 = get_a_mask_sub_0_1 | _get_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_2 = get_a_mask_sub_1_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_acc_T_2 = get_a_mask_size & get_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_2 = get_a_mask_sub_1_1 | _get_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_3 = get_a_mask_sub_1_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_acc_T_3 = get_a_mask_size & get_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_3 = get_a_mask_sub_1_1 | _get_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_4 = get_a_mask_sub_2_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_acc_T_4 = get_a_mask_size & get_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_4 = get_a_mask_sub_2_1 | _get_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_5 = get_a_mask_sub_2_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_acc_T_5 = get_a_mask_size & get_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_5 = get_a_mask_sub_2_1 | _get_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_6 = get_a_mask_sub_3_2 & get_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _get_a_mask_acc_T_6 = get_a_mask_size & get_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_6 = get_a_mask_sub_3_1 | _get_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire get_a_mask_eq_7 = get_a_mask_sub_3_2 & get_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _get_a_mask_acc_T_7 = get_a_mask_size & get_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire get_a_mask_acc_7 = get_a_mask_sub_3_1 | _get_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] get_a_mask_lo_lo = {get_a_mask_acc_1, get_a_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] get_a_mask_lo_hi = {get_a_mask_acc_3, get_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] get_a_mask_lo = {get_a_mask_lo_hi, get_a_mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] get_a_mask_hi_lo = {get_a_mask_acc_5, get_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] get_a_mask_hi_hi = {get_a_mask_acc_7, get_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] get_a_mask_hi = {get_a_mask_hi_hi, get_a_mask_hi_lo}; // @[Misc.scala:222:10]
assign _get_a_mask_T = {get_a_mask_hi, get_a_mask_lo}; // @[Misc.scala:222:10]
assign get_mask = _get_a_mask_T; // @[Misc.scala:222:10]
wire [34:0] _put_legal_T_5 = {1'h0, _put_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _put_legal_T_6 = _put_legal_T_5 & 35'hCA113000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _put_legal_T_7 = _put_legal_T_6; // @[Parameters.scala:137:46]
wire _put_legal_T_8 = _put_legal_T_7 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _put_legal_T_9 = _put_legal_T_8; // @[Parameters.scala:684:54]
wire _put_legal_T_61 = _put_legal_T_9; // @[Parameters.scala:684:54, :686:26]
wire [34:0] _put_legal_T_15 = {1'h0, _put_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _put_legal_T_16 = _put_legal_T_15 & 35'hCA112000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _put_legal_T_17 = _put_legal_T_16; // @[Parameters.scala:137:46]
wire _put_legal_T_18 = _put_legal_T_17 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _put_legal_T_20 = {1'h0, _put_legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _put_legal_T_21 = _put_legal_T_20 & 35'hCA103000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _put_legal_T_22 = _put_legal_T_21; // @[Parameters.scala:137:46]
wire _put_legal_T_23 = _put_legal_T_22 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _put_legal_T_25 = {1'h0, _put_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _put_legal_T_26 = _put_legal_T_25 & 35'hCA110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _put_legal_T_27 = _put_legal_T_26; // @[Parameters.scala:137:46]
wire _put_legal_T_28 = _put_legal_T_27 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _put_legal_T_30 = {1'h0, _put_legal_T_29}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _put_legal_T_31 = _put_legal_T_30 & 35'hC8000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _put_legal_T_32 = _put_legal_T_31; // @[Parameters.scala:137:46]
wire _put_legal_T_33 = _put_legal_T_32 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _put_legal_T_35 = {1'h0, _put_legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _put_legal_T_36 = _put_legal_T_35 & 35'hCA110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _put_legal_T_37 = _put_legal_T_36; // @[Parameters.scala:137:46]
wire _put_legal_T_38 = _put_legal_T_37 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _put_legal_T_39 = _put_legal_T_18 | _put_legal_T_23; // @[Parameters.scala:685:42]
wire _put_legal_T_40 = _put_legal_T_39 | _put_legal_T_28; // @[Parameters.scala:685:42]
wire _put_legal_T_41 = _put_legal_T_40 | _put_legal_T_33; // @[Parameters.scala:685:42]
wire _put_legal_T_42 = _put_legal_T_41 | _put_legal_T_38; // @[Parameters.scala:685:42]
wire _put_legal_T_43 = _put_legal_T_42; // @[Parameters.scala:684:54, :685:42]
wire [34:0] _put_legal_T_46 = {1'h0, _put_legal_T_45}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _put_legal_T_47 = _put_legal_T_46 & 35'hCA110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _put_legal_T_48 = _put_legal_T_47; // @[Parameters.scala:137:46]
wire _put_legal_T_49 = _put_legal_T_48 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _put_legal_T_56 = {1'h0, _put_legal_T_55}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _put_legal_T_57 = _put_legal_T_56 & 35'hC0000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _put_legal_T_58 = _put_legal_T_57; // @[Parameters.scala:137:46]
wire _put_legal_T_59 = _put_legal_T_58 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _put_legal_T_60 = _put_legal_T_59; // @[Parameters.scala:684:54]
wire _put_legal_T_62 = _put_legal_T_61 | _put_legal_T_43; // @[Parameters.scala:684:54, :686:26]
wire _put_legal_T_63 = _put_legal_T_62; // @[Parameters.scala:686:26]
wire put_legal = _put_legal_T_63 | _put_legal_T_60; // @[Parameters.scala:684:54, :686:26]
wire [7:0] _put_a_mask_T; // @[Misc.scala:222:10]
wire [7:0] put_mask; // @[Edges.scala:480:17]
wire [1:0] put_a_mask_sizeOH_shiftAmount = _put_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _put_a_mask_sizeOH_T_1 = 4'h1 << put_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _put_a_mask_sizeOH_T_2 = _put_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] put_a_mask_sizeOH = {_put_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire put_a_mask_sub_sub_sub_0_1 = &s2_req_size; // @[Misc.scala:206:21]
wire put_a_mask_sub_sub_size = put_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire put_a_mask_sub_sub_1_2 = put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire put_a_mask_sub_sub_nbit = ~put_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire put_a_mask_sub_sub_0_2 = put_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_sub_sub_acc_T = put_a_mask_sub_sub_size & put_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_sub_0_1 = put_a_mask_sub_sub_sub_0_1 | _put_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _put_a_mask_sub_sub_acc_T_1 = put_a_mask_sub_sub_size & put_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_sub_1_1 = put_a_mask_sub_sub_sub_0_1 | _put_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire put_a_mask_sub_size = put_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire put_a_mask_sub_nbit = ~put_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire put_a_mask_sub_0_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_sub_acc_T = put_a_mask_sub_size & put_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_0_1 = put_a_mask_sub_sub_0_1 | _put_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire put_a_mask_sub_1_2 = put_a_mask_sub_sub_0_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_sub_acc_T_1 = put_a_mask_sub_size & put_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_1_1 = put_a_mask_sub_sub_0_1 | _put_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire put_a_mask_sub_2_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_sub_acc_T_2 = put_a_mask_sub_size & put_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_2_1 = put_a_mask_sub_sub_1_1 | _put_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire put_a_mask_sub_3_2 = put_a_mask_sub_sub_1_2 & put_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_sub_acc_T_3 = put_a_mask_sub_size & put_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_sub_3_1 = put_a_mask_sub_sub_1_1 | _put_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire put_a_mask_size = put_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire put_a_mask_nbit = ~put_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire put_a_mask_eq = put_a_mask_sub_0_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_acc_T = put_a_mask_size & put_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc = put_a_mask_sub_0_1 | _put_a_mask_acc_T; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_1 = put_a_mask_sub_0_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_acc_T_1 = put_a_mask_size & put_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_1 = put_a_mask_sub_0_1 | _put_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_2 = put_a_mask_sub_1_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_acc_T_2 = put_a_mask_size & put_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_2 = put_a_mask_sub_1_1 | _put_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_3 = put_a_mask_sub_1_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_acc_T_3 = put_a_mask_size & put_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_3 = put_a_mask_sub_1_1 | _put_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_4 = put_a_mask_sub_2_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_acc_T_4 = put_a_mask_size & put_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_4 = put_a_mask_sub_2_1 | _put_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_5 = put_a_mask_sub_2_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_acc_T_5 = put_a_mask_size & put_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_5 = put_a_mask_sub_2_1 | _put_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_6 = put_a_mask_sub_3_2 & put_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _put_a_mask_acc_T_6 = put_a_mask_size & put_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_6 = put_a_mask_sub_3_1 | _put_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire put_a_mask_eq_7 = put_a_mask_sub_3_2 & put_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _put_a_mask_acc_T_7 = put_a_mask_size & put_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire put_a_mask_acc_7 = put_a_mask_sub_3_1 | _put_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] put_a_mask_lo_lo = {put_a_mask_acc_1, put_a_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] put_a_mask_lo_hi = {put_a_mask_acc_3, put_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] put_a_mask_lo = {put_a_mask_lo_hi, put_a_mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] put_a_mask_hi_lo = {put_a_mask_acc_5, put_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] put_a_mask_hi_hi = {put_a_mask_acc_7, put_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] put_a_mask_hi = {put_a_mask_hi_hi, put_a_mask_hi_lo}; // @[Misc.scala:222:10]
assign _put_a_mask_T = {put_a_mask_hi, put_a_mask_lo}; // @[Misc.scala:222:10]
assign put_mask = _put_a_mask_T; // @[Misc.scala:222:10]
wire [34:0] _putpartial_legal_T_5 = {1'h0, _putpartial_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _putpartial_legal_T_6 = _putpartial_legal_T_5 & 35'hCA113000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _putpartial_legal_T_7 = _putpartial_legal_T_6; // @[Parameters.scala:137:46]
wire _putpartial_legal_T_8 = _putpartial_legal_T_7 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _putpartial_legal_T_9 = _putpartial_legal_T_8; // @[Parameters.scala:684:54]
wire _putpartial_legal_T_61 = _putpartial_legal_T_9; // @[Parameters.scala:684:54, :686:26]
wire [34:0] _putpartial_legal_T_15 = {1'h0, _putpartial_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _putpartial_legal_T_16 = _putpartial_legal_T_15 & 35'hCA112000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _putpartial_legal_T_17 = _putpartial_legal_T_16; // @[Parameters.scala:137:46]
wire _putpartial_legal_T_18 = _putpartial_legal_T_17 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _putpartial_legal_T_20 = {1'h0, _putpartial_legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _putpartial_legal_T_21 = _putpartial_legal_T_20 & 35'hCA103000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _putpartial_legal_T_22 = _putpartial_legal_T_21; // @[Parameters.scala:137:46]
wire _putpartial_legal_T_23 = _putpartial_legal_T_22 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _putpartial_legal_T_25 = {1'h0, _putpartial_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _putpartial_legal_T_26 = _putpartial_legal_T_25 & 35'hCA110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _putpartial_legal_T_27 = _putpartial_legal_T_26; // @[Parameters.scala:137:46]
wire _putpartial_legal_T_28 = _putpartial_legal_T_27 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _putpartial_legal_T_30 = {1'h0, _putpartial_legal_T_29}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _putpartial_legal_T_31 = _putpartial_legal_T_30 & 35'hC8000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _putpartial_legal_T_32 = _putpartial_legal_T_31; // @[Parameters.scala:137:46]
wire _putpartial_legal_T_33 = _putpartial_legal_T_32 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _putpartial_legal_T_35 = {1'h0, _putpartial_legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _putpartial_legal_T_36 = _putpartial_legal_T_35 & 35'hCA110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _putpartial_legal_T_37 = _putpartial_legal_T_36; // @[Parameters.scala:137:46]
wire _putpartial_legal_T_38 = _putpartial_legal_T_37 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _putpartial_legal_T_39 = _putpartial_legal_T_18 | _putpartial_legal_T_23; // @[Parameters.scala:685:42]
wire _putpartial_legal_T_40 = _putpartial_legal_T_39 | _putpartial_legal_T_28; // @[Parameters.scala:685:42]
wire _putpartial_legal_T_41 = _putpartial_legal_T_40 | _putpartial_legal_T_33; // @[Parameters.scala:685:42]
wire _putpartial_legal_T_42 = _putpartial_legal_T_41 | _putpartial_legal_T_38; // @[Parameters.scala:685:42]
wire _putpartial_legal_T_43 = _putpartial_legal_T_42; // @[Parameters.scala:684:54, :685:42]
wire [34:0] _putpartial_legal_T_46 = {1'h0, _putpartial_legal_T_45}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _putpartial_legal_T_47 = _putpartial_legal_T_46 & 35'hCA110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _putpartial_legal_T_48 = _putpartial_legal_T_47; // @[Parameters.scala:137:46]
wire _putpartial_legal_T_49 = _putpartial_legal_T_48 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _putpartial_legal_T_56 = {1'h0, _putpartial_legal_T_55}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _putpartial_legal_T_57 = _putpartial_legal_T_56 & 35'hC0000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _putpartial_legal_T_58 = _putpartial_legal_T_57; // @[Parameters.scala:137:46]
wire _putpartial_legal_T_59 = _putpartial_legal_T_58 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _putpartial_legal_T_60 = _putpartial_legal_T_59; // @[Parameters.scala:684:54]
wire _putpartial_legal_T_62 = _putpartial_legal_T_61 | _putpartial_legal_T_43; // @[Parameters.scala:684:54, :686:26]
wire _putpartial_legal_T_63 = _putpartial_legal_T_62; // @[Parameters.scala:686:26]
wire putpartial_legal = _putpartial_legal_T_63 | _putpartial_legal_T_60; // @[Parameters.scala:684:54, :686:26]
wire [7:0] putpartial_mask; // @[Edges.scala:500:17]
assign putpartial_mask = a_mask[7:0]; // @[Edges.scala:500:17, :508:15]
wire [34:0] _atomics_legal_T_5 = {1'h0, _atomics_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_6 = _atomics_legal_T_5 & 35'h48110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_7 = _atomics_legal_T_6; // @[Parameters.scala:137:46]
wire _atomics_legal_T_8 = _atomics_legal_T_7 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _atomics_legal_T_10 = {1'h0, _atomics_legal_T_9}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_11 = _atomics_legal_T_10 & 35'h48101000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_12 = _atomics_legal_T_11; // @[Parameters.scala:137:46]
wire _atomics_legal_T_13 = _atomics_legal_T_12 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _atomics_legal_T_15 = {1'h0, _atomics_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_16 = _atomics_legal_T_15 & 35'h48000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_17 = _atomics_legal_T_16; // @[Parameters.scala:137:46]
wire _atomics_legal_T_18 = _atomics_legal_T_17 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_19 = _atomics_legal_T_8 | _atomics_legal_T_13; // @[Parameters.scala:685:42]
wire _atomics_legal_T_20 = _atomics_legal_T_19 | _atomics_legal_T_18; // @[Parameters.scala:685:42]
wire _atomics_legal_T_21 = _atomics_legal_T_20; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_35 = _atomics_legal_T_21; // @[Parameters.scala:684:54, :686:26]
wire [34:0] _atomics_legal_T_24 = {1'h0, _atomics_legal_T_23}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_25 = _atomics_legal_T_24 & 35'h48110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_26 = _atomics_legal_T_25; // @[Parameters.scala:137:46]
wire _atomics_legal_T_27 = _atomics_legal_T_26 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _atomics_legal_T_29 = {1'h0, _atomics_legal_T_28}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_30 = _atomics_legal_T_29 & 35'h40000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_31 = _atomics_legal_T_30; // @[Parameters.scala:137:46]
wire _atomics_legal_T_32 = _atomics_legal_T_31 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_33 = _atomics_legal_T_27 | _atomics_legal_T_32; // @[Parameters.scala:685:42]
wire atomics_legal = _atomics_legal_T_35; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T; // @[Misc.scala:222:10]
wire [7:0] atomics_a_mask; // @[Edges.scala:534:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount = _atomics_a_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_1 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_2 = _atomics_a_mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH = {_atomics_a_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1 = &s2_req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size = atomics_a_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2 = atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit = ~atomics_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2 = atomics_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1 = atomics_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_1 = atomics_a_mask_sub_sub_size & atomics_a_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1 = atomics_a_mask_sub_sub_sub_0_1 | _atomics_a_mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size = atomics_a_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit = ~atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T = atomics_a_mask_sub_size & atomics_a_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1 = atomics_a_mask_sub_sub_0_1 | _atomics_a_mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2 = atomics_a_mask_sub_sub_0_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_1 = atomics_a_mask_sub_size & atomics_a_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1 = atomics_a_mask_sub_sub_0_1 | _atomics_a_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_2 = atomics_a_mask_sub_size & atomics_a_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1 = atomics_a_mask_sub_sub_1_1 | _atomics_a_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2 = atomics_a_mask_sub_sub_1_2 & atomics_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_3 = atomics_a_mask_sub_size & atomics_a_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1 = atomics_a_mask_sub_sub_1_1 | _atomics_a_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size = atomics_a_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit = ~atomics_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq = atomics_a_mask_sub_0_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T = atomics_a_mask_size & atomics_a_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc = atomics_a_mask_sub_0_1 | _atomics_a_mask_acc_T; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_1 = atomics_a_mask_sub_0_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_1 = atomics_a_mask_size & atomics_a_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_1 = atomics_a_mask_sub_0_1 | _atomics_a_mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_2 = atomics_a_mask_sub_1_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_2 = atomics_a_mask_size & atomics_a_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_2 = atomics_a_mask_sub_1_1 | _atomics_a_mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_3 = atomics_a_mask_sub_1_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_3 = atomics_a_mask_size & atomics_a_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_3 = atomics_a_mask_sub_1_1 | _atomics_a_mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_4 = atomics_a_mask_sub_2_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_4 = atomics_a_mask_size & atomics_a_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_4 = atomics_a_mask_sub_2_1 | _atomics_a_mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_5 = atomics_a_mask_sub_2_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_5 = atomics_a_mask_size & atomics_a_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_5 = atomics_a_mask_sub_2_1 | _atomics_a_mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_6 = atomics_a_mask_sub_3_2 & atomics_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_6 = atomics_a_mask_size & atomics_a_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_6 = atomics_a_mask_sub_3_1 | _atomics_a_mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_7 = atomics_a_mask_sub_3_2 & atomics_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_7 = atomics_a_mask_size & atomics_a_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_7 = atomics_a_mask_sub_3_1 | _atomics_a_mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo = {atomics_a_mask_acc_1, atomics_a_mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi = {atomics_a_mask_acc_3, atomics_a_mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo = {atomics_a_mask_lo_hi, atomics_a_mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo = {atomics_a_mask_acc_5, atomics_a_mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi = {atomics_a_mask_acc_7, atomics_a_mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi = {atomics_a_mask_hi_hi, atomics_a_mask_hi_lo}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T = {atomics_a_mask_hi, atomics_a_mask_lo}; // @[Misc.scala:222:10]
assign atomics_a_mask = _atomics_a_mask_T; // @[Misc.scala:222:10]
wire [34:0] _atomics_legal_T_41 = {1'h0, _atomics_legal_T_40}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_42 = _atomics_legal_T_41 & 35'h48110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_43 = _atomics_legal_T_42; // @[Parameters.scala:137:46]
wire _atomics_legal_T_44 = _atomics_legal_T_43 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _atomics_legal_T_46 = {1'h0, _atomics_legal_T_45}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_47 = _atomics_legal_T_46 & 35'h48101000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_48 = _atomics_legal_T_47; // @[Parameters.scala:137:46]
wire _atomics_legal_T_49 = _atomics_legal_T_48 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _atomics_legal_T_51 = {1'h0, _atomics_legal_T_50}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_52 = _atomics_legal_T_51 & 35'h48000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_53 = _atomics_legal_T_52; // @[Parameters.scala:137:46]
wire _atomics_legal_T_54 = _atomics_legal_T_53 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_55 = _atomics_legal_T_44 | _atomics_legal_T_49; // @[Parameters.scala:685:42]
wire _atomics_legal_T_56 = _atomics_legal_T_55 | _atomics_legal_T_54; // @[Parameters.scala:685:42]
wire _atomics_legal_T_57 = _atomics_legal_T_56; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_71 = _atomics_legal_T_57; // @[Parameters.scala:684:54, :686:26]
wire [34:0] _atomics_legal_T_60 = {1'h0, _atomics_legal_T_59}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_61 = _atomics_legal_T_60 & 35'h48110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_62 = _atomics_legal_T_61; // @[Parameters.scala:137:46]
wire _atomics_legal_T_63 = _atomics_legal_T_62 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _atomics_legal_T_65 = {1'h0, _atomics_legal_T_64}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_66 = _atomics_legal_T_65 & 35'h40000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_67 = _atomics_legal_T_66; // @[Parameters.scala:137:46]
wire _atomics_legal_T_68 = _atomics_legal_T_67 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_69 = _atomics_legal_T_63 | _atomics_legal_T_68; // @[Parameters.scala:685:42]
wire atomics_legal_1 = _atomics_legal_T_71; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_1; // @[Misc.scala:222:10]
wire [7:0] atomics_a_1_mask; // @[Edges.scala:534:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_1 = _atomics_a_mask_sizeOH_T_3[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_4 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_1; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_5 = _atomics_a_mask_sizeOH_T_4[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_1 = {_atomics_a_mask_sizeOH_T_5[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_1 = &s2_req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_1 = atomics_a_mask_sizeOH_1[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_1 = atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_1 = ~atomics_a_mask_sub_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_1 = atomics_a_mask_sub_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_2 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 | _atomics_a_mask_sub_sub_acc_T_2; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_3 = atomics_a_mask_sub_sub_size_1 & atomics_a_mask_sub_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_1 = atomics_a_mask_sub_sub_sub_0_1_1 | _atomics_a_mask_sub_sub_acc_T_3; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_1 = atomics_a_mask_sizeOH_1[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_1 = ~atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_4 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_0_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_1 = atomics_a_mask_sub_sub_0_1_1 | _atomics_a_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_1 = atomics_a_mask_sub_sub_0_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_5 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_1_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_1 = atomics_a_mask_sub_sub_0_1_1 | _atomics_a_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_6 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_2_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_1 = atomics_a_mask_sub_sub_1_1_1 | _atomics_a_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_1 = atomics_a_mask_sub_sub_1_2_1 & atomics_a_mask_sub_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_7 = atomics_a_mask_sub_size_1 & atomics_a_mask_sub_3_2_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_1 = atomics_a_mask_sub_sub_1_1_1 | _atomics_a_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_1 = atomics_a_mask_sizeOH_1[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_1 = ~atomics_a_mask_bit_1; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_8 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_8 = atomics_a_mask_size_1 & atomics_a_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_8 = atomics_a_mask_sub_0_1_1 | _atomics_a_mask_acc_T_8; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_9 = atomics_a_mask_sub_0_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_9 = atomics_a_mask_size_1 & atomics_a_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_9 = atomics_a_mask_sub_0_1_1 | _atomics_a_mask_acc_T_9; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_10 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_10 = atomics_a_mask_size_1 & atomics_a_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_10 = atomics_a_mask_sub_1_1_1 | _atomics_a_mask_acc_T_10; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_11 = atomics_a_mask_sub_1_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_11 = atomics_a_mask_size_1 & atomics_a_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_11 = atomics_a_mask_sub_1_1_1 | _atomics_a_mask_acc_T_11; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_12 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_12 = atomics_a_mask_size_1 & atomics_a_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_12 = atomics_a_mask_sub_2_1_1 | _atomics_a_mask_acc_T_12; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_13 = atomics_a_mask_sub_2_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_13 = atomics_a_mask_size_1 & atomics_a_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_13 = atomics_a_mask_sub_2_1_1 | _atomics_a_mask_acc_T_13; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_14 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_nbit_1; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_14 = atomics_a_mask_size_1 & atomics_a_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_14 = atomics_a_mask_sub_3_1_1 | _atomics_a_mask_acc_T_14; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_15 = atomics_a_mask_sub_3_2_1 & atomics_a_mask_bit_1; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_15 = atomics_a_mask_size_1 & atomics_a_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_15 = atomics_a_mask_sub_3_1_1 | _atomics_a_mask_acc_T_15; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_1 = {atomics_a_mask_acc_9, atomics_a_mask_acc_8}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_1 = {atomics_a_mask_acc_11, atomics_a_mask_acc_10}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_1 = {atomics_a_mask_lo_hi_1, atomics_a_mask_lo_lo_1}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_1 = {atomics_a_mask_acc_13, atomics_a_mask_acc_12}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_1 = {atomics_a_mask_acc_15, atomics_a_mask_acc_14}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_1 = {atomics_a_mask_hi_hi_1, atomics_a_mask_hi_lo_1}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_1 = {atomics_a_mask_hi_1, atomics_a_mask_lo_1}; // @[Misc.scala:222:10]
assign atomics_a_1_mask = _atomics_a_mask_T_1; // @[Misc.scala:222:10]
wire [34:0] _atomics_legal_T_77 = {1'h0, _atomics_legal_T_76}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_78 = _atomics_legal_T_77 & 35'h48110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_79 = _atomics_legal_T_78; // @[Parameters.scala:137:46]
wire _atomics_legal_T_80 = _atomics_legal_T_79 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _atomics_legal_T_82 = {1'h0, _atomics_legal_T_81}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_83 = _atomics_legal_T_82 & 35'h48101000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_84 = _atomics_legal_T_83; // @[Parameters.scala:137:46]
wire _atomics_legal_T_85 = _atomics_legal_T_84 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _atomics_legal_T_87 = {1'h0, _atomics_legal_T_86}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_88 = _atomics_legal_T_87 & 35'h48000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_89 = _atomics_legal_T_88; // @[Parameters.scala:137:46]
wire _atomics_legal_T_90 = _atomics_legal_T_89 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_91 = _atomics_legal_T_80 | _atomics_legal_T_85; // @[Parameters.scala:685:42]
wire _atomics_legal_T_92 = _atomics_legal_T_91 | _atomics_legal_T_90; // @[Parameters.scala:685:42]
wire _atomics_legal_T_93 = _atomics_legal_T_92; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_107 = _atomics_legal_T_93; // @[Parameters.scala:684:54, :686:26]
wire [34:0] _atomics_legal_T_96 = {1'h0, _atomics_legal_T_95}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_97 = _atomics_legal_T_96 & 35'h48110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_98 = _atomics_legal_T_97; // @[Parameters.scala:137:46]
wire _atomics_legal_T_99 = _atomics_legal_T_98 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _atomics_legal_T_101 = {1'h0, _atomics_legal_T_100}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_102 = _atomics_legal_T_101 & 35'h40000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_103 = _atomics_legal_T_102; // @[Parameters.scala:137:46]
wire _atomics_legal_T_104 = _atomics_legal_T_103 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_105 = _atomics_legal_T_99 | _atomics_legal_T_104; // @[Parameters.scala:685:42]
wire atomics_legal_2 = _atomics_legal_T_107; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_2; // @[Misc.scala:222:10]
wire [7:0] atomics_a_2_mask; // @[Edges.scala:534:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_2 = _atomics_a_mask_sizeOH_T_6[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_7 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_2; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_8 = _atomics_a_mask_sizeOH_T_7[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_2 = {_atomics_a_mask_sizeOH_T_8[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_2 = &s2_req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_2 = atomics_a_mask_sizeOH_2[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_2 = atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_2 = ~atomics_a_mask_sub_sub_bit_2; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_2 = atomics_a_mask_sub_sub_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_4 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 | _atomics_a_mask_sub_sub_acc_T_4; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_5 = atomics_a_mask_sub_sub_size_2 & atomics_a_mask_sub_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_2 = atomics_a_mask_sub_sub_sub_0_1_2 | _atomics_a_mask_sub_sub_acc_T_5; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_2 = atomics_a_mask_sizeOH_2[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_2 = ~atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_8 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_0_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_2 = atomics_a_mask_sub_sub_0_1_2 | _atomics_a_mask_sub_acc_T_8; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_2 = atomics_a_mask_sub_sub_0_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_9 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_1_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_2 = atomics_a_mask_sub_sub_0_1_2 | _atomics_a_mask_sub_acc_T_9; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_10 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_2_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_2 = atomics_a_mask_sub_sub_1_1_2 | _atomics_a_mask_sub_acc_T_10; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_2 = atomics_a_mask_sub_sub_1_2_2 & atomics_a_mask_sub_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_11 = atomics_a_mask_sub_size_2 & atomics_a_mask_sub_3_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_2 = atomics_a_mask_sub_sub_1_1_2 | _atomics_a_mask_sub_acc_T_11; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_2 = atomics_a_mask_sizeOH_2[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_2 = ~atomics_a_mask_bit_2; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_16 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_16 = atomics_a_mask_size_2 & atomics_a_mask_eq_16; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_16 = atomics_a_mask_sub_0_1_2 | _atomics_a_mask_acc_T_16; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_17 = atomics_a_mask_sub_0_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_17 = atomics_a_mask_size_2 & atomics_a_mask_eq_17; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_17 = atomics_a_mask_sub_0_1_2 | _atomics_a_mask_acc_T_17; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_18 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_18 = atomics_a_mask_size_2 & atomics_a_mask_eq_18; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_18 = atomics_a_mask_sub_1_1_2 | _atomics_a_mask_acc_T_18; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_19 = atomics_a_mask_sub_1_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_19 = atomics_a_mask_size_2 & atomics_a_mask_eq_19; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_19 = atomics_a_mask_sub_1_1_2 | _atomics_a_mask_acc_T_19; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_20 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_20 = atomics_a_mask_size_2 & atomics_a_mask_eq_20; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_20 = atomics_a_mask_sub_2_1_2 | _atomics_a_mask_acc_T_20; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_21 = atomics_a_mask_sub_2_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_21 = atomics_a_mask_size_2 & atomics_a_mask_eq_21; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_21 = atomics_a_mask_sub_2_1_2 | _atomics_a_mask_acc_T_21; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_22 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_nbit_2; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_22 = atomics_a_mask_size_2 & atomics_a_mask_eq_22; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_22 = atomics_a_mask_sub_3_1_2 | _atomics_a_mask_acc_T_22; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_23 = atomics_a_mask_sub_3_2_2 & atomics_a_mask_bit_2; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_23 = atomics_a_mask_size_2 & atomics_a_mask_eq_23; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_23 = atomics_a_mask_sub_3_1_2 | _atomics_a_mask_acc_T_23; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_2 = {atomics_a_mask_acc_17, atomics_a_mask_acc_16}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_2 = {atomics_a_mask_acc_19, atomics_a_mask_acc_18}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_2 = {atomics_a_mask_lo_hi_2, atomics_a_mask_lo_lo_2}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_2 = {atomics_a_mask_acc_21, atomics_a_mask_acc_20}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_2 = {atomics_a_mask_acc_23, atomics_a_mask_acc_22}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_2 = {atomics_a_mask_hi_hi_2, atomics_a_mask_hi_lo_2}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_2 = {atomics_a_mask_hi_2, atomics_a_mask_lo_2}; // @[Misc.scala:222:10]
assign atomics_a_2_mask = _atomics_a_mask_T_2; // @[Misc.scala:222:10]
wire [34:0] _atomics_legal_T_113 = {1'h0, _atomics_legal_T_112}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_114 = _atomics_legal_T_113 & 35'h48110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_115 = _atomics_legal_T_114; // @[Parameters.scala:137:46]
wire _atomics_legal_T_116 = _atomics_legal_T_115 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _atomics_legal_T_118 = {1'h0, _atomics_legal_T_117}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_119 = _atomics_legal_T_118 & 35'h48101000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_120 = _atomics_legal_T_119; // @[Parameters.scala:137:46]
wire _atomics_legal_T_121 = _atomics_legal_T_120 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _atomics_legal_T_123 = {1'h0, _atomics_legal_T_122}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_124 = _atomics_legal_T_123 & 35'h48000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_125 = _atomics_legal_T_124; // @[Parameters.scala:137:46]
wire _atomics_legal_T_126 = _atomics_legal_T_125 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_127 = _atomics_legal_T_116 | _atomics_legal_T_121; // @[Parameters.scala:685:42]
wire _atomics_legal_T_128 = _atomics_legal_T_127 | _atomics_legal_T_126; // @[Parameters.scala:685:42]
wire _atomics_legal_T_129 = _atomics_legal_T_128; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_143 = _atomics_legal_T_129; // @[Parameters.scala:684:54, :686:26]
wire [34:0] _atomics_legal_T_132 = {1'h0, _atomics_legal_T_131}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_133 = _atomics_legal_T_132 & 35'h48110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_134 = _atomics_legal_T_133; // @[Parameters.scala:137:46]
wire _atomics_legal_T_135 = _atomics_legal_T_134 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _atomics_legal_T_137 = {1'h0, _atomics_legal_T_136}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_138 = _atomics_legal_T_137 & 35'h40000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_139 = _atomics_legal_T_138; // @[Parameters.scala:137:46]
wire _atomics_legal_T_140 = _atomics_legal_T_139 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_141 = _atomics_legal_T_135 | _atomics_legal_T_140; // @[Parameters.scala:685:42]
wire atomics_legal_3 = _atomics_legal_T_143; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_3; // @[Misc.scala:222:10]
wire [7:0] atomics_a_3_mask; // @[Edges.scala:534:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_3 = _atomics_a_mask_sizeOH_T_9[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_10 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_3; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_11 = _atomics_a_mask_sizeOH_T_10[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_3 = {_atomics_a_mask_sizeOH_T_11[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_3 = &s2_req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_3 = atomics_a_mask_sizeOH_3[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_3 = atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_3 = ~atomics_a_mask_sub_sub_bit_3; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_3 = atomics_a_mask_sub_sub_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_6 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 | _atomics_a_mask_sub_sub_acc_T_6; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_7 = atomics_a_mask_sub_sub_size_3 & atomics_a_mask_sub_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_3 = atomics_a_mask_sub_sub_sub_0_1_3 | _atomics_a_mask_sub_sub_acc_T_7; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_3 = atomics_a_mask_sizeOH_3[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_3 = ~atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_12 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_0_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_3 = atomics_a_mask_sub_sub_0_1_3 | _atomics_a_mask_sub_acc_T_12; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_3 = atomics_a_mask_sub_sub_0_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_13 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_1_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_3 = atomics_a_mask_sub_sub_0_1_3 | _atomics_a_mask_sub_acc_T_13; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_14 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_2_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_3 = atomics_a_mask_sub_sub_1_1_3 | _atomics_a_mask_sub_acc_T_14; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_3 = atomics_a_mask_sub_sub_1_2_3 & atomics_a_mask_sub_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_15 = atomics_a_mask_sub_size_3 & atomics_a_mask_sub_3_2_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_3 = atomics_a_mask_sub_sub_1_1_3 | _atomics_a_mask_sub_acc_T_15; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_3 = atomics_a_mask_sizeOH_3[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_3 = ~atomics_a_mask_bit_3; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_24 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_24 = atomics_a_mask_size_3 & atomics_a_mask_eq_24; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_24 = atomics_a_mask_sub_0_1_3 | _atomics_a_mask_acc_T_24; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_25 = atomics_a_mask_sub_0_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_25 = atomics_a_mask_size_3 & atomics_a_mask_eq_25; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_25 = atomics_a_mask_sub_0_1_3 | _atomics_a_mask_acc_T_25; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_26 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_26 = atomics_a_mask_size_3 & atomics_a_mask_eq_26; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_26 = atomics_a_mask_sub_1_1_3 | _atomics_a_mask_acc_T_26; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_27 = atomics_a_mask_sub_1_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_27 = atomics_a_mask_size_3 & atomics_a_mask_eq_27; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_27 = atomics_a_mask_sub_1_1_3 | _atomics_a_mask_acc_T_27; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_28 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_28 = atomics_a_mask_size_3 & atomics_a_mask_eq_28; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_28 = atomics_a_mask_sub_2_1_3 | _atomics_a_mask_acc_T_28; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_29 = atomics_a_mask_sub_2_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_29 = atomics_a_mask_size_3 & atomics_a_mask_eq_29; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_29 = atomics_a_mask_sub_2_1_3 | _atomics_a_mask_acc_T_29; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_30 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_nbit_3; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_30 = atomics_a_mask_size_3 & atomics_a_mask_eq_30; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_30 = atomics_a_mask_sub_3_1_3 | _atomics_a_mask_acc_T_30; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_31 = atomics_a_mask_sub_3_2_3 & atomics_a_mask_bit_3; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_31 = atomics_a_mask_size_3 & atomics_a_mask_eq_31; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_31 = atomics_a_mask_sub_3_1_3 | _atomics_a_mask_acc_T_31; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_3 = {atomics_a_mask_acc_25, atomics_a_mask_acc_24}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_3 = {atomics_a_mask_acc_27, atomics_a_mask_acc_26}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_3 = {atomics_a_mask_lo_hi_3, atomics_a_mask_lo_lo_3}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_3 = {atomics_a_mask_acc_29, atomics_a_mask_acc_28}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_3 = {atomics_a_mask_acc_31, atomics_a_mask_acc_30}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_3 = {atomics_a_mask_hi_hi_3, atomics_a_mask_hi_lo_3}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_3 = {atomics_a_mask_hi_3, atomics_a_mask_lo_3}; // @[Misc.scala:222:10]
assign atomics_a_3_mask = _atomics_a_mask_T_3; // @[Misc.scala:222:10]
wire [34:0] _atomics_legal_T_149 = {1'h0, _atomics_legal_T_148}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_150 = _atomics_legal_T_149 & 35'h48110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_151 = _atomics_legal_T_150; // @[Parameters.scala:137:46]
wire _atomics_legal_T_152 = _atomics_legal_T_151 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _atomics_legal_T_154 = {1'h0, _atomics_legal_T_153}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_155 = _atomics_legal_T_154 & 35'h48101000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_156 = _atomics_legal_T_155; // @[Parameters.scala:137:46]
wire _atomics_legal_T_157 = _atomics_legal_T_156 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _atomics_legal_T_159 = {1'h0, _atomics_legal_T_158}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_160 = _atomics_legal_T_159 & 35'h48000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_161 = _atomics_legal_T_160; // @[Parameters.scala:137:46]
wire _atomics_legal_T_162 = _atomics_legal_T_161 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_163 = _atomics_legal_T_152 | _atomics_legal_T_157; // @[Parameters.scala:685:42]
wire _atomics_legal_T_164 = _atomics_legal_T_163 | _atomics_legal_T_162; // @[Parameters.scala:685:42]
wire _atomics_legal_T_165 = _atomics_legal_T_164; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_179 = _atomics_legal_T_165; // @[Parameters.scala:684:54, :686:26]
wire [34:0] _atomics_legal_T_168 = {1'h0, _atomics_legal_T_167}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_169 = _atomics_legal_T_168 & 35'h48110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_170 = _atomics_legal_T_169; // @[Parameters.scala:137:46]
wire _atomics_legal_T_171 = _atomics_legal_T_170 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _atomics_legal_T_173 = {1'h0, _atomics_legal_T_172}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_174 = _atomics_legal_T_173 & 35'h40000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_175 = _atomics_legal_T_174; // @[Parameters.scala:137:46]
wire _atomics_legal_T_176 = _atomics_legal_T_175 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_177 = _atomics_legal_T_171 | _atomics_legal_T_176; // @[Parameters.scala:685:42]
wire atomics_legal_4 = _atomics_legal_T_179; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_4; // @[Misc.scala:222:10]
wire [7:0] atomics_a_4_mask; // @[Edges.scala:517:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_4 = _atomics_a_mask_sizeOH_T_12[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_13 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_4; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_14 = _atomics_a_mask_sizeOH_T_13[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_4 = {_atomics_a_mask_sizeOH_T_14[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_4 = &s2_req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_4 = atomics_a_mask_sizeOH_4[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_4 = atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_4 = ~atomics_a_mask_sub_sub_bit_4; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_4 = atomics_a_mask_sub_sub_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_8 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 | _atomics_a_mask_sub_sub_acc_T_8; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_9 = atomics_a_mask_sub_sub_size_4 & atomics_a_mask_sub_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_4 = atomics_a_mask_sub_sub_sub_0_1_4 | _atomics_a_mask_sub_sub_acc_T_9; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_4 = atomics_a_mask_sizeOH_4[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_4 = ~atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_16 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_0_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_4 = atomics_a_mask_sub_sub_0_1_4 | _atomics_a_mask_sub_acc_T_16; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_4 = atomics_a_mask_sub_sub_0_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_17 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_1_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_4 = atomics_a_mask_sub_sub_0_1_4 | _atomics_a_mask_sub_acc_T_17; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_18 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_2_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_4 = atomics_a_mask_sub_sub_1_1_4 | _atomics_a_mask_sub_acc_T_18; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_4 = atomics_a_mask_sub_sub_1_2_4 & atomics_a_mask_sub_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_19 = atomics_a_mask_sub_size_4 & atomics_a_mask_sub_3_2_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_4 = atomics_a_mask_sub_sub_1_1_4 | _atomics_a_mask_sub_acc_T_19; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_4 = atomics_a_mask_sizeOH_4[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_4 = ~atomics_a_mask_bit_4; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_32 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_32 = atomics_a_mask_size_4 & atomics_a_mask_eq_32; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_32 = atomics_a_mask_sub_0_1_4 | _atomics_a_mask_acc_T_32; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_33 = atomics_a_mask_sub_0_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_33 = atomics_a_mask_size_4 & atomics_a_mask_eq_33; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_33 = atomics_a_mask_sub_0_1_4 | _atomics_a_mask_acc_T_33; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_34 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_34 = atomics_a_mask_size_4 & atomics_a_mask_eq_34; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_34 = atomics_a_mask_sub_1_1_4 | _atomics_a_mask_acc_T_34; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_35 = atomics_a_mask_sub_1_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_35 = atomics_a_mask_size_4 & atomics_a_mask_eq_35; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_35 = atomics_a_mask_sub_1_1_4 | _atomics_a_mask_acc_T_35; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_36 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_36 = atomics_a_mask_size_4 & atomics_a_mask_eq_36; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_36 = atomics_a_mask_sub_2_1_4 | _atomics_a_mask_acc_T_36; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_37 = atomics_a_mask_sub_2_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_37 = atomics_a_mask_size_4 & atomics_a_mask_eq_37; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_37 = atomics_a_mask_sub_2_1_4 | _atomics_a_mask_acc_T_37; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_38 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_nbit_4; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_38 = atomics_a_mask_size_4 & atomics_a_mask_eq_38; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_38 = atomics_a_mask_sub_3_1_4 | _atomics_a_mask_acc_T_38; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_39 = atomics_a_mask_sub_3_2_4 & atomics_a_mask_bit_4; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_39 = atomics_a_mask_size_4 & atomics_a_mask_eq_39; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_39 = atomics_a_mask_sub_3_1_4 | _atomics_a_mask_acc_T_39; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_4 = {atomics_a_mask_acc_33, atomics_a_mask_acc_32}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_4 = {atomics_a_mask_acc_35, atomics_a_mask_acc_34}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_4 = {atomics_a_mask_lo_hi_4, atomics_a_mask_lo_lo_4}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_4 = {atomics_a_mask_acc_37, atomics_a_mask_acc_36}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_4 = {atomics_a_mask_acc_39, atomics_a_mask_acc_38}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_4 = {atomics_a_mask_hi_hi_4, atomics_a_mask_hi_lo_4}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_4 = {atomics_a_mask_hi_4, atomics_a_mask_lo_4}; // @[Misc.scala:222:10]
assign atomics_a_4_mask = _atomics_a_mask_T_4; // @[Misc.scala:222:10]
wire [34:0] _atomics_legal_T_185 = {1'h0, _atomics_legal_T_184}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_186 = _atomics_legal_T_185 & 35'h48110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_187 = _atomics_legal_T_186; // @[Parameters.scala:137:46]
wire _atomics_legal_T_188 = _atomics_legal_T_187 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _atomics_legal_T_190 = {1'h0, _atomics_legal_T_189}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_191 = _atomics_legal_T_190 & 35'h48101000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_192 = _atomics_legal_T_191; // @[Parameters.scala:137:46]
wire _atomics_legal_T_193 = _atomics_legal_T_192 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _atomics_legal_T_195 = {1'h0, _atomics_legal_T_194}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_196 = _atomics_legal_T_195 & 35'h48000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_197 = _atomics_legal_T_196; // @[Parameters.scala:137:46]
wire _atomics_legal_T_198 = _atomics_legal_T_197 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_199 = _atomics_legal_T_188 | _atomics_legal_T_193; // @[Parameters.scala:685:42]
wire _atomics_legal_T_200 = _atomics_legal_T_199 | _atomics_legal_T_198; // @[Parameters.scala:685:42]
wire _atomics_legal_T_201 = _atomics_legal_T_200; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_215 = _atomics_legal_T_201; // @[Parameters.scala:684:54, :686:26]
wire [34:0] _atomics_legal_T_204 = {1'h0, _atomics_legal_T_203}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_205 = _atomics_legal_T_204 & 35'h48110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_206 = _atomics_legal_T_205; // @[Parameters.scala:137:46]
wire _atomics_legal_T_207 = _atomics_legal_T_206 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _atomics_legal_T_209 = {1'h0, _atomics_legal_T_208}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_210 = _atomics_legal_T_209 & 35'h40000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_211 = _atomics_legal_T_210; // @[Parameters.scala:137:46]
wire _atomics_legal_T_212 = _atomics_legal_T_211 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_213 = _atomics_legal_T_207 | _atomics_legal_T_212; // @[Parameters.scala:685:42]
wire atomics_legal_5 = _atomics_legal_T_215; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_5; // @[Misc.scala:222:10]
wire [7:0] atomics_a_5_mask; // @[Edges.scala:517:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_5 = _atomics_a_mask_sizeOH_T_15[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_16 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_5; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_17 = _atomics_a_mask_sizeOH_T_16[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_5 = {_atomics_a_mask_sizeOH_T_17[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_5 = &s2_req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_5 = atomics_a_mask_sizeOH_5[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_5 = atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_5 = ~atomics_a_mask_sub_sub_bit_5; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_5 = atomics_a_mask_sub_sub_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_10 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 | _atomics_a_mask_sub_sub_acc_T_10; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_11 = atomics_a_mask_sub_sub_size_5 & atomics_a_mask_sub_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_5 = atomics_a_mask_sub_sub_sub_0_1_5 | _atomics_a_mask_sub_sub_acc_T_11; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_5 = atomics_a_mask_sizeOH_5[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_5 = ~atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_20 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_0_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_5 = atomics_a_mask_sub_sub_0_1_5 | _atomics_a_mask_sub_acc_T_20; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_5 = atomics_a_mask_sub_sub_0_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_21 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_1_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_5 = atomics_a_mask_sub_sub_0_1_5 | _atomics_a_mask_sub_acc_T_21; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_22 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_2_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_5 = atomics_a_mask_sub_sub_1_1_5 | _atomics_a_mask_sub_acc_T_22; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_5 = atomics_a_mask_sub_sub_1_2_5 & atomics_a_mask_sub_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_23 = atomics_a_mask_sub_size_5 & atomics_a_mask_sub_3_2_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_5 = atomics_a_mask_sub_sub_1_1_5 | _atomics_a_mask_sub_acc_T_23; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_5 = atomics_a_mask_sizeOH_5[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_5 = ~atomics_a_mask_bit_5; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_40 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_40 = atomics_a_mask_size_5 & atomics_a_mask_eq_40; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_40 = atomics_a_mask_sub_0_1_5 | _atomics_a_mask_acc_T_40; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_41 = atomics_a_mask_sub_0_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_41 = atomics_a_mask_size_5 & atomics_a_mask_eq_41; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_41 = atomics_a_mask_sub_0_1_5 | _atomics_a_mask_acc_T_41; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_42 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_42 = atomics_a_mask_size_5 & atomics_a_mask_eq_42; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_42 = atomics_a_mask_sub_1_1_5 | _atomics_a_mask_acc_T_42; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_43 = atomics_a_mask_sub_1_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_43 = atomics_a_mask_size_5 & atomics_a_mask_eq_43; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_43 = atomics_a_mask_sub_1_1_5 | _atomics_a_mask_acc_T_43; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_44 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_44 = atomics_a_mask_size_5 & atomics_a_mask_eq_44; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_44 = atomics_a_mask_sub_2_1_5 | _atomics_a_mask_acc_T_44; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_45 = atomics_a_mask_sub_2_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_45 = atomics_a_mask_size_5 & atomics_a_mask_eq_45; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_45 = atomics_a_mask_sub_2_1_5 | _atomics_a_mask_acc_T_45; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_46 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_nbit_5; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_46 = atomics_a_mask_size_5 & atomics_a_mask_eq_46; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_46 = atomics_a_mask_sub_3_1_5 | _atomics_a_mask_acc_T_46; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_47 = atomics_a_mask_sub_3_2_5 & atomics_a_mask_bit_5; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_47 = atomics_a_mask_size_5 & atomics_a_mask_eq_47; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_47 = atomics_a_mask_sub_3_1_5 | _atomics_a_mask_acc_T_47; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_5 = {atomics_a_mask_acc_41, atomics_a_mask_acc_40}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_5 = {atomics_a_mask_acc_43, atomics_a_mask_acc_42}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_5 = {atomics_a_mask_lo_hi_5, atomics_a_mask_lo_lo_5}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_5 = {atomics_a_mask_acc_45, atomics_a_mask_acc_44}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_5 = {atomics_a_mask_acc_47, atomics_a_mask_acc_46}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_5 = {atomics_a_mask_hi_hi_5, atomics_a_mask_hi_lo_5}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_5 = {atomics_a_mask_hi_5, atomics_a_mask_lo_5}; // @[Misc.scala:222:10]
assign atomics_a_5_mask = _atomics_a_mask_T_5; // @[Misc.scala:222:10]
wire [34:0] _atomics_legal_T_221 = {1'h0, _atomics_legal_T_220}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_222 = _atomics_legal_T_221 & 35'h48110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_223 = _atomics_legal_T_222; // @[Parameters.scala:137:46]
wire _atomics_legal_T_224 = _atomics_legal_T_223 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _atomics_legal_T_226 = {1'h0, _atomics_legal_T_225}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_227 = _atomics_legal_T_226 & 35'h48101000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_228 = _atomics_legal_T_227; // @[Parameters.scala:137:46]
wire _atomics_legal_T_229 = _atomics_legal_T_228 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _atomics_legal_T_231 = {1'h0, _atomics_legal_T_230}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_232 = _atomics_legal_T_231 & 35'h48000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_233 = _atomics_legal_T_232; // @[Parameters.scala:137:46]
wire _atomics_legal_T_234 = _atomics_legal_T_233 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_235 = _atomics_legal_T_224 | _atomics_legal_T_229; // @[Parameters.scala:685:42]
wire _atomics_legal_T_236 = _atomics_legal_T_235 | _atomics_legal_T_234; // @[Parameters.scala:685:42]
wire _atomics_legal_T_237 = _atomics_legal_T_236; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_251 = _atomics_legal_T_237; // @[Parameters.scala:684:54, :686:26]
wire [34:0] _atomics_legal_T_240 = {1'h0, _atomics_legal_T_239}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_241 = _atomics_legal_T_240 & 35'h48110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_242 = _atomics_legal_T_241; // @[Parameters.scala:137:46]
wire _atomics_legal_T_243 = _atomics_legal_T_242 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _atomics_legal_T_245 = {1'h0, _atomics_legal_T_244}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_246 = _atomics_legal_T_245 & 35'h40000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_247 = _atomics_legal_T_246; // @[Parameters.scala:137:46]
wire _atomics_legal_T_248 = _atomics_legal_T_247 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_249 = _atomics_legal_T_243 | _atomics_legal_T_248; // @[Parameters.scala:685:42]
wire atomics_legal_6 = _atomics_legal_T_251; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_6; // @[Misc.scala:222:10]
wire [7:0] atomics_a_6_mask; // @[Edges.scala:517:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_6 = _atomics_a_mask_sizeOH_T_18[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_19 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_6; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_20 = _atomics_a_mask_sizeOH_T_19[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_6 = {_atomics_a_mask_sizeOH_T_20[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_6 = &s2_req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_6 = atomics_a_mask_sizeOH_6[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_6 = atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_6 = ~atomics_a_mask_sub_sub_bit_6; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_6 = atomics_a_mask_sub_sub_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_12 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 | _atomics_a_mask_sub_sub_acc_T_12; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_13 = atomics_a_mask_sub_sub_size_6 & atomics_a_mask_sub_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_6 = atomics_a_mask_sub_sub_sub_0_1_6 | _atomics_a_mask_sub_sub_acc_T_13; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_6 = atomics_a_mask_sizeOH_6[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_6 = ~atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_24 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_0_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_6 = atomics_a_mask_sub_sub_0_1_6 | _atomics_a_mask_sub_acc_T_24; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_6 = atomics_a_mask_sub_sub_0_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_25 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_1_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_6 = atomics_a_mask_sub_sub_0_1_6 | _atomics_a_mask_sub_acc_T_25; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_26 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_2_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_6 = atomics_a_mask_sub_sub_1_1_6 | _atomics_a_mask_sub_acc_T_26; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_6 = atomics_a_mask_sub_sub_1_2_6 & atomics_a_mask_sub_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_27 = atomics_a_mask_sub_size_6 & atomics_a_mask_sub_3_2_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_6 = atomics_a_mask_sub_sub_1_1_6 | _atomics_a_mask_sub_acc_T_27; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_6 = atomics_a_mask_sizeOH_6[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_6 = ~atomics_a_mask_bit_6; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_48 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_48 = atomics_a_mask_size_6 & atomics_a_mask_eq_48; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_48 = atomics_a_mask_sub_0_1_6 | _atomics_a_mask_acc_T_48; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_49 = atomics_a_mask_sub_0_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_49 = atomics_a_mask_size_6 & atomics_a_mask_eq_49; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_49 = atomics_a_mask_sub_0_1_6 | _atomics_a_mask_acc_T_49; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_50 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_50 = atomics_a_mask_size_6 & atomics_a_mask_eq_50; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_50 = atomics_a_mask_sub_1_1_6 | _atomics_a_mask_acc_T_50; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_51 = atomics_a_mask_sub_1_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_51 = atomics_a_mask_size_6 & atomics_a_mask_eq_51; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_51 = atomics_a_mask_sub_1_1_6 | _atomics_a_mask_acc_T_51; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_52 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_52 = atomics_a_mask_size_6 & atomics_a_mask_eq_52; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_52 = atomics_a_mask_sub_2_1_6 | _atomics_a_mask_acc_T_52; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_53 = atomics_a_mask_sub_2_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_53 = atomics_a_mask_size_6 & atomics_a_mask_eq_53; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_53 = atomics_a_mask_sub_2_1_6 | _atomics_a_mask_acc_T_53; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_54 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_nbit_6; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_54 = atomics_a_mask_size_6 & atomics_a_mask_eq_54; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_54 = atomics_a_mask_sub_3_1_6 | _atomics_a_mask_acc_T_54; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_55 = atomics_a_mask_sub_3_2_6 & atomics_a_mask_bit_6; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_55 = atomics_a_mask_size_6 & atomics_a_mask_eq_55; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_55 = atomics_a_mask_sub_3_1_6 | _atomics_a_mask_acc_T_55; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_6 = {atomics_a_mask_acc_49, atomics_a_mask_acc_48}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_6 = {atomics_a_mask_acc_51, atomics_a_mask_acc_50}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_6 = {atomics_a_mask_lo_hi_6, atomics_a_mask_lo_lo_6}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_6 = {atomics_a_mask_acc_53, atomics_a_mask_acc_52}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_6 = {atomics_a_mask_acc_55, atomics_a_mask_acc_54}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_6 = {atomics_a_mask_hi_hi_6, atomics_a_mask_hi_lo_6}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_6 = {atomics_a_mask_hi_6, atomics_a_mask_lo_6}; // @[Misc.scala:222:10]
assign atomics_a_6_mask = _atomics_a_mask_T_6; // @[Misc.scala:222:10]
wire [34:0] _atomics_legal_T_257 = {1'h0, _atomics_legal_T_256}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_258 = _atomics_legal_T_257 & 35'h48110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_259 = _atomics_legal_T_258; // @[Parameters.scala:137:46]
wire _atomics_legal_T_260 = _atomics_legal_T_259 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _atomics_legal_T_262 = {1'h0, _atomics_legal_T_261}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_263 = _atomics_legal_T_262 & 35'h48101000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_264 = _atomics_legal_T_263; // @[Parameters.scala:137:46]
wire _atomics_legal_T_265 = _atomics_legal_T_264 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _atomics_legal_T_267 = {1'h0, _atomics_legal_T_266}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_268 = _atomics_legal_T_267 & 35'h48000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_269 = _atomics_legal_T_268; // @[Parameters.scala:137:46]
wire _atomics_legal_T_270 = _atomics_legal_T_269 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_271 = _atomics_legal_T_260 | _atomics_legal_T_265; // @[Parameters.scala:685:42]
wire _atomics_legal_T_272 = _atomics_legal_T_271 | _atomics_legal_T_270; // @[Parameters.scala:685:42]
wire _atomics_legal_T_273 = _atomics_legal_T_272; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_287 = _atomics_legal_T_273; // @[Parameters.scala:684:54, :686:26]
wire [34:0] _atomics_legal_T_276 = {1'h0, _atomics_legal_T_275}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_277 = _atomics_legal_T_276 & 35'h48110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_278 = _atomics_legal_T_277; // @[Parameters.scala:137:46]
wire _atomics_legal_T_279 = _atomics_legal_T_278 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _atomics_legal_T_281 = {1'h0, _atomics_legal_T_280}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_282 = _atomics_legal_T_281 & 35'h40000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_283 = _atomics_legal_T_282; // @[Parameters.scala:137:46]
wire _atomics_legal_T_284 = _atomics_legal_T_283 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_285 = _atomics_legal_T_279 | _atomics_legal_T_284; // @[Parameters.scala:685:42]
wire atomics_legal_7 = _atomics_legal_T_287; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_7; // @[Misc.scala:222:10]
wire [7:0] atomics_a_7_mask; // @[Edges.scala:517:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_7 = _atomics_a_mask_sizeOH_T_21[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_22 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_7; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_23 = _atomics_a_mask_sizeOH_T_22[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_7 = {_atomics_a_mask_sizeOH_T_23[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_7 = &s2_req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_7 = atomics_a_mask_sizeOH_7[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_7 = atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_7 = ~atomics_a_mask_sub_sub_bit_7; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_7 = atomics_a_mask_sub_sub_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_14 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 | _atomics_a_mask_sub_sub_acc_T_14; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_15 = atomics_a_mask_sub_sub_size_7 & atomics_a_mask_sub_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_7 = atomics_a_mask_sub_sub_sub_0_1_7 | _atomics_a_mask_sub_sub_acc_T_15; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_7 = atomics_a_mask_sizeOH_7[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_7 = ~atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_28 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_0_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_7 = atomics_a_mask_sub_sub_0_1_7 | _atomics_a_mask_sub_acc_T_28; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_7 = atomics_a_mask_sub_sub_0_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_29 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_1_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_7 = atomics_a_mask_sub_sub_0_1_7 | _atomics_a_mask_sub_acc_T_29; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_30 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_2_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_7 = atomics_a_mask_sub_sub_1_1_7 | _atomics_a_mask_sub_acc_T_30; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_7 = atomics_a_mask_sub_sub_1_2_7 & atomics_a_mask_sub_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_31 = atomics_a_mask_sub_size_7 & atomics_a_mask_sub_3_2_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_7 = atomics_a_mask_sub_sub_1_1_7 | _atomics_a_mask_sub_acc_T_31; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_7 = atomics_a_mask_sizeOH_7[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_7 = ~atomics_a_mask_bit_7; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_56 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_56 = atomics_a_mask_size_7 & atomics_a_mask_eq_56; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_56 = atomics_a_mask_sub_0_1_7 | _atomics_a_mask_acc_T_56; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_57 = atomics_a_mask_sub_0_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_57 = atomics_a_mask_size_7 & atomics_a_mask_eq_57; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_57 = atomics_a_mask_sub_0_1_7 | _atomics_a_mask_acc_T_57; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_58 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_58 = atomics_a_mask_size_7 & atomics_a_mask_eq_58; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_58 = atomics_a_mask_sub_1_1_7 | _atomics_a_mask_acc_T_58; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_59 = atomics_a_mask_sub_1_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_59 = atomics_a_mask_size_7 & atomics_a_mask_eq_59; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_59 = atomics_a_mask_sub_1_1_7 | _atomics_a_mask_acc_T_59; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_60 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_60 = atomics_a_mask_size_7 & atomics_a_mask_eq_60; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_60 = atomics_a_mask_sub_2_1_7 | _atomics_a_mask_acc_T_60; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_61 = atomics_a_mask_sub_2_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_61 = atomics_a_mask_size_7 & atomics_a_mask_eq_61; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_61 = atomics_a_mask_sub_2_1_7 | _atomics_a_mask_acc_T_61; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_62 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_nbit_7; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_62 = atomics_a_mask_size_7 & atomics_a_mask_eq_62; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_62 = atomics_a_mask_sub_3_1_7 | _atomics_a_mask_acc_T_62; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_63 = atomics_a_mask_sub_3_2_7 & atomics_a_mask_bit_7; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_63 = atomics_a_mask_size_7 & atomics_a_mask_eq_63; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_63 = atomics_a_mask_sub_3_1_7 | _atomics_a_mask_acc_T_63; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_7 = {atomics_a_mask_acc_57, atomics_a_mask_acc_56}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_7 = {atomics_a_mask_acc_59, atomics_a_mask_acc_58}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_7 = {atomics_a_mask_lo_hi_7, atomics_a_mask_lo_lo_7}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_7 = {atomics_a_mask_acc_61, atomics_a_mask_acc_60}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_7 = {atomics_a_mask_acc_63, atomics_a_mask_acc_62}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_7 = {atomics_a_mask_hi_hi_7, atomics_a_mask_hi_lo_7}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_7 = {atomics_a_mask_hi_7, atomics_a_mask_lo_7}; // @[Misc.scala:222:10]
assign atomics_a_7_mask = _atomics_a_mask_T_7; // @[Misc.scala:222:10]
wire [34:0] _atomics_legal_T_293 = {1'h0, _atomics_legal_T_292}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_294 = _atomics_legal_T_293 & 35'h48110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_295 = _atomics_legal_T_294; // @[Parameters.scala:137:46]
wire _atomics_legal_T_296 = _atomics_legal_T_295 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _atomics_legal_T_298 = {1'h0, _atomics_legal_T_297}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_299 = _atomics_legal_T_298 & 35'h48101000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_300 = _atomics_legal_T_299; // @[Parameters.scala:137:46]
wire _atomics_legal_T_301 = _atomics_legal_T_300 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _atomics_legal_T_303 = {1'h0, _atomics_legal_T_302}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_304 = _atomics_legal_T_303 & 35'h48000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_305 = _atomics_legal_T_304; // @[Parameters.scala:137:46]
wire _atomics_legal_T_306 = _atomics_legal_T_305 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_307 = _atomics_legal_T_296 | _atomics_legal_T_301; // @[Parameters.scala:685:42]
wire _atomics_legal_T_308 = _atomics_legal_T_307 | _atomics_legal_T_306; // @[Parameters.scala:685:42]
wire _atomics_legal_T_309 = _atomics_legal_T_308; // @[Parameters.scala:684:54, :685:42]
wire _atomics_legal_T_323 = _atomics_legal_T_309; // @[Parameters.scala:684:54, :686:26]
wire [34:0] _atomics_legal_T_312 = {1'h0, _atomics_legal_T_311}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_313 = _atomics_legal_T_312 & 35'h48110000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_314 = _atomics_legal_T_313; // @[Parameters.scala:137:46]
wire _atomics_legal_T_315 = _atomics_legal_T_314 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire [34:0] _atomics_legal_T_317 = {1'h0, _atomics_legal_T_316}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _atomics_legal_T_318 = _atomics_legal_T_317 & 35'h40000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _atomics_legal_T_319 = _atomics_legal_T_318; // @[Parameters.scala:137:46]
wire _atomics_legal_T_320 = _atomics_legal_T_319 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _atomics_legal_T_321 = _atomics_legal_T_315 | _atomics_legal_T_320; // @[Parameters.scala:685:42]
wire atomics_legal_8 = _atomics_legal_T_323; // @[Parameters.scala:686:26]
wire [7:0] _atomics_a_mask_T_8; // @[Misc.scala:222:10]
wire [7:0] atomics_a_8_mask; // @[Edges.scala:517:17]
wire [1:0] atomics_a_mask_sizeOH_shiftAmount_8 = _atomics_a_mask_sizeOH_T_24[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _atomics_a_mask_sizeOH_T_25 = 4'h1 << atomics_a_mask_sizeOH_shiftAmount_8; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _atomics_a_mask_sizeOH_T_26 = _atomics_a_mask_sizeOH_T_25[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] atomics_a_mask_sizeOH_8 = {_atomics_a_mask_sizeOH_T_26[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire atomics_a_mask_sub_sub_sub_0_1_8 = &s2_req_size; // @[Misc.scala:206:21]
wire atomics_a_mask_sub_sub_size_8 = atomics_a_mask_sizeOH_8[2]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_sub_1_2_8 = atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :214:27]
wire atomics_a_mask_sub_sub_nbit_8 = ~atomics_a_mask_sub_sub_bit_8; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_sub_0_2_8 = atomics_a_mask_sub_sub_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_sub_acc_T_16 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_0_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 | _atomics_a_mask_sub_sub_acc_T_16; // @[Misc.scala:206:21, :215:{29,38}]
wire _atomics_a_mask_sub_sub_acc_T_17 = atomics_a_mask_sub_sub_size_8 & atomics_a_mask_sub_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_sub_1_1_8 = atomics_a_mask_sub_sub_sub_0_1_8 | _atomics_a_mask_sub_sub_acc_T_17; // @[Misc.scala:206:21, :215:{29,38}]
wire atomics_a_mask_sub_size_8 = atomics_a_mask_sizeOH_8[1]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_sub_nbit_8 = ~atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_sub_0_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_32 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_0_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_0_1_8 = atomics_a_mask_sub_sub_0_1_8 | _atomics_a_mask_sub_acc_T_32; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_1_2_8 = atomics_a_mask_sub_sub_0_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_33 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_1_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_1_1_8 = atomics_a_mask_sub_sub_0_1_8 | _atomics_a_mask_sub_acc_T_33; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_2_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_sub_acc_T_34 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_2_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_2_1_8 = atomics_a_mask_sub_sub_1_1_8 | _atomics_a_mask_sub_acc_T_34; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_sub_3_2_8 = atomics_a_mask_sub_sub_1_2_8 & atomics_a_mask_sub_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_sub_acc_T_35 = atomics_a_mask_sub_size_8 & atomics_a_mask_sub_3_2_8; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_sub_3_1_8 = atomics_a_mask_sub_sub_1_1_8 | _atomics_a_mask_sub_acc_T_35; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_size_8 = atomics_a_mask_sizeOH_8[0]; // @[Misc.scala:202:81, :209:26]
wire atomics_a_mask_nbit_8 = ~atomics_a_mask_bit_8; // @[Misc.scala:210:26, :211:20]
wire atomics_a_mask_eq_64 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_64 = atomics_a_mask_size_8 & atomics_a_mask_eq_64; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_64 = atomics_a_mask_sub_0_1_8 | _atomics_a_mask_acc_T_64; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_65 = atomics_a_mask_sub_0_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_65 = atomics_a_mask_size_8 & atomics_a_mask_eq_65; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_65 = atomics_a_mask_sub_0_1_8 | _atomics_a_mask_acc_T_65; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_66 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_66 = atomics_a_mask_size_8 & atomics_a_mask_eq_66; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_66 = atomics_a_mask_sub_1_1_8 | _atomics_a_mask_acc_T_66; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_67 = atomics_a_mask_sub_1_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_67 = atomics_a_mask_size_8 & atomics_a_mask_eq_67; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_67 = atomics_a_mask_sub_1_1_8 | _atomics_a_mask_acc_T_67; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_68 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_68 = atomics_a_mask_size_8 & atomics_a_mask_eq_68; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_68 = atomics_a_mask_sub_2_1_8 | _atomics_a_mask_acc_T_68; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_69 = atomics_a_mask_sub_2_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_69 = atomics_a_mask_size_8 & atomics_a_mask_eq_69; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_69 = atomics_a_mask_sub_2_1_8 | _atomics_a_mask_acc_T_69; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_70 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_nbit_8; // @[Misc.scala:211:20, :214:27]
wire _atomics_a_mask_acc_T_70 = atomics_a_mask_size_8 & atomics_a_mask_eq_70; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_70 = atomics_a_mask_sub_3_1_8 | _atomics_a_mask_acc_T_70; // @[Misc.scala:215:{29,38}]
wire atomics_a_mask_eq_71 = atomics_a_mask_sub_3_2_8 & atomics_a_mask_bit_8; // @[Misc.scala:210:26, :214:27]
wire _atomics_a_mask_acc_T_71 = atomics_a_mask_size_8 & atomics_a_mask_eq_71; // @[Misc.scala:209:26, :214:27, :215:38]
wire atomics_a_mask_acc_71 = atomics_a_mask_sub_3_1_8 | _atomics_a_mask_acc_T_71; // @[Misc.scala:215:{29,38}]
wire [1:0] atomics_a_mask_lo_lo_8 = {atomics_a_mask_acc_65, atomics_a_mask_acc_64}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_lo_hi_8 = {atomics_a_mask_acc_67, atomics_a_mask_acc_66}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_lo_8 = {atomics_a_mask_lo_hi_8, atomics_a_mask_lo_lo_8}; // @[Misc.scala:222:10]
wire [1:0] atomics_a_mask_hi_lo_8 = {atomics_a_mask_acc_69, atomics_a_mask_acc_68}; // @[Misc.scala:215:29, :222:10]
wire [1:0] atomics_a_mask_hi_hi_8 = {atomics_a_mask_acc_71, atomics_a_mask_acc_70}; // @[Misc.scala:215:29, :222:10]
wire [3:0] atomics_a_mask_hi_8 = {atomics_a_mask_hi_hi_8, atomics_a_mask_hi_lo_8}; // @[Misc.scala:222:10]
assign _atomics_a_mask_T_8 = {atomics_a_mask_hi_8, atomics_a_mask_lo_8}; // @[Misc.scala:222:10]
assign atomics_a_8_mask = _atomics_a_mask_T_8; // @[Misc.scala:222:10]
wire [2:0] _GEN_101 = _atomics_T ? 3'h3 : 3'h0; // @[DCache.scala:587:81]
wire [2:0] _atomics_T_1_opcode; // @[DCache.scala:587:81]
assign _atomics_T_1_opcode = _GEN_101; // @[DCache.scala:587:81]
wire [2:0] _atomics_T_1_param; // @[DCache.scala:587:81]
assign _atomics_T_1_param = _GEN_101; // @[DCache.scala:587:81]
wire [3:0] _atomics_T_1_size = _atomics_T ? atomics_a_size : 4'h0; // @[Edges.scala:534:17]
wire [31:0] _atomics_T_1_address = _atomics_T ? atomics_a_address : 32'h0; // @[Edges.scala:534:17]
wire [7:0] _atomics_T_1_mask = _atomics_T ? atomics_a_mask : 8'h0; // @[Edges.scala:534:17]
wire [63:0] _atomics_T_1_data = _atomics_T ? atomics_a_data : 64'h0; // @[Edges.scala:534:17]
wire [2:0] _atomics_T_3_opcode = _atomics_T_2 ? 3'h3 : _atomics_T_1_opcode; // @[DCache.scala:587:81]
wire [2:0] _atomics_T_3_param = _atomics_T_2 ? 3'h0 : _atomics_T_1_param; // @[DCache.scala:587:81]
wire [3:0] _atomics_T_3_size = _atomics_T_2 ? atomics_a_1_size : _atomics_T_1_size; // @[Edges.scala:534:17]
wire [31:0] _atomics_T_3_address = _atomics_T_2 ? atomics_a_1_address : _atomics_T_1_address; // @[Edges.scala:534:17]
wire [7:0] _atomics_T_3_mask = _atomics_T_2 ? atomics_a_1_mask : _atomics_T_1_mask; // @[Edges.scala:534:17]
wire [63:0] _atomics_T_3_data = _atomics_T_2 ? atomics_a_1_data : _atomics_T_1_data; // @[Edges.scala:534:17]
wire [2:0] _atomics_T_5_opcode = _atomics_T_4 ? 3'h3 : _atomics_T_3_opcode; // @[DCache.scala:587:81]
wire [2:0] _atomics_T_5_param = _atomics_T_4 ? 3'h1 : _atomics_T_3_param; // @[DCache.scala:587:81]
wire [3:0] _atomics_T_5_size = _atomics_T_4 ? atomics_a_2_size : _atomics_T_3_size; // @[Edges.scala:534:17]
wire [31:0] _atomics_T_5_address = _atomics_T_4 ? atomics_a_2_address : _atomics_T_3_address; // @[Edges.scala:534:17]
wire [7:0] _atomics_T_5_mask = _atomics_T_4 ? atomics_a_2_mask : _atomics_T_3_mask; // @[Edges.scala:534:17]
wire [63:0] _atomics_T_5_data = _atomics_T_4 ? atomics_a_2_data : _atomics_T_3_data; // @[Edges.scala:534:17]
wire [2:0] _atomics_T_7_opcode = _atomics_T_6 ? 3'h3 : _atomics_T_5_opcode; // @[DCache.scala:587:81]
wire [2:0] _atomics_T_7_param = _atomics_T_6 ? 3'h2 : _atomics_T_5_param; // @[DCache.scala:587:81]
wire [3:0] _atomics_T_7_size = _atomics_T_6 ? atomics_a_3_size : _atomics_T_5_size; // @[Edges.scala:534:17]
wire [31:0] _atomics_T_7_address = _atomics_T_6 ? atomics_a_3_address : _atomics_T_5_address; // @[Edges.scala:534:17]
wire [7:0] _atomics_T_7_mask = _atomics_T_6 ? atomics_a_3_mask : _atomics_T_5_mask; // @[Edges.scala:534:17]
wire [63:0] _atomics_T_7_data = _atomics_T_6 ? atomics_a_3_data : _atomics_T_5_data; // @[Edges.scala:534:17]
wire [2:0] _atomics_T_9_opcode = _atomics_T_8 ? 3'h2 : _atomics_T_7_opcode; // @[DCache.scala:587:81]
wire [2:0] _atomics_T_9_param = _atomics_T_8 ? 3'h4 : _atomics_T_7_param; // @[DCache.scala:587:81]
wire [3:0] _atomics_T_9_size = _atomics_T_8 ? atomics_a_4_size : _atomics_T_7_size; // @[Edges.scala:517:17]
wire [31:0] _atomics_T_9_address = _atomics_T_8 ? atomics_a_4_address : _atomics_T_7_address; // @[Edges.scala:517:17]
wire [7:0] _atomics_T_9_mask = _atomics_T_8 ? atomics_a_4_mask : _atomics_T_7_mask; // @[Edges.scala:517:17]
wire [63:0] _atomics_T_9_data = _atomics_T_8 ? atomics_a_4_data : _atomics_T_7_data; // @[Edges.scala:517:17]
wire [2:0] _atomics_T_11_opcode = _atomics_T_10 ? 3'h2 : _atomics_T_9_opcode; // @[DCache.scala:587:81]
wire [2:0] _atomics_T_11_param = _atomics_T_10 ? 3'h0 : _atomics_T_9_param; // @[DCache.scala:587:81]
wire [3:0] _atomics_T_11_size = _atomics_T_10 ? atomics_a_5_size : _atomics_T_9_size; // @[Edges.scala:517:17]
wire [31:0] _atomics_T_11_address = _atomics_T_10 ? atomics_a_5_address : _atomics_T_9_address; // @[Edges.scala:517:17]
wire [7:0] _atomics_T_11_mask = _atomics_T_10 ? atomics_a_5_mask : _atomics_T_9_mask; // @[Edges.scala:517:17]
wire [63:0] _atomics_T_11_data = _atomics_T_10 ? atomics_a_5_data : _atomics_T_9_data; // @[Edges.scala:517:17]
wire [2:0] _atomics_T_13_opcode = _atomics_T_12 ? 3'h2 : _atomics_T_11_opcode; // @[DCache.scala:587:81]
wire [2:0] _atomics_T_13_param = _atomics_T_12 ? 3'h1 : _atomics_T_11_param; // @[DCache.scala:587:81]
wire [3:0] _atomics_T_13_size = _atomics_T_12 ? atomics_a_6_size : _atomics_T_11_size; // @[Edges.scala:517:17]
wire [31:0] _atomics_T_13_address = _atomics_T_12 ? atomics_a_6_address : _atomics_T_11_address; // @[Edges.scala:517:17]
wire [7:0] _atomics_T_13_mask = _atomics_T_12 ? atomics_a_6_mask : _atomics_T_11_mask; // @[Edges.scala:517:17]
wire [63:0] _atomics_T_13_data = _atomics_T_12 ? atomics_a_6_data : _atomics_T_11_data; // @[Edges.scala:517:17]
wire [2:0] _atomics_T_15_opcode = _atomics_T_14 ? 3'h2 : _atomics_T_13_opcode; // @[DCache.scala:587:81]
wire [2:0] _atomics_T_15_param = _atomics_T_14 ? 3'h2 : _atomics_T_13_param; // @[DCache.scala:587:81]
wire [3:0] _atomics_T_15_size = _atomics_T_14 ? atomics_a_7_size : _atomics_T_13_size; // @[Edges.scala:517:17]
wire [31:0] _atomics_T_15_address = _atomics_T_14 ? atomics_a_7_address : _atomics_T_13_address; // @[Edges.scala:517:17]
wire [7:0] _atomics_T_15_mask = _atomics_T_14 ? atomics_a_7_mask : _atomics_T_13_mask; // @[Edges.scala:517:17]
wire [63:0] _atomics_T_15_data = _atomics_T_14 ? atomics_a_7_data : _atomics_T_13_data; // @[Edges.scala:517:17]
wire [2:0] atomics_opcode = _atomics_T_16 ? 3'h2 : _atomics_T_15_opcode; // @[DCache.scala:587:81]
wire [2:0] atomics_param = _atomics_T_16 ? 3'h3 : _atomics_T_15_param; // @[DCache.scala:587:81]
wire [3:0] atomics_size = _atomics_T_16 ? atomics_a_8_size : _atomics_T_15_size; // @[Edges.scala:517:17]
wire [31:0] atomics_address = _atomics_T_16 ? atomics_a_8_address : _atomics_T_15_address; // @[Edges.scala:517:17]
wire [7:0] atomics_mask = _atomics_T_16 ? atomics_a_8_mask : _atomics_T_15_mask; // @[Edges.scala:517:17]
wire [63:0] atomics_data = _atomics_T_16 ? atomics_a_8_data : _atomics_T_15_data; // @[Edges.scala:517:17]
wire [14:0] _tl_out_a_valid_T_2 = _tl_out_a_valid_T_1[20:6]; // @[DCache.scala:606:{43,62}]
wire _tl_out_a_valid_T_3 = _tl_out_a_valid_T_2 == 15'h0; // @[DCache.scala:582:29, :606:{62,118}]
wire _tl_out_a_valid_T_10 = ~s2_victim_dirty; // @[Misc.scala:38:9]
wire _tl_out_a_valid_T_11 = _tl_out_a_valid_T_10; // @[DCache.scala:607:{88,91}]
wire _tl_out_a_valid_T_12 = _tl_out_a_valid_T_6 & _tl_out_a_valid_T_11; // @[DCache.scala:605:29, :606:127, :607:88]
wire _tl_out_a_valid_T_13 = s2_valid_uncached_pending | _tl_out_a_valid_T_12; // @[DCache.scala:430:64, :604:32, :606:127]
assign _tl_out_a_valid_T_14 = _tl_out_a_valid_T_13; // @[DCache.scala:603:37, :604:32]
assign tl_out_a_valid = _tl_out_a_valid_T_14; // @[DCache.scala:159:22, :603:37]
wire _tl_out_a_bits_T = ~s2_uncached; // @[DCache.scala:424:39, :425:47, :608:24]
wire _tl_out_a_bits_T_1 = ~s2_write; // @[DCache.scala:609:9]
wire _tl_out_a_bits_T_3 = ~s2_read; // @[DCache.scala:611:9]
wire [2:0] _tl_out_a_bits_T_4_opcode = _tl_out_a_bits_T_3 ? 3'h0 : atomics_opcode; // @[DCache.scala:587:81, :611:{8,9}]
wire [2:0] _tl_out_a_bits_T_4_param = _tl_out_a_bits_T_3 ? 3'h0 : atomics_param; // @[DCache.scala:587:81, :611:{8,9}]
wire [3:0] _tl_out_a_bits_T_4_size = _tl_out_a_bits_T_3 ? put_size : atomics_size; // @[Edges.scala:480:17]
wire [31:0] _tl_out_a_bits_T_4_address = _tl_out_a_bits_T_3 ? put_address : atomics_address; // @[Edges.scala:480:17]
wire [7:0] _tl_out_a_bits_T_4_mask = _tl_out_a_bits_T_3 ? put_mask : atomics_mask; // @[Edges.scala:480:17]
wire [63:0] _tl_out_a_bits_T_4_data = _tl_out_a_bits_T_3 ? put_data : atomics_data; // @[Edges.scala:480:17]
wire [2:0] _tl_out_a_bits_T_5_opcode = _tl_out_a_bits_T_2 ? 3'h1 : _tl_out_a_bits_T_4_opcode; // @[DCache.scala:610:{8,20}, :611:8]
wire [2:0] _tl_out_a_bits_T_5_param = _tl_out_a_bits_T_2 ? 3'h0 : _tl_out_a_bits_T_4_param; // @[DCache.scala:610:{8,20}, :611:8]
wire [3:0] _tl_out_a_bits_T_5_size = _tl_out_a_bits_T_2 ? putpartial_size : _tl_out_a_bits_T_4_size; // @[Edges.scala:500:17]
wire [31:0] _tl_out_a_bits_T_5_address = _tl_out_a_bits_T_2 ? putpartial_address : _tl_out_a_bits_T_4_address; // @[Edges.scala:500:17]
wire [7:0] _tl_out_a_bits_T_5_mask = _tl_out_a_bits_T_2 ? putpartial_mask : _tl_out_a_bits_T_4_mask; // @[Edges.scala:500:17]
wire [63:0] _tl_out_a_bits_T_5_data = _tl_out_a_bits_T_2 ? putpartial_data : _tl_out_a_bits_T_4_data; // @[Edges.scala:500:17]
wire [2:0] _tl_out_a_bits_T_6_opcode = _tl_out_a_bits_T_1 ? 3'h4 : _tl_out_a_bits_T_5_opcode; // @[DCache.scala:609:{8,9}, :610:8]
wire [2:0] _tl_out_a_bits_T_6_param = _tl_out_a_bits_T_1 ? 3'h0 : _tl_out_a_bits_T_5_param; // @[DCache.scala:609:{8,9}, :610:8]
wire [3:0] _tl_out_a_bits_T_6_size = _tl_out_a_bits_T_1 ? get_size : _tl_out_a_bits_T_5_size; // @[Edges.scala:460:17]
wire [31:0] _tl_out_a_bits_T_6_address = _tl_out_a_bits_T_1 ? get_address : _tl_out_a_bits_T_5_address; // @[Edges.scala:460:17]
wire [7:0] _tl_out_a_bits_T_6_mask = _tl_out_a_bits_T_1 ? get_mask : _tl_out_a_bits_T_5_mask; // @[Edges.scala:460:17]
wire [63:0] _tl_out_a_bits_T_6_data = _tl_out_a_bits_T_1 ? 64'h0 : _tl_out_a_bits_T_5_data; // @[DCache.scala:609:{8,9}, :610:8]
assign _tl_out_a_bits_T_7_opcode = _tl_out_a_bits_T ? 3'h0 : _tl_out_a_bits_T_6_opcode; // @[DCache.scala:608:{23,24}, :609:8]
assign _tl_out_a_bits_T_7_param = _tl_out_a_bits_T ? 3'h0 : _tl_out_a_bits_T_6_param; // @[DCache.scala:608:{23,24}, :609:8]
assign _tl_out_a_bits_T_7_size = _tl_out_a_bits_T ? 4'h0 : _tl_out_a_bits_T_6_size; // @[DCache.scala:608:{23,24}, :609:8]
assign _tl_out_a_bits_T_7_address = _tl_out_a_bits_T ? 32'h0 : _tl_out_a_bits_T_6_address; // @[DCache.scala:608:{23,24}, :609:8]
assign _tl_out_a_bits_T_7_mask = _tl_out_a_bits_T ? 8'h0 : _tl_out_a_bits_T_6_mask; // @[DCache.scala:608:{23,24}, :609:8]
assign _tl_out_a_bits_T_7_data = _tl_out_a_bits_T ? 64'h0 : _tl_out_a_bits_T_6_data; // @[DCache.scala:608:{23,24}, :609:8]
assign tl_out_a_bits_opcode = _tl_out_a_bits_T_7_opcode; // @[DCache.scala:159:22, :608:23]
assign tl_out_a_bits_param = _tl_out_a_bits_T_7_param; // @[DCache.scala:159:22, :608:23]
assign tl_out_a_bits_size = _tl_out_a_bits_T_7_size; // @[DCache.scala:159:22, :608:23]
assign tl_out_a_bits_address = _tl_out_a_bits_T_7_address; // @[DCache.scala:159:22, :608:23]
assign tl_out_a_bits_mask = _tl_out_a_bits_T_7_mask; // @[DCache.scala:159:22, :608:23]
assign tl_out_a_bits_data = _tl_out_a_bits_T_7_data; // @[DCache.scala:159:22, :608:23]
wire _tl_out_a_bits_user_amba_prot_privileged_T = &s2_req_dprv; // @[DCache.scala:339:19, :617:34]
assign _tl_out_a_bits_user_amba_prot_privileged_T_1 = _tl_out_a_bits_user_amba_prot_privileged_T | s2_pma_cacheable; // @[DCache.scala:343:19, :617:{34,46}]
assign tl_out_a_bits_user_amba_prot_privileged = _tl_out_a_bits_user_amba_prot_privileged_T_1; // @[DCache.scala:159:22, :617:46]
wire _io_cpu_perf_acquire_T = tl_out_a_ready & tl_out_a_valid; // @[Decoupled.scala:51:35]
wire [4:0] _uncachedReqs_0_cmd_T_1 = {_uncachedReqs_0_cmd_T, 4'h1}; // @[DCache.scala:637:{37,49}]
wire [4:0] _uncachedReqs_0_cmd_T_2 = s2_write ? _uncachedReqs_0_cmd_T_1 : 5'h0; // @[DCache.scala:637:{23,37}]
wire _T_90 = nodeOut_d_ready & nodeOut_d_valid; // @[Decoupled.scala:51:35]
wire _io_cpu_replay_next_T; // @[Decoupled.scala:51:35]
assign _io_cpu_replay_next_T = _T_90; // @[Decoupled.scala:51:35]
wire _io_cpu_perf_blocked_near_end_of_refill_T; // @[Decoupled.scala:51:35]
assign _io_cpu_perf_blocked_near_end_of_refill_T = _T_90; // @[Decoupled.scala:51:35]
wire _io_errors_bus_valid_T; // @[Decoupled.scala:51:35]
assign _io_errors_bus_valid_T = _T_90; // @[Decoupled.scala:51:35]
wire [26:0] _r_beats1_decode_T = 27'hFFF << nodeOut_d_bits_size; // @[package.scala:243:71]
wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire r_beats1_opdata = nodeOut_d_bits_opcode[0]; // @[Edges.scala:106:36]
wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] r_counter; // @[Edges.scala:229:27]
wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28]
wire d_first = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire d_last = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_done = d_last & _T_90; // @[Decoupled.scala:51:35]
wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _r_counter_T = d_first ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] d_address_inc = {r_4, 3'h0}; // @[Edges.scala:234:25, :269:29]
wire [1:0] d_opc = nodeOut_d_bits_opcode[1:0]; // @[DCache.scala:656:26]
wire [1:0] data_plaInput = d_opc; // @[pla.scala:77:22]
wire [1:0] data_invInputs = ~data_plaInput; // @[pla.scala:77:22, :78:21]
wire data_invMatrixOutputs; // @[pla.scala:124:31]
wire data_plaOutput; // @[pla.scala:81:23]
wire grantIsUncachedData = data_plaOutput; // @[pla.scala:81:23]
wire data_andMatrixOutputs_andMatrixInput_0 = data_plaInput[0]; // @[pla.scala:77:22, :90:45]
wire data_andMatrixOutputs_andMatrixInput_1 = data_invInputs[1]; // @[pla.scala:78:21, :91:29]
wire [1:0] _data_andMatrixOutputs_T = {data_andMatrixOutputs_andMatrixInput_0, data_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :91:29, :98:53]
wire data_andMatrixOutputs_0_2 = &_data_andMatrixOutputs_T; // @[pla.scala:98:{53,70}]
wire data_orMatrixOutputs = data_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36]
assign data_invMatrixOutputs = data_orMatrixOutputs; // @[pla.scala:114:36, :124:31]
assign data_plaOutput = data_invMatrixOutputs; // @[pla.scala:81:23, :124:31]
wire _tl_d_data_encoded_T_9 = io_ptw_customCSRs_csrs_0_value_0[9]; // @[CustomCSRs.scala:47:65]
wire _tl_d_data_encoded_T_10 = ~_tl_d_data_encoded_T_9; // @[CustomCSRs.scala:47:65]
wire _tl_d_data_encoded_T_11 = nodeOut_d_bits_corrupt & _tl_d_data_encoded_T_10; // @[DCache.scala:663:{77,80}]
wire [15:0] tl_d_data_encoded_lo_lo_1 = {_tl_d_data_encoded_T_15, _tl_d_data_encoded_T_14}; // @[package.scala:45:27, :211:50]
wire [15:0] tl_d_data_encoded_lo_hi_1 = {_tl_d_data_encoded_T_17, _tl_d_data_encoded_T_16}; // @[package.scala:45:27, :211:50]
wire [31:0] tl_d_data_encoded_lo_1 = {tl_d_data_encoded_lo_hi_1, tl_d_data_encoded_lo_lo_1}; // @[package.scala:45:27]
wire [15:0] tl_d_data_encoded_hi_lo_1 = {_tl_d_data_encoded_T_19, _tl_d_data_encoded_T_18}; // @[package.scala:45:27, :211:50]
wire [15:0] tl_d_data_encoded_hi_hi_1 = {_tl_d_data_encoded_T_21, _tl_d_data_encoded_T_20}; // @[package.scala:45:27, :211:50]
wire [31:0] tl_d_data_encoded_hi_1 = {tl_d_data_encoded_hi_hi_1, tl_d_data_encoded_hi_lo_1}; // @[package.scala:45:27]
assign _tl_d_data_encoded_T_22 = {tl_d_data_encoded_hi_1, tl_d_data_encoded_lo_1}; // @[package.scala:45:27]
assign tl_d_data_encoded = _tl_d_data_encoded_T_22; // @[package.scala:45:27]
wire grantIsCached = _grantIsCached_T | _grantIsCached_T_1; // @[package.scala:16:47, :81:59]
reg grantInProgress; // @[DCache.scala:667:32]
wire block_probe_for_ordering = grantInProgress; // @[DCache.scala:667:32, :768:89]
reg [2:0] blockProbeAfterGrantCount; // @[DCache.scala:668:42]
wire [3:0] _blockProbeAfterGrantCount_T = {1'h0, blockProbeAfterGrantCount} - 4'h1; // @[DCache.scala:668:42, :669:99]
wire [2:0] _blockProbeAfterGrantCount_T_1 = _blockProbeAfterGrantCount_T[2:0]; // @[DCache.scala:669:99]
wire _nodeOut_d_ready_T = ~d_first; // @[Edges.scala:231:25]
wire _nodeOut_d_ready_T_1 = _nodeOut_d_ready_T; // @[DCache.scala:671:{41,50}]
wire _nodeOut_d_ready_T_2 = _nodeOut_d_ready_T_1; // @[DCache.scala:671:{50,69}]
wire _nodeOut_d_ready_T_3 = ~grantIsCached | _nodeOut_d_ready_T_2; // @[package.scala:81:59]
wire _GEN_102 = _T_90 & grantIsCached; // @[Decoupled.scala:51:35]
assign replace = _GEN_102 & d_last; // @[Replacement.scala:37:29, :38:11]
wire _GEN_103 = ~_T_90 | grantIsCached | ~grantIsUncachedData; // @[Decoupled.scala:51:35]
assign s1_data_way = _GEN_103 ? 2'h1 : 2'h2; // @[DCache.scala:323:32, :674:24, :675:26, :684:35]
wire [28:0] _s2_req_addr_dontCareBits_T = s1_paddr[31:3]; // @[DCache.scala:298:21, :701:41]
wire [31:0] s2_req_addr_dontCareBits = {_s2_req_addr_dontCareBits_T, 3'h0}; // @[DCache.scala:701:{41,55}]
wire [2:0] _s2_req_addr_T = uncachedResp_addr[2:0]; // @[DCache.scala:238:30, :702:45]
wire [31:0] _s2_req_addr_T_1 = {s2_req_addr_dontCareBits[31:3], s2_req_addr_dontCareBits[2:0] | _s2_req_addr_T}; // @[DCache.scala:701:55, :702:{26,45}]
wire _dataArb_io_in_1_valid_T = nodeOut_d_valid & grantIsRefill; // @[DCache.scala:666:29, :721:44]
wire _dataArb_io_in_1_valid_T_1 = _dataArb_io_in_1_valid_T; // @[DCache.scala:721:{44,61}]
wire _metaArb_io_in_3_valid_T = grantIsCached & d_done; // @[package.scala:81:59]
wire _metaArb_io_in_3_valid_T_1 = ~nodeOut_d_bits_denied; // @[DCache.scala:741:56]
assign _metaArb_io_in_3_valid_T_2 = _metaArb_io_in_3_valid_T & _metaArb_io_in_3_valid_T_1; // @[DCache.scala:741:{43,53,56}]
assign metaArb_io_in_3_valid = _metaArb_io_in_3_valid_T_2; // @[DCache.scala:135:28, :741:53]
assign metaArb_io_in_3_bits_way_en = refill_way[0]; // @[DCache.scala:135:28, :229:23, :743:32]
assign metaArb_io_in_3_bits_idx = _metaArb_io_in_3_bits_idx_T; // @[DCache.scala:135:28, :744:40]
assign _metaArb_io_in_3_bits_addr_T_2 = {_metaArb_io_in_3_bits_addr_T, _metaArb_io_in_3_bits_addr_T_1}; // @[DCache.scala:745:{36,58,80}]
assign metaArb_io_in_3_bits_addr = _metaArb_io_in_3_bits_addr_T_2; // @[DCache.scala:135:28, :745:36]
wire _metaArb_io_in_3_bits_data_c_cat_T_2 = _metaArb_io_in_3_bits_data_c_cat_T | _metaArb_io_in_3_bits_data_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _metaArb_io_in_3_bits_data_c_cat_T_4 = _metaArb_io_in_3_bits_data_c_cat_T_2 | _metaArb_io_in_3_bits_data_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _metaArb_io_in_3_bits_data_c_cat_T_9 = _metaArb_io_in_3_bits_data_c_cat_T_5 | _metaArb_io_in_3_bits_data_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_10 = _metaArb_io_in_3_bits_data_c_cat_T_9 | _metaArb_io_in_3_bits_data_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_11 = _metaArb_io_in_3_bits_data_c_cat_T_10 | _metaArb_io_in_3_bits_data_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_17 = _metaArb_io_in_3_bits_data_c_cat_T_12 | _metaArb_io_in_3_bits_data_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_18 = _metaArb_io_in_3_bits_data_c_cat_T_17 | _metaArb_io_in_3_bits_data_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_19 = _metaArb_io_in_3_bits_data_c_cat_T_18 | _metaArb_io_in_3_bits_data_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_20 = _metaArb_io_in_3_bits_data_c_cat_T_19 | _metaArb_io_in_3_bits_data_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_21 = _metaArb_io_in_3_bits_data_c_cat_T_11 | _metaArb_io_in_3_bits_data_c_cat_T_20; // @[package.scala:81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_22 = _metaArb_io_in_3_bits_data_c_cat_T_4 | _metaArb_io_in_3_bits_data_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _metaArb_io_in_3_bits_data_c_cat_T_25 = _metaArb_io_in_3_bits_data_c_cat_T_23 | _metaArb_io_in_3_bits_data_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _metaArb_io_in_3_bits_data_c_cat_T_27 = _metaArb_io_in_3_bits_data_c_cat_T_25 | _metaArb_io_in_3_bits_data_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _metaArb_io_in_3_bits_data_c_cat_T_32 = _metaArb_io_in_3_bits_data_c_cat_T_28 | _metaArb_io_in_3_bits_data_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_33 = _metaArb_io_in_3_bits_data_c_cat_T_32 | _metaArb_io_in_3_bits_data_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_34 = _metaArb_io_in_3_bits_data_c_cat_T_33 | _metaArb_io_in_3_bits_data_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_40 = _metaArb_io_in_3_bits_data_c_cat_T_35 | _metaArb_io_in_3_bits_data_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_41 = _metaArb_io_in_3_bits_data_c_cat_T_40 | _metaArb_io_in_3_bits_data_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_42 = _metaArb_io_in_3_bits_data_c_cat_T_41 | _metaArb_io_in_3_bits_data_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_43 = _metaArb_io_in_3_bits_data_c_cat_T_42 | _metaArb_io_in_3_bits_data_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_44 = _metaArb_io_in_3_bits_data_c_cat_T_34 | _metaArb_io_in_3_bits_data_c_cat_T_43; // @[package.scala:81:59]
wire _metaArb_io_in_3_bits_data_c_cat_T_45 = _metaArb_io_in_3_bits_data_c_cat_T_27 | _metaArb_io_in_3_bits_data_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _metaArb_io_in_3_bits_data_c_cat_T_47 = _metaArb_io_in_3_bits_data_c_cat_T_45 | _metaArb_io_in_3_bits_data_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _metaArb_io_in_3_bits_data_c_cat_T_49 = _metaArb_io_in_3_bits_data_c_cat_T_47 | _metaArb_io_in_3_bits_data_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] metaArb_io_in_3_bits_data_c = {_metaArb_io_in_3_bits_data_c_cat_T_22, _metaArb_io_in_3_bits_data_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _metaArb_io_in_3_bits_data_T_1 = {metaArb_io_in_3_bits_data_c, nodeOut_d_bits_param}; // @[Metadata.scala:29:18, :84:18]
wire _metaArb_io_in_3_bits_data_T_10 = _metaArb_io_in_3_bits_data_T_1 == 4'h1; // @[Metadata.scala:84:{18,38}]
wire [1:0] _metaArb_io_in_3_bits_data_T_11 = {1'h0, _metaArb_io_in_3_bits_data_T_10}; // @[Metadata.scala:84:38]
wire _metaArb_io_in_3_bits_data_T_12 = _metaArb_io_in_3_bits_data_T_1 == 4'h0; // @[Metadata.scala:84:{18,38}]
wire [1:0] _metaArb_io_in_3_bits_data_T_13 = _metaArb_io_in_3_bits_data_T_12 ? 2'h2 : _metaArb_io_in_3_bits_data_T_11; // @[Metadata.scala:84:38]
wire _metaArb_io_in_3_bits_data_T_14 = _metaArb_io_in_3_bits_data_T_1 == 4'h4; // @[Metadata.scala:84:{18,38}]
wire [1:0] _metaArb_io_in_3_bits_data_T_15 = _metaArb_io_in_3_bits_data_T_14 ? 2'h2 : _metaArb_io_in_3_bits_data_T_13; // @[Metadata.scala:84:38]
wire _metaArb_io_in_3_bits_data_T_16 = _metaArb_io_in_3_bits_data_T_1 == 4'hC; // @[Metadata.scala:84:{18,38}]
wire [1:0] _metaArb_io_in_3_bits_data_T_17 = _metaArb_io_in_3_bits_data_T_16 ? 2'h3 : _metaArb_io_in_3_bits_data_T_15; // @[Metadata.scala:84:38]
wire [1:0] metaArb_io_in_3_bits_data_meta_state = _metaArb_io_in_3_bits_data_T_17; // @[Metadata.scala:84:38, :160:20]
wire [1:0] metaArb_io_in_3_bits_data_meta_1_coh_state = metaArb_io_in_3_bits_data_meta_state; // @[Metadata.scala:160:20]
wire [17:0] metaArb_io_in_3_bits_data_meta_1_tag; // @[HellaCache.scala:305:20]
assign metaArb_io_in_3_bits_data_meta_1_tag = _metaArb_io_in_3_bits_data_T[17:0]; // @[HellaCache.scala:305:20, :306:14]
assign _metaArb_io_in_3_bits_data_T_18 = {metaArb_io_in_3_bits_data_meta_1_coh_state, metaArb_io_in_3_bits_data_meta_1_tag}; // @[HellaCache.scala:305:20]
assign metaArb_io_in_3_bits_data = _metaArb_io_in_3_bits_data_T_18; // @[DCache.scala:135:28, :746:134]
reg blockUncachedGrant; // @[DCache.scala:750:33]
wire _T_100 = grantIsUncachedData & (blockUncachedGrant | s1_valid); // @[Decode.scala:55:116]
assign nodeOut_d_ready = ~(_T_100 | grantIsRefill & ~dataArb_io_in_1_ready) & _nodeOut_d_ready_T_3; // @[DCache.scala:152:28, :666:29, :671:{18,24}, :722:{23,26,51}, :724:20, :752:{31,68}, :753:22]
assign io_cpu_req_ready_0 = _T_100 ? ~(nodeOut_d_valid | ~metaArb_io_in_7_ready | _T_4) & _io_cpu_req_ready_T_4 : ~(~metaArb_io_in_7_ready | _T_4) & _io_cpu_req_ready_T_4; // @[DCache.scala:101:7, :135:28, :195:9, :233:{20,73}, :258:{33,45,64}, :267:{34,53}, :275:{79,98}, :752:{31,68}, :755:29, :756:26]
wire _GEN_104 = _T_100 & nodeOut_d_valid; // @[DCache.scala:721:26, :752:{31,68}, :755:29, :757:32]
assign dataArb_io_in_1_valid = _GEN_104 | _dataArb_io_in_1_valid_T_1; // @[DCache.scala:152:28, :721:{26,61}, :752:68, :755:29, :757:32]
assign dataArb_io_in_1_bits_write = ~_GEN_104 & pstore_drain; // @[DCache.scala:152:28, :516:27, :721:26, :734:27, :752:68, :755:29, :757:32, :758:37]
wire _blockUncachedGrant_T = ~dataArb_io_in_1_ready; // @[DCache.scala:152:28, :722:26, :759:31]
wire _block_probe_for_core_progress_T = |blockProbeAfterGrantCount; // @[DCache.scala:668:42, :669:35, :766:65]
wire block_probe_for_core_progress = _block_probe_for_core_progress_T | lrscValid; // @[DCache.scala:473:29, :766:{65,71}]
wire [14:0] _block_probe_for_pending_release_ack_T_1 = _block_probe_for_pending_release_ack_T[20:6]; // @[DCache.scala:767:{88,107}]
wire _block_probe_for_pending_release_ack_T_2 = _block_probe_for_pending_release_ack_T_1 == 15'h0; // @[DCache.scala:582:29, :767:{107,163}]
wire _metaArb_io_in_6_valid_T = ~block_probe_for_core_progress; // @[DCache.scala:766:71, :769:48]
wire _metaArb_io_in_6_valid_T_1 = _metaArb_io_in_6_valid_T | lrscBackingOff; // @[DCache.scala:474:40, :769:{48,79}]
wire [1:0] _metaArb_io_in_6_bits_addr_T = io_cpu_req_bits_addr_0[33:32]; // @[DCache.scala:101:7, :773:58]
assign _metaArb_io_in_6_bits_addr_T_1 = {_metaArb_io_in_6_bits_addr_T, 32'h0}; // @[DCache.scala:773:{36,58}]
assign metaArb_io_in_6_bits_addr = _metaArb_io_in_6_bits_addr_T_1; // @[DCache.scala:135:28, :773:36]
wire _releaseRejected_T_2; // @[DCache.scala:803:44]
wire releaseRejected; // @[DCache.scala:800:29]
wire _s2_release_data_valid_T = ~releaseRejected; // @[DCache.scala:800:29, :802:64]
reg s2_release_data_valid; // @[DCache.scala:802:38]
assign _releaseRejected_T_2 = s2_release_data_valid; // @[DCache.scala:802:38, :803:44]
wire _tl_out_c_valid_T_3 = s2_release_data_valid; // @[DCache.scala:802:38, :810:44]
assign releaseRejected = _releaseRejected_T_2; // @[DCache.scala:800:29, :803:44]
wire [1:0] _releaseDataBeat_T_1 = {1'h0, s2_release_data_valid}; // @[DCache.scala:802:38, :804:98]
wire [2:0] _releaseDataBeat_T_2 = {1'h0, _releaseDataBeat_T_1}; // @[DCache.scala:804:{93,98}]
wire [1:0] _releaseDataBeat_T_3 = _releaseDataBeat_T_2[1:0]; // @[DCache.scala:804:93]
wire [1:0] _releaseDataBeat_T_4 = releaseRejected ? 2'h0 : _releaseDataBeat_T_3; // @[DCache.scala:800:29, :804:{48,93}]
wire [10:0] _releaseDataBeat_T_5 = {9'h0, _releaseDataBeat_T_4}; // @[DCache.scala:804:{43,48}]
wire [9:0] releaseDataBeat = _releaseDataBeat_T_5[9:0]; // @[DCache.scala:804:43]
assign _tl_out_c_valid_T_6 = _tl_out_c_valid_T_3; // @[DCache.scala:810:{44,117}]
assign tl_out_c_valid = _tl_out_c_valid_T_6; // @[Bundles.scala:265:61]
wire [1:0] metaArb_io_in_4_bits_data_meta_coh_state = newCoh_state; // @[HellaCache.scala:305:20]
wire _dataArb_io_in_2_valid_T = releaseDataBeat < 10'h8; // @[DCache.scala:804:43, :900:60]
wire [2:0] _dataArb_io_in_2_bits_addr_T_2 = releaseDataBeat[2:0]; // @[DCache.scala:804:43, :903:90]
wire [5:0] _dataArb_io_in_2_bits_addr_T_3 = {_dataArb_io_in_2_bits_addr_T_2, 3'h0}; // @[DCache.scala:903:{90,117}]
assign _dataArb_io_in_2_bits_addr_T_4 = {8'h0, _dataArb_io_in_2_bits_addr_T_3}; // @[DCache.scala:903:{72,117}]
assign dataArb_io_in_2_bits_addr = _dataArb_io_in_2_bits_addr_T_4; // @[DCache.scala:152:28, :903:72]
assign _metaArb_io_in_4_bits_addr_T_2 = {_metaArb_io_in_4_bits_addr_T, 14'h0}; // @[DCache.scala:912:{36,58}]
assign metaArb_io_in_4_bits_addr = _metaArb_io_in_4_bits_addr_T_2; // @[DCache.scala:135:28, :912:36]
assign _metaArb_io_in_4_bits_data_T_1 = {metaArb_io_in_4_bits_data_meta_coh_state, 18'h0}; // @[HellaCache.scala:305:20]
assign metaArb_io_in_4_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97]
assign metaArb_io_in_5_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97]
assign metaArb_io_in_6_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97]
assign metaArb_io_in_7_bits_data = _metaArb_io_in_4_bits_data_T_1; // @[DCache.scala:135:28, :913:97]
wire _io_cpu_s2_uncached_T = ~s2_hit; // @[Misc.scala:35:9]
assign _io_cpu_s2_uncached_T_1 = s2_uncached & _io_cpu_s2_uncached_T; // @[DCache.scala:424:39, :920:{37,40}]
assign io_cpu_s2_uncached_0 = _io_cpu_s2_uncached_T_1; // @[DCache.scala:101:7, :920:37]
wire _io_cpu_ordered_T = ~s1_req_no_xcpt; // @[DCache.scala:196:25, :929:35]
wire _io_cpu_ordered_T_1 = s1_valid & _io_cpu_ordered_T; // @[DCache.scala:182:25, :929:{32,35}]
wire _io_cpu_ordered_T_2 = ~s2_req_no_xcpt; // @[DCache.scala:339:19, :929:72]
wire _io_cpu_ordered_T_3 = s2_valid & _io_cpu_ordered_T_2; // @[DCache.scala:331:25, :929:{69,72}]
wire _io_cpu_ordered_T_4 = _io_cpu_ordered_T_1 | _io_cpu_ordered_T_3; // @[DCache.scala:929:{32,57,69}]
wire _io_cpu_ordered_T_5 = _io_cpu_ordered_T_4 | cached_grant_wait; // @[DCache.scala:223:34, :929:{57,94}]
wire _io_cpu_ordered_T_7 = _io_cpu_ordered_T_5 | _io_cpu_ordered_T_6; // @[DCache.scala:929:{94,115,142}]
assign _io_cpu_ordered_T_8 = ~_io_cpu_ordered_T_7; // @[DCache.scala:929:{21,115}]
assign io_cpu_ordered_0 = _io_cpu_ordered_T_8; // @[DCache.scala:101:7, :929:21]
wire _io_cpu_store_pending_T_2 = _io_cpu_store_pending_T | _io_cpu_store_pending_T_1; // @[Consts.scala:90:{32,42,49}]
wire _io_cpu_store_pending_T_4 = _io_cpu_store_pending_T_2 | _io_cpu_store_pending_T_3; // @[Consts.scala:90:{42,59,66}]
wire _io_cpu_store_pending_T_9 = _io_cpu_store_pending_T_5 | _io_cpu_store_pending_T_6; // @[package.scala:16:47, :81:59]
wire _io_cpu_store_pending_T_10 = _io_cpu_store_pending_T_9 | _io_cpu_store_pending_T_7; // @[package.scala:16:47, :81:59]
wire _io_cpu_store_pending_T_11 = _io_cpu_store_pending_T_10 | _io_cpu_store_pending_T_8; // @[package.scala:16:47, :81:59]
wire _io_cpu_store_pending_T_17 = _io_cpu_store_pending_T_12 | _io_cpu_store_pending_T_13; // @[package.scala:16:47, :81:59]
wire _io_cpu_store_pending_T_18 = _io_cpu_store_pending_T_17 | _io_cpu_store_pending_T_14; // @[package.scala:16:47, :81:59]
wire _io_cpu_store_pending_T_19 = _io_cpu_store_pending_T_18 | _io_cpu_store_pending_T_15; // @[package.scala:16:47, :81:59]
wire _io_cpu_store_pending_T_20 = _io_cpu_store_pending_T_19 | _io_cpu_store_pending_T_16; // @[package.scala:16:47, :81:59]
wire _io_cpu_store_pending_T_21 = _io_cpu_store_pending_T_11 | _io_cpu_store_pending_T_20; // @[package.scala:81:59]
wire _io_cpu_store_pending_T_22 = _io_cpu_store_pending_T_4 | _io_cpu_store_pending_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _io_cpu_store_pending_T_23 = cached_grant_wait & _io_cpu_store_pending_T_22; // @[DCache.scala:223:34, :930:46]
assign _io_cpu_store_pending_T_25 = _io_cpu_store_pending_T_23 | _io_cpu_store_pending_T_24; // @[DCache.scala:930:{46,70,97}]
assign io_cpu_store_pending_0 = _io_cpu_store_pending_T_25; // @[DCache.scala:101:7, :930:70]
wire _s1_xcpt_valid_T = ~s1_req_no_xcpt; // @[DCache.scala:196:25, :929:35, :932:43]
wire _s1_xcpt_valid_T_1 = _tlb_io_req_valid_T_3 & _s1_xcpt_valid_T; // @[DCache.scala:273:40, :932:{40,43}]
wire _s1_xcpt_valid_T_2 = ~s1_nack; // @[DCache.scala:185:28, :187:41, :932:68]
wire s1_xcpt_valid = _s1_xcpt_valid_T_1 & _s1_xcpt_valid_T_2; // @[DCache.scala:932:{40,65,68}]
reg io_cpu_s2_xcpt_REG; // @[DCache.scala:933:32]
wire [31:0] _io_cpu_s2_xcpt_T_paddr = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_paddr : 32'h0; // @[DCache.scala:342:24, :933:{24,32}]
wire [33:0] _io_cpu_s2_xcpt_T_gpa = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_gpa : 34'h0; // @[DCache.scala:342:24, :933:{24,32}]
assign _io_cpu_s2_xcpt_T_pf_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_ld; // @[DCache.scala:342:24, :933:{24,32}]
assign _io_cpu_s2_xcpt_T_pf_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_st; // @[DCache.scala:342:24, :933:{24,32}]
wire _io_cpu_s2_xcpt_T_pf_inst = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_pf_inst; // @[DCache.scala:342:24, :933:{24,32}]
assign _io_cpu_s2_xcpt_T_ae_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_ld; // @[DCache.scala:342:24, :933:{24,32}]
assign _io_cpu_s2_xcpt_T_ae_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_st; // @[DCache.scala:342:24, :933:{24,32}]
wire _io_cpu_s2_xcpt_T_ae_inst = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ae_inst; // @[DCache.scala:342:24, :933:{24,32}]
assign _io_cpu_s2_xcpt_T_ma_ld = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ma_ld; // @[DCache.scala:342:24, :933:{24,32}]
assign _io_cpu_s2_xcpt_T_ma_st = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_ma_st; // @[DCache.scala:342:24, :933:{24,32}]
wire _io_cpu_s2_xcpt_T_cacheable = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_cacheable; // @[DCache.scala:342:24, :933:{24,32}]
wire _io_cpu_s2_xcpt_T_must_alloc = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_must_alloc; // @[DCache.scala:342:24, :933:{24,32}]
wire _io_cpu_s2_xcpt_T_prefetchable = io_cpu_s2_xcpt_REG & s2_tlb_xcpt_prefetchable; // @[DCache.scala:342:24, :933:{24,32}]
wire [1:0] _io_cpu_s2_xcpt_T_size = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_size : 2'h0; // @[DCache.scala:342:24, :933:{24,32}]
wire [4:0] _io_cpu_s2_xcpt_T_cmd = io_cpu_s2_xcpt_REG ? s2_tlb_xcpt_cmd : 5'h0; // @[DCache.scala:342:24, :933:{24,32}]
assign io_cpu_s2_xcpt_pf_ld_0 = _io_cpu_s2_xcpt_T_pf_ld; // @[DCache.scala:101:7, :933:24]
assign io_cpu_s2_xcpt_pf_st_0 = _io_cpu_s2_xcpt_T_pf_st; // @[DCache.scala:101:7, :933:24]
assign io_cpu_s2_xcpt_ae_ld_0 = _io_cpu_s2_xcpt_T_ae_ld; // @[DCache.scala:101:7, :933:24]
assign io_cpu_s2_xcpt_ae_st_0 = _io_cpu_s2_xcpt_T_ae_st; // @[DCache.scala:101:7, :933:24]
assign io_cpu_s2_xcpt_ma_ld_0 = _io_cpu_s2_xcpt_T_ma_ld; // @[DCache.scala:101:7, :933:24]
assign io_cpu_s2_xcpt_ma_st_0 = _io_cpu_s2_xcpt_T_ma_st; // @[DCache.scala:101:7, :933:24]
reg [63:0] s2_uncached_data_word; // @[DCache.scala:947:40]
reg doUncachedResp; // @[DCache.scala:948:31]
assign io_cpu_resp_bits_replay_0 = doUncachedResp; // @[DCache.scala:101:7, :948:31]
wire _io_cpu_resp_valid_T = s2_valid_hit_pre_data_ecc | doUncachedResp; // @[DCache.scala:420:69, :948:31, :949:51]
assign _io_cpu_resp_valid_T_2 = _io_cpu_resp_valid_T; // @[DCache.scala:949:{51,70}]
assign io_cpu_resp_valid_0 = _io_cpu_resp_valid_T_2; // @[DCache.scala:101:7, :949:70]
wire _io_cpu_replay_next_T_1 = _io_cpu_replay_next_T & grantIsUncachedData; // @[Decoupled.scala:51:35]
assign _io_cpu_replay_next_T_3 = _io_cpu_replay_next_T_1; // @[DCache.scala:950:{39,62}]
assign io_cpu_replay_next_0 = _io_cpu_replay_next_T_3; // @[DCache.scala:101:7, :950:62] |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_60 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_60( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_376 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_376( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module PE_459 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_203
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<32>, clock
reg c2 : SInt<32>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node c1_sign = bits(io.in_d, 19, 19)
node c1_lo_lo_hi = cat(c1_sign, c1_sign)
node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign)
node c1_lo_hi_hi = cat(c1_sign, c1_sign)
node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign)
node c1_lo = cat(c1_lo_hi, c1_lo_lo)
node c1_hi_lo_hi = cat(c1_sign, c1_sign)
node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign)
node c1_hi_hi_hi = cat(c1_sign, c1_sign)
node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign)
node c1_hi = cat(c1_hi_hi, c1_hi_lo)
node _c1_T = cat(c1_hi, c1_lo)
node c1_lo_1 = asUInt(io.in_d)
node _c1_T_1 = cat(_c1_T, c1_lo_1)
wire _c1_WIRE : SInt<32>
node _c1_T_2 = asSInt(_c1_T_1)
connect _c1_WIRE, _c1_T_2
connect c1, _c1_WIRE
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node c2_sign = bits(io.in_d, 19, 19)
node c2_lo_lo_hi = cat(c2_sign, c2_sign)
node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign)
node c2_lo_hi_hi = cat(c2_sign, c2_sign)
node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign)
node c2_lo = cat(c2_lo_hi, c2_lo_lo)
node c2_hi_lo_hi = cat(c2_sign, c2_sign)
node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign)
node c2_hi_hi_hi = cat(c2_sign, c2_sign)
node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign)
node c2_hi = cat(c2_hi_hi, c2_hi_lo)
node _c2_T = cat(c2_hi, c2_lo)
node c2_lo_1 = asUInt(io.in_d)
node _c2_T_1 = cat(_c2_T, c2_lo_1)
wire _c2_WIRE : SInt<32>
node _c2_T_2 = asSInt(_c2_T_1)
connect _c2_WIRE, _c2_T_2
connect c2, _c2_WIRE
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h1), _T_4)
node _T_6 = or(UInt<1>(0h0), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_459( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_203 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_125 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_213
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_125( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_213 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_72 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h2f))
node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[20]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_27
connect _source_ok_WIRE[8], _source_ok_T_28
connect _source_ok_WIRE[9], _source_ok_T_29
connect _source_ok_WIRE[10], _source_ok_T_30
connect _source_ok_WIRE[11], _source_ok_T_31
connect _source_ok_WIRE[12], _source_ok_T_32
connect _source_ok_WIRE[13], _source_ok_T_33
connect _source_ok_WIRE[14], _source_ok_T_34
connect _source_ok_WIRE[15], _source_ok_T_35
connect _source_ok_WIRE[16], _source_ok_T_36
connect _source_ok_WIRE[17], _source_ok_T_37
connect _source_ok_WIRE[18], _source_ok_T_38
connect _source_ok_WIRE[19], _source_ok_T_39
node _source_ok_T_40 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[2])
node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[3])
node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[4])
node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[5])
node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[6])
node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[7])
node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[8])
node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[9])
node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[10])
node _source_ok_T_50 = or(_source_ok_T_49, _source_ok_WIRE[11])
node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[12])
node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[13])
node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[14])
node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[15])
node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE[16])
node _source_ok_T_56 = or(_source_ok_T_55, _source_ok_WIRE[17])
node _source_ok_T_57 = or(_source_ok_T_56, _source_ok_WIRE[18])
node source_ok = or(_source_ok_T_57, _source_ok_WIRE[19])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_83 = cvt(_T_82)
node _T_84 = and(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = asSInt(_T_84)
node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = or(_T_81, _T_86)
node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_89 = eq(_T_88, UInt<1>(0h0))
node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<1>(0h0)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_89, _T_94)
node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h2f))
node _T_97 = eq(_T_96, UInt<1>(0h0))
node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_99 = cvt(_T_98)
node _T_100 = and(_T_99, asSInt(UInt<1>(0h0)))
node _T_101 = asSInt(_T_100)
node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0)))
node _T_103 = or(_T_97, _T_102)
node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_105 = eq(_T_104, UInt<1>(0h0))
node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_107 = cvt(_T_106)
node _T_108 = and(_T_107, asSInt(UInt<1>(0h0)))
node _T_109 = asSInt(_T_108)
node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = or(_T_105, _T_110)
node _T_112 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_113 = eq(_T_112, UInt<1>(0h0))
node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_115 = cvt(_T_114)
node _T_116 = and(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = asSInt(_T_116)
node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0)))
node _T_119 = or(_T_113, _T_118)
node _T_120 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_123 = cvt(_T_122)
node _T_124 = and(_T_123, asSInt(UInt<1>(0h0)))
node _T_125 = asSInt(_T_124)
node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0)))
node _T_127 = or(_T_121, _T_126)
node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_129 = eq(_T_128, UInt<1>(0h0))
node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_131 = cvt(_T_130)
node _T_132 = and(_T_131, asSInt(UInt<1>(0h0)))
node _T_133 = asSInt(_T_132)
node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0)))
node _T_135 = or(_T_129, _T_134)
node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_137 = eq(_T_136, UInt<1>(0h0))
node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_139 = cvt(_T_138)
node _T_140 = and(_T_139, asSInt(UInt<1>(0h0)))
node _T_141 = asSInt(_T_140)
node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0)))
node _T_143 = or(_T_137, _T_142)
node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_145 = eq(_T_144, UInt<1>(0h0))
node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_147 = cvt(_T_146)
node _T_148 = and(_T_147, asSInt(UInt<1>(0h0)))
node _T_149 = asSInt(_T_148)
node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0)))
node _T_151 = or(_T_145, _T_150)
node _T_152 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_155 = cvt(_T_154)
node _T_156 = and(_T_155, asSInt(UInt<1>(0h0)))
node _T_157 = asSInt(_T_156)
node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0)))
node _T_159 = or(_T_153, _T_158)
node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_161 = eq(_T_160, UInt<1>(0h0))
node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_163 = cvt(_T_162)
node _T_164 = and(_T_163, asSInt(UInt<1>(0h0)))
node _T_165 = asSInt(_T_164)
node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0)))
node _T_167 = or(_T_161, _T_166)
node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_169 = eq(_T_168, UInt<1>(0h0))
node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_171 = cvt(_T_170)
node _T_172 = and(_T_171, asSInt(UInt<1>(0h0)))
node _T_173 = asSInt(_T_172)
node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0)))
node _T_175 = or(_T_169, _T_174)
node _T_176 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_177 = eq(_T_176, UInt<1>(0h0))
node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_179 = cvt(_T_178)
node _T_180 = and(_T_179, asSInt(UInt<1>(0h0)))
node _T_181 = asSInt(_T_180)
node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0)))
node _T_183 = or(_T_177, _T_182)
node _T_184 = and(_T_11, _T_24)
node _T_185 = and(_T_184, _T_37)
node _T_186 = and(_T_185, _T_50)
node _T_187 = and(_T_186, _T_63)
node _T_188 = and(_T_187, _T_71)
node _T_189 = and(_T_188, _T_79)
node _T_190 = and(_T_189, _T_87)
node _T_191 = and(_T_190, _T_95)
node _T_192 = and(_T_191, _T_103)
node _T_193 = and(_T_192, _T_111)
node _T_194 = and(_T_193, _T_119)
node _T_195 = and(_T_194, _T_127)
node _T_196 = and(_T_195, _T_135)
node _T_197 = and(_T_196, _T_143)
node _T_198 = and(_T_197, _T_151)
node _T_199 = and(_T_198, _T_159)
node _T_200 = and(_T_199, _T_167)
node _T_201 = and(_T_200, _T_175)
node _T_202 = and(_T_201, _T_183)
node _T_203 = asUInt(reset)
node _T_204 = eq(_T_203, UInt<1>(0h0))
when _T_204 :
node _T_205 = eq(_T_202, UInt<1>(0h0))
when _T_205 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_202, UInt<1>(0h1), "") : assert_1
node _T_206 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_206 :
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_209 = and(_T_207, _T_208)
node _T_210 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_211 = shr(io.in.a.bits.source, 2)
node _T_212 = eq(_T_211, UInt<1>(0h0))
node _T_213 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_214 = and(_T_212, _T_213)
node _T_215 = leq(uncommonBits_4, UInt<2>(0h3))
node _T_216 = and(_T_214, _T_215)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_217 = shr(io.in.a.bits.source, 2)
node _T_218 = eq(_T_217, UInt<1>(0h1))
node _T_219 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_220 = and(_T_218, _T_219)
node _T_221 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_222 = and(_T_220, _T_221)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_223 = shr(io.in.a.bits.source, 2)
node _T_224 = eq(_T_223, UInt<2>(0h2))
node _T_225 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_226 = and(_T_224, _T_225)
node _T_227 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_228 = and(_T_226, _T_227)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_229 = shr(io.in.a.bits.source, 2)
node _T_230 = eq(_T_229, UInt<2>(0h3))
node _T_231 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_232 = and(_T_230, _T_231)
node _T_233 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_234 = and(_T_232, _T_233)
node _T_235 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_236 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_237 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_238 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_239 = eq(io.in.a.bits.source, UInt<6>(0h2f))
node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_241 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_242 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_243 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_244 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_245 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_246 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_247 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_249 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_250 = or(_T_210, _T_216)
node _T_251 = or(_T_250, _T_222)
node _T_252 = or(_T_251, _T_228)
node _T_253 = or(_T_252, _T_234)
node _T_254 = or(_T_253, _T_235)
node _T_255 = or(_T_254, _T_236)
node _T_256 = or(_T_255, _T_237)
node _T_257 = or(_T_256, _T_238)
node _T_258 = or(_T_257, _T_239)
node _T_259 = or(_T_258, _T_240)
node _T_260 = or(_T_259, _T_241)
node _T_261 = or(_T_260, _T_242)
node _T_262 = or(_T_261, _T_243)
node _T_263 = or(_T_262, _T_244)
node _T_264 = or(_T_263, _T_245)
node _T_265 = or(_T_264, _T_246)
node _T_266 = or(_T_265, _T_247)
node _T_267 = or(_T_266, _T_248)
node _T_268 = or(_T_267, _T_249)
node _T_269 = and(_T_209, _T_268)
node _T_270 = or(UInt<1>(0h0), _T_269)
node _T_271 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_272 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_273 = cvt(_T_272)
node _T_274 = and(_T_273, asSInt(UInt<13>(0h1000)))
node _T_275 = asSInt(_T_274)
node _T_276 = eq(_T_275, asSInt(UInt<1>(0h0)))
node _T_277 = and(_T_271, _T_276)
node _T_278 = or(UInt<1>(0h0), _T_277)
node _T_279 = and(_T_270, _T_278)
node _T_280 = asUInt(reset)
node _T_281 = eq(_T_280, UInt<1>(0h0))
when _T_281 :
node _T_282 = eq(_T_279, UInt<1>(0h0))
when _T_282 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_279, UInt<1>(0h1), "") : assert_2
node _T_283 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_284 = shr(io.in.a.bits.source, 2)
node _T_285 = eq(_T_284, UInt<1>(0h0))
node _T_286 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_287 = and(_T_285, _T_286)
node _T_288 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_289 = and(_T_287, _T_288)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_290 = shr(io.in.a.bits.source, 2)
node _T_291 = eq(_T_290, UInt<1>(0h1))
node _T_292 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_293 = and(_T_291, _T_292)
node _T_294 = leq(uncommonBits_9, UInt<2>(0h3))
node _T_295 = and(_T_293, _T_294)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_296 = shr(io.in.a.bits.source, 2)
node _T_297 = eq(_T_296, UInt<2>(0h2))
node _T_298 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_299 = and(_T_297, _T_298)
node _T_300 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_301 = and(_T_299, _T_300)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_302 = shr(io.in.a.bits.source, 2)
node _T_303 = eq(_T_302, UInt<2>(0h3))
node _T_304 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_305 = and(_T_303, _T_304)
node _T_306 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_307 = and(_T_305, _T_306)
node _T_308 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_309 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_310 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_311 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_312 = eq(io.in.a.bits.source, UInt<6>(0h2f))
node _T_313 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_314 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_315 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_316 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_317 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_318 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_319 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_320 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_321 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_322 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE : UInt<1>[20]
connect _WIRE[0], _T_283
connect _WIRE[1], _T_289
connect _WIRE[2], _T_295
connect _WIRE[3], _T_301
connect _WIRE[4], _T_307
connect _WIRE[5], _T_308
connect _WIRE[6], _T_309
connect _WIRE[7], _T_310
connect _WIRE[8], _T_311
connect _WIRE[9], _T_312
connect _WIRE[10], _T_313
connect _WIRE[11], _T_314
connect _WIRE[12], _T_315
connect _WIRE[13], _T_316
connect _WIRE[14], _T_317
connect _WIRE[15], _T_318
connect _WIRE[16], _T_319
connect _WIRE[17], _T_320
connect _WIRE[18], _T_321
connect _WIRE[19], _T_322
node _T_323 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_324 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_325 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_326 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_327 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_328 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_329 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_331 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_332 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_333 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_334 = mux(_WIRE[5], _T_323, UInt<1>(0h0))
node _T_335 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_336 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_337 = mux(_WIRE[8], _T_324, UInt<1>(0h0))
node _T_338 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_339 = mux(_WIRE[10], _T_325, UInt<1>(0h0))
node _T_340 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0))
node _T_341 = mux(_WIRE[12], _T_326, UInt<1>(0h0))
node _T_342 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_343 = mux(_WIRE[14], _T_327, UInt<1>(0h0))
node _T_344 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_345 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_346 = mux(_WIRE[17], _T_328, UInt<1>(0h0))
node _T_347 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0))
node _T_348 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0))
node _T_349 = or(_T_329, _T_330)
node _T_350 = or(_T_349, _T_331)
node _T_351 = or(_T_350, _T_332)
node _T_352 = or(_T_351, _T_333)
node _T_353 = or(_T_352, _T_334)
node _T_354 = or(_T_353, _T_335)
node _T_355 = or(_T_354, _T_336)
node _T_356 = or(_T_355, _T_337)
node _T_357 = or(_T_356, _T_338)
node _T_358 = or(_T_357, _T_339)
node _T_359 = or(_T_358, _T_340)
node _T_360 = or(_T_359, _T_341)
node _T_361 = or(_T_360, _T_342)
node _T_362 = or(_T_361, _T_343)
node _T_363 = or(_T_362, _T_344)
node _T_364 = or(_T_363, _T_345)
node _T_365 = or(_T_364, _T_346)
node _T_366 = or(_T_365, _T_347)
node _T_367 = or(_T_366, _T_348)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_367
node _T_368 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_369 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_370 = and(_T_368, _T_369)
node _T_371 = or(UInt<1>(0h0), _T_370)
node _T_372 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_373 = cvt(_T_372)
node _T_374 = and(_T_373, asSInt(UInt<13>(0h1000)))
node _T_375 = asSInt(_T_374)
node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0)))
node _T_377 = and(_T_371, _T_376)
node _T_378 = or(UInt<1>(0h0), _T_377)
node _T_379 = and(_WIRE_1, _T_378)
node _T_380 = asUInt(reset)
node _T_381 = eq(_T_380, UInt<1>(0h0))
when _T_381 :
node _T_382 = eq(_T_379, UInt<1>(0h0))
when _T_382 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_379, UInt<1>(0h1), "") : assert_3
node _T_383 = asUInt(reset)
node _T_384 = eq(_T_383, UInt<1>(0h0))
when _T_384 :
node _T_385 = eq(source_ok, UInt<1>(0h0))
when _T_385 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_386 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_387 = asUInt(reset)
node _T_388 = eq(_T_387, UInt<1>(0h0))
when _T_388 :
node _T_389 = eq(_T_386, UInt<1>(0h0))
when _T_389 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_386, UInt<1>(0h1), "") : assert_5
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(is_aligned, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_393 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_393, UInt<1>(0h1), "") : assert_7
node _T_397 = not(io.in.a.bits.mask)
node _T_398 = eq(_T_397, UInt<1>(0h0))
node _T_399 = asUInt(reset)
node _T_400 = eq(_T_399, UInt<1>(0h0))
when _T_400 :
node _T_401 = eq(_T_398, UInt<1>(0h0))
when _T_401 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_398, UInt<1>(0h1), "") : assert_8
node _T_402 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_403 = asUInt(reset)
node _T_404 = eq(_T_403, UInt<1>(0h0))
when _T_404 :
node _T_405 = eq(_T_402, UInt<1>(0h0))
when _T_405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_402, UInt<1>(0h1), "") : assert_9
node _T_406 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_406 :
node _T_407 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_408 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_409 = and(_T_407, _T_408)
node _T_410 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_411 = shr(io.in.a.bits.source, 2)
node _T_412 = eq(_T_411, UInt<1>(0h0))
node _T_413 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_414 = and(_T_412, _T_413)
node _T_415 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_416 = and(_T_414, _T_415)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_417 = shr(io.in.a.bits.source, 2)
node _T_418 = eq(_T_417, UInt<1>(0h1))
node _T_419 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_420 = and(_T_418, _T_419)
node _T_421 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_422 = and(_T_420, _T_421)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_423 = shr(io.in.a.bits.source, 2)
node _T_424 = eq(_T_423, UInt<2>(0h2))
node _T_425 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_426 = and(_T_424, _T_425)
node _T_427 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_428 = and(_T_426, _T_427)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_429 = shr(io.in.a.bits.source, 2)
node _T_430 = eq(_T_429, UInt<2>(0h3))
node _T_431 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_432 = and(_T_430, _T_431)
node _T_433 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_434 = and(_T_432, _T_433)
node _T_435 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_436 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_437 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_438 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_439 = eq(io.in.a.bits.source, UInt<6>(0h2f))
node _T_440 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_441 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_442 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_443 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_444 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_445 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_446 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_447 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_448 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_449 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_450 = or(_T_410, _T_416)
node _T_451 = or(_T_450, _T_422)
node _T_452 = or(_T_451, _T_428)
node _T_453 = or(_T_452, _T_434)
node _T_454 = or(_T_453, _T_435)
node _T_455 = or(_T_454, _T_436)
node _T_456 = or(_T_455, _T_437)
node _T_457 = or(_T_456, _T_438)
node _T_458 = or(_T_457, _T_439)
node _T_459 = or(_T_458, _T_440)
node _T_460 = or(_T_459, _T_441)
node _T_461 = or(_T_460, _T_442)
node _T_462 = or(_T_461, _T_443)
node _T_463 = or(_T_462, _T_444)
node _T_464 = or(_T_463, _T_445)
node _T_465 = or(_T_464, _T_446)
node _T_466 = or(_T_465, _T_447)
node _T_467 = or(_T_466, _T_448)
node _T_468 = or(_T_467, _T_449)
node _T_469 = and(_T_409, _T_468)
node _T_470 = or(UInt<1>(0h0), _T_469)
node _T_471 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_472 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_473 = cvt(_T_472)
node _T_474 = and(_T_473, asSInt(UInt<13>(0h1000)))
node _T_475 = asSInt(_T_474)
node _T_476 = eq(_T_475, asSInt(UInt<1>(0h0)))
node _T_477 = and(_T_471, _T_476)
node _T_478 = or(UInt<1>(0h0), _T_477)
node _T_479 = and(_T_470, _T_478)
node _T_480 = asUInt(reset)
node _T_481 = eq(_T_480, UInt<1>(0h0))
when _T_481 :
node _T_482 = eq(_T_479, UInt<1>(0h0))
when _T_482 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_479, UInt<1>(0h1), "") : assert_10
node _T_483 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_484 = shr(io.in.a.bits.source, 2)
node _T_485 = eq(_T_484, UInt<1>(0h0))
node _T_486 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_487 = and(_T_485, _T_486)
node _T_488 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_489 = and(_T_487, _T_488)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_490 = shr(io.in.a.bits.source, 2)
node _T_491 = eq(_T_490, UInt<1>(0h1))
node _T_492 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_493 = and(_T_491, _T_492)
node _T_494 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_495 = and(_T_493, _T_494)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_496 = shr(io.in.a.bits.source, 2)
node _T_497 = eq(_T_496, UInt<2>(0h2))
node _T_498 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_499 = and(_T_497, _T_498)
node _T_500 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_501 = and(_T_499, _T_500)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_502 = shr(io.in.a.bits.source, 2)
node _T_503 = eq(_T_502, UInt<2>(0h3))
node _T_504 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_505 = and(_T_503, _T_504)
node _T_506 = leq(uncommonBits_19, UInt<2>(0h3))
node _T_507 = and(_T_505, _T_506)
node _T_508 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_509 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_510 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_511 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_512 = eq(io.in.a.bits.source, UInt<6>(0h2f))
node _T_513 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_514 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_515 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_516 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_517 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_518 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_519 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_520 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_521 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_522 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE_2 : UInt<1>[20]
connect _WIRE_2[0], _T_483
connect _WIRE_2[1], _T_489
connect _WIRE_2[2], _T_495
connect _WIRE_2[3], _T_501
connect _WIRE_2[4], _T_507
connect _WIRE_2[5], _T_508
connect _WIRE_2[6], _T_509
connect _WIRE_2[7], _T_510
connect _WIRE_2[8], _T_511
connect _WIRE_2[9], _T_512
connect _WIRE_2[10], _T_513
connect _WIRE_2[11], _T_514
connect _WIRE_2[12], _T_515
connect _WIRE_2[13], _T_516
connect _WIRE_2[14], _T_517
connect _WIRE_2[15], _T_518
connect _WIRE_2[16], _T_519
connect _WIRE_2[17], _T_520
connect _WIRE_2[18], _T_521
connect _WIRE_2[19], _T_522
node _T_523 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_524 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_525 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_526 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_527 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_528 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_529 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_530 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_531 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_532 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_533 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_534 = mux(_WIRE_2[5], _T_523, UInt<1>(0h0))
node _T_535 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_536 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_537 = mux(_WIRE_2[8], _T_524, UInt<1>(0h0))
node _T_538 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_539 = mux(_WIRE_2[10], _T_525, UInt<1>(0h0))
node _T_540 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0))
node _T_541 = mux(_WIRE_2[12], _T_526, UInt<1>(0h0))
node _T_542 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_543 = mux(_WIRE_2[14], _T_527, UInt<1>(0h0))
node _T_544 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_545 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_546 = mux(_WIRE_2[17], _T_528, UInt<1>(0h0))
node _T_547 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0))
node _T_548 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0))
node _T_549 = or(_T_529, _T_530)
node _T_550 = or(_T_549, _T_531)
node _T_551 = or(_T_550, _T_532)
node _T_552 = or(_T_551, _T_533)
node _T_553 = or(_T_552, _T_534)
node _T_554 = or(_T_553, _T_535)
node _T_555 = or(_T_554, _T_536)
node _T_556 = or(_T_555, _T_537)
node _T_557 = or(_T_556, _T_538)
node _T_558 = or(_T_557, _T_539)
node _T_559 = or(_T_558, _T_540)
node _T_560 = or(_T_559, _T_541)
node _T_561 = or(_T_560, _T_542)
node _T_562 = or(_T_561, _T_543)
node _T_563 = or(_T_562, _T_544)
node _T_564 = or(_T_563, _T_545)
node _T_565 = or(_T_564, _T_546)
node _T_566 = or(_T_565, _T_547)
node _T_567 = or(_T_566, _T_548)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_567
node _T_568 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_569 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_570 = and(_T_568, _T_569)
node _T_571 = or(UInt<1>(0h0), _T_570)
node _T_572 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_573 = cvt(_T_572)
node _T_574 = and(_T_573, asSInt(UInt<13>(0h1000)))
node _T_575 = asSInt(_T_574)
node _T_576 = eq(_T_575, asSInt(UInt<1>(0h0)))
node _T_577 = and(_T_571, _T_576)
node _T_578 = or(UInt<1>(0h0), _T_577)
node _T_579 = and(_WIRE_3, _T_578)
node _T_580 = asUInt(reset)
node _T_581 = eq(_T_580, UInt<1>(0h0))
when _T_581 :
node _T_582 = eq(_T_579, UInt<1>(0h0))
when _T_582 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_579, UInt<1>(0h1), "") : assert_11
node _T_583 = asUInt(reset)
node _T_584 = eq(_T_583, UInt<1>(0h0))
when _T_584 :
node _T_585 = eq(source_ok, UInt<1>(0h0))
when _T_585 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_586 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_587 = asUInt(reset)
node _T_588 = eq(_T_587, UInt<1>(0h0))
when _T_588 :
node _T_589 = eq(_T_586, UInt<1>(0h0))
when _T_589 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_586, UInt<1>(0h1), "") : assert_13
node _T_590 = asUInt(reset)
node _T_591 = eq(_T_590, UInt<1>(0h0))
when _T_591 :
node _T_592 = eq(is_aligned, UInt<1>(0h0))
when _T_592 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_593 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_594 = asUInt(reset)
node _T_595 = eq(_T_594, UInt<1>(0h0))
when _T_595 :
node _T_596 = eq(_T_593, UInt<1>(0h0))
when _T_596 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_593, UInt<1>(0h1), "") : assert_15
node _T_597 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_598 = asUInt(reset)
node _T_599 = eq(_T_598, UInt<1>(0h0))
when _T_599 :
node _T_600 = eq(_T_597, UInt<1>(0h0))
when _T_600 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_597, UInt<1>(0h1), "") : assert_16
node _T_601 = not(io.in.a.bits.mask)
node _T_602 = eq(_T_601, UInt<1>(0h0))
node _T_603 = asUInt(reset)
node _T_604 = eq(_T_603, UInt<1>(0h0))
when _T_604 :
node _T_605 = eq(_T_602, UInt<1>(0h0))
when _T_605 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_602, UInt<1>(0h1), "") : assert_17
node _T_606 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_607 = asUInt(reset)
node _T_608 = eq(_T_607, UInt<1>(0h0))
when _T_608 :
node _T_609 = eq(_T_606, UInt<1>(0h0))
when _T_609 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_606, UInt<1>(0h1), "") : assert_18
node _T_610 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_610 :
node _T_611 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_612 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_613 = and(_T_611, _T_612)
node _T_614 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_615 = shr(io.in.a.bits.source, 2)
node _T_616 = eq(_T_615, UInt<1>(0h0))
node _T_617 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_618 = and(_T_616, _T_617)
node _T_619 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_620 = and(_T_618, _T_619)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_621 = shr(io.in.a.bits.source, 2)
node _T_622 = eq(_T_621, UInt<1>(0h1))
node _T_623 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_624 = and(_T_622, _T_623)
node _T_625 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_626 = and(_T_624, _T_625)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_627 = shr(io.in.a.bits.source, 2)
node _T_628 = eq(_T_627, UInt<2>(0h2))
node _T_629 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_630 = and(_T_628, _T_629)
node _T_631 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_632 = and(_T_630, _T_631)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_633 = shr(io.in.a.bits.source, 2)
node _T_634 = eq(_T_633, UInt<2>(0h3))
node _T_635 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_636 = and(_T_634, _T_635)
node _T_637 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_638 = and(_T_636, _T_637)
node _T_639 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_640 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_641 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_642 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_643 = eq(io.in.a.bits.source, UInt<6>(0h2f))
node _T_644 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_645 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_646 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_647 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_648 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_649 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_650 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_651 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_652 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_653 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_654 = or(_T_614, _T_620)
node _T_655 = or(_T_654, _T_626)
node _T_656 = or(_T_655, _T_632)
node _T_657 = or(_T_656, _T_638)
node _T_658 = or(_T_657, _T_639)
node _T_659 = or(_T_658, _T_640)
node _T_660 = or(_T_659, _T_641)
node _T_661 = or(_T_660, _T_642)
node _T_662 = or(_T_661, _T_643)
node _T_663 = or(_T_662, _T_644)
node _T_664 = or(_T_663, _T_645)
node _T_665 = or(_T_664, _T_646)
node _T_666 = or(_T_665, _T_647)
node _T_667 = or(_T_666, _T_648)
node _T_668 = or(_T_667, _T_649)
node _T_669 = or(_T_668, _T_650)
node _T_670 = or(_T_669, _T_651)
node _T_671 = or(_T_670, _T_652)
node _T_672 = or(_T_671, _T_653)
node _T_673 = and(_T_613, _T_672)
node _T_674 = or(UInt<1>(0h0), _T_673)
node _T_675 = asUInt(reset)
node _T_676 = eq(_T_675, UInt<1>(0h0))
when _T_676 :
node _T_677 = eq(_T_674, UInt<1>(0h0))
when _T_677 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_674, UInt<1>(0h1), "") : assert_19
node _T_678 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_679 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_680 = and(_T_678, _T_679)
node _T_681 = or(UInt<1>(0h0), _T_680)
node _T_682 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_683 = cvt(_T_682)
node _T_684 = and(_T_683, asSInt(UInt<13>(0h1000)))
node _T_685 = asSInt(_T_684)
node _T_686 = eq(_T_685, asSInt(UInt<1>(0h0)))
node _T_687 = and(_T_681, _T_686)
node _T_688 = or(UInt<1>(0h0), _T_687)
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(_T_688, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_688, UInt<1>(0h1), "") : assert_20
node _T_692 = asUInt(reset)
node _T_693 = eq(_T_692, UInt<1>(0h0))
when _T_693 :
node _T_694 = eq(source_ok, UInt<1>(0h0))
when _T_694 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_695 = asUInt(reset)
node _T_696 = eq(_T_695, UInt<1>(0h0))
when _T_696 :
node _T_697 = eq(is_aligned, UInt<1>(0h0))
when _T_697 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_698 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_699 = asUInt(reset)
node _T_700 = eq(_T_699, UInt<1>(0h0))
when _T_700 :
node _T_701 = eq(_T_698, UInt<1>(0h0))
when _T_701 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_698, UInt<1>(0h1), "") : assert_23
node _T_702 = eq(io.in.a.bits.mask, mask)
node _T_703 = asUInt(reset)
node _T_704 = eq(_T_703, UInt<1>(0h0))
when _T_704 :
node _T_705 = eq(_T_702, UInt<1>(0h0))
when _T_705 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_702, UInt<1>(0h1), "") : assert_24
node _T_706 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_707 = asUInt(reset)
node _T_708 = eq(_T_707, UInt<1>(0h0))
when _T_708 :
node _T_709 = eq(_T_706, UInt<1>(0h0))
when _T_709 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_706, UInt<1>(0h1), "") : assert_25
node _T_710 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_710 :
node _T_711 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_712 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_713 = and(_T_711, _T_712)
node _T_714 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_715 = shr(io.in.a.bits.source, 2)
node _T_716 = eq(_T_715, UInt<1>(0h0))
node _T_717 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_718 = and(_T_716, _T_717)
node _T_719 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_720 = and(_T_718, _T_719)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_721 = shr(io.in.a.bits.source, 2)
node _T_722 = eq(_T_721, UInt<1>(0h1))
node _T_723 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_724 = and(_T_722, _T_723)
node _T_725 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_726 = and(_T_724, _T_725)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_727 = shr(io.in.a.bits.source, 2)
node _T_728 = eq(_T_727, UInt<2>(0h2))
node _T_729 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_730 = and(_T_728, _T_729)
node _T_731 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_732 = and(_T_730, _T_731)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_733 = shr(io.in.a.bits.source, 2)
node _T_734 = eq(_T_733, UInt<2>(0h3))
node _T_735 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_736 = and(_T_734, _T_735)
node _T_737 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_738 = and(_T_736, _T_737)
node _T_739 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_740 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_741 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_742 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_743 = eq(io.in.a.bits.source, UInt<6>(0h2f))
node _T_744 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_745 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_746 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_747 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_748 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_749 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_750 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_751 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_752 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_753 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_754 = or(_T_714, _T_720)
node _T_755 = or(_T_754, _T_726)
node _T_756 = or(_T_755, _T_732)
node _T_757 = or(_T_756, _T_738)
node _T_758 = or(_T_757, _T_739)
node _T_759 = or(_T_758, _T_740)
node _T_760 = or(_T_759, _T_741)
node _T_761 = or(_T_760, _T_742)
node _T_762 = or(_T_761, _T_743)
node _T_763 = or(_T_762, _T_744)
node _T_764 = or(_T_763, _T_745)
node _T_765 = or(_T_764, _T_746)
node _T_766 = or(_T_765, _T_747)
node _T_767 = or(_T_766, _T_748)
node _T_768 = or(_T_767, _T_749)
node _T_769 = or(_T_768, _T_750)
node _T_770 = or(_T_769, _T_751)
node _T_771 = or(_T_770, _T_752)
node _T_772 = or(_T_771, _T_753)
node _T_773 = and(_T_713, _T_772)
node _T_774 = or(UInt<1>(0h0), _T_773)
node _T_775 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_776 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_777 = and(_T_775, _T_776)
node _T_778 = or(UInt<1>(0h0), _T_777)
node _T_779 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_780 = cvt(_T_779)
node _T_781 = and(_T_780, asSInt(UInt<13>(0h1000)))
node _T_782 = asSInt(_T_781)
node _T_783 = eq(_T_782, asSInt(UInt<1>(0h0)))
node _T_784 = and(_T_778, _T_783)
node _T_785 = or(UInt<1>(0h0), _T_784)
node _T_786 = and(_T_774, _T_785)
node _T_787 = asUInt(reset)
node _T_788 = eq(_T_787, UInt<1>(0h0))
when _T_788 :
node _T_789 = eq(_T_786, UInt<1>(0h0))
when _T_789 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_786, UInt<1>(0h1), "") : assert_26
node _T_790 = asUInt(reset)
node _T_791 = eq(_T_790, UInt<1>(0h0))
when _T_791 :
node _T_792 = eq(source_ok, UInt<1>(0h0))
when _T_792 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_793 = asUInt(reset)
node _T_794 = eq(_T_793, UInt<1>(0h0))
when _T_794 :
node _T_795 = eq(is_aligned, UInt<1>(0h0))
when _T_795 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_796 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_797 = asUInt(reset)
node _T_798 = eq(_T_797, UInt<1>(0h0))
when _T_798 :
node _T_799 = eq(_T_796, UInt<1>(0h0))
when _T_799 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_796, UInt<1>(0h1), "") : assert_29
node _T_800 = eq(io.in.a.bits.mask, mask)
node _T_801 = asUInt(reset)
node _T_802 = eq(_T_801, UInt<1>(0h0))
when _T_802 :
node _T_803 = eq(_T_800, UInt<1>(0h0))
when _T_803 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_800, UInt<1>(0h1), "") : assert_30
node _T_804 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_804 :
node _T_805 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_806 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_807 = and(_T_805, _T_806)
node _T_808 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_809 = shr(io.in.a.bits.source, 2)
node _T_810 = eq(_T_809, UInt<1>(0h0))
node _T_811 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_812 = and(_T_810, _T_811)
node _T_813 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_814 = and(_T_812, _T_813)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_815 = shr(io.in.a.bits.source, 2)
node _T_816 = eq(_T_815, UInt<1>(0h1))
node _T_817 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_818 = and(_T_816, _T_817)
node _T_819 = leq(uncommonBits_29, UInt<2>(0h3))
node _T_820 = and(_T_818, _T_819)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_821 = shr(io.in.a.bits.source, 2)
node _T_822 = eq(_T_821, UInt<2>(0h2))
node _T_823 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_824 = and(_T_822, _T_823)
node _T_825 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_826 = and(_T_824, _T_825)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_827 = shr(io.in.a.bits.source, 2)
node _T_828 = eq(_T_827, UInt<2>(0h3))
node _T_829 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_830 = and(_T_828, _T_829)
node _T_831 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_832 = and(_T_830, _T_831)
node _T_833 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_834 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_835 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_836 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_837 = eq(io.in.a.bits.source, UInt<6>(0h2f))
node _T_838 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_839 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_840 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_841 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_842 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_843 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_844 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_845 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_846 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_847 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_848 = or(_T_808, _T_814)
node _T_849 = or(_T_848, _T_820)
node _T_850 = or(_T_849, _T_826)
node _T_851 = or(_T_850, _T_832)
node _T_852 = or(_T_851, _T_833)
node _T_853 = or(_T_852, _T_834)
node _T_854 = or(_T_853, _T_835)
node _T_855 = or(_T_854, _T_836)
node _T_856 = or(_T_855, _T_837)
node _T_857 = or(_T_856, _T_838)
node _T_858 = or(_T_857, _T_839)
node _T_859 = or(_T_858, _T_840)
node _T_860 = or(_T_859, _T_841)
node _T_861 = or(_T_860, _T_842)
node _T_862 = or(_T_861, _T_843)
node _T_863 = or(_T_862, _T_844)
node _T_864 = or(_T_863, _T_845)
node _T_865 = or(_T_864, _T_846)
node _T_866 = or(_T_865, _T_847)
node _T_867 = and(_T_807, _T_866)
node _T_868 = or(UInt<1>(0h0), _T_867)
node _T_869 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_870 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_871 = and(_T_869, _T_870)
node _T_872 = or(UInt<1>(0h0), _T_871)
node _T_873 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_874 = cvt(_T_873)
node _T_875 = and(_T_874, asSInt(UInt<13>(0h1000)))
node _T_876 = asSInt(_T_875)
node _T_877 = eq(_T_876, asSInt(UInt<1>(0h0)))
node _T_878 = and(_T_872, _T_877)
node _T_879 = or(UInt<1>(0h0), _T_878)
node _T_880 = and(_T_868, _T_879)
node _T_881 = asUInt(reset)
node _T_882 = eq(_T_881, UInt<1>(0h0))
when _T_882 :
node _T_883 = eq(_T_880, UInt<1>(0h0))
when _T_883 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_880, UInt<1>(0h1), "") : assert_31
node _T_884 = asUInt(reset)
node _T_885 = eq(_T_884, UInt<1>(0h0))
when _T_885 :
node _T_886 = eq(source_ok, UInt<1>(0h0))
when _T_886 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_887 = asUInt(reset)
node _T_888 = eq(_T_887, UInt<1>(0h0))
when _T_888 :
node _T_889 = eq(is_aligned, UInt<1>(0h0))
when _T_889 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_890 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_891 = asUInt(reset)
node _T_892 = eq(_T_891, UInt<1>(0h0))
when _T_892 :
node _T_893 = eq(_T_890, UInt<1>(0h0))
when _T_893 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_890, UInt<1>(0h1), "") : assert_34
node _T_894 = not(mask)
node _T_895 = and(io.in.a.bits.mask, _T_894)
node _T_896 = eq(_T_895, UInt<1>(0h0))
node _T_897 = asUInt(reset)
node _T_898 = eq(_T_897, UInt<1>(0h0))
when _T_898 :
node _T_899 = eq(_T_896, UInt<1>(0h0))
when _T_899 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_896, UInt<1>(0h1), "") : assert_35
node _T_900 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_900 :
node _T_901 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_902 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_903 = and(_T_901, _T_902)
node _T_904 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_905 = shr(io.in.a.bits.source, 2)
node _T_906 = eq(_T_905, UInt<1>(0h0))
node _T_907 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_908 = and(_T_906, _T_907)
node _T_909 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_910 = and(_T_908, _T_909)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_911 = shr(io.in.a.bits.source, 2)
node _T_912 = eq(_T_911, UInt<1>(0h1))
node _T_913 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_914 = and(_T_912, _T_913)
node _T_915 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_916 = and(_T_914, _T_915)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_917 = shr(io.in.a.bits.source, 2)
node _T_918 = eq(_T_917, UInt<2>(0h2))
node _T_919 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_920 = and(_T_918, _T_919)
node _T_921 = leq(uncommonBits_34, UInt<2>(0h3))
node _T_922 = and(_T_920, _T_921)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_923 = shr(io.in.a.bits.source, 2)
node _T_924 = eq(_T_923, UInt<2>(0h3))
node _T_925 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_926 = and(_T_924, _T_925)
node _T_927 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_928 = and(_T_926, _T_927)
node _T_929 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_930 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_931 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_932 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_933 = eq(io.in.a.bits.source, UInt<6>(0h2f))
node _T_934 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_935 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_936 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_937 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_938 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_939 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_940 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_941 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_942 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_943 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_944 = or(_T_904, _T_910)
node _T_945 = or(_T_944, _T_916)
node _T_946 = or(_T_945, _T_922)
node _T_947 = or(_T_946, _T_928)
node _T_948 = or(_T_947, _T_929)
node _T_949 = or(_T_948, _T_930)
node _T_950 = or(_T_949, _T_931)
node _T_951 = or(_T_950, _T_932)
node _T_952 = or(_T_951, _T_933)
node _T_953 = or(_T_952, _T_934)
node _T_954 = or(_T_953, _T_935)
node _T_955 = or(_T_954, _T_936)
node _T_956 = or(_T_955, _T_937)
node _T_957 = or(_T_956, _T_938)
node _T_958 = or(_T_957, _T_939)
node _T_959 = or(_T_958, _T_940)
node _T_960 = or(_T_959, _T_941)
node _T_961 = or(_T_960, _T_942)
node _T_962 = or(_T_961, _T_943)
node _T_963 = and(_T_903, _T_962)
node _T_964 = or(UInt<1>(0h0), _T_963)
node _T_965 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_966 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_967 = cvt(_T_966)
node _T_968 = and(_T_967, asSInt(UInt<13>(0h1000)))
node _T_969 = asSInt(_T_968)
node _T_970 = eq(_T_969, asSInt(UInt<1>(0h0)))
node _T_971 = and(_T_965, _T_970)
node _T_972 = or(UInt<1>(0h0), _T_971)
node _T_973 = and(_T_964, _T_972)
node _T_974 = asUInt(reset)
node _T_975 = eq(_T_974, UInt<1>(0h0))
when _T_975 :
node _T_976 = eq(_T_973, UInt<1>(0h0))
when _T_976 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_973, UInt<1>(0h1), "") : assert_36
node _T_977 = asUInt(reset)
node _T_978 = eq(_T_977, UInt<1>(0h0))
when _T_978 :
node _T_979 = eq(source_ok, UInt<1>(0h0))
when _T_979 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_980 = asUInt(reset)
node _T_981 = eq(_T_980, UInt<1>(0h0))
when _T_981 :
node _T_982 = eq(is_aligned, UInt<1>(0h0))
when _T_982 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_983 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_984 = asUInt(reset)
node _T_985 = eq(_T_984, UInt<1>(0h0))
when _T_985 :
node _T_986 = eq(_T_983, UInt<1>(0h0))
when _T_986 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_983, UInt<1>(0h1), "") : assert_39
node _T_987 = eq(io.in.a.bits.mask, mask)
node _T_988 = asUInt(reset)
node _T_989 = eq(_T_988, UInt<1>(0h0))
when _T_989 :
node _T_990 = eq(_T_987, UInt<1>(0h0))
when _T_990 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_987, UInt<1>(0h1), "") : assert_40
node _T_991 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_991 :
node _T_992 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_993 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_994 = and(_T_992, _T_993)
node _T_995 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_996 = shr(io.in.a.bits.source, 2)
node _T_997 = eq(_T_996, UInt<1>(0h0))
node _T_998 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_999 = and(_T_997, _T_998)
node _T_1000 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_1001 = and(_T_999, _T_1000)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_1002 = shr(io.in.a.bits.source, 2)
node _T_1003 = eq(_T_1002, UInt<1>(0h1))
node _T_1004 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_1005 = and(_T_1003, _T_1004)
node _T_1006 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_1007 = and(_T_1005, _T_1006)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_1008 = shr(io.in.a.bits.source, 2)
node _T_1009 = eq(_T_1008, UInt<2>(0h2))
node _T_1010 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_1011 = and(_T_1009, _T_1010)
node _T_1012 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_1013 = and(_T_1011, _T_1012)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_1014 = shr(io.in.a.bits.source, 2)
node _T_1015 = eq(_T_1014, UInt<2>(0h3))
node _T_1016 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_1017 = and(_T_1015, _T_1016)
node _T_1018 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_1019 = and(_T_1017, _T_1018)
node _T_1020 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1021 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1022 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1023 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1024 = eq(io.in.a.bits.source, UInt<6>(0h2f))
node _T_1025 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1026 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1027 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1028 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_1029 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1030 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1031 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1032 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1033 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1034 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1035 = or(_T_995, _T_1001)
node _T_1036 = or(_T_1035, _T_1007)
node _T_1037 = or(_T_1036, _T_1013)
node _T_1038 = or(_T_1037, _T_1019)
node _T_1039 = or(_T_1038, _T_1020)
node _T_1040 = or(_T_1039, _T_1021)
node _T_1041 = or(_T_1040, _T_1022)
node _T_1042 = or(_T_1041, _T_1023)
node _T_1043 = or(_T_1042, _T_1024)
node _T_1044 = or(_T_1043, _T_1025)
node _T_1045 = or(_T_1044, _T_1026)
node _T_1046 = or(_T_1045, _T_1027)
node _T_1047 = or(_T_1046, _T_1028)
node _T_1048 = or(_T_1047, _T_1029)
node _T_1049 = or(_T_1048, _T_1030)
node _T_1050 = or(_T_1049, _T_1031)
node _T_1051 = or(_T_1050, _T_1032)
node _T_1052 = or(_T_1051, _T_1033)
node _T_1053 = or(_T_1052, _T_1034)
node _T_1054 = and(_T_994, _T_1053)
node _T_1055 = or(UInt<1>(0h0), _T_1054)
node _T_1056 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1057 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1058 = cvt(_T_1057)
node _T_1059 = and(_T_1058, asSInt(UInt<13>(0h1000)))
node _T_1060 = asSInt(_T_1059)
node _T_1061 = eq(_T_1060, asSInt(UInt<1>(0h0)))
node _T_1062 = and(_T_1056, _T_1061)
node _T_1063 = or(UInt<1>(0h0), _T_1062)
node _T_1064 = and(_T_1055, _T_1063)
node _T_1065 = asUInt(reset)
node _T_1066 = eq(_T_1065, UInt<1>(0h0))
when _T_1066 :
node _T_1067 = eq(_T_1064, UInt<1>(0h0))
when _T_1067 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1064, UInt<1>(0h1), "") : assert_41
node _T_1068 = asUInt(reset)
node _T_1069 = eq(_T_1068, UInt<1>(0h0))
when _T_1069 :
node _T_1070 = eq(source_ok, UInt<1>(0h0))
when _T_1070 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1071 = asUInt(reset)
node _T_1072 = eq(_T_1071, UInt<1>(0h0))
when _T_1072 :
node _T_1073 = eq(is_aligned, UInt<1>(0h0))
when _T_1073 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1074 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1075 = asUInt(reset)
node _T_1076 = eq(_T_1075, UInt<1>(0h0))
when _T_1076 :
node _T_1077 = eq(_T_1074, UInt<1>(0h0))
when _T_1077 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1074, UInt<1>(0h1), "") : assert_44
node _T_1078 = eq(io.in.a.bits.mask, mask)
node _T_1079 = asUInt(reset)
node _T_1080 = eq(_T_1079, UInt<1>(0h0))
when _T_1080 :
node _T_1081 = eq(_T_1078, UInt<1>(0h0))
when _T_1081 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1078, UInt<1>(0h1), "") : assert_45
node _T_1082 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1082 :
node _T_1083 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1084 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1085 = and(_T_1083, _T_1084)
node _T_1086 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_1087 = shr(io.in.a.bits.source, 2)
node _T_1088 = eq(_T_1087, UInt<1>(0h0))
node _T_1089 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_1090 = and(_T_1088, _T_1089)
node _T_1091 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_1092 = and(_T_1090, _T_1091)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_1093 = shr(io.in.a.bits.source, 2)
node _T_1094 = eq(_T_1093, UInt<1>(0h1))
node _T_1095 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_1096 = and(_T_1094, _T_1095)
node _T_1097 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_1098 = and(_T_1096, _T_1097)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_1099 = shr(io.in.a.bits.source, 2)
node _T_1100 = eq(_T_1099, UInt<2>(0h2))
node _T_1101 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_1102 = and(_T_1100, _T_1101)
node _T_1103 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_1104 = and(_T_1102, _T_1103)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_1105 = shr(io.in.a.bits.source, 2)
node _T_1106 = eq(_T_1105, UInt<2>(0h3))
node _T_1107 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_1108 = and(_T_1106, _T_1107)
node _T_1109 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_1110 = and(_T_1108, _T_1109)
node _T_1111 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_1112 = eq(io.in.a.bits.source, UInt<6>(0h25))
node _T_1113 = eq(io.in.a.bits.source, UInt<6>(0h26))
node _T_1114 = eq(io.in.a.bits.source, UInt<6>(0h2e))
node _T_1115 = eq(io.in.a.bits.source, UInt<6>(0h2f))
node _T_1116 = eq(io.in.a.bits.source, UInt<6>(0h2c))
node _T_1117 = eq(io.in.a.bits.source, UInt<6>(0h2d))
node _T_1118 = eq(io.in.a.bits.source, UInt<6>(0h2a))
node _T_1119 = eq(io.in.a.bits.source, UInt<6>(0h2b))
node _T_1120 = eq(io.in.a.bits.source, UInt<6>(0h28))
node _T_1121 = eq(io.in.a.bits.source, UInt<6>(0h29))
node _T_1122 = eq(io.in.a.bits.source, UInt<6>(0h22))
node _T_1123 = eq(io.in.a.bits.source, UInt<6>(0h20))
node _T_1124 = eq(io.in.a.bits.source, UInt<6>(0h21))
node _T_1125 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_1126 = or(_T_1086, _T_1092)
node _T_1127 = or(_T_1126, _T_1098)
node _T_1128 = or(_T_1127, _T_1104)
node _T_1129 = or(_T_1128, _T_1110)
node _T_1130 = or(_T_1129, _T_1111)
node _T_1131 = or(_T_1130, _T_1112)
node _T_1132 = or(_T_1131, _T_1113)
node _T_1133 = or(_T_1132, _T_1114)
node _T_1134 = or(_T_1133, _T_1115)
node _T_1135 = or(_T_1134, _T_1116)
node _T_1136 = or(_T_1135, _T_1117)
node _T_1137 = or(_T_1136, _T_1118)
node _T_1138 = or(_T_1137, _T_1119)
node _T_1139 = or(_T_1138, _T_1120)
node _T_1140 = or(_T_1139, _T_1121)
node _T_1141 = or(_T_1140, _T_1122)
node _T_1142 = or(_T_1141, _T_1123)
node _T_1143 = or(_T_1142, _T_1124)
node _T_1144 = or(_T_1143, _T_1125)
node _T_1145 = and(_T_1085, _T_1144)
node _T_1146 = or(UInt<1>(0h0), _T_1145)
node _T_1147 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1148 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_1149 = cvt(_T_1148)
node _T_1150 = and(_T_1149, asSInt(UInt<13>(0h1000)))
node _T_1151 = asSInt(_T_1150)
node _T_1152 = eq(_T_1151, asSInt(UInt<1>(0h0)))
node _T_1153 = and(_T_1147, _T_1152)
node _T_1154 = or(UInt<1>(0h0), _T_1153)
node _T_1155 = and(_T_1146, _T_1154)
node _T_1156 = asUInt(reset)
node _T_1157 = eq(_T_1156, UInt<1>(0h0))
when _T_1157 :
node _T_1158 = eq(_T_1155, UInt<1>(0h0))
when _T_1158 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1155, UInt<1>(0h1), "") : assert_46
node _T_1159 = asUInt(reset)
node _T_1160 = eq(_T_1159, UInt<1>(0h0))
when _T_1160 :
node _T_1161 = eq(source_ok, UInt<1>(0h0))
when _T_1161 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1162 = asUInt(reset)
node _T_1163 = eq(_T_1162, UInt<1>(0h0))
when _T_1163 :
node _T_1164 = eq(is_aligned, UInt<1>(0h0))
when _T_1164 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1165 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1166 = asUInt(reset)
node _T_1167 = eq(_T_1166, UInt<1>(0h0))
when _T_1167 :
node _T_1168 = eq(_T_1165, UInt<1>(0h0))
when _T_1168 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1165, UInt<1>(0h1), "") : assert_49
node _T_1169 = eq(io.in.a.bits.mask, mask)
node _T_1170 = asUInt(reset)
node _T_1171 = eq(_T_1170, UInt<1>(0h0))
when _T_1171 :
node _T_1172 = eq(_T_1169, UInt<1>(0h0))
when _T_1172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1169, UInt<1>(0h1), "") : assert_50
node _T_1173 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1174 = asUInt(reset)
node _T_1175 = eq(_T_1174, UInt<1>(0h0))
when _T_1175 :
node _T_1176 = eq(_T_1173, UInt<1>(0h0))
when _T_1176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1173, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1177 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1178 = asUInt(reset)
node _T_1179 = eq(_T_1178, UInt<1>(0h0))
when _T_1179 :
node _T_1180 = eq(_T_1177, UInt<1>(0h0))
when _T_1180 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1177, UInt<1>(0h1), "") : assert_52
node _source_ok_T_58 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_59 = shr(io.in.d.bits.source, 2)
node _source_ok_T_60 = eq(_source_ok_T_59, UInt<1>(0h0))
node _source_ok_T_61 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61)
node _source_ok_T_63 = leq(source_ok_uncommonBits_4, UInt<2>(0h3))
node _source_ok_T_64 = and(_source_ok_T_62, _source_ok_T_63)
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_65 = shr(io.in.d.bits.source, 2)
node _source_ok_T_66 = eq(_source_ok_T_65, UInt<1>(0h1))
node _source_ok_T_67 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67)
node _source_ok_T_69 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_70 = and(_source_ok_T_68, _source_ok_T_69)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_71 = shr(io.in.d.bits.source, 2)
node _source_ok_T_72 = eq(_source_ok_T_71, UInt<2>(0h2))
node _source_ok_T_73 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73)
node _source_ok_T_75 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_76 = and(_source_ok_T_74, _source_ok_T_75)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_77 = shr(io.in.d.bits.source, 2)
node _source_ok_T_78 = eq(_source_ok_T_77, UInt<2>(0h3))
node _source_ok_T_79 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79)
node _source_ok_T_81 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81)
node _source_ok_T_83 = eq(io.in.d.bits.source, UInt<6>(0h24))
node _source_ok_T_84 = eq(io.in.d.bits.source, UInt<6>(0h25))
node _source_ok_T_85 = eq(io.in.d.bits.source, UInt<6>(0h26))
node _source_ok_T_86 = eq(io.in.d.bits.source, UInt<6>(0h2e))
node _source_ok_T_87 = eq(io.in.d.bits.source, UInt<6>(0h2f))
node _source_ok_T_88 = eq(io.in.d.bits.source, UInt<6>(0h2c))
node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<6>(0h2d))
node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<6>(0h2a))
node _source_ok_T_91 = eq(io.in.d.bits.source, UInt<6>(0h2b))
node _source_ok_T_92 = eq(io.in.d.bits.source, UInt<6>(0h28))
node _source_ok_T_93 = eq(io.in.d.bits.source, UInt<6>(0h29))
node _source_ok_T_94 = eq(io.in.d.bits.source, UInt<6>(0h22))
node _source_ok_T_95 = eq(io.in.d.bits.source, UInt<6>(0h20))
node _source_ok_T_96 = eq(io.in.d.bits.source, UInt<6>(0h21))
node _source_ok_T_97 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[20]
connect _source_ok_WIRE_1[0], _source_ok_T_58
connect _source_ok_WIRE_1[1], _source_ok_T_64
connect _source_ok_WIRE_1[2], _source_ok_T_70
connect _source_ok_WIRE_1[3], _source_ok_T_76
connect _source_ok_WIRE_1[4], _source_ok_T_82
connect _source_ok_WIRE_1[5], _source_ok_T_83
connect _source_ok_WIRE_1[6], _source_ok_T_84
connect _source_ok_WIRE_1[7], _source_ok_T_85
connect _source_ok_WIRE_1[8], _source_ok_T_86
connect _source_ok_WIRE_1[9], _source_ok_T_87
connect _source_ok_WIRE_1[10], _source_ok_T_88
connect _source_ok_WIRE_1[11], _source_ok_T_89
connect _source_ok_WIRE_1[12], _source_ok_T_90
connect _source_ok_WIRE_1[13], _source_ok_T_91
connect _source_ok_WIRE_1[14], _source_ok_T_92
connect _source_ok_WIRE_1[15], _source_ok_T_93
connect _source_ok_WIRE_1[16], _source_ok_T_94
connect _source_ok_WIRE_1[17], _source_ok_T_95
connect _source_ok_WIRE_1[18], _source_ok_T_96
connect _source_ok_WIRE_1[19], _source_ok_T_97
node _source_ok_T_98 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[2])
node _source_ok_T_100 = or(_source_ok_T_99, _source_ok_WIRE_1[3])
node _source_ok_T_101 = or(_source_ok_T_100, _source_ok_WIRE_1[4])
node _source_ok_T_102 = or(_source_ok_T_101, _source_ok_WIRE_1[5])
node _source_ok_T_103 = or(_source_ok_T_102, _source_ok_WIRE_1[6])
node _source_ok_T_104 = or(_source_ok_T_103, _source_ok_WIRE_1[7])
node _source_ok_T_105 = or(_source_ok_T_104, _source_ok_WIRE_1[8])
node _source_ok_T_106 = or(_source_ok_T_105, _source_ok_WIRE_1[9])
node _source_ok_T_107 = or(_source_ok_T_106, _source_ok_WIRE_1[10])
node _source_ok_T_108 = or(_source_ok_T_107, _source_ok_WIRE_1[11])
node _source_ok_T_109 = or(_source_ok_T_108, _source_ok_WIRE_1[12])
node _source_ok_T_110 = or(_source_ok_T_109, _source_ok_WIRE_1[13])
node _source_ok_T_111 = or(_source_ok_T_110, _source_ok_WIRE_1[14])
node _source_ok_T_112 = or(_source_ok_T_111, _source_ok_WIRE_1[15])
node _source_ok_T_113 = or(_source_ok_T_112, _source_ok_WIRE_1[16])
node _source_ok_T_114 = or(_source_ok_T_113, _source_ok_WIRE_1[17])
node _source_ok_T_115 = or(_source_ok_T_114, _source_ok_WIRE_1[18])
node source_ok_1 = or(_source_ok_T_115, _source_ok_WIRE_1[19])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1181 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1181 :
node _T_1182 = asUInt(reset)
node _T_1183 = eq(_T_1182, UInt<1>(0h0))
when _T_1183 :
node _T_1184 = eq(source_ok_1, UInt<1>(0h0))
when _T_1184 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1185 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1186 = asUInt(reset)
node _T_1187 = eq(_T_1186, UInt<1>(0h0))
when _T_1187 :
node _T_1188 = eq(_T_1185, UInt<1>(0h0))
when _T_1188 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1185, UInt<1>(0h1), "") : assert_54
node _T_1189 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1190 = asUInt(reset)
node _T_1191 = eq(_T_1190, UInt<1>(0h0))
when _T_1191 :
node _T_1192 = eq(_T_1189, UInt<1>(0h0))
when _T_1192 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1189, UInt<1>(0h1), "") : assert_55
node _T_1193 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1194 = asUInt(reset)
node _T_1195 = eq(_T_1194, UInt<1>(0h0))
when _T_1195 :
node _T_1196 = eq(_T_1193, UInt<1>(0h0))
when _T_1196 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1193, UInt<1>(0h1), "") : assert_56
node _T_1197 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1198 = asUInt(reset)
node _T_1199 = eq(_T_1198, UInt<1>(0h0))
when _T_1199 :
node _T_1200 = eq(_T_1197, UInt<1>(0h0))
when _T_1200 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1197, UInt<1>(0h1), "") : assert_57
node _T_1201 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1201 :
node _T_1202 = asUInt(reset)
node _T_1203 = eq(_T_1202, UInt<1>(0h0))
when _T_1203 :
node _T_1204 = eq(source_ok_1, UInt<1>(0h0))
when _T_1204 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1205 = asUInt(reset)
node _T_1206 = eq(_T_1205, UInt<1>(0h0))
when _T_1206 :
node _T_1207 = eq(sink_ok, UInt<1>(0h0))
when _T_1207 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1208 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1209 = asUInt(reset)
node _T_1210 = eq(_T_1209, UInt<1>(0h0))
when _T_1210 :
node _T_1211 = eq(_T_1208, UInt<1>(0h0))
when _T_1211 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1208, UInt<1>(0h1), "") : assert_60
node _T_1212 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1213 = asUInt(reset)
node _T_1214 = eq(_T_1213, UInt<1>(0h0))
when _T_1214 :
node _T_1215 = eq(_T_1212, UInt<1>(0h0))
when _T_1215 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1212, UInt<1>(0h1), "") : assert_61
node _T_1216 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1217 = asUInt(reset)
node _T_1218 = eq(_T_1217, UInt<1>(0h0))
when _T_1218 :
node _T_1219 = eq(_T_1216, UInt<1>(0h0))
when _T_1219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1216, UInt<1>(0h1), "") : assert_62
node _T_1220 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1221 = asUInt(reset)
node _T_1222 = eq(_T_1221, UInt<1>(0h0))
when _T_1222 :
node _T_1223 = eq(_T_1220, UInt<1>(0h0))
when _T_1223 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1220, UInt<1>(0h1), "") : assert_63
node _T_1224 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1225 = or(UInt<1>(0h0), _T_1224)
node _T_1226 = asUInt(reset)
node _T_1227 = eq(_T_1226, UInt<1>(0h0))
when _T_1227 :
node _T_1228 = eq(_T_1225, UInt<1>(0h0))
when _T_1228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1225, UInt<1>(0h1), "") : assert_64
node _T_1229 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1229 :
node _T_1230 = asUInt(reset)
node _T_1231 = eq(_T_1230, UInt<1>(0h0))
when _T_1231 :
node _T_1232 = eq(source_ok_1, UInt<1>(0h0))
when _T_1232 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1233 = asUInt(reset)
node _T_1234 = eq(_T_1233, UInt<1>(0h0))
when _T_1234 :
node _T_1235 = eq(sink_ok, UInt<1>(0h0))
when _T_1235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1236 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1237 = asUInt(reset)
node _T_1238 = eq(_T_1237, UInt<1>(0h0))
when _T_1238 :
node _T_1239 = eq(_T_1236, UInt<1>(0h0))
when _T_1239 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1236, UInt<1>(0h1), "") : assert_67
node _T_1240 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1241 = asUInt(reset)
node _T_1242 = eq(_T_1241, UInt<1>(0h0))
when _T_1242 :
node _T_1243 = eq(_T_1240, UInt<1>(0h0))
when _T_1243 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1240, UInt<1>(0h1), "") : assert_68
node _T_1244 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1245 = asUInt(reset)
node _T_1246 = eq(_T_1245, UInt<1>(0h0))
when _T_1246 :
node _T_1247 = eq(_T_1244, UInt<1>(0h0))
when _T_1247 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1244, UInt<1>(0h1), "") : assert_69
node _T_1248 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1249 = or(_T_1248, io.in.d.bits.corrupt)
node _T_1250 = asUInt(reset)
node _T_1251 = eq(_T_1250, UInt<1>(0h0))
when _T_1251 :
node _T_1252 = eq(_T_1249, UInt<1>(0h0))
when _T_1252 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1249, UInt<1>(0h1), "") : assert_70
node _T_1253 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1254 = or(UInt<1>(0h0), _T_1253)
node _T_1255 = asUInt(reset)
node _T_1256 = eq(_T_1255, UInt<1>(0h0))
when _T_1256 :
node _T_1257 = eq(_T_1254, UInt<1>(0h0))
when _T_1257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1254, UInt<1>(0h1), "") : assert_71
node _T_1258 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1258 :
node _T_1259 = asUInt(reset)
node _T_1260 = eq(_T_1259, UInt<1>(0h0))
when _T_1260 :
node _T_1261 = eq(source_ok_1, UInt<1>(0h0))
when _T_1261 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1262 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1263 = asUInt(reset)
node _T_1264 = eq(_T_1263, UInt<1>(0h0))
when _T_1264 :
node _T_1265 = eq(_T_1262, UInt<1>(0h0))
when _T_1265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1262, UInt<1>(0h1), "") : assert_73
node _T_1266 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1267 = asUInt(reset)
node _T_1268 = eq(_T_1267, UInt<1>(0h0))
when _T_1268 :
node _T_1269 = eq(_T_1266, UInt<1>(0h0))
when _T_1269 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1266, UInt<1>(0h1), "") : assert_74
node _T_1270 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1271 = or(UInt<1>(0h0), _T_1270)
node _T_1272 = asUInt(reset)
node _T_1273 = eq(_T_1272, UInt<1>(0h0))
when _T_1273 :
node _T_1274 = eq(_T_1271, UInt<1>(0h0))
when _T_1274 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1271, UInt<1>(0h1), "") : assert_75
node _T_1275 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1275 :
node _T_1276 = asUInt(reset)
node _T_1277 = eq(_T_1276, UInt<1>(0h0))
when _T_1277 :
node _T_1278 = eq(source_ok_1, UInt<1>(0h0))
when _T_1278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1279 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1280 = asUInt(reset)
node _T_1281 = eq(_T_1280, UInt<1>(0h0))
when _T_1281 :
node _T_1282 = eq(_T_1279, UInt<1>(0h0))
when _T_1282 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1279, UInt<1>(0h1), "") : assert_77
node _T_1283 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1284 = or(_T_1283, io.in.d.bits.corrupt)
node _T_1285 = asUInt(reset)
node _T_1286 = eq(_T_1285, UInt<1>(0h0))
when _T_1286 :
node _T_1287 = eq(_T_1284, UInt<1>(0h0))
when _T_1287 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1284, UInt<1>(0h1), "") : assert_78
node _T_1288 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1289 = or(UInt<1>(0h0), _T_1288)
node _T_1290 = asUInt(reset)
node _T_1291 = eq(_T_1290, UInt<1>(0h0))
when _T_1291 :
node _T_1292 = eq(_T_1289, UInt<1>(0h0))
when _T_1292 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1289, UInt<1>(0h1), "") : assert_79
node _T_1293 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1293 :
node _T_1294 = asUInt(reset)
node _T_1295 = eq(_T_1294, UInt<1>(0h0))
when _T_1295 :
node _T_1296 = eq(source_ok_1, UInt<1>(0h0))
when _T_1296 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1297 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1298 = asUInt(reset)
node _T_1299 = eq(_T_1298, UInt<1>(0h0))
when _T_1299 :
node _T_1300 = eq(_T_1297, UInt<1>(0h0))
when _T_1300 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1297, UInt<1>(0h1), "") : assert_81
node _T_1301 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1302 = asUInt(reset)
node _T_1303 = eq(_T_1302, UInt<1>(0h0))
when _T_1303 :
node _T_1304 = eq(_T_1301, UInt<1>(0h0))
when _T_1304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1301, UInt<1>(0h1), "") : assert_82
node _T_1305 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1306 = or(UInt<1>(0h0), _T_1305)
node _T_1307 = asUInt(reset)
node _T_1308 = eq(_T_1307, UInt<1>(0h0))
when _T_1308 :
node _T_1309 = eq(_T_1306, UInt<1>(0h0))
when _T_1309 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1306, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<21>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1310 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1311 = asUInt(reset)
node _T_1312 = eq(_T_1311, UInt<1>(0h0))
when _T_1312 :
node _T_1313 = eq(_T_1310, UInt<1>(0h0))
when _T_1313 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1310, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<21>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1314 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1315 = asUInt(reset)
node _T_1316 = eq(_T_1315, UInt<1>(0h0))
when _T_1316 :
node _T_1317 = eq(_T_1314, UInt<1>(0h0))
when _T_1317 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1314, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1318 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1319 = asUInt(reset)
node _T_1320 = eq(_T_1319, UInt<1>(0h0))
when _T_1320 :
node _T_1321 = eq(_T_1318, UInt<1>(0h0))
when _T_1321 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1318, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1322 = eq(a_first, UInt<1>(0h0))
node _T_1323 = and(io.in.a.valid, _T_1322)
when _T_1323 :
node _T_1324 = eq(io.in.a.bits.opcode, opcode)
node _T_1325 = asUInt(reset)
node _T_1326 = eq(_T_1325, UInt<1>(0h0))
when _T_1326 :
node _T_1327 = eq(_T_1324, UInt<1>(0h0))
when _T_1327 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1324, UInt<1>(0h1), "") : assert_87
node _T_1328 = eq(io.in.a.bits.param, param)
node _T_1329 = asUInt(reset)
node _T_1330 = eq(_T_1329, UInt<1>(0h0))
when _T_1330 :
node _T_1331 = eq(_T_1328, UInt<1>(0h0))
when _T_1331 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1328, UInt<1>(0h1), "") : assert_88
node _T_1332 = eq(io.in.a.bits.size, size)
node _T_1333 = asUInt(reset)
node _T_1334 = eq(_T_1333, UInt<1>(0h0))
when _T_1334 :
node _T_1335 = eq(_T_1332, UInt<1>(0h0))
when _T_1335 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1332, UInt<1>(0h1), "") : assert_89
node _T_1336 = eq(io.in.a.bits.source, source)
node _T_1337 = asUInt(reset)
node _T_1338 = eq(_T_1337, UInt<1>(0h0))
when _T_1338 :
node _T_1339 = eq(_T_1336, UInt<1>(0h0))
when _T_1339 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1336, UInt<1>(0h1), "") : assert_90
node _T_1340 = eq(io.in.a.bits.address, address)
node _T_1341 = asUInt(reset)
node _T_1342 = eq(_T_1341, UInt<1>(0h0))
when _T_1342 :
node _T_1343 = eq(_T_1340, UInt<1>(0h0))
when _T_1343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1340, UInt<1>(0h1), "") : assert_91
node _T_1344 = and(io.in.a.ready, io.in.a.valid)
node _T_1345 = and(_T_1344, a_first)
when _T_1345 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1346 = eq(d_first, UInt<1>(0h0))
node _T_1347 = and(io.in.d.valid, _T_1346)
when _T_1347 :
node _T_1348 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1349 = asUInt(reset)
node _T_1350 = eq(_T_1349, UInt<1>(0h0))
when _T_1350 :
node _T_1351 = eq(_T_1348, UInt<1>(0h0))
when _T_1351 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1348, UInt<1>(0h1), "") : assert_92
node _T_1352 = eq(io.in.d.bits.param, param_1)
node _T_1353 = asUInt(reset)
node _T_1354 = eq(_T_1353, UInt<1>(0h0))
when _T_1354 :
node _T_1355 = eq(_T_1352, UInt<1>(0h0))
when _T_1355 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1352, UInt<1>(0h1), "") : assert_93
node _T_1356 = eq(io.in.d.bits.size, size_1)
node _T_1357 = asUInt(reset)
node _T_1358 = eq(_T_1357, UInt<1>(0h0))
when _T_1358 :
node _T_1359 = eq(_T_1356, UInt<1>(0h0))
when _T_1359 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1356, UInt<1>(0h1), "") : assert_94
node _T_1360 = eq(io.in.d.bits.source, source_1)
node _T_1361 = asUInt(reset)
node _T_1362 = eq(_T_1361, UInt<1>(0h0))
when _T_1362 :
node _T_1363 = eq(_T_1360, UInt<1>(0h0))
when _T_1363 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1360, UInt<1>(0h1), "") : assert_95
node _T_1364 = eq(io.in.d.bits.sink, sink)
node _T_1365 = asUInt(reset)
node _T_1366 = eq(_T_1365, UInt<1>(0h0))
when _T_1366 :
node _T_1367 = eq(_T_1364, UInt<1>(0h0))
when _T_1367 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1364, UInt<1>(0h1), "") : assert_96
node _T_1368 = eq(io.in.d.bits.denied, denied)
node _T_1369 = asUInt(reset)
node _T_1370 = eq(_T_1369, UInt<1>(0h0))
when _T_1370 :
node _T_1371 = eq(_T_1368, UInt<1>(0h0))
when _T_1371 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1368, UInt<1>(0h1), "") : assert_97
node _T_1372 = and(io.in.d.ready, io.in.d.valid)
node _T_1373 = and(_T_1372, d_first)
when _T_1373 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<260>
connect a_sizes_set, UInt<260>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1374 = and(io.in.a.valid, a_first_1)
node _T_1375 = and(_T_1374, UInt<1>(0h1))
when _T_1375 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1376 = and(io.in.a.ready, io.in.a.valid)
node _T_1377 = and(_T_1376, a_first_1)
node _T_1378 = and(_T_1377, UInt<1>(0h1))
when _T_1378 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1379 = dshr(inflight, io.in.a.bits.source)
node _T_1380 = bits(_T_1379, 0, 0)
node _T_1381 = eq(_T_1380, UInt<1>(0h0))
node _T_1382 = asUInt(reset)
node _T_1383 = eq(_T_1382, UInt<1>(0h0))
when _T_1383 :
node _T_1384 = eq(_T_1381, UInt<1>(0h0))
when _T_1384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1381, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<260>
connect d_sizes_clr, UInt<260>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1385 = and(io.in.d.valid, d_first_1)
node _T_1386 = and(_T_1385, UInt<1>(0h1))
node _T_1387 = eq(d_release_ack, UInt<1>(0h0))
node _T_1388 = and(_T_1386, _T_1387)
when _T_1388 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1389 = and(io.in.d.ready, io.in.d.valid)
node _T_1390 = and(_T_1389, d_first_1)
node _T_1391 = and(_T_1390, UInt<1>(0h1))
node _T_1392 = eq(d_release_ack, UInt<1>(0h0))
node _T_1393 = and(_T_1391, _T_1392)
when _T_1393 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1394 = and(io.in.d.valid, d_first_1)
node _T_1395 = and(_T_1394, UInt<1>(0h1))
node _T_1396 = eq(d_release_ack, UInt<1>(0h0))
node _T_1397 = and(_T_1395, _T_1396)
when _T_1397 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1398 = dshr(inflight, io.in.d.bits.source)
node _T_1399 = bits(_T_1398, 0, 0)
node _T_1400 = or(_T_1399, same_cycle_resp)
node _T_1401 = asUInt(reset)
node _T_1402 = eq(_T_1401, UInt<1>(0h0))
when _T_1402 :
node _T_1403 = eq(_T_1400, UInt<1>(0h0))
when _T_1403 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1400, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1404 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1405 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1406 = or(_T_1404, _T_1405)
node _T_1407 = asUInt(reset)
node _T_1408 = eq(_T_1407, UInt<1>(0h0))
when _T_1408 :
node _T_1409 = eq(_T_1406, UInt<1>(0h0))
when _T_1409 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1406, UInt<1>(0h1), "") : assert_100
node _T_1410 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1411 = asUInt(reset)
node _T_1412 = eq(_T_1411, UInt<1>(0h0))
when _T_1412 :
node _T_1413 = eq(_T_1410, UInt<1>(0h0))
when _T_1413 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1410, UInt<1>(0h1), "") : assert_101
else :
node _T_1414 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1415 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1416 = or(_T_1414, _T_1415)
node _T_1417 = asUInt(reset)
node _T_1418 = eq(_T_1417, UInt<1>(0h0))
when _T_1418 :
node _T_1419 = eq(_T_1416, UInt<1>(0h0))
when _T_1419 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1416, UInt<1>(0h1), "") : assert_102
node _T_1420 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1421 = asUInt(reset)
node _T_1422 = eq(_T_1421, UInt<1>(0h0))
when _T_1422 :
node _T_1423 = eq(_T_1420, UInt<1>(0h0))
when _T_1423 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1420, UInt<1>(0h1), "") : assert_103
node _T_1424 = and(io.in.d.valid, d_first_1)
node _T_1425 = and(_T_1424, a_first_1)
node _T_1426 = and(_T_1425, io.in.a.valid)
node _T_1427 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1428 = and(_T_1426, _T_1427)
node _T_1429 = eq(d_release_ack, UInt<1>(0h0))
node _T_1430 = and(_T_1428, _T_1429)
when _T_1430 :
node _T_1431 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1432 = or(_T_1431, io.in.a.ready)
node _T_1433 = asUInt(reset)
node _T_1434 = eq(_T_1433, UInt<1>(0h0))
when _T_1434 :
node _T_1435 = eq(_T_1432, UInt<1>(0h0))
when _T_1435 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1432, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_147
node _T_1436 = orr(inflight)
node _T_1437 = eq(_T_1436, UInt<1>(0h0))
node _T_1438 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1439 = or(_T_1437, _T_1438)
node _T_1440 = lt(watchdog, plusarg_reader.out)
node _T_1441 = or(_T_1439, _T_1440)
node _T_1442 = asUInt(reset)
node _T_1443 = eq(_T_1442, UInt<1>(0h0))
when _T_1443 :
node _T_1444 = eq(_T_1441, UInt<1>(0h0))
when _T_1444 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1441, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1445 = and(io.in.a.ready, io.in.a.valid)
node _T_1446 = and(io.in.d.ready, io.in.d.valid)
node _T_1447 = or(_T_1445, _T_1446)
when _T_1447 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<21>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<260>
connect c_sizes_set, UInt<260>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<21>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1448 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<21>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1449 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1450 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1451 = and(_T_1449, _T_1450)
node _T_1452 = and(_T_1448, _T_1451)
when _T_1452 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<21>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1453 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1454 = and(_T_1453, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<21>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1455 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1456 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1457 = and(_T_1455, _T_1456)
node _T_1458 = and(_T_1454, _T_1457)
when _T_1458 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<21>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1459 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1460 = bits(_T_1459, 0, 0)
node _T_1461 = eq(_T_1460, UInt<1>(0h0))
node _T_1462 = asUInt(reset)
node _T_1463 = eq(_T_1462, UInt<1>(0h0))
when _T_1463 :
node _T_1464 = eq(_T_1461, UInt<1>(0h0))
when _T_1464 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1461, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<260>
connect d_sizes_clr_1, UInt<260>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1465 = and(io.in.d.valid, d_first_2)
node _T_1466 = and(_T_1465, UInt<1>(0h1))
node _T_1467 = and(_T_1466, d_release_ack_1)
when _T_1467 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1468 = and(io.in.d.ready, io.in.d.valid)
node _T_1469 = and(_T_1468, d_first_2)
node _T_1470 = and(_T_1469, UInt<1>(0h1))
node _T_1471 = and(_T_1470, d_release_ack_1)
when _T_1471 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1472 = and(io.in.d.valid, d_first_2)
node _T_1473 = and(_T_1472, UInt<1>(0h1))
node _T_1474 = and(_T_1473, d_release_ack_1)
when _T_1474 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1475 = dshr(inflight_1, io.in.d.bits.source)
node _T_1476 = bits(_T_1475, 0, 0)
node _T_1477 = or(_T_1476, same_cycle_resp_1)
node _T_1478 = asUInt(reset)
node _T_1479 = eq(_T_1478, UInt<1>(0h0))
when _T_1479 :
node _T_1480 = eq(_T_1477, UInt<1>(0h0))
when _T_1480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_1477, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<21>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1481 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1482 = asUInt(reset)
node _T_1483 = eq(_T_1482, UInt<1>(0h0))
when _T_1483 :
node _T_1484 = eq(_T_1481, UInt<1>(0h0))
when _T_1484 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1481, UInt<1>(0h1), "") : assert_108
else :
node _T_1485 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1486 = asUInt(reset)
node _T_1487 = eq(_T_1486, UInt<1>(0h0))
when _T_1487 :
node _T_1488 = eq(_T_1485, UInt<1>(0h0))
when _T_1488 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1485, UInt<1>(0h1), "") : assert_109
node _T_1489 = and(io.in.d.valid, d_first_2)
node _T_1490 = and(_T_1489, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<21>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1491 = and(_T_1490, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<21>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1492 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1493 = and(_T_1491, _T_1492)
node _T_1494 = and(_T_1493, d_release_ack_1)
node _T_1495 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1496 = and(_T_1494, _T_1495)
when _T_1496 :
node _T_1497 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<21>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1498 = or(_T_1497, _WIRE_27.ready)
node _T_1499 = asUInt(reset)
node _T_1500 = eq(_T_1499, UInt<1>(0h0))
when _T_1500 :
node _T_1501 = eq(_T_1498, UInt<1>(0h0))
when _T_1501 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1498, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_148
node _T_1502 = orr(inflight_1)
node _T_1503 = eq(_T_1502, UInt<1>(0h0))
node _T_1504 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1505 = or(_T_1503, _T_1504)
node _T_1506 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1507 = or(_T_1505, _T_1506)
node _T_1508 = asUInt(reset)
node _T_1509 = eq(_T_1508, UInt<1>(0h0))
when _T_1509 :
node _T_1510 = eq(_T_1507, UInt<1>(0h0))
when _T_1510 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:112)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1507, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<21>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1511 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1512 = and(io.in.d.ready, io.in.d.valid)
node _T_1513 = or(_T_1511, _T_1512)
when _T_1513 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_72( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_63 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_69 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_75 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31]
wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31]
wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h26; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31]
wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31]
wire _source_ok_T_29 = io_in_a_bits_source_0 == 7'h2F; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31]
wire _source_ok_T_30 = io_in_a_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_11 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_12 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h2B; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_13 = _source_ok_T_33; // @[Parameters.scala:1138:31]
wire _source_ok_T_34 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_14 = _source_ok_T_34; // @[Parameters.scala:1138:31]
wire _source_ok_T_35 = io_in_a_bits_source_0 == 7'h29; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_15 = _source_ok_T_35; // @[Parameters.scala:1138:31]
wire _source_ok_T_36 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_16 = _source_ok_T_36; // @[Parameters.scala:1138:31]
wire _source_ok_T_37 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_17 = _source_ok_T_37; // @[Parameters.scala:1138:31]
wire _source_ok_T_38 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_18 = _source_ok_T_38; // @[Parameters.scala:1138:31]
wire _source_ok_T_39 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_19 = _source_ok_T_39; // @[Parameters.scala:1138:31]
wire _source_ok_T_40 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_41 = _source_ok_T_40 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_50 = _source_ok_T_49 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_56 = _source_ok_T_55 | _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_57 = _source_ok_T_56 | _source_ok_WIRE_18; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_57 | _source_ok_WIRE_19; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_58 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_58; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_59 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_65 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_71 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_77 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_60 = _source_ok_T_59 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_64 = _source_ok_T_62; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_64; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_66 = _source_ok_T_65 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_70 = _source_ok_T_68; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_70; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_72 = _source_ok_T_71 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_76 = _source_ok_T_74; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_76; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_78 = _source_ok_T_77 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_82; // @[Parameters.scala:1138:31]
wire _source_ok_T_83 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_5 = _source_ok_T_83; // @[Parameters.scala:1138:31]
wire _source_ok_T_84 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_84; // @[Parameters.scala:1138:31]
wire _source_ok_T_85 = io_in_d_bits_source_0 == 7'h26; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_85; // @[Parameters.scala:1138:31]
wire _source_ok_T_86 = io_in_d_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_86; // @[Parameters.scala:1138:31]
wire _source_ok_T_87 = io_in_d_bits_source_0 == 7'h2F; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_9 = _source_ok_T_87; // @[Parameters.scala:1138:31]
wire _source_ok_T_88 = io_in_d_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_10 = _source_ok_T_88; // @[Parameters.scala:1138:31]
wire _source_ok_T_89 = io_in_d_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_11 = _source_ok_T_89; // @[Parameters.scala:1138:31]
wire _source_ok_T_90 = io_in_d_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_12 = _source_ok_T_90; // @[Parameters.scala:1138:31]
wire _source_ok_T_91 = io_in_d_bits_source_0 == 7'h2B; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_13 = _source_ok_T_91; // @[Parameters.scala:1138:31]
wire _source_ok_T_92 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_14 = _source_ok_T_92; // @[Parameters.scala:1138:31]
wire _source_ok_T_93 = io_in_d_bits_source_0 == 7'h29; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_15 = _source_ok_T_93; // @[Parameters.scala:1138:31]
wire _source_ok_T_94 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_16 = _source_ok_T_94; // @[Parameters.scala:1138:31]
wire _source_ok_T_95 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_17 = _source_ok_T_95; // @[Parameters.scala:1138:31]
wire _source_ok_T_96 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_18 = _source_ok_T_96; // @[Parameters.scala:1138:31]
wire _source_ok_T_97 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_19 = _source_ok_T_97; // @[Parameters.scala:1138:31]
wire _source_ok_T_98 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_100 = _source_ok_T_99 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_101 = _source_ok_T_100 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_102 = _source_ok_T_101 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_103 = _source_ok_T_102 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_104 = _source_ok_T_103 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_105 = _source_ok_T_104 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_106 = _source_ok_T_105 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_107 = _source_ok_T_106 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_108 = _source_ok_T_107 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_109 = _source_ok_T_108 | _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_110 = _source_ok_T_109 | _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_111 = _source_ok_T_110 | _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_112 = _source_ok_T_111 | _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_113 = _source_ok_T_112 | _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_114 = _source_ok_T_113 | _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_115 = _source_ok_T_114 | _source_ok_WIRE_1_18; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_115 | _source_ok_WIRE_1_19; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1445 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1445; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1445; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [20:0] address; // @[Monitor.scala:391:22]
wire _T_1513 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1513; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1513; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1513; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [259:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1378 = _T_1445 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1378 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1378 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1378 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1378 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1378 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1424 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1424 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1393 = _T_1513 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1393 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1393 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1393 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1489 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1489 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1471 = _T_1513 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1471 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1471 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1471 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_101 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0)
node _source_ok_T = shr(io.in.a.bits.source, 11)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits = bits(_uncommonBits_T, 10, 0)
node _T_4 = shr(io.in.a.bits.source, 11)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<11>(0h40f))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0)
node _T_24 = shr(io.in.a.bits.source, 11)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<13>(0h1000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<13>(0h1000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0)
node _T_86 = shr(io.in.a.bits.source, 11)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<13>(0h1000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<13>(0h1000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0)
node _T_152 = shr(io.in.a.bits.source, 11)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<13>(0h1000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0)
node _T_199 = shr(io.in.a.bits.source, 11)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<13>(0h1000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0)
node _T_240 = shr(io.in.a.bits.source, 11)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<13>(0h1000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0)
node _T_283 = shr(io.in.a.bits.source, 11)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<13>(0h1000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0)
node _T_321 = shr(io.in.a.bits.source, 11)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<13>(0h1000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0)
node _T_359 = shr(io.in.a.bits.source, 11)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<13>(0h1000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 11)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<21>(0h0)
connect _WIRE.bits.source, UInt<11>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<21>(0h0)
connect _WIRE_2.bits.source, UInt<11>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0)
regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0)
regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1040>
connect a_set, UInt<1040>(0h0)
wire a_set_wo_ready : UInt<1040>
connect a_set_wo_ready, UInt<1040>(0h0)
wire a_opcodes_set : UInt<4160>
connect a_opcodes_set, UInt<4160>(0h0)
wire a_sizes_set : UInt<4160>
connect a_sizes_set, UInt<4160>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1040>
connect d_clr, UInt<1040>(0h0)
wire d_clr_wo_ready : UInt<1040>
connect d_clr_wo_ready, UInt<1040>(0h0)
wire d_opcodes_clr : UInt<4160>
connect d_opcodes_clr, UInt<4160>(0h0)
wire d_sizes_clr : UInt<4160>
connect d_sizes_clr, UInt<4160>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_205
node _T_656 = orr(inflight)
node _T_657 = eq(_T_656, UInt<1>(0h0))
node _T_658 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_659 = or(_T_657, _T_658)
node _T_660 = lt(watchdog, plusarg_reader.out)
node _T_661 = or(_T_659, _T_660)
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_661, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_665 = and(io.in.a.ready, io.in.a.valid)
node _T_666 = and(io.in.d.ready, io.in.d.valid)
node _T_667 = or(_T_665, _T_666)
when _T_667 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0)
regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0)
regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<21>(0h0)
connect _c_first_WIRE.bits.source, UInt<11>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<11>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1040>
connect c_set, UInt<1040>(0h0)
wire c_set_wo_ready : UInt<1040>
connect c_set_wo_ready, UInt<1040>(0h0)
wire c_opcodes_set : UInt<4160>
connect c_opcodes_set, UInt<4160>(0h0)
wire c_sizes_set : UInt<4160>
connect c_sizes_set, UInt<4160>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<21>(0h0)
connect _WIRE_6.bits.source, UInt<11>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_668 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<21>(0h0)
connect _WIRE_8.bits.source, UInt<11>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_669 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_670 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_671 = and(_T_669, _T_670)
node _T_672 = and(_T_668, _T_671)
when _T_672 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<21>(0h0)
connect _WIRE_10.bits.source, UInt<11>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_673 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_674 = and(_T_673, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<21>(0h0)
connect _WIRE_12.bits.source, UInt<11>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_675 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_676 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_677 = and(_T_675, _T_676)
node _T_678 = and(_T_674, _T_677)
when _T_678 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<21>(0h0)
connect _WIRE_14.bits.source, UInt<11>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_679 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_680 = bits(_T_679, 0, 0)
node _T_681 = eq(_T_680, UInt<1>(0h0))
node _T_682 = asUInt(reset)
node _T_683 = eq(_T_682, UInt<1>(0h0))
when _T_683 :
node _T_684 = eq(_T_681, UInt<1>(0h0))
when _T_684 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_681, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1040>
connect d_clr_1, UInt<1040>(0h0)
wire d_clr_wo_ready_1 : UInt<1040>
connect d_clr_wo_ready_1, UInt<1040>(0h0)
wire d_opcodes_clr_1 : UInt<4160>
connect d_opcodes_clr_1, UInt<4160>(0h0)
wire d_sizes_clr_1 : UInt<4160>
connect d_sizes_clr_1, UInt<4160>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_685 = and(io.in.d.valid, d_first_2)
node _T_686 = and(_T_685, UInt<1>(0h1))
node _T_687 = and(_T_686, d_release_ack_1)
when _T_687 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_688 = and(io.in.d.ready, io.in.d.valid)
node _T_689 = and(_T_688, d_first_2)
node _T_690 = and(_T_689, UInt<1>(0h1))
node _T_691 = and(_T_690, d_release_ack_1)
when _T_691 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_695 = dshr(inflight_1, io.in.d.bits.source)
node _T_696 = bits(_T_695, 0, 0)
node _T_697 = or(_T_696, same_cycle_resp_1)
node _T_698 = asUInt(reset)
node _T_699 = eq(_T_698, UInt<1>(0h0))
when _T_699 :
node _T_700 = eq(_T_697, UInt<1>(0h0))
when _T_700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_697, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<21>(0h0)
connect _WIRE_16.bits.source, UInt<11>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_701 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_702 = asUInt(reset)
node _T_703 = eq(_T_702, UInt<1>(0h0))
when _T_703 :
node _T_704 = eq(_T_701, UInt<1>(0h0))
when _T_704 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_701, UInt<1>(0h1), "") : assert_108
else :
node _T_705 = eq(io.in.d.bits.size, c_size_lookup)
node _T_706 = asUInt(reset)
node _T_707 = eq(_T_706, UInt<1>(0h0))
when _T_707 :
node _T_708 = eq(_T_705, UInt<1>(0h0))
when _T_708 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_705, UInt<1>(0h1), "") : assert_109
node _T_709 = and(io.in.d.valid, d_first_2)
node _T_710 = and(_T_709, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<21>(0h0)
connect _WIRE_18.bits.source, UInt<11>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_711 = and(_T_710, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<21>(0h0)
connect _WIRE_20.bits.source, UInt<11>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_712 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_713 = and(_T_711, _T_712)
node _T_714 = and(_T_713, d_release_ack_1)
node _T_715 = eq(c_probe_ack, UInt<1>(0h0))
node _T_716 = and(_T_714, _T_715)
when _T_716 :
node _T_717 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<21>(0h0)
connect _WIRE_22.bits.source, UInt<11>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_718 = or(_T_717, _WIRE_23.ready)
node _T_719 = asUInt(reset)
node _T_720 = eq(_T_719, UInt<1>(0h0))
when _T_720 :
node _T_721 = eq(_T_718, UInt<1>(0h0))
when _T_721 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_718, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_206
node _T_722 = orr(inflight_1)
node _T_723 = eq(_T_722, UInt<1>(0h0))
node _T_724 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_725 = or(_T_723, _T_724)
node _T_726 = lt(watchdog_1, plusarg_reader_1.out)
node _T_727 = or(_T_725, _T_726)
node _T_728 = asUInt(reset)
node _T_729 = eq(_T_728, UInt<1>(0h0))
when _T_729 :
node _T_730 = eq(_T_727, UInt<1>(0h0))
when _T_730 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:74:24)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_727, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<21>(0h0)
connect _WIRE_24.bits.source, UInt<11>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_731 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_732 = and(io.in.d.ready, io.in.d.valid)
node _T_733 = or(_T_731, _T_732)
when _T_733 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_101( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_d_bits_source, // @[Monitor.scala:20:14]
input [63:0] io_in_d_bits_data // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [10:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10]
wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32]
wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_first_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_first_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_wo_ready_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_wo_ready_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_interm_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_interm_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_opcodes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_opcodes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_sizes_set_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_sizes_set_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _c_probe_ack_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _c_probe_ack_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_1_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_2_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_3_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [10:0] _same_cycle_resp_WIRE_4_bits_source = 11'h0; // @[Bundles.scala:265:74]
wire [10:0] _same_cycle_resp_WIRE_5_bits_source = 11'h0; // @[Bundles.scala:265:61]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_beats1_decode_T_2 = 3'h0; // @[package.scala:243:46]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [16385:0] _c_sizes_set_T_1 = 16386'h0; // @[Monitor.scala:768:52]
wire [13:0] _c_opcodes_set_T = 14'h0; // @[Monitor.scala:767:79]
wire [13:0] _c_sizes_set_T = 14'h0; // @[Monitor.scala:768:77]
wire [16386:0] _c_opcodes_set_T_1 = 16387'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [2047:0] _c_set_wo_ready_T = 2048'h1; // @[OneHot.scala:58:35]
wire [2047:0] _c_set_T = 2048'h1; // @[OneHot.scala:58:35]
wire [4159:0] c_opcodes_set = 4160'h0; // @[Monitor.scala:740:34]
wire [4159:0] c_sizes_set = 4160'h0; // @[Monitor.scala:741:34]
wire [1039:0] c_set = 1040'h0; // @[Monitor.scala:738:34]
wire [1039:0] c_set_wo_ready = 1040'h0; // @[Monitor.scala:739:34]
wire [2:0] _c_first_beats1_decode_T_1 = 3'h7; // @[package.scala:243:76]
wire [5:0] _c_first_beats1_decode_T = 6'h7; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [10:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [10:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_4 = source_ok_uncommonBits < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31]
wire [5:0] _GEN = 6'h7 << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [5:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [2:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [20:0] _is_aligned_T = {18'h0, io_in_a_bits_address_0[2:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}]
wire [2:0] _mask_sizeOH_T = {1'h0, io_in_a_bits_size_0}; // @[Misc.scala:202:34]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = &io_in_a_bits_size_0; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [10:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}]
wire [10:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}]
wire [10:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_10 = source_ok_uncommonBits_1 < 11'h410; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20]
wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31]
wire _T_665 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_665; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_665; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [10:0] source; // @[Monitor.scala:390:22]
reg [20:0] address; // @[Monitor.scala:391:22]
wire _T_733 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_733; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_733; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_733; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [5:0] _GEN_0 = 6'h7 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [2:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [10:0] source_1; // @[Monitor.scala:541:22]
reg [1039:0] inflight; // @[Monitor.scala:614:27]
reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire [1039:0] a_set; // @[Monitor.scala:626:34]
wire [1039:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [4159:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [4159:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [13:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [13:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [13:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [13:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [13:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [13:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [13:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [13:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [13:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [4159:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [4159:0] _a_opcode_lookup_T_6 = {4156'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [4159:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [4159:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [4159:0] _a_size_lookup_T_6 = {4156'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [4159:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[4159:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [2047:0] _GEN_2 = 2048'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [2047:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_598 = _T_665 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_598 ? _a_set_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_598 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [2:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [2:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[2:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_598 ? _a_sizes_set_interm_T_1 : 3'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [13:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [13:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [13:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [16386:0] _a_opcodes_set_T_1 = {16383'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_598 ? _a_opcodes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [16385:0] _a_sizes_set_T_1 = {16383'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_598 ? _a_sizes_set_T_1[4159:0] : 4160'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [1039:0] d_clr; // @[Monitor.scala:664:34]
wire [1039:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [4159:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [4159:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_644 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [2047:0] _GEN_5 = 2048'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [2047:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_644 & ~d_release_ack ? _d_clr_wo_ready_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_613 = _T_733 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_613 ? _d_clr_T[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [16398:0] _d_opcodes_clr_T_5 = 16399'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_613 ? _d_opcodes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [16398:0] _d_sizes_clr_T_5 = 16399'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_613 ? _d_sizes_clr_T_5[4159:0] : 4160'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [1039:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [1039:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1039:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [4159:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [4159:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [4159:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [4159:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [4159:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [4159:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1039:0] inflight_1; // @[Monitor.scala:726:35]
wire [1039:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [4159:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [4159:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [4159:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[2:0]; // @[package.scala:243:{71,76}]
wire [2:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [4159:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [4159:0] _c_opcode_lookup_T_6 = {4156'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [4159:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[4159:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [4159:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [4159:0] _c_size_lookup_T_6 = {4156'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [4159:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[4159:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [1039:0] d_clr_1; // @[Monitor.scala:774:34]
wire [1039:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [4159:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [4159:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_709 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_709 & d_release_ack_1 ? _d_clr_wo_ready_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire _T_691 = _T_733 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_691 ? _d_clr_T_1[1039:0] : 1040'h0; // @[OneHot.scala:58:35]
wire [16398:0] _d_opcodes_clr_T_11 = 16399'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_691 ? _d_opcodes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [16398:0] _d_sizes_clr_T_11 = 16399'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_691 ? _d_sizes_clr_T_11[4159:0] : 4160'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 11'h0; // @[Monitor.scala:36:7, :795:113]
wire [1039:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1039:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [4159:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [4159:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [4159:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [4159:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_138 :
input clock : Clock
input reset : Reset
output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[7], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}}
wire next_state : UInt
wire next_uopc : UInt
wire next_lrs1_rtype : UInt
wire next_lrs2_rtype : UInt
regreset state : UInt<2>, clock, reset, UInt<2>(0h0)
regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0)
regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0)
connect p1_poisoned, UInt<1>(0h0)
connect p2_poisoned, UInt<1>(0h0)
node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned)
node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned)
wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}
invalidate slot_uop_uop.debug_tsrc
invalidate slot_uop_uop.debug_fsrc
invalidate slot_uop_uop.bp_xcpt_if
invalidate slot_uop_uop.bp_debug_if
invalidate slot_uop_uop.xcpt_ma_if
invalidate slot_uop_uop.xcpt_ae_if
invalidate slot_uop_uop.xcpt_pf_if
invalidate slot_uop_uop.fp_single
invalidate slot_uop_uop.fp_val
invalidate slot_uop_uop.frs3_en
invalidate slot_uop_uop.lrs2_rtype
invalidate slot_uop_uop.lrs1_rtype
invalidate slot_uop_uop.dst_rtype
invalidate slot_uop_uop.ldst_val
invalidate slot_uop_uop.lrs3
invalidate slot_uop_uop.lrs2
invalidate slot_uop_uop.lrs1
invalidate slot_uop_uop.ldst
invalidate slot_uop_uop.ldst_is_rs1
invalidate slot_uop_uop.flush_on_commit
invalidate slot_uop_uop.is_unique
invalidate slot_uop_uop.is_sys_pc2epc
invalidate slot_uop_uop.uses_stq
invalidate slot_uop_uop.uses_ldq
invalidate slot_uop_uop.is_amo
invalidate slot_uop_uop.is_fencei
invalidate slot_uop_uop.is_fence
invalidate slot_uop_uop.mem_signed
invalidate slot_uop_uop.mem_size
invalidate slot_uop_uop.mem_cmd
invalidate slot_uop_uop.bypassable
invalidate slot_uop_uop.exc_cause
invalidate slot_uop_uop.exception
invalidate slot_uop_uop.stale_pdst
invalidate slot_uop_uop.ppred_busy
invalidate slot_uop_uop.prs3_busy
invalidate slot_uop_uop.prs2_busy
invalidate slot_uop_uop.prs1_busy
invalidate slot_uop_uop.ppred
invalidate slot_uop_uop.prs3
invalidate slot_uop_uop.prs2
invalidate slot_uop_uop.prs1
invalidate slot_uop_uop.pdst
invalidate slot_uop_uop.rxq_idx
invalidate slot_uop_uop.stq_idx
invalidate slot_uop_uop.ldq_idx
invalidate slot_uop_uop.rob_idx
invalidate slot_uop_uop.csr_addr
invalidate slot_uop_uop.imm_packed
invalidate slot_uop_uop.taken
invalidate slot_uop_uop.pc_lob
invalidate slot_uop_uop.edge_inst
invalidate slot_uop_uop.ftq_idx
invalidate slot_uop_uop.br_tag
invalidate slot_uop_uop.br_mask
invalidate slot_uop_uop.is_sfb
invalidate slot_uop_uop.is_jal
invalidate slot_uop_uop.is_jalr
invalidate slot_uop_uop.is_br
invalidate slot_uop_uop.iw_p2_poisoned
invalidate slot_uop_uop.iw_p1_poisoned
invalidate slot_uop_uop.iw_state
invalidate slot_uop_uop.ctrl.is_std
invalidate slot_uop_uop.ctrl.is_sta
invalidate slot_uop_uop.ctrl.is_load
invalidate slot_uop_uop.ctrl.csr_cmd
invalidate slot_uop_uop.ctrl.fcn_dw
invalidate slot_uop_uop.ctrl.op_fcn
invalidate slot_uop_uop.ctrl.imm_sel
invalidate slot_uop_uop.ctrl.op2_sel
invalidate slot_uop_uop.ctrl.op1_sel
invalidate slot_uop_uop.ctrl.br_type
invalidate slot_uop_uop.fu_code
invalidate slot_uop_uop.iq_type
invalidate slot_uop_uop.debug_pc
invalidate slot_uop_uop.is_rvc
invalidate slot_uop_uop.debug_inst
invalidate slot_uop_uop.inst
invalidate slot_uop_uop.uopc
connect slot_uop_uop.uopc, UInt<7>(0h0)
connect slot_uop_uop.bypassable, UInt<1>(0h0)
connect slot_uop_uop.fp_val, UInt<1>(0h0)
connect slot_uop_uop.uses_stq, UInt<1>(0h0)
connect slot_uop_uop.uses_ldq, UInt<1>(0h0)
connect slot_uop_uop.pdst, UInt<1>(0h0)
connect slot_uop_uop.dst_rtype, UInt<2>(0h2)
wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}
invalidate slot_uop_cs.is_std
invalidate slot_uop_cs.is_sta
invalidate slot_uop_cs.is_load
invalidate slot_uop_cs.csr_cmd
invalidate slot_uop_cs.fcn_dw
invalidate slot_uop_cs.op_fcn
invalidate slot_uop_cs.imm_sel
invalidate slot_uop_cs.op2_sel
invalidate slot_uop_cs.op1_sel
invalidate slot_uop_cs.br_type
connect slot_uop_cs.br_type, UInt<4>(0h0)
connect slot_uop_cs.csr_cmd, UInt<3>(0h0)
connect slot_uop_cs.is_load, UInt<1>(0h0)
connect slot_uop_cs.is_sta, UInt<1>(0h0)
connect slot_uop_cs.is_std, UInt<1>(0h0)
connect slot_uop_uop.ctrl, slot_uop_cs
regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop
node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop)
when io.kill :
connect state, UInt<2>(0h0)
else :
when io.in_uop.valid :
connect state, io.in_uop.bits.iw_state
else :
when io.clear :
connect state, UInt<2>(0h0)
else :
connect state, next_state
connect next_state, state
connect next_uopc, slot_uop.uopc
connect next_lrs1_rtype, slot_uop.lrs1_rtype
connect next_lrs2_rtype, slot_uop.lrs2_rtype
when io.kill :
connect next_state, UInt<2>(0h0)
else :
node _T = eq(state, UInt<2>(0h1))
node _T_1 = and(io.grant, _T)
node _T_2 = eq(state, UInt<2>(0h2))
node _T_3 = and(io.grant, _T_2)
node _T_4 = and(_T_3, p1)
node _T_5 = and(_T_4, p2)
node _T_6 = and(_T_5, ppred)
node _T_7 = or(_T_1, _T_6)
when _T_7 :
node _T_8 = or(p1_poisoned, p2_poisoned)
node _T_9 = and(io.ldspec_miss, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
connect next_state, UInt<2>(0h0)
else :
node _T_11 = eq(state, UInt<2>(0h2))
node _T_12 = and(io.grant, _T_11)
when _T_12 :
node _T_13 = or(p1_poisoned, p2_poisoned)
node _T_14 = and(io.ldspec_miss, _T_13)
node _T_15 = eq(_T_14, UInt<1>(0h0))
when _T_15 :
connect next_state, UInt<2>(0h1)
when p1 :
connect slot_uop.uopc, UInt<7>(0h3)
connect next_uopc, UInt<7>(0h3)
connect slot_uop.lrs1_rtype, UInt<2>(0h2)
connect next_lrs1_rtype, UInt<2>(0h2)
else :
connect slot_uop.lrs2_rtype, UInt<2>(0h2)
connect next_lrs2_rtype, UInt<2>(0h2)
when io.in_uop.valid :
connect slot_uop, io.in_uop.bits
node _T_16 = eq(state, UInt<2>(0h0))
node _T_17 = or(_T_16, io.clear)
node _T_18 = or(_T_17, io.kill)
node _T_19 = asUInt(reset)
node _T_20 = eq(_T_19, UInt<1>(0h0))
when _T_20 :
node _T_21 = eq(_T_18, UInt<1>(0h0))
when _T_21 :
printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf
assert(clock, _T_18, UInt<1>(0h1), "") : assert
wire next_p1 : UInt<1>
connect next_p1, p1
wire next_p2 : UInt<1>
connect next_p2, p2
wire next_p3 : UInt<1>
connect next_p3, p3
wire next_ppred : UInt<1>
connect next_ppred, ppred
when io.in_uop.valid :
node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0))
connect p1, _p1_T
node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0))
connect p2, _p2_T
node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0))
connect p3, _p3_T
node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0))
connect ppred, _ppred_T
node _T_22 = and(io.ldspec_miss, next_p1_poisoned)
when _T_22 :
node _T_23 = neq(next_uop.prs1, UInt<1>(0h0))
node _T_24 = asUInt(reset)
node _T_25 = eq(_T_24, UInt<1>(0h0))
when _T_25 :
node _T_26 = eq(_T_23, UInt<1>(0h0))
when _T_26 :
printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1
assert(clock, _T_23, UInt<1>(0h1), "") : assert_1
connect p1, UInt<1>(0h0)
node _T_27 = and(io.ldspec_miss, next_p2_poisoned)
when _T_27 :
node _T_28 = neq(next_uop.prs2, UInt<1>(0h0))
node _T_29 = asUInt(reset)
node _T_30 = eq(_T_29, UInt<1>(0h0))
when _T_30 :
node _T_31 = eq(_T_28, UInt<1>(0h0))
when _T_31 :
printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2
assert(clock, _T_28, UInt<1>(0h1), "") : assert_2
connect p2, UInt<1>(0h0)
node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1)
node _T_33 = and(io.wakeup_ports[0].valid, _T_32)
when _T_33 :
connect p1, UInt<1>(0h1)
node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2)
node _T_35 = and(io.wakeup_ports[0].valid, _T_34)
when _T_35 :
connect p2, UInt<1>(0h1)
node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3)
node _T_37 = and(io.wakeup_ports[0].valid, _T_36)
when _T_37 :
connect p3, UInt<1>(0h1)
node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1)
node _T_39 = and(io.wakeup_ports[1].valid, _T_38)
when _T_39 :
connect p1, UInt<1>(0h1)
node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2)
node _T_41 = and(io.wakeup_ports[1].valid, _T_40)
when _T_41 :
connect p2, UInt<1>(0h1)
node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3)
node _T_43 = and(io.wakeup_ports[1].valid, _T_42)
when _T_43 :
connect p3, UInt<1>(0h1)
node _T_44 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs1)
node _T_45 = and(io.wakeup_ports[2].valid, _T_44)
when _T_45 :
connect p1, UInt<1>(0h1)
node _T_46 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs2)
node _T_47 = and(io.wakeup_ports[2].valid, _T_46)
when _T_47 :
connect p2, UInt<1>(0h1)
node _T_48 = eq(io.wakeup_ports[2].bits.pdst, next_uop.prs3)
node _T_49 = and(io.wakeup_ports[2].valid, _T_48)
when _T_49 :
connect p3, UInt<1>(0h1)
node _T_50 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs1)
node _T_51 = and(io.wakeup_ports[3].valid, _T_50)
when _T_51 :
connect p1, UInt<1>(0h1)
node _T_52 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs2)
node _T_53 = and(io.wakeup_ports[3].valid, _T_52)
when _T_53 :
connect p2, UInt<1>(0h1)
node _T_54 = eq(io.wakeup_ports[3].bits.pdst, next_uop.prs3)
node _T_55 = and(io.wakeup_ports[3].valid, _T_54)
when _T_55 :
connect p3, UInt<1>(0h1)
node _T_56 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs1)
node _T_57 = and(io.wakeup_ports[4].valid, _T_56)
when _T_57 :
connect p1, UInt<1>(0h1)
node _T_58 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs2)
node _T_59 = and(io.wakeup_ports[4].valid, _T_58)
when _T_59 :
connect p2, UInt<1>(0h1)
node _T_60 = eq(io.wakeup_ports[4].bits.pdst, next_uop.prs3)
node _T_61 = and(io.wakeup_ports[4].valid, _T_60)
when _T_61 :
connect p3, UInt<1>(0h1)
node _T_62 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs1)
node _T_63 = and(io.wakeup_ports[5].valid, _T_62)
when _T_63 :
connect p1, UInt<1>(0h1)
node _T_64 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs2)
node _T_65 = and(io.wakeup_ports[5].valid, _T_64)
when _T_65 :
connect p2, UInt<1>(0h1)
node _T_66 = eq(io.wakeup_ports[5].bits.pdst, next_uop.prs3)
node _T_67 = and(io.wakeup_ports[5].valid, _T_66)
when _T_67 :
connect p3, UInt<1>(0h1)
node _T_68 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs1)
node _T_69 = and(io.wakeup_ports[6].valid, _T_68)
when _T_69 :
connect p1, UInt<1>(0h1)
node _T_70 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs2)
node _T_71 = and(io.wakeup_ports[6].valid, _T_70)
when _T_71 :
connect p2, UInt<1>(0h1)
node _T_72 = eq(io.wakeup_ports[6].bits.pdst, next_uop.prs3)
node _T_73 = and(io.wakeup_ports[6].valid, _T_72)
when _T_73 :
connect p3, UInt<1>(0h1)
node _T_74 = eq(io.pred_wakeup_port.bits, next_uop.ppred)
node _T_75 = and(io.pred_wakeup_port.valid, _T_74)
when _T_75 :
connect ppred, UInt<1>(0h1)
node _T_76 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0))
node _T_77 = and(io.spec_ld_wakeup[0].valid, _T_76)
node _T_78 = eq(_T_77, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3
assert(clock, _T_78, UInt<1>(0h1), "") : assert_3
node _T_82 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1)
node _T_83 = and(io.spec_ld_wakeup[0].valid, _T_82)
node _T_84 = eq(next_uop.lrs1_rtype, UInt<2>(0h0))
node _T_85 = and(_T_83, _T_84)
when _T_85 :
connect p1, UInt<1>(0h1)
connect p1_poisoned, UInt<1>(0h1)
node _T_86 = eq(next_p1_poisoned, UInt<1>(0h0))
node _T_87 = asUInt(reset)
node _T_88 = eq(_T_87, UInt<1>(0h0))
when _T_88 :
node _T_89 = eq(_T_86, UInt<1>(0h0))
when _T_89 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4
assert(clock, _T_86, UInt<1>(0h1), "") : assert_4
node _T_90 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2)
node _T_91 = and(io.spec_ld_wakeup[0].valid, _T_90)
node _T_92 = eq(next_uop.lrs2_rtype, UInt<2>(0h0))
node _T_93 = and(_T_91, _T_92)
when _T_93 :
connect p2, UInt<1>(0h1)
connect p2_poisoned, UInt<1>(0h1)
node _T_94 = eq(next_p2_poisoned, UInt<1>(0h0))
node _T_95 = asUInt(reset)
node _T_96 = eq(_T_95, UInt<1>(0h0))
when _T_96 :
node _T_97 = eq(_T_94, UInt<1>(0h0))
when _T_97 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5
assert(clock, _T_94, UInt<1>(0h1), "") : assert_5
node _next_br_mask_T = not(io.brupdate.b1.resolve_mask)
node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T)
node _T_98 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask)
node _T_99 = neq(_T_98, UInt<1>(0h0))
when _T_99 :
connect next_state, UInt<2>(0h0)
node _T_100 = eq(io.in_uop.valid, UInt<1>(0h0))
when _T_100 :
connect slot_uop.br_mask, next_br_mask
node _io_request_T = neq(state, UInt<2>(0h0))
node _io_request_T_1 = and(_io_request_T, p1)
node _io_request_T_2 = and(_io_request_T_1, p2)
node _io_request_T_3 = and(_io_request_T_2, p3)
node _io_request_T_4 = and(_io_request_T_3, ppred)
node _io_request_T_5 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5)
connect io.request, _io_request_T_6
node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal)
node high_priority = or(_high_priority_T, slot_uop.is_jalr)
node _io_request_hp_T = and(io.request, high_priority)
connect io.request_hp, _io_request_hp_T
node _T_101 = eq(state, UInt<2>(0h1))
when _T_101 :
node _io_request_T_7 = and(p1, p2)
node _io_request_T_8 = and(_io_request_T_7, p3)
node _io_request_T_9 = and(_io_request_T_8, ppred)
node _io_request_T_10 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10)
connect io.request, _io_request_T_11
else :
node _T_102 = eq(state, UInt<2>(0h2))
when _T_102 :
node _io_request_T_12 = or(p1, p2)
node _io_request_T_13 = and(_io_request_T_12, ppred)
node _io_request_T_14 = eq(io.kill, UInt<1>(0h0))
node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14)
connect io.request, _io_request_T_15
else :
connect io.request, UInt<1>(0h0)
node _io_valid_T = neq(state, UInt<2>(0h0))
connect io.valid, _io_valid_T
connect io.uop, slot_uop
connect io.uop.iw_p1_poisoned, p1_poisoned
connect io.uop.iw_p2_poisoned, p2_poisoned
node _may_vacate_T = eq(state, UInt<2>(0h1))
node _may_vacate_T_1 = eq(state, UInt<2>(0h2))
node _may_vacate_T_2 = and(_may_vacate_T_1, p1)
node _may_vacate_T_3 = and(_may_vacate_T_2, p2)
node _may_vacate_T_4 = and(_may_vacate_T_3, ppred)
node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4)
node may_vacate = and(io.grant, _may_vacate_T_5)
node _squash_grant_T = or(p1_poisoned, p2_poisoned)
node squash_grant = and(io.ldspec_miss, _squash_grant_T)
node _io_will_be_valid_T = neq(state, UInt<2>(0h0))
node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0))
node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1)
node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0))
node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3)
connect io.will_be_valid, _io_will_be_valid_T_4
connect io.out_uop, slot_uop
connect io.out_uop.iw_state, next_state
connect io.out_uop.uopc, next_uopc
connect io.out_uop.lrs1_rtype, next_lrs1_rtype
connect io.out_uop.lrs2_rtype, next_lrs2_rtype
connect io.out_uop.br_mask, next_br_mask
node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0))
connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T
node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0))
connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T
node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0))
connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T
node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0))
connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T
connect io.out_uop.iw_p1_poisoned, p1_poisoned
connect io.out_uop.iw_p2_poisoned, p2_poisoned
node _T_103 = eq(state, UInt<2>(0h2))
when _T_103 :
node _T_104 = and(p1, p2)
node _T_105 = and(_T_104, ppred)
when _T_105 :
skip
else :
node _T_106 = and(p1, ppred)
when _T_106 :
connect io.uop.uopc, slot_uop.uopc
connect io.uop.lrs2_rtype, UInt<2>(0h2)
else :
node _T_107 = and(p2, ppred)
when _T_107 :
connect io.uop.uopc, UInt<7>(0h3)
connect io.uop.lrs1_rtype, UInt<2>(0h2)
connect io.debug.p1, p1
connect io.debug.p2, p2
connect io.debug.p3, p3
connect io.debug.ppred, ppred
connect io.debug.state, state | module IssueSlot_138( // @[issue-slot.scala:69:7]
input clock, // @[issue-slot.scala:69:7]
input reset, // @[issue-slot.scala:69:7]
output io_valid, // @[issue-slot.scala:73:14]
output io_will_be_valid, // @[issue-slot.scala:73:14]
output io_request, // @[issue-slot.scala:73:14]
output io_request_hp, // @[issue-slot.scala:73:14]
input io_grant, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14]
input io_brupdate_b2_valid, // @[issue-slot.scala:73:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:73:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14]
input io_kill, // @[issue-slot.scala:73:14]
input io_clear, // @[issue-slot.scala:73:14]
input io_ldspec_miss, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_0_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_1_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_2_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_2_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_3_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_3_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_4_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_4_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_5_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_5_bits_poisoned, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_valid, // @[issue-slot.scala:73:14]
input [6:0] io_wakeup_ports_6_bits_pdst, // @[issue-slot.scala:73:14]
input io_wakeup_ports_6_bits_poisoned, // @[issue-slot.scala:73:14]
input io_spec_ld_wakeup_0_valid, // @[issue-slot.scala:73:14]
input [6:0] io_spec_ld_wakeup_0_bits, // @[issue-slot.scala:73:14]
input io_in_uop_valid, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14]
input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p1_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_iw_p2_poisoned, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14]
input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:73:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14]
input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:73:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14]
input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14]
input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14]
input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_out_uop_is_br, // @[issue-slot.scala:73:14]
output io_out_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_out_uop_is_jal, // @[issue-slot.scala:73:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_out_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_out_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_out_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_out_uop_is_fence, // @[issue-slot.scala:73:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_out_uop_is_amo, // @[issue-slot.scala:73:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_out_uop_is_unique, // @[issue-slot.scala:73:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14]
output io_out_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_out_uop_fp_val, // @[issue-slot.scala:73:14]
output io_out_uop_fp_single, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14]
output [31:0] io_uop_inst, // @[issue-slot.scala:73:14]
output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14]
output io_uop_is_rvc, // @[issue-slot.scala:73:14]
output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14]
output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14]
output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14]
output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14]
output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14]
output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14]
output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14]
output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14]
output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14]
output io_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14]
output io_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14]
output io_uop_is_br, // @[issue-slot.scala:73:14]
output io_uop_is_jalr, // @[issue-slot.scala:73:14]
output io_uop_is_jal, // @[issue-slot.scala:73:14]
output io_uop_is_sfb, // @[issue-slot.scala:73:14]
output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14]
output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14]
output io_uop_edge_inst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14]
output io_uop_taken, // @[issue-slot.scala:73:14]
output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14]
output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14]
output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14]
output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14]
output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14]
output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14]
output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14]
output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14]
output io_uop_prs1_busy, // @[issue-slot.scala:73:14]
output io_uop_prs2_busy, // @[issue-slot.scala:73:14]
output io_uop_prs3_busy, // @[issue-slot.scala:73:14]
output io_uop_ppred_busy, // @[issue-slot.scala:73:14]
output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14]
output io_uop_exception, // @[issue-slot.scala:73:14]
output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14]
output io_uop_bypassable, // @[issue-slot.scala:73:14]
output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14]
output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14]
output io_uop_mem_signed, // @[issue-slot.scala:73:14]
output io_uop_is_fence, // @[issue-slot.scala:73:14]
output io_uop_is_fencei, // @[issue-slot.scala:73:14]
output io_uop_is_amo, // @[issue-slot.scala:73:14]
output io_uop_uses_ldq, // @[issue-slot.scala:73:14]
output io_uop_uses_stq, // @[issue-slot.scala:73:14]
output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14]
output io_uop_is_unique, // @[issue-slot.scala:73:14]
output io_uop_flush_on_commit, // @[issue-slot.scala:73:14]
output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14]
output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14]
output io_uop_ldst_val, // @[issue-slot.scala:73:14]
output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14]
output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14]
output io_uop_frs3_en, // @[issue-slot.scala:73:14]
output io_uop_fp_val, // @[issue-slot.scala:73:14]
output io_uop_fp_single, // @[issue-slot.scala:73:14]
output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14]
output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14]
output io_uop_bp_debug_if, // @[issue-slot.scala:73:14]
output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14]
output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14]
output io_debug_p1, // @[issue-slot.scala:73:14]
output io_debug_p2, // @[issue-slot.scala:73:14]
output io_debug_p3, // @[issue-slot.scala:73:14]
output io_debug_ppred, // @[issue-slot.scala:73:14]
output [1:0] io_debug_state // @[issue-slot.scala:73:14]
);
wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7]
wire io_ldspec_miss_0 = io_ldspec_miss; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_0_bits_poisoned_0 = io_wakeup_ports_0_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_1_bits_poisoned_0 = io_wakeup_ports_1_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_valid_0 = io_wakeup_ports_2_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_2_bits_pdst_0 = io_wakeup_ports_2_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_2_bits_poisoned_0 = io_wakeup_ports_2_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_valid_0 = io_wakeup_ports_3_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_3_bits_pdst_0 = io_wakeup_ports_3_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_3_bits_poisoned_0 = io_wakeup_ports_3_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_valid_0 = io_wakeup_ports_4_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_4_bits_pdst_0 = io_wakeup_ports_4_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_4_bits_poisoned_0 = io_wakeup_ports_4_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_valid_0 = io_wakeup_ports_5_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_5_bits_pdst_0 = io_wakeup_ports_5_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_5_bits_poisoned_0 = io_wakeup_ports_5_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_valid_0 = io_wakeup_ports_6_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_wakeup_ports_6_bits_pdst_0 = io_wakeup_ports_6_bits_pdst; // @[issue-slot.scala:69:7]
wire io_wakeup_ports_6_bits_poisoned_0 = io_wakeup_ports_6_bits_poisoned; // @[issue-slot.scala:69:7]
wire io_spec_ld_wakeup_0_valid_0 = io_spec_ld_wakeup_0_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_spec_ld_wakeup_0_bits_0 = io_spec_ld_wakeup_0_bits; // @[issue-slot.scala:69:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7]
wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7]
wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p1_poisoned_0 = io_in_uop_bits_iw_p1_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_iw_p2_poisoned_0 = io_in_uop_bits_iw_p2_poisoned; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7]
wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7]
wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7]
wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7]
wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19]
wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18]
wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7]
wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19]
wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19]
wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18]
wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19]
wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18]
wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19]
wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18]
wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19]
wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19]
wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19]
wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19]
wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19]
wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19]
wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19]
wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19]
wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19]
wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19]
wire _io_valid_T; // @[issue-slot.scala:79:24]
wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32]
wire _io_request_hp_T; // @[issue-slot.scala:243:31]
wire [6:0] next_uopc; // @[issue-slot.scala:82:29]
wire [1:0] next_state; // @[issue-slot.scala:81:29]
wire [15:0] next_br_mask; // @[util.scala:85:25]
wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28]
wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28]
wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28]
wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28]
wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29]
wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29]
wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7]
wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7]
wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7]
wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7]
wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7]
wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7]
wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p1_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_iw_p2_poisoned_0; // @[issue-slot.scala:69:7]
wire io_uop_is_br_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7]
wire io_uop_is_jal_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7]
wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7]
wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7]
wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7]
wire io_uop_taken_0; // @[issue-slot.scala:69:7]
wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7]
wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7]
wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7]
wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7]
wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7]
wire io_uop_exception_0; // @[issue-slot.scala:69:7]
wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7]
wire io_uop_bypassable_0; // @[issue-slot.scala:69:7]
wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7]
wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fence_0; // @[issue-slot.scala:69:7]
wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7]
wire io_uop_is_amo_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7]
wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7]
wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7]
wire io_uop_is_unique_0; // @[issue-slot.scala:69:7]
wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7]
wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7]
wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7]
wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_val_0; // @[issue-slot.scala:69:7]
wire io_uop_fp_single_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7]
wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7]
wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7]
wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7]
wire io_debug_p1_0; // @[issue-slot.scala:69:7]
wire io_debug_p2_0; // @[issue-slot.scala:69:7]
wire io_debug_p3_0; // @[issue-slot.scala:69:7]
wire io_debug_ppred_0; // @[issue-slot.scala:69:7]
wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7]
wire io_valid_0; // @[issue-slot.scala:69:7]
wire io_will_be_valid_0; // @[issue-slot.scala:69:7]
wire io_request_0; // @[issue-slot.scala:69:7]
wire io_request_hp_0; // @[issue-slot.scala:69:7]
assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29]
assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29]
assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29]
assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29]
reg [1:0] state; // @[issue-slot.scala:86:22]
assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22]
reg p1; // @[issue-slot.scala:87:22]
assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22]
wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25]
reg p2; // @[issue-slot.scala:88:22]
assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22]
wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25]
reg p3; // @[issue-slot.scala:89:22]
assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22]
wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25]
reg ppred; // @[issue-slot.scala:90:22]
assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22]
wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28]
reg p1_poisoned; // @[issue-slot.scala:95:28]
assign io_out_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
assign io_uop_iw_p1_poisoned_0 = p1_poisoned; // @[issue-slot.scala:69:7, :95:28]
reg p2_poisoned; // @[issue-slot.scala:96:28]
assign io_out_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
assign io_uop_iw_p2_poisoned_0 = p2_poisoned; // @[issue-slot.scala:69:7, :96:28]
wire next_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : p1_poisoned; // @[issue-slot.scala:69:7, :95:28, :99:29]
wire next_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : p2_poisoned; // @[issue-slot.scala:69:7, :96:28, :100:29]
reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_rvc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25]
assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25]
reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25]
assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25]
reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25]
assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25]
assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25]
reg slot_uop_is_br; // @[issue-slot.scala:102:25]
assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jalr; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_jal; // @[issue-slot.scala:102:25]
assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sfb; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25]
reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25]
assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25]
assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_edge_inst; // @[issue-slot.scala:102:25]
assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25]
assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_taken; // @[issue-slot.scala:102:25]
assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25]
assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25]
reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25]
assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25]
assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25]
assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25]
assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25]
assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25]
assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25]
assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25]
assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25]
assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_exception; // @[issue-slot.scala:102:25]
assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25]
assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bypassable; // @[issue-slot.scala:102:25]
assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_mem_signed; // @[issue-slot.scala:102:25]
assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fence; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_fencei; // @[issue-slot.scala:102:25]
assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_amo; // @[issue-slot.scala:102:25]
assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_uses_stq; // @[issue-slot.scala:102:25]
assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25]
assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_is_unique; // @[issue-slot.scala:102:25]
assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25]
assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25]
assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_ldst_val; // @[issue-slot.scala:102:25]
assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25]
assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25]
reg slot_uop_frs3_en; // @[issue-slot.scala:102:25]
assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_val; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_fp_single; // @[issue-slot.scala:102:25]
assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25]
assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25]
assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25]
reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25]
assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25]
wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p1_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p1_poisoned_0 : slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_iw_p2_poisoned = io_in_uop_valid_0 ? io_in_uop_bits_iw_p2_poisoned_0 : slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21]
wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25]
wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}]
wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25]
wire _T_14 = io_ldspec_miss_0 & (p1_poisoned | p2_poisoned); // @[issue-slot.scala:69:7, :95:28, :96:28, :140:{28,44}]
wire _GEN = _T_12 & ~_T_14; // @[issue-slot.scala:126:14, :139:{25,51}, :140:{11,28,62}, :141:18]
wire _GEN_0 = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51]
wire _GEN_1 = _GEN_0 | ~(_T_12 & ~_T_14 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:{11,28,62}, :142:17, :143:23]
assign next_uopc = _GEN_1 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51]
assign next_lrs1_rtype = _GEN_1 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51]
wire _GEN_2 = _GEN_0 | ~_GEN | p1; // @[issue-slot.scala:87:22, :102:25, :126:14, :131:18, :134:63, :139:51, :140:62, :141:18, :142:17]
assign next_lrs2_rtype = _GEN_2 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
wire _p1_T = ~io_in_uop_bits_prs1_busy_0; // @[issue-slot.scala:69:7, :169:11]
wire _p2_T = ~io_in_uop_bits_prs2_busy_0; // @[issue-slot.scala:69:7, :170:11]
wire _p3_T = ~io_in_uop_bits_prs3_busy_0; // @[issue-slot.scala:69:7, :171:11]
wire _ppred_T = ~io_in_uop_bits_ppred_busy_0; // @[issue-slot.scala:69:7, :172:14]
wire _T_22 = io_ldspec_miss_0 & next_p1_poisoned; // @[issue-slot.scala:69:7, :99:29, :175:24]
wire _T_27 = io_ldspec_miss_0 & next_p2_poisoned; // @[issue-slot.scala:69:7, :100:29, :179:24]
wire _T_85 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs1 & next_uop_lrs1_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :209:38, :210:{33,51}, :211:27]
wire _T_93 = io_spec_ld_wakeup_0_valid_0 & io_spec_ld_wakeup_0_bits_0 == next_uop_prs2 & next_uop_lrs2_rtype == 2'h0; // @[issue-slot.scala:69:7, :103:21, :216:38, :217:{33,51}, :218:27] |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_201 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_201( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_136 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_146
connect io_out_source_valid_0.clock, clock
connect io_out_source_valid_0.reset, reset
connect io_out_source_valid_0.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid_0.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_136( // @[AsyncQueue.scala:58:7]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in = 1'h1; // @[ShiftReg.scala:45:23]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_146 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ReRoCCManagerTile_1 :
input clock : Clock
input reset : Reset
output auto : { flip ctrl_ctrl_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<12>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, buffer_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip re_ro_cc_in : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}}, flip rerocc_manager_id_sink_in : UInt<7>}
inst accumulator of AccumulatorExample_1
connect accumulator.clock, clock
connect accumulator.reset, reset
inst rerocc_manager of ReRoCCManager_1
connect rerocc_manager.clock, clock
connect rerocc_manager.reset, reset
inst rerocc_buffer of ReRoCCBuffer_2
connect rerocc_buffer.clock, clock
connect rerocc_buffer.reset, reset
inst xbar of TLXbar_i1_o1_a32d64s1k3z4c_1
connect xbar.clock, clock
connect xbar.reset, reset
inst buffer of TLBuffer_a32d64s1k3z4c_5
connect buffer.clock, clock
connect buffer.reset, reset
inst dcache of MiniDCache_1
connect dcache.clock, clock
connect dcache.reset, reset
inst widget of TLWidthWidget8_17
connect widget.clock, clock
connect widget.reset, reset
inst ctrl of ReRoCCManagerControl_1
connect ctrl.clock, clock
connect ctrl.reset, reset
wire reroccManagerIdSinkNodeIn : UInt<7>
invalidate reroccManagerIdSinkNodeIn
wire reRoCCNodeOut : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}}
invalidate reRoCCNodeOut.resp.bits.data
invalidate reRoCCNodeOut.resp.bits.manager_id
invalidate reRoCCNodeOut.resp.bits.client_id
invalidate reRoCCNodeOut.resp.bits.opcode
invalidate reRoCCNodeOut.resp.valid
invalidate reRoCCNodeOut.resp.ready
invalidate reRoCCNodeOut.req.bits.data
invalidate reRoCCNodeOut.req.bits.manager_id
invalidate reRoCCNodeOut.req.bits.client_id
invalidate reRoCCNodeOut.req.bits.opcode
invalidate reRoCCNodeOut.req.valid
invalidate reRoCCNodeOut.req.ready
wire reRoCCNodeIn : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}}
invalidate reRoCCNodeIn.resp.bits.data
invalidate reRoCCNodeIn.resp.bits.manager_id
invalidate reRoCCNodeIn.resp.bits.client_id
invalidate reRoCCNodeIn.resp.bits.opcode
invalidate reRoCCNodeIn.resp.valid
invalidate reRoCCNodeIn.resp.ready
invalidate reRoCCNodeIn.req.bits.data
invalidate reRoCCNodeIn.req.bits.manager_id
invalidate reRoCCNodeIn.req.bits.client_id
invalidate reRoCCNodeIn.req.bits.opcode
invalidate reRoCCNodeIn.req.valid
invalidate reRoCCNodeIn.req.ready
connect reRoCCNodeOut, reRoCCNodeIn
connect rerocc_buffer.auto.in, reRoCCNodeOut
connect rerocc_manager.auto.in, rerocc_buffer.auto.out
connect buffer.auto.in, xbar.auto.anon_out
connect widget.auto.anon_in, dcache.auto.out
connect xbar.auto.anon_in, widget.auto.anon_out
connect reroccManagerIdSinkNodeIn, auto.rerocc_manager_id_sink_in
connect reRoCCNodeIn, auto.re_ro_cc_in
connect auto.buffer_out.e.bits, buffer.auto.out.e.bits
connect auto.buffer_out.e.valid, buffer.auto.out.e.valid
connect buffer.auto.out.e.ready, auto.buffer_out.e.ready
connect buffer.auto.out.d, auto.buffer_out.d
connect auto.buffer_out.c.bits, buffer.auto.out.c.bits
connect auto.buffer_out.c.valid, buffer.auto.out.c.valid
connect buffer.auto.out.c.ready, auto.buffer_out.c.ready
connect buffer.auto.out.b, auto.buffer_out.b
connect auto.buffer_out.a.bits, buffer.auto.out.a.bits
connect auto.buffer_out.a.valid, buffer.auto.out.a.valid
connect buffer.auto.out.a.ready, auto.buffer_out.a.ready
connect ctrl.auto.ctrl_in, auto.ctrl_ctrl_in
inst dcacheArb of HellaCacheArbiter_2
connect dcacheArb.clock, clock
connect dcacheArb.reset, reset
connect dcache.io.cpu, dcacheArb.io.mem
inst ptw of PTW_2
connect ptw.clock, clock
connect ptw.reset, reset
invalidate dcache.io.tlb_port.s2_kill
invalidate dcache.io.tlb_port.s1_resp.cmd
invalidate dcache.io.tlb_port.s1_resp.size
invalidate dcache.io.tlb_port.s1_resp.prefetchable
invalidate dcache.io.tlb_port.s1_resp.must_alloc
invalidate dcache.io.tlb_port.s1_resp.cacheable
invalidate dcache.io.tlb_port.s1_resp.ma.inst
invalidate dcache.io.tlb_port.s1_resp.ma.st
invalidate dcache.io.tlb_port.s1_resp.ma.ld
invalidate dcache.io.tlb_port.s1_resp.ae.inst
invalidate dcache.io.tlb_port.s1_resp.ae.st
invalidate dcache.io.tlb_port.s1_resp.ae.ld
invalidate dcache.io.tlb_port.s1_resp.gf.inst
invalidate dcache.io.tlb_port.s1_resp.gf.st
invalidate dcache.io.tlb_port.s1_resp.gf.ld
invalidate dcache.io.tlb_port.s1_resp.pf.inst
invalidate dcache.io.tlb_port.s1_resp.pf.st
invalidate dcache.io.tlb_port.s1_resp.pf.ld
invalidate dcache.io.tlb_port.s1_resp.gpa_is_pte
invalidate dcache.io.tlb_port.s1_resp.gpa
invalidate dcache.io.tlb_port.s1_resp.paddr
invalidate dcache.io.tlb_port.s1_resp.miss
invalidate dcache.io.tlb_port.req.bits.v
invalidate dcache.io.tlb_port.req.bits.prv
invalidate dcache.io.tlb_port.req.bits.cmd
invalidate dcache.io.tlb_port.req.bits.size
invalidate dcache.io.tlb_port.req.bits.passthrough
invalidate dcache.io.tlb_port.req.bits.vaddr
invalidate dcache.io.tlb_port.req.valid
invalidate dcache.io.tlb_port.req.ready
connect dcache.io.tlb_port.req.valid, UInt<1>(0h0)
connect ptw.io.requestor[0], dcache.io.ptw
connect dcacheArb.io.requestor[0], ptw.io.mem
inst dcIF of SimpleHellaCacheIF_2
connect dcIF.clock, clock
connect dcIF.reset, reset
connect dcIF.io.requestor, accumulator.io.mem
connect dcacheArb.io.requestor[1], dcIF.io.cache
connect rerocc_manager.io.manager_id, reroccManagerIdSinkNodeIn
connect accumulator.io.cmd, rerocc_manager.io.cmd
connect rerocc_manager.io.resp, accumulator.io.resp
connect rerocc_manager.io.busy, accumulator.io.busy
connect rerocc_manager.io.ptw, ptw.io.dpath
connect accumulator.io.fpu_req.ready, UInt<1>(0h0)
node _T = eq(accumulator.io.fpu_req.valid, UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Manager.scala:270 assert(!rocc.module.io.fpu_req.valid)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
connect accumulator.io.fpu_resp.valid, UInt<1>(0h0)
invalidate accumulator.io.fpu_resp.bits.exc
invalidate accumulator.io.fpu_resp.bits.data
connect accumulator.io.exception, UInt<1>(0h0)
connect ctrl.io.mgr_busy, rerocc_manager.io.busy
connect ctrl.io.rocc_busy, accumulator.io.busy | module ReRoCCManagerTile_1( // @[Manager.scala:237:34]
input clock, // @[Manager.scala:237:34]
input reset, // @[Manager.scala:237:34]
output auto_ctrl_ctrl_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_ctrl_ctrl_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_ctrl_ctrl_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_ctrl_ctrl_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_ctrl_ctrl_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_ctrl_ctrl_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [11:0] auto_ctrl_ctrl_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_ctrl_ctrl_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_ctrl_ctrl_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_ctrl_ctrl_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_ctrl_ctrl_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_ctrl_ctrl_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_ctrl_ctrl_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_ctrl_ctrl_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_ctrl_ctrl_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_ctrl_ctrl_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_buffer_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_buffer_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_buffer_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_buffer_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_buffer_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_out_b_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_buffer_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_buffer_out_b_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_buffer_out_b_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_buffer_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_buffer_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_buffer_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_buffer_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_buffer_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_buffer_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_buffer_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_buffer_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_out_e_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_re_ro_cc_in_req_ready, // @[LazyModuleImp.scala:107:25]
input auto_re_ro_cc_in_req_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_re_ro_cc_in_req_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_re_ro_cc_in_req_bits_client_id, // @[LazyModuleImp.scala:107:25]
input auto_re_ro_cc_in_req_bits_manager_id, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_re_ro_cc_in_req_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_re_ro_cc_in_resp_ready, // @[LazyModuleImp.scala:107:25]
output auto_re_ro_cc_in_resp_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_re_ro_cc_in_resp_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_re_ro_cc_in_resp_bits_client_id, // @[LazyModuleImp.scala:107:25]
output auto_re_ro_cc_in_resp_bits_manager_id, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_re_ro_cc_in_resp_bits_data, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_rerocc_manager_id_sink_in // @[LazyModuleImp.scala:107:25]
);
wire reRoCCNodeOut_resp_valid; // @[MixedNode.scala:542:17]
wire [63:0] reRoCCNodeOut_resp_bits_data; // @[MixedNode.scala:542:17]
wire reRoCCNodeOut_resp_bits_manager_id; // @[MixedNode.scala:542:17]
wire [3:0] reRoCCNodeOut_resp_bits_client_id; // @[MixedNode.scala:542:17]
wire [2:0] reRoCCNodeOut_resp_bits_opcode; // @[MixedNode.scala:542:17]
wire reRoCCNodeOut_req_ready; // @[MixedNode.scala:542:17]
wire widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9]
wire [63:0] widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [63:0] widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire [7:0] widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] xbar_out_0_e_bits_sink; // @[Xbar.scala:216:19]
wire [2:0] xbar_out_0_d_bits_sink; // @[Xbar.scala:216:19]
wire xbar_in_0_d_bits_source; // @[Xbar.scala:159:18]
wire xbar_in_0_c_bits_source; // @[Xbar.scala:159:18]
wire xbar_in_0_b_bits_source; // @[Xbar.scala:159:18]
wire xbar_in_0_a_bits_source; // @[Xbar.scala:159:18]
wire xbar_auto_anon_out_e_ready; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9]
wire [63:0] xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9]
wire [3:0] xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9]
wire [1:0] xbar_auto_anon_out_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_c_ready; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_b_valid; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_b_bits_corrupt; // @[Xbar.scala:74:9]
wire [63:0] xbar_auto_anon_out_b_bits_data; // @[Xbar.scala:74:9]
wire [7:0] xbar_auto_anon_out_b_bits_mask; // @[Xbar.scala:74:9]
wire [31:0] xbar_auto_anon_out_b_bits_address; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_b_bits_source; // @[Xbar.scala:74:9]
wire [3:0] xbar_auto_anon_out_b_bits_size; // @[Xbar.scala:74:9]
wire [1:0] xbar_auto_anon_out_b_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_out_b_bits_opcode; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_e_valid; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_e_ready; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_in_e_bits_sink; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_d_valid; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_d_ready; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_d_bits_corrupt; // @[Xbar.scala:74:9]
wire [63:0] xbar_auto_anon_in_d_bits_data; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_d_bits_denied; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_in_d_bits_sink; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_d_bits_source; // @[Xbar.scala:74:9]
wire [3:0] xbar_auto_anon_in_d_bits_size; // @[Xbar.scala:74:9]
wire [1:0] xbar_auto_anon_in_d_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_in_d_bits_opcode; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_c_valid; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_c_ready; // @[Xbar.scala:74:9]
wire [63:0] xbar_auto_anon_in_c_bits_data; // @[Xbar.scala:74:9]
wire [31:0] xbar_auto_anon_in_c_bits_address; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_c_bits_source; // @[Xbar.scala:74:9]
wire [3:0] xbar_auto_anon_in_c_bits_size; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_in_c_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_in_c_bits_opcode; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_b_valid; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_b_ready; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_b_bits_corrupt; // @[Xbar.scala:74:9]
wire [63:0] xbar_auto_anon_in_b_bits_data; // @[Xbar.scala:74:9]
wire [7:0] xbar_auto_anon_in_b_bits_mask; // @[Xbar.scala:74:9]
wire [31:0] xbar_auto_anon_in_b_bits_address; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_b_bits_source; // @[Xbar.scala:74:9]
wire [3:0] xbar_auto_anon_in_b_bits_size; // @[Xbar.scala:74:9]
wire [1:0] xbar_auto_anon_in_b_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_in_b_bits_opcode; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_a_valid; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_a_ready; // @[Xbar.scala:74:9]
wire [63:0] xbar_auto_anon_in_a_bits_data; // @[Xbar.scala:74:9]
wire [7:0] xbar_auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9]
wire [31:0] xbar_auto_anon_in_a_bits_address; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_a_bits_source; // @[Xbar.scala:74:9]
wire [3:0] xbar_auto_anon_in_a_bits_size; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_in_a_bits_param; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9]
wire _dcIF_io_cache_req_valid; // @[Manager.scala:255:22]
wire [39:0] _dcIF_io_cache_req_bits_addr; // @[Manager.scala:255:22]
wire [7:0] _dcIF_io_cache_req_bits_tag; // @[Manager.scala:255:22]
wire [1:0] _dcIF_io_cache_req_bits_dprv; // @[Manager.scala:255:22]
wire _dcIF_io_cache_req_bits_dv; // @[Manager.scala:255:22]
wire [63:0] _dcIF_io_cache_s1_data_data; // @[Manager.scala:255:22]
wire [7:0] _dcIF_io_cache_s1_data_mask; // @[Manager.scala:255:22]
wire _ptw_io_requestor_0_req_ready; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_resp_valid; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_resp_bits_ae_ptw; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_resp_bits_ae_final; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_resp_bits_pf; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_resp_bits_gf; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_resp_bits_hr; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_resp_bits_hw; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_resp_bits_hx; // @[Manager.scala:243:21]
wire [9:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_future; // @[Manager.scala:243:21]
wire [43:0] _ptw_io_requestor_0_resp_bits_pte_ppn; // @[Manager.scala:243:21]
wire [1:0] _ptw_io_requestor_0_resp_bits_pte_reserved_for_software; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_resp_bits_pte_d; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_resp_bits_pte_a; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_resp_bits_pte_g; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_resp_bits_pte_u; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_resp_bits_pte_x; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_resp_bits_pte_w; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_resp_bits_pte_r; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_resp_bits_pte_v; // @[Manager.scala:243:21]
wire [1:0] _ptw_io_requestor_0_resp_bits_level; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_resp_bits_homogeneous; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_resp_bits_gpa_valid; // @[Manager.scala:243:21]
wire [38:0] _ptw_io_requestor_0_resp_bits_gpa_bits; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_resp_bits_gpa_is_pte; // @[Manager.scala:243:21]
wire [3:0] _ptw_io_requestor_0_ptbr_mode; // @[Manager.scala:243:21]
wire [15:0] _ptw_io_requestor_0_ptbr_asid; // @[Manager.scala:243:21]
wire [43:0] _ptw_io_requestor_0_ptbr_ppn; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_status_debug; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_status_cease; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_status_wfi; // @[Manager.scala:243:21]
wire [31:0] _ptw_io_requestor_0_status_isa; // @[Manager.scala:243:21]
wire [1:0] _ptw_io_requestor_0_status_dprv; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_status_dv; // @[Manager.scala:243:21]
wire [1:0] _ptw_io_requestor_0_status_prv; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_status_v; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_status_sd; // @[Manager.scala:243:21]
wire [22:0] _ptw_io_requestor_0_status_zero2; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_status_mpv; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_status_gva; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_status_mbe; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_status_sbe; // @[Manager.scala:243:21]
wire [1:0] _ptw_io_requestor_0_status_sxl; // @[Manager.scala:243:21]
wire [1:0] _ptw_io_requestor_0_status_uxl; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_status_sd_rv32; // @[Manager.scala:243:21]
wire [7:0] _ptw_io_requestor_0_status_zero1; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_status_tsr; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_status_tw; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_status_tvm; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_status_mxr; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_status_sum; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_status_mprv; // @[Manager.scala:243:21]
wire [1:0] _ptw_io_requestor_0_status_xs; // @[Manager.scala:243:21]
wire [1:0] _ptw_io_requestor_0_status_fs; // @[Manager.scala:243:21]
wire [1:0] _ptw_io_requestor_0_status_mpp; // @[Manager.scala:243:21]
wire [1:0] _ptw_io_requestor_0_status_vs; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_status_spp; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_status_mpie; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_status_ube; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_status_spie; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_status_upie; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_status_mie; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_status_hie; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_status_sie; // @[Manager.scala:243:21]
wire _ptw_io_requestor_0_status_uie; // @[Manager.scala:243:21]
wire _ptw_io_mem_req_valid; // @[Manager.scala:243:21]
wire [39:0] _ptw_io_mem_req_bits_addr; // @[Manager.scala:243:21]
wire _ptw_io_mem_req_bits_dv; // @[Manager.scala:243:21]
wire _ptw_io_mem_s1_kill; // @[Manager.scala:243:21]
wire _ptw_io_dpath_perf_pte_miss; // @[Manager.scala:243:21]
wire _ptw_io_dpath_clock_enabled; // @[Manager.scala:243:21]
wire _dcacheArb_io_requestor_0_req_ready; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_0_s2_nack; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_0_s2_nack_cause_raw; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_0_s2_uncached; // @[Manager.scala:238:27]
wire [31:0] _dcacheArb_io_requestor_0_s2_paddr; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_0_resp_valid; // @[Manager.scala:238:27]
wire [39:0] _dcacheArb_io_requestor_0_resp_bits_addr; // @[Manager.scala:238:27]
wire [7:0] _dcacheArb_io_requestor_0_resp_bits_tag; // @[Manager.scala:238:27]
wire [4:0] _dcacheArb_io_requestor_0_resp_bits_cmd; // @[Manager.scala:238:27]
wire [1:0] _dcacheArb_io_requestor_0_resp_bits_size; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_0_resp_bits_signed; // @[Manager.scala:238:27]
wire [1:0] _dcacheArb_io_requestor_0_resp_bits_dprv; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_0_resp_bits_dv; // @[Manager.scala:238:27]
wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data; // @[Manager.scala:238:27]
wire [7:0] _dcacheArb_io_requestor_0_resp_bits_mask; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_0_resp_bits_replay; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_0_resp_bits_has_data; // @[Manager.scala:238:27]
wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data_word_bypass; // @[Manager.scala:238:27]
wire [63:0] _dcacheArb_io_requestor_0_resp_bits_data_raw; // @[Manager.scala:238:27]
wire [63:0] _dcacheArb_io_requestor_0_resp_bits_store_data; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_0_replay_next; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_0_s2_xcpt_ma_ld; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_0_s2_xcpt_ma_st; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_0_s2_xcpt_pf_ld; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_0_s2_xcpt_pf_st; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_0_s2_xcpt_ae_ld; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_0_s2_xcpt_ae_st; // @[Manager.scala:238:27]
wire [39:0] _dcacheArb_io_requestor_0_s2_gpa; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_0_ordered; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_0_store_pending; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_0_perf_acquire; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_0_perf_release; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_0_perf_grant; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_0_perf_tlbMiss; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_0_perf_blocked; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_1_req_ready; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_1_s2_nack; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_1_s2_nack_cause_raw; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_1_s2_uncached; // @[Manager.scala:238:27]
wire [31:0] _dcacheArb_io_requestor_1_s2_paddr; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_1_resp_valid; // @[Manager.scala:238:27]
wire [39:0] _dcacheArb_io_requestor_1_resp_bits_addr; // @[Manager.scala:238:27]
wire [7:0] _dcacheArb_io_requestor_1_resp_bits_tag; // @[Manager.scala:238:27]
wire [4:0] _dcacheArb_io_requestor_1_resp_bits_cmd; // @[Manager.scala:238:27]
wire [1:0] _dcacheArb_io_requestor_1_resp_bits_size; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_1_resp_bits_signed; // @[Manager.scala:238:27]
wire [1:0] _dcacheArb_io_requestor_1_resp_bits_dprv; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_1_resp_bits_dv; // @[Manager.scala:238:27]
wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data; // @[Manager.scala:238:27]
wire [7:0] _dcacheArb_io_requestor_1_resp_bits_mask; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_1_resp_bits_replay; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_1_resp_bits_has_data; // @[Manager.scala:238:27]
wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data_word_bypass; // @[Manager.scala:238:27]
wire [63:0] _dcacheArb_io_requestor_1_resp_bits_data_raw; // @[Manager.scala:238:27]
wire [63:0] _dcacheArb_io_requestor_1_resp_bits_store_data; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_1_replay_next; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_1_s2_xcpt_ma_ld; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_1_s2_xcpt_ma_st; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_1_s2_xcpt_pf_ld; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_1_s2_xcpt_pf_st; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_1_s2_xcpt_ae_ld; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_1_s2_xcpt_ae_st; // @[Manager.scala:238:27]
wire [39:0] _dcacheArb_io_requestor_1_s2_gpa; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_1_ordered; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_1_store_pending; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_1_perf_acquire; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_1_perf_release; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_1_perf_grant; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_1_perf_tlbMiss; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_1_perf_blocked; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad; // @[Manager.scala:238:27]
wire _dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore; // @[Manager.scala:238:27]
wire _dcacheArb_io_mem_req_valid; // @[Manager.scala:238:27]
wire [39:0] _dcacheArb_io_mem_req_bits_addr; // @[Manager.scala:238:27]
wire [7:0] _dcacheArb_io_mem_req_bits_tag; // @[Manager.scala:238:27]
wire [1:0] _dcacheArb_io_mem_req_bits_dprv; // @[Manager.scala:238:27]
wire _dcacheArb_io_mem_req_bits_dv; // @[Manager.scala:238:27]
wire _dcacheArb_io_mem_req_bits_phys; // @[Manager.scala:238:27]
wire _dcacheArb_io_mem_s1_kill; // @[Manager.scala:238:27]
wire [63:0] _dcacheArb_io_mem_s1_data_data; // @[Manager.scala:238:27]
wire [7:0] _dcacheArb_io_mem_s1_data_mask; // @[Manager.scala:238:27]
wire _dcache_io_cpu_req_ready; // @[Manager.scala:226:61]
wire _dcache_io_cpu_s2_nack; // @[Manager.scala:226:61]
wire _dcache_io_cpu_s2_nack_cause_raw; // @[Manager.scala:226:61]
wire _dcache_io_cpu_s2_uncached; // @[Manager.scala:226:61]
wire [31:0] _dcache_io_cpu_s2_paddr; // @[Manager.scala:226:61]
wire _dcache_io_cpu_resp_valid; // @[Manager.scala:226:61]
wire [39:0] _dcache_io_cpu_resp_bits_addr; // @[Manager.scala:226:61]
wire [7:0] _dcache_io_cpu_resp_bits_tag; // @[Manager.scala:226:61]
wire [4:0] _dcache_io_cpu_resp_bits_cmd; // @[Manager.scala:226:61]
wire [1:0] _dcache_io_cpu_resp_bits_size; // @[Manager.scala:226:61]
wire _dcache_io_cpu_resp_bits_signed; // @[Manager.scala:226:61]
wire [1:0] _dcache_io_cpu_resp_bits_dprv; // @[Manager.scala:226:61]
wire _dcache_io_cpu_resp_bits_dv; // @[Manager.scala:226:61]
wire [63:0] _dcache_io_cpu_resp_bits_data; // @[Manager.scala:226:61]
wire [7:0] _dcache_io_cpu_resp_bits_mask; // @[Manager.scala:226:61]
wire _dcache_io_cpu_resp_bits_replay; // @[Manager.scala:226:61]
wire _dcache_io_cpu_resp_bits_has_data; // @[Manager.scala:226:61]
wire [63:0] _dcache_io_cpu_resp_bits_data_word_bypass; // @[Manager.scala:226:61]
wire [63:0] _dcache_io_cpu_resp_bits_data_raw; // @[Manager.scala:226:61]
wire [63:0] _dcache_io_cpu_resp_bits_store_data; // @[Manager.scala:226:61]
wire _dcache_io_cpu_replay_next; // @[Manager.scala:226:61]
wire _dcache_io_cpu_s2_xcpt_ma_ld; // @[Manager.scala:226:61]
wire _dcache_io_cpu_s2_xcpt_ma_st; // @[Manager.scala:226:61]
wire _dcache_io_cpu_s2_xcpt_pf_ld; // @[Manager.scala:226:61]
wire _dcache_io_cpu_s2_xcpt_pf_st; // @[Manager.scala:226:61]
wire _dcache_io_cpu_s2_xcpt_ae_ld; // @[Manager.scala:226:61]
wire _dcache_io_cpu_s2_xcpt_ae_st; // @[Manager.scala:226:61]
wire [39:0] _dcache_io_cpu_s2_gpa; // @[Manager.scala:226:61]
wire _dcache_io_cpu_ordered; // @[Manager.scala:226:61]
wire _dcache_io_cpu_store_pending; // @[Manager.scala:226:61]
wire _dcache_io_cpu_perf_acquire; // @[Manager.scala:226:61]
wire _dcache_io_cpu_perf_release; // @[Manager.scala:226:61]
wire _dcache_io_cpu_perf_grant; // @[Manager.scala:226:61]
wire _dcache_io_cpu_perf_tlbMiss; // @[Manager.scala:226:61]
wire _dcache_io_cpu_perf_blocked; // @[Manager.scala:226:61]
wire _dcache_io_cpu_perf_canAcceptStoreThenLoad; // @[Manager.scala:226:61]
wire _dcache_io_cpu_perf_canAcceptStoreThenRMW; // @[Manager.scala:226:61]
wire _dcache_io_cpu_perf_canAcceptLoadThenLoad; // @[Manager.scala:226:61]
wire _dcache_io_cpu_perf_storeBufferEmptyAfterLoad; // @[Manager.scala:226:61]
wire _dcache_io_cpu_perf_storeBufferEmptyAfterStore; // @[Manager.scala:226:61]
wire _dcache_io_ptw_req_valid; // @[Manager.scala:226:61]
wire [26:0] _dcache_io_ptw_req_bits_bits_addr; // @[Manager.scala:226:61]
wire _dcache_io_ptw_req_bits_bits_need_gpa; // @[Manager.scala:226:61]
wire _rerocc_buffer_auto_out_req_valid; // @[Protocol.scala:134:35]
wire [2:0] _rerocc_buffer_auto_out_req_bits_opcode; // @[Protocol.scala:134:35]
wire [3:0] _rerocc_buffer_auto_out_req_bits_client_id; // @[Protocol.scala:134:35]
wire _rerocc_buffer_auto_out_req_bits_manager_id; // @[Protocol.scala:134:35]
wire [63:0] _rerocc_buffer_auto_out_req_bits_data; // @[Protocol.scala:134:35]
wire _rerocc_buffer_auto_out_resp_ready; // @[Protocol.scala:134:35]
wire _rerocc_manager_auto_in_req_ready; // @[Manager.scala:209:34]
wire _rerocc_manager_auto_in_resp_valid; // @[Manager.scala:209:34]
wire [2:0] _rerocc_manager_auto_in_resp_bits_opcode; // @[Manager.scala:209:34]
wire [3:0] _rerocc_manager_auto_in_resp_bits_client_id; // @[Manager.scala:209:34]
wire _rerocc_manager_auto_in_resp_bits_manager_id; // @[Manager.scala:209:34]
wire [63:0] _rerocc_manager_auto_in_resp_bits_data; // @[Manager.scala:209:34]
wire [3:0] _rerocc_manager_io_ptw_ptbr_mode; // @[Manager.scala:209:34]
wire [15:0] _rerocc_manager_io_ptw_ptbr_asid; // @[Manager.scala:209:34]
wire [43:0] _rerocc_manager_io_ptw_ptbr_ppn; // @[Manager.scala:209:34]
wire _rerocc_manager_io_ptw_sfence_valid; // @[Manager.scala:209:34]
wire _rerocc_manager_io_ptw_status_debug; // @[Manager.scala:209:34]
wire _rerocc_manager_io_ptw_status_cease; // @[Manager.scala:209:34]
wire _rerocc_manager_io_ptw_status_wfi; // @[Manager.scala:209:34]
wire [31:0] _rerocc_manager_io_ptw_status_isa; // @[Manager.scala:209:34]
wire [1:0] _rerocc_manager_io_ptw_status_dprv; // @[Manager.scala:209:34]
wire _rerocc_manager_io_ptw_status_dv; // @[Manager.scala:209:34]
wire [1:0] _rerocc_manager_io_ptw_status_prv; // @[Manager.scala:209:34]
wire _rerocc_manager_io_ptw_status_v; // @[Manager.scala:209:34]
wire _rerocc_manager_io_ptw_status_sd; // @[Manager.scala:209:34]
wire [22:0] _rerocc_manager_io_ptw_status_zero2; // @[Manager.scala:209:34]
wire _rerocc_manager_io_ptw_status_mpv; // @[Manager.scala:209:34]
wire _rerocc_manager_io_ptw_status_gva; // @[Manager.scala:209:34]
wire _rerocc_manager_io_ptw_status_mbe; // @[Manager.scala:209:34]
wire _rerocc_manager_io_ptw_status_sbe; // @[Manager.scala:209:34]
wire [1:0] _rerocc_manager_io_ptw_status_sxl; // @[Manager.scala:209:34]
wire [1:0] _rerocc_manager_io_ptw_status_uxl; // @[Manager.scala:209:34]
wire _rerocc_manager_io_ptw_status_sd_rv32; // @[Manager.scala:209:34]
wire [7:0] _rerocc_manager_io_ptw_status_zero1; // @[Manager.scala:209:34]
wire _rerocc_manager_io_ptw_status_tsr; // @[Manager.scala:209:34]
wire _rerocc_manager_io_ptw_status_tw; // @[Manager.scala:209:34]
wire _rerocc_manager_io_ptw_status_tvm; // @[Manager.scala:209:34]
wire _rerocc_manager_io_ptw_status_mxr; // @[Manager.scala:209:34]
wire _rerocc_manager_io_ptw_status_sum; // @[Manager.scala:209:34]
wire _rerocc_manager_io_ptw_status_mprv; // @[Manager.scala:209:34]
wire [1:0] _rerocc_manager_io_ptw_status_xs; // @[Manager.scala:209:34]
wire [1:0] _rerocc_manager_io_ptw_status_fs; // @[Manager.scala:209:34]
wire [1:0] _rerocc_manager_io_ptw_status_mpp; // @[Manager.scala:209:34]
wire [1:0] _rerocc_manager_io_ptw_status_vs; // @[Manager.scala:209:34]
wire _rerocc_manager_io_ptw_status_spp; // @[Manager.scala:209:34]
wire _rerocc_manager_io_ptw_status_mpie; // @[Manager.scala:209:34]
wire _rerocc_manager_io_ptw_status_ube; // @[Manager.scala:209:34]
wire _rerocc_manager_io_ptw_status_spie; // @[Manager.scala:209:34]
wire _rerocc_manager_io_ptw_status_upie; // @[Manager.scala:209:34]
wire _rerocc_manager_io_ptw_status_mie; // @[Manager.scala:209:34]
wire _rerocc_manager_io_ptw_status_hie; // @[Manager.scala:209:34]
wire _rerocc_manager_io_ptw_status_sie; // @[Manager.scala:209:34]
wire _rerocc_manager_io_ptw_status_uie; // @[Manager.scala:209:34]
wire _accumulator_cmd_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire [6:0] _accumulator_cmd_q_io_deq_bits_inst_funct; // @[Decoupled.scala:362:21]
wire _accumulator_cmd_q_io_deq_bits_inst_xd; // @[Decoupled.scala:362:21]
wire [63:0] _accumulator_cmd_q_io_deq_bits_rs1; // @[Decoupled.scala:362:21]
wire [63:0] _accumulator_cmd_q_io_deq_bits_rs2; // @[Decoupled.scala:362:21]
wire [63:0] _regfile_ext_R0_data; // @[LazyRoCC.scala:124:20]
wire auto_ctrl_ctrl_in_a_valid_0 = auto_ctrl_ctrl_in_a_valid; // @[Manager.scala:237:34]
wire [2:0] auto_ctrl_ctrl_in_a_bits_opcode_0 = auto_ctrl_ctrl_in_a_bits_opcode; // @[Manager.scala:237:34]
wire [2:0] auto_ctrl_ctrl_in_a_bits_param_0 = auto_ctrl_ctrl_in_a_bits_param; // @[Manager.scala:237:34]
wire [2:0] auto_ctrl_ctrl_in_a_bits_size_0 = auto_ctrl_ctrl_in_a_bits_size; // @[Manager.scala:237:34]
wire [6:0] auto_ctrl_ctrl_in_a_bits_source_0 = auto_ctrl_ctrl_in_a_bits_source; // @[Manager.scala:237:34]
wire [11:0] auto_ctrl_ctrl_in_a_bits_address_0 = auto_ctrl_ctrl_in_a_bits_address; // @[Manager.scala:237:34]
wire [7:0] auto_ctrl_ctrl_in_a_bits_mask_0 = auto_ctrl_ctrl_in_a_bits_mask; // @[Manager.scala:237:34]
wire [63:0] auto_ctrl_ctrl_in_a_bits_data_0 = auto_ctrl_ctrl_in_a_bits_data; // @[Manager.scala:237:34]
wire auto_ctrl_ctrl_in_a_bits_corrupt_0 = auto_ctrl_ctrl_in_a_bits_corrupt; // @[Manager.scala:237:34]
wire auto_ctrl_ctrl_in_d_ready_0 = auto_ctrl_ctrl_in_d_ready; // @[Manager.scala:237:34]
wire auto_buffer_out_a_ready_0 = auto_buffer_out_a_ready; // @[Manager.scala:237:34]
wire auto_buffer_out_b_valid_0 = auto_buffer_out_b_valid; // @[Manager.scala:237:34]
wire [2:0] auto_buffer_out_b_bits_opcode_0 = auto_buffer_out_b_bits_opcode; // @[Manager.scala:237:34]
wire [1:0] auto_buffer_out_b_bits_param_0 = auto_buffer_out_b_bits_param; // @[Manager.scala:237:34]
wire [3:0] auto_buffer_out_b_bits_size_0 = auto_buffer_out_b_bits_size; // @[Manager.scala:237:34]
wire auto_buffer_out_b_bits_source_0 = auto_buffer_out_b_bits_source; // @[Manager.scala:237:34]
wire [31:0] auto_buffer_out_b_bits_address_0 = auto_buffer_out_b_bits_address; // @[Manager.scala:237:34]
wire [7:0] auto_buffer_out_b_bits_mask_0 = auto_buffer_out_b_bits_mask; // @[Manager.scala:237:34]
wire [63:0] auto_buffer_out_b_bits_data_0 = auto_buffer_out_b_bits_data; // @[Manager.scala:237:34]
wire auto_buffer_out_b_bits_corrupt_0 = auto_buffer_out_b_bits_corrupt; // @[Manager.scala:237:34]
wire auto_buffer_out_c_ready_0 = auto_buffer_out_c_ready; // @[Manager.scala:237:34]
wire auto_buffer_out_d_valid_0 = auto_buffer_out_d_valid; // @[Manager.scala:237:34]
wire [2:0] auto_buffer_out_d_bits_opcode_0 = auto_buffer_out_d_bits_opcode; // @[Manager.scala:237:34]
wire [1:0] auto_buffer_out_d_bits_param_0 = auto_buffer_out_d_bits_param; // @[Manager.scala:237:34]
wire [3:0] auto_buffer_out_d_bits_size_0 = auto_buffer_out_d_bits_size; // @[Manager.scala:237:34]
wire auto_buffer_out_d_bits_source_0 = auto_buffer_out_d_bits_source; // @[Manager.scala:237:34]
wire [2:0] auto_buffer_out_d_bits_sink_0 = auto_buffer_out_d_bits_sink; // @[Manager.scala:237:34]
wire auto_buffer_out_d_bits_denied_0 = auto_buffer_out_d_bits_denied; // @[Manager.scala:237:34]
wire [63:0] auto_buffer_out_d_bits_data_0 = auto_buffer_out_d_bits_data; // @[Manager.scala:237:34]
wire auto_buffer_out_d_bits_corrupt_0 = auto_buffer_out_d_bits_corrupt; // @[Manager.scala:237:34]
wire auto_buffer_out_e_ready_0 = auto_buffer_out_e_ready; // @[Manager.scala:237:34]
wire auto_re_ro_cc_in_req_valid_0 = auto_re_ro_cc_in_req_valid; // @[Manager.scala:237:34]
wire [2:0] auto_re_ro_cc_in_req_bits_opcode_0 = auto_re_ro_cc_in_req_bits_opcode; // @[Manager.scala:237:34]
wire [3:0] auto_re_ro_cc_in_req_bits_client_id_0 = auto_re_ro_cc_in_req_bits_client_id; // @[Manager.scala:237:34]
wire auto_re_ro_cc_in_req_bits_manager_id_0 = auto_re_ro_cc_in_req_bits_manager_id; // @[Manager.scala:237:34]
wire [63:0] auto_re_ro_cc_in_req_bits_data_0 = auto_re_ro_cc_in_req_bits_data; // @[Manager.scala:237:34]
wire auto_re_ro_cc_in_resp_ready_0 = auto_re_ro_cc_in_resp_ready; // @[Manager.scala:237:34]
wire [6:0] auto_rerocc_manager_id_sink_in_0 = auto_rerocc_manager_id_sink_in; // @[Manager.scala:237:34]
wire xbar__requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire xbar_requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107]
wire xbar__requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire xbar_requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107]
wire xbar__requestBOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire xbar__requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire xbar__requestBOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire xbar__requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire xbar_requestBOI_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire xbar__requestDOI_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire xbar__requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire xbar__requestDOI_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire xbar__requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire xbar_requestDOI_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire xbar__requestEIO_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire xbar__requestEIO_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire xbar__requestEIO_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire xbar__requestEIO_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire xbar_requestEIO_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire xbar__portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire xbar__portsBIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire xbar__portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire xbar__portsDIO_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire xbar__portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire [2:0] accumulator_io_fpu_req_bits_rm = 3'h0; // @[LazyRoCC.scala:122:7]
wire [64:0] accumulator_io_fpu_req_bits_in1 = 65'h0; // @[LazyRoCC.scala:122:7]
wire [64:0] accumulator_io_fpu_req_bits_in2 = 65'h0; // @[LazyRoCC.scala:122:7]
wire [64:0] accumulator_io_fpu_req_bits_in3 = 65'h0; // @[LazyRoCC.scala:122:7]
wire [64:0] accumulator_io_fpu_resp_bits_data = 65'h0; // @[LazyRoCC.scala:122:7]
wire [32:0] xbar__requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] xbar__requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] xbar__requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] xbar__requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [8:0] xbar_beatsBO_0 = 9'h0; // @[Edges.scala:221:14]
wire [39:0] accumulator_io_mem_s2_gpa = 40'h0; // @[LazyRoCC.scala:122:7]
wire [31:0] accumulator_io_mem_s2_paddr = 32'h0; // @[LazyRoCC.scala:122:7]
wire [4:0] accumulator_io_mem_req_bits_cmd = 5'h0; // @[LazyRoCC.scala:122:7]
wire [4:0] accumulator_io_fpu_resp_bits_exc = 5'h0; // @[LazyRoCC.scala:122:7]
wire [1:0] accumulator_io_mem_req_bits_size = 2'h3; // @[LazyRoCC.scala:122:7]
wire [63:0] accumulator_io_mem_req_bits_data = 64'h0; // @[LazyRoCC.scala:122:7]
wire [63:0] accumulator_io_mem_s1_data_data = 64'h0; // @[LazyRoCC.scala:122:7]
wire [7:0] accumulator_io_mem_req_bits_mask = 8'h0; // @[LazyRoCC.scala:122:7]
wire [7:0] accumulator_io_mem_s1_data_mask = 8'h0; // @[LazyRoCC.scala:122:7]
wire auto_ctrl_ctrl_in_d_bits_sink = 1'h0; // @[Manager.scala:237:34]
wire auto_ctrl_ctrl_in_d_bits_denied = 1'h0; // @[Manager.scala:237:34]
wire auto_ctrl_ctrl_in_d_bits_corrupt = 1'h0; // @[Manager.scala:237:34]
wire accumulator_io_mem_req_bits_signed = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_req_bits_phys = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_req_bits_no_resp = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_req_bits_no_alloc = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_req_bits_no_xcpt = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_s1_kill = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_s2_nack = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_s2_nack_cause_raw = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_s2_kill = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_s2_uncached = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_replay_next = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_s2_xcpt_ma_ld = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_s2_xcpt_ma_st = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_s2_xcpt_pf_ld = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_s2_xcpt_pf_st = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_s2_xcpt_gf_ld = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_s2_xcpt_gf_st = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_s2_xcpt_ae_ld = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_s2_xcpt_ae_st = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_s2_gpa_is_pte = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_ordered = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_store_pending = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_perf_acquire = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_perf_release = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_perf_grant = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_perf_tlbMiss = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_perf_blocked = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_keep_clock_enabled = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_clock_enabled = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_interrupt = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_exception = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_fpu_req_ready = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_fpu_req_valid = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_fpu_req_bits_ldst = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_fpu_req_bits_wen = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_fpu_req_bits_ren1 = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_fpu_req_bits_ren2 = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_fpu_req_bits_ren3 = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_fpu_req_bits_swap12 = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_fpu_req_bits_swap23 = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_fpu_req_bits_fromint = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_fpu_req_bits_toint = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_fpu_req_bits_fastpipe = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_fpu_req_bits_fma = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_fpu_req_bits_div = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_fpu_req_bits_sqrt = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_fpu_req_bits_wflags = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_fpu_req_bits_vec = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_fpu_resp_ready = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator_io_fpu_resp_valid = 1'h0; // @[LazyRoCC.scala:122:7]
wire accumulator__busy_WIRE_0 = 1'h0; // @[LazyRoCC.scala:125:29]
wire accumulator__busy_WIRE_1 = 1'h0; // @[LazyRoCC.scala:125:29]
wire accumulator__busy_WIRE_2 = 1'h0; // @[LazyRoCC.scala:125:29]
wire accumulator__busy_WIRE_3 = 1'h0; // @[LazyRoCC.scala:125:29]
wire xbar_auto_anon_in_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire xbar_auto_anon_in_c_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_a_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_c_bits_corrupt = 1'h0; // @[Xbar.scala:74:9]
wire xbar_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire xbar_anonOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire xbar_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire xbar_anonIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire xbar_in_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire xbar_in_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:159:18]
wire xbar_out_0_a_bits_corrupt = 1'h0; // @[Xbar.scala:216:19]
wire xbar_out_0_c_bits_corrupt = 1'h0; // @[Xbar.scala:216:19]
wire xbar__requestBOI_T = 1'h0; // @[Parameters.scala:54:10]
wire xbar__requestDOI_T = 1'h0; // @[Parameters.scala:54:10]
wire xbar__requestEIO_T = 1'h0; // @[Parameters.scala:54:10]
wire xbar_portsAOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire xbar_portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire widget_auto_anon_in_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_a_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_out_c_bits_corrupt = 1'h0; // @[WidthWidget.scala:27:9]
wire widget_anonOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire widget_anonOut_c_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire widget_anonIn_a_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire widget_anonIn_c_bits_corrupt = 1'h0; // @[MixedNode.scala:551:17]
wire [1:0] auto_ctrl_ctrl_in_d_bits_param = 2'h0; // @[Manager.scala:237:34]
wire [1:0] accumulator_io_fpu_req_bits_typeTagIn = 2'h0; // @[LazyRoCC.scala:122:7]
wire [1:0] accumulator_io_fpu_req_bits_typeTagOut = 2'h0; // @[LazyRoCC.scala:122:7]
wire [1:0] accumulator_io_fpu_req_bits_fmaCmd = 2'h0; // @[LazyRoCC.scala:122:7]
wire [1:0] accumulator_io_fpu_req_bits_typ = 2'h0; // @[LazyRoCC.scala:122:7]
wire [1:0] accumulator_io_fpu_req_bits_fmt = 2'h0; // @[LazyRoCC.scala:122:7]
wire reRoCCNodeIn_req_ready; // @[MixedNode.scala:551:17]
wire reRoCCNodeIn_req_valid = auto_re_ro_cc_in_req_valid_0; // @[Manager.scala:237:34]
wire [2:0] reRoCCNodeIn_req_bits_opcode = auto_re_ro_cc_in_req_bits_opcode_0; // @[Manager.scala:237:34]
wire [3:0] reRoCCNodeIn_req_bits_client_id = auto_re_ro_cc_in_req_bits_client_id_0; // @[Manager.scala:237:34]
wire reRoCCNodeIn_req_bits_manager_id = auto_re_ro_cc_in_req_bits_manager_id_0; // @[Manager.scala:237:34]
wire [63:0] reRoCCNodeIn_req_bits_data = auto_re_ro_cc_in_req_bits_data_0; // @[Manager.scala:237:34]
wire reRoCCNodeIn_resp_ready = auto_re_ro_cc_in_resp_ready_0; // @[Manager.scala:237:34]
wire reRoCCNodeIn_resp_valid; // @[MixedNode.scala:551:17]
wire [2:0] reRoCCNodeIn_resp_bits_opcode; // @[MixedNode.scala:551:17]
wire [3:0] reRoCCNodeIn_resp_bits_client_id; // @[MixedNode.scala:551:17]
wire reRoCCNodeIn_resp_bits_manager_id; // @[MixedNode.scala:551:17]
wire [63:0] reRoCCNodeIn_resp_bits_data; // @[MixedNode.scala:551:17]
wire [6:0] reroccManagerIdSinkNodeIn = auto_rerocc_manager_id_sink_in_0; // @[Manager.scala:237:34]
wire auto_ctrl_ctrl_in_a_ready_0; // @[Manager.scala:237:34]
wire [2:0] auto_ctrl_ctrl_in_d_bits_opcode_0; // @[Manager.scala:237:34]
wire [2:0] auto_ctrl_ctrl_in_d_bits_size_0; // @[Manager.scala:237:34]
wire [6:0] auto_ctrl_ctrl_in_d_bits_source_0; // @[Manager.scala:237:34]
wire [63:0] auto_ctrl_ctrl_in_d_bits_data_0; // @[Manager.scala:237:34]
wire auto_ctrl_ctrl_in_d_valid_0; // @[Manager.scala:237:34]
wire [2:0] auto_buffer_out_a_bits_opcode_0; // @[Manager.scala:237:34]
wire [2:0] auto_buffer_out_a_bits_param_0; // @[Manager.scala:237:34]
wire [3:0] auto_buffer_out_a_bits_size_0; // @[Manager.scala:237:34]
wire auto_buffer_out_a_bits_source_0; // @[Manager.scala:237:34]
wire [31:0] auto_buffer_out_a_bits_address_0; // @[Manager.scala:237:34]
wire [7:0] auto_buffer_out_a_bits_mask_0; // @[Manager.scala:237:34]
wire [63:0] auto_buffer_out_a_bits_data_0; // @[Manager.scala:237:34]
wire auto_buffer_out_a_bits_corrupt_0; // @[Manager.scala:237:34]
wire auto_buffer_out_a_valid_0; // @[Manager.scala:237:34]
wire auto_buffer_out_b_ready_0; // @[Manager.scala:237:34]
wire [2:0] auto_buffer_out_c_bits_opcode_0; // @[Manager.scala:237:34]
wire [2:0] auto_buffer_out_c_bits_param_0; // @[Manager.scala:237:34]
wire [3:0] auto_buffer_out_c_bits_size_0; // @[Manager.scala:237:34]
wire auto_buffer_out_c_bits_source_0; // @[Manager.scala:237:34]
wire [31:0] auto_buffer_out_c_bits_address_0; // @[Manager.scala:237:34]
wire [63:0] auto_buffer_out_c_bits_data_0; // @[Manager.scala:237:34]
wire auto_buffer_out_c_bits_corrupt_0; // @[Manager.scala:237:34]
wire auto_buffer_out_c_valid_0; // @[Manager.scala:237:34]
wire auto_buffer_out_d_ready_0; // @[Manager.scala:237:34]
wire [2:0] auto_buffer_out_e_bits_sink_0; // @[Manager.scala:237:34]
wire auto_buffer_out_e_valid_0; // @[Manager.scala:237:34]
wire auto_re_ro_cc_in_req_ready_0; // @[Manager.scala:237:34]
wire [2:0] auto_re_ro_cc_in_resp_bits_opcode_0; // @[Manager.scala:237:34]
wire [3:0] auto_re_ro_cc_in_resp_bits_client_id_0; // @[Manager.scala:237:34]
wire auto_re_ro_cc_in_resp_bits_manager_id_0; // @[Manager.scala:237:34]
wire [63:0] auto_re_ro_cc_in_resp_bits_data_0; // @[Manager.scala:237:34]
wire auto_re_ro_cc_in_resp_valid_0; // @[Manager.scala:237:34]
wire accumulator__io_resp_valid_T_4; // @[LazyRoCC.scala:164:53]
wire accumulator__io_mem_req_valid_T_4; // @[LazyRoCC.scala:177:56]
wire accumulator__io_busy_T_3; // @[LazyRoCC.scala:171:24]
wire [6:0] accumulator_io_cmd_bits_inst_funct; // @[LazyRoCC.scala:122:7]
wire [4:0] accumulator_io_cmd_bits_inst_rs2; // @[LazyRoCC.scala:122:7]
wire [4:0] accumulator_io_cmd_bits_inst_rs1; // @[LazyRoCC.scala:122:7]
wire accumulator_io_cmd_bits_inst_xd; // @[LazyRoCC.scala:122:7]
wire accumulator_io_cmd_bits_inst_xs1; // @[LazyRoCC.scala:122:7]
wire accumulator_io_cmd_bits_inst_xs2; // @[LazyRoCC.scala:122:7]
wire [4:0] accumulator_io_cmd_bits_inst_rd; // @[LazyRoCC.scala:122:7]
wire [6:0] accumulator_io_cmd_bits_inst_opcode; // @[LazyRoCC.scala:122:7]
wire accumulator_io_cmd_bits_status_debug; // @[LazyRoCC.scala:122:7]
wire accumulator_io_cmd_bits_status_cease; // @[LazyRoCC.scala:122:7]
wire accumulator_io_cmd_bits_status_wfi; // @[LazyRoCC.scala:122:7]
wire [31:0] accumulator_io_cmd_bits_status_isa; // @[LazyRoCC.scala:122:7]
wire [1:0] accumulator_io_cmd_bits_status_dprv; // @[LazyRoCC.scala:122:7]
wire accumulator_io_cmd_bits_status_dv; // @[LazyRoCC.scala:122:7]
wire [1:0] accumulator_io_cmd_bits_status_prv; // @[LazyRoCC.scala:122:7]
wire accumulator_io_cmd_bits_status_v; // @[LazyRoCC.scala:122:7]
wire accumulator_io_cmd_bits_status_sd; // @[LazyRoCC.scala:122:7]
wire [22:0] accumulator_io_cmd_bits_status_zero2; // @[LazyRoCC.scala:122:7]
wire accumulator_io_cmd_bits_status_mpv; // @[LazyRoCC.scala:122:7]
wire accumulator_io_cmd_bits_status_gva; // @[LazyRoCC.scala:122:7]
wire accumulator_io_cmd_bits_status_mbe; // @[LazyRoCC.scala:122:7]
wire accumulator_io_cmd_bits_status_sbe; // @[LazyRoCC.scala:122:7]
wire [1:0] accumulator_io_cmd_bits_status_sxl; // @[LazyRoCC.scala:122:7]
wire [1:0] accumulator_io_cmd_bits_status_uxl; // @[LazyRoCC.scala:122:7]
wire accumulator_io_cmd_bits_status_sd_rv32; // @[LazyRoCC.scala:122:7]
wire [7:0] accumulator_io_cmd_bits_status_zero1; // @[LazyRoCC.scala:122:7]
wire accumulator_io_cmd_bits_status_tsr; // @[LazyRoCC.scala:122:7]
wire accumulator_io_cmd_bits_status_tw; // @[LazyRoCC.scala:122:7]
wire accumulator_io_cmd_bits_status_tvm; // @[LazyRoCC.scala:122:7]
wire accumulator_io_cmd_bits_status_mxr; // @[LazyRoCC.scala:122:7]
wire accumulator_io_cmd_bits_status_sum; // @[LazyRoCC.scala:122:7]
wire accumulator_io_cmd_bits_status_mprv; // @[LazyRoCC.scala:122:7]
wire [1:0] accumulator_io_cmd_bits_status_xs; // @[LazyRoCC.scala:122:7]
wire [1:0] accumulator_io_cmd_bits_status_fs; // @[LazyRoCC.scala:122:7]
wire [1:0] accumulator_io_cmd_bits_status_mpp; // @[LazyRoCC.scala:122:7]
wire [1:0] accumulator_io_cmd_bits_status_vs; // @[LazyRoCC.scala:122:7]
wire accumulator_io_cmd_bits_status_spp; // @[LazyRoCC.scala:122:7]
wire accumulator_io_cmd_bits_status_mpie; // @[LazyRoCC.scala:122:7]
wire accumulator_io_cmd_bits_status_ube; // @[LazyRoCC.scala:122:7]
wire accumulator_io_cmd_bits_status_spie; // @[LazyRoCC.scala:122:7]
wire accumulator_io_cmd_bits_status_upie; // @[LazyRoCC.scala:122:7]
wire accumulator_io_cmd_bits_status_mie; // @[LazyRoCC.scala:122:7]
wire accumulator_io_cmd_bits_status_hie; // @[LazyRoCC.scala:122:7]
wire accumulator_io_cmd_bits_status_sie; // @[LazyRoCC.scala:122:7]
wire accumulator_io_cmd_bits_status_uie; // @[LazyRoCC.scala:122:7]
wire [63:0] accumulator_io_cmd_bits_rs1; // @[LazyRoCC.scala:122:7]
wire [63:0] accumulator_io_cmd_bits_rs2; // @[LazyRoCC.scala:122:7]
wire accumulator_io_cmd_ready; // @[LazyRoCC.scala:122:7]
wire accumulator_io_cmd_valid; // @[LazyRoCC.scala:122:7]
wire [4:0] accumulator_io_resp_bits_rd; // @[LazyRoCC.scala:122:7]
wire [63:0] accumulator_io_resp_bits_data; // @[LazyRoCC.scala:122:7]
wire accumulator_io_resp_ready; // @[LazyRoCC.scala:122:7]
wire accumulator_io_resp_valid; // @[LazyRoCC.scala:122:7]
wire [39:0] accumulator_io_mem_req_bits_addr; // @[LazyRoCC.scala:122:7]
wire [7:0] accumulator_io_mem_req_bits_tag; // @[LazyRoCC.scala:122:7]
wire [1:0] accumulator_io_mem_req_bits_dprv; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_req_bits_dv; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_req_ready; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_req_valid; // @[LazyRoCC.scala:122:7]
wire [39:0] accumulator_io_mem_resp_bits_addr; // @[LazyRoCC.scala:122:7]
wire [7:0] accumulator_io_mem_resp_bits_tag; // @[LazyRoCC.scala:122:7]
wire [4:0] accumulator_io_mem_resp_bits_cmd; // @[LazyRoCC.scala:122:7]
wire [1:0] accumulator_io_mem_resp_bits_size; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_resp_bits_signed; // @[LazyRoCC.scala:122:7]
wire [1:0] accumulator_io_mem_resp_bits_dprv; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_resp_bits_dv; // @[LazyRoCC.scala:122:7]
wire [63:0] accumulator_io_mem_resp_bits_data; // @[LazyRoCC.scala:122:7]
wire [7:0] accumulator_io_mem_resp_bits_mask; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_resp_bits_replay; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_resp_bits_has_data; // @[LazyRoCC.scala:122:7]
wire [63:0] accumulator_io_mem_resp_bits_data_word_bypass; // @[LazyRoCC.scala:122:7]
wire [63:0] accumulator_io_mem_resp_bits_data_raw; // @[LazyRoCC.scala:122:7]
wire [63:0] accumulator_io_mem_resp_bits_store_data; // @[LazyRoCC.scala:122:7]
wire accumulator_io_mem_resp_valid; // @[LazyRoCC.scala:122:7]
wire accumulator_io_busy; // @[LazyRoCC.scala:122:7]
reg accumulator_busy_0; // @[LazyRoCC.scala:125:21]
reg accumulator_busy_1; // @[LazyRoCC.scala:125:21]
reg accumulator_busy_2; // @[LazyRoCC.scala:125:21]
reg accumulator_busy_3; // @[LazyRoCC.scala:125:21]
wire [1:0] accumulator_addr = _accumulator_cmd_q_io_deq_bits_rs2[1:0]; // @[Decoupled.scala:362:21]
wire accumulator_doWrite = _accumulator_cmd_q_io_deq_bits_inst_funct == 7'h0; // @[Decoupled.scala:362:21]
wire accumulator_doRead = _accumulator_cmd_q_io_deq_bits_inst_funct == 7'h1; // @[Decoupled.scala:362:21]
wire accumulator_doLoad = _accumulator_cmd_q_io_deq_bits_inst_funct == 7'h2; // @[Decoupled.scala:362:21]
wire accumulator_doAccum = _accumulator_cmd_q_io_deq_bits_inst_funct == 7'h3; // @[Decoupled.scala:362:21]
wire [1:0] accumulator_memRespTag = accumulator_io_mem_resp_bits_tag[1:0]; // @[LazyRoCC.scala:122:7, :134:40]
wire [64:0] accumulator__wdata_T = {1'h0, _regfile_ext_R0_data} + {1'h0, _accumulator_cmd_q_io_deq_bits_rs1}; // @[Decoupled.scala:362:21]
wire [63:0] accumulator__wdata_T_1 = accumulator__wdata_T[63:0]; // @[LazyRoCC.scala:139:42]
wire [63:0] accumulator_wdata = accumulator_doWrite ? _accumulator_cmd_q_io_deq_bits_rs1 : accumulator__wdata_T_1; // @[Decoupled.scala:362:21]
wire accumulator__q_io_deq_ready_T_4; // @[LazyRoCC.scala:160:40]
wire accumulator__stallLoad_T = ~accumulator_io_mem_req_ready; // @[LazyRoCC.scala:122:7, :157:29]
wire accumulator_stallLoad = accumulator_doLoad & accumulator__stallLoad_T; // @[LazyRoCC.scala:132:22, :157:{26,29}]
wire accumulator__stallResp_T = ~accumulator_io_resp_ready; // @[LazyRoCC.scala:122:7, :158:29]
wire accumulator_stallResp = _accumulator_cmd_q_io_deq_bits_inst_xd & accumulator__stallResp_T; // @[Decoupled.scala:362:21]
wire [3:0] _GEN = {{accumulator_busy_3}, {accumulator_busy_2}, {accumulator_busy_1}, {accumulator_busy_0}}; // @[LazyRoCC.scala:125:21, :160:16]
wire accumulator__q_io_deq_ready_T = ~_GEN[accumulator_addr]; // @[LazyRoCC.scala:129:26, :160:16]
wire accumulator__q_io_deq_ready_T_1 = ~accumulator_stallLoad; // @[LazyRoCC.scala:157:26, :160:29]
wire accumulator__q_io_deq_ready_T_2 = accumulator__q_io_deq_ready_T & accumulator__q_io_deq_ready_T_1; // @[LazyRoCC.scala:160:{16,26,29}]
wire accumulator__q_io_deq_ready_T_3 = ~accumulator_stallResp; // @[LazyRoCC.scala:158:26, :160:43]
assign accumulator__q_io_deq_ready_T_4 = accumulator__q_io_deq_ready_T_2 & accumulator__q_io_deq_ready_T_3; // @[LazyRoCC.scala:160:{26,40,43}]
wire accumulator__io_resp_valid_T = _accumulator_cmd_q_io_deq_valid & _accumulator_cmd_q_io_deq_bits_inst_xd; // @[Decoupled.scala:362:21]
wire accumulator__io_resp_valid_T_1 = ~_GEN[accumulator_addr]; // @[LazyRoCC.scala:129:26, :160:16, :164:43]
wire accumulator__io_resp_valid_T_2 = accumulator__io_resp_valid_T & accumulator__io_resp_valid_T_1; // @[LazyRoCC.scala:164:{30,40,43}]
wire accumulator__io_resp_valid_T_3 = ~accumulator_stallLoad; // @[LazyRoCC.scala:157:26, :160:29, :164:56]
assign accumulator__io_resp_valid_T_4 = accumulator__io_resp_valid_T_2 & accumulator__io_resp_valid_T_3; // @[LazyRoCC.scala:164:{40,53,56}]
assign accumulator_io_resp_valid = accumulator__io_resp_valid_T_4; // @[LazyRoCC.scala:122:7, :164:53]
wire accumulator__io_busy_T = accumulator_busy_0 | accumulator_busy_1; // @[LazyRoCC.scala:125:21, :171:40]
wire accumulator__io_busy_T_1 = accumulator__io_busy_T | accumulator_busy_2; // @[LazyRoCC.scala:125:21, :171:40]
wire accumulator__io_busy_T_2 = accumulator__io_busy_T_1 | accumulator_busy_3; // @[LazyRoCC.scala:125:21, :171:40]
assign accumulator__io_busy_T_3 = _accumulator_cmd_q_io_deq_valid | accumulator__io_busy_T_2; // @[Decoupled.scala:362:21]
assign accumulator_io_busy = accumulator__io_busy_T_3; // @[LazyRoCC.scala:122:7, :171:24]
wire accumulator__io_mem_req_valid_T = _accumulator_cmd_q_io_deq_valid & accumulator_doLoad; // @[Decoupled.scala:362:21]
wire accumulator__io_mem_req_valid_T_1 = ~_GEN[accumulator_addr]; // @[LazyRoCC.scala:129:26, :160:16, :177:46]
wire accumulator__io_mem_req_valid_T_2 = accumulator__io_mem_req_valid_T & accumulator__io_mem_req_valid_T_1; // @[LazyRoCC.scala:177:{33,43,46}]
wire accumulator__io_mem_req_valid_T_3 = ~accumulator_stallResp; // @[LazyRoCC.scala:158:26, :160:43, :177:59]
assign accumulator__io_mem_req_valid_T_4 = accumulator__io_mem_req_valid_T_2 & accumulator__io_mem_req_valid_T_3; // @[LazyRoCC.scala:177:{43,56,59}]
assign accumulator_io_mem_req_valid = accumulator__io_mem_req_valid_T_4; // @[LazyRoCC.scala:122:7, :177:56]
assign accumulator_io_mem_req_bits_addr = _accumulator_cmd_q_io_deq_bits_rs1[39:0]; // @[Decoupled.scala:362:21]
assign accumulator_io_mem_req_bits_tag = {6'h0, accumulator_addr}; // @[LazyRoCC.scala:122:7, :129:26, :131:22, :179:23]
wire xbar_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire widget_auto_anon_out_a_ready = xbar_auto_anon_in_a_ready; // @[Xbar.scala:74:9]
wire widget_auto_anon_out_a_valid; // @[WidthWidget.scala:27:9]
wire xbar_anonIn_a_valid = xbar_auto_anon_in_a_valid; // @[Xbar.scala:74:9]
wire [2:0] widget_auto_anon_out_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] xbar_anonIn_a_bits_opcode = xbar_auto_anon_in_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] widget_auto_anon_out_a_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] xbar_anonIn_a_bits_param = xbar_auto_anon_in_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] widget_auto_anon_out_a_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] xbar_anonIn_a_bits_size = xbar_auto_anon_in_a_bits_size; // @[Xbar.scala:74:9]
wire widget_auto_anon_out_a_bits_source; // @[WidthWidget.scala:27:9]
wire xbar_anonIn_a_bits_source = xbar_auto_anon_in_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] widget_auto_anon_out_a_bits_address; // @[WidthWidget.scala:27:9]
wire [31:0] xbar_anonIn_a_bits_address = xbar_auto_anon_in_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] widget_auto_anon_out_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [7:0] xbar_anonIn_a_bits_mask = xbar_auto_anon_in_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] widget_auto_anon_out_a_bits_data; // @[WidthWidget.scala:27:9]
wire [63:0] xbar_anonIn_a_bits_data = xbar_auto_anon_in_a_bits_data; // @[Xbar.scala:74:9]
wire widget_auto_anon_out_b_ready; // @[WidthWidget.scala:27:9]
wire xbar_anonIn_b_ready = xbar_auto_anon_in_b_ready; // @[Xbar.scala:74:9]
wire xbar_anonIn_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] xbar_anonIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire widget_auto_anon_out_b_valid = xbar_auto_anon_in_b_valid; // @[Xbar.scala:74:9]
wire [1:0] xbar_anonIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] widget_auto_anon_out_b_bits_opcode = xbar_auto_anon_in_b_bits_opcode; // @[Xbar.scala:74:9]
wire [3:0] xbar_anonIn_b_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] widget_auto_anon_out_b_bits_param = xbar_auto_anon_in_b_bits_param; // @[Xbar.scala:74:9]
wire xbar_anonIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] widget_auto_anon_out_b_bits_size = xbar_auto_anon_in_b_bits_size; // @[Xbar.scala:74:9]
wire [31:0] xbar_anonIn_b_bits_address; // @[MixedNode.scala:551:17]
wire widget_auto_anon_out_b_bits_source = xbar_auto_anon_in_b_bits_source; // @[Xbar.scala:74:9]
wire [7:0] xbar_anonIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [31:0] widget_auto_anon_out_b_bits_address = xbar_auto_anon_in_b_bits_address; // @[Xbar.scala:74:9]
wire [63:0] xbar_anonIn_b_bits_data; // @[MixedNode.scala:551:17]
wire [7:0] widget_auto_anon_out_b_bits_mask = xbar_auto_anon_in_b_bits_mask; // @[Xbar.scala:74:9]
wire xbar_anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire [63:0] widget_auto_anon_out_b_bits_data = xbar_auto_anon_in_b_bits_data; // @[Xbar.scala:74:9]
wire xbar_anonIn_c_ready; // @[MixedNode.scala:551:17]
wire widget_auto_anon_out_b_bits_corrupt = xbar_auto_anon_in_b_bits_corrupt; // @[Xbar.scala:74:9]
wire widget_auto_anon_out_c_ready = xbar_auto_anon_in_c_ready; // @[Xbar.scala:74:9]
wire widget_auto_anon_out_c_valid; // @[WidthWidget.scala:27:9]
wire xbar_anonIn_c_valid = xbar_auto_anon_in_c_valid; // @[Xbar.scala:74:9]
wire [2:0] widget_auto_anon_out_c_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] xbar_anonIn_c_bits_opcode = xbar_auto_anon_in_c_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] widget_auto_anon_out_c_bits_param; // @[WidthWidget.scala:27:9]
wire [2:0] xbar_anonIn_c_bits_param = xbar_auto_anon_in_c_bits_param; // @[Xbar.scala:74:9]
wire [3:0] widget_auto_anon_out_c_bits_size; // @[WidthWidget.scala:27:9]
wire [3:0] xbar_anonIn_c_bits_size = xbar_auto_anon_in_c_bits_size; // @[Xbar.scala:74:9]
wire widget_auto_anon_out_c_bits_source; // @[WidthWidget.scala:27:9]
wire xbar_anonIn_c_bits_source = xbar_auto_anon_in_c_bits_source; // @[Xbar.scala:74:9]
wire [31:0] widget_auto_anon_out_c_bits_address; // @[WidthWidget.scala:27:9]
wire [31:0] xbar_anonIn_c_bits_address = xbar_auto_anon_in_c_bits_address; // @[Xbar.scala:74:9]
wire [63:0] widget_auto_anon_out_c_bits_data; // @[WidthWidget.scala:27:9]
wire [63:0] xbar_anonIn_c_bits_data = xbar_auto_anon_in_c_bits_data; // @[Xbar.scala:74:9]
wire widget_auto_anon_out_d_ready; // @[WidthWidget.scala:27:9]
wire xbar_anonIn_d_ready = xbar_auto_anon_in_d_ready; // @[Xbar.scala:74:9]
wire xbar_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] xbar_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire widget_auto_anon_out_d_valid = xbar_auto_anon_in_d_valid; // @[Xbar.scala:74:9]
wire [1:0] xbar_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [2:0] widget_auto_anon_out_d_bits_opcode = xbar_auto_anon_in_d_bits_opcode; // @[Xbar.scala:74:9]
wire [3:0] xbar_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] widget_auto_anon_out_d_bits_param = xbar_auto_anon_in_d_bits_param; // @[Xbar.scala:74:9]
wire xbar_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] widget_auto_anon_out_d_bits_size = xbar_auto_anon_in_d_bits_size; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire widget_auto_anon_out_d_bits_source = xbar_auto_anon_in_d_bits_source; // @[Xbar.scala:74:9]
wire xbar_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [2:0] widget_auto_anon_out_d_bits_sink = xbar_auto_anon_in_d_bits_sink; // @[Xbar.scala:74:9]
wire [63:0] xbar_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire widget_auto_anon_out_d_bits_denied = xbar_auto_anon_in_d_bits_denied; // @[Xbar.scala:74:9]
wire xbar_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire [63:0] widget_auto_anon_out_d_bits_data = xbar_auto_anon_in_d_bits_data; // @[Xbar.scala:74:9]
wire xbar_anonIn_e_ready; // @[MixedNode.scala:551:17]
wire widget_auto_anon_out_d_bits_corrupt = xbar_auto_anon_in_d_bits_corrupt; // @[Xbar.scala:74:9]
wire widget_auto_anon_out_e_ready = xbar_auto_anon_in_e_ready; // @[Xbar.scala:74:9]
wire widget_auto_anon_out_e_valid; // @[WidthWidget.scala:27:9]
wire xbar_anonIn_e_valid = xbar_auto_anon_in_e_valid; // @[Xbar.scala:74:9]
wire [2:0] widget_auto_anon_out_e_bits_sink; // @[WidthWidget.scala:27:9]
wire [2:0] xbar_anonIn_e_bits_sink = xbar_auto_anon_in_e_bits_sink; // @[Xbar.scala:74:9]
wire xbar_anonOut_a_ready = xbar_auto_anon_out_a_ready; // @[Xbar.scala:74:9]
wire xbar_anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] xbar_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] xbar_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] xbar_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire xbar_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] xbar_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] xbar_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] xbar_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire xbar_anonOut_b_ready; // @[MixedNode.scala:542:17]
wire xbar_anonOut_b_valid = xbar_auto_anon_out_b_valid; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonOut_b_bits_opcode = xbar_auto_anon_out_b_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] xbar_anonOut_b_bits_param = xbar_auto_anon_out_b_bits_param; // @[Xbar.scala:74:9]
wire [3:0] xbar_anonOut_b_bits_size = xbar_auto_anon_out_b_bits_size; // @[Xbar.scala:74:9]
wire xbar_anonOut_b_bits_source = xbar_auto_anon_out_b_bits_source; // @[Xbar.scala:74:9]
wire [31:0] xbar_anonOut_b_bits_address = xbar_auto_anon_out_b_bits_address; // @[Xbar.scala:74:9]
wire [7:0] xbar_anonOut_b_bits_mask = xbar_auto_anon_out_b_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] xbar_anonOut_b_bits_data = xbar_auto_anon_out_b_bits_data; // @[Xbar.scala:74:9]
wire xbar_anonOut_b_bits_corrupt = xbar_auto_anon_out_b_bits_corrupt; // @[Xbar.scala:74:9]
wire xbar_anonOut_c_ready = xbar_auto_anon_out_c_ready; // @[Xbar.scala:74:9]
wire xbar_anonOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] xbar_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] xbar_anonOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] xbar_anonOut_c_bits_size; // @[MixedNode.scala:542:17]
wire xbar_anonOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] xbar_anonOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] xbar_anonOut_c_bits_data; // @[MixedNode.scala:542:17]
wire xbar_anonOut_d_ready; // @[MixedNode.scala:542:17]
wire xbar_anonOut_d_valid = xbar_auto_anon_out_d_valid; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonOut_d_bits_opcode = xbar_auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] xbar_anonOut_d_bits_param = xbar_auto_anon_out_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] xbar_anonOut_d_bits_size = xbar_auto_anon_out_d_bits_size; // @[Xbar.scala:74:9]
wire xbar_anonOut_d_bits_source = xbar_auto_anon_out_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] xbar_anonOut_d_bits_sink = xbar_auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9]
wire xbar_anonOut_d_bits_denied = xbar_auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] xbar_anonOut_d_bits_data = xbar_auto_anon_out_d_bits_data; // @[Xbar.scala:74:9]
wire xbar_anonOut_d_bits_corrupt = xbar_auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9]
wire xbar_anonOut_e_ready = xbar_auto_anon_out_e_ready; // @[Xbar.scala:74:9]
wire xbar_anonOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] xbar_anonOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire [2:0] xbar_auto_anon_out_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_out_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] xbar_auto_anon_out_a_bits_size; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] xbar_auto_anon_out_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] xbar_auto_anon_out_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] xbar_auto_anon_out_a_bits_data; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_a_valid; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_b_ready; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_out_c_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_out_c_bits_param; // @[Xbar.scala:74:9]
wire [3:0] xbar_auto_anon_out_c_bits_size; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_c_bits_source; // @[Xbar.scala:74:9]
wire [31:0] xbar_auto_anon_out_c_bits_address; // @[Xbar.scala:74:9]
wire [63:0] xbar_auto_anon_out_c_bits_data; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_c_valid; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_d_ready; // @[Xbar.scala:74:9]
wire [2:0] xbar_auto_anon_out_e_bits_sink; // @[Xbar.scala:74:9]
wire xbar_auto_anon_out_e_valid; // @[Xbar.scala:74:9]
wire xbar_out_0_a_ready = xbar_anonOut_a_ready; // @[Xbar.scala:216:19]
wire xbar_out_0_a_valid; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_valid = xbar_anonOut_a_valid; // @[Xbar.scala:74:9]
wire [2:0] xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_opcode = xbar_anonOut_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] xbar_out_0_a_bits_param; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_param = xbar_anonOut_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] xbar_out_0_a_bits_size; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_size = xbar_anonOut_a_bits_size; // @[Xbar.scala:74:9]
wire xbar_out_0_a_bits_source; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_source = xbar_anonOut_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] xbar_out_0_a_bits_address; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_address = xbar_anonOut_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_mask = xbar_anonOut_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] xbar_out_0_a_bits_data; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_a_bits_data = xbar_anonOut_a_bits_data; // @[Xbar.scala:74:9]
wire xbar_out_0_b_ready; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_b_ready = xbar_anonOut_b_ready; // @[Xbar.scala:74:9]
wire xbar_out_0_b_valid = xbar_anonOut_b_valid; // @[Xbar.scala:216:19]
wire [2:0] xbar_out_0_b_bits_opcode = xbar_anonOut_b_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] xbar_out_0_b_bits_param = xbar_anonOut_b_bits_param; // @[Xbar.scala:216:19]
wire [3:0] xbar_out_0_b_bits_size = xbar_anonOut_b_bits_size; // @[Xbar.scala:216:19]
wire xbar_out_0_b_bits_source = xbar_anonOut_b_bits_source; // @[Xbar.scala:216:19]
wire [31:0] xbar_out_0_b_bits_address = xbar_anonOut_b_bits_address; // @[Xbar.scala:216:19]
wire [7:0] xbar_out_0_b_bits_mask = xbar_anonOut_b_bits_mask; // @[Xbar.scala:216:19]
wire [63:0] xbar_out_0_b_bits_data = xbar_anonOut_b_bits_data; // @[Xbar.scala:216:19]
wire xbar_out_0_b_bits_corrupt = xbar_anonOut_b_bits_corrupt; // @[Xbar.scala:216:19]
wire xbar_out_0_c_ready = xbar_anonOut_c_ready; // @[Xbar.scala:216:19]
wire xbar_out_0_c_valid; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_c_valid = xbar_anonOut_c_valid; // @[Xbar.scala:74:9]
wire [2:0] xbar_out_0_c_bits_opcode; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_c_bits_opcode = xbar_anonOut_c_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] xbar_out_0_c_bits_param; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_c_bits_param = xbar_anonOut_c_bits_param; // @[Xbar.scala:74:9]
wire [3:0] xbar_out_0_c_bits_size; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_c_bits_size = xbar_anonOut_c_bits_size; // @[Xbar.scala:74:9]
wire xbar_out_0_c_bits_source; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_c_bits_source = xbar_anonOut_c_bits_source; // @[Xbar.scala:74:9]
wire [31:0] xbar_out_0_c_bits_address; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_c_bits_address = xbar_anonOut_c_bits_address; // @[Xbar.scala:74:9]
wire [63:0] xbar_out_0_c_bits_data; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_c_bits_data = xbar_anonOut_c_bits_data; // @[Xbar.scala:74:9]
wire xbar_out_0_d_ready; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_d_ready = xbar_anonOut_d_ready; // @[Xbar.scala:74:9]
wire xbar_out_0_d_valid = xbar_anonOut_d_valid; // @[Xbar.scala:216:19]
wire [2:0] xbar_out_0_d_bits_opcode = xbar_anonOut_d_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] xbar_out_0_d_bits_param = xbar_anonOut_d_bits_param; // @[Xbar.scala:216:19]
wire [3:0] xbar_out_0_d_bits_size = xbar_anonOut_d_bits_size; // @[Xbar.scala:216:19]
wire xbar_out_0_d_bits_source = xbar_anonOut_d_bits_source; // @[Xbar.scala:216:19]
wire [2:0] xbar__out_0_d_bits_sink_T = xbar_anonOut_d_bits_sink; // @[Xbar.scala:251:53]
wire xbar_out_0_d_bits_denied = xbar_anonOut_d_bits_denied; // @[Xbar.scala:216:19]
wire [63:0] xbar_out_0_d_bits_data = xbar_anonOut_d_bits_data; // @[Xbar.scala:216:19]
wire xbar_out_0_d_bits_corrupt = xbar_anonOut_d_bits_corrupt; // @[Xbar.scala:216:19]
wire xbar_out_0_e_ready = xbar_anonOut_e_ready; // @[Xbar.scala:216:19]
wire xbar_out_0_e_valid; // @[Xbar.scala:216:19]
assign xbar_auto_anon_out_e_valid = xbar_anonOut_e_valid; // @[Xbar.scala:74:9]
wire [2:0] xbar__anonOut_e_bits_sink_T; // @[Xbar.scala:156:69]
assign xbar_auto_anon_out_e_bits_sink = xbar_anonOut_e_bits_sink; // @[Xbar.scala:74:9]
wire xbar_in_0_a_ready; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_a_ready = xbar_anonIn_a_ready; // @[Xbar.scala:74:9]
wire xbar_in_0_a_valid = xbar_anonIn_a_valid; // @[Xbar.scala:159:18]
wire [2:0] xbar_in_0_a_bits_opcode = xbar_anonIn_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] xbar_in_0_a_bits_param = xbar_anonIn_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] xbar_in_0_a_bits_size = xbar_anonIn_a_bits_size; // @[Xbar.scala:159:18]
wire xbar__in_0_a_bits_source_T = xbar_anonIn_a_bits_source; // @[Xbar.scala:166:55]
wire [31:0] xbar_in_0_a_bits_address = xbar_anonIn_a_bits_address; // @[Xbar.scala:159:18]
wire [7:0] xbar_in_0_a_bits_mask = xbar_anonIn_a_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] xbar_in_0_a_bits_data = xbar_anonIn_a_bits_data; // @[Xbar.scala:159:18]
wire xbar_in_0_b_ready = xbar_anonIn_b_ready; // @[Xbar.scala:159:18]
wire xbar_in_0_b_valid; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_b_valid = xbar_anonIn_b_valid; // @[Xbar.scala:74:9]
wire [2:0] xbar_in_0_b_bits_opcode; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_b_bits_opcode = xbar_anonIn_b_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] xbar_in_0_b_bits_param; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_b_bits_param = xbar_anonIn_b_bits_param; // @[Xbar.scala:74:9]
wire [3:0] xbar_in_0_b_bits_size; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_b_bits_size = xbar_anonIn_b_bits_size; // @[Xbar.scala:74:9]
wire xbar__anonIn_b_bits_source_T; // @[Xbar.scala:156:69]
assign xbar_auto_anon_in_b_bits_source = xbar_anonIn_b_bits_source; // @[Xbar.scala:74:9]
wire [31:0] xbar_in_0_b_bits_address; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_b_bits_address = xbar_anonIn_b_bits_address; // @[Xbar.scala:74:9]
wire [7:0] xbar_in_0_b_bits_mask; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_b_bits_mask = xbar_anonIn_b_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] xbar_in_0_b_bits_data; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_b_bits_data = xbar_anonIn_b_bits_data; // @[Xbar.scala:74:9]
wire xbar_in_0_b_bits_corrupt; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_b_bits_corrupt = xbar_anonIn_b_bits_corrupt; // @[Xbar.scala:74:9]
wire xbar_in_0_c_ready; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_c_ready = xbar_anonIn_c_ready; // @[Xbar.scala:74:9]
wire xbar_in_0_c_valid = xbar_anonIn_c_valid; // @[Xbar.scala:159:18]
wire [2:0] xbar_in_0_c_bits_opcode = xbar_anonIn_c_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] xbar_in_0_c_bits_param = xbar_anonIn_c_bits_param; // @[Xbar.scala:159:18]
wire [3:0] xbar_in_0_c_bits_size = xbar_anonIn_c_bits_size; // @[Xbar.scala:159:18]
wire xbar__in_0_c_bits_source_T = xbar_anonIn_c_bits_source; // @[Xbar.scala:187:55]
wire [31:0] xbar_in_0_c_bits_address = xbar_anonIn_c_bits_address; // @[Xbar.scala:159:18]
wire [63:0] xbar_in_0_c_bits_data = xbar_anonIn_c_bits_data; // @[Xbar.scala:159:18]
wire xbar_in_0_d_ready = xbar_anonIn_d_ready; // @[Xbar.scala:159:18]
wire xbar_in_0_d_valid; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_valid = xbar_anonIn_d_valid; // @[Xbar.scala:74:9]
wire [2:0] xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_opcode = xbar_anonIn_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] xbar_in_0_d_bits_param; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_param = xbar_anonIn_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] xbar_in_0_d_bits_size; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_size = xbar_anonIn_d_bits_size; // @[Xbar.scala:74:9]
wire xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign xbar_auto_anon_in_d_bits_source = xbar_anonIn_d_bits_source; // @[Xbar.scala:74:9]
wire [2:0] xbar_in_0_d_bits_sink; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_sink = xbar_anonIn_d_bits_sink; // @[Xbar.scala:74:9]
wire xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_denied = xbar_anonIn_d_bits_denied; // @[Xbar.scala:74:9]
wire [63:0] xbar_in_0_d_bits_data; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_data = xbar_anonIn_d_bits_data; // @[Xbar.scala:74:9]
wire xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_d_bits_corrupt = xbar_anonIn_d_bits_corrupt; // @[Xbar.scala:74:9]
wire xbar_in_0_e_ready; // @[Xbar.scala:159:18]
assign xbar_auto_anon_in_e_ready = xbar_anonIn_e_ready; // @[Xbar.scala:74:9]
wire xbar_in_0_e_valid = xbar_anonIn_e_valid; // @[Xbar.scala:159:18]
wire [2:0] xbar_in_0_e_bits_sink = xbar_anonIn_e_bits_sink; // @[Xbar.scala:159:18]
wire xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign xbar_anonIn_a_ready = xbar_in_0_a_ready; // @[Xbar.scala:159:18]
wire xbar__portsAOI_filtered_0_valid_T_1 = xbar_in_0_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] xbar_portsAOI_filtered_0_bits_opcode = xbar_in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] xbar_portsAOI_filtered_0_bits_param = xbar_in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [3:0] xbar_portsAOI_filtered_0_bits_size = xbar_in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire xbar_portsAOI_filtered_0_bits_source = xbar_in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] xbar__requestAIO_T = xbar_in_0_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] xbar_portsAOI_filtered_0_bits_address = xbar_in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [7:0] xbar_portsAOI_filtered_0_bits_mask = xbar_in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [63:0] xbar_portsAOI_filtered_0_bits_data = xbar_in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire xbar_portsBIO_filtered_0_ready = xbar_in_0_b_ready; // @[Xbar.scala:159:18, :352:24]
wire xbar_portsBIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign xbar_anonIn_b_valid = xbar_in_0_b_valid; // @[Xbar.scala:159:18]
wire [2:0] xbar_portsBIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24]
assign xbar_anonIn_b_bits_opcode = xbar_in_0_b_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] xbar_portsBIO_filtered_0_bits_param; // @[Xbar.scala:352:24]
assign xbar_anonIn_b_bits_param = xbar_in_0_b_bits_param; // @[Xbar.scala:159:18]
wire [3:0] xbar_portsBIO_filtered_0_bits_size; // @[Xbar.scala:352:24]
assign xbar_anonIn_b_bits_size = xbar_in_0_b_bits_size; // @[Xbar.scala:159:18]
wire xbar_portsBIO_filtered_0_bits_source; // @[Xbar.scala:352:24]
assign xbar__anonIn_b_bits_source_T = xbar_in_0_b_bits_source; // @[Xbar.scala:156:69, :159:18]
wire [31:0] xbar_portsBIO_filtered_0_bits_address; // @[Xbar.scala:352:24]
assign xbar_anonIn_b_bits_address = xbar_in_0_b_bits_address; // @[Xbar.scala:159:18]
wire [7:0] xbar_portsBIO_filtered_0_bits_mask; // @[Xbar.scala:352:24]
assign xbar_anonIn_b_bits_mask = xbar_in_0_b_bits_mask; // @[Xbar.scala:159:18]
wire [63:0] xbar_portsBIO_filtered_0_bits_data; // @[Xbar.scala:352:24]
assign xbar_anonIn_b_bits_data = xbar_in_0_b_bits_data; // @[Xbar.scala:159:18]
wire xbar_portsBIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24]
assign xbar_anonIn_b_bits_corrupt = xbar_in_0_b_bits_corrupt; // @[Xbar.scala:159:18]
wire xbar_portsCOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign xbar_anonIn_c_ready = xbar_in_0_c_ready; // @[Xbar.scala:159:18]
wire xbar__portsCOI_filtered_0_valid_T_1 = xbar_in_0_c_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] xbar_portsCOI_filtered_0_bits_opcode = xbar_in_0_c_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] xbar_portsCOI_filtered_0_bits_param = xbar_in_0_c_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [3:0] xbar_portsCOI_filtered_0_bits_size = xbar_in_0_c_bits_size; // @[Xbar.scala:159:18, :352:24]
wire xbar_portsCOI_filtered_0_bits_source = xbar_in_0_c_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] xbar__requestCIO_T = xbar_in_0_c_bits_address; // @[Xbar.scala:159:18]
wire [31:0] xbar_portsCOI_filtered_0_bits_address = xbar_in_0_c_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [63:0] xbar_portsCOI_filtered_0_bits_data = xbar_in_0_c_bits_data; // @[Xbar.scala:159:18, :352:24]
wire xbar_portsDIO_filtered_0_ready = xbar_in_0_d_ready; // @[Xbar.scala:159:18, :352:24]
wire xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_valid = xbar_in_0_d_valid; // @[Xbar.scala:159:18]
wire [2:0] xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_opcode = xbar_in_0_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] xbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_param = xbar_in_0_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_size = xbar_in_0_d_bits_size; // @[Xbar.scala:159:18]
wire xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24]
assign xbar__anonIn_d_bits_source_T = xbar_in_0_d_bits_source; // @[Xbar.scala:156:69, :159:18]
wire [2:0] xbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_sink = xbar_in_0_d_bits_sink; // @[Xbar.scala:159:18]
wire xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_denied = xbar_in_0_d_bits_denied; // @[Xbar.scala:159:18]
wire [63:0] xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_data = xbar_in_0_d_bits_data; // @[Xbar.scala:159:18]
wire xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24]
assign xbar_anonIn_d_bits_corrupt = xbar_in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
wire xbar_portsEOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign xbar_anonIn_e_ready = xbar_in_0_e_ready; // @[Xbar.scala:159:18]
wire xbar__portsEOI_filtered_0_valid_T_1 = xbar_in_0_e_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] xbar__requestEIO_uncommonBits_T = xbar_in_0_e_bits_sink; // @[Xbar.scala:159:18]
wire [2:0] xbar_portsEOI_filtered_0_bits_sink = xbar_in_0_e_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_a_bits_source = xbar__in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55]
assign xbar_anonIn_b_bits_source = xbar__anonIn_b_bits_source_T; // @[Xbar.scala:156:69]
assign xbar_in_0_c_bits_source = xbar__in_0_c_bits_source_T; // @[Xbar.scala:159:18, :187:55]
assign xbar_anonIn_d_bits_source = xbar__anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign xbar_portsAOI_filtered_0_ready = xbar_out_0_a_ready; // @[Xbar.scala:216:19, :352:24]
wire xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign xbar_anonOut_a_valid = xbar_out_0_a_valid; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_opcode = xbar_out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_param = xbar_out_0_a_bits_param; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_size = xbar_out_0_a_bits_size; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_source = xbar_out_0_a_bits_source; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_address = xbar_out_0_a_bits_address; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_mask = xbar_out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign xbar_anonOut_a_bits_data = xbar_out_0_a_bits_data; // @[Xbar.scala:216:19]
assign xbar_anonOut_b_ready = xbar_out_0_b_ready; // @[Xbar.scala:216:19]
wire xbar__portsBIO_filtered_0_valid_T_1 = xbar_out_0_b_valid; // @[Xbar.scala:216:19, :355:40]
assign xbar_portsBIO_filtered_0_bits_opcode = xbar_out_0_b_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsBIO_filtered_0_bits_param = xbar_out_0_b_bits_param; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsBIO_filtered_0_bits_size = xbar_out_0_b_bits_size; // @[Xbar.scala:216:19, :352:24]
wire xbar__requestBOI_uncommonBits_T = xbar_out_0_b_bits_source; // @[Xbar.scala:216:19]
assign xbar_portsBIO_filtered_0_bits_source = xbar_out_0_b_bits_source; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsBIO_filtered_0_bits_address = xbar_out_0_b_bits_address; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsBIO_filtered_0_bits_mask = xbar_out_0_b_bits_mask; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsBIO_filtered_0_bits_data = xbar_out_0_b_bits_data; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsBIO_filtered_0_bits_corrupt = xbar_out_0_b_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsCOI_filtered_0_ready = xbar_out_0_c_ready; // @[Xbar.scala:216:19, :352:24]
wire xbar_portsCOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign xbar_anonOut_c_valid = xbar_out_0_c_valid; // @[Xbar.scala:216:19]
assign xbar_anonOut_c_bits_opcode = xbar_out_0_c_bits_opcode; // @[Xbar.scala:216:19]
assign xbar_anonOut_c_bits_param = xbar_out_0_c_bits_param; // @[Xbar.scala:216:19]
assign xbar_anonOut_c_bits_size = xbar_out_0_c_bits_size; // @[Xbar.scala:216:19]
assign xbar_anonOut_c_bits_source = xbar_out_0_c_bits_source; // @[Xbar.scala:216:19]
assign xbar_anonOut_c_bits_address = xbar_out_0_c_bits_address; // @[Xbar.scala:216:19]
assign xbar_anonOut_c_bits_data = xbar_out_0_c_bits_data; // @[Xbar.scala:216:19]
assign xbar_anonOut_d_ready = xbar_out_0_d_ready; // @[Xbar.scala:216:19]
wire xbar__portsDIO_filtered_0_valid_T_1 = xbar_out_0_d_valid; // @[Xbar.scala:216:19, :355:40]
assign xbar_portsDIO_filtered_0_bits_opcode = xbar_out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsDIO_filtered_0_bits_param = xbar_out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsDIO_filtered_0_bits_size = xbar_out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire xbar__requestDOI_uncommonBits_T = xbar_out_0_d_bits_source; // @[Xbar.scala:216:19]
assign xbar_portsDIO_filtered_0_bits_source = xbar_out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsDIO_filtered_0_bits_sink = xbar_out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsDIO_filtered_0_bits_denied = xbar_out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsDIO_filtered_0_bits_data = xbar_out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsDIO_filtered_0_bits_corrupt = xbar_out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsEOI_filtered_0_ready = xbar_out_0_e_ready; // @[Xbar.scala:216:19, :352:24]
wire xbar_portsEOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign xbar_anonOut_e_valid = xbar_out_0_e_valid; // @[Xbar.scala:216:19]
assign xbar__anonOut_e_bits_sink_T = xbar_out_0_e_bits_sink; // @[Xbar.scala:156:69, :216:19]
assign xbar_out_0_d_bits_sink = xbar__out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53]
assign xbar_anonOut_e_bits_sink = xbar__anonOut_e_bits_sink_T; // @[Xbar.scala:156:69]
wire [32:0] xbar__requestAIO_T_1 = {1'h0, xbar__requestAIO_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] xbar__requestCIO_T_1 = {1'h0, xbar__requestCIO_T}; // @[Parameters.scala:137:{31,41}]
wire xbar_requestBOI_uncommonBits = xbar__requestBOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire xbar_requestDOI_uncommonBits = xbar__requestDOI_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [2:0] xbar_requestEIO_uncommonBits = xbar__requestEIO_uncommonBits_T; // @[Parameters.scala:52:{29,56}]
wire [26:0] xbar__beatsAI_decode_T = 27'hFFF << xbar_in_0_a_bits_size; // @[package.scala:243:71]
wire [11:0] xbar__beatsAI_decode_T_1 = xbar__beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] xbar__beatsAI_decode_T_2 = ~xbar__beatsAI_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] xbar_beatsAI_decode = xbar__beatsAI_decode_T_2[11:3]; // @[package.scala:243:46]
wire xbar__beatsAI_opdata_T = xbar_in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire xbar_beatsAI_opdata = ~xbar__beatsAI_opdata_T; // @[Edges.scala:92:{28,37}]
wire [8:0] xbar_beatsAI_0 = xbar_beatsAI_opdata ? xbar_beatsAI_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] xbar__beatsBO_decode_T = 27'hFFF << xbar_out_0_b_bits_size; // @[package.scala:243:71]
wire [11:0] xbar__beatsBO_decode_T_1 = xbar__beatsBO_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] xbar__beatsBO_decode_T_2 = ~xbar__beatsBO_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] xbar_beatsBO_decode = xbar__beatsBO_decode_T_2[11:3]; // @[package.scala:243:46]
wire xbar__beatsBO_opdata_T = xbar_out_0_b_bits_opcode[2]; // @[Xbar.scala:216:19]
wire xbar_beatsBO_opdata = ~xbar__beatsBO_opdata_T; // @[Edges.scala:97:{28,37}]
wire [26:0] xbar__beatsCI_decode_T = 27'hFFF << xbar_in_0_c_bits_size; // @[package.scala:243:71]
wire [11:0] xbar__beatsCI_decode_T_1 = xbar__beatsCI_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] xbar__beatsCI_decode_T_2 = ~xbar__beatsCI_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] xbar_beatsCI_decode = xbar__beatsCI_decode_T_2[11:3]; // @[package.scala:243:46]
wire xbar_beatsCI_opdata = xbar_in_0_c_bits_opcode[0]; // @[Xbar.scala:159:18]
wire [8:0] xbar_beatsCI_0 = xbar_beatsCI_opdata ? xbar_beatsCI_decode : 9'h0; // @[Edges.scala:102:36, :220:59, :221:14]
wire [26:0] xbar__beatsDO_decode_T = 27'hFFF << xbar_out_0_d_bits_size; // @[package.scala:243:71]
wire [11:0] xbar__beatsDO_decode_T_1 = xbar__beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] xbar__beatsDO_decode_T_2 = ~xbar__beatsDO_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] xbar_beatsDO_decode = xbar__beatsDO_decode_T_2[11:3]; // @[package.scala:243:46]
wire xbar_beatsDO_opdata = xbar_out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [8:0] xbar_beatsDO_0 = xbar_beatsDO_opdata ? xbar_beatsDO_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
assign xbar_in_0_a_ready = xbar_portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
assign xbar_out_0_a_valid = xbar_portsAOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_opcode = xbar_portsAOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_param = xbar_portsAOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_size = xbar_portsAOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_source = xbar_portsAOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_address = xbar_portsAOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_mask = xbar_portsAOI_filtered_0_bits_mask; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_a_bits_data = xbar_portsAOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsAOI_filtered_0_valid = xbar__portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign xbar_out_0_b_ready = xbar_portsBIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24]
assign xbar_in_0_b_valid = xbar_portsBIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_b_bits_opcode = xbar_portsBIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_b_bits_param = xbar_portsBIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_b_bits_size = xbar_portsBIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_b_bits_source = xbar_portsBIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_b_bits_address = xbar_portsBIO_filtered_0_bits_address; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_b_bits_mask = xbar_portsBIO_filtered_0_bits_mask; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_b_bits_data = xbar_portsBIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_b_bits_corrupt = xbar_portsBIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
assign xbar_portsBIO_filtered_0_valid = xbar__portsBIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign xbar_in_0_c_ready = xbar_portsCOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
assign xbar_out_0_c_valid = xbar_portsCOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_c_bits_opcode = xbar_portsCOI_filtered_0_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_c_bits_param = xbar_portsCOI_filtered_0_bits_param; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_c_bits_size = xbar_portsCOI_filtered_0_bits_size; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_c_bits_source = xbar_portsCOI_filtered_0_bits_source; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_c_bits_address = xbar_portsCOI_filtered_0_bits_address; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_c_bits_data = xbar_portsCOI_filtered_0_bits_data; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsCOI_filtered_0_valid = xbar__portsCOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign xbar_out_0_d_ready = xbar_portsDIO_filtered_0_ready; // @[Xbar.scala:216:19, :352:24]
assign xbar_in_0_d_valid = xbar_portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_opcode = xbar_portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_param = xbar_portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_size = xbar_portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_source = xbar_portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_sink = xbar_portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_denied = xbar_portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_data = xbar_portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24]
assign xbar_in_0_d_bits_corrupt = xbar_portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
assign xbar_portsDIO_filtered_0_valid = xbar__portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign xbar_in_0_e_ready = xbar_portsEOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
assign xbar_out_0_e_valid = xbar_portsEOI_filtered_0_valid; // @[Xbar.scala:216:19, :352:24]
assign xbar_out_0_e_bits_sink = xbar_portsEOI_filtered_0_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign xbar_portsEOI_filtered_0_valid = xbar__portsEOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire widget_anonIn_a_ready; // @[MixedNode.scala:551:17]
wire widget_anonIn_a_valid = widget_auto_anon_in_a_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_a_bits_opcode = widget_auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_a_bits_param = widget_auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonIn_a_bits_size = widget_auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9]
wire widget_anonIn_a_bits_source = widget_auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] widget_anonIn_a_bits_address = widget_auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] widget_anonIn_a_bits_mask = widget_auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] widget_anonIn_a_bits_data = widget_auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9]
wire widget_anonIn_b_ready = widget_auto_anon_in_b_ready; // @[WidthWidget.scala:27:9]
wire widget_anonIn_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] widget_anonIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] widget_anonIn_b_bits_size; // @[MixedNode.scala:551:17]
wire widget_anonIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] widget_anonIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [7:0] widget_anonIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [63:0] widget_anonIn_b_bits_data; // @[MixedNode.scala:551:17]
wire widget_anonIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire widget_anonIn_c_ready; // @[MixedNode.scala:551:17]
wire widget_anonIn_c_valid = widget_auto_anon_in_c_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_c_bits_opcode = widget_auto_anon_in_c_bits_opcode; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_c_bits_param = widget_auto_anon_in_c_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonIn_c_bits_size = widget_auto_anon_in_c_bits_size; // @[WidthWidget.scala:27:9]
wire widget_anonIn_c_bits_source = widget_auto_anon_in_c_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] widget_anonIn_c_bits_address = widget_auto_anon_in_c_bits_address; // @[WidthWidget.scala:27:9]
wire [63:0] widget_anonIn_c_bits_data = widget_auto_anon_in_c_bits_data; // @[WidthWidget.scala:27:9]
wire widget_anonIn_d_ready = widget_auto_anon_in_d_ready; // @[WidthWidget.scala:27:9]
wire widget_anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] widget_anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] widget_anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire widget_anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] widget_anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire widget_anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] widget_anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire widget_anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire widget_anonIn_e_ready; // @[MixedNode.scala:551:17]
wire widget_anonIn_e_valid = widget_auto_anon_in_e_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonIn_e_bits_sink = widget_auto_anon_in_e_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_anonOut_a_ready = widget_auto_anon_out_a_ready; // @[WidthWidget.scala:27:9]
wire widget_anonOut_a_valid; // @[MixedNode.scala:542:17]
assign xbar_auto_anon_in_a_valid = widget_auto_anon_out_a_valid; // @[Xbar.scala:74:9]
wire [2:0] widget_anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
assign xbar_auto_anon_in_a_bits_opcode = widget_auto_anon_out_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] widget_anonOut_a_bits_param; // @[MixedNode.scala:542:17]
assign xbar_auto_anon_in_a_bits_param = widget_auto_anon_out_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] widget_anonOut_a_bits_size; // @[MixedNode.scala:542:17]
assign xbar_auto_anon_in_a_bits_size = widget_auto_anon_out_a_bits_size; // @[Xbar.scala:74:9]
wire widget_anonOut_a_bits_source; // @[MixedNode.scala:542:17]
assign xbar_auto_anon_in_a_bits_source = widget_auto_anon_out_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] widget_anonOut_a_bits_address; // @[MixedNode.scala:542:17]
assign xbar_auto_anon_in_a_bits_address = widget_auto_anon_out_a_bits_address; // @[Xbar.scala:74:9]
wire [7:0] widget_anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
assign xbar_auto_anon_in_a_bits_mask = widget_auto_anon_out_a_bits_mask; // @[Xbar.scala:74:9]
wire [63:0] widget_anonOut_a_bits_data; // @[MixedNode.scala:542:17]
assign xbar_auto_anon_in_a_bits_data = widget_auto_anon_out_a_bits_data; // @[Xbar.scala:74:9]
wire widget_anonOut_b_ready; // @[MixedNode.scala:542:17]
assign xbar_auto_anon_in_b_ready = widget_auto_anon_out_b_ready; // @[Xbar.scala:74:9]
wire widget_anonOut_b_valid = widget_auto_anon_out_b_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonOut_b_bits_opcode = widget_auto_anon_out_b_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] widget_anonOut_b_bits_param = widget_auto_anon_out_b_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonOut_b_bits_size = widget_auto_anon_out_b_bits_size; // @[WidthWidget.scala:27:9]
wire widget_anonOut_b_bits_source = widget_auto_anon_out_b_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] widget_anonOut_b_bits_address = widget_auto_anon_out_b_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] widget_anonOut_b_bits_mask = widget_auto_anon_out_b_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] widget_anonOut_b_bits_data = widget_auto_anon_out_b_bits_data; // @[WidthWidget.scala:27:9]
wire widget_anonOut_b_bits_corrupt = widget_auto_anon_out_b_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_anonOut_c_ready = widget_auto_anon_out_c_ready; // @[WidthWidget.scala:27:9]
wire widget_anonOut_c_valid; // @[MixedNode.scala:542:17]
assign xbar_auto_anon_in_c_valid = widget_auto_anon_out_c_valid; // @[Xbar.scala:74:9]
wire [2:0] widget_anonOut_c_bits_opcode; // @[MixedNode.scala:542:17]
assign xbar_auto_anon_in_c_bits_opcode = widget_auto_anon_out_c_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] widget_anonOut_c_bits_param; // @[MixedNode.scala:542:17]
assign xbar_auto_anon_in_c_bits_param = widget_auto_anon_out_c_bits_param; // @[Xbar.scala:74:9]
wire [3:0] widget_anonOut_c_bits_size; // @[MixedNode.scala:542:17]
assign xbar_auto_anon_in_c_bits_size = widget_auto_anon_out_c_bits_size; // @[Xbar.scala:74:9]
wire widget_anonOut_c_bits_source; // @[MixedNode.scala:542:17]
assign xbar_auto_anon_in_c_bits_source = widget_auto_anon_out_c_bits_source; // @[Xbar.scala:74:9]
wire [31:0] widget_anonOut_c_bits_address; // @[MixedNode.scala:542:17]
assign xbar_auto_anon_in_c_bits_address = widget_auto_anon_out_c_bits_address; // @[Xbar.scala:74:9]
wire [63:0] widget_anonOut_c_bits_data; // @[MixedNode.scala:542:17]
assign xbar_auto_anon_in_c_bits_data = widget_auto_anon_out_c_bits_data; // @[Xbar.scala:74:9]
wire widget_anonOut_d_ready; // @[MixedNode.scala:542:17]
assign xbar_auto_anon_in_d_ready = widget_auto_anon_out_d_ready; // @[Xbar.scala:74:9]
wire widget_anonOut_d_valid = widget_auto_anon_out_d_valid; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonOut_d_bits_opcode = widget_auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] widget_anonOut_d_bits_param = widget_auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_anonOut_d_bits_size = widget_auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9]
wire widget_anonOut_d_bits_source = widget_auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] widget_anonOut_d_bits_sink = widget_auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_anonOut_d_bits_denied = widget_auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] widget_anonOut_d_bits_data = widget_auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_anonOut_d_bits_corrupt = widget_auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_anonOut_e_ready = widget_auto_anon_out_e_ready; // @[WidthWidget.scala:27:9]
wire widget_anonOut_e_valid; // @[MixedNode.scala:542:17]
assign xbar_auto_anon_in_e_valid = widget_auto_anon_out_e_valid; // @[Xbar.scala:74:9]
wire [2:0] widget_anonOut_e_bits_sink; // @[MixedNode.scala:542:17]
assign xbar_auto_anon_in_e_bits_sink = widget_auto_anon_out_e_bits_sink; // @[Xbar.scala:74:9]
wire widget_auto_anon_in_a_ready; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_b_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] widget_auto_anon_in_b_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_b_bits_size; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_b_bits_source; // @[WidthWidget.scala:27:9]
wire [31:0] widget_auto_anon_in_b_bits_address; // @[WidthWidget.scala:27:9]
wire [7:0] widget_auto_anon_in_b_bits_mask; // @[WidthWidget.scala:27:9]
wire [63:0] widget_auto_anon_in_b_bits_data; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_b_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_b_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_c_ready; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_d_bits_opcode; // @[WidthWidget.scala:27:9]
wire [1:0] widget_auto_anon_in_d_bits_param; // @[WidthWidget.scala:27:9]
wire [3:0] widget_auto_anon_in_d_bits_size; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_bits_source; // @[WidthWidget.scala:27:9]
wire [2:0] widget_auto_anon_in_d_bits_sink; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_bits_denied; // @[WidthWidget.scala:27:9]
wire [63:0] widget_auto_anon_in_d_bits_data; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_bits_corrupt; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_d_valid; // @[WidthWidget.scala:27:9]
wire widget_auto_anon_in_e_ready; // @[WidthWidget.scala:27:9]
assign widget_anonIn_a_ready = widget_anonOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_out_a_valid = widget_anonOut_a_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_opcode = widget_anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_param = widget_anonOut_a_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_size = widget_anonOut_a_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_source = widget_anonOut_a_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_address = widget_anonOut_a_bits_address; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_mask = widget_anonOut_a_bits_mask; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_a_bits_data = widget_anonOut_a_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_b_ready = widget_anonOut_b_ready; // @[WidthWidget.scala:27:9]
assign widget_anonIn_b_valid = widget_anonOut_b_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_opcode = widget_anonOut_b_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_param = widget_anonOut_b_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_size = widget_anonOut_b_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_source = widget_anonOut_b_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_address = widget_anonOut_b_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_mask = widget_anonOut_b_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_data = widget_anonOut_b_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_b_bits_corrupt = widget_anonOut_b_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_c_ready = widget_anonOut_c_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_out_c_valid = widget_anonOut_c_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_opcode = widget_anonOut_c_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_param = widget_anonOut_c_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_size = widget_anonOut_c_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_source = widget_anonOut_c_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_address = widget_anonOut_c_bits_address; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_c_bits_data = widget_anonOut_c_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_d_ready = widget_anonOut_d_ready; // @[WidthWidget.scala:27:9]
assign widget_anonIn_d_valid = widget_anonOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_opcode = widget_anonOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_param = widget_anonOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_size = widget_anonOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_source = widget_anonOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_sink = widget_anonOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_denied = widget_anonOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_data = widget_anonOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_d_bits_corrupt = widget_anonOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonIn_e_ready = widget_anonOut_e_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_out_e_valid = widget_anonOut_e_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_out_e_bits_sink = widget_anonOut_e_bits_sink; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_a_ready = widget_anonIn_a_ready; // @[WidthWidget.scala:27:9]
assign widget_anonOut_a_valid = widget_anonIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_opcode = widget_anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_param = widget_anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_size = widget_anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_source = widget_anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_address = widget_anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_mask = widget_anonIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_a_bits_data = widget_anonIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_b_ready = widget_anonIn_b_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_in_b_valid = widget_anonIn_b_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_opcode = widget_anonIn_b_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_param = widget_anonIn_b_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_size = widget_anonIn_b_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_source = widget_anonIn_b_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_address = widget_anonIn_b_bits_address; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_mask = widget_anonIn_b_bits_mask; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_data = widget_anonIn_b_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_b_bits_corrupt = widget_anonIn_b_bits_corrupt; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_c_ready = widget_anonIn_c_ready; // @[WidthWidget.scala:27:9]
assign widget_anonOut_c_valid = widget_anonIn_c_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_opcode = widget_anonIn_c_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_param = widget_anonIn_c_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_size = widget_anonIn_c_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_source = widget_anonIn_c_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_address = widget_anonIn_c_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_c_bits_data = widget_anonIn_c_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_d_ready = widget_anonIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
assign widget_auto_anon_in_d_valid = widget_anonIn_d_valid; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_opcode = widget_anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_param = widget_anonIn_d_bits_param; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_size = widget_anonIn_d_bits_size; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_source = widget_anonIn_d_bits_source; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_sink = widget_anonIn_d_bits_sink; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_denied = widget_anonIn_d_bits_denied; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_data = widget_anonIn_d_bits_data; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_d_bits_corrupt = widget_anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9]
assign widget_auto_anon_in_e_ready = widget_anonIn_e_ready; // @[WidthWidget.scala:27:9]
assign widget_anonOut_e_valid = widget_anonIn_e_valid; // @[MixedNode.scala:542:17, :551:17]
assign widget_anonOut_e_bits_sink = widget_anonIn_e_bits_sink; // @[MixedNode.scala:542:17, :551:17]
assign reRoCCNodeIn_req_ready = reRoCCNodeOut_req_ready; // @[MixedNode.scala:542:17, :551:17]
assign reRoCCNodeIn_resp_valid = reRoCCNodeOut_resp_valid; // @[MixedNode.scala:542:17, :551:17]
assign reRoCCNodeIn_resp_bits_opcode = reRoCCNodeOut_resp_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign reRoCCNodeIn_resp_bits_client_id = reRoCCNodeOut_resp_bits_client_id; // @[MixedNode.scala:542:17, :551:17]
assign reRoCCNodeIn_resp_bits_manager_id = reRoCCNodeOut_resp_bits_manager_id; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] reRoCCNodeOut_req_bits_opcode; // @[MixedNode.scala:542:17]
wire [3:0] reRoCCNodeOut_req_bits_client_id; // @[MixedNode.scala:542:17]
wire reRoCCNodeOut_req_bits_manager_id; // @[MixedNode.scala:542:17]
wire [63:0] reRoCCNodeOut_req_bits_data; // @[MixedNode.scala:542:17]
assign reRoCCNodeIn_resp_bits_data = reRoCCNodeOut_resp_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire reRoCCNodeOut_req_valid; // @[MixedNode.scala:542:17]
wire reRoCCNodeOut_resp_ready; // @[MixedNode.scala:542:17]
assign auto_re_ro_cc_in_req_ready_0 = reRoCCNodeIn_req_ready; // @[Manager.scala:237:34]
assign reRoCCNodeOut_req_valid = reRoCCNodeIn_req_valid; // @[MixedNode.scala:542:17, :551:17]
assign reRoCCNodeOut_req_bits_opcode = reRoCCNodeIn_req_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign reRoCCNodeOut_req_bits_client_id = reRoCCNodeIn_req_bits_client_id; // @[MixedNode.scala:542:17, :551:17]
assign reRoCCNodeOut_req_bits_manager_id = reRoCCNodeIn_req_bits_manager_id; // @[MixedNode.scala:542:17, :551:17]
assign reRoCCNodeOut_req_bits_data = reRoCCNodeIn_req_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign reRoCCNodeOut_resp_ready = reRoCCNodeIn_resp_ready; // @[MixedNode.scala:542:17, :551:17]
assign auto_re_ro_cc_in_resp_valid_0 = reRoCCNodeIn_resp_valid; // @[Manager.scala:237:34]
assign auto_re_ro_cc_in_resp_bits_opcode_0 = reRoCCNodeIn_resp_bits_opcode; // @[Manager.scala:237:34]
assign auto_re_ro_cc_in_resp_bits_client_id_0 = reRoCCNodeIn_resp_bits_client_id; // @[Manager.scala:237:34]
assign auto_re_ro_cc_in_resp_bits_manager_id_0 = reRoCCNodeIn_resp_bits_manager_id; // @[Manager.scala:237:34]
assign auto_re_ro_cc_in_resp_bits_data_0 = reRoCCNodeIn_resp_bits_data; // @[Manager.scala:237:34]
wire accumulator__T_3 = accumulator_io_mem_req_ready & accumulator_io_mem_req_valid; // @[Decoupled.scala:51:35]
always @(posedge clock) begin // @[Manager.scala:237:34]
if (reset) begin // @[Manager.scala:237:34]
accumulator_busy_0 <= 1'h0; // @[LazyRoCC.scala:125:21]
accumulator_busy_1 <= 1'h0; // @[LazyRoCC.scala:125:21]
accumulator_busy_2 <= 1'h0; // @[LazyRoCC.scala:125:21]
accumulator_busy_3 <= 1'h0; // @[LazyRoCC.scala:125:21]
end
else begin // @[Manager.scala:237:34]
accumulator_busy_0 <= accumulator__T_3 & accumulator_addr == 2'h0 | ~(accumulator_io_mem_resp_valid & accumulator_memRespTag == 2'h0) & accumulator_busy_0; // @[Decoupled.scala:51:35]
accumulator_busy_1 <= accumulator__T_3 & accumulator_addr == 2'h1 | ~(accumulator_io_mem_resp_valid & accumulator_memRespTag == 2'h1) & accumulator_busy_1; // @[Decoupled.scala:51:35]
accumulator_busy_2 <= accumulator__T_3 & accumulator_addr == 2'h2 | ~(accumulator_io_mem_resp_valid & accumulator_memRespTag == 2'h2) & accumulator_busy_2; // @[Decoupled.scala:51:35]
accumulator_busy_3 <= accumulator__T_3 & (&accumulator_addr) | ~(accumulator_io_mem_resp_valid & (&accumulator_memRespTag)) & accumulator_busy_3; // @[Decoupled.scala:51:35]
end
always @(posedge)
regfile_4x64 regfile_ext ( // @[LazyRoCC.scala:124:20]
.R0_addr (accumulator_addr), // @[LazyRoCC.scala:129:26]
.R0_en (1'h1), // @[Manager.scala:237:34]
.R0_clk (clock),
.R0_data (_regfile_ext_R0_data),
.W0_addr (accumulator_memRespTag), // @[LazyRoCC.scala:134:40]
.W0_en (accumulator_io_mem_resp_valid), // @[LazyRoCC.scala:122:7]
.W0_clk (clock),
.W0_data (accumulator_io_mem_resp_bits_data), // @[LazyRoCC.scala:122:7]
.W1_addr (accumulator_addr), // @[LazyRoCC.scala:129:26]
.W1_en (accumulator__q_io_deq_ready_T_4 & _accumulator_cmd_q_io_deq_valid & (accumulator_doWrite | accumulator_doAccum)), // @[Decoupled.scala:51:35, :362:21]
.W1_clk (clock),
.W1_data (accumulator_wdata) // @[LazyRoCC.scala:139:18]
); // @[LazyRoCC.scala:124:20]
assign accumulator_io_resp_bits_data = _regfile_ext_R0_data; // @[LazyRoCC.scala:122:7, :124:20]
Queue2_RoCCCommand_2 accumulator_cmd_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (accumulator_io_cmd_ready),
.io_enq_valid (accumulator_io_cmd_valid), // @[LazyRoCC.scala:122:7]
.io_enq_bits_inst_funct (accumulator_io_cmd_bits_inst_funct), // @[LazyRoCC.scala:122:7]
.io_enq_bits_inst_rs2 (accumulator_io_cmd_bits_inst_rs2), // @[LazyRoCC.scala:122:7]
.io_enq_bits_inst_rs1 (accumulator_io_cmd_bits_inst_rs1), // @[LazyRoCC.scala:122:7]
.io_enq_bits_inst_xd (accumulator_io_cmd_bits_inst_xd), // @[LazyRoCC.scala:122:7]
.io_enq_bits_inst_xs1 (accumulator_io_cmd_bits_inst_xs1), // @[LazyRoCC.scala:122:7]
.io_enq_bits_inst_xs2 (accumulator_io_cmd_bits_inst_xs2), // @[LazyRoCC.scala:122:7]
.io_enq_bits_inst_rd (accumulator_io_cmd_bits_inst_rd), // @[LazyRoCC.scala:122:7]
.io_enq_bits_inst_opcode (accumulator_io_cmd_bits_inst_opcode), // @[LazyRoCC.scala:122:7]
.io_enq_bits_rs1 (accumulator_io_cmd_bits_rs1), // @[LazyRoCC.scala:122:7]
.io_enq_bits_rs2 (accumulator_io_cmd_bits_rs2), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_debug (accumulator_io_cmd_bits_status_debug), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_cease (accumulator_io_cmd_bits_status_cease), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_wfi (accumulator_io_cmd_bits_status_wfi), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_isa (accumulator_io_cmd_bits_status_isa), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_dprv (accumulator_io_cmd_bits_status_dprv), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_dv (accumulator_io_cmd_bits_status_dv), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_prv (accumulator_io_cmd_bits_status_prv), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_v (accumulator_io_cmd_bits_status_v), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_sd (accumulator_io_cmd_bits_status_sd), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_zero2 (accumulator_io_cmd_bits_status_zero2), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_mpv (accumulator_io_cmd_bits_status_mpv), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_gva (accumulator_io_cmd_bits_status_gva), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_mbe (accumulator_io_cmd_bits_status_mbe), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_sbe (accumulator_io_cmd_bits_status_sbe), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_sxl (accumulator_io_cmd_bits_status_sxl), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_uxl (accumulator_io_cmd_bits_status_uxl), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_sd_rv32 (accumulator_io_cmd_bits_status_sd_rv32), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_zero1 (accumulator_io_cmd_bits_status_zero1), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_tsr (accumulator_io_cmd_bits_status_tsr), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_tw (accumulator_io_cmd_bits_status_tw), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_tvm (accumulator_io_cmd_bits_status_tvm), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_mxr (accumulator_io_cmd_bits_status_mxr), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_sum (accumulator_io_cmd_bits_status_sum), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_mprv (accumulator_io_cmd_bits_status_mprv), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_xs (accumulator_io_cmd_bits_status_xs), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_fs (accumulator_io_cmd_bits_status_fs), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_mpp (accumulator_io_cmd_bits_status_mpp), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_vs (accumulator_io_cmd_bits_status_vs), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_spp (accumulator_io_cmd_bits_status_spp), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_mpie (accumulator_io_cmd_bits_status_mpie), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_ube (accumulator_io_cmd_bits_status_ube), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_spie (accumulator_io_cmd_bits_status_spie), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_upie (accumulator_io_cmd_bits_status_upie), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_mie (accumulator_io_cmd_bits_status_mie), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_hie (accumulator_io_cmd_bits_status_hie), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_sie (accumulator_io_cmd_bits_status_sie), // @[LazyRoCC.scala:122:7]
.io_enq_bits_status_uie (accumulator_io_cmd_bits_status_uie), // @[LazyRoCC.scala:122:7]
.io_deq_ready (accumulator__q_io_deq_ready_T_4), // @[LazyRoCC.scala:160:40]
.io_deq_valid (_accumulator_cmd_q_io_deq_valid),
.io_deq_bits_inst_funct (_accumulator_cmd_q_io_deq_bits_inst_funct),
.io_deq_bits_inst_xd (_accumulator_cmd_q_io_deq_bits_inst_xd),
.io_deq_bits_inst_rd (accumulator_io_resp_bits_rd),
.io_deq_bits_rs1 (_accumulator_cmd_q_io_deq_bits_rs1),
.io_deq_bits_rs2 (_accumulator_cmd_q_io_deq_bits_rs2),
.io_deq_bits_status_dprv (accumulator_io_mem_req_bits_dprv),
.io_deq_bits_status_dv (accumulator_io_mem_req_bits_dv)
); // @[Decoupled.scala:362:21]
ReRoCCManager_1 rerocc_manager ( // @[Manager.scala:209:34]
.clock (clock),
.reset (reset),
.auto_in_req_ready (_rerocc_manager_auto_in_req_ready),
.auto_in_req_valid (_rerocc_buffer_auto_out_req_valid), // @[Protocol.scala:134:35]
.auto_in_req_bits_opcode (_rerocc_buffer_auto_out_req_bits_opcode), // @[Protocol.scala:134:35]
.auto_in_req_bits_client_id (_rerocc_buffer_auto_out_req_bits_client_id), // @[Protocol.scala:134:35]
.auto_in_req_bits_manager_id (_rerocc_buffer_auto_out_req_bits_manager_id), // @[Protocol.scala:134:35]
.auto_in_req_bits_data (_rerocc_buffer_auto_out_req_bits_data), // @[Protocol.scala:134:35]
.auto_in_resp_ready (_rerocc_buffer_auto_out_resp_ready), // @[Protocol.scala:134:35]
.auto_in_resp_valid (_rerocc_manager_auto_in_resp_valid),
.auto_in_resp_bits_opcode (_rerocc_manager_auto_in_resp_bits_opcode),
.auto_in_resp_bits_client_id (_rerocc_manager_auto_in_resp_bits_client_id),
.auto_in_resp_bits_manager_id (_rerocc_manager_auto_in_resp_bits_manager_id),
.auto_in_resp_bits_data (_rerocc_manager_auto_in_resp_bits_data),
.io_manager_id (reroccManagerIdSinkNodeIn[2:0]), // @[Manager.scala:262:41]
.io_cmd_ready (accumulator_io_cmd_ready), // @[LazyRoCC.scala:122:7]
.io_cmd_valid (accumulator_io_cmd_valid),
.io_cmd_bits_inst_funct (accumulator_io_cmd_bits_inst_funct),
.io_cmd_bits_inst_rs2 (accumulator_io_cmd_bits_inst_rs2),
.io_cmd_bits_inst_rs1 (accumulator_io_cmd_bits_inst_rs1),
.io_cmd_bits_inst_xd (accumulator_io_cmd_bits_inst_xd),
.io_cmd_bits_inst_xs1 (accumulator_io_cmd_bits_inst_xs1),
.io_cmd_bits_inst_xs2 (accumulator_io_cmd_bits_inst_xs2),
.io_cmd_bits_inst_rd (accumulator_io_cmd_bits_inst_rd),
.io_cmd_bits_inst_opcode (accumulator_io_cmd_bits_inst_opcode),
.io_cmd_bits_rs1 (accumulator_io_cmd_bits_rs1),
.io_cmd_bits_rs2 (accumulator_io_cmd_bits_rs2),
.io_cmd_bits_status_debug (accumulator_io_cmd_bits_status_debug),
.io_cmd_bits_status_cease (accumulator_io_cmd_bits_status_cease),
.io_cmd_bits_status_wfi (accumulator_io_cmd_bits_status_wfi),
.io_cmd_bits_status_isa (accumulator_io_cmd_bits_status_isa),
.io_cmd_bits_status_dprv (accumulator_io_cmd_bits_status_dprv),
.io_cmd_bits_status_dv (accumulator_io_cmd_bits_status_dv),
.io_cmd_bits_status_prv (accumulator_io_cmd_bits_status_prv),
.io_cmd_bits_status_v (accumulator_io_cmd_bits_status_v),
.io_cmd_bits_status_sd (accumulator_io_cmd_bits_status_sd),
.io_cmd_bits_status_zero2 (accumulator_io_cmd_bits_status_zero2),
.io_cmd_bits_status_mpv (accumulator_io_cmd_bits_status_mpv),
.io_cmd_bits_status_gva (accumulator_io_cmd_bits_status_gva),
.io_cmd_bits_status_mbe (accumulator_io_cmd_bits_status_mbe),
.io_cmd_bits_status_sbe (accumulator_io_cmd_bits_status_sbe),
.io_cmd_bits_status_sxl (accumulator_io_cmd_bits_status_sxl),
.io_cmd_bits_status_uxl (accumulator_io_cmd_bits_status_uxl),
.io_cmd_bits_status_sd_rv32 (accumulator_io_cmd_bits_status_sd_rv32),
.io_cmd_bits_status_zero1 (accumulator_io_cmd_bits_status_zero1),
.io_cmd_bits_status_tsr (accumulator_io_cmd_bits_status_tsr),
.io_cmd_bits_status_tw (accumulator_io_cmd_bits_status_tw),
.io_cmd_bits_status_tvm (accumulator_io_cmd_bits_status_tvm),
.io_cmd_bits_status_mxr (accumulator_io_cmd_bits_status_mxr),
.io_cmd_bits_status_sum (accumulator_io_cmd_bits_status_sum),
.io_cmd_bits_status_mprv (accumulator_io_cmd_bits_status_mprv),
.io_cmd_bits_status_xs (accumulator_io_cmd_bits_status_xs),
.io_cmd_bits_status_fs (accumulator_io_cmd_bits_status_fs),
.io_cmd_bits_status_mpp (accumulator_io_cmd_bits_status_mpp),
.io_cmd_bits_status_vs (accumulator_io_cmd_bits_status_vs),
.io_cmd_bits_status_spp (accumulator_io_cmd_bits_status_spp),
.io_cmd_bits_status_mpie (accumulator_io_cmd_bits_status_mpie),
.io_cmd_bits_status_ube (accumulator_io_cmd_bits_status_ube),
.io_cmd_bits_status_spie (accumulator_io_cmd_bits_status_spie),
.io_cmd_bits_status_upie (accumulator_io_cmd_bits_status_upie),
.io_cmd_bits_status_mie (accumulator_io_cmd_bits_status_mie),
.io_cmd_bits_status_hie (accumulator_io_cmd_bits_status_hie),
.io_cmd_bits_status_sie (accumulator_io_cmd_bits_status_sie),
.io_cmd_bits_status_uie (accumulator_io_cmd_bits_status_uie),
.io_resp_ready (accumulator_io_resp_ready),
.io_resp_valid (accumulator_io_resp_valid), // @[LazyRoCC.scala:122:7]
.io_resp_bits_rd (accumulator_io_resp_bits_rd), // @[LazyRoCC.scala:122:7]
.io_resp_bits_data (accumulator_io_resp_bits_data), // @[LazyRoCC.scala:122:7]
.io_busy (accumulator_io_busy), // @[LazyRoCC.scala:122:7]
.io_ptw_ptbr_mode (_rerocc_manager_io_ptw_ptbr_mode),
.io_ptw_ptbr_asid (_rerocc_manager_io_ptw_ptbr_asid),
.io_ptw_ptbr_ppn (_rerocc_manager_io_ptw_ptbr_ppn),
.io_ptw_sfence_valid (_rerocc_manager_io_ptw_sfence_valid),
.io_ptw_status_debug (_rerocc_manager_io_ptw_status_debug),
.io_ptw_status_cease (_rerocc_manager_io_ptw_status_cease),
.io_ptw_status_wfi (_rerocc_manager_io_ptw_status_wfi),
.io_ptw_status_isa (_rerocc_manager_io_ptw_status_isa),
.io_ptw_status_dprv (_rerocc_manager_io_ptw_status_dprv),
.io_ptw_status_dv (_rerocc_manager_io_ptw_status_dv),
.io_ptw_status_prv (_rerocc_manager_io_ptw_status_prv),
.io_ptw_status_v (_rerocc_manager_io_ptw_status_v),
.io_ptw_status_sd (_rerocc_manager_io_ptw_status_sd),
.io_ptw_status_zero2 (_rerocc_manager_io_ptw_status_zero2),
.io_ptw_status_mpv (_rerocc_manager_io_ptw_status_mpv),
.io_ptw_status_gva (_rerocc_manager_io_ptw_status_gva),
.io_ptw_status_mbe (_rerocc_manager_io_ptw_status_mbe),
.io_ptw_status_sbe (_rerocc_manager_io_ptw_status_sbe),
.io_ptw_status_sxl (_rerocc_manager_io_ptw_status_sxl),
.io_ptw_status_uxl (_rerocc_manager_io_ptw_status_uxl),
.io_ptw_status_sd_rv32 (_rerocc_manager_io_ptw_status_sd_rv32),
.io_ptw_status_zero1 (_rerocc_manager_io_ptw_status_zero1),
.io_ptw_status_tsr (_rerocc_manager_io_ptw_status_tsr),
.io_ptw_status_tw (_rerocc_manager_io_ptw_status_tw),
.io_ptw_status_tvm (_rerocc_manager_io_ptw_status_tvm),
.io_ptw_status_mxr (_rerocc_manager_io_ptw_status_mxr),
.io_ptw_status_sum (_rerocc_manager_io_ptw_status_sum),
.io_ptw_status_mprv (_rerocc_manager_io_ptw_status_mprv),
.io_ptw_status_xs (_rerocc_manager_io_ptw_status_xs),
.io_ptw_status_fs (_rerocc_manager_io_ptw_status_fs),
.io_ptw_status_mpp (_rerocc_manager_io_ptw_status_mpp),
.io_ptw_status_vs (_rerocc_manager_io_ptw_status_vs),
.io_ptw_status_spp (_rerocc_manager_io_ptw_status_spp),
.io_ptw_status_mpie (_rerocc_manager_io_ptw_status_mpie),
.io_ptw_status_ube (_rerocc_manager_io_ptw_status_ube),
.io_ptw_status_spie (_rerocc_manager_io_ptw_status_spie),
.io_ptw_status_upie (_rerocc_manager_io_ptw_status_upie),
.io_ptw_status_mie (_rerocc_manager_io_ptw_status_mie),
.io_ptw_status_hie (_rerocc_manager_io_ptw_status_hie),
.io_ptw_status_sie (_rerocc_manager_io_ptw_status_sie),
.io_ptw_status_uie (_rerocc_manager_io_ptw_status_uie),
.io_ptw_perf_pte_miss (_ptw_io_dpath_perf_pte_miss), // @[Manager.scala:243:21]
.io_ptw_clock_enabled (_ptw_io_dpath_clock_enabled) // @[Manager.scala:243:21]
); // @[Manager.scala:209:34]
ReRoCCBuffer_2 rerocc_buffer ( // @[Protocol.scala:134:35]
.clock (clock),
.reset (reset),
.auto_in_req_ready (reRoCCNodeOut_req_ready),
.auto_in_req_valid (reRoCCNodeOut_req_valid), // @[MixedNode.scala:542:17]
.auto_in_req_bits_opcode (reRoCCNodeOut_req_bits_opcode), // @[MixedNode.scala:542:17]
.auto_in_req_bits_client_id (reRoCCNodeOut_req_bits_client_id), // @[MixedNode.scala:542:17]
.auto_in_req_bits_manager_id (reRoCCNodeOut_req_bits_manager_id), // @[MixedNode.scala:542:17]
.auto_in_req_bits_data (reRoCCNodeOut_req_bits_data), // @[MixedNode.scala:542:17]
.auto_in_resp_ready (reRoCCNodeOut_resp_ready), // @[MixedNode.scala:542:17]
.auto_in_resp_valid (reRoCCNodeOut_resp_valid),
.auto_in_resp_bits_opcode (reRoCCNodeOut_resp_bits_opcode),
.auto_in_resp_bits_client_id (reRoCCNodeOut_resp_bits_client_id),
.auto_in_resp_bits_manager_id (reRoCCNodeOut_resp_bits_manager_id),
.auto_in_resp_bits_data (reRoCCNodeOut_resp_bits_data),
.auto_out_req_ready (_rerocc_manager_auto_in_req_ready), // @[Manager.scala:209:34]
.auto_out_req_valid (_rerocc_buffer_auto_out_req_valid),
.auto_out_req_bits_opcode (_rerocc_buffer_auto_out_req_bits_opcode),
.auto_out_req_bits_client_id (_rerocc_buffer_auto_out_req_bits_client_id),
.auto_out_req_bits_manager_id (_rerocc_buffer_auto_out_req_bits_manager_id),
.auto_out_req_bits_data (_rerocc_buffer_auto_out_req_bits_data),
.auto_out_resp_ready (_rerocc_buffer_auto_out_resp_ready),
.auto_out_resp_valid (_rerocc_manager_auto_in_resp_valid), // @[Manager.scala:209:34]
.auto_out_resp_bits_opcode (_rerocc_manager_auto_in_resp_bits_opcode), // @[Manager.scala:209:34]
.auto_out_resp_bits_client_id (_rerocc_manager_auto_in_resp_bits_client_id), // @[Manager.scala:209:34]
.auto_out_resp_bits_manager_id (_rerocc_manager_auto_in_resp_bits_manager_id), // @[Manager.scala:209:34]
.auto_out_resp_bits_data (_rerocc_manager_auto_in_resp_bits_data) // @[Manager.scala:209:34]
); // @[Protocol.scala:134:35]
TLBuffer_a32d64s1k3z4c_5 buffer ( // @[Buffer.scala:75:28]
.clock (clock),
.reset (reset),
.auto_in_a_ready (xbar_auto_anon_out_a_ready),
.auto_in_a_valid (xbar_auto_anon_out_a_valid), // @[Xbar.scala:74:9]
.auto_in_a_bits_opcode (xbar_auto_anon_out_a_bits_opcode), // @[Xbar.scala:74:9]
.auto_in_a_bits_param (xbar_auto_anon_out_a_bits_param), // @[Xbar.scala:74:9]
.auto_in_a_bits_size (xbar_auto_anon_out_a_bits_size), // @[Xbar.scala:74:9]
.auto_in_a_bits_source (xbar_auto_anon_out_a_bits_source), // @[Xbar.scala:74:9]
.auto_in_a_bits_address (xbar_auto_anon_out_a_bits_address), // @[Xbar.scala:74:9]
.auto_in_a_bits_mask (xbar_auto_anon_out_a_bits_mask), // @[Xbar.scala:74:9]
.auto_in_a_bits_data (xbar_auto_anon_out_a_bits_data), // @[Xbar.scala:74:9]
.auto_in_b_ready (xbar_auto_anon_out_b_ready), // @[Xbar.scala:74:9]
.auto_in_b_valid (xbar_auto_anon_out_b_valid),
.auto_in_b_bits_opcode (xbar_auto_anon_out_b_bits_opcode),
.auto_in_b_bits_param (xbar_auto_anon_out_b_bits_param),
.auto_in_b_bits_size (xbar_auto_anon_out_b_bits_size),
.auto_in_b_bits_source (xbar_auto_anon_out_b_bits_source),
.auto_in_b_bits_address (xbar_auto_anon_out_b_bits_address),
.auto_in_b_bits_mask (xbar_auto_anon_out_b_bits_mask),
.auto_in_b_bits_data (xbar_auto_anon_out_b_bits_data),
.auto_in_b_bits_corrupt (xbar_auto_anon_out_b_bits_corrupt),
.auto_in_c_ready (xbar_auto_anon_out_c_ready),
.auto_in_c_valid (xbar_auto_anon_out_c_valid), // @[Xbar.scala:74:9]
.auto_in_c_bits_opcode (xbar_auto_anon_out_c_bits_opcode), // @[Xbar.scala:74:9]
.auto_in_c_bits_param (xbar_auto_anon_out_c_bits_param), // @[Xbar.scala:74:9]
.auto_in_c_bits_size (xbar_auto_anon_out_c_bits_size), // @[Xbar.scala:74:9]
.auto_in_c_bits_source (xbar_auto_anon_out_c_bits_source), // @[Xbar.scala:74:9]
.auto_in_c_bits_address (xbar_auto_anon_out_c_bits_address), // @[Xbar.scala:74:9]
.auto_in_c_bits_data (xbar_auto_anon_out_c_bits_data), // @[Xbar.scala:74:9]
.auto_in_d_ready (xbar_auto_anon_out_d_ready), // @[Xbar.scala:74:9]
.auto_in_d_valid (xbar_auto_anon_out_d_valid),
.auto_in_d_bits_opcode (xbar_auto_anon_out_d_bits_opcode),
.auto_in_d_bits_param (xbar_auto_anon_out_d_bits_param),
.auto_in_d_bits_size (xbar_auto_anon_out_d_bits_size),
.auto_in_d_bits_source (xbar_auto_anon_out_d_bits_source),
.auto_in_d_bits_sink (xbar_auto_anon_out_d_bits_sink),
.auto_in_d_bits_denied (xbar_auto_anon_out_d_bits_denied),
.auto_in_d_bits_data (xbar_auto_anon_out_d_bits_data),
.auto_in_d_bits_corrupt (xbar_auto_anon_out_d_bits_corrupt),
.auto_in_e_ready (xbar_auto_anon_out_e_ready),
.auto_in_e_valid (xbar_auto_anon_out_e_valid), // @[Xbar.scala:74:9]
.auto_in_e_bits_sink (xbar_auto_anon_out_e_bits_sink), // @[Xbar.scala:74:9]
.auto_out_a_ready (auto_buffer_out_a_ready_0), // @[Manager.scala:237:34]
.auto_out_a_valid (auto_buffer_out_a_valid_0),
.auto_out_a_bits_opcode (auto_buffer_out_a_bits_opcode_0),
.auto_out_a_bits_param (auto_buffer_out_a_bits_param_0),
.auto_out_a_bits_size (auto_buffer_out_a_bits_size_0),
.auto_out_a_bits_source (auto_buffer_out_a_bits_source_0),
.auto_out_a_bits_address (auto_buffer_out_a_bits_address_0),
.auto_out_a_bits_mask (auto_buffer_out_a_bits_mask_0),
.auto_out_a_bits_data (auto_buffer_out_a_bits_data_0),
.auto_out_a_bits_corrupt (auto_buffer_out_a_bits_corrupt_0),
.auto_out_b_ready (auto_buffer_out_b_ready_0),
.auto_out_b_valid (auto_buffer_out_b_valid_0), // @[Manager.scala:237:34]
.auto_out_b_bits_opcode (auto_buffer_out_b_bits_opcode_0), // @[Manager.scala:237:34]
.auto_out_b_bits_param (auto_buffer_out_b_bits_param_0), // @[Manager.scala:237:34]
.auto_out_b_bits_size (auto_buffer_out_b_bits_size_0), // @[Manager.scala:237:34]
.auto_out_b_bits_source (auto_buffer_out_b_bits_source_0), // @[Manager.scala:237:34]
.auto_out_b_bits_address (auto_buffer_out_b_bits_address_0), // @[Manager.scala:237:34]
.auto_out_b_bits_mask (auto_buffer_out_b_bits_mask_0), // @[Manager.scala:237:34]
.auto_out_b_bits_data (auto_buffer_out_b_bits_data_0), // @[Manager.scala:237:34]
.auto_out_b_bits_corrupt (auto_buffer_out_b_bits_corrupt_0), // @[Manager.scala:237:34]
.auto_out_c_ready (auto_buffer_out_c_ready_0), // @[Manager.scala:237:34]
.auto_out_c_valid (auto_buffer_out_c_valid_0),
.auto_out_c_bits_opcode (auto_buffer_out_c_bits_opcode_0),
.auto_out_c_bits_param (auto_buffer_out_c_bits_param_0),
.auto_out_c_bits_size (auto_buffer_out_c_bits_size_0),
.auto_out_c_bits_source (auto_buffer_out_c_bits_source_0),
.auto_out_c_bits_address (auto_buffer_out_c_bits_address_0),
.auto_out_c_bits_data (auto_buffer_out_c_bits_data_0),
.auto_out_c_bits_corrupt (auto_buffer_out_c_bits_corrupt_0),
.auto_out_d_ready (auto_buffer_out_d_ready_0),
.auto_out_d_valid (auto_buffer_out_d_valid_0), // @[Manager.scala:237:34]
.auto_out_d_bits_opcode (auto_buffer_out_d_bits_opcode_0), // @[Manager.scala:237:34]
.auto_out_d_bits_param (auto_buffer_out_d_bits_param_0), // @[Manager.scala:237:34]
.auto_out_d_bits_size (auto_buffer_out_d_bits_size_0), // @[Manager.scala:237:34]
.auto_out_d_bits_source (auto_buffer_out_d_bits_source_0), // @[Manager.scala:237:34]
.auto_out_d_bits_sink (auto_buffer_out_d_bits_sink_0), // @[Manager.scala:237:34]
.auto_out_d_bits_denied (auto_buffer_out_d_bits_denied_0), // @[Manager.scala:237:34]
.auto_out_d_bits_data (auto_buffer_out_d_bits_data_0), // @[Manager.scala:237:34]
.auto_out_d_bits_corrupt (auto_buffer_out_d_bits_corrupt_0), // @[Manager.scala:237:34]
.auto_out_e_ready (auto_buffer_out_e_ready_0), // @[Manager.scala:237:34]
.auto_out_e_valid (auto_buffer_out_e_valid_0),
.auto_out_e_bits_sink (auto_buffer_out_e_bits_sink_0)
); // @[Buffer.scala:75:28]
MiniDCache_1 dcache ( // @[Manager.scala:226:61]
.clock (clock),
.reset (reset),
.auto_out_a_ready (widget_auto_anon_in_a_ready), // @[WidthWidget.scala:27:9]
.auto_out_a_valid (widget_auto_anon_in_a_valid),
.auto_out_a_bits_opcode (widget_auto_anon_in_a_bits_opcode),
.auto_out_a_bits_param (widget_auto_anon_in_a_bits_param),
.auto_out_a_bits_size (widget_auto_anon_in_a_bits_size),
.auto_out_a_bits_source (widget_auto_anon_in_a_bits_source),
.auto_out_a_bits_address (widget_auto_anon_in_a_bits_address),
.auto_out_a_bits_mask (widget_auto_anon_in_a_bits_mask),
.auto_out_a_bits_data (widget_auto_anon_in_a_bits_data),
.auto_out_b_ready (widget_auto_anon_in_b_ready),
.auto_out_b_valid (widget_auto_anon_in_b_valid), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_opcode (widget_auto_anon_in_b_bits_opcode), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_param (widget_auto_anon_in_b_bits_param), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_size (widget_auto_anon_in_b_bits_size), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_source (widget_auto_anon_in_b_bits_source), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_address (widget_auto_anon_in_b_bits_address), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_mask (widget_auto_anon_in_b_bits_mask), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_data (widget_auto_anon_in_b_bits_data), // @[WidthWidget.scala:27:9]
.auto_out_b_bits_corrupt (widget_auto_anon_in_b_bits_corrupt), // @[WidthWidget.scala:27:9]
.auto_out_c_ready (widget_auto_anon_in_c_ready), // @[WidthWidget.scala:27:9]
.auto_out_c_valid (widget_auto_anon_in_c_valid),
.auto_out_c_bits_opcode (widget_auto_anon_in_c_bits_opcode),
.auto_out_c_bits_param (widget_auto_anon_in_c_bits_param),
.auto_out_c_bits_size (widget_auto_anon_in_c_bits_size),
.auto_out_c_bits_source (widget_auto_anon_in_c_bits_source),
.auto_out_c_bits_address (widget_auto_anon_in_c_bits_address),
.auto_out_c_bits_data (widget_auto_anon_in_c_bits_data),
.auto_out_d_ready (widget_auto_anon_in_d_ready),
.auto_out_d_valid (widget_auto_anon_in_d_valid), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_opcode (widget_auto_anon_in_d_bits_opcode), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_param (widget_auto_anon_in_d_bits_param), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_size (widget_auto_anon_in_d_bits_size), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_source (widget_auto_anon_in_d_bits_source), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_sink (widget_auto_anon_in_d_bits_sink), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_denied (widget_auto_anon_in_d_bits_denied), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_data (widget_auto_anon_in_d_bits_data), // @[WidthWidget.scala:27:9]
.auto_out_d_bits_corrupt (widget_auto_anon_in_d_bits_corrupt), // @[WidthWidget.scala:27:9]
.auto_out_e_ready (widget_auto_anon_in_e_ready), // @[WidthWidget.scala:27:9]
.auto_out_e_valid (widget_auto_anon_in_e_valid),
.auto_out_e_bits_sink (widget_auto_anon_in_e_bits_sink),
.io_cpu_req_ready (_dcache_io_cpu_req_ready),
.io_cpu_req_valid (_dcacheArb_io_mem_req_valid), // @[Manager.scala:238:27]
.io_cpu_req_bits_addr (_dcacheArb_io_mem_req_bits_addr), // @[Manager.scala:238:27]
.io_cpu_req_bits_tag (_dcacheArb_io_mem_req_bits_tag), // @[Manager.scala:238:27]
.io_cpu_req_bits_dprv (_dcacheArb_io_mem_req_bits_dprv), // @[Manager.scala:238:27]
.io_cpu_req_bits_dv (_dcacheArb_io_mem_req_bits_dv), // @[Manager.scala:238:27]
.io_cpu_req_bits_phys (_dcacheArb_io_mem_req_bits_phys), // @[Manager.scala:238:27]
.io_cpu_s1_kill (_dcacheArb_io_mem_s1_kill), // @[Manager.scala:238:27]
.io_cpu_s1_data_data (_dcacheArb_io_mem_s1_data_data), // @[Manager.scala:238:27]
.io_cpu_s1_data_mask (_dcacheArb_io_mem_s1_data_mask), // @[Manager.scala:238:27]
.io_cpu_s2_nack (_dcache_io_cpu_s2_nack),
.io_cpu_s2_nack_cause_raw (_dcache_io_cpu_s2_nack_cause_raw),
.io_cpu_s2_uncached (_dcache_io_cpu_s2_uncached),
.io_cpu_s2_paddr (_dcache_io_cpu_s2_paddr),
.io_cpu_resp_valid (_dcache_io_cpu_resp_valid),
.io_cpu_resp_bits_addr (_dcache_io_cpu_resp_bits_addr),
.io_cpu_resp_bits_tag (_dcache_io_cpu_resp_bits_tag),
.io_cpu_resp_bits_cmd (_dcache_io_cpu_resp_bits_cmd),
.io_cpu_resp_bits_size (_dcache_io_cpu_resp_bits_size),
.io_cpu_resp_bits_signed (_dcache_io_cpu_resp_bits_signed),
.io_cpu_resp_bits_dprv (_dcache_io_cpu_resp_bits_dprv),
.io_cpu_resp_bits_dv (_dcache_io_cpu_resp_bits_dv),
.io_cpu_resp_bits_data (_dcache_io_cpu_resp_bits_data),
.io_cpu_resp_bits_mask (_dcache_io_cpu_resp_bits_mask),
.io_cpu_resp_bits_replay (_dcache_io_cpu_resp_bits_replay),
.io_cpu_resp_bits_has_data (_dcache_io_cpu_resp_bits_has_data),
.io_cpu_resp_bits_data_word_bypass (_dcache_io_cpu_resp_bits_data_word_bypass),
.io_cpu_resp_bits_data_raw (_dcache_io_cpu_resp_bits_data_raw),
.io_cpu_resp_bits_store_data (_dcache_io_cpu_resp_bits_store_data),
.io_cpu_replay_next (_dcache_io_cpu_replay_next),
.io_cpu_s2_xcpt_ma_ld (_dcache_io_cpu_s2_xcpt_ma_ld),
.io_cpu_s2_xcpt_ma_st (_dcache_io_cpu_s2_xcpt_ma_st),
.io_cpu_s2_xcpt_pf_ld (_dcache_io_cpu_s2_xcpt_pf_ld),
.io_cpu_s2_xcpt_pf_st (_dcache_io_cpu_s2_xcpt_pf_st),
.io_cpu_s2_xcpt_ae_ld (_dcache_io_cpu_s2_xcpt_ae_ld),
.io_cpu_s2_xcpt_ae_st (_dcache_io_cpu_s2_xcpt_ae_st),
.io_cpu_s2_gpa (_dcache_io_cpu_s2_gpa),
.io_cpu_ordered (_dcache_io_cpu_ordered),
.io_cpu_store_pending (_dcache_io_cpu_store_pending),
.io_cpu_perf_acquire (_dcache_io_cpu_perf_acquire),
.io_cpu_perf_release (_dcache_io_cpu_perf_release),
.io_cpu_perf_grant (_dcache_io_cpu_perf_grant),
.io_cpu_perf_tlbMiss (_dcache_io_cpu_perf_tlbMiss),
.io_cpu_perf_blocked (_dcache_io_cpu_perf_blocked),
.io_cpu_perf_canAcceptStoreThenLoad (_dcache_io_cpu_perf_canAcceptStoreThenLoad),
.io_cpu_perf_canAcceptStoreThenRMW (_dcache_io_cpu_perf_canAcceptStoreThenRMW),
.io_cpu_perf_canAcceptLoadThenLoad (_dcache_io_cpu_perf_canAcceptLoadThenLoad),
.io_cpu_perf_storeBufferEmptyAfterLoad (_dcache_io_cpu_perf_storeBufferEmptyAfterLoad),
.io_cpu_perf_storeBufferEmptyAfterStore (_dcache_io_cpu_perf_storeBufferEmptyAfterStore),
.io_ptw_req_ready (_ptw_io_requestor_0_req_ready), // @[Manager.scala:243:21]
.io_ptw_req_valid (_dcache_io_ptw_req_valid),
.io_ptw_req_bits_bits_addr (_dcache_io_ptw_req_bits_bits_addr),
.io_ptw_req_bits_bits_need_gpa (_dcache_io_ptw_req_bits_bits_need_gpa),
.io_ptw_resp_valid (_ptw_io_requestor_0_resp_valid), // @[Manager.scala:243:21]
.io_ptw_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw), // @[Manager.scala:243:21]
.io_ptw_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final), // @[Manager.scala:243:21]
.io_ptw_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf), // @[Manager.scala:243:21]
.io_ptw_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf), // @[Manager.scala:243:21]
.io_ptw_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr), // @[Manager.scala:243:21]
.io_ptw_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw), // @[Manager.scala:243:21]
.io_ptw_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx), // @[Manager.scala:243:21]
.io_ptw_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future), // @[Manager.scala:243:21]
.io_ptw_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn), // @[Manager.scala:243:21]
.io_ptw_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software), // @[Manager.scala:243:21]
.io_ptw_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d), // @[Manager.scala:243:21]
.io_ptw_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a), // @[Manager.scala:243:21]
.io_ptw_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g), // @[Manager.scala:243:21]
.io_ptw_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u), // @[Manager.scala:243:21]
.io_ptw_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x), // @[Manager.scala:243:21]
.io_ptw_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w), // @[Manager.scala:243:21]
.io_ptw_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r), // @[Manager.scala:243:21]
.io_ptw_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v), // @[Manager.scala:243:21]
.io_ptw_resp_bits_level (_ptw_io_requestor_0_resp_bits_level), // @[Manager.scala:243:21]
.io_ptw_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous), // @[Manager.scala:243:21]
.io_ptw_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid), // @[Manager.scala:243:21]
.io_ptw_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits), // @[Manager.scala:243:21]
.io_ptw_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte), // @[Manager.scala:243:21]
.io_ptw_ptbr_mode (_ptw_io_requestor_0_ptbr_mode), // @[Manager.scala:243:21]
.io_ptw_ptbr_asid (_ptw_io_requestor_0_ptbr_asid), // @[Manager.scala:243:21]
.io_ptw_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn), // @[Manager.scala:243:21]
.io_ptw_status_debug (_ptw_io_requestor_0_status_debug), // @[Manager.scala:243:21]
.io_ptw_status_cease (_ptw_io_requestor_0_status_cease), // @[Manager.scala:243:21]
.io_ptw_status_wfi (_ptw_io_requestor_0_status_wfi), // @[Manager.scala:243:21]
.io_ptw_status_isa (_ptw_io_requestor_0_status_isa), // @[Manager.scala:243:21]
.io_ptw_status_dprv (_ptw_io_requestor_0_status_dprv), // @[Manager.scala:243:21]
.io_ptw_status_dv (_ptw_io_requestor_0_status_dv), // @[Manager.scala:243:21]
.io_ptw_status_prv (_ptw_io_requestor_0_status_prv), // @[Manager.scala:243:21]
.io_ptw_status_v (_ptw_io_requestor_0_status_v), // @[Manager.scala:243:21]
.io_ptw_status_sd (_ptw_io_requestor_0_status_sd), // @[Manager.scala:243:21]
.io_ptw_status_zero2 (_ptw_io_requestor_0_status_zero2), // @[Manager.scala:243:21]
.io_ptw_status_mpv (_ptw_io_requestor_0_status_mpv), // @[Manager.scala:243:21]
.io_ptw_status_gva (_ptw_io_requestor_0_status_gva), // @[Manager.scala:243:21]
.io_ptw_status_mbe (_ptw_io_requestor_0_status_mbe), // @[Manager.scala:243:21]
.io_ptw_status_sbe (_ptw_io_requestor_0_status_sbe), // @[Manager.scala:243:21]
.io_ptw_status_sxl (_ptw_io_requestor_0_status_sxl), // @[Manager.scala:243:21]
.io_ptw_status_uxl (_ptw_io_requestor_0_status_uxl), // @[Manager.scala:243:21]
.io_ptw_status_sd_rv32 (_ptw_io_requestor_0_status_sd_rv32), // @[Manager.scala:243:21]
.io_ptw_status_zero1 (_ptw_io_requestor_0_status_zero1), // @[Manager.scala:243:21]
.io_ptw_status_tsr (_ptw_io_requestor_0_status_tsr), // @[Manager.scala:243:21]
.io_ptw_status_tw (_ptw_io_requestor_0_status_tw), // @[Manager.scala:243:21]
.io_ptw_status_tvm (_ptw_io_requestor_0_status_tvm), // @[Manager.scala:243:21]
.io_ptw_status_mxr (_ptw_io_requestor_0_status_mxr), // @[Manager.scala:243:21]
.io_ptw_status_sum (_ptw_io_requestor_0_status_sum), // @[Manager.scala:243:21]
.io_ptw_status_mprv (_ptw_io_requestor_0_status_mprv), // @[Manager.scala:243:21]
.io_ptw_status_xs (_ptw_io_requestor_0_status_xs), // @[Manager.scala:243:21]
.io_ptw_status_fs (_ptw_io_requestor_0_status_fs), // @[Manager.scala:243:21]
.io_ptw_status_mpp (_ptw_io_requestor_0_status_mpp), // @[Manager.scala:243:21]
.io_ptw_status_vs (_ptw_io_requestor_0_status_vs), // @[Manager.scala:243:21]
.io_ptw_status_spp (_ptw_io_requestor_0_status_spp), // @[Manager.scala:243:21]
.io_ptw_status_mpie (_ptw_io_requestor_0_status_mpie), // @[Manager.scala:243:21]
.io_ptw_status_ube (_ptw_io_requestor_0_status_ube), // @[Manager.scala:243:21]
.io_ptw_status_spie (_ptw_io_requestor_0_status_spie), // @[Manager.scala:243:21]
.io_ptw_status_upie (_ptw_io_requestor_0_status_upie), // @[Manager.scala:243:21]
.io_ptw_status_mie (_ptw_io_requestor_0_status_mie), // @[Manager.scala:243:21]
.io_ptw_status_hie (_ptw_io_requestor_0_status_hie), // @[Manager.scala:243:21]
.io_ptw_status_sie (_ptw_io_requestor_0_status_sie), // @[Manager.scala:243:21]
.io_ptw_status_uie (_ptw_io_requestor_0_status_uie) // @[Manager.scala:243:21]
); // @[Manager.scala:226:61]
ReRoCCManagerControl_1 ctrl ( // @[Manager.scala:235:24]
.clock (clock),
.reset (reset),
.auto_ctrl_in_a_ready (auto_ctrl_ctrl_in_a_ready_0),
.auto_ctrl_in_a_valid (auto_ctrl_ctrl_in_a_valid_0), // @[Manager.scala:237:34]
.auto_ctrl_in_a_bits_opcode (auto_ctrl_ctrl_in_a_bits_opcode_0), // @[Manager.scala:237:34]
.auto_ctrl_in_a_bits_param (auto_ctrl_ctrl_in_a_bits_param_0), // @[Manager.scala:237:34]
.auto_ctrl_in_a_bits_size (auto_ctrl_ctrl_in_a_bits_size_0), // @[Manager.scala:237:34]
.auto_ctrl_in_a_bits_source (auto_ctrl_ctrl_in_a_bits_source_0), // @[Manager.scala:237:34]
.auto_ctrl_in_a_bits_address (auto_ctrl_ctrl_in_a_bits_address_0), // @[Manager.scala:237:34]
.auto_ctrl_in_a_bits_mask (auto_ctrl_ctrl_in_a_bits_mask_0), // @[Manager.scala:237:34]
.auto_ctrl_in_a_bits_data (auto_ctrl_ctrl_in_a_bits_data_0), // @[Manager.scala:237:34]
.auto_ctrl_in_a_bits_corrupt (auto_ctrl_ctrl_in_a_bits_corrupt_0), // @[Manager.scala:237:34]
.auto_ctrl_in_d_ready (auto_ctrl_ctrl_in_d_ready_0), // @[Manager.scala:237:34]
.auto_ctrl_in_d_valid (auto_ctrl_ctrl_in_d_valid_0),
.auto_ctrl_in_d_bits_opcode (auto_ctrl_ctrl_in_d_bits_opcode_0),
.auto_ctrl_in_d_bits_size (auto_ctrl_ctrl_in_d_bits_size_0),
.auto_ctrl_in_d_bits_source (auto_ctrl_ctrl_in_d_bits_source_0),
.auto_ctrl_in_d_bits_data (auto_ctrl_ctrl_in_d_bits_data_0),
.io_mgr_busy (accumulator_io_busy), // @[LazyRoCC.scala:122:7]
.io_rocc_busy (accumulator_io_busy) // @[LazyRoCC.scala:122:7]
); // @[Manager.scala:235:24]
HellaCacheArbiter_2 dcacheArb ( // @[Manager.scala:238:27]
.clock (clock),
.reset (reset),
.io_requestor_0_req_ready (_dcacheArb_io_requestor_0_req_ready),
.io_requestor_0_req_valid (_ptw_io_mem_req_valid), // @[Manager.scala:243:21]
.io_requestor_0_req_bits_addr (_ptw_io_mem_req_bits_addr), // @[Manager.scala:243:21]
.io_requestor_0_req_bits_dv (_ptw_io_mem_req_bits_dv), // @[Manager.scala:243:21]
.io_requestor_0_s1_kill (_ptw_io_mem_s1_kill), // @[Manager.scala:243:21]
.io_requestor_0_s2_nack (_dcacheArb_io_requestor_0_s2_nack),
.io_requestor_0_s2_nack_cause_raw (_dcacheArb_io_requestor_0_s2_nack_cause_raw),
.io_requestor_0_s2_uncached (_dcacheArb_io_requestor_0_s2_uncached),
.io_requestor_0_s2_paddr (_dcacheArb_io_requestor_0_s2_paddr),
.io_requestor_0_resp_valid (_dcacheArb_io_requestor_0_resp_valid),
.io_requestor_0_resp_bits_addr (_dcacheArb_io_requestor_0_resp_bits_addr),
.io_requestor_0_resp_bits_tag (_dcacheArb_io_requestor_0_resp_bits_tag),
.io_requestor_0_resp_bits_cmd (_dcacheArb_io_requestor_0_resp_bits_cmd),
.io_requestor_0_resp_bits_size (_dcacheArb_io_requestor_0_resp_bits_size),
.io_requestor_0_resp_bits_signed (_dcacheArb_io_requestor_0_resp_bits_signed),
.io_requestor_0_resp_bits_dprv (_dcacheArb_io_requestor_0_resp_bits_dprv),
.io_requestor_0_resp_bits_dv (_dcacheArb_io_requestor_0_resp_bits_dv),
.io_requestor_0_resp_bits_data (_dcacheArb_io_requestor_0_resp_bits_data),
.io_requestor_0_resp_bits_mask (_dcacheArb_io_requestor_0_resp_bits_mask),
.io_requestor_0_resp_bits_replay (_dcacheArb_io_requestor_0_resp_bits_replay),
.io_requestor_0_resp_bits_has_data (_dcacheArb_io_requestor_0_resp_bits_has_data),
.io_requestor_0_resp_bits_data_word_bypass (_dcacheArb_io_requestor_0_resp_bits_data_word_bypass),
.io_requestor_0_resp_bits_data_raw (_dcacheArb_io_requestor_0_resp_bits_data_raw),
.io_requestor_0_resp_bits_store_data (_dcacheArb_io_requestor_0_resp_bits_store_data),
.io_requestor_0_replay_next (_dcacheArb_io_requestor_0_replay_next),
.io_requestor_0_s2_xcpt_ma_ld (_dcacheArb_io_requestor_0_s2_xcpt_ma_ld),
.io_requestor_0_s2_xcpt_ma_st (_dcacheArb_io_requestor_0_s2_xcpt_ma_st),
.io_requestor_0_s2_xcpt_pf_ld (_dcacheArb_io_requestor_0_s2_xcpt_pf_ld),
.io_requestor_0_s2_xcpt_pf_st (_dcacheArb_io_requestor_0_s2_xcpt_pf_st),
.io_requestor_0_s2_xcpt_ae_ld (_dcacheArb_io_requestor_0_s2_xcpt_ae_ld),
.io_requestor_0_s2_xcpt_ae_st (_dcacheArb_io_requestor_0_s2_xcpt_ae_st),
.io_requestor_0_s2_gpa (_dcacheArb_io_requestor_0_s2_gpa),
.io_requestor_0_ordered (_dcacheArb_io_requestor_0_ordered),
.io_requestor_0_store_pending (_dcacheArb_io_requestor_0_store_pending),
.io_requestor_0_perf_acquire (_dcacheArb_io_requestor_0_perf_acquire),
.io_requestor_0_perf_release (_dcacheArb_io_requestor_0_perf_release),
.io_requestor_0_perf_grant (_dcacheArb_io_requestor_0_perf_grant),
.io_requestor_0_perf_tlbMiss (_dcacheArb_io_requestor_0_perf_tlbMiss),
.io_requestor_0_perf_blocked (_dcacheArb_io_requestor_0_perf_blocked),
.io_requestor_0_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad),
.io_requestor_0_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW),
.io_requestor_0_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad),
.io_requestor_0_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad),
.io_requestor_0_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore),
.io_requestor_1_req_ready (_dcacheArb_io_requestor_1_req_ready),
.io_requestor_1_req_valid (_dcIF_io_cache_req_valid), // @[Manager.scala:255:22]
.io_requestor_1_req_bits_addr (_dcIF_io_cache_req_bits_addr), // @[Manager.scala:255:22]
.io_requestor_1_req_bits_tag (_dcIF_io_cache_req_bits_tag), // @[Manager.scala:255:22]
.io_requestor_1_req_bits_dprv (_dcIF_io_cache_req_bits_dprv), // @[Manager.scala:255:22]
.io_requestor_1_req_bits_dv (_dcIF_io_cache_req_bits_dv), // @[Manager.scala:255:22]
.io_requestor_1_s1_data_data (_dcIF_io_cache_s1_data_data), // @[Manager.scala:255:22]
.io_requestor_1_s1_data_mask (_dcIF_io_cache_s1_data_mask), // @[Manager.scala:255:22]
.io_requestor_1_s2_nack (_dcacheArb_io_requestor_1_s2_nack),
.io_requestor_1_s2_nack_cause_raw (_dcacheArb_io_requestor_1_s2_nack_cause_raw),
.io_requestor_1_s2_uncached (_dcacheArb_io_requestor_1_s2_uncached),
.io_requestor_1_s2_paddr (_dcacheArb_io_requestor_1_s2_paddr),
.io_requestor_1_resp_valid (_dcacheArb_io_requestor_1_resp_valid),
.io_requestor_1_resp_bits_addr (_dcacheArb_io_requestor_1_resp_bits_addr),
.io_requestor_1_resp_bits_tag (_dcacheArb_io_requestor_1_resp_bits_tag),
.io_requestor_1_resp_bits_cmd (_dcacheArb_io_requestor_1_resp_bits_cmd),
.io_requestor_1_resp_bits_size (_dcacheArb_io_requestor_1_resp_bits_size),
.io_requestor_1_resp_bits_signed (_dcacheArb_io_requestor_1_resp_bits_signed),
.io_requestor_1_resp_bits_dprv (_dcacheArb_io_requestor_1_resp_bits_dprv),
.io_requestor_1_resp_bits_dv (_dcacheArb_io_requestor_1_resp_bits_dv),
.io_requestor_1_resp_bits_data (_dcacheArb_io_requestor_1_resp_bits_data),
.io_requestor_1_resp_bits_mask (_dcacheArb_io_requestor_1_resp_bits_mask),
.io_requestor_1_resp_bits_replay (_dcacheArb_io_requestor_1_resp_bits_replay),
.io_requestor_1_resp_bits_has_data (_dcacheArb_io_requestor_1_resp_bits_has_data),
.io_requestor_1_resp_bits_data_word_bypass (_dcacheArb_io_requestor_1_resp_bits_data_word_bypass),
.io_requestor_1_resp_bits_data_raw (_dcacheArb_io_requestor_1_resp_bits_data_raw),
.io_requestor_1_resp_bits_store_data (_dcacheArb_io_requestor_1_resp_bits_store_data),
.io_requestor_1_replay_next (_dcacheArb_io_requestor_1_replay_next),
.io_requestor_1_s2_xcpt_ma_ld (_dcacheArb_io_requestor_1_s2_xcpt_ma_ld),
.io_requestor_1_s2_xcpt_ma_st (_dcacheArb_io_requestor_1_s2_xcpt_ma_st),
.io_requestor_1_s2_xcpt_pf_ld (_dcacheArb_io_requestor_1_s2_xcpt_pf_ld),
.io_requestor_1_s2_xcpt_pf_st (_dcacheArb_io_requestor_1_s2_xcpt_pf_st),
.io_requestor_1_s2_xcpt_ae_ld (_dcacheArb_io_requestor_1_s2_xcpt_ae_ld),
.io_requestor_1_s2_xcpt_ae_st (_dcacheArb_io_requestor_1_s2_xcpt_ae_st),
.io_requestor_1_s2_gpa (_dcacheArb_io_requestor_1_s2_gpa),
.io_requestor_1_ordered (_dcacheArb_io_requestor_1_ordered),
.io_requestor_1_store_pending (_dcacheArb_io_requestor_1_store_pending),
.io_requestor_1_perf_acquire (_dcacheArb_io_requestor_1_perf_acquire),
.io_requestor_1_perf_release (_dcacheArb_io_requestor_1_perf_release),
.io_requestor_1_perf_grant (_dcacheArb_io_requestor_1_perf_grant),
.io_requestor_1_perf_tlbMiss (_dcacheArb_io_requestor_1_perf_tlbMiss),
.io_requestor_1_perf_blocked (_dcacheArb_io_requestor_1_perf_blocked),
.io_requestor_1_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad),
.io_requestor_1_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW),
.io_requestor_1_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad),
.io_requestor_1_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad),
.io_requestor_1_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore),
.io_mem_req_ready (_dcache_io_cpu_req_ready), // @[Manager.scala:226:61]
.io_mem_req_valid (_dcacheArb_io_mem_req_valid),
.io_mem_req_bits_addr (_dcacheArb_io_mem_req_bits_addr),
.io_mem_req_bits_tag (_dcacheArb_io_mem_req_bits_tag),
.io_mem_req_bits_dprv (_dcacheArb_io_mem_req_bits_dprv),
.io_mem_req_bits_dv (_dcacheArb_io_mem_req_bits_dv),
.io_mem_req_bits_phys (_dcacheArb_io_mem_req_bits_phys),
.io_mem_s1_kill (_dcacheArb_io_mem_s1_kill),
.io_mem_s1_data_data (_dcacheArb_io_mem_s1_data_data),
.io_mem_s1_data_mask (_dcacheArb_io_mem_s1_data_mask),
.io_mem_s2_nack (_dcache_io_cpu_s2_nack), // @[Manager.scala:226:61]
.io_mem_s2_nack_cause_raw (_dcache_io_cpu_s2_nack_cause_raw), // @[Manager.scala:226:61]
.io_mem_s2_uncached (_dcache_io_cpu_s2_uncached), // @[Manager.scala:226:61]
.io_mem_s2_paddr (_dcache_io_cpu_s2_paddr), // @[Manager.scala:226:61]
.io_mem_resp_valid (_dcache_io_cpu_resp_valid), // @[Manager.scala:226:61]
.io_mem_resp_bits_addr (_dcache_io_cpu_resp_bits_addr), // @[Manager.scala:226:61]
.io_mem_resp_bits_tag (_dcache_io_cpu_resp_bits_tag), // @[Manager.scala:226:61]
.io_mem_resp_bits_cmd (_dcache_io_cpu_resp_bits_cmd), // @[Manager.scala:226:61]
.io_mem_resp_bits_size (_dcache_io_cpu_resp_bits_size), // @[Manager.scala:226:61]
.io_mem_resp_bits_signed (_dcache_io_cpu_resp_bits_signed), // @[Manager.scala:226:61]
.io_mem_resp_bits_dprv (_dcache_io_cpu_resp_bits_dprv), // @[Manager.scala:226:61]
.io_mem_resp_bits_dv (_dcache_io_cpu_resp_bits_dv), // @[Manager.scala:226:61]
.io_mem_resp_bits_data (_dcache_io_cpu_resp_bits_data), // @[Manager.scala:226:61]
.io_mem_resp_bits_mask (_dcache_io_cpu_resp_bits_mask), // @[Manager.scala:226:61]
.io_mem_resp_bits_replay (_dcache_io_cpu_resp_bits_replay), // @[Manager.scala:226:61]
.io_mem_resp_bits_has_data (_dcache_io_cpu_resp_bits_has_data), // @[Manager.scala:226:61]
.io_mem_resp_bits_data_word_bypass (_dcache_io_cpu_resp_bits_data_word_bypass), // @[Manager.scala:226:61]
.io_mem_resp_bits_data_raw (_dcache_io_cpu_resp_bits_data_raw), // @[Manager.scala:226:61]
.io_mem_resp_bits_store_data (_dcache_io_cpu_resp_bits_store_data), // @[Manager.scala:226:61]
.io_mem_replay_next (_dcache_io_cpu_replay_next), // @[Manager.scala:226:61]
.io_mem_s2_xcpt_ma_ld (_dcache_io_cpu_s2_xcpt_ma_ld), // @[Manager.scala:226:61]
.io_mem_s2_xcpt_ma_st (_dcache_io_cpu_s2_xcpt_ma_st), // @[Manager.scala:226:61]
.io_mem_s2_xcpt_pf_ld (_dcache_io_cpu_s2_xcpt_pf_ld), // @[Manager.scala:226:61]
.io_mem_s2_xcpt_pf_st (_dcache_io_cpu_s2_xcpt_pf_st), // @[Manager.scala:226:61]
.io_mem_s2_xcpt_ae_ld (_dcache_io_cpu_s2_xcpt_ae_ld), // @[Manager.scala:226:61]
.io_mem_s2_xcpt_ae_st (_dcache_io_cpu_s2_xcpt_ae_st), // @[Manager.scala:226:61]
.io_mem_s2_gpa (_dcache_io_cpu_s2_gpa), // @[Manager.scala:226:61]
.io_mem_ordered (_dcache_io_cpu_ordered), // @[Manager.scala:226:61]
.io_mem_store_pending (_dcache_io_cpu_store_pending), // @[Manager.scala:226:61]
.io_mem_perf_acquire (_dcache_io_cpu_perf_acquire), // @[Manager.scala:226:61]
.io_mem_perf_release (_dcache_io_cpu_perf_release), // @[Manager.scala:226:61]
.io_mem_perf_grant (_dcache_io_cpu_perf_grant), // @[Manager.scala:226:61]
.io_mem_perf_tlbMiss (_dcache_io_cpu_perf_tlbMiss), // @[Manager.scala:226:61]
.io_mem_perf_blocked (_dcache_io_cpu_perf_blocked), // @[Manager.scala:226:61]
.io_mem_perf_canAcceptStoreThenLoad (_dcache_io_cpu_perf_canAcceptStoreThenLoad), // @[Manager.scala:226:61]
.io_mem_perf_canAcceptStoreThenRMW (_dcache_io_cpu_perf_canAcceptStoreThenRMW), // @[Manager.scala:226:61]
.io_mem_perf_canAcceptLoadThenLoad (_dcache_io_cpu_perf_canAcceptLoadThenLoad), // @[Manager.scala:226:61]
.io_mem_perf_storeBufferEmptyAfterLoad (_dcache_io_cpu_perf_storeBufferEmptyAfterLoad), // @[Manager.scala:226:61]
.io_mem_perf_storeBufferEmptyAfterStore (_dcache_io_cpu_perf_storeBufferEmptyAfterStore) // @[Manager.scala:226:61]
); // @[Manager.scala:238:27]
PTW_2 ptw ( // @[Manager.scala:243:21]
.clock (clock),
.reset (reset),
.io_requestor_0_req_ready (_ptw_io_requestor_0_req_ready),
.io_requestor_0_req_valid (_dcache_io_ptw_req_valid), // @[Manager.scala:226:61]
.io_requestor_0_req_bits_bits_addr (_dcache_io_ptw_req_bits_bits_addr), // @[Manager.scala:226:61]
.io_requestor_0_req_bits_bits_need_gpa (_dcache_io_ptw_req_bits_bits_need_gpa), // @[Manager.scala:226:61]
.io_requestor_0_resp_valid (_ptw_io_requestor_0_resp_valid),
.io_requestor_0_resp_bits_ae_ptw (_ptw_io_requestor_0_resp_bits_ae_ptw),
.io_requestor_0_resp_bits_ae_final (_ptw_io_requestor_0_resp_bits_ae_final),
.io_requestor_0_resp_bits_pf (_ptw_io_requestor_0_resp_bits_pf),
.io_requestor_0_resp_bits_gf (_ptw_io_requestor_0_resp_bits_gf),
.io_requestor_0_resp_bits_hr (_ptw_io_requestor_0_resp_bits_hr),
.io_requestor_0_resp_bits_hw (_ptw_io_requestor_0_resp_bits_hw),
.io_requestor_0_resp_bits_hx (_ptw_io_requestor_0_resp_bits_hx),
.io_requestor_0_resp_bits_pte_reserved_for_future (_ptw_io_requestor_0_resp_bits_pte_reserved_for_future),
.io_requestor_0_resp_bits_pte_ppn (_ptw_io_requestor_0_resp_bits_pte_ppn),
.io_requestor_0_resp_bits_pte_reserved_for_software (_ptw_io_requestor_0_resp_bits_pte_reserved_for_software),
.io_requestor_0_resp_bits_pte_d (_ptw_io_requestor_0_resp_bits_pte_d),
.io_requestor_0_resp_bits_pte_a (_ptw_io_requestor_0_resp_bits_pte_a),
.io_requestor_0_resp_bits_pte_g (_ptw_io_requestor_0_resp_bits_pte_g),
.io_requestor_0_resp_bits_pte_u (_ptw_io_requestor_0_resp_bits_pte_u),
.io_requestor_0_resp_bits_pte_x (_ptw_io_requestor_0_resp_bits_pte_x),
.io_requestor_0_resp_bits_pte_w (_ptw_io_requestor_0_resp_bits_pte_w),
.io_requestor_0_resp_bits_pte_r (_ptw_io_requestor_0_resp_bits_pte_r),
.io_requestor_0_resp_bits_pte_v (_ptw_io_requestor_0_resp_bits_pte_v),
.io_requestor_0_resp_bits_level (_ptw_io_requestor_0_resp_bits_level),
.io_requestor_0_resp_bits_homogeneous (_ptw_io_requestor_0_resp_bits_homogeneous),
.io_requestor_0_resp_bits_gpa_valid (_ptw_io_requestor_0_resp_bits_gpa_valid),
.io_requestor_0_resp_bits_gpa_bits (_ptw_io_requestor_0_resp_bits_gpa_bits),
.io_requestor_0_resp_bits_gpa_is_pte (_ptw_io_requestor_0_resp_bits_gpa_is_pte),
.io_requestor_0_ptbr_mode (_ptw_io_requestor_0_ptbr_mode),
.io_requestor_0_ptbr_asid (_ptw_io_requestor_0_ptbr_asid),
.io_requestor_0_ptbr_ppn (_ptw_io_requestor_0_ptbr_ppn),
.io_requestor_0_status_debug (_ptw_io_requestor_0_status_debug),
.io_requestor_0_status_cease (_ptw_io_requestor_0_status_cease),
.io_requestor_0_status_wfi (_ptw_io_requestor_0_status_wfi),
.io_requestor_0_status_isa (_ptw_io_requestor_0_status_isa),
.io_requestor_0_status_dprv (_ptw_io_requestor_0_status_dprv),
.io_requestor_0_status_dv (_ptw_io_requestor_0_status_dv),
.io_requestor_0_status_prv (_ptw_io_requestor_0_status_prv),
.io_requestor_0_status_v (_ptw_io_requestor_0_status_v),
.io_requestor_0_status_sd (_ptw_io_requestor_0_status_sd),
.io_requestor_0_status_zero2 (_ptw_io_requestor_0_status_zero2),
.io_requestor_0_status_mpv (_ptw_io_requestor_0_status_mpv),
.io_requestor_0_status_gva (_ptw_io_requestor_0_status_gva),
.io_requestor_0_status_mbe (_ptw_io_requestor_0_status_mbe),
.io_requestor_0_status_sbe (_ptw_io_requestor_0_status_sbe),
.io_requestor_0_status_sxl (_ptw_io_requestor_0_status_sxl),
.io_requestor_0_status_uxl (_ptw_io_requestor_0_status_uxl),
.io_requestor_0_status_sd_rv32 (_ptw_io_requestor_0_status_sd_rv32),
.io_requestor_0_status_zero1 (_ptw_io_requestor_0_status_zero1),
.io_requestor_0_status_tsr (_ptw_io_requestor_0_status_tsr),
.io_requestor_0_status_tw (_ptw_io_requestor_0_status_tw),
.io_requestor_0_status_tvm (_ptw_io_requestor_0_status_tvm),
.io_requestor_0_status_mxr (_ptw_io_requestor_0_status_mxr),
.io_requestor_0_status_sum (_ptw_io_requestor_0_status_sum),
.io_requestor_0_status_mprv (_ptw_io_requestor_0_status_mprv),
.io_requestor_0_status_xs (_ptw_io_requestor_0_status_xs),
.io_requestor_0_status_fs (_ptw_io_requestor_0_status_fs),
.io_requestor_0_status_mpp (_ptw_io_requestor_0_status_mpp),
.io_requestor_0_status_vs (_ptw_io_requestor_0_status_vs),
.io_requestor_0_status_spp (_ptw_io_requestor_0_status_spp),
.io_requestor_0_status_mpie (_ptw_io_requestor_0_status_mpie),
.io_requestor_0_status_ube (_ptw_io_requestor_0_status_ube),
.io_requestor_0_status_spie (_ptw_io_requestor_0_status_spie),
.io_requestor_0_status_upie (_ptw_io_requestor_0_status_upie),
.io_requestor_0_status_mie (_ptw_io_requestor_0_status_mie),
.io_requestor_0_status_hie (_ptw_io_requestor_0_status_hie),
.io_requestor_0_status_sie (_ptw_io_requestor_0_status_sie),
.io_requestor_0_status_uie (_ptw_io_requestor_0_status_uie),
.io_mem_req_ready (_dcacheArb_io_requestor_0_req_ready), // @[Manager.scala:238:27]
.io_mem_req_valid (_ptw_io_mem_req_valid),
.io_mem_req_bits_addr (_ptw_io_mem_req_bits_addr),
.io_mem_req_bits_dv (_ptw_io_mem_req_bits_dv),
.io_mem_s1_kill (_ptw_io_mem_s1_kill),
.io_mem_s2_nack (_dcacheArb_io_requestor_0_s2_nack), // @[Manager.scala:238:27]
.io_mem_s2_nack_cause_raw (_dcacheArb_io_requestor_0_s2_nack_cause_raw), // @[Manager.scala:238:27]
.io_mem_s2_uncached (_dcacheArb_io_requestor_0_s2_uncached), // @[Manager.scala:238:27]
.io_mem_s2_paddr (_dcacheArb_io_requestor_0_s2_paddr), // @[Manager.scala:238:27]
.io_mem_resp_valid (_dcacheArb_io_requestor_0_resp_valid), // @[Manager.scala:238:27]
.io_mem_resp_bits_addr (_dcacheArb_io_requestor_0_resp_bits_addr), // @[Manager.scala:238:27]
.io_mem_resp_bits_tag (_dcacheArb_io_requestor_0_resp_bits_tag), // @[Manager.scala:238:27]
.io_mem_resp_bits_cmd (_dcacheArb_io_requestor_0_resp_bits_cmd), // @[Manager.scala:238:27]
.io_mem_resp_bits_size (_dcacheArb_io_requestor_0_resp_bits_size), // @[Manager.scala:238:27]
.io_mem_resp_bits_signed (_dcacheArb_io_requestor_0_resp_bits_signed), // @[Manager.scala:238:27]
.io_mem_resp_bits_dprv (_dcacheArb_io_requestor_0_resp_bits_dprv), // @[Manager.scala:238:27]
.io_mem_resp_bits_dv (_dcacheArb_io_requestor_0_resp_bits_dv), // @[Manager.scala:238:27]
.io_mem_resp_bits_data (_dcacheArb_io_requestor_0_resp_bits_data), // @[Manager.scala:238:27]
.io_mem_resp_bits_mask (_dcacheArb_io_requestor_0_resp_bits_mask), // @[Manager.scala:238:27]
.io_mem_resp_bits_replay (_dcacheArb_io_requestor_0_resp_bits_replay), // @[Manager.scala:238:27]
.io_mem_resp_bits_has_data (_dcacheArb_io_requestor_0_resp_bits_has_data), // @[Manager.scala:238:27]
.io_mem_resp_bits_data_word_bypass (_dcacheArb_io_requestor_0_resp_bits_data_word_bypass), // @[Manager.scala:238:27]
.io_mem_resp_bits_data_raw (_dcacheArb_io_requestor_0_resp_bits_data_raw), // @[Manager.scala:238:27]
.io_mem_resp_bits_store_data (_dcacheArb_io_requestor_0_resp_bits_store_data), // @[Manager.scala:238:27]
.io_mem_replay_next (_dcacheArb_io_requestor_0_replay_next), // @[Manager.scala:238:27]
.io_mem_s2_xcpt_ma_ld (_dcacheArb_io_requestor_0_s2_xcpt_ma_ld), // @[Manager.scala:238:27]
.io_mem_s2_xcpt_ma_st (_dcacheArb_io_requestor_0_s2_xcpt_ma_st), // @[Manager.scala:238:27]
.io_mem_s2_xcpt_pf_ld (_dcacheArb_io_requestor_0_s2_xcpt_pf_ld), // @[Manager.scala:238:27]
.io_mem_s2_xcpt_pf_st (_dcacheArb_io_requestor_0_s2_xcpt_pf_st), // @[Manager.scala:238:27]
.io_mem_s2_xcpt_ae_ld (_dcacheArb_io_requestor_0_s2_xcpt_ae_ld), // @[Manager.scala:238:27]
.io_mem_s2_xcpt_ae_st (_dcacheArb_io_requestor_0_s2_xcpt_ae_st), // @[Manager.scala:238:27]
.io_mem_s2_gpa (_dcacheArb_io_requestor_0_s2_gpa), // @[Manager.scala:238:27]
.io_mem_ordered (_dcacheArb_io_requestor_0_ordered), // @[Manager.scala:238:27]
.io_mem_store_pending (_dcacheArb_io_requestor_0_store_pending), // @[Manager.scala:238:27]
.io_mem_perf_acquire (_dcacheArb_io_requestor_0_perf_acquire), // @[Manager.scala:238:27]
.io_mem_perf_release (_dcacheArb_io_requestor_0_perf_release), // @[Manager.scala:238:27]
.io_mem_perf_grant (_dcacheArb_io_requestor_0_perf_grant), // @[Manager.scala:238:27]
.io_mem_perf_tlbMiss (_dcacheArb_io_requestor_0_perf_tlbMiss), // @[Manager.scala:238:27]
.io_mem_perf_blocked (_dcacheArb_io_requestor_0_perf_blocked), // @[Manager.scala:238:27]
.io_mem_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenLoad), // @[Manager.scala:238:27]
.io_mem_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_0_perf_canAcceptStoreThenRMW), // @[Manager.scala:238:27]
.io_mem_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_0_perf_canAcceptLoadThenLoad), // @[Manager.scala:238:27]
.io_mem_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterLoad), // @[Manager.scala:238:27]
.io_mem_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_0_perf_storeBufferEmptyAfterStore), // @[Manager.scala:238:27]
.io_dpath_ptbr_mode (_rerocc_manager_io_ptw_ptbr_mode), // @[Manager.scala:209:34]
.io_dpath_ptbr_asid (_rerocc_manager_io_ptw_ptbr_asid), // @[Manager.scala:209:34]
.io_dpath_ptbr_ppn (_rerocc_manager_io_ptw_ptbr_ppn), // @[Manager.scala:209:34]
.io_dpath_sfence_valid (_rerocc_manager_io_ptw_sfence_valid), // @[Manager.scala:209:34]
.io_dpath_status_debug (_rerocc_manager_io_ptw_status_debug), // @[Manager.scala:209:34]
.io_dpath_status_cease (_rerocc_manager_io_ptw_status_cease), // @[Manager.scala:209:34]
.io_dpath_status_wfi (_rerocc_manager_io_ptw_status_wfi), // @[Manager.scala:209:34]
.io_dpath_status_isa (_rerocc_manager_io_ptw_status_isa), // @[Manager.scala:209:34]
.io_dpath_status_dprv (_rerocc_manager_io_ptw_status_dprv), // @[Manager.scala:209:34]
.io_dpath_status_dv (_rerocc_manager_io_ptw_status_dv), // @[Manager.scala:209:34]
.io_dpath_status_prv (_rerocc_manager_io_ptw_status_prv), // @[Manager.scala:209:34]
.io_dpath_status_v (_rerocc_manager_io_ptw_status_v), // @[Manager.scala:209:34]
.io_dpath_status_sd (_rerocc_manager_io_ptw_status_sd), // @[Manager.scala:209:34]
.io_dpath_status_zero2 (_rerocc_manager_io_ptw_status_zero2), // @[Manager.scala:209:34]
.io_dpath_status_mpv (_rerocc_manager_io_ptw_status_mpv), // @[Manager.scala:209:34]
.io_dpath_status_gva (_rerocc_manager_io_ptw_status_gva), // @[Manager.scala:209:34]
.io_dpath_status_mbe (_rerocc_manager_io_ptw_status_mbe), // @[Manager.scala:209:34]
.io_dpath_status_sbe (_rerocc_manager_io_ptw_status_sbe), // @[Manager.scala:209:34]
.io_dpath_status_sxl (_rerocc_manager_io_ptw_status_sxl), // @[Manager.scala:209:34]
.io_dpath_status_uxl (_rerocc_manager_io_ptw_status_uxl), // @[Manager.scala:209:34]
.io_dpath_status_sd_rv32 (_rerocc_manager_io_ptw_status_sd_rv32), // @[Manager.scala:209:34]
.io_dpath_status_zero1 (_rerocc_manager_io_ptw_status_zero1), // @[Manager.scala:209:34]
.io_dpath_status_tsr (_rerocc_manager_io_ptw_status_tsr), // @[Manager.scala:209:34]
.io_dpath_status_tw (_rerocc_manager_io_ptw_status_tw), // @[Manager.scala:209:34]
.io_dpath_status_tvm (_rerocc_manager_io_ptw_status_tvm), // @[Manager.scala:209:34]
.io_dpath_status_mxr (_rerocc_manager_io_ptw_status_mxr), // @[Manager.scala:209:34]
.io_dpath_status_sum (_rerocc_manager_io_ptw_status_sum), // @[Manager.scala:209:34]
.io_dpath_status_mprv (_rerocc_manager_io_ptw_status_mprv), // @[Manager.scala:209:34]
.io_dpath_status_xs (_rerocc_manager_io_ptw_status_xs), // @[Manager.scala:209:34]
.io_dpath_status_fs (_rerocc_manager_io_ptw_status_fs), // @[Manager.scala:209:34]
.io_dpath_status_mpp (_rerocc_manager_io_ptw_status_mpp), // @[Manager.scala:209:34]
.io_dpath_status_vs (_rerocc_manager_io_ptw_status_vs), // @[Manager.scala:209:34]
.io_dpath_status_spp (_rerocc_manager_io_ptw_status_spp), // @[Manager.scala:209:34]
.io_dpath_status_mpie (_rerocc_manager_io_ptw_status_mpie), // @[Manager.scala:209:34]
.io_dpath_status_ube (_rerocc_manager_io_ptw_status_ube), // @[Manager.scala:209:34]
.io_dpath_status_spie (_rerocc_manager_io_ptw_status_spie), // @[Manager.scala:209:34]
.io_dpath_status_upie (_rerocc_manager_io_ptw_status_upie), // @[Manager.scala:209:34]
.io_dpath_status_mie (_rerocc_manager_io_ptw_status_mie), // @[Manager.scala:209:34]
.io_dpath_status_hie (_rerocc_manager_io_ptw_status_hie), // @[Manager.scala:209:34]
.io_dpath_status_sie (_rerocc_manager_io_ptw_status_sie), // @[Manager.scala:209:34]
.io_dpath_status_uie (_rerocc_manager_io_ptw_status_uie), // @[Manager.scala:209:34]
.io_dpath_perf_pte_miss (_ptw_io_dpath_perf_pte_miss),
.io_dpath_clock_enabled (_ptw_io_dpath_clock_enabled)
); // @[Manager.scala:243:21]
SimpleHellaCacheIF_2 dcIF ( // @[Manager.scala:255:22]
.clock (clock),
.reset (reset),
.io_requestor_req_ready (accumulator_io_mem_req_ready),
.io_requestor_req_valid (accumulator_io_mem_req_valid), // @[LazyRoCC.scala:122:7]
.io_requestor_req_bits_addr (accumulator_io_mem_req_bits_addr), // @[LazyRoCC.scala:122:7]
.io_requestor_req_bits_tag (accumulator_io_mem_req_bits_tag), // @[LazyRoCC.scala:122:7]
.io_requestor_req_bits_dprv (accumulator_io_mem_req_bits_dprv), // @[LazyRoCC.scala:122:7]
.io_requestor_req_bits_dv (accumulator_io_mem_req_bits_dv), // @[LazyRoCC.scala:122:7]
.io_requestor_resp_valid (accumulator_io_mem_resp_valid),
.io_requestor_resp_bits_addr (accumulator_io_mem_resp_bits_addr),
.io_requestor_resp_bits_tag (accumulator_io_mem_resp_bits_tag),
.io_requestor_resp_bits_cmd (accumulator_io_mem_resp_bits_cmd),
.io_requestor_resp_bits_size (accumulator_io_mem_resp_bits_size),
.io_requestor_resp_bits_signed (accumulator_io_mem_resp_bits_signed),
.io_requestor_resp_bits_dprv (accumulator_io_mem_resp_bits_dprv),
.io_requestor_resp_bits_dv (accumulator_io_mem_resp_bits_dv),
.io_requestor_resp_bits_data (accumulator_io_mem_resp_bits_data),
.io_requestor_resp_bits_mask (accumulator_io_mem_resp_bits_mask),
.io_requestor_resp_bits_replay (accumulator_io_mem_resp_bits_replay),
.io_requestor_resp_bits_has_data (accumulator_io_mem_resp_bits_has_data),
.io_requestor_resp_bits_data_word_bypass (accumulator_io_mem_resp_bits_data_word_bypass),
.io_requestor_resp_bits_data_raw (accumulator_io_mem_resp_bits_data_raw),
.io_requestor_resp_bits_store_data (accumulator_io_mem_resp_bits_store_data),
.io_cache_req_ready (_dcacheArb_io_requestor_1_req_ready), // @[Manager.scala:238:27]
.io_cache_req_valid (_dcIF_io_cache_req_valid),
.io_cache_req_bits_addr (_dcIF_io_cache_req_bits_addr),
.io_cache_req_bits_tag (_dcIF_io_cache_req_bits_tag),
.io_cache_req_bits_dprv (_dcIF_io_cache_req_bits_dprv),
.io_cache_req_bits_dv (_dcIF_io_cache_req_bits_dv),
.io_cache_s1_data_data (_dcIF_io_cache_s1_data_data),
.io_cache_s1_data_mask (_dcIF_io_cache_s1_data_mask),
.io_cache_s2_nack (_dcacheArb_io_requestor_1_s2_nack), // @[Manager.scala:238:27]
.io_cache_s2_nack_cause_raw (_dcacheArb_io_requestor_1_s2_nack_cause_raw), // @[Manager.scala:238:27]
.io_cache_s2_uncached (_dcacheArb_io_requestor_1_s2_uncached), // @[Manager.scala:238:27]
.io_cache_s2_paddr (_dcacheArb_io_requestor_1_s2_paddr), // @[Manager.scala:238:27]
.io_cache_resp_valid (_dcacheArb_io_requestor_1_resp_valid), // @[Manager.scala:238:27]
.io_cache_resp_bits_addr (_dcacheArb_io_requestor_1_resp_bits_addr), // @[Manager.scala:238:27]
.io_cache_resp_bits_tag (_dcacheArb_io_requestor_1_resp_bits_tag), // @[Manager.scala:238:27]
.io_cache_resp_bits_cmd (_dcacheArb_io_requestor_1_resp_bits_cmd), // @[Manager.scala:238:27]
.io_cache_resp_bits_size (_dcacheArb_io_requestor_1_resp_bits_size), // @[Manager.scala:238:27]
.io_cache_resp_bits_signed (_dcacheArb_io_requestor_1_resp_bits_signed), // @[Manager.scala:238:27]
.io_cache_resp_bits_dprv (_dcacheArb_io_requestor_1_resp_bits_dprv), // @[Manager.scala:238:27]
.io_cache_resp_bits_dv (_dcacheArb_io_requestor_1_resp_bits_dv), // @[Manager.scala:238:27]
.io_cache_resp_bits_data (_dcacheArb_io_requestor_1_resp_bits_data), // @[Manager.scala:238:27]
.io_cache_resp_bits_mask (_dcacheArb_io_requestor_1_resp_bits_mask), // @[Manager.scala:238:27]
.io_cache_resp_bits_replay (_dcacheArb_io_requestor_1_resp_bits_replay), // @[Manager.scala:238:27]
.io_cache_resp_bits_has_data (_dcacheArb_io_requestor_1_resp_bits_has_data), // @[Manager.scala:238:27]
.io_cache_resp_bits_data_word_bypass (_dcacheArb_io_requestor_1_resp_bits_data_word_bypass), // @[Manager.scala:238:27]
.io_cache_resp_bits_data_raw (_dcacheArb_io_requestor_1_resp_bits_data_raw), // @[Manager.scala:238:27]
.io_cache_resp_bits_store_data (_dcacheArb_io_requestor_1_resp_bits_store_data), // @[Manager.scala:238:27]
.io_cache_replay_next (_dcacheArb_io_requestor_1_replay_next), // @[Manager.scala:238:27]
.io_cache_s2_xcpt_ma_ld (_dcacheArb_io_requestor_1_s2_xcpt_ma_ld), // @[Manager.scala:238:27]
.io_cache_s2_xcpt_ma_st (_dcacheArb_io_requestor_1_s2_xcpt_ma_st), // @[Manager.scala:238:27]
.io_cache_s2_xcpt_pf_ld (_dcacheArb_io_requestor_1_s2_xcpt_pf_ld), // @[Manager.scala:238:27]
.io_cache_s2_xcpt_pf_st (_dcacheArb_io_requestor_1_s2_xcpt_pf_st), // @[Manager.scala:238:27]
.io_cache_s2_xcpt_ae_ld (_dcacheArb_io_requestor_1_s2_xcpt_ae_ld), // @[Manager.scala:238:27]
.io_cache_s2_xcpt_ae_st (_dcacheArb_io_requestor_1_s2_xcpt_ae_st), // @[Manager.scala:238:27]
.io_cache_s2_gpa (_dcacheArb_io_requestor_1_s2_gpa), // @[Manager.scala:238:27]
.io_cache_ordered (_dcacheArb_io_requestor_1_ordered), // @[Manager.scala:238:27]
.io_cache_store_pending (_dcacheArb_io_requestor_1_store_pending), // @[Manager.scala:238:27]
.io_cache_perf_acquire (_dcacheArb_io_requestor_1_perf_acquire), // @[Manager.scala:238:27]
.io_cache_perf_release (_dcacheArb_io_requestor_1_perf_release), // @[Manager.scala:238:27]
.io_cache_perf_grant (_dcacheArb_io_requestor_1_perf_grant), // @[Manager.scala:238:27]
.io_cache_perf_tlbMiss (_dcacheArb_io_requestor_1_perf_tlbMiss), // @[Manager.scala:238:27]
.io_cache_perf_blocked (_dcacheArb_io_requestor_1_perf_blocked), // @[Manager.scala:238:27]
.io_cache_perf_canAcceptStoreThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenLoad), // @[Manager.scala:238:27]
.io_cache_perf_canAcceptStoreThenRMW (_dcacheArb_io_requestor_1_perf_canAcceptStoreThenRMW), // @[Manager.scala:238:27]
.io_cache_perf_canAcceptLoadThenLoad (_dcacheArb_io_requestor_1_perf_canAcceptLoadThenLoad), // @[Manager.scala:238:27]
.io_cache_perf_storeBufferEmptyAfterLoad (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterLoad), // @[Manager.scala:238:27]
.io_cache_perf_storeBufferEmptyAfterStore (_dcacheArb_io_requestor_1_perf_storeBufferEmptyAfterStore) // @[Manager.scala:238:27]
); // @[Manager.scala:255:22]
assign auto_ctrl_ctrl_in_a_ready = auto_ctrl_ctrl_in_a_ready_0; // @[Manager.scala:237:34]
assign auto_ctrl_ctrl_in_d_valid = auto_ctrl_ctrl_in_d_valid_0; // @[Manager.scala:237:34]
assign auto_ctrl_ctrl_in_d_bits_opcode = auto_ctrl_ctrl_in_d_bits_opcode_0; // @[Manager.scala:237:34]
assign auto_ctrl_ctrl_in_d_bits_size = auto_ctrl_ctrl_in_d_bits_size_0; // @[Manager.scala:237:34]
assign auto_ctrl_ctrl_in_d_bits_source = auto_ctrl_ctrl_in_d_bits_source_0; // @[Manager.scala:237:34]
assign auto_ctrl_ctrl_in_d_bits_data = auto_ctrl_ctrl_in_d_bits_data_0; // @[Manager.scala:237:34]
assign auto_buffer_out_a_valid = auto_buffer_out_a_valid_0; // @[Manager.scala:237:34]
assign auto_buffer_out_a_bits_opcode = auto_buffer_out_a_bits_opcode_0; // @[Manager.scala:237:34]
assign auto_buffer_out_a_bits_param = auto_buffer_out_a_bits_param_0; // @[Manager.scala:237:34]
assign auto_buffer_out_a_bits_size = auto_buffer_out_a_bits_size_0; // @[Manager.scala:237:34]
assign auto_buffer_out_a_bits_source = auto_buffer_out_a_bits_source_0; // @[Manager.scala:237:34]
assign auto_buffer_out_a_bits_address = auto_buffer_out_a_bits_address_0; // @[Manager.scala:237:34]
assign auto_buffer_out_a_bits_mask = auto_buffer_out_a_bits_mask_0; // @[Manager.scala:237:34]
assign auto_buffer_out_a_bits_data = auto_buffer_out_a_bits_data_0; // @[Manager.scala:237:34]
assign auto_buffer_out_a_bits_corrupt = auto_buffer_out_a_bits_corrupt_0; // @[Manager.scala:237:34]
assign auto_buffer_out_b_ready = auto_buffer_out_b_ready_0; // @[Manager.scala:237:34]
assign auto_buffer_out_c_valid = auto_buffer_out_c_valid_0; // @[Manager.scala:237:34]
assign auto_buffer_out_c_bits_opcode = auto_buffer_out_c_bits_opcode_0; // @[Manager.scala:237:34]
assign auto_buffer_out_c_bits_param = auto_buffer_out_c_bits_param_0; // @[Manager.scala:237:34]
assign auto_buffer_out_c_bits_size = auto_buffer_out_c_bits_size_0; // @[Manager.scala:237:34]
assign auto_buffer_out_c_bits_source = auto_buffer_out_c_bits_source_0; // @[Manager.scala:237:34]
assign auto_buffer_out_c_bits_address = auto_buffer_out_c_bits_address_0; // @[Manager.scala:237:34]
assign auto_buffer_out_c_bits_data = auto_buffer_out_c_bits_data_0; // @[Manager.scala:237:34]
assign auto_buffer_out_c_bits_corrupt = auto_buffer_out_c_bits_corrupt_0; // @[Manager.scala:237:34]
assign auto_buffer_out_d_ready = auto_buffer_out_d_ready_0; // @[Manager.scala:237:34]
assign auto_buffer_out_e_valid = auto_buffer_out_e_valid_0; // @[Manager.scala:237:34]
assign auto_buffer_out_e_bits_sink = auto_buffer_out_e_bits_sink_0; // @[Manager.scala:237:34]
assign auto_re_ro_cc_in_req_ready = auto_re_ro_cc_in_req_ready_0; // @[Manager.scala:237:34]
assign auto_re_ro_cc_in_resp_valid = auto_re_ro_cc_in_resp_valid_0; // @[Manager.scala:237:34]
assign auto_re_ro_cc_in_resp_bits_opcode = auto_re_ro_cc_in_resp_bits_opcode_0; // @[Manager.scala:237:34]
assign auto_re_ro_cc_in_resp_bits_client_id = auto_re_ro_cc_in_resp_bits_client_id_0; // @[Manager.scala:237:34]
assign auto_re_ro_cc_in_resp_bits_manager_id = auto_re_ro_cc_in_resp_bits_manager_id_0; // @[Manager.scala:237:34]
assign auto_re_ro_cc_in_resp_bits_data = auto_re_ro_cc_in_resp_bits_data_0; // @[Manager.scala:237:34]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_114 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_194
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_114( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_194 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IntSyncCrossingSource_n1x1_29 :
input clock : Clock
input reset : Reset
output auto : { flip in : UInt<1>[1], out : { sync : UInt<1>[1]}}
wire nodeIn : UInt<1>[1]
invalidate nodeIn[0]
wire nodeOut : { sync : UInt<1>[1]}
invalidate nodeOut.sync[0]
connect auto.out, nodeOut
connect nodeIn, auto.in
inst reg of AsyncResetRegVec_w1_i0_29
connect reg.clock, clock
connect reg.reset, reset
connect reg.io.d, nodeIn[0]
connect reg.io.en, UInt<1>(0h1)
node _T = bits(reg.io.q, 0, 0)
connect nodeOut.sync[0], _T | module IntSyncCrossingSource_n1x1_29( // @[Crossing.scala:41:9]
input clock, // @[Crossing.scala:41:9]
input reset // @[Crossing.scala:41:9]
);
wire auto_in_0 = 1'h0; // @[Crossing.scala:41:9]
wire auto_out_sync_0 = 1'h0; // @[Crossing.scala:41:9]
wire nodeIn_0 = 1'h0; // @[MixedNode.scala:551:17]
wire nodeOut_sync_0 = 1'h0; // @[MixedNode.scala:542:17]
AsyncResetRegVec_w1_i0_29 reg_0 ( // @[AsyncResetReg.scala:86:21]
.clock (clock),
.reset (reset)
); // @[AsyncResetReg.scala:86:21]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i32_e8_s24_1 :
output io : { flip signedIn : UInt<1>, flip in : UInt<32>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node _intAsRawFloat_sign_T = bits(io.in, 31, 31)
node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T)
node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in)
node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1)
node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in)
node _intAsRawFloat_extAbsIn_T = cat(UInt<32>(0h0), intAsRawFloat_absIn)
node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 31, 0)
node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0)
node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1)
node _intAsRawFloat_adjustedNormDist_T_2 = bits(intAsRawFloat_extAbsIn, 2, 2)
node _intAsRawFloat_adjustedNormDist_T_3 = bits(intAsRawFloat_extAbsIn, 3, 3)
node _intAsRawFloat_adjustedNormDist_T_4 = bits(intAsRawFloat_extAbsIn, 4, 4)
node _intAsRawFloat_adjustedNormDist_T_5 = bits(intAsRawFloat_extAbsIn, 5, 5)
node _intAsRawFloat_adjustedNormDist_T_6 = bits(intAsRawFloat_extAbsIn, 6, 6)
node _intAsRawFloat_adjustedNormDist_T_7 = bits(intAsRawFloat_extAbsIn, 7, 7)
node _intAsRawFloat_adjustedNormDist_T_8 = bits(intAsRawFloat_extAbsIn, 8, 8)
node _intAsRawFloat_adjustedNormDist_T_9 = bits(intAsRawFloat_extAbsIn, 9, 9)
node _intAsRawFloat_adjustedNormDist_T_10 = bits(intAsRawFloat_extAbsIn, 10, 10)
node _intAsRawFloat_adjustedNormDist_T_11 = bits(intAsRawFloat_extAbsIn, 11, 11)
node _intAsRawFloat_adjustedNormDist_T_12 = bits(intAsRawFloat_extAbsIn, 12, 12)
node _intAsRawFloat_adjustedNormDist_T_13 = bits(intAsRawFloat_extAbsIn, 13, 13)
node _intAsRawFloat_adjustedNormDist_T_14 = bits(intAsRawFloat_extAbsIn, 14, 14)
node _intAsRawFloat_adjustedNormDist_T_15 = bits(intAsRawFloat_extAbsIn, 15, 15)
node _intAsRawFloat_adjustedNormDist_T_16 = bits(intAsRawFloat_extAbsIn, 16, 16)
node _intAsRawFloat_adjustedNormDist_T_17 = bits(intAsRawFloat_extAbsIn, 17, 17)
node _intAsRawFloat_adjustedNormDist_T_18 = bits(intAsRawFloat_extAbsIn, 18, 18)
node _intAsRawFloat_adjustedNormDist_T_19 = bits(intAsRawFloat_extAbsIn, 19, 19)
node _intAsRawFloat_adjustedNormDist_T_20 = bits(intAsRawFloat_extAbsIn, 20, 20)
node _intAsRawFloat_adjustedNormDist_T_21 = bits(intAsRawFloat_extAbsIn, 21, 21)
node _intAsRawFloat_adjustedNormDist_T_22 = bits(intAsRawFloat_extAbsIn, 22, 22)
node _intAsRawFloat_adjustedNormDist_T_23 = bits(intAsRawFloat_extAbsIn, 23, 23)
node _intAsRawFloat_adjustedNormDist_T_24 = bits(intAsRawFloat_extAbsIn, 24, 24)
node _intAsRawFloat_adjustedNormDist_T_25 = bits(intAsRawFloat_extAbsIn, 25, 25)
node _intAsRawFloat_adjustedNormDist_T_26 = bits(intAsRawFloat_extAbsIn, 26, 26)
node _intAsRawFloat_adjustedNormDist_T_27 = bits(intAsRawFloat_extAbsIn, 27, 27)
node _intAsRawFloat_adjustedNormDist_T_28 = bits(intAsRawFloat_extAbsIn, 28, 28)
node _intAsRawFloat_adjustedNormDist_T_29 = bits(intAsRawFloat_extAbsIn, 29, 29)
node _intAsRawFloat_adjustedNormDist_T_30 = bits(intAsRawFloat_extAbsIn, 30, 30)
node _intAsRawFloat_adjustedNormDist_T_31 = bits(intAsRawFloat_extAbsIn, 31, 31)
node _intAsRawFloat_adjustedNormDist_T_32 = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<5>(0h1e), UInt<5>(0h1f))
node _intAsRawFloat_adjustedNormDist_T_33 = mux(_intAsRawFloat_adjustedNormDist_T_2, UInt<5>(0h1d), _intAsRawFloat_adjustedNormDist_T_32)
node _intAsRawFloat_adjustedNormDist_T_34 = mux(_intAsRawFloat_adjustedNormDist_T_3, UInt<5>(0h1c), _intAsRawFloat_adjustedNormDist_T_33)
node _intAsRawFloat_adjustedNormDist_T_35 = mux(_intAsRawFloat_adjustedNormDist_T_4, UInt<5>(0h1b), _intAsRawFloat_adjustedNormDist_T_34)
node _intAsRawFloat_adjustedNormDist_T_36 = mux(_intAsRawFloat_adjustedNormDist_T_5, UInt<5>(0h1a), _intAsRawFloat_adjustedNormDist_T_35)
node _intAsRawFloat_adjustedNormDist_T_37 = mux(_intAsRawFloat_adjustedNormDist_T_6, UInt<5>(0h19), _intAsRawFloat_adjustedNormDist_T_36)
node _intAsRawFloat_adjustedNormDist_T_38 = mux(_intAsRawFloat_adjustedNormDist_T_7, UInt<5>(0h18), _intAsRawFloat_adjustedNormDist_T_37)
node _intAsRawFloat_adjustedNormDist_T_39 = mux(_intAsRawFloat_adjustedNormDist_T_8, UInt<5>(0h17), _intAsRawFloat_adjustedNormDist_T_38)
node _intAsRawFloat_adjustedNormDist_T_40 = mux(_intAsRawFloat_adjustedNormDist_T_9, UInt<5>(0h16), _intAsRawFloat_adjustedNormDist_T_39)
node _intAsRawFloat_adjustedNormDist_T_41 = mux(_intAsRawFloat_adjustedNormDist_T_10, UInt<5>(0h15), _intAsRawFloat_adjustedNormDist_T_40)
node _intAsRawFloat_adjustedNormDist_T_42 = mux(_intAsRawFloat_adjustedNormDist_T_11, UInt<5>(0h14), _intAsRawFloat_adjustedNormDist_T_41)
node _intAsRawFloat_adjustedNormDist_T_43 = mux(_intAsRawFloat_adjustedNormDist_T_12, UInt<5>(0h13), _intAsRawFloat_adjustedNormDist_T_42)
node _intAsRawFloat_adjustedNormDist_T_44 = mux(_intAsRawFloat_adjustedNormDist_T_13, UInt<5>(0h12), _intAsRawFloat_adjustedNormDist_T_43)
node _intAsRawFloat_adjustedNormDist_T_45 = mux(_intAsRawFloat_adjustedNormDist_T_14, UInt<5>(0h11), _intAsRawFloat_adjustedNormDist_T_44)
node _intAsRawFloat_adjustedNormDist_T_46 = mux(_intAsRawFloat_adjustedNormDist_T_15, UInt<5>(0h10), _intAsRawFloat_adjustedNormDist_T_45)
node _intAsRawFloat_adjustedNormDist_T_47 = mux(_intAsRawFloat_adjustedNormDist_T_16, UInt<4>(0hf), _intAsRawFloat_adjustedNormDist_T_46)
node _intAsRawFloat_adjustedNormDist_T_48 = mux(_intAsRawFloat_adjustedNormDist_T_17, UInt<4>(0he), _intAsRawFloat_adjustedNormDist_T_47)
node _intAsRawFloat_adjustedNormDist_T_49 = mux(_intAsRawFloat_adjustedNormDist_T_18, UInt<4>(0hd), _intAsRawFloat_adjustedNormDist_T_48)
node _intAsRawFloat_adjustedNormDist_T_50 = mux(_intAsRawFloat_adjustedNormDist_T_19, UInt<4>(0hc), _intAsRawFloat_adjustedNormDist_T_49)
node _intAsRawFloat_adjustedNormDist_T_51 = mux(_intAsRawFloat_adjustedNormDist_T_20, UInt<4>(0hb), _intAsRawFloat_adjustedNormDist_T_50)
node _intAsRawFloat_adjustedNormDist_T_52 = mux(_intAsRawFloat_adjustedNormDist_T_21, UInt<4>(0ha), _intAsRawFloat_adjustedNormDist_T_51)
node _intAsRawFloat_adjustedNormDist_T_53 = mux(_intAsRawFloat_adjustedNormDist_T_22, UInt<4>(0h9), _intAsRawFloat_adjustedNormDist_T_52)
node _intAsRawFloat_adjustedNormDist_T_54 = mux(_intAsRawFloat_adjustedNormDist_T_23, UInt<4>(0h8), _intAsRawFloat_adjustedNormDist_T_53)
node _intAsRawFloat_adjustedNormDist_T_55 = mux(_intAsRawFloat_adjustedNormDist_T_24, UInt<3>(0h7), _intAsRawFloat_adjustedNormDist_T_54)
node _intAsRawFloat_adjustedNormDist_T_56 = mux(_intAsRawFloat_adjustedNormDist_T_25, UInt<3>(0h6), _intAsRawFloat_adjustedNormDist_T_55)
node _intAsRawFloat_adjustedNormDist_T_57 = mux(_intAsRawFloat_adjustedNormDist_T_26, UInt<3>(0h5), _intAsRawFloat_adjustedNormDist_T_56)
node _intAsRawFloat_adjustedNormDist_T_58 = mux(_intAsRawFloat_adjustedNormDist_T_27, UInt<3>(0h4), _intAsRawFloat_adjustedNormDist_T_57)
node _intAsRawFloat_adjustedNormDist_T_59 = mux(_intAsRawFloat_adjustedNormDist_T_28, UInt<2>(0h3), _intAsRawFloat_adjustedNormDist_T_58)
node _intAsRawFloat_adjustedNormDist_T_60 = mux(_intAsRawFloat_adjustedNormDist_T_29, UInt<2>(0h2), _intAsRawFloat_adjustedNormDist_T_59)
node _intAsRawFloat_adjustedNormDist_T_61 = mux(_intAsRawFloat_adjustedNormDist_T_30, UInt<1>(0h1), _intAsRawFloat_adjustedNormDist_T_60)
node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_31, UInt<1>(0h0), _intAsRawFloat_adjustedNormDist_T_61)
node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist)
node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 31, 0)
wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<8>, sig : UInt<33>}
connect intAsRawFloat.isNaN, UInt<1>(0h0)
connect intAsRawFloat.isInf, UInt<1>(0h0)
node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 31, 31)
node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0))
connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1
connect intAsRawFloat.sign, intAsRawFloat_sign
node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 4, 0)
node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T)
node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1)
node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2)
connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3
connect intAsRawFloat.sig, intAsRawFloat_sig
inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie6_is32_oe8_os24_1
connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0)
connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig
connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp
connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign
connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero
connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf
connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN
connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundAnyRawFNToRecFN.io.out
connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags | module INToRecFN_i32_e8_s24_1( // @[INToRecFN.scala:43:7]
input [31:0] io_in, // @[INToRecFN.scala:46:16]
output [32:0] io_out // @[INToRecFN.scala:46:16]
);
wire [31:0] io_in_0 = io_in; // @[INToRecFN.scala:43:7]
wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire [2:0] io_roundingMode = 3'h0; // @[INToRecFN.scala:43:7, :46:16, :60:15]
wire io_signedIn = 1'h1; // @[INToRecFN.scala:43:7]
wire io_detectTininess = 1'h1; // @[INToRecFN.scala:43:7]
wire [32:0] io_out_0; // @[INToRecFN.scala:43:7]
wire [4:0] io_exceptionFlags; // @[INToRecFN.scala:43:7]
wire _intAsRawFloat_sign_T = io_in_0[31]; // @[rawFloatFromIN.scala:51:34]
wire intAsRawFloat_sign = _intAsRawFloat_sign_T; // @[rawFloatFromIN.scala:51:{29,34}]
wire intAsRawFloat_sign_0 = intAsRawFloat_sign; // @[rawFloatFromIN.scala:51:29, :59:23]
wire [32:0] _intAsRawFloat_absIn_T = 33'h0 - {1'h0, io_in_0}; // @[rawFloatFromIN.scala:52:31]
wire [31:0] _intAsRawFloat_absIn_T_1 = _intAsRawFloat_absIn_T[31:0]; // @[rawFloatFromIN.scala:52:31]
wire [31:0] intAsRawFloat_absIn = intAsRawFloat_sign ? _intAsRawFloat_absIn_T_1 : io_in_0; // @[rawFloatFromIN.scala:51:29, :52:{24,31}]
wire [63:0] _intAsRawFloat_extAbsIn_T = {32'h0, intAsRawFloat_absIn}; // @[rawFloatFromIN.scala:52:24, :53:44]
wire [31:0] intAsRawFloat_extAbsIn = _intAsRawFloat_extAbsIn_T[31:0]; // @[rawFloatFromIN.scala:53:{44,53}]
wire _intAsRawFloat_adjustedNormDist_T = intAsRawFloat_extAbsIn[0]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_1 = intAsRawFloat_extAbsIn[1]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_2 = intAsRawFloat_extAbsIn[2]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_3 = intAsRawFloat_extAbsIn[3]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_4 = intAsRawFloat_extAbsIn[4]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_5 = intAsRawFloat_extAbsIn[5]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_6 = intAsRawFloat_extAbsIn[6]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_7 = intAsRawFloat_extAbsIn[7]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_8 = intAsRawFloat_extAbsIn[8]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_9 = intAsRawFloat_extAbsIn[9]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_10 = intAsRawFloat_extAbsIn[10]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_11 = intAsRawFloat_extAbsIn[11]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_12 = intAsRawFloat_extAbsIn[12]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_13 = intAsRawFloat_extAbsIn[13]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_14 = intAsRawFloat_extAbsIn[14]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_15 = intAsRawFloat_extAbsIn[15]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_16 = intAsRawFloat_extAbsIn[16]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_17 = intAsRawFloat_extAbsIn[17]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_18 = intAsRawFloat_extAbsIn[18]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_19 = intAsRawFloat_extAbsIn[19]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_20 = intAsRawFloat_extAbsIn[20]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_21 = intAsRawFloat_extAbsIn[21]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_22 = intAsRawFloat_extAbsIn[22]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_23 = intAsRawFloat_extAbsIn[23]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_24 = intAsRawFloat_extAbsIn[24]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_25 = intAsRawFloat_extAbsIn[25]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_26 = intAsRawFloat_extAbsIn[26]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_27 = intAsRawFloat_extAbsIn[27]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_28 = intAsRawFloat_extAbsIn[28]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_29 = intAsRawFloat_extAbsIn[29]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_30 = intAsRawFloat_extAbsIn[30]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_31 = intAsRawFloat_extAbsIn[31]; // @[rawFloatFromIN.scala:53:53]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_32 = {4'hF, ~_intAsRawFloat_adjustedNormDist_T_1}; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_33 = _intAsRawFloat_adjustedNormDist_T_2 ? 5'h1D : _intAsRawFloat_adjustedNormDist_T_32; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_34 = _intAsRawFloat_adjustedNormDist_T_3 ? 5'h1C : _intAsRawFloat_adjustedNormDist_T_33; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_35 = _intAsRawFloat_adjustedNormDist_T_4 ? 5'h1B : _intAsRawFloat_adjustedNormDist_T_34; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_36 = _intAsRawFloat_adjustedNormDist_T_5 ? 5'h1A : _intAsRawFloat_adjustedNormDist_T_35; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_37 = _intAsRawFloat_adjustedNormDist_T_6 ? 5'h19 : _intAsRawFloat_adjustedNormDist_T_36; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_38 = _intAsRawFloat_adjustedNormDist_T_7 ? 5'h18 : _intAsRawFloat_adjustedNormDist_T_37; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_39 = _intAsRawFloat_adjustedNormDist_T_8 ? 5'h17 : _intAsRawFloat_adjustedNormDist_T_38; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_40 = _intAsRawFloat_adjustedNormDist_T_9 ? 5'h16 : _intAsRawFloat_adjustedNormDist_T_39; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_41 = _intAsRawFloat_adjustedNormDist_T_10 ? 5'h15 : _intAsRawFloat_adjustedNormDist_T_40; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_42 = _intAsRawFloat_adjustedNormDist_T_11 ? 5'h14 : _intAsRawFloat_adjustedNormDist_T_41; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_43 = _intAsRawFloat_adjustedNormDist_T_12 ? 5'h13 : _intAsRawFloat_adjustedNormDist_T_42; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_44 = _intAsRawFloat_adjustedNormDist_T_13 ? 5'h12 : _intAsRawFloat_adjustedNormDist_T_43; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_45 = _intAsRawFloat_adjustedNormDist_T_14 ? 5'h11 : _intAsRawFloat_adjustedNormDist_T_44; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_46 = _intAsRawFloat_adjustedNormDist_T_15 ? 5'h10 : _intAsRawFloat_adjustedNormDist_T_45; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_47 = _intAsRawFloat_adjustedNormDist_T_16 ? 5'hF : _intAsRawFloat_adjustedNormDist_T_46; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_48 = _intAsRawFloat_adjustedNormDist_T_17 ? 5'hE : _intAsRawFloat_adjustedNormDist_T_47; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_49 = _intAsRawFloat_adjustedNormDist_T_18 ? 5'hD : _intAsRawFloat_adjustedNormDist_T_48; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_50 = _intAsRawFloat_adjustedNormDist_T_19 ? 5'hC : _intAsRawFloat_adjustedNormDist_T_49; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_51 = _intAsRawFloat_adjustedNormDist_T_20 ? 5'hB : _intAsRawFloat_adjustedNormDist_T_50; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_52 = _intAsRawFloat_adjustedNormDist_T_21 ? 5'hA : _intAsRawFloat_adjustedNormDist_T_51; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_53 = _intAsRawFloat_adjustedNormDist_T_22 ? 5'h9 : _intAsRawFloat_adjustedNormDist_T_52; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_54 = _intAsRawFloat_adjustedNormDist_T_23 ? 5'h8 : _intAsRawFloat_adjustedNormDist_T_53; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_55 = _intAsRawFloat_adjustedNormDist_T_24 ? 5'h7 : _intAsRawFloat_adjustedNormDist_T_54; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_56 = _intAsRawFloat_adjustedNormDist_T_25 ? 5'h6 : _intAsRawFloat_adjustedNormDist_T_55; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_57 = _intAsRawFloat_adjustedNormDist_T_26 ? 5'h5 : _intAsRawFloat_adjustedNormDist_T_56; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_58 = _intAsRawFloat_adjustedNormDist_T_27 ? 5'h4 : _intAsRawFloat_adjustedNormDist_T_57; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_59 = _intAsRawFloat_adjustedNormDist_T_28 ? 5'h3 : _intAsRawFloat_adjustedNormDist_T_58; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_60 = _intAsRawFloat_adjustedNormDist_T_29 ? 5'h2 : _intAsRawFloat_adjustedNormDist_T_59; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_adjustedNormDist_T_61 = _intAsRawFloat_adjustedNormDist_T_30 ? 5'h1 : _intAsRawFloat_adjustedNormDist_T_60; // @[Mux.scala:50:70]
wire [4:0] intAsRawFloat_adjustedNormDist = _intAsRawFloat_adjustedNormDist_T_31 ? 5'h0 : _intAsRawFloat_adjustedNormDist_T_61; // @[Mux.scala:50:70]
wire [4:0] _intAsRawFloat_out_sExp_T = intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70]
wire [62:0] _intAsRawFloat_sig_T = {31'h0, intAsRawFloat_extAbsIn} << intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70]
wire [31:0] intAsRawFloat_sig = _intAsRawFloat_sig_T[31:0]; // @[rawFloatFromIN.scala:56:{22,41}]
wire _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:62:23]
wire [7:0] _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:64:72]
wire intAsRawFloat_isZero; // @[rawFloatFromIN.scala:59:23]
wire [7:0] intAsRawFloat_sExp; // @[rawFloatFromIN.scala:59:23]
wire [32:0] intAsRawFloat_sig_0; // @[rawFloatFromIN.scala:59:23]
wire _intAsRawFloat_out_isZero_T = intAsRawFloat_sig[31]; // @[rawFloatFromIN.scala:56:41, :62:28]
assign _intAsRawFloat_out_isZero_T_1 = ~_intAsRawFloat_out_isZero_T; // @[rawFloatFromIN.scala:62:{23,28}]
assign intAsRawFloat_isZero = _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:59:23, :62:23]
wire [4:0] _intAsRawFloat_out_sExp_T_1 = ~_intAsRawFloat_out_sExp_T; // @[rawFloatFromIN.scala:64:{36,53}]
wire [6:0] _intAsRawFloat_out_sExp_T_2 = {2'h2, _intAsRawFloat_out_sExp_T_1}; // @[rawFloatFromIN.scala:64:{33,36}]
assign _intAsRawFloat_out_sExp_T_3 = {1'h0, _intAsRawFloat_out_sExp_T_2}; // @[rawFloatFromIN.scala:64:{33,72}]
assign intAsRawFloat_sExp = _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:59:23, :64:72]
assign intAsRawFloat_sig_0 = {1'h0, intAsRawFloat_sig}; // @[rawFloatFromIN.scala:56:41, :59:23, :65:20]
RoundAnyRawFNToRecFN_ie6_is32_oe8_os24_1 roundAnyRawFNToRecFN ( // @[INToRecFN.scala:60:15]
.io_in_isZero (intAsRawFloat_isZero), // @[rawFloatFromIN.scala:59:23]
.io_in_sign (intAsRawFloat_sign_0), // @[rawFloatFromIN.scala:59:23]
.io_in_sExp (intAsRawFloat_sExp), // @[rawFloatFromIN.scala:59:23]
.io_in_sig (intAsRawFloat_sig_0), // @[rawFloatFromIN.scala:59:23]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[INToRecFN.scala:60:15]
assign io_out = io_out_0; // @[INToRecFN.scala:43:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_191 :
input clock : Clock
input reset : Reset
output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}}
regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff)
reg value_reg : { symbol : UInt<10>}, clock
connect io.output_prev.key, key_reg
connect io.output_prev.value, value_reg
connect io.output_nxt.key, key_reg
connect io.output_nxt.value, value_reg
connect io.cur_output_keyval.key, key_reg
connect io.cur_output_keyval.value, value_reg
when io.cmd.valid :
node _T = eq(UInt<1>(0h0), io.cmd.bits)
when _T :
connect key_reg, io.input_nxt.key
connect value_reg, io.input_nxt.value
else :
node _T_1 = eq(UInt<1>(0h1), io.cmd.bits)
when _T_1 :
when io.insert_here :
connect key_reg, io.cur_input_keyval.key
connect value_reg, io.cur_input_keyval.value
else :
node _T_2 = geq(key_reg, io.cur_input_keyval.key)
when _T_2 :
connect key_reg, io.input_prev.key
connect value_reg, io.input_prev.value
else :
skip | module PriorityQueueStage_191( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetRegVec_w1_i0_3 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>, flip en : UInt<1>}
node _reg_T = asAsyncReset(reset)
regreset reg : UInt<1>, clock, _reg_T, UInt<1>(0h0)
when io.en :
connect reg, io.d
connect io.q, reg | module AsyncResetRegVec_w1_i0_3( // @[AsyncResetReg.scala:56:7]
input clock, // @[AsyncResetReg.scala:56:7]
input reset // @[AsyncResetReg.scala:56:7]
);
wire _reg_T = reset; // @[AsyncResetReg.scala:61:29]
wire io_en = 1'h1; // @[AsyncResetReg.scala:56:7, :59:14]
wire io_d = 1'h0; // @[AsyncResetReg.scala:56:7]
wire io_q = 1'h0; // @[AsyncResetReg.scala:56:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_62 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0)
node _source_ok_T_25 = shr(io.in.a.bits.source, 2)
node _source_ok_T_26 = eq(_source_ok_T_25, UInt<4>(0h8))
node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27)
node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<2>(0h2))
node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29)
node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE : UInt<1>[9]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_30
connect _source_ok_WIRE[6], _source_ok_T_31
connect _source_ok_WIRE[7], _source_ok_T_32
connect _source_ok_WIRE[8], _source_ok_T_33
node _source_ok_T_34 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[2])
node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[3])
node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[4])
node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[5])
node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[6])
node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[7])
node source_ok = or(_source_ok_T_40, _source_ok_WIRE[8])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<1>(0h0))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<1>(0h1))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<2>(0h2))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<2>(0h3))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0)
node _T_64 = shr(io.in.a.bits.source, 2)
node _T_65 = eq(_T_64, UInt<4>(0h8))
node _T_66 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_67 = and(_T_65, _T_66)
node _T_68 = leq(uncommonBits_4, UInt<2>(0h2))
node _T_69 = and(_T_67, _T_68)
node _T_70 = eq(_T_69, UInt<1>(0h0))
node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_72 = cvt(_T_71)
node _T_73 = and(_T_72, asSInt(UInt<1>(0h0)))
node _T_74 = asSInt(_T_73)
node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0)))
node _T_76 = or(_T_70, _T_75)
node _T_77 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_78 = eq(_T_77, UInt<1>(0h0))
node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_80 = cvt(_T_79)
node _T_81 = and(_T_80, asSInt(UInt<1>(0h0)))
node _T_82 = asSInt(_T_81)
node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0)))
node _T_84 = or(_T_78, _T_83)
node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_86 = eq(_T_85, UInt<1>(0h0))
node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_88 = cvt(_T_87)
node _T_89 = and(_T_88, asSInt(UInt<1>(0h0)))
node _T_90 = asSInt(_T_89)
node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0)))
node _T_92 = or(_T_86, _T_91)
node _T_93 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_94 = eq(_T_93, UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<1>(0h0)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = or(_T_94, _T_99)
node _T_101 = and(_T_11, _T_24)
node _T_102 = and(_T_101, _T_37)
node _T_103 = and(_T_102, _T_50)
node _T_104 = and(_T_103, _T_63)
node _T_105 = and(_T_104, _T_76)
node _T_106 = and(_T_105, _T_84)
node _T_107 = and(_T_106, _T_92)
node _T_108 = and(_T_107, _T_100)
node _T_109 = asUInt(reset)
node _T_110 = eq(_T_109, UInt<1>(0h0))
when _T_110 :
node _T_111 = eq(_T_108, UInt<1>(0h0))
when _T_111 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_108, UInt<1>(0h1), "") : assert_1
node _T_112 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_112 :
node _T_113 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_114 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_115 = and(_T_113, _T_114)
node _T_116 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0)
node _T_117 = shr(io.in.a.bits.source, 2)
node _T_118 = eq(_T_117, UInt<1>(0h0))
node _T_119 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_120 = and(_T_118, _T_119)
node _T_121 = leq(uncommonBits_5, UInt<2>(0h3))
node _T_122 = and(_T_120, _T_121)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0)
node _T_123 = shr(io.in.a.bits.source, 2)
node _T_124 = eq(_T_123, UInt<1>(0h1))
node _T_125 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_126 = and(_T_124, _T_125)
node _T_127 = leq(uncommonBits_6, UInt<2>(0h3))
node _T_128 = and(_T_126, _T_127)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0)
node _T_129 = shr(io.in.a.bits.source, 2)
node _T_130 = eq(_T_129, UInt<2>(0h2))
node _T_131 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_132 = and(_T_130, _T_131)
node _T_133 = leq(uncommonBits_7, UInt<2>(0h3))
node _T_134 = and(_T_132, _T_133)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0)
node _T_135 = shr(io.in.a.bits.source, 2)
node _T_136 = eq(_T_135, UInt<2>(0h3))
node _T_137 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_138 = and(_T_136, _T_137)
node _T_139 = leq(uncommonBits_8, UInt<2>(0h3))
node _T_140 = and(_T_138, _T_139)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0)
node _T_141 = shr(io.in.a.bits.source, 2)
node _T_142 = eq(_T_141, UInt<4>(0h8))
node _T_143 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_144 = and(_T_142, _T_143)
node _T_145 = leq(uncommonBits_9, UInt<2>(0h2))
node _T_146 = and(_T_144, _T_145)
node _T_147 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_148 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_149 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_150 = or(_T_116, _T_122)
node _T_151 = or(_T_150, _T_128)
node _T_152 = or(_T_151, _T_134)
node _T_153 = or(_T_152, _T_140)
node _T_154 = or(_T_153, _T_146)
node _T_155 = or(_T_154, _T_147)
node _T_156 = or(_T_155, _T_148)
node _T_157 = or(_T_156, _T_149)
node _T_158 = and(_T_115, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_161 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_162 = cvt(_T_161)
node _T_163 = and(_T_162, asSInt(UInt<13>(0h1000)))
node _T_164 = asSInt(_T_163)
node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0)))
node _T_166 = and(_T_160, _T_165)
node _T_167 = or(UInt<1>(0h0), _T_166)
node _T_168 = and(_T_159, _T_167)
node _T_169 = asUInt(reset)
node _T_170 = eq(_T_169, UInt<1>(0h0))
when _T_170 :
node _T_171 = eq(_T_168, UInt<1>(0h0))
when _T_171 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_168, UInt<1>(0h1), "") : assert_2
node _T_172 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0)
node _T_173 = shr(io.in.a.bits.source, 2)
node _T_174 = eq(_T_173, UInt<1>(0h0))
node _T_175 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_176 = and(_T_174, _T_175)
node _T_177 = leq(uncommonBits_10, UInt<2>(0h3))
node _T_178 = and(_T_176, _T_177)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0)
node _T_179 = shr(io.in.a.bits.source, 2)
node _T_180 = eq(_T_179, UInt<1>(0h1))
node _T_181 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_182 = and(_T_180, _T_181)
node _T_183 = leq(uncommonBits_11, UInt<2>(0h3))
node _T_184 = and(_T_182, _T_183)
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_185 = shr(io.in.a.bits.source, 2)
node _T_186 = eq(_T_185, UInt<2>(0h2))
node _T_187 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_188 = and(_T_186, _T_187)
node _T_189 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_190 = and(_T_188, _T_189)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_191 = shr(io.in.a.bits.source, 2)
node _T_192 = eq(_T_191, UInt<2>(0h3))
node _T_193 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_194 = and(_T_192, _T_193)
node _T_195 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_196 = and(_T_194, _T_195)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_197 = shr(io.in.a.bits.source, 2)
node _T_198 = eq(_T_197, UInt<4>(0h8))
node _T_199 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_200 = and(_T_198, _T_199)
node _T_201 = leq(uncommonBits_14, UInt<2>(0h2))
node _T_202 = and(_T_200, _T_201)
node _T_203 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_204 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_205 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE : UInt<1>[9]
connect _WIRE[0], _T_172
connect _WIRE[1], _T_178
connect _WIRE[2], _T_184
connect _WIRE[3], _T_190
connect _WIRE[4], _T_196
connect _WIRE[5], _T_202
connect _WIRE[6], _T_203
connect _WIRE[7], _T_204
connect _WIRE[8], _T_205
node _T_206 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_207 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_208 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_209 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_210 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_211 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_212 = mux(_WIRE[5], _T_206, UInt<1>(0h0))
node _T_213 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_214 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_215 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_216 = or(_T_207, _T_208)
node _T_217 = or(_T_216, _T_209)
node _T_218 = or(_T_217, _T_210)
node _T_219 = or(_T_218, _T_211)
node _T_220 = or(_T_219, _T_212)
node _T_221 = or(_T_220, _T_213)
node _T_222 = or(_T_221, _T_214)
node _T_223 = or(_T_222, _T_215)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_223
node _T_224 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_225 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_226 = and(_T_224, _T_225)
node _T_227 = or(UInt<1>(0h0), _T_226)
node _T_228 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_229 = cvt(_T_228)
node _T_230 = and(_T_229, asSInt(UInt<13>(0h1000)))
node _T_231 = asSInt(_T_230)
node _T_232 = eq(_T_231, asSInt(UInt<1>(0h0)))
node _T_233 = and(_T_227, _T_232)
node _T_234 = or(UInt<1>(0h0), _T_233)
node _T_235 = and(_WIRE_1, _T_234)
node _T_236 = asUInt(reset)
node _T_237 = eq(_T_236, UInt<1>(0h0))
when _T_237 :
node _T_238 = eq(_T_235, UInt<1>(0h0))
when _T_238 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_235, UInt<1>(0h1), "") : assert_3
node _T_239 = asUInt(reset)
node _T_240 = eq(_T_239, UInt<1>(0h0))
when _T_240 :
node _T_241 = eq(source_ok, UInt<1>(0h0))
when _T_241 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_242 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_243 = asUInt(reset)
node _T_244 = eq(_T_243, UInt<1>(0h0))
when _T_244 :
node _T_245 = eq(_T_242, UInt<1>(0h0))
when _T_245 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_242, UInt<1>(0h1), "") : assert_5
node _T_246 = asUInt(reset)
node _T_247 = eq(_T_246, UInt<1>(0h0))
when _T_247 :
node _T_248 = eq(is_aligned, UInt<1>(0h0))
when _T_248 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_249 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_250 = asUInt(reset)
node _T_251 = eq(_T_250, UInt<1>(0h0))
when _T_251 :
node _T_252 = eq(_T_249, UInt<1>(0h0))
when _T_252 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_249, UInt<1>(0h1), "") : assert_7
node _T_253 = not(io.in.a.bits.mask)
node _T_254 = eq(_T_253, UInt<1>(0h0))
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(_T_254, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_254, UInt<1>(0h1), "") : assert_8
node _T_258 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_259 = asUInt(reset)
node _T_260 = eq(_T_259, UInt<1>(0h0))
when _T_260 :
node _T_261 = eq(_T_258, UInt<1>(0h0))
when _T_261 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_258, UInt<1>(0h1), "") : assert_9
node _T_262 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_262 :
node _T_263 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_264 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_265 = and(_T_263, _T_264)
node _T_266 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_267 = shr(io.in.a.bits.source, 2)
node _T_268 = eq(_T_267, UInt<1>(0h0))
node _T_269 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_270 = and(_T_268, _T_269)
node _T_271 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_272 = and(_T_270, _T_271)
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0)
node _T_273 = shr(io.in.a.bits.source, 2)
node _T_274 = eq(_T_273, UInt<1>(0h1))
node _T_275 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_276 = and(_T_274, _T_275)
node _T_277 = leq(uncommonBits_16, UInt<2>(0h3))
node _T_278 = and(_T_276, _T_277)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0)
node _T_279 = shr(io.in.a.bits.source, 2)
node _T_280 = eq(_T_279, UInt<2>(0h2))
node _T_281 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_282 = and(_T_280, _T_281)
node _T_283 = leq(uncommonBits_17, UInt<2>(0h3))
node _T_284 = and(_T_282, _T_283)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0)
node _T_285 = shr(io.in.a.bits.source, 2)
node _T_286 = eq(_T_285, UInt<2>(0h3))
node _T_287 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_288 = and(_T_286, _T_287)
node _T_289 = leq(uncommonBits_18, UInt<2>(0h3))
node _T_290 = and(_T_288, _T_289)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0)
node _T_291 = shr(io.in.a.bits.source, 2)
node _T_292 = eq(_T_291, UInt<4>(0h8))
node _T_293 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_294 = and(_T_292, _T_293)
node _T_295 = leq(uncommonBits_19, UInt<2>(0h2))
node _T_296 = and(_T_294, _T_295)
node _T_297 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_298 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_299 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_300 = or(_T_266, _T_272)
node _T_301 = or(_T_300, _T_278)
node _T_302 = or(_T_301, _T_284)
node _T_303 = or(_T_302, _T_290)
node _T_304 = or(_T_303, _T_296)
node _T_305 = or(_T_304, _T_297)
node _T_306 = or(_T_305, _T_298)
node _T_307 = or(_T_306, _T_299)
node _T_308 = and(_T_265, _T_307)
node _T_309 = or(UInt<1>(0h0), _T_308)
node _T_310 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_311 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_312 = cvt(_T_311)
node _T_313 = and(_T_312, asSInt(UInt<13>(0h1000)))
node _T_314 = asSInt(_T_313)
node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0)))
node _T_316 = and(_T_310, _T_315)
node _T_317 = or(UInt<1>(0h0), _T_316)
node _T_318 = and(_T_309, _T_317)
node _T_319 = asUInt(reset)
node _T_320 = eq(_T_319, UInt<1>(0h0))
when _T_320 :
node _T_321 = eq(_T_318, UInt<1>(0h0))
when _T_321 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_318, UInt<1>(0h1), "") : assert_10
node _T_322 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0)
node _T_323 = shr(io.in.a.bits.source, 2)
node _T_324 = eq(_T_323, UInt<1>(0h0))
node _T_325 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_326 = and(_T_324, _T_325)
node _T_327 = leq(uncommonBits_20, UInt<2>(0h3))
node _T_328 = and(_T_326, _T_327)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0)
node _T_329 = shr(io.in.a.bits.source, 2)
node _T_330 = eq(_T_329, UInt<1>(0h1))
node _T_331 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_332 = and(_T_330, _T_331)
node _T_333 = leq(uncommonBits_21, UInt<2>(0h3))
node _T_334 = and(_T_332, _T_333)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0)
node _T_335 = shr(io.in.a.bits.source, 2)
node _T_336 = eq(_T_335, UInt<2>(0h2))
node _T_337 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_338 = and(_T_336, _T_337)
node _T_339 = leq(uncommonBits_22, UInt<2>(0h3))
node _T_340 = and(_T_338, _T_339)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0)
node _T_341 = shr(io.in.a.bits.source, 2)
node _T_342 = eq(_T_341, UInt<2>(0h3))
node _T_343 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_344 = and(_T_342, _T_343)
node _T_345 = leq(uncommonBits_23, UInt<2>(0h3))
node _T_346 = and(_T_344, _T_345)
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_347 = shr(io.in.a.bits.source, 2)
node _T_348 = eq(_T_347, UInt<4>(0h8))
node _T_349 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_350 = and(_T_348, _T_349)
node _T_351 = leq(uncommonBits_24, UInt<2>(0h2))
node _T_352 = and(_T_350, _T_351)
node _T_353 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_354 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_355 = eq(io.in.a.bits.source, UInt<7>(0h40))
wire _WIRE_2 : UInt<1>[9]
connect _WIRE_2[0], _T_322
connect _WIRE_2[1], _T_328
connect _WIRE_2[2], _T_334
connect _WIRE_2[3], _T_340
connect _WIRE_2[4], _T_346
connect _WIRE_2[5], _T_352
connect _WIRE_2[6], _T_353
connect _WIRE_2[7], _T_354
connect _WIRE_2[8], _T_355
node _T_356 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_357 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_358 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_359 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_360 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_361 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_362 = mux(_WIRE_2[5], _T_356, UInt<1>(0h0))
node _T_363 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_364 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_365 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_366 = or(_T_357, _T_358)
node _T_367 = or(_T_366, _T_359)
node _T_368 = or(_T_367, _T_360)
node _T_369 = or(_T_368, _T_361)
node _T_370 = or(_T_369, _T_362)
node _T_371 = or(_T_370, _T_363)
node _T_372 = or(_T_371, _T_364)
node _T_373 = or(_T_372, _T_365)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_373
node _T_374 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_375 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_376 = and(_T_374, _T_375)
node _T_377 = or(UInt<1>(0h0), _T_376)
node _T_378 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_379 = cvt(_T_378)
node _T_380 = and(_T_379, asSInt(UInt<13>(0h1000)))
node _T_381 = asSInt(_T_380)
node _T_382 = eq(_T_381, asSInt(UInt<1>(0h0)))
node _T_383 = and(_T_377, _T_382)
node _T_384 = or(UInt<1>(0h0), _T_383)
node _T_385 = and(_WIRE_3, _T_384)
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_385, UInt<1>(0h1), "") : assert_11
node _T_389 = asUInt(reset)
node _T_390 = eq(_T_389, UInt<1>(0h0))
when _T_390 :
node _T_391 = eq(source_ok, UInt<1>(0h0))
when _T_391 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_392 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_393 = asUInt(reset)
node _T_394 = eq(_T_393, UInt<1>(0h0))
when _T_394 :
node _T_395 = eq(_T_392, UInt<1>(0h0))
when _T_395 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_392, UInt<1>(0h1), "") : assert_13
node _T_396 = asUInt(reset)
node _T_397 = eq(_T_396, UInt<1>(0h0))
when _T_397 :
node _T_398 = eq(is_aligned, UInt<1>(0h0))
when _T_398 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_399 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_400 = asUInt(reset)
node _T_401 = eq(_T_400, UInt<1>(0h0))
when _T_401 :
node _T_402 = eq(_T_399, UInt<1>(0h0))
when _T_402 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_399, UInt<1>(0h1), "") : assert_15
node _T_403 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_404 = asUInt(reset)
node _T_405 = eq(_T_404, UInt<1>(0h0))
when _T_405 :
node _T_406 = eq(_T_403, UInt<1>(0h0))
when _T_406 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_403, UInt<1>(0h1), "") : assert_16
node _T_407 = not(io.in.a.bits.mask)
node _T_408 = eq(_T_407, UInt<1>(0h0))
node _T_409 = asUInt(reset)
node _T_410 = eq(_T_409, UInt<1>(0h0))
when _T_410 :
node _T_411 = eq(_T_408, UInt<1>(0h0))
when _T_411 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_408, UInt<1>(0h1), "") : assert_17
node _T_412 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_413 = asUInt(reset)
node _T_414 = eq(_T_413, UInt<1>(0h0))
when _T_414 :
node _T_415 = eq(_T_412, UInt<1>(0h0))
when _T_415 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_412, UInt<1>(0h1), "") : assert_18
node _T_416 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_416 :
node _T_417 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_418 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_419 = and(_T_417, _T_418)
node _T_420 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_421 = shr(io.in.a.bits.source, 2)
node _T_422 = eq(_T_421, UInt<1>(0h0))
node _T_423 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_424 = and(_T_422, _T_423)
node _T_425 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_426 = and(_T_424, _T_425)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_427 = shr(io.in.a.bits.source, 2)
node _T_428 = eq(_T_427, UInt<1>(0h1))
node _T_429 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_430 = and(_T_428, _T_429)
node _T_431 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_432 = and(_T_430, _T_431)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_433 = shr(io.in.a.bits.source, 2)
node _T_434 = eq(_T_433, UInt<2>(0h2))
node _T_435 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_436 = and(_T_434, _T_435)
node _T_437 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_438 = and(_T_436, _T_437)
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0)
node _T_439 = shr(io.in.a.bits.source, 2)
node _T_440 = eq(_T_439, UInt<2>(0h3))
node _T_441 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_442 = and(_T_440, _T_441)
node _T_443 = leq(uncommonBits_28, UInt<2>(0h3))
node _T_444 = and(_T_442, _T_443)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0)
node _T_445 = shr(io.in.a.bits.source, 2)
node _T_446 = eq(_T_445, UInt<4>(0h8))
node _T_447 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_448 = and(_T_446, _T_447)
node _T_449 = leq(uncommonBits_29, UInt<2>(0h2))
node _T_450 = and(_T_448, _T_449)
node _T_451 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_452 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_453 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_454 = or(_T_420, _T_426)
node _T_455 = or(_T_454, _T_432)
node _T_456 = or(_T_455, _T_438)
node _T_457 = or(_T_456, _T_444)
node _T_458 = or(_T_457, _T_450)
node _T_459 = or(_T_458, _T_451)
node _T_460 = or(_T_459, _T_452)
node _T_461 = or(_T_460, _T_453)
node _T_462 = and(_T_419, _T_461)
node _T_463 = or(UInt<1>(0h0), _T_462)
node _T_464 = asUInt(reset)
node _T_465 = eq(_T_464, UInt<1>(0h0))
when _T_465 :
node _T_466 = eq(_T_463, UInt<1>(0h0))
when _T_466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_463, UInt<1>(0h1), "") : assert_19
node _T_467 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_468 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_469 = and(_T_467, _T_468)
node _T_470 = or(UInt<1>(0h0), _T_469)
node _T_471 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_472 = cvt(_T_471)
node _T_473 = and(_T_472, asSInt(UInt<13>(0h1000)))
node _T_474 = asSInt(_T_473)
node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0)))
node _T_476 = and(_T_470, _T_475)
node _T_477 = or(UInt<1>(0h0), _T_476)
node _T_478 = asUInt(reset)
node _T_479 = eq(_T_478, UInt<1>(0h0))
when _T_479 :
node _T_480 = eq(_T_477, UInt<1>(0h0))
when _T_480 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_477, UInt<1>(0h1), "") : assert_20
node _T_481 = asUInt(reset)
node _T_482 = eq(_T_481, UInt<1>(0h0))
when _T_482 :
node _T_483 = eq(source_ok, UInt<1>(0h0))
when _T_483 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_484 = asUInt(reset)
node _T_485 = eq(_T_484, UInt<1>(0h0))
when _T_485 :
node _T_486 = eq(is_aligned, UInt<1>(0h0))
when _T_486 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_487 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_488 = asUInt(reset)
node _T_489 = eq(_T_488, UInt<1>(0h0))
when _T_489 :
node _T_490 = eq(_T_487, UInt<1>(0h0))
when _T_490 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_487, UInt<1>(0h1), "") : assert_23
node _T_491 = eq(io.in.a.bits.mask, mask)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_491, UInt<1>(0h1), "") : assert_24
node _T_495 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_T_495, UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_495, UInt<1>(0h1), "") : assert_25
node _T_499 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_499 :
node _T_500 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_501 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_502 = and(_T_500, _T_501)
node _T_503 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0)
node _T_504 = shr(io.in.a.bits.source, 2)
node _T_505 = eq(_T_504, UInt<1>(0h0))
node _T_506 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_507 = and(_T_505, _T_506)
node _T_508 = leq(uncommonBits_30, UInt<2>(0h3))
node _T_509 = and(_T_507, _T_508)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0)
node _T_510 = shr(io.in.a.bits.source, 2)
node _T_511 = eq(_T_510, UInt<1>(0h1))
node _T_512 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_513 = and(_T_511, _T_512)
node _T_514 = leq(uncommonBits_31, UInt<2>(0h3))
node _T_515 = and(_T_513, _T_514)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0)
node _T_516 = shr(io.in.a.bits.source, 2)
node _T_517 = eq(_T_516, UInt<2>(0h2))
node _T_518 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_519 = and(_T_517, _T_518)
node _T_520 = leq(uncommonBits_32, UInt<2>(0h3))
node _T_521 = and(_T_519, _T_520)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0)
node _T_522 = shr(io.in.a.bits.source, 2)
node _T_523 = eq(_T_522, UInt<2>(0h3))
node _T_524 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_525 = and(_T_523, _T_524)
node _T_526 = leq(uncommonBits_33, UInt<2>(0h3))
node _T_527 = and(_T_525, _T_526)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0)
node _T_528 = shr(io.in.a.bits.source, 2)
node _T_529 = eq(_T_528, UInt<4>(0h8))
node _T_530 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_531 = and(_T_529, _T_530)
node _T_532 = leq(uncommonBits_34, UInt<2>(0h2))
node _T_533 = and(_T_531, _T_532)
node _T_534 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_535 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_536 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_537 = or(_T_503, _T_509)
node _T_538 = or(_T_537, _T_515)
node _T_539 = or(_T_538, _T_521)
node _T_540 = or(_T_539, _T_527)
node _T_541 = or(_T_540, _T_533)
node _T_542 = or(_T_541, _T_534)
node _T_543 = or(_T_542, _T_535)
node _T_544 = or(_T_543, _T_536)
node _T_545 = and(_T_502, _T_544)
node _T_546 = or(UInt<1>(0h0), _T_545)
node _T_547 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_548 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_549 = and(_T_547, _T_548)
node _T_550 = or(UInt<1>(0h0), _T_549)
node _T_551 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_552 = cvt(_T_551)
node _T_553 = and(_T_552, asSInt(UInt<13>(0h1000)))
node _T_554 = asSInt(_T_553)
node _T_555 = eq(_T_554, asSInt(UInt<1>(0h0)))
node _T_556 = and(_T_550, _T_555)
node _T_557 = or(UInt<1>(0h0), _T_556)
node _T_558 = and(_T_546, _T_557)
node _T_559 = asUInt(reset)
node _T_560 = eq(_T_559, UInt<1>(0h0))
when _T_560 :
node _T_561 = eq(_T_558, UInt<1>(0h0))
when _T_561 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_558, UInt<1>(0h1), "") : assert_26
node _T_562 = asUInt(reset)
node _T_563 = eq(_T_562, UInt<1>(0h0))
when _T_563 :
node _T_564 = eq(source_ok, UInt<1>(0h0))
when _T_564 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_565 = asUInt(reset)
node _T_566 = eq(_T_565, UInt<1>(0h0))
when _T_566 :
node _T_567 = eq(is_aligned, UInt<1>(0h0))
when _T_567 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_568 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_568, UInt<1>(0h1), "") : assert_29
node _T_572 = eq(io.in.a.bits.mask, mask)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_572, UInt<1>(0h1), "") : assert_30
node _T_576 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_576 :
node _T_577 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_578 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_579 = and(_T_577, _T_578)
node _T_580 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0)
node _T_581 = shr(io.in.a.bits.source, 2)
node _T_582 = eq(_T_581, UInt<1>(0h0))
node _T_583 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_584 = and(_T_582, _T_583)
node _T_585 = leq(uncommonBits_35, UInt<2>(0h3))
node _T_586 = and(_T_584, _T_585)
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_587 = shr(io.in.a.bits.source, 2)
node _T_588 = eq(_T_587, UInt<1>(0h1))
node _T_589 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_590 = and(_T_588, _T_589)
node _T_591 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_592 = and(_T_590, _T_591)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_593 = shr(io.in.a.bits.source, 2)
node _T_594 = eq(_T_593, UInt<2>(0h2))
node _T_595 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_596 = and(_T_594, _T_595)
node _T_597 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_598 = and(_T_596, _T_597)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_599 = shr(io.in.a.bits.source, 2)
node _T_600 = eq(_T_599, UInt<2>(0h3))
node _T_601 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_602 = and(_T_600, _T_601)
node _T_603 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_604 = and(_T_602, _T_603)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_605 = shr(io.in.a.bits.source, 2)
node _T_606 = eq(_T_605, UInt<4>(0h8))
node _T_607 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_608 = and(_T_606, _T_607)
node _T_609 = leq(uncommonBits_39, UInt<2>(0h2))
node _T_610 = and(_T_608, _T_609)
node _T_611 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_612 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_613 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_614 = or(_T_580, _T_586)
node _T_615 = or(_T_614, _T_592)
node _T_616 = or(_T_615, _T_598)
node _T_617 = or(_T_616, _T_604)
node _T_618 = or(_T_617, _T_610)
node _T_619 = or(_T_618, _T_611)
node _T_620 = or(_T_619, _T_612)
node _T_621 = or(_T_620, _T_613)
node _T_622 = and(_T_579, _T_621)
node _T_623 = or(UInt<1>(0h0), _T_622)
node _T_624 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_625 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_626 = and(_T_624, _T_625)
node _T_627 = or(UInt<1>(0h0), _T_626)
node _T_628 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_629 = cvt(_T_628)
node _T_630 = and(_T_629, asSInt(UInt<13>(0h1000)))
node _T_631 = asSInt(_T_630)
node _T_632 = eq(_T_631, asSInt(UInt<1>(0h0)))
node _T_633 = and(_T_627, _T_632)
node _T_634 = or(UInt<1>(0h0), _T_633)
node _T_635 = and(_T_623, _T_634)
node _T_636 = asUInt(reset)
node _T_637 = eq(_T_636, UInt<1>(0h0))
when _T_637 :
node _T_638 = eq(_T_635, UInt<1>(0h0))
when _T_638 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_635, UInt<1>(0h1), "") : assert_31
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(source_ok, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_642 = asUInt(reset)
node _T_643 = eq(_T_642, UInt<1>(0h0))
when _T_643 :
node _T_644 = eq(is_aligned, UInt<1>(0h0))
when _T_644 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_645 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_646 = asUInt(reset)
node _T_647 = eq(_T_646, UInt<1>(0h0))
when _T_647 :
node _T_648 = eq(_T_645, UInt<1>(0h0))
when _T_648 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_645, UInt<1>(0h1), "") : assert_34
node _T_649 = not(mask)
node _T_650 = and(io.in.a.bits.mask, _T_649)
node _T_651 = eq(_T_650, UInt<1>(0h0))
node _T_652 = asUInt(reset)
node _T_653 = eq(_T_652, UInt<1>(0h0))
when _T_653 :
node _T_654 = eq(_T_651, UInt<1>(0h0))
when _T_654 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_651, UInt<1>(0h1), "") : assert_35
node _T_655 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_655 :
node _T_656 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_657 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_658 = and(_T_656, _T_657)
node _T_659 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0)
node _T_660 = shr(io.in.a.bits.source, 2)
node _T_661 = eq(_T_660, UInt<1>(0h0))
node _T_662 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_663 = and(_T_661, _T_662)
node _T_664 = leq(uncommonBits_40, UInt<2>(0h3))
node _T_665 = and(_T_663, _T_664)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0)
node _T_666 = shr(io.in.a.bits.source, 2)
node _T_667 = eq(_T_666, UInt<1>(0h1))
node _T_668 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_669 = and(_T_667, _T_668)
node _T_670 = leq(uncommonBits_41, UInt<2>(0h3))
node _T_671 = and(_T_669, _T_670)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0)
node _T_672 = shr(io.in.a.bits.source, 2)
node _T_673 = eq(_T_672, UInt<2>(0h2))
node _T_674 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_675 = and(_T_673, _T_674)
node _T_676 = leq(uncommonBits_42, UInt<2>(0h3))
node _T_677 = and(_T_675, _T_676)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0)
node _T_678 = shr(io.in.a.bits.source, 2)
node _T_679 = eq(_T_678, UInt<2>(0h3))
node _T_680 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_681 = and(_T_679, _T_680)
node _T_682 = leq(uncommonBits_43, UInt<2>(0h3))
node _T_683 = and(_T_681, _T_682)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0)
node _T_684 = shr(io.in.a.bits.source, 2)
node _T_685 = eq(_T_684, UInt<4>(0h8))
node _T_686 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_687 = and(_T_685, _T_686)
node _T_688 = leq(uncommonBits_44, UInt<2>(0h2))
node _T_689 = and(_T_687, _T_688)
node _T_690 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_691 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_692 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_693 = or(_T_659, _T_665)
node _T_694 = or(_T_693, _T_671)
node _T_695 = or(_T_694, _T_677)
node _T_696 = or(_T_695, _T_683)
node _T_697 = or(_T_696, _T_689)
node _T_698 = or(_T_697, _T_690)
node _T_699 = or(_T_698, _T_691)
node _T_700 = or(_T_699, _T_692)
node _T_701 = and(_T_658, _T_700)
node _T_702 = or(UInt<1>(0h0), _T_701)
node _T_703 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_704 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_705 = cvt(_T_704)
node _T_706 = and(_T_705, asSInt(UInt<13>(0h1000)))
node _T_707 = asSInt(_T_706)
node _T_708 = eq(_T_707, asSInt(UInt<1>(0h0)))
node _T_709 = and(_T_703, _T_708)
node _T_710 = or(UInt<1>(0h0), _T_709)
node _T_711 = and(_T_702, _T_710)
node _T_712 = asUInt(reset)
node _T_713 = eq(_T_712, UInt<1>(0h0))
when _T_713 :
node _T_714 = eq(_T_711, UInt<1>(0h0))
when _T_714 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_711, UInt<1>(0h1), "") : assert_36
node _T_715 = asUInt(reset)
node _T_716 = eq(_T_715, UInt<1>(0h0))
when _T_716 :
node _T_717 = eq(source_ok, UInt<1>(0h0))
when _T_717 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_718 = asUInt(reset)
node _T_719 = eq(_T_718, UInt<1>(0h0))
when _T_719 :
node _T_720 = eq(is_aligned, UInt<1>(0h0))
when _T_720 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_721 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_722 = asUInt(reset)
node _T_723 = eq(_T_722, UInt<1>(0h0))
when _T_723 :
node _T_724 = eq(_T_721, UInt<1>(0h0))
when _T_724 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_721, UInt<1>(0h1), "") : assert_39
node _T_725 = eq(io.in.a.bits.mask, mask)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_725, UInt<1>(0h1), "") : assert_40
node _T_729 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_729 :
node _T_730 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_731 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_732 = and(_T_730, _T_731)
node _T_733 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0)
node _T_734 = shr(io.in.a.bits.source, 2)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_737 = and(_T_735, _T_736)
node _T_738 = leq(uncommonBits_45, UInt<2>(0h3))
node _T_739 = and(_T_737, _T_738)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0)
node _T_740 = shr(io.in.a.bits.source, 2)
node _T_741 = eq(_T_740, UInt<1>(0h1))
node _T_742 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_743 = and(_T_741, _T_742)
node _T_744 = leq(uncommonBits_46, UInt<2>(0h3))
node _T_745 = and(_T_743, _T_744)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0)
node _T_746 = shr(io.in.a.bits.source, 2)
node _T_747 = eq(_T_746, UInt<2>(0h2))
node _T_748 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_749 = and(_T_747, _T_748)
node _T_750 = leq(uncommonBits_47, UInt<2>(0h3))
node _T_751 = and(_T_749, _T_750)
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_752 = shr(io.in.a.bits.source, 2)
node _T_753 = eq(_T_752, UInt<2>(0h3))
node _T_754 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_755 = and(_T_753, _T_754)
node _T_756 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_757 = and(_T_755, _T_756)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_758 = shr(io.in.a.bits.source, 2)
node _T_759 = eq(_T_758, UInt<4>(0h8))
node _T_760 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_761 = and(_T_759, _T_760)
node _T_762 = leq(uncommonBits_49, UInt<2>(0h2))
node _T_763 = and(_T_761, _T_762)
node _T_764 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_765 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_766 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_767 = or(_T_733, _T_739)
node _T_768 = or(_T_767, _T_745)
node _T_769 = or(_T_768, _T_751)
node _T_770 = or(_T_769, _T_757)
node _T_771 = or(_T_770, _T_763)
node _T_772 = or(_T_771, _T_764)
node _T_773 = or(_T_772, _T_765)
node _T_774 = or(_T_773, _T_766)
node _T_775 = and(_T_732, _T_774)
node _T_776 = or(UInt<1>(0h0), _T_775)
node _T_777 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_778 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_779 = cvt(_T_778)
node _T_780 = and(_T_779, asSInt(UInt<13>(0h1000)))
node _T_781 = asSInt(_T_780)
node _T_782 = eq(_T_781, asSInt(UInt<1>(0h0)))
node _T_783 = and(_T_777, _T_782)
node _T_784 = or(UInt<1>(0h0), _T_783)
node _T_785 = and(_T_776, _T_784)
node _T_786 = asUInt(reset)
node _T_787 = eq(_T_786, UInt<1>(0h0))
when _T_787 :
node _T_788 = eq(_T_785, UInt<1>(0h0))
when _T_788 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_785, UInt<1>(0h1), "") : assert_41
node _T_789 = asUInt(reset)
node _T_790 = eq(_T_789, UInt<1>(0h0))
when _T_790 :
node _T_791 = eq(source_ok, UInt<1>(0h0))
when _T_791 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_792 = asUInt(reset)
node _T_793 = eq(_T_792, UInt<1>(0h0))
when _T_793 :
node _T_794 = eq(is_aligned, UInt<1>(0h0))
when _T_794 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_795 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_796 = asUInt(reset)
node _T_797 = eq(_T_796, UInt<1>(0h0))
when _T_797 :
node _T_798 = eq(_T_795, UInt<1>(0h0))
when _T_798 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_795, UInt<1>(0h1), "") : assert_44
node _T_799 = eq(io.in.a.bits.mask, mask)
node _T_800 = asUInt(reset)
node _T_801 = eq(_T_800, UInt<1>(0h0))
when _T_801 :
node _T_802 = eq(_T_799, UInt<1>(0h0))
when _T_802 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_799, UInt<1>(0h1), "") : assert_45
node _T_803 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_803 :
node _T_804 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_805 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_806 = and(_T_804, _T_805)
node _T_807 = eq(io.in.a.bits.source, UInt<5>(0h10))
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_808 = shr(io.in.a.bits.source, 2)
node _T_809 = eq(_T_808, UInt<1>(0h0))
node _T_810 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_811 = and(_T_809, _T_810)
node _T_812 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_813 = and(_T_811, _T_812)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_814 = shr(io.in.a.bits.source, 2)
node _T_815 = eq(_T_814, UInt<1>(0h1))
node _T_816 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_817 = and(_T_815, _T_816)
node _T_818 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_819 = and(_T_817, _T_818)
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0)
node _T_820 = shr(io.in.a.bits.source, 2)
node _T_821 = eq(_T_820, UInt<2>(0h2))
node _T_822 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_823 = and(_T_821, _T_822)
node _T_824 = leq(uncommonBits_52, UInt<2>(0h3))
node _T_825 = and(_T_823, _T_824)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0)
node _T_826 = shr(io.in.a.bits.source, 2)
node _T_827 = eq(_T_826, UInt<2>(0h3))
node _T_828 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_829 = and(_T_827, _T_828)
node _T_830 = leq(uncommonBits_53, UInt<2>(0h3))
node _T_831 = and(_T_829, _T_830)
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0)
node _T_832 = shr(io.in.a.bits.source, 2)
node _T_833 = eq(_T_832, UInt<4>(0h8))
node _T_834 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_835 = and(_T_833, _T_834)
node _T_836 = leq(uncommonBits_54, UInt<2>(0h2))
node _T_837 = and(_T_835, _T_836)
node _T_838 = eq(io.in.a.bits.source, UInt<6>(0h23))
node _T_839 = eq(io.in.a.bits.source, UInt<6>(0h24))
node _T_840 = eq(io.in.a.bits.source, UInt<7>(0h40))
node _T_841 = or(_T_807, _T_813)
node _T_842 = or(_T_841, _T_819)
node _T_843 = or(_T_842, _T_825)
node _T_844 = or(_T_843, _T_831)
node _T_845 = or(_T_844, _T_837)
node _T_846 = or(_T_845, _T_838)
node _T_847 = or(_T_846, _T_839)
node _T_848 = or(_T_847, _T_840)
node _T_849 = and(_T_806, _T_848)
node _T_850 = or(UInt<1>(0h0), _T_849)
node _T_851 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_852 = xor(io.in.a.bits.address, UInt<21>(0h110000))
node _T_853 = cvt(_T_852)
node _T_854 = and(_T_853, asSInt(UInt<13>(0h1000)))
node _T_855 = asSInt(_T_854)
node _T_856 = eq(_T_855, asSInt(UInt<1>(0h0)))
node _T_857 = and(_T_851, _T_856)
node _T_858 = or(UInt<1>(0h0), _T_857)
node _T_859 = and(_T_850, _T_858)
node _T_860 = asUInt(reset)
node _T_861 = eq(_T_860, UInt<1>(0h0))
when _T_861 :
node _T_862 = eq(_T_859, UInt<1>(0h0))
when _T_862 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_859, UInt<1>(0h1), "") : assert_46
node _T_863 = asUInt(reset)
node _T_864 = eq(_T_863, UInt<1>(0h0))
when _T_864 :
node _T_865 = eq(source_ok, UInt<1>(0h0))
when _T_865 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_866 = asUInt(reset)
node _T_867 = eq(_T_866, UInt<1>(0h0))
when _T_867 :
node _T_868 = eq(is_aligned, UInt<1>(0h0))
when _T_868 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_869 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_870 = asUInt(reset)
node _T_871 = eq(_T_870, UInt<1>(0h0))
when _T_871 :
node _T_872 = eq(_T_869, UInt<1>(0h0))
when _T_872 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_869, UInt<1>(0h1), "") : assert_49
node _T_873 = eq(io.in.a.bits.mask, mask)
node _T_874 = asUInt(reset)
node _T_875 = eq(_T_874, UInt<1>(0h0))
when _T_875 :
node _T_876 = eq(_T_873, UInt<1>(0h0))
when _T_876 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_873, UInt<1>(0h1), "") : assert_50
node _T_877 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_878 = asUInt(reset)
node _T_879 = eq(_T_878, UInt<1>(0h0))
when _T_879 :
node _T_880 = eq(_T_877, UInt<1>(0h0))
when _T_880 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_877, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_881 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_882 = asUInt(reset)
node _T_883 = eq(_T_882, UInt<1>(0h0))
when _T_883 :
node _T_884 = eq(_T_881, UInt<1>(0h0))
when _T_884 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_881, UInt<1>(0h1), "") : assert_52
node _source_ok_T_41 = eq(io.in.d.bits.source, UInt<5>(0h10))
node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0)
node _source_ok_T_42 = shr(io.in.d.bits.source, 2)
node _source_ok_T_43 = eq(_source_ok_T_42, UInt<1>(0h0))
node _source_ok_T_44 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44)
node _source_ok_T_46 = leq(source_ok_uncommonBits_5, UInt<2>(0h3))
node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46)
node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0)
node _source_ok_T_48 = shr(io.in.d.bits.source, 2)
node _source_ok_T_49 = eq(_source_ok_T_48, UInt<1>(0h1))
node _source_ok_T_50 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50)
node _source_ok_T_52 = leq(source_ok_uncommonBits_6, UInt<2>(0h3))
node _source_ok_T_53 = and(_source_ok_T_51, _source_ok_T_52)
node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0)
node _source_ok_T_54 = shr(io.in.d.bits.source, 2)
node _source_ok_T_55 = eq(_source_ok_T_54, UInt<2>(0h2))
node _source_ok_T_56 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56)
node _source_ok_T_58 = leq(source_ok_uncommonBits_7, UInt<2>(0h3))
node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58)
node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0)
node _source_ok_T_60 = shr(io.in.d.bits.source, 2)
node _source_ok_T_61 = eq(_source_ok_T_60, UInt<2>(0h3))
node _source_ok_T_62 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62)
node _source_ok_T_64 = leq(source_ok_uncommonBits_8, UInt<2>(0h3))
node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64)
node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0)
node _source_ok_T_66 = shr(io.in.d.bits.source, 2)
node _source_ok_T_67 = eq(_source_ok_T_66, UInt<4>(0h8))
node _source_ok_T_68 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68)
node _source_ok_T_70 = leq(source_ok_uncommonBits_9, UInt<2>(0h2))
node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70)
node _source_ok_T_72 = eq(io.in.d.bits.source, UInt<6>(0h23))
node _source_ok_T_73 = eq(io.in.d.bits.source, UInt<6>(0h24))
node _source_ok_T_74 = eq(io.in.d.bits.source, UInt<7>(0h40))
wire _source_ok_WIRE_1 : UInt<1>[9]
connect _source_ok_WIRE_1[0], _source_ok_T_41
connect _source_ok_WIRE_1[1], _source_ok_T_47
connect _source_ok_WIRE_1[2], _source_ok_T_53
connect _source_ok_WIRE_1[3], _source_ok_T_59
connect _source_ok_WIRE_1[4], _source_ok_T_65
connect _source_ok_WIRE_1[5], _source_ok_T_71
connect _source_ok_WIRE_1[6], _source_ok_T_72
connect _source_ok_WIRE_1[7], _source_ok_T_73
connect _source_ok_WIRE_1[8], _source_ok_T_74
node _source_ok_T_75 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE_1[2])
node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE_1[3])
node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE_1[4])
node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[5])
node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[6])
node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[7])
node source_ok_1 = or(_source_ok_T_81, _source_ok_WIRE_1[8])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_885 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_885 :
node _T_886 = asUInt(reset)
node _T_887 = eq(_T_886, UInt<1>(0h0))
when _T_887 :
node _T_888 = eq(source_ok_1, UInt<1>(0h0))
when _T_888 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_889 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_890 = asUInt(reset)
node _T_891 = eq(_T_890, UInt<1>(0h0))
when _T_891 :
node _T_892 = eq(_T_889, UInt<1>(0h0))
when _T_892 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_889, UInt<1>(0h1), "") : assert_54
node _T_893 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_894 = asUInt(reset)
node _T_895 = eq(_T_894, UInt<1>(0h0))
when _T_895 :
node _T_896 = eq(_T_893, UInt<1>(0h0))
when _T_896 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_893, UInt<1>(0h1), "") : assert_55
node _T_897 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_898 = asUInt(reset)
node _T_899 = eq(_T_898, UInt<1>(0h0))
when _T_899 :
node _T_900 = eq(_T_897, UInt<1>(0h0))
when _T_900 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_897, UInt<1>(0h1), "") : assert_56
node _T_901 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_902 = asUInt(reset)
node _T_903 = eq(_T_902, UInt<1>(0h0))
when _T_903 :
node _T_904 = eq(_T_901, UInt<1>(0h0))
when _T_904 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_901, UInt<1>(0h1), "") : assert_57
node _T_905 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_905 :
node _T_906 = asUInt(reset)
node _T_907 = eq(_T_906, UInt<1>(0h0))
when _T_907 :
node _T_908 = eq(source_ok_1, UInt<1>(0h0))
when _T_908 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_909 = asUInt(reset)
node _T_910 = eq(_T_909, UInt<1>(0h0))
when _T_910 :
node _T_911 = eq(sink_ok, UInt<1>(0h0))
when _T_911 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_912 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_913 = asUInt(reset)
node _T_914 = eq(_T_913, UInt<1>(0h0))
when _T_914 :
node _T_915 = eq(_T_912, UInt<1>(0h0))
when _T_915 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_912, UInt<1>(0h1), "") : assert_60
node _T_916 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_917 = asUInt(reset)
node _T_918 = eq(_T_917, UInt<1>(0h0))
when _T_918 :
node _T_919 = eq(_T_916, UInt<1>(0h0))
when _T_919 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_916, UInt<1>(0h1), "") : assert_61
node _T_920 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_921 = asUInt(reset)
node _T_922 = eq(_T_921, UInt<1>(0h0))
when _T_922 :
node _T_923 = eq(_T_920, UInt<1>(0h0))
when _T_923 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_920, UInt<1>(0h1), "") : assert_62
node _T_924 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_925 = asUInt(reset)
node _T_926 = eq(_T_925, UInt<1>(0h0))
when _T_926 :
node _T_927 = eq(_T_924, UInt<1>(0h0))
when _T_927 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_924, UInt<1>(0h1), "") : assert_63
node _T_928 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_929 = or(UInt<1>(0h0), _T_928)
node _T_930 = asUInt(reset)
node _T_931 = eq(_T_930, UInt<1>(0h0))
when _T_931 :
node _T_932 = eq(_T_929, UInt<1>(0h0))
when _T_932 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_929, UInt<1>(0h1), "") : assert_64
node _T_933 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_933 :
node _T_934 = asUInt(reset)
node _T_935 = eq(_T_934, UInt<1>(0h0))
when _T_935 :
node _T_936 = eq(source_ok_1, UInt<1>(0h0))
when _T_936 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_937 = asUInt(reset)
node _T_938 = eq(_T_937, UInt<1>(0h0))
when _T_938 :
node _T_939 = eq(sink_ok, UInt<1>(0h0))
when _T_939 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_940 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_941 = asUInt(reset)
node _T_942 = eq(_T_941, UInt<1>(0h0))
when _T_942 :
node _T_943 = eq(_T_940, UInt<1>(0h0))
when _T_943 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_940, UInt<1>(0h1), "") : assert_67
node _T_944 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_945 = asUInt(reset)
node _T_946 = eq(_T_945, UInt<1>(0h0))
when _T_946 :
node _T_947 = eq(_T_944, UInt<1>(0h0))
when _T_947 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_944, UInt<1>(0h1), "") : assert_68
node _T_948 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_949 = asUInt(reset)
node _T_950 = eq(_T_949, UInt<1>(0h0))
when _T_950 :
node _T_951 = eq(_T_948, UInt<1>(0h0))
when _T_951 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_948, UInt<1>(0h1), "") : assert_69
node _T_952 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_953 = or(_T_952, io.in.d.bits.corrupt)
node _T_954 = asUInt(reset)
node _T_955 = eq(_T_954, UInt<1>(0h0))
when _T_955 :
node _T_956 = eq(_T_953, UInt<1>(0h0))
when _T_956 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_953, UInt<1>(0h1), "") : assert_70
node _T_957 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_958 = or(UInt<1>(0h0), _T_957)
node _T_959 = asUInt(reset)
node _T_960 = eq(_T_959, UInt<1>(0h0))
when _T_960 :
node _T_961 = eq(_T_958, UInt<1>(0h0))
when _T_961 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_958, UInt<1>(0h1), "") : assert_71
node _T_962 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_962 :
node _T_963 = asUInt(reset)
node _T_964 = eq(_T_963, UInt<1>(0h0))
when _T_964 :
node _T_965 = eq(source_ok_1, UInt<1>(0h0))
when _T_965 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_966 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_967 = asUInt(reset)
node _T_968 = eq(_T_967, UInt<1>(0h0))
when _T_968 :
node _T_969 = eq(_T_966, UInt<1>(0h0))
when _T_969 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_966, UInt<1>(0h1), "") : assert_73
node _T_970 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_971 = asUInt(reset)
node _T_972 = eq(_T_971, UInt<1>(0h0))
when _T_972 :
node _T_973 = eq(_T_970, UInt<1>(0h0))
when _T_973 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_970, UInt<1>(0h1), "") : assert_74
node _T_974 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_975 = or(UInt<1>(0h0), _T_974)
node _T_976 = asUInt(reset)
node _T_977 = eq(_T_976, UInt<1>(0h0))
when _T_977 :
node _T_978 = eq(_T_975, UInt<1>(0h0))
when _T_978 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_975, UInt<1>(0h1), "") : assert_75
node _T_979 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_979 :
node _T_980 = asUInt(reset)
node _T_981 = eq(_T_980, UInt<1>(0h0))
when _T_981 :
node _T_982 = eq(source_ok_1, UInt<1>(0h0))
when _T_982 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_983 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_984 = asUInt(reset)
node _T_985 = eq(_T_984, UInt<1>(0h0))
when _T_985 :
node _T_986 = eq(_T_983, UInt<1>(0h0))
when _T_986 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_983, UInt<1>(0h1), "") : assert_77
node _T_987 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_988 = or(_T_987, io.in.d.bits.corrupt)
node _T_989 = asUInt(reset)
node _T_990 = eq(_T_989, UInt<1>(0h0))
when _T_990 :
node _T_991 = eq(_T_988, UInt<1>(0h0))
when _T_991 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_988, UInt<1>(0h1), "") : assert_78
node _T_992 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_993 = or(UInt<1>(0h0), _T_992)
node _T_994 = asUInt(reset)
node _T_995 = eq(_T_994, UInt<1>(0h0))
when _T_995 :
node _T_996 = eq(_T_993, UInt<1>(0h0))
when _T_996 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_993, UInt<1>(0h1), "") : assert_79
node _T_997 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_997 :
node _T_998 = asUInt(reset)
node _T_999 = eq(_T_998, UInt<1>(0h0))
when _T_999 :
node _T_1000 = eq(source_ok_1, UInt<1>(0h0))
when _T_1000 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1001 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1002 = asUInt(reset)
node _T_1003 = eq(_T_1002, UInt<1>(0h0))
when _T_1003 :
node _T_1004 = eq(_T_1001, UInt<1>(0h0))
when _T_1004 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1001, UInt<1>(0h1), "") : assert_81
node _T_1005 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1006 = asUInt(reset)
node _T_1007 = eq(_T_1006, UInt<1>(0h0))
when _T_1007 :
node _T_1008 = eq(_T_1005, UInt<1>(0h0))
when _T_1008 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1005, UInt<1>(0h1), "") : assert_82
node _T_1009 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1010 = or(UInt<1>(0h0), _T_1009)
node _T_1011 = asUInt(reset)
node _T_1012 = eq(_T_1011, UInt<1>(0h0))
when _T_1012 :
node _T_1013 = eq(_T_1010, UInt<1>(0h0))
when _T_1013 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1010, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<21>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1014 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1015 = asUInt(reset)
node _T_1016 = eq(_T_1015, UInt<1>(0h0))
when _T_1016 :
node _T_1017 = eq(_T_1014, UInt<1>(0h0))
when _T_1017 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1014, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<21>(0h0)
connect _WIRE_6.bits.source, UInt<7>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1018 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1019 = asUInt(reset)
node _T_1020 = eq(_T_1019, UInt<1>(0h0))
when _T_1020 :
node _T_1021 = eq(_T_1018, UInt<1>(0h0))
when _T_1021 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1018, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1022 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1023 = asUInt(reset)
node _T_1024 = eq(_T_1023, UInt<1>(0h0))
when _T_1024 :
node _T_1025 = eq(_T_1022, UInt<1>(0h0))
when _T_1025 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1022, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1026 = eq(a_first, UInt<1>(0h0))
node _T_1027 = and(io.in.a.valid, _T_1026)
when _T_1027 :
node _T_1028 = eq(io.in.a.bits.opcode, opcode)
node _T_1029 = asUInt(reset)
node _T_1030 = eq(_T_1029, UInt<1>(0h0))
when _T_1030 :
node _T_1031 = eq(_T_1028, UInt<1>(0h0))
when _T_1031 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1028, UInt<1>(0h1), "") : assert_87
node _T_1032 = eq(io.in.a.bits.param, param)
node _T_1033 = asUInt(reset)
node _T_1034 = eq(_T_1033, UInt<1>(0h0))
when _T_1034 :
node _T_1035 = eq(_T_1032, UInt<1>(0h0))
when _T_1035 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1032, UInt<1>(0h1), "") : assert_88
node _T_1036 = eq(io.in.a.bits.size, size)
node _T_1037 = asUInt(reset)
node _T_1038 = eq(_T_1037, UInt<1>(0h0))
when _T_1038 :
node _T_1039 = eq(_T_1036, UInt<1>(0h0))
when _T_1039 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1036, UInt<1>(0h1), "") : assert_89
node _T_1040 = eq(io.in.a.bits.source, source)
node _T_1041 = asUInt(reset)
node _T_1042 = eq(_T_1041, UInt<1>(0h0))
when _T_1042 :
node _T_1043 = eq(_T_1040, UInt<1>(0h0))
when _T_1043 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1040, UInt<1>(0h1), "") : assert_90
node _T_1044 = eq(io.in.a.bits.address, address)
node _T_1045 = asUInt(reset)
node _T_1046 = eq(_T_1045, UInt<1>(0h0))
when _T_1046 :
node _T_1047 = eq(_T_1044, UInt<1>(0h0))
when _T_1047 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1044, UInt<1>(0h1), "") : assert_91
node _T_1048 = and(io.in.a.ready, io.in.a.valid)
node _T_1049 = and(_T_1048, a_first)
when _T_1049 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1050 = eq(d_first, UInt<1>(0h0))
node _T_1051 = and(io.in.d.valid, _T_1050)
when _T_1051 :
node _T_1052 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1053 = asUInt(reset)
node _T_1054 = eq(_T_1053, UInt<1>(0h0))
when _T_1054 :
node _T_1055 = eq(_T_1052, UInt<1>(0h0))
when _T_1055 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1052, UInt<1>(0h1), "") : assert_92
node _T_1056 = eq(io.in.d.bits.param, param_1)
node _T_1057 = asUInt(reset)
node _T_1058 = eq(_T_1057, UInt<1>(0h0))
when _T_1058 :
node _T_1059 = eq(_T_1056, UInt<1>(0h0))
when _T_1059 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1056, UInt<1>(0h1), "") : assert_93
node _T_1060 = eq(io.in.d.bits.size, size_1)
node _T_1061 = asUInt(reset)
node _T_1062 = eq(_T_1061, UInt<1>(0h0))
when _T_1062 :
node _T_1063 = eq(_T_1060, UInt<1>(0h0))
when _T_1063 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1060, UInt<1>(0h1), "") : assert_94
node _T_1064 = eq(io.in.d.bits.source, source_1)
node _T_1065 = asUInt(reset)
node _T_1066 = eq(_T_1065, UInt<1>(0h0))
when _T_1066 :
node _T_1067 = eq(_T_1064, UInt<1>(0h0))
when _T_1067 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1064, UInt<1>(0h1), "") : assert_95
node _T_1068 = eq(io.in.d.bits.sink, sink)
node _T_1069 = asUInt(reset)
node _T_1070 = eq(_T_1069, UInt<1>(0h0))
when _T_1070 :
node _T_1071 = eq(_T_1068, UInt<1>(0h0))
when _T_1071 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1068, UInt<1>(0h1), "") : assert_96
node _T_1072 = eq(io.in.d.bits.denied, denied)
node _T_1073 = asUInt(reset)
node _T_1074 = eq(_T_1073, UInt<1>(0h0))
when _T_1074 :
node _T_1075 = eq(_T_1072, UInt<1>(0h0))
when _T_1075 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1072, UInt<1>(0h1), "") : assert_97
node _T_1076 = and(io.in.d.ready, io.in.d.valid)
node _T_1077 = and(_T_1076, d_first)
when _T_1077 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<65>
connect a_set, UInt<65>(0h0)
wire a_set_wo_ready : UInt<65>
connect a_set_wo_ready, UInt<65>(0h0)
wire a_opcodes_set : UInt<260>
connect a_opcodes_set, UInt<260>(0h0)
wire a_sizes_set : UInt<260>
connect a_sizes_set, UInt<260>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1078 = and(io.in.a.valid, a_first_1)
node _T_1079 = and(_T_1078, UInt<1>(0h1))
when _T_1079 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1080 = and(io.in.a.ready, io.in.a.valid)
node _T_1081 = and(_T_1080, a_first_1)
node _T_1082 = and(_T_1081, UInt<1>(0h1))
when _T_1082 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1083 = dshr(inflight, io.in.a.bits.source)
node _T_1084 = bits(_T_1083, 0, 0)
node _T_1085 = eq(_T_1084, UInt<1>(0h0))
node _T_1086 = asUInt(reset)
node _T_1087 = eq(_T_1086, UInt<1>(0h0))
when _T_1087 :
node _T_1088 = eq(_T_1085, UInt<1>(0h0))
when _T_1088 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1085, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<65>
connect d_clr, UInt<65>(0h0)
wire d_clr_wo_ready : UInt<65>
connect d_clr_wo_ready, UInt<65>(0h0)
wire d_opcodes_clr : UInt<260>
connect d_opcodes_clr, UInt<260>(0h0)
wire d_sizes_clr : UInt<260>
connect d_sizes_clr, UInt<260>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1089 = and(io.in.d.valid, d_first_1)
node _T_1090 = and(_T_1089, UInt<1>(0h1))
node _T_1091 = eq(d_release_ack, UInt<1>(0h0))
node _T_1092 = and(_T_1090, _T_1091)
when _T_1092 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1093 = and(io.in.d.ready, io.in.d.valid)
node _T_1094 = and(_T_1093, d_first_1)
node _T_1095 = and(_T_1094, UInt<1>(0h1))
node _T_1096 = eq(d_release_ack, UInt<1>(0h0))
node _T_1097 = and(_T_1095, _T_1096)
when _T_1097 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1098 = and(io.in.d.valid, d_first_1)
node _T_1099 = and(_T_1098, UInt<1>(0h1))
node _T_1100 = eq(d_release_ack, UInt<1>(0h0))
node _T_1101 = and(_T_1099, _T_1100)
when _T_1101 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1102 = dshr(inflight, io.in.d.bits.source)
node _T_1103 = bits(_T_1102, 0, 0)
node _T_1104 = or(_T_1103, same_cycle_resp)
node _T_1105 = asUInt(reset)
node _T_1106 = eq(_T_1105, UInt<1>(0h0))
when _T_1106 :
node _T_1107 = eq(_T_1104, UInt<1>(0h0))
when _T_1107 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1104, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1108 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1109 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1110 = or(_T_1108, _T_1109)
node _T_1111 = asUInt(reset)
node _T_1112 = eq(_T_1111, UInt<1>(0h0))
when _T_1112 :
node _T_1113 = eq(_T_1110, UInt<1>(0h0))
when _T_1113 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1110, UInt<1>(0h1), "") : assert_100
node _T_1114 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1115 = asUInt(reset)
node _T_1116 = eq(_T_1115, UInt<1>(0h0))
when _T_1116 :
node _T_1117 = eq(_T_1114, UInt<1>(0h0))
when _T_1117 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1114, UInt<1>(0h1), "") : assert_101
else :
node _T_1118 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1119 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1120 = or(_T_1118, _T_1119)
node _T_1121 = asUInt(reset)
node _T_1122 = eq(_T_1121, UInt<1>(0h0))
when _T_1122 :
node _T_1123 = eq(_T_1120, UInt<1>(0h0))
when _T_1123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1120, UInt<1>(0h1), "") : assert_102
node _T_1124 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1125 = asUInt(reset)
node _T_1126 = eq(_T_1125, UInt<1>(0h0))
when _T_1126 :
node _T_1127 = eq(_T_1124, UInt<1>(0h0))
when _T_1127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1124, UInt<1>(0h1), "") : assert_103
node _T_1128 = and(io.in.d.valid, d_first_1)
node _T_1129 = and(_T_1128, a_first_1)
node _T_1130 = and(_T_1129, io.in.a.valid)
node _T_1131 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1132 = and(_T_1130, _T_1131)
node _T_1133 = eq(d_release_ack, UInt<1>(0h0))
node _T_1134 = and(_T_1132, _T_1133)
when _T_1134 :
node _T_1135 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1136 = or(_T_1135, io.in.a.ready)
node _T_1137 = asUInt(reset)
node _T_1138 = eq(_T_1137, UInt<1>(0h0))
when _T_1138 :
node _T_1139 = eq(_T_1136, UInt<1>(0h0))
when _T_1139 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1136, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_127
node _T_1140 = orr(inflight)
node _T_1141 = eq(_T_1140, UInt<1>(0h0))
node _T_1142 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1143 = or(_T_1141, _T_1142)
node _T_1144 = lt(watchdog, plusarg_reader.out)
node _T_1145 = or(_T_1143, _T_1144)
node _T_1146 = asUInt(reset)
node _T_1147 = eq(_T_1146, UInt<1>(0h0))
when _T_1147 :
node _T_1148 = eq(_T_1145, UInt<1>(0h0))
when _T_1148 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1145, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1149 = and(io.in.a.ready, io.in.a.valid)
node _T_1150 = and(io.in.d.ready, io.in.d.valid)
node _T_1151 = or(_T_1149, _T_1150)
when _T_1151 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0)
regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<21>(0h0)
connect _c_first_WIRE.bits.source, UInt<7>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<65>
connect c_set, UInt<65>(0h0)
wire c_set_wo_ready : UInt<65>
connect c_set_wo_ready, UInt<65>(0h0)
wire c_opcodes_set : UInt<260>
connect c_opcodes_set, UInt<260>(0h0)
wire c_sizes_set : UInt<260>
connect c_sizes_set, UInt<260>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<21>(0h0)
connect _WIRE_10.bits.source, UInt<7>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1152 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<21>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1153 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1154 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1155 = and(_T_1153, _T_1154)
node _T_1156 = and(_T_1152, _T_1155)
when _T_1156 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<21>(0h0)
connect _WIRE_14.bits.source, UInt<7>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1157 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1158 = and(_T_1157, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<21>(0h0)
connect _WIRE_16.bits.source, UInt<7>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1159 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1160 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1161 = and(_T_1159, _T_1160)
node _T_1162 = and(_T_1158, _T_1161)
when _T_1162 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<21>(0h0)
connect _WIRE_18.bits.source, UInt<7>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1163 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1164 = bits(_T_1163, 0, 0)
node _T_1165 = eq(_T_1164, UInt<1>(0h0))
node _T_1166 = asUInt(reset)
node _T_1167 = eq(_T_1166, UInt<1>(0h0))
when _T_1167 :
node _T_1168 = eq(_T_1165, UInt<1>(0h0))
when _T_1168 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1165, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<65>
connect d_clr_1, UInt<65>(0h0)
wire d_clr_wo_ready_1 : UInt<65>
connect d_clr_wo_ready_1, UInt<65>(0h0)
wire d_opcodes_clr_1 : UInt<260>
connect d_opcodes_clr_1, UInt<260>(0h0)
wire d_sizes_clr_1 : UInt<260>
connect d_sizes_clr_1, UInt<260>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1169 = and(io.in.d.valid, d_first_2)
node _T_1170 = and(_T_1169, UInt<1>(0h1))
node _T_1171 = and(_T_1170, d_release_ack_1)
when _T_1171 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1172 = and(io.in.d.ready, io.in.d.valid)
node _T_1173 = and(_T_1172, d_first_2)
node _T_1174 = and(_T_1173, UInt<1>(0h1))
node _T_1175 = and(_T_1174, d_release_ack_1)
when _T_1175 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1176 = and(io.in.d.valid, d_first_2)
node _T_1177 = and(_T_1176, UInt<1>(0h1))
node _T_1178 = and(_T_1177, d_release_ack_1)
when _T_1178 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1179 = dshr(inflight_1, io.in.d.bits.source)
node _T_1180 = bits(_T_1179, 0, 0)
node _T_1181 = or(_T_1180, same_cycle_resp_1)
node _T_1182 = asUInt(reset)
node _T_1183 = eq(_T_1182, UInt<1>(0h0))
when _T_1183 :
node _T_1184 = eq(_T_1181, UInt<1>(0h0))
when _T_1184 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_1181, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<21>(0h0)
connect _WIRE_20.bits.source, UInt<7>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1185 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1186 = asUInt(reset)
node _T_1187 = eq(_T_1186, UInt<1>(0h0))
when _T_1187 :
node _T_1188 = eq(_T_1185, UInt<1>(0h0))
when _T_1188 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1185, UInt<1>(0h1), "") : assert_108
else :
node _T_1189 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1190 = asUInt(reset)
node _T_1191 = eq(_T_1190, UInt<1>(0h0))
when _T_1191 :
node _T_1192 = eq(_T_1189, UInt<1>(0h0))
when _T_1192 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1189, UInt<1>(0h1), "") : assert_109
node _T_1193 = and(io.in.d.valid, d_first_2)
node _T_1194 = and(_T_1193, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<21>(0h0)
connect _WIRE_22.bits.source, UInt<7>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1195 = and(_T_1194, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<21>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1196 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1197 = and(_T_1195, _T_1196)
node _T_1198 = and(_T_1197, d_release_ack_1)
node _T_1199 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1200 = and(_T_1198, _T_1199)
when _T_1200 :
node _T_1201 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<21>(0h0)
connect _WIRE_26.bits.source, UInt<7>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1202 = or(_T_1201, _WIRE_27.ready)
node _T_1203 = asUInt(reset)
node _T_1204 = eq(_T_1203, UInt<1>(0h0))
when _T_1204 :
node _T_1205 = eq(_T_1202, UInt<1>(0h0))
when _T_1205 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1202, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_128
node _T_1206 = orr(inflight_1)
node _T_1207 = eq(_T_1206, UInt<1>(0h0))
node _T_1208 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1209 = or(_T_1207, _T_1208)
node _T_1210 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1211 = or(_T_1209, _T_1210)
node _T_1212 = asUInt(reset)
node _T_1213 = eq(_T_1212, UInt<1>(0h0))
when _T_1213 :
node _T_1214 = eq(_T_1211, UInt<1>(0h0))
when _T_1214 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1211, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<21>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1215 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1216 = and(io.in.d.ready, io.in.d.valid)
node _T_1217 = or(_T_1215, _T_1216)
when _T_1217 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_62( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7]
wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7]
wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7]
wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7]
wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74]
wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire sink_ok = 1'h0; // @[Monitor.scala:309:31]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59]
wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14]
wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27]
wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25]
wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61]
wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_44 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_50 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_56 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_62 = 1'h1; // @[Parameters.scala:56:32]
wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:57:20]
wire _source_ok_T_68 = 1'h1; // @[Parameters.scala:56:32]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28]
wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28]
wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7]
wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74]
wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74]
wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54]
wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52]
wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79]
wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51]
wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35]
wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35]
wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34]
wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34]
wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34]
wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34]
wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46]
wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76]
wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34]
wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7]
wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_25 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_26 = _source_ok_T_25 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_29 = source_ok_uncommonBits_4 != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_30 = _source_ok_T_28 & _source_ok_T_29; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31]
wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h23; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31]
wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31]
wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31]
wire _source_ok_T_34 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_35 = _source_ok_T_34 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok = _source_ok_T_40 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46]
wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71]
wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71]
assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71]
assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}]
wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46]
wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}]
wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49]
wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}]
wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27]
wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21]
wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26]
wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}]
wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}]
wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}]
wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}]
wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}]
wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}]
wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38]
wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}]
wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10]
wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10]
wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10]
wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10]
wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10]
wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}]
wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_41 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_0 = _source_ok_T_41; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}]
wire [4:0] _source_ok_T_42 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_48 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_54 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_60 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire [4:0] _source_ok_T_66 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7]
wire _source_ok_T_43 = _source_ok_T_42 == 5'h0; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_45 = _source_ok_T_43; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_1 = _source_ok_T_47; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_49 = _source_ok_T_48 == 5'h1; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_51 = _source_ok_T_49; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_2 = _source_ok_T_53; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_55 = _source_ok_T_54 == 5'h2; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_57 = _source_ok_T_55; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_3 = _source_ok_T_59; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_61 = _source_ok_T_60 == 5'h3; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_63 = _source_ok_T_61; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:67, :56:48]
wire _source_ok_WIRE_1_4 = _source_ok_T_65; // @[Parameters.scala:1138:31]
wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}]
wire _source_ok_T_67 = _source_ok_T_66 == 5'h8; // @[Parameters.scala:54:{10,32}]
wire _source_ok_T_69 = _source_ok_T_67; // @[Parameters.scala:54:{32,67}]
wire _source_ok_T_70 = source_ok_uncommonBits_9 != 2'h3; // @[Parameters.scala:52:56, :57:20]
wire _source_ok_T_71 = _source_ok_T_69 & _source_ok_T_70; // @[Parameters.scala:54:67, :56:48, :57:20]
wire _source_ok_WIRE_1_5 = _source_ok_T_71; // @[Parameters.scala:1138:31]
wire _source_ok_T_72 = io_in_d_bits_source_0 == 7'h23; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_6 = _source_ok_T_72; // @[Parameters.scala:1138:31]
wire _source_ok_T_73 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_7 = _source_ok_T_73; // @[Parameters.scala:1138:31]
wire _source_ok_T_74 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7]
wire _source_ok_WIRE_1_8 = _source_ok_T_74; // @[Parameters.scala:1138:31]
wire _source_ok_T_75 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_78 = _source_ok_T_77 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46]
wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46]
wire source_ok_1 = _source_ok_T_81 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46]
wire _T_1149 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_1149; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_1149; // @[Decoupled.scala:51:35]
wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [6:0] source; // @[Monitor.scala:390:22]
reg [20:0] address; // @[Monitor.scala:391:22]
wire _T_1217 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_1217; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_1217; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_1217; // @[Decoupled.scala:51:35]
wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71]
wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71]
wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28]
wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [6:0] source_1; // @[Monitor.scala:541:22]
reg [64:0] inflight; // @[Monitor.scala:614:27]
reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [259:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [64:0] a_set; // @[Monitor.scala:626:34]
wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34]
wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [259:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69]
wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69]
assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69]
wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65]
assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65]
wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101]
assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101]
wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99]
assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99]
wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69]
assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69]
wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67]
assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67]
wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101]
assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101]
wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99]
assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99]
wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}]
wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}]
wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}]
wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}]
wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44]
wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35]
assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35]
wire [127:0] _a_set_T; // @[OneHot.scala:58:35]
assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35]
assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1082 = _T_1149 & a_first_1; // @[Decoupled.scala:51:35]
assign a_set = _T_1082 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = _T_1082 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}]
wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51]
wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}]
assign a_sizes_set_interm = _T_1082 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}]
wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79]
wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79]
assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79]
wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77]
assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77]
wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}]
assign a_opcodes_set = _T_1082 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}]
wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}]
assign a_sizes_set = _T_1082 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}]
wire [64:0] d_clr; // @[Monitor.scala:664:34]
wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46]
wire _T_1128 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T; // @[OneHot.scala:58:35]
assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35]
assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35]
wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35]
assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35]
assign d_clr_wo_ready = _T_1128 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1097 = _T_1217 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
assign d_clr = _T_1097 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}]
assign d_opcodes_clr = _T_1097 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}]
wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}]
assign d_sizes_clr = _T_1097 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113]
wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}]
wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27]
wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}]
wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [64:0] inflight_1; // @[Monitor.scala:726:35]
wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46]
wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28]
wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25]
wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43]
wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}]
wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35]
wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}]
wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}]
wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}]
wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}]
wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}]
wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire [64:0] d_clr_1; // @[Monitor.scala:774:34]
wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_1193 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_1193 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire _T_1175 = _T_1217 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
assign d_clr_1 = _T_1175 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35]
wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}]
assign d_opcodes_clr_1 = _T_1175 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}]
wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}]
assign d_sizes_clr_1 = _T_1175 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}]
wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113]
wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}]
wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_131 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_219
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_131( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_219 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module ShuttleDCacheMSHR_1 :
input clock : Clock
input reset : Reset
output io : { flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip req_bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, data : UInt<64>, mask : UInt<8>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<4>, sdq_id : UInt<5>}, flip probe_addr : UInt<32>, idx_match : UInt<1>, tag : UInt<20>, mem_acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip mem_grant : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, mem_finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}, refill : { way_en : UInt<4>, addr : UInt<12>}, meta_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<6>, way_en : UInt<4>, tag : UInt<20>, data : { coh : { state : UInt<2>}, tag : UInt<20>}}}, replay : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, data : UInt<64>, mask : UInt<8>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<4>, sdq_id : UInt<5>}}, wb_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { tag : UInt<20>, idx : UInt<6>, source : UInt<3>, param : UInt<3>, way_en : UInt<4>, voluntary : UInt<1>}}, probe_rdy : UInt<1>}
regreset state : UInt<4>, clock, reset, UInt<4>(0h0)
reg req : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, data : UInt<64>, mask : UInt<8>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<4>, sdq_id : UInt<5>}, clock
node req_idx = bits(req.addr, 11, 6)
node req_tag = shr(req.addr, 12)
node _req_block_addr_T = shr(req.addr, 6)
node req_block_addr = shl(_req_block_addr_T, 6)
node _idx_match_T = bits(io.req_bits.addr, 11, 6)
node idx_match = eq(req_idx, _idx_match_T)
node _probe_idx_match_T = bits(io.probe_addr, 11, 6)
node probe_idx_match = eq(req_idx, _probe_idx_match_T)
wire new_coh_meta : { state : UInt<2>}
connect new_coh_meta.state, UInt<2>(0h0)
regreset new_coh : { state : UInt<2>}, clock, reset, new_coh_meta
node _r_T = eq(UInt<5>(0h10), UInt<5>(0h10))
node _r_T_1 = mux(_r_T, UInt<2>(0h2), UInt<2>(0h2))
node _r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _r_T_3 = mux(_r_T_2, UInt<2>(0h1), _r_T_1)
node _r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _r_T_5 = mux(_r_T_4, UInt<2>(0h0), _r_T_3)
node _r_T_6 = cat(_r_T_5, req.old_meta.coh.state)
node _r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _r_T_19 = eq(_r_T_18, _r_T_6)
node _r_T_20 = mux(_r_T_19, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_21 = mux(_r_T_19, UInt<3>(0h5), UInt<1>(0h0))
node _r_T_22 = mux(_r_T_19, UInt<2>(0h0), UInt<1>(0h0))
node _r_T_23 = eq(_r_T_17, _r_T_6)
node _r_T_24 = mux(_r_T_23, UInt<1>(0h0), _r_T_20)
node _r_T_25 = mux(_r_T_23, UInt<3>(0h2), _r_T_21)
node _r_T_26 = mux(_r_T_23, UInt<2>(0h0), _r_T_22)
node _r_T_27 = eq(_r_T_16, _r_T_6)
node _r_T_28 = mux(_r_T_27, UInt<1>(0h0), _r_T_24)
node _r_T_29 = mux(_r_T_27, UInt<3>(0h1), _r_T_25)
node _r_T_30 = mux(_r_T_27, UInt<2>(0h0), _r_T_26)
node _r_T_31 = eq(_r_T_15, _r_T_6)
node _r_T_32 = mux(_r_T_31, UInt<1>(0h1), _r_T_28)
node _r_T_33 = mux(_r_T_31, UInt<3>(0h1), _r_T_29)
node _r_T_34 = mux(_r_T_31, UInt<2>(0h0), _r_T_30)
node _r_T_35 = eq(_r_T_14, _r_T_6)
node _r_T_36 = mux(_r_T_35, UInt<1>(0h0), _r_T_32)
node _r_T_37 = mux(_r_T_35, UInt<3>(0h5), _r_T_33)
node _r_T_38 = mux(_r_T_35, UInt<2>(0h0), _r_T_34)
node _r_T_39 = eq(_r_T_13, _r_T_6)
node _r_T_40 = mux(_r_T_39, UInt<1>(0h0), _r_T_36)
node _r_T_41 = mux(_r_T_39, UInt<3>(0h4), _r_T_37)
node _r_T_42 = mux(_r_T_39, UInt<2>(0h1), _r_T_38)
node _r_T_43 = eq(_r_T_12, _r_T_6)
node _r_T_44 = mux(_r_T_43, UInt<1>(0h0), _r_T_40)
node _r_T_45 = mux(_r_T_43, UInt<3>(0h0), _r_T_41)
node _r_T_46 = mux(_r_T_43, UInt<2>(0h1), _r_T_42)
node _r_T_47 = eq(_r_T_11, _r_T_6)
node _r_T_48 = mux(_r_T_47, UInt<1>(0h1), _r_T_44)
node _r_T_49 = mux(_r_T_47, UInt<3>(0h0), _r_T_45)
node _r_T_50 = mux(_r_T_47, UInt<2>(0h1), _r_T_46)
node _r_T_51 = eq(_r_T_10, _r_T_6)
node _r_T_52 = mux(_r_T_51, UInt<1>(0h0), _r_T_48)
node _r_T_53 = mux(_r_T_51, UInt<3>(0h5), _r_T_49)
node _r_T_54 = mux(_r_T_51, UInt<2>(0h0), _r_T_50)
node _r_T_55 = eq(_r_T_9, _r_T_6)
node _r_T_56 = mux(_r_T_55, UInt<1>(0h0), _r_T_52)
node _r_T_57 = mux(_r_T_55, UInt<3>(0h4), _r_T_53)
node _r_T_58 = mux(_r_T_55, UInt<2>(0h1), _r_T_54)
node _r_T_59 = eq(_r_T_8, _r_T_6)
node _r_T_60 = mux(_r_T_59, UInt<1>(0h0), _r_T_56)
node _r_T_61 = mux(_r_T_59, UInt<3>(0h3), _r_T_57)
node _r_T_62 = mux(_r_T_59, UInt<2>(0h2), _r_T_58)
node _r_T_63 = eq(_r_T_7, _r_T_6)
node r_1 = mux(_r_T_63, UInt<1>(0h1), _r_T_60)
node shrink_param = mux(_r_T_63, UInt<3>(0h3), _r_T_61)
node r_3 = mux(_r_T_63, UInt<2>(0h2), _r_T_62)
wire coh_on_clear : { state : UInt<2>}
connect coh_on_clear.state, r_3
node _grow_param_r_c_cat_T = eq(req.cmd, UInt<1>(0h1))
node _grow_param_r_c_cat_T_1 = eq(req.cmd, UInt<5>(0h11))
node _grow_param_r_c_cat_T_2 = or(_grow_param_r_c_cat_T, _grow_param_r_c_cat_T_1)
node _grow_param_r_c_cat_T_3 = eq(req.cmd, UInt<3>(0h7))
node _grow_param_r_c_cat_T_4 = or(_grow_param_r_c_cat_T_2, _grow_param_r_c_cat_T_3)
node _grow_param_r_c_cat_T_5 = eq(req.cmd, UInt<3>(0h4))
node _grow_param_r_c_cat_T_6 = eq(req.cmd, UInt<4>(0h9))
node _grow_param_r_c_cat_T_7 = eq(req.cmd, UInt<4>(0ha))
node _grow_param_r_c_cat_T_8 = eq(req.cmd, UInt<4>(0hb))
node _grow_param_r_c_cat_T_9 = or(_grow_param_r_c_cat_T_5, _grow_param_r_c_cat_T_6)
node _grow_param_r_c_cat_T_10 = or(_grow_param_r_c_cat_T_9, _grow_param_r_c_cat_T_7)
node _grow_param_r_c_cat_T_11 = or(_grow_param_r_c_cat_T_10, _grow_param_r_c_cat_T_8)
node _grow_param_r_c_cat_T_12 = eq(req.cmd, UInt<4>(0h8))
node _grow_param_r_c_cat_T_13 = eq(req.cmd, UInt<4>(0hc))
node _grow_param_r_c_cat_T_14 = eq(req.cmd, UInt<4>(0hd))
node _grow_param_r_c_cat_T_15 = eq(req.cmd, UInt<4>(0he))
node _grow_param_r_c_cat_T_16 = eq(req.cmd, UInt<4>(0hf))
node _grow_param_r_c_cat_T_17 = or(_grow_param_r_c_cat_T_12, _grow_param_r_c_cat_T_13)
node _grow_param_r_c_cat_T_18 = or(_grow_param_r_c_cat_T_17, _grow_param_r_c_cat_T_14)
node _grow_param_r_c_cat_T_19 = or(_grow_param_r_c_cat_T_18, _grow_param_r_c_cat_T_15)
node _grow_param_r_c_cat_T_20 = or(_grow_param_r_c_cat_T_19, _grow_param_r_c_cat_T_16)
node _grow_param_r_c_cat_T_21 = or(_grow_param_r_c_cat_T_11, _grow_param_r_c_cat_T_20)
node _grow_param_r_c_cat_T_22 = or(_grow_param_r_c_cat_T_4, _grow_param_r_c_cat_T_21)
node _grow_param_r_c_cat_T_23 = eq(req.cmd, UInt<1>(0h1))
node _grow_param_r_c_cat_T_24 = eq(req.cmd, UInt<5>(0h11))
node _grow_param_r_c_cat_T_25 = or(_grow_param_r_c_cat_T_23, _grow_param_r_c_cat_T_24)
node _grow_param_r_c_cat_T_26 = eq(req.cmd, UInt<3>(0h7))
node _grow_param_r_c_cat_T_27 = or(_grow_param_r_c_cat_T_25, _grow_param_r_c_cat_T_26)
node _grow_param_r_c_cat_T_28 = eq(req.cmd, UInt<3>(0h4))
node _grow_param_r_c_cat_T_29 = eq(req.cmd, UInt<4>(0h9))
node _grow_param_r_c_cat_T_30 = eq(req.cmd, UInt<4>(0ha))
node _grow_param_r_c_cat_T_31 = eq(req.cmd, UInt<4>(0hb))
node _grow_param_r_c_cat_T_32 = or(_grow_param_r_c_cat_T_28, _grow_param_r_c_cat_T_29)
node _grow_param_r_c_cat_T_33 = or(_grow_param_r_c_cat_T_32, _grow_param_r_c_cat_T_30)
node _grow_param_r_c_cat_T_34 = or(_grow_param_r_c_cat_T_33, _grow_param_r_c_cat_T_31)
node _grow_param_r_c_cat_T_35 = eq(req.cmd, UInt<4>(0h8))
node _grow_param_r_c_cat_T_36 = eq(req.cmd, UInt<4>(0hc))
node _grow_param_r_c_cat_T_37 = eq(req.cmd, UInt<4>(0hd))
node _grow_param_r_c_cat_T_38 = eq(req.cmd, UInt<4>(0he))
node _grow_param_r_c_cat_T_39 = eq(req.cmd, UInt<4>(0hf))
node _grow_param_r_c_cat_T_40 = or(_grow_param_r_c_cat_T_35, _grow_param_r_c_cat_T_36)
node _grow_param_r_c_cat_T_41 = or(_grow_param_r_c_cat_T_40, _grow_param_r_c_cat_T_37)
node _grow_param_r_c_cat_T_42 = or(_grow_param_r_c_cat_T_41, _grow_param_r_c_cat_T_38)
node _grow_param_r_c_cat_T_43 = or(_grow_param_r_c_cat_T_42, _grow_param_r_c_cat_T_39)
node _grow_param_r_c_cat_T_44 = or(_grow_param_r_c_cat_T_34, _grow_param_r_c_cat_T_43)
node _grow_param_r_c_cat_T_45 = or(_grow_param_r_c_cat_T_27, _grow_param_r_c_cat_T_44)
node _grow_param_r_c_cat_T_46 = eq(req.cmd, UInt<2>(0h3))
node _grow_param_r_c_cat_T_47 = or(_grow_param_r_c_cat_T_45, _grow_param_r_c_cat_T_46)
node _grow_param_r_c_cat_T_48 = eq(req.cmd, UInt<3>(0h6))
node _grow_param_r_c_cat_T_49 = or(_grow_param_r_c_cat_T_47, _grow_param_r_c_cat_T_48)
node grow_param_r_c = cat(_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49)
node _grow_param_r_T = cat(grow_param_r_c, new_coh.state)
node _grow_param_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_2 = cat(_grow_param_r_T_1, UInt<2>(0h3))
node _grow_param_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_4 = cat(_grow_param_r_T_3, UInt<2>(0h2))
node _grow_param_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_6 = cat(_grow_param_r_T_5, UInt<2>(0h1))
node _grow_param_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_8 = cat(_grow_param_r_T_7, UInt<2>(0h3))
node _grow_param_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_10 = cat(_grow_param_r_T_9, UInt<2>(0h2))
node _grow_param_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_12 = cat(_grow_param_r_T_11, UInt<2>(0h3))
node _grow_param_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_14 = cat(_grow_param_r_T_13, UInt<2>(0h2))
node _grow_param_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_16 = cat(_grow_param_r_T_15, UInt<2>(0h0))
node _grow_param_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_18 = cat(_grow_param_r_T_17, UInt<2>(0h1))
node _grow_param_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_20 = cat(_grow_param_r_T_19, UInt<2>(0h0))
node _grow_param_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_22 = cat(_grow_param_r_T_21, UInt<2>(0h1))
node _grow_param_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_24 = cat(_grow_param_r_T_23, UInt<2>(0h0))
node _grow_param_r_T_25 = eq(_grow_param_r_T_24, _grow_param_r_T)
node _grow_param_r_T_26 = mux(_grow_param_r_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_27 = mux(_grow_param_r_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _grow_param_r_T_28 = eq(_grow_param_r_T_22, _grow_param_r_T)
node _grow_param_r_T_29 = mux(_grow_param_r_T_28, UInt<1>(0h0), _grow_param_r_T_26)
node _grow_param_r_T_30 = mux(_grow_param_r_T_28, UInt<2>(0h2), _grow_param_r_T_27)
node _grow_param_r_T_31 = eq(_grow_param_r_T_20, _grow_param_r_T)
node _grow_param_r_T_32 = mux(_grow_param_r_T_31, UInt<1>(0h0), _grow_param_r_T_29)
node _grow_param_r_T_33 = mux(_grow_param_r_T_31, UInt<2>(0h1), _grow_param_r_T_30)
node _grow_param_r_T_34 = eq(_grow_param_r_T_18, _grow_param_r_T)
node _grow_param_r_T_35 = mux(_grow_param_r_T_34, UInt<1>(0h0), _grow_param_r_T_32)
node _grow_param_r_T_36 = mux(_grow_param_r_T_34, UInt<2>(0h2), _grow_param_r_T_33)
node _grow_param_r_T_37 = eq(_grow_param_r_T_16, _grow_param_r_T)
node _grow_param_r_T_38 = mux(_grow_param_r_T_37, UInt<1>(0h0), _grow_param_r_T_35)
node _grow_param_r_T_39 = mux(_grow_param_r_T_37, UInt<2>(0h0), _grow_param_r_T_36)
node _grow_param_r_T_40 = eq(_grow_param_r_T_14, _grow_param_r_T)
node _grow_param_r_T_41 = mux(_grow_param_r_T_40, UInt<1>(0h1), _grow_param_r_T_38)
node _grow_param_r_T_42 = mux(_grow_param_r_T_40, UInt<2>(0h3), _grow_param_r_T_39)
node _grow_param_r_T_43 = eq(_grow_param_r_T_12, _grow_param_r_T)
node _grow_param_r_T_44 = mux(_grow_param_r_T_43, UInt<1>(0h1), _grow_param_r_T_41)
node _grow_param_r_T_45 = mux(_grow_param_r_T_43, UInt<2>(0h3), _grow_param_r_T_42)
node _grow_param_r_T_46 = eq(_grow_param_r_T_10, _grow_param_r_T)
node _grow_param_r_T_47 = mux(_grow_param_r_T_46, UInt<1>(0h1), _grow_param_r_T_44)
node _grow_param_r_T_48 = mux(_grow_param_r_T_46, UInt<2>(0h2), _grow_param_r_T_45)
node _grow_param_r_T_49 = eq(_grow_param_r_T_8, _grow_param_r_T)
node _grow_param_r_T_50 = mux(_grow_param_r_T_49, UInt<1>(0h1), _grow_param_r_T_47)
node _grow_param_r_T_51 = mux(_grow_param_r_T_49, UInt<2>(0h3), _grow_param_r_T_48)
node _grow_param_r_T_52 = eq(_grow_param_r_T_6, _grow_param_r_T)
node _grow_param_r_T_53 = mux(_grow_param_r_T_52, UInt<1>(0h1), _grow_param_r_T_50)
node _grow_param_r_T_54 = mux(_grow_param_r_T_52, UInt<2>(0h1), _grow_param_r_T_51)
node _grow_param_r_T_55 = eq(_grow_param_r_T_4, _grow_param_r_T)
node _grow_param_r_T_56 = mux(_grow_param_r_T_55, UInt<1>(0h1), _grow_param_r_T_53)
node _grow_param_r_T_57 = mux(_grow_param_r_T_55, UInt<2>(0h2), _grow_param_r_T_54)
node _grow_param_r_T_58 = eq(_grow_param_r_T_2, _grow_param_r_T)
node grow_param_r_1 = mux(_grow_param_r_T_58, UInt<1>(0h1), _grow_param_r_T_56)
node grow_param = mux(_grow_param_r_T_58, UInt<2>(0h3), _grow_param_r_T_57)
wire grow_param_meta : { state : UInt<2>}
connect grow_param_meta.state, grow_param
node _coh_on_grant_c_cat_T = eq(req.cmd, UInt<1>(0h1))
node _coh_on_grant_c_cat_T_1 = eq(req.cmd, UInt<5>(0h11))
node _coh_on_grant_c_cat_T_2 = or(_coh_on_grant_c_cat_T, _coh_on_grant_c_cat_T_1)
node _coh_on_grant_c_cat_T_3 = eq(req.cmd, UInt<3>(0h7))
node _coh_on_grant_c_cat_T_4 = or(_coh_on_grant_c_cat_T_2, _coh_on_grant_c_cat_T_3)
node _coh_on_grant_c_cat_T_5 = eq(req.cmd, UInt<3>(0h4))
node _coh_on_grant_c_cat_T_6 = eq(req.cmd, UInt<4>(0h9))
node _coh_on_grant_c_cat_T_7 = eq(req.cmd, UInt<4>(0ha))
node _coh_on_grant_c_cat_T_8 = eq(req.cmd, UInt<4>(0hb))
node _coh_on_grant_c_cat_T_9 = or(_coh_on_grant_c_cat_T_5, _coh_on_grant_c_cat_T_6)
node _coh_on_grant_c_cat_T_10 = or(_coh_on_grant_c_cat_T_9, _coh_on_grant_c_cat_T_7)
node _coh_on_grant_c_cat_T_11 = or(_coh_on_grant_c_cat_T_10, _coh_on_grant_c_cat_T_8)
node _coh_on_grant_c_cat_T_12 = eq(req.cmd, UInt<4>(0h8))
node _coh_on_grant_c_cat_T_13 = eq(req.cmd, UInt<4>(0hc))
node _coh_on_grant_c_cat_T_14 = eq(req.cmd, UInt<4>(0hd))
node _coh_on_grant_c_cat_T_15 = eq(req.cmd, UInt<4>(0he))
node _coh_on_grant_c_cat_T_16 = eq(req.cmd, UInt<4>(0hf))
node _coh_on_grant_c_cat_T_17 = or(_coh_on_grant_c_cat_T_12, _coh_on_grant_c_cat_T_13)
node _coh_on_grant_c_cat_T_18 = or(_coh_on_grant_c_cat_T_17, _coh_on_grant_c_cat_T_14)
node _coh_on_grant_c_cat_T_19 = or(_coh_on_grant_c_cat_T_18, _coh_on_grant_c_cat_T_15)
node _coh_on_grant_c_cat_T_20 = or(_coh_on_grant_c_cat_T_19, _coh_on_grant_c_cat_T_16)
node _coh_on_grant_c_cat_T_21 = or(_coh_on_grant_c_cat_T_11, _coh_on_grant_c_cat_T_20)
node _coh_on_grant_c_cat_T_22 = or(_coh_on_grant_c_cat_T_4, _coh_on_grant_c_cat_T_21)
node _coh_on_grant_c_cat_T_23 = eq(req.cmd, UInt<1>(0h1))
node _coh_on_grant_c_cat_T_24 = eq(req.cmd, UInt<5>(0h11))
node _coh_on_grant_c_cat_T_25 = or(_coh_on_grant_c_cat_T_23, _coh_on_grant_c_cat_T_24)
node _coh_on_grant_c_cat_T_26 = eq(req.cmd, UInt<3>(0h7))
node _coh_on_grant_c_cat_T_27 = or(_coh_on_grant_c_cat_T_25, _coh_on_grant_c_cat_T_26)
node _coh_on_grant_c_cat_T_28 = eq(req.cmd, UInt<3>(0h4))
node _coh_on_grant_c_cat_T_29 = eq(req.cmd, UInt<4>(0h9))
node _coh_on_grant_c_cat_T_30 = eq(req.cmd, UInt<4>(0ha))
node _coh_on_grant_c_cat_T_31 = eq(req.cmd, UInt<4>(0hb))
node _coh_on_grant_c_cat_T_32 = or(_coh_on_grant_c_cat_T_28, _coh_on_grant_c_cat_T_29)
node _coh_on_grant_c_cat_T_33 = or(_coh_on_grant_c_cat_T_32, _coh_on_grant_c_cat_T_30)
node _coh_on_grant_c_cat_T_34 = or(_coh_on_grant_c_cat_T_33, _coh_on_grant_c_cat_T_31)
node _coh_on_grant_c_cat_T_35 = eq(req.cmd, UInt<4>(0h8))
node _coh_on_grant_c_cat_T_36 = eq(req.cmd, UInt<4>(0hc))
node _coh_on_grant_c_cat_T_37 = eq(req.cmd, UInt<4>(0hd))
node _coh_on_grant_c_cat_T_38 = eq(req.cmd, UInt<4>(0he))
node _coh_on_grant_c_cat_T_39 = eq(req.cmd, UInt<4>(0hf))
node _coh_on_grant_c_cat_T_40 = or(_coh_on_grant_c_cat_T_35, _coh_on_grant_c_cat_T_36)
node _coh_on_grant_c_cat_T_41 = or(_coh_on_grant_c_cat_T_40, _coh_on_grant_c_cat_T_37)
node _coh_on_grant_c_cat_T_42 = or(_coh_on_grant_c_cat_T_41, _coh_on_grant_c_cat_T_38)
node _coh_on_grant_c_cat_T_43 = or(_coh_on_grant_c_cat_T_42, _coh_on_grant_c_cat_T_39)
node _coh_on_grant_c_cat_T_44 = or(_coh_on_grant_c_cat_T_34, _coh_on_grant_c_cat_T_43)
node _coh_on_grant_c_cat_T_45 = or(_coh_on_grant_c_cat_T_27, _coh_on_grant_c_cat_T_44)
node _coh_on_grant_c_cat_T_46 = eq(req.cmd, UInt<2>(0h3))
node _coh_on_grant_c_cat_T_47 = or(_coh_on_grant_c_cat_T_45, _coh_on_grant_c_cat_T_46)
node _coh_on_grant_c_cat_T_48 = eq(req.cmd, UInt<3>(0h6))
node _coh_on_grant_c_cat_T_49 = or(_coh_on_grant_c_cat_T_47, _coh_on_grant_c_cat_T_48)
node coh_on_grant_c = cat(_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49)
node _coh_on_grant_T = cat(coh_on_grant_c, io.mem_grant.bits.param)
node _coh_on_grant_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _coh_on_grant_T_2 = cat(_coh_on_grant_T_1, UInt<2>(0h1))
node _coh_on_grant_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _coh_on_grant_T_4 = cat(_coh_on_grant_T_3, UInt<2>(0h0))
node _coh_on_grant_T_5 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _coh_on_grant_T_6 = cat(_coh_on_grant_T_5, UInt<2>(0h0))
node _coh_on_grant_T_7 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _coh_on_grant_T_8 = cat(_coh_on_grant_T_7, UInt<2>(0h0))
node _coh_on_grant_T_9 = eq(_coh_on_grant_T_2, _coh_on_grant_T)
node _coh_on_grant_T_10 = mux(_coh_on_grant_T_9, UInt<2>(0h1), UInt<2>(0h0))
node _coh_on_grant_T_11 = eq(_coh_on_grant_T_4, _coh_on_grant_T)
node _coh_on_grant_T_12 = mux(_coh_on_grant_T_11, UInt<2>(0h2), _coh_on_grant_T_10)
node _coh_on_grant_T_13 = eq(_coh_on_grant_T_6, _coh_on_grant_T)
node _coh_on_grant_T_14 = mux(_coh_on_grant_T_13, UInt<2>(0h2), _coh_on_grant_T_12)
node _coh_on_grant_T_15 = eq(_coh_on_grant_T_8, _coh_on_grant_T)
node _coh_on_grant_T_16 = mux(_coh_on_grant_T_15, UInt<2>(0h3), _coh_on_grant_T_14)
wire coh_on_grant : { state : UInt<2>}
connect coh_on_grant.state, _coh_on_grant_T_16
node _r1_c_cat_T = eq(req.cmd, UInt<1>(0h1))
node _r1_c_cat_T_1 = eq(req.cmd, UInt<5>(0h11))
node _r1_c_cat_T_2 = or(_r1_c_cat_T, _r1_c_cat_T_1)
node _r1_c_cat_T_3 = eq(req.cmd, UInt<3>(0h7))
node _r1_c_cat_T_4 = or(_r1_c_cat_T_2, _r1_c_cat_T_3)
node _r1_c_cat_T_5 = eq(req.cmd, UInt<3>(0h4))
node _r1_c_cat_T_6 = eq(req.cmd, UInt<4>(0h9))
node _r1_c_cat_T_7 = eq(req.cmd, UInt<4>(0ha))
node _r1_c_cat_T_8 = eq(req.cmd, UInt<4>(0hb))
node _r1_c_cat_T_9 = or(_r1_c_cat_T_5, _r1_c_cat_T_6)
node _r1_c_cat_T_10 = or(_r1_c_cat_T_9, _r1_c_cat_T_7)
node _r1_c_cat_T_11 = or(_r1_c_cat_T_10, _r1_c_cat_T_8)
node _r1_c_cat_T_12 = eq(req.cmd, UInt<4>(0h8))
node _r1_c_cat_T_13 = eq(req.cmd, UInt<4>(0hc))
node _r1_c_cat_T_14 = eq(req.cmd, UInt<4>(0hd))
node _r1_c_cat_T_15 = eq(req.cmd, UInt<4>(0he))
node _r1_c_cat_T_16 = eq(req.cmd, UInt<4>(0hf))
node _r1_c_cat_T_17 = or(_r1_c_cat_T_12, _r1_c_cat_T_13)
node _r1_c_cat_T_18 = or(_r1_c_cat_T_17, _r1_c_cat_T_14)
node _r1_c_cat_T_19 = or(_r1_c_cat_T_18, _r1_c_cat_T_15)
node _r1_c_cat_T_20 = or(_r1_c_cat_T_19, _r1_c_cat_T_16)
node _r1_c_cat_T_21 = or(_r1_c_cat_T_11, _r1_c_cat_T_20)
node _r1_c_cat_T_22 = or(_r1_c_cat_T_4, _r1_c_cat_T_21)
node _r1_c_cat_T_23 = eq(req.cmd, UInt<1>(0h1))
node _r1_c_cat_T_24 = eq(req.cmd, UInt<5>(0h11))
node _r1_c_cat_T_25 = or(_r1_c_cat_T_23, _r1_c_cat_T_24)
node _r1_c_cat_T_26 = eq(req.cmd, UInt<3>(0h7))
node _r1_c_cat_T_27 = or(_r1_c_cat_T_25, _r1_c_cat_T_26)
node _r1_c_cat_T_28 = eq(req.cmd, UInt<3>(0h4))
node _r1_c_cat_T_29 = eq(req.cmd, UInt<4>(0h9))
node _r1_c_cat_T_30 = eq(req.cmd, UInt<4>(0ha))
node _r1_c_cat_T_31 = eq(req.cmd, UInt<4>(0hb))
node _r1_c_cat_T_32 = or(_r1_c_cat_T_28, _r1_c_cat_T_29)
node _r1_c_cat_T_33 = or(_r1_c_cat_T_32, _r1_c_cat_T_30)
node _r1_c_cat_T_34 = or(_r1_c_cat_T_33, _r1_c_cat_T_31)
node _r1_c_cat_T_35 = eq(req.cmd, UInt<4>(0h8))
node _r1_c_cat_T_36 = eq(req.cmd, UInt<4>(0hc))
node _r1_c_cat_T_37 = eq(req.cmd, UInt<4>(0hd))
node _r1_c_cat_T_38 = eq(req.cmd, UInt<4>(0he))
node _r1_c_cat_T_39 = eq(req.cmd, UInt<4>(0hf))
node _r1_c_cat_T_40 = or(_r1_c_cat_T_35, _r1_c_cat_T_36)
node _r1_c_cat_T_41 = or(_r1_c_cat_T_40, _r1_c_cat_T_37)
node _r1_c_cat_T_42 = or(_r1_c_cat_T_41, _r1_c_cat_T_38)
node _r1_c_cat_T_43 = or(_r1_c_cat_T_42, _r1_c_cat_T_39)
node _r1_c_cat_T_44 = or(_r1_c_cat_T_34, _r1_c_cat_T_43)
node _r1_c_cat_T_45 = or(_r1_c_cat_T_27, _r1_c_cat_T_44)
node _r1_c_cat_T_46 = eq(req.cmd, UInt<2>(0h3))
node _r1_c_cat_T_47 = or(_r1_c_cat_T_45, _r1_c_cat_T_46)
node _r1_c_cat_T_48 = eq(req.cmd, UInt<3>(0h6))
node _r1_c_cat_T_49 = or(_r1_c_cat_T_47, _r1_c_cat_T_48)
node r1_c = cat(_r1_c_cat_T_22, _r1_c_cat_T_49)
node _r1_T = cat(r1_c, new_coh.state)
node _r1_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_2 = cat(_r1_T_1, UInt<2>(0h3))
node _r1_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_4 = cat(_r1_T_3, UInt<2>(0h2))
node _r1_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_6 = cat(_r1_T_5, UInt<2>(0h1))
node _r1_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_8 = cat(_r1_T_7, UInt<2>(0h3))
node _r1_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_10 = cat(_r1_T_9, UInt<2>(0h2))
node _r1_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_12 = cat(_r1_T_11, UInt<2>(0h3))
node _r1_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_14 = cat(_r1_T_13, UInt<2>(0h2))
node _r1_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_16 = cat(_r1_T_15, UInt<2>(0h0))
node _r1_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_18 = cat(_r1_T_17, UInt<2>(0h1))
node _r1_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_20 = cat(_r1_T_19, UInt<2>(0h0))
node _r1_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_22 = cat(_r1_T_21, UInt<2>(0h1))
node _r1_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_24 = cat(_r1_T_23, UInt<2>(0h0))
node _r1_T_25 = eq(_r1_T_24, _r1_T)
node _r1_T_26 = mux(_r1_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_27 = mux(_r1_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _r1_T_28 = eq(_r1_T_22, _r1_T)
node _r1_T_29 = mux(_r1_T_28, UInt<1>(0h0), _r1_T_26)
node _r1_T_30 = mux(_r1_T_28, UInt<2>(0h2), _r1_T_27)
node _r1_T_31 = eq(_r1_T_20, _r1_T)
node _r1_T_32 = mux(_r1_T_31, UInt<1>(0h0), _r1_T_29)
node _r1_T_33 = mux(_r1_T_31, UInt<2>(0h1), _r1_T_30)
node _r1_T_34 = eq(_r1_T_18, _r1_T)
node _r1_T_35 = mux(_r1_T_34, UInt<1>(0h0), _r1_T_32)
node _r1_T_36 = mux(_r1_T_34, UInt<2>(0h2), _r1_T_33)
node _r1_T_37 = eq(_r1_T_16, _r1_T)
node _r1_T_38 = mux(_r1_T_37, UInt<1>(0h0), _r1_T_35)
node _r1_T_39 = mux(_r1_T_37, UInt<2>(0h0), _r1_T_36)
node _r1_T_40 = eq(_r1_T_14, _r1_T)
node _r1_T_41 = mux(_r1_T_40, UInt<1>(0h1), _r1_T_38)
node _r1_T_42 = mux(_r1_T_40, UInt<2>(0h3), _r1_T_39)
node _r1_T_43 = eq(_r1_T_12, _r1_T)
node _r1_T_44 = mux(_r1_T_43, UInt<1>(0h1), _r1_T_41)
node _r1_T_45 = mux(_r1_T_43, UInt<2>(0h3), _r1_T_42)
node _r1_T_46 = eq(_r1_T_10, _r1_T)
node _r1_T_47 = mux(_r1_T_46, UInt<1>(0h1), _r1_T_44)
node _r1_T_48 = mux(_r1_T_46, UInt<2>(0h2), _r1_T_45)
node _r1_T_49 = eq(_r1_T_8, _r1_T)
node _r1_T_50 = mux(_r1_T_49, UInt<1>(0h1), _r1_T_47)
node _r1_T_51 = mux(_r1_T_49, UInt<2>(0h3), _r1_T_48)
node _r1_T_52 = eq(_r1_T_6, _r1_T)
node _r1_T_53 = mux(_r1_T_52, UInt<1>(0h1), _r1_T_50)
node _r1_T_54 = mux(_r1_T_52, UInt<2>(0h1), _r1_T_51)
node _r1_T_55 = eq(_r1_T_4, _r1_T)
node _r1_T_56 = mux(_r1_T_55, UInt<1>(0h1), _r1_T_53)
node _r1_T_57 = mux(_r1_T_55, UInt<2>(0h2), _r1_T_54)
node _r1_T_58 = eq(_r1_T_2, _r1_T)
node r1_1 = mux(_r1_T_58, UInt<1>(0h1), _r1_T_56)
node r1_2 = mux(_r1_T_58, UInt<2>(0h3), _r1_T_57)
node _r2_c_cat_T = eq(io.req_bits.cmd, UInt<1>(0h1))
node _r2_c_cat_T_1 = eq(io.req_bits.cmd, UInt<5>(0h11))
node _r2_c_cat_T_2 = or(_r2_c_cat_T, _r2_c_cat_T_1)
node _r2_c_cat_T_3 = eq(io.req_bits.cmd, UInt<3>(0h7))
node _r2_c_cat_T_4 = or(_r2_c_cat_T_2, _r2_c_cat_T_3)
node _r2_c_cat_T_5 = eq(io.req_bits.cmd, UInt<3>(0h4))
node _r2_c_cat_T_6 = eq(io.req_bits.cmd, UInt<4>(0h9))
node _r2_c_cat_T_7 = eq(io.req_bits.cmd, UInt<4>(0ha))
node _r2_c_cat_T_8 = eq(io.req_bits.cmd, UInt<4>(0hb))
node _r2_c_cat_T_9 = or(_r2_c_cat_T_5, _r2_c_cat_T_6)
node _r2_c_cat_T_10 = or(_r2_c_cat_T_9, _r2_c_cat_T_7)
node _r2_c_cat_T_11 = or(_r2_c_cat_T_10, _r2_c_cat_T_8)
node _r2_c_cat_T_12 = eq(io.req_bits.cmd, UInt<4>(0h8))
node _r2_c_cat_T_13 = eq(io.req_bits.cmd, UInt<4>(0hc))
node _r2_c_cat_T_14 = eq(io.req_bits.cmd, UInt<4>(0hd))
node _r2_c_cat_T_15 = eq(io.req_bits.cmd, UInt<4>(0he))
node _r2_c_cat_T_16 = eq(io.req_bits.cmd, UInt<4>(0hf))
node _r2_c_cat_T_17 = or(_r2_c_cat_T_12, _r2_c_cat_T_13)
node _r2_c_cat_T_18 = or(_r2_c_cat_T_17, _r2_c_cat_T_14)
node _r2_c_cat_T_19 = or(_r2_c_cat_T_18, _r2_c_cat_T_15)
node _r2_c_cat_T_20 = or(_r2_c_cat_T_19, _r2_c_cat_T_16)
node _r2_c_cat_T_21 = or(_r2_c_cat_T_11, _r2_c_cat_T_20)
node _r2_c_cat_T_22 = or(_r2_c_cat_T_4, _r2_c_cat_T_21)
node _r2_c_cat_T_23 = eq(io.req_bits.cmd, UInt<1>(0h1))
node _r2_c_cat_T_24 = eq(io.req_bits.cmd, UInt<5>(0h11))
node _r2_c_cat_T_25 = or(_r2_c_cat_T_23, _r2_c_cat_T_24)
node _r2_c_cat_T_26 = eq(io.req_bits.cmd, UInt<3>(0h7))
node _r2_c_cat_T_27 = or(_r2_c_cat_T_25, _r2_c_cat_T_26)
node _r2_c_cat_T_28 = eq(io.req_bits.cmd, UInt<3>(0h4))
node _r2_c_cat_T_29 = eq(io.req_bits.cmd, UInt<4>(0h9))
node _r2_c_cat_T_30 = eq(io.req_bits.cmd, UInt<4>(0ha))
node _r2_c_cat_T_31 = eq(io.req_bits.cmd, UInt<4>(0hb))
node _r2_c_cat_T_32 = or(_r2_c_cat_T_28, _r2_c_cat_T_29)
node _r2_c_cat_T_33 = or(_r2_c_cat_T_32, _r2_c_cat_T_30)
node _r2_c_cat_T_34 = or(_r2_c_cat_T_33, _r2_c_cat_T_31)
node _r2_c_cat_T_35 = eq(io.req_bits.cmd, UInt<4>(0h8))
node _r2_c_cat_T_36 = eq(io.req_bits.cmd, UInt<4>(0hc))
node _r2_c_cat_T_37 = eq(io.req_bits.cmd, UInt<4>(0hd))
node _r2_c_cat_T_38 = eq(io.req_bits.cmd, UInt<4>(0he))
node _r2_c_cat_T_39 = eq(io.req_bits.cmd, UInt<4>(0hf))
node _r2_c_cat_T_40 = or(_r2_c_cat_T_35, _r2_c_cat_T_36)
node _r2_c_cat_T_41 = or(_r2_c_cat_T_40, _r2_c_cat_T_37)
node _r2_c_cat_T_42 = or(_r2_c_cat_T_41, _r2_c_cat_T_38)
node _r2_c_cat_T_43 = or(_r2_c_cat_T_42, _r2_c_cat_T_39)
node _r2_c_cat_T_44 = or(_r2_c_cat_T_34, _r2_c_cat_T_43)
node _r2_c_cat_T_45 = or(_r2_c_cat_T_27, _r2_c_cat_T_44)
node _r2_c_cat_T_46 = eq(io.req_bits.cmd, UInt<2>(0h3))
node _r2_c_cat_T_47 = or(_r2_c_cat_T_45, _r2_c_cat_T_46)
node _r2_c_cat_T_48 = eq(io.req_bits.cmd, UInt<3>(0h6))
node _r2_c_cat_T_49 = or(_r2_c_cat_T_47, _r2_c_cat_T_48)
node r2_c = cat(_r2_c_cat_T_22, _r2_c_cat_T_49)
node _r2_T = cat(r2_c, new_coh.state)
node _r2_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_2 = cat(_r2_T_1, UInt<2>(0h3))
node _r2_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_4 = cat(_r2_T_3, UInt<2>(0h2))
node _r2_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_6 = cat(_r2_T_5, UInt<2>(0h1))
node _r2_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_8 = cat(_r2_T_7, UInt<2>(0h3))
node _r2_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_10 = cat(_r2_T_9, UInt<2>(0h2))
node _r2_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_12 = cat(_r2_T_11, UInt<2>(0h3))
node _r2_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_14 = cat(_r2_T_13, UInt<2>(0h2))
node _r2_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_16 = cat(_r2_T_15, UInt<2>(0h0))
node _r2_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_18 = cat(_r2_T_17, UInt<2>(0h1))
node _r2_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_20 = cat(_r2_T_19, UInt<2>(0h0))
node _r2_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_22 = cat(_r2_T_21, UInt<2>(0h1))
node _r2_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_24 = cat(_r2_T_23, UInt<2>(0h0))
node _r2_T_25 = eq(_r2_T_24, _r2_T)
node _r2_T_26 = mux(_r2_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_27 = mux(_r2_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _r2_T_28 = eq(_r2_T_22, _r2_T)
node _r2_T_29 = mux(_r2_T_28, UInt<1>(0h0), _r2_T_26)
node _r2_T_30 = mux(_r2_T_28, UInt<2>(0h2), _r2_T_27)
node _r2_T_31 = eq(_r2_T_20, _r2_T)
node _r2_T_32 = mux(_r2_T_31, UInt<1>(0h0), _r2_T_29)
node _r2_T_33 = mux(_r2_T_31, UInt<2>(0h1), _r2_T_30)
node _r2_T_34 = eq(_r2_T_18, _r2_T)
node _r2_T_35 = mux(_r2_T_34, UInt<1>(0h0), _r2_T_32)
node _r2_T_36 = mux(_r2_T_34, UInt<2>(0h2), _r2_T_33)
node _r2_T_37 = eq(_r2_T_16, _r2_T)
node _r2_T_38 = mux(_r2_T_37, UInt<1>(0h0), _r2_T_35)
node _r2_T_39 = mux(_r2_T_37, UInt<2>(0h0), _r2_T_36)
node _r2_T_40 = eq(_r2_T_14, _r2_T)
node _r2_T_41 = mux(_r2_T_40, UInt<1>(0h1), _r2_T_38)
node _r2_T_42 = mux(_r2_T_40, UInt<2>(0h3), _r2_T_39)
node _r2_T_43 = eq(_r2_T_12, _r2_T)
node _r2_T_44 = mux(_r2_T_43, UInt<1>(0h1), _r2_T_41)
node _r2_T_45 = mux(_r2_T_43, UInt<2>(0h3), _r2_T_42)
node _r2_T_46 = eq(_r2_T_10, _r2_T)
node _r2_T_47 = mux(_r2_T_46, UInt<1>(0h1), _r2_T_44)
node _r2_T_48 = mux(_r2_T_46, UInt<2>(0h2), _r2_T_45)
node _r2_T_49 = eq(_r2_T_8, _r2_T)
node _r2_T_50 = mux(_r2_T_49, UInt<1>(0h1), _r2_T_47)
node _r2_T_51 = mux(_r2_T_49, UInt<2>(0h3), _r2_T_48)
node _r2_T_52 = eq(_r2_T_6, _r2_T)
node _r2_T_53 = mux(_r2_T_52, UInt<1>(0h1), _r2_T_50)
node _r2_T_54 = mux(_r2_T_52, UInt<2>(0h1), _r2_T_51)
node _r2_T_55 = eq(_r2_T_4, _r2_T)
node _r2_T_56 = mux(_r2_T_55, UInt<1>(0h1), _r2_T_53)
node _r2_T_57 = mux(_r2_T_55, UInt<2>(0h2), _r2_T_54)
node _r2_T_58 = eq(_r2_T_2, _r2_T)
node r2_1 = mux(_r2_T_58, UInt<1>(0h1), _r2_T_56)
node r2_2 = mux(_r2_T_58, UInt<2>(0h3), _r2_T_57)
node _needs_second_acq_T = eq(io.req_bits.cmd, UInt<1>(0h1))
node _needs_second_acq_T_1 = eq(io.req_bits.cmd, UInt<5>(0h11))
node _needs_second_acq_T_2 = or(_needs_second_acq_T, _needs_second_acq_T_1)
node _needs_second_acq_T_3 = eq(io.req_bits.cmd, UInt<3>(0h7))
node _needs_second_acq_T_4 = or(_needs_second_acq_T_2, _needs_second_acq_T_3)
node _needs_second_acq_T_5 = eq(io.req_bits.cmd, UInt<3>(0h4))
node _needs_second_acq_T_6 = eq(io.req_bits.cmd, UInt<4>(0h9))
node _needs_second_acq_T_7 = eq(io.req_bits.cmd, UInt<4>(0ha))
node _needs_second_acq_T_8 = eq(io.req_bits.cmd, UInt<4>(0hb))
node _needs_second_acq_T_9 = or(_needs_second_acq_T_5, _needs_second_acq_T_6)
node _needs_second_acq_T_10 = or(_needs_second_acq_T_9, _needs_second_acq_T_7)
node _needs_second_acq_T_11 = or(_needs_second_acq_T_10, _needs_second_acq_T_8)
node _needs_second_acq_T_12 = eq(io.req_bits.cmd, UInt<4>(0h8))
node _needs_second_acq_T_13 = eq(io.req_bits.cmd, UInt<4>(0hc))
node _needs_second_acq_T_14 = eq(io.req_bits.cmd, UInt<4>(0hd))
node _needs_second_acq_T_15 = eq(io.req_bits.cmd, UInt<4>(0he))
node _needs_second_acq_T_16 = eq(io.req_bits.cmd, UInt<4>(0hf))
node _needs_second_acq_T_17 = or(_needs_second_acq_T_12, _needs_second_acq_T_13)
node _needs_second_acq_T_18 = or(_needs_second_acq_T_17, _needs_second_acq_T_14)
node _needs_second_acq_T_19 = or(_needs_second_acq_T_18, _needs_second_acq_T_15)
node _needs_second_acq_T_20 = or(_needs_second_acq_T_19, _needs_second_acq_T_16)
node _needs_second_acq_T_21 = or(_needs_second_acq_T_11, _needs_second_acq_T_20)
node _needs_second_acq_T_22 = or(_needs_second_acq_T_4, _needs_second_acq_T_21)
node _needs_second_acq_T_23 = eq(io.req_bits.cmd, UInt<2>(0h3))
node _needs_second_acq_T_24 = or(_needs_second_acq_T_22, _needs_second_acq_T_23)
node _needs_second_acq_T_25 = eq(io.req_bits.cmd, UInt<3>(0h6))
node _needs_second_acq_T_26 = or(_needs_second_acq_T_24, _needs_second_acq_T_25)
node _needs_second_acq_T_27 = eq(req.cmd, UInt<1>(0h1))
node _needs_second_acq_T_28 = eq(req.cmd, UInt<5>(0h11))
node _needs_second_acq_T_29 = or(_needs_second_acq_T_27, _needs_second_acq_T_28)
node _needs_second_acq_T_30 = eq(req.cmd, UInt<3>(0h7))
node _needs_second_acq_T_31 = or(_needs_second_acq_T_29, _needs_second_acq_T_30)
node _needs_second_acq_T_32 = eq(req.cmd, UInt<3>(0h4))
node _needs_second_acq_T_33 = eq(req.cmd, UInt<4>(0h9))
node _needs_second_acq_T_34 = eq(req.cmd, UInt<4>(0ha))
node _needs_second_acq_T_35 = eq(req.cmd, UInt<4>(0hb))
node _needs_second_acq_T_36 = or(_needs_second_acq_T_32, _needs_second_acq_T_33)
node _needs_second_acq_T_37 = or(_needs_second_acq_T_36, _needs_second_acq_T_34)
node _needs_second_acq_T_38 = or(_needs_second_acq_T_37, _needs_second_acq_T_35)
node _needs_second_acq_T_39 = eq(req.cmd, UInt<4>(0h8))
node _needs_second_acq_T_40 = eq(req.cmd, UInt<4>(0hc))
node _needs_second_acq_T_41 = eq(req.cmd, UInt<4>(0hd))
node _needs_second_acq_T_42 = eq(req.cmd, UInt<4>(0he))
node _needs_second_acq_T_43 = eq(req.cmd, UInt<4>(0hf))
node _needs_second_acq_T_44 = or(_needs_second_acq_T_39, _needs_second_acq_T_40)
node _needs_second_acq_T_45 = or(_needs_second_acq_T_44, _needs_second_acq_T_41)
node _needs_second_acq_T_46 = or(_needs_second_acq_T_45, _needs_second_acq_T_42)
node _needs_second_acq_T_47 = or(_needs_second_acq_T_46, _needs_second_acq_T_43)
node _needs_second_acq_T_48 = or(_needs_second_acq_T_38, _needs_second_acq_T_47)
node _needs_second_acq_T_49 = or(_needs_second_acq_T_31, _needs_second_acq_T_48)
node _needs_second_acq_T_50 = eq(req.cmd, UInt<2>(0h3))
node _needs_second_acq_T_51 = or(_needs_second_acq_T_49, _needs_second_acq_T_50)
node _needs_second_acq_T_52 = eq(req.cmd, UInt<3>(0h6))
node _needs_second_acq_T_53 = or(_needs_second_acq_T_51, _needs_second_acq_T_52)
node _needs_second_acq_T_54 = eq(_needs_second_acq_T_53, UInt<1>(0h0))
node cmd_requires_second_acquire = and(_needs_second_acq_T_26, _needs_second_acq_T_54)
node is_hit_again = and(r1_1, r2_1)
node _dirties_cat_T = eq(io.req_bits.cmd, UInt<1>(0h1))
node _dirties_cat_T_1 = eq(io.req_bits.cmd, UInt<5>(0h11))
node _dirties_cat_T_2 = or(_dirties_cat_T, _dirties_cat_T_1)
node _dirties_cat_T_3 = eq(io.req_bits.cmd, UInt<3>(0h7))
node _dirties_cat_T_4 = or(_dirties_cat_T_2, _dirties_cat_T_3)
node _dirties_cat_T_5 = eq(io.req_bits.cmd, UInt<3>(0h4))
node _dirties_cat_T_6 = eq(io.req_bits.cmd, UInt<4>(0h9))
node _dirties_cat_T_7 = eq(io.req_bits.cmd, UInt<4>(0ha))
node _dirties_cat_T_8 = eq(io.req_bits.cmd, UInt<4>(0hb))
node _dirties_cat_T_9 = or(_dirties_cat_T_5, _dirties_cat_T_6)
node _dirties_cat_T_10 = or(_dirties_cat_T_9, _dirties_cat_T_7)
node _dirties_cat_T_11 = or(_dirties_cat_T_10, _dirties_cat_T_8)
node _dirties_cat_T_12 = eq(io.req_bits.cmd, UInt<4>(0h8))
node _dirties_cat_T_13 = eq(io.req_bits.cmd, UInt<4>(0hc))
node _dirties_cat_T_14 = eq(io.req_bits.cmd, UInt<4>(0hd))
node _dirties_cat_T_15 = eq(io.req_bits.cmd, UInt<4>(0he))
node _dirties_cat_T_16 = eq(io.req_bits.cmd, UInt<4>(0hf))
node _dirties_cat_T_17 = or(_dirties_cat_T_12, _dirties_cat_T_13)
node _dirties_cat_T_18 = or(_dirties_cat_T_17, _dirties_cat_T_14)
node _dirties_cat_T_19 = or(_dirties_cat_T_18, _dirties_cat_T_15)
node _dirties_cat_T_20 = or(_dirties_cat_T_19, _dirties_cat_T_16)
node _dirties_cat_T_21 = or(_dirties_cat_T_11, _dirties_cat_T_20)
node _dirties_cat_T_22 = or(_dirties_cat_T_4, _dirties_cat_T_21)
node _dirties_cat_T_23 = eq(io.req_bits.cmd, UInt<1>(0h1))
node _dirties_cat_T_24 = eq(io.req_bits.cmd, UInt<5>(0h11))
node _dirties_cat_T_25 = or(_dirties_cat_T_23, _dirties_cat_T_24)
node _dirties_cat_T_26 = eq(io.req_bits.cmd, UInt<3>(0h7))
node _dirties_cat_T_27 = or(_dirties_cat_T_25, _dirties_cat_T_26)
node _dirties_cat_T_28 = eq(io.req_bits.cmd, UInt<3>(0h4))
node _dirties_cat_T_29 = eq(io.req_bits.cmd, UInt<4>(0h9))
node _dirties_cat_T_30 = eq(io.req_bits.cmd, UInt<4>(0ha))
node _dirties_cat_T_31 = eq(io.req_bits.cmd, UInt<4>(0hb))
node _dirties_cat_T_32 = or(_dirties_cat_T_28, _dirties_cat_T_29)
node _dirties_cat_T_33 = or(_dirties_cat_T_32, _dirties_cat_T_30)
node _dirties_cat_T_34 = or(_dirties_cat_T_33, _dirties_cat_T_31)
node _dirties_cat_T_35 = eq(io.req_bits.cmd, UInt<4>(0h8))
node _dirties_cat_T_36 = eq(io.req_bits.cmd, UInt<4>(0hc))
node _dirties_cat_T_37 = eq(io.req_bits.cmd, UInt<4>(0hd))
node _dirties_cat_T_38 = eq(io.req_bits.cmd, UInt<4>(0he))
node _dirties_cat_T_39 = eq(io.req_bits.cmd, UInt<4>(0hf))
node _dirties_cat_T_40 = or(_dirties_cat_T_35, _dirties_cat_T_36)
node _dirties_cat_T_41 = or(_dirties_cat_T_40, _dirties_cat_T_37)
node _dirties_cat_T_42 = or(_dirties_cat_T_41, _dirties_cat_T_38)
node _dirties_cat_T_43 = or(_dirties_cat_T_42, _dirties_cat_T_39)
node _dirties_cat_T_44 = or(_dirties_cat_T_34, _dirties_cat_T_43)
node _dirties_cat_T_45 = or(_dirties_cat_T_27, _dirties_cat_T_44)
node _dirties_cat_T_46 = eq(io.req_bits.cmd, UInt<2>(0h3))
node _dirties_cat_T_47 = or(_dirties_cat_T_45, _dirties_cat_T_46)
node _dirties_cat_T_48 = eq(io.req_bits.cmd, UInt<3>(0h6))
node _dirties_cat_T_49 = or(_dirties_cat_T_47, _dirties_cat_T_48)
node dirties_cat = cat(_dirties_cat_T_22, _dirties_cat_T_49)
node _dirties_T = cat(UInt<1>(0h1), UInt<1>(0h1))
node dirties = eq(dirties_cat, _dirties_T)
node biggest_grow_param = mux(dirties, r2_2, r1_2)
wire dirtier_coh : { state : UInt<2>}
connect dirtier_coh.state, biggest_grow_param
node dirtier_cmd = mux(dirties, io.req_bits.cmd, req.cmd)
node _r_beats1_decode_T = dshl(UInt<12>(0hfff), io.mem_grant.bits.size)
node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0)
node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1)
node r_beats1_decode = shr(_r_beats1_decode_T_2, 3)
node r_beats1_opdata = bits(io.mem_grant.bits.opcode, 0, 0)
node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0))
regreset r_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _r_counter1_T = sub(r_counter, UInt<1>(0h1))
node r_counter1 = tail(_r_counter1_T, 1)
node r_1_1 = eq(r_counter, UInt<1>(0h0))
node _r_last_T = eq(r_counter, UInt<1>(0h1))
node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0))
node r_2 = or(_r_last_T, _r_last_T_1)
node refill_done = and(r_2, io.mem_grant.valid)
node _r_count_T = not(r_counter1)
node r_4 = and(r_beats1, _r_count_T)
when io.mem_grant.valid :
node _r_counter_T = mux(r_1_1, r_beats1, r_counter1)
connect r_counter, _r_counter_T
node refill_address_inc = shl(r_4, 3)
node _sec_rdy_T = eq(state, UInt<4>(0h1))
node _sec_rdy_T_1 = eq(state, UInt<4>(0h2))
node _sec_rdy_T_2 = eq(state, UInt<4>(0h3))
node _sec_rdy_T_3 = or(_sec_rdy_T, _sec_rdy_T_1)
node _sec_rdy_T_4 = or(_sec_rdy_T_3, _sec_rdy_T_2)
node _sec_rdy_T_5 = eq(state, UInt<4>(0h4))
node _sec_rdy_T_6 = eq(state, UInt<4>(0h5))
node _sec_rdy_T_7 = or(_sec_rdy_T_5, _sec_rdy_T_6)
node _sec_rdy_T_8 = eq(cmd_requires_second_acquire, UInt<1>(0h0))
node _sec_rdy_T_9 = and(_sec_rdy_T_7, _sec_rdy_T_8)
node _sec_rdy_T_10 = eq(refill_done, UInt<1>(0h0))
node _sec_rdy_T_11 = and(_sec_rdy_T_9, _sec_rdy_T_10)
node _sec_rdy_T_12 = or(_sec_rdy_T_4, _sec_rdy_T_11)
node sec_rdy = and(idx_match, _sec_rdy_T_12)
inst rpq of Queue16_ShuttleMSHRReq_1
connect rpq.clock, clock
connect rpq.reset, reset
node _rpq_io_enq_valid_T = and(io.req_pri_val, io.req_pri_rdy)
node _rpq_io_enq_valid_T_1 = and(io.req_sec_val, sec_rdy)
node _rpq_io_enq_valid_T_2 = or(_rpq_io_enq_valid_T, _rpq_io_enq_valid_T_1)
node _rpq_io_enq_valid_T_3 = eq(io.req_bits.cmd, UInt<2>(0h2))
node _rpq_io_enq_valid_T_4 = eq(io.req_bits.cmd, UInt<2>(0h3))
node _rpq_io_enq_valid_T_5 = or(_rpq_io_enq_valid_T_3, _rpq_io_enq_valid_T_4)
node _rpq_io_enq_valid_T_6 = eq(_rpq_io_enq_valid_T_5, UInt<1>(0h0))
node _rpq_io_enq_valid_T_7 = and(_rpq_io_enq_valid_T_2, _rpq_io_enq_valid_T_6)
connect rpq.io.enq.valid, _rpq_io_enq_valid_T_7
connect rpq.io.enq.bits.sdq_id, io.req_bits.sdq_id
connect rpq.io.enq.bits.way_en, io.req_bits.way_en
connect rpq.io.enq.bits.old_meta.tag, io.req_bits.old_meta.tag
connect rpq.io.enq.bits.old_meta.coh.state, io.req_bits.old_meta.coh.state
connect rpq.io.enq.bits.tag_match, io.req_bits.tag_match
connect rpq.io.enq.bits.mask, io.req_bits.mask
connect rpq.io.enq.bits.data, io.req_bits.data
connect rpq.io.enq.bits.signed, io.req_bits.signed
connect rpq.io.enq.bits.size, io.req_bits.size
connect rpq.io.enq.bits.cmd, io.req_bits.cmd
connect rpq.io.enq.bits.tag, io.req_bits.tag
connect rpq.io.enq.bits.addr, io.req_bits.addr
node _rpq_io_deq_ready_T = eq(state, UInt<4>(0h8))
node _rpq_io_deq_ready_T_1 = and(io.replay.ready, _rpq_io_deq_ready_T)
node _rpq_io_deq_ready_T_2 = eq(state, UInt<4>(0h0))
node _rpq_io_deq_ready_T_3 = or(_rpq_io_deq_ready_T_1, _rpq_io_deq_ready_T_2)
connect rpq.io.deq.ready, _rpq_io_deq_ready_T_3
reg acked : UInt<1>, clock
when io.mem_grant.valid :
connect acked, UInt<1>(0h1)
node _T = eq(state, UInt<4>(0h8))
node _T_1 = eq(rpq.io.deq.valid, UInt<1>(0h0))
node _T_2 = and(_T, _T_1)
when _T_2 :
connect state, UInt<4>(0h0)
node _T_3 = eq(state, UInt<4>(0h7))
when _T_3 :
connect state, UInt<4>(0h8)
node _T_4 = eq(state, UInt<4>(0h6))
node _T_5 = and(_T_4, io.meta_write.ready)
when _T_5 :
connect state, UInt<4>(0h7)
node _T_6 = eq(state, UInt<4>(0h5))
node _T_7 = and(_T_6, refill_done)
when _T_7 :
connect new_coh, coh_on_grant
connect state, UInt<4>(0h6)
node _T_8 = and(io.mem_acquire.ready, io.mem_acquire.valid)
when _T_8 :
connect state, UInt<4>(0h5)
node _T_9 = eq(state, UInt<4>(0h3))
node _T_10 = and(_T_9, io.meta_write.ready)
when _T_10 :
connect state, UInt<4>(0h4)
node _T_11 = eq(state, UInt<4>(0h2))
node _T_12 = and(_T_11, io.wb_req.ready)
node _T_13 = and(_T_12, acked)
when _T_13 :
connect state, UInt<4>(0h3)
node _T_14 = and(io.wb_req.ready, io.wb_req.valid)
when _T_14 :
connect state, UInt<4>(0h2)
node _T_15 = and(io.req_sec_val, io.req_sec_rdy)
when _T_15 :
connect req.cmd, dirtier_cmd
when is_hit_again :
connect new_coh, dirtier_coh
node _T_16 = and(io.req_pri_val, io.req_pri_rdy)
when _T_16 :
connect req, io.req_bits
connect acked, UInt<1>(0h0)
node _needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10))
node _needs_wb_r_T_1 = mux(_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2))
node _needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _needs_wb_r_T_3 = mux(_needs_wb_r_T_2, UInt<2>(0h1), _needs_wb_r_T_1)
node _needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _needs_wb_r_T_5 = mux(_needs_wb_r_T_4, UInt<2>(0h0), _needs_wb_r_T_3)
node _needs_wb_r_T_6 = cat(_needs_wb_r_T_5, io.req_bits.old_meta.coh.state)
node _needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _needs_wb_r_T_19 = eq(_needs_wb_r_T_18, _needs_wb_r_T_6)
node _needs_wb_r_T_20 = mux(_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0))
node _needs_wb_r_T_21 = mux(_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0))
node _needs_wb_r_T_22 = mux(_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0))
node _needs_wb_r_T_23 = eq(_needs_wb_r_T_17, _needs_wb_r_T_6)
node _needs_wb_r_T_24 = mux(_needs_wb_r_T_23, UInt<1>(0h0), _needs_wb_r_T_20)
node _needs_wb_r_T_25 = mux(_needs_wb_r_T_23, UInt<3>(0h2), _needs_wb_r_T_21)
node _needs_wb_r_T_26 = mux(_needs_wb_r_T_23, UInt<2>(0h0), _needs_wb_r_T_22)
node _needs_wb_r_T_27 = eq(_needs_wb_r_T_16, _needs_wb_r_T_6)
node _needs_wb_r_T_28 = mux(_needs_wb_r_T_27, UInt<1>(0h0), _needs_wb_r_T_24)
node _needs_wb_r_T_29 = mux(_needs_wb_r_T_27, UInt<3>(0h1), _needs_wb_r_T_25)
node _needs_wb_r_T_30 = mux(_needs_wb_r_T_27, UInt<2>(0h0), _needs_wb_r_T_26)
node _needs_wb_r_T_31 = eq(_needs_wb_r_T_15, _needs_wb_r_T_6)
node _needs_wb_r_T_32 = mux(_needs_wb_r_T_31, UInt<1>(0h1), _needs_wb_r_T_28)
node _needs_wb_r_T_33 = mux(_needs_wb_r_T_31, UInt<3>(0h1), _needs_wb_r_T_29)
node _needs_wb_r_T_34 = mux(_needs_wb_r_T_31, UInt<2>(0h0), _needs_wb_r_T_30)
node _needs_wb_r_T_35 = eq(_needs_wb_r_T_14, _needs_wb_r_T_6)
node _needs_wb_r_T_36 = mux(_needs_wb_r_T_35, UInt<1>(0h0), _needs_wb_r_T_32)
node _needs_wb_r_T_37 = mux(_needs_wb_r_T_35, UInt<3>(0h5), _needs_wb_r_T_33)
node _needs_wb_r_T_38 = mux(_needs_wb_r_T_35, UInt<2>(0h0), _needs_wb_r_T_34)
node _needs_wb_r_T_39 = eq(_needs_wb_r_T_13, _needs_wb_r_T_6)
node _needs_wb_r_T_40 = mux(_needs_wb_r_T_39, UInt<1>(0h0), _needs_wb_r_T_36)
node _needs_wb_r_T_41 = mux(_needs_wb_r_T_39, UInt<3>(0h4), _needs_wb_r_T_37)
node _needs_wb_r_T_42 = mux(_needs_wb_r_T_39, UInt<2>(0h1), _needs_wb_r_T_38)
node _needs_wb_r_T_43 = eq(_needs_wb_r_T_12, _needs_wb_r_T_6)
node _needs_wb_r_T_44 = mux(_needs_wb_r_T_43, UInt<1>(0h0), _needs_wb_r_T_40)
node _needs_wb_r_T_45 = mux(_needs_wb_r_T_43, UInt<3>(0h0), _needs_wb_r_T_41)
node _needs_wb_r_T_46 = mux(_needs_wb_r_T_43, UInt<2>(0h1), _needs_wb_r_T_42)
node _needs_wb_r_T_47 = eq(_needs_wb_r_T_11, _needs_wb_r_T_6)
node _needs_wb_r_T_48 = mux(_needs_wb_r_T_47, UInt<1>(0h1), _needs_wb_r_T_44)
node _needs_wb_r_T_49 = mux(_needs_wb_r_T_47, UInt<3>(0h0), _needs_wb_r_T_45)
node _needs_wb_r_T_50 = mux(_needs_wb_r_T_47, UInt<2>(0h1), _needs_wb_r_T_46)
node _needs_wb_r_T_51 = eq(_needs_wb_r_T_10, _needs_wb_r_T_6)
node _needs_wb_r_T_52 = mux(_needs_wb_r_T_51, UInt<1>(0h0), _needs_wb_r_T_48)
node _needs_wb_r_T_53 = mux(_needs_wb_r_T_51, UInt<3>(0h5), _needs_wb_r_T_49)
node _needs_wb_r_T_54 = mux(_needs_wb_r_T_51, UInt<2>(0h0), _needs_wb_r_T_50)
node _needs_wb_r_T_55 = eq(_needs_wb_r_T_9, _needs_wb_r_T_6)
node _needs_wb_r_T_56 = mux(_needs_wb_r_T_55, UInt<1>(0h0), _needs_wb_r_T_52)
node _needs_wb_r_T_57 = mux(_needs_wb_r_T_55, UInt<3>(0h4), _needs_wb_r_T_53)
node _needs_wb_r_T_58 = mux(_needs_wb_r_T_55, UInt<2>(0h1), _needs_wb_r_T_54)
node _needs_wb_r_T_59 = eq(_needs_wb_r_T_8, _needs_wb_r_T_6)
node _needs_wb_r_T_60 = mux(_needs_wb_r_T_59, UInt<1>(0h0), _needs_wb_r_T_56)
node _needs_wb_r_T_61 = mux(_needs_wb_r_T_59, UInt<3>(0h3), _needs_wb_r_T_57)
node _needs_wb_r_T_62 = mux(_needs_wb_r_T_59, UInt<2>(0h2), _needs_wb_r_T_58)
node _needs_wb_r_T_63 = eq(_needs_wb_r_T_7, _needs_wb_r_T_6)
node needs_wb = mux(_needs_wb_r_T_63, UInt<1>(0h1), _needs_wb_r_T_60)
node needs_wb_r_2 = mux(_needs_wb_r_T_63, UInt<3>(0h3), _needs_wb_r_T_61)
node needs_wb_r_3 = mux(_needs_wb_r_T_63, UInt<2>(0h2), _needs_wb_r_T_62)
wire needs_wb_meta : { state : UInt<2>}
connect needs_wb_meta.state, needs_wb_r_3
node _r_c_cat_T = eq(io.req_bits.cmd, UInt<1>(0h1))
node _r_c_cat_T_1 = eq(io.req_bits.cmd, UInt<5>(0h11))
node _r_c_cat_T_2 = or(_r_c_cat_T, _r_c_cat_T_1)
node _r_c_cat_T_3 = eq(io.req_bits.cmd, UInt<3>(0h7))
node _r_c_cat_T_4 = or(_r_c_cat_T_2, _r_c_cat_T_3)
node _r_c_cat_T_5 = eq(io.req_bits.cmd, UInt<3>(0h4))
node _r_c_cat_T_6 = eq(io.req_bits.cmd, UInt<4>(0h9))
node _r_c_cat_T_7 = eq(io.req_bits.cmd, UInt<4>(0ha))
node _r_c_cat_T_8 = eq(io.req_bits.cmd, UInt<4>(0hb))
node _r_c_cat_T_9 = or(_r_c_cat_T_5, _r_c_cat_T_6)
node _r_c_cat_T_10 = or(_r_c_cat_T_9, _r_c_cat_T_7)
node _r_c_cat_T_11 = or(_r_c_cat_T_10, _r_c_cat_T_8)
node _r_c_cat_T_12 = eq(io.req_bits.cmd, UInt<4>(0h8))
node _r_c_cat_T_13 = eq(io.req_bits.cmd, UInt<4>(0hc))
node _r_c_cat_T_14 = eq(io.req_bits.cmd, UInt<4>(0hd))
node _r_c_cat_T_15 = eq(io.req_bits.cmd, UInt<4>(0he))
node _r_c_cat_T_16 = eq(io.req_bits.cmd, UInt<4>(0hf))
node _r_c_cat_T_17 = or(_r_c_cat_T_12, _r_c_cat_T_13)
node _r_c_cat_T_18 = or(_r_c_cat_T_17, _r_c_cat_T_14)
node _r_c_cat_T_19 = or(_r_c_cat_T_18, _r_c_cat_T_15)
node _r_c_cat_T_20 = or(_r_c_cat_T_19, _r_c_cat_T_16)
node _r_c_cat_T_21 = or(_r_c_cat_T_11, _r_c_cat_T_20)
node _r_c_cat_T_22 = or(_r_c_cat_T_4, _r_c_cat_T_21)
node _r_c_cat_T_23 = eq(io.req_bits.cmd, UInt<1>(0h1))
node _r_c_cat_T_24 = eq(io.req_bits.cmd, UInt<5>(0h11))
node _r_c_cat_T_25 = or(_r_c_cat_T_23, _r_c_cat_T_24)
node _r_c_cat_T_26 = eq(io.req_bits.cmd, UInt<3>(0h7))
node _r_c_cat_T_27 = or(_r_c_cat_T_25, _r_c_cat_T_26)
node _r_c_cat_T_28 = eq(io.req_bits.cmd, UInt<3>(0h4))
node _r_c_cat_T_29 = eq(io.req_bits.cmd, UInt<4>(0h9))
node _r_c_cat_T_30 = eq(io.req_bits.cmd, UInt<4>(0ha))
node _r_c_cat_T_31 = eq(io.req_bits.cmd, UInt<4>(0hb))
node _r_c_cat_T_32 = or(_r_c_cat_T_28, _r_c_cat_T_29)
node _r_c_cat_T_33 = or(_r_c_cat_T_32, _r_c_cat_T_30)
node _r_c_cat_T_34 = or(_r_c_cat_T_33, _r_c_cat_T_31)
node _r_c_cat_T_35 = eq(io.req_bits.cmd, UInt<4>(0h8))
node _r_c_cat_T_36 = eq(io.req_bits.cmd, UInt<4>(0hc))
node _r_c_cat_T_37 = eq(io.req_bits.cmd, UInt<4>(0hd))
node _r_c_cat_T_38 = eq(io.req_bits.cmd, UInt<4>(0he))
node _r_c_cat_T_39 = eq(io.req_bits.cmd, UInt<4>(0hf))
node _r_c_cat_T_40 = or(_r_c_cat_T_35, _r_c_cat_T_36)
node _r_c_cat_T_41 = or(_r_c_cat_T_40, _r_c_cat_T_37)
node _r_c_cat_T_42 = or(_r_c_cat_T_41, _r_c_cat_T_38)
node _r_c_cat_T_43 = or(_r_c_cat_T_42, _r_c_cat_T_39)
node _r_c_cat_T_44 = or(_r_c_cat_T_34, _r_c_cat_T_43)
node _r_c_cat_T_45 = or(_r_c_cat_T_27, _r_c_cat_T_44)
node _r_c_cat_T_46 = eq(io.req_bits.cmd, UInt<2>(0h3))
node _r_c_cat_T_47 = or(_r_c_cat_T_45, _r_c_cat_T_46)
node _r_c_cat_T_48 = eq(io.req_bits.cmd, UInt<3>(0h6))
node _r_c_cat_T_49 = or(_r_c_cat_T_47, _r_c_cat_T_48)
node r_c = cat(_r_c_cat_T_22, _r_c_cat_T_49)
node _r_T_64 = cat(r_c, io.req_bits.old_meta.coh.state)
node _r_T_65 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_66 = cat(_r_T_65, UInt<2>(0h3))
node _r_T_67 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_68 = cat(_r_T_67, UInt<2>(0h2))
node _r_T_69 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_70 = cat(_r_T_69, UInt<2>(0h1))
node _r_T_71 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_72 = cat(_r_T_71, UInt<2>(0h3))
node _r_T_73 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_74 = cat(_r_T_73, UInt<2>(0h2))
node _r_T_75 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_76 = cat(_r_T_75, UInt<2>(0h3))
node _r_T_77 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_78 = cat(_r_T_77, UInt<2>(0h2))
node _r_T_79 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_80 = cat(_r_T_79, UInt<2>(0h0))
node _r_T_81 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_82 = cat(_r_T_81, UInt<2>(0h1))
node _r_T_83 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_84 = cat(_r_T_83, UInt<2>(0h0))
node _r_T_85 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_86 = cat(_r_T_85, UInt<2>(0h1))
node _r_T_87 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_88 = cat(_r_T_87, UInt<2>(0h0))
node _r_T_89 = eq(_r_T_88, _r_T_64)
node _r_T_90 = mux(_r_T_89, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_91 = mux(_r_T_89, UInt<2>(0h1), UInt<1>(0h0))
node _r_T_92 = eq(_r_T_86, _r_T_64)
node _r_T_93 = mux(_r_T_92, UInt<1>(0h0), _r_T_90)
node _r_T_94 = mux(_r_T_92, UInt<2>(0h2), _r_T_91)
node _r_T_95 = eq(_r_T_84, _r_T_64)
node _r_T_96 = mux(_r_T_95, UInt<1>(0h0), _r_T_93)
node _r_T_97 = mux(_r_T_95, UInt<2>(0h1), _r_T_94)
node _r_T_98 = eq(_r_T_82, _r_T_64)
node _r_T_99 = mux(_r_T_98, UInt<1>(0h0), _r_T_96)
node _r_T_100 = mux(_r_T_98, UInt<2>(0h2), _r_T_97)
node _r_T_101 = eq(_r_T_80, _r_T_64)
node _r_T_102 = mux(_r_T_101, UInt<1>(0h0), _r_T_99)
node _r_T_103 = mux(_r_T_101, UInt<2>(0h0), _r_T_100)
node _r_T_104 = eq(_r_T_78, _r_T_64)
node _r_T_105 = mux(_r_T_104, UInt<1>(0h1), _r_T_102)
node _r_T_106 = mux(_r_T_104, UInt<2>(0h3), _r_T_103)
node _r_T_107 = eq(_r_T_76, _r_T_64)
node _r_T_108 = mux(_r_T_107, UInt<1>(0h1), _r_T_105)
node _r_T_109 = mux(_r_T_107, UInt<2>(0h3), _r_T_106)
node _r_T_110 = eq(_r_T_74, _r_T_64)
node _r_T_111 = mux(_r_T_110, UInt<1>(0h1), _r_T_108)
node _r_T_112 = mux(_r_T_110, UInt<2>(0h2), _r_T_109)
node _r_T_113 = eq(_r_T_72, _r_T_64)
node _r_T_114 = mux(_r_T_113, UInt<1>(0h1), _r_T_111)
node _r_T_115 = mux(_r_T_113, UInt<2>(0h3), _r_T_112)
node _r_T_116 = eq(_r_T_70, _r_T_64)
node _r_T_117 = mux(_r_T_116, UInt<1>(0h1), _r_T_114)
node _r_T_118 = mux(_r_T_116, UInt<2>(0h1), _r_T_115)
node _r_T_119 = eq(_r_T_68, _r_T_64)
node _r_T_120 = mux(_r_T_119, UInt<1>(0h1), _r_T_117)
node _r_T_121 = mux(_r_T_119, UInt<2>(0h2), _r_T_118)
node _r_T_122 = eq(_r_T_66, _r_T_64)
node is_hit = mux(_r_T_122, UInt<1>(0h1), _r_T_120)
node r_2_1 = mux(_r_T_122, UInt<2>(0h3), _r_T_121)
wire coh_on_hit : { state : UInt<2>}
connect coh_on_hit.state, r_2_1
when io.req_bits.tag_match :
when is_hit :
connect new_coh, coh_on_hit
connect state, UInt<4>(0h6)
else :
connect new_coh, io.req_bits.old_meta.coh
connect state, UInt<4>(0h4)
else :
wire new_coh_meta_1 : { state : UInt<2>}
connect new_coh_meta_1.state, UInt<2>(0h0)
connect new_coh, new_coh_meta_1
node _state_T = mux(needs_wb, UInt<4>(0h1), UInt<4>(0h3))
connect state, _state_T
inst grantackq of Queue1_TLBundleE_a32d64s3k3z4c_1
connect grantackq.clock, clock
connect grantackq.reset, reset
node _can_finish_T = eq(state, UInt<4>(0h0))
node _can_finish_T_1 = eq(state, UInt<4>(0h4))
node can_finish = or(_can_finish_T, _can_finish_T_1)
node _grantackq_io_enq_valid_T = bits(io.mem_grant.bits.opcode, 2, 2)
node _grantackq_io_enq_valid_T_1 = bits(io.mem_grant.bits.opcode, 1, 1)
node _grantackq_io_enq_valid_T_2 = eq(_grantackq_io_enq_valid_T_1, UInt<1>(0h0))
node _grantackq_io_enq_valid_T_3 = and(_grantackq_io_enq_valid_T, _grantackq_io_enq_valid_T_2)
node _grantackq_io_enq_valid_T_4 = and(refill_done, _grantackq_io_enq_valid_T_3)
connect grantackq.io.enq.valid, _grantackq_io_enq_valid_T_4
wire grantackq_io_enq_bits_e : { sink : UInt<3>}
connect grantackq_io_enq_bits_e.sink, io.mem_grant.bits.sink
connect grantackq.io.enq.bits.sink, grantackq_io_enq_bits_e.sink
node _io_mem_finish_valid_T = and(grantackq.io.deq.valid, can_finish)
connect io.mem_finish.valid, _io_mem_finish_valid_T
connect io.mem_finish.bits, grantackq.io.deq.bits
node _grantackq_io_deq_ready_T = and(io.mem_finish.ready, can_finish)
connect grantackq.io.deq.ready, _grantackq_io_deq_ready_T
node _io_idx_match_T = neq(state, UInt<4>(0h0))
node _io_idx_match_T_1 = and(_io_idx_match_T, idx_match)
connect io.idx_match, _io_idx_match_T_1
connect io.refill.way_en, req.way_en
node _io_refill_addr_T = or(req_block_addr, refill_address_inc)
connect io.refill.addr, _io_refill_addr_T
connect io.tag, req_tag
node _io_req_pri_rdy_T = eq(state, UInt<4>(0h0))
connect io.req_pri_rdy, _io_req_pri_rdy_T
node _io_req_sec_rdy_T = and(sec_rdy, rpq.io.enq.ready)
connect io.req_sec_rdy, _io_req_sec_rdy_T
regreset meta_hazard : UInt<2>, clock, reset, UInt<2>(0h0)
node _T_17 = neq(meta_hazard, UInt<1>(0h0))
when _T_17 :
node _meta_hazard_T = add(meta_hazard, UInt<1>(0h1))
node _meta_hazard_T_1 = tail(_meta_hazard_T, 1)
connect meta_hazard, _meta_hazard_T_1
node _T_18 = and(io.meta_write.ready, io.meta_write.valid)
when _T_18 :
connect meta_hazard, UInt<1>(0h1)
node _io_probe_rdy_T = neq(state, UInt<4>(0h0))
node _io_probe_rdy_T_1 = and(_io_probe_rdy_T, probe_idx_match)
node _io_probe_rdy_T_2 = eq(_io_probe_rdy_T_1, UInt<1>(0h0))
node _io_probe_rdy_T_3 = eq(state, UInt<4>(0h1))
node _io_probe_rdy_T_4 = eq(state, UInt<4>(0h2))
node _io_probe_rdy_T_5 = eq(state, UInt<4>(0h3))
node _io_probe_rdy_T_6 = or(_io_probe_rdy_T_3, _io_probe_rdy_T_4)
node _io_probe_rdy_T_7 = or(_io_probe_rdy_T_6, _io_probe_rdy_T_5)
node _io_probe_rdy_T_8 = eq(_io_probe_rdy_T_7, UInt<1>(0h0))
node _io_probe_rdy_T_9 = eq(meta_hazard, UInt<1>(0h0))
node _io_probe_rdy_T_10 = and(_io_probe_rdy_T_8, _io_probe_rdy_T_9)
node _io_probe_rdy_T_11 = or(_io_probe_rdy_T_2, _io_probe_rdy_T_10)
connect io.probe_rdy, _io_probe_rdy_T_11
node _io_meta_write_valid_T = eq(state, UInt<4>(0h6))
node _io_meta_write_valid_T_1 = eq(state, UInt<4>(0h3))
node _io_meta_write_valid_T_2 = or(_io_meta_write_valid_T, _io_meta_write_valid_T_1)
connect io.meta_write.valid, _io_meta_write_valid_T_2
connect io.meta_write.bits.idx, req_idx
connect io.meta_write.bits.tag, io.tag
node _io_meta_write_bits_data_coh_T = eq(state, UInt<4>(0h3))
node _io_meta_write_bits_data_coh_T_1 = mux(_io_meta_write_bits_data_coh_T, coh_on_clear, new_coh)
connect io.meta_write.bits.data.coh, _io_meta_write_bits_data_coh_T_1
connect io.meta_write.bits.data.tag, io.tag
connect io.meta_write.bits.way_en, req.way_en
node _io_wb_req_valid_T = eq(state, UInt<4>(0h1))
connect io.wb_req.valid, _io_wb_req_valid_T
connect io.wb_req.bits.source, UInt<1>(0h1)
connect io.wb_req.bits.tag, req.old_meta.tag
connect io.wb_req.bits.idx, req_idx
connect io.wb_req.bits.param, shrink_param
connect io.wb_req.bits.way_en, req.way_en
connect io.wb_req.bits.voluntary, UInt<1>(0h1)
node _io_mem_acquire_valid_T = eq(state, UInt<4>(0h4))
node _io_mem_acquire_valid_T_1 = and(_io_mem_acquire_valid_T, grantackq.io.enq.ready)
connect io.mem_acquire.valid, _io_mem_acquire_valid_T_1
node _io_mem_acquire_bits_T = cat(io.tag, req_idx)
node _io_mem_acquire_bits_T_1 = shl(_io_mem_acquire_bits_T, 6)
node _io_mem_acquire_bits_legal_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _io_mem_acquire_bits_legal_T_1 = xor(_io_mem_acquire_bits_T_1, UInt<1>(0h0))
node _io_mem_acquire_bits_legal_T_2 = cvt(_io_mem_acquire_bits_legal_T_1)
node _io_mem_acquire_bits_legal_T_3 = and(_io_mem_acquire_bits_legal_T_2, asSInt(UInt<33>(0h8c000000)))
node _io_mem_acquire_bits_legal_T_4 = asSInt(_io_mem_acquire_bits_legal_T_3)
node _io_mem_acquire_bits_legal_T_5 = eq(_io_mem_acquire_bits_legal_T_4, asSInt(UInt<1>(0h0)))
node _io_mem_acquire_bits_legal_T_6 = xor(_io_mem_acquire_bits_T_1, UInt<17>(0h10000))
node _io_mem_acquire_bits_legal_T_7 = cvt(_io_mem_acquire_bits_legal_T_6)
node _io_mem_acquire_bits_legal_T_8 = and(_io_mem_acquire_bits_legal_T_7, asSInt(UInt<33>(0h8c011000)))
node _io_mem_acquire_bits_legal_T_9 = asSInt(_io_mem_acquire_bits_legal_T_8)
node _io_mem_acquire_bits_legal_T_10 = eq(_io_mem_acquire_bits_legal_T_9, asSInt(UInt<1>(0h0)))
node _io_mem_acquire_bits_legal_T_11 = xor(_io_mem_acquire_bits_T_1, UInt<28>(0hc000000))
node _io_mem_acquire_bits_legal_T_12 = cvt(_io_mem_acquire_bits_legal_T_11)
node _io_mem_acquire_bits_legal_T_13 = and(_io_mem_acquire_bits_legal_T_12, asSInt(UInt<33>(0h8c000000)))
node _io_mem_acquire_bits_legal_T_14 = asSInt(_io_mem_acquire_bits_legal_T_13)
node _io_mem_acquire_bits_legal_T_15 = eq(_io_mem_acquire_bits_legal_T_14, asSInt(UInt<1>(0h0)))
node _io_mem_acquire_bits_legal_T_16 = or(_io_mem_acquire_bits_legal_T_5, _io_mem_acquire_bits_legal_T_10)
node _io_mem_acquire_bits_legal_T_17 = or(_io_mem_acquire_bits_legal_T_16, _io_mem_acquire_bits_legal_T_15)
node _io_mem_acquire_bits_legal_T_18 = and(_io_mem_acquire_bits_legal_T, _io_mem_acquire_bits_legal_T_17)
node _io_mem_acquire_bits_legal_T_19 = eq(UInt<3>(0h6), UInt<3>(0h6))
node _io_mem_acquire_bits_legal_T_20 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_19)
node _io_mem_acquire_bits_legal_T_21 = xor(_io_mem_acquire_bits_T_1, UInt<28>(0h8000000))
node _io_mem_acquire_bits_legal_T_22 = cvt(_io_mem_acquire_bits_legal_T_21)
node _io_mem_acquire_bits_legal_T_23 = and(_io_mem_acquire_bits_legal_T_22, asSInt(UInt<33>(0h8c010000)))
node _io_mem_acquire_bits_legal_T_24 = asSInt(_io_mem_acquire_bits_legal_T_23)
node _io_mem_acquire_bits_legal_T_25 = eq(_io_mem_acquire_bits_legal_T_24, asSInt(UInt<1>(0h0)))
node _io_mem_acquire_bits_legal_T_26 = xor(_io_mem_acquire_bits_T_1, UInt<32>(0h80000000))
node _io_mem_acquire_bits_legal_T_27 = cvt(_io_mem_acquire_bits_legal_T_26)
node _io_mem_acquire_bits_legal_T_28 = and(_io_mem_acquire_bits_legal_T_27, asSInt(UInt<33>(0h80000000)))
node _io_mem_acquire_bits_legal_T_29 = asSInt(_io_mem_acquire_bits_legal_T_28)
node _io_mem_acquire_bits_legal_T_30 = eq(_io_mem_acquire_bits_legal_T_29, asSInt(UInt<1>(0h0)))
node _io_mem_acquire_bits_legal_T_31 = or(_io_mem_acquire_bits_legal_T_25, _io_mem_acquire_bits_legal_T_30)
node _io_mem_acquire_bits_legal_T_32 = and(_io_mem_acquire_bits_legal_T_20, _io_mem_acquire_bits_legal_T_31)
node _io_mem_acquire_bits_legal_T_33 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_18)
node io_mem_acquire_bits_legal = or(_io_mem_acquire_bits_legal_T_33, _io_mem_acquire_bits_legal_T_32)
wire io_mem_acquire_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<3>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect io_mem_acquire_bits_a.opcode, UInt<3>(0h6)
connect io_mem_acquire_bits_a.param, grow_param
connect io_mem_acquire_bits_a.size, UInt<3>(0h6)
connect io_mem_acquire_bits_a.source, UInt<1>(0h1)
connect io_mem_acquire_bits_a.address, _io_mem_acquire_bits_T_1
node _io_mem_acquire_bits_a_mask_sizeOH_T = or(UInt<3>(0h6), UInt<3>(0h0))
node io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = bits(_io_mem_acquire_bits_a_mask_sizeOH_T, 1, 0)
node _io_mem_acquire_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sizeOH_shiftAmount)
node _io_mem_acquire_bits_a_mask_sizeOH_T_2 = bits(_io_mem_acquire_bits_a_mask_sizeOH_T_1, 2, 0)
node io_mem_acquire_bits_a_mask_sizeOH = or(_io_mem_acquire_bits_a_mask_sizeOH_T_2, UInt<1>(0h1))
node io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = geq(UInt<3>(0h6), UInt<2>(0h3))
node io_mem_acquire_bits_a_mask_sub_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 2, 2)
node io_mem_acquire_bits_a_mask_sub_sub_bit = bits(_io_mem_acquire_bits_T_1, 2, 2)
node io_mem_acquire_bits_a_mask_sub_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_sub_bit, UInt<1>(0h0))
node io_mem_acquire_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_0_2)
node io_mem_acquire_bits_a_mask_sub_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T)
node io_mem_acquire_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_1_2)
node io_mem_acquire_bits_a_mask_sub_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1)
node io_mem_acquire_bits_a_mask_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 1, 1)
node io_mem_acquire_bits_a_mask_sub_bit = bits(_io_mem_acquire_bits_T_1, 1, 1)
node io_mem_acquire_bits_a_mask_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_bit, UInt<1>(0h0))
node io_mem_acquire_bits_a_mask_sub_0_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_0_2)
node io_mem_acquire_bits_a_mask_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T)
node io_mem_acquire_bits_a_mask_sub_1_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_1_2)
node io_mem_acquire_bits_a_mask_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T_1)
node io_mem_acquire_bits_a_mask_sub_2_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_2 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_2_2)
node io_mem_acquire_bits_a_mask_sub_2_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_2)
node io_mem_acquire_bits_a_mask_sub_3_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_3 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_3_2)
node io_mem_acquire_bits_a_mask_sub_3_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_3)
node io_mem_acquire_bits_a_mask_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 0, 0)
node io_mem_acquire_bits_a_mask_bit = bits(_io_mem_acquire_bits_T_1, 0, 0)
node io_mem_acquire_bits_a_mask_nbit = eq(io_mem_acquire_bits_a_mask_bit, UInt<1>(0h0))
node io_mem_acquire_bits_a_mask_eq = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq)
node io_mem_acquire_bits_a_mask_acc = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T)
node io_mem_acquire_bits_a_mask_eq_1 = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_1 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_1)
node io_mem_acquire_bits_a_mask_acc_1 = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T_1)
node io_mem_acquire_bits_a_mask_eq_2 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_2 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_2)
node io_mem_acquire_bits_a_mask_acc_2 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_2)
node io_mem_acquire_bits_a_mask_eq_3 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_3 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_3)
node io_mem_acquire_bits_a_mask_acc_3 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_3)
node io_mem_acquire_bits_a_mask_eq_4 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_4 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_4)
node io_mem_acquire_bits_a_mask_acc_4 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_4)
node io_mem_acquire_bits_a_mask_eq_5 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_5 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_5)
node io_mem_acquire_bits_a_mask_acc_5 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_5)
node io_mem_acquire_bits_a_mask_eq_6 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_6 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_6)
node io_mem_acquire_bits_a_mask_acc_6 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_6)
node io_mem_acquire_bits_a_mask_eq_7 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_7 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_7)
node io_mem_acquire_bits_a_mask_acc_7 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_7)
node io_mem_acquire_bits_a_mask_lo_lo = cat(io_mem_acquire_bits_a_mask_acc_1, io_mem_acquire_bits_a_mask_acc)
node io_mem_acquire_bits_a_mask_lo_hi = cat(io_mem_acquire_bits_a_mask_acc_3, io_mem_acquire_bits_a_mask_acc_2)
node io_mem_acquire_bits_a_mask_lo = cat(io_mem_acquire_bits_a_mask_lo_hi, io_mem_acquire_bits_a_mask_lo_lo)
node io_mem_acquire_bits_a_mask_hi_lo = cat(io_mem_acquire_bits_a_mask_acc_5, io_mem_acquire_bits_a_mask_acc_4)
node io_mem_acquire_bits_a_mask_hi_hi = cat(io_mem_acquire_bits_a_mask_acc_7, io_mem_acquire_bits_a_mask_acc_6)
node io_mem_acquire_bits_a_mask_hi = cat(io_mem_acquire_bits_a_mask_hi_hi, io_mem_acquire_bits_a_mask_hi_lo)
node _io_mem_acquire_bits_a_mask_T = cat(io_mem_acquire_bits_a_mask_hi, io_mem_acquire_bits_a_mask_lo)
connect io_mem_acquire_bits_a.mask, _io_mem_acquire_bits_a_mask_T
invalidate io_mem_acquire_bits_a.data
connect io_mem_acquire_bits_a.corrupt, UInt<1>(0h0)
connect io.mem_acquire.bits, io_mem_acquire_bits_a
node _io_replay_valid_T = eq(state, UInt<4>(0h8))
node _io_replay_valid_T_1 = and(_io_replay_valid_T, rpq.io.deq.valid)
connect io.replay.valid, _io_replay_valid_T_1
connect io.replay.bits, rpq.io.deq.bits
node _io_replay_bits_addr_T = bits(rpq.io.deq.bits.addr, 5, 0)
node io_replay_bits_addr_hi = cat(io.tag, req_idx)
node _io_replay_bits_addr_T_1 = cat(io_replay_bits_addr_hi, _io_replay_bits_addr_T)
connect io.replay.bits.addr, _io_replay_bits_addr_T_1
connect io.replay.bits.cmd, rpq.io.deq.bits.cmd
node _T_19 = eq(state, UInt<4>(0h8))
node _T_20 = eq(rpq.io.deq.valid, UInt<1>(0h0))
node _T_21 = and(_T_19, _T_20)
when _T_21 :
node _state_T_1 = eq(rpq.io.deq.valid, UInt<1>(0h0))
reg state_REG : UInt<1>, clock
connect state_REG, _state_T_1
node _state_T_2 = mux(state_REG, UInt<4>(0h0), state)
connect state, _state_T_2
node _rpq_io_deq_ready_T_4 = eq(state, UInt<4>(0h8))
node _rpq_io_deq_ready_T_5 = and(io.replay.ready, _rpq_io_deq_ready_T_4)
connect rpq.io.deq.ready, _rpq_io_deq_ready_T_5 | module ShuttleDCacheMSHR_1( // @[MSHR.scala:12:7]
input clock, // @[MSHR.scala:12:7]
input reset, // @[MSHR.scala:12:7]
input io_req_pri_val, // @[MSHR.scala:13:14]
output io_req_pri_rdy, // @[MSHR.scala:13:14]
input io_req_sec_val, // @[MSHR.scala:13:14]
output io_req_sec_rdy, // @[MSHR.scala:13:14]
input [39:0] io_req_bits_addr, // @[MSHR.scala:13:14]
input [6:0] io_req_bits_tag, // @[MSHR.scala:13:14]
input [4:0] io_req_bits_cmd, // @[MSHR.scala:13:14]
input [1:0] io_req_bits_size, // @[MSHR.scala:13:14]
input io_req_bits_signed, // @[MSHR.scala:13:14]
input [63:0] io_req_bits_data, // @[MSHR.scala:13:14]
input [7:0] io_req_bits_mask, // @[MSHR.scala:13:14]
input io_req_bits_tag_match, // @[MSHR.scala:13:14]
input [1:0] io_req_bits_old_meta_coh_state, // @[MSHR.scala:13:14]
input [19:0] io_req_bits_old_meta_tag, // @[MSHR.scala:13:14]
input [3:0] io_req_bits_way_en, // @[MSHR.scala:13:14]
input [4:0] io_req_bits_sdq_id, // @[MSHR.scala:13:14]
input [31:0] io_probe_addr, // @[MSHR.scala:13:14]
output io_idx_match, // @[MSHR.scala:13:14]
output [19:0] io_tag, // @[MSHR.scala:13:14]
input io_mem_acquire_ready, // @[MSHR.scala:13:14]
output io_mem_acquire_valid, // @[MSHR.scala:13:14]
output [2:0] io_mem_acquire_bits_param, // @[MSHR.scala:13:14]
output [31:0] io_mem_acquire_bits_address, // @[MSHR.scala:13:14]
input io_mem_grant_valid, // @[MSHR.scala:13:14]
input [2:0] io_mem_grant_bits_opcode, // @[MSHR.scala:13:14]
input [1:0] io_mem_grant_bits_param, // @[MSHR.scala:13:14]
input [3:0] io_mem_grant_bits_size, // @[MSHR.scala:13:14]
input [2:0] io_mem_grant_bits_source, // @[MSHR.scala:13:14]
input [2:0] io_mem_grant_bits_sink, // @[MSHR.scala:13:14]
input io_mem_grant_bits_denied, // @[MSHR.scala:13:14]
input [63:0] io_mem_grant_bits_data, // @[MSHR.scala:13:14]
input io_mem_grant_bits_corrupt, // @[MSHR.scala:13:14]
input io_mem_finish_ready, // @[MSHR.scala:13:14]
output io_mem_finish_valid, // @[MSHR.scala:13:14]
output [2:0] io_mem_finish_bits_sink, // @[MSHR.scala:13:14]
output [3:0] io_refill_way_en, // @[MSHR.scala:13:14]
output [11:0] io_refill_addr, // @[MSHR.scala:13:14]
input io_meta_write_ready, // @[MSHR.scala:13:14]
output io_meta_write_valid, // @[MSHR.scala:13:14]
output [5:0] io_meta_write_bits_idx, // @[MSHR.scala:13:14]
output [3:0] io_meta_write_bits_way_en, // @[MSHR.scala:13:14]
output [19:0] io_meta_write_bits_tag, // @[MSHR.scala:13:14]
output [1:0] io_meta_write_bits_data_coh_state, // @[MSHR.scala:13:14]
output [19:0] io_meta_write_bits_data_tag, // @[MSHR.scala:13:14]
input io_replay_ready, // @[MSHR.scala:13:14]
output io_replay_valid, // @[MSHR.scala:13:14]
output [39:0] io_replay_bits_addr, // @[MSHR.scala:13:14]
output [6:0] io_replay_bits_tag, // @[MSHR.scala:13:14]
output [4:0] io_replay_bits_cmd, // @[MSHR.scala:13:14]
output [1:0] io_replay_bits_size, // @[MSHR.scala:13:14]
output io_replay_bits_signed, // @[MSHR.scala:13:14]
output [63:0] io_replay_bits_data, // @[MSHR.scala:13:14]
output [7:0] io_replay_bits_mask, // @[MSHR.scala:13:14]
output io_replay_bits_tag_match, // @[MSHR.scala:13:14]
output [1:0] io_replay_bits_old_meta_coh_state, // @[MSHR.scala:13:14]
output [19:0] io_replay_bits_old_meta_tag, // @[MSHR.scala:13:14]
output [3:0] io_replay_bits_way_en, // @[MSHR.scala:13:14]
output [4:0] io_replay_bits_sdq_id, // @[MSHR.scala:13:14]
input io_wb_req_ready, // @[MSHR.scala:13:14]
output io_wb_req_valid, // @[MSHR.scala:13:14]
output [19:0] io_wb_req_bits_tag, // @[MSHR.scala:13:14]
output [5:0] io_wb_req_bits_idx, // @[MSHR.scala:13:14]
output [2:0] io_wb_req_bits_param, // @[MSHR.scala:13:14]
output [3:0] io_wb_req_bits_way_en, // @[MSHR.scala:13:14]
output io_probe_rdy // @[MSHR.scala:13:14]
);
wire [19:0] io_tag_0; // @[MSHR.scala:12:7]
wire _grantackq_io_enq_ready; // @[MSHR.scala:126:25]
wire _grantackq_io_deq_valid; // @[MSHR.scala:126:25]
wire _rpq_io_enq_ready; // @[MSHR.scala:63:19]
wire _rpq_io_deq_valid; // @[MSHR.scala:63:19]
wire [39:0] _rpq_io_deq_bits_addr; // @[MSHR.scala:63:19]
wire io_req_pri_val_0 = io_req_pri_val; // @[MSHR.scala:12:7]
wire io_req_sec_val_0 = io_req_sec_val; // @[MSHR.scala:12:7]
wire [39:0] io_req_bits_addr_0 = io_req_bits_addr; // @[MSHR.scala:12:7]
wire [6:0] io_req_bits_tag_0 = io_req_bits_tag; // @[MSHR.scala:12:7]
wire [4:0] io_req_bits_cmd_0 = io_req_bits_cmd; // @[MSHR.scala:12:7]
wire [1:0] io_req_bits_size_0 = io_req_bits_size; // @[MSHR.scala:12:7]
wire io_req_bits_signed_0 = io_req_bits_signed; // @[MSHR.scala:12:7]
wire [63:0] io_req_bits_data_0 = io_req_bits_data; // @[MSHR.scala:12:7]
wire [7:0] io_req_bits_mask_0 = io_req_bits_mask; // @[MSHR.scala:12:7]
wire io_req_bits_tag_match_0 = io_req_bits_tag_match; // @[MSHR.scala:12:7]
wire [1:0] io_req_bits_old_meta_coh_state_0 = io_req_bits_old_meta_coh_state; // @[MSHR.scala:12:7]
wire [19:0] io_req_bits_old_meta_tag_0 = io_req_bits_old_meta_tag; // @[MSHR.scala:12:7]
wire [3:0] io_req_bits_way_en_0 = io_req_bits_way_en; // @[MSHR.scala:12:7]
wire [4:0] io_req_bits_sdq_id_0 = io_req_bits_sdq_id; // @[MSHR.scala:12:7]
wire [31:0] io_probe_addr_0 = io_probe_addr; // @[MSHR.scala:12:7]
wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[MSHR.scala:12:7]
wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[MSHR.scala:12:7]
wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[MSHR.scala:12:7]
wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[MSHR.scala:12:7]
wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[MSHR.scala:12:7]
wire [2:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[MSHR.scala:12:7]
wire [2:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[MSHR.scala:12:7]
wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[MSHR.scala:12:7]
wire [63:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[MSHR.scala:12:7]
wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[MSHR.scala:12:7]
wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[MSHR.scala:12:7]
wire io_meta_write_ready_0 = io_meta_write_ready; // @[MSHR.scala:12:7]
wire io_replay_ready_0 = io_replay_ready; // @[MSHR.scala:12:7]
wire io_wb_req_ready_0 = io_wb_req_ready; // @[MSHR.scala:12:7]
wire [1:0] _grow_param_r_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _coh_on_grant_T_5 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_71 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_73 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_81 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_83 = 2'h1; // @[Metadata.scala:25:15]
wire [3:0] _r_T_15 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _r_T_16 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _r_T_17 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _r_T_18 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _r_T_7 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _grow_param_r_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r1_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r2_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _r_T_66 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r_T_8 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _grow_param_r_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r1_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r2_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _r_T_68 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r_T_9 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _grow_param_r_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _coh_on_grant_T_2 = 4'h1; // @[Metadata.scala:86:10]
wire [3:0] _r1_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r2_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _r_T_70 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r_T_11 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _grow_param_r_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r1_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r2_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _r_T_72 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _grow_param_r_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r1_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r2_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r_T_78 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r_T_10 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _grow_param_r_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _coh_on_grant_T_4 = 4'h0; // @[Metadata.scala:87:10]
wire [3:0] _r1_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _r2_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _r_T_80 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _r_T_13 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _grow_param_r_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r1_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r2_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _r_T_82 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _grow_param_r_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r1_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r2_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_86 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _grow_param_r_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _coh_on_grant_T_8 = 4'hC; // @[Metadata.scala:89:10]
wire [3:0] _r1_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _r2_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _r_T_88 = 4'hC; // @[Metadata.scala:72:10]
wire [1:0] new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _r_T_22 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_26 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_30 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_34 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_38 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _grow_param_r_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _coh_on_grant_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _coh_on_grant_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_65 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_67 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_69 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_79 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _r_T_1 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _r_T_3 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _r_T_5 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49]
wire [3:0] _r_T_14 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _grow_param_r_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _coh_on_grant_T_6 = 4'h4; // @[Metadata.scala:88:10]
wire [3:0] _r1_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r2_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _r_T_84 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12]
wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27]
wire [2:0] io_mem_acquire_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81]
wire [1:0] _grow_param_r_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _coh_on_grant_T_7 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _dirties_T = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_75 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_77 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_85 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_87 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] io_mem_acquire_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10]
wire [3:0] _grow_param_r_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r1_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r2_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r_T_76 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] io_mem_acquire_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10]
wire [3:0] io_mem_acquire_bits_a_mask_hi = 4'hF; // @[Misc.scala:222:10]
wire io_wb_req_bits_voluntary = 1'h1; // @[MSHR.scala:12:7]
wire _r_T = 1'h1; // @[Metadata.scala:140:24]
wire _needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24]
wire _io_mem_acquire_bits_legal_T_19 = 1'h1; // @[Parameters.scala:91:44]
wire _io_mem_acquire_bits_legal_T_20 = 1'h1; // @[Parameters.scala:684:29]
wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire io_mem_acquire_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26]
wire io_mem_acquire_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26]
wire io_mem_acquire_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_corrupt = 1'h0; // @[MSHR.scala:12:7]
wire _r_T_2 = 1'h0; // @[Metadata.scala:140:24]
wire _r_T_4 = 1'h0; // @[Metadata.scala:140:24]
wire _r_T_20 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_24 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_28 = 1'h0; // @[Misc.scala:38:9]
wire _grow_param_r_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24]
wire _needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24]
wire _needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9]
wire _needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9]
wire _needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_90 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_93 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_96 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_99 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_102 = 1'h0; // @[Misc.scala:35:9]
wire _io_mem_acquire_bits_legal_T = 1'h0; // @[Parameters.scala:684:29]
wire _io_mem_acquire_bits_legal_T_18 = 1'h0; // @[Parameters.scala:684:54]
wire _io_mem_acquire_bits_legal_T_33 = 1'h0; // @[Parameters.scala:686:26]
wire io_mem_acquire_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17]
wire io_mem_acquire_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _io_mem_acquire_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire [63:0] io_mem_acquire_bits_data = 64'h0; // @[MSHR.scala:12:7]
wire [63:0] io_mem_acquire_bits_a_data = 64'h0; // @[Edges.scala:346:17]
wire [7:0] io_mem_acquire_bits_mask = 8'hFF; // @[MSHR.scala:12:7, :13:14]
wire [7:0] io_mem_acquire_bits_a_mask = 8'hFF; // @[MSHR.scala:12:7, :13:14]
wire [7:0] _io_mem_acquire_bits_a_mask_T = 8'hFF; // @[MSHR.scala:12:7, :13:14]
wire [2:0] io_mem_acquire_bits_source = 3'h1; // @[MSHR.scala:12:7, :142:59]
wire [2:0] io_wb_req_bits_source = 3'h1; // @[MSHR.scala:12:7, :142:59]
wire [2:0] io_mem_acquire_bits_a_source = 3'h1; // @[MSHR.scala:142:59]
wire [3:0] io_mem_acquire_bits_size = 4'h6; // @[MSHR.scala:12:7]
wire [3:0] _r_T_12 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _grow_param_r_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r1_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r2_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _r_T_74 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] io_mem_acquire_bits_a_size = 4'h6; // @[Edges.scala:346:17]
wire [2:0] io_mem_acquire_bits_opcode = 3'h6; // @[MSHR.scala:12:7]
wire [2:0] io_mem_acquire_bits_a_opcode = 3'h6; // @[Edges.scala:346:17]
wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34]
wire _io_req_pri_rdy_T; // @[MSHR.scala:138:27]
wire _io_req_sec_rdy_T; // @[MSHR.scala:139:29]
wire _io_idx_match_T_1; // @[MSHR.scala:134:41]
wire [19:0] io_meta_write_bits_tag_0 = io_tag_0; // @[MSHR.scala:12:7]
wire [19:0] io_meta_write_bits_data_tag_0 = io_tag_0; // @[MSHR.scala:12:7]
wire _io_mem_acquire_valid_T_1; // @[MSHR.scala:161:50]
wire [2:0] io_mem_acquire_bits_a_param; // @[Edges.scala:346:17]
wire [31:0] io_mem_acquire_bits_a_address; // @[Edges.scala:346:17]
wire [2:0] grantackq_io_enq_bits_e_sink = io_mem_grant_bits_sink_0; // @[MSHR.scala:12:7]
wire _io_mem_finish_valid_T; // @[MSHR.scala:130:49]
wire _io_meta_write_valid_T_2; // @[package.scala:81:59]
wire [5:0] req_idx; // @[MSHR.scala:39:25]
wire [1:0] _io_meta_write_bits_data_coh_T_1_state; // @[MSHR.scala:149:37]
wire _io_replay_valid_T_1; // @[MSHR.scala:168:44]
wire _io_wb_req_valid_T; // @[MSHR.scala:153:28]
wire [2:0] shrink_param; // @[Misc.scala:38:36]
wire _io_probe_rdy_T_11; // @[MSHR.scala:144:61]
wire [2:0] io_mem_acquire_bits_param_0; // @[MSHR.scala:12:7]
wire [31:0] io_mem_acquire_bits_address_0; // @[MSHR.scala:12:7]
wire io_mem_acquire_valid_0; // @[MSHR.scala:12:7]
wire [2:0] io_mem_finish_bits_sink_0; // @[MSHR.scala:12:7]
wire io_mem_finish_valid_0; // @[MSHR.scala:12:7]
wire [3:0] io_refill_way_en_0; // @[MSHR.scala:12:7]
wire [11:0] io_refill_addr_0; // @[MSHR.scala:12:7]
wire [1:0] io_meta_write_bits_data_coh_state_0; // @[MSHR.scala:12:7]
wire [5:0] io_meta_write_bits_idx_0; // @[MSHR.scala:12:7]
wire [3:0] io_meta_write_bits_way_en_0; // @[MSHR.scala:12:7]
wire io_meta_write_valid_0; // @[MSHR.scala:12:7]
wire [1:0] io_replay_bits_old_meta_coh_state_0; // @[MSHR.scala:12:7]
wire [19:0] io_replay_bits_old_meta_tag_0; // @[MSHR.scala:12:7]
wire [39:0] io_replay_bits_addr_0; // @[MSHR.scala:12:7]
wire [6:0] io_replay_bits_tag_0; // @[MSHR.scala:12:7]
wire [4:0] io_replay_bits_cmd_0; // @[MSHR.scala:12:7]
wire [1:0] io_replay_bits_size_0; // @[MSHR.scala:12:7]
wire io_replay_bits_signed_0; // @[MSHR.scala:12:7]
wire [63:0] io_replay_bits_data_0; // @[MSHR.scala:12:7]
wire [7:0] io_replay_bits_mask_0; // @[MSHR.scala:12:7]
wire io_replay_bits_tag_match_0; // @[MSHR.scala:12:7]
wire [3:0] io_replay_bits_way_en_0; // @[MSHR.scala:12:7]
wire [4:0] io_replay_bits_sdq_id_0; // @[MSHR.scala:12:7]
wire io_replay_valid_0; // @[MSHR.scala:12:7]
wire [19:0] io_wb_req_bits_tag_0; // @[MSHR.scala:12:7]
wire [5:0] io_wb_req_bits_idx_0; // @[MSHR.scala:12:7]
wire [2:0] io_wb_req_bits_param_0; // @[MSHR.scala:12:7]
wire [3:0] io_wb_req_bits_way_en_0; // @[MSHR.scala:12:7]
wire io_wb_req_valid_0; // @[MSHR.scala:12:7]
wire io_req_pri_rdy_0; // @[MSHR.scala:12:7]
wire io_req_sec_rdy_0; // @[MSHR.scala:12:7]
wire io_idx_match_0; // @[MSHR.scala:12:7]
wire io_probe_rdy_0; // @[MSHR.scala:12:7]
reg [3:0] state; // @[MSHR.scala:36:22]
reg [39:0] req_addr; // @[MSHR.scala:38:16]
reg [6:0] req_tag; // @[MSHR.scala:38:16]
reg [4:0] req_cmd; // @[MSHR.scala:38:16]
reg [1:0] req_size; // @[MSHR.scala:38:16]
reg req_signed; // @[MSHR.scala:38:16]
reg [63:0] req_data; // @[MSHR.scala:38:16]
reg [7:0] req_mask; // @[MSHR.scala:38:16]
reg req_tag_match; // @[MSHR.scala:38:16]
reg [1:0] req_old_meta_coh_state; // @[MSHR.scala:38:16]
reg [19:0] req_old_meta_tag; // @[MSHR.scala:38:16]
assign io_wb_req_bits_tag_0 = req_old_meta_tag; // @[MSHR.scala:12:7, :38:16]
reg [3:0] req_way_en; // @[MSHR.scala:38:16]
assign io_refill_way_en_0 = req_way_en; // @[MSHR.scala:12:7, :38:16]
assign io_meta_write_bits_way_en_0 = req_way_en; // @[MSHR.scala:12:7, :38:16]
assign io_wb_req_bits_way_en_0 = req_way_en; // @[MSHR.scala:12:7, :38:16]
reg [4:0] req_sdq_id; // @[MSHR.scala:38:16]
assign req_idx = req_addr[11:6]; // @[MSHR.scala:38:16, :39:25]
assign io_meta_write_bits_idx_0 = req_idx; // @[MSHR.scala:12:7, :39:25]
assign io_wb_req_bits_idx_0 = req_idx; // @[MSHR.scala:12:7, :39:25]
wire [27:0] req_tag_0 = req_addr[39:12]; // @[MSHR.scala:38:16, :40:26]
wire [33:0] _req_block_addr_T = req_addr[39:6]; // @[MSHR.scala:38:16, :41:34]
wire [39:0] req_block_addr = {_req_block_addr_T, 6'h0}; // @[MSHR.scala:41:{34,51}]
wire [5:0] _idx_match_T = io_req_bits_addr_0[11:6]; // @[MSHR.scala:12:7, :42:47]
wire idx_match = req_idx == _idx_match_T; // @[MSHR.scala:39:25, :42:{27,47}]
wire [5:0] _probe_idx_match_T = io_probe_addr_0[11:6]; // @[MSHR.scala:12:7, :43:50]
wire probe_idx_match = req_idx == _probe_idx_match_T; // @[MSHR.scala:39:25, :43:{33,50}]
reg [1:0] new_coh_state; // @[MSHR.scala:45:24]
wire [3:0] _r_T_6 = {2'h2, req_old_meta_coh_state}; // @[MSHR.scala:38:16]
wire _r_T_19 = _r_T_6 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _r_T_21 = _r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _r_T_23 = _r_T_6 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _r_T_25 = _r_T_23 ? 3'h2 : _r_T_21; // @[Misc.scala:38:36, :56:20]
wire _r_T_27 = _r_T_6 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _r_T_29 = _r_T_27 ? 3'h1 : _r_T_25; // @[MSHR.scala:142:59]
wire _r_T_31 = _r_T_6 == 4'hB; // @[Misc.scala:56:20]
wire _r_T_32 = _r_T_31; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_33 = _r_T_31 ? 3'h1 : _r_T_29; // @[MSHR.scala:142:59]
wire _r_T_35 = _r_T_6 == 4'h4; // @[Misc.scala:56:20]
wire _r_T_36 = ~_r_T_35 & _r_T_32; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_37 = _r_T_35 ? 3'h5 : _r_T_33; // @[Misc.scala:38:36, :56:20]
wire _r_T_39 = _r_T_6 == 4'h5; // @[Misc.scala:56:20]
wire _r_T_40 = ~_r_T_39 & _r_T_36; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_41 = _r_T_39 ? 3'h4 : _r_T_37; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_42 = {1'h0, _r_T_39}; // @[Misc.scala:38:63, :56:20]
wire _r_T_43 = _r_T_6 == 4'h6; // @[Misc.scala:56:20]
wire _r_T_44 = ~_r_T_43 & _r_T_40; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_45 = _r_T_43 ? 3'h0 : _r_T_41; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_46 = _r_T_43 ? 2'h1 : _r_T_42; // @[Misc.scala:38:63, :56:20]
wire _r_T_47 = _r_T_6 == 4'h7; // @[Misc.scala:56:20]
wire _r_T_48 = _r_T_47 | _r_T_44; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_49 = _r_T_47 ? 3'h0 : _r_T_45; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_50 = _r_T_47 ? 2'h1 : _r_T_46; // @[Misc.scala:38:63, :56:20]
wire _r_T_51 = _r_T_6 == 4'h0; // @[Misc.scala:56:20]
wire _r_T_52 = ~_r_T_51 & _r_T_48; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_53 = _r_T_51 ? 3'h5 : _r_T_49; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_54 = _r_T_51 ? 2'h0 : _r_T_50; // @[Misc.scala:38:63, :56:20]
wire _r_T_55 = _r_T_6 == 4'h1; // @[Misc.scala:56:20]
wire _r_T_56 = ~_r_T_55 & _r_T_52; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_57 = _r_T_55 ? 3'h4 : _r_T_53; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_58 = _r_T_55 ? 2'h1 : _r_T_54; // @[Misc.scala:38:63, :56:20]
wire _r_T_59 = _r_T_6 == 4'h2; // @[Misc.scala:56:20]
wire _r_T_60 = ~_r_T_59 & _r_T_56; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_61 = _r_T_59 ? 3'h3 : _r_T_57; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_62 = _r_T_59 ? 2'h2 : _r_T_58; // @[Misc.scala:38:63, :56:20]
wire _r_T_63 = _r_T_6 == 4'h3; // @[Misc.scala:56:20]
wire r_1 = _r_T_63 | _r_T_60; // @[Misc.scala:38:9, :56:20]
assign shrink_param = _r_T_63 ? 3'h3 : _r_T_61; // @[Misc.scala:38:36, :56:20]
assign io_wb_req_bits_param_0 = shrink_param; // @[MSHR.scala:12:7]
wire [1:0] r_3 = _r_T_63 ? 2'h2 : _r_T_62; // @[Misc.scala:38:63, :56:20]
wire [1:0] coh_on_clear_state = r_3; // @[Misc.scala:38:63]
wire _GEN = req_cmd == 5'h1; // @[MSHR.scala:38:16]
wire _grow_param_r_c_cat_T; // @[Consts.scala:90:32]
assign _grow_param_r_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _grow_param_r_c_cat_T_23; // @[Consts.scala:90:32]
assign _grow_param_r_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _coh_on_grant_c_cat_T; // @[Consts.scala:90:32]
assign _coh_on_grant_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _coh_on_grant_c_cat_T_23; // @[Consts.scala:90:32]
assign _coh_on_grant_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _r1_c_cat_T; // @[Consts.scala:90:32]
assign _r1_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _r1_c_cat_T_23; // @[Consts.scala:90:32]
assign _r1_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _needs_second_acq_T_27; // @[Consts.scala:90:32]
assign _needs_second_acq_T_27 = _GEN; // @[Consts.scala:90:32]
wire _GEN_0 = req_cmd == 5'h11; // @[MSHR.scala:38:16]
wire _grow_param_r_c_cat_T_1; // @[Consts.scala:90:49]
assign _grow_param_r_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _grow_param_r_c_cat_T_24; // @[Consts.scala:90:49]
assign _grow_param_r_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:49]
assign _coh_on_grant_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:49]
assign _coh_on_grant_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _r1_c_cat_T_1; // @[Consts.scala:90:49]
assign _r1_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _r1_c_cat_T_24; // @[Consts.scala:90:49]
assign _r1_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _needs_second_acq_T_28; // @[Consts.scala:90:49]
assign _needs_second_acq_T_28 = _GEN_0; // @[Consts.scala:90:49]
wire _grow_param_r_c_cat_T_2 = _grow_param_r_c_cat_T | _grow_param_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _GEN_1 = req_cmd == 5'h7; // @[MSHR.scala:38:16]
wire _grow_param_r_c_cat_T_3; // @[Consts.scala:90:66]
assign _grow_param_r_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _grow_param_r_c_cat_T_26; // @[Consts.scala:90:66]
assign _grow_param_r_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:66]
assign _coh_on_grant_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:66]
assign _coh_on_grant_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _r1_c_cat_T_3; // @[Consts.scala:90:66]
assign _r1_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _r1_c_cat_T_26; // @[Consts.scala:90:66]
assign _r1_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _needs_second_acq_T_30; // @[Consts.scala:90:66]
assign _needs_second_acq_T_30 = _GEN_1; // @[Consts.scala:90:66]
wire _grow_param_r_c_cat_T_4 = _grow_param_r_c_cat_T_2 | _grow_param_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _GEN_2 = req_cmd == 5'h4; // @[MSHR.scala:38:16]
wire _grow_param_r_c_cat_T_5; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_28; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_5; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_28; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _r1_c_cat_T_5; // @[package.scala:16:47]
assign _r1_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _r1_c_cat_T_28; // @[package.scala:16:47]
assign _r1_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _needs_second_acq_T_32; // @[package.scala:16:47]
assign _needs_second_acq_T_32 = _GEN_2; // @[package.scala:16:47]
wire _GEN_3 = req_cmd == 5'h9; // @[MSHR.scala:38:16]
wire _grow_param_r_c_cat_T_6; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_29; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_6; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_29; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _r1_c_cat_T_6; // @[package.scala:16:47]
assign _r1_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _r1_c_cat_T_29; // @[package.scala:16:47]
assign _r1_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _needs_second_acq_T_33; // @[package.scala:16:47]
assign _needs_second_acq_T_33 = _GEN_3; // @[package.scala:16:47]
wire _GEN_4 = req_cmd == 5'hA; // @[MSHR.scala:38:16]
wire _grow_param_r_c_cat_T_7; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_30; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_7; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_30; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _r1_c_cat_T_7; // @[package.scala:16:47]
assign _r1_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _r1_c_cat_T_30; // @[package.scala:16:47]
assign _r1_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _needs_second_acq_T_34; // @[package.scala:16:47]
assign _needs_second_acq_T_34 = _GEN_4; // @[package.scala:16:47]
wire _GEN_5 = req_cmd == 5'hB; // @[MSHR.scala:38:16]
wire _grow_param_r_c_cat_T_8; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_31; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_8; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_31; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _r1_c_cat_T_8; // @[package.scala:16:47]
assign _r1_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _r1_c_cat_T_31; // @[package.scala:16:47]
assign _r1_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _needs_second_acq_T_35; // @[package.scala:16:47]
assign _needs_second_acq_T_35 = _GEN_5; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_9 = _grow_param_r_c_cat_T_5 | _grow_param_r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_10 = _grow_param_r_c_cat_T_9 | _grow_param_r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_11 = _grow_param_r_c_cat_T_10 | _grow_param_r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _GEN_6 = req_cmd == 5'h8; // @[MSHR.scala:38:16]
wire _grow_param_r_c_cat_T_12; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_35; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_12; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_35; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _r1_c_cat_T_12; // @[package.scala:16:47]
assign _r1_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _r1_c_cat_T_35; // @[package.scala:16:47]
assign _r1_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _needs_second_acq_T_39; // @[package.scala:16:47]
assign _needs_second_acq_T_39 = _GEN_6; // @[package.scala:16:47]
wire _GEN_7 = req_cmd == 5'hC; // @[MSHR.scala:38:16]
wire _grow_param_r_c_cat_T_13; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_36; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_13; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_36; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _r1_c_cat_T_13; // @[package.scala:16:47]
assign _r1_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _r1_c_cat_T_36; // @[package.scala:16:47]
assign _r1_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _needs_second_acq_T_40; // @[package.scala:16:47]
assign _needs_second_acq_T_40 = _GEN_7; // @[package.scala:16:47]
wire _GEN_8 = req_cmd == 5'hD; // @[MSHR.scala:38:16]
wire _grow_param_r_c_cat_T_14; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_37; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_14; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_37; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _r1_c_cat_T_14; // @[package.scala:16:47]
assign _r1_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _r1_c_cat_T_37; // @[package.scala:16:47]
assign _r1_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _needs_second_acq_T_41; // @[package.scala:16:47]
assign _needs_second_acq_T_41 = _GEN_8; // @[package.scala:16:47]
wire _GEN_9 = req_cmd == 5'hE; // @[MSHR.scala:38:16]
wire _grow_param_r_c_cat_T_15; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_38; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_15; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_38; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _r1_c_cat_T_15; // @[package.scala:16:47]
assign _r1_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _r1_c_cat_T_38; // @[package.scala:16:47]
assign _r1_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _needs_second_acq_T_42; // @[package.scala:16:47]
assign _needs_second_acq_T_42 = _GEN_9; // @[package.scala:16:47]
wire _GEN_10 = req_cmd == 5'hF; // @[MSHR.scala:38:16]
wire _grow_param_r_c_cat_T_16; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_39; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_16; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_39; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _r1_c_cat_T_16; // @[package.scala:16:47]
assign _r1_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _r1_c_cat_T_39; // @[package.scala:16:47]
assign _r1_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _needs_second_acq_T_43; // @[package.scala:16:47]
assign _needs_second_acq_T_43 = _GEN_10; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_17 = _grow_param_r_c_cat_T_12 | _grow_param_r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_18 = _grow_param_r_c_cat_T_17 | _grow_param_r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_19 = _grow_param_r_c_cat_T_18 | _grow_param_r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_20 = _grow_param_r_c_cat_T_19 | _grow_param_r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_21 = _grow_param_r_c_cat_T_11 | _grow_param_r_c_cat_T_20; // @[package.scala:81:59]
wire _grow_param_r_c_cat_T_22 = _grow_param_r_c_cat_T_4 | _grow_param_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _grow_param_r_c_cat_T_25 = _grow_param_r_c_cat_T_23 | _grow_param_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _grow_param_r_c_cat_T_27 = _grow_param_r_c_cat_T_25 | _grow_param_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _grow_param_r_c_cat_T_32 = _grow_param_r_c_cat_T_28 | _grow_param_r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_33 = _grow_param_r_c_cat_T_32 | _grow_param_r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_34 = _grow_param_r_c_cat_T_33 | _grow_param_r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_40 = _grow_param_r_c_cat_T_35 | _grow_param_r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_41 = _grow_param_r_c_cat_T_40 | _grow_param_r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_42 = _grow_param_r_c_cat_T_41 | _grow_param_r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_43 = _grow_param_r_c_cat_T_42 | _grow_param_r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_44 = _grow_param_r_c_cat_T_34 | _grow_param_r_c_cat_T_43; // @[package.scala:81:59]
wire _grow_param_r_c_cat_T_45 = _grow_param_r_c_cat_T_27 | _grow_param_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _GEN_11 = req_cmd == 5'h3; // @[MSHR.scala:38:16]
wire _grow_param_r_c_cat_T_46; // @[Consts.scala:91:54]
assign _grow_param_r_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _coh_on_grant_c_cat_T_46; // @[Consts.scala:91:54]
assign _coh_on_grant_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _r1_c_cat_T_46; // @[Consts.scala:91:54]
assign _r1_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _needs_second_acq_T_50; // @[Consts.scala:91:54]
assign _needs_second_acq_T_50 = _GEN_11; // @[Consts.scala:91:54]
wire _grow_param_r_c_cat_T_47 = _grow_param_r_c_cat_T_45 | _grow_param_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _GEN_12 = req_cmd == 5'h6; // @[MSHR.scala:38:16]
wire _grow_param_r_c_cat_T_48; // @[Consts.scala:91:71]
assign _grow_param_r_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:71]
assign _coh_on_grant_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _r1_c_cat_T_48; // @[Consts.scala:91:71]
assign _r1_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _needs_second_acq_T_52; // @[Consts.scala:91:71]
assign _needs_second_acq_T_52 = _GEN_12; // @[Consts.scala:91:71]
wire _grow_param_r_c_cat_T_49 = _grow_param_r_c_cat_T_47 | _grow_param_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] grow_param_r_c = {_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _grow_param_r_T = {grow_param_r_c, new_coh_state}; // @[MSHR.scala:45:24]
wire _grow_param_r_T_25 = _grow_param_r_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_27 = {1'h0, _grow_param_r_T_25}; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_28 = _grow_param_r_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_30 = _grow_param_r_T_28 ? 2'h2 : _grow_param_r_T_27; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_31 = _grow_param_r_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_33 = _grow_param_r_T_31 ? 2'h1 : _grow_param_r_T_30; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_34 = _grow_param_r_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_36 = _grow_param_r_T_34 ? 2'h2 : _grow_param_r_T_33; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_37 = _grow_param_r_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_39 = _grow_param_r_T_37 ? 2'h0 : _grow_param_r_T_36; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_40 = _grow_param_r_T == 4'hE; // @[Misc.scala:49:20]
wire _grow_param_r_T_41 = _grow_param_r_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_42 = _grow_param_r_T_40 ? 2'h3 : _grow_param_r_T_39; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_43 = &_grow_param_r_T; // @[Misc.scala:49:20]
wire _grow_param_r_T_44 = _grow_param_r_T_43 | _grow_param_r_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_45 = _grow_param_r_T_43 ? 2'h3 : _grow_param_r_T_42; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_46 = _grow_param_r_T == 4'h6; // @[Misc.scala:49:20]
wire _grow_param_r_T_47 = _grow_param_r_T_46 | _grow_param_r_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_48 = _grow_param_r_T_46 ? 2'h2 : _grow_param_r_T_45; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_49 = _grow_param_r_T == 4'h7; // @[Misc.scala:49:20]
wire _grow_param_r_T_50 = _grow_param_r_T_49 | _grow_param_r_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_51 = _grow_param_r_T_49 ? 2'h3 : _grow_param_r_T_48; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_52 = _grow_param_r_T == 4'h1; // @[Misc.scala:49:20]
wire _grow_param_r_T_53 = _grow_param_r_T_52 | _grow_param_r_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_54 = _grow_param_r_T_52 ? 2'h1 : _grow_param_r_T_51; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_55 = _grow_param_r_T == 4'h2; // @[Misc.scala:49:20]
wire _grow_param_r_T_56 = _grow_param_r_T_55 | _grow_param_r_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_57 = _grow_param_r_T_55 ? 2'h2 : _grow_param_r_T_54; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_58 = _grow_param_r_T == 4'h3; // @[Misc.scala:49:20]
wire grow_param_r_1 = _grow_param_r_T_58 | _grow_param_r_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] grow_param = _grow_param_r_T_58 ? 2'h3 : _grow_param_r_T_57; // @[Misc.scala:35:36, :49:20]
wire [1:0] grow_param_meta_state = grow_param; // @[Misc.scala:35:36]
wire _coh_on_grant_c_cat_T_2 = _coh_on_grant_c_cat_T | _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _coh_on_grant_c_cat_T_4 = _coh_on_grant_c_cat_T_2 | _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _coh_on_grant_c_cat_T_9 = _coh_on_grant_c_cat_T_5 | _coh_on_grant_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_10 = _coh_on_grant_c_cat_T_9 | _coh_on_grant_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_11 = _coh_on_grant_c_cat_T_10 | _coh_on_grant_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_17 = _coh_on_grant_c_cat_T_12 | _coh_on_grant_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_18 = _coh_on_grant_c_cat_T_17 | _coh_on_grant_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_19 = _coh_on_grant_c_cat_T_18 | _coh_on_grant_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_20 = _coh_on_grant_c_cat_T_19 | _coh_on_grant_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_21 = _coh_on_grant_c_cat_T_11 | _coh_on_grant_c_cat_T_20; // @[package.scala:81:59]
wire _coh_on_grant_c_cat_T_22 = _coh_on_grant_c_cat_T_4 | _coh_on_grant_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _coh_on_grant_c_cat_T_25 = _coh_on_grant_c_cat_T_23 | _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _coh_on_grant_c_cat_T_27 = _coh_on_grant_c_cat_T_25 | _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _coh_on_grant_c_cat_T_32 = _coh_on_grant_c_cat_T_28 | _coh_on_grant_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_33 = _coh_on_grant_c_cat_T_32 | _coh_on_grant_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_34 = _coh_on_grant_c_cat_T_33 | _coh_on_grant_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_40 = _coh_on_grant_c_cat_T_35 | _coh_on_grant_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_41 = _coh_on_grant_c_cat_T_40 | _coh_on_grant_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_42 = _coh_on_grant_c_cat_T_41 | _coh_on_grant_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_43 = _coh_on_grant_c_cat_T_42 | _coh_on_grant_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_44 = _coh_on_grant_c_cat_T_34 | _coh_on_grant_c_cat_T_43; // @[package.scala:81:59]
wire _coh_on_grant_c_cat_T_45 = _coh_on_grant_c_cat_T_27 | _coh_on_grant_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _coh_on_grant_c_cat_T_47 = _coh_on_grant_c_cat_T_45 | _coh_on_grant_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _coh_on_grant_c_cat_T_49 = _coh_on_grant_c_cat_T_47 | _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] coh_on_grant_c = {_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _coh_on_grant_T = {coh_on_grant_c, io_mem_grant_bits_param_0}; // @[MSHR.scala:12:7]
wire _coh_on_grant_T_9 = _coh_on_grant_T == 4'h1; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_10 = {1'h0, _coh_on_grant_T_9}; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_11 = _coh_on_grant_T == 4'h0; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_12 = _coh_on_grant_T_11 ? 2'h2 : _coh_on_grant_T_10; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_13 = _coh_on_grant_T == 4'h4; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_14 = _coh_on_grant_T_13 ? 2'h2 : _coh_on_grant_T_12; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_15 = _coh_on_grant_T == 4'hC; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_16 = _coh_on_grant_T_15 ? 2'h3 : _coh_on_grant_T_14; // @[Metadata.scala:84:38]
wire [1:0] coh_on_grant_state = _coh_on_grant_T_16; // @[Metadata.scala:84:38, :160:20]
wire _r1_c_cat_T_2 = _r1_c_cat_T | _r1_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _r1_c_cat_T_4 = _r1_c_cat_T_2 | _r1_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _r1_c_cat_T_9 = _r1_c_cat_T_5 | _r1_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_10 = _r1_c_cat_T_9 | _r1_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_11 = _r1_c_cat_T_10 | _r1_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_17 = _r1_c_cat_T_12 | _r1_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_18 = _r1_c_cat_T_17 | _r1_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_19 = _r1_c_cat_T_18 | _r1_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_20 = _r1_c_cat_T_19 | _r1_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_21 = _r1_c_cat_T_11 | _r1_c_cat_T_20; // @[package.scala:81:59]
wire _r1_c_cat_T_22 = _r1_c_cat_T_4 | _r1_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r1_c_cat_T_25 = _r1_c_cat_T_23 | _r1_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r1_c_cat_T_27 = _r1_c_cat_T_25 | _r1_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r1_c_cat_T_32 = _r1_c_cat_T_28 | _r1_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_33 = _r1_c_cat_T_32 | _r1_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_34 = _r1_c_cat_T_33 | _r1_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_40 = _r1_c_cat_T_35 | _r1_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_41 = _r1_c_cat_T_40 | _r1_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_42 = _r1_c_cat_T_41 | _r1_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_43 = _r1_c_cat_T_42 | _r1_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_44 = _r1_c_cat_T_34 | _r1_c_cat_T_43; // @[package.scala:81:59]
wire _r1_c_cat_T_45 = _r1_c_cat_T_27 | _r1_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _r1_c_cat_T_47 = _r1_c_cat_T_45 | _r1_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _r1_c_cat_T_49 = _r1_c_cat_T_47 | _r1_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r1_c = {_r1_c_cat_T_22, _r1_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r1_T = {r1_c, new_coh_state}; // @[MSHR.scala:45:24]
wire _r1_T_25 = _r1_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r1_T_27 = {1'h0, _r1_T_25}; // @[Misc.scala:35:36, :49:20]
wire _r1_T_28 = _r1_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r1_T_30 = _r1_T_28 ? 2'h2 : _r1_T_27; // @[Misc.scala:35:36, :49:20]
wire _r1_T_31 = _r1_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r1_T_33 = _r1_T_31 ? 2'h1 : _r1_T_30; // @[Misc.scala:35:36, :49:20]
wire _r1_T_34 = _r1_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r1_T_36 = _r1_T_34 ? 2'h2 : _r1_T_33; // @[Misc.scala:35:36, :49:20]
wire _r1_T_37 = _r1_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r1_T_39 = _r1_T_37 ? 2'h0 : _r1_T_36; // @[Misc.scala:35:36, :49:20]
wire _r1_T_40 = _r1_T == 4'hE; // @[Misc.scala:49:20]
wire _r1_T_41 = _r1_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_42 = _r1_T_40 ? 2'h3 : _r1_T_39; // @[Misc.scala:35:36, :49:20]
wire _r1_T_43 = &_r1_T; // @[Misc.scala:49:20]
wire _r1_T_44 = _r1_T_43 | _r1_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_45 = _r1_T_43 ? 2'h3 : _r1_T_42; // @[Misc.scala:35:36, :49:20]
wire _r1_T_46 = _r1_T == 4'h6; // @[Misc.scala:49:20]
wire _r1_T_47 = _r1_T_46 | _r1_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_48 = _r1_T_46 ? 2'h2 : _r1_T_45; // @[Misc.scala:35:36, :49:20]
wire _r1_T_49 = _r1_T == 4'h7; // @[Misc.scala:49:20]
wire _r1_T_50 = _r1_T_49 | _r1_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_51 = _r1_T_49 ? 2'h3 : _r1_T_48; // @[Misc.scala:35:36, :49:20]
wire _r1_T_52 = _r1_T == 4'h1; // @[Misc.scala:49:20]
wire _r1_T_53 = _r1_T_52 | _r1_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_54 = _r1_T_52 ? 2'h1 : _r1_T_51; // @[Misc.scala:35:36, :49:20]
wire _r1_T_55 = _r1_T == 4'h2; // @[Misc.scala:49:20]
wire _r1_T_56 = _r1_T_55 | _r1_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_57 = _r1_T_55 ? 2'h2 : _r1_T_54; // @[Misc.scala:35:36, :49:20]
wire _r1_T_58 = _r1_T == 4'h3; // @[Misc.scala:49:20]
wire r1_1 = _r1_T_58 | _r1_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] r1_2 = _r1_T_58 ? 2'h3 : _r1_T_57; // @[Misc.scala:35:36, :49:20]
wire _GEN_13 = io_req_bits_cmd_0 == 5'h1; // @[MSHR.scala:12:7]
wire _r2_c_cat_T; // @[Consts.scala:90:32]
assign _r2_c_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _r2_c_cat_T_23; // @[Consts.scala:90:32]
assign _r2_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _needs_second_acq_T; // @[Consts.scala:90:32]
assign _needs_second_acq_T = _GEN_13; // @[Consts.scala:90:32]
wire _dirties_cat_T; // @[Consts.scala:90:32]
assign _dirties_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _dirties_cat_T_23; // @[Consts.scala:90:32]
assign _dirties_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _r_c_cat_T; // @[Consts.scala:90:32]
assign _r_c_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _r_c_cat_T_23; // @[Consts.scala:90:32]
assign _r_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _GEN_14 = io_req_bits_cmd_0 == 5'h11; // @[MSHR.scala:12:7]
wire _r2_c_cat_T_1; // @[Consts.scala:90:49]
assign _r2_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _r2_c_cat_T_24; // @[Consts.scala:90:49]
assign _r2_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _needs_second_acq_T_1; // @[Consts.scala:90:49]
assign _needs_second_acq_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _dirties_cat_T_1; // @[Consts.scala:90:49]
assign _dirties_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _dirties_cat_T_24; // @[Consts.scala:90:49]
assign _dirties_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _r_c_cat_T_1; // @[Consts.scala:90:49]
assign _r_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _r_c_cat_T_24; // @[Consts.scala:90:49]
assign _r_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _r2_c_cat_T_2 = _r2_c_cat_T | _r2_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _GEN_15 = io_req_bits_cmd_0 == 5'h7; // @[MSHR.scala:12:7]
wire _r2_c_cat_T_3; // @[Consts.scala:90:66]
assign _r2_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _r2_c_cat_T_26; // @[Consts.scala:90:66]
assign _r2_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _needs_second_acq_T_3; // @[Consts.scala:90:66]
assign _needs_second_acq_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _dirties_cat_T_3; // @[Consts.scala:90:66]
assign _dirties_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _dirties_cat_T_26; // @[Consts.scala:90:66]
assign _dirties_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _r_c_cat_T_3; // @[Consts.scala:90:66]
assign _r_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _r_c_cat_T_26; // @[Consts.scala:90:66]
assign _r_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _r2_c_cat_T_4 = _r2_c_cat_T_2 | _r2_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _GEN_16 = io_req_bits_cmd_0 == 5'h4; // @[MSHR.scala:12:7]
wire _r2_c_cat_T_5; // @[package.scala:16:47]
assign _r2_c_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _r2_c_cat_T_28; // @[package.scala:16:47]
assign _r2_c_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _needs_second_acq_T_5; // @[package.scala:16:47]
assign _needs_second_acq_T_5 = _GEN_16; // @[package.scala:16:47]
wire _dirties_cat_T_5; // @[package.scala:16:47]
assign _dirties_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _dirties_cat_T_28; // @[package.scala:16:47]
assign _dirties_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _r_c_cat_T_5; // @[package.scala:16:47]
assign _r_c_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _r_c_cat_T_28; // @[package.scala:16:47]
assign _r_c_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _GEN_17 = io_req_bits_cmd_0 == 5'h9; // @[MSHR.scala:12:7]
wire _r2_c_cat_T_6; // @[package.scala:16:47]
assign _r2_c_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _r2_c_cat_T_29; // @[package.scala:16:47]
assign _r2_c_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _needs_second_acq_T_6; // @[package.scala:16:47]
assign _needs_second_acq_T_6 = _GEN_17; // @[package.scala:16:47]
wire _dirties_cat_T_6; // @[package.scala:16:47]
assign _dirties_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _dirties_cat_T_29; // @[package.scala:16:47]
assign _dirties_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _r_c_cat_T_6; // @[package.scala:16:47]
assign _r_c_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _r_c_cat_T_29; // @[package.scala:16:47]
assign _r_c_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _GEN_18 = io_req_bits_cmd_0 == 5'hA; // @[MSHR.scala:12:7]
wire _r2_c_cat_T_7; // @[package.scala:16:47]
assign _r2_c_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _r2_c_cat_T_30; // @[package.scala:16:47]
assign _r2_c_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _needs_second_acq_T_7; // @[package.scala:16:47]
assign _needs_second_acq_T_7 = _GEN_18; // @[package.scala:16:47]
wire _dirties_cat_T_7; // @[package.scala:16:47]
assign _dirties_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _dirties_cat_T_30; // @[package.scala:16:47]
assign _dirties_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _r_c_cat_T_7; // @[package.scala:16:47]
assign _r_c_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _r_c_cat_T_30; // @[package.scala:16:47]
assign _r_c_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _GEN_19 = io_req_bits_cmd_0 == 5'hB; // @[MSHR.scala:12:7]
wire _r2_c_cat_T_8; // @[package.scala:16:47]
assign _r2_c_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _r2_c_cat_T_31; // @[package.scala:16:47]
assign _r2_c_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _needs_second_acq_T_8; // @[package.scala:16:47]
assign _needs_second_acq_T_8 = _GEN_19; // @[package.scala:16:47]
wire _dirties_cat_T_8; // @[package.scala:16:47]
assign _dirties_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _dirties_cat_T_31; // @[package.scala:16:47]
assign _dirties_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _r_c_cat_T_8; // @[package.scala:16:47]
assign _r_c_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _r_c_cat_T_31; // @[package.scala:16:47]
assign _r_c_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _r2_c_cat_T_9 = _r2_c_cat_T_5 | _r2_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_10 = _r2_c_cat_T_9 | _r2_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_11 = _r2_c_cat_T_10 | _r2_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _GEN_20 = io_req_bits_cmd_0 == 5'h8; // @[MSHR.scala:12:7]
wire _r2_c_cat_T_12; // @[package.scala:16:47]
assign _r2_c_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _r2_c_cat_T_35; // @[package.scala:16:47]
assign _r2_c_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _needs_second_acq_T_12; // @[package.scala:16:47]
assign _needs_second_acq_T_12 = _GEN_20; // @[package.scala:16:47]
wire _dirties_cat_T_12; // @[package.scala:16:47]
assign _dirties_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _dirties_cat_T_35; // @[package.scala:16:47]
assign _dirties_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _r_c_cat_T_12; // @[package.scala:16:47]
assign _r_c_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _r_c_cat_T_35; // @[package.scala:16:47]
assign _r_c_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _GEN_21 = io_req_bits_cmd_0 == 5'hC; // @[MSHR.scala:12:7]
wire _r2_c_cat_T_13; // @[package.scala:16:47]
assign _r2_c_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _r2_c_cat_T_36; // @[package.scala:16:47]
assign _r2_c_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _needs_second_acq_T_13; // @[package.scala:16:47]
assign _needs_second_acq_T_13 = _GEN_21; // @[package.scala:16:47]
wire _dirties_cat_T_13; // @[package.scala:16:47]
assign _dirties_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _dirties_cat_T_36; // @[package.scala:16:47]
assign _dirties_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _r_c_cat_T_13; // @[package.scala:16:47]
assign _r_c_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _r_c_cat_T_36; // @[package.scala:16:47]
assign _r_c_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _GEN_22 = io_req_bits_cmd_0 == 5'hD; // @[MSHR.scala:12:7]
wire _r2_c_cat_T_14; // @[package.scala:16:47]
assign _r2_c_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _r2_c_cat_T_37; // @[package.scala:16:47]
assign _r2_c_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _needs_second_acq_T_14; // @[package.scala:16:47]
assign _needs_second_acq_T_14 = _GEN_22; // @[package.scala:16:47]
wire _dirties_cat_T_14; // @[package.scala:16:47]
assign _dirties_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _dirties_cat_T_37; // @[package.scala:16:47]
assign _dirties_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _r_c_cat_T_14; // @[package.scala:16:47]
assign _r_c_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _r_c_cat_T_37; // @[package.scala:16:47]
assign _r_c_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _GEN_23 = io_req_bits_cmd_0 == 5'hE; // @[MSHR.scala:12:7]
wire _r2_c_cat_T_15; // @[package.scala:16:47]
assign _r2_c_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _r2_c_cat_T_38; // @[package.scala:16:47]
assign _r2_c_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _needs_second_acq_T_15; // @[package.scala:16:47]
assign _needs_second_acq_T_15 = _GEN_23; // @[package.scala:16:47]
wire _dirties_cat_T_15; // @[package.scala:16:47]
assign _dirties_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _dirties_cat_T_38; // @[package.scala:16:47]
assign _dirties_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _r_c_cat_T_15; // @[package.scala:16:47]
assign _r_c_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _r_c_cat_T_38; // @[package.scala:16:47]
assign _r_c_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _GEN_24 = io_req_bits_cmd_0 == 5'hF; // @[MSHR.scala:12:7]
wire _r2_c_cat_T_16; // @[package.scala:16:47]
assign _r2_c_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _r2_c_cat_T_39; // @[package.scala:16:47]
assign _r2_c_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _needs_second_acq_T_16; // @[package.scala:16:47]
assign _needs_second_acq_T_16 = _GEN_24; // @[package.scala:16:47]
wire _dirties_cat_T_16; // @[package.scala:16:47]
assign _dirties_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _dirties_cat_T_39; // @[package.scala:16:47]
assign _dirties_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _r_c_cat_T_16; // @[package.scala:16:47]
assign _r_c_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _r_c_cat_T_39; // @[package.scala:16:47]
assign _r_c_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _r2_c_cat_T_17 = _r2_c_cat_T_12 | _r2_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_18 = _r2_c_cat_T_17 | _r2_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_19 = _r2_c_cat_T_18 | _r2_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_20 = _r2_c_cat_T_19 | _r2_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_21 = _r2_c_cat_T_11 | _r2_c_cat_T_20; // @[package.scala:81:59]
wire _r2_c_cat_T_22 = _r2_c_cat_T_4 | _r2_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r2_c_cat_T_25 = _r2_c_cat_T_23 | _r2_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r2_c_cat_T_27 = _r2_c_cat_T_25 | _r2_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r2_c_cat_T_32 = _r2_c_cat_T_28 | _r2_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_33 = _r2_c_cat_T_32 | _r2_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_34 = _r2_c_cat_T_33 | _r2_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_40 = _r2_c_cat_T_35 | _r2_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_41 = _r2_c_cat_T_40 | _r2_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_42 = _r2_c_cat_T_41 | _r2_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_43 = _r2_c_cat_T_42 | _r2_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_44 = _r2_c_cat_T_34 | _r2_c_cat_T_43; // @[package.scala:81:59]
wire _r2_c_cat_T_45 = _r2_c_cat_T_27 | _r2_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _GEN_25 = io_req_bits_cmd_0 == 5'h3; // @[MSHR.scala:12:7]
wire _r2_c_cat_T_46; // @[Consts.scala:91:54]
assign _r2_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _needs_second_acq_T_23; // @[Consts.scala:91:54]
assign _needs_second_acq_T_23 = _GEN_25; // @[Consts.scala:91:54]
wire _dirties_cat_T_46; // @[Consts.scala:91:54]
assign _dirties_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _rpq_io_enq_valid_T_4; // @[Consts.scala:88:52]
assign _rpq_io_enq_valid_T_4 = _GEN_25; // @[Consts.scala:88:52, :91:54]
wire _r_c_cat_T_46; // @[Consts.scala:91:54]
assign _r_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _r2_c_cat_T_47 = _r2_c_cat_T_45 | _r2_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _GEN_26 = io_req_bits_cmd_0 == 5'h6; // @[MSHR.scala:12:7]
wire _r2_c_cat_T_48; // @[Consts.scala:91:71]
assign _r2_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _needs_second_acq_T_25; // @[Consts.scala:91:71]
assign _needs_second_acq_T_25 = _GEN_26; // @[Consts.scala:91:71]
wire _dirties_cat_T_48; // @[Consts.scala:91:71]
assign _dirties_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _r_c_cat_T_48; // @[Consts.scala:91:71]
assign _r_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _r2_c_cat_T_49 = _r2_c_cat_T_47 | _r2_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r2_c = {_r2_c_cat_T_22, _r2_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r2_T = {r2_c, new_coh_state}; // @[MSHR.scala:45:24]
wire _r2_T_25 = _r2_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r2_T_27 = {1'h0, _r2_T_25}; // @[Misc.scala:35:36, :49:20]
wire _r2_T_28 = _r2_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r2_T_30 = _r2_T_28 ? 2'h2 : _r2_T_27; // @[Misc.scala:35:36, :49:20]
wire _r2_T_31 = _r2_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r2_T_33 = _r2_T_31 ? 2'h1 : _r2_T_30; // @[Misc.scala:35:36, :49:20]
wire _r2_T_34 = _r2_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r2_T_36 = _r2_T_34 ? 2'h2 : _r2_T_33; // @[Misc.scala:35:36, :49:20]
wire _r2_T_37 = _r2_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r2_T_39 = _r2_T_37 ? 2'h0 : _r2_T_36; // @[Misc.scala:35:36, :49:20]
wire _r2_T_40 = _r2_T == 4'hE; // @[Misc.scala:49:20]
wire _r2_T_41 = _r2_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_42 = _r2_T_40 ? 2'h3 : _r2_T_39; // @[Misc.scala:35:36, :49:20]
wire _r2_T_43 = &_r2_T; // @[Misc.scala:49:20]
wire _r2_T_44 = _r2_T_43 | _r2_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_45 = _r2_T_43 ? 2'h3 : _r2_T_42; // @[Misc.scala:35:36, :49:20]
wire _r2_T_46 = _r2_T == 4'h6; // @[Misc.scala:49:20]
wire _r2_T_47 = _r2_T_46 | _r2_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_48 = _r2_T_46 ? 2'h2 : _r2_T_45; // @[Misc.scala:35:36, :49:20]
wire _r2_T_49 = _r2_T == 4'h7; // @[Misc.scala:49:20]
wire _r2_T_50 = _r2_T_49 | _r2_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_51 = _r2_T_49 ? 2'h3 : _r2_T_48; // @[Misc.scala:35:36, :49:20]
wire _r2_T_52 = _r2_T == 4'h1; // @[Misc.scala:49:20]
wire _r2_T_53 = _r2_T_52 | _r2_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_54 = _r2_T_52 ? 2'h1 : _r2_T_51; // @[Misc.scala:35:36, :49:20]
wire _r2_T_55 = _r2_T == 4'h2; // @[Misc.scala:49:20]
wire _r2_T_56 = _r2_T_55 | _r2_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_57 = _r2_T_55 ? 2'h2 : _r2_T_54; // @[Misc.scala:35:36, :49:20]
wire _r2_T_58 = _r2_T == 4'h3; // @[Misc.scala:49:20]
wire r2_1 = _r2_T_58 | _r2_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] r2_2 = _r2_T_58 ? 2'h3 : _r2_T_57; // @[Misc.scala:35:36, :49:20]
wire _needs_second_acq_T_2 = _needs_second_acq_T | _needs_second_acq_T_1; // @[Consts.scala:90:{32,42,49}]
wire _needs_second_acq_T_4 = _needs_second_acq_T_2 | _needs_second_acq_T_3; // @[Consts.scala:90:{42,59,66}]
wire _needs_second_acq_T_9 = _needs_second_acq_T_5 | _needs_second_acq_T_6; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_10 = _needs_second_acq_T_9 | _needs_second_acq_T_7; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_11 = _needs_second_acq_T_10 | _needs_second_acq_T_8; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_17 = _needs_second_acq_T_12 | _needs_second_acq_T_13; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_18 = _needs_second_acq_T_17 | _needs_second_acq_T_14; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_19 = _needs_second_acq_T_18 | _needs_second_acq_T_15; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_20 = _needs_second_acq_T_19 | _needs_second_acq_T_16; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_21 = _needs_second_acq_T_11 | _needs_second_acq_T_20; // @[package.scala:81:59]
wire _needs_second_acq_T_22 = _needs_second_acq_T_4 | _needs_second_acq_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _needs_second_acq_T_24 = _needs_second_acq_T_22 | _needs_second_acq_T_23; // @[Consts.scala:90:76, :91:{47,54}]
wire _needs_second_acq_T_26 = _needs_second_acq_T_24 | _needs_second_acq_T_25; // @[Consts.scala:91:{47,64,71}]
wire _needs_second_acq_T_29 = _needs_second_acq_T_27 | _needs_second_acq_T_28; // @[Consts.scala:90:{32,42,49}]
wire _needs_second_acq_T_31 = _needs_second_acq_T_29 | _needs_second_acq_T_30; // @[Consts.scala:90:{42,59,66}]
wire _needs_second_acq_T_36 = _needs_second_acq_T_32 | _needs_second_acq_T_33; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_37 = _needs_second_acq_T_36 | _needs_second_acq_T_34; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_38 = _needs_second_acq_T_37 | _needs_second_acq_T_35; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_44 = _needs_second_acq_T_39 | _needs_second_acq_T_40; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_45 = _needs_second_acq_T_44 | _needs_second_acq_T_41; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_46 = _needs_second_acq_T_45 | _needs_second_acq_T_42; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_47 = _needs_second_acq_T_46 | _needs_second_acq_T_43; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_48 = _needs_second_acq_T_38 | _needs_second_acq_T_47; // @[package.scala:81:59]
wire _needs_second_acq_T_49 = _needs_second_acq_T_31 | _needs_second_acq_T_48; // @[Consts.scala:87:44, :90:{59,76}]
wire _needs_second_acq_T_51 = _needs_second_acq_T_49 | _needs_second_acq_T_50; // @[Consts.scala:90:76, :91:{47,54}]
wire _needs_second_acq_T_53 = _needs_second_acq_T_51 | _needs_second_acq_T_52; // @[Consts.scala:91:{47,64,71}]
wire _needs_second_acq_T_54 = ~_needs_second_acq_T_53; // @[Metadata.scala:104:57]
wire cmd_requires_second_acquire = _needs_second_acq_T_26 & _needs_second_acq_T_54; // @[Metadata.scala:104:{54,57}]
wire is_hit_again = r1_1 & r2_1; // @[Misc.scala:35:9]
wire _dirties_cat_T_2 = _dirties_cat_T | _dirties_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _dirties_cat_T_4 = _dirties_cat_T_2 | _dirties_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _dirties_cat_T_9 = _dirties_cat_T_5 | _dirties_cat_T_6; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_10 = _dirties_cat_T_9 | _dirties_cat_T_7; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_11 = _dirties_cat_T_10 | _dirties_cat_T_8; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_17 = _dirties_cat_T_12 | _dirties_cat_T_13; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_18 = _dirties_cat_T_17 | _dirties_cat_T_14; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_19 = _dirties_cat_T_18 | _dirties_cat_T_15; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_20 = _dirties_cat_T_19 | _dirties_cat_T_16; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_21 = _dirties_cat_T_11 | _dirties_cat_T_20; // @[package.scala:81:59]
wire _dirties_cat_T_22 = _dirties_cat_T_4 | _dirties_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _dirties_cat_T_25 = _dirties_cat_T_23 | _dirties_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _dirties_cat_T_27 = _dirties_cat_T_25 | _dirties_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _dirties_cat_T_32 = _dirties_cat_T_28 | _dirties_cat_T_29; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_33 = _dirties_cat_T_32 | _dirties_cat_T_30; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_34 = _dirties_cat_T_33 | _dirties_cat_T_31; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_40 = _dirties_cat_T_35 | _dirties_cat_T_36; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_41 = _dirties_cat_T_40 | _dirties_cat_T_37; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_42 = _dirties_cat_T_41 | _dirties_cat_T_38; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_43 = _dirties_cat_T_42 | _dirties_cat_T_39; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_44 = _dirties_cat_T_34 | _dirties_cat_T_43; // @[package.scala:81:59]
wire _dirties_cat_T_45 = _dirties_cat_T_27 | _dirties_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _dirties_cat_T_47 = _dirties_cat_T_45 | _dirties_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _dirties_cat_T_49 = _dirties_cat_T_47 | _dirties_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] dirties_cat = {_dirties_cat_T_22, _dirties_cat_T_49}; // @[Metadata.scala:29:18]
wire dirties = &dirties_cat; // @[Metadata.scala:29:18, :106:42]
wire [1:0] biggest_grow_param = dirties ? r2_2 : r1_2; // @[Misc.scala:35:36]
wire [1:0] dirtier_coh_state = biggest_grow_param; // @[Metadata.scala:107:33, :160:20]
wire [4:0] dirtier_cmd = dirties ? io_req_bits_cmd_0 : req_cmd; // @[MSHR.scala:12:7, :38:16]
wire [26:0] _r_beats1_decode_T = 27'hFFF << io_mem_grant_bits_size_0; // @[MSHR.scala:12:7]
wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire r_beats1_opdata = io_mem_grant_bits_opcode_0[0]; // @[MSHR.scala:12:7]
wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] r_counter; // @[Edges.scala:229:27]
wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28]
wire r_1_1 = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire r_2 = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire refill_done = r_2 & io_mem_grant_valid_0; // @[MSHR.scala:12:7]
wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _r_counter_T = r_1_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] refill_address_inc = {r_4, 3'h0}; // @[Edges.scala:234:25, :269:29]
wire _GEN_27 = state == 4'h1; // @[MSHR.scala:36:22]
wire _sec_rdy_T; // @[package.scala:16:47]
assign _sec_rdy_T = _GEN_27; // @[package.scala:16:47]
wire _io_probe_rdy_T_3; // @[package.scala:16:47]
assign _io_probe_rdy_T_3 = _GEN_27; // @[package.scala:16:47]
assign _io_wb_req_valid_T = _GEN_27; // @[MSHR.scala:153:28]
wire _T_11 = state == 4'h2; // @[MSHR.scala:36:22]
wire _sec_rdy_T_1; // @[package.scala:16:47]
assign _sec_rdy_T_1 = _T_11; // @[package.scala:16:47]
wire _io_probe_rdy_T_4; // @[package.scala:16:47]
assign _io_probe_rdy_T_4 = _T_11; // @[package.scala:16:47]
wire _T_9 = state == 4'h3; // @[MSHR.scala:36:22]
wire _sec_rdy_T_2; // @[package.scala:16:47]
assign _sec_rdy_T_2 = _T_9; // @[package.scala:16:47]
wire _io_probe_rdy_T_5; // @[package.scala:16:47]
assign _io_probe_rdy_T_5 = _T_9; // @[package.scala:16:47]
wire _io_meta_write_valid_T_1; // @[package.scala:16:47]
assign _io_meta_write_valid_T_1 = _T_9; // @[package.scala:16:47]
wire _io_meta_write_bits_data_coh_T; // @[MSHR.scala:149:44]
assign _io_meta_write_bits_data_coh_T = _T_9; // @[MSHR.scala:149:44]
wire _sec_rdy_T_3 = _sec_rdy_T | _sec_rdy_T_1; // @[package.scala:16:47, :81:59]
wire _sec_rdy_T_4 = _sec_rdy_T_3 | _sec_rdy_T_2; // @[package.scala:16:47, :81:59]
wire _GEN_28 = state == 4'h4; // @[MSHR.scala:36:22]
wire _sec_rdy_T_5; // @[package.scala:16:47]
assign _sec_rdy_T_5 = _GEN_28; // @[package.scala:16:47]
wire _can_finish_T_1; // @[package.scala:16:47]
assign _can_finish_T_1 = _GEN_28; // @[package.scala:16:47]
wire _io_mem_acquire_valid_T; // @[MSHR.scala:161:33]
assign _io_mem_acquire_valid_T = _GEN_28; // @[MSHR.scala:161:33]
wire _sec_rdy_T_6 = state == 4'h5; // @[MSHR.scala:36:22]
wire _sec_rdy_T_7 = _sec_rdy_T_5 | _sec_rdy_T_6; // @[package.scala:16:47, :81:59]
wire _sec_rdy_T_8 = ~cmd_requires_second_acquire; // @[MSHR.scala:61:23]
wire _sec_rdy_T_9 = _sec_rdy_T_7 & _sec_rdy_T_8; // @[MSHR.scala:60:65, :61:23]
wire _sec_rdy_T_10 = ~refill_done; // @[MSHR.scala:61:55]
wire _sec_rdy_T_11 = _sec_rdy_T_9 & _sec_rdy_T_10; // @[MSHR.scala:60:65, :61:{52,55}]
wire _sec_rdy_T_12 = _sec_rdy_T_4 | _sec_rdy_T_11; // @[MSHR.scala:59:56, :61:52]
wire sec_rdy = idx_match & _sec_rdy_T_12; // @[MSHR.scala:42:27, :58:27, :59:56]
wire _rpq_io_enq_valid_T = io_req_pri_val_0 & io_req_pri_rdy_0; // @[MSHR.scala:12:7, :64:39]
wire _rpq_io_enq_valid_T_1 = io_req_sec_val_0 & sec_rdy; // @[MSHR.scala:12:7, :58:27, :64:75]
wire _rpq_io_enq_valid_T_2 = _rpq_io_enq_valid_T | _rpq_io_enq_valid_T_1; // @[MSHR.scala:64:{39,57,75}]
wire _rpq_io_enq_valid_T_3 = io_req_bits_cmd_0 == 5'h2; // @[MSHR.scala:12:7]
wire _rpq_io_enq_valid_T_5 = _rpq_io_enq_valid_T_3 | _rpq_io_enq_valid_T_4; // @[Consts.scala:88:{35,45,52}]
wire _rpq_io_enq_valid_T_6 = ~_rpq_io_enq_valid_T_5; // @[MSHR.scala:64:90]
wire _rpq_io_enq_valid_T_7 = _rpq_io_enq_valid_T_2 & _rpq_io_enq_valid_T_6; // @[MSHR.scala:64:{57,87,90}]
wire _T_19 = state == 4'h8; // @[MSHR.scala:36:22, :66:49]
wire _rpq_io_deq_ready_T; // @[MSHR.scala:66:49]
assign _rpq_io_deq_ready_T = _T_19; // @[MSHR.scala:66:49]
wire _io_replay_valid_T; // @[MSHR.scala:168:28]
assign _io_replay_valid_T = _T_19; // @[MSHR.scala:66:49, :168:28]
wire _rpq_io_deq_ready_T_4; // @[MSHR.scala:176:48]
assign _rpq_io_deq_ready_T_4 = _T_19; // @[MSHR.scala:66:49, :176:48]
wire _rpq_io_deq_ready_T_1 = io_replay_ready_0 & _rpq_io_deq_ready_T; // @[MSHR.scala:12:7, :66:{40,49}]
wire _rpq_io_deq_ready_T_2 = ~(|state); // @[MSHR.scala:36:22, :66:75]
wire _rpq_io_deq_ready_T_3 = _rpq_io_deq_ready_T_1 | _rpq_io_deq_ready_T_2; // @[MSHR.scala:66:{40,66,75}]
reg acked; // @[MSHR.scala:68:18]
wire _io_meta_write_valid_T = state == 4'h6; // @[MSHR.scala:36:22, :78:15]
wire [3:0] _needs_wb_r_T_6 = {2'h2, io_req_bits_old_meta_coh_state_0}; // @[MSHR.scala:12:7]
wire _needs_wb_r_T_19 = _needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_21 = _needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_23 = _needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_25 = _needs_wb_r_T_23 ? 3'h2 : _needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_27 = _needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_29 = _needs_wb_r_T_27 ? 3'h1 : _needs_wb_r_T_25; // @[MSHR.scala:142:59]
wire _needs_wb_r_T_31 = _needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20]
wire _needs_wb_r_T_32 = _needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_33 = _needs_wb_r_T_31 ? 3'h1 : _needs_wb_r_T_29; // @[MSHR.scala:142:59]
wire _needs_wb_r_T_35 = _needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20]
wire _needs_wb_r_T_36 = ~_needs_wb_r_T_35 & _needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_37 = _needs_wb_r_T_35 ? 3'h5 : _needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_39 = _needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20]
wire _needs_wb_r_T_40 = ~_needs_wb_r_T_39 & _needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_41 = _needs_wb_r_T_39 ? 3'h4 : _needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_42 = {1'h0, _needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_43 = _needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20]
wire _needs_wb_r_T_44 = ~_needs_wb_r_T_43 & _needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_45 = _needs_wb_r_T_43 ? 3'h0 : _needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_46 = _needs_wb_r_T_43 ? 2'h1 : _needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_47 = _needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20]
wire _needs_wb_r_T_48 = _needs_wb_r_T_47 | _needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_49 = _needs_wb_r_T_47 ? 3'h0 : _needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_50 = _needs_wb_r_T_47 ? 2'h1 : _needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_51 = _needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20]
wire _needs_wb_r_T_52 = ~_needs_wb_r_T_51 & _needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_53 = _needs_wb_r_T_51 ? 3'h5 : _needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_54 = _needs_wb_r_T_51 ? 2'h0 : _needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_55 = _needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20]
wire _needs_wb_r_T_56 = ~_needs_wb_r_T_55 & _needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_57 = _needs_wb_r_T_55 ? 3'h4 : _needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_58 = _needs_wb_r_T_55 ? 2'h1 : _needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_59 = _needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20]
wire _needs_wb_r_T_60 = ~_needs_wb_r_T_59 & _needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_61 = _needs_wb_r_T_59 ? 3'h3 : _needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_62 = _needs_wb_r_T_59 ? 2'h2 : _needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_63 = _needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20]
wire needs_wb = _needs_wb_r_T_63 | _needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20]
wire [2:0] needs_wb_r_2 = _needs_wb_r_T_63 ? 3'h3 : _needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20]
wire [1:0] needs_wb_r_3 = _needs_wb_r_T_63 ? 2'h2 : _needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20]
wire [1:0] needs_wb_meta_state = needs_wb_r_3; // @[Misc.scala:38:63]
wire _r_c_cat_T_2 = _r_c_cat_T | _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_4 = _r_c_cat_T_2 | _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_9 = _r_c_cat_T_5 | _r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_10 = _r_c_cat_T_9 | _r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_11 = _r_c_cat_T_10 | _r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_17 = _r_c_cat_T_12 | _r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_18 = _r_c_cat_T_17 | _r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_19 = _r_c_cat_T_18 | _r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_20 = _r_c_cat_T_19 | _r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_21 = _r_c_cat_T_11 | _r_c_cat_T_20; // @[package.scala:81:59]
wire _r_c_cat_T_22 = _r_c_cat_T_4 | _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_25 = _r_c_cat_T_23 | _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_27 = _r_c_cat_T_25 | _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_32 = _r_c_cat_T_28 | _r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_33 = _r_c_cat_T_32 | _r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_34 = _r_c_cat_T_33 | _r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_40 = _r_c_cat_T_35 | _r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_41 = _r_c_cat_T_40 | _r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_42 = _r_c_cat_T_41 | _r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_43 = _r_c_cat_T_42 | _r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_44 = _r_c_cat_T_34 | _r_c_cat_T_43; // @[package.scala:81:59]
wire _r_c_cat_T_45 = _r_c_cat_T_27 | _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_47 = _r_c_cat_T_45 | _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _r_c_cat_T_49 = _r_c_cat_T_47 | _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r_T_64 = {r_c, io_req_bits_old_meta_coh_state_0}; // @[MSHR.scala:12:7]
wire _r_T_89 = _r_T_64 == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r_T_91 = {1'h0, _r_T_89}; // @[Misc.scala:35:36, :49:20]
wire _r_T_92 = _r_T_64 == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r_T_94 = _r_T_92 ? 2'h2 : _r_T_91; // @[Misc.scala:35:36, :49:20]
wire _r_T_95 = _r_T_64 == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r_T_97 = _r_T_95 ? 2'h1 : _r_T_94; // @[Misc.scala:35:36, :49:20]
wire _r_T_98 = _r_T_64 == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r_T_100 = _r_T_98 ? 2'h2 : _r_T_97; // @[Misc.scala:35:36, :49:20]
wire _r_T_101 = _r_T_64 == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r_T_103 = _r_T_101 ? 2'h0 : _r_T_100; // @[Misc.scala:35:36, :49:20]
wire _r_T_104 = _r_T_64 == 4'hE; // @[Misc.scala:49:20]
wire _r_T_105 = _r_T_104; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_106 = _r_T_104 ? 2'h3 : _r_T_103; // @[Misc.scala:35:36, :49:20]
wire _r_T_107 = &_r_T_64; // @[Misc.scala:49:20]
wire _r_T_108 = _r_T_107 | _r_T_105; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_109 = _r_T_107 ? 2'h3 : _r_T_106; // @[Misc.scala:35:36, :49:20]
wire _r_T_110 = _r_T_64 == 4'h6; // @[Misc.scala:49:20]
wire _r_T_111 = _r_T_110 | _r_T_108; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_112 = _r_T_110 ? 2'h2 : _r_T_109; // @[Misc.scala:35:36, :49:20]
wire _r_T_113 = _r_T_64 == 4'h7; // @[Misc.scala:49:20]
wire _r_T_114 = _r_T_113 | _r_T_111; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_115 = _r_T_113 ? 2'h3 : _r_T_112; // @[Misc.scala:35:36, :49:20]
wire _r_T_116 = _r_T_64 == 4'h1; // @[Misc.scala:49:20]
wire _r_T_117 = _r_T_116 | _r_T_114; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_118 = _r_T_116 ? 2'h1 : _r_T_115; // @[Misc.scala:35:36, :49:20]
wire _r_T_119 = _r_T_64 == 4'h2; // @[Misc.scala:49:20]
wire _r_T_120 = _r_T_119 | _r_T_117; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_121 = _r_T_119 ? 2'h2 : _r_T_118; // @[Misc.scala:35:36, :49:20]
wire _r_T_122 = _r_T_64 == 4'h3; // @[Misc.scala:49:20]
wire is_hit = _r_T_122 | _r_T_120; // @[Misc.scala:35:9, :49:20]
wire [1:0] r_2_1 = _r_T_122 ? 2'h3 : _r_T_121; // @[Misc.scala:35:36, :49:20]
wire [1:0] coh_on_hit_state = r_2_1; // @[Misc.scala:35:36]
wire [3:0] _state_T = {2'h0, ~needs_wb, 1'h1}; // @[MSHR.scala:122:19]
wire _can_finish_T = ~(|state); // @[MSHR.scala:36:22, :66:75]
wire can_finish = _can_finish_T | _can_finish_T_1; // @[package.scala:16:47, :81:59]
wire _grantackq_io_enq_valid_T = io_mem_grant_bits_opcode_0[2]; // @[MSHR.scala:12:7]
wire _grantackq_io_enq_valid_T_1 = io_mem_grant_bits_opcode_0[1]; // @[MSHR.scala:12:7]
wire _grantackq_io_enq_valid_T_2 = ~_grantackq_io_enq_valid_T_1; // @[Edges.scala:71:{43,52}]
wire _grantackq_io_enq_valid_T_3 = _grantackq_io_enq_valid_T & _grantackq_io_enq_valid_T_2; // @[Edges.scala:71:{36,40,43}]
wire _grantackq_io_enq_valid_T_4 = refill_done & _grantackq_io_enq_valid_T_3; // @[MSHR.scala:128:41]
assign _io_mem_finish_valid_T = _grantackq_io_deq_valid & can_finish; // @[MSHR.scala:126:25, :130:49]
assign io_mem_finish_valid_0 = _io_mem_finish_valid_T; // @[MSHR.scala:12:7, :130:49]
wire _grantackq_io_deq_ready_T = io_mem_finish_ready_0 & can_finish; // @[MSHR.scala:12:7, :132:49]
wire _io_idx_match_T = |state; // @[MSHR.scala:36:22, :66:75, :134:26]
assign _io_idx_match_T_1 = _io_idx_match_T & idx_match; // @[MSHR.scala:42:27, :134:{26,41}]
assign io_idx_match_0 = _io_idx_match_T_1; // @[MSHR.scala:12:7, :134:41]
wire [39:0] _io_refill_addr_T = {req_block_addr[39:12], req_block_addr[11:0] | refill_address_inc}; // @[MSHR.scala:41:51, :136:36]
assign io_refill_addr_0 = _io_refill_addr_T[11:0]; // @[MSHR.scala:12:7, :136:{18,36}]
assign io_tag_0 = req_tag_0[19:0]; // @[MSHR.scala:12:7, :40:26, :137:10]
assign _io_req_pri_rdy_T = ~(|state); // @[MSHR.scala:36:22, :66:75, :138:27]
assign io_req_pri_rdy_0 = _io_req_pri_rdy_T; // @[MSHR.scala:12:7, :138:27]
assign _io_req_sec_rdy_T = sec_rdy & _rpq_io_enq_ready; // @[MSHR.scala:58:27, :63:19, :139:29]
assign io_req_sec_rdy_0 = _io_req_sec_rdy_T; // @[MSHR.scala:12:7, :139:29]
reg [1:0] meta_hazard; // @[MSHR.scala:141:28]
wire [2:0] _meta_hazard_T = {1'h0, meta_hazard} + 3'h1; // @[MSHR.scala:141:28, :142:59]
wire [1:0] _meta_hazard_T_1 = _meta_hazard_T[1:0]; // @[MSHR.scala:142:59]
wire _io_probe_rdy_T = |state; // @[MSHR.scala:36:22, :66:75, :144:27]
wire _io_probe_rdy_T_1 = _io_probe_rdy_T & probe_idx_match; // @[MSHR.scala:43:33, :144:{27,41}]
wire _io_probe_rdy_T_2 = ~_io_probe_rdy_T_1; // @[MSHR.scala:144:{19,41}]
wire _io_probe_rdy_T_6 = _io_probe_rdy_T_3 | _io_probe_rdy_T_4; // @[package.scala:16:47, :81:59]
wire _io_probe_rdy_T_7 = _io_probe_rdy_T_6 | _io_probe_rdy_T_5; // @[package.scala:16:47, :81:59]
wire _io_probe_rdy_T_8 = ~_io_probe_rdy_T_7; // @[MSHR.scala:144:65]
wire _io_probe_rdy_T_9 = meta_hazard == 2'h0; // @[MSHR.scala:141:28, :144:117]
wire _io_probe_rdy_T_10 = _io_probe_rdy_T_8 & _io_probe_rdy_T_9; // @[MSHR.scala:144:{65,102,117}]
assign _io_probe_rdy_T_11 = _io_probe_rdy_T_2 | _io_probe_rdy_T_10; // @[MSHR.scala:144:{19,61,102}]
assign io_probe_rdy_0 = _io_probe_rdy_T_11; // @[MSHR.scala:12:7, :144:61]
assign _io_meta_write_valid_T_2 = _io_meta_write_valid_T | _io_meta_write_valid_T_1; // @[package.scala:16:47, :81:59]
assign io_meta_write_valid_0 = _io_meta_write_valid_T_2; // @[MSHR.scala:12:7]
assign _io_meta_write_bits_data_coh_T_1_state = _io_meta_write_bits_data_coh_T ? coh_on_clear_state : new_coh_state; // @[MSHR.scala:45:24, :149:{37,44}]
assign io_meta_write_bits_data_coh_state_0 = _io_meta_write_bits_data_coh_T_1_state; // @[MSHR.scala:12:7, :149:37]
assign io_wb_req_valid_0 = _io_wb_req_valid_T; // @[MSHR.scala:12:7, :153:28]
assign _io_mem_acquire_valid_T_1 = _io_mem_acquire_valid_T & _grantackq_io_enq_ready; // @[MSHR.scala:126:25, :161:{33,50}]
assign io_mem_acquire_valid_0 = _io_mem_acquire_valid_T_1; // @[MSHR.scala:12:7, :161:50]
wire [25:0] _GEN_29 = {io_tag_0, req_idx}; // @[MSHR.scala:12:7, :39:25, :164:48]
wire [25:0] _io_mem_acquire_bits_T; // @[MSHR.scala:164:48]
assign _io_mem_acquire_bits_T = _GEN_29; // @[MSHR.scala:164:48]
wire [25:0] io_replay_bits_addr_hi; // @[MSHR.scala:170:29]
assign io_replay_bits_addr_hi = _GEN_29; // @[MSHR.scala:164:48, :170:29]
wire [31:0] _io_mem_acquire_bits_T_1 = {_io_mem_acquire_bits_T, 6'h0}; // @[MSHR.scala:41:51, :164:{48,66}]
wire [31:0] _io_mem_acquire_bits_legal_T_1 = _io_mem_acquire_bits_T_1; // @[MSHR.scala:164:66]
assign io_mem_acquire_bits_a_address = _io_mem_acquire_bits_T_1; // @[MSHR.scala:164:66]
wire [32:0] _io_mem_acquire_bits_legal_T_2 = {1'h0, _io_mem_acquire_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _io_mem_acquire_bits_legal_T_3 = _io_mem_acquire_bits_legal_T_2 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _io_mem_acquire_bits_legal_T_4 = _io_mem_acquire_bits_legal_T_3; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_5 = _io_mem_acquire_bits_legal_T_4 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _io_mem_acquire_bits_legal_T_6 = {_io_mem_acquire_bits_T_1[31:17], _io_mem_acquire_bits_T_1[16:0] ^ 17'h10000}; // @[MSHR.scala:164:66]
wire [32:0] _io_mem_acquire_bits_legal_T_7 = {1'h0, _io_mem_acquire_bits_legal_T_6}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _io_mem_acquire_bits_legal_T_8 = _io_mem_acquire_bits_legal_T_7 & 33'h8C011000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _io_mem_acquire_bits_legal_T_9 = _io_mem_acquire_bits_legal_T_8; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_10 = _io_mem_acquire_bits_legal_T_9 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _io_mem_acquire_bits_legal_T_11 = {_io_mem_acquire_bits_T_1[31:28], _io_mem_acquire_bits_T_1[27:0] ^ 28'hC000000}; // @[MSHR.scala:164:66]
wire [32:0] _io_mem_acquire_bits_legal_T_12 = {1'h0, _io_mem_acquire_bits_legal_T_11}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _io_mem_acquire_bits_legal_T_13 = _io_mem_acquire_bits_legal_T_12 & 33'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _io_mem_acquire_bits_legal_T_14 = _io_mem_acquire_bits_legal_T_13; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_15 = _io_mem_acquire_bits_legal_T_14 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _io_mem_acquire_bits_legal_T_16 = _io_mem_acquire_bits_legal_T_5 | _io_mem_acquire_bits_legal_T_10; // @[Parameters.scala:685:42]
wire _io_mem_acquire_bits_legal_T_17 = _io_mem_acquire_bits_legal_T_16 | _io_mem_acquire_bits_legal_T_15; // @[Parameters.scala:685:42]
wire [31:0] _io_mem_acquire_bits_legal_T_21 = {_io_mem_acquire_bits_T_1[31:28], _io_mem_acquire_bits_T_1[27:0] ^ 28'h8000000}; // @[MSHR.scala:164:66]
wire [32:0] _io_mem_acquire_bits_legal_T_22 = {1'h0, _io_mem_acquire_bits_legal_T_21}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _io_mem_acquire_bits_legal_T_23 = _io_mem_acquire_bits_legal_T_22 & 33'h8C010000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _io_mem_acquire_bits_legal_T_24 = _io_mem_acquire_bits_legal_T_23; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_25 = _io_mem_acquire_bits_legal_T_24 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] _io_mem_acquire_bits_legal_T_26 = _io_mem_acquire_bits_T_1 ^ 32'h80000000; // @[MSHR.scala:164:66]
wire [32:0] _io_mem_acquire_bits_legal_T_27 = {1'h0, _io_mem_acquire_bits_legal_T_26}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _io_mem_acquire_bits_legal_T_28 = _io_mem_acquire_bits_legal_T_27 & 33'h80000000; // @[Parameters.scala:137:{41,46}]
wire [32:0] _io_mem_acquire_bits_legal_T_29 = _io_mem_acquire_bits_legal_T_28; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_30 = _io_mem_acquire_bits_legal_T_29 == 33'h0; // @[Parameters.scala:137:{46,59}]
wire _io_mem_acquire_bits_legal_T_31 = _io_mem_acquire_bits_legal_T_25 | _io_mem_acquire_bits_legal_T_30; // @[Parameters.scala:685:42]
wire _io_mem_acquire_bits_legal_T_32 = _io_mem_acquire_bits_legal_T_31; // @[Parameters.scala:684:54, :685:42]
wire io_mem_acquire_bits_legal = _io_mem_acquire_bits_legal_T_32; // @[Parameters.scala:684:54, :686:26]
assign io_mem_acquire_bits_param_0 = io_mem_acquire_bits_a_param; // @[MSHR.scala:12:7]
assign io_mem_acquire_bits_address_0 = io_mem_acquire_bits_a_address; // @[MSHR.scala:12:7]
assign io_mem_acquire_bits_a_param = {1'h0, grow_param}; // @[Misc.scala:35:36]
wire io_mem_acquire_bits_a_mask_sub_sub_bit = _io_mem_acquire_bits_T_1[2]; // @[MSHR.scala:164:66]
wire io_mem_acquire_bits_a_mask_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T = io_mem_acquire_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38]
wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = io_mem_acquire_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_sub_bit = _io_mem_acquire_bits_T_1[1]; // @[MSHR.scala:164:66]
wire io_mem_acquire_bits_a_mask_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire io_mem_acquire_bits_a_mask_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire io_mem_acquire_bits_a_mask_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_bit = _io_mem_acquire_bits_T_1[0]; // @[MSHR.scala:164:66]
wire io_mem_acquire_bits_a_mask_nbit = ~io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_eq = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T = io_mem_acquire_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_1 = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_1 = io_mem_acquire_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_2 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_2 = io_mem_acquire_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_3 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_3 = io_mem_acquire_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_4 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_4 = io_mem_acquire_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_5 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_5 = io_mem_acquire_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_6 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_6 = io_mem_acquire_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_7 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_7 = io_mem_acquire_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38]
assign _io_replay_valid_T_1 = _io_replay_valid_T & _rpq_io_deq_valid; // @[MSHR.scala:63:19, :168:{28,44}]
assign io_replay_valid_0 = _io_replay_valid_T_1; // @[MSHR.scala:12:7, :168:44]
wire [5:0] _io_replay_bits_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[MSHR.scala:63:19, :170:67]
wire [31:0] _io_replay_bits_addr_T_1 = {io_replay_bits_addr_hi, _io_replay_bits_addr_T}; // @[MSHR.scala:170:{29,67}]
assign io_replay_bits_addr_0 = {8'h0, _io_replay_bits_addr_T_1}; // @[MSHR.scala:12:7, :170:{23,29}]
wire _state_T_1 = ~_rpq_io_deq_valid; // @[MSHR.scala:63:19, :71:34, :174:26]
reg state_REG; // @[MSHR.scala:174:25]
wire [3:0] _state_T_2 = state_REG ? 4'h0 : state; // @[MSHR.scala:36:22, :174:{17,25}]
wire _rpq_io_deq_ready_T_5 = io_replay_ready_0 & _rpq_io_deq_ready_T_4; // @[MSHR.scala:12:7, :176:{39,48}]
wire _T_7 = _sec_rdy_T_6 & refill_done; // @[MSHR.scala:81:33]
wire _T_15 = io_req_sec_val_0 & io_req_sec_rdy_0; // @[MSHR.scala:12:7, :97:24]
always @(posedge clock) begin // @[MSHR.scala:12:7]
if (reset) begin // @[MSHR.scala:12:7]
state <= 4'h0; // @[MSHR.scala:36:22]
new_coh_state <= 2'h0; // @[MSHR.scala:45:24]
r_counter <= 9'h0; // @[Edges.scala:229:27]
meta_hazard <= 2'h0; // @[MSHR.scala:141:28]
end
else begin // @[MSHR.scala:12:7]
if (_T_19 & ~_rpq_io_deq_valid) // @[MSHR.scala:63:19, :66:49, :71:34, :173:31]
state <= _state_T_2; // @[MSHR.scala:36:22, :174:17]
else if (_rpq_io_enq_valid_T) // @[MSHR.scala:64:39]
state <= io_req_bits_tag_match_0 ? {2'h1, is_hit, 1'h0} : _state_T; // @[MSHR.scala:12:7, :36:22, :112:34, :113:21, :115:15, :118:15, :122:{13,19}]
else if (io_wb_req_ready_0 & io_wb_req_valid_0) // @[Decoupled.scala:51:35]
state <= 4'h2; // @[MSHR.scala:36:22]
else if (_T_11 & io_wb_req_ready_0 & acked) // @[MSHR.scala:12:7, :68:18, :91:{29,48}]
state <= 4'h3; // @[MSHR.scala:36:22]
else if (_T_9 & io_meta_write_ready_0) // @[MSHR.scala:12:7, :88:32]
state <= 4'h4; // @[MSHR.scala:36:22]
else if (io_mem_acquire_ready_0 & io_mem_acquire_valid_0) // @[Decoupled.scala:51:35]
state <= 4'h5; // @[MSHR.scala:36:22]
else if (_T_7) // @[MSHR.scala:81:33]
state <= 4'h6; // @[MSHR.scala:36:22]
else if (_io_meta_write_valid_T & io_meta_write_ready_0) // @[MSHR.scala:12:7, :78:36]
state <= 4'h7; // @[MSHR.scala:36:22]
else if (state == 4'h7) // @[MSHR.scala:36:22, :74:15]
state <= 4'h8; // @[MSHR.scala:36:22]
else if (_T_19 & ~_rpq_io_deq_valid) // @[MSHR.scala:63:19, :66:49, :71:{31,34}]
state <= 4'h0; // @[MSHR.scala:36:22]
if (_rpq_io_enq_valid_T) // @[MSHR.scala:64:39]
new_coh_state <= io_req_bits_tag_match_0 ? (is_hit ? coh_on_hit_state : io_req_bits_old_meta_coh_state_0) : 2'h0; // @[MSHR.scala:12:7, :45:24, :112:34, :113:21, :114:17, :117:17, :121:15]
else if (_T_15 & is_hit_again) // @[MSHR.scala:81:49, :97:{24,43}, :102:25, :103:15]
new_coh_state <= dirtier_coh_state; // @[MSHR.scala:45:24]
else if (_T_7) // @[MSHR.scala:81:33]
new_coh_state <= coh_on_grant_state; // @[MSHR.scala:45:24]
if (io_mem_grant_valid_0) // @[MSHR.scala:12:7]
r_counter <= _r_counter_T; // @[Edges.scala:229:27, :236:21]
if (io_meta_write_ready_0 & io_meta_write_valid_0) // @[Decoupled.scala:51:35]
meta_hazard <= 2'h1; // @[MSHR.scala:141:28]
else if (|meta_hazard) // @[MSHR.scala:141:28, :142:21]
meta_hazard <= _meta_hazard_T_1; // @[MSHR.scala:141:28, :142:59]
end
if (_rpq_io_enq_valid_T) begin // @[MSHR.scala:64:39]
req_addr <= io_req_bits_addr_0; // @[MSHR.scala:12:7, :38:16]
req_tag <= io_req_bits_tag_0; // @[MSHR.scala:12:7, :38:16]
req_cmd <= io_req_bits_cmd_0; // @[MSHR.scala:12:7, :38:16]
req_size <= io_req_bits_size_0; // @[MSHR.scala:12:7, :38:16]
req_signed <= io_req_bits_signed_0; // @[MSHR.scala:12:7, :38:16]
req_data <= io_req_bits_data_0; // @[MSHR.scala:12:7, :38:16]
req_mask <= io_req_bits_mask_0; // @[MSHR.scala:12:7, :38:16]
req_tag_match <= io_req_bits_tag_match_0; // @[MSHR.scala:12:7, :38:16]
req_old_meta_coh_state <= io_req_bits_old_meta_coh_state_0; // @[MSHR.scala:12:7, :38:16]
req_old_meta_tag <= io_req_bits_old_meta_tag_0; // @[MSHR.scala:12:7, :38:16]
req_way_en <= io_req_bits_way_en_0; // @[MSHR.scala:12:7, :38:16]
req_sdq_id <= io_req_bits_sdq_id_0; // @[MSHR.scala:12:7, :38:16]
end
else if (_T_15) // @[MSHR.scala:97:24]
req_cmd <= dirtier_cmd; // @[MSHR.scala:38:16]
acked <= ~_rpq_io_enq_valid_T & (io_mem_grant_valid_0 | acked); // @[MSHR.scala:12:7, :64:39, :68:18, :69:{29,37}, :106:43, :108:11]
state_REG <= _state_T_1; // @[MSHR.scala:174:{25,26}]
always @(posedge)
Queue16_ShuttleMSHRReq_1 rpq ( // @[MSHR.scala:63:19]
.clock (clock),
.reset (reset),
.io_enq_ready (_rpq_io_enq_ready),
.io_enq_valid (_rpq_io_enq_valid_T_7), // @[MSHR.scala:64:87]
.io_enq_bits_addr (io_req_bits_addr_0), // @[MSHR.scala:12:7]
.io_enq_bits_tag (io_req_bits_tag_0), // @[MSHR.scala:12:7]
.io_enq_bits_cmd (io_req_bits_cmd_0), // @[MSHR.scala:12:7]
.io_enq_bits_size (io_req_bits_size_0), // @[MSHR.scala:12:7]
.io_enq_bits_signed (io_req_bits_signed_0), // @[MSHR.scala:12:7]
.io_enq_bits_data (io_req_bits_data_0), // @[MSHR.scala:12:7]
.io_enq_bits_mask (io_req_bits_mask_0), // @[MSHR.scala:12:7]
.io_enq_bits_tag_match (io_req_bits_tag_match_0), // @[MSHR.scala:12:7]
.io_enq_bits_old_meta_coh_state (io_req_bits_old_meta_coh_state_0), // @[MSHR.scala:12:7]
.io_enq_bits_old_meta_tag (io_req_bits_old_meta_tag_0), // @[MSHR.scala:12:7]
.io_enq_bits_way_en (io_req_bits_way_en_0), // @[MSHR.scala:12:7]
.io_enq_bits_sdq_id (io_req_bits_sdq_id_0), // @[MSHR.scala:12:7]
.io_deq_ready (_rpq_io_deq_ready_T_5), // @[MSHR.scala:176:39]
.io_deq_valid (_rpq_io_deq_valid),
.io_deq_bits_addr (_rpq_io_deq_bits_addr),
.io_deq_bits_tag (io_replay_bits_tag_0),
.io_deq_bits_cmd (io_replay_bits_cmd_0),
.io_deq_bits_size (io_replay_bits_size_0),
.io_deq_bits_signed (io_replay_bits_signed_0),
.io_deq_bits_data (io_replay_bits_data_0),
.io_deq_bits_mask (io_replay_bits_mask_0),
.io_deq_bits_tag_match (io_replay_bits_tag_match_0),
.io_deq_bits_old_meta_coh_state (io_replay_bits_old_meta_coh_state_0),
.io_deq_bits_old_meta_tag (io_replay_bits_old_meta_tag_0),
.io_deq_bits_way_en (io_replay_bits_way_en_0),
.io_deq_bits_sdq_id (io_replay_bits_sdq_id_0)
); // @[MSHR.scala:63:19]
Queue1_TLBundleE_a32d64s3k3z4c_1 grantackq ( // @[MSHR.scala:126:25]
.clock (clock),
.reset (reset),
.io_enq_ready (_grantackq_io_enq_ready),
.io_enq_valid (_grantackq_io_enq_valid_T_4), // @[MSHR.scala:128:41]
.io_enq_bits_sink (grantackq_io_enq_bits_e_sink), // @[Edges.scala:451:17]
.io_deq_ready (_grantackq_io_deq_ready_T), // @[MSHR.scala:132:49]
.io_deq_valid (_grantackq_io_deq_valid),
.io_deq_bits_sink (io_mem_finish_bits_sink_0)
); // @[MSHR.scala:126:25]
assign io_req_pri_rdy = io_req_pri_rdy_0; // @[MSHR.scala:12:7]
assign io_req_sec_rdy = io_req_sec_rdy_0; // @[MSHR.scala:12:7]
assign io_idx_match = io_idx_match_0; // @[MSHR.scala:12:7]
assign io_tag = io_tag_0; // @[MSHR.scala:12:7]
assign io_mem_acquire_valid = io_mem_acquire_valid_0; // @[MSHR.scala:12:7]
assign io_mem_acquire_bits_param = io_mem_acquire_bits_param_0; // @[MSHR.scala:12:7]
assign io_mem_acquire_bits_address = io_mem_acquire_bits_address_0; // @[MSHR.scala:12:7]
assign io_mem_finish_valid = io_mem_finish_valid_0; // @[MSHR.scala:12:7]
assign io_mem_finish_bits_sink = io_mem_finish_bits_sink_0; // @[MSHR.scala:12:7]
assign io_refill_way_en = io_refill_way_en_0; // @[MSHR.scala:12:7]
assign io_refill_addr = io_refill_addr_0; // @[MSHR.scala:12:7]
assign io_meta_write_valid = io_meta_write_valid_0; // @[MSHR.scala:12:7]
assign io_meta_write_bits_idx = io_meta_write_bits_idx_0; // @[MSHR.scala:12:7]
assign io_meta_write_bits_way_en = io_meta_write_bits_way_en_0; // @[MSHR.scala:12:7]
assign io_meta_write_bits_tag = io_meta_write_bits_tag_0; // @[MSHR.scala:12:7]
assign io_meta_write_bits_data_coh_state = io_meta_write_bits_data_coh_state_0; // @[MSHR.scala:12:7]
assign io_meta_write_bits_data_tag = io_meta_write_bits_data_tag_0; // @[MSHR.scala:12:7]
assign io_replay_valid = io_replay_valid_0; // @[MSHR.scala:12:7]
assign io_replay_bits_addr = io_replay_bits_addr_0; // @[MSHR.scala:12:7]
assign io_replay_bits_tag = io_replay_bits_tag_0; // @[MSHR.scala:12:7]
assign io_replay_bits_cmd = io_replay_bits_cmd_0; // @[MSHR.scala:12:7]
assign io_replay_bits_size = io_replay_bits_size_0; // @[MSHR.scala:12:7]
assign io_replay_bits_signed = io_replay_bits_signed_0; // @[MSHR.scala:12:7]
assign io_replay_bits_data = io_replay_bits_data_0; // @[MSHR.scala:12:7]
assign io_replay_bits_mask = io_replay_bits_mask_0; // @[MSHR.scala:12:7]
assign io_replay_bits_tag_match = io_replay_bits_tag_match_0; // @[MSHR.scala:12:7]
assign io_replay_bits_old_meta_coh_state = io_replay_bits_old_meta_coh_state_0; // @[MSHR.scala:12:7]
assign io_replay_bits_old_meta_tag = io_replay_bits_old_meta_tag_0; // @[MSHR.scala:12:7]
assign io_replay_bits_way_en = io_replay_bits_way_en_0; // @[MSHR.scala:12:7]
assign io_replay_bits_sdq_id = io_replay_bits_sdq_id_0; // @[MSHR.scala:12:7]
assign io_wb_req_valid = io_wb_req_valid_0; // @[MSHR.scala:12:7]
assign io_wb_req_bits_tag = io_wb_req_bits_tag_0; // @[MSHR.scala:12:7]
assign io_wb_req_bits_idx = io_wb_req_bits_idx_0; // @[MSHR.scala:12:7]
assign io_wb_req_bits_param = io_wb_req_bits_param_0; // @[MSHR.scala:12:7]
assign io_wb_req_bits_way_en = io_wb_req_bits_way_en_0; // @[MSHR.scala:12:7]
assign io_probe_rdy = io_probe_rdy_0; // @[MSHR.scala:12:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_78 :
input clock : Clock
input reset : Reset
output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], credit_return : UInt<2>, vc_free : UInt<2>}}
wire _in_flight_WIRE : UInt<1>[2]
connect _in_flight_WIRE[0], UInt<1>(0h0)
connect _in_flight_WIRE[1], UInt<1>(0h0)
regreset in_flight : UInt<1>[2], clock, reset, _in_flight_WIRE
when io.in.flit[0].valid :
when io.in.flit[0].bits.head :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1)
node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
when io.in.flit[0].bits.tail :
connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)
node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T_4 :
node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0))
node _T_6 = or(_T_5, UInt<1>(0h0))
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1
assert(clock, _T_6, UInt<1>(0h1), "") : assert_1
node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1))
node _T_11 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h5))
node _T_12 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_13 = and(_T_11, _T_12)
node _T_14 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_15 = and(_T_13, _T_14)
node _T_16 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h6))
node _T_19 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_20 = and(_T_18, _T_19)
node _T_21 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_22 = and(_T_20, _T_21)
node _T_23 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_24 = and(_T_22, _T_23)
node _T_25 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0h9))
node _T_26 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_27 = and(_T_25, _T_26)
node _T_28 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_29 = and(_T_27, _T_28)
node _T_30 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_31 = and(_T_29, _T_30)
node _T_32 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<4>(0ha))
node _T_33 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hc))
node _T_34 = and(_T_32, _T_33)
node _T_35 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0))
node _T_36 = and(_T_34, _T_35)
node _T_37 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0))
node _T_38 = and(_T_36, _T_37)
node _T_39 = or(_T_17, _T_24)
node _T_40 = or(_T_39, _T_31)
node _T_41 = or(_T_40, _T_38)
node _T_42 = or(_T_10, _T_41)
node _T_43 = asUInt(reset)
node _T_44 = eq(_T_43, UInt<1>(0h0))
when _T_44 :
node _T_45 = eq(_T_42, UInt<1>(0h0))
when _T_45 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2
assert(clock, _T_42, UInt<1>(0h1), "") : assert_2 | module NoCMonitor_78( // @[Monitor.scala:11:7]
input clock, // @[Monitor.scala:11:7]
input reset, // @[Monitor.scala:11:7]
input io_in_flit_0_valid, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_head, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14]
input io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14]
);
reg in_flight_0; // @[Monitor.scala:16:26]
reg in_flight_1; // @[Monitor.scala:16:26] |
Generate the Verilog code corresponding to this FIRRTL code module PE_189 :
input clock : Clock
input reset : Reset
output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>}
node _reg_T = eq(io.dir, UInt<1>(0h0))
node _reg_T_1 = mux(_reg_T, io.inR, io.inD)
reg reg : SInt<8>, clock
when io.en :
connect reg, _reg_T_1
connect io.outU, reg
connect io.outL, reg | module PE_189( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Tile_26 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_282
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_26( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_282 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_11 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<9>(0h110))
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0)
node _source_ok_T_1 = shr(io.in.a.bits.source, 2)
node _source_ok_T_2 = eq(_source_ok_T_1, UInt<7>(0h40))
node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3)
node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3))
node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5)
node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0)
node _source_ok_T_7 = shr(io.in.a.bits.source, 2)
node _source_ok_T_8 = eq(_source_ok_T_7, UInt<7>(0h41))
node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9)
node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3))
node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11)
node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0)
node _source_ok_T_13 = shr(io.in.a.bits.source, 2)
node _source_ok_T_14 = eq(_source_ok_T_13, UInt<7>(0h42))
node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2)
node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15)
node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3))
node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17)
node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0)
node _source_ok_T_19 = shr(io.in.a.bits.source, 2)
node _source_ok_T_20 = eq(_source_ok_T_19, UInt<7>(0h43))
node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3)
node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21)
node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3))
node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23)
node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 4, 0)
node _source_ok_T_28 = shr(io.in.a.bits.source, 5)
node _source_ok_T_29 = eq(_source_ok_T_28, UInt<1>(0h0))
node _source_ok_T_30 = leq(UInt<1>(0h0), source_ok_uncommonBits_4)
node _source_ok_T_31 = and(_source_ok_T_29, _source_ok_T_30)
node _source_ok_T_32 = leq(source_ok_uncommonBits_4, UInt<5>(0h1f))
node _source_ok_T_33 = and(_source_ok_T_31, _source_ok_T_32)
node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 4, 0)
node _source_ok_T_34 = shr(io.in.a.bits.source, 5)
node _source_ok_T_35 = eq(_source_ok_T_34, UInt<1>(0h1))
node _source_ok_T_36 = leq(UInt<1>(0h0), source_ok_uncommonBits_5)
node _source_ok_T_37 = and(_source_ok_T_35, _source_ok_T_36)
node _source_ok_T_38 = leq(source_ok_uncommonBits_5, UInt<5>(0h1f))
node _source_ok_T_39 = and(_source_ok_T_37, _source_ok_T_38)
node _source_ok_uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 4, 0)
node _source_ok_T_40 = shr(io.in.a.bits.source, 5)
node _source_ok_T_41 = eq(_source_ok_T_40, UInt<2>(0h2))
node _source_ok_T_42 = leq(UInt<1>(0h0), source_ok_uncommonBits_6)
node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42)
node _source_ok_T_44 = leq(source_ok_uncommonBits_6, UInt<5>(0h1f))
node _source_ok_T_45 = and(_source_ok_T_43, _source_ok_T_44)
node _source_ok_uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 4, 0)
node _source_ok_T_46 = shr(io.in.a.bits.source, 5)
node _source_ok_T_47 = eq(_source_ok_T_46, UInt<2>(0h3))
node _source_ok_T_48 = leq(UInt<1>(0h0), source_ok_uncommonBits_7)
node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48)
node _source_ok_T_50 = leq(source_ok_uncommonBits_7, UInt<5>(0h1f))
node _source_ok_T_51 = and(_source_ok_T_49, _source_ok_T_50)
node _source_ok_uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 4, 0)
node _source_ok_T_52 = shr(io.in.a.bits.source, 5)
node _source_ok_T_53 = eq(_source_ok_T_52, UInt<3>(0h4))
node _source_ok_T_54 = leq(UInt<1>(0h0), source_ok_uncommonBits_8)
node _source_ok_T_55 = and(_source_ok_T_53, _source_ok_T_54)
node _source_ok_T_56 = leq(source_ok_uncommonBits_8, UInt<5>(0h1f))
node _source_ok_T_57 = and(_source_ok_T_55, _source_ok_T_56)
node _source_ok_uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 4, 0)
node _source_ok_T_58 = shr(io.in.a.bits.source, 5)
node _source_ok_T_59 = eq(_source_ok_T_58, UInt<3>(0h5))
node _source_ok_T_60 = leq(UInt<1>(0h0), source_ok_uncommonBits_9)
node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60)
node _source_ok_T_62 = leq(source_ok_uncommonBits_9, UInt<5>(0h1f))
node _source_ok_T_63 = and(_source_ok_T_61, _source_ok_T_62)
node _source_ok_uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 4, 0)
node _source_ok_T_64 = shr(io.in.a.bits.source, 5)
node _source_ok_T_65 = eq(_source_ok_T_64, UInt<3>(0h6))
node _source_ok_T_66 = leq(UInt<1>(0h0), source_ok_uncommonBits_10)
node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66)
node _source_ok_T_68 = leq(source_ok_uncommonBits_10, UInt<5>(0h1f))
node _source_ok_T_69 = and(_source_ok_T_67, _source_ok_T_68)
node _source_ok_uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 4, 0)
node _source_ok_T_70 = shr(io.in.a.bits.source, 5)
node _source_ok_T_71 = eq(_source_ok_T_70, UInt<3>(0h7))
node _source_ok_T_72 = leq(UInt<1>(0h0), source_ok_uncommonBits_11)
node _source_ok_T_73 = and(_source_ok_T_71, _source_ok_T_72)
node _source_ok_T_74 = leq(source_ok_uncommonBits_11, UInt<5>(0h1f))
node _source_ok_T_75 = and(_source_ok_T_73, _source_ok_T_74)
node _source_ok_T_76 = eq(io.in.a.bits.source, UInt<10>(0h200))
wire _source_ok_WIRE : UInt<1>[17]
connect _source_ok_WIRE[0], _source_ok_T
connect _source_ok_WIRE[1], _source_ok_T_6
connect _source_ok_WIRE[2], _source_ok_T_12
connect _source_ok_WIRE[3], _source_ok_T_18
connect _source_ok_WIRE[4], _source_ok_T_24
connect _source_ok_WIRE[5], _source_ok_T_25
connect _source_ok_WIRE[6], _source_ok_T_26
connect _source_ok_WIRE[7], _source_ok_T_27
connect _source_ok_WIRE[8], _source_ok_T_33
connect _source_ok_WIRE[9], _source_ok_T_39
connect _source_ok_WIRE[10], _source_ok_T_45
connect _source_ok_WIRE[11], _source_ok_T_51
connect _source_ok_WIRE[12], _source_ok_T_57
connect _source_ok_WIRE[13], _source_ok_T_63
connect _source_ok_WIRE[14], _source_ok_T_69
connect _source_ok_WIRE[15], _source_ok_T_75
connect _source_ok_WIRE[16], _source_ok_T_76
node _source_ok_T_77 = or(_source_ok_WIRE[0], _source_ok_WIRE[1])
node _source_ok_T_78 = or(_source_ok_T_77, _source_ok_WIRE[2])
node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE[3])
node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE[4])
node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE[5])
node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE[6])
node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE[7])
node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE[8])
node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE[9])
node _source_ok_T_86 = or(_source_ok_T_85, _source_ok_WIRE[10])
node _source_ok_T_87 = or(_source_ok_T_86, _source_ok_WIRE[11])
node _source_ok_T_88 = or(_source_ok_T_87, _source_ok_WIRE[12])
node _source_ok_T_89 = or(_source_ok_T_88, _source_ok_WIRE[13])
node _source_ok_T_90 = or(_source_ok_T_89, _source_ok_WIRE[14])
node _source_ok_T_91 = or(_source_ok_T_90, _source_ok_WIRE[15])
node source_ok = or(_source_ok_T_91, _source_ok_WIRE[16])
node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits = bits(_uncommonBits_T, 1, 0)
node _T_12 = shr(io.in.a.bits.source, 2)
node _T_13 = eq(_T_12, UInt<7>(0h40))
node _T_14 = leq(UInt<1>(0h0), uncommonBits)
node _T_15 = and(_T_13, _T_14)
node _T_16 = leq(uncommonBits, UInt<2>(0h3))
node _T_17 = and(_T_15, _T_16)
node _T_18 = eq(_T_17, UInt<1>(0h0))
node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_20 = cvt(_T_19)
node _T_21 = and(_T_20, asSInt(UInt<1>(0h0)))
node _T_22 = asSInt(_T_21)
node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0)))
node _T_24 = or(_T_18, _T_23)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0)
node _T_25 = shr(io.in.a.bits.source, 2)
node _T_26 = eq(_T_25, UInt<7>(0h41))
node _T_27 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_28 = and(_T_26, _T_27)
node _T_29 = leq(uncommonBits_1, UInt<2>(0h3))
node _T_30 = and(_T_28, _T_29)
node _T_31 = eq(_T_30, UInt<1>(0h0))
node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_33 = cvt(_T_32)
node _T_34 = and(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = asSInt(_T_34)
node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0)))
node _T_37 = or(_T_31, _T_36)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0)
node _T_38 = shr(io.in.a.bits.source, 2)
node _T_39 = eq(_T_38, UInt<7>(0h42))
node _T_40 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_41 = and(_T_39, _T_40)
node _T_42 = leq(uncommonBits_2, UInt<2>(0h3))
node _T_43 = and(_T_41, _T_42)
node _T_44 = eq(_T_43, UInt<1>(0h0))
node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_44, _T_49)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0)
node _T_51 = shr(io.in.a.bits.source, 2)
node _T_52 = eq(_T_51, UInt<7>(0h43))
node _T_53 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_54 = and(_T_52, _T_53)
node _T_55 = leq(uncommonBits_3, UInt<2>(0h3))
node _T_56 = and(_T_54, _T_55)
node _T_57 = eq(_T_56, UInt<1>(0h0))
node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<1>(0h0)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = or(_T_57, _T_62)
node _T_64 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_67 = cvt(_T_66)
node _T_68 = and(_T_67, asSInt(UInt<1>(0h0)))
node _T_69 = asSInt(_T_68)
node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0)))
node _T_71 = or(_T_65, _T_70)
node _T_72 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_73 = eq(_T_72, UInt<1>(0h0))
node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_75 = cvt(_T_74)
node _T_76 = and(_T_75, asSInt(UInt<1>(0h0)))
node _T_77 = asSInt(_T_76)
node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0)))
node _T_79 = or(_T_73, _T_78)
node _T_80 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _T_81 = eq(_T_80, UInt<1>(0h0))
node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_83 = cvt(_T_82)
node _T_84 = and(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = asSInt(_T_84)
node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0)))
node _T_87 = or(_T_81, _T_86)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 4, 0)
node _T_88 = shr(io.in.a.bits.source, 5)
node _T_89 = eq(_T_88, UInt<1>(0h0))
node _T_90 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_91 = and(_T_89, _T_90)
node _T_92 = leq(uncommonBits_4, UInt<5>(0h1f))
node _T_93 = and(_T_91, _T_92)
node _T_94 = eq(_T_93, UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<1>(0h0)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = or(_T_94, _T_99)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 4, 0)
node _T_101 = shr(io.in.a.bits.source, 5)
node _T_102 = eq(_T_101, UInt<1>(0h1))
node _T_103 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_104 = and(_T_102, _T_103)
node _T_105 = leq(uncommonBits_5, UInt<5>(0h1f))
node _T_106 = and(_T_104, _T_105)
node _T_107 = eq(_T_106, UInt<1>(0h0))
node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_109 = cvt(_T_108)
node _T_110 = and(_T_109, asSInt(UInt<1>(0h0)))
node _T_111 = asSInt(_T_110)
node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0)))
node _T_113 = or(_T_107, _T_112)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 4, 0)
node _T_114 = shr(io.in.a.bits.source, 5)
node _T_115 = eq(_T_114, UInt<2>(0h2))
node _T_116 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_117 = and(_T_115, _T_116)
node _T_118 = leq(uncommonBits_6, UInt<5>(0h1f))
node _T_119 = and(_T_117, _T_118)
node _T_120 = eq(_T_119, UInt<1>(0h0))
node _T_121 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_122 = cvt(_T_121)
node _T_123 = and(_T_122, asSInt(UInt<1>(0h0)))
node _T_124 = asSInt(_T_123)
node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0)))
node _T_126 = or(_T_120, _T_125)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 4, 0)
node _T_127 = shr(io.in.a.bits.source, 5)
node _T_128 = eq(_T_127, UInt<2>(0h3))
node _T_129 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_130 = and(_T_128, _T_129)
node _T_131 = leq(uncommonBits_7, UInt<5>(0h1f))
node _T_132 = and(_T_130, _T_131)
node _T_133 = eq(_T_132, UInt<1>(0h0))
node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_135 = cvt(_T_134)
node _T_136 = and(_T_135, asSInt(UInt<1>(0h0)))
node _T_137 = asSInt(_T_136)
node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0)))
node _T_139 = or(_T_133, _T_138)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 4, 0)
node _T_140 = shr(io.in.a.bits.source, 5)
node _T_141 = eq(_T_140, UInt<3>(0h4))
node _T_142 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_143 = and(_T_141, _T_142)
node _T_144 = leq(uncommonBits_8, UInt<5>(0h1f))
node _T_145 = and(_T_143, _T_144)
node _T_146 = eq(_T_145, UInt<1>(0h0))
node _T_147 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_148 = cvt(_T_147)
node _T_149 = and(_T_148, asSInt(UInt<1>(0h0)))
node _T_150 = asSInt(_T_149)
node _T_151 = eq(_T_150, asSInt(UInt<1>(0h0)))
node _T_152 = or(_T_146, _T_151)
node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_9 = bits(_uncommonBits_T_9, 4, 0)
node _T_153 = shr(io.in.a.bits.source, 5)
node _T_154 = eq(_T_153, UInt<3>(0h5))
node _T_155 = leq(UInt<1>(0h0), uncommonBits_9)
node _T_156 = and(_T_154, _T_155)
node _T_157 = leq(uncommonBits_9, UInt<5>(0h1f))
node _T_158 = and(_T_156, _T_157)
node _T_159 = eq(_T_158, UInt<1>(0h0))
node _T_160 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_161 = cvt(_T_160)
node _T_162 = and(_T_161, asSInt(UInt<1>(0h0)))
node _T_163 = asSInt(_T_162)
node _T_164 = eq(_T_163, asSInt(UInt<1>(0h0)))
node _T_165 = or(_T_159, _T_164)
node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_10 = bits(_uncommonBits_T_10, 4, 0)
node _T_166 = shr(io.in.a.bits.source, 5)
node _T_167 = eq(_T_166, UInt<3>(0h6))
node _T_168 = leq(UInt<1>(0h0), uncommonBits_10)
node _T_169 = and(_T_167, _T_168)
node _T_170 = leq(uncommonBits_10, UInt<5>(0h1f))
node _T_171 = and(_T_169, _T_170)
node _T_172 = eq(_T_171, UInt<1>(0h0))
node _T_173 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_174 = cvt(_T_173)
node _T_175 = and(_T_174, asSInt(UInt<1>(0h0)))
node _T_176 = asSInt(_T_175)
node _T_177 = eq(_T_176, asSInt(UInt<1>(0h0)))
node _T_178 = or(_T_172, _T_177)
node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_11 = bits(_uncommonBits_T_11, 4, 0)
node _T_179 = shr(io.in.a.bits.source, 5)
node _T_180 = eq(_T_179, UInt<3>(0h7))
node _T_181 = leq(UInt<1>(0h0), uncommonBits_11)
node _T_182 = and(_T_180, _T_181)
node _T_183 = leq(uncommonBits_11, UInt<5>(0h1f))
node _T_184 = and(_T_182, _T_183)
node _T_185 = eq(_T_184, UInt<1>(0h0))
node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_187 = cvt(_T_186)
node _T_188 = and(_T_187, asSInt(UInt<1>(0h0)))
node _T_189 = asSInt(_T_188)
node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0)))
node _T_191 = or(_T_185, _T_190)
node _T_192 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_193 = eq(_T_192, UInt<1>(0h0))
node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_195 = cvt(_T_194)
node _T_196 = and(_T_195, asSInt(UInt<1>(0h0)))
node _T_197 = asSInt(_T_196)
node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0)))
node _T_199 = or(_T_193, _T_198)
node _T_200 = and(_T_11, _T_24)
node _T_201 = and(_T_200, _T_37)
node _T_202 = and(_T_201, _T_50)
node _T_203 = and(_T_202, _T_63)
node _T_204 = and(_T_203, _T_71)
node _T_205 = and(_T_204, _T_79)
node _T_206 = and(_T_205, _T_87)
node _T_207 = and(_T_206, _T_100)
node _T_208 = and(_T_207, _T_113)
node _T_209 = and(_T_208, _T_126)
node _T_210 = and(_T_209, _T_139)
node _T_211 = and(_T_210, _T_152)
node _T_212 = and(_T_211, _T_165)
node _T_213 = and(_T_212, _T_178)
node _T_214 = and(_T_213, _T_191)
node _T_215 = and(_T_214, _T_199)
node _T_216 = asUInt(reset)
node _T_217 = eq(_T_216, UInt<1>(0h0))
when _T_217 :
node _T_218 = eq(_T_215, UInt<1>(0h0))
when _T_218 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_215, UInt<1>(0h1), "") : assert_1
node _T_219 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_219 :
node _T_220 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_221 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_222 = and(_T_220, _T_221)
node _T_223 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0)
node _T_224 = shr(io.in.a.bits.source, 2)
node _T_225 = eq(_T_224, UInt<7>(0h40))
node _T_226 = leq(UInt<1>(0h0), uncommonBits_12)
node _T_227 = and(_T_225, _T_226)
node _T_228 = leq(uncommonBits_12, UInt<2>(0h3))
node _T_229 = and(_T_227, _T_228)
node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0)
node _T_230 = shr(io.in.a.bits.source, 2)
node _T_231 = eq(_T_230, UInt<7>(0h41))
node _T_232 = leq(UInt<1>(0h0), uncommonBits_13)
node _T_233 = and(_T_231, _T_232)
node _T_234 = leq(uncommonBits_13, UInt<2>(0h3))
node _T_235 = and(_T_233, _T_234)
node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0)
node _T_236 = shr(io.in.a.bits.source, 2)
node _T_237 = eq(_T_236, UInt<7>(0h42))
node _T_238 = leq(UInt<1>(0h0), uncommonBits_14)
node _T_239 = and(_T_237, _T_238)
node _T_240 = leq(uncommonBits_14, UInt<2>(0h3))
node _T_241 = and(_T_239, _T_240)
node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0)
node _T_242 = shr(io.in.a.bits.source, 2)
node _T_243 = eq(_T_242, UInt<7>(0h43))
node _T_244 = leq(UInt<1>(0h0), uncommonBits_15)
node _T_245 = and(_T_243, _T_244)
node _T_246 = leq(uncommonBits_15, UInt<2>(0h3))
node _T_247 = and(_T_245, _T_246)
node _T_248 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_249 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_250 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_16 = bits(_uncommonBits_T_16, 4, 0)
node _T_251 = shr(io.in.a.bits.source, 5)
node _T_252 = eq(_T_251, UInt<1>(0h0))
node _T_253 = leq(UInt<1>(0h0), uncommonBits_16)
node _T_254 = and(_T_252, _T_253)
node _T_255 = leq(uncommonBits_16, UInt<5>(0h1f))
node _T_256 = and(_T_254, _T_255)
node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_17 = bits(_uncommonBits_T_17, 4, 0)
node _T_257 = shr(io.in.a.bits.source, 5)
node _T_258 = eq(_T_257, UInt<1>(0h1))
node _T_259 = leq(UInt<1>(0h0), uncommonBits_17)
node _T_260 = and(_T_258, _T_259)
node _T_261 = leq(uncommonBits_17, UInt<5>(0h1f))
node _T_262 = and(_T_260, _T_261)
node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_18 = bits(_uncommonBits_T_18, 4, 0)
node _T_263 = shr(io.in.a.bits.source, 5)
node _T_264 = eq(_T_263, UInt<2>(0h2))
node _T_265 = leq(UInt<1>(0h0), uncommonBits_18)
node _T_266 = and(_T_264, _T_265)
node _T_267 = leq(uncommonBits_18, UInt<5>(0h1f))
node _T_268 = and(_T_266, _T_267)
node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_19 = bits(_uncommonBits_T_19, 4, 0)
node _T_269 = shr(io.in.a.bits.source, 5)
node _T_270 = eq(_T_269, UInt<2>(0h3))
node _T_271 = leq(UInt<1>(0h0), uncommonBits_19)
node _T_272 = and(_T_270, _T_271)
node _T_273 = leq(uncommonBits_19, UInt<5>(0h1f))
node _T_274 = and(_T_272, _T_273)
node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_20 = bits(_uncommonBits_T_20, 4, 0)
node _T_275 = shr(io.in.a.bits.source, 5)
node _T_276 = eq(_T_275, UInt<3>(0h4))
node _T_277 = leq(UInt<1>(0h0), uncommonBits_20)
node _T_278 = and(_T_276, _T_277)
node _T_279 = leq(uncommonBits_20, UInt<5>(0h1f))
node _T_280 = and(_T_278, _T_279)
node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_21 = bits(_uncommonBits_T_21, 4, 0)
node _T_281 = shr(io.in.a.bits.source, 5)
node _T_282 = eq(_T_281, UInt<3>(0h5))
node _T_283 = leq(UInt<1>(0h0), uncommonBits_21)
node _T_284 = and(_T_282, _T_283)
node _T_285 = leq(uncommonBits_21, UInt<5>(0h1f))
node _T_286 = and(_T_284, _T_285)
node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_22 = bits(_uncommonBits_T_22, 4, 0)
node _T_287 = shr(io.in.a.bits.source, 5)
node _T_288 = eq(_T_287, UInt<3>(0h6))
node _T_289 = leq(UInt<1>(0h0), uncommonBits_22)
node _T_290 = and(_T_288, _T_289)
node _T_291 = leq(uncommonBits_22, UInt<5>(0h1f))
node _T_292 = and(_T_290, _T_291)
node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_23 = bits(_uncommonBits_T_23, 4, 0)
node _T_293 = shr(io.in.a.bits.source, 5)
node _T_294 = eq(_T_293, UInt<3>(0h7))
node _T_295 = leq(UInt<1>(0h0), uncommonBits_23)
node _T_296 = and(_T_294, _T_295)
node _T_297 = leq(uncommonBits_23, UInt<5>(0h1f))
node _T_298 = and(_T_296, _T_297)
node _T_299 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_300 = or(_T_223, _T_229)
node _T_301 = or(_T_300, _T_235)
node _T_302 = or(_T_301, _T_241)
node _T_303 = or(_T_302, _T_247)
node _T_304 = or(_T_303, _T_248)
node _T_305 = or(_T_304, _T_249)
node _T_306 = or(_T_305, _T_250)
node _T_307 = or(_T_306, _T_256)
node _T_308 = or(_T_307, _T_262)
node _T_309 = or(_T_308, _T_268)
node _T_310 = or(_T_309, _T_274)
node _T_311 = or(_T_310, _T_280)
node _T_312 = or(_T_311, _T_286)
node _T_313 = or(_T_312, _T_292)
node _T_314 = or(_T_313, _T_298)
node _T_315 = or(_T_314, _T_299)
node _T_316 = and(_T_222, _T_315)
node _T_317 = or(UInt<1>(0h0), _T_316)
node _T_318 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_319 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_320 = cvt(_T_319)
node _T_321 = and(_T_320, asSInt(UInt<13>(0h1000)))
node _T_322 = asSInt(_T_321)
node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0)))
node _T_324 = and(_T_318, _T_323)
node _T_325 = or(UInt<1>(0h0), _T_324)
node _T_326 = and(_T_317, _T_325)
node _T_327 = asUInt(reset)
node _T_328 = eq(_T_327, UInt<1>(0h0))
when _T_328 :
node _T_329 = eq(_T_326, UInt<1>(0h0))
when _T_329 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_326, UInt<1>(0h1), "") : assert_2
node _T_330 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0)
node _T_331 = shr(io.in.a.bits.source, 2)
node _T_332 = eq(_T_331, UInt<7>(0h40))
node _T_333 = leq(UInt<1>(0h0), uncommonBits_24)
node _T_334 = and(_T_332, _T_333)
node _T_335 = leq(uncommonBits_24, UInt<2>(0h3))
node _T_336 = and(_T_334, _T_335)
node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0)
node _T_337 = shr(io.in.a.bits.source, 2)
node _T_338 = eq(_T_337, UInt<7>(0h41))
node _T_339 = leq(UInt<1>(0h0), uncommonBits_25)
node _T_340 = and(_T_338, _T_339)
node _T_341 = leq(uncommonBits_25, UInt<2>(0h3))
node _T_342 = and(_T_340, _T_341)
node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0)
node _T_343 = shr(io.in.a.bits.source, 2)
node _T_344 = eq(_T_343, UInt<7>(0h42))
node _T_345 = leq(UInt<1>(0h0), uncommonBits_26)
node _T_346 = and(_T_344, _T_345)
node _T_347 = leq(uncommonBits_26, UInt<2>(0h3))
node _T_348 = and(_T_346, _T_347)
node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0)
node _T_349 = shr(io.in.a.bits.source, 2)
node _T_350 = eq(_T_349, UInt<7>(0h43))
node _T_351 = leq(UInt<1>(0h0), uncommonBits_27)
node _T_352 = and(_T_350, _T_351)
node _T_353 = leq(uncommonBits_27, UInt<2>(0h3))
node _T_354 = and(_T_352, _T_353)
node _T_355 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_356 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_357 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_28 = bits(_uncommonBits_T_28, 4, 0)
node _T_358 = shr(io.in.a.bits.source, 5)
node _T_359 = eq(_T_358, UInt<1>(0h0))
node _T_360 = leq(UInt<1>(0h0), uncommonBits_28)
node _T_361 = and(_T_359, _T_360)
node _T_362 = leq(uncommonBits_28, UInt<5>(0h1f))
node _T_363 = and(_T_361, _T_362)
node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_29 = bits(_uncommonBits_T_29, 4, 0)
node _T_364 = shr(io.in.a.bits.source, 5)
node _T_365 = eq(_T_364, UInt<1>(0h1))
node _T_366 = leq(UInt<1>(0h0), uncommonBits_29)
node _T_367 = and(_T_365, _T_366)
node _T_368 = leq(uncommonBits_29, UInt<5>(0h1f))
node _T_369 = and(_T_367, _T_368)
node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_30 = bits(_uncommonBits_T_30, 4, 0)
node _T_370 = shr(io.in.a.bits.source, 5)
node _T_371 = eq(_T_370, UInt<2>(0h2))
node _T_372 = leq(UInt<1>(0h0), uncommonBits_30)
node _T_373 = and(_T_371, _T_372)
node _T_374 = leq(uncommonBits_30, UInt<5>(0h1f))
node _T_375 = and(_T_373, _T_374)
node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_31 = bits(_uncommonBits_T_31, 4, 0)
node _T_376 = shr(io.in.a.bits.source, 5)
node _T_377 = eq(_T_376, UInt<2>(0h3))
node _T_378 = leq(UInt<1>(0h0), uncommonBits_31)
node _T_379 = and(_T_377, _T_378)
node _T_380 = leq(uncommonBits_31, UInt<5>(0h1f))
node _T_381 = and(_T_379, _T_380)
node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_32 = bits(_uncommonBits_T_32, 4, 0)
node _T_382 = shr(io.in.a.bits.source, 5)
node _T_383 = eq(_T_382, UInt<3>(0h4))
node _T_384 = leq(UInt<1>(0h0), uncommonBits_32)
node _T_385 = and(_T_383, _T_384)
node _T_386 = leq(uncommonBits_32, UInt<5>(0h1f))
node _T_387 = and(_T_385, _T_386)
node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_33 = bits(_uncommonBits_T_33, 4, 0)
node _T_388 = shr(io.in.a.bits.source, 5)
node _T_389 = eq(_T_388, UInt<3>(0h5))
node _T_390 = leq(UInt<1>(0h0), uncommonBits_33)
node _T_391 = and(_T_389, _T_390)
node _T_392 = leq(uncommonBits_33, UInt<5>(0h1f))
node _T_393 = and(_T_391, _T_392)
node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_34 = bits(_uncommonBits_T_34, 4, 0)
node _T_394 = shr(io.in.a.bits.source, 5)
node _T_395 = eq(_T_394, UInt<3>(0h6))
node _T_396 = leq(UInt<1>(0h0), uncommonBits_34)
node _T_397 = and(_T_395, _T_396)
node _T_398 = leq(uncommonBits_34, UInt<5>(0h1f))
node _T_399 = and(_T_397, _T_398)
node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_35 = bits(_uncommonBits_T_35, 4, 0)
node _T_400 = shr(io.in.a.bits.source, 5)
node _T_401 = eq(_T_400, UInt<3>(0h7))
node _T_402 = leq(UInt<1>(0h0), uncommonBits_35)
node _T_403 = and(_T_401, _T_402)
node _T_404 = leq(uncommonBits_35, UInt<5>(0h1f))
node _T_405 = and(_T_403, _T_404)
node _T_406 = eq(io.in.a.bits.source, UInt<10>(0h200))
wire _WIRE : UInt<1>[17]
connect _WIRE[0], _T_330
connect _WIRE[1], _T_336
connect _WIRE[2], _T_342
connect _WIRE[3], _T_348
connect _WIRE[4], _T_354
connect _WIRE[5], _T_355
connect _WIRE[6], _T_356
connect _WIRE[7], _T_357
connect _WIRE[8], _T_363
connect _WIRE[9], _T_369
connect _WIRE[10], _T_375
connect _WIRE[11], _T_381
connect _WIRE[12], _T_387
connect _WIRE[13], _T_393
connect _WIRE[14], _T_399
connect _WIRE[15], _T_405
connect _WIRE[16], _T_406
node _T_407 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_408 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_409 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_410 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_411 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_412 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_413 = mux(_WIRE[5], _T_407, UInt<1>(0h0))
node _T_414 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_415 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_416 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_417 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_418 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_419 = mux(_WIRE[11], UInt<1>(0h0), UInt<1>(0h0))
node _T_420 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_421 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_422 = mux(_WIRE[14], UInt<1>(0h0), UInt<1>(0h0))
node _T_423 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_424 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_425 = or(_T_408, _T_409)
node _T_426 = or(_T_425, _T_410)
node _T_427 = or(_T_426, _T_411)
node _T_428 = or(_T_427, _T_412)
node _T_429 = or(_T_428, _T_413)
node _T_430 = or(_T_429, _T_414)
node _T_431 = or(_T_430, _T_415)
node _T_432 = or(_T_431, _T_416)
node _T_433 = or(_T_432, _T_417)
node _T_434 = or(_T_433, _T_418)
node _T_435 = or(_T_434, _T_419)
node _T_436 = or(_T_435, _T_420)
node _T_437 = or(_T_436, _T_421)
node _T_438 = or(_T_437, _T_422)
node _T_439 = or(_T_438, _T_423)
node _T_440 = or(_T_439, _T_424)
wire _WIRE_1 : UInt<1>
connect _WIRE_1, _T_440
node _T_441 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_442 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_443 = and(_T_441, _T_442)
node _T_444 = or(UInt<1>(0h0), _T_443)
node _T_445 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_446 = cvt(_T_445)
node _T_447 = and(_T_446, asSInt(UInt<13>(0h1000)))
node _T_448 = asSInt(_T_447)
node _T_449 = eq(_T_448, asSInt(UInt<1>(0h0)))
node _T_450 = and(_T_444, _T_449)
node _T_451 = or(UInt<1>(0h0), _T_450)
node _T_452 = and(_WIRE_1, _T_451)
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(_T_452, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_452, UInt<1>(0h1), "") : assert_3
node _T_456 = asUInt(reset)
node _T_457 = eq(_T_456, UInt<1>(0h0))
when _T_457 :
node _T_458 = eq(source_ok, UInt<1>(0h0))
when _T_458 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, source_ok, UInt<1>(0h1), "") : assert_4
node _T_459 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_459, UInt<1>(0h1), "") : assert_5
node _T_463 = asUInt(reset)
node _T_464 = eq(_T_463, UInt<1>(0h0))
when _T_464 :
node _T_465 = eq(is_aligned, UInt<1>(0h0))
when _T_465 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_466 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_467 = asUInt(reset)
node _T_468 = eq(_T_467, UInt<1>(0h0))
when _T_468 :
node _T_469 = eq(_T_466, UInt<1>(0h0))
when _T_469 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_466, UInt<1>(0h1), "") : assert_7
node _T_470 = not(io.in.a.bits.mask)
node _T_471 = eq(_T_470, UInt<1>(0h0))
node _T_472 = asUInt(reset)
node _T_473 = eq(_T_472, UInt<1>(0h0))
when _T_473 :
node _T_474 = eq(_T_471, UInt<1>(0h0))
when _T_474 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_471, UInt<1>(0h1), "") : assert_8
node _T_475 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_476 = asUInt(reset)
node _T_477 = eq(_T_476, UInt<1>(0h0))
when _T_477 :
node _T_478 = eq(_T_475, UInt<1>(0h0))
when _T_478 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_475, UInt<1>(0h1), "") : assert_9
node _T_479 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_479 :
node _T_480 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_481 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_482 = and(_T_480, _T_481)
node _T_483 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0)
node _T_484 = shr(io.in.a.bits.source, 2)
node _T_485 = eq(_T_484, UInt<7>(0h40))
node _T_486 = leq(UInt<1>(0h0), uncommonBits_36)
node _T_487 = and(_T_485, _T_486)
node _T_488 = leq(uncommonBits_36, UInt<2>(0h3))
node _T_489 = and(_T_487, _T_488)
node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0)
node _T_490 = shr(io.in.a.bits.source, 2)
node _T_491 = eq(_T_490, UInt<7>(0h41))
node _T_492 = leq(UInt<1>(0h0), uncommonBits_37)
node _T_493 = and(_T_491, _T_492)
node _T_494 = leq(uncommonBits_37, UInt<2>(0h3))
node _T_495 = and(_T_493, _T_494)
node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0)
node _T_496 = shr(io.in.a.bits.source, 2)
node _T_497 = eq(_T_496, UInt<7>(0h42))
node _T_498 = leq(UInt<1>(0h0), uncommonBits_38)
node _T_499 = and(_T_497, _T_498)
node _T_500 = leq(uncommonBits_38, UInt<2>(0h3))
node _T_501 = and(_T_499, _T_500)
node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0)
node _T_502 = shr(io.in.a.bits.source, 2)
node _T_503 = eq(_T_502, UInt<7>(0h43))
node _T_504 = leq(UInt<1>(0h0), uncommonBits_39)
node _T_505 = and(_T_503, _T_504)
node _T_506 = leq(uncommonBits_39, UInt<2>(0h3))
node _T_507 = and(_T_505, _T_506)
node _T_508 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_509 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_510 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_40 = bits(_uncommonBits_T_40, 4, 0)
node _T_511 = shr(io.in.a.bits.source, 5)
node _T_512 = eq(_T_511, UInt<1>(0h0))
node _T_513 = leq(UInt<1>(0h0), uncommonBits_40)
node _T_514 = and(_T_512, _T_513)
node _T_515 = leq(uncommonBits_40, UInt<5>(0h1f))
node _T_516 = and(_T_514, _T_515)
node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_41 = bits(_uncommonBits_T_41, 4, 0)
node _T_517 = shr(io.in.a.bits.source, 5)
node _T_518 = eq(_T_517, UInt<1>(0h1))
node _T_519 = leq(UInt<1>(0h0), uncommonBits_41)
node _T_520 = and(_T_518, _T_519)
node _T_521 = leq(uncommonBits_41, UInt<5>(0h1f))
node _T_522 = and(_T_520, _T_521)
node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_42 = bits(_uncommonBits_T_42, 4, 0)
node _T_523 = shr(io.in.a.bits.source, 5)
node _T_524 = eq(_T_523, UInt<2>(0h2))
node _T_525 = leq(UInt<1>(0h0), uncommonBits_42)
node _T_526 = and(_T_524, _T_525)
node _T_527 = leq(uncommonBits_42, UInt<5>(0h1f))
node _T_528 = and(_T_526, _T_527)
node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_43 = bits(_uncommonBits_T_43, 4, 0)
node _T_529 = shr(io.in.a.bits.source, 5)
node _T_530 = eq(_T_529, UInt<2>(0h3))
node _T_531 = leq(UInt<1>(0h0), uncommonBits_43)
node _T_532 = and(_T_530, _T_531)
node _T_533 = leq(uncommonBits_43, UInt<5>(0h1f))
node _T_534 = and(_T_532, _T_533)
node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_44 = bits(_uncommonBits_T_44, 4, 0)
node _T_535 = shr(io.in.a.bits.source, 5)
node _T_536 = eq(_T_535, UInt<3>(0h4))
node _T_537 = leq(UInt<1>(0h0), uncommonBits_44)
node _T_538 = and(_T_536, _T_537)
node _T_539 = leq(uncommonBits_44, UInt<5>(0h1f))
node _T_540 = and(_T_538, _T_539)
node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_45 = bits(_uncommonBits_T_45, 4, 0)
node _T_541 = shr(io.in.a.bits.source, 5)
node _T_542 = eq(_T_541, UInt<3>(0h5))
node _T_543 = leq(UInt<1>(0h0), uncommonBits_45)
node _T_544 = and(_T_542, _T_543)
node _T_545 = leq(uncommonBits_45, UInt<5>(0h1f))
node _T_546 = and(_T_544, _T_545)
node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_46 = bits(_uncommonBits_T_46, 4, 0)
node _T_547 = shr(io.in.a.bits.source, 5)
node _T_548 = eq(_T_547, UInt<3>(0h6))
node _T_549 = leq(UInt<1>(0h0), uncommonBits_46)
node _T_550 = and(_T_548, _T_549)
node _T_551 = leq(uncommonBits_46, UInt<5>(0h1f))
node _T_552 = and(_T_550, _T_551)
node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_47 = bits(_uncommonBits_T_47, 4, 0)
node _T_553 = shr(io.in.a.bits.source, 5)
node _T_554 = eq(_T_553, UInt<3>(0h7))
node _T_555 = leq(UInt<1>(0h0), uncommonBits_47)
node _T_556 = and(_T_554, _T_555)
node _T_557 = leq(uncommonBits_47, UInt<5>(0h1f))
node _T_558 = and(_T_556, _T_557)
node _T_559 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_560 = or(_T_483, _T_489)
node _T_561 = or(_T_560, _T_495)
node _T_562 = or(_T_561, _T_501)
node _T_563 = or(_T_562, _T_507)
node _T_564 = or(_T_563, _T_508)
node _T_565 = or(_T_564, _T_509)
node _T_566 = or(_T_565, _T_510)
node _T_567 = or(_T_566, _T_516)
node _T_568 = or(_T_567, _T_522)
node _T_569 = or(_T_568, _T_528)
node _T_570 = or(_T_569, _T_534)
node _T_571 = or(_T_570, _T_540)
node _T_572 = or(_T_571, _T_546)
node _T_573 = or(_T_572, _T_552)
node _T_574 = or(_T_573, _T_558)
node _T_575 = or(_T_574, _T_559)
node _T_576 = and(_T_482, _T_575)
node _T_577 = or(UInt<1>(0h0), _T_576)
node _T_578 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_579 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_580 = cvt(_T_579)
node _T_581 = and(_T_580, asSInt(UInt<13>(0h1000)))
node _T_582 = asSInt(_T_581)
node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0)))
node _T_584 = and(_T_578, _T_583)
node _T_585 = or(UInt<1>(0h0), _T_584)
node _T_586 = and(_T_577, _T_585)
node _T_587 = asUInt(reset)
node _T_588 = eq(_T_587, UInt<1>(0h0))
when _T_588 :
node _T_589 = eq(_T_586, UInt<1>(0h0))
when _T_589 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_586, UInt<1>(0h1), "") : assert_10
node _T_590 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0)
node _T_591 = shr(io.in.a.bits.source, 2)
node _T_592 = eq(_T_591, UInt<7>(0h40))
node _T_593 = leq(UInt<1>(0h0), uncommonBits_48)
node _T_594 = and(_T_592, _T_593)
node _T_595 = leq(uncommonBits_48, UInt<2>(0h3))
node _T_596 = and(_T_594, _T_595)
node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0)
node _T_597 = shr(io.in.a.bits.source, 2)
node _T_598 = eq(_T_597, UInt<7>(0h41))
node _T_599 = leq(UInt<1>(0h0), uncommonBits_49)
node _T_600 = and(_T_598, _T_599)
node _T_601 = leq(uncommonBits_49, UInt<2>(0h3))
node _T_602 = and(_T_600, _T_601)
node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0)
node _T_603 = shr(io.in.a.bits.source, 2)
node _T_604 = eq(_T_603, UInt<7>(0h42))
node _T_605 = leq(UInt<1>(0h0), uncommonBits_50)
node _T_606 = and(_T_604, _T_605)
node _T_607 = leq(uncommonBits_50, UInt<2>(0h3))
node _T_608 = and(_T_606, _T_607)
node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0)
node _T_609 = shr(io.in.a.bits.source, 2)
node _T_610 = eq(_T_609, UInt<7>(0h43))
node _T_611 = leq(UInt<1>(0h0), uncommonBits_51)
node _T_612 = and(_T_610, _T_611)
node _T_613 = leq(uncommonBits_51, UInt<2>(0h3))
node _T_614 = and(_T_612, _T_613)
node _T_615 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_616 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_617 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_52 = bits(_uncommonBits_T_52, 4, 0)
node _T_618 = shr(io.in.a.bits.source, 5)
node _T_619 = eq(_T_618, UInt<1>(0h0))
node _T_620 = leq(UInt<1>(0h0), uncommonBits_52)
node _T_621 = and(_T_619, _T_620)
node _T_622 = leq(uncommonBits_52, UInt<5>(0h1f))
node _T_623 = and(_T_621, _T_622)
node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_53 = bits(_uncommonBits_T_53, 4, 0)
node _T_624 = shr(io.in.a.bits.source, 5)
node _T_625 = eq(_T_624, UInt<1>(0h1))
node _T_626 = leq(UInt<1>(0h0), uncommonBits_53)
node _T_627 = and(_T_625, _T_626)
node _T_628 = leq(uncommonBits_53, UInt<5>(0h1f))
node _T_629 = and(_T_627, _T_628)
node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_54 = bits(_uncommonBits_T_54, 4, 0)
node _T_630 = shr(io.in.a.bits.source, 5)
node _T_631 = eq(_T_630, UInt<2>(0h2))
node _T_632 = leq(UInt<1>(0h0), uncommonBits_54)
node _T_633 = and(_T_631, _T_632)
node _T_634 = leq(uncommonBits_54, UInt<5>(0h1f))
node _T_635 = and(_T_633, _T_634)
node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_55 = bits(_uncommonBits_T_55, 4, 0)
node _T_636 = shr(io.in.a.bits.source, 5)
node _T_637 = eq(_T_636, UInt<2>(0h3))
node _T_638 = leq(UInt<1>(0h0), uncommonBits_55)
node _T_639 = and(_T_637, _T_638)
node _T_640 = leq(uncommonBits_55, UInt<5>(0h1f))
node _T_641 = and(_T_639, _T_640)
node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_56 = bits(_uncommonBits_T_56, 4, 0)
node _T_642 = shr(io.in.a.bits.source, 5)
node _T_643 = eq(_T_642, UInt<3>(0h4))
node _T_644 = leq(UInt<1>(0h0), uncommonBits_56)
node _T_645 = and(_T_643, _T_644)
node _T_646 = leq(uncommonBits_56, UInt<5>(0h1f))
node _T_647 = and(_T_645, _T_646)
node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_57 = bits(_uncommonBits_T_57, 4, 0)
node _T_648 = shr(io.in.a.bits.source, 5)
node _T_649 = eq(_T_648, UInt<3>(0h5))
node _T_650 = leq(UInt<1>(0h0), uncommonBits_57)
node _T_651 = and(_T_649, _T_650)
node _T_652 = leq(uncommonBits_57, UInt<5>(0h1f))
node _T_653 = and(_T_651, _T_652)
node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_58 = bits(_uncommonBits_T_58, 4, 0)
node _T_654 = shr(io.in.a.bits.source, 5)
node _T_655 = eq(_T_654, UInt<3>(0h6))
node _T_656 = leq(UInt<1>(0h0), uncommonBits_58)
node _T_657 = and(_T_655, _T_656)
node _T_658 = leq(uncommonBits_58, UInt<5>(0h1f))
node _T_659 = and(_T_657, _T_658)
node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_59 = bits(_uncommonBits_T_59, 4, 0)
node _T_660 = shr(io.in.a.bits.source, 5)
node _T_661 = eq(_T_660, UInt<3>(0h7))
node _T_662 = leq(UInt<1>(0h0), uncommonBits_59)
node _T_663 = and(_T_661, _T_662)
node _T_664 = leq(uncommonBits_59, UInt<5>(0h1f))
node _T_665 = and(_T_663, _T_664)
node _T_666 = eq(io.in.a.bits.source, UInt<10>(0h200))
wire _WIRE_2 : UInt<1>[17]
connect _WIRE_2[0], _T_590
connect _WIRE_2[1], _T_596
connect _WIRE_2[2], _T_602
connect _WIRE_2[3], _T_608
connect _WIRE_2[4], _T_614
connect _WIRE_2[5], _T_615
connect _WIRE_2[6], _T_616
connect _WIRE_2[7], _T_617
connect _WIRE_2[8], _T_623
connect _WIRE_2[9], _T_629
connect _WIRE_2[10], _T_635
connect _WIRE_2[11], _T_641
connect _WIRE_2[12], _T_647
connect _WIRE_2[13], _T_653
connect _WIRE_2[14], _T_659
connect _WIRE_2[15], _T_665
connect _WIRE_2[16], _T_666
node _T_667 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_668 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0))
node _T_669 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0))
node _T_670 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0))
node _T_671 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0))
node _T_672 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0))
node _T_673 = mux(_WIRE_2[5], _T_667, UInt<1>(0h0))
node _T_674 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0))
node _T_675 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0))
node _T_676 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0))
node _T_677 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0))
node _T_678 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0))
node _T_679 = mux(_WIRE_2[11], UInt<1>(0h0), UInt<1>(0h0))
node _T_680 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0))
node _T_681 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0))
node _T_682 = mux(_WIRE_2[14], UInt<1>(0h0), UInt<1>(0h0))
node _T_683 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0))
node _T_684 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0))
node _T_685 = or(_T_668, _T_669)
node _T_686 = or(_T_685, _T_670)
node _T_687 = or(_T_686, _T_671)
node _T_688 = or(_T_687, _T_672)
node _T_689 = or(_T_688, _T_673)
node _T_690 = or(_T_689, _T_674)
node _T_691 = or(_T_690, _T_675)
node _T_692 = or(_T_691, _T_676)
node _T_693 = or(_T_692, _T_677)
node _T_694 = or(_T_693, _T_678)
node _T_695 = or(_T_694, _T_679)
node _T_696 = or(_T_695, _T_680)
node _T_697 = or(_T_696, _T_681)
node _T_698 = or(_T_697, _T_682)
node _T_699 = or(_T_698, _T_683)
node _T_700 = or(_T_699, _T_684)
wire _WIRE_3 : UInt<1>
connect _WIRE_3, _T_700
node _T_701 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_702 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_703 = and(_T_701, _T_702)
node _T_704 = or(UInt<1>(0h0), _T_703)
node _T_705 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_706 = cvt(_T_705)
node _T_707 = and(_T_706, asSInt(UInt<13>(0h1000)))
node _T_708 = asSInt(_T_707)
node _T_709 = eq(_T_708, asSInt(UInt<1>(0h0)))
node _T_710 = and(_T_704, _T_709)
node _T_711 = or(UInt<1>(0h0), _T_710)
node _T_712 = and(_WIRE_3, _T_711)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_712, UInt<1>(0h1), "") : assert_11
node _T_716 = asUInt(reset)
node _T_717 = eq(_T_716, UInt<1>(0h0))
when _T_717 :
node _T_718 = eq(source_ok, UInt<1>(0h0))
when _T_718 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, source_ok, UInt<1>(0h1), "") : assert_12
node _T_719 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_720 = asUInt(reset)
node _T_721 = eq(_T_720, UInt<1>(0h0))
when _T_721 :
node _T_722 = eq(_T_719, UInt<1>(0h0))
when _T_722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_719, UInt<1>(0h1), "") : assert_13
node _T_723 = asUInt(reset)
node _T_724 = eq(_T_723, UInt<1>(0h0))
when _T_724 :
node _T_725 = eq(is_aligned, UInt<1>(0h0))
when _T_725 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_726 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_727 = asUInt(reset)
node _T_728 = eq(_T_727, UInt<1>(0h0))
when _T_728 :
node _T_729 = eq(_T_726, UInt<1>(0h0))
when _T_729 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_726, UInt<1>(0h1), "") : assert_15
node _T_730 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_731 = asUInt(reset)
node _T_732 = eq(_T_731, UInt<1>(0h0))
when _T_732 :
node _T_733 = eq(_T_730, UInt<1>(0h0))
when _T_733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_730, UInt<1>(0h1), "") : assert_16
node _T_734 = not(io.in.a.bits.mask)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = asUInt(reset)
node _T_737 = eq(_T_736, UInt<1>(0h0))
when _T_737 :
node _T_738 = eq(_T_735, UInt<1>(0h0))
when _T_738 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_735, UInt<1>(0h1), "") : assert_17
node _T_739 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_740 = asUInt(reset)
node _T_741 = eq(_T_740, UInt<1>(0h0))
when _T_741 :
node _T_742 = eq(_T_739, UInt<1>(0h0))
when _T_742 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_739, UInt<1>(0h1), "") : assert_18
node _T_743 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_743 :
node _T_744 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_745 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_746 = and(_T_744, _T_745)
node _T_747 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0)
node _T_748 = shr(io.in.a.bits.source, 2)
node _T_749 = eq(_T_748, UInt<7>(0h40))
node _T_750 = leq(UInt<1>(0h0), uncommonBits_60)
node _T_751 = and(_T_749, _T_750)
node _T_752 = leq(uncommonBits_60, UInt<2>(0h3))
node _T_753 = and(_T_751, _T_752)
node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0)
node _T_754 = shr(io.in.a.bits.source, 2)
node _T_755 = eq(_T_754, UInt<7>(0h41))
node _T_756 = leq(UInt<1>(0h0), uncommonBits_61)
node _T_757 = and(_T_755, _T_756)
node _T_758 = leq(uncommonBits_61, UInt<2>(0h3))
node _T_759 = and(_T_757, _T_758)
node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0)
node _T_760 = shr(io.in.a.bits.source, 2)
node _T_761 = eq(_T_760, UInt<7>(0h42))
node _T_762 = leq(UInt<1>(0h0), uncommonBits_62)
node _T_763 = and(_T_761, _T_762)
node _T_764 = leq(uncommonBits_62, UInt<2>(0h3))
node _T_765 = and(_T_763, _T_764)
node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0)
node _T_766 = shr(io.in.a.bits.source, 2)
node _T_767 = eq(_T_766, UInt<7>(0h43))
node _T_768 = leq(UInt<1>(0h0), uncommonBits_63)
node _T_769 = and(_T_767, _T_768)
node _T_770 = leq(uncommonBits_63, UInt<2>(0h3))
node _T_771 = and(_T_769, _T_770)
node _T_772 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_773 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_774 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_64 = bits(_uncommonBits_T_64, 4, 0)
node _T_775 = shr(io.in.a.bits.source, 5)
node _T_776 = eq(_T_775, UInt<1>(0h0))
node _T_777 = leq(UInt<1>(0h0), uncommonBits_64)
node _T_778 = and(_T_776, _T_777)
node _T_779 = leq(uncommonBits_64, UInt<5>(0h1f))
node _T_780 = and(_T_778, _T_779)
node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_65 = bits(_uncommonBits_T_65, 4, 0)
node _T_781 = shr(io.in.a.bits.source, 5)
node _T_782 = eq(_T_781, UInt<1>(0h1))
node _T_783 = leq(UInt<1>(0h0), uncommonBits_65)
node _T_784 = and(_T_782, _T_783)
node _T_785 = leq(uncommonBits_65, UInt<5>(0h1f))
node _T_786 = and(_T_784, _T_785)
node _uncommonBits_T_66 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_66 = bits(_uncommonBits_T_66, 4, 0)
node _T_787 = shr(io.in.a.bits.source, 5)
node _T_788 = eq(_T_787, UInt<2>(0h2))
node _T_789 = leq(UInt<1>(0h0), uncommonBits_66)
node _T_790 = and(_T_788, _T_789)
node _T_791 = leq(uncommonBits_66, UInt<5>(0h1f))
node _T_792 = and(_T_790, _T_791)
node _uncommonBits_T_67 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_67 = bits(_uncommonBits_T_67, 4, 0)
node _T_793 = shr(io.in.a.bits.source, 5)
node _T_794 = eq(_T_793, UInt<2>(0h3))
node _T_795 = leq(UInt<1>(0h0), uncommonBits_67)
node _T_796 = and(_T_794, _T_795)
node _T_797 = leq(uncommonBits_67, UInt<5>(0h1f))
node _T_798 = and(_T_796, _T_797)
node _uncommonBits_T_68 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_68 = bits(_uncommonBits_T_68, 4, 0)
node _T_799 = shr(io.in.a.bits.source, 5)
node _T_800 = eq(_T_799, UInt<3>(0h4))
node _T_801 = leq(UInt<1>(0h0), uncommonBits_68)
node _T_802 = and(_T_800, _T_801)
node _T_803 = leq(uncommonBits_68, UInt<5>(0h1f))
node _T_804 = and(_T_802, _T_803)
node _uncommonBits_T_69 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_69 = bits(_uncommonBits_T_69, 4, 0)
node _T_805 = shr(io.in.a.bits.source, 5)
node _T_806 = eq(_T_805, UInt<3>(0h5))
node _T_807 = leq(UInt<1>(0h0), uncommonBits_69)
node _T_808 = and(_T_806, _T_807)
node _T_809 = leq(uncommonBits_69, UInt<5>(0h1f))
node _T_810 = and(_T_808, _T_809)
node _uncommonBits_T_70 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_70 = bits(_uncommonBits_T_70, 4, 0)
node _T_811 = shr(io.in.a.bits.source, 5)
node _T_812 = eq(_T_811, UInt<3>(0h6))
node _T_813 = leq(UInt<1>(0h0), uncommonBits_70)
node _T_814 = and(_T_812, _T_813)
node _T_815 = leq(uncommonBits_70, UInt<5>(0h1f))
node _T_816 = and(_T_814, _T_815)
node _uncommonBits_T_71 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_71 = bits(_uncommonBits_T_71, 4, 0)
node _T_817 = shr(io.in.a.bits.source, 5)
node _T_818 = eq(_T_817, UInt<3>(0h7))
node _T_819 = leq(UInt<1>(0h0), uncommonBits_71)
node _T_820 = and(_T_818, _T_819)
node _T_821 = leq(uncommonBits_71, UInt<5>(0h1f))
node _T_822 = and(_T_820, _T_821)
node _T_823 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_824 = or(_T_747, _T_753)
node _T_825 = or(_T_824, _T_759)
node _T_826 = or(_T_825, _T_765)
node _T_827 = or(_T_826, _T_771)
node _T_828 = or(_T_827, _T_772)
node _T_829 = or(_T_828, _T_773)
node _T_830 = or(_T_829, _T_774)
node _T_831 = or(_T_830, _T_780)
node _T_832 = or(_T_831, _T_786)
node _T_833 = or(_T_832, _T_792)
node _T_834 = or(_T_833, _T_798)
node _T_835 = or(_T_834, _T_804)
node _T_836 = or(_T_835, _T_810)
node _T_837 = or(_T_836, _T_816)
node _T_838 = or(_T_837, _T_822)
node _T_839 = or(_T_838, _T_823)
node _T_840 = and(_T_746, _T_839)
node _T_841 = or(UInt<1>(0h0), _T_840)
node _T_842 = asUInt(reset)
node _T_843 = eq(_T_842, UInt<1>(0h0))
when _T_843 :
node _T_844 = eq(_T_841, UInt<1>(0h0))
when _T_844 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_841, UInt<1>(0h1), "") : assert_19
node _T_845 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_846 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_847 = and(_T_845, _T_846)
node _T_848 = or(UInt<1>(0h0), _T_847)
node _T_849 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_850 = cvt(_T_849)
node _T_851 = and(_T_850, asSInt(UInt<13>(0h1000)))
node _T_852 = asSInt(_T_851)
node _T_853 = eq(_T_852, asSInt(UInt<1>(0h0)))
node _T_854 = and(_T_848, _T_853)
node _T_855 = or(UInt<1>(0h0), _T_854)
node _T_856 = asUInt(reset)
node _T_857 = eq(_T_856, UInt<1>(0h0))
when _T_857 :
node _T_858 = eq(_T_855, UInt<1>(0h0))
when _T_858 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_855, UInt<1>(0h1), "") : assert_20
node _T_859 = asUInt(reset)
node _T_860 = eq(_T_859, UInt<1>(0h0))
when _T_860 :
node _T_861 = eq(source_ok, UInt<1>(0h0))
when _T_861 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, source_ok, UInt<1>(0h1), "") : assert_21
node _T_862 = asUInt(reset)
node _T_863 = eq(_T_862, UInt<1>(0h0))
when _T_863 :
node _T_864 = eq(is_aligned, UInt<1>(0h0))
when _T_864 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_865 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_866 = asUInt(reset)
node _T_867 = eq(_T_866, UInt<1>(0h0))
when _T_867 :
node _T_868 = eq(_T_865, UInt<1>(0h0))
when _T_868 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_865, UInt<1>(0h1), "") : assert_23
node _T_869 = eq(io.in.a.bits.mask, mask)
node _T_870 = asUInt(reset)
node _T_871 = eq(_T_870, UInt<1>(0h0))
when _T_871 :
node _T_872 = eq(_T_869, UInt<1>(0h0))
when _T_872 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_869, UInt<1>(0h1), "") : assert_24
node _T_873 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_874 = asUInt(reset)
node _T_875 = eq(_T_874, UInt<1>(0h0))
when _T_875 :
node _T_876 = eq(_T_873, UInt<1>(0h0))
when _T_876 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_873, UInt<1>(0h1), "") : assert_25
node _T_877 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_877 :
node _T_878 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_879 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_880 = and(_T_878, _T_879)
node _T_881 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_72 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_72 = bits(_uncommonBits_T_72, 1, 0)
node _T_882 = shr(io.in.a.bits.source, 2)
node _T_883 = eq(_T_882, UInt<7>(0h40))
node _T_884 = leq(UInt<1>(0h0), uncommonBits_72)
node _T_885 = and(_T_883, _T_884)
node _T_886 = leq(uncommonBits_72, UInt<2>(0h3))
node _T_887 = and(_T_885, _T_886)
node _uncommonBits_T_73 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_73 = bits(_uncommonBits_T_73, 1, 0)
node _T_888 = shr(io.in.a.bits.source, 2)
node _T_889 = eq(_T_888, UInt<7>(0h41))
node _T_890 = leq(UInt<1>(0h0), uncommonBits_73)
node _T_891 = and(_T_889, _T_890)
node _T_892 = leq(uncommonBits_73, UInt<2>(0h3))
node _T_893 = and(_T_891, _T_892)
node _uncommonBits_T_74 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_74 = bits(_uncommonBits_T_74, 1, 0)
node _T_894 = shr(io.in.a.bits.source, 2)
node _T_895 = eq(_T_894, UInt<7>(0h42))
node _T_896 = leq(UInt<1>(0h0), uncommonBits_74)
node _T_897 = and(_T_895, _T_896)
node _T_898 = leq(uncommonBits_74, UInt<2>(0h3))
node _T_899 = and(_T_897, _T_898)
node _uncommonBits_T_75 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_75 = bits(_uncommonBits_T_75, 1, 0)
node _T_900 = shr(io.in.a.bits.source, 2)
node _T_901 = eq(_T_900, UInt<7>(0h43))
node _T_902 = leq(UInt<1>(0h0), uncommonBits_75)
node _T_903 = and(_T_901, _T_902)
node _T_904 = leq(uncommonBits_75, UInt<2>(0h3))
node _T_905 = and(_T_903, _T_904)
node _T_906 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_907 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_908 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_76 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_76 = bits(_uncommonBits_T_76, 4, 0)
node _T_909 = shr(io.in.a.bits.source, 5)
node _T_910 = eq(_T_909, UInt<1>(0h0))
node _T_911 = leq(UInt<1>(0h0), uncommonBits_76)
node _T_912 = and(_T_910, _T_911)
node _T_913 = leq(uncommonBits_76, UInt<5>(0h1f))
node _T_914 = and(_T_912, _T_913)
node _uncommonBits_T_77 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_77 = bits(_uncommonBits_T_77, 4, 0)
node _T_915 = shr(io.in.a.bits.source, 5)
node _T_916 = eq(_T_915, UInt<1>(0h1))
node _T_917 = leq(UInt<1>(0h0), uncommonBits_77)
node _T_918 = and(_T_916, _T_917)
node _T_919 = leq(uncommonBits_77, UInt<5>(0h1f))
node _T_920 = and(_T_918, _T_919)
node _uncommonBits_T_78 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_78 = bits(_uncommonBits_T_78, 4, 0)
node _T_921 = shr(io.in.a.bits.source, 5)
node _T_922 = eq(_T_921, UInt<2>(0h2))
node _T_923 = leq(UInt<1>(0h0), uncommonBits_78)
node _T_924 = and(_T_922, _T_923)
node _T_925 = leq(uncommonBits_78, UInt<5>(0h1f))
node _T_926 = and(_T_924, _T_925)
node _uncommonBits_T_79 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_79 = bits(_uncommonBits_T_79, 4, 0)
node _T_927 = shr(io.in.a.bits.source, 5)
node _T_928 = eq(_T_927, UInt<2>(0h3))
node _T_929 = leq(UInt<1>(0h0), uncommonBits_79)
node _T_930 = and(_T_928, _T_929)
node _T_931 = leq(uncommonBits_79, UInt<5>(0h1f))
node _T_932 = and(_T_930, _T_931)
node _uncommonBits_T_80 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_80 = bits(_uncommonBits_T_80, 4, 0)
node _T_933 = shr(io.in.a.bits.source, 5)
node _T_934 = eq(_T_933, UInt<3>(0h4))
node _T_935 = leq(UInt<1>(0h0), uncommonBits_80)
node _T_936 = and(_T_934, _T_935)
node _T_937 = leq(uncommonBits_80, UInt<5>(0h1f))
node _T_938 = and(_T_936, _T_937)
node _uncommonBits_T_81 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_81 = bits(_uncommonBits_T_81, 4, 0)
node _T_939 = shr(io.in.a.bits.source, 5)
node _T_940 = eq(_T_939, UInt<3>(0h5))
node _T_941 = leq(UInt<1>(0h0), uncommonBits_81)
node _T_942 = and(_T_940, _T_941)
node _T_943 = leq(uncommonBits_81, UInt<5>(0h1f))
node _T_944 = and(_T_942, _T_943)
node _uncommonBits_T_82 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_82 = bits(_uncommonBits_T_82, 4, 0)
node _T_945 = shr(io.in.a.bits.source, 5)
node _T_946 = eq(_T_945, UInt<3>(0h6))
node _T_947 = leq(UInt<1>(0h0), uncommonBits_82)
node _T_948 = and(_T_946, _T_947)
node _T_949 = leq(uncommonBits_82, UInt<5>(0h1f))
node _T_950 = and(_T_948, _T_949)
node _uncommonBits_T_83 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_83 = bits(_uncommonBits_T_83, 4, 0)
node _T_951 = shr(io.in.a.bits.source, 5)
node _T_952 = eq(_T_951, UInt<3>(0h7))
node _T_953 = leq(UInt<1>(0h0), uncommonBits_83)
node _T_954 = and(_T_952, _T_953)
node _T_955 = leq(uncommonBits_83, UInt<5>(0h1f))
node _T_956 = and(_T_954, _T_955)
node _T_957 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_958 = or(_T_881, _T_887)
node _T_959 = or(_T_958, _T_893)
node _T_960 = or(_T_959, _T_899)
node _T_961 = or(_T_960, _T_905)
node _T_962 = or(_T_961, _T_906)
node _T_963 = or(_T_962, _T_907)
node _T_964 = or(_T_963, _T_908)
node _T_965 = or(_T_964, _T_914)
node _T_966 = or(_T_965, _T_920)
node _T_967 = or(_T_966, _T_926)
node _T_968 = or(_T_967, _T_932)
node _T_969 = or(_T_968, _T_938)
node _T_970 = or(_T_969, _T_944)
node _T_971 = or(_T_970, _T_950)
node _T_972 = or(_T_971, _T_956)
node _T_973 = or(_T_972, _T_957)
node _T_974 = and(_T_880, _T_973)
node _T_975 = or(UInt<1>(0h0), _T_974)
node _T_976 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_977 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_978 = and(_T_976, _T_977)
node _T_979 = or(UInt<1>(0h0), _T_978)
node _T_980 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_981 = cvt(_T_980)
node _T_982 = and(_T_981, asSInt(UInt<13>(0h1000)))
node _T_983 = asSInt(_T_982)
node _T_984 = eq(_T_983, asSInt(UInt<1>(0h0)))
node _T_985 = and(_T_979, _T_984)
node _T_986 = or(UInt<1>(0h0), _T_985)
node _T_987 = and(_T_975, _T_986)
node _T_988 = asUInt(reset)
node _T_989 = eq(_T_988, UInt<1>(0h0))
when _T_989 :
node _T_990 = eq(_T_987, UInt<1>(0h0))
when _T_990 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_987, UInt<1>(0h1), "") : assert_26
node _T_991 = asUInt(reset)
node _T_992 = eq(_T_991, UInt<1>(0h0))
when _T_992 :
node _T_993 = eq(source_ok, UInt<1>(0h0))
when _T_993 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, source_ok, UInt<1>(0h1), "") : assert_27
node _T_994 = asUInt(reset)
node _T_995 = eq(_T_994, UInt<1>(0h0))
when _T_995 :
node _T_996 = eq(is_aligned, UInt<1>(0h0))
when _T_996 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_997 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_998 = asUInt(reset)
node _T_999 = eq(_T_998, UInt<1>(0h0))
when _T_999 :
node _T_1000 = eq(_T_997, UInt<1>(0h0))
when _T_1000 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_997, UInt<1>(0h1), "") : assert_29
node _T_1001 = eq(io.in.a.bits.mask, mask)
node _T_1002 = asUInt(reset)
node _T_1003 = eq(_T_1002, UInt<1>(0h0))
when _T_1003 :
node _T_1004 = eq(_T_1001, UInt<1>(0h0))
when _T_1004 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_1001, UInt<1>(0h1), "") : assert_30
node _T_1005 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_1005 :
node _T_1006 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1007 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1008 = and(_T_1006, _T_1007)
node _T_1009 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_84 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_84 = bits(_uncommonBits_T_84, 1, 0)
node _T_1010 = shr(io.in.a.bits.source, 2)
node _T_1011 = eq(_T_1010, UInt<7>(0h40))
node _T_1012 = leq(UInt<1>(0h0), uncommonBits_84)
node _T_1013 = and(_T_1011, _T_1012)
node _T_1014 = leq(uncommonBits_84, UInt<2>(0h3))
node _T_1015 = and(_T_1013, _T_1014)
node _uncommonBits_T_85 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_85 = bits(_uncommonBits_T_85, 1, 0)
node _T_1016 = shr(io.in.a.bits.source, 2)
node _T_1017 = eq(_T_1016, UInt<7>(0h41))
node _T_1018 = leq(UInt<1>(0h0), uncommonBits_85)
node _T_1019 = and(_T_1017, _T_1018)
node _T_1020 = leq(uncommonBits_85, UInt<2>(0h3))
node _T_1021 = and(_T_1019, _T_1020)
node _uncommonBits_T_86 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_86 = bits(_uncommonBits_T_86, 1, 0)
node _T_1022 = shr(io.in.a.bits.source, 2)
node _T_1023 = eq(_T_1022, UInt<7>(0h42))
node _T_1024 = leq(UInt<1>(0h0), uncommonBits_86)
node _T_1025 = and(_T_1023, _T_1024)
node _T_1026 = leq(uncommonBits_86, UInt<2>(0h3))
node _T_1027 = and(_T_1025, _T_1026)
node _uncommonBits_T_87 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_87 = bits(_uncommonBits_T_87, 1, 0)
node _T_1028 = shr(io.in.a.bits.source, 2)
node _T_1029 = eq(_T_1028, UInt<7>(0h43))
node _T_1030 = leq(UInt<1>(0h0), uncommonBits_87)
node _T_1031 = and(_T_1029, _T_1030)
node _T_1032 = leq(uncommonBits_87, UInt<2>(0h3))
node _T_1033 = and(_T_1031, _T_1032)
node _T_1034 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_1035 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_1036 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_88 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_88 = bits(_uncommonBits_T_88, 4, 0)
node _T_1037 = shr(io.in.a.bits.source, 5)
node _T_1038 = eq(_T_1037, UInt<1>(0h0))
node _T_1039 = leq(UInt<1>(0h0), uncommonBits_88)
node _T_1040 = and(_T_1038, _T_1039)
node _T_1041 = leq(uncommonBits_88, UInt<5>(0h1f))
node _T_1042 = and(_T_1040, _T_1041)
node _uncommonBits_T_89 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_89 = bits(_uncommonBits_T_89, 4, 0)
node _T_1043 = shr(io.in.a.bits.source, 5)
node _T_1044 = eq(_T_1043, UInt<1>(0h1))
node _T_1045 = leq(UInt<1>(0h0), uncommonBits_89)
node _T_1046 = and(_T_1044, _T_1045)
node _T_1047 = leq(uncommonBits_89, UInt<5>(0h1f))
node _T_1048 = and(_T_1046, _T_1047)
node _uncommonBits_T_90 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_90 = bits(_uncommonBits_T_90, 4, 0)
node _T_1049 = shr(io.in.a.bits.source, 5)
node _T_1050 = eq(_T_1049, UInt<2>(0h2))
node _T_1051 = leq(UInt<1>(0h0), uncommonBits_90)
node _T_1052 = and(_T_1050, _T_1051)
node _T_1053 = leq(uncommonBits_90, UInt<5>(0h1f))
node _T_1054 = and(_T_1052, _T_1053)
node _uncommonBits_T_91 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_91 = bits(_uncommonBits_T_91, 4, 0)
node _T_1055 = shr(io.in.a.bits.source, 5)
node _T_1056 = eq(_T_1055, UInt<2>(0h3))
node _T_1057 = leq(UInt<1>(0h0), uncommonBits_91)
node _T_1058 = and(_T_1056, _T_1057)
node _T_1059 = leq(uncommonBits_91, UInt<5>(0h1f))
node _T_1060 = and(_T_1058, _T_1059)
node _uncommonBits_T_92 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_92 = bits(_uncommonBits_T_92, 4, 0)
node _T_1061 = shr(io.in.a.bits.source, 5)
node _T_1062 = eq(_T_1061, UInt<3>(0h4))
node _T_1063 = leq(UInt<1>(0h0), uncommonBits_92)
node _T_1064 = and(_T_1062, _T_1063)
node _T_1065 = leq(uncommonBits_92, UInt<5>(0h1f))
node _T_1066 = and(_T_1064, _T_1065)
node _uncommonBits_T_93 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_93 = bits(_uncommonBits_T_93, 4, 0)
node _T_1067 = shr(io.in.a.bits.source, 5)
node _T_1068 = eq(_T_1067, UInt<3>(0h5))
node _T_1069 = leq(UInt<1>(0h0), uncommonBits_93)
node _T_1070 = and(_T_1068, _T_1069)
node _T_1071 = leq(uncommonBits_93, UInt<5>(0h1f))
node _T_1072 = and(_T_1070, _T_1071)
node _uncommonBits_T_94 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_94 = bits(_uncommonBits_T_94, 4, 0)
node _T_1073 = shr(io.in.a.bits.source, 5)
node _T_1074 = eq(_T_1073, UInt<3>(0h6))
node _T_1075 = leq(UInt<1>(0h0), uncommonBits_94)
node _T_1076 = and(_T_1074, _T_1075)
node _T_1077 = leq(uncommonBits_94, UInt<5>(0h1f))
node _T_1078 = and(_T_1076, _T_1077)
node _uncommonBits_T_95 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_95 = bits(_uncommonBits_T_95, 4, 0)
node _T_1079 = shr(io.in.a.bits.source, 5)
node _T_1080 = eq(_T_1079, UInt<3>(0h7))
node _T_1081 = leq(UInt<1>(0h0), uncommonBits_95)
node _T_1082 = and(_T_1080, _T_1081)
node _T_1083 = leq(uncommonBits_95, UInt<5>(0h1f))
node _T_1084 = and(_T_1082, _T_1083)
node _T_1085 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_1086 = or(_T_1009, _T_1015)
node _T_1087 = or(_T_1086, _T_1021)
node _T_1088 = or(_T_1087, _T_1027)
node _T_1089 = or(_T_1088, _T_1033)
node _T_1090 = or(_T_1089, _T_1034)
node _T_1091 = or(_T_1090, _T_1035)
node _T_1092 = or(_T_1091, _T_1036)
node _T_1093 = or(_T_1092, _T_1042)
node _T_1094 = or(_T_1093, _T_1048)
node _T_1095 = or(_T_1094, _T_1054)
node _T_1096 = or(_T_1095, _T_1060)
node _T_1097 = or(_T_1096, _T_1066)
node _T_1098 = or(_T_1097, _T_1072)
node _T_1099 = or(_T_1098, _T_1078)
node _T_1100 = or(_T_1099, _T_1084)
node _T_1101 = or(_T_1100, _T_1085)
node _T_1102 = and(_T_1008, _T_1101)
node _T_1103 = or(UInt<1>(0h0), _T_1102)
node _T_1104 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1105 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1106 = and(_T_1104, _T_1105)
node _T_1107 = or(UInt<1>(0h0), _T_1106)
node _T_1108 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_1109 = cvt(_T_1108)
node _T_1110 = and(_T_1109, asSInt(UInt<13>(0h1000)))
node _T_1111 = asSInt(_T_1110)
node _T_1112 = eq(_T_1111, asSInt(UInt<1>(0h0)))
node _T_1113 = and(_T_1107, _T_1112)
node _T_1114 = or(UInt<1>(0h0), _T_1113)
node _T_1115 = and(_T_1103, _T_1114)
node _T_1116 = asUInt(reset)
node _T_1117 = eq(_T_1116, UInt<1>(0h0))
when _T_1117 :
node _T_1118 = eq(_T_1115, UInt<1>(0h0))
when _T_1118 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_1115, UInt<1>(0h1), "") : assert_31
node _T_1119 = asUInt(reset)
node _T_1120 = eq(_T_1119, UInt<1>(0h0))
when _T_1120 :
node _T_1121 = eq(source_ok, UInt<1>(0h0))
when _T_1121 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, source_ok, UInt<1>(0h1), "") : assert_32
node _T_1122 = asUInt(reset)
node _T_1123 = eq(_T_1122, UInt<1>(0h0))
when _T_1123 :
node _T_1124 = eq(is_aligned, UInt<1>(0h0))
when _T_1124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_1125 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_1126 = asUInt(reset)
node _T_1127 = eq(_T_1126, UInt<1>(0h0))
when _T_1127 :
node _T_1128 = eq(_T_1125, UInt<1>(0h0))
when _T_1128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_1125, UInt<1>(0h1), "") : assert_34
node _T_1129 = not(mask)
node _T_1130 = and(io.in.a.bits.mask, _T_1129)
node _T_1131 = eq(_T_1130, UInt<1>(0h0))
node _T_1132 = asUInt(reset)
node _T_1133 = eq(_T_1132, UInt<1>(0h0))
when _T_1133 :
node _T_1134 = eq(_T_1131, UInt<1>(0h0))
when _T_1134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_1131, UInt<1>(0h1), "") : assert_35
node _T_1135 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_1135 :
node _T_1136 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1137 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1138 = and(_T_1136, _T_1137)
node _T_1139 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_96 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_96 = bits(_uncommonBits_T_96, 1, 0)
node _T_1140 = shr(io.in.a.bits.source, 2)
node _T_1141 = eq(_T_1140, UInt<7>(0h40))
node _T_1142 = leq(UInt<1>(0h0), uncommonBits_96)
node _T_1143 = and(_T_1141, _T_1142)
node _T_1144 = leq(uncommonBits_96, UInt<2>(0h3))
node _T_1145 = and(_T_1143, _T_1144)
node _uncommonBits_T_97 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_97 = bits(_uncommonBits_T_97, 1, 0)
node _T_1146 = shr(io.in.a.bits.source, 2)
node _T_1147 = eq(_T_1146, UInt<7>(0h41))
node _T_1148 = leq(UInt<1>(0h0), uncommonBits_97)
node _T_1149 = and(_T_1147, _T_1148)
node _T_1150 = leq(uncommonBits_97, UInt<2>(0h3))
node _T_1151 = and(_T_1149, _T_1150)
node _uncommonBits_T_98 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_98 = bits(_uncommonBits_T_98, 1, 0)
node _T_1152 = shr(io.in.a.bits.source, 2)
node _T_1153 = eq(_T_1152, UInt<7>(0h42))
node _T_1154 = leq(UInt<1>(0h0), uncommonBits_98)
node _T_1155 = and(_T_1153, _T_1154)
node _T_1156 = leq(uncommonBits_98, UInt<2>(0h3))
node _T_1157 = and(_T_1155, _T_1156)
node _uncommonBits_T_99 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_99 = bits(_uncommonBits_T_99, 1, 0)
node _T_1158 = shr(io.in.a.bits.source, 2)
node _T_1159 = eq(_T_1158, UInt<7>(0h43))
node _T_1160 = leq(UInt<1>(0h0), uncommonBits_99)
node _T_1161 = and(_T_1159, _T_1160)
node _T_1162 = leq(uncommonBits_99, UInt<2>(0h3))
node _T_1163 = and(_T_1161, _T_1162)
node _T_1164 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_1165 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_1166 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_100 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_100 = bits(_uncommonBits_T_100, 4, 0)
node _T_1167 = shr(io.in.a.bits.source, 5)
node _T_1168 = eq(_T_1167, UInt<1>(0h0))
node _T_1169 = leq(UInt<1>(0h0), uncommonBits_100)
node _T_1170 = and(_T_1168, _T_1169)
node _T_1171 = leq(uncommonBits_100, UInt<5>(0h1f))
node _T_1172 = and(_T_1170, _T_1171)
node _uncommonBits_T_101 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_101 = bits(_uncommonBits_T_101, 4, 0)
node _T_1173 = shr(io.in.a.bits.source, 5)
node _T_1174 = eq(_T_1173, UInt<1>(0h1))
node _T_1175 = leq(UInt<1>(0h0), uncommonBits_101)
node _T_1176 = and(_T_1174, _T_1175)
node _T_1177 = leq(uncommonBits_101, UInt<5>(0h1f))
node _T_1178 = and(_T_1176, _T_1177)
node _uncommonBits_T_102 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_102 = bits(_uncommonBits_T_102, 4, 0)
node _T_1179 = shr(io.in.a.bits.source, 5)
node _T_1180 = eq(_T_1179, UInt<2>(0h2))
node _T_1181 = leq(UInt<1>(0h0), uncommonBits_102)
node _T_1182 = and(_T_1180, _T_1181)
node _T_1183 = leq(uncommonBits_102, UInt<5>(0h1f))
node _T_1184 = and(_T_1182, _T_1183)
node _uncommonBits_T_103 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_103 = bits(_uncommonBits_T_103, 4, 0)
node _T_1185 = shr(io.in.a.bits.source, 5)
node _T_1186 = eq(_T_1185, UInt<2>(0h3))
node _T_1187 = leq(UInt<1>(0h0), uncommonBits_103)
node _T_1188 = and(_T_1186, _T_1187)
node _T_1189 = leq(uncommonBits_103, UInt<5>(0h1f))
node _T_1190 = and(_T_1188, _T_1189)
node _uncommonBits_T_104 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_104 = bits(_uncommonBits_T_104, 4, 0)
node _T_1191 = shr(io.in.a.bits.source, 5)
node _T_1192 = eq(_T_1191, UInt<3>(0h4))
node _T_1193 = leq(UInt<1>(0h0), uncommonBits_104)
node _T_1194 = and(_T_1192, _T_1193)
node _T_1195 = leq(uncommonBits_104, UInt<5>(0h1f))
node _T_1196 = and(_T_1194, _T_1195)
node _uncommonBits_T_105 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_105 = bits(_uncommonBits_T_105, 4, 0)
node _T_1197 = shr(io.in.a.bits.source, 5)
node _T_1198 = eq(_T_1197, UInt<3>(0h5))
node _T_1199 = leq(UInt<1>(0h0), uncommonBits_105)
node _T_1200 = and(_T_1198, _T_1199)
node _T_1201 = leq(uncommonBits_105, UInt<5>(0h1f))
node _T_1202 = and(_T_1200, _T_1201)
node _uncommonBits_T_106 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_106 = bits(_uncommonBits_T_106, 4, 0)
node _T_1203 = shr(io.in.a.bits.source, 5)
node _T_1204 = eq(_T_1203, UInt<3>(0h6))
node _T_1205 = leq(UInt<1>(0h0), uncommonBits_106)
node _T_1206 = and(_T_1204, _T_1205)
node _T_1207 = leq(uncommonBits_106, UInt<5>(0h1f))
node _T_1208 = and(_T_1206, _T_1207)
node _uncommonBits_T_107 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_107 = bits(_uncommonBits_T_107, 4, 0)
node _T_1209 = shr(io.in.a.bits.source, 5)
node _T_1210 = eq(_T_1209, UInt<3>(0h7))
node _T_1211 = leq(UInt<1>(0h0), uncommonBits_107)
node _T_1212 = and(_T_1210, _T_1211)
node _T_1213 = leq(uncommonBits_107, UInt<5>(0h1f))
node _T_1214 = and(_T_1212, _T_1213)
node _T_1215 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_1216 = or(_T_1139, _T_1145)
node _T_1217 = or(_T_1216, _T_1151)
node _T_1218 = or(_T_1217, _T_1157)
node _T_1219 = or(_T_1218, _T_1163)
node _T_1220 = or(_T_1219, _T_1164)
node _T_1221 = or(_T_1220, _T_1165)
node _T_1222 = or(_T_1221, _T_1166)
node _T_1223 = or(_T_1222, _T_1172)
node _T_1224 = or(_T_1223, _T_1178)
node _T_1225 = or(_T_1224, _T_1184)
node _T_1226 = or(_T_1225, _T_1190)
node _T_1227 = or(_T_1226, _T_1196)
node _T_1228 = or(_T_1227, _T_1202)
node _T_1229 = or(_T_1228, _T_1208)
node _T_1230 = or(_T_1229, _T_1214)
node _T_1231 = or(_T_1230, _T_1215)
node _T_1232 = and(_T_1138, _T_1231)
node _T_1233 = or(UInt<1>(0h0), _T_1232)
node _T_1234 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1235 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_1236 = cvt(_T_1235)
node _T_1237 = and(_T_1236, asSInt(UInt<13>(0h1000)))
node _T_1238 = asSInt(_T_1237)
node _T_1239 = eq(_T_1238, asSInt(UInt<1>(0h0)))
node _T_1240 = and(_T_1234, _T_1239)
node _T_1241 = or(UInt<1>(0h0), _T_1240)
node _T_1242 = and(_T_1233, _T_1241)
node _T_1243 = asUInt(reset)
node _T_1244 = eq(_T_1243, UInt<1>(0h0))
when _T_1244 :
node _T_1245 = eq(_T_1242, UInt<1>(0h0))
when _T_1245 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_1242, UInt<1>(0h1), "") : assert_36
node _T_1246 = asUInt(reset)
node _T_1247 = eq(_T_1246, UInt<1>(0h0))
when _T_1247 :
node _T_1248 = eq(source_ok, UInt<1>(0h0))
when _T_1248 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, source_ok, UInt<1>(0h1), "") : assert_37
node _T_1249 = asUInt(reset)
node _T_1250 = eq(_T_1249, UInt<1>(0h0))
when _T_1250 :
node _T_1251 = eq(is_aligned, UInt<1>(0h0))
when _T_1251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_1252 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_1253 = asUInt(reset)
node _T_1254 = eq(_T_1253, UInt<1>(0h0))
when _T_1254 :
node _T_1255 = eq(_T_1252, UInt<1>(0h0))
when _T_1255 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_1252, UInt<1>(0h1), "") : assert_39
node _T_1256 = eq(io.in.a.bits.mask, mask)
node _T_1257 = asUInt(reset)
node _T_1258 = eq(_T_1257, UInt<1>(0h0))
when _T_1258 :
node _T_1259 = eq(_T_1256, UInt<1>(0h0))
when _T_1259 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_1256, UInt<1>(0h1), "") : assert_40
node _T_1260 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_1260 :
node _T_1261 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1262 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1263 = and(_T_1261, _T_1262)
node _T_1264 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_108 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_108 = bits(_uncommonBits_T_108, 1, 0)
node _T_1265 = shr(io.in.a.bits.source, 2)
node _T_1266 = eq(_T_1265, UInt<7>(0h40))
node _T_1267 = leq(UInt<1>(0h0), uncommonBits_108)
node _T_1268 = and(_T_1266, _T_1267)
node _T_1269 = leq(uncommonBits_108, UInt<2>(0h3))
node _T_1270 = and(_T_1268, _T_1269)
node _uncommonBits_T_109 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_109 = bits(_uncommonBits_T_109, 1, 0)
node _T_1271 = shr(io.in.a.bits.source, 2)
node _T_1272 = eq(_T_1271, UInt<7>(0h41))
node _T_1273 = leq(UInt<1>(0h0), uncommonBits_109)
node _T_1274 = and(_T_1272, _T_1273)
node _T_1275 = leq(uncommonBits_109, UInt<2>(0h3))
node _T_1276 = and(_T_1274, _T_1275)
node _uncommonBits_T_110 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_110 = bits(_uncommonBits_T_110, 1, 0)
node _T_1277 = shr(io.in.a.bits.source, 2)
node _T_1278 = eq(_T_1277, UInt<7>(0h42))
node _T_1279 = leq(UInt<1>(0h0), uncommonBits_110)
node _T_1280 = and(_T_1278, _T_1279)
node _T_1281 = leq(uncommonBits_110, UInt<2>(0h3))
node _T_1282 = and(_T_1280, _T_1281)
node _uncommonBits_T_111 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_111 = bits(_uncommonBits_T_111, 1, 0)
node _T_1283 = shr(io.in.a.bits.source, 2)
node _T_1284 = eq(_T_1283, UInt<7>(0h43))
node _T_1285 = leq(UInt<1>(0h0), uncommonBits_111)
node _T_1286 = and(_T_1284, _T_1285)
node _T_1287 = leq(uncommonBits_111, UInt<2>(0h3))
node _T_1288 = and(_T_1286, _T_1287)
node _T_1289 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_1290 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_1291 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_112 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_112 = bits(_uncommonBits_T_112, 4, 0)
node _T_1292 = shr(io.in.a.bits.source, 5)
node _T_1293 = eq(_T_1292, UInt<1>(0h0))
node _T_1294 = leq(UInt<1>(0h0), uncommonBits_112)
node _T_1295 = and(_T_1293, _T_1294)
node _T_1296 = leq(uncommonBits_112, UInt<5>(0h1f))
node _T_1297 = and(_T_1295, _T_1296)
node _uncommonBits_T_113 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_113 = bits(_uncommonBits_T_113, 4, 0)
node _T_1298 = shr(io.in.a.bits.source, 5)
node _T_1299 = eq(_T_1298, UInt<1>(0h1))
node _T_1300 = leq(UInt<1>(0h0), uncommonBits_113)
node _T_1301 = and(_T_1299, _T_1300)
node _T_1302 = leq(uncommonBits_113, UInt<5>(0h1f))
node _T_1303 = and(_T_1301, _T_1302)
node _uncommonBits_T_114 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_114 = bits(_uncommonBits_T_114, 4, 0)
node _T_1304 = shr(io.in.a.bits.source, 5)
node _T_1305 = eq(_T_1304, UInt<2>(0h2))
node _T_1306 = leq(UInt<1>(0h0), uncommonBits_114)
node _T_1307 = and(_T_1305, _T_1306)
node _T_1308 = leq(uncommonBits_114, UInt<5>(0h1f))
node _T_1309 = and(_T_1307, _T_1308)
node _uncommonBits_T_115 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_115 = bits(_uncommonBits_T_115, 4, 0)
node _T_1310 = shr(io.in.a.bits.source, 5)
node _T_1311 = eq(_T_1310, UInt<2>(0h3))
node _T_1312 = leq(UInt<1>(0h0), uncommonBits_115)
node _T_1313 = and(_T_1311, _T_1312)
node _T_1314 = leq(uncommonBits_115, UInt<5>(0h1f))
node _T_1315 = and(_T_1313, _T_1314)
node _uncommonBits_T_116 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_116 = bits(_uncommonBits_T_116, 4, 0)
node _T_1316 = shr(io.in.a.bits.source, 5)
node _T_1317 = eq(_T_1316, UInt<3>(0h4))
node _T_1318 = leq(UInt<1>(0h0), uncommonBits_116)
node _T_1319 = and(_T_1317, _T_1318)
node _T_1320 = leq(uncommonBits_116, UInt<5>(0h1f))
node _T_1321 = and(_T_1319, _T_1320)
node _uncommonBits_T_117 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_117 = bits(_uncommonBits_T_117, 4, 0)
node _T_1322 = shr(io.in.a.bits.source, 5)
node _T_1323 = eq(_T_1322, UInt<3>(0h5))
node _T_1324 = leq(UInt<1>(0h0), uncommonBits_117)
node _T_1325 = and(_T_1323, _T_1324)
node _T_1326 = leq(uncommonBits_117, UInt<5>(0h1f))
node _T_1327 = and(_T_1325, _T_1326)
node _uncommonBits_T_118 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_118 = bits(_uncommonBits_T_118, 4, 0)
node _T_1328 = shr(io.in.a.bits.source, 5)
node _T_1329 = eq(_T_1328, UInt<3>(0h6))
node _T_1330 = leq(UInt<1>(0h0), uncommonBits_118)
node _T_1331 = and(_T_1329, _T_1330)
node _T_1332 = leq(uncommonBits_118, UInt<5>(0h1f))
node _T_1333 = and(_T_1331, _T_1332)
node _uncommonBits_T_119 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_119 = bits(_uncommonBits_T_119, 4, 0)
node _T_1334 = shr(io.in.a.bits.source, 5)
node _T_1335 = eq(_T_1334, UInt<3>(0h7))
node _T_1336 = leq(UInt<1>(0h0), uncommonBits_119)
node _T_1337 = and(_T_1335, _T_1336)
node _T_1338 = leq(uncommonBits_119, UInt<5>(0h1f))
node _T_1339 = and(_T_1337, _T_1338)
node _T_1340 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_1341 = or(_T_1264, _T_1270)
node _T_1342 = or(_T_1341, _T_1276)
node _T_1343 = or(_T_1342, _T_1282)
node _T_1344 = or(_T_1343, _T_1288)
node _T_1345 = or(_T_1344, _T_1289)
node _T_1346 = or(_T_1345, _T_1290)
node _T_1347 = or(_T_1346, _T_1291)
node _T_1348 = or(_T_1347, _T_1297)
node _T_1349 = or(_T_1348, _T_1303)
node _T_1350 = or(_T_1349, _T_1309)
node _T_1351 = or(_T_1350, _T_1315)
node _T_1352 = or(_T_1351, _T_1321)
node _T_1353 = or(_T_1352, _T_1327)
node _T_1354 = or(_T_1353, _T_1333)
node _T_1355 = or(_T_1354, _T_1339)
node _T_1356 = or(_T_1355, _T_1340)
node _T_1357 = and(_T_1263, _T_1356)
node _T_1358 = or(UInt<1>(0h0), _T_1357)
node _T_1359 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1360 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_1361 = cvt(_T_1360)
node _T_1362 = and(_T_1361, asSInt(UInt<13>(0h1000)))
node _T_1363 = asSInt(_T_1362)
node _T_1364 = eq(_T_1363, asSInt(UInt<1>(0h0)))
node _T_1365 = and(_T_1359, _T_1364)
node _T_1366 = or(UInt<1>(0h0), _T_1365)
node _T_1367 = and(_T_1358, _T_1366)
node _T_1368 = asUInt(reset)
node _T_1369 = eq(_T_1368, UInt<1>(0h0))
when _T_1369 :
node _T_1370 = eq(_T_1367, UInt<1>(0h0))
when _T_1370 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_1367, UInt<1>(0h1), "") : assert_41
node _T_1371 = asUInt(reset)
node _T_1372 = eq(_T_1371, UInt<1>(0h0))
when _T_1372 :
node _T_1373 = eq(source_ok, UInt<1>(0h0))
when _T_1373 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, source_ok, UInt<1>(0h1), "") : assert_42
node _T_1374 = asUInt(reset)
node _T_1375 = eq(_T_1374, UInt<1>(0h0))
when _T_1375 :
node _T_1376 = eq(is_aligned, UInt<1>(0h0))
when _T_1376 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_1377 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_1378 = asUInt(reset)
node _T_1379 = eq(_T_1378, UInt<1>(0h0))
when _T_1379 :
node _T_1380 = eq(_T_1377, UInt<1>(0h0))
when _T_1380 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_1377, UInt<1>(0h1), "") : assert_44
node _T_1381 = eq(io.in.a.bits.mask, mask)
node _T_1382 = asUInt(reset)
node _T_1383 = eq(_T_1382, UInt<1>(0h0))
when _T_1383 :
node _T_1384 = eq(_T_1381, UInt<1>(0h0))
when _T_1384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_1381, UInt<1>(0h1), "") : assert_45
node _T_1385 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_1385 :
node _T_1386 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1387 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_1388 = and(_T_1386, _T_1387)
node _T_1389 = eq(io.in.a.bits.source, UInt<9>(0h110))
node _uncommonBits_T_120 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_120 = bits(_uncommonBits_T_120, 1, 0)
node _T_1390 = shr(io.in.a.bits.source, 2)
node _T_1391 = eq(_T_1390, UInt<7>(0h40))
node _T_1392 = leq(UInt<1>(0h0), uncommonBits_120)
node _T_1393 = and(_T_1391, _T_1392)
node _T_1394 = leq(uncommonBits_120, UInt<2>(0h3))
node _T_1395 = and(_T_1393, _T_1394)
node _uncommonBits_T_121 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_121 = bits(_uncommonBits_T_121, 1, 0)
node _T_1396 = shr(io.in.a.bits.source, 2)
node _T_1397 = eq(_T_1396, UInt<7>(0h41))
node _T_1398 = leq(UInt<1>(0h0), uncommonBits_121)
node _T_1399 = and(_T_1397, _T_1398)
node _T_1400 = leq(uncommonBits_121, UInt<2>(0h3))
node _T_1401 = and(_T_1399, _T_1400)
node _uncommonBits_T_122 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_122 = bits(_uncommonBits_T_122, 1, 0)
node _T_1402 = shr(io.in.a.bits.source, 2)
node _T_1403 = eq(_T_1402, UInt<7>(0h42))
node _T_1404 = leq(UInt<1>(0h0), uncommonBits_122)
node _T_1405 = and(_T_1403, _T_1404)
node _T_1406 = leq(uncommonBits_122, UInt<2>(0h3))
node _T_1407 = and(_T_1405, _T_1406)
node _uncommonBits_T_123 = or(io.in.a.bits.source, UInt<2>(0h0))
node uncommonBits_123 = bits(_uncommonBits_T_123, 1, 0)
node _T_1408 = shr(io.in.a.bits.source, 2)
node _T_1409 = eq(_T_1408, UInt<7>(0h43))
node _T_1410 = leq(UInt<1>(0h0), uncommonBits_123)
node _T_1411 = and(_T_1409, _T_1410)
node _T_1412 = leq(uncommonBits_123, UInt<2>(0h3))
node _T_1413 = and(_T_1411, _T_1412)
node _T_1414 = eq(io.in.a.bits.source, UInt<9>(0h120))
node _T_1415 = eq(io.in.a.bits.source, UInt<9>(0h121))
node _T_1416 = eq(io.in.a.bits.source, UInt<9>(0h122))
node _uncommonBits_T_124 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_124 = bits(_uncommonBits_T_124, 4, 0)
node _T_1417 = shr(io.in.a.bits.source, 5)
node _T_1418 = eq(_T_1417, UInt<1>(0h0))
node _T_1419 = leq(UInt<1>(0h0), uncommonBits_124)
node _T_1420 = and(_T_1418, _T_1419)
node _T_1421 = leq(uncommonBits_124, UInt<5>(0h1f))
node _T_1422 = and(_T_1420, _T_1421)
node _uncommonBits_T_125 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_125 = bits(_uncommonBits_T_125, 4, 0)
node _T_1423 = shr(io.in.a.bits.source, 5)
node _T_1424 = eq(_T_1423, UInt<1>(0h1))
node _T_1425 = leq(UInt<1>(0h0), uncommonBits_125)
node _T_1426 = and(_T_1424, _T_1425)
node _T_1427 = leq(uncommonBits_125, UInt<5>(0h1f))
node _T_1428 = and(_T_1426, _T_1427)
node _uncommonBits_T_126 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_126 = bits(_uncommonBits_T_126, 4, 0)
node _T_1429 = shr(io.in.a.bits.source, 5)
node _T_1430 = eq(_T_1429, UInt<2>(0h2))
node _T_1431 = leq(UInt<1>(0h0), uncommonBits_126)
node _T_1432 = and(_T_1430, _T_1431)
node _T_1433 = leq(uncommonBits_126, UInt<5>(0h1f))
node _T_1434 = and(_T_1432, _T_1433)
node _uncommonBits_T_127 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_127 = bits(_uncommonBits_T_127, 4, 0)
node _T_1435 = shr(io.in.a.bits.source, 5)
node _T_1436 = eq(_T_1435, UInt<2>(0h3))
node _T_1437 = leq(UInt<1>(0h0), uncommonBits_127)
node _T_1438 = and(_T_1436, _T_1437)
node _T_1439 = leq(uncommonBits_127, UInt<5>(0h1f))
node _T_1440 = and(_T_1438, _T_1439)
node _uncommonBits_T_128 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_128 = bits(_uncommonBits_T_128, 4, 0)
node _T_1441 = shr(io.in.a.bits.source, 5)
node _T_1442 = eq(_T_1441, UInt<3>(0h4))
node _T_1443 = leq(UInt<1>(0h0), uncommonBits_128)
node _T_1444 = and(_T_1442, _T_1443)
node _T_1445 = leq(uncommonBits_128, UInt<5>(0h1f))
node _T_1446 = and(_T_1444, _T_1445)
node _uncommonBits_T_129 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_129 = bits(_uncommonBits_T_129, 4, 0)
node _T_1447 = shr(io.in.a.bits.source, 5)
node _T_1448 = eq(_T_1447, UInt<3>(0h5))
node _T_1449 = leq(UInt<1>(0h0), uncommonBits_129)
node _T_1450 = and(_T_1448, _T_1449)
node _T_1451 = leq(uncommonBits_129, UInt<5>(0h1f))
node _T_1452 = and(_T_1450, _T_1451)
node _uncommonBits_T_130 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_130 = bits(_uncommonBits_T_130, 4, 0)
node _T_1453 = shr(io.in.a.bits.source, 5)
node _T_1454 = eq(_T_1453, UInt<3>(0h6))
node _T_1455 = leq(UInt<1>(0h0), uncommonBits_130)
node _T_1456 = and(_T_1454, _T_1455)
node _T_1457 = leq(uncommonBits_130, UInt<5>(0h1f))
node _T_1458 = and(_T_1456, _T_1457)
node _uncommonBits_T_131 = or(io.in.a.bits.source, UInt<5>(0h0))
node uncommonBits_131 = bits(_uncommonBits_T_131, 4, 0)
node _T_1459 = shr(io.in.a.bits.source, 5)
node _T_1460 = eq(_T_1459, UInt<3>(0h7))
node _T_1461 = leq(UInt<1>(0h0), uncommonBits_131)
node _T_1462 = and(_T_1460, _T_1461)
node _T_1463 = leq(uncommonBits_131, UInt<5>(0h1f))
node _T_1464 = and(_T_1462, _T_1463)
node _T_1465 = eq(io.in.a.bits.source, UInt<10>(0h200))
node _T_1466 = or(_T_1389, _T_1395)
node _T_1467 = or(_T_1466, _T_1401)
node _T_1468 = or(_T_1467, _T_1407)
node _T_1469 = or(_T_1468, _T_1413)
node _T_1470 = or(_T_1469, _T_1414)
node _T_1471 = or(_T_1470, _T_1415)
node _T_1472 = or(_T_1471, _T_1416)
node _T_1473 = or(_T_1472, _T_1422)
node _T_1474 = or(_T_1473, _T_1428)
node _T_1475 = or(_T_1474, _T_1434)
node _T_1476 = or(_T_1475, _T_1440)
node _T_1477 = or(_T_1476, _T_1446)
node _T_1478 = or(_T_1477, _T_1452)
node _T_1479 = or(_T_1478, _T_1458)
node _T_1480 = or(_T_1479, _T_1464)
node _T_1481 = or(_T_1480, _T_1465)
node _T_1482 = and(_T_1388, _T_1481)
node _T_1483 = or(UInt<1>(0h0), _T_1482)
node _T_1484 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_1485 = xor(io.in.a.bits.address, UInt<13>(0h1000))
node _T_1486 = cvt(_T_1485)
node _T_1487 = and(_T_1486, asSInt(UInt<13>(0h1000)))
node _T_1488 = asSInt(_T_1487)
node _T_1489 = eq(_T_1488, asSInt(UInt<1>(0h0)))
node _T_1490 = and(_T_1484, _T_1489)
node _T_1491 = or(UInt<1>(0h0), _T_1490)
node _T_1492 = and(_T_1483, _T_1491)
node _T_1493 = asUInt(reset)
node _T_1494 = eq(_T_1493, UInt<1>(0h0))
when _T_1494 :
node _T_1495 = eq(_T_1492, UInt<1>(0h0))
when _T_1495 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1492, UInt<1>(0h1), "") : assert_46
node _T_1496 = asUInt(reset)
node _T_1497 = eq(_T_1496, UInt<1>(0h0))
when _T_1497 :
node _T_1498 = eq(source_ok, UInt<1>(0h0))
when _T_1498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, source_ok, UInt<1>(0h1), "") : assert_47
node _T_1499 = asUInt(reset)
node _T_1500 = eq(_T_1499, UInt<1>(0h0))
when _T_1500 :
node _T_1501 = eq(is_aligned, UInt<1>(0h0))
when _T_1501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1502 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1503 = asUInt(reset)
node _T_1504 = eq(_T_1503, UInt<1>(0h0))
when _T_1504 :
node _T_1505 = eq(_T_1502, UInt<1>(0h0))
when _T_1505 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1502, UInt<1>(0h1), "") : assert_49
node _T_1506 = eq(io.in.a.bits.mask, mask)
node _T_1507 = asUInt(reset)
node _T_1508 = eq(_T_1507, UInt<1>(0h0))
when _T_1508 :
node _T_1509 = eq(_T_1506, UInt<1>(0h0))
when _T_1509 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1506, UInt<1>(0h1), "") : assert_50
node _T_1510 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1511 = asUInt(reset)
node _T_1512 = eq(_T_1511, UInt<1>(0h0))
when _T_1512 :
node _T_1513 = eq(_T_1510, UInt<1>(0h0))
when _T_1513 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1510, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1514 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1515 = asUInt(reset)
node _T_1516 = eq(_T_1515, UInt<1>(0h0))
when _T_1516 :
node _T_1517 = eq(_T_1514, UInt<1>(0h0))
when _T_1517 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1514, UInt<1>(0h1), "") : assert_52
node _source_ok_T_92 = eq(io.in.d.bits.source, UInt<9>(0h110))
node _source_ok_uncommonBits_T_12 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_12 = bits(_source_ok_uncommonBits_T_12, 1, 0)
node _source_ok_T_93 = shr(io.in.d.bits.source, 2)
node _source_ok_T_94 = eq(_source_ok_T_93, UInt<7>(0h40))
node _source_ok_T_95 = leq(UInt<1>(0h0), source_ok_uncommonBits_12)
node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95)
node _source_ok_T_97 = leq(source_ok_uncommonBits_12, UInt<2>(0h3))
node _source_ok_T_98 = and(_source_ok_T_96, _source_ok_T_97)
node _source_ok_uncommonBits_T_13 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_13 = bits(_source_ok_uncommonBits_T_13, 1, 0)
node _source_ok_T_99 = shr(io.in.d.bits.source, 2)
node _source_ok_T_100 = eq(_source_ok_T_99, UInt<7>(0h41))
node _source_ok_T_101 = leq(UInt<1>(0h0), source_ok_uncommonBits_13)
node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101)
node _source_ok_T_103 = leq(source_ok_uncommonBits_13, UInt<2>(0h3))
node _source_ok_T_104 = and(_source_ok_T_102, _source_ok_T_103)
node _source_ok_uncommonBits_T_14 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_14 = bits(_source_ok_uncommonBits_T_14, 1, 0)
node _source_ok_T_105 = shr(io.in.d.bits.source, 2)
node _source_ok_T_106 = eq(_source_ok_T_105, UInt<7>(0h42))
node _source_ok_T_107 = leq(UInt<1>(0h0), source_ok_uncommonBits_14)
node _source_ok_T_108 = and(_source_ok_T_106, _source_ok_T_107)
node _source_ok_T_109 = leq(source_ok_uncommonBits_14, UInt<2>(0h3))
node _source_ok_T_110 = and(_source_ok_T_108, _source_ok_T_109)
node _source_ok_uncommonBits_T_15 = or(io.in.d.bits.source, UInt<2>(0h0))
node source_ok_uncommonBits_15 = bits(_source_ok_uncommonBits_T_15, 1, 0)
node _source_ok_T_111 = shr(io.in.d.bits.source, 2)
node _source_ok_T_112 = eq(_source_ok_T_111, UInt<7>(0h43))
node _source_ok_T_113 = leq(UInt<1>(0h0), source_ok_uncommonBits_15)
node _source_ok_T_114 = and(_source_ok_T_112, _source_ok_T_113)
node _source_ok_T_115 = leq(source_ok_uncommonBits_15, UInt<2>(0h3))
node _source_ok_T_116 = and(_source_ok_T_114, _source_ok_T_115)
node _source_ok_T_117 = eq(io.in.d.bits.source, UInt<9>(0h120))
node _source_ok_T_118 = eq(io.in.d.bits.source, UInt<9>(0h121))
node _source_ok_T_119 = eq(io.in.d.bits.source, UInt<9>(0h122))
node _source_ok_uncommonBits_T_16 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_16 = bits(_source_ok_uncommonBits_T_16, 4, 0)
node _source_ok_T_120 = shr(io.in.d.bits.source, 5)
node _source_ok_T_121 = eq(_source_ok_T_120, UInt<1>(0h0))
node _source_ok_T_122 = leq(UInt<1>(0h0), source_ok_uncommonBits_16)
node _source_ok_T_123 = and(_source_ok_T_121, _source_ok_T_122)
node _source_ok_T_124 = leq(source_ok_uncommonBits_16, UInt<5>(0h1f))
node _source_ok_T_125 = and(_source_ok_T_123, _source_ok_T_124)
node _source_ok_uncommonBits_T_17 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_17 = bits(_source_ok_uncommonBits_T_17, 4, 0)
node _source_ok_T_126 = shr(io.in.d.bits.source, 5)
node _source_ok_T_127 = eq(_source_ok_T_126, UInt<1>(0h1))
node _source_ok_T_128 = leq(UInt<1>(0h0), source_ok_uncommonBits_17)
node _source_ok_T_129 = and(_source_ok_T_127, _source_ok_T_128)
node _source_ok_T_130 = leq(source_ok_uncommonBits_17, UInt<5>(0h1f))
node _source_ok_T_131 = and(_source_ok_T_129, _source_ok_T_130)
node _source_ok_uncommonBits_T_18 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_18 = bits(_source_ok_uncommonBits_T_18, 4, 0)
node _source_ok_T_132 = shr(io.in.d.bits.source, 5)
node _source_ok_T_133 = eq(_source_ok_T_132, UInt<2>(0h2))
node _source_ok_T_134 = leq(UInt<1>(0h0), source_ok_uncommonBits_18)
node _source_ok_T_135 = and(_source_ok_T_133, _source_ok_T_134)
node _source_ok_T_136 = leq(source_ok_uncommonBits_18, UInt<5>(0h1f))
node _source_ok_T_137 = and(_source_ok_T_135, _source_ok_T_136)
node _source_ok_uncommonBits_T_19 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_19 = bits(_source_ok_uncommonBits_T_19, 4, 0)
node _source_ok_T_138 = shr(io.in.d.bits.source, 5)
node _source_ok_T_139 = eq(_source_ok_T_138, UInt<2>(0h3))
node _source_ok_T_140 = leq(UInt<1>(0h0), source_ok_uncommonBits_19)
node _source_ok_T_141 = and(_source_ok_T_139, _source_ok_T_140)
node _source_ok_T_142 = leq(source_ok_uncommonBits_19, UInt<5>(0h1f))
node _source_ok_T_143 = and(_source_ok_T_141, _source_ok_T_142)
node _source_ok_uncommonBits_T_20 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_20 = bits(_source_ok_uncommonBits_T_20, 4, 0)
node _source_ok_T_144 = shr(io.in.d.bits.source, 5)
node _source_ok_T_145 = eq(_source_ok_T_144, UInt<3>(0h4))
node _source_ok_T_146 = leq(UInt<1>(0h0), source_ok_uncommonBits_20)
node _source_ok_T_147 = and(_source_ok_T_145, _source_ok_T_146)
node _source_ok_T_148 = leq(source_ok_uncommonBits_20, UInt<5>(0h1f))
node _source_ok_T_149 = and(_source_ok_T_147, _source_ok_T_148)
node _source_ok_uncommonBits_T_21 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_21 = bits(_source_ok_uncommonBits_T_21, 4, 0)
node _source_ok_T_150 = shr(io.in.d.bits.source, 5)
node _source_ok_T_151 = eq(_source_ok_T_150, UInt<3>(0h5))
node _source_ok_T_152 = leq(UInt<1>(0h0), source_ok_uncommonBits_21)
node _source_ok_T_153 = and(_source_ok_T_151, _source_ok_T_152)
node _source_ok_T_154 = leq(source_ok_uncommonBits_21, UInt<5>(0h1f))
node _source_ok_T_155 = and(_source_ok_T_153, _source_ok_T_154)
node _source_ok_uncommonBits_T_22 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_22 = bits(_source_ok_uncommonBits_T_22, 4, 0)
node _source_ok_T_156 = shr(io.in.d.bits.source, 5)
node _source_ok_T_157 = eq(_source_ok_T_156, UInt<3>(0h6))
node _source_ok_T_158 = leq(UInt<1>(0h0), source_ok_uncommonBits_22)
node _source_ok_T_159 = and(_source_ok_T_157, _source_ok_T_158)
node _source_ok_T_160 = leq(source_ok_uncommonBits_22, UInt<5>(0h1f))
node _source_ok_T_161 = and(_source_ok_T_159, _source_ok_T_160)
node _source_ok_uncommonBits_T_23 = or(io.in.d.bits.source, UInt<5>(0h0))
node source_ok_uncommonBits_23 = bits(_source_ok_uncommonBits_T_23, 4, 0)
node _source_ok_T_162 = shr(io.in.d.bits.source, 5)
node _source_ok_T_163 = eq(_source_ok_T_162, UInt<3>(0h7))
node _source_ok_T_164 = leq(UInt<1>(0h0), source_ok_uncommonBits_23)
node _source_ok_T_165 = and(_source_ok_T_163, _source_ok_T_164)
node _source_ok_T_166 = leq(source_ok_uncommonBits_23, UInt<5>(0h1f))
node _source_ok_T_167 = and(_source_ok_T_165, _source_ok_T_166)
node _source_ok_T_168 = eq(io.in.d.bits.source, UInt<10>(0h200))
wire _source_ok_WIRE_1 : UInt<1>[17]
connect _source_ok_WIRE_1[0], _source_ok_T_92
connect _source_ok_WIRE_1[1], _source_ok_T_98
connect _source_ok_WIRE_1[2], _source_ok_T_104
connect _source_ok_WIRE_1[3], _source_ok_T_110
connect _source_ok_WIRE_1[4], _source_ok_T_116
connect _source_ok_WIRE_1[5], _source_ok_T_117
connect _source_ok_WIRE_1[6], _source_ok_T_118
connect _source_ok_WIRE_1[7], _source_ok_T_119
connect _source_ok_WIRE_1[8], _source_ok_T_125
connect _source_ok_WIRE_1[9], _source_ok_T_131
connect _source_ok_WIRE_1[10], _source_ok_T_137
connect _source_ok_WIRE_1[11], _source_ok_T_143
connect _source_ok_WIRE_1[12], _source_ok_T_149
connect _source_ok_WIRE_1[13], _source_ok_T_155
connect _source_ok_WIRE_1[14], _source_ok_T_161
connect _source_ok_WIRE_1[15], _source_ok_T_167
connect _source_ok_WIRE_1[16], _source_ok_T_168
node _source_ok_T_169 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1])
node _source_ok_T_170 = or(_source_ok_T_169, _source_ok_WIRE_1[2])
node _source_ok_T_171 = or(_source_ok_T_170, _source_ok_WIRE_1[3])
node _source_ok_T_172 = or(_source_ok_T_171, _source_ok_WIRE_1[4])
node _source_ok_T_173 = or(_source_ok_T_172, _source_ok_WIRE_1[5])
node _source_ok_T_174 = or(_source_ok_T_173, _source_ok_WIRE_1[6])
node _source_ok_T_175 = or(_source_ok_T_174, _source_ok_WIRE_1[7])
node _source_ok_T_176 = or(_source_ok_T_175, _source_ok_WIRE_1[8])
node _source_ok_T_177 = or(_source_ok_T_176, _source_ok_WIRE_1[9])
node _source_ok_T_178 = or(_source_ok_T_177, _source_ok_WIRE_1[10])
node _source_ok_T_179 = or(_source_ok_T_178, _source_ok_WIRE_1[11])
node _source_ok_T_180 = or(_source_ok_T_179, _source_ok_WIRE_1[12])
node _source_ok_T_181 = or(_source_ok_T_180, _source_ok_WIRE_1[13])
node _source_ok_T_182 = or(_source_ok_T_181, _source_ok_WIRE_1[14])
node _source_ok_T_183 = or(_source_ok_T_182, _source_ok_WIRE_1[15])
node source_ok_1 = or(_source_ok_T_183, _source_ok_WIRE_1[16])
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_1518 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1518 :
node _T_1519 = asUInt(reset)
node _T_1520 = eq(_T_1519, UInt<1>(0h0))
when _T_1520 :
node _T_1521 = eq(source_ok_1, UInt<1>(0h0))
when _T_1521 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53
node _T_1522 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1523 = asUInt(reset)
node _T_1524 = eq(_T_1523, UInt<1>(0h0))
when _T_1524 :
node _T_1525 = eq(_T_1522, UInt<1>(0h0))
when _T_1525 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1522, UInt<1>(0h1), "") : assert_54
node _T_1526 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1527 = asUInt(reset)
node _T_1528 = eq(_T_1527, UInt<1>(0h0))
when _T_1528 :
node _T_1529 = eq(_T_1526, UInt<1>(0h0))
when _T_1529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1526, UInt<1>(0h1), "") : assert_55
node _T_1530 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1531 = asUInt(reset)
node _T_1532 = eq(_T_1531, UInt<1>(0h0))
when _T_1532 :
node _T_1533 = eq(_T_1530, UInt<1>(0h0))
when _T_1533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1530, UInt<1>(0h1), "") : assert_56
node _T_1534 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1535 = asUInt(reset)
node _T_1536 = eq(_T_1535, UInt<1>(0h0))
when _T_1536 :
node _T_1537 = eq(_T_1534, UInt<1>(0h0))
when _T_1537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1534, UInt<1>(0h1), "") : assert_57
node _T_1538 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1538 :
node _T_1539 = asUInt(reset)
node _T_1540 = eq(_T_1539, UInt<1>(0h0))
when _T_1540 :
node _T_1541 = eq(source_ok_1, UInt<1>(0h0))
when _T_1541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58
node _T_1542 = asUInt(reset)
node _T_1543 = eq(_T_1542, UInt<1>(0h0))
when _T_1543 :
node _T_1544 = eq(sink_ok, UInt<1>(0h0))
when _T_1544 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1545 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1546 = asUInt(reset)
node _T_1547 = eq(_T_1546, UInt<1>(0h0))
when _T_1547 :
node _T_1548 = eq(_T_1545, UInt<1>(0h0))
when _T_1548 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1545, UInt<1>(0h1), "") : assert_60
node _T_1549 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1550 = asUInt(reset)
node _T_1551 = eq(_T_1550, UInt<1>(0h0))
when _T_1551 :
node _T_1552 = eq(_T_1549, UInt<1>(0h0))
when _T_1552 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1549, UInt<1>(0h1), "") : assert_61
node _T_1553 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1554 = asUInt(reset)
node _T_1555 = eq(_T_1554, UInt<1>(0h0))
when _T_1555 :
node _T_1556 = eq(_T_1553, UInt<1>(0h0))
when _T_1556 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1553, UInt<1>(0h1), "") : assert_62
node _T_1557 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1558 = asUInt(reset)
node _T_1559 = eq(_T_1558, UInt<1>(0h0))
when _T_1559 :
node _T_1560 = eq(_T_1557, UInt<1>(0h0))
when _T_1560 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1557, UInt<1>(0h1), "") : assert_63
node _T_1561 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1562 = or(UInt<1>(0h0), _T_1561)
node _T_1563 = asUInt(reset)
node _T_1564 = eq(_T_1563, UInt<1>(0h0))
when _T_1564 :
node _T_1565 = eq(_T_1562, UInt<1>(0h0))
when _T_1565 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1562, UInt<1>(0h1), "") : assert_64
node _T_1566 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1566 :
node _T_1567 = asUInt(reset)
node _T_1568 = eq(_T_1567, UInt<1>(0h0))
when _T_1568 :
node _T_1569 = eq(source_ok_1, UInt<1>(0h0))
when _T_1569 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65
node _T_1570 = asUInt(reset)
node _T_1571 = eq(_T_1570, UInt<1>(0h0))
when _T_1571 :
node _T_1572 = eq(sink_ok, UInt<1>(0h0))
when _T_1572 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1573 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1574 = asUInt(reset)
node _T_1575 = eq(_T_1574, UInt<1>(0h0))
when _T_1575 :
node _T_1576 = eq(_T_1573, UInt<1>(0h0))
when _T_1576 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1573, UInt<1>(0h1), "") : assert_67
node _T_1577 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1578 = asUInt(reset)
node _T_1579 = eq(_T_1578, UInt<1>(0h0))
when _T_1579 :
node _T_1580 = eq(_T_1577, UInt<1>(0h0))
when _T_1580 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1577, UInt<1>(0h1), "") : assert_68
node _T_1581 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1582 = asUInt(reset)
node _T_1583 = eq(_T_1582, UInt<1>(0h0))
when _T_1583 :
node _T_1584 = eq(_T_1581, UInt<1>(0h0))
when _T_1584 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1581, UInt<1>(0h1), "") : assert_69
node _T_1585 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1586 = or(_T_1585, io.in.d.bits.corrupt)
node _T_1587 = asUInt(reset)
node _T_1588 = eq(_T_1587, UInt<1>(0h0))
when _T_1588 :
node _T_1589 = eq(_T_1586, UInt<1>(0h0))
when _T_1589 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1586, UInt<1>(0h1), "") : assert_70
node _T_1590 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1591 = or(UInt<1>(0h0), _T_1590)
node _T_1592 = asUInt(reset)
node _T_1593 = eq(_T_1592, UInt<1>(0h0))
when _T_1593 :
node _T_1594 = eq(_T_1591, UInt<1>(0h0))
when _T_1594 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1591, UInt<1>(0h1), "") : assert_71
node _T_1595 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1595 :
node _T_1596 = asUInt(reset)
node _T_1597 = eq(_T_1596, UInt<1>(0h0))
when _T_1597 :
node _T_1598 = eq(source_ok_1, UInt<1>(0h0))
when _T_1598 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72
node _T_1599 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1600 = asUInt(reset)
node _T_1601 = eq(_T_1600, UInt<1>(0h0))
when _T_1601 :
node _T_1602 = eq(_T_1599, UInt<1>(0h0))
when _T_1602 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1599, UInt<1>(0h1), "") : assert_73
node _T_1603 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1604 = asUInt(reset)
node _T_1605 = eq(_T_1604, UInt<1>(0h0))
when _T_1605 :
node _T_1606 = eq(_T_1603, UInt<1>(0h0))
when _T_1606 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1603, UInt<1>(0h1), "") : assert_74
node _T_1607 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1608 = or(UInt<1>(0h0), _T_1607)
node _T_1609 = asUInt(reset)
node _T_1610 = eq(_T_1609, UInt<1>(0h0))
when _T_1610 :
node _T_1611 = eq(_T_1608, UInt<1>(0h0))
when _T_1611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1608, UInt<1>(0h1), "") : assert_75
node _T_1612 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1612 :
node _T_1613 = asUInt(reset)
node _T_1614 = eq(_T_1613, UInt<1>(0h0))
when _T_1614 :
node _T_1615 = eq(source_ok_1, UInt<1>(0h0))
when _T_1615 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76
node _T_1616 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1617 = asUInt(reset)
node _T_1618 = eq(_T_1617, UInt<1>(0h0))
when _T_1618 :
node _T_1619 = eq(_T_1616, UInt<1>(0h0))
when _T_1619 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1616, UInt<1>(0h1), "") : assert_77
node _T_1620 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1621 = or(_T_1620, io.in.d.bits.corrupt)
node _T_1622 = asUInt(reset)
node _T_1623 = eq(_T_1622, UInt<1>(0h0))
when _T_1623 :
node _T_1624 = eq(_T_1621, UInt<1>(0h0))
when _T_1624 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1621, UInt<1>(0h1), "") : assert_78
node _T_1625 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1626 = or(UInt<1>(0h0), _T_1625)
node _T_1627 = asUInt(reset)
node _T_1628 = eq(_T_1627, UInt<1>(0h0))
when _T_1628 :
node _T_1629 = eq(_T_1626, UInt<1>(0h0))
when _T_1629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1626, UInt<1>(0h1), "") : assert_79
node _T_1630 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1630 :
node _T_1631 = asUInt(reset)
node _T_1632 = eq(_T_1631, UInt<1>(0h0))
when _T_1632 :
node _T_1633 = eq(source_ok_1, UInt<1>(0h0))
when _T_1633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80
node _T_1634 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1635 = asUInt(reset)
node _T_1636 = eq(_T_1635, UInt<1>(0h0))
when _T_1636 :
node _T_1637 = eq(_T_1634, UInt<1>(0h0))
when _T_1637 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1634, UInt<1>(0h1), "") : assert_81
node _T_1638 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1639 = asUInt(reset)
node _T_1640 = eq(_T_1639, UInt<1>(0h0))
when _T_1640 :
node _T_1641 = eq(_T_1638, UInt<1>(0h0))
when _T_1641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1638, UInt<1>(0h1), "") : assert_82
node _T_1642 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1643 = or(UInt<1>(0h0), _T_1642)
node _T_1644 = asUInt(reset)
node _T_1645 = eq(_T_1644, UInt<1>(0h0))
when _T_1645 :
node _T_1646 = eq(_T_1643, UInt<1>(0h0))
when _T_1646 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1643, UInt<1>(0h1), "") : assert_83
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<13>(0h0)
connect _WIRE_4.bits.source, UInt<10>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<10>, address : UInt<13>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1647 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1648 = asUInt(reset)
node _T_1649 = eq(_T_1648, UInt<1>(0h0))
when _T_1649 :
node _T_1650 = eq(_T_1647, UInt<1>(0h0))
when _T_1650 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1647, UInt<1>(0h1), "") : assert_84
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<13>(0h0)
connect _WIRE_6.bits.source, UInt<10>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1651 = eq(_WIRE_7.valid, UInt<1>(0h0))
node _T_1652 = asUInt(reset)
node _T_1653 = eq(_T_1652, UInt<1>(0h0))
when _T_1653 :
node _T_1654 = eq(_T_1651, UInt<1>(0h0))
when _T_1654 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1651, UInt<1>(0h1), "") : assert_85
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_8.bits.sink, UInt<1>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1655 = eq(_WIRE_9.valid, UInt<1>(0h0))
node _T_1656 = asUInt(reset)
node _T_1657 = eq(_T_1656, UInt<1>(0h0))
when _T_1657 :
node _T_1658 = eq(_T_1655, UInt<1>(0h0))
when _T_1658 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1655, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1659 = eq(a_first, UInt<1>(0h0))
node _T_1660 = and(io.in.a.valid, _T_1659)
when _T_1660 :
node _T_1661 = eq(io.in.a.bits.opcode, opcode)
node _T_1662 = asUInt(reset)
node _T_1663 = eq(_T_1662, UInt<1>(0h0))
when _T_1663 :
node _T_1664 = eq(_T_1661, UInt<1>(0h0))
when _T_1664 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1661, UInt<1>(0h1), "") : assert_87
node _T_1665 = eq(io.in.a.bits.param, param)
node _T_1666 = asUInt(reset)
node _T_1667 = eq(_T_1666, UInt<1>(0h0))
when _T_1667 :
node _T_1668 = eq(_T_1665, UInt<1>(0h0))
when _T_1668 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1665, UInt<1>(0h1), "") : assert_88
node _T_1669 = eq(io.in.a.bits.size, size)
node _T_1670 = asUInt(reset)
node _T_1671 = eq(_T_1670, UInt<1>(0h0))
when _T_1671 :
node _T_1672 = eq(_T_1669, UInt<1>(0h0))
when _T_1672 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1669, UInt<1>(0h1), "") : assert_89
node _T_1673 = eq(io.in.a.bits.source, source)
node _T_1674 = asUInt(reset)
node _T_1675 = eq(_T_1674, UInt<1>(0h0))
when _T_1675 :
node _T_1676 = eq(_T_1673, UInt<1>(0h0))
when _T_1676 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1673, UInt<1>(0h1), "") : assert_90
node _T_1677 = eq(io.in.a.bits.address, address)
node _T_1678 = asUInt(reset)
node _T_1679 = eq(_T_1678, UInt<1>(0h0))
when _T_1679 :
node _T_1680 = eq(_T_1677, UInt<1>(0h0))
when _T_1680 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1677, UInt<1>(0h1), "") : assert_91
node _T_1681 = and(io.in.a.ready, io.in.a.valid)
node _T_1682 = and(_T_1681, a_first)
when _T_1682 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1683 = eq(d_first, UInt<1>(0h0))
node _T_1684 = and(io.in.d.valid, _T_1683)
when _T_1684 :
node _T_1685 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1686 = asUInt(reset)
node _T_1687 = eq(_T_1686, UInt<1>(0h0))
when _T_1687 :
node _T_1688 = eq(_T_1685, UInt<1>(0h0))
when _T_1688 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1685, UInt<1>(0h1), "") : assert_92
node _T_1689 = eq(io.in.d.bits.param, param_1)
node _T_1690 = asUInt(reset)
node _T_1691 = eq(_T_1690, UInt<1>(0h0))
when _T_1691 :
node _T_1692 = eq(_T_1689, UInt<1>(0h0))
when _T_1692 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1689, UInt<1>(0h1), "") : assert_93
node _T_1693 = eq(io.in.d.bits.size, size_1)
node _T_1694 = asUInt(reset)
node _T_1695 = eq(_T_1694, UInt<1>(0h0))
when _T_1695 :
node _T_1696 = eq(_T_1693, UInt<1>(0h0))
when _T_1696 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1693, UInt<1>(0h1), "") : assert_94
node _T_1697 = eq(io.in.d.bits.source, source_1)
node _T_1698 = asUInt(reset)
node _T_1699 = eq(_T_1698, UInt<1>(0h0))
when _T_1699 :
node _T_1700 = eq(_T_1697, UInt<1>(0h0))
when _T_1700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1697, UInt<1>(0h1), "") : assert_95
node _T_1701 = eq(io.in.d.bits.sink, sink)
node _T_1702 = asUInt(reset)
node _T_1703 = eq(_T_1702, UInt<1>(0h0))
when _T_1703 :
node _T_1704 = eq(_T_1701, UInt<1>(0h0))
when _T_1704 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1701, UInt<1>(0h1), "") : assert_96
node _T_1705 = eq(io.in.d.bits.denied, denied)
node _T_1706 = asUInt(reset)
node _T_1707 = eq(_T_1706, UInt<1>(0h0))
when _T_1707 :
node _T_1708 = eq(_T_1705, UInt<1>(0h0))
when _T_1708 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1705, UInt<1>(0h1), "") : assert_97
node _T_1709 = and(io.in.d.ready, io.in.d.valid)
node _T_1710 = and(_T_1709, d_first)
when _T_1710 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<513>, clock, reset, UInt<513>(0h0)
regreset inflight_opcodes : UInt<2052>, clock, reset, UInt<2052>(0h0)
regreset inflight_sizes : UInt<2052>, clock, reset, UInt<2052>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<513>
connect a_set, UInt<513>(0h0)
wire a_set_wo_ready : UInt<513>
connect a_set_wo_ready, UInt<513>(0h0)
wire a_opcodes_set : UInt<2052>
connect a_opcodes_set, UInt<2052>(0h0)
wire a_sizes_set : UInt<2052>
connect a_sizes_set, UInt<2052>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<4>
connect a_sizes_set_interm, UInt<4>(0h0)
node _T_1711 = and(io.in.a.valid, a_first_1)
node _T_1712 = and(_T_1711, UInt<1>(0h1))
when _T_1712 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1713 = and(io.in.a.ready, io.in.a.valid)
node _T_1714 = and(_T_1713, a_first_1)
node _T_1715 = and(_T_1714, UInt<1>(0h1))
when _T_1715 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1716 = dshr(inflight, io.in.a.bits.source)
node _T_1717 = bits(_T_1716, 0, 0)
node _T_1718 = eq(_T_1717, UInt<1>(0h0))
node _T_1719 = asUInt(reset)
node _T_1720 = eq(_T_1719, UInt<1>(0h0))
when _T_1720 :
node _T_1721 = eq(_T_1718, UInt<1>(0h0))
when _T_1721 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1718, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<513>
connect d_clr, UInt<513>(0h0)
wire d_clr_wo_ready : UInt<513>
connect d_clr_wo_ready, UInt<513>(0h0)
wire d_opcodes_clr : UInt<2052>
connect d_opcodes_clr, UInt<2052>(0h0)
wire d_sizes_clr : UInt<2052>
connect d_sizes_clr, UInt<2052>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1722 = and(io.in.d.valid, d_first_1)
node _T_1723 = and(_T_1722, UInt<1>(0h1))
node _T_1724 = eq(d_release_ack, UInt<1>(0h0))
node _T_1725 = and(_T_1723, _T_1724)
when _T_1725 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1726 = and(io.in.d.ready, io.in.d.valid)
node _T_1727 = and(_T_1726, d_first_1)
node _T_1728 = and(_T_1727, UInt<1>(0h1))
node _T_1729 = eq(d_release_ack, UInt<1>(0h0))
node _T_1730 = and(_T_1728, _T_1729)
when _T_1730 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1731 = and(io.in.d.valid, d_first_1)
node _T_1732 = and(_T_1731, UInt<1>(0h1))
node _T_1733 = eq(d_release_ack, UInt<1>(0h0))
node _T_1734 = and(_T_1732, _T_1733)
when _T_1734 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1735 = dshr(inflight, io.in.d.bits.source)
node _T_1736 = bits(_T_1735, 0, 0)
node _T_1737 = or(_T_1736, same_cycle_resp)
node _T_1738 = asUInt(reset)
node _T_1739 = eq(_T_1738, UInt<1>(0h0))
when _T_1739 :
node _T_1740 = eq(_T_1737, UInt<1>(0h0))
when _T_1740 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1737, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1741 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1742 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1743 = or(_T_1741, _T_1742)
node _T_1744 = asUInt(reset)
node _T_1745 = eq(_T_1744, UInt<1>(0h0))
when _T_1745 :
node _T_1746 = eq(_T_1743, UInt<1>(0h0))
when _T_1746 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1743, UInt<1>(0h1), "") : assert_100
node _T_1747 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1748 = asUInt(reset)
node _T_1749 = eq(_T_1748, UInt<1>(0h0))
when _T_1749 :
node _T_1750 = eq(_T_1747, UInt<1>(0h0))
when _T_1750 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1747, UInt<1>(0h1), "") : assert_101
else :
node _T_1751 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1752 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1753 = or(_T_1751, _T_1752)
node _T_1754 = asUInt(reset)
node _T_1755 = eq(_T_1754, UInt<1>(0h0))
when _T_1755 :
node _T_1756 = eq(_T_1753, UInt<1>(0h0))
when _T_1756 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1753, UInt<1>(0h1), "") : assert_102
node _T_1757 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1758 = asUInt(reset)
node _T_1759 = eq(_T_1758, UInt<1>(0h0))
when _T_1759 :
node _T_1760 = eq(_T_1757, UInt<1>(0h0))
when _T_1760 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1757, UInt<1>(0h1), "") : assert_103
node _T_1761 = and(io.in.d.valid, d_first_1)
node _T_1762 = and(_T_1761, a_first_1)
node _T_1763 = and(_T_1762, io.in.a.valid)
node _T_1764 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1765 = and(_T_1763, _T_1764)
node _T_1766 = eq(d_release_ack, UInt<1>(0h0))
node _T_1767 = and(_T_1765, _T_1766)
when _T_1767 :
node _T_1768 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1769 = or(_T_1768, io.in.a.ready)
node _T_1770 = asUInt(reset)
node _T_1771 = eq(_T_1770, UInt<1>(0h0))
when _T_1771 :
node _T_1772 = eq(_T_1769, UInt<1>(0h0))
when _T_1772 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1769, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_22
node _T_1773 = orr(inflight)
node _T_1774 = eq(_T_1773, UInt<1>(0h0))
node _T_1775 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1776 = or(_T_1774, _T_1775)
node _T_1777 = lt(watchdog, plusarg_reader.out)
node _T_1778 = or(_T_1776, _T_1777)
node _T_1779 = asUInt(reset)
node _T_1780 = eq(_T_1779, UInt<1>(0h0))
when _T_1780 :
node _T_1781 = eq(_T_1778, UInt<1>(0h0))
when _T_1781 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_1778, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1782 = and(io.in.a.ready, io.in.a.valid)
node _T_1783 = and(io.in.d.ready, io.in.d.valid)
node _T_1784 = or(_T_1782, _T_1783)
when _T_1784 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<513>, clock, reset, UInt<513>(0h0)
regreset inflight_opcodes_1 : UInt<2052>, clock, reset, UInt<2052>(0h0)
regreset inflight_sizes_1 : UInt<2052>, clock, reset, UInt<2052>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<13>(0h0)
connect _c_first_WIRE.bits.source, UInt<10>(0h0)
connect _c_first_WIRE.bits.size, UInt<3>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<13>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<10>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<513>
connect c_set, UInt<513>(0h0)
wire c_set_wo_ready : UInt<513>
connect c_set_wo_ready, UInt<513>(0h0)
wire c_opcodes_set : UInt<2052>
connect c_opcodes_set, UInt<2052>(0h0)
wire c_sizes_set : UInt<2052>
connect c_sizes_set, UInt<2052>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<4>
connect c_sizes_set_interm, UInt<4>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<13>(0h0)
connect _WIRE_10.bits.source, UInt<10>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1785 = and(_WIRE_11.valid, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<13>(0h0)
connect _WIRE_12.bits.source, UInt<10>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1786 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1787 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1788 = and(_T_1786, _T_1787)
node _T_1789 = and(_T_1785, _T_1788)
when _T_1789 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<13>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<10>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<13>(0h0)
connect _WIRE_14.bits.source, UInt<10>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1790 = and(_WIRE_15.ready, _WIRE_15.valid)
node _T_1791 = and(_T_1790, c_first)
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<13>(0h0)
connect _WIRE_16.bits.source, UInt<10>(0h0)
connect _WIRE_16.bits.size, UInt<3>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1792 = bits(_WIRE_17.bits.opcode, 2, 2)
node _T_1793 = bits(_WIRE_17.bits.opcode, 1, 1)
node _T_1794 = and(_T_1792, _T_1793)
node _T_1795 = and(_T_1791, _T_1794)
when _T_1795 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<13>(0h0)
connect _c_set_WIRE.bits.source, UInt<10>(0h0)
connect _c_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<13>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<10>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<13>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<10>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<13>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<10>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<13>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<10>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<13>(0h0)
connect _WIRE_18.bits.source, UInt<10>(0h0)
connect _WIRE_18.bits.size, UInt<3>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1796 = dshr(inflight_1, _WIRE_19.bits.source)
node _T_1797 = bits(_T_1796, 0, 0)
node _T_1798 = eq(_T_1797, UInt<1>(0h0))
node _T_1799 = asUInt(reset)
node _T_1800 = eq(_T_1799, UInt<1>(0h0))
when _T_1800 :
node _T_1801 = eq(_T_1798, UInt<1>(0h0))
when _T_1801 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1798, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<13>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<10>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<13>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<10>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<513>
connect d_clr_1, UInt<513>(0h0)
wire d_clr_wo_ready_1 : UInt<513>
connect d_clr_wo_ready_1, UInt<513>(0h0)
wire d_opcodes_clr_1 : UInt<2052>
connect d_opcodes_clr_1, UInt<2052>(0h0)
wire d_sizes_clr_1 : UInt<2052>
connect d_sizes_clr_1, UInt<2052>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1802 = and(io.in.d.valid, d_first_2)
node _T_1803 = and(_T_1802, UInt<1>(0h1))
node _T_1804 = and(_T_1803, d_release_ack_1)
when _T_1804 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1805 = and(io.in.d.ready, io.in.d.valid)
node _T_1806 = and(_T_1805, d_first_2)
node _T_1807 = and(_T_1806, UInt<1>(0h1))
node _T_1808 = and(_T_1807, d_release_ack_1)
when _T_1808 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1809 = and(io.in.d.valid, d_first_2)
node _T_1810 = and(_T_1809, UInt<1>(0h1))
node _T_1811 = and(_T_1810, d_release_ack_1)
when _T_1811 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<13>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<10>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<13>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<10>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<13>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<10>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1812 = dshr(inflight_1, io.in.d.bits.source)
node _T_1813 = bits(_T_1812, 0, 0)
node _T_1814 = or(_T_1813, same_cycle_resp_1)
node _T_1815 = asUInt(reset)
node _T_1816 = eq(_T_1815, UInt<1>(0h0))
when _T_1816 :
node _T_1817 = eq(_T_1814, UInt<1>(0h0))
when _T_1817 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_1814, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<13>(0h0)
connect _WIRE_20.bits.source, UInt<10>(0h0)
connect _WIRE_20.bits.size, UInt<3>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1818 = eq(io.in.d.bits.size, _WIRE_21.bits.size)
node _T_1819 = asUInt(reset)
node _T_1820 = eq(_T_1819, UInt<1>(0h0))
when _T_1820 :
node _T_1821 = eq(_T_1818, UInt<1>(0h0))
when _T_1821 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1818, UInt<1>(0h1), "") : assert_108
else :
node _T_1822 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1823 = asUInt(reset)
node _T_1824 = eq(_T_1823, UInt<1>(0h0))
when _T_1824 :
node _T_1825 = eq(_T_1822, UInt<1>(0h0))
when _T_1825 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1822, UInt<1>(0h1), "") : assert_109
node _T_1826 = and(io.in.d.valid, d_first_2)
node _T_1827 = and(_T_1826, c_first)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<13>(0h0)
connect _WIRE_22.bits.source, UInt<10>(0h0)
connect _WIRE_22.bits.size, UInt<3>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1828 = and(_T_1827, _WIRE_23.valid)
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<13>(0h0)
connect _WIRE_24.bits.source, UInt<10>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1829 = eq(_WIRE_25.bits.source, io.in.d.bits.source)
node _T_1830 = and(_T_1828, _T_1829)
node _T_1831 = and(_T_1830, d_release_ack_1)
node _T_1832 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1833 = and(_T_1831, _T_1832)
when _T_1833 :
node _T_1834 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.address, UInt<13>(0h0)
connect _WIRE_26.bits.source, UInt<10>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<3>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
node _T_1835 = or(_T_1834, _WIRE_27.ready)
node _T_1836 = asUInt(reset)
node _T_1837 = eq(_T_1836, UInt<1>(0h0))
when _T_1837 :
node _T_1838 = eq(_T_1835, UInt<1>(0h0))
when _T_1838 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1835, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_23
node _T_1839 = orr(inflight_1)
node _T_1840 = eq(_T_1839, UInt<1>(0h0))
node _T_1841 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1842 = or(_T_1840, _T_1841)
node _T_1843 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1844 = or(_T_1842, _T_1843)
node _T_1845 = asUInt(reset)
node _T_1846 = eq(_T_1845, UInt<1>(0h0))
when _T_1846 :
node _T_1847 = eq(_T_1844, UInt<1>(0h0))
when _T_1847 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/boot/BootAddrReg.scala:25:93)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_1844, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.address, UInt<13>(0h0)
connect _WIRE_28.bits.source, UInt<10>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<3>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<13>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
node _T_1848 = and(_WIRE_29.ready, _WIRE_29.valid)
node _T_1849 = and(io.in.d.ready, io.in.d.valid)
node _T_1850 = or(_T_1848, _T_1849)
when _T_1850 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_11( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [9:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [12:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [9:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [2:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [2:0] size; // @[Monitor.scala:389:22]
reg [9:0] source; // @[Monitor.scala:390:22]
reg [12:0] address; // @[Monitor.scala:391:22]
reg [2:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [2:0] size_1; // @[Monitor.scala:540:22]
reg [9:0] source_1; // @[Monitor.scala:541:22]
reg [512:0] inflight; // @[Monitor.scala:614:27]
reg [2051:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [2051:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [2:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [2:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [512:0] inflight_1; // @[Monitor.scala:726:35]
reg [2051:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [2:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s4k1z4u_1 :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_20
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_q of Queue2_TLBundleA_a32d64s4k1z4u_1
connect nodeOut_a_q.clock, clock
connect nodeOut_a_q.reset, reset
connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid
connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data
connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address
connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source
connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size
connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param
connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready
connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid
connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_q of Queue2_TLBundleD_a32d64s4k1z4u_1
connect nodeIn_d_q.clock, clock
connect nodeIn_d_q.reset, reset
connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid
connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data
connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source
connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size
connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param
connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready
connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid
connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<4>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.valid, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<4>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.ready, UInt<1>(0h1)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<4>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.ready, UInt<1>(0h1)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<4>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
connect _WIRE_9.valid, UInt<1>(0h0)
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_10.bits.sink, UInt<1>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
connect _WIRE_11.valid, UInt<1>(0h0) | module TLBuffer_a32d64s4k1z4u_1( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_a_bits_corrupt_0 = auto_in_a_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_a_bits_corrupt = auto_in_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
TLMonitor_20 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_a_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a32d64s4k1z4u_1 nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_enq_bits_corrupt (nodeIn_a_bits_corrupt), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a32d64s4k1z4u_1 nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_367 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_111
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<32>, clock
reg c2 : SInt<32>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node c1_sign = bits(io.in_d, 19, 19)
node c1_lo_lo_hi = cat(c1_sign, c1_sign)
node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign)
node c1_lo_hi_hi = cat(c1_sign, c1_sign)
node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign)
node c1_lo = cat(c1_lo_hi, c1_lo_lo)
node c1_hi_lo_hi = cat(c1_sign, c1_sign)
node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign)
node c1_hi_hi_hi = cat(c1_sign, c1_sign)
node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign)
node c1_hi = cat(c1_hi_hi, c1_hi_lo)
node _c1_T = cat(c1_hi, c1_lo)
node c1_lo_1 = asUInt(io.in_d)
node _c1_T_1 = cat(_c1_T, c1_lo_1)
wire _c1_WIRE : SInt<32>
node _c1_T_2 = asSInt(_c1_T_1)
connect _c1_WIRE, _c1_T_2
connect c1, _c1_WIRE
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node c2_sign = bits(io.in_d, 19, 19)
node c2_lo_lo_hi = cat(c2_sign, c2_sign)
node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign)
node c2_lo_hi_hi = cat(c2_sign, c2_sign)
node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign)
node c2_lo = cat(c2_lo_hi, c2_lo_lo)
node c2_hi_lo_hi = cat(c2_sign, c2_sign)
node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign)
node c2_hi_hi_hi = cat(c2_sign, c2_sign)
node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign)
node c2_hi = cat(c2_hi_hi, c2_hi_lo)
node _c2_T = cat(c2_hi, c2_lo)
node c2_lo_1 = asUInt(io.in_d)
node _c2_T_1 = cat(_c2_T, c2_lo_1)
wire _c2_WIRE : SInt<32>
node _c2_T_2 = asSInt(_c2_T_1)
connect _c2_WIRE, _c2_T_2
connect c2, _c2_WIRE
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h1), _T_4)
node _T_6 = or(UInt<1>(0h0), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_367( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_111 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_158 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
node _io_out_T = shl(io.in, 0)
connect io.out, _io_out_T
node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22)
node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0))
node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1)
node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0))
connect io.exceptionFlags, _io_exceptionFlags_T_3 | module RecFNToRecFN_158( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [32:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16]
wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35]
wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54]
wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35]
wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}]
wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23]
assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46]
assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_26 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, flip out_credit_available : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], debug : { va_stall : UInt<2>, sa_stall : UInt<2>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}}
inst input_buffer of InputBuffer_26
connect input_buffer.clock, clock
connect input_buffer.reset, reset
connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id
connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id
connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node
connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id
connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node
connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id
connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload
connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail
connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head
connect input_buffer.io.enq[0].valid, io.in.flit[0].valid
connect input_buffer.io.deq[0].ready, UInt<1>(0h0)
connect input_buffer.io.deq[1].ready, UInt<1>(0h0)
connect input_buffer.io.deq[2].ready, UInt<1>(0h0)
inst route_arbiter of Arbiter3_RouteComputerReq_26
connect route_arbiter.clock, clock
connect route_arbiter.reset, reset
connect io.router_req.bits, route_arbiter.io.out.bits
connect io.router_req.valid, route_arbiter.io.out.valid
connect route_arbiter.io.out.ready, io.router_req.ready
reg states : { g : UInt<3>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<3>}[3], clock
node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T :
node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3))
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert
node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0))
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1
assert(clock, _T_5, UInt<1>(0h1), "") : assert_1
node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h8))
node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1))
connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0)
node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id)
when _T_9 :
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h1)
connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow
connect route_arbiter.io.in[0].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[0].bits.flow.egress_node_id
invalidate route_arbiter.io.in[0].bits.flow.egress_node
invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[0].bits.flow.ingress_node
invalidate route_arbiter.io.in[0].bits.flow.vnet_id
invalidate route_arbiter.io.in[0].bits.src_virt_id
connect route_arbiter.io.in[1].valid, UInt<1>(0h0)
invalidate route_arbiter.io.in[1].bits.flow.egress_node_id
invalidate route_arbiter.io.in[1].bits.flow.egress_node
invalidate route_arbiter.io.in[1].bits.flow.ingress_node_id
invalidate route_arbiter.io.in[1].bits.flow.ingress_node
invalidate route_arbiter.io.in[1].bits.flow.vnet_id
invalidate route_arbiter.io.in[1].bits.src_virt_id
node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1))
connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T
connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id
connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node
connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id
connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node
connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id
connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2)
node _T_10 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid)
when _T_10 :
connect states[2].g, UInt<3>(0h2)
node _T_11 = and(io.router_req.ready, io.router_req.valid)
when _T_11 :
node _T_12 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1))
node _T_13 = asUInt(reset)
node _T_14 = eq(_T_13, UInt<1>(0h0))
when _T_14 :
node _T_15 = eq(_T_12, UInt<1>(0h0))
when _T_15 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2
assert(clock, _T_12, UInt<1>(0h1), "") : assert_2
connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2)
node _T_16 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id)
when _T_16 :
connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_17 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id)
when _T_17 :
connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _T_18 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id)
when _T_18 :
connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3`
regreset mask : UInt<3>, clock, reset, UInt<3>(0h0)
wire vcalloc_reqs : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}[3]
wire vcalloc_vals : UInt<1>[3]
node vcalloc_filter_hi = cat(vcalloc_vals[2], vcalloc_vals[1])
node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_vals[0])
node vcalloc_filter_hi_1 = cat(vcalloc_vals[2], vcalloc_vals[1])
node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_vals[0])
node _vcalloc_filter_T_2 = not(mask)
node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2)
node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3)
node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0)
node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1)
node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2)
node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3)
node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4)
node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5)
node _vcalloc_filter_T_11 = mux(_vcalloc_filter_T_10, UInt<6>(0h20), UInt<6>(0h0))
node _vcalloc_filter_T_12 = mux(_vcalloc_filter_T_9, UInt<6>(0h10), _vcalloc_filter_T_11)
node _vcalloc_filter_T_13 = mux(_vcalloc_filter_T_8, UInt<6>(0h8), _vcalloc_filter_T_12)
node _vcalloc_filter_T_14 = mux(_vcalloc_filter_T_7, UInt<6>(0h4), _vcalloc_filter_T_13)
node _vcalloc_filter_T_15 = mux(_vcalloc_filter_T_6, UInt<6>(0h2), _vcalloc_filter_T_14)
node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<6>(0h1), _vcalloc_filter_T_15)
node _vcalloc_sel_T = bits(vcalloc_filter, 2, 0)
node _vcalloc_sel_T_1 = shr(vcalloc_filter, 3)
node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1)
node _T_19 = and(io.router_req.ready, io.router_req.valid)
when _T_19 :
node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id)
node _mask_T_1 = sub(_mask_T, UInt<1>(0h1))
node _mask_T_2 = tail(_mask_T_1, 1)
connect mask, _mask_T_2
else :
node _T_20 = or(vcalloc_vals[0], vcalloc_vals[1])
node _T_21 = or(_T_20, vcalloc_vals[2])
when _T_21 :
node _mask_T_3 = not(UInt<1>(0h0))
node _mask_T_4 = not(UInt<2>(0h0))
node _mask_T_5 = not(UInt<3>(0h0))
node _mask_T_6 = bits(vcalloc_sel, 0, 0)
node _mask_T_7 = bits(vcalloc_sel, 1, 1)
node _mask_T_8 = bits(vcalloc_sel, 2, 2)
node _mask_T_9 = mux(_mask_T_6, _mask_T_3, UInt<1>(0h0))
node _mask_T_10 = mux(_mask_T_7, _mask_T_4, UInt<1>(0h0))
node _mask_T_11 = mux(_mask_T_8, _mask_T_5, UInt<1>(0h0))
node _mask_T_12 = or(_mask_T_9, _mask_T_10)
node _mask_T_13 = or(_mask_T_12, _mask_T_11)
wire _mask_WIRE : UInt<3>
connect _mask_WIRE, _mask_T_13
connect mask, _mask_WIRE
node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1])
node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2])
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_1
node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0)
node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1)
node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2)
wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}
wire _io_vcalloc_req_bits_WIRE_1 : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}
wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[3]
node _io_vcalloc_req_bits_T_3 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_4 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_6 = or(_io_vcalloc_req_bits_T_3, _io_vcalloc_req_bits_T_4)
node _io_vcalloc_req_bits_T_7 = or(_io_vcalloc_req_bits_T_6, _io_vcalloc_req_bits_T_5)
wire _io_vcalloc_req_bits_WIRE_3 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_7
connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3
node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_11 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9)
node _io_vcalloc_req_bits_T_12 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_10)
wire _io_vcalloc_req_bits_WIRE_4 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_12
connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4
node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_13, _io_vcalloc_req_bits_T_14)
node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_15)
wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_17
connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5
connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2
wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>[3]
node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_19)
node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_20)
wire _io_vcalloc_req_bits_WIRE_7 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_22
connect _io_vcalloc_req_bits_WIRE_6[0], _io_vcalloc_req_bits_WIRE_7
node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24)
node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_25)
wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_27
connect _io_vcalloc_req_bits_WIRE_6[1], _io_vcalloc_req_bits_WIRE_8
node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_28, _io_vcalloc_req_bits_T_29)
node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_30)
wire _io_vcalloc_req_bits_WIRE_9 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_32
connect _io_vcalloc_req_bits_WIRE_6[2], _io_vcalloc_req_bits_WIRE_9
connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_6
wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>[3]
node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_34)
node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_35)
wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_37
connect _io_vcalloc_req_bits_WIRE_10[0], _io_vcalloc_req_bits_WIRE_11
node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_41 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39)
node _io_vcalloc_req_bits_T_42 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_40)
wire _io_vcalloc_req_bits_WIRE_12 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_42
connect _io_vcalloc_req_bits_WIRE_10[1], _io_vcalloc_req_bits_WIRE_12
node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_43, _io_vcalloc_req_bits_T_44)
node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_45)
wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_47
connect _io_vcalloc_req_bits_WIRE_10[2], _io_vcalloc_req_bits_WIRE_13
connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_10
wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>[1]
node _io_vcalloc_req_bits_T_48 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_49 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_49)
node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_50)
wire _io_vcalloc_req_bits_WIRE_15 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_52
connect _io_vcalloc_req_bits_WIRE_14[0], _io_vcalloc_req_bits_WIRE_15
connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_14
connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1
node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_56 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54)
node _io_vcalloc_req_bits_T_57 = or(_io_vcalloc_req_bits_T_56, _io_vcalloc_req_bits_T_55)
wire _io_vcalloc_req_bits_WIRE_16 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_57
connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_16
wire _io_vcalloc_req_bits_WIRE_17 : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_59)
node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_60)
wire _io_vcalloc_req_bits_WIRE_18 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_62
connect _io_vcalloc_req_bits_WIRE_17.egress_node_id, _io_vcalloc_req_bits_WIRE_18
node _io_vcalloc_req_bits_T_63 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_64 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_65 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_64)
node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_65)
wire _io_vcalloc_req_bits_WIRE_19 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_67
connect _io_vcalloc_req_bits_WIRE_17.egress_node, _io_vcalloc_req_bits_WIRE_19
node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_71 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69)
node _io_vcalloc_req_bits_T_72 = or(_io_vcalloc_req_bits_T_71, _io_vcalloc_req_bits_T_70)
wire _io_vcalloc_req_bits_WIRE_20 : UInt<3>
connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_72
connect _io_vcalloc_req_bits_WIRE_17.ingress_node_id, _io_vcalloc_req_bits_WIRE_20
node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_73, _io_vcalloc_req_bits_T_74)
node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_75)
wire _io_vcalloc_req_bits_WIRE_21 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_77
connect _io_vcalloc_req_bits_WIRE_17.ingress_node, _io_vcalloc_req_bits_WIRE_21
node _io_vcalloc_req_bits_T_78 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_79 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_80 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_79)
node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_80)
wire _io_vcalloc_req_bits_WIRE_22 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_82
connect _io_vcalloc_req_bits_WIRE_17.vnet_id, _io_vcalloc_req_bits_WIRE_22
connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_17
connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE
connect vcalloc_vals[0], UInt<1>(0h0)
invalidate vcalloc_reqs[0].vc_sel.`0`[0]
invalidate vcalloc_reqs[0].vc_sel.`0`[1]
invalidate vcalloc_reqs[0].vc_sel.`0`[2]
invalidate vcalloc_reqs[0].vc_sel.`1`[0]
invalidate vcalloc_reqs[0].vc_sel.`1`[1]
invalidate vcalloc_reqs[0].vc_sel.`1`[2]
invalidate vcalloc_reqs[0].vc_sel.`2`[0]
invalidate vcalloc_reqs[0].vc_sel.`2`[1]
invalidate vcalloc_reqs[0].vc_sel.`2`[2]
invalidate vcalloc_reqs[0].vc_sel.`3`[0]
invalidate vcalloc_reqs[0].in_vc
invalidate vcalloc_reqs[0].flow.egress_node_id
invalidate vcalloc_reqs[0].flow.egress_node
invalidate vcalloc_reqs[0].flow.ingress_node_id
invalidate vcalloc_reqs[0].flow.ingress_node
invalidate vcalloc_reqs[0].flow.vnet_id
connect vcalloc_vals[1], UInt<1>(0h0)
invalidate vcalloc_reqs[1].vc_sel.`0`[0]
invalidate vcalloc_reqs[1].vc_sel.`0`[1]
invalidate vcalloc_reqs[1].vc_sel.`0`[2]
invalidate vcalloc_reqs[1].vc_sel.`1`[0]
invalidate vcalloc_reqs[1].vc_sel.`1`[1]
invalidate vcalloc_reqs[1].vc_sel.`1`[2]
invalidate vcalloc_reqs[1].vc_sel.`2`[0]
invalidate vcalloc_reqs[1].vc_sel.`2`[1]
invalidate vcalloc_reqs[1].vc_sel.`2`[2]
invalidate vcalloc_reqs[1].vc_sel.`3`[0]
invalidate vcalloc_reqs[1].in_vc
invalidate vcalloc_reqs[1].flow.egress_node_id
invalidate vcalloc_reqs[1].flow.egress_node
invalidate vcalloc_reqs[1].flow.ingress_node_id
invalidate vcalloc_reqs[1].flow.ingress_node
invalidate vcalloc_reqs[1].flow.vnet_id
node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2))
node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1)
connect vcalloc_vals[2], _vcalloc_vals_2_T_2
connect vcalloc_reqs[2].in_vc, UInt<2>(0h2)
connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0`
connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1`
connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2`
connect vcalloc_reqs[2].vc_sel.`3`, states[2].vc_sel.`3`
connect vcalloc_reqs[2].flow, states[2].flow
node _T_22 = bits(vcalloc_sel, 2, 2)
node _T_23 = and(vcalloc_vals[2], _T_22)
node _T_24 = and(_T_23, io.vcalloc_req.ready)
when _T_24 :
connect states[2].g, UInt<3>(0h3)
node _T_25 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid)
when _T_25 :
connect vcalloc_vals[2], UInt<1>(0h1)
connect vcalloc_reqs[2].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect vcalloc_reqs[2].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect vcalloc_reqs[2].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect vcalloc_reqs[2].vc_sel.`3`, io.router_resp.vc_sel.`3`
node _io_debug_va_stall_T = add(vcalloc_vals[1], vcalloc_vals[2])
node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0)
node _io_debug_va_stall_T_2 = add(vcalloc_vals[0], _io_debug_va_stall_T_1)
node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0)
node _io_debug_va_stall_T_4 = sub(_io_debug_va_stall_T_3, io.vcalloc_req.ready)
node _io_debug_va_stall_T_5 = tail(_io_debug_va_stall_T_4, 1)
connect io.debug.va_stall, _io_debug_va_stall_T_5
node _T_26 = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
when _T_26 :
node _T_27 = bits(vcalloc_sel, 0, 0)
when _T_27 :
connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[0].g, UInt<3>(0h3)
node _T_28 = bits(vcalloc_sel, 1, 1)
when _T_28 :
connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[1].g, UInt<3>(0h3)
node _T_29 = bits(vcalloc_sel, 2, 2)
when _T_29 :
connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[2].g, UInt<3>(0h3)
inst salloc_arb of SwitchArbiter_63
connect salloc_arb.clock, clock
connect salloc_arb.reset, reset
connect salloc_arb.io.in[0].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[0].bits.tail
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[1]
invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[2]
invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[0]
connect salloc_arb.io.in[1].valid, UInt<1>(0h0)
invalidate salloc_arb.io.in[1].bits.tail
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`0`[2]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`1`[2]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[0]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[1]
invalidate salloc_arb.io.in[1].bits.vc_sel.`2`[2]
invalidate salloc_arb.io.in[1].bits.vc_sel.`3`[0]
node credit_available_hi = cat(states[2].vc_sel.`0`[2], states[2].vc_sel.`0`[1])
node _credit_available_T = cat(credit_available_hi, states[2].vc_sel.`0`[0])
node credit_available_hi_1 = cat(states[2].vc_sel.`1`[2], states[2].vc_sel.`1`[1])
node _credit_available_T_1 = cat(credit_available_hi_1, states[2].vc_sel.`1`[0])
node credit_available_hi_2 = cat(states[2].vc_sel.`2`[2], states[2].vc_sel.`2`[1])
node _credit_available_T_2 = cat(credit_available_hi_2, states[2].vc_sel.`2`[0])
node credit_available_lo = cat(_credit_available_T_1, _credit_available_T)
node credit_available_hi_3 = cat(states[2].vc_sel.`3`[0], _credit_available_T_2)
node _credit_available_T_3 = cat(credit_available_hi_3, credit_available_lo)
node credit_available_hi_4 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1])
node _credit_available_T_4 = cat(credit_available_hi_4, io.out_credit_available.`0`[0])
node credit_available_hi_5 = cat(io.out_credit_available.`1`[2], io.out_credit_available.`1`[1])
node _credit_available_T_5 = cat(credit_available_hi_5, io.out_credit_available.`1`[0])
node credit_available_hi_6 = cat(io.out_credit_available.`2`[2], io.out_credit_available.`2`[1])
node _credit_available_T_6 = cat(credit_available_hi_6, io.out_credit_available.`2`[0])
node credit_available_lo_1 = cat(_credit_available_T_5, _credit_available_T_4)
node credit_available_hi_7 = cat(io.out_credit_available.`3`[0], _credit_available_T_6)
node _credit_available_T_7 = cat(credit_available_hi_7, credit_available_lo_1)
node _credit_available_T_8 = and(_credit_available_T_3, _credit_available_T_7)
node credit_available = neq(_credit_available_T_8, UInt<1>(0h0))
node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3))
node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available)
node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid)
connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2
connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[1], states[2].vc_sel.`1`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`1`[2], states[2].vc_sel.`1`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[1], states[2].vc_sel.`2`[1]
connect salloc_arb.io.in[2].bits.vc_sel.`2`[2], states[2].vc_sel.`2`[2]
connect salloc_arb.io.in[2].bits.vc_sel.`3`[0], states[2].vc_sel.`3`[0]
connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail
node _T_30 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid)
node _T_31 = and(_T_30, input_buffer.io.deq[2].bits.tail)
when _T_31 :
connect states[2].g, UInt<3>(0h0)
connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready
node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T)
node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2)
node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4)
node _io_debug_sa_stall_T_6 = add(_io_debug_sa_stall_T_3, _io_debug_sa_stall_T_5)
node _io_debug_sa_stall_T_7 = bits(_io_debug_sa_stall_T_6, 1, 0)
node _io_debug_sa_stall_T_8 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_7)
node _io_debug_sa_stall_T_9 = bits(_io_debug_sa_stall_T_8, 1, 0)
connect io.debug.sa_stall, _io_debug_sa_stall_T_9
connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits
connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid
connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready
when io.block :
connect salloc_arb.io.out[0].ready, UInt<1>(0h0)
connect io.salloc_req[0].valid, UInt<1>(0h0)
wire salloc_outs : { valid : UInt<1>, vid : UInt<2>, out_vid : UInt<2>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1]
node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.credit_return, _io_in_credit_return_T_1
node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _io_in_vc_free_T_4 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_5 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_6 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_7 = or(_io_in_vc_free_T_4, _io_in_vc_free_T_5)
node _io_in_vc_free_T_8 = or(_io_in_vc_free_T_7, _io_in_vc_free_T_6)
wire _io_in_vc_free_WIRE : UInt<1>
connect _io_in_vc_free_WIRE, _io_in_vc_free_T_8
node _io_in_vc_free_T_9 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE)
node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_9, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.vc_free, _io_in_vc_free_T_10
node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
connect salloc_outs[0].valid, _salloc_outs_0_valid_T
node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 1, 0)
node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi)
node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo)
node _salloc_outs_0_vid_T_2 = bits(_salloc_outs_0_vid_T_1, 1, 1)
node _salloc_outs_0_vid_T_3 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_2)
connect salloc_outs[0].vid, _salloc_outs_0_vid_T_3
node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
wire vc_sel : { `3` : UInt<1>[1], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}
wire _vc_sel_WIRE : UInt<1>[3]
node _vc_sel_T_3 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_4 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_5 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_6 = or(_vc_sel_T_3, _vc_sel_T_4)
node _vc_sel_T_7 = or(_vc_sel_T_6, _vc_sel_T_5)
wire _vc_sel_WIRE_1 : UInt<1>
connect _vc_sel_WIRE_1, _vc_sel_T_7
connect _vc_sel_WIRE[0], _vc_sel_WIRE_1
node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_11 = or(_vc_sel_T_8, _vc_sel_T_9)
node _vc_sel_T_12 = or(_vc_sel_T_11, _vc_sel_T_10)
wire _vc_sel_WIRE_2 : UInt<1>
connect _vc_sel_WIRE_2, _vc_sel_T_12
connect _vc_sel_WIRE[1], _vc_sel_WIRE_2
node _vc_sel_T_13 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_14 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_15 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0))
node _vc_sel_T_16 = or(_vc_sel_T_13, _vc_sel_T_14)
node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_15)
wire _vc_sel_WIRE_3 : UInt<1>
connect _vc_sel_WIRE_3, _vc_sel_T_17
connect _vc_sel_WIRE[2], _vc_sel_WIRE_3
connect vc_sel.`0`, _vc_sel_WIRE
wire _vc_sel_WIRE_4 : UInt<1>[3]
node _vc_sel_T_18 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_19 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_20 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_21 = or(_vc_sel_T_18, _vc_sel_T_19)
node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_20)
wire _vc_sel_WIRE_5 : UInt<1>
connect _vc_sel_WIRE_5, _vc_sel_T_22
connect _vc_sel_WIRE_4[0], _vc_sel_WIRE_5
node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_26 = or(_vc_sel_T_23, _vc_sel_T_24)
node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_25)
wire _vc_sel_WIRE_6 : UInt<1>
connect _vc_sel_WIRE_6, _vc_sel_T_27
connect _vc_sel_WIRE_4[1], _vc_sel_WIRE_6
node _vc_sel_T_28 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_29 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_30 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0))
node _vc_sel_T_31 = or(_vc_sel_T_28, _vc_sel_T_29)
node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_30)
wire _vc_sel_WIRE_7 : UInt<1>
connect _vc_sel_WIRE_7, _vc_sel_T_32
connect _vc_sel_WIRE_4[2], _vc_sel_WIRE_7
connect vc_sel.`1`, _vc_sel_WIRE_4
wire _vc_sel_WIRE_8 : UInt<1>[3]
node _vc_sel_T_33 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_34 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_35 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_36 = or(_vc_sel_T_33, _vc_sel_T_34)
node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_35)
wire _vc_sel_WIRE_9 : UInt<1>
connect _vc_sel_WIRE_9, _vc_sel_T_37
connect _vc_sel_WIRE_8[0], _vc_sel_WIRE_9
node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_41 = or(_vc_sel_T_38, _vc_sel_T_39)
node _vc_sel_T_42 = or(_vc_sel_T_41, _vc_sel_T_40)
wire _vc_sel_WIRE_10 : UInt<1>
connect _vc_sel_WIRE_10, _vc_sel_T_42
connect _vc_sel_WIRE_8[1], _vc_sel_WIRE_10
node _vc_sel_T_43 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_44 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_45 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0))
node _vc_sel_T_46 = or(_vc_sel_T_43, _vc_sel_T_44)
node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_45)
wire _vc_sel_WIRE_11 : UInt<1>
connect _vc_sel_WIRE_11, _vc_sel_T_47
connect _vc_sel_WIRE_8[2], _vc_sel_WIRE_11
connect vc_sel.`2`, _vc_sel_WIRE_8
wire _vc_sel_WIRE_12 : UInt<1>[1]
node _vc_sel_T_48 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_49 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_50 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_51 = or(_vc_sel_T_48, _vc_sel_T_49)
node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_50)
wire _vc_sel_WIRE_13 : UInt<1>
connect _vc_sel_WIRE_13, _vc_sel_T_52
connect _vc_sel_WIRE_12[0], _vc_sel_WIRE_13
connect vc_sel.`3`, _vc_sel_WIRE_12
node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1])
node channel_oh_0 = or(_channel_oh_T, vc_sel.`0`[2])
node _channel_oh_T_1 = or(vc_sel.`1`[0], vc_sel.`1`[1])
node channel_oh_1 = or(_channel_oh_T_1, vc_sel.`1`[2])
node _channel_oh_T_2 = or(vc_sel.`2`[0], vc_sel.`2`[1])
node channel_oh_2 = or(_channel_oh_T_2, vc_sel.`2`[2])
node virt_channel_hi = cat(vc_sel.`0`[2], vc_sel.`0`[1])
node _virt_channel_T = cat(virt_channel_hi, vc_sel.`0`[0])
node virt_channel_hi_1 = bits(_virt_channel_T, 2, 2)
node virt_channel_lo = bits(_virt_channel_T, 1, 0)
node _virt_channel_T_1 = orr(virt_channel_hi_1)
node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo)
node _virt_channel_T_3 = bits(_virt_channel_T_2, 1, 1)
node _virt_channel_T_4 = cat(_virt_channel_T_1, _virt_channel_T_3)
node virt_channel_hi_2 = cat(vc_sel.`1`[2], vc_sel.`1`[1])
node _virt_channel_T_5 = cat(virt_channel_hi_2, vc_sel.`1`[0])
node virt_channel_hi_3 = bits(_virt_channel_T_5, 2, 2)
node virt_channel_lo_1 = bits(_virt_channel_T_5, 1, 0)
node _virt_channel_T_6 = orr(virt_channel_hi_3)
node _virt_channel_T_7 = or(virt_channel_hi_3, virt_channel_lo_1)
node _virt_channel_T_8 = bits(_virt_channel_T_7, 1, 1)
node _virt_channel_T_9 = cat(_virt_channel_T_6, _virt_channel_T_8)
node virt_channel_hi_4 = cat(vc_sel.`2`[2], vc_sel.`2`[1])
node _virt_channel_T_10 = cat(virt_channel_hi_4, vc_sel.`2`[0])
node virt_channel_hi_5 = bits(_virt_channel_T_10, 2, 2)
node virt_channel_lo_2 = bits(_virt_channel_T_10, 1, 0)
node _virt_channel_T_11 = orr(virt_channel_hi_5)
node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_2)
node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1)
node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13)
node _virt_channel_T_15 = mux(channel_oh_0, _virt_channel_T_4, UInt<1>(0h0))
node _virt_channel_T_16 = mux(channel_oh_1, _virt_channel_T_9, UInt<1>(0h0))
node _virt_channel_T_17 = mux(channel_oh_2, _virt_channel_T_14, UInt<1>(0h0))
node _virt_channel_T_18 = mux(vc_sel.`3`[0], UInt<1>(0h0), UInt<1>(0h0))
node _virt_channel_T_19 = or(_virt_channel_T_15, _virt_channel_T_16)
node _virt_channel_T_20 = or(_virt_channel_T_19, _virt_channel_T_17)
node _virt_channel_T_21 = or(_virt_channel_T_20, _virt_channel_T_18)
wire virt_channel : UInt<2>
connect virt_channel, _virt_channel_T_21
node _T_32 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
when _T_32 :
connect salloc_outs[0].out_vid, virt_channel
node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_payload_T_3 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_4 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_5 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_6 = or(_salloc_outs_0_flit_payload_T_3, _salloc_outs_0_flit_payload_T_4)
node _salloc_outs_0_flit_payload_T_7 = or(_salloc_outs_0_flit_payload_T_6, _salloc_outs_0_flit_payload_T_5)
wire _salloc_outs_0_flit_payload_WIRE : UInt<145>
connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_7
connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE
node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_head_T_3 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_4 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_5 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_6 = or(_salloc_outs_0_flit_head_T_3, _salloc_outs_0_flit_head_T_4)
node _salloc_outs_0_flit_head_T_7 = or(_salloc_outs_0_flit_head_T_6, _salloc_outs_0_flit_head_T_5)
wire _salloc_outs_0_flit_head_WIRE : UInt<1>
connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_7
connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE
node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
node _salloc_outs_0_flit_tail_T_3 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_4 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_5 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_6 = or(_salloc_outs_0_flit_tail_T_3, _salloc_outs_0_flit_tail_T_4)
node _salloc_outs_0_flit_tail_T_7 = or(_salloc_outs_0_flit_tail_T_6, _salloc_outs_0_flit_tail_T_5)
wire _salloc_outs_0_flit_tail_WIRE : UInt<1>
connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_7
connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE
node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2)
wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _salloc_outs_0_flit_flow_T_3 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_4 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_6 = or(_salloc_outs_0_flit_flow_T_3, _salloc_outs_0_flit_flow_T_4)
node _salloc_outs_0_flit_flow_T_7 = or(_salloc_outs_0_flit_flow_T_6, _salloc_outs_0_flit_flow_T_5)
wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_7
connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1
node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_11 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9)
node _salloc_outs_0_flit_flow_T_12 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_10)
wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4>
connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_12
connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2
node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_13, _salloc_outs_0_flit_flow_T_14)
node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_15)
wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<3>
connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_17
connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3
node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_20 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_19)
node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_20)
wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4>
connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_22
connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4
node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24)
node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_25)
wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_27
connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5
connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE
else :
invalidate salloc_outs[0].out_vid
invalidate salloc_outs[0].flit.virt_channel_id
invalidate salloc_outs[0].flit.flow.egress_node_id
invalidate salloc_outs[0].flit.flow.egress_node
invalidate salloc_outs[0].flit.flow.ingress_node_id
invalidate salloc_outs[0].flit.flow.ingress_node
invalidate salloc_outs[0].flit.flow.vnet_id
invalidate salloc_outs[0].flit.payload
invalidate salloc_outs[0].flit.tail
invalidate salloc_outs[0].flit.head
invalidate salloc_outs[0].flit.virt_channel_id
connect io.out[0].valid, salloc_outs[0].valid
connect io.out[0].bits.flit, salloc_outs[0].flit
connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid
invalidate states[0].fifo_deps
invalidate states[0].flow.egress_node_id
invalidate states[0].flow.egress_node
invalidate states[0].flow.ingress_node_id
invalidate states[0].flow.ingress_node
invalidate states[0].flow.vnet_id
invalidate states[0].vc_sel.`0`[0]
invalidate states[0].vc_sel.`0`[1]
invalidate states[0].vc_sel.`0`[2]
invalidate states[0].vc_sel.`1`[0]
invalidate states[0].vc_sel.`1`[1]
invalidate states[0].vc_sel.`1`[2]
invalidate states[0].vc_sel.`2`[0]
invalidate states[0].vc_sel.`2`[1]
invalidate states[0].vc_sel.`2`[2]
invalidate states[0].vc_sel.`3`[0]
invalidate states[0].g
invalidate states[1].fifo_deps
invalidate states[1].flow.egress_node_id
invalidate states[1].flow.egress_node
invalidate states[1].flow.ingress_node_id
invalidate states[1].flow.ingress_node
invalidate states[1].flow.vnet_id
invalidate states[1].vc_sel.`0`[0]
invalidate states[1].vc_sel.`0`[1]
invalidate states[1].vc_sel.`0`[2]
invalidate states[1].vc_sel.`1`[0]
invalidate states[1].vc_sel.`1`[1]
invalidate states[1].vc_sel.`1`[2]
invalidate states[1].vc_sel.`2`[0]
invalidate states[1].vc_sel.`2`[1]
invalidate states[1].vc_sel.`2`[2]
invalidate states[1].vc_sel.`3`[0]
invalidate states[1].g
connect states[2].vc_sel.`0`[0], UInt<1>(0h0)
connect states[2].vc_sel.`0`[1], UInt<1>(0h0)
connect states[2].vc_sel.`1`[0], UInt<1>(0h0)
connect states[2].vc_sel.`1`[1], UInt<1>(0h0)
connect states[2].vc_sel.`1`[2], UInt<1>(0h0)
connect states[2].vc_sel.`2`[0], UInt<1>(0h0)
connect states[2].vc_sel.`2`[1], UInt<1>(0h0)
connect states[2].vc_sel.`2`[2], UInt<1>(0h0)
node _T_33 = asUInt(reset)
when _T_33 :
connect states[0].g, UInt<3>(0h0)
connect states[1].g, UInt<3>(0h0)
connect states[2].g, UInt<3>(0h0) | module InputUnit_26( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output [1:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output [2:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_2, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_2, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_2, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_2, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [144:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output [1:0] io_debug_va_stall, // @[InputUnit.scala:170:14]
output [1:0] io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [144:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [2:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [2:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire _GEN; // @[MixedVec.scala:116:9]
wire vcalloc_reqs_2_vc_sel_0_2; // @[MixedVec.scala:116:9]
wire vcalloc_vals_2; // @[InputUnit.scala:266:25, :272:46, :273:29]
wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [2:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire [1:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [144:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [144:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28]
wire [144:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_2_g; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_3_0; // @[InputUnit.scala:192:19]
reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [2:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN_0 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire _GEN_1 = _route_arbiter_io_in_2_ready & route_arbiter_io_in_2_valid; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to this FIRRTL code module MulRecFN_34 :
output io : { flip a : UInt<33>, flip b : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
inst mulRawFN of MulRawFN_34
node mulRawFN_io_a_exp = bits(io.a, 31, 23)
node _mulRawFN_io_a_isZero_T = bits(mulRawFN_io_a_exp, 8, 6)
node mulRawFN_io_a_isZero = eq(_mulRawFN_io_a_isZero_T, UInt<1>(0h0))
node _mulRawFN_io_a_isSpecial_T = bits(mulRawFN_io_a_exp, 8, 7)
node mulRawFN_io_a_isSpecial = eq(_mulRawFN_io_a_isSpecial_T, UInt<2>(0h3))
wire mulRawFN_io_a_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _mulRawFN_io_a_out_isNaN_T = bits(mulRawFN_io_a_exp, 6, 6)
node _mulRawFN_io_a_out_isNaN_T_1 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isNaN_T)
connect mulRawFN_io_a_out.isNaN, _mulRawFN_io_a_out_isNaN_T_1
node _mulRawFN_io_a_out_isInf_T = bits(mulRawFN_io_a_exp, 6, 6)
node _mulRawFN_io_a_out_isInf_T_1 = eq(_mulRawFN_io_a_out_isInf_T, UInt<1>(0h0))
node _mulRawFN_io_a_out_isInf_T_2 = and(mulRawFN_io_a_isSpecial, _mulRawFN_io_a_out_isInf_T_1)
connect mulRawFN_io_a_out.isInf, _mulRawFN_io_a_out_isInf_T_2
connect mulRawFN_io_a_out.isZero, mulRawFN_io_a_isZero
node _mulRawFN_io_a_out_sign_T = bits(io.a, 32, 32)
connect mulRawFN_io_a_out.sign, _mulRawFN_io_a_out_sign_T
node _mulRawFN_io_a_out_sExp_T = cvt(mulRawFN_io_a_exp)
connect mulRawFN_io_a_out.sExp, _mulRawFN_io_a_out_sExp_T
node _mulRawFN_io_a_out_sig_T = eq(mulRawFN_io_a_isZero, UInt<1>(0h0))
node _mulRawFN_io_a_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_a_out_sig_T)
node _mulRawFN_io_a_out_sig_T_2 = bits(io.a, 22, 0)
node _mulRawFN_io_a_out_sig_T_3 = cat(_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2)
connect mulRawFN_io_a_out.sig, _mulRawFN_io_a_out_sig_T_3
connect mulRawFN.io.a.sig, mulRawFN_io_a_out.sig
connect mulRawFN.io.a.sExp, mulRawFN_io_a_out.sExp
connect mulRawFN.io.a.sign, mulRawFN_io_a_out.sign
connect mulRawFN.io.a.isZero, mulRawFN_io_a_out.isZero
connect mulRawFN.io.a.isInf, mulRawFN_io_a_out.isInf
connect mulRawFN.io.a.isNaN, mulRawFN_io_a_out.isNaN
node mulRawFN_io_b_exp = bits(io.b, 31, 23)
node _mulRawFN_io_b_isZero_T = bits(mulRawFN_io_b_exp, 8, 6)
node mulRawFN_io_b_isZero = eq(_mulRawFN_io_b_isZero_T, UInt<1>(0h0))
node _mulRawFN_io_b_isSpecial_T = bits(mulRawFN_io_b_exp, 8, 7)
node mulRawFN_io_b_isSpecial = eq(_mulRawFN_io_b_isSpecial_T, UInt<2>(0h3))
wire mulRawFN_io_b_out : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _mulRawFN_io_b_out_isNaN_T = bits(mulRawFN_io_b_exp, 6, 6)
node _mulRawFN_io_b_out_isNaN_T_1 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isNaN_T)
connect mulRawFN_io_b_out.isNaN, _mulRawFN_io_b_out_isNaN_T_1
node _mulRawFN_io_b_out_isInf_T = bits(mulRawFN_io_b_exp, 6, 6)
node _mulRawFN_io_b_out_isInf_T_1 = eq(_mulRawFN_io_b_out_isInf_T, UInt<1>(0h0))
node _mulRawFN_io_b_out_isInf_T_2 = and(mulRawFN_io_b_isSpecial, _mulRawFN_io_b_out_isInf_T_1)
connect mulRawFN_io_b_out.isInf, _mulRawFN_io_b_out_isInf_T_2
connect mulRawFN_io_b_out.isZero, mulRawFN_io_b_isZero
node _mulRawFN_io_b_out_sign_T = bits(io.b, 32, 32)
connect mulRawFN_io_b_out.sign, _mulRawFN_io_b_out_sign_T
node _mulRawFN_io_b_out_sExp_T = cvt(mulRawFN_io_b_exp)
connect mulRawFN_io_b_out.sExp, _mulRawFN_io_b_out_sExp_T
node _mulRawFN_io_b_out_sig_T = eq(mulRawFN_io_b_isZero, UInt<1>(0h0))
node _mulRawFN_io_b_out_sig_T_1 = cat(UInt<1>(0h0), _mulRawFN_io_b_out_sig_T)
node _mulRawFN_io_b_out_sig_T_2 = bits(io.b, 22, 0)
node _mulRawFN_io_b_out_sig_T_3 = cat(_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2)
connect mulRawFN_io_b_out.sig, _mulRawFN_io_b_out_sig_T_3
connect mulRawFN.io.b.sig, mulRawFN_io_b_out.sig
connect mulRawFN.io.b.sExp, mulRawFN_io_b_out.sExp
connect mulRawFN.io.b.sign, mulRawFN_io_b_out.sign
connect mulRawFN.io.b.isZero, mulRawFN_io_b_out.isZero
connect mulRawFN.io.b.isInf, mulRawFN_io_b_out.isInf
connect mulRawFN.io.b.isNaN, mulRawFN_io_b_out.isNaN
inst roundRawFNToRecFN of RoundRawFNToRecFN_e8_s24_104
connect roundRawFNToRecFN.io.invalidExc, mulRawFN.io.invalidExc
connect roundRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundRawFNToRecFN.io.in.sig, mulRawFN.io.rawOut.sig
connect roundRawFNToRecFN.io.in.sExp, mulRawFN.io.rawOut.sExp
connect roundRawFNToRecFN.io.in.sign, mulRawFN.io.rawOut.sign
connect roundRawFNToRecFN.io.in.isZero, mulRawFN.io.rawOut.isZero
connect roundRawFNToRecFN.io.in.isInf, mulRawFN.io.rawOut.isInf
connect roundRawFNToRecFN.io.in.isNaN, mulRawFN.io.rawOut.isNaN
connect roundRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundRawFNToRecFN.io.out
connect io.exceptionFlags, roundRawFNToRecFN.io.exceptionFlags | module MulRecFN_34( // @[MulRecFN.scala:100:7]
input [32:0] io_a, // @[MulRecFN.scala:102:16]
input [32:0] io_b, // @[MulRecFN.scala:102:16]
output [32:0] io_out // @[MulRecFN.scala:102:16]
);
wire _mulRawFN_io_invalidExc; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_isNaN; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_isInf; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_isZero; // @[MulRecFN.scala:113:26]
wire _mulRawFN_io_rawOut_sign; // @[MulRecFN.scala:113:26]
wire [9:0] _mulRawFN_io_rawOut_sExp; // @[MulRecFN.scala:113:26]
wire [26:0] _mulRawFN_io_rawOut_sig; // @[MulRecFN.scala:113:26]
wire [32:0] io_a_0 = io_a; // @[MulRecFN.scala:100:7]
wire [32:0] io_b_0 = io_b; // @[MulRecFN.scala:100:7]
wire io_detectTininess = 1'h1; // @[MulRecFN.scala:100:7, :102:16, :121:15]
wire [2:0] io_roundingMode = 3'h0; // @[MulRecFN.scala:100:7, :102:16, :121:15]
wire [32:0] io_out_0; // @[MulRecFN.scala:100:7]
wire [4:0] io_exceptionFlags; // @[MulRecFN.scala:100:7]
wire [8:0] mulRawFN_io_a_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _mulRawFN_io_a_isZero_T = mulRawFN_io_a_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire mulRawFN_io_a_isZero = _mulRawFN_io_a_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire mulRawFN_io_a_out_isZero = mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _mulRawFN_io_a_isSpecial_T = mulRawFN_io_a_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire mulRawFN_io_a_isSpecial = &_mulRawFN_io_a_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire mulRawFN_io_a_out_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_a_out_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_a_out_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] mulRawFN_io_a_out_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] mulRawFN_io_a_out_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _mulRawFN_io_a_out_isNaN_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _mulRawFN_io_a_out_isInf_T = mulRawFN_io_a_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _mulRawFN_io_a_out_isNaN_T_1 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign mulRawFN_io_a_out_isNaN = _mulRawFN_io_a_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _mulRawFN_io_a_out_isInf_T_1 = ~_mulRawFN_io_a_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _mulRawFN_io_a_out_isInf_T_2 = mulRawFN_io_a_isSpecial & _mulRawFN_io_a_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign mulRawFN_io_a_out_isInf = _mulRawFN_io_a_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _mulRawFN_io_a_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign mulRawFN_io_a_out_sign = _mulRawFN_io_a_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _mulRawFN_io_a_out_sExp_T = {1'h0, mulRawFN_io_a_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign mulRawFN_io_a_out_sExp = _mulRawFN_io_a_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _mulRawFN_io_a_out_sig_T = ~mulRawFN_io_a_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _mulRawFN_io_a_out_sig_T_1 = {1'h0, _mulRawFN_io_a_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _mulRawFN_io_a_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _mulRawFN_io_a_out_sig_T_3 = {_mulRawFN_io_a_out_sig_T_1, _mulRawFN_io_a_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign mulRawFN_io_a_out_sig = _mulRawFN_io_a_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire [8:0] mulRawFN_io_b_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _mulRawFN_io_b_isZero_T = mulRawFN_io_b_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire mulRawFN_io_b_isZero = _mulRawFN_io_b_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire mulRawFN_io_b_out_isZero = mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _mulRawFN_io_b_isSpecial_T = mulRawFN_io_b_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire mulRawFN_io_b_isSpecial = &_mulRawFN_io_b_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire mulRawFN_io_b_out_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_b_out_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire mulRawFN_io_b_out_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] mulRawFN_io_b_out_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] mulRawFN_io_b_out_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _mulRawFN_io_b_out_isNaN_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _mulRawFN_io_b_out_isInf_T = mulRawFN_io_b_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _mulRawFN_io_b_out_isNaN_T_1 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign mulRawFN_io_b_out_isNaN = _mulRawFN_io_b_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _mulRawFN_io_b_out_isInf_T_1 = ~_mulRawFN_io_b_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _mulRawFN_io_b_out_isInf_T_2 = mulRawFN_io_b_isSpecial & _mulRawFN_io_b_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign mulRawFN_io_b_out_isInf = _mulRawFN_io_b_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _mulRawFN_io_b_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign mulRawFN_io_b_out_sign = _mulRawFN_io_b_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _mulRawFN_io_b_out_sExp_T = {1'h0, mulRawFN_io_b_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign mulRawFN_io_b_out_sExp = _mulRawFN_io_b_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _mulRawFN_io_b_out_sig_T = ~mulRawFN_io_b_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _mulRawFN_io_b_out_sig_T_1 = {1'h0, _mulRawFN_io_b_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _mulRawFN_io_b_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _mulRawFN_io_b_out_sig_T_3 = {_mulRawFN_io_b_out_sig_T_1, _mulRawFN_io_b_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign mulRawFN_io_b_out_sig = _mulRawFN_io_b_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
MulRawFN_34 mulRawFN ( // @[MulRecFN.scala:113:26]
.io_a_isNaN (mulRawFN_io_a_out_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_a_isInf (mulRawFN_io_a_out_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_a_isZero (mulRawFN_io_a_out_isZero), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sign (mulRawFN_io_a_out_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sExp (mulRawFN_io_a_out_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_a_sig (mulRawFN_io_a_out_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isNaN (mulRawFN_io_b_out_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isInf (mulRawFN_io_b_out_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_b_isZero (mulRawFN_io_b_out_isZero), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sign (mulRawFN_io_b_out_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sExp (mulRawFN_io_b_out_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_b_sig (mulRawFN_io_b_out_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_invalidExc (_mulRawFN_io_invalidExc),
.io_rawOut_isNaN (_mulRawFN_io_rawOut_isNaN),
.io_rawOut_isInf (_mulRawFN_io_rawOut_isInf),
.io_rawOut_isZero (_mulRawFN_io_rawOut_isZero),
.io_rawOut_sign (_mulRawFN_io_rawOut_sign),
.io_rawOut_sExp (_mulRawFN_io_rawOut_sExp),
.io_rawOut_sig (_mulRawFN_io_rawOut_sig)
); // @[MulRecFN.scala:113:26]
RoundRawFNToRecFN_e8_s24_104 roundRawFNToRecFN ( // @[MulRecFN.scala:121:15]
.io_invalidExc (_mulRawFN_io_invalidExc), // @[MulRecFN.scala:113:26]
.io_in_isNaN (_mulRawFN_io_rawOut_isNaN), // @[MulRecFN.scala:113:26]
.io_in_isInf (_mulRawFN_io_rawOut_isInf), // @[MulRecFN.scala:113:26]
.io_in_isZero (_mulRawFN_io_rawOut_isZero), // @[MulRecFN.scala:113:26]
.io_in_sign (_mulRawFN_io_rawOut_sign), // @[MulRecFN.scala:113:26]
.io_in_sExp (_mulRawFN_io_rawOut_sExp), // @[MulRecFN.scala:113:26]
.io_in_sig (_mulRawFN_io_rawOut_sig), // @[MulRecFN.scala:113:26]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[MulRecFN.scala:121:15]
assign io_out = io_out_0; // @[MulRecFN.scala:100:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e8_s24_68 :
output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<49>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}}
node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2))
node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags)
node _sigSum_T = bits(io.mulAddResult, 48, 48)
node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1))
node _sigSum_T_2 = tail(_sigSum_T_1, 1)
node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC)
node _sigSum_T_4 = bits(io.mulAddResult, 47, 0)
node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4)
node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC)
node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags)
node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T)
node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1)
node CDom_sExp = asSInt(_CDom_sExp_T_2)
node _CDom_absSigSum_T = bits(sigSum, 74, 25)
node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T)
node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 25, 24)
node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2)
node _CDom_absSigSum_T_4 = bits(sigSum, 72, 26)
node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4)
node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5)
node _CDom_absSigSumExtra_T = bits(sigSum, 24, 1)
node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T)
node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1)
node _CDom_absSigSumExtra_T_3 = bits(sigSum, 25, 1)
node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3)
node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4)
node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist)
node CDom_mainSig = bits(_CDom_mainSig_T, 49, 21)
node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 23, 0)
node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 3)
wire CDom_reduced4SigExtra_reducedVec : UInt<1>[7]
node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0)
node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T)
connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1
node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4)
node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T)
connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1
node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8)
node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T)
connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1
node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12)
node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T)
connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1
node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16)
node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T)
connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1
node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20)
node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T)
connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1
node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 26, 24)
node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T)
connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1
node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1])
node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec[0])
node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3])
node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5])
node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo)
node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo)
node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2)
node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3)
node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<9>(0h100)), _CDom_reduced4SigExtra_T_4)
node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 6, 1)
node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 3, 0)
node _CDom_reduced4SigExtra_T_7 = bits(_CDom_reduced4SigExtra_T_6, 1, 0)
node _CDom_reduced4SigExtra_T_8 = bits(_CDom_reduced4SigExtra_T_7, 0, 0)
node _CDom_reduced4SigExtra_T_9 = bits(_CDom_reduced4SigExtra_T_7, 1, 1)
node _CDom_reduced4SigExtra_T_10 = cat(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9)
node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 2)
node _CDom_reduced4SigExtra_T_12 = bits(_CDom_reduced4SigExtra_T_11, 0, 0)
node _CDom_reduced4SigExtra_T_13 = bits(_CDom_reduced4SigExtra_T_11, 1, 1)
node _CDom_reduced4SigExtra_T_14 = cat(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13)
node _CDom_reduced4SigExtra_T_15 = cat(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14)
node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_5, 5, 4)
node _CDom_reduced4SigExtra_T_17 = bits(_CDom_reduced4SigExtra_T_16, 0, 0)
node _CDom_reduced4SigExtra_T_18 = bits(_CDom_reduced4SigExtra_T_16, 1, 1)
node _CDom_reduced4SigExtra_T_19 = cat(_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18)
node _CDom_reduced4SigExtra_T_20 = cat(_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19)
node _CDom_reduced4SigExtra_T_21 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_20)
node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_21)
node _CDom_sig_T = shr(CDom_mainSig, 3)
node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0)
node _CDom_sig_T_2 = orr(_CDom_sig_T_1)
node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra)
node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra)
node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4)
node notCDom_signSigSum = bits(sigSum, 51, 51)
node _notCDom_absSigSum_T = bits(sigSum, 50, 0)
node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T)
node _notCDom_absSigSum_T_2 = bits(sigSum, 50, 0)
node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags)
node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1)
node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4)
wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[26]
node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0)
node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T)
connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2)
node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T)
connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4)
node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T)
connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6)
node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T)
connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8)
node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T)
connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10)
node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T)
connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12)
node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T)
connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14)
node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T)
connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16)
node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T)
connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18)
node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T)
connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20)
node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T)
connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22)
node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T)
connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24)
node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T)
connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26)
node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T)
connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28)
node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T)
connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30)
node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T)
connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32)
node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T)
connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34)
node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T)
connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36)
node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T)
connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38)
node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T)
connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40)
node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T)
connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42)
node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T)
connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44)
node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T)
connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46)
node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T)
connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48)
node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T)
connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1
node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 50, 50)
node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T)
connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1
node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1])
node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0])
node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4])
node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3])
node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo)
node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7])
node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6])
node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9])
node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11])
node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo)
node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo)
node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo)
node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14])
node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13])
node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[18], notCDom_reduced2AbsSigSum_reducedVec[17])
node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[16])
node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo)
node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[21], notCDom_reduced2AbsSigSum_reducedVec[20])
node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[19])
node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[23], notCDom_reduced2AbsSigSum_reducedVec[22])
node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[25], notCDom_reduced2AbsSigSum_reducedVec[24])
node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo)
node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo)
node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo)
node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo)
node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0)
node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1)
node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2)
node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3)
node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4)
node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5)
node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6)
node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7)
node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8)
node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9)
node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10)
node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11)
node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12)
node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13)
node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14)
node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15)
node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16)
node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17)
node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18)
node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19)
node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20)
node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21)
node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22)
node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23)
node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24)
node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25)
node _notCDom_normDistReduced2_T_26 = mux(_notCDom_normDistReduced2_T_1, UInt<5>(0h18), UInt<5>(0h19))
node _notCDom_normDistReduced2_T_27 = mux(_notCDom_normDistReduced2_T_2, UInt<5>(0h17), _notCDom_normDistReduced2_T_26)
node _notCDom_normDistReduced2_T_28 = mux(_notCDom_normDistReduced2_T_3, UInt<5>(0h16), _notCDom_normDistReduced2_T_27)
node _notCDom_normDistReduced2_T_29 = mux(_notCDom_normDistReduced2_T_4, UInt<5>(0h15), _notCDom_normDistReduced2_T_28)
node _notCDom_normDistReduced2_T_30 = mux(_notCDom_normDistReduced2_T_5, UInt<5>(0h14), _notCDom_normDistReduced2_T_29)
node _notCDom_normDistReduced2_T_31 = mux(_notCDom_normDistReduced2_T_6, UInt<5>(0h13), _notCDom_normDistReduced2_T_30)
node _notCDom_normDistReduced2_T_32 = mux(_notCDom_normDistReduced2_T_7, UInt<5>(0h12), _notCDom_normDistReduced2_T_31)
node _notCDom_normDistReduced2_T_33 = mux(_notCDom_normDistReduced2_T_8, UInt<5>(0h11), _notCDom_normDistReduced2_T_32)
node _notCDom_normDistReduced2_T_34 = mux(_notCDom_normDistReduced2_T_9, UInt<5>(0h10), _notCDom_normDistReduced2_T_33)
node _notCDom_normDistReduced2_T_35 = mux(_notCDom_normDistReduced2_T_10, UInt<4>(0hf), _notCDom_normDistReduced2_T_34)
node _notCDom_normDistReduced2_T_36 = mux(_notCDom_normDistReduced2_T_11, UInt<4>(0he), _notCDom_normDistReduced2_T_35)
node _notCDom_normDistReduced2_T_37 = mux(_notCDom_normDistReduced2_T_12, UInt<4>(0hd), _notCDom_normDistReduced2_T_36)
node _notCDom_normDistReduced2_T_38 = mux(_notCDom_normDistReduced2_T_13, UInt<4>(0hc), _notCDom_normDistReduced2_T_37)
node _notCDom_normDistReduced2_T_39 = mux(_notCDom_normDistReduced2_T_14, UInt<4>(0hb), _notCDom_normDistReduced2_T_38)
node _notCDom_normDistReduced2_T_40 = mux(_notCDom_normDistReduced2_T_15, UInt<4>(0ha), _notCDom_normDistReduced2_T_39)
node _notCDom_normDistReduced2_T_41 = mux(_notCDom_normDistReduced2_T_16, UInt<4>(0h9), _notCDom_normDistReduced2_T_40)
node _notCDom_normDistReduced2_T_42 = mux(_notCDom_normDistReduced2_T_17, UInt<4>(0h8), _notCDom_normDistReduced2_T_41)
node _notCDom_normDistReduced2_T_43 = mux(_notCDom_normDistReduced2_T_18, UInt<3>(0h7), _notCDom_normDistReduced2_T_42)
node _notCDom_normDistReduced2_T_44 = mux(_notCDom_normDistReduced2_T_19, UInt<3>(0h6), _notCDom_normDistReduced2_T_43)
node _notCDom_normDistReduced2_T_45 = mux(_notCDom_normDistReduced2_T_20, UInt<3>(0h5), _notCDom_normDistReduced2_T_44)
node _notCDom_normDistReduced2_T_46 = mux(_notCDom_normDistReduced2_T_21, UInt<3>(0h4), _notCDom_normDistReduced2_T_45)
node _notCDom_normDistReduced2_T_47 = mux(_notCDom_normDistReduced2_T_22, UInt<2>(0h3), _notCDom_normDistReduced2_T_46)
node _notCDom_normDistReduced2_T_48 = mux(_notCDom_normDistReduced2_T_23, UInt<2>(0h2), _notCDom_normDistReduced2_T_47)
node _notCDom_normDistReduced2_T_49 = mux(_notCDom_normDistReduced2_T_24, UInt<1>(0h1), _notCDom_normDistReduced2_T_48)
node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_25, UInt<1>(0h0), _notCDom_normDistReduced2_T_49)
node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1)
node _notCDom_sExp_T = cvt(notCDom_nearNormDist)
node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T)
node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1)
node notCDom_sExp = asSInt(_notCDom_sExp_T_2)
node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist)
node notCDom_mainSig = bits(_notCDom_mainSig_T, 51, 23)
node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 12, 0)
node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0)
wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[7]
node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0)
node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T)
connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1
node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2)
node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T)
connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1
node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4)
node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T)
connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1
node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6)
node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T)
connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1
node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8)
node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T)
connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1
node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10)
node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T)
connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1
node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 12, 12)
node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T)
connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1
node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1])
node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec[0])
node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3])
node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5])
node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo)
node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo)
node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1)
node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3)
node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _notCDom_reduced4SigExtra_T_4)
node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 6, 1)
node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 3, 0)
node _notCDom_reduced4SigExtra_T_7 = bits(_notCDom_reduced4SigExtra_T_6, 1, 0)
node _notCDom_reduced4SigExtra_T_8 = bits(_notCDom_reduced4SigExtra_T_7, 0, 0)
node _notCDom_reduced4SigExtra_T_9 = bits(_notCDom_reduced4SigExtra_T_7, 1, 1)
node _notCDom_reduced4SigExtra_T_10 = cat(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9)
node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 2)
node _notCDom_reduced4SigExtra_T_12 = bits(_notCDom_reduced4SigExtra_T_11, 0, 0)
node _notCDom_reduced4SigExtra_T_13 = bits(_notCDom_reduced4SigExtra_T_11, 1, 1)
node _notCDom_reduced4SigExtra_T_14 = cat(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13)
node _notCDom_reduced4SigExtra_T_15 = cat(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14)
node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_5, 5, 4)
node _notCDom_reduced4SigExtra_T_17 = bits(_notCDom_reduced4SigExtra_T_16, 0, 0)
node _notCDom_reduced4SigExtra_T_18 = bits(_notCDom_reduced4SigExtra_T_16, 1, 1)
node _notCDom_reduced4SigExtra_T_19 = cat(_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18)
node _notCDom_reduced4SigExtra_T_20 = cat(_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19)
node _notCDom_reduced4SigExtra_T_21 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_20)
node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_21)
node _notCDom_sig_T = shr(notCDom_mainSig, 3)
node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0)
node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1)
node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra)
node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3)
node _notCDom_completeCancellation_T = bits(notCDom_sig, 26, 25)
node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0))
node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum)
node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T)
node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB)
node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC)
node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB)
node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC)
node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB)
node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T)
node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB)
node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2)
node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0))
node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB)
node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5)
node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC)
node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags)
node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8)
connect io.invalidExc, _io_invalidExc_T_9
node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC)
connect io.rawOut.isNaN, _io_rawOut_isNaN_T
connect io.rawOut.isInf, notNaN_isInfOut
node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0))
node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation)
node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1)
connect io.rawOut.isZero, _io_rawOut_isZero_T_2
node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd)
node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC)
node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1)
node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0))
node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3)
node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd)
node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC)
node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6)
node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min)
node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC)
node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9)
node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10)
node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0))
node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0))
node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13)
node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign)
node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15)
node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16)
connect io.rawOut.sign, _io_rawOut_sign_T_17
node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp)
connect io.rawOut.sExp, _io_rawOut_sExp_T
node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig)
connect io.rawOut.sig, _io_rawOut_sig_T | module MulAddRecFNToRaw_postMul_e8_s24_68( // @[MulAddRecFN.scala:169:7]
input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16]
input [9:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16]
input [4:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16]
input [25:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16]
input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16]
input [48:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16]
output io_invalidExc, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16]
output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16]
output io_rawOut_sign, // @[MulAddRecFN.scala:172:16]
output [9:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16]
output [26:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16]
);
wire io_fromPreMul_isSigNaNAny_0 = io_fromPreMul_isSigNaNAny; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNAOrB_0 = io_fromPreMul_isNaNAOrB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfA_0 = io_fromPreMul_isInfA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroA_0 = io_fromPreMul_isZeroA; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfB_0 = io_fromPreMul_isInfB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroB_0 = io_fromPreMul_isZeroB; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_signProd_0 = io_fromPreMul_signProd; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isNaNC_0 = io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isInfC_0 = io_fromPreMul_isInfC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_isZeroC_0 = io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_fromPreMul_sExpSum_0 = io_fromPreMul_sExpSum; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_doSubMags_0 = io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_CIsDominant_0 = io_fromPreMul_CIsDominant; // @[MulAddRecFN.scala:169:7]
wire [4:0] io_fromPreMul_CDom_CAlignDist_0 = io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:169:7]
wire [25:0] io_fromPreMul_highAlignedSigC_0 = io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:169:7]
wire io_fromPreMul_bit0AlignedSigC_0 = io_fromPreMul_bit0AlignedSigC; // @[MulAddRecFN.scala:169:7]
wire [48:0] io_mulAddResult_0 = io_mulAddResult; // @[MulAddRecFN.scala:169:7]
wire _io_rawOut_sign_T_3 = 1'h1; // @[MulAddRecFN.scala:287:29]
wire roundingMode_min = 1'h0; // @[MulAddRecFN.scala:186:45]
wire _io_rawOut_sign_T_8 = 1'h0; // @[MulAddRecFN.scala:289:26]
wire _io_rawOut_sign_T_10 = 1'h0; // @[MulAddRecFN.scala:289:46]
wire [2:0] io_roundingMode = 3'h0; // @[MulAddRecFN.scala:169:7, :172:16]
wire _io_invalidExc_T_9; // @[MulAddRecFN.scala:273:57]
wire _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:278:48]
wire notNaN_isInfOut; // @[MulAddRecFN.scala:265:44]
wire _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:282:25]
wire _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:290:50]
wire [9:0] _io_rawOut_sExp_T; // @[MulAddRecFN.scala:293:26]
wire [26:0] _io_rawOut_sig_T; // @[MulAddRecFN.scala:294:25]
wire io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
wire io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
wire [9:0] io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
wire [26:0] io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
wire io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
wire opSignC = io_fromPreMul_signProd_0 ^ io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :190:42]
wire _sigSum_T = io_mulAddResult_0[48]; // @[MulAddRecFN.scala:169:7, :192:32]
wire [26:0] _sigSum_T_1 = {1'h0, io_fromPreMul_highAlignedSigC_0} + 27'h1; // @[MulAddRecFN.scala:169:7, :193:47]
wire [25:0] _sigSum_T_2 = _sigSum_T_1[25:0]; // @[MulAddRecFN.scala:193:47]
wire [25:0] _sigSum_T_3 = _sigSum_T ? _sigSum_T_2 : io_fromPreMul_highAlignedSigC_0; // @[MulAddRecFN.scala:169:7, :192:{16,32}, :193:47]
wire [47:0] _sigSum_T_4 = io_mulAddResult_0[47:0]; // @[MulAddRecFN.scala:169:7, :196:28]
wire [73:0] sigSum_hi = {_sigSum_T_3, _sigSum_T_4}; // @[MulAddRecFN.scala:192:{12,16}, :196:28]
wire [74:0] sigSum = {sigSum_hi, io_fromPreMul_bit0AlignedSigC_0}; // @[MulAddRecFN.scala:169:7, :192:12]
wire [1:0] _CDom_sExp_T = {1'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :203:69]
wire [10:0] _GEN = {io_fromPreMul_sExpSum_0[9], io_fromPreMul_sExpSum_0}; // @[MulAddRecFN.scala:169:7, :203:43]
wire [10:0] _CDom_sExp_T_1 = _GEN - {{9{_CDom_sExp_T[1]}}, _CDom_sExp_T}; // @[MulAddRecFN.scala:203:{43,69}]
wire [9:0] _CDom_sExp_T_2 = _CDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:203:43]
wire [9:0] CDom_sExp = _CDom_sExp_T_2; // @[MulAddRecFN.scala:203:43]
wire [49:0] _CDom_absSigSum_T = sigSum[74:25]; // @[MulAddRecFN.scala:192:12, :206:20]
wire [49:0] _CDom_absSigSum_T_1 = ~_CDom_absSigSum_T; // @[MulAddRecFN.scala:206:{13,20}]
wire [1:0] _CDom_absSigSum_T_2 = io_fromPreMul_highAlignedSigC_0[25:24]; // @[MulAddRecFN.scala:169:7, :209:46]
wire [2:0] _CDom_absSigSum_T_3 = {1'h0, _CDom_absSigSum_T_2}; // @[MulAddRecFN.scala:207:22, :209:46]
wire [46:0] _CDom_absSigSum_T_4 = sigSum[72:26]; // @[MulAddRecFN.scala:192:12, :210:23]
wire [49:0] _CDom_absSigSum_T_5 = {_CDom_absSigSum_T_3, _CDom_absSigSum_T_4}; // @[MulAddRecFN.scala:207:22, :209:71, :210:23]
wire [49:0] CDom_absSigSum = io_fromPreMul_doSubMags_0 ? _CDom_absSigSum_T_1 : _CDom_absSigSum_T_5; // @[MulAddRecFN.scala:169:7, :205:12, :206:13, :209:71]
wire [23:0] _CDom_absSigSumExtra_T = sigSum[24:1]; // @[MulAddRecFN.scala:192:12, :215:21]
wire [23:0] _CDom_absSigSumExtra_T_1 = ~_CDom_absSigSumExtra_T; // @[MulAddRecFN.scala:215:{14,21}]
wire _CDom_absSigSumExtra_T_2 = |_CDom_absSigSumExtra_T_1; // @[MulAddRecFN.scala:215:{14,36}]
wire [24:0] _CDom_absSigSumExtra_T_3 = sigSum[25:1]; // @[MulAddRecFN.scala:192:12, :216:19]
wire _CDom_absSigSumExtra_T_4 = |_CDom_absSigSumExtra_T_3; // @[MulAddRecFN.scala:216:{19,37}]
wire CDom_absSigSumExtra = io_fromPreMul_doSubMags_0 ? _CDom_absSigSumExtra_T_2 : _CDom_absSigSumExtra_T_4; // @[MulAddRecFN.scala:169:7, :214:12, :215:36, :216:37]
wire [80:0] _CDom_mainSig_T = {31'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:169:7, :205:12, :219:24]
wire [28:0] CDom_mainSig = _CDom_mainSig_T[49:21]; // @[MulAddRecFN.scala:219:{24,56}]
wire [23:0] _CDom_reduced4SigExtra_T = CDom_absSigSum[23:0]; // @[MulAddRecFN.scala:205:12, :222:36]
wire [26:0] _CDom_reduced4SigExtra_T_1 = {_CDom_reduced4SigExtra_T, 3'h0}; // @[MulAddRecFN.scala:169:7, :172:16, :222:{36,53}]
wire _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:120:54]
wire _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:123:57]
wire CDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:118:30]
wire CDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:118:30]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_0_T = _CDom_reduced4SigExtra_T_1[3:0]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_0_T_1 = |_CDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_0 = _CDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_1_T = _CDom_reduced4SigExtra_T_1[7:4]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_1_T_1 = |_CDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_1 = _CDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_2_T = _CDom_reduced4SigExtra_T_1[11:8]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_2_T_1 = |_CDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_2 = _CDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_3_T = _CDom_reduced4SigExtra_T_1[15:12]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_3_T_1 = |_CDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_3 = _CDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_4_T = _CDom_reduced4SigExtra_T_1[19:16]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_4_T_1 = |_CDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_4 = _CDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54]
wire [3:0] _CDom_reduced4SigExtra_reducedVec_5_T = _CDom_reduced4SigExtra_T_1[23:20]; // @[primitives.scala:120:33]
assign _CDom_reduced4SigExtra_reducedVec_5_T_1 = |_CDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}]
assign CDom_reduced4SigExtra_reducedVec_5 = _CDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54]
wire [2:0] _CDom_reduced4SigExtra_reducedVec_6_T = _CDom_reduced4SigExtra_T_1[26:24]; // @[primitives.scala:123:15]
assign _CDom_reduced4SigExtra_reducedVec_6_T_1 = |_CDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}]
assign CDom_reduced4SigExtra_reducedVec_6 = _CDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57]
wire [1:0] CDom_reduced4SigExtra_lo_hi = {CDom_reduced4SigExtra_reducedVec_2, CDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20]
wire [2:0] CDom_reduced4SigExtra_lo = {CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_lo = {CDom_reduced4SigExtra_reducedVec_4, CDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20]
wire [1:0] CDom_reduced4SigExtra_hi_hi = {CDom_reduced4SigExtra_reducedVec_6, CDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20]
wire [3:0] CDom_reduced4SigExtra_hi = {CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:124:20]
wire [6:0] _CDom_reduced4SigExtra_T_2 = {CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo}; // @[primitives.scala:124:20]
wire [2:0] _CDom_reduced4SigExtra_T_3 = io_fromPreMul_CDom_CAlignDist_0[4:2]; // @[MulAddRecFN.scala:169:7, :223:51]
wire [2:0] _CDom_reduced4SigExtra_T_4 = ~_CDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [8:0] CDom_reduced4SigExtra_shift = $signed(9'sh100 >>> _CDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _CDom_reduced4SigExtra_T_5 = CDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _CDom_reduced4SigExtra_T_6 = _CDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _CDom_reduced4SigExtra_T_7 = _CDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_8 = _CDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_9 = _CDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_10 = {_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_11 = _CDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_12 = _CDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_13 = _CDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_14 = {_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _CDom_reduced4SigExtra_T_15 = {_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_16 = _CDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _CDom_reduced4SigExtra_T_17 = _CDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _CDom_reduced4SigExtra_T_18 = _CDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _CDom_reduced4SigExtra_T_19 = {_CDom_reduced4SigExtra_T_17, _CDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _CDom_reduced4SigExtra_T_20 = {_CDom_reduced4SigExtra_T_15, _CDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _CDom_reduced4SigExtra_T_21 = {1'h0, _CDom_reduced4SigExtra_T_2[5:0] & _CDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :124:20]
wire CDom_reduced4SigExtra = |_CDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:222:72, :223:73]
wire [25:0] _CDom_sig_T = CDom_mainSig[28:3]; // @[MulAddRecFN.scala:219:56, :225:25]
wire [2:0] _CDom_sig_T_1 = CDom_mainSig[2:0]; // @[MulAddRecFN.scala:219:56, :226:25]
wire _CDom_sig_T_2 = |_CDom_sig_T_1; // @[MulAddRecFN.scala:226:{25,32}]
wire _CDom_sig_T_3 = _CDom_sig_T_2 | CDom_reduced4SigExtra; // @[MulAddRecFN.scala:223:73, :226:{32,36}]
wire _CDom_sig_T_4 = _CDom_sig_T_3 | CDom_absSigSumExtra; // @[MulAddRecFN.scala:214:12, :226:{36,61}]
wire [26:0] CDom_sig = {_CDom_sig_T, _CDom_sig_T_4}; // @[MulAddRecFN.scala:225:{12,25}, :226:61]
wire notCDom_signSigSum = sigSum[51]; // @[MulAddRecFN.scala:192:12, :232:36]
wire [50:0] _notCDom_absSigSum_T = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20]
wire [50:0] _notCDom_absSigSum_T_2 = sigSum[50:0]; // @[MulAddRecFN.scala:192:12, :235:20, :236:19]
wire [50:0] _notCDom_absSigSum_T_1 = ~_notCDom_absSigSum_T; // @[MulAddRecFN.scala:235:{13,20}]
wire [51:0] _notCDom_absSigSum_T_3 = {1'h0, _notCDom_absSigSum_T_2} + {51'h0, io_fromPreMul_doSubMags_0}; // @[MulAddRecFN.scala:169:7, :236:{19,41}]
wire [50:0] _notCDom_absSigSum_T_4 = _notCDom_absSigSum_T_3[50:0]; // @[MulAddRecFN.scala:236:41]
wire [50:0] notCDom_absSigSum = notCDom_signSigSum ? _notCDom_absSigSum_T_1 : _notCDom_absSigSum_T_4; // @[MulAddRecFN.scala:232:36, :234:12, :235:13, :236:41]
wire _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced2AbsSigSum_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_6; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_7; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_8; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_9; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_10; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_11; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_12; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_13; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_14; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_15; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_16; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_17; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_18; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_19; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_20; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_21; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_22; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_23; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_24; // @[primitives.scala:101:30]
wire notCDom_reduced2AbsSigSum_reducedVec_25; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_0_T = notCDom_absSigSum[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_0 = _notCDom_reduced2AbsSigSum_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_1_T = notCDom_absSigSum[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_1 = _notCDom_reduced2AbsSigSum_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_2_T = notCDom_absSigSum[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_2 = _notCDom_reduced2AbsSigSum_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_3_T = notCDom_absSigSum[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_3 = _notCDom_reduced2AbsSigSum_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_4_T = notCDom_absSigSum[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_4 = _notCDom_reduced2AbsSigSum_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_5_T = notCDom_absSigSum[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_5 = _notCDom_reduced2AbsSigSum_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_6_T = notCDom_absSigSum[13:12]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_6_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_6 = _notCDom_reduced2AbsSigSum_reducedVec_6_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_7_T = notCDom_absSigSum[15:14]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_7_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_7 = _notCDom_reduced2AbsSigSum_reducedVec_7_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_8_T = notCDom_absSigSum[17:16]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_8_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_8 = _notCDom_reduced2AbsSigSum_reducedVec_8_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_9_T = notCDom_absSigSum[19:18]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_9_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_9 = _notCDom_reduced2AbsSigSum_reducedVec_9_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_10_T = notCDom_absSigSum[21:20]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_10_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_10 = _notCDom_reduced2AbsSigSum_reducedVec_10_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_11_T = notCDom_absSigSum[23:22]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_11_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_11 = _notCDom_reduced2AbsSigSum_reducedVec_11_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_12_T = notCDom_absSigSum[25:24]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_12_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_12 = _notCDom_reduced2AbsSigSum_reducedVec_12_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_13_T = notCDom_absSigSum[27:26]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_13_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_13 = _notCDom_reduced2AbsSigSum_reducedVec_13_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_14_T = notCDom_absSigSum[29:28]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_14_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_14 = _notCDom_reduced2AbsSigSum_reducedVec_14_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_15_T = notCDom_absSigSum[31:30]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_15_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_15 = _notCDom_reduced2AbsSigSum_reducedVec_15_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_16_T = notCDom_absSigSum[33:32]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_16_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_16 = _notCDom_reduced2AbsSigSum_reducedVec_16_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_17_T = notCDom_absSigSum[35:34]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_17_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_17 = _notCDom_reduced2AbsSigSum_reducedVec_17_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_18_T = notCDom_absSigSum[37:36]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_18_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_18 = _notCDom_reduced2AbsSigSum_reducedVec_18_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_19_T = notCDom_absSigSum[39:38]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_19_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_19 = _notCDom_reduced2AbsSigSum_reducedVec_19_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_20_T = notCDom_absSigSum[41:40]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_20_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_20 = _notCDom_reduced2AbsSigSum_reducedVec_20_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_21_T = notCDom_absSigSum[43:42]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_21_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_21 = _notCDom_reduced2AbsSigSum_reducedVec_21_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_22_T = notCDom_absSigSum[45:44]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_22_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_22 = _notCDom_reduced2AbsSigSum_reducedVec_22_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_23_T = notCDom_absSigSum[47:46]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_23_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_23 = _notCDom_reduced2AbsSigSum_reducedVec_23_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced2AbsSigSum_reducedVec_24_T = notCDom_absSigSum[49:48]; // @[primitives.scala:103:33]
assign _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = |_notCDom_reduced2AbsSigSum_reducedVec_24_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced2AbsSigSum_reducedVec_24 = _notCDom_reduced2AbsSigSum_reducedVec_24_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced2AbsSigSum_reducedVec_25_T = notCDom_absSigSum[50]; // @[primitives.scala:106:15]
assign _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = _notCDom_reduced2AbsSigSum_reducedVec_25_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced2AbsSigSum_reducedVec_25 = _notCDom_reduced2AbsSigSum_reducedVec_25_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_2, notCDom_reduced2AbsSigSum_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_5, notCDom_reduced2AbsSigSum_reducedVec_4}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_lo_hi = {notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_lo_lo = {notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_8, notCDom_reduced2AbsSigSum_reducedVec_7}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_lo_hi_lo = {notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_6}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_10, notCDom_reduced2AbsSigSum_reducedVec_9}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_lo_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_12, notCDom_reduced2AbsSigSum_reducedVec_11}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_lo_hi_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_lo_hi = {notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_lo = {notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_15, notCDom_reduced2AbsSigSum_reducedVec_14}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_lo = {notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_13}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_lo_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_18, notCDom_reduced2AbsSigSum_reducedVec_17}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_lo_hi = {notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec_16}; // @[primitives.scala:101:30, :107:20]
wire [5:0] notCDom_reduced2AbsSigSum_hi_lo = {notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo}; // @[primitives.scala:107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_lo_hi = {notCDom_reduced2AbsSigSum_reducedVec_21, notCDom_reduced2AbsSigSum_reducedVec_20}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced2AbsSigSum_hi_hi_lo = {notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec_19}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_lo = {notCDom_reduced2AbsSigSum_reducedVec_23, notCDom_reduced2AbsSigSum_reducedVec_22}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced2AbsSigSum_hi_hi_hi_hi = {notCDom_reduced2AbsSigSum_reducedVec_25, notCDom_reduced2AbsSigSum_reducedVec_24}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced2AbsSigSum_hi_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] notCDom_reduced2AbsSigSum_hi_hi = {notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo}; // @[primitives.scala:107:20]
wire [12:0] notCDom_reduced2AbsSigSum_hi = {notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo}; // @[primitives.scala:107:20]
wire [25:0] notCDom_reduced2AbsSigSum = {notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo}; // @[primitives.scala:107:20]
wire _notCDom_normDistReduced2_T = notCDom_reduced2AbsSigSum[0]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_1 = notCDom_reduced2AbsSigSum[1]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_2 = notCDom_reduced2AbsSigSum[2]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_3 = notCDom_reduced2AbsSigSum[3]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_4 = notCDom_reduced2AbsSigSum[4]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_5 = notCDom_reduced2AbsSigSum[5]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_6 = notCDom_reduced2AbsSigSum[6]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_7 = notCDom_reduced2AbsSigSum[7]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_8 = notCDom_reduced2AbsSigSum[8]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_9 = notCDom_reduced2AbsSigSum[9]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_10 = notCDom_reduced2AbsSigSum[10]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_11 = notCDom_reduced2AbsSigSum[11]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_12 = notCDom_reduced2AbsSigSum[12]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_13 = notCDom_reduced2AbsSigSum[13]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_14 = notCDom_reduced2AbsSigSum[14]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_15 = notCDom_reduced2AbsSigSum[15]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_16 = notCDom_reduced2AbsSigSum[16]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_17 = notCDom_reduced2AbsSigSum[17]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_18 = notCDom_reduced2AbsSigSum[18]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_19 = notCDom_reduced2AbsSigSum[19]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_20 = notCDom_reduced2AbsSigSum[20]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_21 = notCDom_reduced2AbsSigSum[21]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_22 = notCDom_reduced2AbsSigSum[22]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_23 = notCDom_reduced2AbsSigSum[23]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_24 = notCDom_reduced2AbsSigSum[24]; // @[primitives.scala:91:52, :107:20]
wire _notCDom_normDistReduced2_T_25 = notCDom_reduced2AbsSigSum[25]; // @[primitives.scala:91:52, :107:20]
wire [4:0] _notCDom_normDistReduced2_T_26 = {4'hC, ~_notCDom_normDistReduced2_T_1}; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_27 = _notCDom_normDistReduced2_T_2 ? 5'h17 : _notCDom_normDistReduced2_T_26; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_28 = _notCDom_normDistReduced2_T_3 ? 5'h16 : _notCDom_normDistReduced2_T_27; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_29 = _notCDom_normDistReduced2_T_4 ? 5'h15 : _notCDom_normDistReduced2_T_28; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_30 = _notCDom_normDistReduced2_T_5 ? 5'h14 : _notCDom_normDistReduced2_T_29; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_31 = _notCDom_normDistReduced2_T_6 ? 5'h13 : _notCDom_normDistReduced2_T_30; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_32 = _notCDom_normDistReduced2_T_7 ? 5'h12 : _notCDom_normDistReduced2_T_31; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_33 = _notCDom_normDistReduced2_T_8 ? 5'h11 : _notCDom_normDistReduced2_T_32; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_34 = _notCDom_normDistReduced2_T_9 ? 5'h10 : _notCDom_normDistReduced2_T_33; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_35 = _notCDom_normDistReduced2_T_10 ? 5'hF : _notCDom_normDistReduced2_T_34; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_36 = _notCDom_normDistReduced2_T_11 ? 5'hE : _notCDom_normDistReduced2_T_35; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_37 = _notCDom_normDistReduced2_T_12 ? 5'hD : _notCDom_normDistReduced2_T_36; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_38 = _notCDom_normDistReduced2_T_13 ? 5'hC : _notCDom_normDistReduced2_T_37; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_39 = _notCDom_normDistReduced2_T_14 ? 5'hB : _notCDom_normDistReduced2_T_38; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_40 = _notCDom_normDistReduced2_T_15 ? 5'hA : _notCDom_normDistReduced2_T_39; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_41 = _notCDom_normDistReduced2_T_16 ? 5'h9 : _notCDom_normDistReduced2_T_40; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_42 = _notCDom_normDistReduced2_T_17 ? 5'h8 : _notCDom_normDistReduced2_T_41; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_43 = _notCDom_normDistReduced2_T_18 ? 5'h7 : _notCDom_normDistReduced2_T_42; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_44 = _notCDom_normDistReduced2_T_19 ? 5'h6 : _notCDom_normDistReduced2_T_43; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_45 = _notCDom_normDistReduced2_T_20 ? 5'h5 : _notCDom_normDistReduced2_T_44; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_46 = _notCDom_normDistReduced2_T_21 ? 5'h4 : _notCDom_normDistReduced2_T_45; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_47 = _notCDom_normDistReduced2_T_22 ? 5'h3 : _notCDom_normDistReduced2_T_46; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_48 = _notCDom_normDistReduced2_T_23 ? 5'h2 : _notCDom_normDistReduced2_T_47; // @[Mux.scala:50:70]
wire [4:0] _notCDom_normDistReduced2_T_49 = _notCDom_normDistReduced2_T_24 ? 5'h1 : _notCDom_normDistReduced2_T_48; // @[Mux.scala:50:70]
wire [4:0] notCDom_normDistReduced2 = _notCDom_normDistReduced2_T_25 ? 5'h0 : _notCDom_normDistReduced2_T_49; // @[Mux.scala:50:70]
wire [5:0] notCDom_nearNormDist = {notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70]
wire [6:0] _notCDom_sExp_T = {1'h0, notCDom_nearNormDist}; // @[MulAddRecFN.scala:240:56, :241:76]
wire [10:0] _notCDom_sExp_T_1 = _GEN - {{4{_notCDom_sExp_T[6]}}, _notCDom_sExp_T}; // @[MulAddRecFN.scala:203:43, :241:{46,76}]
wire [9:0] _notCDom_sExp_T_2 = _notCDom_sExp_T_1[9:0]; // @[MulAddRecFN.scala:241:46]
wire [9:0] notCDom_sExp = _notCDom_sExp_T_2; // @[MulAddRecFN.scala:241:46]
wire [113:0] _notCDom_mainSig_T = {63'h0, notCDom_absSigSum} << notCDom_nearNormDist; // @[MulAddRecFN.scala:234:12, :240:56, :243:27]
wire [28:0] notCDom_mainSig = _notCDom_mainSig_T[51:23]; // @[MulAddRecFN.scala:243:{27,50}]
wire [12:0] _notCDom_reduced4SigExtra_T = notCDom_reduced2AbsSigSum[12:0]; // @[primitives.scala:107:20]
wire [12:0] _notCDom_reduced4SigExtra_T_1 = _notCDom_reduced4SigExtra_T; // @[MulAddRecFN.scala:247:{39,55}]
wire _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:106:57]
wire notCDom_reduced4SigExtra_reducedVec_0; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_1; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_2; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_3; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_4; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_5; // @[primitives.scala:101:30]
wire notCDom_reduced4SigExtra_reducedVec_6; // @[primitives.scala:101:30]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_0_T = _notCDom_reduced4SigExtra_T_1[1:0]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_0_T_1 = |_notCDom_reduced4SigExtra_reducedVec_0_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_0 = _notCDom_reduced4SigExtra_reducedVec_0_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_1_T = _notCDom_reduced4SigExtra_T_1[3:2]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_1_T_1 = |_notCDom_reduced4SigExtra_reducedVec_1_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_1 = _notCDom_reduced4SigExtra_reducedVec_1_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_2_T = _notCDom_reduced4SigExtra_T_1[5:4]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_2_T_1 = |_notCDom_reduced4SigExtra_reducedVec_2_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_2 = _notCDom_reduced4SigExtra_reducedVec_2_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_3_T = _notCDom_reduced4SigExtra_T_1[7:6]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_3_T_1 = |_notCDom_reduced4SigExtra_reducedVec_3_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_3 = _notCDom_reduced4SigExtra_reducedVec_3_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_4_T = _notCDom_reduced4SigExtra_T_1[9:8]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_4_T_1 = |_notCDom_reduced4SigExtra_reducedVec_4_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_4 = _notCDom_reduced4SigExtra_reducedVec_4_T_1; // @[primitives.scala:101:30, :103:54]
wire [1:0] _notCDom_reduced4SigExtra_reducedVec_5_T = _notCDom_reduced4SigExtra_T_1[11:10]; // @[primitives.scala:103:33]
assign _notCDom_reduced4SigExtra_reducedVec_5_T_1 = |_notCDom_reduced4SigExtra_reducedVec_5_T; // @[primitives.scala:103:{33,54}]
assign notCDom_reduced4SigExtra_reducedVec_5 = _notCDom_reduced4SigExtra_reducedVec_5_T_1; // @[primitives.scala:101:30, :103:54]
wire _notCDom_reduced4SigExtra_reducedVec_6_T = _notCDom_reduced4SigExtra_T_1[12]; // @[primitives.scala:106:15]
assign _notCDom_reduced4SigExtra_reducedVec_6_T_1 = _notCDom_reduced4SigExtra_reducedVec_6_T; // @[primitives.scala:106:{15,57}]
assign notCDom_reduced4SigExtra_reducedVec_6 = _notCDom_reduced4SigExtra_reducedVec_6_T_1; // @[primitives.scala:101:30, :106:57]
wire [1:0] notCDom_reduced4SigExtra_lo_hi = {notCDom_reduced4SigExtra_reducedVec_2, notCDom_reduced4SigExtra_reducedVec_1}; // @[primitives.scala:101:30, :107:20]
wire [2:0] notCDom_reduced4SigExtra_lo = {notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_reducedVec_0}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_lo = {notCDom_reduced4SigExtra_reducedVec_4, notCDom_reduced4SigExtra_reducedVec_3}; // @[primitives.scala:101:30, :107:20]
wire [1:0] notCDom_reduced4SigExtra_hi_hi = {notCDom_reduced4SigExtra_reducedVec_6, notCDom_reduced4SigExtra_reducedVec_5}; // @[primitives.scala:101:30, :107:20]
wire [3:0] notCDom_reduced4SigExtra_hi = {notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo}; // @[primitives.scala:107:20]
wire [6:0] _notCDom_reduced4SigExtra_T_2 = {notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo}; // @[primitives.scala:107:20]
wire [3:0] _notCDom_reduced4SigExtra_T_3 = notCDom_normDistReduced2[4:1]; // @[Mux.scala:50:70]
wire [3:0] _notCDom_reduced4SigExtra_T_4 = ~_notCDom_reduced4SigExtra_T_3; // @[primitives.scala:52:21]
wire [16:0] notCDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> _notCDom_reduced4SigExtra_T_4); // @[primitives.scala:52:21, :76:56]
wire [5:0] _notCDom_reduced4SigExtra_T_5 = notCDom_reduced4SigExtra_shift[6:1]; // @[primitives.scala:76:56, :78:22]
wire [3:0] _notCDom_reduced4SigExtra_T_6 = _notCDom_reduced4SigExtra_T_5[3:0]; // @[primitives.scala:77:20, :78:22]
wire [1:0] _notCDom_reduced4SigExtra_T_7 = _notCDom_reduced4SigExtra_T_6[1:0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_8 = _notCDom_reduced4SigExtra_T_7[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_9 = _notCDom_reduced4SigExtra_T_7[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_10 = {_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_9}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_11 = _notCDom_reduced4SigExtra_T_6[3:2]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_12 = _notCDom_reduced4SigExtra_T_11[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_13 = _notCDom_reduced4SigExtra_T_11[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_14 = {_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13}; // @[primitives.scala:77:20]
wire [3:0] _notCDom_reduced4SigExtra_T_15 = {_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14}; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_16 = _notCDom_reduced4SigExtra_T_5[5:4]; // @[primitives.scala:77:20, :78:22]
wire _notCDom_reduced4SigExtra_T_17 = _notCDom_reduced4SigExtra_T_16[0]; // @[primitives.scala:77:20]
wire _notCDom_reduced4SigExtra_T_18 = _notCDom_reduced4SigExtra_T_16[1]; // @[primitives.scala:77:20]
wire [1:0] _notCDom_reduced4SigExtra_T_19 = {_notCDom_reduced4SigExtra_T_17, _notCDom_reduced4SigExtra_T_18}; // @[primitives.scala:77:20]
wire [5:0] _notCDom_reduced4SigExtra_T_20 = {_notCDom_reduced4SigExtra_T_15, _notCDom_reduced4SigExtra_T_19}; // @[primitives.scala:77:20]
wire [6:0] _notCDom_reduced4SigExtra_T_21 = {1'h0, _notCDom_reduced4SigExtra_T_2[5:0] & _notCDom_reduced4SigExtra_T_20}; // @[primitives.scala:77:20, :107:20]
wire notCDom_reduced4SigExtra = |_notCDom_reduced4SigExtra_T_21; // @[MulAddRecFN.scala:247:78, :249:11]
wire [25:0] _notCDom_sig_T = notCDom_mainSig[28:3]; // @[MulAddRecFN.scala:243:50, :251:28]
wire [2:0] _notCDom_sig_T_1 = notCDom_mainSig[2:0]; // @[MulAddRecFN.scala:243:50, :252:28]
wire _notCDom_sig_T_2 = |_notCDom_sig_T_1; // @[MulAddRecFN.scala:252:{28,35}]
wire _notCDom_sig_T_3 = _notCDom_sig_T_2 | notCDom_reduced4SigExtra; // @[MulAddRecFN.scala:249:11, :252:{35,39}]
wire [26:0] notCDom_sig = {_notCDom_sig_T, _notCDom_sig_T_3}; // @[MulAddRecFN.scala:251:{12,28}, :252:39]
wire [1:0] _notCDom_completeCancellation_T = notCDom_sig[26:25]; // @[MulAddRecFN.scala:251:12, :255:21]
wire notCDom_completeCancellation = _notCDom_completeCancellation_T == 2'h0; // @[primitives.scala:103:54]
wire _notCDom_sign_T = io_fromPreMul_signProd_0 ^ notCDom_signSigSum; // @[MulAddRecFN.scala:169:7, :232:36, :259:36]
wire notCDom_sign = ~notCDom_completeCancellation & _notCDom_sign_T; // @[MulAddRecFN.scala:255:50, :257:12, :259:36]
wire _GEN_0 = io_fromPreMul_isInfA_0 | io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :264:49]
wire notNaN_isInfProd; // @[MulAddRecFN.scala:264:49]
assign notNaN_isInfProd = _GEN_0; // @[MulAddRecFN.scala:264:49]
wire _io_invalidExc_T_5; // @[MulAddRecFN.scala:275:36]
assign _io_invalidExc_T_5 = _GEN_0; // @[MulAddRecFN.scala:264:49, :275:36]
assign notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :264:49, :265:44]
assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44]
wire _notNaN_addZeros_T = io_fromPreMul_isZeroA_0 | io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :267:32]
wire notNaN_addZeros = _notNaN_addZeros_T & io_fromPreMul_isZeroC_0; // @[MulAddRecFN.scala:169:7, :267:{32,58}]
wire _io_rawOut_sign_T_4 = notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :287:26]
wire _io_invalidExc_T = io_fromPreMul_isInfA_0 & io_fromPreMul_isZeroB_0; // @[MulAddRecFN.scala:169:7, :272:31]
wire _io_invalidExc_T_1 = io_fromPreMul_isSigNaNAny_0 | _io_invalidExc_T; // @[MulAddRecFN.scala:169:7, :271:35, :272:31]
wire _io_invalidExc_T_2 = io_fromPreMul_isZeroA_0 & io_fromPreMul_isInfB_0; // @[MulAddRecFN.scala:169:7, :273:32]
wire _io_invalidExc_T_3 = _io_invalidExc_T_1 | _io_invalidExc_T_2; // @[MulAddRecFN.scala:271:35, :272:57, :273:32]
wire _io_invalidExc_T_4 = ~io_fromPreMul_isNaNAOrB_0; // @[MulAddRecFN.scala:169:7, :274:10]
wire _io_invalidExc_T_6 = _io_invalidExc_T_4 & _io_invalidExc_T_5; // @[MulAddRecFN.scala:274:{10,36}, :275:36]
wire _io_invalidExc_T_7 = _io_invalidExc_T_6 & io_fromPreMul_isInfC_0; // @[MulAddRecFN.scala:169:7, :274:36, :275:61]
wire _io_invalidExc_T_8 = _io_invalidExc_T_7 & io_fromPreMul_doSubMags_0; // @[MulAddRecFN.scala:169:7, :275:61, :276:35]
assign _io_invalidExc_T_9 = _io_invalidExc_T_3 | _io_invalidExc_T_8; // @[MulAddRecFN.scala:272:57, :273:57, :276:35]
assign io_invalidExc_0 = _io_invalidExc_T_9; // @[MulAddRecFN.scala:169:7, :273:57]
assign _io_rawOut_isNaN_T = io_fromPreMul_isNaNAOrB_0 | io_fromPreMul_isNaNC_0; // @[MulAddRecFN.scala:169:7, :278:48]
assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulAddRecFN.scala:169:7, :278:48]
wire _io_rawOut_isZero_T = ~io_fromPreMul_CIsDominant_0; // @[MulAddRecFN.scala:169:7, :283:14]
wire _io_rawOut_isZero_T_1 = _io_rawOut_isZero_T & notCDom_completeCancellation; // @[MulAddRecFN.scala:255:50, :283:{14,42}]
assign _io_rawOut_isZero_T_2 = notNaN_addZeros | _io_rawOut_isZero_T_1; // @[MulAddRecFN.scala:267:58, :282:25, :283:42]
assign io_rawOut_isZero_0 = _io_rawOut_isZero_T_2; // @[MulAddRecFN.scala:169:7, :282:25]
wire _io_rawOut_sign_T = notNaN_isInfProd & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :264:49, :285:27]
wire _io_rawOut_sign_T_1 = io_fromPreMul_isInfC_0 & opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :286:31]
wire _io_rawOut_sign_T_2 = _io_rawOut_sign_T | _io_rawOut_sign_T_1; // @[MulAddRecFN.scala:285:{27,54}, :286:31]
wire _io_rawOut_sign_T_5 = _io_rawOut_sign_T_4 & io_fromPreMul_signProd_0; // @[MulAddRecFN.scala:169:7, :287:{26,48}]
wire _io_rawOut_sign_T_6 = _io_rawOut_sign_T_5 & opSignC; // @[MulAddRecFN.scala:190:42, :287:48, :288:36]
wire _io_rawOut_sign_T_7 = _io_rawOut_sign_T_2 | _io_rawOut_sign_T_6; // @[MulAddRecFN.scala:285:54, :286:43, :288:36]
wire _io_rawOut_sign_T_11 = _io_rawOut_sign_T_7; // @[MulAddRecFN.scala:286:43, :288:48]
wire _io_rawOut_sign_T_9 = io_fromPreMul_signProd_0 | opSignC; // @[MulAddRecFN.scala:169:7, :190:42, :290:37]
wire _io_rawOut_sign_T_12 = ~notNaN_isInfOut; // @[MulAddRecFN.scala:265:44, :291:10]
wire _io_rawOut_sign_T_13 = ~notNaN_addZeros; // @[MulAddRecFN.scala:267:58, :291:31]
wire _io_rawOut_sign_T_14 = _io_rawOut_sign_T_12 & _io_rawOut_sign_T_13; // @[MulAddRecFN.scala:291:{10,28,31}]
wire _io_rawOut_sign_T_15 = io_fromPreMul_CIsDominant_0 ? opSignC : notCDom_sign; // @[MulAddRecFN.scala:169:7, :190:42, :257:12, :292:17]
wire _io_rawOut_sign_T_16 = _io_rawOut_sign_T_14 & _io_rawOut_sign_T_15; // @[MulAddRecFN.scala:291:{28,49}, :292:17]
assign _io_rawOut_sign_T_17 = _io_rawOut_sign_T_11 | _io_rawOut_sign_T_16; // @[MulAddRecFN.scala:288:48, :290:50, :291:49]
assign io_rawOut_sign_0 = _io_rawOut_sign_T_17; // @[MulAddRecFN.scala:169:7, :290:50]
assign _io_rawOut_sExp_T = io_fromPreMul_CIsDominant_0 ? CDom_sExp : notCDom_sExp; // @[MulAddRecFN.scala:169:7, :203:43, :241:46, :293:26]
assign io_rawOut_sExp_0 = _io_rawOut_sExp_T; // @[MulAddRecFN.scala:169:7, :293:26]
assign _io_rawOut_sig_T = io_fromPreMul_CIsDominant_0 ? CDom_sig : notCDom_sig; // @[MulAddRecFN.scala:169:7, :225:12, :251:12, :294:25]
assign io_rawOut_sig_0 = _io_rawOut_sig_T; // @[MulAddRecFN.scala:169:7, :294:25]
assign io_invalidExc = io_invalidExc_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sign = io_rawOut_sign_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulAddRecFN.scala:169:7]
assign io_rawOut_sig = io_rawOut_sig_0; // @[MulAddRecFN.scala:169:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module InclusiveCacheBankScheduler :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip ways : UInt<8>[9], flip divs : UInt<11>[9], flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { address : UInt<32>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { fail : UInt<1>}}}
inst sourceA of SourceA
connect sourceA.clock, clock
connect sourceA.reset, reset
inst sourceB of SourceB
connect sourceB.clock, clock
connect sourceB.reset, reset
inst sourceC of SourceC
connect sourceC.clock, clock
connect sourceC.reset, reset
inst sourceD of SourceD
connect sourceD.clock, clock
connect sourceD.reset, reset
inst sourceE of SourceE
connect sourceE.clock, clock
connect sourceE.reset, reset
inst sourceX of SourceX
connect sourceX.clock, clock
connect sourceX.reset, reset
connect io.out.a.bits, sourceA.io.a.bits
connect io.out.a.valid, sourceA.io.a.valid
connect sourceA.io.a.ready, io.out.a.ready
connect io.out.c.bits, sourceC.io.c.bits
connect io.out.c.valid, sourceC.io.c.valid
connect sourceC.io.c.ready, io.out.c.ready
connect io.out.e.bits, sourceE.io.e.bits
connect io.out.e.valid, sourceE.io.e.valid
connect sourceE.io.e.ready, io.out.e.ready
connect io.in.b.bits, sourceB.io.b.bits
connect io.in.b.valid, sourceB.io.b.valid
connect sourceB.io.b.ready, io.in.b.ready
connect io.in.d.bits, sourceD.io.d.bits
connect io.in.d.valid, sourceD.io.d.valid
connect sourceD.io.d.ready, io.in.d.ready
connect io.resp.bits, sourceX.io.x.bits
connect io.resp.valid, sourceX.io.x.valid
connect sourceX.io.x.ready, io.resp.ready
inst sinkA of SinkA
connect sinkA.clock, clock
connect sinkA.reset, reset
inst sinkC of SinkC
connect sinkC.clock, clock
connect sinkC.reset, reset
inst sinkD of SinkD
connect sinkD.clock, clock
connect sinkD.reset, reset
inst sinkE of SinkE
connect sinkE.clock, clock
connect sinkE.reset, reset
inst sinkX of SinkX
connect sinkX.clock, clock
connect sinkX.reset, reset
connect sinkA.io.a, io.in.a
connect sinkC.io.c, io.in.c
connect sinkE.io.e, io.in.e
connect sinkD.io.d, io.out.d
connect sinkX.io.x, io.req
connect io.out.b.ready, UInt<1>(0h1)
inst directory of Directory
connect directory.clock, clock
connect directory.reset, reset
inst bankedStore of BankedStore
connect bankedStore.clock, clock
connect bankedStore.reset, reset
inst requests of ListBuffer_QueuedRequest_q36_e28
connect requests.clock, clock
connect requests.reset, reset
inst mshrs_0 of MSHR
connect mshrs_0.clock, clock
connect mshrs_0.reset, reset
inst mshrs_1 of MSHR_1
connect mshrs_1.clock, clock
connect mshrs_1.reset, reset
inst mshrs_2 of MSHR_2
connect mshrs_2.clock, clock
connect mshrs_2.reset, reset
inst mshrs_3 of MSHR_3
connect mshrs_3.clock, clock
connect mshrs_3.reset, reset
inst mshrs_4 of MSHR_4
connect mshrs_4.clock, clock
connect mshrs_4.reset, reset
inst mshrs_5 of MSHR_5
connect mshrs_5.clock, clock
connect mshrs_5.reset, reset
inst mshrs_6 of MSHR_6
connect mshrs_6.clock, clock
connect mshrs_6.reset, reset
inst mshrs_7 of MSHR_7
connect mshrs_7.clock, clock
connect mshrs_7.reset, reset
inst mshrs_8 of MSHR_8
connect mshrs_8.clock, clock
connect mshrs_8.reset, reset
inst mshrs_9 of MSHR_9
connect mshrs_9.clock, clock
connect mshrs_9.reset, reset
inst mshrs_10 of MSHR_10
connect mshrs_10.clock, clock
connect mshrs_10.reset, reset
inst mshrs_11 of MSHR_11
connect mshrs_11.clock, clock
connect mshrs_11.reset, reset
wire nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}
node _mshrs_0_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_0.io.status.bits.set)
node _mshrs_0_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_0_io_sinkc_valid_T)
connect mshrs_0.io.sinkc.valid, _mshrs_0_io_sinkc_valid_T_1
node _mshrs_0_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<1>(0h0))
node _mshrs_0_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_0_io_sinkd_valid_T)
connect mshrs_0.io.sinkd.valid, _mshrs_0_io_sinkd_valid_T_1
node _mshrs_0_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<1>(0h0))
node _mshrs_0_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_0_io_sinke_valid_T)
connect mshrs_0.io.sinke.valid, _mshrs_0_io_sinke_valid_T_1
connect mshrs_0.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_0.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_0.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_0.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_0.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_0.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_0.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_0.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_0.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_0.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_0.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_0.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_0.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_0.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_0.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_0.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_0.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_0.io.nestedwb.tag, nestedwb.tag
connect mshrs_0.io.nestedwb.set, nestedwb.set
node _mshrs_1_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_1.io.status.bits.set)
node _mshrs_1_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_1_io_sinkc_valid_T)
connect mshrs_1.io.sinkc.valid, _mshrs_1_io_sinkc_valid_T_1
node _mshrs_1_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<1>(0h1))
node _mshrs_1_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_1_io_sinkd_valid_T)
connect mshrs_1.io.sinkd.valid, _mshrs_1_io_sinkd_valid_T_1
node _mshrs_1_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<1>(0h1))
node _mshrs_1_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_1_io_sinke_valid_T)
connect mshrs_1.io.sinke.valid, _mshrs_1_io_sinke_valid_T_1
connect mshrs_1.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_1.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_1.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_1.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_1.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_1.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_1.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_1.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_1.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_1.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_1.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_1.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_1.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_1.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_1.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_1.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_1.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_1.io.nestedwb.tag, nestedwb.tag
connect mshrs_1.io.nestedwb.set, nestedwb.set
node _mshrs_2_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_2.io.status.bits.set)
node _mshrs_2_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_2_io_sinkc_valid_T)
connect mshrs_2.io.sinkc.valid, _mshrs_2_io_sinkc_valid_T_1
node _mshrs_2_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<2>(0h2))
node _mshrs_2_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_2_io_sinkd_valid_T)
connect mshrs_2.io.sinkd.valid, _mshrs_2_io_sinkd_valid_T_1
node _mshrs_2_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<2>(0h2))
node _mshrs_2_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_2_io_sinke_valid_T)
connect mshrs_2.io.sinke.valid, _mshrs_2_io_sinke_valid_T_1
connect mshrs_2.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_2.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_2.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_2.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_2.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_2.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_2.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_2.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_2.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_2.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_2.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_2.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_2.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_2.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_2.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_2.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_2.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_2.io.nestedwb.tag, nestedwb.tag
connect mshrs_2.io.nestedwb.set, nestedwb.set
node _mshrs_3_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_3.io.status.bits.set)
node _mshrs_3_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_3_io_sinkc_valid_T)
connect mshrs_3.io.sinkc.valid, _mshrs_3_io_sinkc_valid_T_1
node _mshrs_3_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<2>(0h3))
node _mshrs_3_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_3_io_sinkd_valid_T)
connect mshrs_3.io.sinkd.valid, _mshrs_3_io_sinkd_valid_T_1
node _mshrs_3_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<2>(0h3))
node _mshrs_3_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_3_io_sinke_valid_T)
connect mshrs_3.io.sinke.valid, _mshrs_3_io_sinke_valid_T_1
connect mshrs_3.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_3.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_3.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_3.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_3.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_3.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_3.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_3.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_3.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_3.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_3.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_3.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_3.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_3.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_3.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_3.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_3.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_3.io.nestedwb.tag, nestedwb.tag
connect mshrs_3.io.nestedwb.set, nestedwb.set
node _mshrs_4_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_4.io.status.bits.set)
node _mshrs_4_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_4_io_sinkc_valid_T)
connect mshrs_4.io.sinkc.valid, _mshrs_4_io_sinkc_valid_T_1
node _mshrs_4_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<3>(0h4))
node _mshrs_4_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_4_io_sinkd_valid_T)
connect mshrs_4.io.sinkd.valid, _mshrs_4_io_sinkd_valid_T_1
node _mshrs_4_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<3>(0h4))
node _mshrs_4_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_4_io_sinke_valid_T)
connect mshrs_4.io.sinke.valid, _mshrs_4_io_sinke_valid_T_1
connect mshrs_4.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_4.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_4.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_4.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_4.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_4.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_4.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_4.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_4.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_4.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_4.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_4.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_4.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_4.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_4.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_4.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_4.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_4.io.nestedwb.tag, nestedwb.tag
connect mshrs_4.io.nestedwb.set, nestedwb.set
node _mshrs_5_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_5.io.status.bits.set)
node _mshrs_5_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_5_io_sinkc_valid_T)
connect mshrs_5.io.sinkc.valid, _mshrs_5_io_sinkc_valid_T_1
node _mshrs_5_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<3>(0h5))
node _mshrs_5_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_5_io_sinkd_valid_T)
connect mshrs_5.io.sinkd.valid, _mshrs_5_io_sinkd_valid_T_1
node _mshrs_5_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<3>(0h5))
node _mshrs_5_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_5_io_sinke_valid_T)
connect mshrs_5.io.sinke.valid, _mshrs_5_io_sinke_valid_T_1
connect mshrs_5.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_5.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_5.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_5.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_5.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_5.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_5.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_5.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_5.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_5.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_5.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_5.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_5.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_5.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_5.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_5.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_5.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_5.io.nestedwb.tag, nestedwb.tag
connect mshrs_5.io.nestedwb.set, nestedwb.set
node _mshrs_6_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_6.io.status.bits.set)
node _mshrs_6_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_6_io_sinkc_valid_T)
connect mshrs_6.io.sinkc.valid, _mshrs_6_io_sinkc_valid_T_1
node _mshrs_6_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<3>(0h6))
node _mshrs_6_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_6_io_sinkd_valid_T)
connect mshrs_6.io.sinkd.valid, _mshrs_6_io_sinkd_valid_T_1
node _mshrs_6_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<3>(0h6))
node _mshrs_6_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_6_io_sinke_valid_T)
connect mshrs_6.io.sinke.valid, _mshrs_6_io_sinke_valid_T_1
connect mshrs_6.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_6.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_6.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_6.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_6.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_6.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_6.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_6.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_6.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_6.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_6.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_6.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_6.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_6.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_6.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_6.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_6.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_6.io.nestedwb.tag, nestedwb.tag
connect mshrs_6.io.nestedwb.set, nestedwb.set
node _mshrs_7_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_7.io.status.bits.set)
node _mshrs_7_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_7_io_sinkc_valid_T)
connect mshrs_7.io.sinkc.valid, _mshrs_7_io_sinkc_valid_T_1
node _mshrs_7_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<3>(0h7))
node _mshrs_7_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_7_io_sinkd_valid_T)
connect mshrs_7.io.sinkd.valid, _mshrs_7_io_sinkd_valid_T_1
node _mshrs_7_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<3>(0h7))
node _mshrs_7_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_7_io_sinke_valid_T)
connect mshrs_7.io.sinke.valid, _mshrs_7_io_sinke_valid_T_1
connect mshrs_7.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_7.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_7.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_7.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_7.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_7.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_7.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_7.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_7.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_7.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_7.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_7.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_7.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_7.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_7.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_7.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_7.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_7.io.nestedwb.tag, nestedwb.tag
connect mshrs_7.io.nestedwb.set, nestedwb.set
node _mshrs_8_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_8.io.status.bits.set)
node _mshrs_8_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_8_io_sinkc_valid_T)
connect mshrs_8.io.sinkc.valid, _mshrs_8_io_sinkc_valid_T_1
node _mshrs_8_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<4>(0h8))
node _mshrs_8_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_8_io_sinkd_valid_T)
connect mshrs_8.io.sinkd.valid, _mshrs_8_io_sinkd_valid_T_1
node _mshrs_8_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<4>(0h8))
node _mshrs_8_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_8_io_sinke_valid_T)
connect mshrs_8.io.sinke.valid, _mshrs_8_io_sinke_valid_T_1
connect mshrs_8.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_8.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_8.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_8.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_8.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_8.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_8.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_8.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_8.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_8.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_8.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_8.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_8.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_8.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_8.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_8.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_8.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_8.io.nestedwb.tag, nestedwb.tag
connect mshrs_8.io.nestedwb.set, nestedwb.set
node _mshrs_9_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_9.io.status.bits.set)
node _mshrs_9_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_9_io_sinkc_valid_T)
connect mshrs_9.io.sinkc.valid, _mshrs_9_io_sinkc_valid_T_1
node _mshrs_9_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<4>(0h9))
node _mshrs_9_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_9_io_sinkd_valid_T)
connect mshrs_9.io.sinkd.valid, _mshrs_9_io_sinkd_valid_T_1
node _mshrs_9_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<4>(0h9))
node _mshrs_9_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_9_io_sinke_valid_T)
connect mshrs_9.io.sinke.valid, _mshrs_9_io_sinke_valid_T_1
connect mshrs_9.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_9.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_9.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_9.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_9.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_9.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_9.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_9.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_9.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_9.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_9.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_9.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_9.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_9.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_9.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_9.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_9.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_9.io.nestedwb.tag, nestedwb.tag
connect mshrs_9.io.nestedwb.set, nestedwb.set
node _mshrs_10_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_10.io.status.bits.set)
node _mshrs_10_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_10_io_sinkc_valid_T)
connect mshrs_10.io.sinkc.valid, _mshrs_10_io_sinkc_valid_T_1
node _mshrs_10_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<4>(0ha))
node _mshrs_10_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_10_io_sinkd_valid_T)
connect mshrs_10.io.sinkd.valid, _mshrs_10_io_sinkd_valid_T_1
node _mshrs_10_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<4>(0ha))
node _mshrs_10_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_10_io_sinke_valid_T)
connect mshrs_10.io.sinke.valid, _mshrs_10_io_sinke_valid_T_1
connect mshrs_10.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_10.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_10.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_10.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_10.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_10.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_10.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_10.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_10.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_10.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_10.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_10.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_10.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_10.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_10.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_10.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_10.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_10.io.nestedwb.tag, nestedwb.tag
connect mshrs_10.io.nestedwb.set, nestedwb.set
node _mshrs_11_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_11.io.status.bits.set)
node _mshrs_11_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_11_io_sinkc_valid_T)
connect mshrs_11.io.sinkc.valid, _mshrs_11_io_sinkc_valid_T_1
node _mshrs_11_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<4>(0hb))
node _mshrs_11_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_11_io_sinkd_valid_T)
connect mshrs_11.io.sinkd.valid, _mshrs_11_io_sinkd_valid_T_1
node _mshrs_11_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<4>(0hb))
node _mshrs_11_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_11_io_sinke_valid_T)
connect mshrs_11.io.sinke.valid, _mshrs_11_io_sinke_valid_T_1
connect mshrs_11.io.sinkc.bits.data, sinkC.io.resp.bits.data
connect mshrs_11.io.sinkc.bits.param, sinkC.io.resp.bits.param
connect mshrs_11.io.sinkc.bits.source, sinkC.io.resp.bits.source
connect mshrs_11.io.sinkc.bits.tag, sinkC.io.resp.bits.tag
connect mshrs_11.io.sinkc.bits.set, sinkC.io.resp.bits.set
connect mshrs_11.io.sinkc.bits.last, sinkC.io.resp.bits.last
connect mshrs_11.io.sinkd.bits.denied, sinkD.io.resp.bits.denied
connect mshrs_11.io.sinkd.bits.sink, sinkD.io.resp.bits.sink
connect mshrs_11.io.sinkd.bits.source, sinkD.io.resp.bits.source
connect mshrs_11.io.sinkd.bits.param, sinkD.io.resp.bits.param
connect mshrs_11.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode
connect mshrs_11.io.sinkd.bits.last, sinkD.io.resp.bits.last
connect mshrs_11.io.sinke.bits.sink, sinkE.io.resp.bits.sink
connect mshrs_11.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty
connect mshrs_11.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty
connect mshrs_11.io.nestedwb.b_toB, nestedwb.b_toB
connect mshrs_11.io.nestedwb.b_toN, nestedwb.b_toN
connect mshrs_11.io.nestedwb.tag, nestedwb.tag
connect mshrs_11.io.nestedwb.set, nestedwb.set
node _mshr_stall_abc_T = eq(mshrs_0.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_1 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T)
node _mshr_stall_abc_T_2 = eq(mshrs_0.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_3 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_2)
node mshr_stall_abc_0 = or(_mshr_stall_abc_T_1, _mshr_stall_abc_T_3)
node _mshr_stall_abc_T_4 = eq(mshrs_1.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_5 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_4)
node _mshr_stall_abc_T_6 = eq(mshrs_1.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_7 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_6)
node mshr_stall_abc_1 = or(_mshr_stall_abc_T_5, _mshr_stall_abc_T_7)
node _mshr_stall_abc_T_8 = eq(mshrs_2.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_9 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_8)
node _mshr_stall_abc_T_10 = eq(mshrs_2.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_11 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_10)
node mshr_stall_abc_2 = or(_mshr_stall_abc_T_9, _mshr_stall_abc_T_11)
node _mshr_stall_abc_T_12 = eq(mshrs_3.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_13 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_12)
node _mshr_stall_abc_T_14 = eq(mshrs_3.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_15 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_14)
node mshr_stall_abc_3 = or(_mshr_stall_abc_T_13, _mshr_stall_abc_T_15)
node _mshr_stall_abc_T_16 = eq(mshrs_4.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_17 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_16)
node _mshr_stall_abc_T_18 = eq(mshrs_4.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_19 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_18)
node mshr_stall_abc_4 = or(_mshr_stall_abc_T_17, _mshr_stall_abc_T_19)
node _mshr_stall_abc_T_20 = eq(mshrs_5.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_21 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_20)
node _mshr_stall_abc_T_22 = eq(mshrs_5.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_23 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_22)
node mshr_stall_abc_5 = or(_mshr_stall_abc_T_21, _mshr_stall_abc_T_23)
node _mshr_stall_abc_T_24 = eq(mshrs_6.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_25 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_24)
node _mshr_stall_abc_T_26 = eq(mshrs_6.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_27 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_26)
node mshr_stall_abc_6 = or(_mshr_stall_abc_T_25, _mshr_stall_abc_T_27)
node _mshr_stall_abc_T_28 = eq(mshrs_7.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_29 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_28)
node _mshr_stall_abc_T_30 = eq(mshrs_7.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_31 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_30)
node mshr_stall_abc_7 = or(_mshr_stall_abc_T_29, _mshr_stall_abc_T_31)
node _mshr_stall_abc_T_32 = eq(mshrs_8.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_33 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_32)
node _mshr_stall_abc_T_34 = eq(mshrs_8.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_35 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_34)
node mshr_stall_abc_8 = or(_mshr_stall_abc_T_33, _mshr_stall_abc_T_35)
node _mshr_stall_abc_T_36 = eq(mshrs_9.io.status.bits.set, mshrs_10.io.status.bits.set)
node _mshr_stall_abc_T_37 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_36)
node _mshr_stall_abc_T_38 = eq(mshrs_9.io.status.bits.set, mshrs_11.io.status.bits.set)
node _mshr_stall_abc_T_39 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_38)
node mshr_stall_abc_9 = or(_mshr_stall_abc_T_37, _mshr_stall_abc_T_39)
node _mshr_stall_bc_T = eq(mshrs_10.io.status.bits.set, mshrs_11.io.status.bits.set)
node mshr_stall_bc = and(mshrs_11.io.status.valid, _mshr_stall_bc_T)
node stall_abc_0 = and(mshr_stall_abc_0, mshrs_0.io.status.valid)
node stall_abc_1 = and(mshr_stall_abc_1, mshrs_1.io.status.valid)
node stall_abc_2 = and(mshr_stall_abc_2, mshrs_2.io.status.valid)
node stall_abc_3 = and(mshr_stall_abc_3, mshrs_3.io.status.valid)
node stall_abc_4 = and(mshr_stall_abc_4, mshrs_4.io.status.valid)
node stall_abc_5 = and(mshr_stall_abc_5, mshrs_5.io.status.valid)
node stall_abc_6 = and(mshr_stall_abc_6, mshrs_6.io.status.valid)
node stall_abc_7 = and(mshr_stall_abc_7, mshrs_7.io.status.valid)
node stall_abc_8 = and(mshr_stall_abc_8, mshrs_8.io.status.valid)
node stall_abc_9 = and(mshr_stall_abc_9, mshrs_9.io.status.valid)
node _T = or(stall_abc_0, stall_abc_1)
node _T_1 = or(_T, stall_abc_2)
node _T_2 = or(_T_1, stall_abc_3)
node _T_3 = or(_T_2, stall_abc_4)
node _T_4 = or(_T_3, stall_abc_5)
node _T_5 = or(_T_4, stall_abc_6)
node _T_6 = or(_T_5, stall_abc_7)
node _T_7 = or(_T_6, stall_abc_8)
node _T_8 = or(_T_7, stall_abc_9)
node _mshr_request_T = eq(mshr_stall_abc_0, UInt<1>(0h0))
node _mshr_request_T_1 = and(mshrs_0.io.schedule.valid, _mshr_request_T)
node _mshr_request_T_2 = eq(mshrs_0.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_3 = or(sourceA.io.req.ready, _mshr_request_T_2)
node _mshr_request_T_4 = and(_mshr_request_T_1, _mshr_request_T_3)
node _mshr_request_T_5 = eq(mshrs_0.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_6 = or(sourceB.io.req.ready, _mshr_request_T_5)
node _mshr_request_T_7 = and(_mshr_request_T_4, _mshr_request_T_6)
node _mshr_request_T_8 = eq(mshrs_0.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_9 = or(sourceC.io.req.ready, _mshr_request_T_8)
node _mshr_request_T_10 = and(_mshr_request_T_7, _mshr_request_T_9)
node _mshr_request_T_11 = eq(mshrs_0.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_12 = or(sourceD.io.req.ready, _mshr_request_T_11)
node _mshr_request_T_13 = and(_mshr_request_T_10, _mshr_request_T_12)
node _mshr_request_T_14 = eq(mshrs_0.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_15 = or(sourceE.io.req.ready, _mshr_request_T_14)
node _mshr_request_T_16 = and(_mshr_request_T_13, _mshr_request_T_15)
node _mshr_request_T_17 = eq(mshrs_0.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_18 = or(sourceX.io.req.ready, _mshr_request_T_17)
node _mshr_request_T_19 = and(_mshr_request_T_16, _mshr_request_T_18)
node _mshr_request_T_20 = eq(mshrs_0.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_21 = or(directory.io.write.ready, _mshr_request_T_20)
node _mshr_request_T_22 = and(_mshr_request_T_19, _mshr_request_T_21)
node _mshr_request_T_23 = eq(mshr_stall_abc_1, UInt<1>(0h0))
node _mshr_request_T_24 = and(mshrs_1.io.schedule.valid, _mshr_request_T_23)
node _mshr_request_T_25 = eq(mshrs_1.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_26 = or(sourceA.io.req.ready, _mshr_request_T_25)
node _mshr_request_T_27 = and(_mshr_request_T_24, _mshr_request_T_26)
node _mshr_request_T_28 = eq(mshrs_1.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_29 = or(sourceB.io.req.ready, _mshr_request_T_28)
node _mshr_request_T_30 = and(_mshr_request_T_27, _mshr_request_T_29)
node _mshr_request_T_31 = eq(mshrs_1.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_32 = or(sourceC.io.req.ready, _mshr_request_T_31)
node _mshr_request_T_33 = and(_mshr_request_T_30, _mshr_request_T_32)
node _mshr_request_T_34 = eq(mshrs_1.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_35 = or(sourceD.io.req.ready, _mshr_request_T_34)
node _mshr_request_T_36 = and(_mshr_request_T_33, _mshr_request_T_35)
node _mshr_request_T_37 = eq(mshrs_1.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_38 = or(sourceE.io.req.ready, _mshr_request_T_37)
node _mshr_request_T_39 = and(_mshr_request_T_36, _mshr_request_T_38)
node _mshr_request_T_40 = eq(mshrs_1.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_41 = or(sourceX.io.req.ready, _mshr_request_T_40)
node _mshr_request_T_42 = and(_mshr_request_T_39, _mshr_request_T_41)
node _mshr_request_T_43 = eq(mshrs_1.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_44 = or(directory.io.write.ready, _mshr_request_T_43)
node _mshr_request_T_45 = and(_mshr_request_T_42, _mshr_request_T_44)
node _mshr_request_T_46 = eq(mshr_stall_abc_2, UInt<1>(0h0))
node _mshr_request_T_47 = and(mshrs_2.io.schedule.valid, _mshr_request_T_46)
node _mshr_request_T_48 = eq(mshrs_2.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_49 = or(sourceA.io.req.ready, _mshr_request_T_48)
node _mshr_request_T_50 = and(_mshr_request_T_47, _mshr_request_T_49)
node _mshr_request_T_51 = eq(mshrs_2.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_52 = or(sourceB.io.req.ready, _mshr_request_T_51)
node _mshr_request_T_53 = and(_mshr_request_T_50, _mshr_request_T_52)
node _mshr_request_T_54 = eq(mshrs_2.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_55 = or(sourceC.io.req.ready, _mshr_request_T_54)
node _mshr_request_T_56 = and(_mshr_request_T_53, _mshr_request_T_55)
node _mshr_request_T_57 = eq(mshrs_2.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_58 = or(sourceD.io.req.ready, _mshr_request_T_57)
node _mshr_request_T_59 = and(_mshr_request_T_56, _mshr_request_T_58)
node _mshr_request_T_60 = eq(mshrs_2.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_61 = or(sourceE.io.req.ready, _mshr_request_T_60)
node _mshr_request_T_62 = and(_mshr_request_T_59, _mshr_request_T_61)
node _mshr_request_T_63 = eq(mshrs_2.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_64 = or(sourceX.io.req.ready, _mshr_request_T_63)
node _mshr_request_T_65 = and(_mshr_request_T_62, _mshr_request_T_64)
node _mshr_request_T_66 = eq(mshrs_2.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_67 = or(directory.io.write.ready, _mshr_request_T_66)
node _mshr_request_T_68 = and(_mshr_request_T_65, _mshr_request_T_67)
node _mshr_request_T_69 = eq(mshr_stall_abc_3, UInt<1>(0h0))
node _mshr_request_T_70 = and(mshrs_3.io.schedule.valid, _mshr_request_T_69)
node _mshr_request_T_71 = eq(mshrs_3.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_72 = or(sourceA.io.req.ready, _mshr_request_T_71)
node _mshr_request_T_73 = and(_mshr_request_T_70, _mshr_request_T_72)
node _mshr_request_T_74 = eq(mshrs_3.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_75 = or(sourceB.io.req.ready, _mshr_request_T_74)
node _mshr_request_T_76 = and(_mshr_request_T_73, _mshr_request_T_75)
node _mshr_request_T_77 = eq(mshrs_3.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_78 = or(sourceC.io.req.ready, _mshr_request_T_77)
node _mshr_request_T_79 = and(_mshr_request_T_76, _mshr_request_T_78)
node _mshr_request_T_80 = eq(mshrs_3.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_81 = or(sourceD.io.req.ready, _mshr_request_T_80)
node _mshr_request_T_82 = and(_mshr_request_T_79, _mshr_request_T_81)
node _mshr_request_T_83 = eq(mshrs_3.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_84 = or(sourceE.io.req.ready, _mshr_request_T_83)
node _mshr_request_T_85 = and(_mshr_request_T_82, _mshr_request_T_84)
node _mshr_request_T_86 = eq(mshrs_3.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_87 = or(sourceX.io.req.ready, _mshr_request_T_86)
node _mshr_request_T_88 = and(_mshr_request_T_85, _mshr_request_T_87)
node _mshr_request_T_89 = eq(mshrs_3.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_90 = or(directory.io.write.ready, _mshr_request_T_89)
node _mshr_request_T_91 = and(_mshr_request_T_88, _mshr_request_T_90)
node _mshr_request_T_92 = eq(mshr_stall_abc_4, UInt<1>(0h0))
node _mshr_request_T_93 = and(mshrs_4.io.schedule.valid, _mshr_request_T_92)
node _mshr_request_T_94 = eq(mshrs_4.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_95 = or(sourceA.io.req.ready, _mshr_request_T_94)
node _mshr_request_T_96 = and(_mshr_request_T_93, _mshr_request_T_95)
node _mshr_request_T_97 = eq(mshrs_4.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_98 = or(sourceB.io.req.ready, _mshr_request_T_97)
node _mshr_request_T_99 = and(_mshr_request_T_96, _mshr_request_T_98)
node _mshr_request_T_100 = eq(mshrs_4.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_101 = or(sourceC.io.req.ready, _mshr_request_T_100)
node _mshr_request_T_102 = and(_mshr_request_T_99, _mshr_request_T_101)
node _mshr_request_T_103 = eq(mshrs_4.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_104 = or(sourceD.io.req.ready, _mshr_request_T_103)
node _mshr_request_T_105 = and(_mshr_request_T_102, _mshr_request_T_104)
node _mshr_request_T_106 = eq(mshrs_4.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_107 = or(sourceE.io.req.ready, _mshr_request_T_106)
node _mshr_request_T_108 = and(_mshr_request_T_105, _mshr_request_T_107)
node _mshr_request_T_109 = eq(mshrs_4.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_110 = or(sourceX.io.req.ready, _mshr_request_T_109)
node _mshr_request_T_111 = and(_mshr_request_T_108, _mshr_request_T_110)
node _mshr_request_T_112 = eq(mshrs_4.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_113 = or(directory.io.write.ready, _mshr_request_T_112)
node _mshr_request_T_114 = and(_mshr_request_T_111, _mshr_request_T_113)
node _mshr_request_T_115 = eq(mshr_stall_abc_5, UInt<1>(0h0))
node _mshr_request_T_116 = and(mshrs_5.io.schedule.valid, _mshr_request_T_115)
node _mshr_request_T_117 = eq(mshrs_5.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_118 = or(sourceA.io.req.ready, _mshr_request_T_117)
node _mshr_request_T_119 = and(_mshr_request_T_116, _mshr_request_T_118)
node _mshr_request_T_120 = eq(mshrs_5.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_121 = or(sourceB.io.req.ready, _mshr_request_T_120)
node _mshr_request_T_122 = and(_mshr_request_T_119, _mshr_request_T_121)
node _mshr_request_T_123 = eq(mshrs_5.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_124 = or(sourceC.io.req.ready, _mshr_request_T_123)
node _mshr_request_T_125 = and(_mshr_request_T_122, _mshr_request_T_124)
node _mshr_request_T_126 = eq(mshrs_5.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_127 = or(sourceD.io.req.ready, _mshr_request_T_126)
node _mshr_request_T_128 = and(_mshr_request_T_125, _mshr_request_T_127)
node _mshr_request_T_129 = eq(mshrs_5.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_130 = or(sourceE.io.req.ready, _mshr_request_T_129)
node _mshr_request_T_131 = and(_mshr_request_T_128, _mshr_request_T_130)
node _mshr_request_T_132 = eq(mshrs_5.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_133 = or(sourceX.io.req.ready, _mshr_request_T_132)
node _mshr_request_T_134 = and(_mshr_request_T_131, _mshr_request_T_133)
node _mshr_request_T_135 = eq(mshrs_5.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_136 = or(directory.io.write.ready, _mshr_request_T_135)
node _mshr_request_T_137 = and(_mshr_request_T_134, _mshr_request_T_136)
node _mshr_request_T_138 = eq(mshr_stall_abc_6, UInt<1>(0h0))
node _mshr_request_T_139 = and(mshrs_6.io.schedule.valid, _mshr_request_T_138)
node _mshr_request_T_140 = eq(mshrs_6.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_141 = or(sourceA.io.req.ready, _mshr_request_T_140)
node _mshr_request_T_142 = and(_mshr_request_T_139, _mshr_request_T_141)
node _mshr_request_T_143 = eq(mshrs_6.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_144 = or(sourceB.io.req.ready, _mshr_request_T_143)
node _mshr_request_T_145 = and(_mshr_request_T_142, _mshr_request_T_144)
node _mshr_request_T_146 = eq(mshrs_6.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_147 = or(sourceC.io.req.ready, _mshr_request_T_146)
node _mshr_request_T_148 = and(_mshr_request_T_145, _mshr_request_T_147)
node _mshr_request_T_149 = eq(mshrs_6.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_150 = or(sourceD.io.req.ready, _mshr_request_T_149)
node _mshr_request_T_151 = and(_mshr_request_T_148, _mshr_request_T_150)
node _mshr_request_T_152 = eq(mshrs_6.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_153 = or(sourceE.io.req.ready, _mshr_request_T_152)
node _mshr_request_T_154 = and(_mshr_request_T_151, _mshr_request_T_153)
node _mshr_request_T_155 = eq(mshrs_6.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_156 = or(sourceX.io.req.ready, _mshr_request_T_155)
node _mshr_request_T_157 = and(_mshr_request_T_154, _mshr_request_T_156)
node _mshr_request_T_158 = eq(mshrs_6.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_159 = or(directory.io.write.ready, _mshr_request_T_158)
node _mshr_request_T_160 = and(_mshr_request_T_157, _mshr_request_T_159)
node _mshr_request_T_161 = eq(mshr_stall_abc_7, UInt<1>(0h0))
node _mshr_request_T_162 = and(mshrs_7.io.schedule.valid, _mshr_request_T_161)
node _mshr_request_T_163 = eq(mshrs_7.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_164 = or(sourceA.io.req.ready, _mshr_request_T_163)
node _mshr_request_T_165 = and(_mshr_request_T_162, _mshr_request_T_164)
node _mshr_request_T_166 = eq(mshrs_7.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_167 = or(sourceB.io.req.ready, _mshr_request_T_166)
node _mshr_request_T_168 = and(_mshr_request_T_165, _mshr_request_T_167)
node _mshr_request_T_169 = eq(mshrs_7.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_170 = or(sourceC.io.req.ready, _mshr_request_T_169)
node _mshr_request_T_171 = and(_mshr_request_T_168, _mshr_request_T_170)
node _mshr_request_T_172 = eq(mshrs_7.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_173 = or(sourceD.io.req.ready, _mshr_request_T_172)
node _mshr_request_T_174 = and(_mshr_request_T_171, _mshr_request_T_173)
node _mshr_request_T_175 = eq(mshrs_7.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_176 = or(sourceE.io.req.ready, _mshr_request_T_175)
node _mshr_request_T_177 = and(_mshr_request_T_174, _mshr_request_T_176)
node _mshr_request_T_178 = eq(mshrs_7.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_179 = or(sourceX.io.req.ready, _mshr_request_T_178)
node _mshr_request_T_180 = and(_mshr_request_T_177, _mshr_request_T_179)
node _mshr_request_T_181 = eq(mshrs_7.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_182 = or(directory.io.write.ready, _mshr_request_T_181)
node _mshr_request_T_183 = and(_mshr_request_T_180, _mshr_request_T_182)
node _mshr_request_T_184 = eq(mshr_stall_abc_8, UInt<1>(0h0))
node _mshr_request_T_185 = and(mshrs_8.io.schedule.valid, _mshr_request_T_184)
node _mshr_request_T_186 = eq(mshrs_8.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_187 = or(sourceA.io.req.ready, _mshr_request_T_186)
node _mshr_request_T_188 = and(_mshr_request_T_185, _mshr_request_T_187)
node _mshr_request_T_189 = eq(mshrs_8.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_190 = or(sourceB.io.req.ready, _mshr_request_T_189)
node _mshr_request_T_191 = and(_mshr_request_T_188, _mshr_request_T_190)
node _mshr_request_T_192 = eq(mshrs_8.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_193 = or(sourceC.io.req.ready, _mshr_request_T_192)
node _mshr_request_T_194 = and(_mshr_request_T_191, _mshr_request_T_193)
node _mshr_request_T_195 = eq(mshrs_8.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_196 = or(sourceD.io.req.ready, _mshr_request_T_195)
node _mshr_request_T_197 = and(_mshr_request_T_194, _mshr_request_T_196)
node _mshr_request_T_198 = eq(mshrs_8.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_199 = or(sourceE.io.req.ready, _mshr_request_T_198)
node _mshr_request_T_200 = and(_mshr_request_T_197, _mshr_request_T_199)
node _mshr_request_T_201 = eq(mshrs_8.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_202 = or(sourceX.io.req.ready, _mshr_request_T_201)
node _mshr_request_T_203 = and(_mshr_request_T_200, _mshr_request_T_202)
node _mshr_request_T_204 = eq(mshrs_8.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_205 = or(directory.io.write.ready, _mshr_request_T_204)
node _mshr_request_T_206 = and(_mshr_request_T_203, _mshr_request_T_205)
node _mshr_request_T_207 = eq(mshr_stall_abc_9, UInt<1>(0h0))
node _mshr_request_T_208 = and(mshrs_9.io.schedule.valid, _mshr_request_T_207)
node _mshr_request_T_209 = eq(mshrs_9.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_210 = or(sourceA.io.req.ready, _mshr_request_T_209)
node _mshr_request_T_211 = and(_mshr_request_T_208, _mshr_request_T_210)
node _mshr_request_T_212 = eq(mshrs_9.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_213 = or(sourceB.io.req.ready, _mshr_request_T_212)
node _mshr_request_T_214 = and(_mshr_request_T_211, _mshr_request_T_213)
node _mshr_request_T_215 = eq(mshrs_9.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_216 = or(sourceC.io.req.ready, _mshr_request_T_215)
node _mshr_request_T_217 = and(_mshr_request_T_214, _mshr_request_T_216)
node _mshr_request_T_218 = eq(mshrs_9.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_219 = or(sourceD.io.req.ready, _mshr_request_T_218)
node _mshr_request_T_220 = and(_mshr_request_T_217, _mshr_request_T_219)
node _mshr_request_T_221 = eq(mshrs_9.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_222 = or(sourceE.io.req.ready, _mshr_request_T_221)
node _mshr_request_T_223 = and(_mshr_request_T_220, _mshr_request_T_222)
node _mshr_request_T_224 = eq(mshrs_9.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_225 = or(sourceX.io.req.ready, _mshr_request_T_224)
node _mshr_request_T_226 = and(_mshr_request_T_223, _mshr_request_T_225)
node _mshr_request_T_227 = eq(mshrs_9.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_228 = or(directory.io.write.ready, _mshr_request_T_227)
node _mshr_request_T_229 = and(_mshr_request_T_226, _mshr_request_T_228)
node _mshr_request_T_230 = eq(mshr_stall_bc, UInt<1>(0h0))
node _mshr_request_T_231 = and(mshrs_10.io.schedule.valid, _mshr_request_T_230)
node _mshr_request_T_232 = eq(mshrs_10.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_233 = or(sourceA.io.req.ready, _mshr_request_T_232)
node _mshr_request_T_234 = and(_mshr_request_T_231, _mshr_request_T_233)
node _mshr_request_T_235 = eq(mshrs_10.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_236 = or(sourceB.io.req.ready, _mshr_request_T_235)
node _mshr_request_T_237 = and(_mshr_request_T_234, _mshr_request_T_236)
node _mshr_request_T_238 = eq(mshrs_10.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_239 = or(sourceC.io.req.ready, _mshr_request_T_238)
node _mshr_request_T_240 = and(_mshr_request_T_237, _mshr_request_T_239)
node _mshr_request_T_241 = eq(mshrs_10.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_242 = or(sourceD.io.req.ready, _mshr_request_T_241)
node _mshr_request_T_243 = and(_mshr_request_T_240, _mshr_request_T_242)
node _mshr_request_T_244 = eq(mshrs_10.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_245 = or(sourceE.io.req.ready, _mshr_request_T_244)
node _mshr_request_T_246 = and(_mshr_request_T_243, _mshr_request_T_245)
node _mshr_request_T_247 = eq(mshrs_10.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_248 = or(sourceX.io.req.ready, _mshr_request_T_247)
node _mshr_request_T_249 = and(_mshr_request_T_246, _mshr_request_T_248)
node _mshr_request_T_250 = eq(mshrs_10.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_251 = or(directory.io.write.ready, _mshr_request_T_250)
node _mshr_request_T_252 = and(_mshr_request_T_249, _mshr_request_T_251)
node _mshr_request_T_253 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _mshr_request_T_254 = and(mshrs_11.io.schedule.valid, _mshr_request_T_253)
node _mshr_request_T_255 = eq(mshrs_11.io.schedule.bits.a.valid, UInt<1>(0h0))
node _mshr_request_T_256 = or(sourceA.io.req.ready, _mshr_request_T_255)
node _mshr_request_T_257 = and(_mshr_request_T_254, _mshr_request_T_256)
node _mshr_request_T_258 = eq(mshrs_11.io.schedule.bits.b.valid, UInt<1>(0h0))
node _mshr_request_T_259 = or(sourceB.io.req.ready, _mshr_request_T_258)
node _mshr_request_T_260 = and(_mshr_request_T_257, _mshr_request_T_259)
node _mshr_request_T_261 = eq(mshrs_11.io.schedule.bits.c.valid, UInt<1>(0h0))
node _mshr_request_T_262 = or(sourceC.io.req.ready, _mshr_request_T_261)
node _mshr_request_T_263 = and(_mshr_request_T_260, _mshr_request_T_262)
node _mshr_request_T_264 = eq(mshrs_11.io.schedule.bits.d.valid, UInt<1>(0h0))
node _mshr_request_T_265 = or(sourceD.io.req.ready, _mshr_request_T_264)
node _mshr_request_T_266 = and(_mshr_request_T_263, _mshr_request_T_265)
node _mshr_request_T_267 = eq(mshrs_11.io.schedule.bits.e.valid, UInt<1>(0h0))
node _mshr_request_T_268 = or(sourceE.io.req.ready, _mshr_request_T_267)
node _mshr_request_T_269 = and(_mshr_request_T_266, _mshr_request_T_268)
node _mshr_request_T_270 = eq(mshrs_11.io.schedule.bits.x.valid, UInt<1>(0h0))
node _mshr_request_T_271 = or(sourceX.io.req.ready, _mshr_request_T_270)
node _mshr_request_T_272 = and(_mshr_request_T_269, _mshr_request_T_271)
node _mshr_request_T_273 = eq(mshrs_11.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _mshr_request_T_274 = or(directory.io.write.ready, _mshr_request_T_273)
node _mshr_request_T_275 = and(_mshr_request_T_272, _mshr_request_T_274)
node mshr_request_lo_lo_hi = cat(_mshr_request_T_68, _mshr_request_T_45)
node mshr_request_lo_lo = cat(mshr_request_lo_lo_hi, _mshr_request_T_22)
node mshr_request_lo_hi_hi = cat(_mshr_request_T_137, _mshr_request_T_114)
node mshr_request_lo_hi = cat(mshr_request_lo_hi_hi, _mshr_request_T_91)
node mshr_request_lo = cat(mshr_request_lo_hi, mshr_request_lo_lo)
node mshr_request_hi_lo_hi = cat(_mshr_request_T_206, _mshr_request_T_183)
node mshr_request_hi_lo = cat(mshr_request_hi_lo_hi, _mshr_request_T_160)
node mshr_request_hi_hi_hi = cat(_mshr_request_T_275, _mshr_request_T_252)
node mshr_request_hi_hi = cat(mshr_request_hi_hi_hi, _mshr_request_T_229)
node mshr_request_hi = cat(mshr_request_hi_hi, mshr_request_hi_lo)
node mshr_request = cat(mshr_request_hi, mshr_request_lo)
regreset robin_filter : UInt<12>, clock, reset, UInt<12>(0h0)
node _robin_request_T = and(mshr_request, robin_filter)
node robin_request = cat(mshr_request, _robin_request_T)
node _mshr_selectOH2_T = shl(robin_request, 1)
node _mshr_selectOH2_T_1 = bits(_mshr_selectOH2_T, 23, 0)
node _mshr_selectOH2_T_2 = or(robin_request, _mshr_selectOH2_T_1)
node _mshr_selectOH2_T_3 = shl(_mshr_selectOH2_T_2, 2)
node _mshr_selectOH2_T_4 = bits(_mshr_selectOH2_T_3, 23, 0)
node _mshr_selectOH2_T_5 = or(_mshr_selectOH2_T_2, _mshr_selectOH2_T_4)
node _mshr_selectOH2_T_6 = shl(_mshr_selectOH2_T_5, 4)
node _mshr_selectOH2_T_7 = bits(_mshr_selectOH2_T_6, 23, 0)
node _mshr_selectOH2_T_8 = or(_mshr_selectOH2_T_5, _mshr_selectOH2_T_7)
node _mshr_selectOH2_T_9 = shl(_mshr_selectOH2_T_8, 8)
node _mshr_selectOH2_T_10 = bits(_mshr_selectOH2_T_9, 23, 0)
node _mshr_selectOH2_T_11 = or(_mshr_selectOH2_T_8, _mshr_selectOH2_T_10)
node _mshr_selectOH2_T_12 = shl(_mshr_selectOH2_T_11, 16)
node _mshr_selectOH2_T_13 = bits(_mshr_selectOH2_T_12, 23, 0)
node _mshr_selectOH2_T_14 = or(_mshr_selectOH2_T_11, _mshr_selectOH2_T_13)
node _mshr_selectOH2_T_15 = bits(_mshr_selectOH2_T_14, 23, 0)
node _mshr_selectOH2_T_16 = shl(_mshr_selectOH2_T_15, 1)
node _mshr_selectOH2_T_17 = not(_mshr_selectOH2_T_16)
node mshr_selectOH2 = and(_mshr_selectOH2_T_17, robin_request)
node _mshr_selectOH_T = bits(mshr_selectOH2, 23, 12)
node _mshr_selectOH_T_1 = bits(mshr_selectOH2, 11, 0)
node mshr_selectOH = or(_mshr_selectOH_T, _mshr_selectOH_T_1)
node mshr_select_hi = bits(mshr_selectOH, 11, 8)
node mshr_select_lo = bits(mshr_selectOH, 7, 0)
node _mshr_select_T = orr(mshr_select_hi)
node _mshr_select_T_1 = or(mshr_select_hi, mshr_select_lo)
node mshr_select_hi_1 = bits(_mshr_select_T_1, 7, 4)
node mshr_select_lo_1 = bits(_mshr_select_T_1, 3, 0)
node _mshr_select_T_2 = orr(mshr_select_hi_1)
node _mshr_select_T_3 = or(mshr_select_hi_1, mshr_select_lo_1)
node mshr_select_hi_2 = bits(_mshr_select_T_3, 3, 2)
node mshr_select_lo_2 = bits(_mshr_select_T_3, 1, 0)
node _mshr_select_T_4 = orr(mshr_select_hi_2)
node _mshr_select_T_5 = or(mshr_select_hi_2, mshr_select_lo_2)
node _mshr_select_T_6 = bits(_mshr_select_T_5, 1, 1)
node _mshr_select_T_7 = cat(_mshr_select_T_4, _mshr_select_T_6)
node _mshr_select_T_8 = cat(_mshr_select_T_2, _mshr_select_T_7)
node mshr_select = cat(_mshr_select_T, _mshr_select_T_8)
node _schedule_T = bits(mshr_selectOH, 0, 0)
node _schedule_T_1 = bits(mshr_selectOH, 1, 1)
node _schedule_T_2 = bits(mshr_selectOH, 2, 2)
node _schedule_T_3 = bits(mshr_selectOH, 3, 3)
node _schedule_T_4 = bits(mshr_selectOH, 4, 4)
node _schedule_T_5 = bits(mshr_selectOH, 5, 5)
node _schedule_T_6 = bits(mshr_selectOH, 6, 6)
node _schedule_T_7 = bits(mshr_selectOH, 7, 7)
node _schedule_T_8 = bits(mshr_selectOH, 8, 8)
node _schedule_T_9 = bits(mshr_selectOH, 9, 9)
node _schedule_T_10 = bits(mshr_selectOH, 10, 10)
node _schedule_T_11 = bits(mshr_selectOH, 11, 11)
wire schedule : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<4>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}}}, reload : UInt<1>}
node _schedule_T_12 = mux(_schedule_T, mshrs_0.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_13 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_14 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_15 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_16 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_17 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_18 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_19 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_20 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_21 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_22 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_23 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.reload, UInt<1>(0h0))
node _schedule_T_24 = or(_schedule_T_12, _schedule_T_13)
node _schedule_T_25 = or(_schedule_T_24, _schedule_T_14)
node _schedule_T_26 = or(_schedule_T_25, _schedule_T_15)
node _schedule_T_27 = or(_schedule_T_26, _schedule_T_16)
node _schedule_T_28 = or(_schedule_T_27, _schedule_T_17)
node _schedule_T_29 = or(_schedule_T_28, _schedule_T_18)
node _schedule_T_30 = or(_schedule_T_29, _schedule_T_19)
node _schedule_T_31 = or(_schedule_T_30, _schedule_T_20)
node _schedule_T_32 = or(_schedule_T_31, _schedule_T_21)
node _schedule_T_33 = or(_schedule_T_32, _schedule_T_22)
node _schedule_T_34 = or(_schedule_T_33, _schedule_T_23)
wire _schedule_WIRE : UInt<1>
connect _schedule_WIRE, _schedule_T_34
connect schedule.reload, _schedule_WIRE
wire _schedule_WIRE_1 : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}}}
wire _schedule_WIRE_2 : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}}
wire _schedule_WIRE_3 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}
node _schedule_T_35 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_36 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_37 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_38 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_39 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_40 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_41 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_42 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_43 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_44 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_45 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_46 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0))
node _schedule_T_47 = or(_schedule_T_35, _schedule_T_36)
node _schedule_T_48 = or(_schedule_T_47, _schedule_T_37)
node _schedule_T_49 = or(_schedule_T_48, _schedule_T_38)
node _schedule_T_50 = or(_schedule_T_49, _schedule_T_39)
node _schedule_T_51 = or(_schedule_T_50, _schedule_T_40)
node _schedule_T_52 = or(_schedule_T_51, _schedule_T_41)
node _schedule_T_53 = or(_schedule_T_52, _schedule_T_42)
node _schedule_T_54 = or(_schedule_T_53, _schedule_T_43)
node _schedule_T_55 = or(_schedule_T_54, _schedule_T_44)
node _schedule_T_56 = or(_schedule_T_55, _schedule_T_45)
node _schedule_T_57 = or(_schedule_T_56, _schedule_T_46)
wire _schedule_WIRE_4 : UInt<13>
connect _schedule_WIRE_4, _schedule_T_57
connect _schedule_WIRE_3.tag, _schedule_WIRE_4
node _schedule_T_58 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_59 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_60 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_61 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_62 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_63 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_64 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_65 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_66 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_67 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_68 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_69 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0))
node _schedule_T_70 = or(_schedule_T_58, _schedule_T_59)
node _schedule_T_71 = or(_schedule_T_70, _schedule_T_60)
node _schedule_T_72 = or(_schedule_T_71, _schedule_T_61)
node _schedule_T_73 = or(_schedule_T_72, _schedule_T_62)
node _schedule_T_74 = or(_schedule_T_73, _schedule_T_63)
node _schedule_T_75 = or(_schedule_T_74, _schedule_T_64)
node _schedule_T_76 = or(_schedule_T_75, _schedule_T_65)
node _schedule_T_77 = or(_schedule_T_76, _schedule_T_66)
node _schedule_T_78 = or(_schedule_T_77, _schedule_T_67)
node _schedule_T_79 = or(_schedule_T_78, _schedule_T_68)
node _schedule_T_80 = or(_schedule_T_79, _schedule_T_69)
wire _schedule_WIRE_5 : UInt<1>
connect _schedule_WIRE_5, _schedule_T_80
connect _schedule_WIRE_3.clients, _schedule_WIRE_5
node _schedule_T_81 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_82 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_83 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_84 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_85 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_86 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_87 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_88 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_89 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_90 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_91 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_92 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0))
node _schedule_T_93 = or(_schedule_T_81, _schedule_T_82)
node _schedule_T_94 = or(_schedule_T_93, _schedule_T_83)
node _schedule_T_95 = or(_schedule_T_94, _schedule_T_84)
node _schedule_T_96 = or(_schedule_T_95, _schedule_T_85)
node _schedule_T_97 = or(_schedule_T_96, _schedule_T_86)
node _schedule_T_98 = or(_schedule_T_97, _schedule_T_87)
node _schedule_T_99 = or(_schedule_T_98, _schedule_T_88)
node _schedule_T_100 = or(_schedule_T_99, _schedule_T_89)
node _schedule_T_101 = or(_schedule_T_100, _schedule_T_90)
node _schedule_T_102 = or(_schedule_T_101, _schedule_T_91)
node _schedule_T_103 = or(_schedule_T_102, _schedule_T_92)
wire _schedule_WIRE_6 : UInt<2>
connect _schedule_WIRE_6, _schedule_T_103
connect _schedule_WIRE_3.state, _schedule_WIRE_6
node _schedule_T_104 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_105 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_106 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_107 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_108 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_109 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_110 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_111 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_112 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_113 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_114 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_115 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0))
node _schedule_T_116 = or(_schedule_T_104, _schedule_T_105)
node _schedule_T_117 = or(_schedule_T_116, _schedule_T_106)
node _schedule_T_118 = or(_schedule_T_117, _schedule_T_107)
node _schedule_T_119 = or(_schedule_T_118, _schedule_T_108)
node _schedule_T_120 = or(_schedule_T_119, _schedule_T_109)
node _schedule_T_121 = or(_schedule_T_120, _schedule_T_110)
node _schedule_T_122 = or(_schedule_T_121, _schedule_T_111)
node _schedule_T_123 = or(_schedule_T_122, _schedule_T_112)
node _schedule_T_124 = or(_schedule_T_123, _schedule_T_113)
node _schedule_T_125 = or(_schedule_T_124, _schedule_T_114)
node _schedule_T_126 = or(_schedule_T_125, _schedule_T_115)
wire _schedule_WIRE_7 : UInt<1>
connect _schedule_WIRE_7, _schedule_T_126
connect _schedule_WIRE_3.dirty, _schedule_WIRE_7
connect _schedule_WIRE_2.data, _schedule_WIRE_3
node _schedule_T_127 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_128 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_129 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_130 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_131 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_132 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_133 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_134 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_135 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_136 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_137 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_138 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.way, UInt<1>(0h0))
node _schedule_T_139 = or(_schedule_T_127, _schedule_T_128)
node _schedule_T_140 = or(_schedule_T_139, _schedule_T_129)
node _schedule_T_141 = or(_schedule_T_140, _schedule_T_130)
node _schedule_T_142 = or(_schedule_T_141, _schedule_T_131)
node _schedule_T_143 = or(_schedule_T_142, _schedule_T_132)
node _schedule_T_144 = or(_schedule_T_143, _schedule_T_133)
node _schedule_T_145 = or(_schedule_T_144, _schedule_T_134)
node _schedule_T_146 = or(_schedule_T_145, _schedule_T_135)
node _schedule_T_147 = or(_schedule_T_146, _schedule_T_136)
node _schedule_T_148 = or(_schedule_T_147, _schedule_T_137)
node _schedule_T_149 = or(_schedule_T_148, _schedule_T_138)
wire _schedule_WIRE_8 : UInt<3>
connect _schedule_WIRE_8, _schedule_T_149
connect _schedule_WIRE_2.way, _schedule_WIRE_8
node _schedule_T_150 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_151 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_152 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_153 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_154 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_155 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_156 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_157 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_158 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_159 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_160 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_161 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.set, UInt<1>(0h0))
node _schedule_T_162 = or(_schedule_T_150, _schedule_T_151)
node _schedule_T_163 = or(_schedule_T_162, _schedule_T_152)
node _schedule_T_164 = or(_schedule_T_163, _schedule_T_153)
node _schedule_T_165 = or(_schedule_T_164, _schedule_T_154)
node _schedule_T_166 = or(_schedule_T_165, _schedule_T_155)
node _schedule_T_167 = or(_schedule_T_166, _schedule_T_156)
node _schedule_T_168 = or(_schedule_T_167, _schedule_T_157)
node _schedule_T_169 = or(_schedule_T_168, _schedule_T_158)
node _schedule_T_170 = or(_schedule_T_169, _schedule_T_159)
node _schedule_T_171 = or(_schedule_T_170, _schedule_T_160)
node _schedule_T_172 = or(_schedule_T_171, _schedule_T_161)
wire _schedule_WIRE_9 : UInt<10>
connect _schedule_WIRE_9, _schedule_T_172
connect _schedule_WIRE_2.set, _schedule_WIRE_9
connect _schedule_WIRE_1.bits, _schedule_WIRE_2
node _schedule_T_173 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_174 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_175 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_176 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_177 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_178 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_179 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_180 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_181 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_182 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_183 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_184 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.valid, UInt<1>(0h0))
node _schedule_T_185 = or(_schedule_T_173, _schedule_T_174)
node _schedule_T_186 = or(_schedule_T_185, _schedule_T_175)
node _schedule_T_187 = or(_schedule_T_186, _schedule_T_176)
node _schedule_T_188 = or(_schedule_T_187, _schedule_T_177)
node _schedule_T_189 = or(_schedule_T_188, _schedule_T_178)
node _schedule_T_190 = or(_schedule_T_189, _schedule_T_179)
node _schedule_T_191 = or(_schedule_T_190, _schedule_T_180)
node _schedule_T_192 = or(_schedule_T_191, _schedule_T_181)
node _schedule_T_193 = or(_schedule_T_192, _schedule_T_182)
node _schedule_T_194 = or(_schedule_T_193, _schedule_T_183)
node _schedule_T_195 = or(_schedule_T_194, _schedule_T_184)
wire _schedule_WIRE_10 : UInt<1>
connect _schedule_WIRE_10, _schedule_T_195
connect _schedule_WIRE_1.valid, _schedule_WIRE_10
connect schedule.dir, _schedule_WIRE_1
wire _schedule_WIRE_11 : { valid : UInt<1>, bits : { fail : UInt<1>}}
wire _schedule_WIRE_12 : { fail : UInt<1>}
node _schedule_T_196 = mux(_schedule_T, mshrs_0.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_197 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_198 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_199 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_200 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_201 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_202 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_203 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_204 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_205 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_206 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_207 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.x.bits.fail, UInt<1>(0h0))
node _schedule_T_208 = or(_schedule_T_196, _schedule_T_197)
node _schedule_T_209 = or(_schedule_T_208, _schedule_T_198)
node _schedule_T_210 = or(_schedule_T_209, _schedule_T_199)
node _schedule_T_211 = or(_schedule_T_210, _schedule_T_200)
node _schedule_T_212 = or(_schedule_T_211, _schedule_T_201)
node _schedule_T_213 = or(_schedule_T_212, _schedule_T_202)
node _schedule_T_214 = or(_schedule_T_213, _schedule_T_203)
node _schedule_T_215 = or(_schedule_T_214, _schedule_T_204)
node _schedule_T_216 = or(_schedule_T_215, _schedule_T_205)
node _schedule_T_217 = or(_schedule_T_216, _schedule_T_206)
node _schedule_T_218 = or(_schedule_T_217, _schedule_T_207)
wire _schedule_WIRE_13 : UInt<1>
connect _schedule_WIRE_13, _schedule_T_218
connect _schedule_WIRE_12.fail, _schedule_WIRE_13
connect _schedule_WIRE_11.bits, _schedule_WIRE_12
node _schedule_T_219 = mux(_schedule_T, mshrs_0.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_220 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_221 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_222 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_223 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_224 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_225 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_226 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_227 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_228 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_229 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_230 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.x.valid, UInt<1>(0h0))
node _schedule_T_231 = or(_schedule_T_219, _schedule_T_220)
node _schedule_T_232 = or(_schedule_T_231, _schedule_T_221)
node _schedule_T_233 = or(_schedule_T_232, _schedule_T_222)
node _schedule_T_234 = or(_schedule_T_233, _schedule_T_223)
node _schedule_T_235 = or(_schedule_T_234, _schedule_T_224)
node _schedule_T_236 = or(_schedule_T_235, _schedule_T_225)
node _schedule_T_237 = or(_schedule_T_236, _schedule_T_226)
node _schedule_T_238 = or(_schedule_T_237, _schedule_T_227)
node _schedule_T_239 = or(_schedule_T_238, _schedule_T_228)
node _schedule_T_240 = or(_schedule_T_239, _schedule_T_229)
node _schedule_T_241 = or(_schedule_T_240, _schedule_T_230)
wire _schedule_WIRE_14 : UInt<1>
connect _schedule_WIRE_14, _schedule_T_241
connect _schedule_WIRE_11.valid, _schedule_WIRE_14
connect schedule.x, _schedule_WIRE_11
wire _schedule_WIRE_15 : { valid : UInt<1>, bits : { sink : UInt<3>}}
wire _schedule_WIRE_16 : { sink : UInt<3>}
node _schedule_T_242 = mux(_schedule_T, mshrs_0.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_243 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_244 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_245 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_246 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_247 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_248 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_249 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_250 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_251 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_252 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_253 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.e.bits.sink, UInt<1>(0h0))
node _schedule_T_254 = or(_schedule_T_242, _schedule_T_243)
node _schedule_T_255 = or(_schedule_T_254, _schedule_T_244)
node _schedule_T_256 = or(_schedule_T_255, _schedule_T_245)
node _schedule_T_257 = or(_schedule_T_256, _schedule_T_246)
node _schedule_T_258 = or(_schedule_T_257, _schedule_T_247)
node _schedule_T_259 = or(_schedule_T_258, _schedule_T_248)
node _schedule_T_260 = or(_schedule_T_259, _schedule_T_249)
node _schedule_T_261 = or(_schedule_T_260, _schedule_T_250)
node _schedule_T_262 = or(_schedule_T_261, _schedule_T_251)
node _schedule_T_263 = or(_schedule_T_262, _schedule_T_252)
node _schedule_T_264 = or(_schedule_T_263, _schedule_T_253)
wire _schedule_WIRE_17 : UInt<3>
connect _schedule_WIRE_17, _schedule_T_264
connect _schedule_WIRE_16.sink, _schedule_WIRE_17
connect _schedule_WIRE_15.bits, _schedule_WIRE_16
node _schedule_T_265 = mux(_schedule_T, mshrs_0.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_266 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_267 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_268 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_269 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_270 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_271 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_272 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_273 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_274 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_275 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_276 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.e.valid, UInt<1>(0h0))
node _schedule_T_277 = or(_schedule_T_265, _schedule_T_266)
node _schedule_T_278 = or(_schedule_T_277, _schedule_T_267)
node _schedule_T_279 = or(_schedule_T_278, _schedule_T_268)
node _schedule_T_280 = or(_schedule_T_279, _schedule_T_269)
node _schedule_T_281 = or(_schedule_T_280, _schedule_T_270)
node _schedule_T_282 = or(_schedule_T_281, _schedule_T_271)
node _schedule_T_283 = or(_schedule_T_282, _schedule_T_272)
node _schedule_T_284 = or(_schedule_T_283, _schedule_T_273)
node _schedule_T_285 = or(_schedule_T_284, _schedule_T_274)
node _schedule_T_286 = or(_schedule_T_285, _schedule_T_275)
node _schedule_T_287 = or(_schedule_T_286, _schedule_T_276)
wire _schedule_WIRE_18 : UInt<1>
connect _schedule_WIRE_18, _schedule_T_287
connect _schedule_WIRE_15.valid, _schedule_WIRE_18
connect schedule.e, _schedule_WIRE_15
wire _schedule_WIRE_19 : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<4>, way : UInt<3>, bad : UInt<1>}}
wire _schedule_WIRE_20 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<4>, way : UInt<3>, bad : UInt<1>}
node _schedule_T_288 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_289 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_290 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_291 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_292 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_293 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_294 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_295 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_296 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_297 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_298 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_299 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.bad, UInt<1>(0h0))
node _schedule_T_300 = or(_schedule_T_288, _schedule_T_289)
node _schedule_T_301 = or(_schedule_T_300, _schedule_T_290)
node _schedule_T_302 = or(_schedule_T_301, _schedule_T_291)
node _schedule_T_303 = or(_schedule_T_302, _schedule_T_292)
node _schedule_T_304 = or(_schedule_T_303, _schedule_T_293)
node _schedule_T_305 = or(_schedule_T_304, _schedule_T_294)
node _schedule_T_306 = or(_schedule_T_305, _schedule_T_295)
node _schedule_T_307 = or(_schedule_T_306, _schedule_T_296)
node _schedule_T_308 = or(_schedule_T_307, _schedule_T_297)
node _schedule_T_309 = or(_schedule_T_308, _schedule_T_298)
node _schedule_T_310 = or(_schedule_T_309, _schedule_T_299)
wire _schedule_WIRE_21 : UInt<1>
connect _schedule_WIRE_21, _schedule_T_310
connect _schedule_WIRE_20.bad, _schedule_WIRE_21
node _schedule_T_311 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_312 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_313 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_314 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_315 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_316 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_317 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_318 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_319 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_320 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_321 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_322 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.way, UInt<1>(0h0))
node _schedule_T_323 = or(_schedule_T_311, _schedule_T_312)
node _schedule_T_324 = or(_schedule_T_323, _schedule_T_313)
node _schedule_T_325 = or(_schedule_T_324, _schedule_T_314)
node _schedule_T_326 = or(_schedule_T_325, _schedule_T_315)
node _schedule_T_327 = or(_schedule_T_326, _schedule_T_316)
node _schedule_T_328 = or(_schedule_T_327, _schedule_T_317)
node _schedule_T_329 = or(_schedule_T_328, _schedule_T_318)
node _schedule_T_330 = or(_schedule_T_329, _schedule_T_319)
node _schedule_T_331 = or(_schedule_T_330, _schedule_T_320)
node _schedule_T_332 = or(_schedule_T_331, _schedule_T_321)
node _schedule_T_333 = or(_schedule_T_332, _schedule_T_322)
wire _schedule_WIRE_22 : UInt<3>
connect _schedule_WIRE_22, _schedule_T_333
connect _schedule_WIRE_20.way, _schedule_WIRE_22
node _schedule_T_334 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_335 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_336 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_337 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_338 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_339 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_340 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_341 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_342 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_343 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_344 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_345 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.sink, UInt<1>(0h0))
node _schedule_T_346 = or(_schedule_T_334, _schedule_T_335)
node _schedule_T_347 = or(_schedule_T_346, _schedule_T_336)
node _schedule_T_348 = or(_schedule_T_347, _schedule_T_337)
node _schedule_T_349 = or(_schedule_T_348, _schedule_T_338)
node _schedule_T_350 = or(_schedule_T_349, _schedule_T_339)
node _schedule_T_351 = or(_schedule_T_350, _schedule_T_340)
node _schedule_T_352 = or(_schedule_T_351, _schedule_T_341)
node _schedule_T_353 = or(_schedule_T_352, _schedule_T_342)
node _schedule_T_354 = or(_schedule_T_353, _schedule_T_343)
node _schedule_T_355 = or(_schedule_T_354, _schedule_T_344)
node _schedule_T_356 = or(_schedule_T_355, _schedule_T_345)
wire _schedule_WIRE_23 : UInt<4>
connect _schedule_WIRE_23, _schedule_T_356
connect _schedule_WIRE_20.sink, _schedule_WIRE_23
node _schedule_T_357 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_358 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_359 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_360 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_361 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_362 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_363 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_364 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_365 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_366 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_367 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_368 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.set, UInt<1>(0h0))
node _schedule_T_369 = or(_schedule_T_357, _schedule_T_358)
node _schedule_T_370 = or(_schedule_T_369, _schedule_T_359)
node _schedule_T_371 = or(_schedule_T_370, _schedule_T_360)
node _schedule_T_372 = or(_schedule_T_371, _schedule_T_361)
node _schedule_T_373 = or(_schedule_T_372, _schedule_T_362)
node _schedule_T_374 = or(_schedule_T_373, _schedule_T_363)
node _schedule_T_375 = or(_schedule_T_374, _schedule_T_364)
node _schedule_T_376 = or(_schedule_T_375, _schedule_T_365)
node _schedule_T_377 = or(_schedule_T_376, _schedule_T_366)
node _schedule_T_378 = or(_schedule_T_377, _schedule_T_367)
node _schedule_T_379 = or(_schedule_T_378, _schedule_T_368)
wire _schedule_WIRE_24 : UInt<10>
connect _schedule_WIRE_24, _schedule_T_379
connect _schedule_WIRE_20.set, _schedule_WIRE_24
node _schedule_T_380 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_381 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_382 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_383 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_384 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_385 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_386 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_387 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_388 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_389 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_390 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_391 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.put, UInt<1>(0h0))
node _schedule_T_392 = or(_schedule_T_380, _schedule_T_381)
node _schedule_T_393 = or(_schedule_T_392, _schedule_T_382)
node _schedule_T_394 = or(_schedule_T_393, _schedule_T_383)
node _schedule_T_395 = or(_schedule_T_394, _schedule_T_384)
node _schedule_T_396 = or(_schedule_T_395, _schedule_T_385)
node _schedule_T_397 = or(_schedule_T_396, _schedule_T_386)
node _schedule_T_398 = or(_schedule_T_397, _schedule_T_387)
node _schedule_T_399 = or(_schedule_T_398, _schedule_T_388)
node _schedule_T_400 = or(_schedule_T_399, _schedule_T_389)
node _schedule_T_401 = or(_schedule_T_400, _schedule_T_390)
node _schedule_T_402 = or(_schedule_T_401, _schedule_T_391)
wire _schedule_WIRE_25 : UInt<6>
connect _schedule_WIRE_25, _schedule_T_402
connect _schedule_WIRE_20.put, _schedule_WIRE_25
node _schedule_T_403 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_404 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_405 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_406 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_407 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_408 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_409 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_410 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_411 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_412 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_413 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_414 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.offset, UInt<1>(0h0))
node _schedule_T_415 = or(_schedule_T_403, _schedule_T_404)
node _schedule_T_416 = or(_schedule_T_415, _schedule_T_405)
node _schedule_T_417 = or(_schedule_T_416, _schedule_T_406)
node _schedule_T_418 = or(_schedule_T_417, _schedule_T_407)
node _schedule_T_419 = or(_schedule_T_418, _schedule_T_408)
node _schedule_T_420 = or(_schedule_T_419, _schedule_T_409)
node _schedule_T_421 = or(_schedule_T_420, _schedule_T_410)
node _schedule_T_422 = or(_schedule_T_421, _schedule_T_411)
node _schedule_T_423 = or(_schedule_T_422, _schedule_T_412)
node _schedule_T_424 = or(_schedule_T_423, _schedule_T_413)
node _schedule_T_425 = or(_schedule_T_424, _schedule_T_414)
wire _schedule_WIRE_26 : UInt<6>
connect _schedule_WIRE_26, _schedule_T_425
connect _schedule_WIRE_20.offset, _schedule_WIRE_26
node _schedule_T_426 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_427 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_428 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_429 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_430 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_431 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_432 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_433 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_434 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_435 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_436 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_437 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.tag, UInt<1>(0h0))
node _schedule_T_438 = or(_schedule_T_426, _schedule_T_427)
node _schedule_T_439 = or(_schedule_T_438, _schedule_T_428)
node _schedule_T_440 = or(_schedule_T_439, _schedule_T_429)
node _schedule_T_441 = or(_schedule_T_440, _schedule_T_430)
node _schedule_T_442 = or(_schedule_T_441, _schedule_T_431)
node _schedule_T_443 = or(_schedule_T_442, _schedule_T_432)
node _schedule_T_444 = or(_schedule_T_443, _schedule_T_433)
node _schedule_T_445 = or(_schedule_T_444, _schedule_T_434)
node _schedule_T_446 = or(_schedule_T_445, _schedule_T_435)
node _schedule_T_447 = or(_schedule_T_446, _schedule_T_436)
node _schedule_T_448 = or(_schedule_T_447, _schedule_T_437)
wire _schedule_WIRE_27 : UInt<13>
connect _schedule_WIRE_27, _schedule_T_448
connect _schedule_WIRE_20.tag, _schedule_WIRE_27
node _schedule_T_449 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_450 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_451 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_452 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_453 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_454 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_455 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_456 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_457 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_458 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_459 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_460 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.source, UInt<1>(0h0))
node _schedule_T_461 = or(_schedule_T_449, _schedule_T_450)
node _schedule_T_462 = or(_schedule_T_461, _schedule_T_451)
node _schedule_T_463 = or(_schedule_T_462, _schedule_T_452)
node _schedule_T_464 = or(_schedule_T_463, _schedule_T_453)
node _schedule_T_465 = or(_schedule_T_464, _schedule_T_454)
node _schedule_T_466 = or(_schedule_T_465, _schedule_T_455)
node _schedule_T_467 = or(_schedule_T_466, _schedule_T_456)
node _schedule_T_468 = or(_schedule_T_467, _schedule_T_457)
node _schedule_T_469 = or(_schedule_T_468, _schedule_T_458)
node _schedule_T_470 = or(_schedule_T_469, _schedule_T_459)
node _schedule_T_471 = or(_schedule_T_470, _schedule_T_460)
wire _schedule_WIRE_28 : UInt<8>
connect _schedule_WIRE_28, _schedule_T_471
connect _schedule_WIRE_20.source, _schedule_WIRE_28
node _schedule_T_472 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_473 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_474 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_475 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_476 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_477 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_478 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_479 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_480 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_481 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_482 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_483 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.size, UInt<1>(0h0))
node _schedule_T_484 = or(_schedule_T_472, _schedule_T_473)
node _schedule_T_485 = or(_schedule_T_484, _schedule_T_474)
node _schedule_T_486 = or(_schedule_T_485, _schedule_T_475)
node _schedule_T_487 = or(_schedule_T_486, _schedule_T_476)
node _schedule_T_488 = or(_schedule_T_487, _schedule_T_477)
node _schedule_T_489 = or(_schedule_T_488, _schedule_T_478)
node _schedule_T_490 = or(_schedule_T_489, _schedule_T_479)
node _schedule_T_491 = or(_schedule_T_490, _schedule_T_480)
node _schedule_T_492 = or(_schedule_T_491, _schedule_T_481)
node _schedule_T_493 = or(_schedule_T_492, _schedule_T_482)
node _schedule_T_494 = or(_schedule_T_493, _schedule_T_483)
wire _schedule_WIRE_29 : UInt<3>
connect _schedule_WIRE_29, _schedule_T_494
connect _schedule_WIRE_20.size, _schedule_WIRE_29
node _schedule_T_495 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_496 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_497 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_498 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_499 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_500 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_501 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_502 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_503 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_504 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_505 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_506 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.param, UInt<1>(0h0))
node _schedule_T_507 = or(_schedule_T_495, _schedule_T_496)
node _schedule_T_508 = or(_schedule_T_507, _schedule_T_497)
node _schedule_T_509 = or(_schedule_T_508, _schedule_T_498)
node _schedule_T_510 = or(_schedule_T_509, _schedule_T_499)
node _schedule_T_511 = or(_schedule_T_510, _schedule_T_500)
node _schedule_T_512 = or(_schedule_T_511, _schedule_T_501)
node _schedule_T_513 = or(_schedule_T_512, _schedule_T_502)
node _schedule_T_514 = or(_schedule_T_513, _schedule_T_503)
node _schedule_T_515 = or(_schedule_T_514, _schedule_T_504)
node _schedule_T_516 = or(_schedule_T_515, _schedule_T_505)
node _schedule_T_517 = or(_schedule_T_516, _schedule_T_506)
wire _schedule_WIRE_30 : UInt<3>
connect _schedule_WIRE_30, _schedule_T_517
connect _schedule_WIRE_20.param, _schedule_WIRE_30
node _schedule_T_518 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_519 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_520 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_521 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_522 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_523 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_524 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_525 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_526 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_527 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_528 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_529 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.opcode, UInt<1>(0h0))
node _schedule_T_530 = or(_schedule_T_518, _schedule_T_519)
node _schedule_T_531 = or(_schedule_T_530, _schedule_T_520)
node _schedule_T_532 = or(_schedule_T_531, _schedule_T_521)
node _schedule_T_533 = or(_schedule_T_532, _schedule_T_522)
node _schedule_T_534 = or(_schedule_T_533, _schedule_T_523)
node _schedule_T_535 = or(_schedule_T_534, _schedule_T_524)
node _schedule_T_536 = or(_schedule_T_535, _schedule_T_525)
node _schedule_T_537 = or(_schedule_T_536, _schedule_T_526)
node _schedule_T_538 = or(_schedule_T_537, _schedule_T_527)
node _schedule_T_539 = or(_schedule_T_538, _schedule_T_528)
node _schedule_T_540 = or(_schedule_T_539, _schedule_T_529)
wire _schedule_WIRE_31 : UInt<3>
connect _schedule_WIRE_31, _schedule_T_540
connect _schedule_WIRE_20.opcode, _schedule_WIRE_31
node _schedule_T_541 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_542 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_543 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_544 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_545 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_546 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_547 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_548 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_549 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_550 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_551 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_552 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.control, UInt<1>(0h0))
node _schedule_T_553 = or(_schedule_T_541, _schedule_T_542)
node _schedule_T_554 = or(_schedule_T_553, _schedule_T_543)
node _schedule_T_555 = or(_schedule_T_554, _schedule_T_544)
node _schedule_T_556 = or(_schedule_T_555, _schedule_T_545)
node _schedule_T_557 = or(_schedule_T_556, _schedule_T_546)
node _schedule_T_558 = or(_schedule_T_557, _schedule_T_547)
node _schedule_T_559 = or(_schedule_T_558, _schedule_T_548)
node _schedule_T_560 = or(_schedule_T_559, _schedule_T_549)
node _schedule_T_561 = or(_schedule_T_560, _schedule_T_550)
node _schedule_T_562 = or(_schedule_T_561, _schedule_T_551)
node _schedule_T_563 = or(_schedule_T_562, _schedule_T_552)
wire _schedule_WIRE_32 : UInt<1>
connect _schedule_WIRE_32, _schedule_T_563
connect _schedule_WIRE_20.control, _schedule_WIRE_32
wire _schedule_WIRE_33 : UInt<1>[3]
node _schedule_T_564 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_565 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_566 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_567 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_568 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_569 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_570 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_571 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_572 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_573 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_574 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_575 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0))
node _schedule_T_576 = or(_schedule_T_564, _schedule_T_565)
node _schedule_T_577 = or(_schedule_T_576, _schedule_T_566)
node _schedule_T_578 = or(_schedule_T_577, _schedule_T_567)
node _schedule_T_579 = or(_schedule_T_578, _schedule_T_568)
node _schedule_T_580 = or(_schedule_T_579, _schedule_T_569)
node _schedule_T_581 = or(_schedule_T_580, _schedule_T_570)
node _schedule_T_582 = or(_schedule_T_581, _schedule_T_571)
node _schedule_T_583 = or(_schedule_T_582, _schedule_T_572)
node _schedule_T_584 = or(_schedule_T_583, _schedule_T_573)
node _schedule_T_585 = or(_schedule_T_584, _schedule_T_574)
node _schedule_T_586 = or(_schedule_T_585, _schedule_T_575)
wire _schedule_WIRE_34 : UInt<1>
connect _schedule_WIRE_34, _schedule_T_586
connect _schedule_WIRE_33[0], _schedule_WIRE_34
node _schedule_T_587 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_588 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_589 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_590 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_591 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_592 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_593 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_594 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_595 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_596 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_597 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_598 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0))
node _schedule_T_599 = or(_schedule_T_587, _schedule_T_588)
node _schedule_T_600 = or(_schedule_T_599, _schedule_T_589)
node _schedule_T_601 = or(_schedule_T_600, _schedule_T_590)
node _schedule_T_602 = or(_schedule_T_601, _schedule_T_591)
node _schedule_T_603 = or(_schedule_T_602, _schedule_T_592)
node _schedule_T_604 = or(_schedule_T_603, _schedule_T_593)
node _schedule_T_605 = or(_schedule_T_604, _schedule_T_594)
node _schedule_T_606 = or(_schedule_T_605, _schedule_T_595)
node _schedule_T_607 = or(_schedule_T_606, _schedule_T_596)
node _schedule_T_608 = or(_schedule_T_607, _schedule_T_597)
node _schedule_T_609 = or(_schedule_T_608, _schedule_T_598)
wire _schedule_WIRE_35 : UInt<1>
connect _schedule_WIRE_35, _schedule_T_609
connect _schedule_WIRE_33[1], _schedule_WIRE_35
node _schedule_T_610 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_611 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_612 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_613 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_614 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_615 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_616 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_617 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_618 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_619 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_620 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_621 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0))
node _schedule_T_622 = or(_schedule_T_610, _schedule_T_611)
node _schedule_T_623 = or(_schedule_T_622, _schedule_T_612)
node _schedule_T_624 = or(_schedule_T_623, _schedule_T_613)
node _schedule_T_625 = or(_schedule_T_624, _schedule_T_614)
node _schedule_T_626 = or(_schedule_T_625, _schedule_T_615)
node _schedule_T_627 = or(_schedule_T_626, _schedule_T_616)
node _schedule_T_628 = or(_schedule_T_627, _schedule_T_617)
node _schedule_T_629 = or(_schedule_T_628, _schedule_T_618)
node _schedule_T_630 = or(_schedule_T_629, _schedule_T_619)
node _schedule_T_631 = or(_schedule_T_630, _schedule_T_620)
node _schedule_T_632 = or(_schedule_T_631, _schedule_T_621)
wire _schedule_WIRE_36 : UInt<1>
connect _schedule_WIRE_36, _schedule_T_632
connect _schedule_WIRE_33[2], _schedule_WIRE_36
connect _schedule_WIRE_20.prio, _schedule_WIRE_33
connect _schedule_WIRE_19.bits, _schedule_WIRE_20
node _schedule_T_633 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_634 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_635 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_636 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_637 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_638 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_639 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_640 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_641 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_642 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_643 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_644 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.valid, UInt<1>(0h0))
node _schedule_T_645 = or(_schedule_T_633, _schedule_T_634)
node _schedule_T_646 = or(_schedule_T_645, _schedule_T_635)
node _schedule_T_647 = or(_schedule_T_646, _schedule_T_636)
node _schedule_T_648 = or(_schedule_T_647, _schedule_T_637)
node _schedule_T_649 = or(_schedule_T_648, _schedule_T_638)
node _schedule_T_650 = or(_schedule_T_649, _schedule_T_639)
node _schedule_T_651 = or(_schedule_T_650, _schedule_T_640)
node _schedule_T_652 = or(_schedule_T_651, _schedule_T_641)
node _schedule_T_653 = or(_schedule_T_652, _schedule_T_642)
node _schedule_T_654 = or(_schedule_T_653, _schedule_T_643)
node _schedule_T_655 = or(_schedule_T_654, _schedule_T_644)
wire _schedule_WIRE_37 : UInt<1>
connect _schedule_WIRE_37, _schedule_T_655
connect _schedule_WIRE_19.valid, _schedule_WIRE_37
connect schedule.d, _schedule_WIRE_19
wire _schedule_WIRE_38 : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}
wire _schedule_WIRE_39 : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}
node _schedule_T_656 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_657 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_658 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_659 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_660 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_661 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_662 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_663 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_664 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_665 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_666 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_667 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.dirty, UInt<1>(0h0))
node _schedule_T_668 = or(_schedule_T_656, _schedule_T_657)
node _schedule_T_669 = or(_schedule_T_668, _schedule_T_658)
node _schedule_T_670 = or(_schedule_T_669, _schedule_T_659)
node _schedule_T_671 = or(_schedule_T_670, _schedule_T_660)
node _schedule_T_672 = or(_schedule_T_671, _schedule_T_661)
node _schedule_T_673 = or(_schedule_T_672, _schedule_T_662)
node _schedule_T_674 = or(_schedule_T_673, _schedule_T_663)
node _schedule_T_675 = or(_schedule_T_674, _schedule_T_664)
node _schedule_T_676 = or(_schedule_T_675, _schedule_T_665)
node _schedule_T_677 = or(_schedule_T_676, _schedule_T_666)
node _schedule_T_678 = or(_schedule_T_677, _schedule_T_667)
wire _schedule_WIRE_40 : UInt<1>
connect _schedule_WIRE_40, _schedule_T_678
connect _schedule_WIRE_39.dirty, _schedule_WIRE_40
node _schedule_T_679 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_680 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_681 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_682 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_683 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_684 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_685 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_686 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_687 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_688 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_689 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_690 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.way, UInt<1>(0h0))
node _schedule_T_691 = or(_schedule_T_679, _schedule_T_680)
node _schedule_T_692 = or(_schedule_T_691, _schedule_T_681)
node _schedule_T_693 = or(_schedule_T_692, _schedule_T_682)
node _schedule_T_694 = or(_schedule_T_693, _schedule_T_683)
node _schedule_T_695 = or(_schedule_T_694, _schedule_T_684)
node _schedule_T_696 = or(_schedule_T_695, _schedule_T_685)
node _schedule_T_697 = or(_schedule_T_696, _schedule_T_686)
node _schedule_T_698 = or(_schedule_T_697, _schedule_T_687)
node _schedule_T_699 = or(_schedule_T_698, _schedule_T_688)
node _schedule_T_700 = or(_schedule_T_699, _schedule_T_689)
node _schedule_T_701 = or(_schedule_T_700, _schedule_T_690)
wire _schedule_WIRE_41 : UInt<3>
connect _schedule_WIRE_41, _schedule_T_701
connect _schedule_WIRE_39.way, _schedule_WIRE_41
node _schedule_T_702 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_703 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_704 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_705 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_706 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_707 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_708 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_709 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_710 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_711 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_712 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_713 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.set, UInt<1>(0h0))
node _schedule_T_714 = or(_schedule_T_702, _schedule_T_703)
node _schedule_T_715 = or(_schedule_T_714, _schedule_T_704)
node _schedule_T_716 = or(_schedule_T_715, _schedule_T_705)
node _schedule_T_717 = or(_schedule_T_716, _schedule_T_706)
node _schedule_T_718 = or(_schedule_T_717, _schedule_T_707)
node _schedule_T_719 = or(_schedule_T_718, _schedule_T_708)
node _schedule_T_720 = or(_schedule_T_719, _schedule_T_709)
node _schedule_T_721 = or(_schedule_T_720, _schedule_T_710)
node _schedule_T_722 = or(_schedule_T_721, _schedule_T_711)
node _schedule_T_723 = or(_schedule_T_722, _schedule_T_712)
node _schedule_T_724 = or(_schedule_T_723, _schedule_T_713)
wire _schedule_WIRE_42 : UInt<10>
connect _schedule_WIRE_42, _schedule_T_724
connect _schedule_WIRE_39.set, _schedule_WIRE_42
node _schedule_T_725 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_726 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_727 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_728 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_729 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_730 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_731 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_732 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_733 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_734 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_735 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_736 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.tag, UInt<1>(0h0))
node _schedule_T_737 = or(_schedule_T_725, _schedule_T_726)
node _schedule_T_738 = or(_schedule_T_737, _schedule_T_727)
node _schedule_T_739 = or(_schedule_T_738, _schedule_T_728)
node _schedule_T_740 = or(_schedule_T_739, _schedule_T_729)
node _schedule_T_741 = or(_schedule_T_740, _schedule_T_730)
node _schedule_T_742 = or(_schedule_T_741, _schedule_T_731)
node _schedule_T_743 = or(_schedule_T_742, _schedule_T_732)
node _schedule_T_744 = or(_schedule_T_743, _schedule_T_733)
node _schedule_T_745 = or(_schedule_T_744, _schedule_T_734)
node _schedule_T_746 = or(_schedule_T_745, _schedule_T_735)
node _schedule_T_747 = or(_schedule_T_746, _schedule_T_736)
wire _schedule_WIRE_43 : UInt<13>
connect _schedule_WIRE_43, _schedule_T_747
connect _schedule_WIRE_39.tag, _schedule_WIRE_43
node _schedule_T_748 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_749 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_750 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_751 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_752 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_753 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_754 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_755 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_756 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_757 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_758 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_759 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.source, UInt<1>(0h0))
node _schedule_T_760 = or(_schedule_T_748, _schedule_T_749)
node _schedule_T_761 = or(_schedule_T_760, _schedule_T_750)
node _schedule_T_762 = or(_schedule_T_761, _schedule_T_751)
node _schedule_T_763 = or(_schedule_T_762, _schedule_T_752)
node _schedule_T_764 = or(_schedule_T_763, _schedule_T_753)
node _schedule_T_765 = or(_schedule_T_764, _schedule_T_754)
node _schedule_T_766 = or(_schedule_T_765, _schedule_T_755)
node _schedule_T_767 = or(_schedule_T_766, _schedule_T_756)
node _schedule_T_768 = or(_schedule_T_767, _schedule_T_757)
node _schedule_T_769 = or(_schedule_T_768, _schedule_T_758)
node _schedule_T_770 = or(_schedule_T_769, _schedule_T_759)
wire _schedule_WIRE_44 : UInt<4>
connect _schedule_WIRE_44, _schedule_T_770
connect _schedule_WIRE_39.source, _schedule_WIRE_44
node _schedule_T_771 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_772 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_773 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_774 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_775 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_776 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_777 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_778 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_779 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_780 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_781 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_782 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.param, UInt<1>(0h0))
node _schedule_T_783 = or(_schedule_T_771, _schedule_T_772)
node _schedule_T_784 = or(_schedule_T_783, _schedule_T_773)
node _schedule_T_785 = or(_schedule_T_784, _schedule_T_774)
node _schedule_T_786 = or(_schedule_T_785, _schedule_T_775)
node _schedule_T_787 = or(_schedule_T_786, _schedule_T_776)
node _schedule_T_788 = or(_schedule_T_787, _schedule_T_777)
node _schedule_T_789 = or(_schedule_T_788, _schedule_T_778)
node _schedule_T_790 = or(_schedule_T_789, _schedule_T_779)
node _schedule_T_791 = or(_schedule_T_790, _schedule_T_780)
node _schedule_T_792 = or(_schedule_T_791, _schedule_T_781)
node _schedule_T_793 = or(_schedule_T_792, _schedule_T_782)
wire _schedule_WIRE_45 : UInt<3>
connect _schedule_WIRE_45, _schedule_T_793
connect _schedule_WIRE_39.param, _schedule_WIRE_45
node _schedule_T_794 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_795 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_796 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_797 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_798 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_799 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_800 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_801 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_802 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_803 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_804 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_805 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.opcode, UInt<1>(0h0))
node _schedule_T_806 = or(_schedule_T_794, _schedule_T_795)
node _schedule_T_807 = or(_schedule_T_806, _schedule_T_796)
node _schedule_T_808 = or(_schedule_T_807, _schedule_T_797)
node _schedule_T_809 = or(_schedule_T_808, _schedule_T_798)
node _schedule_T_810 = or(_schedule_T_809, _schedule_T_799)
node _schedule_T_811 = or(_schedule_T_810, _schedule_T_800)
node _schedule_T_812 = or(_schedule_T_811, _schedule_T_801)
node _schedule_T_813 = or(_schedule_T_812, _schedule_T_802)
node _schedule_T_814 = or(_schedule_T_813, _schedule_T_803)
node _schedule_T_815 = or(_schedule_T_814, _schedule_T_804)
node _schedule_T_816 = or(_schedule_T_815, _schedule_T_805)
wire _schedule_WIRE_46 : UInt<3>
connect _schedule_WIRE_46, _schedule_T_816
connect _schedule_WIRE_39.opcode, _schedule_WIRE_46
connect _schedule_WIRE_38.bits, _schedule_WIRE_39
node _schedule_T_817 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_818 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_819 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_820 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_821 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_822 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_823 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_824 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_825 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_826 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_827 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_828 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.valid, UInt<1>(0h0))
node _schedule_T_829 = or(_schedule_T_817, _schedule_T_818)
node _schedule_T_830 = or(_schedule_T_829, _schedule_T_819)
node _schedule_T_831 = or(_schedule_T_830, _schedule_T_820)
node _schedule_T_832 = or(_schedule_T_831, _schedule_T_821)
node _schedule_T_833 = or(_schedule_T_832, _schedule_T_822)
node _schedule_T_834 = or(_schedule_T_833, _schedule_T_823)
node _schedule_T_835 = or(_schedule_T_834, _schedule_T_824)
node _schedule_T_836 = or(_schedule_T_835, _schedule_T_825)
node _schedule_T_837 = or(_schedule_T_836, _schedule_T_826)
node _schedule_T_838 = or(_schedule_T_837, _schedule_T_827)
node _schedule_T_839 = or(_schedule_T_838, _schedule_T_828)
wire _schedule_WIRE_47 : UInt<1>
connect _schedule_WIRE_47, _schedule_T_839
connect _schedule_WIRE_38.valid, _schedule_WIRE_47
connect schedule.c, _schedule_WIRE_38
wire _schedule_WIRE_48 : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}}
wire _schedule_WIRE_49 : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}
node _schedule_T_840 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_841 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_842 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_843 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_844 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_845 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_846 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_847 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_848 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_849 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_850 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_851 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.b.bits.clients, UInt<1>(0h0))
node _schedule_T_852 = or(_schedule_T_840, _schedule_T_841)
node _schedule_T_853 = or(_schedule_T_852, _schedule_T_842)
node _schedule_T_854 = or(_schedule_T_853, _schedule_T_843)
node _schedule_T_855 = or(_schedule_T_854, _schedule_T_844)
node _schedule_T_856 = or(_schedule_T_855, _schedule_T_845)
node _schedule_T_857 = or(_schedule_T_856, _schedule_T_846)
node _schedule_T_858 = or(_schedule_T_857, _schedule_T_847)
node _schedule_T_859 = or(_schedule_T_858, _schedule_T_848)
node _schedule_T_860 = or(_schedule_T_859, _schedule_T_849)
node _schedule_T_861 = or(_schedule_T_860, _schedule_T_850)
node _schedule_T_862 = or(_schedule_T_861, _schedule_T_851)
wire _schedule_WIRE_50 : UInt<1>
connect _schedule_WIRE_50, _schedule_T_862
connect _schedule_WIRE_49.clients, _schedule_WIRE_50
node _schedule_T_863 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_864 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_865 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_866 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_867 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_868 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_869 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_870 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_871 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_872 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_873 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_874 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.b.bits.set, UInt<1>(0h0))
node _schedule_T_875 = or(_schedule_T_863, _schedule_T_864)
node _schedule_T_876 = or(_schedule_T_875, _schedule_T_865)
node _schedule_T_877 = or(_schedule_T_876, _schedule_T_866)
node _schedule_T_878 = or(_schedule_T_877, _schedule_T_867)
node _schedule_T_879 = or(_schedule_T_878, _schedule_T_868)
node _schedule_T_880 = or(_schedule_T_879, _schedule_T_869)
node _schedule_T_881 = or(_schedule_T_880, _schedule_T_870)
node _schedule_T_882 = or(_schedule_T_881, _schedule_T_871)
node _schedule_T_883 = or(_schedule_T_882, _schedule_T_872)
node _schedule_T_884 = or(_schedule_T_883, _schedule_T_873)
node _schedule_T_885 = or(_schedule_T_884, _schedule_T_874)
wire _schedule_WIRE_51 : UInt<10>
connect _schedule_WIRE_51, _schedule_T_885
connect _schedule_WIRE_49.set, _schedule_WIRE_51
node _schedule_T_886 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_887 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_888 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_889 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_890 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_891 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_892 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_893 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_894 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_895 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_896 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_897 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.b.bits.tag, UInt<1>(0h0))
node _schedule_T_898 = or(_schedule_T_886, _schedule_T_887)
node _schedule_T_899 = or(_schedule_T_898, _schedule_T_888)
node _schedule_T_900 = or(_schedule_T_899, _schedule_T_889)
node _schedule_T_901 = or(_schedule_T_900, _schedule_T_890)
node _schedule_T_902 = or(_schedule_T_901, _schedule_T_891)
node _schedule_T_903 = or(_schedule_T_902, _schedule_T_892)
node _schedule_T_904 = or(_schedule_T_903, _schedule_T_893)
node _schedule_T_905 = or(_schedule_T_904, _schedule_T_894)
node _schedule_T_906 = or(_schedule_T_905, _schedule_T_895)
node _schedule_T_907 = or(_schedule_T_906, _schedule_T_896)
node _schedule_T_908 = or(_schedule_T_907, _schedule_T_897)
wire _schedule_WIRE_52 : UInt<13>
connect _schedule_WIRE_52, _schedule_T_908
connect _schedule_WIRE_49.tag, _schedule_WIRE_52
node _schedule_T_909 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_910 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_911 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_912 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_913 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_914 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_915 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_916 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_917 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_918 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_919 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_920 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.b.bits.param, UInt<1>(0h0))
node _schedule_T_921 = or(_schedule_T_909, _schedule_T_910)
node _schedule_T_922 = or(_schedule_T_921, _schedule_T_911)
node _schedule_T_923 = or(_schedule_T_922, _schedule_T_912)
node _schedule_T_924 = or(_schedule_T_923, _schedule_T_913)
node _schedule_T_925 = or(_schedule_T_924, _schedule_T_914)
node _schedule_T_926 = or(_schedule_T_925, _schedule_T_915)
node _schedule_T_927 = or(_schedule_T_926, _schedule_T_916)
node _schedule_T_928 = or(_schedule_T_927, _schedule_T_917)
node _schedule_T_929 = or(_schedule_T_928, _schedule_T_918)
node _schedule_T_930 = or(_schedule_T_929, _schedule_T_919)
node _schedule_T_931 = or(_schedule_T_930, _schedule_T_920)
wire _schedule_WIRE_53 : UInt<3>
connect _schedule_WIRE_53, _schedule_T_931
connect _schedule_WIRE_49.param, _schedule_WIRE_53
connect _schedule_WIRE_48.bits, _schedule_WIRE_49
node _schedule_T_932 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_933 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_934 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_935 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_936 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_937 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_938 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_939 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_940 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_941 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_942 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_943 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.b.valid, UInt<1>(0h0))
node _schedule_T_944 = or(_schedule_T_932, _schedule_T_933)
node _schedule_T_945 = or(_schedule_T_944, _schedule_T_934)
node _schedule_T_946 = or(_schedule_T_945, _schedule_T_935)
node _schedule_T_947 = or(_schedule_T_946, _schedule_T_936)
node _schedule_T_948 = or(_schedule_T_947, _schedule_T_937)
node _schedule_T_949 = or(_schedule_T_948, _schedule_T_938)
node _schedule_T_950 = or(_schedule_T_949, _schedule_T_939)
node _schedule_T_951 = or(_schedule_T_950, _schedule_T_940)
node _schedule_T_952 = or(_schedule_T_951, _schedule_T_941)
node _schedule_T_953 = or(_schedule_T_952, _schedule_T_942)
node _schedule_T_954 = or(_schedule_T_953, _schedule_T_943)
wire _schedule_WIRE_54 : UInt<1>
connect _schedule_WIRE_54, _schedule_T_954
connect _schedule_WIRE_48.valid, _schedule_WIRE_54
connect schedule.b, _schedule_WIRE_48
wire _schedule_WIRE_55 : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}
wire _schedule_WIRE_56 : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<4>, block : UInt<1>}
node _schedule_T_955 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_956 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_957 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_958 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_959 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_960 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_961 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_962 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_963 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_964 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_965 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_966 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.bits.block, UInt<1>(0h0))
node _schedule_T_967 = or(_schedule_T_955, _schedule_T_956)
node _schedule_T_968 = or(_schedule_T_967, _schedule_T_957)
node _schedule_T_969 = or(_schedule_T_968, _schedule_T_958)
node _schedule_T_970 = or(_schedule_T_969, _schedule_T_959)
node _schedule_T_971 = or(_schedule_T_970, _schedule_T_960)
node _schedule_T_972 = or(_schedule_T_971, _schedule_T_961)
node _schedule_T_973 = or(_schedule_T_972, _schedule_T_962)
node _schedule_T_974 = or(_schedule_T_973, _schedule_T_963)
node _schedule_T_975 = or(_schedule_T_974, _schedule_T_964)
node _schedule_T_976 = or(_schedule_T_975, _schedule_T_965)
node _schedule_T_977 = or(_schedule_T_976, _schedule_T_966)
wire _schedule_WIRE_57 : UInt<1>
connect _schedule_WIRE_57, _schedule_T_977
connect _schedule_WIRE_56.block, _schedule_WIRE_57
node _schedule_T_978 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_979 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_980 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_981 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_982 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_983 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_984 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_985 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_986 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_987 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_988 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_989 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.bits.source, UInt<1>(0h0))
node _schedule_T_990 = or(_schedule_T_978, _schedule_T_979)
node _schedule_T_991 = or(_schedule_T_990, _schedule_T_980)
node _schedule_T_992 = or(_schedule_T_991, _schedule_T_981)
node _schedule_T_993 = or(_schedule_T_992, _schedule_T_982)
node _schedule_T_994 = or(_schedule_T_993, _schedule_T_983)
node _schedule_T_995 = or(_schedule_T_994, _schedule_T_984)
node _schedule_T_996 = or(_schedule_T_995, _schedule_T_985)
node _schedule_T_997 = or(_schedule_T_996, _schedule_T_986)
node _schedule_T_998 = or(_schedule_T_997, _schedule_T_987)
node _schedule_T_999 = or(_schedule_T_998, _schedule_T_988)
node _schedule_T_1000 = or(_schedule_T_999, _schedule_T_989)
wire _schedule_WIRE_58 : UInt<4>
connect _schedule_WIRE_58, _schedule_T_1000
connect _schedule_WIRE_56.source, _schedule_WIRE_58
node _schedule_T_1001 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1002 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1003 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1004 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1005 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1006 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1007 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1008 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1009 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1010 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1011 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1012 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.bits.param, UInt<1>(0h0))
node _schedule_T_1013 = or(_schedule_T_1001, _schedule_T_1002)
node _schedule_T_1014 = or(_schedule_T_1013, _schedule_T_1003)
node _schedule_T_1015 = or(_schedule_T_1014, _schedule_T_1004)
node _schedule_T_1016 = or(_schedule_T_1015, _schedule_T_1005)
node _schedule_T_1017 = or(_schedule_T_1016, _schedule_T_1006)
node _schedule_T_1018 = or(_schedule_T_1017, _schedule_T_1007)
node _schedule_T_1019 = or(_schedule_T_1018, _schedule_T_1008)
node _schedule_T_1020 = or(_schedule_T_1019, _schedule_T_1009)
node _schedule_T_1021 = or(_schedule_T_1020, _schedule_T_1010)
node _schedule_T_1022 = or(_schedule_T_1021, _schedule_T_1011)
node _schedule_T_1023 = or(_schedule_T_1022, _schedule_T_1012)
wire _schedule_WIRE_59 : UInt<3>
connect _schedule_WIRE_59, _schedule_T_1023
connect _schedule_WIRE_56.param, _schedule_WIRE_59
node _schedule_T_1024 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1025 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1026 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1027 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1028 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1029 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1030 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1031 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1032 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1033 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1034 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1035 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.bits.set, UInt<1>(0h0))
node _schedule_T_1036 = or(_schedule_T_1024, _schedule_T_1025)
node _schedule_T_1037 = or(_schedule_T_1036, _schedule_T_1026)
node _schedule_T_1038 = or(_schedule_T_1037, _schedule_T_1027)
node _schedule_T_1039 = or(_schedule_T_1038, _schedule_T_1028)
node _schedule_T_1040 = or(_schedule_T_1039, _schedule_T_1029)
node _schedule_T_1041 = or(_schedule_T_1040, _schedule_T_1030)
node _schedule_T_1042 = or(_schedule_T_1041, _schedule_T_1031)
node _schedule_T_1043 = or(_schedule_T_1042, _schedule_T_1032)
node _schedule_T_1044 = or(_schedule_T_1043, _schedule_T_1033)
node _schedule_T_1045 = or(_schedule_T_1044, _schedule_T_1034)
node _schedule_T_1046 = or(_schedule_T_1045, _schedule_T_1035)
wire _schedule_WIRE_60 : UInt<10>
connect _schedule_WIRE_60, _schedule_T_1046
connect _schedule_WIRE_56.set, _schedule_WIRE_60
node _schedule_T_1047 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1048 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1049 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1050 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1051 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1052 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1053 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1054 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1055 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1056 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1057 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1058 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.bits.tag, UInt<1>(0h0))
node _schedule_T_1059 = or(_schedule_T_1047, _schedule_T_1048)
node _schedule_T_1060 = or(_schedule_T_1059, _schedule_T_1049)
node _schedule_T_1061 = or(_schedule_T_1060, _schedule_T_1050)
node _schedule_T_1062 = or(_schedule_T_1061, _schedule_T_1051)
node _schedule_T_1063 = or(_schedule_T_1062, _schedule_T_1052)
node _schedule_T_1064 = or(_schedule_T_1063, _schedule_T_1053)
node _schedule_T_1065 = or(_schedule_T_1064, _schedule_T_1054)
node _schedule_T_1066 = or(_schedule_T_1065, _schedule_T_1055)
node _schedule_T_1067 = or(_schedule_T_1066, _schedule_T_1056)
node _schedule_T_1068 = or(_schedule_T_1067, _schedule_T_1057)
node _schedule_T_1069 = or(_schedule_T_1068, _schedule_T_1058)
wire _schedule_WIRE_61 : UInt<13>
connect _schedule_WIRE_61, _schedule_T_1069
connect _schedule_WIRE_56.tag, _schedule_WIRE_61
connect _schedule_WIRE_55.bits, _schedule_WIRE_56
node _schedule_T_1070 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1071 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1072 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1073 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1074 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1075 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1076 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1077 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1078 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1079 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1080 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1081 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.valid, UInt<1>(0h0))
node _schedule_T_1082 = or(_schedule_T_1070, _schedule_T_1071)
node _schedule_T_1083 = or(_schedule_T_1082, _schedule_T_1072)
node _schedule_T_1084 = or(_schedule_T_1083, _schedule_T_1073)
node _schedule_T_1085 = or(_schedule_T_1084, _schedule_T_1074)
node _schedule_T_1086 = or(_schedule_T_1085, _schedule_T_1075)
node _schedule_T_1087 = or(_schedule_T_1086, _schedule_T_1076)
node _schedule_T_1088 = or(_schedule_T_1087, _schedule_T_1077)
node _schedule_T_1089 = or(_schedule_T_1088, _schedule_T_1078)
node _schedule_T_1090 = or(_schedule_T_1089, _schedule_T_1079)
node _schedule_T_1091 = or(_schedule_T_1090, _schedule_T_1080)
node _schedule_T_1092 = or(_schedule_T_1091, _schedule_T_1081)
wire _schedule_WIRE_62 : UInt<1>
connect _schedule_WIRE_62, _schedule_T_1092
connect _schedule_WIRE_55.valid, _schedule_WIRE_62
connect schedule.a, _schedule_WIRE_55
node _scheduleTag_T = bits(mshr_selectOH, 0, 0)
node _scheduleTag_T_1 = bits(mshr_selectOH, 1, 1)
node _scheduleTag_T_2 = bits(mshr_selectOH, 2, 2)
node _scheduleTag_T_3 = bits(mshr_selectOH, 3, 3)
node _scheduleTag_T_4 = bits(mshr_selectOH, 4, 4)
node _scheduleTag_T_5 = bits(mshr_selectOH, 5, 5)
node _scheduleTag_T_6 = bits(mshr_selectOH, 6, 6)
node _scheduleTag_T_7 = bits(mshr_selectOH, 7, 7)
node _scheduleTag_T_8 = bits(mshr_selectOH, 8, 8)
node _scheduleTag_T_9 = bits(mshr_selectOH, 9, 9)
node _scheduleTag_T_10 = bits(mshr_selectOH, 10, 10)
node _scheduleTag_T_11 = bits(mshr_selectOH, 11, 11)
node _scheduleTag_T_12 = mux(_scheduleTag_T, mshrs_0.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_13 = mux(_scheduleTag_T_1, mshrs_1.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_14 = mux(_scheduleTag_T_2, mshrs_2.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_15 = mux(_scheduleTag_T_3, mshrs_3.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_16 = mux(_scheduleTag_T_4, mshrs_4.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_17 = mux(_scheduleTag_T_5, mshrs_5.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_18 = mux(_scheduleTag_T_6, mshrs_6.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_19 = mux(_scheduleTag_T_7, mshrs_7.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_20 = mux(_scheduleTag_T_8, mshrs_8.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_21 = mux(_scheduleTag_T_9, mshrs_9.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_22 = mux(_scheduleTag_T_10, mshrs_10.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_23 = mux(_scheduleTag_T_11, mshrs_11.io.status.bits.tag, UInt<1>(0h0))
node _scheduleTag_T_24 = or(_scheduleTag_T_12, _scheduleTag_T_13)
node _scheduleTag_T_25 = or(_scheduleTag_T_24, _scheduleTag_T_14)
node _scheduleTag_T_26 = or(_scheduleTag_T_25, _scheduleTag_T_15)
node _scheduleTag_T_27 = or(_scheduleTag_T_26, _scheduleTag_T_16)
node _scheduleTag_T_28 = or(_scheduleTag_T_27, _scheduleTag_T_17)
node _scheduleTag_T_29 = or(_scheduleTag_T_28, _scheduleTag_T_18)
node _scheduleTag_T_30 = or(_scheduleTag_T_29, _scheduleTag_T_19)
node _scheduleTag_T_31 = or(_scheduleTag_T_30, _scheduleTag_T_20)
node _scheduleTag_T_32 = or(_scheduleTag_T_31, _scheduleTag_T_21)
node _scheduleTag_T_33 = or(_scheduleTag_T_32, _scheduleTag_T_22)
node _scheduleTag_T_34 = or(_scheduleTag_T_33, _scheduleTag_T_23)
wire scheduleTag : UInt<13>
connect scheduleTag, _scheduleTag_T_34
node _scheduleSet_T = bits(mshr_selectOH, 0, 0)
node _scheduleSet_T_1 = bits(mshr_selectOH, 1, 1)
node _scheduleSet_T_2 = bits(mshr_selectOH, 2, 2)
node _scheduleSet_T_3 = bits(mshr_selectOH, 3, 3)
node _scheduleSet_T_4 = bits(mshr_selectOH, 4, 4)
node _scheduleSet_T_5 = bits(mshr_selectOH, 5, 5)
node _scheduleSet_T_6 = bits(mshr_selectOH, 6, 6)
node _scheduleSet_T_7 = bits(mshr_selectOH, 7, 7)
node _scheduleSet_T_8 = bits(mshr_selectOH, 8, 8)
node _scheduleSet_T_9 = bits(mshr_selectOH, 9, 9)
node _scheduleSet_T_10 = bits(mshr_selectOH, 10, 10)
node _scheduleSet_T_11 = bits(mshr_selectOH, 11, 11)
node _scheduleSet_T_12 = mux(_scheduleSet_T, mshrs_0.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_13 = mux(_scheduleSet_T_1, mshrs_1.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_14 = mux(_scheduleSet_T_2, mshrs_2.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_15 = mux(_scheduleSet_T_3, mshrs_3.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_16 = mux(_scheduleSet_T_4, mshrs_4.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_17 = mux(_scheduleSet_T_5, mshrs_5.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_18 = mux(_scheduleSet_T_6, mshrs_6.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_19 = mux(_scheduleSet_T_7, mshrs_7.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_20 = mux(_scheduleSet_T_8, mshrs_8.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_21 = mux(_scheduleSet_T_9, mshrs_9.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_22 = mux(_scheduleSet_T_10, mshrs_10.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_23 = mux(_scheduleSet_T_11, mshrs_11.io.status.bits.set, UInt<1>(0h0))
node _scheduleSet_T_24 = or(_scheduleSet_T_12, _scheduleSet_T_13)
node _scheduleSet_T_25 = or(_scheduleSet_T_24, _scheduleSet_T_14)
node _scheduleSet_T_26 = or(_scheduleSet_T_25, _scheduleSet_T_15)
node _scheduleSet_T_27 = or(_scheduleSet_T_26, _scheduleSet_T_16)
node _scheduleSet_T_28 = or(_scheduleSet_T_27, _scheduleSet_T_17)
node _scheduleSet_T_29 = or(_scheduleSet_T_28, _scheduleSet_T_18)
node _scheduleSet_T_30 = or(_scheduleSet_T_29, _scheduleSet_T_19)
node _scheduleSet_T_31 = or(_scheduleSet_T_30, _scheduleSet_T_20)
node _scheduleSet_T_32 = or(_scheduleSet_T_31, _scheduleSet_T_21)
node _scheduleSet_T_33 = or(_scheduleSet_T_32, _scheduleSet_T_22)
node _scheduleSet_T_34 = or(_scheduleSet_T_33, _scheduleSet_T_23)
wire scheduleSet : UInt<10>
connect scheduleSet, _scheduleSet_T_34
node _T_9 = orr(mshr_request)
when _T_9 :
node _robin_filter_T = shr(mshr_selectOH, 1)
node _robin_filter_T_1 = or(mshr_selectOH, _robin_filter_T)
node _robin_filter_T_2 = shr(_robin_filter_T_1, 2)
node _robin_filter_T_3 = or(_robin_filter_T_1, _robin_filter_T_2)
node _robin_filter_T_4 = shr(_robin_filter_T_3, 4)
node _robin_filter_T_5 = or(_robin_filter_T_3, _robin_filter_T_4)
node _robin_filter_T_6 = shr(_robin_filter_T_5, 8)
node _robin_filter_T_7 = or(_robin_filter_T_5, _robin_filter_T_6)
node _robin_filter_T_8 = bits(_robin_filter_T_7, 11, 0)
node _robin_filter_T_9 = not(_robin_filter_T_8)
connect robin_filter, _robin_filter_T_9
connect schedule.a.bits.source, mshr_select
node _schedule_c_bits_source_T = bits(schedule.c.bits.opcode, 1, 1)
node _schedule_c_bits_source_T_1 = mux(_schedule_c_bits_source_T, mshr_select, UInt<1>(0h0))
connect schedule.c.bits.source, _schedule_c_bits_source_T_1
connect schedule.d.bits.sink, mshr_select
connect sourceA.io.req.valid, schedule.a.valid
connect sourceB.io.req.valid, schedule.b.valid
connect sourceC.io.req.valid, schedule.c.valid
connect sourceD.io.req.valid, schedule.d.valid
connect sourceE.io.req.valid, schedule.e.valid
connect sourceX.io.req.valid, schedule.x.valid
connect sourceA.io.req.bits.block, schedule.a.bits.block
connect sourceA.io.req.bits.source, schedule.a.bits.source
connect sourceA.io.req.bits.param, schedule.a.bits.param
connect sourceA.io.req.bits.set, schedule.a.bits.set
connect sourceA.io.req.bits.tag, schedule.a.bits.tag
connect sourceB.io.req.bits.clients, schedule.b.bits.clients
connect sourceB.io.req.bits.set, schedule.b.bits.set
connect sourceB.io.req.bits.tag, schedule.b.bits.tag
connect sourceB.io.req.bits.param, schedule.b.bits.param
connect sourceC.io.req.bits.dirty, schedule.c.bits.dirty
connect sourceC.io.req.bits.way, schedule.c.bits.way
connect sourceC.io.req.bits.set, schedule.c.bits.set
connect sourceC.io.req.bits.tag, schedule.c.bits.tag
connect sourceC.io.req.bits.source, schedule.c.bits.source
connect sourceC.io.req.bits.param, schedule.c.bits.param
connect sourceC.io.req.bits.opcode, schedule.c.bits.opcode
connect sourceD.io.req.bits.bad, schedule.d.bits.bad
connect sourceD.io.req.bits.way, schedule.d.bits.way
connect sourceD.io.req.bits.sink, schedule.d.bits.sink
connect sourceD.io.req.bits.set, schedule.d.bits.set
connect sourceD.io.req.bits.put, schedule.d.bits.put
connect sourceD.io.req.bits.offset, schedule.d.bits.offset
connect sourceD.io.req.bits.tag, schedule.d.bits.tag
connect sourceD.io.req.bits.source, schedule.d.bits.source
connect sourceD.io.req.bits.size, schedule.d.bits.size
connect sourceD.io.req.bits.param, schedule.d.bits.param
connect sourceD.io.req.bits.opcode, schedule.d.bits.opcode
connect sourceD.io.req.bits.control, schedule.d.bits.control
connect sourceD.io.req.bits.prio[0], schedule.d.bits.prio[0]
connect sourceD.io.req.bits.prio[1], schedule.d.bits.prio[1]
connect sourceD.io.req.bits.prio[2], schedule.d.bits.prio[2]
connect sourceE.io.req.bits.sink, schedule.e.bits.sink
connect sourceX.io.req.bits.fail, schedule.x.bits.fail
connect directory.io.write.valid, schedule.dir.valid
connect directory.io.write.bits.data.tag, schedule.dir.bits.data.tag
connect directory.io.write.bits.data.clients, schedule.dir.bits.data.clients
connect directory.io.write.bits.data.state, schedule.dir.bits.data.state
connect directory.io.write.bits.data.dirty, schedule.dir.bits.data.dirty
connect directory.io.write.bits.way, schedule.dir.bits.way
connect directory.io.write.bits.set, schedule.dir.bits.set
node select_c = bits(mshr_selectOH, 11, 11)
node select_bc = bits(mshr_selectOH, 10, 10)
node _nestedwb_set_T = mux(select_c, mshrs_11.io.status.bits.set, mshrs_10.io.status.bits.set)
connect nestedwb.set, _nestedwb_set_T
node _nestedwb_tag_T = mux(select_c, mshrs_11.io.status.bits.tag, mshrs_10.io.status.bits.tag)
connect nestedwb.tag, _nestedwb_tag_T
node _nestedwb_b_toN_T = and(select_bc, mshrs_10.io.schedule.bits.dir.valid)
node _nestedwb_b_toN_T_1 = eq(mshrs_10.io.schedule.bits.dir.bits.data.state, UInt<2>(0h0))
node _nestedwb_b_toN_T_2 = and(_nestedwb_b_toN_T, _nestedwb_b_toN_T_1)
connect nestedwb.b_toN, _nestedwb_b_toN_T_2
node _nestedwb_b_toB_T = and(select_bc, mshrs_10.io.schedule.bits.dir.valid)
node _nestedwb_b_toB_T_1 = eq(mshrs_10.io.schedule.bits.dir.bits.data.state, UInt<2>(0h1))
node _nestedwb_b_toB_T_2 = and(_nestedwb_b_toB_T, _nestedwb_b_toB_T_1)
connect nestedwb.b_toB, _nestedwb_b_toB_T_2
node _nestedwb_b_clr_dirty_T = and(select_bc, mshrs_10.io.schedule.bits.dir.valid)
connect nestedwb.b_clr_dirty, _nestedwb_b_clr_dirty_T
node _nestedwb_c_set_dirty_T = and(select_c, mshrs_11.io.schedule.bits.dir.valid)
node _nestedwb_c_set_dirty_T_1 = and(_nestedwb_c_set_dirty_T, mshrs_11.io.schedule.bits.dir.bits.data.dirty)
connect nestedwb.c_set_dirty, _nestedwb_c_set_dirty_T_1
wire request : { flip ready : UInt<1>, valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}}
node _request_valid_T = or(sinkA.io.req.valid, sinkX.io.req.valid)
node _request_valid_T_1 = or(_request_valid_T, sinkC.io.req.valid)
node _request_valid_T_2 = and(directory.io.ready, _request_valid_T_1)
connect request.valid, _request_valid_T_2
node _request_bits_T = mux(sinkX.io.req.valid, sinkX.io.req.bits, sinkA.io.req.bits)
node _request_bits_T_1 = mux(sinkC.io.req.valid, sinkC.io.req.bits, _request_bits_T)
connect request.bits, _request_bits_T_1
node _sinkC_io_req_ready_T = and(directory.io.ready, request.ready)
connect sinkC.io.req.ready, _sinkC_io_req_ready_T
node _sinkX_io_req_ready_T = and(directory.io.ready, request.ready)
node _sinkX_io_req_ready_T_1 = eq(sinkC.io.req.valid, UInt<1>(0h0))
node _sinkX_io_req_ready_T_2 = and(_sinkX_io_req_ready_T, _sinkX_io_req_ready_T_1)
connect sinkX.io.req.ready, _sinkX_io_req_ready_T_2
node _sinkA_io_req_ready_T = and(directory.io.ready, request.ready)
node _sinkA_io_req_ready_T_1 = eq(sinkC.io.req.valid, UInt<1>(0h0))
node _sinkA_io_req_ready_T_2 = and(_sinkA_io_req_ready_T, _sinkA_io_req_ready_T_1)
node _sinkA_io_req_ready_T_3 = eq(sinkX.io.req.valid, UInt<1>(0h0))
node _sinkA_io_req_ready_T_4 = and(_sinkA_io_req_ready_T_2, _sinkA_io_req_ready_T_3)
connect sinkA.io.req.ready, _sinkA_io_req_ready_T_4
node _setMatches_T = eq(mshrs_0.io.status.bits.set, request.bits.set)
node _setMatches_T_1 = and(mshrs_0.io.status.valid, _setMatches_T)
node _setMatches_T_2 = eq(mshrs_1.io.status.bits.set, request.bits.set)
node _setMatches_T_3 = and(mshrs_1.io.status.valid, _setMatches_T_2)
node _setMatches_T_4 = eq(mshrs_2.io.status.bits.set, request.bits.set)
node _setMatches_T_5 = and(mshrs_2.io.status.valid, _setMatches_T_4)
node _setMatches_T_6 = eq(mshrs_3.io.status.bits.set, request.bits.set)
node _setMatches_T_7 = and(mshrs_3.io.status.valid, _setMatches_T_6)
node _setMatches_T_8 = eq(mshrs_4.io.status.bits.set, request.bits.set)
node _setMatches_T_9 = and(mshrs_4.io.status.valid, _setMatches_T_8)
node _setMatches_T_10 = eq(mshrs_5.io.status.bits.set, request.bits.set)
node _setMatches_T_11 = and(mshrs_5.io.status.valid, _setMatches_T_10)
node _setMatches_T_12 = eq(mshrs_6.io.status.bits.set, request.bits.set)
node _setMatches_T_13 = and(mshrs_6.io.status.valid, _setMatches_T_12)
node _setMatches_T_14 = eq(mshrs_7.io.status.bits.set, request.bits.set)
node _setMatches_T_15 = and(mshrs_7.io.status.valid, _setMatches_T_14)
node _setMatches_T_16 = eq(mshrs_8.io.status.bits.set, request.bits.set)
node _setMatches_T_17 = and(mshrs_8.io.status.valid, _setMatches_T_16)
node _setMatches_T_18 = eq(mshrs_9.io.status.bits.set, request.bits.set)
node _setMatches_T_19 = and(mshrs_9.io.status.valid, _setMatches_T_18)
node _setMatches_T_20 = eq(mshrs_10.io.status.bits.set, request.bits.set)
node _setMatches_T_21 = and(mshrs_10.io.status.valid, _setMatches_T_20)
node _setMatches_T_22 = eq(mshrs_11.io.status.bits.set, request.bits.set)
node _setMatches_T_23 = and(mshrs_11.io.status.valid, _setMatches_T_22)
node setMatches_lo_lo_hi = cat(_setMatches_T_5, _setMatches_T_3)
node setMatches_lo_lo = cat(setMatches_lo_lo_hi, _setMatches_T_1)
node setMatches_lo_hi_hi = cat(_setMatches_T_11, _setMatches_T_9)
node setMatches_lo_hi = cat(setMatches_lo_hi_hi, _setMatches_T_7)
node setMatches_lo = cat(setMatches_lo_hi, setMatches_lo_lo)
node setMatches_hi_lo_hi = cat(_setMatches_T_17, _setMatches_T_15)
node setMatches_hi_lo = cat(setMatches_hi_lo_hi, _setMatches_T_13)
node setMatches_hi_hi_hi = cat(_setMatches_T_23, _setMatches_T_21)
node setMatches_hi_hi = cat(setMatches_hi_hi_hi, _setMatches_T_19)
node setMatches_hi = cat(setMatches_hi_hi, setMatches_hi_lo)
node setMatches = cat(setMatches_hi, setMatches_lo)
node _alloc_T = orr(setMatches)
node alloc = eq(_alloc_T, UInt<1>(0h0))
node _blockB_T = bits(setMatches, 0, 0)
node _blockB_T_1 = bits(setMatches, 1, 1)
node _blockB_T_2 = bits(setMatches, 2, 2)
node _blockB_T_3 = bits(setMatches, 3, 3)
node _blockB_T_4 = bits(setMatches, 4, 4)
node _blockB_T_5 = bits(setMatches, 5, 5)
node _blockB_T_6 = bits(setMatches, 6, 6)
node _blockB_T_7 = bits(setMatches, 7, 7)
node _blockB_T_8 = bits(setMatches, 8, 8)
node _blockB_T_9 = bits(setMatches, 9, 9)
node _blockB_T_10 = bits(setMatches, 10, 10)
node _blockB_T_11 = bits(setMatches, 11, 11)
node _blockB_T_12 = mux(_blockB_T, mshrs_0.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_13 = mux(_blockB_T_1, mshrs_1.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_14 = mux(_blockB_T_2, mshrs_2.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_15 = mux(_blockB_T_3, mshrs_3.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_16 = mux(_blockB_T_4, mshrs_4.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_17 = mux(_blockB_T_5, mshrs_5.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_18 = mux(_blockB_T_6, mshrs_6.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_19 = mux(_blockB_T_7, mshrs_7.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_20 = mux(_blockB_T_8, mshrs_8.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_21 = mux(_blockB_T_9, mshrs_9.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_22 = mux(_blockB_T_10, mshrs_10.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_23 = mux(_blockB_T_11, mshrs_11.io.status.bits.blockB, UInt<1>(0h0))
node _blockB_T_24 = or(_blockB_T_12, _blockB_T_13)
node _blockB_T_25 = or(_blockB_T_24, _blockB_T_14)
node _blockB_T_26 = or(_blockB_T_25, _blockB_T_15)
node _blockB_T_27 = or(_blockB_T_26, _blockB_T_16)
node _blockB_T_28 = or(_blockB_T_27, _blockB_T_17)
node _blockB_T_29 = or(_blockB_T_28, _blockB_T_18)
node _blockB_T_30 = or(_blockB_T_29, _blockB_T_19)
node _blockB_T_31 = or(_blockB_T_30, _blockB_T_20)
node _blockB_T_32 = or(_blockB_T_31, _blockB_T_21)
node _blockB_T_33 = or(_blockB_T_32, _blockB_T_22)
node _blockB_T_34 = or(_blockB_T_33, _blockB_T_23)
wire _blockB_WIRE : UInt<1>
connect _blockB_WIRE, _blockB_T_34
node blockB = and(_blockB_WIRE, request.bits.prio[1])
node _blockC_T = bits(setMatches, 0, 0)
node _blockC_T_1 = bits(setMatches, 1, 1)
node _blockC_T_2 = bits(setMatches, 2, 2)
node _blockC_T_3 = bits(setMatches, 3, 3)
node _blockC_T_4 = bits(setMatches, 4, 4)
node _blockC_T_5 = bits(setMatches, 5, 5)
node _blockC_T_6 = bits(setMatches, 6, 6)
node _blockC_T_7 = bits(setMatches, 7, 7)
node _blockC_T_8 = bits(setMatches, 8, 8)
node _blockC_T_9 = bits(setMatches, 9, 9)
node _blockC_T_10 = bits(setMatches, 10, 10)
node _blockC_T_11 = bits(setMatches, 11, 11)
node _blockC_T_12 = mux(_blockC_T, mshrs_0.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_13 = mux(_blockC_T_1, mshrs_1.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_14 = mux(_blockC_T_2, mshrs_2.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_15 = mux(_blockC_T_3, mshrs_3.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_16 = mux(_blockC_T_4, mshrs_4.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_17 = mux(_blockC_T_5, mshrs_5.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_18 = mux(_blockC_T_6, mshrs_6.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_19 = mux(_blockC_T_7, mshrs_7.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_20 = mux(_blockC_T_8, mshrs_8.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_21 = mux(_blockC_T_9, mshrs_9.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_22 = mux(_blockC_T_10, mshrs_10.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_23 = mux(_blockC_T_11, mshrs_11.io.status.bits.blockC, UInt<1>(0h0))
node _blockC_T_24 = or(_blockC_T_12, _blockC_T_13)
node _blockC_T_25 = or(_blockC_T_24, _blockC_T_14)
node _blockC_T_26 = or(_blockC_T_25, _blockC_T_15)
node _blockC_T_27 = or(_blockC_T_26, _blockC_T_16)
node _blockC_T_28 = or(_blockC_T_27, _blockC_T_17)
node _blockC_T_29 = or(_blockC_T_28, _blockC_T_18)
node _blockC_T_30 = or(_blockC_T_29, _blockC_T_19)
node _blockC_T_31 = or(_blockC_T_30, _blockC_T_20)
node _blockC_T_32 = or(_blockC_T_31, _blockC_T_21)
node _blockC_T_33 = or(_blockC_T_32, _blockC_T_22)
node _blockC_T_34 = or(_blockC_T_33, _blockC_T_23)
wire _blockC_WIRE : UInt<1>
connect _blockC_WIRE, _blockC_T_34
node blockC = and(_blockC_WIRE, request.bits.prio[2])
node _nestB_T = bits(setMatches, 0, 0)
node _nestB_T_1 = bits(setMatches, 1, 1)
node _nestB_T_2 = bits(setMatches, 2, 2)
node _nestB_T_3 = bits(setMatches, 3, 3)
node _nestB_T_4 = bits(setMatches, 4, 4)
node _nestB_T_5 = bits(setMatches, 5, 5)
node _nestB_T_6 = bits(setMatches, 6, 6)
node _nestB_T_7 = bits(setMatches, 7, 7)
node _nestB_T_8 = bits(setMatches, 8, 8)
node _nestB_T_9 = bits(setMatches, 9, 9)
node _nestB_T_10 = bits(setMatches, 10, 10)
node _nestB_T_11 = bits(setMatches, 11, 11)
node _nestB_T_12 = mux(_nestB_T, mshrs_0.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_13 = mux(_nestB_T_1, mshrs_1.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_14 = mux(_nestB_T_2, mshrs_2.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_15 = mux(_nestB_T_3, mshrs_3.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_16 = mux(_nestB_T_4, mshrs_4.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_17 = mux(_nestB_T_5, mshrs_5.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_18 = mux(_nestB_T_6, mshrs_6.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_19 = mux(_nestB_T_7, mshrs_7.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_20 = mux(_nestB_T_8, mshrs_8.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_21 = mux(_nestB_T_9, mshrs_9.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_22 = mux(_nestB_T_10, mshrs_10.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_23 = mux(_nestB_T_11, mshrs_11.io.status.bits.nestB, UInt<1>(0h0))
node _nestB_T_24 = or(_nestB_T_12, _nestB_T_13)
node _nestB_T_25 = or(_nestB_T_24, _nestB_T_14)
node _nestB_T_26 = or(_nestB_T_25, _nestB_T_15)
node _nestB_T_27 = or(_nestB_T_26, _nestB_T_16)
node _nestB_T_28 = or(_nestB_T_27, _nestB_T_17)
node _nestB_T_29 = or(_nestB_T_28, _nestB_T_18)
node _nestB_T_30 = or(_nestB_T_29, _nestB_T_19)
node _nestB_T_31 = or(_nestB_T_30, _nestB_T_20)
node _nestB_T_32 = or(_nestB_T_31, _nestB_T_21)
node _nestB_T_33 = or(_nestB_T_32, _nestB_T_22)
node _nestB_T_34 = or(_nestB_T_33, _nestB_T_23)
wire _nestB_WIRE : UInt<1>
connect _nestB_WIRE, _nestB_T_34
node nestB = and(_nestB_WIRE, request.bits.prio[1])
node _nestC_T = bits(setMatches, 0, 0)
node _nestC_T_1 = bits(setMatches, 1, 1)
node _nestC_T_2 = bits(setMatches, 2, 2)
node _nestC_T_3 = bits(setMatches, 3, 3)
node _nestC_T_4 = bits(setMatches, 4, 4)
node _nestC_T_5 = bits(setMatches, 5, 5)
node _nestC_T_6 = bits(setMatches, 6, 6)
node _nestC_T_7 = bits(setMatches, 7, 7)
node _nestC_T_8 = bits(setMatches, 8, 8)
node _nestC_T_9 = bits(setMatches, 9, 9)
node _nestC_T_10 = bits(setMatches, 10, 10)
node _nestC_T_11 = bits(setMatches, 11, 11)
node _nestC_T_12 = mux(_nestC_T, mshrs_0.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_13 = mux(_nestC_T_1, mshrs_1.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_14 = mux(_nestC_T_2, mshrs_2.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_15 = mux(_nestC_T_3, mshrs_3.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_16 = mux(_nestC_T_4, mshrs_4.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_17 = mux(_nestC_T_5, mshrs_5.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_18 = mux(_nestC_T_6, mshrs_6.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_19 = mux(_nestC_T_7, mshrs_7.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_20 = mux(_nestC_T_8, mshrs_8.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_21 = mux(_nestC_T_9, mshrs_9.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_22 = mux(_nestC_T_10, mshrs_10.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_23 = mux(_nestC_T_11, mshrs_11.io.status.bits.nestC, UInt<1>(0h0))
node _nestC_T_24 = or(_nestC_T_12, _nestC_T_13)
node _nestC_T_25 = or(_nestC_T_24, _nestC_T_14)
node _nestC_T_26 = or(_nestC_T_25, _nestC_T_15)
node _nestC_T_27 = or(_nestC_T_26, _nestC_T_16)
node _nestC_T_28 = or(_nestC_T_27, _nestC_T_17)
node _nestC_T_29 = or(_nestC_T_28, _nestC_T_18)
node _nestC_T_30 = or(_nestC_T_29, _nestC_T_19)
node _nestC_T_31 = or(_nestC_T_30, _nestC_T_20)
node _nestC_T_32 = or(_nestC_T_31, _nestC_T_21)
node _nestC_T_33 = or(_nestC_T_32, _nestC_T_22)
node _nestC_T_34 = or(_nestC_T_33, _nestC_T_23)
wire _nestC_WIRE : UInt<1>
connect _nestC_WIRE, _nestC_T_34
node nestC = and(_nestC_WIRE, request.bits.prio[2])
node _prioFilter_T = eq(request.bits.prio[0], UInt<1>(0h0))
node _prioFilter_T_1 = not(UInt<10>(0h0))
node prioFilter_hi = cat(request.bits.prio[2], _prioFilter_T)
node prioFilter = cat(prioFilter_hi, _prioFilter_T_1)
node lowerMatches = and(setMatches, prioFilter)
node _queue_T = orr(lowerMatches)
node _queue_T_1 = eq(nestB, UInt<1>(0h0))
node _queue_T_2 = and(_queue_T, _queue_T_1)
node _queue_T_3 = eq(nestC, UInt<1>(0h0))
node _queue_T_4 = and(_queue_T_2, _queue_T_3)
node _queue_T_5 = eq(blockB, UInt<1>(0h0))
node _queue_T_6 = and(_queue_T_4, _queue_T_5)
node _queue_T_7 = eq(blockC, UInt<1>(0h0))
node queue = and(_queue_T_6, _queue_T_7)
node _T_10 = and(request.valid, blockC)
node _T_11 = and(request.valid, nestC)
node _T_12 = and(request.valid, queue)
node _lowerMatches1_T = bits(lowerMatches, 11, 11)
node _lowerMatches1_T_1 = shl(UInt<1>(0h1), 11)
node _lowerMatches1_T_2 = bits(lowerMatches, 10, 10)
node _lowerMatches1_T_3 = shl(UInt<1>(0h1), 10)
node _lowerMatches1_T_4 = mux(_lowerMatches1_T_2, _lowerMatches1_T_3, lowerMatches)
node lowerMatches1 = mux(_lowerMatches1_T, _lowerMatches1_T_1, _lowerMatches1_T_4)
node selected_requests_hi = cat(mshr_selectOH, mshr_selectOH)
node _selected_requests_T = cat(selected_requests_hi, mshr_selectOH)
node selected_requests = and(_selected_requests_T, requests.io.valid)
node _a_pop_T = bits(selected_requests, 11, 0)
node a_pop = orr(_a_pop_T)
node _b_pop_T = bits(selected_requests, 23, 12)
node b_pop = orr(_b_pop_T)
node _c_pop_T = bits(selected_requests, 35, 24)
node c_pop = orr(_c_pop_T)
node _bypassMatches_T = and(mshr_selectOH, lowerMatches1)
node _bypassMatches_T_1 = orr(_bypassMatches_T)
node _bypassMatches_T_2 = or(c_pop, request.bits.prio[2])
node _bypassMatches_T_3 = eq(c_pop, UInt<1>(0h0))
node _bypassMatches_T_4 = or(b_pop, request.bits.prio[1])
node _bypassMatches_T_5 = eq(b_pop, UInt<1>(0h0))
node _bypassMatches_T_6 = eq(a_pop, UInt<1>(0h0))
node _bypassMatches_T_7 = mux(_bypassMatches_T_4, _bypassMatches_T_5, _bypassMatches_T_6)
node _bypassMatches_T_8 = mux(_bypassMatches_T_2, _bypassMatches_T_3, _bypassMatches_T_7)
node bypassMatches = and(_bypassMatches_T_1, _bypassMatches_T_8)
node _may_pop_T = or(a_pop, b_pop)
node may_pop = or(_may_pop_T, c_pop)
node _bypass_T = and(request.valid, queue)
node bypass = and(_bypass_T, bypassMatches)
node _will_reload_T = or(may_pop, bypass)
node will_reload = and(schedule.reload, _will_reload_T)
node _will_pop_T = and(schedule.reload, may_pop)
node _will_pop_T_1 = eq(bypass, UInt<1>(0h0))
node will_pop = and(_will_pop_T, _will_pop_T_1)
node _T_13 = orr(mshr_selectOH)
node _T_14 = and(_T_13, bypass)
node _T_15 = orr(mshr_selectOH)
node _T_16 = and(_T_15, will_reload)
node _T_17 = orr(mshr_selectOH)
node _T_18 = and(_T_17, will_pop)
node sel = bits(mshr_selectOH, 0, 0)
connect mshrs_0.io.schedule.ready, sel
node a_pop_1 = bits(requests.io.valid, 0, 0)
node b_pop_1 = bits(requests.io.valid, 12, 12)
node c_pop_1 = bits(requests.io.valid, 24, 24)
node _bypassMatches_T_9 = bits(lowerMatches1, 0, 0)
node _bypassMatches_T_10 = or(c_pop_1, request.bits.prio[2])
node _bypassMatches_T_11 = eq(c_pop_1, UInt<1>(0h0))
node _bypassMatches_T_12 = or(b_pop_1, request.bits.prio[1])
node _bypassMatches_T_13 = eq(b_pop_1, UInt<1>(0h0))
node _bypassMatches_T_14 = eq(a_pop_1, UInt<1>(0h0))
node _bypassMatches_T_15 = mux(_bypassMatches_T_12, _bypassMatches_T_13, _bypassMatches_T_14)
node _bypassMatches_T_16 = mux(_bypassMatches_T_10, _bypassMatches_T_11, _bypassMatches_T_15)
node bypassMatches_1 = and(_bypassMatches_T_9, _bypassMatches_T_16)
node _may_pop_T_1 = or(a_pop_1, b_pop_1)
node may_pop_1 = or(_may_pop_T_1, c_pop_1)
node _bypass_T_1 = and(request.valid, queue)
node bypass_1 = and(_bypass_T_1, bypassMatches_1)
node _will_reload_T_1 = or(may_pop_1, bypass_1)
node will_reload_1 = and(mshrs_0.io.schedule.bits.reload, _will_reload_T_1)
wire _view__WIRE : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE.put, request.bits.put
connect _view__WIRE.offset, request.bits.offset
connect _view__WIRE.tag, request.bits.tag
connect _view__WIRE.source, request.bits.source
connect _view__WIRE.size, request.bits.size
connect _view__WIRE.param, request.bits.param
connect _view__WIRE.opcode, request.bits.opcode
connect _view__WIRE.control, request.bits.control
connect _view__WIRE.prio, request.bits.prio
node _view__T = mux(bypass_1, _view__WIRE, requests.io.data)
connect mshrs_0.io.allocate.bits.put, _view__T.put
connect mshrs_0.io.allocate.bits.offset, _view__T.offset
connect mshrs_0.io.allocate.bits.tag, _view__T.tag
connect mshrs_0.io.allocate.bits.source, _view__T.source
connect mshrs_0.io.allocate.bits.size, _view__T.size
connect mshrs_0.io.allocate.bits.param, _view__T.param
connect mshrs_0.io.allocate.bits.opcode, _view__T.opcode
connect mshrs_0.io.allocate.bits.control, _view__T.control
connect mshrs_0.io.allocate.bits.prio[0], _view__T.prio[0]
connect mshrs_0.io.allocate.bits.prio[1], _view__T.prio[1]
connect mshrs_0.io.allocate.bits.prio[2], _view__T.prio[2]
connect mshrs_0.io.allocate.bits.set, mshrs_0.io.status.bits.set
node _mshrs_0_io_allocate_bits_repeat_T = eq(mshrs_0.io.allocate.bits.tag, mshrs_0.io.status.bits.tag)
connect mshrs_0.io.allocate.bits.repeat, _mshrs_0_io_allocate_bits_repeat_T
node _mshrs_0_io_allocate_valid_T = and(sel, will_reload_1)
connect mshrs_0.io.allocate.valid, _mshrs_0_io_allocate_valid_T
node sel_1 = bits(mshr_selectOH, 1, 1)
connect mshrs_1.io.schedule.ready, sel_1
node a_pop_2 = bits(requests.io.valid, 1, 1)
node b_pop_2 = bits(requests.io.valid, 13, 13)
node c_pop_2 = bits(requests.io.valid, 25, 25)
node _bypassMatches_T_17 = bits(lowerMatches1, 1, 1)
node _bypassMatches_T_18 = or(c_pop_2, request.bits.prio[2])
node _bypassMatches_T_19 = eq(c_pop_2, UInt<1>(0h0))
node _bypassMatches_T_20 = or(b_pop_2, request.bits.prio[1])
node _bypassMatches_T_21 = eq(b_pop_2, UInt<1>(0h0))
node _bypassMatches_T_22 = eq(a_pop_2, UInt<1>(0h0))
node _bypassMatches_T_23 = mux(_bypassMatches_T_20, _bypassMatches_T_21, _bypassMatches_T_22)
node _bypassMatches_T_24 = mux(_bypassMatches_T_18, _bypassMatches_T_19, _bypassMatches_T_23)
node bypassMatches_2 = and(_bypassMatches_T_17, _bypassMatches_T_24)
node _may_pop_T_2 = or(a_pop_2, b_pop_2)
node may_pop_2 = or(_may_pop_T_2, c_pop_2)
node _bypass_T_2 = and(request.valid, queue)
node bypass_2 = and(_bypass_T_2, bypassMatches_2)
node _will_reload_T_2 = or(may_pop_2, bypass_2)
node will_reload_2 = and(mshrs_1.io.schedule.bits.reload, _will_reload_T_2)
wire _view__WIRE_1 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_1.put, request.bits.put
connect _view__WIRE_1.offset, request.bits.offset
connect _view__WIRE_1.tag, request.bits.tag
connect _view__WIRE_1.source, request.bits.source
connect _view__WIRE_1.size, request.bits.size
connect _view__WIRE_1.param, request.bits.param
connect _view__WIRE_1.opcode, request.bits.opcode
connect _view__WIRE_1.control, request.bits.control
connect _view__WIRE_1.prio, request.bits.prio
node _view__T_1 = mux(bypass_2, _view__WIRE_1, requests.io.data)
connect mshrs_1.io.allocate.bits.put, _view__T_1.put
connect mshrs_1.io.allocate.bits.offset, _view__T_1.offset
connect mshrs_1.io.allocate.bits.tag, _view__T_1.tag
connect mshrs_1.io.allocate.bits.source, _view__T_1.source
connect mshrs_1.io.allocate.bits.size, _view__T_1.size
connect mshrs_1.io.allocate.bits.param, _view__T_1.param
connect mshrs_1.io.allocate.bits.opcode, _view__T_1.opcode
connect mshrs_1.io.allocate.bits.control, _view__T_1.control
connect mshrs_1.io.allocate.bits.prio[0], _view__T_1.prio[0]
connect mshrs_1.io.allocate.bits.prio[1], _view__T_1.prio[1]
connect mshrs_1.io.allocate.bits.prio[2], _view__T_1.prio[2]
connect mshrs_1.io.allocate.bits.set, mshrs_1.io.status.bits.set
node _mshrs_1_io_allocate_bits_repeat_T = eq(mshrs_1.io.allocate.bits.tag, mshrs_1.io.status.bits.tag)
connect mshrs_1.io.allocate.bits.repeat, _mshrs_1_io_allocate_bits_repeat_T
node _mshrs_1_io_allocate_valid_T = and(sel_1, will_reload_2)
connect mshrs_1.io.allocate.valid, _mshrs_1_io_allocate_valid_T
node sel_2 = bits(mshr_selectOH, 2, 2)
connect mshrs_2.io.schedule.ready, sel_2
node a_pop_3 = bits(requests.io.valid, 2, 2)
node b_pop_3 = bits(requests.io.valid, 14, 14)
node c_pop_3 = bits(requests.io.valid, 26, 26)
node _bypassMatches_T_25 = bits(lowerMatches1, 2, 2)
node _bypassMatches_T_26 = or(c_pop_3, request.bits.prio[2])
node _bypassMatches_T_27 = eq(c_pop_3, UInt<1>(0h0))
node _bypassMatches_T_28 = or(b_pop_3, request.bits.prio[1])
node _bypassMatches_T_29 = eq(b_pop_3, UInt<1>(0h0))
node _bypassMatches_T_30 = eq(a_pop_3, UInt<1>(0h0))
node _bypassMatches_T_31 = mux(_bypassMatches_T_28, _bypassMatches_T_29, _bypassMatches_T_30)
node _bypassMatches_T_32 = mux(_bypassMatches_T_26, _bypassMatches_T_27, _bypassMatches_T_31)
node bypassMatches_3 = and(_bypassMatches_T_25, _bypassMatches_T_32)
node _may_pop_T_3 = or(a_pop_3, b_pop_3)
node may_pop_3 = or(_may_pop_T_3, c_pop_3)
node _bypass_T_3 = and(request.valid, queue)
node bypass_3 = and(_bypass_T_3, bypassMatches_3)
node _will_reload_T_3 = or(may_pop_3, bypass_3)
node will_reload_3 = and(mshrs_2.io.schedule.bits.reload, _will_reload_T_3)
wire _view__WIRE_2 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_2.put, request.bits.put
connect _view__WIRE_2.offset, request.bits.offset
connect _view__WIRE_2.tag, request.bits.tag
connect _view__WIRE_2.source, request.bits.source
connect _view__WIRE_2.size, request.bits.size
connect _view__WIRE_2.param, request.bits.param
connect _view__WIRE_2.opcode, request.bits.opcode
connect _view__WIRE_2.control, request.bits.control
connect _view__WIRE_2.prio, request.bits.prio
node _view__T_2 = mux(bypass_3, _view__WIRE_2, requests.io.data)
connect mshrs_2.io.allocate.bits.put, _view__T_2.put
connect mshrs_2.io.allocate.bits.offset, _view__T_2.offset
connect mshrs_2.io.allocate.bits.tag, _view__T_2.tag
connect mshrs_2.io.allocate.bits.source, _view__T_2.source
connect mshrs_2.io.allocate.bits.size, _view__T_2.size
connect mshrs_2.io.allocate.bits.param, _view__T_2.param
connect mshrs_2.io.allocate.bits.opcode, _view__T_2.opcode
connect mshrs_2.io.allocate.bits.control, _view__T_2.control
connect mshrs_2.io.allocate.bits.prio[0], _view__T_2.prio[0]
connect mshrs_2.io.allocate.bits.prio[1], _view__T_2.prio[1]
connect mshrs_2.io.allocate.bits.prio[2], _view__T_2.prio[2]
connect mshrs_2.io.allocate.bits.set, mshrs_2.io.status.bits.set
node _mshrs_2_io_allocate_bits_repeat_T = eq(mshrs_2.io.allocate.bits.tag, mshrs_2.io.status.bits.tag)
connect mshrs_2.io.allocate.bits.repeat, _mshrs_2_io_allocate_bits_repeat_T
node _mshrs_2_io_allocate_valid_T = and(sel_2, will_reload_3)
connect mshrs_2.io.allocate.valid, _mshrs_2_io_allocate_valid_T
node sel_3 = bits(mshr_selectOH, 3, 3)
connect mshrs_3.io.schedule.ready, sel_3
node a_pop_4 = bits(requests.io.valid, 3, 3)
node b_pop_4 = bits(requests.io.valid, 15, 15)
node c_pop_4 = bits(requests.io.valid, 27, 27)
node _bypassMatches_T_33 = bits(lowerMatches1, 3, 3)
node _bypassMatches_T_34 = or(c_pop_4, request.bits.prio[2])
node _bypassMatches_T_35 = eq(c_pop_4, UInt<1>(0h0))
node _bypassMatches_T_36 = or(b_pop_4, request.bits.prio[1])
node _bypassMatches_T_37 = eq(b_pop_4, UInt<1>(0h0))
node _bypassMatches_T_38 = eq(a_pop_4, UInt<1>(0h0))
node _bypassMatches_T_39 = mux(_bypassMatches_T_36, _bypassMatches_T_37, _bypassMatches_T_38)
node _bypassMatches_T_40 = mux(_bypassMatches_T_34, _bypassMatches_T_35, _bypassMatches_T_39)
node bypassMatches_4 = and(_bypassMatches_T_33, _bypassMatches_T_40)
node _may_pop_T_4 = or(a_pop_4, b_pop_4)
node may_pop_4 = or(_may_pop_T_4, c_pop_4)
node _bypass_T_4 = and(request.valid, queue)
node bypass_4 = and(_bypass_T_4, bypassMatches_4)
node _will_reload_T_4 = or(may_pop_4, bypass_4)
node will_reload_4 = and(mshrs_3.io.schedule.bits.reload, _will_reload_T_4)
wire _view__WIRE_3 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_3.put, request.bits.put
connect _view__WIRE_3.offset, request.bits.offset
connect _view__WIRE_3.tag, request.bits.tag
connect _view__WIRE_3.source, request.bits.source
connect _view__WIRE_3.size, request.bits.size
connect _view__WIRE_3.param, request.bits.param
connect _view__WIRE_3.opcode, request.bits.opcode
connect _view__WIRE_3.control, request.bits.control
connect _view__WIRE_3.prio, request.bits.prio
node _view__T_3 = mux(bypass_4, _view__WIRE_3, requests.io.data)
connect mshrs_3.io.allocate.bits.put, _view__T_3.put
connect mshrs_3.io.allocate.bits.offset, _view__T_3.offset
connect mshrs_3.io.allocate.bits.tag, _view__T_3.tag
connect mshrs_3.io.allocate.bits.source, _view__T_3.source
connect mshrs_3.io.allocate.bits.size, _view__T_3.size
connect mshrs_3.io.allocate.bits.param, _view__T_3.param
connect mshrs_3.io.allocate.bits.opcode, _view__T_3.opcode
connect mshrs_3.io.allocate.bits.control, _view__T_3.control
connect mshrs_3.io.allocate.bits.prio[0], _view__T_3.prio[0]
connect mshrs_3.io.allocate.bits.prio[1], _view__T_3.prio[1]
connect mshrs_3.io.allocate.bits.prio[2], _view__T_3.prio[2]
connect mshrs_3.io.allocate.bits.set, mshrs_3.io.status.bits.set
node _mshrs_3_io_allocate_bits_repeat_T = eq(mshrs_3.io.allocate.bits.tag, mshrs_3.io.status.bits.tag)
connect mshrs_3.io.allocate.bits.repeat, _mshrs_3_io_allocate_bits_repeat_T
node _mshrs_3_io_allocate_valid_T = and(sel_3, will_reload_4)
connect mshrs_3.io.allocate.valid, _mshrs_3_io_allocate_valid_T
node sel_4 = bits(mshr_selectOH, 4, 4)
connect mshrs_4.io.schedule.ready, sel_4
node a_pop_5 = bits(requests.io.valid, 4, 4)
node b_pop_5 = bits(requests.io.valid, 16, 16)
node c_pop_5 = bits(requests.io.valid, 28, 28)
node _bypassMatches_T_41 = bits(lowerMatches1, 4, 4)
node _bypassMatches_T_42 = or(c_pop_5, request.bits.prio[2])
node _bypassMatches_T_43 = eq(c_pop_5, UInt<1>(0h0))
node _bypassMatches_T_44 = or(b_pop_5, request.bits.prio[1])
node _bypassMatches_T_45 = eq(b_pop_5, UInt<1>(0h0))
node _bypassMatches_T_46 = eq(a_pop_5, UInt<1>(0h0))
node _bypassMatches_T_47 = mux(_bypassMatches_T_44, _bypassMatches_T_45, _bypassMatches_T_46)
node _bypassMatches_T_48 = mux(_bypassMatches_T_42, _bypassMatches_T_43, _bypassMatches_T_47)
node bypassMatches_5 = and(_bypassMatches_T_41, _bypassMatches_T_48)
node _may_pop_T_5 = or(a_pop_5, b_pop_5)
node may_pop_5 = or(_may_pop_T_5, c_pop_5)
node _bypass_T_5 = and(request.valid, queue)
node bypass_5 = and(_bypass_T_5, bypassMatches_5)
node _will_reload_T_5 = or(may_pop_5, bypass_5)
node will_reload_5 = and(mshrs_4.io.schedule.bits.reload, _will_reload_T_5)
wire _view__WIRE_4 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_4.put, request.bits.put
connect _view__WIRE_4.offset, request.bits.offset
connect _view__WIRE_4.tag, request.bits.tag
connect _view__WIRE_4.source, request.bits.source
connect _view__WIRE_4.size, request.bits.size
connect _view__WIRE_4.param, request.bits.param
connect _view__WIRE_4.opcode, request.bits.opcode
connect _view__WIRE_4.control, request.bits.control
connect _view__WIRE_4.prio, request.bits.prio
node _view__T_4 = mux(bypass_5, _view__WIRE_4, requests.io.data)
connect mshrs_4.io.allocate.bits.put, _view__T_4.put
connect mshrs_4.io.allocate.bits.offset, _view__T_4.offset
connect mshrs_4.io.allocate.bits.tag, _view__T_4.tag
connect mshrs_4.io.allocate.bits.source, _view__T_4.source
connect mshrs_4.io.allocate.bits.size, _view__T_4.size
connect mshrs_4.io.allocate.bits.param, _view__T_4.param
connect mshrs_4.io.allocate.bits.opcode, _view__T_4.opcode
connect mshrs_4.io.allocate.bits.control, _view__T_4.control
connect mshrs_4.io.allocate.bits.prio[0], _view__T_4.prio[0]
connect mshrs_4.io.allocate.bits.prio[1], _view__T_4.prio[1]
connect mshrs_4.io.allocate.bits.prio[2], _view__T_4.prio[2]
connect mshrs_4.io.allocate.bits.set, mshrs_4.io.status.bits.set
node _mshrs_4_io_allocate_bits_repeat_T = eq(mshrs_4.io.allocate.bits.tag, mshrs_4.io.status.bits.tag)
connect mshrs_4.io.allocate.bits.repeat, _mshrs_4_io_allocate_bits_repeat_T
node _mshrs_4_io_allocate_valid_T = and(sel_4, will_reload_5)
connect mshrs_4.io.allocate.valid, _mshrs_4_io_allocate_valid_T
node sel_5 = bits(mshr_selectOH, 5, 5)
connect mshrs_5.io.schedule.ready, sel_5
node a_pop_6 = bits(requests.io.valid, 5, 5)
node b_pop_6 = bits(requests.io.valid, 17, 17)
node c_pop_6 = bits(requests.io.valid, 29, 29)
node _bypassMatches_T_49 = bits(lowerMatches1, 5, 5)
node _bypassMatches_T_50 = or(c_pop_6, request.bits.prio[2])
node _bypassMatches_T_51 = eq(c_pop_6, UInt<1>(0h0))
node _bypassMatches_T_52 = or(b_pop_6, request.bits.prio[1])
node _bypassMatches_T_53 = eq(b_pop_6, UInt<1>(0h0))
node _bypassMatches_T_54 = eq(a_pop_6, UInt<1>(0h0))
node _bypassMatches_T_55 = mux(_bypassMatches_T_52, _bypassMatches_T_53, _bypassMatches_T_54)
node _bypassMatches_T_56 = mux(_bypassMatches_T_50, _bypassMatches_T_51, _bypassMatches_T_55)
node bypassMatches_6 = and(_bypassMatches_T_49, _bypassMatches_T_56)
node _may_pop_T_6 = or(a_pop_6, b_pop_6)
node may_pop_6 = or(_may_pop_T_6, c_pop_6)
node _bypass_T_6 = and(request.valid, queue)
node bypass_6 = and(_bypass_T_6, bypassMatches_6)
node _will_reload_T_6 = or(may_pop_6, bypass_6)
node will_reload_6 = and(mshrs_5.io.schedule.bits.reload, _will_reload_T_6)
wire _view__WIRE_5 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_5.put, request.bits.put
connect _view__WIRE_5.offset, request.bits.offset
connect _view__WIRE_5.tag, request.bits.tag
connect _view__WIRE_5.source, request.bits.source
connect _view__WIRE_5.size, request.bits.size
connect _view__WIRE_5.param, request.bits.param
connect _view__WIRE_5.opcode, request.bits.opcode
connect _view__WIRE_5.control, request.bits.control
connect _view__WIRE_5.prio, request.bits.prio
node _view__T_5 = mux(bypass_6, _view__WIRE_5, requests.io.data)
connect mshrs_5.io.allocate.bits.put, _view__T_5.put
connect mshrs_5.io.allocate.bits.offset, _view__T_5.offset
connect mshrs_5.io.allocate.bits.tag, _view__T_5.tag
connect mshrs_5.io.allocate.bits.source, _view__T_5.source
connect mshrs_5.io.allocate.bits.size, _view__T_5.size
connect mshrs_5.io.allocate.bits.param, _view__T_5.param
connect mshrs_5.io.allocate.bits.opcode, _view__T_5.opcode
connect mshrs_5.io.allocate.bits.control, _view__T_5.control
connect mshrs_5.io.allocate.bits.prio[0], _view__T_5.prio[0]
connect mshrs_5.io.allocate.bits.prio[1], _view__T_5.prio[1]
connect mshrs_5.io.allocate.bits.prio[2], _view__T_5.prio[2]
connect mshrs_5.io.allocate.bits.set, mshrs_5.io.status.bits.set
node _mshrs_5_io_allocate_bits_repeat_T = eq(mshrs_5.io.allocate.bits.tag, mshrs_5.io.status.bits.tag)
connect mshrs_5.io.allocate.bits.repeat, _mshrs_5_io_allocate_bits_repeat_T
node _mshrs_5_io_allocate_valid_T = and(sel_5, will_reload_6)
connect mshrs_5.io.allocate.valid, _mshrs_5_io_allocate_valid_T
node sel_6 = bits(mshr_selectOH, 6, 6)
connect mshrs_6.io.schedule.ready, sel_6
node a_pop_7 = bits(requests.io.valid, 6, 6)
node b_pop_7 = bits(requests.io.valid, 18, 18)
node c_pop_7 = bits(requests.io.valid, 30, 30)
node _bypassMatches_T_57 = bits(lowerMatches1, 6, 6)
node _bypassMatches_T_58 = or(c_pop_7, request.bits.prio[2])
node _bypassMatches_T_59 = eq(c_pop_7, UInt<1>(0h0))
node _bypassMatches_T_60 = or(b_pop_7, request.bits.prio[1])
node _bypassMatches_T_61 = eq(b_pop_7, UInt<1>(0h0))
node _bypassMatches_T_62 = eq(a_pop_7, UInt<1>(0h0))
node _bypassMatches_T_63 = mux(_bypassMatches_T_60, _bypassMatches_T_61, _bypassMatches_T_62)
node _bypassMatches_T_64 = mux(_bypassMatches_T_58, _bypassMatches_T_59, _bypassMatches_T_63)
node bypassMatches_7 = and(_bypassMatches_T_57, _bypassMatches_T_64)
node _may_pop_T_7 = or(a_pop_7, b_pop_7)
node may_pop_7 = or(_may_pop_T_7, c_pop_7)
node _bypass_T_7 = and(request.valid, queue)
node bypass_7 = and(_bypass_T_7, bypassMatches_7)
node _will_reload_T_7 = or(may_pop_7, bypass_7)
node will_reload_7 = and(mshrs_6.io.schedule.bits.reload, _will_reload_T_7)
wire _view__WIRE_6 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_6.put, request.bits.put
connect _view__WIRE_6.offset, request.bits.offset
connect _view__WIRE_6.tag, request.bits.tag
connect _view__WIRE_6.source, request.bits.source
connect _view__WIRE_6.size, request.bits.size
connect _view__WIRE_6.param, request.bits.param
connect _view__WIRE_6.opcode, request.bits.opcode
connect _view__WIRE_6.control, request.bits.control
connect _view__WIRE_6.prio, request.bits.prio
node _view__T_6 = mux(bypass_7, _view__WIRE_6, requests.io.data)
connect mshrs_6.io.allocate.bits.put, _view__T_6.put
connect mshrs_6.io.allocate.bits.offset, _view__T_6.offset
connect mshrs_6.io.allocate.bits.tag, _view__T_6.tag
connect mshrs_6.io.allocate.bits.source, _view__T_6.source
connect mshrs_6.io.allocate.bits.size, _view__T_6.size
connect mshrs_6.io.allocate.bits.param, _view__T_6.param
connect mshrs_6.io.allocate.bits.opcode, _view__T_6.opcode
connect mshrs_6.io.allocate.bits.control, _view__T_6.control
connect mshrs_6.io.allocate.bits.prio[0], _view__T_6.prio[0]
connect mshrs_6.io.allocate.bits.prio[1], _view__T_6.prio[1]
connect mshrs_6.io.allocate.bits.prio[2], _view__T_6.prio[2]
connect mshrs_6.io.allocate.bits.set, mshrs_6.io.status.bits.set
node _mshrs_6_io_allocate_bits_repeat_T = eq(mshrs_6.io.allocate.bits.tag, mshrs_6.io.status.bits.tag)
connect mshrs_6.io.allocate.bits.repeat, _mshrs_6_io_allocate_bits_repeat_T
node _mshrs_6_io_allocate_valid_T = and(sel_6, will_reload_7)
connect mshrs_6.io.allocate.valid, _mshrs_6_io_allocate_valid_T
node sel_7 = bits(mshr_selectOH, 7, 7)
connect mshrs_7.io.schedule.ready, sel_7
node a_pop_8 = bits(requests.io.valid, 7, 7)
node b_pop_8 = bits(requests.io.valid, 19, 19)
node c_pop_8 = bits(requests.io.valid, 31, 31)
node _bypassMatches_T_65 = bits(lowerMatches1, 7, 7)
node _bypassMatches_T_66 = or(c_pop_8, request.bits.prio[2])
node _bypassMatches_T_67 = eq(c_pop_8, UInt<1>(0h0))
node _bypassMatches_T_68 = or(b_pop_8, request.bits.prio[1])
node _bypassMatches_T_69 = eq(b_pop_8, UInt<1>(0h0))
node _bypassMatches_T_70 = eq(a_pop_8, UInt<1>(0h0))
node _bypassMatches_T_71 = mux(_bypassMatches_T_68, _bypassMatches_T_69, _bypassMatches_T_70)
node _bypassMatches_T_72 = mux(_bypassMatches_T_66, _bypassMatches_T_67, _bypassMatches_T_71)
node bypassMatches_8 = and(_bypassMatches_T_65, _bypassMatches_T_72)
node _may_pop_T_8 = or(a_pop_8, b_pop_8)
node may_pop_8 = or(_may_pop_T_8, c_pop_8)
node _bypass_T_8 = and(request.valid, queue)
node bypass_8 = and(_bypass_T_8, bypassMatches_8)
node _will_reload_T_8 = or(may_pop_8, bypass_8)
node will_reload_8 = and(mshrs_7.io.schedule.bits.reload, _will_reload_T_8)
wire _view__WIRE_7 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_7.put, request.bits.put
connect _view__WIRE_7.offset, request.bits.offset
connect _view__WIRE_7.tag, request.bits.tag
connect _view__WIRE_7.source, request.bits.source
connect _view__WIRE_7.size, request.bits.size
connect _view__WIRE_7.param, request.bits.param
connect _view__WIRE_7.opcode, request.bits.opcode
connect _view__WIRE_7.control, request.bits.control
connect _view__WIRE_7.prio, request.bits.prio
node _view__T_7 = mux(bypass_8, _view__WIRE_7, requests.io.data)
connect mshrs_7.io.allocate.bits.put, _view__T_7.put
connect mshrs_7.io.allocate.bits.offset, _view__T_7.offset
connect mshrs_7.io.allocate.bits.tag, _view__T_7.tag
connect mshrs_7.io.allocate.bits.source, _view__T_7.source
connect mshrs_7.io.allocate.bits.size, _view__T_7.size
connect mshrs_7.io.allocate.bits.param, _view__T_7.param
connect mshrs_7.io.allocate.bits.opcode, _view__T_7.opcode
connect mshrs_7.io.allocate.bits.control, _view__T_7.control
connect mshrs_7.io.allocate.bits.prio[0], _view__T_7.prio[0]
connect mshrs_7.io.allocate.bits.prio[1], _view__T_7.prio[1]
connect mshrs_7.io.allocate.bits.prio[2], _view__T_7.prio[2]
connect mshrs_7.io.allocate.bits.set, mshrs_7.io.status.bits.set
node _mshrs_7_io_allocate_bits_repeat_T = eq(mshrs_7.io.allocate.bits.tag, mshrs_7.io.status.bits.tag)
connect mshrs_7.io.allocate.bits.repeat, _mshrs_7_io_allocate_bits_repeat_T
node _mshrs_7_io_allocate_valid_T = and(sel_7, will_reload_8)
connect mshrs_7.io.allocate.valid, _mshrs_7_io_allocate_valid_T
node sel_8 = bits(mshr_selectOH, 8, 8)
connect mshrs_8.io.schedule.ready, sel_8
node a_pop_9 = bits(requests.io.valid, 8, 8)
node b_pop_9 = bits(requests.io.valid, 20, 20)
node c_pop_9 = bits(requests.io.valid, 32, 32)
node _bypassMatches_T_73 = bits(lowerMatches1, 8, 8)
node _bypassMatches_T_74 = or(c_pop_9, request.bits.prio[2])
node _bypassMatches_T_75 = eq(c_pop_9, UInt<1>(0h0))
node _bypassMatches_T_76 = or(b_pop_9, request.bits.prio[1])
node _bypassMatches_T_77 = eq(b_pop_9, UInt<1>(0h0))
node _bypassMatches_T_78 = eq(a_pop_9, UInt<1>(0h0))
node _bypassMatches_T_79 = mux(_bypassMatches_T_76, _bypassMatches_T_77, _bypassMatches_T_78)
node _bypassMatches_T_80 = mux(_bypassMatches_T_74, _bypassMatches_T_75, _bypassMatches_T_79)
node bypassMatches_9 = and(_bypassMatches_T_73, _bypassMatches_T_80)
node _may_pop_T_9 = or(a_pop_9, b_pop_9)
node may_pop_9 = or(_may_pop_T_9, c_pop_9)
node _bypass_T_9 = and(request.valid, queue)
node bypass_9 = and(_bypass_T_9, bypassMatches_9)
node _will_reload_T_9 = or(may_pop_9, bypass_9)
node will_reload_9 = and(mshrs_8.io.schedule.bits.reload, _will_reload_T_9)
wire _view__WIRE_8 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_8.put, request.bits.put
connect _view__WIRE_8.offset, request.bits.offset
connect _view__WIRE_8.tag, request.bits.tag
connect _view__WIRE_8.source, request.bits.source
connect _view__WIRE_8.size, request.bits.size
connect _view__WIRE_8.param, request.bits.param
connect _view__WIRE_8.opcode, request.bits.opcode
connect _view__WIRE_8.control, request.bits.control
connect _view__WIRE_8.prio, request.bits.prio
node _view__T_8 = mux(bypass_9, _view__WIRE_8, requests.io.data)
connect mshrs_8.io.allocate.bits.put, _view__T_8.put
connect mshrs_8.io.allocate.bits.offset, _view__T_8.offset
connect mshrs_8.io.allocate.bits.tag, _view__T_8.tag
connect mshrs_8.io.allocate.bits.source, _view__T_8.source
connect mshrs_8.io.allocate.bits.size, _view__T_8.size
connect mshrs_8.io.allocate.bits.param, _view__T_8.param
connect mshrs_8.io.allocate.bits.opcode, _view__T_8.opcode
connect mshrs_8.io.allocate.bits.control, _view__T_8.control
connect mshrs_8.io.allocate.bits.prio[0], _view__T_8.prio[0]
connect mshrs_8.io.allocate.bits.prio[1], _view__T_8.prio[1]
connect mshrs_8.io.allocate.bits.prio[2], _view__T_8.prio[2]
connect mshrs_8.io.allocate.bits.set, mshrs_8.io.status.bits.set
node _mshrs_8_io_allocate_bits_repeat_T = eq(mshrs_8.io.allocate.bits.tag, mshrs_8.io.status.bits.tag)
connect mshrs_8.io.allocate.bits.repeat, _mshrs_8_io_allocate_bits_repeat_T
node _mshrs_8_io_allocate_valid_T = and(sel_8, will_reload_9)
connect mshrs_8.io.allocate.valid, _mshrs_8_io_allocate_valid_T
node sel_9 = bits(mshr_selectOH, 9, 9)
connect mshrs_9.io.schedule.ready, sel_9
node a_pop_10 = bits(requests.io.valid, 9, 9)
node b_pop_10 = bits(requests.io.valid, 21, 21)
node c_pop_10 = bits(requests.io.valid, 33, 33)
node _bypassMatches_T_81 = bits(lowerMatches1, 9, 9)
node _bypassMatches_T_82 = or(c_pop_10, request.bits.prio[2])
node _bypassMatches_T_83 = eq(c_pop_10, UInt<1>(0h0))
node _bypassMatches_T_84 = or(b_pop_10, request.bits.prio[1])
node _bypassMatches_T_85 = eq(b_pop_10, UInt<1>(0h0))
node _bypassMatches_T_86 = eq(a_pop_10, UInt<1>(0h0))
node _bypassMatches_T_87 = mux(_bypassMatches_T_84, _bypassMatches_T_85, _bypassMatches_T_86)
node _bypassMatches_T_88 = mux(_bypassMatches_T_82, _bypassMatches_T_83, _bypassMatches_T_87)
node bypassMatches_10 = and(_bypassMatches_T_81, _bypassMatches_T_88)
node _may_pop_T_10 = or(a_pop_10, b_pop_10)
node may_pop_10 = or(_may_pop_T_10, c_pop_10)
node _bypass_T_10 = and(request.valid, queue)
node bypass_10 = and(_bypass_T_10, bypassMatches_10)
node _will_reload_T_10 = or(may_pop_10, bypass_10)
node will_reload_10 = and(mshrs_9.io.schedule.bits.reload, _will_reload_T_10)
wire _view__WIRE_9 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_9.put, request.bits.put
connect _view__WIRE_9.offset, request.bits.offset
connect _view__WIRE_9.tag, request.bits.tag
connect _view__WIRE_9.source, request.bits.source
connect _view__WIRE_9.size, request.bits.size
connect _view__WIRE_9.param, request.bits.param
connect _view__WIRE_9.opcode, request.bits.opcode
connect _view__WIRE_9.control, request.bits.control
connect _view__WIRE_9.prio, request.bits.prio
node _view__T_9 = mux(bypass_10, _view__WIRE_9, requests.io.data)
connect mshrs_9.io.allocate.bits.put, _view__T_9.put
connect mshrs_9.io.allocate.bits.offset, _view__T_9.offset
connect mshrs_9.io.allocate.bits.tag, _view__T_9.tag
connect mshrs_9.io.allocate.bits.source, _view__T_9.source
connect mshrs_9.io.allocate.bits.size, _view__T_9.size
connect mshrs_9.io.allocate.bits.param, _view__T_9.param
connect mshrs_9.io.allocate.bits.opcode, _view__T_9.opcode
connect mshrs_9.io.allocate.bits.control, _view__T_9.control
connect mshrs_9.io.allocate.bits.prio[0], _view__T_9.prio[0]
connect mshrs_9.io.allocate.bits.prio[1], _view__T_9.prio[1]
connect mshrs_9.io.allocate.bits.prio[2], _view__T_9.prio[2]
connect mshrs_9.io.allocate.bits.set, mshrs_9.io.status.bits.set
node _mshrs_9_io_allocate_bits_repeat_T = eq(mshrs_9.io.allocate.bits.tag, mshrs_9.io.status.bits.tag)
connect mshrs_9.io.allocate.bits.repeat, _mshrs_9_io_allocate_bits_repeat_T
node _mshrs_9_io_allocate_valid_T = and(sel_9, will_reload_10)
connect mshrs_9.io.allocate.valid, _mshrs_9_io_allocate_valid_T
node sel_10 = bits(mshr_selectOH, 10, 10)
connect mshrs_10.io.schedule.ready, sel_10
node a_pop_11 = bits(requests.io.valid, 10, 10)
node b_pop_11 = bits(requests.io.valid, 22, 22)
node c_pop_11 = bits(requests.io.valid, 34, 34)
node _bypassMatches_T_89 = bits(lowerMatches1, 10, 10)
node _bypassMatches_T_90 = or(c_pop_11, request.bits.prio[2])
node _bypassMatches_T_91 = eq(c_pop_11, UInt<1>(0h0))
node _bypassMatches_T_92 = or(b_pop_11, request.bits.prio[1])
node _bypassMatches_T_93 = eq(b_pop_11, UInt<1>(0h0))
node _bypassMatches_T_94 = eq(a_pop_11, UInt<1>(0h0))
node _bypassMatches_T_95 = mux(_bypassMatches_T_92, _bypassMatches_T_93, _bypassMatches_T_94)
node _bypassMatches_T_96 = mux(_bypassMatches_T_90, _bypassMatches_T_91, _bypassMatches_T_95)
node bypassMatches_11 = and(_bypassMatches_T_89, _bypassMatches_T_96)
node _may_pop_T_11 = or(a_pop_11, b_pop_11)
node may_pop_11 = or(_may_pop_T_11, c_pop_11)
node _bypass_T_11 = and(request.valid, queue)
node bypass_11 = and(_bypass_T_11, bypassMatches_11)
node _will_reload_T_11 = or(may_pop_11, bypass_11)
node will_reload_11 = and(mshrs_10.io.schedule.bits.reload, _will_reload_T_11)
wire _view__WIRE_10 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_10.put, request.bits.put
connect _view__WIRE_10.offset, request.bits.offset
connect _view__WIRE_10.tag, request.bits.tag
connect _view__WIRE_10.source, request.bits.source
connect _view__WIRE_10.size, request.bits.size
connect _view__WIRE_10.param, request.bits.param
connect _view__WIRE_10.opcode, request.bits.opcode
connect _view__WIRE_10.control, request.bits.control
connect _view__WIRE_10.prio, request.bits.prio
node _view__T_10 = mux(bypass_11, _view__WIRE_10, requests.io.data)
connect mshrs_10.io.allocate.bits.put, _view__T_10.put
connect mshrs_10.io.allocate.bits.offset, _view__T_10.offset
connect mshrs_10.io.allocate.bits.tag, _view__T_10.tag
connect mshrs_10.io.allocate.bits.source, _view__T_10.source
connect mshrs_10.io.allocate.bits.size, _view__T_10.size
connect mshrs_10.io.allocate.bits.param, _view__T_10.param
connect mshrs_10.io.allocate.bits.opcode, _view__T_10.opcode
connect mshrs_10.io.allocate.bits.control, _view__T_10.control
connect mshrs_10.io.allocate.bits.prio[0], _view__T_10.prio[0]
connect mshrs_10.io.allocate.bits.prio[1], _view__T_10.prio[1]
connect mshrs_10.io.allocate.bits.prio[2], _view__T_10.prio[2]
connect mshrs_10.io.allocate.bits.set, mshrs_10.io.status.bits.set
node _mshrs_10_io_allocate_bits_repeat_T = eq(mshrs_10.io.allocate.bits.tag, mshrs_10.io.status.bits.tag)
connect mshrs_10.io.allocate.bits.repeat, _mshrs_10_io_allocate_bits_repeat_T
node _mshrs_10_io_allocate_valid_T = and(sel_10, will_reload_11)
connect mshrs_10.io.allocate.valid, _mshrs_10_io_allocate_valid_T
node sel_11 = bits(mshr_selectOH, 11, 11)
connect mshrs_11.io.schedule.ready, sel_11
node a_pop_12 = bits(requests.io.valid, 11, 11)
node b_pop_12 = bits(requests.io.valid, 23, 23)
node c_pop_12 = bits(requests.io.valid, 35, 35)
node _bypassMatches_T_97 = bits(lowerMatches1, 11, 11)
node _bypassMatches_T_98 = or(c_pop_12, request.bits.prio[2])
node _bypassMatches_T_99 = eq(c_pop_12, UInt<1>(0h0))
node _bypassMatches_T_100 = or(b_pop_12, request.bits.prio[1])
node _bypassMatches_T_101 = eq(b_pop_12, UInt<1>(0h0))
node _bypassMatches_T_102 = eq(a_pop_12, UInt<1>(0h0))
node _bypassMatches_T_103 = mux(_bypassMatches_T_100, _bypassMatches_T_101, _bypassMatches_T_102)
node _bypassMatches_T_104 = mux(_bypassMatches_T_98, _bypassMatches_T_99, _bypassMatches_T_103)
node bypassMatches_12 = and(_bypassMatches_T_97, _bypassMatches_T_104)
node _may_pop_T_12 = or(a_pop_12, b_pop_12)
node may_pop_12 = or(_may_pop_T_12, c_pop_12)
node _bypass_T_12 = and(request.valid, queue)
node bypass_12 = and(_bypass_T_12, bypassMatches_12)
node _will_reload_T_12 = or(may_pop_12, bypass_12)
node will_reload_12 = and(mshrs_11.io.schedule.bits.reload, _will_reload_T_12)
wire _view__WIRE_11 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>}
connect _view__WIRE_11.put, request.bits.put
connect _view__WIRE_11.offset, request.bits.offset
connect _view__WIRE_11.tag, request.bits.tag
connect _view__WIRE_11.source, request.bits.source
connect _view__WIRE_11.size, request.bits.size
connect _view__WIRE_11.param, request.bits.param
connect _view__WIRE_11.opcode, request.bits.opcode
connect _view__WIRE_11.control, request.bits.control
connect _view__WIRE_11.prio, request.bits.prio
node _view__T_11 = mux(bypass_12, _view__WIRE_11, requests.io.data)
connect mshrs_11.io.allocate.bits.put, _view__T_11.put
connect mshrs_11.io.allocate.bits.offset, _view__T_11.offset
connect mshrs_11.io.allocate.bits.tag, _view__T_11.tag
connect mshrs_11.io.allocate.bits.source, _view__T_11.source
connect mshrs_11.io.allocate.bits.size, _view__T_11.size
connect mshrs_11.io.allocate.bits.param, _view__T_11.param
connect mshrs_11.io.allocate.bits.opcode, _view__T_11.opcode
connect mshrs_11.io.allocate.bits.control, _view__T_11.control
connect mshrs_11.io.allocate.bits.prio[0], _view__T_11.prio[0]
connect mshrs_11.io.allocate.bits.prio[1], _view__T_11.prio[1]
connect mshrs_11.io.allocate.bits.prio[2], _view__T_11.prio[2]
connect mshrs_11.io.allocate.bits.set, mshrs_11.io.status.bits.set
node _mshrs_11_io_allocate_bits_repeat_T = eq(mshrs_11.io.allocate.bits.tag, mshrs_11.io.status.bits.tag)
connect mshrs_11.io.allocate.bits.repeat, _mshrs_11_io_allocate_bits_repeat_T
node _mshrs_11_io_allocate_valid_T = and(sel_11, will_reload_12)
connect mshrs_11.io.allocate.valid, _mshrs_11_io_allocate_valid_T
node _prio_requests_T = not(requests.io.valid)
node _prio_requests_T_1 = shr(requests.io.valid, 12)
node _prio_requests_T_2 = or(_prio_requests_T, _prio_requests_T_1)
node _prio_requests_T_3 = shr(requests.io.valid, 24)
node _prio_requests_T_4 = or(_prio_requests_T_2, _prio_requests_T_3)
node prio_requests = not(_prio_requests_T_4)
node pop_index_hi = cat(mshr_selectOH, mshr_selectOH)
node _pop_index_T = cat(pop_index_hi, mshr_selectOH)
node _pop_index_T_1 = and(_pop_index_T, prio_requests)
node pop_index_hi_1 = bits(_pop_index_T_1, 35, 32)
node pop_index_lo = bits(_pop_index_T_1, 31, 0)
node _pop_index_T_2 = orr(pop_index_hi_1)
node _pop_index_T_3 = or(pop_index_hi_1, pop_index_lo)
node pop_index_hi_2 = bits(_pop_index_T_3, 31, 16)
node pop_index_lo_1 = bits(_pop_index_T_3, 15, 0)
node _pop_index_T_4 = orr(pop_index_hi_2)
node _pop_index_T_5 = or(pop_index_hi_2, pop_index_lo_1)
node pop_index_hi_3 = bits(_pop_index_T_5, 15, 8)
node pop_index_lo_2 = bits(_pop_index_T_5, 7, 0)
node _pop_index_T_6 = orr(pop_index_hi_3)
node _pop_index_T_7 = or(pop_index_hi_3, pop_index_lo_2)
node pop_index_hi_4 = bits(_pop_index_T_7, 7, 4)
node pop_index_lo_3 = bits(_pop_index_T_7, 3, 0)
node _pop_index_T_8 = orr(pop_index_hi_4)
node _pop_index_T_9 = or(pop_index_hi_4, pop_index_lo_3)
node pop_index_hi_5 = bits(_pop_index_T_9, 3, 2)
node pop_index_lo_4 = bits(_pop_index_T_9, 1, 0)
node _pop_index_T_10 = orr(pop_index_hi_5)
node _pop_index_T_11 = or(pop_index_hi_5, pop_index_lo_4)
node _pop_index_T_12 = bits(_pop_index_T_11, 1, 1)
node _pop_index_T_13 = cat(_pop_index_T_10, _pop_index_T_12)
node _pop_index_T_14 = cat(_pop_index_T_8, _pop_index_T_13)
node _pop_index_T_15 = cat(_pop_index_T_6, _pop_index_T_14)
node _pop_index_T_16 = cat(_pop_index_T_4, _pop_index_T_15)
node pop_index = cat(_pop_index_T_2, _pop_index_T_16)
connect requests.io.pop.valid, will_pop
connect requests.io.pop.bits, pop_index
node lb_tag_mismatch = neq(scheduleTag, requests.io.data.tag)
node _mshr_uses_directory_assuming_no_bypass_T = and(schedule.reload, may_pop)
node mshr_uses_directory_assuming_no_bypass = and(_mshr_uses_directory_assuming_no_bypass_T, lb_tag_mismatch)
node mshr_uses_directory_for_lb = and(will_pop, lb_tag_mismatch)
node _mshr_uses_directory_T = mux(bypass, request.bits.tag, requests.io.data.tag)
node _mshr_uses_directory_T_1 = neq(scheduleTag, _mshr_uses_directory_T)
node mshr_uses_directory = and(will_reload, _mshr_uses_directory_T_1)
node mshr_validOH_lo_lo_hi = cat(mshrs_2.io.status.valid, mshrs_1.io.status.valid)
node mshr_validOH_lo_lo = cat(mshr_validOH_lo_lo_hi, mshrs_0.io.status.valid)
node mshr_validOH_lo_hi_hi = cat(mshrs_5.io.status.valid, mshrs_4.io.status.valid)
node mshr_validOH_lo_hi = cat(mshr_validOH_lo_hi_hi, mshrs_3.io.status.valid)
node mshr_validOH_lo = cat(mshr_validOH_lo_hi, mshr_validOH_lo_lo)
node mshr_validOH_hi_lo_hi = cat(mshrs_8.io.status.valid, mshrs_7.io.status.valid)
node mshr_validOH_hi_lo = cat(mshr_validOH_hi_lo_hi, mshrs_6.io.status.valid)
node mshr_validOH_hi_hi_hi = cat(mshrs_11.io.status.valid, mshrs_10.io.status.valid)
node mshr_validOH_hi_hi = cat(mshr_validOH_hi_hi_hi, mshrs_9.io.status.valid)
node mshr_validOH_hi = cat(mshr_validOH_hi_hi, mshr_validOH_hi_lo)
node mshr_validOH = cat(mshr_validOH_hi, mshr_validOH_lo)
node _mshr_free_T = not(mshr_validOH)
node _mshr_free_T_1 = and(_mshr_free_T, prioFilter)
node mshr_free = orr(_mshr_free_T_1)
node bypassQueue = and(schedule.reload, bypassMatches)
node _request_alloc_cases_T = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _request_alloc_cases_T_1 = and(alloc, _request_alloc_cases_T)
node _request_alloc_cases_T_2 = and(_request_alloc_cases_T_1, mshr_free)
node _request_alloc_cases_T_3 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _request_alloc_cases_T_4 = and(nestB, _request_alloc_cases_T_3)
node _request_alloc_cases_T_5 = eq(mshrs_10.io.status.valid, UInt<1>(0h0))
node _request_alloc_cases_T_6 = and(_request_alloc_cases_T_4, _request_alloc_cases_T_5)
node _request_alloc_cases_T_7 = eq(mshrs_11.io.status.valid, UInt<1>(0h0))
node _request_alloc_cases_T_8 = and(_request_alloc_cases_T_6, _request_alloc_cases_T_7)
node _request_alloc_cases_T_9 = or(_request_alloc_cases_T_2, _request_alloc_cases_T_8)
node _request_alloc_cases_T_10 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _request_alloc_cases_T_11 = and(nestC, _request_alloc_cases_T_10)
node _request_alloc_cases_T_12 = eq(mshrs_11.io.status.valid, UInt<1>(0h0))
node _request_alloc_cases_T_13 = and(_request_alloc_cases_T_11, _request_alloc_cases_T_12)
node request_alloc_cases = or(_request_alloc_cases_T_9, _request_alloc_cases_T_13)
node _request_ready_T = or(bypassQueue, requests.io.push.ready)
node _request_ready_T_1 = and(queue, _request_ready_T)
node _request_ready_T_2 = or(request_alloc_cases, _request_ready_T_1)
connect request.ready, _request_ready_T_2
node alloc_uses_directory = and(request.valid, request_alloc_cases)
node _directory_io_read_valid_T = or(mshr_uses_directory, alloc_uses_directory)
connect directory.io.read.valid, _directory_io_read_valid_T
node _directory_io_read_bits_set_T = mux(mshr_uses_directory_for_lb, scheduleSet, request.bits.set)
connect directory.io.read.bits.set, _directory_io_read_bits_set_T
node _directory_io_read_bits_tag_T = mux(mshr_uses_directory_for_lb, requests.io.data.tag, request.bits.tag)
connect directory.io.read.bits.tag, _directory_io_read_bits_tag_T
node _requests_io_push_valid_T = and(request.valid, queue)
node _requests_io_push_valid_T_1 = eq(bypassQueue, UInt<1>(0h0))
node _requests_io_push_valid_T_2 = and(_requests_io_push_valid_T, _requests_io_push_valid_T_1)
connect requests.io.push.valid, _requests_io_push_valid_T_2
connect requests.io.push.bits.data.put, request.bits.put
connect requests.io.push.bits.data.offset, request.bits.offset
connect requests.io.push.bits.data.tag, request.bits.tag
connect requests.io.push.bits.data.source, request.bits.source
connect requests.io.push.bits.data.size, request.bits.size
connect requests.io.push.bits.data.param, request.bits.param
connect requests.io.push.bits.data.opcode, request.bits.opcode
connect requests.io.push.bits.data.control, request.bits.control
connect requests.io.push.bits.data.prio[0], request.bits.prio[0]
connect requests.io.push.bits.data.prio[1], request.bits.prio[1]
connect requests.io.push.bits.data.prio[2], request.bits.prio[2]
node _requests_io_push_bits_index_T = shl(lowerMatches1, 0)
node requests_io_push_bits_index_hi = bits(_requests_io_push_bits_index_T, 11, 8)
node requests_io_push_bits_index_lo = bits(_requests_io_push_bits_index_T, 7, 0)
node _requests_io_push_bits_index_T_1 = orr(requests_io_push_bits_index_hi)
node _requests_io_push_bits_index_T_2 = or(requests_io_push_bits_index_hi, requests_io_push_bits_index_lo)
node requests_io_push_bits_index_hi_1 = bits(_requests_io_push_bits_index_T_2, 7, 4)
node requests_io_push_bits_index_lo_1 = bits(_requests_io_push_bits_index_T_2, 3, 0)
node _requests_io_push_bits_index_T_3 = orr(requests_io_push_bits_index_hi_1)
node _requests_io_push_bits_index_T_4 = or(requests_io_push_bits_index_hi_1, requests_io_push_bits_index_lo_1)
node requests_io_push_bits_index_hi_2 = bits(_requests_io_push_bits_index_T_4, 3, 2)
node requests_io_push_bits_index_lo_2 = bits(_requests_io_push_bits_index_T_4, 1, 0)
node _requests_io_push_bits_index_T_5 = orr(requests_io_push_bits_index_hi_2)
node _requests_io_push_bits_index_T_6 = or(requests_io_push_bits_index_hi_2, requests_io_push_bits_index_lo_2)
node _requests_io_push_bits_index_T_7 = bits(_requests_io_push_bits_index_T_6, 1, 1)
node _requests_io_push_bits_index_T_8 = cat(_requests_io_push_bits_index_T_5, _requests_io_push_bits_index_T_7)
node _requests_io_push_bits_index_T_9 = cat(_requests_io_push_bits_index_T_3, _requests_io_push_bits_index_T_8)
node _requests_io_push_bits_index_T_10 = cat(_requests_io_push_bits_index_T_1, _requests_io_push_bits_index_T_9)
node _requests_io_push_bits_index_T_11 = shl(lowerMatches1, 12)
node requests_io_push_bits_index_hi_3 = bits(_requests_io_push_bits_index_T_11, 23, 16)
node requests_io_push_bits_index_lo_3 = bits(_requests_io_push_bits_index_T_11, 15, 0)
node _requests_io_push_bits_index_T_12 = orr(requests_io_push_bits_index_hi_3)
node _requests_io_push_bits_index_T_13 = or(requests_io_push_bits_index_hi_3, requests_io_push_bits_index_lo_3)
node requests_io_push_bits_index_hi_4 = bits(_requests_io_push_bits_index_T_13, 15, 8)
node requests_io_push_bits_index_lo_4 = bits(_requests_io_push_bits_index_T_13, 7, 0)
node _requests_io_push_bits_index_T_14 = orr(requests_io_push_bits_index_hi_4)
node _requests_io_push_bits_index_T_15 = or(requests_io_push_bits_index_hi_4, requests_io_push_bits_index_lo_4)
node requests_io_push_bits_index_hi_5 = bits(_requests_io_push_bits_index_T_15, 7, 4)
node requests_io_push_bits_index_lo_5 = bits(_requests_io_push_bits_index_T_15, 3, 0)
node _requests_io_push_bits_index_T_16 = orr(requests_io_push_bits_index_hi_5)
node _requests_io_push_bits_index_T_17 = or(requests_io_push_bits_index_hi_5, requests_io_push_bits_index_lo_5)
node requests_io_push_bits_index_hi_6 = bits(_requests_io_push_bits_index_T_17, 3, 2)
node requests_io_push_bits_index_lo_6 = bits(_requests_io_push_bits_index_T_17, 1, 0)
node _requests_io_push_bits_index_T_18 = orr(requests_io_push_bits_index_hi_6)
node _requests_io_push_bits_index_T_19 = or(requests_io_push_bits_index_hi_6, requests_io_push_bits_index_lo_6)
node _requests_io_push_bits_index_T_20 = bits(_requests_io_push_bits_index_T_19, 1, 1)
node _requests_io_push_bits_index_T_21 = cat(_requests_io_push_bits_index_T_18, _requests_io_push_bits_index_T_20)
node _requests_io_push_bits_index_T_22 = cat(_requests_io_push_bits_index_T_16, _requests_io_push_bits_index_T_21)
node _requests_io_push_bits_index_T_23 = cat(_requests_io_push_bits_index_T_14, _requests_io_push_bits_index_T_22)
node _requests_io_push_bits_index_T_24 = cat(_requests_io_push_bits_index_T_12, _requests_io_push_bits_index_T_23)
node _requests_io_push_bits_index_T_25 = shl(lowerMatches1, 24)
node requests_io_push_bits_index_hi_7 = bits(_requests_io_push_bits_index_T_25, 35, 32)
node requests_io_push_bits_index_lo_7 = bits(_requests_io_push_bits_index_T_25, 31, 0)
node _requests_io_push_bits_index_T_26 = orr(requests_io_push_bits_index_hi_7)
node _requests_io_push_bits_index_T_27 = or(requests_io_push_bits_index_hi_7, requests_io_push_bits_index_lo_7)
node requests_io_push_bits_index_hi_8 = bits(_requests_io_push_bits_index_T_27, 31, 16)
node requests_io_push_bits_index_lo_8 = bits(_requests_io_push_bits_index_T_27, 15, 0)
node _requests_io_push_bits_index_T_28 = orr(requests_io_push_bits_index_hi_8)
node _requests_io_push_bits_index_T_29 = or(requests_io_push_bits_index_hi_8, requests_io_push_bits_index_lo_8)
node requests_io_push_bits_index_hi_9 = bits(_requests_io_push_bits_index_T_29, 15, 8)
node requests_io_push_bits_index_lo_9 = bits(_requests_io_push_bits_index_T_29, 7, 0)
node _requests_io_push_bits_index_T_30 = orr(requests_io_push_bits_index_hi_9)
node _requests_io_push_bits_index_T_31 = or(requests_io_push_bits_index_hi_9, requests_io_push_bits_index_lo_9)
node requests_io_push_bits_index_hi_10 = bits(_requests_io_push_bits_index_T_31, 7, 4)
node requests_io_push_bits_index_lo_10 = bits(_requests_io_push_bits_index_T_31, 3, 0)
node _requests_io_push_bits_index_T_32 = orr(requests_io_push_bits_index_hi_10)
node _requests_io_push_bits_index_T_33 = or(requests_io_push_bits_index_hi_10, requests_io_push_bits_index_lo_10)
node requests_io_push_bits_index_hi_11 = bits(_requests_io_push_bits_index_T_33, 3, 2)
node requests_io_push_bits_index_lo_11 = bits(_requests_io_push_bits_index_T_33, 1, 0)
node _requests_io_push_bits_index_T_34 = orr(requests_io_push_bits_index_hi_11)
node _requests_io_push_bits_index_T_35 = or(requests_io_push_bits_index_hi_11, requests_io_push_bits_index_lo_11)
node _requests_io_push_bits_index_T_36 = bits(_requests_io_push_bits_index_T_35, 1, 1)
node _requests_io_push_bits_index_T_37 = cat(_requests_io_push_bits_index_T_34, _requests_io_push_bits_index_T_36)
node _requests_io_push_bits_index_T_38 = cat(_requests_io_push_bits_index_T_32, _requests_io_push_bits_index_T_37)
node _requests_io_push_bits_index_T_39 = cat(_requests_io_push_bits_index_T_30, _requests_io_push_bits_index_T_38)
node _requests_io_push_bits_index_T_40 = cat(_requests_io_push_bits_index_T_28, _requests_io_push_bits_index_T_39)
node _requests_io_push_bits_index_T_41 = cat(_requests_io_push_bits_index_T_26, _requests_io_push_bits_index_T_40)
node _requests_io_push_bits_index_T_42 = mux(request.bits.prio[0], _requests_io_push_bits_index_T_10, UInt<1>(0h0))
node _requests_io_push_bits_index_T_43 = mux(request.bits.prio[1], _requests_io_push_bits_index_T_24, UInt<1>(0h0))
node _requests_io_push_bits_index_T_44 = mux(request.bits.prio[2], _requests_io_push_bits_index_T_41, UInt<1>(0h0))
node _requests_io_push_bits_index_T_45 = or(_requests_io_push_bits_index_T_42, _requests_io_push_bits_index_T_43)
node _requests_io_push_bits_index_T_46 = or(_requests_io_push_bits_index_T_45, _requests_io_push_bits_index_T_44)
wire _requests_io_push_bits_index_WIRE : UInt<6>
connect _requests_io_push_bits_index_WIRE, _requests_io_push_bits_index_T_46
connect requests.io.push.bits.index, _requests_io_push_bits_index_WIRE
node _mshr_insertOH_T = not(mshr_validOH)
node _mshr_insertOH_T_1 = shl(_mshr_insertOH_T, 1)
node _mshr_insertOH_T_2 = bits(_mshr_insertOH_T_1, 11, 0)
node _mshr_insertOH_T_3 = or(_mshr_insertOH_T, _mshr_insertOH_T_2)
node _mshr_insertOH_T_4 = shl(_mshr_insertOH_T_3, 2)
node _mshr_insertOH_T_5 = bits(_mshr_insertOH_T_4, 11, 0)
node _mshr_insertOH_T_6 = or(_mshr_insertOH_T_3, _mshr_insertOH_T_5)
node _mshr_insertOH_T_7 = shl(_mshr_insertOH_T_6, 4)
node _mshr_insertOH_T_8 = bits(_mshr_insertOH_T_7, 11, 0)
node _mshr_insertOH_T_9 = or(_mshr_insertOH_T_6, _mshr_insertOH_T_8)
node _mshr_insertOH_T_10 = shl(_mshr_insertOH_T_9, 8)
node _mshr_insertOH_T_11 = bits(_mshr_insertOH_T_10, 11, 0)
node _mshr_insertOH_T_12 = or(_mshr_insertOH_T_9, _mshr_insertOH_T_11)
node _mshr_insertOH_T_13 = bits(_mshr_insertOH_T_12, 11, 0)
node _mshr_insertOH_T_14 = shl(_mshr_insertOH_T_13, 1)
node _mshr_insertOH_T_15 = not(_mshr_insertOH_T_14)
node _mshr_insertOH_T_16 = not(mshr_validOH)
node _mshr_insertOH_T_17 = and(_mshr_insertOH_T_15, _mshr_insertOH_T_16)
node mshr_insertOH = and(_mshr_insertOH_T_17, prioFilter)
node _T_19 = bits(mshr_insertOH, 0, 0)
node _T_20 = bits(mshr_insertOH, 1, 1)
node _T_21 = bits(mshr_insertOH, 2, 2)
node _T_22 = bits(mshr_insertOH, 3, 3)
node _T_23 = bits(mshr_insertOH, 4, 4)
node _T_24 = bits(mshr_insertOH, 5, 5)
node _T_25 = bits(mshr_insertOH, 6, 6)
node _T_26 = bits(mshr_insertOH, 7, 7)
node _T_27 = bits(mshr_insertOH, 8, 8)
node _T_28 = bits(mshr_insertOH, 9, 9)
node _T_29 = bits(mshr_insertOH, 10, 10)
node _T_30 = bits(mshr_insertOH, 11, 11)
node _T_31 = bits(mshr_insertOH, 12, 12)
node _T_32 = and(request.valid, alloc)
node _T_33 = and(_T_32, _T_19)
node _T_34 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_35 = and(_T_33, _T_34)
when _T_35 :
connect mshrs_0.io.allocate.valid, UInt<1>(0h1)
connect mshrs_0.io.allocate.bits.set, request.bits.set
connect mshrs_0.io.allocate.bits.put, request.bits.put
connect mshrs_0.io.allocate.bits.offset, request.bits.offset
connect mshrs_0.io.allocate.bits.tag, request.bits.tag
connect mshrs_0.io.allocate.bits.source, request.bits.source
connect mshrs_0.io.allocate.bits.size, request.bits.size
connect mshrs_0.io.allocate.bits.param, request.bits.param
connect mshrs_0.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_0.io.allocate.bits.control, request.bits.control
connect mshrs_0.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_0.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_0.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_0.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_36 = and(request.valid, alloc)
node _T_37 = and(_T_36, _T_20)
node _T_38 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_39 = and(_T_37, _T_38)
when _T_39 :
connect mshrs_1.io.allocate.valid, UInt<1>(0h1)
connect mshrs_1.io.allocate.bits.set, request.bits.set
connect mshrs_1.io.allocate.bits.put, request.bits.put
connect mshrs_1.io.allocate.bits.offset, request.bits.offset
connect mshrs_1.io.allocate.bits.tag, request.bits.tag
connect mshrs_1.io.allocate.bits.source, request.bits.source
connect mshrs_1.io.allocate.bits.size, request.bits.size
connect mshrs_1.io.allocate.bits.param, request.bits.param
connect mshrs_1.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_1.io.allocate.bits.control, request.bits.control
connect mshrs_1.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_1.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_1.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_1.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_40 = and(request.valid, alloc)
node _T_41 = and(_T_40, _T_21)
node _T_42 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_43 = and(_T_41, _T_42)
when _T_43 :
connect mshrs_2.io.allocate.valid, UInt<1>(0h1)
connect mshrs_2.io.allocate.bits.set, request.bits.set
connect mshrs_2.io.allocate.bits.put, request.bits.put
connect mshrs_2.io.allocate.bits.offset, request.bits.offset
connect mshrs_2.io.allocate.bits.tag, request.bits.tag
connect mshrs_2.io.allocate.bits.source, request.bits.source
connect mshrs_2.io.allocate.bits.size, request.bits.size
connect mshrs_2.io.allocate.bits.param, request.bits.param
connect mshrs_2.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_2.io.allocate.bits.control, request.bits.control
connect mshrs_2.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_2.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_2.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_2.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_44 = and(request.valid, alloc)
node _T_45 = and(_T_44, _T_22)
node _T_46 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_47 = and(_T_45, _T_46)
when _T_47 :
connect mshrs_3.io.allocate.valid, UInt<1>(0h1)
connect mshrs_3.io.allocate.bits.set, request.bits.set
connect mshrs_3.io.allocate.bits.put, request.bits.put
connect mshrs_3.io.allocate.bits.offset, request.bits.offset
connect mshrs_3.io.allocate.bits.tag, request.bits.tag
connect mshrs_3.io.allocate.bits.source, request.bits.source
connect mshrs_3.io.allocate.bits.size, request.bits.size
connect mshrs_3.io.allocate.bits.param, request.bits.param
connect mshrs_3.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_3.io.allocate.bits.control, request.bits.control
connect mshrs_3.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_3.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_3.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_3.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_48 = and(request.valid, alloc)
node _T_49 = and(_T_48, _T_23)
node _T_50 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_51 = and(_T_49, _T_50)
when _T_51 :
connect mshrs_4.io.allocate.valid, UInt<1>(0h1)
connect mshrs_4.io.allocate.bits.set, request.bits.set
connect mshrs_4.io.allocate.bits.put, request.bits.put
connect mshrs_4.io.allocate.bits.offset, request.bits.offset
connect mshrs_4.io.allocate.bits.tag, request.bits.tag
connect mshrs_4.io.allocate.bits.source, request.bits.source
connect mshrs_4.io.allocate.bits.size, request.bits.size
connect mshrs_4.io.allocate.bits.param, request.bits.param
connect mshrs_4.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_4.io.allocate.bits.control, request.bits.control
connect mshrs_4.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_4.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_4.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_4.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_52 = and(request.valid, alloc)
node _T_53 = and(_T_52, _T_24)
node _T_54 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_55 = and(_T_53, _T_54)
when _T_55 :
connect mshrs_5.io.allocate.valid, UInt<1>(0h1)
connect mshrs_5.io.allocate.bits.set, request.bits.set
connect mshrs_5.io.allocate.bits.put, request.bits.put
connect mshrs_5.io.allocate.bits.offset, request.bits.offset
connect mshrs_5.io.allocate.bits.tag, request.bits.tag
connect mshrs_5.io.allocate.bits.source, request.bits.source
connect mshrs_5.io.allocate.bits.size, request.bits.size
connect mshrs_5.io.allocate.bits.param, request.bits.param
connect mshrs_5.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_5.io.allocate.bits.control, request.bits.control
connect mshrs_5.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_5.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_5.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_5.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_56 = and(request.valid, alloc)
node _T_57 = and(_T_56, _T_25)
node _T_58 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_59 = and(_T_57, _T_58)
when _T_59 :
connect mshrs_6.io.allocate.valid, UInt<1>(0h1)
connect mshrs_6.io.allocate.bits.set, request.bits.set
connect mshrs_6.io.allocate.bits.put, request.bits.put
connect mshrs_6.io.allocate.bits.offset, request.bits.offset
connect mshrs_6.io.allocate.bits.tag, request.bits.tag
connect mshrs_6.io.allocate.bits.source, request.bits.source
connect mshrs_6.io.allocate.bits.size, request.bits.size
connect mshrs_6.io.allocate.bits.param, request.bits.param
connect mshrs_6.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_6.io.allocate.bits.control, request.bits.control
connect mshrs_6.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_6.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_6.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_6.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_60 = and(request.valid, alloc)
node _T_61 = and(_T_60, _T_26)
node _T_62 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_63 = and(_T_61, _T_62)
when _T_63 :
connect mshrs_7.io.allocate.valid, UInt<1>(0h1)
connect mshrs_7.io.allocate.bits.set, request.bits.set
connect mshrs_7.io.allocate.bits.put, request.bits.put
connect mshrs_7.io.allocate.bits.offset, request.bits.offset
connect mshrs_7.io.allocate.bits.tag, request.bits.tag
connect mshrs_7.io.allocate.bits.source, request.bits.source
connect mshrs_7.io.allocate.bits.size, request.bits.size
connect mshrs_7.io.allocate.bits.param, request.bits.param
connect mshrs_7.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_7.io.allocate.bits.control, request.bits.control
connect mshrs_7.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_7.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_7.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_7.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_64 = and(request.valid, alloc)
node _T_65 = and(_T_64, _T_27)
node _T_66 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_67 = and(_T_65, _T_66)
when _T_67 :
connect mshrs_8.io.allocate.valid, UInt<1>(0h1)
connect mshrs_8.io.allocate.bits.set, request.bits.set
connect mshrs_8.io.allocate.bits.put, request.bits.put
connect mshrs_8.io.allocate.bits.offset, request.bits.offset
connect mshrs_8.io.allocate.bits.tag, request.bits.tag
connect mshrs_8.io.allocate.bits.source, request.bits.source
connect mshrs_8.io.allocate.bits.size, request.bits.size
connect mshrs_8.io.allocate.bits.param, request.bits.param
connect mshrs_8.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_8.io.allocate.bits.control, request.bits.control
connect mshrs_8.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_8.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_8.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_8.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_68 = and(request.valid, alloc)
node _T_69 = and(_T_68, _T_28)
node _T_70 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_71 = and(_T_69, _T_70)
when _T_71 :
connect mshrs_9.io.allocate.valid, UInt<1>(0h1)
connect mshrs_9.io.allocate.bits.set, request.bits.set
connect mshrs_9.io.allocate.bits.put, request.bits.put
connect mshrs_9.io.allocate.bits.offset, request.bits.offset
connect mshrs_9.io.allocate.bits.tag, request.bits.tag
connect mshrs_9.io.allocate.bits.source, request.bits.source
connect mshrs_9.io.allocate.bits.size, request.bits.size
connect mshrs_9.io.allocate.bits.param, request.bits.param
connect mshrs_9.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_9.io.allocate.bits.control, request.bits.control
connect mshrs_9.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_9.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_9.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_9.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_72 = and(request.valid, alloc)
node _T_73 = and(_T_72, _T_29)
node _T_74 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_75 = and(_T_73, _T_74)
when _T_75 :
connect mshrs_10.io.allocate.valid, UInt<1>(0h1)
connect mshrs_10.io.allocate.bits.set, request.bits.set
connect mshrs_10.io.allocate.bits.put, request.bits.put
connect mshrs_10.io.allocate.bits.offset, request.bits.offset
connect mshrs_10.io.allocate.bits.tag, request.bits.tag
connect mshrs_10.io.allocate.bits.source, request.bits.source
connect mshrs_10.io.allocate.bits.size, request.bits.size
connect mshrs_10.io.allocate.bits.param, request.bits.param
connect mshrs_10.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_10.io.allocate.bits.control, request.bits.control
connect mshrs_10.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_10.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_10.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_10.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_76 = and(request.valid, alloc)
node _T_77 = and(_T_76, _T_30)
node _T_78 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_79 = and(_T_77, _T_78)
when _T_79 :
connect mshrs_11.io.allocate.valid, UInt<1>(0h1)
connect mshrs_11.io.allocate.bits.set, request.bits.set
connect mshrs_11.io.allocate.bits.put, request.bits.put
connect mshrs_11.io.allocate.bits.offset, request.bits.offset
connect mshrs_11.io.allocate.bits.tag, request.bits.tag
connect mshrs_11.io.allocate.bits.source, request.bits.source
connect mshrs_11.io.allocate.bits.size, request.bits.size
connect mshrs_11.io.allocate.bits.param, request.bits.param
connect mshrs_11.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_11.io.allocate.bits.control, request.bits.control
connect mshrs_11.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_11.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_11.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_11.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_80 = and(request.valid, nestB)
node _T_81 = eq(mshrs_10.io.status.valid, UInt<1>(0h0))
node _T_82 = and(_T_80, _T_81)
node _T_83 = eq(mshrs_11.io.status.valid, UInt<1>(0h0))
node _T_84 = and(_T_82, _T_83)
node _T_85 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_86 = and(_T_84, _T_85)
when _T_86 :
connect mshrs_10.io.allocate.valid, UInt<1>(0h1)
connect mshrs_10.io.allocate.bits.set, request.bits.set
connect mshrs_10.io.allocate.bits.put, request.bits.put
connect mshrs_10.io.allocate.bits.offset, request.bits.offset
connect mshrs_10.io.allocate.bits.tag, request.bits.tag
connect mshrs_10.io.allocate.bits.source, request.bits.source
connect mshrs_10.io.allocate.bits.size, request.bits.size
connect mshrs_10.io.allocate.bits.param, request.bits.param
connect mshrs_10.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_10.io.allocate.bits.control, request.bits.control
connect mshrs_10.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_10.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_10.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_10.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_87 = eq(request.bits.prio[0], UInt<1>(0h0))
node _T_88 = asUInt(reset)
node _T_89 = eq(_T_88, UInt<1>(0h0))
when _T_89 :
node _T_90 = eq(_T_87, UInt<1>(0h0))
when _T_90 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Scheduler.scala:291 assert (!request.bits.prio(0))\n") : printf
assert(clock, _T_87, UInt<1>(0h1), "") : assert
connect mshrs_10.io.allocate.bits.prio[0], UInt<1>(0h0)
node _T_91 = and(request.valid, nestC)
node _T_92 = eq(mshrs_11.io.status.valid, UInt<1>(0h0))
node _T_93 = and(_T_91, _T_92)
node _T_94 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0))
node _T_95 = and(_T_93, _T_94)
when _T_95 :
connect mshrs_11.io.allocate.valid, UInt<1>(0h1)
connect mshrs_11.io.allocate.bits.set, request.bits.set
connect mshrs_11.io.allocate.bits.put, request.bits.put
connect mshrs_11.io.allocate.bits.offset, request.bits.offset
connect mshrs_11.io.allocate.bits.tag, request.bits.tag
connect mshrs_11.io.allocate.bits.source, request.bits.source
connect mshrs_11.io.allocate.bits.size, request.bits.size
connect mshrs_11.io.allocate.bits.param, request.bits.param
connect mshrs_11.io.allocate.bits.opcode, request.bits.opcode
connect mshrs_11.io.allocate.bits.control, request.bits.control
connect mshrs_11.io.allocate.bits.prio[0], request.bits.prio[0]
connect mshrs_11.io.allocate.bits.prio[1], request.bits.prio[1]
connect mshrs_11.io.allocate.bits.prio[2], request.bits.prio[2]
connect mshrs_11.io.allocate.bits.repeat, UInt<1>(0h0)
node _T_96 = eq(request.bits.prio[0], UInt<1>(0h0))
node _T_97 = asUInt(reset)
node _T_98 = eq(_T_97, UInt<1>(0h0))
when _T_98 :
node _T_99 = eq(_T_96, UInt<1>(0h0))
when _T_99 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Scheduler.scala:299 assert (!request.bits.prio(0))\n") : printf_1
assert(clock, _T_96, UInt<1>(0h1), "") : assert_1
node _T_100 = eq(request.bits.prio[1], UInt<1>(0h0))
node _T_101 = asUInt(reset)
node _T_102 = eq(_T_101, UInt<1>(0h0))
when _T_102 :
node _T_103 = eq(_T_100, UInt<1>(0h0))
when _T_103 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Scheduler.scala:300 assert (!request.bits.prio(1))\n") : printf_2
assert(clock, _T_100, UInt<1>(0h1), "") : assert_2
connect mshrs_11.io.allocate.bits.prio[0], UInt<1>(0h0)
connect mshrs_11.io.allocate.bits.prio[1], UInt<1>(0h0)
node _dirTarget_T = mux(nestB, UInt<11>(0h400), UInt<12>(0h800))
node dirTarget = mux(alloc, mshr_insertOH, _dirTarget_T)
node _directoryFanout_T = mux(alloc_uses_directory, dirTarget, UInt<1>(0h0))
node _directoryFanout_T_1 = mux(mshr_uses_directory, mshr_selectOH, _directoryFanout_T)
reg directoryFanout : UInt, clock
connect directoryFanout, _directoryFanout_T_1
node _mshrs_0_io_directory_valid_T = bits(directoryFanout, 0, 0)
connect mshrs_0.io.directory.valid, _mshrs_0_io_directory_valid_T
connect mshrs_0.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_0.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_0.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_0.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_0.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_0.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_1_io_directory_valid_T = bits(directoryFanout, 1, 1)
connect mshrs_1.io.directory.valid, _mshrs_1_io_directory_valid_T
connect mshrs_1.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_1.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_1.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_1.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_1.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_1.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_2_io_directory_valid_T = bits(directoryFanout, 2, 2)
connect mshrs_2.io.directory.valid, _mshrs_2_io_directory_valid_T
connect mshrs_2.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_2.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_2.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_2.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_2.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_2.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_3_io_directory_valid_T = bits(directoryFanout, 3, 3)
connect mshrs_3.io.directory.valid, _mshrs_3_io_directory_valid_T
connect mshrs_3.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_3.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_3.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_3.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_3.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_3.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_4_io_directory_valid_T = bits(directoryFanout, 4, 4)
connect mshrs_4.io.directory.valid, _mshrs_4_io_directory_valid_T
connect mshrs_4.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_4.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_4.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_4.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_4.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_4.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_5_io_directory_valid_T = bits(directoryFanout, 5, 5)
connect mshrs_5.io.directory.valid, _mshrs_5_io_directory_valid_T
connect mshrs_5.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_5.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_5.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_5.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_5.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_5.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_6_io_directory_valid_T = bits(directoryFanout, 6, 6)
connect mshrs_6.io.directory.valid, _mshrs_6_io_directory_valid_T
connect mshrs_6.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_6.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_6.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_6.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_6.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_6.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_7_io_directory_valid_T = bits(directoryFanout, 7, 7)
connect mshrs_7.io.directory.valid, _mshrs_7_io_directory_valid_T
connect mshrs_7.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_7.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_7.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_7.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_7.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_7.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_8_io_directory_valid_T = bits(directoryFanout, 8, 8)
connect mshrs_8.io.directory.valid, _mshrs_8_io_directory_valid_T
connect mshrs_8.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_8.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_8.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_8.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_8.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_8.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_9_io_directory_valid_T = bits(directoryFanout, 9, 9)
connect mshrs_9.io.directory.valid, _mshrs_9_io_directory_valid_T
connect mshrs_9.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_9.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_9.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_9.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_9.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_9.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_10_io_directory_valid_T = bits(directoryFanout, 10, 10)
connect mshrs_10.io.directory.valid, _mshrs_10_io_directory_valid_T
connect mshrs_10.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_10.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_10.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_10.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_10.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_10.io.directory.bits.dirty, directory.io.result.bits.dirty
node _mshrs_11_io_directory_valid_T = bits(directoryFanout, 11, 11)
connect mshrs_11.io.directory.valid, _mshrs_11_io_directory_valid_T
connect mshrs_11.io.directory.bits.way, directory.io.result.bits.way
connect mshrs_11.io.directory.bits.hit, directory.io.result.bits.hit
connect mshrs_11.io.directory.bits.tag, directory.io.result.bits.tag
connect mshrs_11.io.directory.bits.clients, directory.io.result.bits.clients
connect mshrs_11.io.directory.bits.state, directory.io.result.bits.state
connect mshrs_11.io.directory.bits.dirty, directory.io.result.bits.dirty
node _sinkC_io_way_T = eq(mshrs_10.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_1 = and(mshrs_10.io.status.valid, _sinkC_io_way_T)
node _sinkC_io_way_T_2 = eq(mshrs_0.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_3 = and(mshrs_0.io.status.valid, _sinkC_io_way_T_2)
node _sinkC_io_way_T_4 = eq(mshrs_1.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_5 = and(mshrs_1.io.status.valid, _sinkC_io_way_T_4)
node _sinkC_io_way_T_6 = eq(mshrs_2.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_7 = and(mshrs_2.io.status.valid, _sinkC_io_way_T_6)
node _sinkC_io_way_T_8 = eq(mshrs_3.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_9 = and(mshrs_3.io.status.valid, _sinkC_io_way_T_8)
node _sinkC_io_way_T_10 = eq(mshrs_4.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_11 = and(mshrs_4.io.status.valid, _sinkC_io_way_T_10)
node _sinkC_io_way_T_12 = eq(mshrs_5.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_13 = and(mshrs_5.io.status.valid, _sinkC_io_way_T_12)
node _sinkC_io_way_T_14 = eq(mshrs_6.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_15 = and(mshrs_6.io.status.valid, _sinkC_io_way_T_14)
node _sinkC_io_way_T_16 = eq(mshrs_7.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_17 = and(mshrs_7.io.status.valid, _sinkC_io_way_T_16)
node _sinkC_io_way_T_18 = eq(mshrs_8.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_19 = and(mshrs_8.io.status.valid, _sinkC_io_way_T_18)
node _sinkC_io_way_T_20 = eq(mshrs_9.io.status.bits.set, sinkC.io.set)
node _sinkC_io_way_T_21 = and(mshrs_9.io.status.valid, _sinkC_io_way_T_20)
node _sinkC_io_way_T_22 = mux(_sinkC_io_way_T_3, mshrs_0.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_23 = mux(_sinkC_io_way_T_5, mshrs_1.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_24 = mux(_sinkC_io_way_T_7, mshrs_2.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_25 = mux(_sinkC_io_way_T_9, mshrs_3.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_26 = mux(_sinkC_io_way_T_11, mshrs_4.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_27 = mux(_sinkC_io_way_T_13, mshrs_5.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_28 = mux(_sinkC_io_way_T_15, mshrs_6.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_29 = mux(_sinkC_io_way_T_17, mshrs_7.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_30 = mux(_sinkC_io_way_T_19, mshrs_8.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_31 = mux(_sinkC_io_way_T_21, mshrs_9.io.status.bits.way, UInt<1>(0h0))
node _sinkC_io_way_T_32 = or(_sinkC_io_way_T_22, _sinkC_io_way_T_23)
node _sinkC_io_way_T_33 = or(_sinkC_io_way_T_32, _sinkC_io_way_T_24)
node _sinkC_io_way_T_34 = or(_sinkC_io_way_T_33, _sinkC_io_way_T_25)
node _sinkC_io_way_T_35 = or(_sinkC_io_way_T_34, _sinkC_io_way_T_26)
node _sinkC_io_way_T_36 = or(_sinkC_io_way_T_35, _sinkC_io_way_T_27)
node _sinkC_io_way_T_37 = or(_sinkC_io_way_T_36, _sinkC_io_way_T_28)
node _sinkC_io_way_T_38 = or(_sinkC_io_way_T_37, _sinkC_io_way_T_29)
node _sinkC_io_way_T_39 = or(_sinkC_io_way_T_38, _sinkC_io_way_T_30)
node _sinkC_io_way_T_40 = or(_sinkC_io_way_T_39, _sinkC_io_way_T_31)
wire _sinkC_io_way_WIRE : UInt<3>
connect _sinkC_io_way_WIRE, _sinkC_io_way_T_40
node _sinkC_io_way_T_41 = mux(_sinkC_io_way_T_1, mshrs_10.io.status.bits.way, _sinkC_io_way_WIRE)
connect sinkC.io.way, _sinkC_io_way_T_41
wire _sinkD_io_way_WIRE : UInt<3>[12]
connect _sinkD_io_way_WIRE[0], mshrs_0.io.status.bits.way
connect _sinkD_io_way_WIRE[1], mshrs_1.io.status.bits.way
connect _sinkD_io_way_WIRE[2], mshrs_2.io.status.bits.way
connect _sinkD_io_way_WIRE[3], mshrs_3.io.status.bits.way
connect _sinkD_io_way_WIRE[4], mshrs_4.io.status.bits.way
connect _sinkD_io_way_WIRE[5], mshrs_5.io.status.bits.way
connect _sinkD_io_way_WIRE[6], mshrs_6.io.status.bits.way
connect _sinkD_io_way_WIRE[7], mshrs_7.io.status.bits.way
connect _sinkD_io_way_WIRE[8], mshrs_8.io.status.bits.way
connect _sinkD_io_way_WIRE[9], mshrs_9.io.status.bits.way
connect _sinkD_io_way_WIRE[10], mshrs_10.io.status.bits.way
connect _sinkD_io_way_WIRE[11], mshrs_11.io.status.bits.way
connect sinkD.io.way, _sinkD_io_way_WIRE[sinkD.io.source]
wire _sinkD_io_set_WIRE : UInt<10>[12]
connect _sinkD_io_set_WIRE[0], mshrs_0.io.status.bits.set
connect _sinkD_io_set_WIRE[1], mshrs_1.io.status.bits.set
connect _sinkD_io_set_WIRE[2], mshrs_2.io.status.bits.set
connect _sinkD_io_set_WIRE[3], mshrs_3.io.status.bits.set
connect _sinkD_io_set_WIRE[4], mshrs_4.io.status.bits.set
connect _sinkD_io_set_WIRE[5], mshrs_5.io.status.bits.set
connect _sinkD_io_set_WIRE[6], mshrs_6.io.status.bits.set
connect _sinkD_io_set_WIRE[7], mshrs_7.io.status.bits.set
connect _sinkD_io_set_WIRE[8], mshrs_8.io.status.bits.set
connect _sinkD_io_set_WIRE[9], mshrs_9.io.status.bits.set
connect _sinkD_io_set_WIRE[10], mshrs_10.io.status.bits.set
connect _sinkD_io_set_WIRE[11], mshrs_11.io.status.bits.set
connect sinkD.io.set, _sinkD_io_set_WIRE[sinkD.io.source]
connect sinkA.io.pb_pop, sourceD.io.pb_pop
connect sourceD.io.pb_beat.corrupt, sinkA.io.pb_beat.corrupt
connect sourceD.io.pb_beat.mask, sinkA.io.pb_beat.mask
connect sourceD.io.pb_beat.data, sinkA.io.pb_beat.data
connect sinkC.io.rel_pop, sourceD.io.rel_pop
connect sourceD.io.rel_beat.corrupt, sinkC.io.rel_beat.corrupt
connect sourceD.io.rel_beat.data, sinkC.io.rel_beat.data
connect bankedStore.io.sinkC_adr, sinkC.io.bs_adr
connect bankedStore.io.sinkC_dat.data, sinkC.io.bs_dat.data
connect bankedStore.io.sinkD_adr, sinkD.io.bs_adr
connect bankedStore.io.sinkD_dat.data, sinkD.io.bs_dat.data
connect bankedStore.io.sourceC_adr, sourceC.io.bs_adr
connect bankedStore.io.sourceD_radr, sourceD.io.bs_radr
connect bankedStore.io.sourceD_wadr, sourceD.io.bs_wadr
connect bankedStore.io.sourceD_wdat.data, sourceD.io.bs_wdat.data
connect sourceC.io.bs_dat.data, bankedStore.io.sourceC_dat.data
connect sourceD.io.bs_rdat.data, bankedStore.io.sourceD_rdat.data
connect sourceD.io.evict_req.way, sourceC.io.evict_req.way
connect sourceD.io.evict_req.set, sourceC.io.evict_req.set
connect sourceD.io.grant_req.way, sinkD.io.grant_req.way
connect sourceD.io.grant_req.set, sinkD.io.grant_req.set
connect sourceC.io.evict_safe, sourceD.io.evict_safe
connect sinkD.io.grant_safe, sourceD.io.grant_safe | module InclusiveCacheBankScheduler( // @[Scheduler.scala:27:7]
input clock, // @[Scheduler.scala:27:7]
input reset, // @[Scheduler.scala:27:7]
output io_in_a_ready, // @[Scheduler.scala:29:14]
input io_in_a_valid, // @[Scheduler.scala:29:14]
input [2:0] io_in_a_bits_opcode, // @[Scheduler.scala:29:14]
input [2:0] io_in_a_bits_param, // @[Scheduler.scala:29:14]
input [2:0] io_in_a_bits_size, // @[Scheduler.scala:29:14]
input [7:0] io_in_a_bits_source, // @[Scheduler.scala:29:14]
input [31:0] io_in_a_bits_address, // @[Scheduler.scala:29:14]
input [15:0] io_in_a_bits_mask, // @[Scheduler.scala:29:14]
input [127:0] io_in_a_bits_data, // @[Scheduler.scala:29:14]
input io_in_a_bits_corrupt, // @[Scheduler.scala:29:14]
input io_in_b_ready, // @[Scheduler.scala:29:14]
output io_in_b_valid, // @[Scheduler.scala:29:14]
output [1:0] io_in_b_bits_param, // @[Scheduler.scala:29:14]
output [31:0] io_in_b_bits_address, // @[Scheduler.scala:29:14]
output io_in_c_ready, // @[Scheduler.scala:29:14]
input io_in_c_valid, // @[Scheduler.scala:29:14]
input [2:0] io_in_c_bits_opcode, // @[Scheduler.scala:29:14]
input [2:0] io_in_c_bits_param, // @[Scheduler.scala:29:14]
input [2:0] io_in_c_bits_size, // @[Scheduler.scala:29:14]
input [7:0] io_in_c_bits_source, // @[Scheduler.scala:29:14]
input [31:0] io_in_c_bits_address, // @[Scheduler.scala:29:14]
input [127:0] io_in_c_bits_data, // @[Scheduler.scala:29:14]
input io_in_c_bits_corrupt, // @[Scheduler.scala:29:14]
input io_in_d_ready, // @[Scheduler.scala:29:14]
output io_in_d_valid, // @[Scheduler.scala:29:14]
output [2:0] io_in_d_bits_opcode, // @[Scheduler.scala:29:14]
output [1:0] io_in_d_bits_param, // @[Scheduler.scala:29:14]
output [2:0] io_in_d_bits_size, // @[Scheduler.scala:29:14]
output [7:0] io_in_d_bits_source, // @[Scheduler.scala:29:14]
output [3:0] io_in_d_bits_sink, // @[Scheduler.scala:29:14]
output io_in_d_bits_denied, // @[Scheduler.scala:29:14]
output [127:0] io_in_d_bits_data, // @[Scheduler.scala:29:14]
output io_in_d_bits_corrupt, // @[Scheduler.scala:29:14]
input io_in_e_valid, // @[Scheduler.scala:29:14]
input [3:0] io_in_e_bits_sink, // @[Scheduler.scala:29:14]
input io_out_a_ready, // @[Scheduler.scala:29:14]
output io_out_a_valid, // @[Scheduler.scala:29:14]
output [2:0] io_out_a_bits_opcode, // @[Scheduler.scala:29:14]
output [2:0] io_out_a_bits_param, // @[Scheduler.scala:29:14]
output [2:0] io_out_a_bits_size, // @[Scheduler.scala:29:14]
output [3:0] io_out_a_bits_source, // @[Scheduler.scala:29:14]
output [31:0] io_out_a_bits_address, // @[Scheduler.scala:29:14]
output [7:0] io_out_a_bits_mask, // @[Scheduler.scala:29:14]
output [63:0] io_out_a_bits_data, // @[Scheduler.scala:29:14]
output io_out_a_bits_corrupt, // @[Scheduler.scala:29:14]
input io_out_c_ready, // @[Scheduler.scala:29:14]
output io_out_c_valid, // @[Scheduler.scala:29:14]
output [2:0] io_out_c_bits_opcode, // @[Scheduler.scala:29:14]
output [2:0] io_out_c_bits_param, // @[Scheduler.scala:29:14]
output [2:0] io_out_c_bits_size, // @[Scheduler.scala:29:14]
output [3:0] io_out_c_bits_source, // @[Scheduler.scala:29:14]
output [31:0] io_out_c_bits_address, // @[Scheduler.scala:29:14]
output [63:0] io_out_c_bits_data, // @[Scheduler.scala:29:14]
output io_out_c_bits_corrupt, // @[Scheduler.scala:29:14]
output io_out_d_ready, // @[Scheduler.scala:29:14]
input io_out_d_valid, // @[Scheduler.scala:29:14]
input [2:0] io_out_d_bits_opcode, // @[Scheduler.scala:29:14]
input [1:0] io_out_d_bits_param, // @[Scheduler.scala:29:14]
input [2:0] io_out_d_bits_size, // @[Scheduler.scala:29:14]
input [3:0] io_out_d_bits_source, // @[Scheduler.scala:29:14]
input [2:0] io_out_d_bits_sink, // @[Scheduler.scala:29:14]
input io_out_d_bits_denied, // @[Scheduler.scala:29:14]
input [63:0] io_out_d_bits_data, // @[Scheduler.scala:29:14]
input io_out_d_bits_corrupt, // @[Scheduler.scala:29:14]
output io_out_e_valid, // @[Scheduler.scala:29:14]
output [2:0] io_out_e_bits_sink, // @[Scheduler.scala:29:14]
output io_req_ready, // @[Scheduler.scala:29:14]
input io_req_valid, // @[Scheduler.scala:29:14]
input [31:0] io_req_bits_address, // @[Scheduler.scala:29:14]
output io_resp_valid // @[Scheduler.scala:29:14]
);
wire [12:0] mshrs_11_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70, :295:103, :297:73]
wire [12:0] mshrs_10_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70, :287:131, :289:74]
wire [12:0] mshrs_9_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [12:0] mshrs_8_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [12:0] mshrs_7_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [12:0] mshrs_6_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [12:0] mshrs_5_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [12:0] mshrs_4_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [12:0] mshrs_3_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [12:0] mshrs_2_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [12:0] mshrs_1_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [12:0] mshrs_0_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70]
wire [5:0] request_bits_put; // @[Scheduler.scala:163:21]
wire [5:0] request_bits_offset; // @[Scheduler.scala:163:21]
wire [12:0] request_bits_tag; // @[Scheduler.scala:163:21]
wire [7:0] request_bits_source; // @[Scheduler.scala:163:21]
wire [2:0] request_bits_size; // @[Scheduler.scala:163:21]
wire [2:0] request_bits_param; // @[Scheduler.scala:163:21]
wire [2:0] request_bits_opcode; // @[Scheduler.scala:163:21]
wire request_bits_control; // @[Scheduler.scala:163:21]
wire request_bits_prio_2; // @[Scheduler.scala:163:21]
wire request_bits_prio_0; // @[Scheduler.scala:163:21]
wire _mshrs_11_io_status_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_11_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_11_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_11_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_11_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_11_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_11_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_11_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [7:0] _mshrs_11_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_11_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_11_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_11_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_11_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_11_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_11_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_11_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_11_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_11_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_status_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_10_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_10_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_10_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_10_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_10_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_10_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_10_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [7:0] _mshrs_10_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_10_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_10_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_10_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_10_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_10_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_10_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_10_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_10_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_10_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_status_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_9_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_9_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_9_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_9_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_9_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_9_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_9_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_9_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [7:0] _mshrs_9_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_9_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_9_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_9_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_9_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_9_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_9_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_9_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_9_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_9_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_status_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_8_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_8_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_8_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_8_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_8_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_8_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_8_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_8_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [7:0] _mshrs_8_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_8_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_8_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_8_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_8_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_8_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_8_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_8_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_8_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_8_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_status_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_7_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_7_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_7_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_7_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_7_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_7_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_7_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_7_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [7:0] _mshrs_7_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_7_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_7_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_7_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_7_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_7_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_7_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_7_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_7_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_7_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_status_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_6_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_6_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_6_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_6_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_6_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_6_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_6_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [7:0] _mshrs_6_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_6_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_6_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_6_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_6_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_6_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_6_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_6_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_6_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_6_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_status_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_5_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_5_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_5_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_5_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_5_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_5_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_5_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [7:0] _mshrs_5_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_5_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_5_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_5_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_5_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_5_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_5_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_5_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_5_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_5_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_status_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_4_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_4_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_4_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_4_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_4_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_4_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_4_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_4_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [7:0] _mshrs_4_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_4_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_4_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_4_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_4_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_4_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_4_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_4_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_4_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_4_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_status_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_3_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_3_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_3_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_3_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_3_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_3_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_3_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_3_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [7:0] _mshrs_3_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_3_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_3_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_3_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_3_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_3_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_3_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_3_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_3_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_3_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_status_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_2_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_2_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_2_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_2_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_2_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_2_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_2_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_2_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [7:0] _mshrs_2_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_2_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_2_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_2_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_2_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_2_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_2_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_2_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_2_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_2_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_status_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_1_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_1_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_1_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_1_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_1_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_1_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_1_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_1_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [7:0] _mshrs_1_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_1_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_1_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_1_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_1_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_1_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_1_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_1_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_1_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_1_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_status_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_0_io_status_bits_set; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_0_io_status_bits_tag; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_status_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_status_bits_blockB; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_status_bits_nestB; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_status_bits_blockC; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_status_bits_nestC; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_valid; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_0_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_0_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_0_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_0_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_0_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_0_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46]
wire [7:0] _mshrs_0_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_0_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_0_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46]
wire [5:0] _mshrs_0_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_0_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46]
wire [9:0] _mshrs_0_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46]
wire [2:0] _mshrs_0_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46]
wire [1:0] _mshrs_0_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46]
wire [12:0] _mshrs_0_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46]
wire _mshrs_0_io_schedule_bits_reload; // @[Scheduler.scala:71:46]
wire _requests_io_push_ready; // @[Scheduler.scala:70:24]
wire [35:0] _requests_io_valid; // @[Scheduler.scala:70:24]
wire _requests_io_data_prio_0; // @[Scheduler.scala:70:24]
wire _requests_io_data_prio_1; // @[Scheduler.scala:70:24]
wire _requests_io_data_prio_2; // @[Scheduler.scala:70:24]
wire _requests_io_data_control; // @[Scheduler.scala:70:24]
wire [2:0] _requests_io_data_opcode; // @[Scheduler.scala:70:24]
wire [2:0] _requests_io_data_param; // @[Scheduler.scala:70:24]
wire [2:0] _requests_io_data_size; // @[Scheduler.scala:70:24]
wire [7:0] _requests_io_data_source; // @[Scheduler.scala:70:24]
wire [12:0] _requests_io_data_tag; // @[Scheduler.scala:70:24]
wire [5:0] _requests_io_data_offset; // @[Scheduler.scala:70:24]
wire [5:0] _requests_io_data_put; // @[Scheduler.scala:70:24]
wire _bankedStore_io_sinkC_adr_ready; // @[Scheduler.scala:69:27]
wire _bankedStore_io_sinkD_adr_ready; // @[Scheduler.scala:69:27]
wire _bankedStore_io_sourceC_adr_ready; // @[Scheduler.scala:69:27]
wire [63:0] _bankedStore_io_sourceC_dat_data; // @[Scheduler.scala:69:27]
wire _bankedStore_io_sourceD_radr_ready; // @[Scheduler.scala:69:27]
wire [127:0] _bankedStore_io_sourceD_rdat_data; // @[Scheduler.scala:69:27]
wire _bankedStore_io_sourceD_wadr_ready; // @[Scheduler.scala:69:27]
wire _directory_io_write_ready; // @[Scheduler.scala:68:25]
wire _directory_io_result_bits_dirty; // @[Scheduler.scala:68:25]
wire [1:0] _directory_io_result_bits_state; // @[Scheduler.scala:68:25]
wire _directory_io_result_bits_clients; // @[Scheduler.scala:68:25]
wire [12:0] _directory_io_result_bits_tag; // @[Scheduler.scala:68:25]
wire _directory_io_result_bits_hit; // @[Scheduler.scala:68:25]
wire [2:0] _directory_io_result_bits_way; // @[Scheduler.scala:68:25]
wire _directory_io_ready; // @[Scheduler.scala:68:25]
wire _sinkX_io_req_valid; // @[Scheduler.scala:58:21]
wire [12:0] _sinkX_io_req_bits_tag; // @[Scheduler.scala:58:21]
wire [9:0] _sinkX_io_req_bits_set; // @[Scheduler.scala:58:21]
wire _sinkE_io_resp_valid; // @[Scheduler.scala:57:21]
wire [3:0] _sinkE_io_resp_bits_sink; // @[Scheduler.scala:57:21]
wire _sinkD_io_resp_valid; // @[Scheduler.scala:56:21]
wire _sinkD_io_resp_bits_last; // @[Scheduler.scala:56:21]
wire [2:0] _sinkD_io_resp_bits_opcode; // @[Scheduler.scala:56:21]
wire [2:0] _sinkD_io_resp_bits_param; // @[Scheduler.scala:56:21]
wire [3:0] _sinkD_io_resp_bits_source; // @[Scheduler.scala:56:21]
wire [2:0] _sinkD_io_resp_bits_sink; // @[Scheduler.scala:56:21]
wire _sinkD_io_resp_bits_denied; // @[Scheduler.scala:56:21]
wire [3:0] _sinkD_io_source; // @[Scheduler.scala:56:21]
wire _sinkD_io_bs_adr_valid; // @[Scheduler.scala:56:21]
wire _sinkD_io_bs_adr_bits_noop; // @[Scheduler.scala:56:21]
wire [2:0] _sinkD_io_bs_adr_bits_way; // @[Scheduler.scala:56:21]
wire [9:0] _sinkD_io_bs_adr_bits_set; // @[Scheduler.scala:56:21]
wire [2:0] _sinkD_io_bs_adr_bits_beat; // @[Scheduler.scala:56:21]
wire [63:0] _sinkD_io_bs_dat_data; // @[Scheduler.scala:56:21]
wire [9:0] _sinkD_io_grant_req_set; // @[Scheduler.scala:56:21]
wire [2:0] _sinkD_io_grant_req_way; // @[Scheduler.scala:56:21]
wire _sinkC_io_req_valid; // @[Scheduler.scala:55:21]
wire [2:0] _sinkC_io_req_bits_opcode; // @[Scheduler.scala:55:21]
wire [2:0] _sinkC_io_req_bits_param; // @[Scheduler.scala:55:21]
wire [2:0] _sinkC_io_req_bits_size; // @[Scheduler.scala:55:21]
wire [7:0] _sinkC_io_req_bits_source; // @[Scheduler.scala:55:21]
wire [12:0] _sinkC_io_req_bits_tag; // @[Scheduler.scala:55:21]
wire [5:0] _sinkC_io_req_bits_offset; // @[Scheduler.scala:55:21]
wire [5:0] _sinkC_io_req_bits_put; // @[Scheduler.scala:55:21]
wire [9:0] _sinkC_io_req_bits_set; // @[Scheduler.scala:55:21]
wire _sinkC_io_resp_valid; // @[Scheduler.scala:55:21]
wire _sinkC_io_resp_bits_last; // @[Scheduler.scala:55:21]
wire [9:0] _sinkC_io_resp_bits_set; // @[Scheduler.scala:55:21]
wire [12:0] _sinkC_io_resp_bits_tag; // @[Scheduler.scala:55:21]
wire [7:0] _sinkC_io_resp_bits_source; // @[Scheduler.scala:55:21]
wire [2:0] _sinkC_io_resp_bits_param; // @[Scheduler.scala:55:21]
wire _sinkC_io_resp_bits_data; // @[Scheduler.scala:55:21]
wire [9:0] _sinkC_io_set; // @[Scheduler.scala:55:21]
wire _sinkC_io_bs_adr_valid; // @[Scheduler.scala:55:21]
wire _sinkC_io_bs_adr_bits_noop; // @[Scheduler.scala:55:21]
wire [2:0] _sinkC_io_bs_adr_bits_way; // @[Scheduler.scala:55:21]
wire [9:0] _sinkC_io_bs_adr_bits_set; // @[Scheduler.scala:55:21]
wire [1:0] _sinkC_io_bs_adr_bits_beat; // @[Scheduler.scala:55:21]
wire [1:0] _sinkC_io_bs_adr_bits_mask; // @[Scheduler.scala:55:21]
wire [127:0] _sinkC_io_bs_dat_data; // @[Scheduler.scala:55:21]
wire _sinkC_io_rel_pop_ready; // @[Scheduler.scala:55:21]
wire [127:0] _sinkC_io_rel_beat_data; // @[Scheduler.scala:55:21]
wire _sinkC_io_rel_beat_corrupt; // @[Scheduler.scala:55:21]
wire _sinkA_io_req_valid; // @[Scheduler.scala:54:21]
wire [2:0] _sinkA_io_req_bits_opcode; // @[Scheduler.scala:54:21]
wire [2:0] _sinkA_io_req_bits_param; // @[Scheduler.scala:54:21]
wire [2:0] _sinkA_io_req_bits_size; // @[Scheduler.scala:54:21]
wire [7:0] _sinkA_io_req_bits_source; // @[Scheduler.scala:54:21]
wire [12:0] _sinkA_io_req_bits_tag; // @[Scheduler.scala:54:21]
wire [5:0] _sinkA_io_req_bits_offset; // @[Scheduler.scala:54:21]
wire [5:0] _sinkA_io_req_bits_put; // @[Scheduler.scala:54:21]
wire [9:0] _sinkA_io_req_bits_set; // @[Scheduler.scala:54:21]
wire _sinkA_io_pb_pop_ready; // @[Scheduler.scala:54:21]
wire [127:0] _sinkA_io_pb_beat_data; // @[Scheduler.scala:54:21]
wire [15:0] _sinkA_io_pb_beat_mask; // @[Scheduler.scala:54:21]
wire _sinkA_io_pb_beat_corrupt; // @[Scheduler.scala:54:21]
wire _sourceX_io_req_ready; // @[Scheduler.scala:45:23]
wire _sourceE_io_req_ready; // @[Scheduler.scala:44:23]
wire _sourceD_io_req_ready; // @[Scheduler.scala:43:23]
wire _sourceD_io_pb_pop_valid; // @[Scheduler.scala:43:23]
wire [5:0] _sourceD_io_pb_pop_bits_index; // @[Scheduler.scala:43:23]
wire _sourceD_io_pb_pop_bits_last; // @[Scheduler.scala:43:23]
wire _sourceD_io_rel_pop_valid; // @[Scheduler.scala:43:23]
wire [5:0] _sourceD_io_rel_pop_bits_index; // @[Scheduler.scala:43:23]
wire _sourceD_io_rel_pop_bits_last; // @[Scheduler.scala:43:23]
wire _sourceD_io_bs_radr_valid; // @[Scheduler.scala:43:23]
wire [2:0] _sourceD_io_bs_radr_bits_way; // @[Scheduler.scala:43:23]
wire [9:0] _sourceD_io_bs_radr_bits_set; // @[Scheduler.scala:43:23]
wire [1:0] _sourceD_io_bs_radr_bits_beat; // @[Scheduler.scala:43:23]
wire [1:0] _sourceD_io_bs_radr_bits_mask; // @[Scheduler.scala:43:23]
wire _sourceD_io_bs_wadr_valid; // @[Scheduler.scala:43:23]
wire [2:0] _sourceD_io_bs_wadr_bits_way; // @[Scheduler.scala:43:23]
wire [9:0] _sourceD_io_bs_wadr_bits_set; // @[Scheduler.scala:43:23]
wire [1:0] _sourceD_io_bs_wadr_bits_beat; // @[Scheduler.scala:43:23]
wire [1:0] _sourceD_io_bs_wadr_bits_mask; // @[Scheduler.scala:43:23]
wire [127:0] _sourceD_io_bs_wdat_data; // @[Scheduler.scala:43:23]
wire _sourceD_io_evict_safe; // @[Scheduler.scala:43:23]
wire _sourceD_io_grant_safe; // @[Scheduler.scala:43:23]
wire _sourceC_io_req_ready; // @[Scheduler.scala:42:23]
wire _sourceC_io_bs_adr_valid; // @[Scheduler.scala:42:23]
wire [2:0] _sourceC_io_bs_adr_bits_way; // @[Scheduler.scala:42:23]
wire [9:0] _sourceC_io_bs_adr_bits_set; // @[Scheduler.scala:42:23]
wire [2:0] _sourceC_io_bs_adr_bits_beat; // @[Scheduler.scala:42:23]
wire [9:0] _sourceC_io_evict_req_set; // @[Scheduler.scala:42:23]
wire [2:0] _sourceC_io_evict_req_way; // @[Scheduler.scala:42:23]
wire _sourceB_io_req_ready; // @[Scheduler.scala:41:23]
wire _sourceA_io_req_ready; // @[Scheduler.scala:40:23]
wire io_in_a_valid_0 = io_in_a_valid; // @[Scheduler.scala:27:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Scheduler.scala:27:7]
wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Scheduler.scala:27:7]
wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Scheduler.scala:27:7]
wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Scheduler.scala:27:7]
wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Scheduler.scala:27:7]
wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Scheduler.scala:27:7]
wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Scheduler.scala:27:7]
wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Scheduler.scala:27:7]
wire io_in_b_ready_0 = io_in_b_ready; // @[Scheduler.scala:27:7]
wire io_in_c_valid_0 = io_in_c_valid; // @[Scheduler.scala:27:7]
wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Scheduler.scala:27:7]
wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Scheduler.scala:27:7]
wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Scheduler.scala:27:7]
wire [7:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Scheduler.scala:27:7]
wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Scheduler.scala:27:7]
wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Scheduler.scala:27:7]
wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Scheduler.scala:27:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Scheduler.scala:27:7]
wire io_in_e_valid_0 = io_in_e_valid; // @[Scheduler.scala:27:7]
wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Scheduler.scala:27:7]
wire io_out_a_ready_0 = io_out_a_ready; // @[Scheduler.scala:27:7]
wire io_out_c_ready_0 = io_out_c_ready; // @[Scheduler.scala:27:7]
wire io_out_d_valid_0 = io_out_d_valid; // @[Scheduler.scala:27:7]
wire [2:0] io_out_d_bits_opcode_0 = io_out_d_bits_opcode; // @[Scheduler.scala:27:7]
wire [1:0] io_out_d_bits_param_0 = io_out_d_bits_param; // @[Scheduler.scala:27:7]
wire [2:0] io_out_d_bits_size_0 = io_out_d_bits_size; // @[Scheduler.scala:27:7]
wire [3:0] io_out_d_bits_source_0 = io_out_d_bits_source; // @[Scheduler.scala:27:7]
wire [2:0] io_out_d_bits_sink_0 = io_out_d_bits_sink; // @[Scheduler.scala:27:7]
wire io_out_d_bits_denied_0 = io_out_d_bits_denied; // @[Scheduler.scala:27:7]
wire [63:0] io_out_d_bits_data_0 = io_out_d_bits_data; // @[Scheduler.scala:27:7]
wire io_out_d_bits_corrupt_0 = io_out_d_bits_corrupt; // @[Scheduler.scala:27:7]
wire io_req_valid_0 = io_req_valid; // @[Scheduler.scala:27:7]
wire [31:0] io_req_bits_address_0 = io_req_bits_address; // @[Scheduler.scala:27:7]
wire io_in_b_bits_corrupt = 1'h0; // @[Scheduler.scala:27:7]
wire io_out_b_valid = 1'h0; // @[Scheduler.scala:27:7]
wire io_out_b_bits_corrupt = 1'h0; // @[Scheduler.scala:27:7]
wire io_resp_bits_fail = 1'h0; // @[Scheduler.scala:27:7]
wire schedule_x_bits_fail = 1'h0; // @[Mux.scala:30:73]
wire _schedule_WIRE_11_bits_fail = 1'h0; // @[Mux.scala:30:73]
wire _schedule_WIRE_12_fail = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_196 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_197 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_198 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_199 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_200 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_201 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_202 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_203 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_204 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_205 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_206 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_207 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_208 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_209 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_210 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_211 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_212 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_213 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_214 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_215 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_216 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_217 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_218 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_WIRE_13 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_574 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_575 = 1'h0; // @[Mux.scala:30:73]
wire _schedule_T_598 = 1'h0; // @[Mux.scala:30:73]
wire request_bits_prio_1 = 1'h0; // @[Scheduler.scala:163:21]
wire _request_bits_T_prio_1 = 1'h0; // @[Scheduler.scala:166:22]
wire _request_bits_T_prio_2 = 1'h0; // @[Scheduler.scala:166:22]
wire _request_bits_T_1_prio_1 = 1'h0; // @[Scheduler.scala:165:22]
wire blockB = 1'h0; // @[Scheduler.scala:175:70]
wire nestB = 1'h0; // @[Scheduler.scala:179:70]
wire _view__WIRE_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_1_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_2_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_3_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_4_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_5_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_6_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_7_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_8_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_9_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_10_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _view__WIRE_11_prio_1 = 1'h0; // @[Scheduler.scala:233:95]
wire _request_alloc_cases_T_4 = 1'h0; // @[Scheduler.scala:259:13]
wire _request_alloc_cases_T_6 = 1'h0; // @[Scheduler.scala:259:56]
wire _request_alloc_cases_T_8 = 1'h0; // @[Scheduler.scala:259:84]
wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Scheduler.scala:27:7]
wire [2:0] io_in_b_bits_size = 3'h6; // @[Scheduler.scala:27:7]
wire [7:0] io_in_b_bits_source = 8'hA0; // @[Scheduler.scala:27:7]
wire [15:0] io_in_b_bits_mask = 16'hFFFF; // @[Scheduler.scala:27:7]
wire [127:0] io_in_b_bits_data = 128'h0; // @[Scheduler.scala:27:7]
wire io_in_e_ready = 1'h1; // @[Scheduler.scala:27:7]
wire io_out_b_ready = 1'h1; // @[Scheduler.scala:27:7]
wire io_out_e_ready = 1'h1; // @[Scheduler.scala:27:7]
wire io_resp_ready = 1'h1; // @[Scheduler.scala:27:7]
wire _mshr_request_T_253 = 1'h1; // @[Scheduler.scala:107:28]
wire _request_bits_T_prio_0 = 1'h1; // @[Scheduler.scala:166:22]
wire _queue_T_1 = 1'h1; // @[Scheduler.scala:185:35]
wire _queue_T_5 = 1'h1; // @[Scheduler.scala:185:55]
wire [2:0] io_out_b_bits_opcode = 3'h0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_b_bits_size = 3'h0; // @[Scheduler.scala:27:7]
wire [1:0] io_out_b_bits_param = 2'h0; // @[Scheduler.scala:27:7]
wire [3:0] io_out_b_bits_source = 4'h0; // @[Scheduler.scala:27:7]
wire [3:0] _schedule_WIRE_19_bits_sink = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_20_sink = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_334 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_335 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_336 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_337 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_338 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_339 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_340 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_341 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_342 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_343 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_344 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_345 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_346 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_347 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_348 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_349 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_350 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_351 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_352 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_353 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_354 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_355 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_356 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_23 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_38_bits_source = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_39_source = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_748 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_749 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_750 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_751 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_752 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_753 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_754 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_755 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_756 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_757 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_758 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_759 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_760 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_761 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_762 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_763 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_764 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_765 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_766 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_767 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_768 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_769 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_770 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_44 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_55_bits_source = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_56_source = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_978 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_979 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_980 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_981 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_982 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_983 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_984 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_985 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_986 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_987 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_988 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_989 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_990 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_991 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_992 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_993 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_994 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_995 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_996 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_997 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_998 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_999 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_T_1000 = 4'h0; // @[Mux.scala:30:73]
wire [3:0] _schedule_WIRE_58 = 4'h0; // @[Mux.scala:30:73]
wire [31:0] io_out_b_bits_address = 32'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_out_b_bits_mask = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_0 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_1 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_2 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_3 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_4 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_5 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_6 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_7 = 8'h0; // @[Scheduler.scala:27:7]
wire [7:0] io_ways_8 = 8'h0; // @[Scheduler.scala:27:7]
wire [63:0] io_out_b_bits_data = 64'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_0 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_1 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_2 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_3 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_4 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_5 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_6 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_7 = 11'h0; // @[Scheduler.scala:27:7]
wire [10:0] io_divs_8 = 11'h0; // @[Scheduler.scala:27:7]
wire [11:0] _lowerMatches1_T_1 = 12'h800; // @[Scheduler.scala:200:43]
wire [11:0] _dirTarget_T = 12'h800; // @[Scheduler.scala:306:48]
wire [4:0] _requests_io_push_bits_index_T_43 = 5'h0; // @[Mux.scala:30:73]
wire [9:0] _prioFilter_T_1 = 10'h3FF; // @[Scheduler.scala:182:69]
wire [10:0] _lowerMatches1_T_3 = 11'h400; // @[Scheduler.scala:201:43]
wire io_in_a_ready_0; // @[Scheduler.scala:27:7]
wire [1:0] io_in_b_bits_param_0; // @[Scheduler.scala:27:7]
wire [31:0] io_in_b_bits_address_0; // @[Scheduler.scala:27:7]
wire io_in_b_valid_0; // @[Scheduler.scala:27:7]
wire io_in_c_ready_0; // @[Scheduler.scala:27:7]
wire [2:0] io_in_d_bits_opcode_0; // @[Scheduler.scala:27:7]
wire [1:0] io_in_d_bits_param_0; // @[Scheduler.scala:27:7]
wire [2:0] io_in_d_bits_size_0; // @[Scheduler.scala:27:7]
wire [7:0] io_in_d_bits_source_0; // @[Scheduler.scala:27:7]
wire [3:0] io_in_d_bits_sink_0; // @[Scheduler.scala:27:7]
wire io_in_d_bits_denied_0; // @[Scheduler.scala:27:7]
wire [127:0] io_in_d_bits_data_0; // @[Scheduler.scala:27:7]
wire io_in_d_bits_corrupt_0; // @[Scheduler.scala:27:7]
wire io_in_d_valid_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_a_bits_opcode_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_a_bits_param_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_a_bits_size_0; // @[Scheduler.scala:27:7]
wire [3:0] io_out_a_bits_source_0; // @[Scheduler.scala:27:7]
wire [31:0] io_out_a_bits_address_0; // @[Scheduler.scala:27:7]
wire [7:0] io_out_a_bits_mask_0; // @[Scheduler.scala:27:7]
wire [63:0] io_out_a_bits_data_0; // @[Scheduler.scala:27:7]
wire io_out_a_bits_corrupt_0; // @[Scheduler.scala:27:7]
wire io_out_a_valid_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_c_bits_opcode_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_c_bits_param_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_c_bits_size_0; // @[Scheduler.scala:27:7]
wire [3:0] io_out_c_bits_source_0; // @[Scheduler.scala:27:7]
wire [31:0] io_out_c_bits_address_0; // @[Scheduler.scala:27:7]
wire [63:0] io_out_c_bits_data_0; // @[Scheduler.scala:27:7]
wire io_out_c_bits_corrupt_0; // @[Scheduler.scala:27:7]
wire io_out_c_valid_0; // @[Scheduler.scala:27:7]
wire io_out_d_ready_0; // @[Scheduler.scala:27:7]
wire [2:0] io_out_e_bits_sink_0; // @[Scheduler.scala:27:7]
wire io_out_e_valid_0; // @[Scheduler.scala:27:7]
wire io_req_ready_0; // @[Scheduler.scala:27:7]
wire io_resp_valid_0; // @[Scheduler.scala:27:7]
wire [9:0] _nestedwb_set_T; // @[Scheduler.scala:155:24]
wire [12:0] _nestedwb_tag_T; // @[Scheduler.scala:156:24]
wire _nestedwb_b_toN_T_2; // @[Scheduler.scala:157:75]
wire _nestedwb_b_toB_T_2; // @[Scheduler.scala:158:75]
wire _nestedwb_b_clr_dirty_T; // @[Scheduler.scala:159:37]
wire _nestedwb_c_set_dirty_T_1; // @[Scheduler.scala:160:75]
wire [9:0] nestedwb_set; // @[Scheduler.scala:75:22]
wire [12:0] nestedwb_tag; // @[Scheduler.scala:75:22]
wire nestedwb_b_toN; // @[Scheduler.scala:75:22]
wire nestedwb_b_toB; // @[Scheduler.scala:75:22]
wire nestedwb_b_clr_dirty; // @[Scheduler.scala:75:22]
wire nestedwb_c_set_dirty; // @[Scheduler.scala:75:22]
wire _mshrs_0_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_0_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_0_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_0_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_0_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h0; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_0_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_0_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_0_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h0; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_0_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_0_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_1_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_1_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_1_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_1_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_1_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h1; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_1_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_1_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_1_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h1; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_1_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_1_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_2_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_2_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_2_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_2_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_2_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h2; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_2_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_2_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_2_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h2; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_2_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_2_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_3_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_3_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_3_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_3_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_3_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h3; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_3_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_3_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_3_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h3; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_3_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_3_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_4_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_4_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_4_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_4_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_4_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h4; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_4_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_4_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_4_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h4; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_4_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_4_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_5_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_5_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_5_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_5_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h5; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_5_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_5_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_5_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h5; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_5_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_5_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_6_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_6_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_6_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_6_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h6; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_6_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_6_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_6_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h6; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_6_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_6_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_7_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_7_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_7_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_7_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_7_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h7; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_7_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_7_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_7_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h7; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_7_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_7_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_8_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_8_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_8_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_8_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_8_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h8; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_8_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_8_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_8_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h8; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_8_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_8_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_9_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_9_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_9_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_9_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_9_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h9; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_9_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_9_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_9_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h9; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_9_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_9_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_10_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_10_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_10_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_10_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'hA; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_10_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_10_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_10_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'hA; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_10_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_10_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshrs_11_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71]
wire _mshrs_11_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_11_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}]
wire _mshrs_11_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'hB; // @[Scheduler.scala:56:21, :80:74]
wire _mshrs_11_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_11_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}]
wire _mshrs_11_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'hB; // @[Scheduler.scala:57:21, :81:74]
wire _mshrs_11_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_11_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}]
wire _mshr_stall_abc_T = _mshrs_0_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_1 = _mshrs_10_io_status_valid & _mshr_stall_abc_T; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_2 = _mshrs_0_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_3 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_2; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_0 = _mshr_stall_abc_T_1 | _mshr_stall_abc_T_3; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_4 = _mshrs_1_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_5 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_4; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_6 = _mshrs_1_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_7 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_6; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_1 = _mshr_stall_abc_T_5 | _mshr_stall_abc_T_7; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_8 = _mshrs_2_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_9 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_8; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_10 = _mshrs_2_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_11 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_10; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_2 = _mshr_stall_abc_T_9 | _mshr_stall_abc_T_11; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_12 = _mshrs_3_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_13 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_12; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_14 = _mshrs_3_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_15 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_14; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_3 = _mshr_stall_abc_T_13 | _mshr_stall_abc_T_15; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_16 = _mshrs_4_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_17 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_16; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_18 = _mshrs_4_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_19 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_18; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_4 = _mshr_stall_abc_T_17 | _mshr_stall_abc_T_19; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_20 = _mshrs_5_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_21 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_20; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_22 = _mshrs_5_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_23 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_22; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_5 = _mshr_stall_abc_T_21 | _mshr_stall_abc_T_23; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_24 = _mshrs_6_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_25 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_24; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_26 = _mshrs_6_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_27 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_26; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_6 = _mshr_stall_abc_T_25 | _mshr_stall_abc_T_27; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_28 = _mshrs_7_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_29 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_28; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_30 = _mshrs_7_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_31 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_30; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_7 = _mshr_stall_abc_T_29 | _mshr_stall_abc_T_31; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_32 = _mshrs_8_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_33 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_32; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_34 = _mshrs_8_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_35 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_34; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_8 = _mshr_stall_abc_T_33 | _mshr_stall_abc_T_35; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_abc_T_36 = _mshrs_9_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54]
wire _mshr_stall_abc_T_37 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_36; // @[Scheduler.scala:71:46, :90:{30,54}]
wire _mshr_stall_abc_T_38 = _mshrs_9_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54]
wire _mshr_stall_abc_T_39 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_38; // @[Scheduler.scala:71:46, :91:{30,54}]
wire mshr_stall_abc_9 = _mshr_stall_abc_T_37 | _mshr_stall_abc_T_39; // @[Scheduler.scala:90:{30,86}, :91:30]
wire _mshr_stall_bc_T = _mshrs_10_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :94:58]
wire mshr_stall_bc = _mshrs_11_io_status_valid & _mshr_stall_bc_T; // @[Scheduler.scala:71:46, :94:{28,58}]
wire stall_abc_0 = mshr_stall_abc_0 & _mshrs_0_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_1 = mshr_stall_abc_1 & _mshrs_1_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_2 = mshr_stall_abc_2 & _mshrs_2_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_3 = mshr_stall_abc_3 & _mshrs_3_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_4 = mshr_stall_abc_4 & _mshrs_4_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_5 = mshr_stall_abc_5 & _mshrs_5_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_6 = mshr_stall_abc_6 & _mshrs_6_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_7 = mshr_stall_abc_7 & _mshrs_7_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_8 = mshr_stall_abc_8 & _mshrs_8_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire stall_abc_9 = mshr_stall_abc_9 & _mshrs_9_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73]
wire _mshr_request_T = ~mshr_stall_abc_0; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_1 = _mshrs_0_io_schedule_valid & _mshr_request_T; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_2 = ~_mshrs_0_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_3 = _sourceA_io_req_ready | _mshr_request_T_2; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_4 = _mshr_request_T_1 & _mshr_request_T_3; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_5 = ~_mshrs_0_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_6 = _sourceB_io_req_ready | _mshr_request_T_5; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_7 = _mshr_request_T_4 & _mshr_request_T_6; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_8 = ~_mshrs_0_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_9 = _sourceC_io_req_ready | _mshr_request_T_8; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_10 = _mshr_request_T_7 & _mshr_request_T_9; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_11 = ~_mshrs_0_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_12 = _sourceD_io_req_ready | _mshr_request_T_11; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_13 = _mshr_request_T_10 & _mshr_request_T_12; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_14 = ~_mshrs_0_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_15 = _sourceE_io_req_ready | _mshr_request_T_14; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_16 = _mshr_request_T_13 & _mshr_request_T_15; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_17 = ~_mshrs_0_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_18 = _sourceX_io_req_ready | _mshr_request_T_17; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_19 = _mshr_request_T_16 & _mshr_request_T_18; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_20 = ~_mshrs_0_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_21 = _directory_io_write_ready | _mshr_request_T_20; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_22 = _mshr_request_T_19 & _mshr_request_T_21; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_23 = ~mshr_stall_abc_1; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_24 = _mshrs_1_io_schedule_valid & _mshr_request_T_23; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_25 = ~_mshrs_1_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_26 = _sourceA_io_req_ready | _mshr_request_T_25; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_27 = _mshr_request_T_24 & _mshr_request_T_26; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_28 = ~_mshrs_1_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_29 = _sourceB_io_req_ready | _mshr_request_T_28; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_30 = _mshr_request_T_27 & _mshr_request_T_29; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_31 = ~_mshrs_1_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_32 = _sourceC_io_req_ready | _mshr_request_T_31; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_33 = _mshr_request_T_30 & _mshr_request_T_32; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_34 = ~_mshrs_1_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_35 = _sourceD_io_req_ready | _mshr_request_T_34; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_36 = _mshr_request_T_33 & _mshr_request_T_35; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_37 = ~_mshrs_1_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_38 = _sourceE_io_req_ready | _mshr_request_T_37; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_39 = _mshr_request_T_36 & _mshr_request_T_38; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_40 = ~_mshrs_1_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_41 = _sourceX_io_req_ready | _mshr_request_T_40; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_42 = _mshr_request_T_39 & _mshr_request_T_41; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_43 = ~_mshrs_1_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_44 = _directory_io_write_ready | _mshr_request_T_43; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_45 = _mshr_request_T_42 & _mshr_request_T_44; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_46 = ~mshr_stall_abc_2; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_47 = _mshrs_2_io_schedule_valid & _mshr_request_T_46; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_48 = ~_mshrs_2_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_49 = _sourceA_io_req_ready | _mshr_request_T_48; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_50 = _mshr_request_T_47 & _mshr_request_T_49; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_51 = ~_mshrs_2_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_52 = _sourceB_io_req_ready | _mshr_request_T_51; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_53 = _mshr_request_T_50 & _mshr_request_T_52; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_54 = ~_mshrs_2_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_55 = _sourceC_io_req_ready | _mshr_request_T_54; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_56 = _mshr_request_T_53 & _mshr_request_T_55; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_57 = ~_mshrs_2_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_58 = _sourceD_io_req_ready | _mshr_request_T_57; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_59 = _mshr_request_T_56 & _mshr_request_T_58; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_60 = ~_mshrs_2_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_61 = _sourceE_io_req_ready | _mshr_request_T_60; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_62 = _mshr_request_T_59 & _mshr_request_T_61; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_63 = ~_mshrs_2_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_64 = _sourceX_io_req_ready | _mshr_request_T_63; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_65 = _mshr_request_T_62 & _mshr_request_T_64; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_66 = ~_mshrs_2_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_67 = _directory_io_write_ready | _mshr_request_T_66; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_68 = _mshr_request_T_65 & _mshr_request_T_67; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_69 = ~mshr_stall_abc_3; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_70 = _mshrs_3_io_schedule_valid & _mshr_request_T_69; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_71 = ~_mshrs_3_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_72 = _sourceA_io_req_ready | _mshr_request_T_71; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_73 = _mshr_request_T_70 & _mshr_request_T_72; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_74 = ~_mshrs_3_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_75 = _sourceB_io_req_ready | _mshr_request_T_74; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_76 = _mshr_request_T_73 & _mshr_request_T_75; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_77 = ~_mshrs_3_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_78 = _sourceC_io_req_ready | _mshr_request_T_77; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_79 = _mshr_request_T_76 & _mshr_request_T_78; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_80 = ~_mshrs_3_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_81 = _sourceD_io_req_ready | _mshr_request_T_80; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_82 = _mshr_request_T_79 & _mshr_request_T_81; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_83 = ~_mshrs_3_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_84 = _sourceE_io_req_ready | _mshr_request_T_83; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_85 = _mshr_request_T_82 & _mshr_request_T_84; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_86 = ~_mshrs_3_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_87 = _sourceX_io_req_ready | _mshr_request_T_86; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_88 = _mshr_request_T_85 & _mshr_request_T_87; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_89 = ~_mshrs_3_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_90 = _directory_io_write_ready | _mshr_request_T_89; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_91 = _mshr_request_T_88 & _mshr_request_T_90; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_92 = ~mshr_stall_abc_4; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_93 = _mshrs_4_io_schedule_valid & _mshr_request_T_92; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_94 = ~_mshrs_4_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_95 = _sourceA_io_req_ready | _mshr_request_T_94; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_96 = _mshr_request_T_93 & _mshr_request_T_95; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_97 = ~_mshrs_4_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_98 = _sourceB_io_req_ready | _mshr_request_T_97; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_99 = _mshr_request_T_96 & _mshr_request_T_98; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_100 = ~_mshrs_4_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_101 = _sourceC_io_req_ready | _mshr_request_T_100; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_102 = _mshr_request_T_99 & _mshr_request_T_101; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_103 = ~_mshrs_4_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_104 = _sourceD_io_req_ready | _mshr_request_T_103; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_105 = _mshr_request_T_102 & _mshr_request_T_104; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_106 = ~_mshrs_4_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_107 = _sourceE_io_req_ready | _mshr_request_T_106; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_108 = _mshr_request_T_105 & _mshr_request_T_107; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_109 = ~_mshrs_4_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_110 = _sourceX_io_req_ready | _mshr_request_T_109; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_111 = _mshr_request_T_108 & _mshr_request_T_110; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_112 = ~_mshrs_4_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_113 = _directory_io_write_ready | _mshr_request_T_112; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_114 = _mshr_request_T_111 & _mshr_request_T_113; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_115 = ~mshr_stall_abc_5; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_116 = _mshrs_5_io_schedule_valid & _mshr_request_T_115; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_117 = ~_mshrs_5_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_118 = _sourceA_io_req_ready | _mshr_request_T_117; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_119 = _mshr_request_T_116 & _mshr_request_T_118; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_120 = ~_mshrs_5_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_121 = _sourceB_io_req_ready | _mshr_request_T_120; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_122 = _mshr_request_T_119 & _mshr_request_T_121; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_123 = ~_mshrs_5_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_124 = _sourceC_io_req_ready | _mshr_request_T_123; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_125 = _mshr_request_T_122 & _mshr_request_T_124; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_126 = ~_mshrs_5_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_127 = _sourceD_io_req_ready | _mshr_request_T_126; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_128 = _mshr_request_T_125 & _mshr_request_T_127; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_129 = ~_mshrs_5_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_130 = _sourceE_io_req_ready | _mshr_request_T_129; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_131 = _mshr_request_T_128 & _mshr_request_T_130; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_132 = ~_mshrs_5_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_133 = _sourceX_io_req_ready | _mshr_request_T_132; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_134 = _mshr_request_T_131 & _mshr_request_T_133; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_135 = ~_mshrs_5_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_136 = _directory_io_write_ready | _mshr_request_T_135; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_137 = _mshr_request_T_134 & _mshr_request_T_136; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_138 = ~mshr_stall_abc_6; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_139 = _mshrs_6_io_schedule_valid & _mshr_request_T_138; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_140 = ~_mshrs_6_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_141 = _sourceA_io_req_ready | _mshr_request_T_140; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_142 = _mshr_request_T_139 & _mshr_request_T_141; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_143 = ~_mshrs_6_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_144 = _sourceB_io_req_ready | _mshr_request_T_143; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_145 = _mshr_request_T_142 & _mshr_request_T_144; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_146 = ~_mshrs_6_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_147 = _sourceC_io_req_ready | _mshr_request_T_146; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_148 = _mshr_request_T_145 & _mshr_request_T_147; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_149 = ~_mshrs_6_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_150 = _sourceD_io_req_ready | _mshr_request_T_149; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_151 = _mshr_request_T_148 & _mshr_request_T_150; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_152 = ~_mshrs_6_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_153 = _sourceE_io_req_ready | _mshr_request_T_152; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_154 = _mshr_request_T_151 & _mshr_request_T_153; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_155 = ~_mshrs_6_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_156 = _sourceX_io_req_ready | _mshr_request_T_155; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_157 = _mshr_request_T_154 & _mshr_request_T_156; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_158 = ~_mshrs_6_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_159 = _directory_io_write_ready | _mshr_request_T_158; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_160 = _mshr_request_T_157 & _mshr_request_T_159; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_161 = ~mshr_stall_abc_7; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_162 = _mshrs_7_io_schedule_valid & _mshr_request_T_161; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_163 = ~_mshrs_7_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_164 = _sourceA_io_req_ready | _mshr_request_T_163; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_165 = _mshr_request_T_162 & _mshr_request_T_164; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_166 = ~_mshrs_7_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_167 = _sourceB_io_req_ready | _mshr_request_T_166; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_168 = _mshr_request_T_165 & _mshr_request_T_167; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_169 = ~_mshrs_7_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_170 = _sourceC_io_req_ready | _mshr_request_T_169; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_171 = _mshr_request_T_168 & _mshr_request_T_170; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_172 = ~_mshrs_7_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_173 = _sourceD_io_req_ready | _mshr_request_T_172; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_174 = _mshr_request_T_171 & _mshr_request_T_173; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_175 = ~_mshrs_7_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_176 = _sourceE_io_req_ready | _mshr_request_T_175; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_177 = _mshr_request_T_174 & _mshr_request_T_176; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_178 = ~_mshrs_7_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_179 = _sourceX_io_req_ready | _mshr_request_T_178; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_180 = _mshr_request_T_177 & _mshr_request_T_179; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_181 = ~_mshrs_7_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_182 = _directory_io_write_ready | _mshr_request_T_181; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_183 = _mshr_request_T_180 & _mshr_request_T_182; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_184 = ~mshr_stall_abc_8; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_185 = _mshrs_8_io_schedule_valid & _mshr_request_T_184; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_186 = ~_mshrs_8_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_187 = _sourceA_io_req_ready | _mshr_request_T_186; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_188 = _mshr_request_T_185 & _mshr_request_T_187; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_189 = ~_mshrs_8_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_190 = _sourceB_io_req_ready | _mshr_request_T_189; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_191 = _mshr_request_T_188 & _mshr_request_T_190; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_192 = ~_mshrs_8_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_193 = _sourceC_io_req_ready | _mshr_request_T_192; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_194 = _mshr_request_T_191 & _mshr_request_T_193; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_195 = ~_mshrs_8_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_196 = _sourceD_io_req_ready | _mshr_request_T_195; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_197 = _mshr_request_T_194 & _mshr_request_T_196; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_198 = ~_mshrs_8_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_199 = _sourceE_io_req_ready | _mshr_request_T_198; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_200 = _mshr_request_T_197 & _mshr_request_T_199; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_201 = ~_mshrs_8_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_202 = _sourceX_io_req_ready | _mshr_request_T_201; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_203 = _mshr_request_T_200 & _mshr_request_T_202; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_204 = ~_mshrs_8_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_205 = _directory_io_write_ready | _mshr_request_T_204; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_206 = _mshr_request_T_203 & _mshr_request_T_205; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_207 = ~mshr_stall_abc_9; // @[Scheduler.scala:90:86, :107:28]
wire _mshr_request_T_208 = _mshrs_9_io_schedule_valid & _mshr_request_T_207; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_209 = ~_mshrs_9_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_210 = _sourceA_io_req_ready | _mshr_request_T_209; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_211 = _mshr_request_T_208 & _mshr_request_T_210; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_212 = ~_mshrs_9_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_213 = _sourceB_io_req_ready | _mshr_request_T_212; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_214 = _mshr_request_T_211 & _mshr_request_T_213; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_215 = ~_mshrs_9_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_216 = _sourceC_io_req_ready | _mshr_request_T_215; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_217 = _mshr_request_T_214 & _mshr_request_T_216; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_218 = ~_mshrs_9_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_219 = _sourceD_io_req_ready | _mshr_request_T_218; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_220 = _mshr_request_T_217 & _mshr_request_T_219; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_221 = ~_mshrs_9_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_222 = _sourceE_io_req_ready | _mshr_request_T_221; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_223 = _mshr_request_T_220 & _mshr_request_T_222; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_224 = ~_mshrs_9_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_225 = _sourceX_io_req_ready | _mshr_request_T_224; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_226 = _mshr_request_T_223 & _mshr_request_T_225; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_227 = ~_mshrs_9_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_228 = _directory_io_write_ready | _mshr_request_T_227; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_229 = _mshr_request_T_226 & _mshr_request_T_228; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_230 = ~mshr_stall_bc; // @[Scheduler.scala:94:28, :107:28]
wire _mshr_request_T_231 = _mshrs_10_io_schedule_valid & _mshr_request_T_230; // @[Scheduler.scala:71:46, :107:{25,28}]
wire _mshr_request_T_232 = ~_mshrs_10_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_233 = _sourceA_io_req_ready | _mshr_request_T_232; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_234 = _mshr_request_T_231 & _mshr_request_T_233; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_235 = ~_mshrs_10_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_236 = _sourceB_io_req_ready | _mshr_request_T_235; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_237 = _mshr_request_T_234 & _mshr_request_T_236; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_238 = ~_mshrs_10_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_239 = _sourceC_io_req_ready | _mshr_request_T_238; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_240 = _mshr_request_T_237 & _mshr_request_T_239; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_241 = ~_mshrs_10_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_242 = _sourceD_io_req_ready | _mshr_request_T_241; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_243 = _mshr_request_T_240 & _mshr_request_T_242; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_244 = ~_mshrs_10_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_245 = _sourceE_io_req_ready | _mshr_request_T_244; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_246 = _mshr_request_T_243 & _mshr_request_T_245; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_247 = ~_mshrs_10_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_248 = _sourceX_io_req_ready | _mshr_request_T_247; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_249 = _mshr_request_T_246 & _mshr_request_T_248; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_250 = ~_mshrs_10_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_251 = _directory_io_write_ready | _mshr_request_T_250; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_252 = _mshr_request_T_249 & _mshr_request_T_251; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire _mshr_request_T_255 = ~_mshrs_11_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32]
wire _mshr_request_T_256 = _sourceA_io_req_ready | _mshr_request_T_255; // @[Scheduler.scala:40:23, :108:{29,32}]
wire _mshr_request_T_254; // @[Scheduler.scala:107:25]
wire _mshr_request_T_257 = _mshr_request_T_254 & _mshr_request_T_256; // @[Scheduler.scala:107:{25,31}, :108:29]
wire _mshr_request_T_258 = ~_mshrs_11_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32]
wire _mshr_request_T_259 = _sourceB_io_req_ready | _mshr_request_T_258; // @[Scheduler.scala:41:23, :109:{29,32}]
wire _mshr_request_T_260 = _mshr_request_T_257 & _mshr_request_T_259; // @[Scheduler.scala:107:31, :108:61, :109:29]
wire _mshr_request_T_261 = ~_mshrs_11_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32]
wire _mshr_request_T_262 = _sourceC_io_req_ready | _mshr_request_T_261; // @[Scheduler.scala:42:23, :110:{29,32}]
wire _mshr_request_T_263 = _mshr_request_T_260 & _mshr_request_T_262; // @[Scheduler.scala:108:61, :109:61, :110:29]
wire _mshr_request_T_264 = ~_mshrs_11_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32]
wire _mshr_request_T_265 = _sourceD_io_req_ready | _mshr_request_T_264; // @[Scheduler.scala:43:23, :111:{29,32}]
wire _mshr_request_T_266 = _mshr_request_T_263 & _mshr_request_T_265; // @[Scheduler.scala:109:61, :110:61, :111:29]
wire _mshr_request_T_267 = ~_mshrs_11_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32]
wire _mshr_request_T_268 = _sourceE_io_req_ready | _mshr_request_T_267; // @[Scheduler.scala:44:23, :112:{29,32}]
wire _mshr_request_T_269 = _mshr_request_T_266 & _mshr_request_T_268; // @[Scheduler.scala:110:61, :111:61, :112:29]
wire _mshr_request_T_270 = ~_mshrs_11_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32]
wire _mshr_request_T_271 = _sourceX_io_req_ready | _mshr_request_T_270; // @[Scheduler.scala:45:23, :113:{29,32}]
wire _mshr_request_T_272 = _mshr_request_T_269 & _mshr_request_T_271; // @[Scheduler.scala:111:61, :112:61, :113:29]
wire _mshr_request_T_273 = ~_mshrs_11_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36]
wire _mshr_request_T_274 = _directory_io_write_ready | _mshr_request_T_273; // @[Scheduler.scala:68:25, :114:{33,36}]
wire _mshr_request_T_275 = _mshr_request_T_272 & _mshr_request_T_274; // @[Scheduler.scala:112:61, :113:61, :114:33]
wire [1:0] mshr_request_lo_lo_hi = {_mshr_request_T_68, _mshr_request_T_45}; // @[Scheduler.scala:106:25, :113:61]
wire [2:0] mshr_request_lo_lo = {mshr_request_lo_lo_hi, _mshr_request_T_22}; // @[Scheduler.scala:106:25, :113:61]
wire [1:0] mshr_request_lo_hi_hi = {_mshr_request_T_137, _mshr_request_T_114}; // @[Scheduler.scala:106:25, :113:61]
wire [2:0] mshr_request_lo_hi = {mshr_request_lo_hi_hi, _mshr_request_T_91}; // @[Scheduler.scala:106:25, :113:61]
wire [5:0] mshr_request_lo = {mshr_request_lo_hi, mshr_request_lo_lo}; // @[Scheduler.scala:106:25]
wire [1:0] mshr_request_hi_lo_hi = {_mshr_request_T_206, _mshr_request_T_183}; // @[Scheduler.scala:106:25, :113:61]
wire [2:0] mshr_request_hi_lo = {mshr_request_hi_lo_hi, _mshr_request_T_160}; // @[Scheduler.scala:106:25, :113:61]
wire [1:0] mshr_request_hi_hi_hi = {_mshr_request_T_275, _mshr_request_T_252}; // @[Scheduler.scala:106:25, :113:61]
wire [2:0] mshr_request_hi_hi = {mshr_request_hi_hi_hi, _mshr_request_T_229}; // @[Scheduler.scala:106:25, :113:61]
wire [5:0] mshr_request_hi = {mshr_request_hi_hi, mshr_request_hi_lo}; // @[Scheduler.scala:106:25]
wire [11:0] mshr_request = {mshr_request_hi, mshr_request_lo}; // @[Scheduler.scala:106:25]
reg [11:0] robin_filter; // @[Scheduler.scala:118:29]
wire [11:0] _robin_request_T = mshr_request & robin_filter; // @[Scheduler.scala:106:25, :118:29, :119:54]
wire [23:0] robin_request = {mshr_request, _robin_request_T}; // @[Scheduler.scala:106:25, :119:{26,54}]
wire [24:0] _mshr_selectOH2_T = {robin_request, 1'h0}; // @[package.scala:253:48]
wire [23:0] _mshr_selectOH2_T_1 = _mshr_selectOH2_T[23:0]; // @[package.scala:253:{48,53}]
wire [23:0] _mshr_selectOH2_T_2 = robin_request | _mshr_selectOH2_T_1; // @[package.scala:253:{43,53}]
wire [25:0] _mshr_selectOH2_T_3 = {_mshr_selectOH2_T_2, 2'h0}; // @[package.scala:253:{43,48}]
wire [23:0] _mshr_selectOH2_T_4 = _mshr_selectOH2_T_3[23:0]; // @[package.scala:253:{48,53}]
wire [23:0] _mshr_selectOH2_T_5 = _mshr_selectOH2_T_2 | _mshr_selectOH2_T_4; // @[package.scala:253:{43,53}]
wire [27:0] _mshr_selectOH2_T_6 = {_mshr_selectOH2_T_5, 4'h0}; // @[package.scala:253:{43,48}]
wire [23:0] _mshr_selectOH2_T_7 = _mshr_selectOH2_T_6[23:0]; // @[package.scala:253:{48,53}]
wire [23:0] _mshr_selectOH2_T_8 = _mshr_selectOH2_T_5 | _mshr_selectOH2_T_7; // @[package.scala:253:{43,53}]
wire [31:0] _mshr_selectOH2_T_9 = {_mshr_selectOH2_T_8, 8'h0}; // @[package.scala:253:{43,48}]
wire [23:0] _mshr_selectOH2_T_10 = _mshr_selectOH2_T_9[23:0]; // @[package.scala:253:{48,53}]
wire [23:0] _mshr_selectOH2_T_11 = _mshr_selectOH2_T_8 | _mshr_selectOH2_T_10; // @[package.scala:253:{43,53}]
wire [39:0] _mshr_selectOH2_T_12 = {_mshr_selectOH2_T_11, 16'h0}; // @[package.scala:253:{43,48}]
wire [23:0] _mshr_selectOH2_T_13 = _mshr_selectOH2_T_12[23:0]; // @[package.scala:253:{48,53}]
wire [23:0] _mshr_selectOH2_T_14 = _mshr_selectOH2_T_11 | _mshr_selectOH2_T_13; // @[package.scala:253:{43,53}]
wire [23:0] _mshr_selectOH2_T_15 = _mshr_selectOH2_T_14; // @[package.scala:253:43, :254:17]
wire [24:0] _mshr_selectOH2_T_16 = {_mshr_selectOH2_T_15, 1'h0}; // @[package.scala:254:17]
wire [24:0] _mshr_selectOH2_T_17 = ~_mshr_selectOH2_T_16; // @[Scheduler.scala:120:{24,48}]
wire [24:0] mshr_selectOH2 = {1'h0, _mshr_selectOH2_T_17[23:0] & robin_request}; // @[Scheduler.scala:119:26, :120:{24,54}]
wire [11:0] _mshr_selectOH_T = mshr_selectOH2[23:12]; // @[Scheduler.scala:120:54, :121:37]
wire [11:0] _mshr_selectOH_T_1 = mshr_selectOH2[11:0]; // @[Scheduler.scala:120:54, :121:86]
wire [11:0] mshr_selectOH = _mshr_selectOH_T | _mshr_selectOH_T_1; // @[Scheduler.scala:121:{37,70,86}]
wire [3:0] mshr_select_hi = mshr_selectOH[11:8]; // @[OneHot.scala:30:18]
wire [7:0] mshr_select_lo = mshr_selectOH[7:0]; // @[OneHot.scala:31:18]
wire _mshr_select_T = |mshr_select_hi; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _mshr_select_T_1 = {4'h0, mshr_select_hi} | mshr_select_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] mshr_select_hi_1 = _mshr_select_T_1[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] mshr_select_lo_1 = _mshr_select_T_1[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _mshr_select_T_2 = |mshr_select_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _mshr_select_T_3 = mshr_select_hi_1 | mshr_select_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] mshr_select_hi_2 = _mshr_select_T_3[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] mshr_select_lo_2 = _mshr_select_T_3[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _mshr_select_T_4 = |mshr_select_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _mshr_select_T_5 = mshr_select_hi_2 | mshr_select_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _mshr_select_T_6 = _mshr_select_T_5[1]; // @[OneHot.scala:32:28]
wire [1:0] _mshr_select_T_7 = {_mshr_select_T_4, _mshr_select_T_6}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _mshr_select_T_8 = {_mshr_select_T_2, _mshr_select_T_7}; // @[OneHot.scala:32:{10,14}]
wire [3:0] mshr_select = {_mshr_select_T, _mshr_select_T_8}; // @[OneHot.scala:32:{10,14}]
wire [3:0] schedule_a_bits_source = mshr_select; // @[OneHot.scala:32:10]
wire [3:0] schedule_d_bits_sink = mshr_select; // @[OneHot.scala:32:10]
wire _schedule_T = mshr_selectOH[0]; // @[Mux.scala:32:36]
wire _scheduleTag_T = mshr_selectOH[0]; // @[Mux.scala:32:36]
wire _scheduleSet_T = mshr_selectOH[0]; // @[Mux.scala:32:36]
wire sel = mshr_selectOH[0]; // @[Mux.scala:32:36]
wire _schedule_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36]
wire _scheduleTag_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36]
wire _scheduleSet_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36]
wire sel_1 = mshr_selectOH[1]; // @[Mux.scala:32:36]
wire _schedule_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36]
wire _scheduleTag_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36]
wire _scheduleSet_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36]
wire sel_2 = mshr_selectOH[2]; // @[Mux.scala:32:36]
wire _schedule_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36]
wire _scheduleTag_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36]
wire _scheduleSet_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36]
wire sel_3 = mshr_selectOH[3]; // @[Mux.scala:32:36]
wire _schedule_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36]
wire _scheduleTag_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36]
wire _scheduleSet_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36]
wire sel_4 = mshr_selectOH[4]; // @[Mux.scala:32:36]
wire _schedule_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36]
wire _scheduleTag_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36]
wire _scheduleSet_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36]
wire sel_5 = mshr_selectOH[5]; // @[Mux.scala:32:36]
wire _schedule_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36]
wire _scheduleTag_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36]
wire _scheduleSet_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36]
wire sel_6 = mshr_selectOH[6]; // @[Mux.scala:32:36]
wire _schedule_T_7 = mshr_selectOH[7]; // @[Mux.scala:32:36]
wire _scheduleTag_T_7 = mshr_selectOH[7]; // @[Mux.scala:32:36]
wire _scheduleSet_T_7 = mshr_selectOH[7]; // @[Mux.scala:32:36]
wire sel_7 = mshr_selectOH[7]; // @[Mux.scala:32:36]
wire _schedule_T_8 = mshr_selectOH[8]; // @[Mux.scala:32:36]
wire _scheduleTag_T_8 = mshr_selectOH[8]; // @[Mux.scala:32:36]
wire _scheduleSet_T_8 = mshr_selectOH[8]; // @[Mux.scala:32:36]
wire sel_8 = mshr_selectOH[8]; // @[Mux.scala:32:36]
wire _schedule_T_9 = mshr_selectOH[9]; // @[Mux.scala:32:36]
wire _scheduleTag_T_9 = mshr_selectOH[9]; // @[Mux.scala:32:36]
wire _scheduleSet_T_9 = mshr_selectOH[9]; // @[Mux.scala:32:36]
wire sel_9 = mshr_selectOH[9]; // @[Mux.scala:32:36]
wire _schedule_T_10 = mshr_selectOH[10]; // @[Mux.scala:32:36]
wire _scheduleTag_T_10 = mshr_selectOH[10]; // @[Mux.scala:32:36]
wire _scheduleSet_T_10 = mshr_selectOH[10]; // @[Mux.scala:32:36]
wire select_bc = mshr_selectOH[10]; // @[Mux.scala:32:36]
wire sel_10 = mshr_selectOH[10]; // @[Mux.scala:32:36]
wire _schedule_T_11 = mshr_selectOH[11]; // @[Mux.scala:32:36]
wire _scheduleTag_T_11 = mshr_selectOH[11]; // @[Mux.scala:32:36]
wire _scheduleSet_T_11 = mshr_selectOH[11]; // @[Mux.scala:32:36]
wire select_c = mshr_selectOH[11]; // @[Mux.scala:32:36]
wire sel_11 = mshr_selectOH[11]; // @[Mux.scala:32:36]
wire _schedule_WIRE_55_valid; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_55_bits_tag; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_55_bits_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_55_bits_param; // @[Mux.scala:30:73]
wire _schedule_WIRE_55_bits_block; // @[Mux.scala:30:73]
wire _schedule_WIRE_48_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_48_bits_param; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_48_bits_tag; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_48_bits_set; // @[Mux.scala:30:73]
wire _schedule_WIRE_48_bits_clients; // @[Mux.scala:30:73]
wire _schedule_WIRE_38_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_38_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_38_bits_param; // @[Mux.scala:30:73]
wire [3:0] _schedule_c_bits_source_T_1; // @[Scheduler.scala:132:32]
wire [12:0] _schedule_WIRE_38_bits_tag; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_38_bits_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_38_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_38_bits_dirty; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_valid; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_bits_prio_0; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_bits_prio_1; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_bits_prio_2; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_bits_control; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_19_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_19_bits_param; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_19_bits_size; // @[Mux.scala:30:73]
wire [7:0] _schedule_WIRE_19_bits_source; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_19_bits_tag; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_19_bits_offset; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_19_bits_put; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_19_bits_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_19_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_19_bits_bad; // @[Mux.scala:30:73]
wire _schedule_WIRE_15_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_15_bits_sink; // @[Mux.scala:30:73]
wire _schedule_WIRE_11_valid; // @[Mux.scala:30:73]
wire _schedule_WIRE_1_valid; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_1_bits_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_1_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_1_bits_data_dirty; // @[Mux.scala:30:73]
wire [1:0] _schedule_WIRE_1_bits_data_state; // @[Mux.scala:30:73]
wire _schedule_WIRE_1_bits_data_clients; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_1_bits_data_tag; // @[Mux.scala:30:73]
wire _schedule_WIRE; // @[Mux.scala:30:73]
wire [12:0] schedule_a_bits_tag; // @[Mux.scala:30:73]
wire [9:0] schedule_a_bits_set; // @[Mux.scala:30:73]
wire [2:0] schedule_a_bits_param; // @[Mux.scala:30:73]
wire schedule_a_bits_block; // @[Mux.scala:30:73]
wire schedule_a_valid; // @[Mux.scala:30:73]
wire [2:0] schedule_b_bits_param; // @[Mux.scala:30:73]
wire [12:0] schedule_b_bits_tag; // @[Mux.scala:30:73]
wire [9:0] schedule_b_bits_set; // @[Mux.scala:30:73]
wire schedule_b_bits_clients; // @[Mux.scala:30:73]
wire schedule_b_valid; // @[Mux.scala:30:73]
wire [2:0] schedule_c_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] schedule_c_bits_param; // @[Mux.scala:30:73]
wire [3:0] schedule_c_bits_source; // @[Mux.scala:30:73]
wire [12:0] schedule_c_bits_tag; // @[Mux.scala:30:73]
wire [9:0] schedule_c_bits_set; // @[Mux.scala:30:73]
wire [2:0] schedule_c_bits_way; // @[Mux.scala:30:73]
wire schedule_c_bits_dirty; // @[Mux.scala:30:73]
wire schedule_c_valid; // @[Mux.scala:30:73]
wire schedule_d_bits_prio_0; // @[Mux.scala:30:73]
wire schedule_d_bits_prio_1; // @[Mux.scala:30:73]
wire schedule_d_bits_prio_2; // @[Mux.scala:30:73]
wire schedule_d_bits_control; // @[Mux.scala:30:73]
wire [2:0] schedule_d_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] schedule_d_bits_param; // @[Mux.scala:30:73]
wire [2:0] schedule_d_bits_size; // @[Mux.scala:30:73]
wire [7:0] schedule_d_bits_source; // @[Mux.scala:30:73]
wire [12:0] schedule_d_bits_tag; // @[Mux.scala:30:73]
wire [5:0] schedule_d_bits_offset; // @[Mux.scala:30:73]
wire [5:0] schedule_d_bits_put; // @[Mux.scala:30:73]
wire [9:0] schedule_d_bits_set; // @[Mux.scala:30:73]
wire [2:0] schedule_d_bits_way; // @[Mux.scala:30:73]
wire schedule_d_bits_bad; // @[Mux.scala:30:73]
wire schedule_d_valid; // @[Mux.scala:30:73]
wire [2:0] schedule_e_bits_sink; // @[Mux.scala:30:73]
wire schedule_e_valid; // @[Mux.scala:30:73]
wire schedule_x_valid; // @[Mux.scala:30:73]
wire schedule_dir_bits_data_dirty; // @[Mux.scala:30:73]
wire [1:0] schedule_dir_bits_data_state; // @[Mux.scala:30:73]
wire schedule_dir_bits_data_clients; // @[Mux.scala:30:73]
wire [12:0] schedule_dir_bits_data_tag; // @[Mux.scala:30:73]
wire [9:0] schedule_dir_bits_set; // @[Mux.scala:30:73]
wire [2:0] schedule_dir_bits_way; // @[Mux.scala:30:73]
wire schedule_dir_valid; // @[Mux.scala:30:73]
wire schedule_reload; // @[Mux.scala:30:73]
wire _schedule_T_12 = _schedule_T & _mshrs_0_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_13 = _schedule_T_1 & _mshrs_1_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_14 = _schedule_T_2 & _mshrs_2_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_15 = _schedule_T_3 & _mshrs_3_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_16 = _schedule_T_4 & _mshrs_4_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_17 = _schedule_T_5 & _mshrs_5_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_18 = _schedule_T_6 & _mshrs_6_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_19 = _schedule_T_7 & _mshrs_7_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_20 = _schedule_T_8 & _mshrs_8_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_21 = _schedule_T_9 & _mshrs_9_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_22 = _schedule_T_10 & _mshrs_10_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_23 = _schedule_T_11 & _mshrs_11_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_24 = _schedule_T_12 | _schedule_T_13; // @[Mux.scala:30:73]
wire _schedule_T_25 = _schedule_T_24 | _schedule_T_14; // @[Mux.scala:30:73]
wire _schedule_T_26 = _schedule_T_25 | _schedule_T_15; // @[Mux.scala:30:73]
wire _schedule_T_27 = _schedule_T_26 | _schedule_T_16; // @[Mux.scala:30:73]
wire _schedule_T_28 = _schedule_T_27 | _schedule_T_17; // @[Mux.scala:30:73]
wire _schedule_T_29 = _schedule_T_28 | _schedule_T_18; // @[Mux.scala:30:73]
wire _schedule_T_30 = _schedule_T_29 | _schedule_T_19; // @[Mux.scala:30:73]
wire _schedule_T_31 = _schedule_T_30 | _schedule_T_20; // @[Mux.scala:30:73]
wire _schedule_T_32 = _schedule_T_31 | _schedule_T_21; // @[Mux.scala:30:73]
wire _schedule_T_33 = _schedule_T_32 | _schedule_T_22; // @[Mux.scala:30:73]
wire _schedule_T_34 = _schedule_T_33 | _schedule_T_23; // @[Mux.scala:30:73]
assign _schedule_WIRE = _schedule_T_34; // @[Mux.scala:30:73]
assign schedule_reload = _schedule_WIRE; // @[Mux.scala:30:73]
wire _schedule_WIRE_10; // @[Mux.scala:30:73]
assign schedule_dir_valid = _schedule_WIRE_1_valid; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_2_set; // @[Mux.scala:30:73]
assign schedule_dir_bits_set = _schedule_WIRE_1_bits_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_2_way; // @[Mux.scala:30:73]
assign schedule_dir_bits_way = _schedule_WIRE_1_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_2_data_dirty; // @[Mux.scala:30:73]
assign schedule_dir_bits_data_dirty = _schedule_WIRE_1_bits_data_dirty; // @[Mux.scala:30:73]
wire [1:0] _schedule_WIRE_2_data_state; // @[Mux.scala:30:73]
assign schedule_dir_bits_data_state = _schedule_WIRE_1_bits_data_state; // @[Mux.scala:30:73]
wire _schedule_WIRE_2_data_clients; // @[Mux.scala:30:73]
assign schedule_dir_bits_data_clients = _schedule_WIRE_1_bits_data_clients; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_2_data_tag; // @[Mux.scala:30:73]
assign schedule_dir_bits_data_tag = _schedule_WIRE_1_bits_data_tag; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_9; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_set = _schedule_WIRE_2_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_8; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_way = _schedule_WIRE_2_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_3_dirty; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_data_dirty = _schedule_WIRE_2_data_dirty; // @[Mux.scala:30:73]
wire [1:0] _schedule_WIRE_3_state; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_data_state = _schedule_WIRE_2_data_state; // @[Mux.scala:30:73]
wire _schedule_WIRE_3_clients; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_data_clients = _schedule_WIRE_2_data_clients; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_3_tag; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_bits_data_tag = _schedule_WIRE_2_data_tag; // @[Mux.scala:30:73]
wire _schedule_WIRE_7; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_data_dirty = _schedule_WIRE_3_dirty; // @[Mux.scala:30:73]
wire [1:0] _schedule_WIRE_6; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_data_state = _schedule_WIRE_3_state; // @[Mux.scala:30:73]
wire _schedule_WIRE_5; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_data_clients = _schedule_WIRE_3_clients; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_4; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_data_tag = _schedule_WIRE_3_tag; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_35 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_36 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_37 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_38 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_39 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_40 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_41 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_42 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_43 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_44 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_45 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_46 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_dir_bits_data_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_47 = _schedule_T_35 | _schedule_T_36; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_48 = _schedule_T_47 | _schedule_T_37; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_49 = _schedule_T_48 | _schedule_T_38; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_50 = _schedule_T_49 | _schedule_T_39; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_51 = _schedule_T_50 | _schedule_T_40; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_52 = _schedule_T_51 | _schedule_T_41; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_53 = _schedule_T_52 | _schedule_T_42; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_54 = _schedule_T_53 | _schedule_T_43; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_55 = _schedule_T_54 | _schedule_T_44; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_56 = _schedule_T_55 | _schedule_T_45; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_57 = _schedule_T_56 | _schedule_T_46; // @[Mux.scala:30:73]
assign _schedule_WIRE_4 = _schedule_T_57; // @[Mux.scala:30:73]
assign _schedule_WIRE_3_tag = _schedule_WIRE_4; // @[Mux.scala:30:73]
wire _schedule_T_58 = _schedule_T & _mshrs_0_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_59 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_60 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_61 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_62 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_63 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_64 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_65 = _schedule_T_7 & _mshrs_7_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_66 = _schedule_T_8 & _mshrs_8_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_67 = _schedule_T_9 & _mshrs_9_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_68 = _schedule_T_10 & _mshrs_10_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_69 = _schedule_T_11 & _mshrs_11_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_70 = _schedule_T_58 | _schedule_T_59; // @[Mux.scala:30:73]
wire _schedule_T_71 = _schedule_T_70 | _schedule_T_60; // @[Mux.scala:30:73]
wire _schedule_T_72 = _schedule_T_71 | _schedule_T_61; // @[Mux.scala:30:73]
wire _schedule_T_73 = _schedule_T_72 | _schedule_T_62; // @[Mux.scala:30:73]
wire _schedule_T_74 = _schedule_T_73 | _schedule_T_63; // @[Mux.scala:30:73]
wire _schedule_T_75 = _schedule_T_74 | _schedule_T_64; // @[Mux.scala:30:73]
wire _schedule_T_76 = _schedule_T_75 | _schedule_T_65; // @[Mux.scala:30:73]
wire _schedule_T_77 = _schedule_T_76 | _schedule_T_66; // @[Mux.scala:30:73]
wire _schedule_T_78 = _schedule_T_77 | _schedule_T_67; // @[Mux.scala:30:73]
wire _schedule_T_79 = _schedule_T_78 | _schedule_T_68; // @[Mux.scala:30:73]
wire _schedule_T_80 = _schedule_T_79 | _schedule_T_69; // @[Mux.scala:30:73]
assign _schedule_WIRE_5 = _schedule_T_80; // @[Mux.scala:30:73]
assign _schedule_WIRE_3_clients = _schedule_WIRE_5; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_81 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_82 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_83 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_84 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_85 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_86 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_87 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_88 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_89 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_90 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_91 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_92 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36]
wire [1:0] _schedule_T_93 = _schedule_T_81 | _schedule_T_82; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_94 = _schedule_T_93 | _schedule_T_83; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_95 = _schedule_T_94 | _schedule_T_84; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_96 = _schedule_T_95 | _schedule_T_85; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_97 = _schedule_T_96 | _schedule_T_86; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_98 = _schedule_T_97 | _schedule_T_87; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_99 = _schedule_T_98 | _schedule_T_88; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_100 = _schedule_T_99 | _schedule_T_89; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_101 = _schedule_T_100 | _schedule_T_90; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_102 = _schedule_T_101 | _schedule_T_91; // @[Mux.scala:30:73]
wire [1:0] _schedule_T_103 = _schedule_T_102 | _schedule_T_92; // @[Mux.scala:30:73]
assign _schedule_WIRE_6 = _schedule_T_103; // @[Mux.scala:30:73]
assign _schedule_WIRE_3_state = _schedule_WIRE_6; // @[Mux.scala:30:73]
wire _schedule_T_104 = _schedule_T & _mshrs_0_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_105 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_106 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_107 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_108 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_109 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_110 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_111 = _schedule_T_7 & _mshrs_7_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_112 = _schedule_T_8 & _mshrs_8_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_113 = _schedule_T_9 & _mshrs_9_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_114 = _schedule_T_10 & _mshrs_10_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_115 = _schedule_T_11 & _mshrs_11_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_116 = _schedule_T_104 | _schedule_T_105; // @[Mux.scala:30:73]
wire _schedule_T_117 = _schedule_T_116 | _schedule_T_106; // @[Mux.scala:30:73]
wire _schedule_T_118 = _schedule_T_117 | _schedule_T_107; // @[Mux.scala:30:73]
wire _schedule_T_119 = _schedule_T_118 | _schedule_T_108; // @[Mux.scala:30:73]
wire _schedule_T_120 = _schedule_T_119 | _schedule_T_109; // @[Mux.scala:30:73]
wire _schedule_T_121 = _schedule_T_120 | _schedule_T_110; // @[Mux.scala:30:73]
wire _schedule_T_122 = _schedule_T_121 | _schedule_T_111; // @[Mux.scala:30:73]
wire _schedule_T_123 = _schedule_T_122 | _schedule_T_112; // @[Mux.scala:30:73]
wire _schedule_T_124 = _schedule_T_123 | _schedule_T_113; // @[Mux.scala:30:73]
wire _schedule_T_125 = _schedule_T_124 | _schedule_T_114; // @[Mux.scala:30:73]
wire _schedule_T_126 = _schedule_T_125 | _schedule_T_115; // @[Mux.scala:30:73]
assign _schedule_WIRE_7 = _schedule_T_126; // @[Mux.scala:30:73]
assign _schedule_WIRE_3_dirty = _schedule_WIRE_7; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_127 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_128 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_129 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_130 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_131 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_132 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_133 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_134 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_135 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_136 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_137 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_138 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_dir_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_139 = _schedule_T_127 | _schedule_T_128; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_140 = _schedule_T_139 | _schedule_T_129; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_141 = _schedule_T_140 | _schedule_T_130; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_142 = _schedule_T_141 | _schedule_T_131; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_143 = _schedule_T_142 | _schedule_T_132; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_144 = _schedule_T_143 | _schedule_T_133; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_145 = _schedule_T_144 | _schedule_T_134; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_146 = _schedule_T_145 | _schedule_T_135; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_147 = _schedule_T_146 | _schedule_T_136; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_148 = _schedule_T_147 | _schedule_T_137; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_149 = _schedule_T_148 | _schedule_T_138; // @[Mux.scala:30:73]
assign _schedule_WIRE_8 = _schedule_T_149; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_way = _schedule_WIRE_8; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_150 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_151 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_152 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_153 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_154 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_155 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_156 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_157 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_158 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_159 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_160 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_161 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_dir_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_162 = _schedule_T_150 | _schedule_T_151; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_163 = _schedule_T_162 | _schedule_T_152; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_164 = _schedule_T_163 | _schedule_T_153; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_165 = _schedule_T_164 | _schedule_T_154; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_166 = _schedule_T_165 | _schedule_T_155; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_167 = _schedule_T_166 | _schedule_T_156; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_168 = _schedule_T_167 | _schedule_T_157; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_169 = _schedule_T_168 | _schedule_T_158; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_170 = _schedule_T_169 | _schedule_T_159; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_171 = _schedule_T_170 | _schedule_T_160; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_172 = _schedule_T_171 | _schedule_T_161; // @[Mux.scala:30:73]
assign _schedule_WIRE_9 = _schedule_T_172; // @[Mux.scala:30:73]
assign _schedule_WIRE_2_set = _schedule_WIRE_9; // @[Mux.scala:30:73]
wire _schedule_T_173 = _schedule_T & _mshrs_0_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_174 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_175 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_176 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_177 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_178 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_179 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_180 = _schedule_T_7 & _mshrs_7_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_181 = _schedule_T_8 & _mshrs_8_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_182 = _schedule_T_9 & _mshrs_9_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_183 = _schedule_T_10 & _mshrs_10_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_184 = _schedule_T_11 & _mshrs_11_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_185 = _schedule_T_173 | _schedule_T_174; // @[Mux.scala:30:73]
wire _schedule_T_186 = _schedule_T_185 | _schedule_T_175; // @[Mux.scala:30:73]
wire _schedule_T_187 = _schedule_T_186 | _schedule_T_176; // @[Mux.scala:30:73]
wire _schedule_T_188 = _schedule_T_187 | _schedule_T_177; // @[Mux.scala:30:73]
wire _schedule_T_189 = _schedule_T_188 | _schedule_T_178; // @[Mux.scala:30:73]
wire _schedule_T_190 = _schedule_T_189 | _schedule_T_179; // @[Mux.scala:30:73]
wire _schedule_T_191 = _schedule_T_190 | _schedule_T_180; // @[Mux.scala:30:73]
wire _schedule_T_192 = _schedule_T_191 | _schedule_T_181; // @[Mux.scala:30:73]
wire _schedule_T_193 = _schedule_T_192 | _schedule_T_182; // @[Mux.scala:30:73]
wire _schedule_T_194 = _schedule_T_193 | _schedule_T_183; // @[Mux.scala:30:73]
wire _schedule_T_195 = _schedule_T_194 | _schedule_T_184; // @[Mux.scala:30:73]
assign _schedule_WIRE_10 = _schedule_T_195; // @[Mux.scala:30:73]
assign _schedule_WIRE_1_valid = _schedule_WIRE_10; // @[Mux.scala:30:73]
wire _schedule_WIRE_14; // @[Mux.scala:30:73]
assign schedule_x_valid = _schedule_WIRE_11_valid; // @[Mux.scala:30:73]
wire _schedule_T_219 = _schedule_T & _mshrs_0_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_220 = _schedule_T_1 & _mshrs_1_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_221 = _schedule_T_2 & _mshrs_2_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_222 = _schedule_T_3 & _mshrs_3_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_223 = _schedule_T_4 & _mshrs_4_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_224 = _schedule_T_5 & _mshrs_5_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_225 = _schedule_T_6 & _mshrs_6_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_226 = _schedule_T_7 & _mshrs_7_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_227 = _schedule_T_8 & _mshrs_8_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_228 = _schedule_T_9 & _mshrs_9_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_229 = _schedule_T_10 & _mshrs_10_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_230 = _schedule_T_11 & _mshrs_11_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_231 = _schedule_T_219 | _schedule_T_220; // @[Mux.scala:30:73]
wire _schedule_T_232 = _schedule_T_231 | _schedule_T_221; // @[Mux.scala:30:73]
wire _schedule_T_233 = _schedule_T_232 | _schedule_T_222; // @[Mux.scala:30:73]
wire _schedule_T_234 = _schedule_T_233 | _schedule_T_223; // @[Mux.scala:30:73]
wire _schedule_T_235 = _schedule_T_234 | _schedule_T_224; // @[Mux.scala:30:73]
wire _schedule_T_236 = _schedule_T_235 | _schedule_T_225; // @[Mux.scala:30:73]
wire _schedule_T_237 = _schedule_T_236 | _schedule_T_226; // @[Mux.scala:30:73]
wire _schedule_T_238 = _schedule_T_237 | _schedule_T_227; // @[Mux.scala:30:73]
wire _schedule_T_239 = _schedule_T_238 | _schedule_T_228; // @[Mux.scala:30:73]
wire _schedule_T_240 = _schedule_T_239 | _schedule_T_229; // @[Mux.scala:30:73]
wire _schedule_T_241 = _schedule_T_240 | _schedule_T_230; // @[Mux.scala:30:73]
assign _schedule_WIRE_14 = _schedule_T_241; // @[Mux.scala:30:73]
assign _schedule_WIRE_11_valid = _schedule_WIRE_14; // @[Mux.scala:30:73]
wire _schedule_WIRE_18; // @[Mux.scala:30:73]
assign schedule_e_valid = _schedule_WIRE_15_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_16_sink; // @[Mux.scala:30:73]
assign schedule_e_bits_sink = _schedule_WIRE_15_bits_sink; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_17; // @[Mux.scala:30:73]
assign _schedule_WIRE_15_bits_sink = _schedule_WIRE_16_sink; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_242 = _schedule_T ? _mshrs_0_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_243 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_244 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_245 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_246 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_247 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_248 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_249 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_250 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_251 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_252 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_253 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_254 = _schedule_T_242 | _schedule_T_243; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_255 = _schedule_T_254 | _schedule_T_244; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_256 = _schedule_T_255 | _schedule_T_245; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_257 = _schedule_T_256 | _schedule_T_246; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_258 = _schedule_T_257 | _schedule_T_247; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_259 = _schedule_T_258 | _schedule_T_248; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_260 = _schedule_T_259 | _schedule_T_249; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_261 = _schedule_T_260 | _schedule_T_250; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_262 = _schedule_T_261 | _schedule_T_251; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_263 = _schedule_T_262 | _schedule_T_252; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_264 = _schedule_T_263 | _schedule_T_253; // @[Mux.scala:30:73]
assign _schedule_WIRE_17 = _schedule_T_264; // @[Mux.scala:30:73]
assign _schedule_WIRE_16_sink = _schedule_WIRE_17; // @[Mux.scala:30:73]
wire _schedule_T_265 = _schedule_T & _mshrs_0_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_266 = _schedule_T_1 & _mshrs_1_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_267 = _schedule_T_2 & _mshrs_2_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_268 = _schedule_T_3 & _mshrs_3_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_269 = _schedule_T_4 & _mshrs_4_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_270 = _schedule_T_5 & _mshrs_5_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_271 = _schedule_T_6 & _mshrs_6_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_272 = _schedule_T_7 & _mshrs_7_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_273 = _schedule_T_8 & _mshrs_8_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_274 = _schedule_T_9 & _mshrs_9_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_275 = _schedule_T_10 & _mshrs_10_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_276 = _schedule_T_11 & _mshrs_11_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_277 = _schedule_T_265 | _schedule_T_266; // @[Mux.scala:30:73]
wire _schedule_T_278 = _schedule_T_277 | _schedule_T_267; // @[Mux.scala:30:73]
wire _schedule_T_279 = _schedule_T_278 | _schedule_T_268; // @[Mux.scala:30:73]
wire _schedule_T_280 = _schedule_T_279 | _schedule_T_269; // @[Mux.scala:30:73]
wire _schedule_T_281 = _schedule_T_280 | _schedule_T_270; // @[Mux.scala:30:73]
wire _schedule_T_282 = _schedule_T_281 | _schedule_T_271; // @[Mux.scala:30:73]
wire _schedule_T_283 = _schedule_T_282 | _schedule_T_272; // @[Mux.scala:30:73]
wire _schedule_T_284 = _schedule_T_283 | _schedule_T_273; // @[Mux.scala:30:73]
wire _schedule_T_285 = _schedule_T_284 | _schedule_T_274; // @[Mux.scala:30:73]
wire _schedule_T_286 = _schedule_T_285 | _schedule_T_275; // @[Mux.scala:30:73]
wire _schedule_T_287 = _schedule_T_286 | _schedule_T_276; // @[Mux.scala:30:73]
assign _schedule_WIRE_18 = _schedule_T_287; // @[Mux.scala:30:73]
assign _schedule_WIRE_15_valid = _schedule_WIRE_18; // @[Mux.scala:30:73]
wire _schedule_WIRE_37; // @[Mux.scala:30:73]
assign schedule_d_valid = _schedule_WIRE_19_valid; // @[Mux.scala:30:73]
wire _schedule_WIRE_20_prio_0; // @[Mux.scala:30:73]
assign schedule_d_bits_prio_0 = _schedule_WIRE_19_bits_prio_0; // @[Mux.scala:30:73]
wire _schedule_WIRE_20_prio_1; // @[Mux.scala:30:73]
assign schedule_d_bits_prio_1 = _schedule_WIRE_19_bits_prio_1; // @[Mux.scala:30:73]
wire _schedule_WIRE_20_prio_2; // @[Mux.scala:30:73]
assign schedule_d_bits_prio_2 = _schedule_WIRE_19_bits_prio_2; // @[Mux.scala:30:73]
wire _schedule_WIRE_20_control; // @[Mux.scala:30:73]
assign schedule_d_bits_control = _schedule_WIRE_19_bits_control; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_20_opcode; // @[Mux.scala:30:73]
assign schedule_d_bits_opcode = _schedule_WIRE_19_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_20_param; // @[Mux.scala:30:73]
assign schedule_d_bits_param = _schedule_WIRE_19_bits_param; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_20_size; // @[Mux.scala:30:73]
assign schedule_d_bits_size = _schedule_WIRE_19_bits_size; // @[Mux.scala:30:73]
wire [7:0] _schedule_WIRE_20_source; // @[Mux.scala:30:73]
assign schedule_d_bits_source = _schedule_WIRE_19_bits_source; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_20_tag; // @[Mux.scala:30:73]
assign schedule_d_bits_tag = _schedule_WIRE_19_bits_tag; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_20_offset; // @[Mux.scala:30:73]
assign schedule_d_bits_offset = _schedule_WIRE_19_bits_offset; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_20_put; // @[Mux.scala:30:73]
assign schedule_d_bits_put = _schedule_WIRE_19_bits_put; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_20_set; // @[Mux.scala:30:73]
assign schedule_d_bits_set = _schedule_WIRE_19_bits_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_20_way; // @[Mux.scala:30:73]
assign schedule_d_bits_way = _schedule_WIRE_19_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_20_bad; // @[Mux.scala:30:73]
assign schedule_d_bits_bad = _schedule_WIRE_19_bits_bad; // @[Mux.scala:30:73]
wire _schedule_WIRE_33_0; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_prio_0 = _schedule_WIRE_20_prio_0; // @[Mux.scala:30:73]
wire _schedule_WIRE_33_1; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_prio_1 = _schedule_WIRE_20_prio_1; // @[Mux.scala:30:73]
wire _schedule_WIRE_33_2; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_prio_2 = _schedule_WIRE_20_prio_2; // @[Mux.scala:30:73]
wire _schedule_WIRE_32; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_control = _schedule_WIRE_20_control; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_31; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_opcode = _schedule_WIRE_20_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_30; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_param = _schedule_WIRE_20_param; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_29; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_size = _schedule_WIRE_20_size; // @[Mux.scala:30:73]
wire [7:0] _schedule_WIRE_28; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_source = _schedule_WIRE_20_source; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_27; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_tag = _schedule_WIRE_20_tag; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_26; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_offset = _schedule_WIRE_20_offset; // @[Mux.scala:30:73]
wire [5:0] _schedule_WIRE_25; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_put = _schedule_WIRE_20_put; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_24; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_set = _schedule_WIRE_20_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_22; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_way = _schedule_WIRE_20_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_21; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_bits_bad = _schedule_WIRE_20_bad; // @[Mux.scala:30:73]
wire _schedule_T_288 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_289 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_290 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_291 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_292 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_293 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_294 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_295 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_296 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_297 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_298 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_299 = _schedule_T_11 & _mshrs_11_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_300 = _schedule_T_288 | _schedule_T_289; // @[Mux.scala:30:73]
wire _schedule_T_301 = _schedule_T_300 | _schedule_T_290; // @[Mux.scala:30:73]
wire _schedule_T_302 = _schedule_T_301 | _schedule_T_291; // @[Mux.scala:30:73]
wire _schedule_T_303 = _schedule_T_302 | _schedule_T_292; // @[Mux.scala:30:73]
wire _schedule_T_304 = _schedule_T_303 | _schedule_T_293; // @[Mux.scala:30:73]
wire _schedule_T_305 = _schedule_T_304 | _schedule_T_294; // @[Mux.scala:30:73]
wire _schedule_T_306 = _schedule_T_305 | _schedule_T_295; // @[Mux.scala:30:73]
wire _schedule_T_307 = _schedule_T_306 | _schedule_T_296; // @[Mux.scala:30:73]
wire _schedule_T_308 = _schedule_T_307 | _schedule_T_297; // @[Mux.scala:30:73]
wire _schedule_T_309 = _schedule_T_308 | _schedule_T_298; // @[Mux.scala:30:73]
wire _schedule_T_310 = _schedule_T_309 | _schedule_T_299; // @[Mux.scala:30:73]
assign _schedule_WIRE_21 = _schedule_T_310; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_bad = _schedule_WIRE_21; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_311 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_312 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_313 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_314 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_315 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_316 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_317 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_318 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_319 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_320 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_321 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_322 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_323 = _schedule_T_311 | _schedule_T_312; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_324 = _schedule_T_323 | _schedule_T_313; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_325 = _schedule_T_324 | _schedule_T_314; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_326 = _schedule_T_325 | _schedule_T_315; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_327 = _schedule_T_326 | _schedule_T_316; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_328 = _schedule_T_327 | _schedule_T_317; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_329 = _schedule_T_328 | _schedule_T_318; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_330 = _schedule_T_329 | _schedule_T_319; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_331 = _schedule_T_330 | _schedule_T_320; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_332 = _schedule_T_331 | _schedule_T_321; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_333 = _schedule_T_332 | _schedule_T_322; // @[Mux.scala:30:73]
assign _schedule_WIRE_22 = _schedule_T_333; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_way = _schedule_WIRE_22; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_357 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_358 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_359 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_360 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_361 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_362 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_363 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_364 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_365 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_366 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_367 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_368 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_369 = _schedule_T_357 | _schedule_T_358; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_370 = _schedule_T_369 | _schedule_T_359; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_371 = _schedule_T_370 | _schedule_T_360; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_372 = _schedule_T_371 | _schedule_T_361; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_373 = _schedule_T_372 | _schedule_T_362; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_374 = _schedule_T_373 | _schedule_T_363; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_375 = _schedule_T_374 | _schedule_T_364; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_376 = _schedule_T_375 | _schedule_T_365; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_377 = _schedule_T_376 | _schedule_T_366; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_378 = _schedule_T_377 | _schedule_T_367; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_379 = _schedule_T_378 | _schedule_T_368; // @[Mux.scala:30:73]
assign _schedule_WIRE_24 = _schedule_T_379; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_set = _schedule_WIRE_24; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_380 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_381 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_382 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_383 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_384 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_385 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_386 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_387 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_388 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_389 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_390 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_391 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_392 = _schedule_T_380 | _schedule_T_381; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_393 = _schedule_T_392 | _schedule_T_382; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_394 = _schedule_T_393 | _schedule_T_383; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_395 = _schedule_T_394 | _schedule_T_384; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_396 = _schedule_T_395 | _schedule_T_385; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_397 = _schedule_T_396 | _schedule_T_386; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_398 = _schedule_T_397 | _schedule_T_387; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_399 = _schedule_T_398 | _schedule_T_388; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_400 = _schedule_T_399 | _schedule_T_389; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_401 = _schedule_T_400 | _schedule_T_390; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_402 = _schedule_T_401 | _schedule_T_391; // @[Mux.scala:30:73]
assign _schedule_WIRE_25 = _schedule_T_402; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_put = _schedule_WIRE_25; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_403 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_404 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_405 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_406 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_407 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_408 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_409 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_410 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_411 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_412 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_413 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_414 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36]
wire [5:0] _schedule_T_415 = _schedule_T_403 | _schedule_T_404; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_416 = _schedule_T_415 | _schedule_T_405; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_417 = _schedule_T_416 | _schedule_T_406; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_418 = _schedule_T_417 | _schedule_T_407; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_419 = _schedule_T_418 | _schedule_T_408; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_420 = _schedule_T_419 | _schedule_T_409; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_421 = _schedule_T_420 | _schedule_T_410; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_422 = _schedule_T_421 | _schedule_T_411; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_423 = _schedule_T_422 | _schedule_T_412; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_424 = _schedule_T_423 | _schedule_T_413; // @[Mux.scala:30:73]
wire [5:0] _schedule_T_425 = _schedule_T_424 | _schedule_T_414; // @[Mux.scala:30:73]
assign _schedule_WIRE_26 = _schedule_T_425; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_offset = _schedule_WIRE_26; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_426 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_427 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_428 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_429 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_430 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_431 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_432 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_433 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_434 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_435 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_436 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_437 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_438 = _schedule_T_426 | _schedule_T_427; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_439 = _schedule_T_438 | _schedule_T_428; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_440 = _schedule_T_439 | _schedule_T_429; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_441 = _schedule_T_440 | _schedule_T_430; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_442 = _schedule_T_441 | _schedule_T_431; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_443 = _schedule_T_442 | _schedule_T_432; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_444 = _schedule_T_443 | _schedule_T_433; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_445 = _schedule_T_444 | _schedule_T_434; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_446 = _schedule_T_445 | _schedule_T_435; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_447 = _schedule_T_446 | _schedule_T_436; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_448 = _schedule_T_447 | _schedule_T_437; // @[Mux.scala:30:73]
assign _schedule_WIRE_27 = _schedule_T_448; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_tag = _schedule_WIRE_27; // @[Mux.scala:30:73]
wire [7:0] _schedule_T_449 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_source : 8'h0; // @[Mux.scala:30:73, :32:36]
wire [7:0] _schedule_T_450 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_source : 8'h0; // @[Mux.scala:30:73, :32:36]
wire [7:0] _schedule_T_451 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_source : 8'h0; // @[Mux.scala:30:73, :32:36]
wire [7:0] _schedule_T_452 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_source : 8'h0; // @[Mux.scala:30:73, :32:36]
wire [7:0] _schedule_T_453 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_source : 8'h0; // @[Mux.scala:30:73, :32:36]
wire [7:0] _schedule_T_454 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_source : 8'h0; // @[Mux.scala:30:73, :32:36]
wire [7:0] _schedule_T_455 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_source : 8'h0; // @[Mux.scala:30:73, :32:36]
wire [7:0] _schedule_T_456 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_source : 8'h0; // @[Mux.scala:30:73, :32:36]
wire [7:0] _schedule_T_457 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_source : 8'h0; // @[Mux.scala:30:73, :32:36]
wire [7:0] _schedule_T_458 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_source : 8'h0; // @[Mux.scala:30:73, :32:36]
wire [7:0] _schedule_T_459 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_source : 8'h0; // @[Mux.scala:30:73, :32:36]
wire [7:0] _schedule_T_460 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_source : 8'h0; // @[Mux.scala:30:73, :32:36]
wire [7:0] _schedule_T_461 = _schedule_T_449 | _schedule_T_450; // @[Mux.scala:30:73]
wire [7:0] _schedule_T_462 = _schedule_T_461 | _schedule_T_451; // @[Mux.scala:30:73]
wire [7:0] _schedule_T_463 = _schedule_T_462 | _schedule_T_452; // @[Mux.scala:30:73]
wire [7:0] _schedule_T_464 = _schedule_T_463 | _schedule_T_453; // @[Mux.scala:30:73]
wire [7:0] _schedule_T_465 = _schedule_T_464 | _schedule_T_454; // @[Mux.scala:30:73]
wire [7:0] _schedule_T_466 = _schedule_T_465 | _schedule_T_455; // @[Mux.scala:30:73]
wire [7:0] _schedule_T_467 = _schedule_T_466 | _schedule_T_456; // @[Mux.scala:30:73]
wire [7:0] _schedule_T_468 = _schedule_T_467 | _schedule_T_457; // @[Mux.scala:30:73]
wire [7:0] _schedule_T_469 = _schedule_T_468 | _schedule_T_458; // @[Mux.scala:30:73]
wire [7:0] _schedule_T_470 = _schedule_T_469 | _schedule_T_459; // @[Mux.scala:30:73]
wire [7:0] _schedule_T_471 = _schedule_T_470 | _schedule_T_460; // @[Mux.scala:30:73]
assign _schedule_WIRE_28 = _schedule_T_471; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_source = _schedule_WIRE_28; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_472 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_473 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_474 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_475 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_476 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_477 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_478 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_479 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_480 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_481 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_482 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_483 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_484 = _schedule_T_472 | _schedule_T_473; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_485 = _schedule_T_484 | _schedule_T_474; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_486 = _schedule_T_485 | _schedule_T_475; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_487 = _schedule_T_486 | _schedule_T_476; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_488 = _schedule_T_487 | _schedule_T_477; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_489 = _schedule_T_488 | _schedule_T_478; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_490 = _schedule_T_489 | _schedule_T_479; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_491 = _schedule_T_490 | _schedule_T_480; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_492 = _schedule_T_491 | _schedule_T_481; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_493 = _schedule_T_492 | _schedule_T_482; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_494 = _schedule_T_493 | _schedule_T_483; // @[Mux.scala:30:73]
assign _schedule_WIRE_29 = _schedule_T_494; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_size = _schedule_WIRE_29; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_495 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_496 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_497 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_498 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_499 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_500 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_501 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_502 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_503 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_504 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_505 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_506 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_507 = _schedule_T_495 | _schedule_T_496; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_508 = _schedule_T_507 | _schedule_T_497; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_509 = _schedule_T_508 | _schedule_T_498; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_510 = _schedule_T_509 | _schedule_T_499; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_511 = _schedule_T_510 | _schedule_T_500; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_512 = _schedule_T_511 | _schedule_T_501; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_513 = _schedule_T_512 | _schedule_T_502; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_514 = _schedule_T_513 | _schedule_T_503; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_515 = _schedule_T_514 | _schedule_T_504; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_516 = _schedule_T_515 | _schedule_T_505; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_517 = _schedule_T_516 | _schedule_T_506; // @[Mux.scala:30:73]
assign _schedule_WIRE_30 = _schedule_T_517; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_param = _schedule_WIRE_30; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_518 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_519 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_520 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_521 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_522 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_523 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_524 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_525 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_526 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_527 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_528 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_529 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_530 = _schedule_T_518 | _schedule_T_519; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_531 = _schedule_T_530 | _schedule_T_520; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_532 = _schedule_T_531 | _schedule_T_521; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_533 = _schedule_T_532 | _schedule_T_522; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_534 = _schedule_T_533 | _schedule_T_523; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_535 = _schedule_T_534 | _schedule_T_524; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_536 = _schedule_T_535 | _schedule_T_525; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_537 = _schedule_T_536 | _schedule_T_526; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_538 = _schedule_T_537 | _schedule_T_527; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_539 = _schedule_T_538 | _schedule_T_528; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_540 = _schedule_T_539 | _schedule_T_529; // @[Mux.scala:30:73]
assign _schedule_WIRE_31 = _schedule_T_540; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_opcode = _schedule_WIRE_31; // @[Mux.scala:30:73]
wire _schedule_T_541 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_542 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_543 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_544 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_545 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_546 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_547 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_548 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_549 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_550 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_551 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_552 = _schedule_T_11 & _mshrs_11_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_553 = _schedule_T_541 | _schedule_T_542; // @[Mux.scala:30:73]
wire _schedule_T_554 = _schedule_T_553 | _schedule_T_543; // @[Mux.scala:30:73]
wire _schedule_T_555 = _schedule_T_554 | _schedule_T_544; // @[Mux.scala:30:73]
wire _schedule_T_556 = _schedule_T_555 | _schedule_T_545; // @[Mux.scala:30:73]
wire _schedule_T_557 = _schedule_T_556 | _schedule_T_546; // @[Mux.scala:30:73]
wire _schedule_T_558 = _schedule_T_557 | _schedule_T_547; // @[Mux.scala:30:73]
wire _schedule_T_559 = _schedule_T_558 | _schedule_T_548; // @[Mux.scala:30:73]
wire _schedule_T_560 = _schedule_T_559 | _schedule_T_549; // @[Mux.scala:30:73]
wire _schedule_T_561 = _schedule_T_560 | _schedule_T_550; // @[Mux.scala:30:73]
wire _schedule_T_562 = _schedule_T_561 | _schedule_T_551; // @[Mux.scala:30:73]
wire _schedule_T_563 = _schedule_T_562 | _schedule_T_552; // @[Mux.scala:30:73]
assign _schedule_WIRE_32 = _schedule_T_563; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_control = _schedule_WIRE_32; // @[Mux.scala:30:73]
wire _schedule_WIRE_34; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_prio_0 = _schedule_WIRE_33_0; // @[Mux.scala:30:73]
wire _schedule_WIRE_35; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_prio_1 = _schedule_WIRE_33_1; // @[Mux.scala:30:73]
wire _schedule_WIRE_36; // @[Mux.scala:30:73]
assign _schedule_WIRE_20_prio_2 = _schedule_WIRE_33_2; // @[Mux.scala:30:73]
wire _schedule_T_564 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_565 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_566 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_567 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_568 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_569 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_570 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_571 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_572 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_573 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_576 = _schedule_T_564 | _schedule_T_565; // @[Mux.scala:30:73]
wire _schedule_T_577 = _schedule_T_576 | _schedule_T_566; // @[Mux.scala:30:73]
wire _schedule_T_578 = _schedule_T_577 | _schedule_T_567; // @[Mux.scala:30:73]
wire _schedule_T_579 = _schedule_T_578 | _schedule_T_568; // @[Mux.scala:30:73]
wire _schedule_T_580 = _schedule_T_579 | _schedule_T_569; // @[Mux.scala:30:73]
wire _schedule_T_581 = _schedule_T_580 | _schedule_T_570; // @[Mux.scala:30:73]
wire _schedule_T_582 = _schedule_T_581 | _schedule_T_571; // @[Mux.scala:30:73]
wire _schedule_T_583 = _schedule_T_582 | _schedule_T_572; // @[Mux.scala:30:73]
wire _schedule_T_584 = _schedule_T_583 | _schedule_T_573; // @[Mux.scala:30:73]
wire _schedule_T_585 = _schedule_T_584; // @[Mux.scala:30:73]
wire _schedule_T_586 = _schedule_T_585; // @[Mux.scala:30:73]
assign _schedule_WIRE_34 = _schedule_T_586; // @[Mux.scala:30:73]
assign _schedule_WIRE_33_0 = _schedule_WIRE_34; // @[Mux.scala:30:73]
wire _schedule_T_587 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_588 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_589 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_590 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_591 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_592 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_593 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_594 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_595 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_596 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_597 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_599 = _schedule_T_587 | _schedule_T_588; // @[Mux.scala:30:73]
wire _schedule_T_600 = _schedule_T_599 | _schedule_T_589; // @[Mux.scala:30:73]
wire _schedule_T_601 = _schedule_T_600 | _schedule_T_590; // @[Mux.scala:30:73]
wire _schedule_T_602 = _schedule_T_601 | _schedule_T_591; // @[Mux.scala:30:73]
wire _schedule_T_603 = _schedule_T_602 | _schedule_T_592; // @[Mux.scala:30:73]
wire _schedule_T_604 = _schedule_T_603 | _schedule_T_593; // @[Mux.scala:30:73]
wire _schedule_T_605 = _schedule_T_604 | _schedule_T_594; // @[Mux.scala:30:73]
wire _schedule_T_606 = _schedule_T_605 | _schedule_T_595; // @[Mux.scala:30:73]
wire _schedule_T_607 = _schedule_T_606 | _schedule_T_596; // @[Mux.scala:30:73]
wire _schedule_T_608 = _schedule_T_607 | _schedule_T_597; // @[Mux.scala:30:73]
wire _schedule_T_609 = _schedule_T_608; // @[Mux.scala:30:73]
assign _schedule_WIRE_35 = _schedule_T_609; // @[Mux.scala:30:73]
assign _schedule_WIRE_33_1 = _schedule_WIRE_35; // @[Mux.scala:30:73]
wire _schedule_T_610 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_611 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_612 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_613 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_614 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_615 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_616 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_617 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_618 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_619 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_620 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_621 = _schedule_T_11 & _mshrs_11_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_622 = _schedule_T_610 | _schedule_T_611; // @[Mux.scala:30:73]
wire _schedule_T_623 = _schedule_T_622 | _schedule_T_612; // @[Mux.scala:30:73]
wire _schedule_T_624 = _schedule_T_623 | _schedule_T_613; // @[Mux.scala:30:73]
wire _schedule_T_625 = _schedule_T_624 | _schedule_T_614; // @[Mux.scala:30:73]
wire _schedule_T_626 = _schedule_T_625 | _schedule_T_615; // @[Mux.scala:30:73]
wire _schedule_T_627 = _schedule_T_626 | _schedule_T_616; // @[Mux.scala:30:73]
wire _schedule_T_628 = _schedule_T_627 | _schedule_T_617; // @[Mux.scala:30:73]
wire _schedule_T_629 = _schedule_T_628 | _schedule_T_618; // @[Mux.scala:30:73]
wire _schedule_T_630 = _schedule_T_629 | _schedule_T_619; // @[Mux.scala:30:73]
wire _schedule_T_631 = _schedule_T_630 | _schedule_T_620; // @[Mux.scala:30:73]
wire _schedule_T_632 = _schedule_T_631 | _schedule_T_621; // @[Mux.scala:30:73]
assign _schedule_WIRE_36 = _schedule_T_632; // @[Mux.scala:30:73]
assign _schedule_WIRE_33_2 = _schedule_WIRE_36; // @[Mux.scala:30:73]
wire _schedule_T_633 = _schedule_T & _mshrs_0_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_634 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_635 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_636 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_637 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_638 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_639 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_640 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_641 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_642 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_643 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_644 = _schedule_T_11 & _mshrs_11_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_645 = _schedule_T_633 | _schedule_T_634; // @[Mux.scala:30:73]
wire _schedule_T_646 = _schedule_T_645 | _schedule_T_635; // @[Mux.scala:30:73]
wire _schedule_T_647 = _schedule_T_646 | _schedule_T_636; // @[Mux.scala:30:73]
wire _schedule_T_648 = _schedule_T_647 | _schedule_T_637; // @[Mux.scala:30:73]
wire _schedule_T_649 = _schedule_T_648 | _schedule_T_638; // @[Mux.scala:30:73]
wire _schedule_T_650 = _schedule_T_649 | _schedule_T_639; // @[Mux.scala:30:73]
wire _schedule_T_651 = _schedule_T_650 | _schedule_T_640; // @[Mux.scala:30:73]
wire _schedule_T_652 = _schedule_T_651 | _schedule_T_641; // @[Mux.scala:30:73]
wire _schedule_T_653 = _schedule_T_652 | _schedule_T_642; // @[Mux.scala:30:73]
wire _schedule_T_654 = _schedule_T_653 | _schedule_T_643; // @[Mux.scala:30:73]
wire _schedule_T_655 = _schedule_T_654 | _schedule_T_644; // @[Mux.scala:30:73]
assign _schedule_WIRE_37 = _schedule_T_655; // @[Mux.scala:30:73]
assign _schedule_WIRE_19_valid = _schedule_WIRE_37; // @[Mux.scala:30:73]
wire _schedule_WIRE_47; // @[Mux.scala:30:73]
assign schedule_c_valid = _schedule_WIRE_38_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_39_opcode; // @[Mux.scala:30:73]
assign schedule_c_bits_opcode = _schedule_WIRE_38_bits_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_39_param; // @[Mux.scala:30:73]
assign schedule_c_bits_param = _schedule_WIRE_38_bits_param; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_39_tag; // @[Mux.scala:30:73]
assign schedule_c_bits_tag = _schedule_WIRE_38_bits_tag; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_39_set; // @[Mux.scala:30:73]
assign schedule_c_bits_set = _schedule_WIRE_38_bits_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_39_way; // @[Mux.scala:30:73]
assign schedule_c_bits_way = _schedule_WIRE_38_bits_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_39_dirty; // @[Mux.scala:30:73]
assign schedule_c_bits_dirty = _schedule_WIRE_38_bits_dirty; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_46; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_opcode = _schedule_WIRE_39_opcode; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_45; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_param = _schedule_WIRE_39_param; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_43; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_tag = _schedule_WIRE_39_tag; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_42; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_set = _schedule_WIRE_39_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_41; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_way = _schedule_WIRE_39_way; // @[Mux.scala:30:73]
wire _schedule_WIRE_40; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_bits_dirty = _schedule_WIRE_39_dirty; // @[Mux.scala:30:73]
wire _schedule_T_656 = _schedule_T & _mshrs_0_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_657 = _schedule_T_1 & _mshrs_1_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_658 = _schedule_T_2 & _mshrs_2_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_659 = _schedule_T_3 & _mshrs_3_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_660 = _schedule_T_4 & _mshrs_4_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_661 = _schedule_T_5 & _mshrs_5_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_662 = _schedule_T_6 & _mshrs_6_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_663 = _schedule_T_7 & _mshrs_7_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_664 = _schedule_T_8 & _mshrs_8_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_665 = _schedule_T_9 & _mshrs_9_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_666 = _schedule_T_10 & _mshrs_10_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_667 = _schedule_T_11 & _mshrs_11_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_668 = _schedule_T_656 | _schedule_T_657; // @[Mux.scala:30:73]
wire _schedule_T_669 = _schedule_T_668 | _schedule_T_658; // @[Mux.scala:30:73]
wire _schedule_T_670 = _schedule_T_669 | _schedule_T_659; // @[Mux.scala:30:73]
wire _schedule_T_671 = _schedule_T_670 | _schedule_T_660; // @[Mux.scala:30:73]
wire _schedule_T_672 = _schedule_T_671 | _schedule_T_661; // @[Mux.scala:30:73]
wire _schedule_T_673 = _schedule_T_672 | _schedule_T_662; // @[Mux.scala:30:73]
wire _schedule_T_674 = _schedule_T_673 | _schedule_T_663; // @[Mux.scala:30:73]
wire _schedule_T_675 = _schedule_T_674 | _schedule_T_664; // @[Mux.scala:30:73]
wire _schedule_T_676 = _schedule_T_675 | _schedule_T_665; // @[Mux.scala:30:73]
wire _schedule_T_677 = _schedule_T_676 | _schedule_T_666; // @[Mux.scala:30:73]
wire _schedule_T_678 = _schedule_T_677 | _schedule_T_667; // @[Mux.scala:30:73]
assign _schedule_WIRE_40 = _schedule_T_678; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_dirty = _schedule_WIRE_40; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_679 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_680 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_681 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_682 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_683 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_684 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_685 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_686 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_687 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_688 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_689 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_690 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_way : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_691 = _schedule_T_679 | _schedule_T_680; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_692 = _schedule_T_691 | _schedule_T_681; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_693 = _schedule_T_692 | _schedule_T_682; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_694 = _schedule_T_693 | _schedule_T_683; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_695 = _schedule_T_694 | _schedule_T_684; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_696 = _schedule_T_695 | _schedule_T_685; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_697 = _schedule_T_696 | _schedule_T_686; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_698 = _schedule_T_697 | _schedule_T_687; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_699 = _schedule_T_698 | _schedule_T_688; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_700 = _schedule_T_699 | _schedule_T_689; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_701 = _schedule_T_700 | _schedule_T_690; // @[Mux.scala:30:73]
assign _schedule_WIRE_41 = _schedule_T_701; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_way = _schedule_WIRE_41; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_702 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_703 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_704 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_705 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_706 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_707 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_708 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_709 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_710 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_711 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_712 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_713 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_714 = _schedule_T_702 | _schedule_T_703; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_715 = _schedule_T_714 | _schedule_T_704; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_716 = _schedule_T_715 | _schedule_T_705; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_717 = _schedule_T_716 | _schedule_T_706; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_718 = _schedule_T_717 | _schedule_T_707; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_719 = _schedule_T_718 | _schedule_T_708; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_720 = _schedule_T_719 | _schedule_T_709; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_721 = _schedule_T_720 | _schedule_T_710; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_722 = _schedule_T_721 | _schedule_T_711; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_723 = _schedule_T_722 | _schedule_T_712; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_724 = _schedule_T_723 | _schedule_T_713; // @[Mux.scala:30:73]
assign _schedule_WIRE_42 = _schedule_T_724; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_set = _schedule_WIRE_42; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_725 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_726 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_727 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_728 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_729 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_730 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_731 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_732 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_733 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_734 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_735 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_736 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_737 = _schedule_T_725 | _schedule_T_726; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_738 = _schedule_T_737 | _schedule_T_727; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_739 = _schedule_T_738 | _schedule_T_728; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_740 = _schedule_T_739 | _schedule_T_729; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_741 = _schedule_T_740 | _schedule_T_730; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_742 = _schedule_T_741 | _schedule_T_731; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_743 = _schedule_T_742 | _schedule_T_732; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_744 = _schedule_T_743 | _schedule_T_733; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_745 = _schedule_T_744 | _schedule_T_734; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_746 = _schedule_T_745 | _schedule_T_735; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_747 = _schedule_T_746 | _schedule_T_736; // @[Mux.scala:30:73]
assign _schedule_WIRE_43 = _schedule_T_747; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_tag = _schedule_WIRE_43; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_771 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_772 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_773 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_774 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_775 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_776 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_777 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_778 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_779 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_780 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_781 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_782 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_783 = _schedule_T_771 | _schedule_T_772; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_784 = _schedule_T_783 | _schedule_T_773; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_785 = _schedule_T_784 | _schedule_T_774; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_786 = _schedule_T_785 | _schedule_T_775; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_787 = _schedule_T_786 | _schedule_T_776; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_788 = _schedule_T_787 | _schedule_T_777; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_789 = _schedule_T_788 | _schedule_T_778; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_790 = _schedule_T_789 | _schedule_T_779; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_791 = _schedule_T_790 | _schedule_T_780; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_792 = _schedule_T_791 | _schedule_T_781; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_793 = _schedule_T_792 | _schedule_T_782; // @[Mux.scala:30:73]
assign _schedule_WIRE_45 = _schedule_T_793; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_param = _schedule_WIRE_45; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_794 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_795 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_796 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_797 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_798 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_799 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_800 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_801 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_802 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_803 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_804 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_805 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_806 = _schedule_T_794 | _schedule_T_795; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_807 = _schedule_T_806 | _schedule_T_796; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_808 = _schedule_T_807 | _schedule_T_797; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_809 = _schedule_T_808 | _schedule_T_798; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_810 = _schedule_T_809 | _schedule_T_799; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_811 = _schedule_T_810 | _schedule_T_800; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_812 = _schedule_T_811 | _schedule_T_801; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_813 = _schedule_T_812 | _schedule_T_802; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_814 = _schedule_T_813 | _schedule_T_803; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_815 = _schedule_T_814 | _schedule_T_804; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_816 = _schedule_T_815 | _schedule_T_805; // @[Mux.scala:30:73]
assign _schedule_WIRE_46 = _schedule_T_816; // @[Mux.scala:30:73]
assign _schedule_WIRE_39_opcode = _schedule_WIRE_46; // @[Mux.scala:30:73]
wire _schedule_T_817 = _schedule_T & _mshrs_0_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_818 = _schedule_T_1 & _mshrs_1_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_819 = _schedule_T_2 & _mshrs_2_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_820 = _schedule_T_3 & _mshrs_3_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_821 = _schedule_T_4 & _mshrs_4_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_822 = _schedule_T_5 & _mshrs_5_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_823 = _schedule_T_6 & _mshrs_6_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_824 = _schedule_T_7 & _mshrs_7_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_825 = _schedule_T_8 & _mshrs_8_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_826 = _schedule_T_9 & _mshrs_9_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_827 = _schedule_T_10 & _mshrs_10_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_828 = _schedule_T_11 & _mshrs_11_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_829 = _schedule_T_817 | _schedule_T_818; // @[Mux.scala:30:73]
wire _schedule_T_830 = _schedule_T_829 | _schedule_T_819; // @[Mux.scala:30:73]
wire _schedule_T_831 = _schedule_T_830 | _schedule_T_820; // @[Mux.scala:30:73]
wire _schedule_T_832 = _schedule_T_831 | _schedule_T_821; // @[Mux.scala:30:73]
wire _schedule_T_833 = _schedule_T_832 | _schedule_T_822; // @[Mux.scala:30:73]
wire _schedule_T_834 = _schedule_T_833 | _schedule_T_823; // @[Mux.scala:30:73]
wire _schedule_T_835 = _schedule_T_834 | _schedule_T_824; // @[Mux.scala:30:73]
wire _schedule_T_836 = _schedule_T_835 | _schedule_T_825; // @[Mux.scala:30:73]
wire _schedule_T_837 = _schedule_T_836 | _schedule_T_826; // @[Mux.scala:30:73]
wire _schedule_T_838 = _schedule_T_837 | _schedule_T_827; // @[Mux.scala:30:73]
wire _schedule_T_839 = _schedule_T_838 | _schedule_T_828; // @[Mux.scala:30:73]
assign _schedule_WIRE_47 = _schedule_T_839; // @[Mux.scala:30:73]
assign _schedule_WIRE_38_valid = _schedule_WIRE_47; // @[Mux.scala:30:73]
wire _schedule_WIRE_54; // @[Mux.scala:30:73]
assign schedule_b_valid = _schedule_WIRE_48_valid; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_49_param; // @[Mux.scala:30:73]
assign schedule_b_bits_param = _schedule_WIRE_48_bits_param; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_49_tag; // @[Mux.scala:30:73]
assign schedule_b_bits_tag = _schedule_WIRE_48_bits_tag; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_49_set; // @[Mux.scala:30:73]
assign schedule_b_bits_set = _schedule_WIRE_48_bits_set; // @[Mux.scala:30:73]
wire _schedule_WIRE_49_clients; // @[Mux.scala:30:73]
assign schedule_b_bits_clients = _schedule_WIRE_48_bits_clients; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_53; // @[Mux.scala:30:73]
assign _schedule_WIRE_48_bits_param = _schedule_WIRE_49_param; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_52; // @[Mux.scala:30:73]
assign _schedule_WIRE_48_bits_tag = _schedule_WIRE_49_tag; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_51; // @[Mux.scala:30:73]
assign _schedule_WIRE_48_bits_set = _schedule_WIRE_49_set; // @[Mux.scala:30:73]
wire _schedule_WIRE_50; // @[Mux.scala:30:73]
assign _schedule_WIRE_48_bits_clients = _schedule_WIRE_49_clients; // @[Mux.scala:30:73]
wire _schedule_T_840 = _schedule_T & _mshrs_0_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_841 = _schedule_T_1 & _mshrs_1_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_842 = _schedule_T_2 & _mshrs_2_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_843 = _schedule_T_3 & _mshrs_3_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_844 = _schedule_T_4 & _mshrs_4_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_845 = _schedule_T_5 & _mshrs_5_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_846 = _schedule_T_6 & _mshrs_6_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_847 = _schedule_T_7 & _mshrs_7_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_848 = _schedule_T_8 & _mshrs_8_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_849 = _schedule_T_9 & _mshrs_9_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_850 = _schedule_T_10 & _mshrs_10_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_851 = _schedule_T_11 & _mshrs_11_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_852 = _schedule_T_840 | _schedule_T_841; // @[Mux.scala:30:73]
wire _schedule_T_853 = _schedule_T_852 | _schedule_T_842; // @[Mux.scala:30:73]
wire _schedule_T_854 = _schedule_T_853 | _schedule_T_843; // @[Mux.scala:30:73]
wire _schedule_T_855 = _schedule_T_854 | _schedule_T_844; // @[Mux.scala:30:73]
wire _schedule_T_856 = _schedule_T_855 | _schedule_T_845; // @[Mux.scala:30:73]
wire _schedule_T_857 = _schedule_T_856 | _schedule_T_846; // @[Mux.scala:30:73]
wire _schedule_T_858 = _schedule_T_857 | _schedule_T_847; // @[Mux.scala:30:73]
wire _schedule_T_859 = _schedule_T_858 | _schedule_T_848; // @[Mux.scala:30:73]
wire _schedule_T_860 = _schedule_T_859 | _schedule_T_849; // @[Mux.scala:30:73]
wire _schedule_T_861 = _schedule_T_860 | _schedule_T_850; // @[Mux.scala:30:73]
wire _schedule_T_862 = _schedule_T_861 | _schedule_T_851; // @[Mux.scala:30:73]
assign _schedule_WIRE_50 = _schedule_T_862; // @[Mux.scala:30:73]
assign _schedule_WIRE_49_clients = _schedule_WIRE_50; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_863 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_864 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_865 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_866 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_867 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_868 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_869 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_870 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_871 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_872 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_873 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_874 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_b_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_875 = _schedule_T_863 | _schedule_T_864; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_876 = _schedule_T_875 | _schedule_T_865; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_877 = _schedule_T_876 | _schedule_T_866; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_878 = _schedule_T_877 | _schedule_T_867; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_879 = _schedule_T_878 | _schedule_T_868; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_880 = _schedule_T_879 | _schedule_T_869; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_881 = _schedule_T_880 | _schedule_T_870; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_882 = _schedule_T_881 | _schedule_T_871; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_883 = _schedule_T_882 | _schedule_T_872; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_884 = _schedule_T_883 | _schedule_T_873; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_885 = _schedule_T_884 | _schedule_T_874; // @[Mux.scala:30:73]
assign _schedule_WIRE_51 = _schedule_T_885; // @[Mux.scala:30:73]
assign _schedule_WIRE_49_set = _schedule_WIRE_51; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_886 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_887 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_888 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_889 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_890 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_891 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_892 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_893 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_894 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_895 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_896 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_897 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_b_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_898 = _schedule_T_886 | _schedule_T_887; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_899 = _schedule_T_898 | _schedule_T_888; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_900 = _schedule_T_899 | _schedule_T_889; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_901 = _schedule_T_900 | _schedule_T_890; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_902 = _schedule_T_901 | _schedule_T_891; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_903 = _schedule_T_902 | _schedule_T_892; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_904 = _schedule_T_903 | _schedule_T_893; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_905 = _schedule_T_904 | _schedule_T_894; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_906 = _schedule_T_905 | _schedule_T_895; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_907 = _schedule_T_906 | _schedule_T_896; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_908 = _schedule_T_907 | _schedule_T_897; // @[Mux.scala:30:73]
assign _schedule_WIRE_52 = _schedule_T_908; // @[Mux.scala:30:73]
assign _schedule_WIRE_49_tag = _schedule_WIRE_52; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_909 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_910 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_911 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_912 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_913 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_914 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_915 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_916 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_917 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_918 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_919 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_920 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_921 = _schedule_T_909 | _schedule_T_910; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_922 = _schedule_T_921 | _schedule_T_911; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_923 = _schedule_T_922 | _schedule_T_912; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_924 = _schedule_T_923 | _schedule_T_913; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_925 = _schedule_T_924 | _schedule_T_914; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_926 = _schedule_T_925 | _schedule_T_915; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_927 = _schedule_T_926 | _schedule_T_916; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_928 = _schedule_T_927 | _schedule_T_917; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_929 = _schedule_T_928 | _schedule_T_918; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_930 = _schedule_T_929 | _schedule_T_919; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_931 = _schedule_T_930 | _schedule_T_920; // @[Mux.scala:30:73]
assign _schedule_WIRE_53 = _schedule_T_931; // @[Mux.scala:30:73]
assign _schedule_WIRE_49_param = _schedule_WIRE_53; // @[Mux.scala:30:73]
wire _schedule_T_932 = _schedule_T & _mshrs_0_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_933 = _schedule_T_1 & _mshrs_1_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_934 = _schedule_T_2 & _mshrs_2_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_935 = _schedule_T_3 & _mshrs_3_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_936 = _schedule_T_4 & _mshrs_4_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_937 = _schedule_T_5 & _mshrs_5_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_938 = _schedule_T_6 & _mshrs_6_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_939 = _schedule_T_7 & _mshrs_7_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_940 = _schedule_T_8 & _mshrs_8_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_941 = _schedule_T_9 & _mshrs_9_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_942 = _schedule_T_10 & _mshrs_10_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_943 = _schedule_T_11 & _mshrs_11_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_944 = _schedule_T_932 | _schedule_T_933; // @[Mux.scala:30:73]
wire _schedule_T_945 = _schedule_T_944 | _schedule_T_934; // @[Mux.scala:30:73]
wire _schedule_T_946 = _schedule_T_945 | _schedule_T_935; // @[Mux.scala:30:73]
wire _schedule_T_947 = _schedule_T_946 | _schedule_T_936; // @[Mux.scala:30:73]
wire _schedule_T_948 = _schedule_T_947 | _schedule_T_937; // @[Mux.scala:30:73]
wire _schedule_T_949 = _schedule_T_948 | _schedule_T_938; // @[Mux.scala:30:73]
wire _schedule_T_950 = _schedule_T_949 | _schedule_T_939; // @[Mux.scala:30:73]
wire _schedule_T_951 = _schedule_T_950 | _schedule_T_940; // @[Mux.scala:30:73]
wire _schedule_T_952 = _schedule_T_951 | _schedule_T_941; // @[Mux.scala:30:73]
wire _schedule_T_953 = _schedule_T_952 | _schedule_T_942; // @[Mux.scala:30:73]
wire _schedule_T_954 = _schedule_T_953 | _schedule_T_943; // @[Mux.scala:30:73]
assign _schedule_WIRE_54 = _schedule_T_954; // @[Mux.scala:30:73]
assign _schedule_WIRE_48_valid = _schedule_WIRE_54; // @[Mux.scala:30:73]
wire _schedule_WIRE_62; // @[Mux.scala:30:73]
assign schedule_a_valid = _schedule_WIRE_55_valid; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_56_tag; // @[Mux.scala:30:73]
assign schedule_a_bits_tag = _schedule_WIRE_55_bits_tag; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_56_set; // @[Mux.scala:30:73]
assign schedule_a_bits_set = _schedule_WIRE_55_bits_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_56_param; // @[Mux.scala:30:73]
assign schedule_a_bits_param = _schedule_WIRE_55_bits_param; // @[Mux.scala:30:73]
wire _schedule_WIRE_56_block; // @[Mux.scala:30:73]
assign schedule_a_bits_block = _schedule_WIRE_55_bits_block; // @[Mux.scala:30:73]
wire [12:0] _schedule_WIRE_61; // @[Mux.scala:30:73]
assign _schedule_WIRE_55_bits_tag = _schedule_WIRE_56_tag; // @[Mux.scala:30:73]
wire [9:0] _schedule_WIRE_60; // @[Mux.scala:30:73]
assign _schedule_WIRE_55_bits_set = _schedule_WIRE_56_set; // @[Mux.scala:30:73]
wire [2:0] _schedule_WIRE_59; // @[Mux.scala:30:73]
assign _schedule_WIRE_55_bits_param = _schedule_WIRE_56_param; // @[Mux.scala:30:73]
wire _schedule_WIRE_57; // @[Mux.scala:30:73]
assign _schedule_WIRE_55_bits_block = _schedule_WIRE_56_block; // @[Mux.scala:30:73]
wire _schedule_T_955 = _schedule_T & _mshrs_0_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_956 = _schedule_T_1 & _mshrs_1_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_957 = _schedule_T_2 & _mshrs_2_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_958 = _schedule_T_3 & _mshrs_3_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_959 = _schedule_T_4 & _mshrs_4_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_960 = _schedule_T_5 & _mshrs_5_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_961 = _schedule_T_6 & _mshrs_6_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_962 = _schedule_T_7 & _mshrs_7_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_963 = _schedule_T_8 & _mshrs_8_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_964 = _schedule_T_9 & _mshrs_9_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_965 = _schedule_T_10 & _mshrs_10_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_966 = _schedule_T_11 & _mshrs_11_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_967 = _schedule_T_955 | _schedule_T_956; // @[Mux.scala:30:73]
wire _schedule_T_968 = _schedule_T_967 | _schedule_T_957; // @[Mux.scala:30:73]
wire _schedule_T_969 = _schedule_T_968 | _schedule_T_958; // @[Mux.scala:30:73]
wire _schedule_T_970 = _schedule_T_969 | _schedule_T_959; // @[Mux.scala:30:73]
wire _schedule_T_971 = _schedule_T_970 | _schedule_T_960; // @[Mux.scala:30:73]
wire _schedule_T_972 = _schedule_T_971 | _schedule_T_961; // @[Mux.scala:30:73]
wire _schedule_T_973 = _schedule_T_972 | _schedule_T_962; // @[Mux.scala:30:73]
wire _schedule_T_974 = _schedule_T_973 | _schedule_T_963; // @[Mux.scala:30:73]
wire _schedule_T_975 = _schedule_T_974 | _schedule_T_964; // @[Mux.scala:30:73]
wire _schedule_T_976 = _schedule_T_975 | _schedule_T_965; // @[Mux.scala:30:73]
wire _schedule_T_977 = _schedule_T_976 | _schedule_T_966; // @[Mux.scala:30:73]
assign _schedule_WIRE_57 = _schedule_T_977; // @[Mux.scala:30:73]
assign _schedule_WIRE_56_block = _schedule_WIRE_57; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1001 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1002 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1003 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1004 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1005 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1006 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1007 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1008 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1009 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1010 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1011 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1012 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36]
wire [2:0] _schedule_T_1013 = _schedule_T_1001 | _schedule_T_1002; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1014 = _schedule_T_1013 | _schedule_T_1003; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1015 = _schedule_T_1014 | _schedule_T_1004; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1016 = _schedule_T_1015 | _schedule_T_1005; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1017 = _schedule_T_1016 | _schedule_T_1006; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1018 = _schedule_T_1017 | _schedule_T_1007; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1019 = _schedule_T_1018 | _schedule_T_1008; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1020 = _schedule_T_1019 | _schedule_T_1009; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1021 = _schedule_T_1020 | _schedule_T_1010; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1022 = _schedule_T_1021 | _schedule_T_1011; // @[Mux.scala:30:73]
wire [2:0] _schedule_T_1023 = _schedule_T_1022 | _schedule_T_1012; // @[Mux.scala:30:73]
assign _schedule_WIRE_59 = _schedule_T_1023; // @[Mux.scala:30:73]
assign _schedule_WIRE_56_param = _schedule_WIRE_59; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_1024 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_1025 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_1026 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_1027 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_1028 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_1029 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_1030 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_1031 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_1032 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_1033 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_1034 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_1035 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_a_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _schedule_T_1036 = _schedule_T_1024 | _schedule_T_1025; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_1037 = _schedule_T_1036 | _schedule_T_1026; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_1038 = _schedule_T_1037 | _schedule_T_1027; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_1039 = _schedule_T_1038 | _schedule_T_1028; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_1040 = _schedule_T_1039 | _schedule_T_1029; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_1041 = _schedule_T_1040 | _schedule_T_1030; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_1042 = _schedule_T_1041 | _schedule_T_1031; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_1043 = _schedule_T_1042 | _schedule_T_1032; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_1044 = _schedule_T_1043 | _schedule_T_1033; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_1045 = _schedule_T_1044 | _schedule_T_1034; // @[Mux.scala:30:73]
wire [9:0] _schedule_T_1046 = _schedule_T_1045 | _schedule_T_1035; // @[Mux.scala:30:73]
assign _schedule_WIRE_60 = _schedule_T_1046; // @[Mux.scala:30:73]
assign _schedule_WIRE_56_set = _schedule_WIRE_60; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_1047 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_1048 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_1049 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_1050 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_1051 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_1052 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_1053 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_1054 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_1055 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_1056 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_1057 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_1058 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_a_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _schedule_T_1059 = _schedule_T_1047 | _schedule_T_1048; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_1060 = _schedule_T_1059 | _schedule_T_1049; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_1061 = _schedule_T_1060 | _schedule_T_1050; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_1062 = _schedule_T_1061 | _schedule_T_1051; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_1063 = _schedule_T_1062 | _schedule_T_1052; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_1064 = _schedule_T_1063 | _schedule_T_1053; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_1065 = _schedule_T_1064 | _schedule_T_1054; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_1066 = _schedule_T_1065 | _schedule_T_1055; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_1067 = _schedule_T_1066 | _schedule_T_1056; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_1068 = _schedule_T_1067 | _schedule_T_1057; // @[Mux.scala:30:73]
wire [12:0] _schedule_T_1069 = _schedule_T_1068 | _schedule_T_1058; // @[Mux.scala:30:73]
assign _schedule_WIRE_61 = _schedule_T_1069; // @[Mux.scala:30:73]
assign _schedule_WIRE_56_tag = _schedule_WIRE_61; // @[Mux.scala:30:73]
wire _schedule_T_1070 = _schedule_T & _mshrs_0_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1071 = _schedule_T_1 & _mshrs_1_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1072 = _schedule_T_2 & _mshrs_2_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1073 = _schedule_T_3 & _mshrs_3_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1074 = _schedule_T_4 & _mshrs_4_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1075 = _schedule_T_5 & _mshrs_5_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1076 = _schedule_T_6 & _mshrs_6_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1077 = _schedule_T_7 & _mshrs_7_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1078 = _schedule_T_8 & _mshrs_8_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1079 = _schedule_T_9 & _mshrs_9_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1080 = _schedule_T_10 & _mshrs_10_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1081 = _schedule_T_11 & _mshrs_11_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36]
wire _schedule_T_1082 = _schedule_T_1070 | _schedule_T_1071; // @[Mux.scala:30:73]
wire _schedule_T_1083 = _schedule_T_1082 | _schedule_T_1072; // @[Mux.scala:30:73]
wire _schedule_T_1084 = _schedule_T_1083 | _schedule_T_1073; // @[Mux.scala:30:73]
wire _schedule_T_1085 = _schedule_T_1084 | _schedule_T_1074; // @[Mux.scala:30:73]
wire _schedule_T_1086 = _schedule_T_1085 | _schedule_T_1075; // @[Mux.scala:30:73]
wire _schedule_T_1087 = _schedule_T_1086 | _schedule_T_1076; // @[Mux.scala:30:73]
wire _schedule_T_1088 = _schedule_T_1087 | _schedule_T_1077; // @[Mux.scala:30:73]
wire _schedule_T_1089 = _schedule_T_1088 | _schedule_T_1078; // @[Mux.scala:30:73]
wire _schedule_T_1090 = _schedule_T_1089 | _schedule_T_1079; // @[Mux.scala:30:73]
wire _schedule_T_1091 = _schedule_T_1090 | _schedule_T_1080; // @[Mux.scala:30:73]
wire _schedule_T_1092 = _schedule_T_1091 | _schedule_T_1081; // @[Mux.scala:30:73]
assign _schedule_WIRE_62 = _schedule_T_1092; // @[Mux.scala:30:73]
assign _schedule_WIRE_55_valid = _schedule_WIRE_62; // @[Mux.scala:30:73]
wire [12:0] _scheduleTag_T_12 = _scheduleTag_T ? _mshrs_0_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _scheduleTag_T_13 = _scheduleTag_T_1 ? _mshrs_1_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _scheduleTag_T_14 = _scheduleTag_T_2 ? _mshrs_2_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _scheduleTag_T_15 = _scheduleTag_T_3 ? _mshrs_3_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _scheduleTag_T_16 = _scheduleTag_T_4 ? _mshrs_4_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _scheduleTag_T_17 = _scheduleTag_T_5 ? _mshrs_5_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _scheduleTag_T_18 = _scheduleTag_T_6 ? _mshrs_6_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _scheduleTag_T_19 = _scheduleTag_T_7 ? _mshrs_7_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _scheduleTag_T_20 = _scheduleTag_T_8 ? _mshrs_8_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _scheduleTag_T_21 = _scheduleTag_T_9 ? _mshrs_9_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _scheduleTag_T_22 = _scheduleTag_T_10 ? _mshrs_10_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _scheduleTag_T_23 = _scheduleTag_T_11 ? _mshrs_11_io_status_bits_tag : 13'h0; // @[Mux.scala:30:73, :32:36]
wire [12:0] _scheduleTag_T_24 = _scheduleTag_T_12 | _scheduleTag_T_13; // @[Mux.scala:30:73]
wire [12:0] _scheduleTag_T_25 = _scheduleTag_T_24 | _scheduleTag_T_14; // @[Mux.scala:30:73]
wire [12:0] _scheduleTag_T_26 = _scheduleTag_T_25 | _scheduleTag_T_15; // @[Mux.scala:30:73]
wire [12:0] _scheduleTag_T_27 = _scheduleTag_T_26 | _scheduleTag_T_16; // @[Mux.scala:30:73]
wire [12:0] _scheduleTag_T_28 = _scheduleTag_T_27 | _scheduleTag_T_17; // @[Mux.scala:30:73]
wire [12:0] _scheduleTag_T_29 = _scheduleTag_T_28 | _scheduleTag_T_18; // @[Mux.scala:30:73]
wire [12:0] _scheduleTag_T_30 = _scheduleTag_T_29 | _scheduleTag_T_19; // @[Mux.scala:30:73]
wire [12:0] _scheduleTag_T_31 = _scheduleTag_T_30 | _scheduleTag_T_20; // @[Mux.scala:30:73]
wire [12:0] _scheduleTag_T_32 = _scheduleTag_T_31 | _scheduleTag_T_21; // @[Mux.scala:30:73]
wire [12:0] _scheduleTag_T_33 = _scheduleTag_T_32 | _scheduleTag_T_22; // @[Mux.scala:30:73]
wire [12:0] _scheduleTag_T_34 = _scheduleTag_T_33 | _scheduleTag_T_23; // @[Mux.scala:30:73]
wire [12:0] scheduleTag = _scheduleTag_T_34; // @[Mux.scala:30:73]
wire [9:0] _scheduleSet_T_12 = _scheduleSet_T ? _mshrs_0_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _scheduleSet_T_13 = _scheduleSet_T_1 ? _mshrs_1_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _scheduleSet_T_14 = _scheduleSet_T_2 ? _mshrs_2_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _scheduleSet_T_15 = _scheduleSet_T_3 ? _mshrs_3_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _scheduleSet_T_16 = _scheduleSet_T_4 ? _mshrs_4_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _scheduleSet_T_17 = _scheduleSet_T_5 ? _mshrs_5_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _scheduleSet_T_18 = _scheduleSet_T_6 ? _mshrs_6_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _scheduleSet_T_19 = _scheduleSet_T_7 ? _mshrs_7_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _scheduleSet_T_20 = _scheduleSet_T_8 ? _mshrs_8_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _scheduleSet_T_21 = _scheduleSet_T_9 ? _mshrs_9_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _scheduleSet_T_22 = _scheduleSet_T_10 ? _mshrs_10_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _scheduleSet_T_23 = _scheduleSet_T_11 ? _mshrs_11_io_status_bits_set : 10'h0; // @[Mux.scala:30:73, :32:36]
wire [9:0] _scheduleSet_T_24 = _scheduleSet_T_12 | _scheduleSet_T_13; // @[Mux.scala:30:73]
wire [9:0] _scheduleSet_T_25 = _scheduleSet_T_24 | _scheduleSet_T_14; // @[Mux.scala:30:73]
wire [9:0] _scheduleSet_T_26 = _scheduleSet_T_25 | _scheduleSet_T_15; // @[Mux.scala:30:73]
wire [9:0] _scheduleSet_T_27 = _scheduleSet_T_26 | _scheduleSet_T_16; // @[Mux.scala:30:73]
wire [9:0] _scheduleSet_T_28 = _scheduleSet_T_27 | _scheduleSet_T_17; // @[Mux.scala:30:73]
wire [9:0] _scheduleSet_T_29 = _scheduleSet_T_28 | _scheduleSet_T_18; // @[Mux.scala:30:73]
wire [9:0] _scheduleSet_T_30 = _scheduleSet_T_29 | _scheduleSet_T_19; // @[Mux.scala:30:73]
wire [9:0] _scheduleSet_T_31 = _scheduleSet_T_30 | _scheduleSet_T_20; // @[Mux.scala:30:73]
wire [9:0] _scheduleSet_T_32 = _scheduleSet_T_31 | _scheduleSet_T_21; // @[Mux.scala:30:73]
wire [9:0] _scheduleSet_T_33 = _scheduleSet_T_32 | _scheduleSet_T_22; // @[Mux.scala:30:73]
wire [9:0] _scheduleSet_T_34 = _scheduleSet_T_33 | _scheduleSet_T_23; // @[Mux.scala:30:73]
wire [9:0] scheduleSet = _scheduleSet_T_34; // @[Mux.scala:30:73]
wire [10:0] _robin_filter_T = mshr_selectOH[11:1]; // @[package.scala:262:48]
wire [11:0] _robin_filter_T_1 = {mshr_selectOH[11], mshr_selectOH[10:0] | _robin_filter_T}; // @[Mux.scala:32:36]
wire [9:0] _robin_filter_T_2 = _robin_filter_T_1[11:2]; // @[package.scala:262:{43,48}]
wire [11:0] _robin_filter_T_3 = {_robin_filter_T_1[11:10], _robin_filter_T_1[9:0] | _robin_filter_T_2}; // @[package.scala:262:{43,48}]
wire [7:0] _robin_filter_T_4 = _robin_filter_T_3[11:4]; // @[package.scala:262:{43,48}]
wire [11:0] _robin_filter_T_5 = {_robin_filter_T_3[11:8], _robin_filter_T_3[7:0] | _robin_filter_T_4}; // @[package.scala:262:{43,48}]
wire [3:0] _robin_filter_T_6 = _robin_filter_T_5[11:8]; // @[package.scala:262:{43,48}]
wire [11:0] _robin_filter_T_7 = {_robin_filter_T_5[11:4], _robin_filter_T_5[3:0] | _robin_filter_T_6}; // @[package.scala:262:{43,48}]
wire [11:0] _robin_filter_T_8 = _robin_filter_T_7; // @[package.scala:262:43, :263:17]
wire [11:0] _robin_filter_T_9 = ~_robin_filter_T_8; // @[package.scala:263:17]
wire _schedule_c_bits_source_T = schedule_c_bits_opcode[1]; // @[Mux.scala:30:73]
assign _schedule_c_bits_source_T_1 = _schedule_c_bits_source_T ? mshr_select : 4'h0; // @[OneHot.scala:32:10]
assign schedule_c_bits_source = _schedule_c_bits_source_T_1; // @[Mux.scala:30:73]
assign _nestedwb_set_T = select_c ? _mshrs_11_io_status_bits_set : _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :153:32, :155:24]
assign nestedwb_set = _nestedwb_set_T; // @[Scheduler.scala:75:22, :155:24]
assign _nestedwb_tag_T = select_c ? _mshrs_11_io_status_bits_tag : _mshrs_10_io_status_bits_tag; // @[Scheduler.scala:71:46, :153:32, :156:24]
assign nestedwb_tag = _nestedwb_tag_T; // @[Scheduler.scala:75:22, :156:24]
wire _GEN = select_bc & _mshrs_10_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :154:32, :157:37]
wire _nestedwb_b_toN_T; // @[Scheduler.scala:157:37]
assign _nestedwb_b_toN_T = _GEN; // @[Scheduler.scala:157:37]
wire _nestedwb_b_toB_T; // @[Scheduler.scala:158:37]
assign _nestedwb_b_toB_T = _GEN; // @[Scheduler.scala:157:37, :158:37]
assign _nestedwb_b_clr_dirty_T = _GEN; // @[Scheduler.scala:157:37, :159:37]
wire _nestedwb_b_toN_T_1 = _mshrs_10_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala:71:46, :157:123]
assign _nestedwb_b_toN_T_2 = _nestedwb_b_toN_T & _nestedwb_b_toN_T_1; // @[Scheduler.scala:157:{37,75,123}]
assign nestedwb_b_toN = _nestedwb_b_toN_T_2; // @[Scheduler.scala:75:22, :157:75]
wire _nestedwb_b_toB_T_1 = _mshrs_10_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala:71:46, :158:123]
assign _nestedwb_b_toB_T_2 = _nestedwb_b_toB_T & _nestedwb_b_toB_T_1; // @[Scheduler.scala:158:{37,75,123}]
assign nestedwb_b_toB = _nestedwb_b_toB_T_2; // @[Scheduler.scala:75:22, :158:75]
assign nestedwb_b_clr_dirty = _nestedwb_b_clr_dirty_T; // @[Scheduler.scala:75:22, :159:37]
wire _nestedwb_c_set_dirty_T = select_c & _mshrs_11_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :153:32, :160:37]
assign _nestedwb_c_set_dirty_T_1 = _nestedwb_c_set_dirty_T & _mshrs_11_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46, :160:{37,75}]
assign nestedwb_c_set_dirty = _nestedwb_c_set_dirty_T_1; // @[Scheduler.scala:75:22, :160:75]
wire _request_ready_T_2; // @[Scheduler.scala:261:40]
wire _request_valid_T_2; // @[Scheduler.scala:164:39]
wire _request_bits_T_1_prio_0; // @[Scheduler.scala:165:22]
wire _view__WIRE_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_1_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_2_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_3_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_4_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_5_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_6_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_7_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_8_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_9_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_10_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_11_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95]
wire _request_bits_T_1_prio_2; // @[Scheduler.scala:165:22]
wire _request_bits_T_1_control; // @[Scheduler.scala:165:22]
wire _view__WIRE_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_1_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_2_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_3_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_4_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_5_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_6_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_7_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_8_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_9_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_10_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_11_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _request_bits_T_1_opcode; // @[Scheduler.scala:165:22]
wire _view__WIRE_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_1_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_2_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_3_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_4_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_5_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_6_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_7_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_8_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_9_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_10_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire _view__WIRE_11_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _request_bits_T_1_param; // @[Scheduler.scala:165:22]
wire [2:0] _view__WIRE_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_1_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_2_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_3_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_4_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_5_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_6_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_7_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_8_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_9_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_10_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_11_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _request_bits_T_1_size; // @[Scheduler.scala:165:22]
wire [2:0] _view__WIRE_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_1_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_2_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_3_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_4_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_5_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_6_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_7_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_8_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_9_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_10_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_11_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95]
wire [7:0] _request_bits_T_1_source; // @[Scheduler.scala:165:22]
wire [2:0] _view__WIRE_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_1_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_2_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_3_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_4_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_5_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_6_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_7_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_8_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_9_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_10_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [2:0] _view__WIRE_11_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95]
wire [12:0] _request_bits_T_1_tag; // @[Scheduler.scala:165:22]
wire [7:0] _view__WIRE_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [7:0] _view__WIRE_1_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [7:0] _view__WIRE_2_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [7:0] _view__WIRE_3_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [7:0] _view__WIRE_4_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [7:0] _view__WIRE_5_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [7:0] _view__WIRE_6_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [7:0] _view__WIRE_7_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [7:0] _view__WIRE_8_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [7:0] _view__WIRE_9_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [7:0] _view__WIRE_10_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [7:0] _view__WIRE_11_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _request_bits_T_1_offset; // @[Scheduler.scala:165:22]
wire [12:0] _view__WIRE_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [12:0] _view__WIRE_1_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [12:0] _view__WIRE_2_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [12:0] _view__WIRE_3_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [12:0] _view__WIRE_4_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [12:0] _view__WIRE_5_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [12:0] _view__WIRE_6_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [12:0] _view__WIRE_7_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [12:0] _view__WIRE_8_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [12:0] _view__WIRE_9_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [12:0] _view__WIRE_10_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [12:0] _view__WIRE_11_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _request_bits_T_1_put; // @[Scheduler.scala:165:22]
wire [5:0] _view__WIRE_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_1_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_2_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_3_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_4_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_5_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_6_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_7_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_8_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_9_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_10_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_11_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95]
wire [9:0] _request_bits_T_1_set; // @[Scheduler.scala:165:22]
wire [5:0] _view__WIRE_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_1_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_2_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_3_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_4_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_5_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_6_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_7_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_8_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_9_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_10_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [5:0] _view__WIRE_11_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95]
wire [9:0] request_bits_set; // @[Scheduler.scala:163:21]
wire request_ready; // @[Scheduler.scala:163:21]
wire request_valid; // @[Scheduler.scala:163:21]
wire _request_valid_T = _sinkA_io_req_valid | _sinkX_io_req_valid; // @[Scheduler.scala:54:21, :58:21, :164:62]
wire _request_valid_T_1 = _request_valid_T | _sinkC_io_req_valid; // @[Scheduler.scala:55:21, :164:{62,84}]
assign _request_valid_T_2 = _directory_io_ready & _request_valid_T_1; // @[Scheduler.scala:68:25, :164:{39,84}]
assign request_valid = _request_valid_T_2; // @[Scheduler.scala:163:21, :164:39]
wire [2:0] _request_bits_T_opcode = _sinkX_io_req_valid ? 3'h0 : _sinkA_io_req_bits_opcode; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [2:0] _request_bits_T_param = _sinkX_io_req_valid ? 3'h0 : _sinkA_io_req_bits_param; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [2:0] _request_bits_T_size = _sinkX_io_req_valid ? 3'h6 : _sinkA_io_req_bits_size; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [7:0] _request_bits_T_source = _sinkX_io_req_valid ? 8'h0 : _sinkA_io_req_bits_source; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [12:0] _request_bits_T_tag = _sinkX_io_req_valid ? _sinkX_io_req_bits_tag : _sinkA_io_req_bits_tag; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [5:0] _request_bits_T_offset = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_offset; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [5:0] _request_bits_T_put = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_put; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire [9:0] _request_bits_T_set = _sinkX_io_req_valid ? _sinkX_io_req_bits_set : _sinkA_io_req_bits_set; // @[Scheduler.scala:54:21, :58:21, :166:22]
wire _request_bits_T_control; // @[Scheduler.scala:166:22]
assign _request_bits_T_1_control = ~_sinkC_io_req_valid & _request_bits_T_control; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_opcode = _sinkC_io_req_valid ? _sinkC_io_req_bits_opcode : _request_bits_T_opcode; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_param = _sinkC_io_req_valid ? _sinkC_io_req_bits_param : _request_bits_T_param; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_size = _sinkC_io_req_valid ? _sinkC_io_req_bits_size : _request_bits_T_size; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_source = _sinkC_io_req_valid ? _sinkC_io_req_bits_source : _request_bits_T_source; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_tag = _sinkC_io_req_valid ? _sinkC_io_req_bits_tag : _request_bits_T_tag; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_offset = _sinkC_io_req_valid ? _sinkC_io_req_bits_offset : _request_bits_T_offset; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_put = _sinkC_io_req_valid ? _sinkC_io_req_bits_put : _request_bits_T_put; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_set = _sinkC_io_req_valid ? _sinkC_io_req_bits_set : _request_bits_T_set; // @[Scheduler.scala:55:21, :165:22, :166:22]
assign _request_bits_T_1_prio_0 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22]
assign request_bits_prio_0 = _request_bits_T_1_prio_0; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_prio_2 = _request_bits_T_1_prio_2; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_control = _request_bits_T_1_control; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_opcode = _request_bits_T_1_opcode; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_param = _request_bits_T_1_param; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_size = _request_bits_T_1_size; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_source = _request_bits_T_1_source; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_tag = _request_bits_T_1_tag; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_offset = _request_bits_T_1_offset; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_put = _request_bits_T_1_put; // @[Scheduler.scala:163:21, :165:22]
assign request_bits_set = _request_bits_T_1_set; // @[Scheduler.scala:163:21, :165:22]
wire _GEN_0 = _directory_io_ready & request_ready; // @[Scheduler.scala:68:25, :163:21, :167:44]
wire _sinkC_io_req_ready_T; // @[Scheduler.scala:167:44]
assign _sinkC_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44]
wire _sinkX_io_req_ready_T; // @[Scheduler.scala:168:44]
assign _sinkX_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44, :168:44]
wire _sinkA_io_req_ready_T; // @[Scheduler.scala:169:44]
assign _sinkA_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44, :169:44]
wire _sinkX_io_req_ready_T_1 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22, :168:64]
wire _sinkX_io_req_ready_T_2 = _sinkX_io_req_ready_T & _sinkX_io_req_ready_T_1; // @[Scheduler.scala:168:{44,61,64}]
wire _sinkA_io_req_ready_T_1 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22, :169:64]
wire _sinkA_io_req_ready_T_2 = _sinkA_io_req_ready_T & _sinkA_io_req_ready_T_1; // @[Scheduler.scala:169:{44,61,64}]
wire _sinkA_io_req_ready_T_3 = ~_sinkX_io_req_valid; // @[Scheduler.scala:58:21, :169:87]
wire _sinkA_io_req_ready_T_4 = _sinkA_io_req_ready_T_2 & _sinkA_io_req_ready_T_3; // @[Scheduler.scala:169:{61,84,87}]
wire _setMatches_T = _mshrs_0_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_1 = _mshrs_0_io_status_valid & _setMatches_T; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_2 = _mshrs_1_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_3 = _mshrs_1_io_status_valid & _setMatches_T_2; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_4 = _mshrs_2_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_5 = _mshrs_2_io_status_valid & _setMatches_T_4; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_6 = _mshrs_3_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_7 = _mshrs_3_io_status_valid & _setMatches_T_6; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_8 = _mshrs_4_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_9 = _mshrs_4_io_status_valid & _setMatches_T_8; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_10 = _mshrs_5_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_11 = _mshrs_5_io_status_valid & _setMatches_T_10; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_12 = _mshrs_6_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_13 = _mshrs_6_io_status_valid & _setMatches_T_12; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_14 = _mshrs_7_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_15 = _mshrs_7_io_status_valid & _setMatches_T_14; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_16 = _mshrs_8_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_17 = _mshrs_8_io_status_valid & _setMatches_T_16; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_18 = _mshrs_9_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_19 = _mshrs_9_io_status_valid & _setMatches_T_18; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_20 = _mshrs_10_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_21 = _mshrs_10_io_status_valid & _setMatches_T_20; // @[Scheduler.scala:71:46, :172:{59,83}]
wire _setMatches_T_22 = _mshrs_11_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83]
wire _setMatches_T_23 = _mshrs_11_io_status_valid & _setMatches_T_22; // @[Scheduler.scala:71:46, :172:{59,83}]
wire [1:0] setMatches_lo_lo_hi = {_setMatches_T_5, _setMatches_T_3}; // @[Scheduler.scala:172:{23,59}]
wire [2:0] setMatches_lo_lo = {setMatches_lo_lo_hi, _setMatches_T_1}; // @[Scheduler.scala:172:{23,59}]
wire [1:0] setMatches_lo_hi_hi = {_setMatches_T_11, _setMatches_T_9}; // @[Scheduler.scala:172:{23,59}]
wire [2:0] setMatches_lo_hi = {setMatches_lo_hi_hi, _setMatches_T_7}; // @[Scheduler.scala:172:{23,59}]
wire [5:0] setMatches_lo = {setMatches_lo_hi, setMatches_lo_lo}; // @[Scheduler.scala:172:23]
wire [1:0] setMatches_hi_lo_hi = {_setMatches_T_17, _setMatches_T_15}; // @[Scheduler.scala:172:{23,59}]
wire [2:0] setMatches_hi_lo = {setMatches_hi_lo_hi, _setMatches_T_13}; // @[Scheduler.scala:172:{23,59}]
wire [1:0] setMatches_hi_hi_hi = {_setMatches_T_23, _setMatches_T_21}; // @[Scheduler.scala:172:{23,59}]
wire [2:0] setMatches_hi_hi = {setMatches_hi_hi_hi, _setMatches_T_19}; // @[Scheduler.scala:172:{23,59}]
wire [5:0] setMatches_hi = {setMatches_hi_hi, setMatches_hi_lo}; // @[Scheduler.scala:172:23]
wire [11:0] setMatches = {setMatches_hi, setMatches_lo}; // @[Scheduler.scala:172:23]
wire _alloc_T = |setMatches; // @[Scheduler.scala:172:23, :173:27]
wire alloc = ~_alloc_T; // @[Scheduler.scala:173:{15,27}]
wire _blockB_T = setMatches[0]; // @[Mux.scala:32:36]
wire _blockC_T = setMatches[0]; // @[Mux.scala:32:36]
wire _nestB_T = setMatches[0]; // @[Mux.scala:32:36]
wire _nestC_T = setMatches[0]; // @[Mux.scala:32:36]
wire _blockB_T_1 = setMatches[1]; // @[Mux.scala:32:36]
wire _blockC_T_1 = setMatches[1]; // @[Mux.scala:32:36]
wire _nestB_T_1 = setMatches[1]; // @[Mux.scala:32:36]
wire _nestC_T_1 = setMatches[1]; // @[Mux.scala:32:36]
wire _blockB_T_2 = setMatches[2]; // @[Mux.scala:32:36]
wire _blockC_T_2 = setMatches[2]; // @[Mux.scala:32:36]
wire _nestB_T_2 = setMatches[2]; // @[Mux.scala:32:36]
wire _nestC_T_2 = setMatches[2]; // @[Mux.scala:32:36]
wire _blockB_T_3 = setMatches[3]; // @[Mux.scala:32:36]
wire _blockC_T_3 = setMatches[3]; // @[Mux.scala:32:36]
wire _nestB_T_3 = setMatches[3]; // @[Mux.scala:32:36]
wire _nestC_T_3 = setMatches[3]; // @[Mux.scala:32:36]
wire _blockB_T_4 = setMatches[4]; // @[Mux.scala:32:36]
wire _blockC_T_4 = setMatches[4]; // @[Mux.scala:32:36]
wire _nestB_T_4 = setMatches[4]; // @[Mux.scala:32:36]
wire _nestC_T_4 = setMatches[4]; // @[Mux.scala:32:36]
wire _blockB_T_5 = setMatches[5]; // @[Mux.scala:32:36]
wire _blockC_T_5 = setMatches[5]; // @[Mux.scala:32:36]
wire _nestB_T_5 = setMatches[5]; // @[Mux.scala:32:36]
wire _nestC_T_5 = setMatches[5]; // @[Mux.scala:32:36]
wire _blockB_T_6 = setMatches[6]; // @[Mux.scala:32:36]
wire _blockC_T_6 = setMatches[6]; // @[Mux.scala:32:36]
wire _nestB_T_6 = setMatches[6]; // @[Mux.scala:32:36]
wire _nestC_T_6 = setMatches[6]; // @[Mux.scala:32:36]
wire _blockB_T_7 = setMatches[7]; // @[Mux.scala:32:36]
wire _blockC_T_7 = setMatches[7]; // @[Mux.scala:32:36]
wire _nestB_T_7 = setMatches[7]; // @[Mux.scala:32:36]
wire _nestC_T_7 = setMatches[7]; // @[Mux.scala:32:36]
wire _blockB_T_8 = setMatches[8]; // @[Mux.scala:32:36]
wire _blockC_T_8 = setMatches[8]; // @[Mux.scala:32:36]
wire _nestB_T_8 = setMatches[8]; // @[Mux.scala:32:36]
wire _nestC_T_8 = setMatches[8]; // @[Mux.scala:32:36]
wire _blockB_T_9 = setMatches[9]; // @[Mux.scala:32:36]
wire _blockC_T_9 = setMatches[9]; // @[Mux.scala:32:36]
wire _nestB_T_9 = setMatches[9]; // @[Mux.scala:32:36]
wire _nestC_T_9 = setMatches[9]; // @[Mux.scala:32:36]
wire _blockB_T_10 = setMatches[10]; // @[Mux.scala:32:36]
wire _blockC_T_10 = setMatches[10]; // @[Mux.scala:32:36]
wire _nestB_T_10 = setMatches[10]; // @[Mux.scala:32:36]
wire _nestC_T_10 = setMatches[10]; // @[Mux.scala:32:36]
wire _blockB_T_11 = setMatches[11]; // @[Mux.scala:32:36]
wire _blockC_T_11 = setMatches[11]; // @[Mux.scala:32:36]
wire _nestB_T_11 = setMatches[11]; // @[Mux.scala:32:36]
wire _nestC_T_11 = setMatches[11]; // @[Mux.scala:32:36]
wire _blockB_T_12 = _blockB_T & _mshrs_0_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_13 = _blockB_T_1 & _mshrs_1_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_14 = _blockB_T_2 & _mshrs_2_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_15 = _blockB_T_3 & _mshrs_3_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_16 = _blockB_T_4 & _mshrs_4_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_17 = _blockB_T_5 & _mshrs_5_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_18 = _blockB_T_6 & _mshrs_6_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_19 = _blockB_T_7 & _mshrs_7_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_20 = _blockB_T_8 & _mshrs_8_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_21 = _blockB_T_9 & _mshrs_9_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_22 = _blockB_T_10 & _mshrs_10_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_23 = _blockB_T_11 & _mshrs_11_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36]
wire _blockB_T_24 = _blockB_T_12 | _blockB_T_13; // @[Mux.scala:30:73]
wire _blockB_T_25 = _blockB_T_24 | _blockB_T_14; // @[Mux.scala:30:73]
wire _blockB_T_26 = _blockB_T_25 | _blockB_T_15; // @[Mux.scala:30:73]
wire _blockB_T_27 = _blockB_T_26 | _blockB_T_16; // @[Mux.scala:30:73]
wire _blockB_T_28 = _blockB_T_27 | _blockB_T_17; // @[Mux.scala:30:73]
wire _blockB_T_29 = _blockB_T_28 | _blockB_T_18; // @[Mux.scala:30:73]
wire _blockB_T_30 = _blockB_T_29 | _blockB_T_19; // @[Mux.scala:30:73]
wire _blockB_T_31 = _blockB_T_30 | _blockB_T_20; // @[Mux.scala:30:73]
wire _blockB_T_32 = _blockB_T_31 | _blockB_T_21; // @[Mux.scala:30:73]
wire _blockB_T_33 = _blockB_T_32 | _blockB_T_22; // @[Mux.scala:30:73]
wire _blockB_T_34 = _blockB_T_33 | _blockB_T_23; // @[Mux.scala:30:73]
wire _blockB_WIRE = _blockB_T_34; // @[Mux.scala:30:73]
wire _blockC_T_12 = _blockC_T & _mshrs_0_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_13 = _blockC_T_1 & _mshrs_1_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_14 = _blockC_T_2 & _mshrs_2_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_15 = _blockC_T_3 & _mshrs_3_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_16 = _blockC_T_4 & _mshrs_4_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_17 = _blockC_T_5 & _mshrs_5_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_18 = _blockC_T_6 & _mshrs_6_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_19 = _blockC_T_7 & _mshrs_7_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_20 = _blockC_T_8 & _mshrs_8_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_21 = _blockC_T_9 & _mshrs_9_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_22 = _blockC_T_10 & _mshrs_10_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_23 = _blockC_T_11 & _mshrs_11_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36]
wire _blockC_T_24 = _blockC_T_12 | _blockC_T_13; // @[Mux.scala:30:73]
wire _blockC_T_25 = _blockC_T_24 | _blockC_T_14; // @[Mux.scala:30:73]
wire _blockC_T_26 = _blockC_T_25 | _blockC_T_15; // @[Mux.scala:30:73]
wire _blockC_T_27 = _blockC_T_26 | _blockC_T_16; // @[Mux.scala:30:73]
wire _blockC_T_28 = _blockC_T_27 | _blockC_T_17; // @[Mux.scala:30:73]
wire _blockC_T_29 = _blockC_T_28 | _blockC_T_18; // @[Mux.scala:30:73]
wire _blockC_T_30 = _blockC_T_29 | _blockC_T_19; // @[Mux.scala:30:73]
wire _blockC_T_31 = _blockC_T_30 | _blockC_T_20; // @[Mux.scala:30:73]
wire _blockC_T_32 = _blockC_T_31 | _blockC_T_21; // @[Mux.scala:30:73]
wire _blockC_T_33 = _blockC_T_32 | _blockC_T_22; // @[Mux.scala:30:73]
wire _blockC_T_34 = _blockC_T_33 | _blockC_T_23; // @[Mux.scala:30:73]
wire _blockC_WIRE = _blockC_T_34; // @[Mux.scala:30:73]
wire blockC = _blockC_WIRE & request_bits_prio_2; // @[Mux.scala:30:73]
wire _nestB_T_12 = _nestB_T & _mshrs_0_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_13 = _nestB_T_1 & _mshrs_1_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_14 = _nestB_T_2 & _mshrs_2_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_15 = _nestB_T_3 & _mshrs_3_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_16 = _nestB_T_4 & _mshrs_4_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_17 = _nestB_T_5 & _mshrs_5_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_18 = _nestB_T_6 & _mshrs_6_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_19 = _nestB_T_7 & _mshrs_7_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_20 = _nestB_T_8 & _mshrs_8_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_21 = _nestB_T_9 & _mshrs_9_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_22 = _nestB_T_10 & _mshrs_10_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_23 = _nestB_T_11 & _mshrs_11_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36]
wire _nestB_T_24 = _nestB_T_12 | _nestB_T_13; // @[Mux.scala:30:73]
wire _nestB_T_25 = _nestB_T_24 | _nestB_T_14; // @[Mux.scala:30:73]
wire _nestB_T_26 = _nestB_T_25 | _nestB_T_15; // @[Mux.scala:30:73]
wire _nestB_T_27 = _nestB_T_26 | _nestB_T_16; // @[Mux.scala:30:73]
wire _nestB_T_28 = _nestB_T_27 | _nestB_T_17; // @[Mux.scala:30:73]
wire _nestB_T_29 = _nestB_T_28 | _nestB_T_18; // @[Mux.scala:30:73]
wire _nestB_T_30 = _nestB_T_29 | _nestB_T_19; // @[Mux.scala:30:73]
wire _nestB_T_31 = _nestB_T_30 | _nestB_T_20; // @[Mux.scala:30:73]
wire _nestB_T_32 = _nestB_T_31 | _nestB_T_21; // @[Mux.scala:30:73]
wire _nestB_T_33 = _nestB_T_32 | _nestB_T_22; // @[Mux.scala:30:73]
wire _nestB_T_34 = _nestB_T_33 | _nestB_T_23; // @[Mux.scala:30:73]
wire _nestB_WIRE = _nestB_T_34; // @[Mux.scala:30:73]
wire _nestC_T_12 = _nestC_T & _mshrs_0_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_13 = _nestC_T_1 & _mshrs_1_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_14 = _nestC_T_2 & _mshrs_2_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_15 = _nestC_T_3 & _mshrs_3_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_16 = _nestC_T_4 & _mshrs_4_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_17 = _nestC_T_5 & _mshrs_5_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_18 = _nestC_T_6 & _mshrs_6_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_19 = _nestC_T_7 & _mshrs_7_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_20 = _nestC_T_8 & _mshrs_8_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_21 = _nestC_T_9 & _mshrs_9_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_22 = _nestC_T_10 & _mshrs_10_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_23 = _nestC_T_11 & _mshrs_11_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36]
wire _nestC_T_24 = _nestC_T_12 | _nestC_T_13; // @[Mux.scala:30:73]
wire _nestC_T_25 = _nestC_T_24 | _nestC_T_14; // @[Mux.scala:30:73]
wire _nestC_T_26 = _nestC_T_25 | _nestC_T_15; // @[Mux.scala:30:73]
wire _nestC_T_27 = _nestC_T_26 | _nestC_T_16; // @[Mux.scala:30:73]
wire _nestC_T_28 = _nestC_T_27 | _nestC_T_17; // @[Mux.scala:30:73]
wire _nestC_T_29 = _nestC_T_28 | _nestC_T_18; // @[Mux.scala:30:73]
wire _nestC_T_30 = _nestC_T_29 | _nestC_T_19; // @[Mux.scala:30:73]
wire _nestC_T_31 = _nestC_T_30 | _nestC_T_20; // @[Mux.scala:30:73]
wire _nestC_T_32 = _nestC_T_31 | _nestC_T_21; // @[Mux.scala:30:73]
wire _nestC_T_33 = _nestC_T_32 | _nestC_T_22; // @[Mux.scala:30:73]
wire _nestC_T_34 = _nestC_T_33 | _nestC_T_23; // @[Mux.scala:30:73]
wire _nestC_WIRE = _nestC_T_34; // @[Mux.scala:30:73]
wire nestC = _nestC_WIRE & request_bits_prio_2; // @[Mux.scala:30:73]
wire _prioFilter_T = ~request_bits_prio_0; // @[Scheduler.scala:163:21, :182:46]
wire [1:0] prioFilter_hi = {request_bits_prio_2, _prioFilter_T}; // @[Scheduler.scala:163:21, :182:{23,46}]
wire [11:0] prioFilter = {prioFilter_hi, 10'h3FF}; // @[Scheduler.scala:182:23]
wire [11:0] lowerMatches = setMatches & prioFilter; // @[Scheduler.scala:172:23, :182:23, :183:33]
wire _queue_T = |lowerMatches; // @[Scheduler.scala:183:33, :185:28]
wire _queue_T_2 = _queue_T; // @[Scheduler.scala:185:{28,32}]
wire _queue_T_3 = ~nestC; // @[Scheduler.scala:180:70, :185:45]
wire _queue_T_4 = _queue_T_2 & _queue_T_3; // @[Scheduler.scala:185:{32,42,45}]
wire _queue_T_6 = _queue_T_4; // @[Scheduler.scala:185:{42,52}]
wire _queue_T_7 = ~blockC; // @[Scheduler.scala:176:70, :185:66]
wire queue = _queue_T_6 & _queue_T_7; // @[Scheduler.scala:185:{52,63,66}]
wire _T_12 = request_valid & queue; // @[Scheduler.scala:163:21, :185:63, :195:31]
wire _bypass_T; // @[Scheduler.scala:213:30]
assign _bypass_T = _T_12; // @[Scheduler.scala:195:31, :213:30]
wire _bypass_T_1; // @[Scheduler.scala:231:32]
assign _bypass_T_1 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_2; // @[Scheduler.scala:231:32]
assign _bypass_T_2 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_3; // @[Scheduler.scala:231:32]
assign _bypass_T_3 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_4; // @[Scheduler.scala:231:32]
assign _bypass_T_4 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_5; // @[Scheduler.scala:231:32]
assign _bypass_T_5 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_6; // @[Scheduler.scala:231:32]
assign _bypass_T_6 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_7; // @[Scheduler.scala:231:32]
assign _bypass_T_7 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_8; // @[Scheduler.scala:231:32]
assign _bypass_T_8 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_9; // @[Scheduler.scala:231:32]
assign _bypass_T_9 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_10; // @[Scheduler.scala:231:32]
assign _bypass_T_10 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_11; // @[Scheduler.scala:231:32]
assign _bypass_T_11 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _bypass_T_12; // @[Scheduler.scala:231:32]
assign _bypass_T_12 = _T_12; // @[Scheduler.scala:195:31, :231:32]
wire _requests_io_push_valid_T; // @[Scheduler.scala:270:43]
assign _requests_io_push_valid_T = _T_12; // @[Scheduler.scala:195:31, :270:43]
wire _lowerMatches1_T = lowerMatches[11]; // @[Scheduler.scala:183:33, :200:21]
wire _lowerMatches1_T_2 = lowerMatches[10]; // @[Scheduler.scala:183:33, :201:21]
wire [11:0] _lowerMatches1_T_4 = _lowerMatches1_T_2 ? 12'h400 : lowerMatches; // @[Scheduler.scala:183:33, :201:{8,21}]
wire [11:0] lowerMatches1 = _lowerMatches1_T ? 12'h800 : _lowerMatches1_T_4; // @[Scheduler.scala:200:{8,21}, :201:8]
wire [11:0] _requests_io_push_bits_index_T = lowerMatches1; // @[Scheduler.scala:200:8, :274:30]
wire [23:0] _GEN_1 = {2{mshr_selectOH}}; // @[Scheduler.scala:121:70, :206:30]
wire [23:0] selected_requests_hi; // @[Scheduler.scala:206:30]
assign selected_requests_hi = _GEN_1; // @[Scheduler.scala:206:30]
wire [23:0] pop_index_hi; // @[Scheduler.scala:241:31]
assign pop_index_hi = _GEN_1; // @[Scheduler.scala:206:30, :241:31]
wire [35:0] _selected_requests_T = {selected_requests_hi, mshr_selectOH}; // @[Scheduler.scala:121:70, :206:30]
wire [35:0] selected_requests = _selected_requests_T & _requests_io_valid; // @[Scheduler.scala:70:24, :206:{30,76}]
wire [11:0] _a_pop_T = selected_requests[11:0]; // @[Scheduler.scala:206:76, :207:32]
wire a_pop = |_a_pop_T; // @[Scheduler.scala:207:{32,79}]
wire [11:0] _b_pop_T = selected_requests[23:12]; // @[Scheduler.scala:206:76, :208:32]
wire b_pop = |_b_pop_T; // @[Scheduler.scala:208:{32,79}]
wire _bypassMatches_T_4 = b_pop; // @[Scheduler.scala:208:79, :211:76]
wire [11:0] _c_pop_T = selected_requests[35:24]; // @[Scheduler.scala:206:76, :209:32]
wire c_pop = |_c_pop_T; // @[Scheduler.scala:209:{32,79}]
wire [11:0] _bypassMatches_T = mshr_selectOH & lowerMatches1; // @[Scheduler.scala:121:70, :200:8, :210:38]
wire _bypassMatches_T_1 = |_bypassMatches_T; // @[Scheduler.scala:210:{38,55}]
wire _bypassMatches_T_2 = c_pop | request_bits_prio_2; // @[Scheduler.scala:163:21, :209:79, :211:33]
wire _bypassMatches_T_3 = ~c_pop; // @[Scheduler.scala:209:79, :211:58]
wire _bypassMatches_T_5 = ~b_pop; // @[Scheduler.scala:208:79, :211:101]
wire _bypassMatches_T_6 = ~a_pop; // @[Scheduler.scala:207:79, :211:109]
wire _bypassMatches_T_7 = _bypassMatches_T_4 ? _bypassMatches_T_5 : _bypassMatches_T_6; // @[Scheduler.scala:211:{69,76,101,109}]
wire _bypassMatches_T_8 = _bypassMatches_T_2 ? _bypassMatches_T_3 : _bypassMatches_T_7; // @[Scheduler.scala:211:{26,33,58,69}]
wire bypassMatches = _bypassMatches_T_1 & _bypassMatches_T_8; // @[Scheduler.scala:210:{55,59}, :211:26]
wire _may_pop_T = a_pop | b_pop; // @[Scheduler.scala:207:79, :208:79, :212:23]
wire may_pop = _may_pop_T | c_pop; // @[Scheduler.scala:209:79, :212:{23,32}]
wire bypass = _bypass_T & bypassMatches; // @[Scheduler.scala:210:59, :213:{30,39}]
wire _will_reload_T = may_pop | bypass; // @[Scheduler.scala:212:32, :213:39, :214:49]
wire will_reload = schedule_reload & _will_reload_T; // @[Mux.scala:30:73]
wire _GEN_2 = schedule_reload & may_pop; // @[Mux.scala:30:73]
wire _will_pop_T; // @[Scheduler.scala:215:34]
assign _will_pop_T = _GEN_2; // @[Scheduler.scala:215:34]
wire _mshr_uses_directory_assuming_no_bypass_T; // @[Scheduler.scala:247:64]
assign _mshr_uses_directory_assuming_no_bypass_T = _GEN_2; // @[Scheduler.scala:215:34, :247:64]
wire _will_pop_T_1 = ~bypass; // @[Scheduler.scala:213:39, :215:48]
wire will_pop = _will_pop_T & _will_pop_T_1; // @[Scheduler.scala:215:{34,45,48}]
wire a_pop_1 = _requests_io_valid[0]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_1 = _requests_io_valid[12]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_12 = b_pop_1; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_1 = _requests_io_valid[24]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_9 = lowerMatches1[0]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_10 = c_pop_1 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_11 = ~c_pop_1; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_13 = ~b_pop_1; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_14 = ~a_pop_1; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_15 = _bypassMatches_T_12 ? _bypassMatches_T_13 : _bypassMatches_T_14; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_16 = _bypassMatches_T_10 ? _bypassMatches_T_11 : _bypassMatches_T_15; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_1 = _bypassMatches_T_9 & _bypassMatches_T_16; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_1 = a_pop_1 | b_pop_1; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_1 = _may_pop_T_1 | c_pop_1; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_1 = _bypass_T_1 & bypassMatches_1; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_1 = may_pop_1 | bypass_1; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_1 = _mshrs_0_io_schedule_bits_reload & _will_reload_T_1; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_prio_0 = bypass_1 ? _view__WIRE_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_prio_1 = ~bypass_1 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_prio_2 = bypass_1 ? _view__WIRE_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_control = bypass_1 ? _view__WIRE_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_opcode = bypass_1 ? _view__WIRE_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_param = bypass_1 ? _view__WIRE_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_size = bypass_1 ? _view__WIRE_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [7:0] _view__T_source = bypass_1 ? _view__WIRE_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [12:0] _view__T_tag = bypass_1 ? _view__WIRE_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_offset = bypass_1 ? _view__WIRE_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_put = bypass_1 ? _view__WIRE_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_0_io_allocate_bits_repeat_T = mshrs_0_io_allocate_bits_tag == _mshrs_0_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_0_io_allocate_valid_T = sel & will_reload_1; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_2 = _requests_io_valid[1]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_2 = _requests_io_valid[13]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_20 = b_pop_2; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_2 = _requests_io_valid[25]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_17 = lowerMatches1[1]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_18 = c_pop_2 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_19 = ~c_pop_2; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_21 = ~b_pop_2; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_22 = ~a_pop_2; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_23 = _bypassMatches_T_20 ? _bypassMatches_T_21 : _bypassMatches_T_22; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_24 = _bypassMatches_T_18 ? _bypassMatches_T_19 : _bypassMatches_T_23; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_2 = _bypassMatches_T_17 & _bypassMatches_T_24; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_2 = a_pop_2 | b_pop_2; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_2 = _may_pop_T_2 | c_pop_2; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_2 = _bypass_T_2 & bypassMatches_2; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_2 = may_pop_2 | bypass_2; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_2 = _mshrs_1_io_schedule_bits_reload & _will_reload_T_2; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_1_prio_0 = bypass_2 ? _view__WIRE_1_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_1_prio_1 = ~bypass_2 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_1_prio_2 = bypass_2 ? _view__WIRE_1_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_1_control = bypass_2 ? _view__WIRE_1_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_1_opcode = bypass_2 ? _view__WIRE_1_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_1_param = bypass_2 ? _view__WIRE_1_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_1_size = bypass_2 ? _view__WIRE_1_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [7:0] _view__T_1_source = bypass_2 ? _view__WIRE_1_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [12:0] _view__T_1_tag = bypass_2 ? _view__WIRE_1_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_1_offset = bypass_2 ? _view__WIRE_1_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_1_put = bypass_2 ? _view__WIRE_1_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_1_io_allocate_bits_repeat_T = mshrs_1_io_allocate_bits_tag == _mshrs_1_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_1_io_allocate_valid_T = sel_1 & will_reload_2; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_3 = _requests_io_valid[2]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_3 = _requests_io_valid[14]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_28 = b_pop_3; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_3 = _requests_io_valid[26]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_25 = lowerMatches1[2]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_26 = c_pop_3 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_27 = ~c_pop_3; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_29 = ~b_pop_3; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_30 = ~a_pop_3; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_31 = _bypassMatches_T_28 ? _bypassMatches_T_29 : _bypassMatches_T_30; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_32 = _bypassMatches_T_26 ? _bypassMatches_T_27 : _bypassMatches_T_31; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_3 = _bypassMatches_T_25 & _bypassMatches_T_32; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_3 = a_pop_3 | b_pop_3; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_3 = _may_pop_T_3 | c_pop_3; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_3 = _bypass_T_3 & bypassMatches_3; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_3 = may_pop_3 | bypass_3; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_3 = _mshrs_2_io_schedule_bits_reload & _will_reload_T_3; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_2_prio_0 = bypass_3 ? _view__WIRE_2_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_2_prio_1 = ~bypass_3 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_2_prio_2 = bypass_3 ? _view__WIRE_2_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_2_control = bypass_3 ? _view__WIRE_2_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_2_opcode = bypass_3 ? _view__WIRE_2_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_2_param = bypass_3 ? _view__WIRE_2_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_2_size = bypass_3 ? _view__WIRE_2_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [7:0] _view__T_2_source = bypass_3 ? _view__WIRE_2_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [12:0] _view__T_2_tag = bypass_3 ? _view__WIRE_2_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_2_offset = bypass_3 ? _view__WIRE_2_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_2_put = bypass_3 ? _view__WIRE_2_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_2_io_allocate_bits_repeat_T = mshrs_2_io_allocate_bits_tag == _mshrs_2_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_2_io_allocate_valid_T = sel_2 & will_reload_3; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_4 = _requests_io_valid[3]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_4 = _requests_io_valid[15]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_36 = b_pop_4; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_4 = _requests_io_valid[27]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_33 = lowerMatches1[3]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_34 = c_pop_4 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_35 = ~c_pop_4; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_37 = ~b_pop_4; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_38 = ~a_pop_4; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_39 = _bypassMatches_T_36 ? _bypassMatches_T_37 : _bypassMatches_T_38; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_40 = _bypassMatches_T_34 ? _bypassMatches_T_35 : _bypassMatches_T_39; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_4 = _bypassMatches_T_33 & _bypassMatches_T_40; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_4 = a_pop_4 | b_pop_4; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_4 = _may_pop_T_4 | c_pop_4; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_4 = _bypass_T_4 & bypassMatches_4; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_4 = may_pop_4 | bypass_4; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_4 = _mshrs_3_io_schedule_bits_reload & _will_reload_T_4; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_3_prio_0 = bypass_4 ? _view__WIRE_3_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_3_prio_1 = ~bypass_4 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_3_prio_2 = bypass_4 ? _view__WIRE_3_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_3_control = bypass_4 ? _view__WIRE_3_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_3_opcode = bypass_4 ? _view__WIRE_3_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_3_param = bypass_4 ? _view__WIRE_3_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_3_size = bypass_4 ? _view__WIRE_3_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [7:0] _view__T_3_source = bypass_4 ? _view__WIRE_3_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [12:0] _view__T_3_tag = bypass_4 ? _view__WIRE_3_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_3_offset = bypass_4 ? _view__WIRE_3_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_3_put = bypass_4 ? _view__WIRE_3_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_3_io_allocate_bits_repeat_T = mshrs_3_io_allocate_bits_tag == _mshrs_3_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_3_io_allocate_valid_T = sel_3 & will_reload_4; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_5 = _requests_io_valid[4]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_5 = _requests_io_valid[16]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_44 = b_pop_5; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_5 = _requests_io_valid[28]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_41 = lowerMatches1[4]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_42 = c_pop_5 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_43 = ~c_pop_5; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_45 = ~b_pop_5; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_46 = ~a_pop_5; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_47 = _bypassMatches_T_44 ? _bypassMatches_T_45 : _bypassMatches_T_46; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_48 = _bypassMatches_T_42 ? _bypassMatches_T_43 : _bypassMatches_T_47; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_5 = _bypassMatches_T_41 & _bypassMatches_T_48; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_5 = a_pop_5 | b_pop_5; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_5 = _may_pop_T_5 | c_pop_5; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_5 = _bypass_T_5 & bypassMatches_5; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_5 = may_pop_5 | bypass_5; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_5 = _mshrs_4_io_schedule_bits_reload & _will_reload_T_5; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_4_prio_0 = bypass_5 ? _view__WIRE_4_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_4_prio_1 = ~bypass_5 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_4_prio_2 = bypass_5 ? _view__WIRE_4_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_4_control = bypass_5 ? _view__WIRE_4_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_4_opcode = bypass_5 ? _view__WIRE_4_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_4_param = bypass_5 ? _view__WIRE_4_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_4_size = bypass_5 ? _view__WIRE_4_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [7:0] _view__T_4_source = bypass_5 ? _view__WIRE_4_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [12:0] _view__T_4_tag = bypass_5 ? _view__WIRE_4_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_4_offset = bypass_5 ? _view__WIRE_4_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_4_put = bypass_5 ? _view__WIRE_4_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_4_io_allocate_bits_repeat_T = mshrs_4_io_allocate_bits_tag == _mshrs_4_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_4_io_allocate_valid_T = sel_4 & will_reload_5; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_6 = _requests_io_valid[5]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_6 = _requests_io_valid[17]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_52 = b_pop_6; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_6 = _requests_io_valid[29]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_49 = lowerMatches1[5]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_50 = c_pop_6 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_51 = ~c_pop_6; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_53 = ~b_pop_6; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_54 = ~a_pop_6; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_55 = _bypassMatches_T_52 ? _bypassMatches_T_53 : _bypassMatches_T_54; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_56 = _bypassMatches_T_50 ? _bypassMatches_T_51 : _bypassMatches_T_55; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_6 = _bypassMatches_T_49 & _bypassMatches_T_56; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_6 = a_pop_6 | b_pop_6; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_6 = _may_pop_T_6 | c_pop_6; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_6 = _bypass_T_6 & bypassMatches_6; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_6 = may_pop_6 | bypass_6; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_6 = _mshrs_5_io_schedule_bits_reload & _will_reload_T_6; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_5_prio_0 = bypass_6 ? _view__WIRE_5_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_5_prio_1 = ~bypass_6 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_5_prio_2 = bypass_6 ? _view__WIRE_5_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_5_control = bypass_6 ? _view__WIRE_5_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_5_opcode = bypass_6 ? _view__WIRE_5_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_5_param = bypass_6 ? _view__WIRE_5_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_5_size = bypass_6 ? _view__WIRE_5_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [7:0] _view__T_5_source = bypass_6 ? _view__WIRE_5_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [12:0] _view__T_5_tag = bypass_6 ? _view__WIRE_5_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_5_offset = bypass_6 ? _view__WIRE_5_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_5_put = bypass_6 ? _view__WIRE_5_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_5_io_allocate_bits_repeat_T = mshrs_5_io_allocate_bits_tag == _mshrs_5_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_5_io_allocate_valid_T = sel_5 & will_reload_6; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_7 = _requests_io_valid[6]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_7 = _requests_io_valid[18]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_60 = b_pop_7; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_7 = _requests_io_valid[30]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_57 = lowerMatches1[6]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_58 = c_pop_7 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_59 = ~c_pop_7; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_61 = ~b_pop_7; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_62 = ~a_pop_7; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_63 = _bypassMatches_T_60 ? _bypassMatches_T_61 : _bypassMatches_T_62; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_64 = _bypassMatches_T_58 ? _bypassMatches_T_59 : _bypassMatches_T_63; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_7 = _bypassMatches_T_57 & _bypassMatches_T_64; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_7 = a_pop_7 | b_pop_7; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_7 = _may_pop_T_7 | c_pop_7; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_7 = _bypass_T_7 & bypassMatches_7; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_7 = may_pop_7 | bypass_7; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_7 = _mshrs_6_io_schedule_bits_reload & _will_reload_T_7; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_6_prio_0 = bypass_7 ? _view__WIRE_6_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_6_prio_1 = ~bypass_7 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_6_prio_2 = bypass_7 ? _view__WIRE_6_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_6_control = bypass_7 ? _view__WIRE_6_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_6_opcode = bypass_7 ? _view__WIRE_6_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_6_param = bypass_7 ? _view__WIRE_6_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_6_size = bypass_7 ? _view__WIRE_6_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [7:0] _view__T_6_source = bypass_7 ? _view__WIRE_6_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [12:0] _view__T_6_tag = bypass_7 ? _view__WIRE_6_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_6_offset = bypass_7 ? _view__WIRE_6_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_6_put = bypass_7 ? _view__WIRE_6_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_6_io_allocate_bits_repeat_T = mshrs_6_io_allocate_bits_tag == _mshrs_6_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_6_io_allocate_valid_T = sel_6 & will_reload_7; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_8 = _requests_io_valid[7]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_8 = _requests_io_valid[19]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_68 = b_pop_8; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_8 = _requests_io_valid[31]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_65 = lowerMatches1[7]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_66 = c_pop_8 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_67 = ~c_pop_8; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_69 = ~b_pop_8; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_70 = ~a_pop_8; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_71 = _bypassMatches_T_68 ? _bypassMatches_T_69 : _bypassMatches_T_70; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_72 = _bypassMatches_T_66 ? _bypassMatches_T_67 : _bypassMatches_T_71; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_8 = _bypassMatches_T_65 & _bypassMatches_T_72; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_8 = a_pop_8 | b_pop_8; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_8 = _may_pop_T_8 | c_pop_8; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_8 = _bypass_T_8 & bypassMatches_8; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_8 = may_pop_8 | bypass_8; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_8 = _mshrs_7_io_schedule_bits_reload & _will_reload_T_8; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_7_prio_0 = bypass_8 ? _view__WIRE_7_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_7_prio_1 = ~bypass_8 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_7_prio_2 = bypass_8 ? _view__WIRE_7_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_7_control = bypass_8 ? _view__WIRE_7_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_7_opcode = bypass_8 ? _view__WIRE_7_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_7_param = bypass_8 ? _view__WIRE_7_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_7_size = bypass_8 ? _view__WIRE_7_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [7:0] _view__T_7_source = bypass_8 ? _view__WIRE_7_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [12:0] _view__T_7_tag = bypass_8 ? _view__WIRE_7_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_7_offset = bypass_8 ? _view__WIRE_7_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_7_put = bypass_8 ? _view__WIRE_7_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_7_io_allocate_bits_repeat_T = mshrs_7_io_allocate_bits_tag == _mshrs_7_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_7_io_allocate_valid_T = sel_7 & will_reload_8; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_9 = _requests_io_valid[8]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_9 = _requests_io_valid[20]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_76 = b_pop_9; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_9 = _requests_io_valid[32]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_73 = lowerMatches1[8]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_74 = c_pop_9 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_75 = ~c_pop_9; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_77 = ~b_pop_9; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_78 = ~a_pop_9; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_79 = _bypassMatches_T_76 ? _bypassMatches_T_77 : _bypassMatches_T_78; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_80 = _bypassMatches_T_74 ? _bypassMatches_T_75 : _bypassMatches_T_79; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_9 = _bypassMatches_T_73 & _bypassMatches_T_80; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_9 = a_pop_9 | b_pop_9; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_9 = _may_pop_T_9 | c_pop_9; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_9 = _bypass_T_9 & bypassMatches_9; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_9 = may_pop_9 | bypass_9; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_9 = _mshrs_8_io_schedule_bits_reload & _will_reload_T_9; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_8_prio_0 = bypass_9 ? _view__WIRE_8_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_8_prio_1 = ~bypass_9 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_8_prio_2 = bypass_9 ? _view__WIRE_8_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_8_control = bypass_9 ? _view__WIRE_8_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_8_opcode = bypass_9 ? _view__WIRE_8_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_8_param = bypass_9 ? _view__WIRE_8_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_8_size = bypass_9 ? _view__WIRE_8_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [7:0] _view__T_8_source = bypass_9 ? _view__WIRE_8_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [12:0] _view__T_8_tag = bypass_9 ? _view__WIRE_8_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_8_offset = bypass_9 ? _view__WIRE_8_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_8_put = bypass_9 ? _view__WIRE_8_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_8_io_allocate_bits_repeat_T = mshrs_8_io_allocate_bits_tag == _mshrs_8_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_8_io_allocate_valid_T = sel_8 & will_reload_9; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_10 = _requests_io_valid[9]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_10 = _requests_io_valid[21]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_84 = b_pop_10; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_10 = _requests_io_valid[33]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_81 = lowerMatches1[9]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_82 = c_pop_10 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_83 = ~c_pop_10; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_85 = ~b_pop_10; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_86 = ~a_pop_10; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_87 = _bypassMatches_T_84 ? _bypassMatches_T_85 : _bypassMatches_T_86; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_88 = _bypassMatches_T_82 ? _bypassMatches_T_83 : _bypassMatches_T_87; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_10 = _bypassMatches_T_81 & _bypassMatches_T_88; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_10 = a_pop_10 | b_pop_10; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_10 = _may_pop_T_10 | c_pop_10; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_10 = _bypass_T_10 & bypassMatches_10; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_10 = may_pop_10 | bypass_10; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_10 = _mshrs_9_io_schedule_bits_reload & _will_reload_T_10; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_9_prio_0 = bypass_10 ? _view__WIRE_9_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_9_prio_1 = ~bypass_10 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_9_prio_2 = bypass_10 ? _view__WIRE_9_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_9_control = bypass_10 ? _view__WIRE_9_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_9_opcode = bypass_10 ? _view__WIRE_9_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_9_param = bypass_10 ? _view__WIRE_9_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_9_size = bypass_10 ? _view__WIRE_9_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [7:0] _view__T_9_source = bypass_10 ? _view__WIRE_9_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [12:0] _view__T_9_tag = bypass_10 ? _view__WIRE_9_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_9_offset = bypass_10 ? _view__WIRE_9_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_9_put = bypass_10 ? _view__WIRE_9_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_9_io_allocate_bits_repeat_T = mshrs_9_io_allocate_bits_tag == _mshrs_9_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70]
wire _mshrs_9_io_allocate_valid_T = sel_9 & will_reload_10; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_11 = _requests_io_valid[10]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_11 = _requests_io_valid[22]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_92 = b_pop_11; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_11 = _requests_io_valid[34]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_89 = lowerMatches1[10]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_90 = c_pop_11 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_91 = ~c_pop_11; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_93 = ~b_pop_11; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_94 = ~a_pop_11; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_95 = _bypassMatches_T_92 ? _bypassMatches_T_93 : _bypassMatches_T_94; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_96 = _bypassMatches_T_90 ? _bypassMatches_T_91 : _bypassMatches_T_95; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_11 = _bypassMatches_T_89 & _bypassMatches_T_96; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_11 = a_pop_11 | b_pop_11; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_11 = _may_pop_T_11 | c_pop_11; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_11 = _bypass_T_11 & bypassMatches_11; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_11 = may_pop_11 | bypass_11; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_11 = _mshrs_10_io_schedule_bits_reload & _will_reload_T_11; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_10_prio_0 = bypass_11 ? _view__WIRE_10_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_10_prio_1 = ~bypass_11 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_10_prio_2 = bypass_11 ? _view__WIRE_10_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_10_control = bypass_11 ? _view__WIRE_10_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_10_opcode = bypass_11 ? _view__WIRE_10_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_10_param = bypass_11 ? _view__WIRE_10_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_10_size = bypass_11 ? _view__WIRE_10_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [7:0] _view__T_10_source = bypass_11 ? _view__WIRE_10_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [12:0] _view__T_10_tag = bypass_11 ? _view__WIRE_10_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_10_offset = bypass_11 ? _view__WIRE_10_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_10_put = bypass_11 ? _view__WIRE_10_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_10_io_allocate_bits_repeat_T = mshrs_10_io_allocate_bits_tag == _mshrs_10_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70, :287:131, :289:74]
wire _mshrs_10_io_allocate_valid_T = sel_10 & will_reload_11; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire a_pop_12 = _requests_io_valid[11]; // @[Scheduler.scala:70:24, :225:34]
wire b_pop_12 = _requests_io_valid[23]; // @[Scheduler.scala:70:24, :226:34]
wire _bypassMatches_T_100 = b_pop_12; // @[Scheduler.scala:226:34, :229:78]
wire c_pop_12 = _requests_io_valid[35]; // @[Scheduler.scala:70:24, :227:34]
wire _bypassMatches_T_97 = lowerMatches1[11]; // @[Scheduler.scala:200:8, :228:38]
wire _bypassMatches_T_98 = c_pop_12 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35]
wire _bypassMatches_T_99 = ~c_pop_12; // @[Scheduler.scala:227:34, :229:60]
wire _bypassMatches_T_101 = ~b_pop_12; // @[Scheduler.scala:226:34, :229:103]
wire _bypassMatches_T_102 = ~a_pop_12; // @[Scheduler.scala:225:34, :229:111]
wire _bypassMatches_T_103 = _bypassMatches_T_100 ? _bypassMatches_T_101 : _bypassMatches_T_102; // @[Scheduler.scala:229:{71,78,103,111}]
wire _bypassMatches_T_104 = _bypassMatches_T_98 ? _bypassMatches_T_99 : _bypassMatches_T_103; // @[Scheduler.scala:229:{28,35,60,71}]
wire bypassMatches_12 = _bypassMatches_T_97 & _bypassMatches_T_104; // @[Scheduler.scala:228:{38,42}, :229:28]
wire _may_pop_T_12 = a_pop_12 | b_pop_12; // @[Scheduler.scala:225:34, :226:34, :230:25]
wire may_pop_12 = _may_pop_T_12 | c_pop_12; // @[Scheduler.scala:227:34, :230:{25,34}]
wire bypass_12 = _bypass_T_12 & bypassMatches_12; // @[Scheduler.scala:228:42, :231:{32,41}]
wire _will_reload_T_12 = may_pop_12 | bypass_12; // @[Scheduler.scala:230:34, :231:41, :232:61]
wire will_reload_12 = _mshrs_11_io_schedule_bits_reload & _will_reload_T_12; // @[Scheduler.scala:71:46, :232:{49,61}]
wire _view__T_11_prio_0 = bypass_12 ? _view__WIRE_11_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_11_prio_1 = ~bypass_12 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78]
wire _view__T_11_prio_2 = bypass_12 ? _view__WIRE_11_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _view__T_11_control = bypass_12 ? _view__WIRE_11_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_11_opcode = bypass_12 ? _view__WIRE_11_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_11_param = bypass_12 ? _view__WIRE_11_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [2:0] _view__T_11_size = bypass_12 ? _view__WIRE_11_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [7:0] _view__T_11_source = bypass_12 ? _view__WIRE_11_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [12:0] _view__T_11_tag = bypass_12 ? _view__WIRE_11_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_11_offset = bypass_12 ? _view__WIRE_11_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire [5:0] _view__T_11_put = bypass_12 ? _view__WIRE_11_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}]
wire _mshrs_11_io_allocate_bits_repeat_T = mshrs_11_io_allocate_bits_tag == _mshrs_11_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70, :295:103, :297:73]
wire _mshrs_11_io_allocate_valid_T = sel_11 & will_reload_12; // @[Scheduler.scala:223:28, :232:49, :236:32]
wire [35:0] _prio_requests_T = ~_requests_io_valid; // @[Scheduler.scala:70:24, :240:25]
wire [23:0] _prio_requests_T_1 = _requests_io_valid[35:12]; // @[Scheduler.scala:70:24, :240:65]
wire [35:0] _prio_requests_T_2 = {_prio_requests_T[35:24], _prio_requests_T[23:0] | _prio_requests_T_1}; // @[Scheduler.scala:240:{25,44,65}]
wire [11:0] _prio_requests_T_3 = _requests_io_valid[35:24]; // @[Scheduler.scala:70:24, :240:103]
wire [35:0] _prio_requests_T_4 = {_prio_requests_T_2[35:12], _prio_requests_T_2[11:0] | _prio_requests_T_3}; // @[Scheduler.scala:240:{44,82,103}]
wire [35:0] prio_requests = ~_prio_requests_T_4; // @[Scheduler.scala:240:{23,82}]
wire [35:0] _pop_index_T = {pop_index_hi, mshr_selectOH}; // @[Scheduler.scala:121:70, :241:31]
wire [35:0] _pop_index_T_1 = _pop_index_T & prio_requests; // @[Scheduler.scala:240:23, :241:{31,77}]
wire [3:0] pop_index_hi_1 = _pop_index_T_1[35:32]; // @[OneHot.scala:30:18]
wire [31:0] pop_index_lo = _pop_index_T_1[31:0]; // @[OneHot.scala:31:18]
wire _pop_index_T_2 = |pop_index_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [31:0] _pop_index_T_3 = {28'h0, pop_index_hi_1} | pop_index_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [15:0] pop_index_hi_2 = _pop_index_T_3[31:16]; // @[OneHot.scala:30:18, :32:28]
wire [15:0] pop_index_lo_1 = _pop_index_T_3[15:0]; // @[OneHot.scala:31:18, :32:28]
wire _pop_index_T_4 = |pop_index_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [15:0] _pop_index_T_5 = pop_index_hi_2 | pop_index_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [7:0] pop_index_hi_3 = _pop_index_T_5[15:8]; // @[OneHot.scala:30:18, :32:28]
wire [7:0] pop_index_lo_2 = _pop_index_T_5[7:0]; // @[OneHot.scala:31:18, :32:28]
wire _pop_index_T_6 = |pop_index_hi_3; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _pop_index_T_7 = pop_index_hi_3 | pop_index_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] pop_index_hi_4 = _pop_index_T_7[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] pop_index_lo_3 = _pop_index_T_7[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _pop_index_T_8 = |pop_index_hi_4; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _pop_index_T_9 = pop_index_hi_4 | pop_index_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] pop_index_hi_5 = _pop_index_T_9[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] pop_index_lo_4 = _pop_index_T_9[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _pop_index_T_10 = |pop_index_hi_5; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _pop_index_T_11 = pop_index_hi_5 | pop_index_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _pop_index_T_12 = _pop_index_T_11[1]; // @[OneHot.scala:32:28]
wire [1:0] _pop_index_T_13 = {_pop_index_T_10, _pop_index_T_12}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _pop_index_T_14 = {_pop_index_T_8, _pop_index_T_13}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _pop_index_T_15 = {_pop_index_T_6, _pop_index_T_14}; // @[OneHot.scala:32:{10,14}]
wire [4:0] _pop_index_T_16 = {_pop_index_T_4, _pop_index_T_15}; // @[OneHot.scala:32:{10,14}]
wire [5:0] pop_index = {_pop_index_T_2, _pop_index_T_16}; // @[OneHot.scala:32:{10,14}]
wire lb_tag_mismatch = scheduleTag != _requests_io_data_tag; // @[Mux.scala:30:73]
wire mshr_uses_directory_assuming_no_bypass = _mshr_uses_directory_assuming_no_bypass_T & lb_tag_mismatch; // @[Scheduler.scala:246:37, :247:{64,75}]
wire mshr_uses_directory_for_lb = will_pop & lb_tag_mismatch; // @[Scheduler.scala:215:45, :246:37, :248:45]
wire [12:0] _mshr_uses_directory_T = bypass ? request_bits_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :163:21, :213:39, :249:63]
wire _mshr_uses_directory_T_1 = scheduleTag != _mshr_uses_directory_T; // @[Mux.scala:30:73]
wire mshr_uses_directory = will_reload & _mshr_uses_directory_T_1; // @[Scheduler.scala:214:37, :249:{41,56}]
wire [1:0] mshr_validOH_lo_lo_hi = {_mshrs_2_io_status_valid, _mshrs_1_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [2:0] mshr_validOH_lo_lo = {mshr_validOH_lo_lo_hi, _mshrs_0_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [1:0] mshr_validOH_lo_hi_hi = {_mshrs_5_io_status_valid, _mshrs_4_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [2:0] mshr_validOH_lo_hi = {mshr_validOH_lo_hi_hi, _mshrs_3_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [5:0] mshr_validOH_lo = {mshr_validOH_lo_hi, mshr_validOH_lo_lo}; // @[Scheduler.scala:252:25]
wire [1:0] mshr_validOH_hi_lo_hi = {_mshrs_8_io_status_valid, _mshrs_7_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [2:0] mshr_validOH_hi_lo = {mshr_validOH_hi_lo_hi, _mshrs_6_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [1:0] mshr_validOH_hi_hi_hi = {_mshrs_11_io_status_valid, _mshrs_10_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [2:0] mshr_validOH_hi_hi = {mshr_validOH_hi_hi_hi, _mshrs_9_io_status_valid}; // @[Scheduler.scala:71:46, :252:25]
wire [5:0] mshr_validOH_hi = {mshr_validOH_hi_hi, mshr_validOH_hi_lo}; // @[Scheduler.scala:252:25]
wire [11:0] mshr_validOH = {mshr_validOH_hi, mshr_validOH_lo}; // @[Scheduler.scala:252:25]
wire [11:0] _mshr_free_T = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20]
wire [11:0] _mshr_free_T_1 = _mshr_free_T & prioFilter; // @[Scheduler.scala:182:23, :253:{20,34}]
wire mshr_free = |_mshr_free_T_1; // @[Scheduler.scala:253:{34,48}]
wire bypassQueue = schedule_reload & bypassMatches; // @[Mux.scala:30:73]
wire _request_alloc_cases_T = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16]
wire _request_alloc_cases_T_1 = alloc & _request_alloc_cases_T; // @[Scheduler.scala:173:15, :258:{13,16}]
wire _request_alloc_cases_T_2 = _request_alloc_cases_T_1 & mshr_free; // @[Scheduler.scala:253:48, :258:{13,56}]
wire _request_alloc_cases_T_9 = _request_alloc_cases_T_2; // @[Scheduler.scala:258:{56,70}]
wire _request_alloc_cases_T_3 = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :259:16]
wire _request_alloc_cases_T_5 = ~_mshrs_10_io_status_valid; // @[Scheduler.scala:71:46, :259:59]
wire _request_alloc_cases_T_7 = ~_mshrs_11_io_status_valid; // @[Scheduler.scala:71:46, :259:87]
wire _request_alloc_cases_T_10 = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :260:16]
wire _request_alloc_cases_T_11 = nestC & _request_alloc_cases_T_10; // @[Scheduler.scala:180:70, :260:{13,16}]
wire _request_alloc_cases_T_12 = ~_mshrs_11_io_status_valid; // @[Scheduler.scala:71:46, :259:87, :260:59]
wire _request_alloc_cases_T_13 = _request_alloc_cases_T_11 & _request_alloc_cases_T_12; // @[Scheduler.scala:260:{13,56,59}]
wire request_alloc_cases = _request_alloc_cases_T_9 | _request_alloc_cases_T_13; // @[Scheduler.scala:258:70, :259:112, :260:56]
wire _request_ready_T = bypassQueue | _requests_io_push_ready; // @[Scheduler.scala:70:24, :256:37, :261:66]
wire _request_ready_T_1 = queue & _request_ready_T; // @[Scheduler.scala:185:63, :261:{50,66}]
assign _request_ready_T_2 = request_alloc_cases | _request_ready_T_1; // @[Scheduler.scala:259:112, :261:{40,50}]
assign request_ready = _request_ready_T_2; // @[Scheduler.scala:163:21, :261:40]
wire alloc_uses_directory = request_valid & request_alloc_cases; // @[Scheduler.scala:163:21, :259:112, :262:44]
wire _directory_io_read_valid_T = mshr_uses_directory | alloc_uses_directory; // @[Scheduler.scala:249:41, :262:44, :265:50]
wire [9:0] _directory_io_read_bits_set_T = mshr_uses_directory_for_lb ? scheduleSet : request_bits_set; // @[Mux.scala:30:73]
wire [12:0] _directory_io_read_bits_tag_T = mshr_uses_directory_for_lb ? _requests_io_data_tag : request_bits_tag; // @[Scheduler.scala:70:24, :163:21, :248:45, :267:36]
wire _requests_io_push_valid_T_1 = ~bypassQueue; // @[Scheduler.scala:256:37, :270:55]
wire _requests_io_push_valid_T_2 = _requests_io_push_valid_T & _requests_io_push_valid_T_1; // @[Scheduler.scala:270:{43,52,55}]
wire [3:0] requests_io_push_bits_index_hi = _requests_io_push_bits_index_T[11:8]; // @[OneHot.scala:30:18]
wire [7:0] requests_io_push_bits_index_lo = _requests_io_push_bits_index_T[7:0]; // @[OneHot.scala:31:18]
wire _requests_io_push_bits_index_T_1 = |requests_io_push_bits_index_hi; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _requests_io_push_bits_index_T_2 = {4'h0, requests_io_push_bits_index_hi} | requests_io_push_bits_index_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] requests_io_push_bits_index_hi_1 = _requests_io_push_bits_index_T_2[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] requests_io_push_bits_index_lo_1 = _requests_io_push_bits_index_T_2[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_3 = |requests_io_push_bits_index_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _requests_io_push_bits_index_T_4 = requests_io_push_bits_index_hi_1 | requests_io_push_bits_index_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] requests_io_push_bits_index_hi_2 = _requests_io_push_bits_index_T_4[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] requests_io_push_bits_index_lo_2 = _requests_io_push_bits_index_T_4[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_5 = |requests_io_push_bits_index_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _requests_io_push_bits_index_T_6 = requests_io_push_bits_index_hi_2 | requests_io_push_bits_index_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _requests_io_push_bits_index_T_7 = _requests_io_push_bits_index_T_6[1]; // @[OneHot.scala:32:28]
wire [1:0] _requests_io_push_bits_index_T_8 = {_requests_io_push_bits_index_T_5, _requests_io_push_bits_index_T_7}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _requests_io_push_bits_index_T_9 = {_requests_io_push_bits_index_T_3, _requests_io_push_bits_index_T_8}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _requests_io_push_bits_index_T_10 = {_requests_io_push_bits_index_T_1, _requests_io_push_bits_index_T_9}; // @[OneHot.scala:32:{10,14}]
wire [23:0] _requests_io_push_bits_index_T_11 = {lowerMatches1, 12'h0}; // @[Scheduler.scala:200:8, :275:30]
wire [7:0] requests_io_push_bits_index_hi_3 = _requests_io_push_bits_index_T_11[23:16]; // @[OneHot.scala:30:18]
wire [15:0] requests_io_push_bits_index_lo_3 = _requests_io_push_bits_index_T_11[15:0]; // @[OneHot.scala:31:18]
wire _requests_io_push_bits_index_T_12 = |requests_io_push_bits_index_hi_3; // @[OneHot.scala:30:18, :32:14]
wire [15:0] _requests_io_push_bits_index_T_13 = {8'h0, requests_io_push_bits_index_hi_3} | requests_io_push_bits_index_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [7:0] requests_io_push_bits_index_hi_4 = _requests_io_push_bits_index_T_13[15:8]; // @[OneHot.scala:30:18, :32:28]
wire [7:0] requests_io_push_bits_index_lo_4 = _requests_io_push_bits_index_T_13[7:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_14 = |requests_io_push_bits_index_hi_4; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _requests_io_push_bits_index_T_15 = requests_io_push_bits_index_hi_4 | requests_io_push_bits_index_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] requests_io_push_bits_index_hi_5 = _requests_io_push_bits_index_T_15[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] requests_io_push_bits_index_lo_5 = _requests_io_push_bits_index_T_15[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_16 = |requests_io_push_bits_index_hi_5; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _requests_io_push_bits_index_T_17 = requests_io_push_bits_index_hi_5 | requests_io_push_bits_index_lo_5; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] requests_io_push_bits_index_hi_6 = _requests_io_push_bits_index_T_17[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] requests_io_push_bits_index_lo_6 = _requests_io_push_bits_index_T_17[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_18 = |requests_io_push_bits_index_hi_6; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _requests_io_push_bits_index_T_19 = requests_io_push_bits_index_hi_6 | requests_io_push_bits_index_lo_6; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _requests_io_push_bits_index_T_20 = _requests_io_push_bits_index_T_19[1]; // @[OneHot.scala:32:28]
wire [1:0] _requests_io_push_bits_index_T_21 = {_requests_io_push_bits_index_T_18, _requests_io_push_bits_index_T_20}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _requests_io_push_bits_index_T_22 = {_requests_io_push_bits_index_T_16, _requests_io_push_bits_index_T_21}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _requests_io_push_bits_index_T_23 = {_requests_io_push_bits_index_T_14, _requests_io_push_bits_index_T_22}; // @[OneHot.scala:32:{10,14}]
wire [4:0] _requests_io_push_bits_index_T_24 = {_requests_io_push_bits_index_T_12, _requests_io_push_bits_index_T_23}; // @[OneHot.scala:32:{10,14}]
wire [35:0] _requests_io_push_bits_index_T_25 = {lowerMatches1, 24'h0}; // @[Scheduler.scala:200:8, :276:30]
wire [3:0] requests_io_push_bits_index_hi_7 = _requests_io_push_bits_index_T_25[35:32]; // @[OneHot.scala:30:18]
wire [31:0] requests_io_push_bits_index_lo_7 = _requests_io_push_bits_index_T_25[31:0]; // @[OneHot.scala:31:18]
wire _requests_io_push_bits_index_T_26 = |requests_io_push_bits_index_hi_7; // @[OneHot.scala:30:18, :32:14]
wire [31:0] _requests_io_push_bits_index_T_27 = {28'h0, requests_io_push_bits_index_hi_7} | requests_io_push_bits_index_lo_7; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [15:0] requests_io_push_bits_index_hi_8 = _requests_io_push_bits_index_T_27[31:16]; // @[OneHot.scala:30:18, :32:28]
wire [15:0] requests_io_push_bits_index_lo_8 = _requests_io_push_bits_index_T_27[15:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_28 = |requests_io_push_bits_index_hi_8; // @[OneHot.scala:30:18, :32:14]
wire [15:0] _requests_io_push_bits_index_T_29 = requests_io_push_bits_index_hi_8 | requests_io_push_bits_index_lo_8; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [7:0] requests_io_push_bits_index_hi_9 = _requests_io_push_bits_index_T_29[15:8]; // @[OneHot.scala:30:18, :32:28]
wire [7:0] requests_io_push_bits_index_lo_9 = _requests_io_push_bits_index_T_29[7:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_30 = |requests_io_push_bits_index_hi_9; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _requests_io_push_bits_index_T_31 = requests_io_push_bits_index_hi_9 | requests_io_push_bits_index_lo_9; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] requests_io_push_bits_index_hi_10 = _requests_io_push_bits_index_T_31[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] requests_io_push_bits_index_lo_10 = _requests_io_push_bits_index_T_31[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_32 = |requests_io_push_bits_index_hi_10; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _requests_io_push_bits_index_T_33 = requests_io_push_bits_index_hi_10 | requests_io_push_bits_index_lo_10; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] requests_io_push_bits_index_hi_11 = _requests_io_push_bits_index_T_33[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] requests_io_push_bits_index_lo_11 = _requests_io_push_bits_index_T_33[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _requests_io_push_bits_index_T_34 = |requests_io_push_bits_index_hi_11; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _requests_io_push_bits_index_T_35 = requests_io_push_bits_index_hi_11 | requests_io_push_bits_index_lo_11; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _requests_io_push_bits_index_T_36 = _requests_io_push_bits_index_T_35[1]; // @[OneHot.scala:32:28]
wire [1:0] _requests_io_push_bits_index_T_37 = {_requests_io_push_bits_index_T_34, _requests_io_push_bits_index_T_36}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _requests_io_push_bits_index_T_38 = {_requests_io_push_bits_index_T_32, _requests_io_push_bits_index_T_37}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _requests_io_push_bits_index_T_39 = {_requests_io_push_bits_index_T_30, _requests_io_push_bits_index_T_38}; // @[OneHot.scala:32:{10,14}]
wire [4:0] _requests_io_push_bits_index_T_40 = {_requests_io_push_bits_index_T_28, _requests_io_push_bits_index_T_39}; // @[OneHot.scala:32:{10,14}]
wire [5:0] _requests_io_push_bits_index_T_41 = {_requests_io_push_bits_index_T_26, _requests_io_push_bits_index_T_40}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _requests_io_push_bits_index_T_42 = request_bits_prio_0 ? _requests_io_push_bits_index_T_10 : 4'h0; // @[OneHot.scala:32:10]
wire [5:0] _requests_io_push_bits_index_T_44 = request_bits_prio_2 ? _requests_io_push_bits_index_T_41 : 6'h0; // @[OneHot.scala:32:10]
wire [4:0] _requests_io_push_bits_index_T_45 = {1'h0, _requests_io_push_bits_index_T_42}; // @[Mux.scala:30:73]
wire [5:0] _requests_io_push_bits_index_T_46 = {1'h0, _requests_io_push_bits_index_T_45} | _requests_io_push_bits_index_T_44; // @[Mux.scala:30:73]
wire [5:0] _requests_io_push_bits_index_WIRE = _requests_io_push_bits_index_T_46; // @[Mux.scala:30:73]
wire [11:0] _mshr_insertOH_T = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20, :278:32]
wire [12:0] _mshr_insertOH_T_1 = {_mshr_insertOH_T, 1'h0}; // @[package.scala:253:48]
wire [11:0] _mshr_insertOH_T_2 = _mshr_insertOH_T_1[11:0]; // @[package.scala:253:{48,53}]
wire [11:0] _mshr_insertOH_T_3 = _mshr_insertOH_T | _mshr_insertOH_T_2; // @[package.scala:253:{43,53}]
wire [13:0] _mshr_insertOH_T_4 = {_mshr_insertOH_T_3, 2'h0}; // @[package.scala:253:{43,48}]
wire [11:0] _mshr_insertOH_T_5 = _mshr_insertOH_T_4[11:0]; // @[package.scala:253:{48,53}]
wire [11:0] _mshr_insertOH_T_6 = _mshr_insertOH_T_3 | _mshr_insertOH_T_5; // @[package.scala:253:{43,53}]
wire [15:0] _mshr_insertOH_T_7 = {_mshr_insertOH_T_6, 4'h0}; // @[package.scala:253:{43,48}]
wire [11:0] _mshr_insertOH_T_8 = _mshr_insertOH_T_7[11:0]; // @[package.scala:253:{48,53}]
wire [11:0] _mshr_insertOH_T_9 = _mshr_insertOH_T_6 | _mshr_insertOH_T_8; // @[package.scala:253:{43,53}]
wire [19:0] _mshr_insertOH_T_10 = {_mshr_insertOH_T_9, 8'h0}; // @[package.scala:253:{43,48}]
wire [11:0] _mshr_insertOH_T_11 = _mshr_insertOH_T_10[11:0]; // @[package.scala:253:{48,53}]
wire [11:0] _mshr_insertOH_T_12 = _mshr_insertOH_T_9 | _mshr_insertOH_T_11; // @[package.scala:253:{43,53}]
wire [11:0] _mshr_insertOH_T_13 = _mshr_insertOH_T_12; // @[package.scala:253:43, :254:17]
wire [12:0] _mshr_insertOH_T_14 = {_mshr_insertOH_T_13, 1'h0}; // @[package.scala:254:17]
wire [12:0] _mshr_insertOH_T_15 = ~_mshr_insertOH_T_14; // @[Scheduler.scala:278:{23,47}]
wire [11:0] _mshr_insertOH_T_16 = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20, :278:55]
wire [12:0] _mshr_insertOH_T_17 = {1'h0, _mshr_insertOH_T_15[11:0] & _mshr_insertOH_T_16}; // @[Scheduler.scala:278:{23,53,55}]
wire [12:0] mshr_insertOH = {1'h0, _mshr_insertOH_T_17[11:0] & prioFilter}; // @[Scheduler.scala:182:23, :278:{53,69}]
wire _T_76 = request_valid & alloc; // @[Scheduler.scala:163:21, :173:15, :280:25]
wire _T_35 = _T_76 & mshr_insertOH[0] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_0_io_allocate_bits_tag = _T_35 ? request_bits_tag : _view__T_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_39 = _T_76 & mshr_insertOH[1] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_1_io_allocate_bits_tag = _T_39 ? request_bits_tag : _view__T_1_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_43 = _T_76 & mshr_insertOH[2] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_2_io_allocate_bits_tag = _T_43 ? request_bits_tag : _view__T_2_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_47 = _T_76 & mshr_insertOH[3] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_3_io_allocate_bits_tag = _T_47 ? request_bits_tag : _view__T_3_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_51 = _T_76 & mshr_insertOH[4] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_4_io_allocate_bits_tag = _T_51 ? request_bits_tag : _view__T_4_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_55 = _T_76 & mshr_insertOH[5] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_5_io_allocate_bits_tag = _T_55 ? request_bits_tag : _view__T_5_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_59 = _T_76 & mshr_insertOH[6] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_6_io_allocate_bits_tag = _T_59 ? request_bits_tag : _view__T_6_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_63 = _T_76 & mshr_insertOH[7] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_7_io_allocate_bits_tag = _T_63 ? request_bits_tag : _view__T_7_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_67 = _T_76 & mshr_insertOH[8] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_8_io_allocate_bits_tag = _T_67 ? request_bits_tag : _view__T_8_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_71 = _T_76 & mshr_insertOH[9] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_9_io_allocate_bits_tag = _T_71 ? request_bits_tag : _view__T_9_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70]
wire _T_75 = _T_76 & mshr_insertOH[10] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}]
assign mshrs_10_io_allocate_bits_tag = _T_75 ? request_bits_tag : _view__T_10_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70, :287:131, :289:74]
wire _T_95 = request_valid & nestC & ~_mshrs_11_io_status_valid & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:71:46, :163:21, :180:70, :193:33, :247:75, :258:16, :259:87, :295:{32,59}]
wire _GEN_3 = _T_95 | _T_76 & mshr_insertOH[11] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:193:33, :236:25, :247:75, :258:16, :278:69, :279:18, :280:{25,34,39,83}, :281:27, :295:{32,59,103}, :296:30]
assign mshrs_11_io_allocate_bits_tag = _GEN_3 ? request_bits_tag : _view__T_11_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :236:25, :280:83, :281:27, :282:70, :295:103, :296:30, :297:73] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_252 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_252( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_18 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_18
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_18( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
output io_q // @[ShiftReg.scala:36:14]
);
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire io_d = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire _output_T_1 = 1'h1; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_18 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module SBToTL :
input clock : Clock
input reset : Reset
output auto : { out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<7>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}}
output io : { flip rdEn : UInt<1>, flip wrEn : UInt<1>, flip addrIn : UInt<128>, flip dataIn : UInt<128>, flip sizeIn : UInt<3>, rdLegal : UInt<1>, wrLegal : UInt<1>, rdDone : UInt<1>, wrDone : UInt<1>, respError : UInt<1>, dataOut : UInt<8>, rdLoad : UInt<1>[8], sbStateOut : UInt<3>}
input rf_reset : Reset
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<7>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
regreset sbState : UInt, clock, reset, UInt<1>(0h0)
inst d_q of Queue2_TLBundleD_a32d8s1k7z4u
connect d_q.clock, clock
connect d_q.reset, reset
connect d_q.io.enq.valid, nodeOut.d.valid
connect d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect d_q.io.enq.bits.data, nodeOut.d.bits.data
connect d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect d_q.io.enq.bits.source, nodeOut.d.bits.source
connect d_q.io.enq.bits.size, nodeOut.d.bits.size
connect d_q.io.enq.bits.param, nodeOut.d.bits.param
connect d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, d_q.io.enq.ready
node _q_io_deq_ready_T = eq(sbState, UInt<2>(0h3))
node _q_io_deq_ready_T_1 = eq(sbState, UInt<3>(0h4))
node _q_io_deq_ready_T_2 = or(_q_io_deq_ready_T, _q_io_deq_ready_T_1)
connect d_q.io.deq.ready, _q_io_deq_ready_T_2
wire muxedData : UInt<8>
connect muxedData, UInt<8>(0h0)
regreset counter : UInt<4>, clock, reset, UInt<4>(0h0)
wire vecData : UInt<8>[8]
node _vecData_0_T = bits(io.dataIn, 7, 0)
connect vecData[0], _vecData_0_T
node _vecData_1_T = bits(io.dataIn, 15, 8)
connect vecData[1], _vecData_1_T
node _vecData_2_T = bits(io.dataIn, 23, 16)
connect vecData[2], _vecData_2_T
node _vecData_3_T = bits(io.dataIn, 31, 24)
connect vecData[3], _vecData_3_T
node _vecData_4_T = bits(io.dataIn, 39, 32)
connect vecData[4], _vecData_4_T
node _vecData_5_T = bits(io.dataIn, 47, 40)
connect vecData[5], _vecData_5_T
node _vecData_6_T = bits(io.dataIn, 55, 48)
connect vecData[6], _vecData_6_T
node _vecData_7_T = bits(io.dataIn, 63, 56)
connect vecData[7], _vecData_7_T
node _muxedData_T = bits(counter, 2, 0)
connect muxedData, vecData[_muxedData_T]
node _rdLegal_addr_T = leq(UInt<1>(0h0), io.sizeIn)
node _rdLegal_addr_T_1 = leq(io.sizeIn, UInt<2>(0h3))
node _rdLegal_addr_T_2 = and(_rdLegal_addr_T, _rdLegal_addr_T_1)
node _rdLegal_addr_T_3 = or(UInt<1>(0h1), _rdLegal_addr_T_2)
node _rdLegal_addr_T_4 = xor(io.addrIn, UInt<1>(0h0))
node _rdLegal_addr_T_5 = cvt(_rdLegal_addr_T_4)
node _rdLegal_addr_T_6 = and(_rdLegal_addr_T_5, asSInt(UInt<14>(0h2000)))
node _rdLegal_addr_T_7 = asSInt(_rdLegal_addr_T_6)
node _rdLegal_addr_T_8 = eq(_rdLegal_addr_T_7, asSInt(UInt<1>(0h0)))
node _rdLegal_addr_T_9 = xor(io.addrIn, UInt<14>(0h3000))
node _rdLegal_addr_T_10 = cvt(_rdLegal_addr_T_9)
node _rdLegal_addr_T_11 = and(_rdLegal_addr_T_10, asSInt(UInt<13>(0h1000)))
node _rdLegal_addr_T_12 = asSInt(_rdLegal_addr_T_11)
node _rdLegal_addr_T_13 = eq(_rdLegal_addr_T_12, asSInt(UInt<1>(0h0)))
node _rdLegal_addr_T_14 = xor(io.addrIn, UInt<17>(0h10000))
node _rdLegal_addr_T_15 = cvt(_rdLegal_addr_T_14)
node _rdLegal_addr_T_16 = and(_rdLegal_addr_T_15, asSInt(UInt<17>(0h10000)))
node _rdLegal_addr_T_17 = asSInt(_rdLegal_addr_T_16)
node _rdLegal_addr_T_18 = eq(_rdLegal_addr_T_17, asSInt(UInt<1>(0h0)))
node _rdLegal_addr_T_19 = xor(io.addrIn, UInt<21>(0h100000))
node _rdLegal_addr_T_20 = cvt(_rdLegal_addr_T_19)
node _rdLegal_addr_T_21 = and(_rdLegal_addr_T_20, asSInt(UInt<18>(0h2f000)))
node _rdLegal_addr_T_22 = asSInt(_rdLegal_addr_T_21)
node _rdLegal_addr_T_23 = eq(_rdLegal_addr_T_22, asSInt(UInt<1>(0h0)))
node _rdLegal_addr_T_24 = xor(io.addrIn, UInt<26>(0h2000000))
node _rdLegal_addr_T_25 = cvt(_rdLegal_addr_T_24)
node _rdLegal_addr_T_26 = and(_rdLegal_addr_T_25, asSInt(UInt<17>(0h10000)))
node _rdLegal_addr_T_27 = asSInt(_rdLegal_addr_T_26)
node _rdLegal_addr_T_28 = eq(_rdLegal_addr_T_27, asSInt(UInt<1>(0h0)))
node _rdLegal_addr_T_29 = xor(io.addrIn, UInt<26>(0h2010000))
node _rdLegal_addr_T_30 = cvt(_rdLegal_addr_T_29)
node _rdLegal_addr_T_31 = and(_rdLegal_addr_T_30, asSInt(UInt<13>(0h1000)))
node _rdLegal_addr_T_32 = asSInt(_rdLegal_addr_T_31)
node _rdLegal_addr_T_33 = eq(_rdLegal_addr_T_32, asSInt(UInt<1>(0h0)))
node _rdLegal_addr_T_34 = xor(io.addrIn, UInt<28>(0h8000000))
node _rdLegal_addr_T_35 = cvt(_rdLegal_addr_T_34)
node _rdLegal_addr_T_36 = and(_rdLegal_addr_T_35, asSInt(UInt<17>(0h10000)))
node _rdLegal_addr_T_37 = asSInt(_rdLegal_addr_T_36)
node _rdLegal_addr_T_38 = eq(_rdLegal_addr_T_37, asSInt(UInt<1>(0h0)))
node _rdLegal_addr_T_39 = xor(io.addrIn, UInt<28>(0hc000000))
node _rdLegal_addr_T_40 = cvt(_rdLegal_addr_T_39)
node _rdLegal_addr_T_41 = and(_rdLegal_addr_T_40, asSInt(UInt<27>(0h4000000)))
node _rdLegal_addr_T_42 = asSInt(_rdLegal_addr_T_41)
node _rdLegal_addr_T_43 = eq(_rdLegal_addr_T_42, asSInt(UInt<1>(0h0)))
node _rdLegal_addr_T_44 = xor(io.addrIn, UInt<29>(0h10020000))
node _rdLegal_addr_T_45 = cvt(_rdLegal_addr_T_44)
node _rdLegal_addr_T_46 = and(_rdLegal_addr_T_45, asSInt(UInt<13>(0h1000)))
node _rdLegal_addr_T_47 = asSInt(_rdLegal_addr_T_46)
node _rdLegal_addr_T_48 = eq(_rdLegal_addr_T_47, asSInt(UInt<1>(0h0)))
node _rdLegal_addr_T_49 = xor(io.addrIn, UInt<32>(0h80000000))
node _rdLegal_addr_T_50 = cvt(_rdLegal_addr_T_49)
node _rdLegal_addr_T_51 = and(_rdLegal_addr_T_50, asSInt(UInt<29>(0h10000000)))
node _rdLegal_addr_T_52 = asSInt(_rdLegal_addr_T_51)
node _rdLegal_addr_T_53 = eq(_rdLegal_addr_T_52, asSInt(UInt<1>(0h0)))
node _rdLegal_addr_T_54 = or(_rdLegal_addr_T_8, _rdLegal_addr_T_13)
node _rdLegal_addr_T_55 = or(_rdLegal_addr_T_54, _rdLegal_addr_T_18)
node _rdLegal_addr_T_56 = or(_rdLegal_addr_T_55, _rdLegal_addr_T_23)
node _rdLegal_addr_T_57 = or(_rdLegal_addr_T_56, _rdLegal_addr_T_28)
node _rdLegal_addr_T_58 = or(_rdLegal_addr_T_57, _rdLegal_addr_T_33)
node _rdLegal_addr_T_59 = or(_rdLegal_addr_T_58, _rdLegal_addr_T_38)
node _rdLegal_addr_T_60 = or(_rdLegal_addr_T_59, _rdLegal_addr_T_43)
node _rdLegal_addr_T_61 = or(_rdLegal_addr_T_60, _rdLegal_addr_T_48)
node _rdLegal_addr_T_62 = or(_rdLegal_addr_T_61, _rdLegal_addr_T_53)
node _rdLegal_addr_T_63 = and(_rdLegal_addr_T_3, _rdLegal_addr_T_62)
node rdLegal_addr = or(UInt<1>(0h0), _rdLegal_addr_T_63)
node _wrLegal_addr_T = leq(UInt<1>(0h0), io.sizeIn)
node _wrLegal_addr_T_1 = leq(io.sizeIn, UInt<2>(0h3))
node _wrLegal_addr_T_2 = and(_wrLegal_addr_T, _wrLegal_addr_T_1)
node _wrLegal_addr_T_3 = or(UInt<1>(0h1), _wrLegal_addr_T_2)
node _wrLegal_addr_T_4 = xor(io.addrIn, UInt<1>(0h0))
node _wrLegal_addr_T_5 = cvt(_wrLegal_addr_T_4)
node _wrLegal_addr_T_6 = and(_wrLegal_addr_T_5, asSInt(UInt<14>(0h2000)))
node _wrLegal_addr_T_7 = asSInt(_wrLegal_addr_T_6)
node _wrLegal_addr_T_8 = eq(_wrLegal_addr_T_7, asSInt(UInt<1>(0h0)))
node _wrLegal_addr_T_9 = xor(io.addrIn, UInt<14>(0h3000))
node _wrLegal_addr_T_10 = cvt(_wrLegal_addr_T_9)
node _wrLegal_addr_T_11 = and(_wrLegal_addr_T_10, asSInt(UInt<13>(0h1000)))
node _wrLegal_addr_T_12 = asSInt(_wrLegal_addr_T_11)
node _wrLegal_addr_T_13 = eq(_wrLegal_addr_T_12, asSInt(UInt<1>(0h0)))
node _wrLegal_addr_T_14 = xor(io.addrIn, UInt<21>(0h100000))
node _wrLegal_addr_T_15 = cvt(_wrLegal_addr_T_14)
node _wrLegal_addr_T_16 = and(_wrLegal_addr_T_15, asSInt(UInt<18>(0h2f000)))
node _wrLegal_addr_T_17 = asSInt(_wrLegal_addr_T_16)
node _wrLegal_addr_T_18 = eq(_wrLegal_addr_T_17, asSInt(UInt<1>(0h0)))
node _wrLegal_addr_T_19 = xor(io.addrIn, UInt<26>(0h2000000))
node _wrLegal_addr_T_20 = cvt(_wrLegal_addr_T_19)
node _wrLegal_addr_T_21 = and(_wrLegal_addr_T_20, asSInt(UInt<17>(0h10000)))
node _wrLegal_addr_T_22 = asSInt(_wrLegal_addr_T_21)
node _wrLegal_addr_T_23 = eq(_wrLegal_addr_T_22, asSInt(UInt<1>(0h0)))
node _wrLegal_addr_T_24 = xor(io.addrIn, UInt<26>(0h2010000))
node _wrLegal_addr_T_25 = cvt(_wrLegal_addr_T_24)
node _wrLegal_addr_T_26 = and(_wrLegal_addr_T_25, asSInt(UInt<13>(0h1000)))
node _wrLegal_addr_T_27 = asSInt(_wrLegal_addr_T_26)
node _wrLegal_addr_T_28 = eq(_wrLegal_addr_T_27, asSInt(UInt<1>(0h0)))
node _wrLegal_addr_T_29 = xor(io.addrIn, UInt<28>(0h8000000))
node _wrLegal_addr_T_30 = cvt(_wrLegal_addr_T_29)
node _wrLegal_addr_T_31 = and(_wrLegal_addr_T_30, asSInt(UInt<17>(0h10000)))
node _wrLegal_addr_T_32 = asSInt(_wrLegal_addr_T_31)
node _wrLegal_addr_T_33 = eq(_wrLegal_addr_T_32, asSInt(UInt<1>(0h0)))
node _wrLegal_addr_T_34 = xor(io.addrIn, UInt<28>(0hc000000))
node _wrLegal_addr_T_35 = cvt(_wrLegal_addr_T_34)
node _wrLegal_addr_T_36 = and(_wrLegal_addr_T_35, asSInt(UInt<27>(0h4000000)))
node _wrLegal_addr_T_37 = asSInt(_wrLegal_addr_T_36)
node _wrLegal_addr_T_38 = eq(_wrLegal_addr_T_37, asSInt(UInt<1>(0h0)))
node _wrLegal_addr_T_39 = xor(io.addrIn, UInt<29>(0h10020000))
node _wrLegal_addr_T_40 = cvt(_wrLegal_addr_T_39)
node _wrLegal_addr_T_41 = and(_wrLegal_addr_T_40, asSInt(UInt<13>(0h1000)))
node _wrLegal_addr_T_42 = asSInt(_wrLegal_addr_T_41)
node _wrLegal_addr_T_43 = eq(_wrLegal_addr_T_42, asSInt(UInt<1>(0h0)))
node _wrLegal_addr_T_44 = xor(io.addrIn, UInt<32>(0h80000000))
node _wrLegal_addr_T_45 = cvt(_wrLegal_addr_T_44)
node _wrLegal_addr_T_46 = and(_wrLegal_addr_T_45, asSInt(UInt<29>(0h10000000)))
node _wrLegal_addr_T_47 = asSInt(_wrLegal_addr_T_46)
node _wrLegal_addr_T_48 = eq(_wrLegal_addr_T_47, asSInt(UInt<1>(0h0)))
node _wrLegal_addr_T_49 = or(_wrLegal_addr_T_8, _wrLegal_addr_T_13)
node _wrLegal_addr_T_50 = or(_wrLegal_addr_T_49, _wrLegal_addr_T_18)
node _wrLegal_addr_T_51 = or(_wrLegal_addr_T_50, _wrLegal_addr_T_23)
node _wrLegal_addr_T_52 = or(_wrLegal_addr_T_51, _wrLegal_addr_T_28)
node _wrLegal_addr_T_53 = or(_wrLegal_addr_T_52, _wrLegal_addr_T_33)
node _wrLegal_addr_T_54 = or(_wrLegal_addr_T_53, _wrLegal_addr_T_38)
node _wrLegal_addr_T_55 = or(_wrLegal_addr_T_54, _wrLegal_addr_T_43)
node _wrLegal_addr_T_56 = or(_wrLegal_addr_T_55, _wrLegal_addr_T_48)
node _wrLegal_addr_T_57 = and(_wrLegal_addr_T_3, _wrLegal_addr_T_56)
node _wrLegal_addr_T_58 = or(UInt<1>(0h0), UInt<1>(0h0))
node _wrLegal_addr_T_59 = xor(io.addrIn, UInt<17>(0h10000))
node _wrLegal_addr_T_60 = cvt(_wrLegal_addr_T_59)
node _wrLegal_addr_T_61 = and(_wrLegal_addr_T_60, asSInt(UInt<17>(0h10000)))
node _wrLegal_addr_T_62 = asSInt(_wrLegal_addr_T_61)
node _wrLegal_addr_T_63 = eq(_wrLegal_addr_T_62, asSInt(UInt<1>(0h0)))
node _wrLegal_addr_T_64 = and(_wrLegal_addr_T_58, _wrLegal_addr_T_63)
node _wrLegal_addr_T_65 = or(UInt<1>(0h0), _wrLegal_addr_T_57)
node wrLegal_addr = or(_wrLegal_addr_T_65, _wrLegal_addr_T_64)
node _gbits_legal_T = leq(UInt<1>(0h0), io.sizeIn)
node _gbits_legal_T_1 = leq(io.sizeIn, UInt<4>(0hc))
node _gbits_legal_T_2 = and(_gbits_legal_T, _gbits_legal_T_1)
node _gbits_legal_T_3 = or(UInt<1>(0h0), _gbits_legal_T_2)
node _gbits_legal_T_4 = xor(io.addrIn, UInt<14>(0h2000))
node _gbits_legal_T_5 = cvt(_gbits_legal_T_4)
node _gbits_legal_T_6 = and(_gbits_legal_T_5, asSInt(UInt<33>(0hffffe000)))
node _gbits_legal_T_7 = asSInt(_gbits_legal_T_6)
node _gbits_legal_T_8 = eq(_gbits_legal_T_7, asSInt(UInt<1>(0h0)))
node _gbits_legal_T_9 = and(_gbits_legal_T_3, _gbits_legal_T_8)
node _gbits_legal_T_10 = leq(UInt<1>(0h0), io.sizeIn)
node _gbits_legal_T_11 = leq(io.sizeIn, UInt<3>(0h6))
node _gbits_legal_T_12 = and(_gbits_legal_T_10, _gbits_legal_T_11)
node _gbits_legal_T_13 = or(UInt<1>(0h0), _gbits_legal_T_12)
node _gbits_legal_T_14 = xor(io.addrIn, UInt<1>(0h0))
node _gbits_legal_T_15 = cvt(_gbits_legal_T_14)
node _gbits_legal_T_16 = and(_gbits_legal_T_15, asSInt(UInt<33>(0hffffe000)))
node _gbits_legal_T_17 = asSInt(_gbits_legal_T_16)
node _gbits_legal_T_18 = eq(_gbits_legal_T_17, asSInt(UInt<1>(0h0)))
node _gbits_legal_T_19 = xor(io.addrIn, UInt<17>(0h10000))
node _gbits_legal_T_20 = cvt(_gbits_legal_T_19)
node _gbits_legal_T_21 = and(_gbits_legal_T_20, asSInt(UInt<33>(0hffff0000)))
node _gbits_legal_T_22 = asSInt(_gbits_legal_T_21)
node _gbits_legal_T_23 = eq(_gbits_legal_T_22, asSInt(UInt<1>(0h0)))
node _gbits_legal_T_24 = xor(io.addrIn, UInt<21>(0h100000))
node _gbits_legal_T_25 = cvt(_gbits_legal_T_24)
node _gbits_legal_T_26 = and(_gbits_legal_T_25, asSInt(UInt<33>(0hfffee000)))
node _gbits_legal_T_27 = asSInt(_gbits_legal_T_26)
node _gbits_legal_T_28 = eq(_gbits_legal_T_27, asSInt(UInt<1>(0h0)))
node _gbits_legal_T_29 = xor(io.addrIn, UInt<26>(0h2000000))
node _gbits_legal_T_30 = cvt(_gbits_legal_T_29)
node _gbits_legal_T_31 = and(_gbits_legal_T_30, asSInt(UInt<33>(0hffff0000)))
node _gbits_legal_T_32 = asSInt(_gbits_legal_T_31)
node _gbits_legal_T_33 = eq(_gbits_legal_T_32, asSInt(UInt<1>(0h0)))
node _gbits_legal_T_34 = xor(io.addrIn, UInt<26>(0h2010000))
node _gbits_legal_T_35 = cvt(_gbits_legal_T_34)
node _gbits_legal_T_36 = and(_gbits_legal_T_35, asSInt(UInt<33>(0hffffe000)))
node _gbits_legal_T_37 = asSInt(_gbits_legal_T_36)
node _gbits_legal_T_38 = eq(_gbits_legal_T_37, asSInt(UInt<1>(0h0)))
node _gbits_legal_T_39 = xor(io.addrIn, UInt<28>(0h8000000))
node _gbits_legal_T_40 = cvt(_gbits_legal_T_39)
node _gbits_legal_T_41 = and(_gbits_legal_T_40, asSInt(UInt<33>(0hffff0000)))
node _gbits_legal_T_42 = asSInt(_gbits_legal_T_41)
node _gbits_legal_T_43 = eq(_gbits_legal_T_42, asSInt(UInt<1>(0h0)))
node _gbits_legal_T_44 = xor(io.addrIn, UInt<28>(0hc000000))
node _gbits_legal_T_45 = cvt(_gbits_legal_T_44)
node _gbits_legal_T_46 = and(_gbits_legal_T_45, asSInt(UInt<33>(0hfc000000)))
node _gbits_legal_T_47 = asSInt(_gbits_legal_T_46)
node _gbits_legal_T_48 = eq(_gbits_legal_T_47, asSInt(UInt<1>(0h0)))
node _gbits_legal_T_49 = xor(io.addrIn, UInt<29>(0h10020000))
node _gbits_legal_T_50 = cvt(_gbits_legal_T_49)
node _gbits_legal_T_51 = and(_gbits_legal_T_50, asSInt(UInt<33>(0hffffe000)))
node _gbits_legal_T_52 = asSInt(_gbits_legal_T_51)
node _gbits_legal_T_53 = eq(_gbits_legal_T_52, asSInt(UInt<1>(0h0)))
node _gbits_legal_T_54 = xor(io.addrIn, UInt<32>(0h80000000))
node _gbits_legal_T_55 = cvt(_gbits_legal_T_54)
node _gbits_legal_T_56 = and(_gbits_legal_T_55, asSInt(UInt<33>(0hf0000000)))
node _gbits_legal_T_57 = asSInt(_gbits_legal_T_56)
node _gbits_legal_T_58 = eq(_gbits_legal_T_57, asSInt(UInt<1>(0h0)))
node _gbits_legal_T_59 = or(_gbits_legal_T_18, _gbits_legal_T_23)
node _gbits_legal_T_60 = or(_gbits_legal_T_59, _gbits_legal_T_28)
node _gbits_legal_T_61 = or(_gbits_legal_T_60, _gbits_legal_T_33)
node _gbits_legal_T_62 = or(_gbits_legal_T_61, _gbits_legal_T_38)
node _gbits_legal_T_63 = or(_gbits_legal_T_62, _gbits_legal_T_43)
node _gbits_legal_T_64 = or(_gbits_legal_T_63, _gbits_legal_T_48)
node _gbits_legal_T_65 = or(_gbits_legal_T_64, _gbits_legal_T_53)
node _gbits_legal_T_66 = or(_gbits_legal_T_65, _gbits_legal_T_58)
node _gbits_legal_T_67 = and(_gbits_legal_T_13, _gbits_legal_T_66)
node _gbits_legal_T_68 = or(UInt<1>(0h0), _gbits_legal_T_9)
node gbits_legal = or(_gbits_legal_T_68, _gbits_legal_T_67)
wire gbits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}
connect gbits.opcode, UInt<3>(0h4)
connect gbits.param, UInt<1>(0h0)
connect gbits.size, io.sizeIn
connect gbits.source, UInt<1>(0h0)
connect gbits.address, io.addrIn
node _gbits_a_mask_sizeOH_T = or(io.sizeIn, UInt<1>(0h0))
node gbits_a_mask_sizeOH = or(UInt<1>(0h1), UInt<1>(0h1))
connect gbits.mask, UInt<1>(0h1)
invalidate gbits.data
connect gbits.corrupt, UInt<1>(0h0)
node _pfbits_legal_T = leq(UInt<1>(0h0), io.sizeIn)
node _pfbits_legal_T_1 = leq(io.sizeIn, UInt<4>(0hc))
node _pfbits_legal_T_2 = and(_pfbits_legal_T, _pfbits_legal_T_1)
node _pfbits_legal_T_3 = or(UInt<1>(0h0), _pfbits_legal_T_2)
node _pfbits_legal_T_4 = xor(io.addrIn, UInt<14>(0h2000))
node _pfbits_legal_T_5 = cvt(_pfbits_legal_T_4)
node _pfbits_legal_T_6 = and(_pfbits_legal_T_5, asSInt(UInt<33>(0h9e112000)))
node _pfbits_legal_T_7 = asSInt(_pfbits_legal_T_6)
node _pfbits_legal_T_8 = eq(_pfbits_legal_T_7, asSInt(UInt<1>(0h0)))
node _pfbits_legal_T_9 = and(_pfbits_legal_T_3, _pfbits_legal_T_8)
node _pfbits_legal_T_10 = leq(UInt<1>(0h0), io.sizeIn)
node _pfbits_legal_T_11 = leq(io.sizeIn, UInt<3>(0h6))
node _pfbits_legal_T_12 = and(_pfbits_legal_T_10, _pfbits_legal_T_11)
node _pfbits_legal_T_13 = or(UInt<1>(0h0), _pfbits_legal_T_12)
node _pfbits_legal_T_14 = xor(io.addrIn, UInt<1>(0h0))
node _pfbits_legal_T_15 = cvt(_pfbits_legal_T_14)
node _pfbits_legal_T_16 = and(_pfbits_legal_T_15, asSInt(UInt<33>(0h8e112000)))
node _pfbits_legal_T_17 = asSInt(_pfbits_legal_T_16)
node _pfbits_legal_T_18 = eq(_pfbits_legal_T_17, asSInt(UInt<1>(0h0)))
node _pfbits_legal_T_19 = xor(io.addrIn, UInt<21>(0h100000))
node _pfbits_legal_T_20 = cvt(_pfbits_legal_T_19)
node _pfbits_legal_T_21 = and(_pfbits_legal_T_20, asSInt(UInt<33>(0h9e102000)))
node _pfbits_legal_T_22 = asSInt(_pfbits_legal_T_21)
node _pfbits_legal_T_23 = eq(_pfbits_legal_T_22, asSInt(UInt<1>(0h0)))
node _pfbits_legal_T_24 = xor(io.addrIn, UInt<26>(0h2000000))
node _pfbits_legal_T_25 = cvt(_pfbits_legal_T_24)
node _pfbits_legal_T_26 = and(_pfbits_legal_T_25, asSInt(UInt<33>(0h9e110000)))
node _pfbits_legal_T_27 = asSInt(_pfbits_legal_T_26)
node _pfbits_legal_T_28 = eq(_pfbits_legal_T_27, asSInt(UInt<1>(0h0)))
node _pfbits_legal_T_29 = xor(io.addrIn, UInt<26>(0h2010000))
node _pfbits_legal_T_30 = cvt(_pfbits_legal_T_29)
node _pfbits_legal_T_31 = and(_pfbits_legal_T_30, asSInt(UInt<33>(0h9e112000)))
node _pfbits_legal_T_32 = asSInt(_pfbits_legal_T_31)
node _pfbits_legal_T_33 = eq(_pfbits_legal_T_32, asSInt(UInt<1>(0h0)))
node _pfbits_legal_T_34 = xor(io.addrIn, UInt<28>(0h8000000))
node _pfbits_legal_T_35 = cvt(_pfbits_legal_T_34)
node _pfbits_legal_T_36 = and(_pfbits_legal_T_35, asSInt(UInt<33>(0h9e110000)))
node _pfbits_legal_T_37 = asSInt(_pfbits_legal_T_36)
node _pfbits_legal_T_38 = eq(_pfbits_legal_T_37, asSInt(UInt<1>(0h0)))
node _pfbits_legal_T_39 = xor(io.addrIn, UInt<28>(0hc000000))
node _pfbits_legal_T_40 = cvt(_pfbits_legal_T_39)
node _pfbits_legal_T_41 = and(_pfbits_legal_T_40, asSInt(UInt<33>(0h9c000000)))
node _pfbits_legal_T_42 = asSInt(_pfbits_legal_T_41)
node _pfbits_legal_T_43 = eq(_pfbits_legal_T_42, asSInt(UInt<1>(0h0)))
node _pfbits_legal_T_44 = xor(io.addrIn, UInt<32>(0h80000000))
node _pfbits_legal_T_45 = cvt(_pfbits_legal_T_44)
node _pfbits_legal_T_46 = and(_pfbits_legal_T_45, asSInt(UInt<33>(0h90000000)))
node _pfbits_legal_T_47 = asSInt(_pfbits_legal_T_46)
node _pfbits_legal_T_48 = eq(_pfbits_legal_T_47, asSInt(UInt<1>(0h0)))
node _pfbits_legal_T_49 = or(_pfbits_legal_T_18, _pfbits_legal_T_23)
node _pfbits_legal_T_50 = or(_pfbits_legal_T_49, _pfbits_legal_T_28)
node _pfbits_legal_T_51 = or(_pfbits_legal_T_50, _pfbits_legal_T_33)
node _pfbits_legal_T_52 = or(_pfbits_legal_T_51, _pfbits_legal_T_38)
node _pfbits_legal_T_53 = or(_pfbits_legal_T_52, _pfbits_legal_T_43)
node _pfbits_legal_T_54 = or(_pfbits_legal_T_53, _pfbits_legal_T_48)
node _pfbits_legal_T_55 = and(_pfbits_legal_T_13, _pfbits_legal_T_54)
node _pfbits_legal_T_56 = or(UInt<1>(0h0), UInt<1>(0h0))
node _pfbits_legal_T_57 = xor(io.addrIn, UInt<17>(0h10000))
node _pfbits_legal_T_58 = cvt(_pfbits_legal_T_57)
node _pfbits_legal_T_59 = and(_pfbits_legal_T_58, asSInt(UInt<33>(0h9e110000)))
node _pfbits_legal_T_60 = asSInt(_pfbits_legal_T_59)
node _pfbits_legal_T_61 = eq(_pfbits_legal_T_60, asSInt(UInt<1>(0h0)))
node _pfbits_legal_T_62 = and(_pfbits_legal_T_56, _pfbits_legal_T_61)
node _pfbits_legal_T_63 = or(UInt<1>(0h0), _pfbits_legal_T_9)
node _pfbits_legal_T_64 = or(_pfbits_legal_T_63, _pfbits_legal_T_55)
node pfbits_legal = or(_pfbits_legal_T_64, _pfbits_legal_T_62)
wire pfbits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}
connect pfbits.opcode, UInt<1>(0h0)
connect pfbits.param, UInt<1>(0h0)
connect pfbits.size, io.sizeIn
connect pfbits.source, UInt<1>(0h0)
connect pfbits.address, io.addrIn
node _pfbits_a_mask_sizeOH_T = or(io.sizeIn, UInt<1>(0h0))
node pfbits_a_mask_sizeOH = or(UInt<1>(0h1), UInt<1>(0h1))
connect pfbits.mask, UInt<1>(0h1)
connect pfbits.data, muxedData
connect pfbits.corrupt, UInt<1>(0h0)
connect io.rdLegal, rdLegal_addr
connect io.wrLegal, wrLegal_addr
connect io.sbStateOut, sbState
node _T = eq(sbState, UInt<1>(0h1))
when _T :
connect nodeOut.a.bits, gbits
else :
connect nodeOut.a.bits, pfbits
node respError = or(d_q.io.deq.bits.denied, d_q.io.deq.bits.corrupt)
connect io.respError, respError
node _wrTxValid_T = eq(sbState, UInt<2>(0h2))
node _wrTxValid_T_1 = and(_wrTxValid_T, nodeOut.a.valid)
node wrTxValid = and(_wrTxValid_T_1, nodeOut.a.ready)
node _rdTxValid_T = eq(sbState, UInt<2>(0h3))
node _rdTxValid_T_1 = and(_rdTxValid_T, d_q.io.deq.valid)
node rdTxValid = and(_rdTxValid_T_1, d_q.io.deq.ready)
node _txLast_T = dshl(UInt<1>(0h1), io.sizeIn)
node _txLast_T_1 = sub(_txLast_T, UInt<1>(0h1))
node _txLast_T_2 = tail(_txLast_T_1, 1)
node txLast = eq(counter, _txLast_T_2)
node _counter_T = or(wrTxValid, rdTxValid)
node _counter_T_1 = and(_counter_T, txLast)
node _counter_T_2 = or(wrTxValid, rdTxValid)
node _counter_T_3 = add(counter, UInt<1>(0h1))
node _counter_T_4 = tail(_counter_T_3, 1)
node _counter_T_5 = mux(_counter_T_2, _counter_T_4, counter)
node _counter_T_6 = mux(_counter_T_1, UInt<1>(0h0), _counter_T_5)
connect counter, _counter_T_6
node _io_rdLoad_0_T = eq(counter, UInt<1>(0h0))
node _io_rdLoad_0_T_1 = and(rdTxValid, _io_rdLoad_0_T)
connect io.rdLoad[0], _io_rdLoad_0_T_1
node _io_rdLoad_1_T = eq(counter, UInt<1>(0h1))
node _io_rdLoad_1_T_1 = and(rdTxValid, _io_rdLoad_1_T)
connect io.rdLoad[1], _io_rdLoad_1_T_1
node _io_rdLoad_2_T = eq(counter, UInt<2>(0h2))
node _io_rdLoad_2_T_1 = and(rdTxValid, _io_rdLoad_2_T)
connect io.rdLoad[2], _io_rdLoad_2_T_1
node _io_rdLoad_3_T = eq(counter, UInt<2>(0h3))
node _io_rdLoad_3_T_1 = and(rdTxValid, _io_rdLoad_3_T)
connect io.rdLoad[3], _io_rdLoad_3_T_1
node _io_rdLoad_4_T = eq(counter, UInt<3>(0h4))
node _io_rdLoad_4_T_1 = and(rdTxValid, _io_rdLoad_4_T)
connect io.rdLoad[4], _io_rdLoad_4_T_1
node _io_rdLoad_5_T = eq(counter, UInt<3>(0h5))
node _io_rdLoad_5_T_1 = and(rdTxValid, _io_rdLoad_5_T)
connect io.rdLoad[5], _io_rdLoad_5_T_1
node _io_rdLoad_6_T = eq(counter, UInt<3>(0h6))
node _io_rdLoad_6_T_1 = and(rdTxValid, _io_rdLoad_6_T)
connect io.rdLoad[6], _io_rdLoad_6_T_1
node _io_rdLoad_7_T = eq(counter, UInt<3>(0h7))
node _io_rdLoad_7_T_1 = and(rdTxValid, _io_rdLoad_7_T)
connect io.rdLoad[7], _io_rdLoad_7_T_1
node _T_1 = eq(sbState, UInt<1>(0h0))
when _T_1 :
node _sbState_T = and(io.rdEn, io.rdLegal)
node _sbState_T_1 = and(io.wrEn, io.wrLegal)
node _sbState_T_2 = mux(_sbState_T_1, UInt<2>(0h2), sbState)
node _sbState_T_3 = mux(_sbState_T, UInt<1>(0h1), _sbState_T_2)
connect sbState, _sbState_T_3
else :
node _T_2 = eq(sbState, UInt<1>(0h1))
when _T_2 :
node _sbState_T_4 = and(nodeOut.a.valid, nodeOut.a.ready)
node _sbState_T_5 = mux(_sbState_T_4, UInt<2>(0h3), sbState)
connect sbState, _sbState_T_5
else :
node _T_3 = eq(sbState, UInt<2>(0h2))
when _T_3 :
node _sbState_T_6 = and(wrTxValid, txLast)
node _sbState_T_7 = mux(_sbState_T_6, UInt<3>(0h4), sbState)
connect sbState, _sbState_T_7
else :
node _T_4 = eq(sbState, UInt<2>(0h3))
when _T_4 :
node _sbState_T_8 = and(rdTxValid, txLast)
node _sbState_T_9 = mux(_sbState_T_8, UInt<1>(0h0), sbState)
connect sbState, _sbState_T_9
else :
node _T_5 = eq(sbState, UInt<3>(0h4))
when _T_5 :
node _sbState_T_10 = and(d_q.io.deq.valid, d_q.io.deq.ready)
node _sbState_T_11 = mux(_sbState_T_10, UInt<1>(0h0), sbState)
connect sbState, _sbState_T_11
node _io_rdDone_T = and(rdTxValid, txLast)
connect io.rdDone, _io_rdDone_T
node _io_wrDone_T = eq(sbState, UInt<3>(0h4))
node _io_wrDone_T_1 = and(_io_wrDone_T, d_q.io.deq.valid)
node _io_wrDone_T_2 = and(_io_wrDone_T_1, d_q.io.deq.ready)
connect io.wrDone, _io_wrDone_T_2
connect io.dataOut, d_q.io.deq.bits.data
node _nodeOut_a_valid_T = eq(sbState, UInt<1>(0h1))
node _nodeOut_a_valid_T_1 = eq(sbState, UInt<2>(0h2))
node _nodeOut_a_valid_T_2 = or(_nodeOut_a_valid_T, _nodeOut_a_valid_T_1)
connect nodeOut.a.valid, _nodeOut_a_valid_T_2
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<8>(0h0)
connect _WIRE.bits.mask, UInt<1>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
connect _WIRE_1.ready, UInt<1>(0h0)
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<8>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
connect _WIRE_3.valid, UInt<1>(0h0)
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<7>}}
connect _WIRE_4.bits.sink, UInt<7>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<7>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.valid, UInt<1>(0h0)
node _T_6 = eq(sbState, UInt<1>(0h0))
node _T_7 = eq(sbState, UInt<1>(0h1))
node _T_8 = or(_T_6, _T_7)
node _T_9 = eq(sbState, UInt<2>(0h2))
node _T_10 = or(_T_8, _T_9)
node _T_11 = eq(sbState, UInt<2>(0h3))
node _T_12 = or(_T_10, _T_11)
node _T_13 = eq(sbState, UInt<3>(0h4))
node _T_14 = or(_T_12, _T_13)
node _T_15 = asUInt(reset)
node _T_16 = eq(_T_15, UInt<1>(0h0))
when _T_16 :
node _T_17 = eq(_T_14, UInt<1>(0h0))
when _T_17 :
printf(clock, UInt<1>(0h1), "Assertion failed: SBA state machine in undefined state\n at SBA.scala:373 assert (sbState === Idle.id.U ||\n") : printf
assert(clock, _T_14, UInt<1>(0h1), "") : assert
node _T_18 = eq(sbState, UInt<1>(0h0))
node _T_19 = eq(sbState, UInt<1>(0h1))
node _T_20 = eq(sbState, UInt<2>(0h2))
node _T_21 = eq(sbState, UInt<2>(0h3))
node _T_22 = eq(sbState, UInt<3>(0h4))
node _T_23 = eq(io.rdLegal, UInt<1>(0h0))
node _T_24 = and(io.rdEn, _T_23)
node _T_25 = eq(io.wrLegal, UInt<1>(0h0))
node _T_26 = and(io.wrEn, _T_25)
extmodule plusarg_reader_187 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32
extmodule plusarg_reader_188 :
output out : UInt<32>
defname = plusarg_reader
parameter DEFAULT = 0
parameter FORMAT = "tilelink_timeout=%d"
parameter WIDTH = 32 | module SBToTL( // @[SBA.scala:273:9]
input clock, // @[SBA.scala:273:9]
input reset, // @[SBA.scala:273:9]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input io_rdEn, // @[SBA.scala:274:16]
input io_wrEn, // @[SBA.scala:274:16]
input [127:0] io_addrIn, // @[SBA.scala:274:16]
input [127:0] io_dataIn, // @[SBA.scala:274:16]
input [2:0] io_sizeIn, // @[SBA.scala:274:16]
output io_rdLegal, // @[SBA.scala:274:16]
output io_wrLegal, // @[SBA.scala:274:16]
output io_rdDone, // @[SBA.scala:274:16]
output io_wrDone, // @[SBA.scala:274:16]
output io_respError, // @[SBA.scala:274:16]
output [7:0] io_dataOut, // @[SBA.scala:274:16]
output io_rdLoad_0, // @[SBA.scala:274:16]
output io_rdLoad_1, // @[SBA.scala:274:16]
output io_rdLoad_2, // @[SBA.scala:274:16]
output io_rdLoad_3, // @[SBA.scala:274:16]
output io_rdLoad_4, // @[SBA.scala:274:16]
output io_rdLoad_5, // @[SBA.scala:274:16]
output io_rdLoad_6, // @[SBA.scala:274:16]
output io_rdLoad_7, // @[SBA.scala:274:16]
output [2:0] io_sbStateOut, // @[SBA.scala:274:16]
input rf_reset // @[SBA.scala:289:28]
);
wire _d_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire _d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21]
wire _d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[SBA.scala:273:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[SBA.scala:273:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[SBA.scala:273:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[SBA.scala:273:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[SBA.scala:273:9]
wire [6:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[SBA.scala:273:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[SBA.scala:273:9]
wire [7:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[SBA.scala:273:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[SBA.scala:273:9]
wire io_rdEn_0 = io_rdEn; // @[SBA.scala:273:9]
wire io_wrEn_0 = io_wrEn; // @[SBA.scala:273:9]
wire [127:0] io_addrIn_0 = io_addrIn; // @[SBA.scala:273:9]
wire [127:0] io_dataIn_0 = io_dataIn; // @[SBA.scala:273:9]
wire [2:0] io_sizeIn_0 = io_sizeIn; // @[SBA.scala:273:9]
wire auto_out_a_bits_source = 1'h0; // @[SBA.scala:273:9]
wire auto_out_a_bits_corrupt = 1'h0; // @[SBA.scala:273:9]
wire auto_out_d_bits_source = 1'h0; // @[SBA.scala:273:9]
wire nodeOut_a_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt = 1'h0; // @[MixedNode.scala:542:17]
wire nodeOut_d_bits_source = 1'h0; // @[MixedNode.scala:542:17]
wire _wrLegal_addr_T_58 = 1'h0; // @[Parameters.scala:684:29]
wire _wrLegal_addr_T_64 = 1'h0; // @[Parameters.scala:684:54]
wire gbits_source = 1'h0; // @[Edges.scala:460:17]
wire gbits_corrupt = 1'h0; // @[Edges.scala:460:17]
wire _pfbits_legal_T_56 = 1'h0; // @[Parameters.scala:684:29]
wire _pfbits_legal_T_62 = 1'h0; // @[Parameters.scala:684:54]
wire pfbits_source = 1'h0; // @[Edges.scala:480:17]
wire pfbits_corrupt = 1'h0; // @[Edges.scala:480:17]
wire [2:0] auto_out_a_bits_param = 3'h0; // @[SBA.scala:273:9]
wire [2:0] nodeOut_a_bits_param = 3'h0; // @[MixedNode.scala:542:17]
wire [2:0] gbits_param = 3'h0; // @[Edges.scala:460:17]
wire [2:0] pfbits_opcode = 3'h0; // @[Edges.scala:480:17]
wire [2:0] pfbits_param = 3'h0; // @[Edges.scala:480:17]
wire auto_out_a_bits_mask = 1'h1; // @[SBA.scala:273:9]
wire nodeOut_a_bits_mask = 1'h1; // @[MixedNode.scala:542:17]
wire _rdLegal_addr_T = 1'h1; // @[Parameters.scala:92:28]
wire _rdLegal_addr_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _wrLegal_addr_T = 1'h1; // @[Parameters.scala:92:28]
wire _wrLegal_addr_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _gbits_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _gbits_legal_T_1 = 1'h1; // @[Parameters.scala:92:38]
wire _gbits_legal_T_2 = 1'h1; // @[Parameters.scala:92:33]
wire _gbits_legal_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _gbits_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire gbits_mask = 1'h1; // @[Edges.scala:460:17]
wire gbits_a_mask_sizeOH = 1'h1; // @[Misc.scala:202:81]
wire _pfbits_legal_T = 1'h1; // @[Parameters.scala:92:28]
wire _pfbits_legal_T_1 = 1'h1; // @[Parameters.scala:92:38]
wire _pfbits_legal_T_2 = 1'h1; // @[Parameters.scala:92:33]
wire _pfbits_legal_T_3 = 1'h1; // @[Parameters.scala:684:29]
wire _pfbits_legal_T_10 = 1'h1; // @[Parameters.scala:92:28]
wire pfbits_mask = 1'h1; // @[Edges.scala:480:17]
wire pfbits_a_mask_sizeOH = 1'h1; // @[Misc.scala:202:81]
wire [7:0] gbits_data = 8'h0; // @[Edges.scala:460:17]
wire [2:0] gbits_opcode = 3'h4; // @[Edges.scala:460:17]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[SBA.scala:273:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[SBA.scala:273:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[SBA.scala:273:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[SBA.scala:273:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[SBA.scala:273:9]
wire [6:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[SBA.scala:273:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[SBA.scala:273:9]
wire [7:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[SBA.scala:273:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[SBA.scala:273:9]
wire [127:0] _rdLegal_addr_T_4 = io_addrIn_0; // @[Parameters.scala:137:31]
wire [127:0] _wrLegal_addr_T_4 = io_addrIn_0; // @[Parameters.scala:137:31]
wire [127:0] _gbits_legal_T_14 = io_addrIn_0; // @[Parameters.scala:137:31]
wire [127:0] _pfbits_legal_T_14 = io_addrIn_0; // @[Parameters.scala:137:31]
wire rdLegal_addr; // @[Parameters.scala:686:26]
wire [2:0] _gbits_a_mask_sizeOH_T = io_sizeIn_0; // @[Misc.scala:202:34]
wire [2:0] _pfbits_a_mask_sizeOH_T = io_sizeIn_0; // @[Misc.scala:202:34]
wire wrLegal_addr; // @[Parameters.scala:686:26]
wire _io_rdDone_T; // @[SBA.scala:362:29]
wire _io_wrDone_T_2; // @[SBA.scala:363:71]
wire respError; // @[SBA.scala:335:35]
wire _io_rdLoad_0_T_1; // @[SBA.scala:345:33]
wire _io_rdLoad_1_T_1; // @[SBA.scala:345:33]
wire _io_rdLoad_2_T_1; // @[SBA.scala:345:33]
wire _io_rdLoad_3_T_1; // @[SBA.scala:345:33]
wire _io_rdLoad_4_T_1; // @[SBA.scala:345:33]
wire _io_rdLoad_5_T_1; // @[SBA.scala:345:33]
wire _io_rdLoad_6_T_1; // @[SBA.scala:345:33]
wire _io_rdLoad_7_T_1; // @[SBA.scala:345:33]
wire [2:0] auto_out_a_bits_opcode_0; // @[SBA.scala:273:9]
wire [3:0] auto_out_a_bits_size_0; // @[SBA.scala:273:9]
wire [31:0] auto_out_a_bits_address_0; // @[SBA.scala:273:9]
wire [7:0] auto_out_a_bits_data_0; // @[SBA.scala:273:9]
wire auto_out_a_valid_0; // @[SBA.scala:273:9]
wire auto_out_d_ready_0; // @[SBA.scala:273:9]
wire io_rdLoad_0_0; // @[SBA.scala:273:9]
wire io_rdLoad_1_0; // @[SBA.scala:273:9]
wire io_rdLoad_2_0; // @[SBA.scala:273:9]
wire io_rdLoad_3_0; // @[SBA.scala:273:9]
wire io_rdLoad_4_0; // @[SBA.scala:273:9]
wire io_rdLoad_5_0; // @[SBA.scala:273:9]
wire io_rdLoad_6_0; // @[SBA.scala:273:9]
wire io_rdLoad_7_0; // @[SBA.scala:273:9]
wire io_rdLegal_0; // @[SBA.scala:273:9]
wire io_wrLegal_0; // @[SBA.scala:273:9]
wire io_rdDone_0; // @[SBA.scala:273:9]
wire io_wrDone_0; // @[SBA.scala:273:9]
wire io_respError_0; // @[SBA.scala:273:9]
wire [7:0] io_dataOut_0; // @[SBA.scala:273:9]
wire [2:0] io_sbStateOut_0; // @[SBA.scala:273:9]
wire _nodeOut_a_valid_T_2; // @[SBA.scala:366:52]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[SBA.scala:273:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[SBA.scala:273:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[SBA.scala:273:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[SBA.scala:273:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[SBA.scala:273:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[SBA.scala:273:9]
reg [2:0] sbState; // @[SBA.scala:295:26]
assign io_sbStateOut_0 = sbState; // @[SBA.scala:273:9, :295:26]
wire _T_21 = sbState == 3'h3; // @[SBA.scala:295:26, :299:25]
wire _q_io_deq_ready_T; // @[SBA.scala:299:25]
assign _q_io_deq_ready_T = _T_21; // @[SBA.scala:299:25]
wire _rdTxValid_T; // @[SBA.scala:339:29]
assign _rdTxValid_T = _T_21; // @[SBA.scala:299:25, :339:29]
wire _T_22 = sbState == 3'h4; // @[SBA.scala:295:26, :299:62]
wire _q_io_deq_ready_T_1; // @[SBA.scala:299:62]
assign _q_io_deq_ready_T_1 = _T_22; // @[SBA.scala:299:62]
wire _io_wrDone_T; // @[SBA.scala:363:28]
assign _io_wrDone_T = _T_22; // @[SBA.scala:299:62, :363:28]
wire _q_io_deq_ready_T_2 = _q_io_deq_ready_T | _q_io_deq_ready_T_1; // @[SBA.scala:299:{25,50,62}]
wire [7:0] muxedData; // @[SBA.scala:301:29]
wire [7:0] pfbits_data = muxedData; // @[Edges.scala:480:17]
reg [3:0] counter; // @[SBA.scala:307:26]
wire [7:0] _vecData_0_T; // @[SBA.scala:309:63]
wire [7:0] _vecData_1_T; // @[SBA.scala:309:63]
wire [7:0] _vecData_2_T; // @[SBA.scala:309:63]
wire [7:0] _vecData_3_T; // @[SBA.scala:309:63]
wire [7:0] _vecData_4_T; // @[SBA.scala:309:63]
wire [7:0] _vecData_5_T; // @[SBA.scala:309:63]
wire [7:0] _vecData_6_T; // @[SBA.scala:309:63]
wire [7:0] _vecData_7_T; // @[SBA.scala:309:63]
wire [7:0] vecData_0; // @[SBA.scala:308:25]
wire [7:0] vecData_1; // @[SBA.scala:308:25]
wire [7:0] vecData_2; // @[SBA.scala:308:25]
wire [7:0] vecData_3; // @[SBA.scala:308:25]
wire [7:0] vecData_4; // @[SBA.scala:308:25]
wire [7:0] vecData_5; // @[SBA.scala:308:25]
wire [7:0] vecData_6; // @[SBA.scala:308:25]
wire [7:0] vecData_7; // @[SBA.scala:308:25]
assign _vecData_0_T = io_dataIn_0[7:0]; // @[SBA.scala:273:9, :309:63]
assign vecData_0 = _vecData_0_T; // @[SBA.scala:308:25, :309:63]
assign _vecData_1_T = io_dataIn_0[15:8]; // @[SBA.scala:273:9, :309:63]
assign vecData_1 = _vecData_1_T; // @[SBA.scala:308:25, :309:63]
assign _vecData_2_T = io_dataIn_0[23:16]; // @[SBA.scala:273:9, :309:63]
assign vecData_2 = _vecData_2_T; // @[SBA.scala:308:25, :309:63]
assign _vecData_3_T = io_dataIn_0[31:24]; // @[SBA.scala:273:9, :309:63]
assign vecData_3 = _vecData_3_T; // @[SBA.scala:308:25, :309:63]
assign _vecData_4_T = io_dataIn_0[39:32]; // @[SBA.scala:273:9, :309:63]
assign vecData_4 = _vecData_4_T; // @[SBA.scala:308:25, :309:63]
assign _vecData_5_T = io_dataIn_0[47:40]; // @[SBA.scala:273:9, :309:63]
assign vecData_5 = _vecData_5_T; // @[SBA.scala:308:25, :309:63]
assign _vecData_6_T = io_dataIn_0[55:48]; // @[SBA.scala:273:9, :309:63]
assign vecData_6 = _vecData_6_T; // @[SBA.scala:308:25, :309:63]
assign _vecData_7_T = io_dataIn_0[63:56]; // @[SBA.scala:273:9, :309:63]
assign vecData_7 = _vecData_7_T; // @[SBA.scala:308:25, :309:63]
wire [2:0] _muxedData_T = counter[2:0]; // @[SBA.scala:307:26, :310:33]
wire [7:0][7:0] _GEN = {{vecData_7}, {vecData_6}, {vecData_5}, {vecData_4}, {vecData_3}, {vecData_2}, {vecData_1}, {vecData_0}}; // @[SBA.scala:308:25, :310:15]
assign muxedData = _GEN[_muxedData_T]; // @[SBA.scala:301:29, :310:{15,33}]
wire _rdLegal_addr_T_1 = ~(io_sizeIn_0[2]); // @[Parameters.scala:92:38]
wire _rdLegal_addr_T_2 = _rdLegal_addr_T_1; // @[Parameters.scala:92:{33,38}]
wire [128:0] _rdLegal_addr_T_5 = {1'h0, _rdLegal_addr_T_4}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _rdLegal_addr_T_6 = _rdLegal_addr_T_5 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFE000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _rdLegal_addr_T_7 = _rdLegal_addr_T_6; // @[Parameters.scala:137:46]
wire _rdLegal_addr_T_8 = _rdLegal_addr_T_7 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [127:0] _GEN_0 = {io_addrIn_0[127:14], io_addrIn_0[13:0] ^ 14'h3000}; // @[Parameters.scala:137:31]
wire [127:0] _rdLegal_addr_T_9; // @[Parameters.scala:137:31]
assign _rdLegal_addr_T_9 = _GEN_0; // @[Parameters.scala:137:31]
wire [127:0] _wrLegal_addr_T_9; // @[Parameters.scala:137:31]
assign _wrLegal_addr_T_9 = _GEN_0; // @[Parameters.scala:137:31]
wire [128:0] _rdLegal_addr_T_10 = {1'h0, _rdLegal_addr_T_9}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _rdLegal_addr_T_11 = _rdLegal_addr_T_10 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _rdLegal_addr_T_12 = _rdLegal_addr_T_11; // @[Parameters.scala:137:46]
wire _rdLegal_addr_T_13 = _rdLegal_addr_T_12 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [127:0] _GEN_1 = {io_addrIn_0[127:17], io_addrIn_0[16:0] ^ 17'h10000}; // @[Parameters.scala:137:31]
wire [127:0] _rdLegal_addr_T_14; // @[Parameters.scala:137:31]
assign _rdLegal_addr_T_14 = _GEN_1; // @[Parameters.scala:137:31]
wire [127:0] _wrLegal_addr_T_59; // @[Parameters.scala:137:31]
assign _wrLegal_addr_T_59 = _GEN_1; // @[Parameters.scala:137:31]
wire [127:0] _gbits_legal_T_19; // @[Parameters.scala:137:31]
assign _gbits_legal_T_19 = _GEN_1; // @[Parameters.scala:137:31]
wire [127:0] _pfbits_legal_T_57; // @[Parameters.scala:137:31]
assign _pfbits_legal_T_57 = _GEN_1; // @[Parameters.scala:137:31]
wire [128:0] _rdLegal_addr_T_15 = {1'h0, _rdLegal_addr_T_14}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _rdLegal_addr_T_16 = _rdLegal_addr_T_15 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _rdLegal_addr_T_17 = _rdLegal_addr_T_16; // @[Parameters.scala:137:46]
wire _rdLegal_addr_T_18 = _rdLegal_addr_T_17 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [127:0] _GEN_2 = {io_addrIn_0[127:21], io_addrIn_0[20:0] ^ 21'h100000}; // @[Parameters.scala:137:31]
wire [127:0] _rdLegal_addr_T_19; // @[Parameters.scala:137:31]
assign _rdLegal_addr_T_19 = _GEN_2; // @[Parameters.scala:137:31]
wire [127:0] _wrLegal_addr_T_14; // @[Parameters.scala:137:31]
assign _wrLegal_addr_T_14 = _GEN_2; // @[Parameters.scala:137:31]
wire [127:0] _gbits_legal_T_24; // @[Parameters.scala:137:31]
assign _gbits_legal_T_24 = _GEN_2; // @[Parameters.scala:137:31]
wire [127:0] _pfbits_legal_T_19; // @[Parameters.scala:137:31]
assign _pfbits_legal_T_19 = _GEN_2; // @[Parameters.scala:137:31]
wire [128:0] _rdLegal_addr_T_20 = {1'h0, _rdLegal_addr_T_19}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _rdLegal_addr_T_21 = _rdLegal_addr_T_20 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFEF000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _rdLegal_addr_T_22 = _rdLegal_addr_T_21; // @[Parameters.scala:137:46]
wire _rdLegal_addr_T_23 = _rdLegal_addr_T_22 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [127:0] _GEN_3 = {io_addrIn_0[127:26], io_addrIn_0[25:0] ^ 26'h2000000}; // @[Parameters.scala:137:31]
wire [127:0] _rdLegal_addr_T_24; // @[Parameters.scala:137:31]
assign _rdLegal_addr_T_24 = _GEN_3; // @[Parameters.scala:137:31]
wire [127:0] _wrLegal_addr_T_19; // @[Parameters.scala:137:31]
assign _wrLegal_addr_T_19 = _GEN_3; // @[Parameters.scala:137:31]
wire [127:0] _gbits_legal_T_29; // @[Parameters.scala:137:31]
assign _gbits_legal_T_29 = _GEN_3; // @[Parameters.scala:137:31]
wire [127:0] _pfbits_legal_T_24; // @[Parameters.scala:137:31]
assign _pfbits_legal_T_24 = _GEN_3; // @[Parameters.scala:137:31]
wire [128:0] _rdLegal_addr_T_25 = {1'h0, _rdLegal_addr_T_24}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _rdLegal_addr_T_26 = _rdLegal_addr_T_25 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _rdLegal_addr_T_27 = _rdLegal_addr_T_26; // @[Parameters.scala:137:46]
wire _rdLegal_addr_T_28 = _rdLegal_addr_T_27 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [127:0] _GEN_4 = {io_addrIn_0[127:26], io_addrIn_0[25:0] ^ 26'h2010000}; // @[Parameters.scala:137:31]
wire [127:0] _rdLegal_addr_T_29; // @[Parameters.scala:137:31]
assign _rdLegal_addr_T_29 = _GEN_4; // @[Parameters.scala:137:31]
wire [127:0] _wrLegal_addr_T_24; // @[Parameters.scala:137:31]
assign _wrLegal_addr_T_24 = _GEN_4; // @[Parameters.scala:137:31]
wire [127:0] _gbits_legal_T_34; // @[Parameters.scala:137:31]
assign _gbits_legal_T_34 = _GEN_4; // @[Parameters.scala:137:31]
wire [127:0] _pfbits_legal_T_29; // @[Parameters.scala:137:31]
assign _pfbits_legal_T_29 = _GEN_4; // @[Parameters.scala:137:31]
wire [128:0] _rdLegal_addr_T_30 = {1'h0, _rdLegal_addr_T_29}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _rdLegal_addr_T_31 = _rdLegal_addr_T_30 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _rdLegal_addr_T_32 = _rdLegal_addr_T_31; // @[Parameters.scala:137:46]
wire _rdLegal_addr_T_33 = _rdLegal_addr_T_32 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [127:0] _GEN_5 = {io_addrIn_0[127:28], io_addrIn_0[27:0] ^ 28'h8000000}; // @[Parameters.scala:137:31]
wire [127:0] _rdLegal_addr_T_34; // @[Parameters.scala:137:31]
assign _rdLegal_addr_T_34 = _GEN_5; // @[Parameters.scala:137:31]
wire [127:0] _wrLegal_addr_T_29; // @[Parameters.scala:137:31]
assign _wrLegal_addr_T_29 = _GEN_5; // @[Parameters.scala:137:31]
wire [127:0] _gbits_legal_T_39; // @[Parameters.scala:137:31]
assign _gbits_legal_T_39 = _GEN_5; // @[Parameters.scala:137:31]
wire [127:0] _pfbits_legal_T_34; // @[Parameters.scala:137:31]
assign _pfbits_legal_T_34 = _GEN_5; // @[Parameters.scala:137:31]
wire [128:0] _rdLegal_addr_T_35 = {1'h0, _rdLegal_addr_T_34}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _rdLegal_addr_T_36 = _rdLegal_addr_T_35 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _rdLegal_addr_T_37 = _rdLegal_addr_T_36; // @[Parameters.scala:137:46]
wire _rdLegal_addr_T_38 = _rdLegal_addr_T_37 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [127:0] _GEN_6 = {io_addrIn_0[127:28], io_addrIn_0[27:0] ^ 28'hC000000}; // @[Parameters.scala:137:31]
wire [127:0] _rdLegal_addr_T_39; // @[Parameters.scala:137:31]
assign _rdLegal_addr_T_39 = _GEN_6; // @[Parameters.scala:137:31]
wire [127:0] _wrLegal_addr_T_34; // @[Parameters.scala:137:31]
assign _wrLegal_addr_T_34 = _GEN_6; // @[Parameters.scala:137:31]
wire [127:0] _gbits_legal_T_44; // @[Parameters.scala:137:31]
assign _gbits_legal_T_44 = _GEN_6; // @[Parameters.scala:137:31]
wire [127:0] _pfbits_legal_T_39; // @[Parameters.scala:137:31]
assign _pfbits_legal_T_39 = _GEN_6; // @[Parameters.scala:137:31]
wire [128:0] _rdLegal_addr_T_40 = {1'h0, _rdLegal_addr_T_39}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _rdLegal_addr_T_41 = _rdLegal_addr_T_40 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFC000000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _rdLegal_addr_T_42 = _rdLegal_addr_T_41; // @[Parameters.scala:137:46]
wire _rdLegal_addr_T_43 = _rdLegal_addr_T_42 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [127:0] _GEN_7 = {io_addrIn_0[127:29], io_addrIn_0[28:0] ^ 29'h10020000}; // @[Parameters.scala:137:31]
wire [127:0] _rdLegal_addr_T_44; // @[Parameters.scala:137:31]
assign _rdLegal_addr_T_44 = _GEN_7; // @[Parameters.scala:137:31]
wire [127:0] _wrLegal_addr_T_39; // @[Parameters.scala:137:31]
assign _wrLegal_addr_T_39 = _GEN_7; // @[Parameters.scala:137:31]
wire [127:0] _gbits_legal_T_49; // @[Parameters.scala:137:31]
assign _gbits_legal_T_49 = _GEN_7; // @[Parameters.scala:137:31]
wire [128:0] _rdLegal_addr_T_45 = {1'h0, _rdLegal_addr_T_44}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _rdLegal_addr_T_46 = _rdLegal_addr_T_45 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _rdLegal_addr_T_47 = _rdLegal_addr_T_46; // @[Parameters.scala:137:46]
wire _rdLegal_addr_T_48 = _rdLegal_addr_T_47 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [31:0] gbits_address = io_addrIn_0[31:0]; // @[Edges.scala:460:17]
wire [31:0] pfbits_address = io_addrIn_0[31:0]; // @[Edges.scala:480:17]
wire [127:0] _GEN_8 = {io_addrIn_0[127:32], io_addrIn_0[31:0] ^ 32'h80000000}; // @[Parameters.scala:137:31]
wire [127:0] _rdLegal_addr_T_49; // @[Parameters.scala:137:31]
assign _rdLegal_addr_T_49 = _GEN_8; // @[Parameters.scala:137:31]
wire [127:0] _wrLegal_addr_T_44; // @[Parameters.scala:137:31]
assign _wrLegal_addr_T_44 = _GEN_8; // @[Parameters.scala:137:31]
wire [127:0] _gbits_legal_T_54; // @[Parameters.scala:137:31]
assign _gbits_legal_T_54 = _GEN_8; // @[Parameters.scala:137:31]
wire [127:0] _pfbits_legal_T_44; // @[Parameters.scala:137:31]
assign _pfbits_legal_T_44 = _GEN_8; // @[Parameters.scala:137:31]
wire [128:0] _rdLegal_addr_T_50 = {1'h0, _rdLegal_addr_T_49}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _rdLegal_addr_T_51 = _rdLegal_addr_T_50 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFF0000000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _rdLegal_addr_T_52 = _rdLegal_addr_T_51; // @[Parameters.scala:137:46]
wire _rdLegal_addr_T_53 = _rdLegal_addr_T_52 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire _rdLegal_addr_T_54 = _rdLegal_addr_T_8 | _rdLegal_addr_T_13; // @[Parameters.scala:685:42]
wire _rdLegal_addr_T_55 = _rdLegal_addr_T_54 | _rdLegal_addr_T_18; // @[Parameters.scala:685:42]
wire _rdLegal_addr_T_56 = _rdLegal_addr_T_55 | _rdLegal_addr_T_23; // @[Parameters.scala:685:42]
wire _rdLegal_addr_T_57 = _rdLegal_addr_T_56 | _rdLegal_addr_T_28; // @[Parameters.scala:685:42]
wire _rdLegal_addr_T_58 = _rdLegal_addr_T_57 | _rdLegal_addr_T_33; // @[Parameters.scala:685:42]
wire _rdLegal_addr_T_59 = _rdLegal_addr_T_58 | _rdLegal_addr_T_38; // @[Parameters.scala:685:42]
wire _rdLegal_addr_T_60 = _rdLegal_addr_T_59 | _rdLegal_addr_T_43; // @[Parameters.scala:685:42]
wire _rdLegal_addr_T_61 = _rdLegal_addr_T_60 | _rdLegal_addr_T_48; // @[Parameters.scala:685:42]
wire _rdLegal_addr_T_62 = _rdLegal_addr_T_61 | _rdLegal_addr_T_53; // @[Parameters.scala:685:42]
wire _rdLegal_addr_T_63 = _rdLegal_addr_T_62; // @[Parameters.scala:684:54, :685:42]
assign rdLegal_addr = _rdLegal_addr_T_63; // @[Parameters.scala:684:54, :686:26]
assign io_rdLegal_0 = rdLegal_addr; // @[Parameters.scala:686:26]
wire _wrLegal_addr_T_1 = ~(io_sizeIn_0[2]); // @[Parameters.scala:92:38]
wire _wrLegal_addr_T_2 = _wrLegal_addr_T_1; // @[Parameters.scala:92:{33,38}]
wire [128:0] _wrLegal_addr_T_5 = {1'h0, _wrLegal_addr_T_4}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _wrLegal_addr_T_6 = _wrLegal_addr_T_5 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFE000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _wrLegal_addr_T_7 = _wrLegal_addr_T_6; // @[Parameters.scala:137:46]
wire _wrLegal_addr_T_8 = _wrLegal_addr_T_7 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _wrLegal_addr_T_10 = {1'h0, _wrLegal_addr_T_9}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _wrLegal_addr_T_11 = _wrLegal_addr_T_10 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _wrLegal_addr_T_12 = _wrLegal_addr_T_11; // @[Parameters.scala:137:46]
wire _wrLegal_addr_T_13 = _wrLegal_addr_T_12 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _wrLegal_addr_T_15 = {1'h0, _wrLegal_addr_T_14}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _wrLegal_addr_T_16 = _wrLegal_addr_T_15 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFEF000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _wrLegal_addr_T_17 = _wrLegal_addr_T_16; // @[Parameters.scala:137:46]
wire _wrLegal_addr_T_18 = _wrLegal_addr_T_17 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _wrLegal_addr_T_20 = {1'h0, _wrLegal_addr_T_19}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _wrLegal_addr_T_21 = _wrLegal_addr_T_20 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _wrLegal_addr_T_22 = _wrLegal_addr_T_21; // @[Parameters.scala:137:46]
wire _wrLegal_addr_T_23 = _wrLegal_addr_T_22 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _wrLegal_addr_T_25 = {1'h0, _wrLegal_addr_T_24}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _wrLegal_addr_T_26 = _wrLegal_addr_T_25 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _wrLegal_addr_T_27 = _wrLegal_addr_T_26; // @[Parameters.scala:137:46]
wire _wrLegal_addr_T_28 = _wrLegal_addr_T_27 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _wrLegal_addr_T_30 = {1'h0, _wrLegal_addr_T_29}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _wrLegal_addr_T_31 = _wrLegal_addr_T_30 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _wrLegal_addr_T_32 = _wrLegal_addr_T_31; // @[Parameters.scala:137:46]
wire _wrLegal_addr_T_33 = _wrLegal_addr_T_32 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _wrLegal_addr_T_35 = {1'h0, _wrLegal_addr_T_34}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _wrLegal_addr_T_36 = _wrLegal_addr_T_35 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFC000000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _wrLegal_addr_T_37 = _wrLegal_addr_T_36; // @[Parameters.scala:137:46]
wire _wrLegal_addr_T_38 = _wrLegal_addr_T_37 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _wrLegal_addr_T_40 = {1'h0, _wrLegal_addr_T_39}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _wrLegal_addr_T_41 = _wrLegal_addr_T_40 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _wrLegal_addr_T_42 = _wrLegal_addr_T_41; // @[Parameters.scala:137:46]
wire _wrLegal_addr_T_43 = _wrLegal_addr_T_42 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _wrLegal_addr_T_45 = {1'h0, _wrLegal_addr_T_44}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _wrLegal_addr_T_46 = _wrLegal_addr_T_45 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFF0000000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _wrLegal_addr_T_47 = _wrLegal_addr_T_46; // @[Parameters.scala:137:46]
wire _wrLegal_addr_T_48 = _wrLegal_addr_T_47 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire _wrLegal_addr_T_49 = _wrLegal_addr_T_8 | _wrLegal_addr_T_13; // @[Parameters.scala:685:42]
wire _wrLegal_addr_T_50 = _wrLegal_addr_T_49 | _wrLegal_addr_T_18; // @[Parameters.scala:685:42]
wire _wrLegal_addr_T_51 = _wrLegal_addr_T_50 | _wrLegal_addr_T_23; // @[Parameters.scala:685:42]
wire _wrLegal_addr_T_52 = _wrLegal_addr_T_51 | _wrLegal_addr_T_28; // @[Parameters.scala:685:42]
wire _wrLegal_addr_T_53 = _wrLegal_addr_T_52 | _wrLegal_addr_T_33; // @[Parameters.scala:685:42]
wire _wrLegal_addr_T_54 = _wrLegal_addr_T_53 | _wrLegal_addr_T_38; // @[Parameters.scala:685:42]
wire _wrLegal_addr_T_55 = _wrLegal_addr_T_54 | _wrLegal_addr_T_43; // @[Parameters.scala:685:42]
wire _wrLegal_addr_T_56 = _wrLegal_addr_T_55 | _wrLegal_addr_T_48; // @[Parameters.scala:685:42]
wire _wrLegal_addr_T_57 = _wrLegal_addr_T_56; // @[Parameters.scala:684:54, :685:42]
wire _wrLegal_addr_T_65 = _wrLegal_addr_T_57; // @[Parameters.scala:684:54, :686:26]
wire [128:0] _wrLegal_addr_T_60 = {1'h0, _wrLegal_addr_T_59}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _wrLegal_addr_T_61 = _wrLegal_addr_T_60 & 129'h1FFFFFFFFFFFFFFFFFFFFFFFFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _wrLegal_addr_T_62 = _wrLegal_addr_T_61; // @[Parameters.scala:137:46]
wire _wrLegal_addr_T_63 = _wrLegal_addr_T_62 == 129'h0; // @[Parameters.scala:137:{46,59}]
assign wrLegal_addr = _wrLegal_addr_T_65; // @[Parameters.scala:686:26]
assign io_wrLegal_0 = wrLegal_addr; // @[Parameters.scala:686:26]
wire [127:0] _GEN_9 = {io_addrIn_0[127:14], io_addrIn_0[13:0] ^ 14'h2000}; // @[Parameters.scala:137:31]
wire [127:0] _gbits_legal_T_4; // @[Parameters.scala:137:31]
assign _gbits_legal_T_4 = _GEN_9; // @[Parameters.scala:137:31]
wire [127:0] _pfbits_legal_T_4; // @[Parameters.scala:137:31]
assign _pfbits_legal_T_4 = _GEN_9; // @[Parameters.scala:137:31]
wire [128:0] _gbits_legal_T_5 = {1'h0, _gbits_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _gbits_legal_T_6 = _gbits_legal_T_5 & 129'hFFFFE000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _gbits_legal_T_7 = _gbits_legal_T_6; // @[Parameters.scala:137:46]
wire _gbits_legal_T_8 = _gbits_legal_T_7 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire _gbits_legal_T_9 = _gbits_legal_T_8; // @[Parameters.scala:684:54]
wire _gbits_legal_T_68 = _gbits_legal_T_9; // @[Parameters.scala:684:54, :686:26]
wire _GEN_10 = io_sizeIn_0 != 3'h7; // @[Parameters.scala:92:38]
wire _gbits_legal_T_11; // @[Parameters.scala:92:38]
assign _gbits_legal_T_11 = _GEN_10; // @[Parameters.scala:92:38]
wire _pfbits_legal_T_11; // @[Parameters.scala:92:38]
assign _pfbits_legal_T_11 = _GEN_10; // @[Parameters.scala:92:38]
wire _gbits_legal_T_12 = _gbits_legal_T_11; // @[Parameters.scala:92:{33,38}]
wire _gbits_legal_T_13 = _gbits_legal_T_12; // @[Parameters.scala:684:29]
wire [128:0] _gbits_legal_T_15 = {1'h0, _gbits_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _gbits_legal_T_16 = _gbits_legal_T_15 & 129'hFFFFE000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _gbits_legal_T_17 = _gbits_legal_T_16; // @[Parameters.scala:137:46]
wire _gbits_legal_T_18 = _gbits_legal_T_17 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _gbits_legal_T_20 = {1'h0, _gbits_legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _gbits_legal_T_21 = _gbits_legal_T_20 & 129'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _gbits_legal_T_22 = _gbits_legal_T_21; // @[Parameters.scala:137:46]
wire _gbits_legal_T_23 = _gbits_legal_T_22 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _gbits_legal_T_25 = {1'h0, _gbits_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _gbits_legal_T_26 = _gbits_legal_T_25 & 129'hFFFEE000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _gbits_legal_T_27 = _gbits_legal_T_26; // @[Parameters.scala:137:46]
wire _gbits_legal_T_28 = _gbits_legal_T_27 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _gbits_legal_T_30 = {1'h0, _gbits_legal_T_29}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _gbits_legal_T_31 = _gbits_legal_T_30 & 129'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _gbits_legal_T_32 = _gbits_legal_T_31; // @[Parameters.scala:137:46]
wire _gbits_legal_T_33 = _gbits_legal_T_32 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _gbits_legal_T_35 = {1'h0, _gbits_legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _gbits_legal_T_36 = _gbits_legal_T_35 & 129'hFFFFE000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _gbits_legal_T_37 = _gbits_legal_T_36; // @[Parameters.scala:137:46]
wire _gbits_legal_T_38 = _gbits_legal_T_37 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _gbits_legal_T_40 = {1'h0, _gbits_legal_T_39}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _gbits_legal_T_41 = _gbits_legal_T_40 & 129'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _gbits_legal_T_42 = _gbits_legal_T_41; // @[Parameters.scala:137:46]
wire _gbits_legal_T_43 = _gbits_legal_T_42 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _gbits_legal_T_45 = {1'h0, _gbits_legal_T_44}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _gbits_legal_T_46 = _gbits_legal_T_45 & 129'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _gbits_legal_T_47 = _gbits_legal_T_46; // @[Parameters.scala:137:46]
wire _gbits_legal_T_48 = _gbits_legal_T_47 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _gbits_legal_T_50 = {1'h0, _gbits_legal_T_49}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _gbits_legal_T_51 = _gbits_legal_T_50 & 129'hFFFFE000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _gbits_legal_T_52 = _gbits_legal_T_51; // @[Parameters.scala:137:46]
wire _gbits_legal_T_53 = _gbits_legal_T_52 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _gbits_legal_T_55 = {1'h0, _gbits_legal_T_54}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _gbits_legal_T_56 = _gbits_legal_T_55 & 129'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _gbits_legal_T_57 = _gbits_legal_T_56; // @[Parameters.scala:137:46]
wire _gbits_legal_T_58 = _gbits_legal_T_57 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire _gbits_legal_T_59 = _gbits_legal_T_18 | _gbits_legal_T_23; // @[Parameters.scala:685:42]
wire _gbits_legal_T_60 = _gbits_legal_T_59 | _gbits_legal_T_28; // @[Parameters.scala:685:42]
wire _gbits_legal_T_61 = _gbits_legal_T_60 | _gbits_legal_T_33; // @[Parameters.scala:685:42]
wire _gbits_legal_T_62 = _gbits_legal_T_61 | _gbits_legal_T_38; // @[Parameters.scala:685:42]
wire _gbits_legal_T_63 = _gbits_legal_T_62 | _gbits_legal_T_43; // @[Parameters.scala:685:42]
wire _gbits_legal_T_64 = _gbits_legal_T_63 | _gbits_legal_T_48; // @[Parameters.scala:685:42]
wire _gbits_legal_T_65 = _gbits_legal_T_64 | _gbits_legal_T_53; // @[Parameters.scala:685:42]
wire _gbits_legal_T_66 = _gbits_legal_T_65 | _gbits_legal_T_58; // @[Parameters.scala:685:42]
wire _gbits_legal_T_67 = _gbits_legal_T_13 & _gbits_legal_T_66; // @[Parameters.scala:684:{29,54}, :685:42]
wire gbits_legal = _gbits_legal_T_68 | _gbits_legal_T_67; // @[Parameters.scala:684:54, :686:26]
wire [3:0] gbits_size; // @[Edges.scala:460:17]
wire [3:0] _GEN_11 = {1'h0, io_sizeIn_0}; // @[Edges.scala:463:15]
assign gbits_size = _GEN_11; // @[Edges.scala:460:17, :463:15]
wire [3:0] pfbits_size; // @[Edges.scala:480:17]
assign pfbits_size = _GEN_11; // @[Edges.scala:463:15, :480:17]
wire [128:0] _pfbits_legal_T_5 = {1'h0, _pfbits_legal_T_4}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _pfbits_legal_T_6 = _pfbits_legal_T_5 & 129'h9E112000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _pfbits_legal_T_7 = _pfbits_legal_T_6; // @[Parameters.scala:137:46]
wire _pfbits_legal_T_8 = _pfbits_legal_T_7 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire _pfbits_legal_T_9 = _pfbits_legal_T_8; // @[Parameters.scala:684:54]
wire _pfbits_legal_T_63 = _pfbits_legal_T_9; // @[Parameters.scala:684:54, :686:26]
wire _pfbits_legal_T_12 = _pfbits_legal_T_11; // @[Parameters.scala:92:{33,38}]
wire _pfbits_legal_T_13 = _pfbits_legal_T_12; // @[Parameters.scala:684:29]
wire [128:0] _pfbits_legal_T_15 = {1'h0, _pfbits_legal_T_14}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _pfbits_legal_T_16 = _pfbits_legal_T_15 & 129'h8E112000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _pfbits_legal_T_17 = _pfbits_legal_T_16; // @[Parameters.scala:137:46]
wire _pfbits_legal_T_18 = _pfbits_legal_T_17 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _pfbits_legal_T_20 = {1'h0, _pfbits_legal_T_19}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _pfbits_legal_T_21 = _pfbits_legal_T_20 & 129'h9E102000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _pfbits_legal_T_22 = _pfbits_legal_T_21; // @[Parameters.scala:137:46]
wire _pfbits_legal_T_23 = _pfbits_legal_T_22 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _pfbits_legal_T_25 = {1'h0, _pfbits_legal_T_24}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _pfbits_legal_T_26 = _pfbits_legal_T_25 & 129'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _pfbits_legal_T_27 = _pfbits_legal_T_26; // @[Parameters.scala:137:46]
wire _pfbits_legal_T_28 = _pfbits_legal_T_27 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _pfbits_legal_T_30 = {1'h0, _pfbits_legal_T_29}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _pfbits_legal_T_31 = _pfbits_legal_T_30 & 129'h9E112000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _pfbits_legal_T_32 = _pfbits_legal_T_31; // @[Parameters.scala:137:46]
wire _pfbits_legal_T_33 = _pfbits_legal_T_32 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _pfbits_legal_T_35 = {1'h0, _pfbits_legal_T_34}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _pfbits_legal_T_36 = _pfbits_legal_T_35 & 129'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _pfbits_legal_T_37 = _pfbits_legal_T_36; // @[Parameters.scala:137:46]
wire _pfbits_legal_T_38 = _pfbits_legal_T_37 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _pfbits_legal_T_40 = {1'h0, _pfbits_legal_T_39}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _pfbits_legal_T_41 = _pfbits_legal_T_40 & 129'h9C000000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _pfbits_legal_T_42 = _pfbits_legal_T_41; // @[Parameters.scala:137:46]
wire _pfbits_legal_T_43 = _pfbits_legal_T_42 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire [128:0] _pfbits_legal_T_45 = {1'h0, _pfbits_legal_T_44}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _pfbits_legal_T_46 = _pfbits_legal_T_45 & 129'h90000000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _pfbits_legal_T_47 = _pfbits_legal_T_46; // @[Parameters.scala:137:46]
wire _pfbits_legal_T_48 = _pfbits_legal_T_47 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire _pfbits_legal_T_49 = _pfbits_legal_T_18 | _pfbits_legal_T_23; // @[Parameters.scala:685:42]
wire _pfbits_legal_T_50 = _pfbits_legal_T_49 | _pfbits_legal_T_28; // @[Parameters.scala:685:42]
wire _pfbits_legal_T_51 = _pfbits_legal_T_50 | _pfbits_legal_T_33; // @[Parameters.scala:685:42]
wire _pfbits_legal_T_52 = _pfbits_legal_T_51 | _pfbits_legal_T_38; // @[Parameters.scala:685:42]
wire _pfbits_legal_T_53 = _pfbits_legal_T_52 | _pfbits_legal_T_43; // @[Parameters.scala:685:42]
wire _pfbits_legal_T_54 = _pfbits_legal_T_53 | _pfbits_legal_T_48; // @[Parameters.scala:685:42]
wire _pfbits_legal_T_55 = _pfbits_legal_T_13 & _pfbits_legal_T_54; // @[Parameters.scala:684:{29,54}, :685:42]
wire [128:0] _pfbits_legal_T_58 = {1'h0, _pfbits_legal_T_57}; // @[Parameters.scala:137:{31,41}]
wire [128:0] _pfbits_legal_T_59 = _pfbits_legal_T_58 & 129'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [128:0] _pfbits_legal_T_60 = _pfbits_legal_T_59; // @[Parameters.scala:137:46]
wire _pfbits_legal_T_61 = _pfbits_legal_T_60 == 129'h0; // @[Parameters.scala:137:{46,59}]
wire _pfbits_legal_T_64 = _pfbits_legal_T_63 | _pfbits_legal_T_55; // @[Parameters.scala:684:54, :686:26]
wire pfbits_legal = _pfbits_legal_T_64; // @[Parameters.scala:686:26]
wire _nodeOut_a_valid_T = sbState == 3'h1; // @[SBA.scala:295:26, :322:18, :366:28]
assign nodeOut_a_bits_opcode = {_nodeOut_a_valid_T, 2'h0}; // @[SBA.scala:322:{42,54}, :323:54, :366:28]
assign nodeOut_a_bits_size = _nodeOut_a_valid_T ? gbits_size : pfbits_size; // @[Edges.scala:460:17, :480:17]
assign nodeOut_a_bits_address = _nodeOut_a_valid_T ? gbits_address : pfbits_address; // @[Edges.scala:460:17, :480:17]
assign nodeOut_a_bits_data = _nodeOut_a_valid_T ? 8'h0 : pfbits_data; // @[Edges.scala:480:17]
assign respError = _d_q_io_deq_bits_denied | _d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21]
assign io_respError_0 = respError; // @[SBA.scala:273:9, :335:35]
wire _T_20 = sbState == 3'h2; // @[SBA.scala:295:26, :338:29]
wire _wrTxValid_T; // @[SBA.scala:338:29]
assign _wrTxValid_T = _T_20; // @[SBA.scala:338:29]
wire _nodeOut_a_valid_T_1; // @[SBA.scala:366:64]
assign _nodeOut_a_valid_T_1 = _T_20; // @[SBA.scala:338:29, :366:64]
wire _wrTxValid_T_1 = _wrTxValid_T & nodeOut_a_valid; // @[SBA.scala:338:{29,53}]
wire wrTxValid = _wrTxValid_T_1 & nodeOut_a_ready; // @[SBA.scala:338:{53,69}]
wire _rdTxValid_T_1 = _rdTxValid_T & _d_q_io_deq_valid; // @[Decoupled.scala:362:21]
wire rdTxValid = _rdTxValid_T_1 & _q_io_deq_ready_T_2; // @[SBA.scala:299:50, :339:{53,70}]
wire [7:0] _txLast_T = 8'h1 << io_sizeIn_0; // @[SBA.scala:273:9, :340:39]
wire [8:0] _txLast_T_1 = {1'h0, _txLast_T} - 9'h1; // @[SBA.scala:340:{39,53}]
wire [7:0] _txLast_T_2 = _txLast_T_1[7:0]; // @[SBA.scala:340:53]
wire txLast = {4'h0, counter} == _txLast_T_2; // @[SBA.scala:307:26, :340:{29,53}]
wire _GEN_12 = wrTxValid | rdTxValid; // @[SBA.scala:338:69, :339:70, :341:31]
wire _counter_T; // @[SBA.scala:341:31]
assign _counter_T = _GEN_12; // @[SBA.scala:341:31]
wire _counter_T_2; // @[SBA.scala:342:31]
assign _counter_T_2 = _GEN_12; // @[SBA.scala:341:31, :342:31]
wire _counter_T_1 = _counter_T & txLast; // @[SBA.scala:340:29, :341:{31,45}]
wire [4:0] _counter_T_3 = {1'h0, counter} + 5'h1; // @[SBA.scala:307:26, :342:63]
wire [3:0] _counter_T_4 = _counter_T_3[3:0]; // @[SBA.scala:342:63]
wire [3:0] _counter_T_5 = _counter_T_2 ? _counter_T_4 : counter; // @[SBA.scala:307:26, :342:{19,31,63}]
wire [3:0] _counter_T_6 = _counter_T_1 ? 4'h0 : _counter_T_5; // @[SBA.scala:341:{19,45}, :342:19]
wire _io_rdLoad_0_T = counter == 4'h0; // @[SBA.scala:307:26, :345:45]
assign _io_rdLoad_0_T_1 = rdTxValid & _io_rdLoad_0_T; // @[SBA.scala:339:70, :345:{33,45}]
assign io_rdLoad_0_0 = _io_rdLoad_0_T_1; // @[SBA.scala:273:9, :345:33]
wire _io_rdLoad_1_T = counter == 4'h1; // @[SBA.scala:307:26, :345:45]
assign _io_rdLoad_1_T_1 = rdTxValid & _io_rdLoad_1_T; // @[SBA.scala:339:70, :345:{33,45}]
assign io_rdLoad_1_0 = _io_rdLoad_1_T_1; // @[SBA.scala:273:9, :345:33]
wire _io_rdLoad_2_T = counter == 4'h2; // @[SBA.scala:307:26, :345:45]
assign _io_rdLoad_2_T_1 = rdTxValid & _io_rdLoad_2_T; // @[SBA.scala:339:70, :345:{33,45}]
assign io_rdLoad_2_0 = _io_rdLoad_2_T_1; // @[SBA.scala:273:9, :345:33]
wire _io_rdLoad_3_T = counter == 4'h3; // @[SBA.scala:307:26, :345:45]
assign _io_rdLoad_3_T_1 = rdTxValid & _io_rdLoad_3_T; // @[SBA.scala:339:70, :345:{33,45}]
assign io_rdLoad_3_0 = _io_rdLoad_3_T_1; // @[SBA.scala:273:9, :345:33]
wire _io_rdLoad_4_T = counter == 4'h4; // @[SBA.scala:307:26, :345:45]
assign _io_rdLoad_4_T_1 = rdTxValid & _io_rdLoad_4_T; // @[SBA.scala:339:70, :345:{33,45}]
assign io_rdLoad_4_0 = _io_rdLoad_4_T_1; // @[SBA.scala:273:9, :345:33]
wire _io_rdLoad_5_T = counter == 4'h5; // @[SBA.scala:307:26, :345:45]
assign _io_rdLoad_5_T_1 = rdTxValid & _io_rdLoad_5_T; // @[SBA.scala:339:70, :345:{33,45}]
assign io_rdLoad_5_0 = _io_rdLoad_5_T_1; // @[SBA.scala:273:9, :345:33]
wire _io_rdLoad_6_T = counter == 4'h6; // @[SBA.scala:307:26, :345:45]
assign _io_rdLoad_6_T_1 = rdTxValid & _io_rdLoad_6_T; // @[SBA.scala:339:70, :345:{33,45}]
assign io_rdLoad_6_0 = _io_rdLoad_6_T_1; // @[SBA.scala:273:9, :345:33]
wire _io_rdLoad_7_T = counter == 4'h7; // @[SBA.scala:307:26, :345:45]
assign _io_rdLoad_7_T_1 = rdTxValid & _io_rdLoad_7_T; // @[SBA.scala:339:70, :345:{33,45}]
assign io_rdLoad_7_0 = _io_rdLoad_7_T_1; // @[SBA.scala:273:9, :345:33]
wire _sbState_T = io_rdEn_0 & io_rdLegal_0; // @[SBA.scala:273:9, :350:30]
wire _sbState_T_1 = io_wrEn_0 & io_wrLegal_0; // @[SBA.scala:273:9, :351:30]
wire [2:0] _sbState_T_2 = _sbState_T_1 ? 3'h2 : sbState; // @[SBA.scala:295:26, :351:{21,30}]
wire [2:0] _sbState_T_3 = _sbState_T ? 3'h1 : _sbState_T_2; // @[SBA.scala:350:{21,30}, :351:21]
wire _sbState_T_4 = nodeOut_a_valid & nodeOut_a_ready; // @[SBA.scala:353:35]
wire [2:0] _sbState_T_5 = _sbState_T_4 ? 3'h3 : sbState; // @[SBA.scala:295:26, :353:{21,35}]
wire _sbState_T_6 = wrTxValid & txLast; // @[SBA.scala:338:69, :340:29, :355:32]
wire [2:0] _sbState_T_7 = _sbState_T_6 ? 3'h4 : sbState; // @[SBA.scala:295:26, :355:{21,32}]
wire _GEN_13 = rdTxValid & txLast; // @[SBA.scala:339:70, :340:29, :357:32]
wire _sbState_T_8; // @[SBA.scala:357:32]
assign _sbState_T_8 = _GEN_13; // @[SBA.scala:357:32]
assign _io_rdDone_T = _GEN_13; // @[SBA.scala:357:32, :362:29]
wire [2:0] _sbState_T_9 = _sbState_T_8 ? 3'h0 : sbState; // @[SBA.scala:295:26, :357:{21,32}]
wire _sbState_T_10 = _d_q_io_deq_valid & _q_io_deq_ready_T_2; // @[Decoupled.scala:362:21]
wire [2:0] _sbState_T_11 = _sbState_T_10 ? 3'h0 : sbState; // @[SBA.scala:295:26, :359:{21,36}]
assign io_rdDone_0 = _io_rdDone_T; // @[SBA.scala:273:9, :362:29]
wire _io_wrDone_T_1 = _io_wrDone_T & _d_q_io_deq_valid; // @[Decoupled.scala:362:21]
assign _io_wrDone_T_2 = _io_wrDone_T_1 & _q_io_deq_ready_T_2; // @[SBA.scala:299:50, :363:{54,71}]
assign io_wrDone_0 = _io_wrDone_T_2; // @[SBA.scala:273:9, :363:71]
assign _nodeOut_a_valid_T_2 = _nodeOut_a_valid_T | _nodeOut_a_valid_T_1; // @[SBA.scala:366:{28,52,64}]
assign nodeOut_a_valid = _nodeOut_a_valid_T_2; // @[SBA.scala:366:52] |
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_mbus_i4_o2_a32d64s7k1z3u :
input clock : Clock
input reset : Reset
output auto : { flip anon_in_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn_1.d.bits.corrupt
invalidate anonIn_1.d.bits.data
invalidate anonIn_1.d.bits.denied
invalidate anonIn_1.d.bits.sink
invalidate anonIn_1.d.bits.source
invalidate anonIn_1.d.bits.size
invalidate anonIn_1.d.bits.param
invalidate anonIn_1.d.bits.opcode
invalidate anonIn_1.d.valid
invalidate anonIn_1.d.ready
invalidate anonIn_1.a.bits.corrupt
invalidate anonIn_1.a.bits.data
invalidate anonIn_1.a.bits.mask
invalidate anonIn_1.a.bits.address
invalidate anonIn_1.a.bits.source
invalidate anonIn_1.a.bits.size
invalidate anonIn_1.a.bits.param
invalidate anonIn_1.a.bits.opcode
invalidate anonIn_1.a.valid
invalidate anonIn_1.a.ready
wire anonIn_2 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn_2.d.bits.corrupt
invalidate anonIn_2.d.bits.data
invalidate anonIn_2.d.bits.denied
invalidate anonIn_2.d.bits.sink
invalidate anonIn_2.d.bits.source
invalidate anonIn_2.d.bits.size
invalidate anonIn_2.d.bits.param
invalidate anonIn_2.d.bits.opcode
invalidate anonIn_2.d.valid
invalidate anonIn_2.d.ready
invalidate anonIn_2.a.bits.corrupt
invalidate anonIn_2.a.bits.data
invalidate anonIn_2.a.bits.mask
invalidate anonIn_2.a.bits.address
invalidate anonIn_2.a.bits.source
invalidate anonIn_2.a.bits.size
invalidate anonIn_2.a.bits.param
invalidate anonIn_2.a.bits.opcode
invalidate anonIn_2.a.valid
invalidate anonIn_2.a.ready
wire anonIn_3 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonIn_3.d.bits.corrupt
invalidate anonIn_3.d.bits.data
invalidate anonIn_3.d.bits.denied
invalidate anonIn_3.d.bits.sink
invalidate anonIn_3.d.bits.source
invalidate anonIn_3.d.bits.size
invalidate anonIn_3.d.bits.param
invalidate anonIn_3.d.bits.opcode
invalidate anonIn_3.d.valid
invalidate anonIn_3.d.ready
invalidate anonIn_3.a.bits.corrupt
invalidate anonIn_3.a.bits.data
invalidate anonIn_3.a.bits.mask
invalidate anonIn_3.a.bits.address
invalidate anonIn_3.a.bits.source
invalidate anonIn_3.a.bits.size
invalidate anonIn_3.a.bits.param
invalidate anonIn_3.a.bits.opcode
invalidate anonIn_3.a.valid
invalidate anonIn_3.a.ready
inst monitor of TLMonitor_41
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
inst monitor_1 of TLMonitor_42
connect monitor_1.clock, clock
connect monitor_1.reset, reset
connect monitor_1.io.in.d.bits.corrupt, anonIn_1.d.bits.corrupt
connect monitor_1.io.in.d.bits.data, anonIn_1.d.bits.data
connect monitor_1.io.in.d.bits.denied, anonIn_1.d.bits.denied
connect monitor_1.io.in.d.bits.sink, anonIn_1.d.bits.sink
connect monitor_1.io.in.d.bits.source, anonIn_1.d.bits.source
connect monitor_1.io.in.d.bits.size, anonIn_1.d.bits.size
connect monitor_1.io.in.d.bits.param, anonIn_1.d.bits.param
connect monitor_1.io.in.d.bits.opcode, anonIn_1.d.bits.opcode
connect monitor_1.io.in.d.valid, anonIn_1.d.valid
connect monitor_1.io.in.d.ready, anonIn_1.d.ready
connect monitor_1.io.in.a.bits.corrupt, anonIn_1.a.bits.corrupt
connect monitor_1.io.in.a.bits.data, anonIn_1.a.bits.data
connect monitor_1.io.in.a.bits.mask, anonIn_1.a.bits.mask
connect monitor_1.io.in.a.bits.address, anonIn_1.a.bits.address
connect monitor_1.io.in.a.bits.source, anonIn_1.a.bits.source
connect monitor_1.io.in.a.bits.size, anonIn_1.a.bits.size
connect monitor_1.io.in.a.bits.param, anonIn_1.a.bits.param
connect monitor_1.io.in.a.bits.opcode, anonIn_1.a.bits.opcode
connect monitor_1.io.in.a.valid, anonIn_1.a.valid
connect monitor_1.io.in.a.ready, anonIn_1.a.ready
inst monitor_2 of TLMonitor_43
connect monitor_2.clock, clock
connect monitor_2.reset, reset
connect monitor_2.io.in.d.bits.corrupt, anonIn_2.d.bits.corrupt
connect monitor_2.io.in.d.bits.data, anonIn_2.d.bits.data
connect monitor_2.io.in.d.bits.denied, anonIn_2.d.bits.denied
connect monitor_2.io.in.d.bits.sink, anonIn_2.d.bits.sink
connect monitor_2.io.in.d.bits.source, anonIn_2.d.bits.source
connect monitor_2.io.in.d.bits.size, anonIn_2.d.bits.size
connect monitor_2.io.in.d.bits.param, anonIn_2.d.bits.param
connect monitor_2.io.in.d.bits.opcode, anonIn_2.d.bits.opcode
connect monitor_2.io.in.d.valid, anonIn_2.d.valid
connect monitor_2.io.in.d.ready, anonIn_2.d.ready
connect monitor_2.io.in.a.bits.corrupt, anonIn_2.a.bits.corrupt
connect monitor_2.io.in.a.bits.data, anonIn_2.a.bits.data
connect monitor_2.io.in.a.bits.mask, anonIn_2.a.bits.mask
connect monitor_2.io.in.a.bits.address, anonIn_2.a.bits.address
connect monitor_2.io.in.a.bits.source, anonIn_2.a.bits.source
connect monitor_2.io.in.a.bits.size, anonIn_2.a.bits.size
connect monitor_2.io.in.a.bits.param, anonIn_2.a.bits.param
connect monitor_2.io.in.a.bits.opcode, anonIn_2.a.bits.opcode
connect monitor_2.io.in.a.valid, anonIn_2.a.valid
connect monitor_2.io.in.a.ready, anonIn_2.a.ready
inst monitor_3 of TLMonitor_44
connect monitor_3.clock, clock
connect monitor_3.reset, reset
connect monitor_3.io.in.d.bits.corrupt, anonIn_3.d.bits.corrupt
connect monitor_3.io.in.d.bits.data, anonIn_3.d.bits.data
connect monitor_3.io.in.d.bits.denied, anonIn_3.d.bits.denied
connect monitor_3.io.in.d.bits.sink, anonIn_3.d.bits.sink
connect monitor_3.io.in.d.bits.source, anonIn_3.d.bits.source
connect monitor_3.io.in.d.bits.size, anonIn_3.d.bits.size
connect monitor_3.io.in.d.bits.param, anonIn_3.d.bits.param
connect monitor_3.io.in.d.bits.opcode, anonIn_3.d.bits.opcode
connect monitor_3.io.in.d.valid, anonIn_3.d.valid
connect monitor_3.io.in.d.ready, anonIn_3.d.ready
connect monitor_3.io.in.a.bits.corrupt, anonIn_3.a.bits.corrupt
connect monitor_3.io.in.a.bits.data, anonIn_3.a.bits.data
connect monitor_3.io.in.a.bits.mask, anonIn_3.a.bits.mask
connect monitor_3.io.in.a.bits.address, anonIn_3.a.bits.address
connect monitor_3.io.in.a.bits.source, anonIn_3.a.bits.source
connect monitor_3.io.in.a.bits.size, anonIn_3.a.bits.size
connect monitor_3.io.in.a.bits.param, anonIn_3.a.bits.param
connect monitor_3.io.in.a.bits.opcode, anonIn_3.a.bits.opcode
connect monitor_3.io.in.a.valid, anonIn_3.a.valid
connect monitor_3.io.in.a.ready, anonIn_3.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
wire x1_anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate x1_anonOut.d.bits.corrupt
invalidate x1_anonOut.d.bits.data
invalidate x1_anonOut.d.bits.denied
invalidate x1_anonOut.d.bits.sink
invalidate x1_anonOut.d.bits.source
invalidate x1_anonOut.d.bits.size
invalidate x1_anonOut.d.bits.param
invalidate x1_anonOut.d.bits.opcode
invalidate x1_anonOut.d.valid
invalidate x1_anonOut.d.ready
invalidate x1_anonOut.a.bits.corrupt
invalidate x1_anonOut.a.bits.data
invalidate x1_anonOut.a.bits.mask
invalidate x1_anonOut.a.bits.address
invalidate x1_anonOut.a.bits.source
invalidate x1_anonOut.a.bits.size
invalidate x1_anonOut.a.bits.param
invalidate x1_anonOut.a.bits.opcode
invalidate x1_anonOut.a.valid
invalidate x1_anonOut.a.ready
connect auto.anon_out_0, anonOut
connect auto.anon_out_1, x1_anonOut
connect anonIn, auto.anon_in_0
connect anonIn_1, auto.anon_in_1
connect anonIn_2, auto.anon_in_2
connect anonIn_3, auto.anon_in_3
wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[4]
connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt
connect in[0].a.bits.data, anonIn.a.bits.data
connect in[0].a.bits.mask, anonIn.a.bits.mask
connect in[0].a.bits.address, anonIn.a.bits.address
connect in[0].a.bits.source, anonIn.a.bits.source
connect in[0].a.bits.size, anonIn.a.bits.size
connect in[0].a.bits.param, anonIn.a.bits.param
connect in[0].a.bits.opcode, anonIn.a.bits.opcode
connect in[0].a.valid, anonIn.a.valid
connect anonIn.a.ready, in[0].a.ready
node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<7>(0h60))
connect in[0].a.bits.source, _in_0_a_bits_source_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<7>(0h0)
connect _WIRE.bits.size, UInt<3>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
invalidate _WIRE_1.bits.corrupt
invalidate _WIRE_1.bits.data
invalidate _WIRE_1.bits.mask
invalidate _WIRE_1.bits.address
invalidate _WIRE_1.bits.source
invalidate _WIRE_1.bits.size
invalidate _WIRE_1.bits.param
invalidate _WIRE_1.bits.opcode
invalidate _WIRE_1.valid
invalidate _WIRE_1.ready
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.mask, UInt<8>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<5>(0h0)
connect _WIRE_2.bits.size, UInt<3>(0h0)
connect _WIRE_2.bits.param, UInt<2>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
invalidate _WIRE_3.bits.corrupt
invalidate _WIRE_3.bits.data
invalidate _WIRE_3.bits.mask
invalidate _WIRE_3.bits.address
invalidate _WIRE_3.bits.source
invalidate _WIRE_3.bits.size
invalidate _WIRE_3.bits.param
invalidate _WIRE_3.bits.opcode
invalidate _WIRE_3.valid
invalidate _WIRE_3.ready
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<64>(0h0)
connect _WIRE_4.bits.mask, UInt<8>(0h0)
connect _WIRE_4.bits.address, UInt<32>(0h0)
connect _WIRE_4.bits.source, UInt<7>(0h0)
connect _WIRE_4.bits.size, UInt<3>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.mask, UInt<8>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<5>(0h0)
connect _WIRE_6.bits.size, UInt<3>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.valid, UInt<1>(0h0)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<7>(0h0)
connect _WIRE_8.bits.size, UInt<3>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
invalidate _WIRE_9.bits.corrupt
invalidate _WIRE_9.bits.data
invalidate _WIRE_9.bits.address
invalidate _WIRE_9.bits.source
invalidate _WIRE_9.bits.size
invalidate _WIRE_9.bits.param
invalidate _WIRE_9.bits.opcode
invalidate _WIRE_9.valid
invalidate _WIRE_9.ready
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<5>(0h0)
connect _WIRE_10.bits.size, UInt<3>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
invalidate _WIRE_11.bits.corrupt
invalidate _WIRE_11.bits.data
invalidate _WIRE_11.bits.address
invalidate _WIRE_11.bits.source
invalidate _WIRE_11.bits.size
invalidate _WIRE_11.bits.param
invalidate _WIRE_11.bits.opcode
invalidate _WIRE_11.valid
invalidate _WIRE_11.ready
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<7>(0h0)
connect _WIRE_12.bits.size, UInt<3>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
connect _WIRE_13.valid, UInt<1>(0h0)
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<5>(0h0)
connect _WIRE_14.bits.size, UInt<3>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
connect _WIRE_15.ready, UInt<1>(0h1)
connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt
connect anonIn.d.bits.data, in[0].d.bits.data
connect anonIn.d.bits.denied, in[0].d.bits.denied
connect anonIn.d.bits.sink, in[0].d.bits.sink
connect anonIn.d.bits.source, in[0].d.bits.source
connect anonIn.d.bits.size, in[0].d.bits.size
connect anonIn.d.bits.param, in[0].d.bits.param
connect anonIn.d.bits.opcode, in[0].d.bits.opcode
connect anonIn.d.valid, in[0].d.valid
connect in[0].d.ready, anonIn.d.ready
node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 4, 0)
connect anonIn.d.bits.source, _anonIn_d_bits_source_T
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_16.bits.sink, UInt<1>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
invalidate _WIRE_17.bits.sink
invalidate _WIRE_17.valid
invalidate _WIRE_17.ready
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_18.bits.sink, UInt<1>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
invalidate _WIRE_19.bits.sink
invalidate _WIRE_19.valid
invalidate _WIRE_19.ready
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_20.bits.sink, UInt<1>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
connect _WIRE_21.valid, UInt<1>(0h0)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_22.bits.sink, UInt<1>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
connect _WIRE_23.ready, UInt<1>(0h1)
connect in[1].a.bits.corrupt, anonIn_1.a.bits.corrupt
connect in[1].a.bits.data, anonIn_1.a.bits.data
connect in[1].a.bits.mask, anonIn_1.a.bits.mask
connect in[1].a.bits.address, anonIn_1.a.bits.address
connect in[1].a.bits.source, anonIn_1.a.bits.source
connect in[1].a.bits.size, anonIn_1.a.bits.size
connect in[1].a.bits.param, anonIn_1.a.bits.param
connect in[1].a.bits.opcode, anonIn_1.a.bits.opcode
connect in[1].a.valid, anonIn_1.a.valid
connect anonIn_1.a.ready, in[1].a.ready
node _in_1_a_bits_source_T = or(anonIn_1.a.bits.source, UInt<7>(0h40))
connect in[1].a.bits.source, _in_1_a_bits_source_T
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.mask, UInt<8>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<7>(0h0)
connect _WIRE_24.bits.size, UInt<3>(0h0)
connect _WIRE_24.bits.param, UInt<2>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
invalidate _WIRE_25.bits.corrupt
invalidate _WIRE_25.bits.data
invalidate _WIRE_25.bits.mask
invalidate _WIRE_25.bits.address
invalidate _WIRE_25.bits.source
invalidate _WIRE_25.bits.size
invalidate _WIRE_25.bits.param
invalidate _WIRE_25.bits.opcode
invalidate _WIRE_25.valid
invalidate _WIRE_25.ready
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<64>(0h0)
connect _WIRE_26.bits.mask, UInt<8>(0h0)
connect _WIRE_26.bits.address, UInt<32>(0h0)
connect _WIRE_26.bits.source, UInt<5>(0h0)
connect _WIRE_26.bits.size, UInt<3>(0h0)
connect _WIRE_26.bits.param, UInt<2>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
invalidate _WIRE_27.bits.corrupt
invalidate _WIRE_27.bits.data
invalidate _WIRE_27.bits.mask
invalidate _WIRE_27.bits.address
invalidate _WIRE_27.bits.source
invalidate _WIRE_27.bits.size
invalidate _WIRE_27.bits.param
invalidate _WIRE_27.bits.opcode
invalidate _WIRE_27.valid
invalidate _WIRE_27.ready
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<64>(0h0)
connect _WIRE_28.bits.mask, UInt<8>(0h0)
connect _WIRE_28.bits.address, UInt<32>(0h0)
connect _WIRE_28.bits.source, UInt<7>(0h0)
connect _WIRE_28.bits.size, UInt<3>(0h0)
connect _WIRE_28.bits.param, UInt<2>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
connect _WIRE_29.ready, UInt<1>(0h1)
wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_30.bits.corrupt, UInt<1>(0h0)
connect _WIRE_30.bits.data, UInt<64>(0h0)
connect _WIRE_30.bits.mask, UInt<8>(0h0)
connect _WIRE_30.bits.address, UInt<32>(0h0)
connect _WIRE_30.bits.source, UInt<5>(0h0)
connect _WIRE_30.bits.size, UInt<3>(0h0)
connect _WIRE_30.bits.param, UInt<2>(0h0)
connect _WIRE_30.bits.opcode, UInt<3>(0h0)
connect _WIRE_30.valid, UInt<1>(0h0)
connect _WIRE_30.ready, UInt<1>(0h0)
wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_31.bits, _WIRE_30.bits
connect _WIRE_31.valid, _WIRE_30.valid
connect _WIRE_31.ready, _WIRE_30.ready
connect _WIRE_31.valid, UInt<1>(0h0)
wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_32.bits.corrupt, UInt<1>(0h0)
connect _WIRE_32.bits.data, UInt<64>(0h0)
connect _WIRE_32.bits.address, UInt<32>(0h0)
connect _WIRE_32.bits.source, UInt<7>(0h0)
connect _WIRE_32.bits.size, UInt<3>(0h0)
connect _WIRE_32.bits.param, UInt<3>(0h0)
connect _WIRE_32.bits.opcode, UInt<3>(0h0)
connect _WIRE_32.valid, UInt<1>(0h0)
connect _WIRE_32.ready, UInt<1>(0h0)
wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_33.bits, _WIRE_32.bits
connect _WIRE_33.valid, _WIRE_32.valid
connect _WIRE_33.ready, _WIRE_32.ready
invalidate _WIRE_33.bits.corrupt
invalidate _WIRE_33.bits.data
invalidate _WIRE_33.bits.address
invalidate _WIRE_33.bits.source
invalidate _WIRE_33.bits.size
invalidate _WIRE_33.bits.param
invalidate _WIRE_33.bits.opcode
invalidate _WIRE_33.valid
invalidate _WIRE_33.ready
wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_34.bits.corrupt, UInt<1>(0h0)
connect _WIRE_34.bits.data, UInt<64>(0h0)
connect _WIRE_34.bits.address, UInt<32>(0h0)
connect _WIRE_34.bits.source, UInt<5>(0h0)
connect _WIRE_34.bits.size, UInt<3>(0h0)
connect _WIRE_34.bits.param, UInt<3>(0h0)
connect _WIRE_34.bits.opcode, UInt<3>(0h0)
connect _WIRE_34.valid, UInt<1>(0h0)
connect _WIRE_34.ready, UInt<1>(0h0)
wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_35.bits, _WIRE_34.bits
connect _WIRE_35.valid, _WIRE_34.valid
connect _WIRE_35.ready, _WIRE_34.ready
invalidate _WIRE_35.bits.corrupt
invalidate _WIRE_35.bits.data
invalidate _WIRE_35.bits.address
invalidate _WIRE_35.bits.source
invalidate _WIRE_35.bits.size
invalidate _WIRE_35.bits.param
invalidate _WIRE_35.bits.opcode
invalidate _WIRE_35.valid
invalidate _WIRE_35.ready
wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_36.bits.corrupt, UInt<1>(0h0)
connect _WIRE_36.bits.data, UInt<64>(0h0)
connect _WIRE_36.bits.address, UInt<32>(0h0)
connect _WIRE_36.bits.source, UInt<7>(0h0)
connect _WIRE_36.bits.size, UInt<3>(0h0)
connect _WIRE_36.bits.param, UInt<3>(0h0)
connect _WIRE_36.bits.opcode, UInt<3>(0h0)
connect _WIRE_36.valid, UInt<1>(0h0)
connect _WIRE_36.ready, UInt<1>(0h0)
wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_37.bits, _WIRE_36.bits
connect _WIRE_37.valid, _WIRE_36.valid
connect _WIRE_37.ready, _WIRE_36.ready
connect _WIRE_37.valid, UInt<1>(0h0)
wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_38.bits.corrupt, UInt<1>(0h0)
connect _WIRE_38.bits.data, UInt<64>(0h0)
connect _WIRE_38.bits.address, UInt<32>(0h0)
connect _WIRE_38.bits.source, UInt<5>(0h0)
connect _WIRE_38.bits.size, UInt<3>(0h0)
connect _WIRE_38.bits.param, UInt<3>(0h0)
connect _WIRE_38.bits.opcode, UInt<3>(0h0)
connect _WIRE_38.valid, UInt<1>(0h0)
connect _WIRE_38.ready, UInt<1>(0h0)
wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_39.bits, _WIRE_38.bits
connect _WIRE_39.valid, _WIRE_38.valid
connect _WIRE_39.ready, _WIRE_38.ready
connect _WIRE_39.ready, UInt<1>(0h1)
connect anonIn_1.d.bits.corrupt, in[1].d.bits.corrupt
connect anonIn_1.d.bits.data, in[1].d.bits.data
connect anonIn_1.d.bits.denied, in[1].d.bits.denied
connect anonIn_1.d.bits.sink, in[1].d.bits.sink
connect anonIn_1.d.bits.source, in[1].d.bits.source
connect anonIn_1.d.bits.size, in[1].d.bits.size
connect anonIn_1.d.bits.param, in[1].d.bits.param
connect anonIn_1.d.bits.opcode, in[1].d.bits.opcode
connect anonIn_1.d.valid, in[1].d.valid
connect in[1].d.ready, anonIn_1.d.ready
node _anonIn_d_bits_source_T_1 = bits(in[1].d.bits.source, 4, 0)
connect anonIn_1.d.bits.source, _anonIn_d_bits_source_T_1
wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_40.bits.sink, UInt<1>(0h0)
connect _WIRE_40.valid, UInt<1>(0h0)
connect _WIRE_40.ready, UInt<1>(0h0)
wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_41.bits, _WIRE_40.bits
connect _WIRE_41.valid, _WIRE_40.valid
connect _WIRE_41.ready, _WIRE_40.ready
invalidate _WIRE_41.bits.sink
invalidate _WIRE_41.valid
invalidate _WIRE_41.ready
wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_42.bits.sink, UInt<1>(0h0)
connect _WIRE_42.valid, UInt<1>(0h0)
connect _WIRE_42.ready, UInt<1>(0h0)
wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_43.bits, _WIRE_42.bits
connect _WIRE_43.valid, _WIRE_42.valid
connect _WIRE_43.ready, _WIRE_42.ready
invalidate _WIRE_43.bits.sink
invalidate _WIRE_43.valid
invalidate _WIRE_43.ready
wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_44.bits.sink, UInt<1>(0h0)
connect _WIRE_44.valid, UInt<1>(0h0)
connect _WIRE_44.ready, UInt<1>(0h0)
wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_45.bits, _WIRE_44.bits
connect _WIRE_45.valid, _WIRE_44.valid
connect _WIRE_45.ready, _WIRE_44.ready
connect _WIRE_45.valid, UInt<1>(0h0)
wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_46.bits.sink, UInt<1>(0h0)
connect _WIRE_46.valid, UInt<1>(0h0)
connect _WIRE_46.ready, UInt<1>(0h0)
wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_47.bits, _WIRE_46.bits
connect _WIRE_47.valid, _WIRE_46.valid
connect _WIRE_47.ready, _WIRE_46.ready
connect _WIRE_47.ready, UInt<1>(0h1)
connect in[2].a.bits.corrupt, anonIn_2.a.bits.corrupt
connect in[2].a.bits.data, anonIn_2.a.bits.data
connect in[2].a.bits.mask, anonIn_2.a.bits.mask
connect in[2].a.bits.address, anonIn_2.a.bits.address
connect in[2].a.bits.source, anonIn_2.a.bits.source
connect in[2].a.bits.size, anonIn_2.a.bits.size
connect in[2].a.bits.param, anonIn_2.a.bits.param
connect in[2].a.bits.opcode, anonIn_2.a.bits.opcode
connect in[2].a.valid, anonIn_2.a.valid
connect anonIn_2.a.ready, in[2].a.ready
node _in_2_a_bits_source_T = or(anonIn_2.a.bits.source, UInt<6>(0h20))
connect in[2].a.bits.source, _in_2_a_bits_source_T
wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_48.bits.corrupt, UInt<1>(0h0)
connect _WIRE_48.bits.data, UInt<64>(0h0)
connect _WIRE_48.bits.mask, UInt<8>(0h0)
connect _WIRE_48.bits.address, UInt<32>(0h0)
connect _WIRE_48.bits.source, UInt<7>(0h0)
connect _WIRE_48.bits.size, UInt<3>(0h0)
connect _WIRE_48.bits.param, UInt<2>(0h0)
connect _WIRE_48.bits.opcode, UInt<3>(0h0)
connect _WIRE_48.valid, UInt<1>(0h0)
connect _WIRE_48.ready, UInt<1>(0h0)
wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_49.bits, _WIRE_48.bits
connect _WIRE_49.valid, _WIRE_48.valid
connect _WIRE_49.ready, _WIRE_48.ready
invalidate _WIRE_49.bits.corrupt
invalidate _WIRE_49.bits.data
invalidate _WIRE_49.bits.mask
invalidate _WIRE_49.bits.address
invalidate _WIRE_49.bits.source
invalidate _WIRE_49.bits.size
invalidate _WIRE_49.bits.param
invalidate _WIRE_49.bits.opcode
invalidate _WIRE_49.valid
invalidate _WIRE_49.ready
wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_50.bits.corrupt, UInt<1>(0h0)
connect _WIRE_50.bits.data, UInt<64>(0h0)
connect _WIRE_50.bits.mask, UInt<8>(0h0)
connect _WIRE_50.bits.address, UInt<32>(0h0)
connect _WIRE_50.bits.source, UInt<5>(0h0)
connect _WIRE_50.bits.size, UInt<3>(0h0)
connect _WIRE_50.bits.param, UInt<2>(0h0)
connect _WIRE_50.bits.opcode, UInt<3>(0h0)
connect _WIRE_50.valid, UInt<1>(0h0)
connect _WIRE_50.ready, UInt<1>(0h0)
wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_51.bits, _WIRE_50.bits
connect _WIRE_51.valid, _WIRE_50.valid
connect _WIRE_51.ready, _WIRE_50.ready
invalidate _WIRE_51.bits.corrupt
invalidate _WIRE_51.bits.data
invalidate _WIRE_51.bits.mask
invalidate _WIRE_51.bits.address
invalidate _WIRE_51.bits.source
invalidate _WIRE_51.bits.size
invalidate _WIRE_51.bits.param
invalidate _WIRE_51.bits.opcode
invalidate _WIRE_51.valid
invalidate _WIRE_51.ready
wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_52.bits.corrupt, UInt<1>(0h0)
connect _WIRE_52.bits.data, UInt<64>(0h0)
connect _WIRE_52.bits.mask, UInt<8>(0h0)
connect _WIRE_52.bits.address, UInt<32>(0h0)
connect _WIRE_52.bits.source, UInt<7>(0h0)
connect _WIRE_52.bits.size, UInt<3>(0h0)
connect _WIRE_52.bits.param, UInt<2>(0h0)
connect _WIRE_52.bits.opcode, UInt<3>(0h0)
connect _WIRE_52.valid, UInt<1>(0h0)
connect _WIRE_52.ready, UInt<1>(0h0)
wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_53.bits, _WIRE_52.bits
connect _WIRE_53.valid, _WIRE_52.valid
connect _WIRE_53.ready, _WIRE_52.ready
connect _WIRE_53.ready, UInt<1>(0h1)
wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_54.bits.corrupt, UInt<1>(0h0)
connect _WIRE_54.bits.data, UInt<64>(0h0)
connect _WIRE_54.bits.mask, UInt<8>(0h0)
connect _WIRE_54.bits.address, UInt<32>(0h0)
connect _WIRE_54.bits.source, UInt<5>(0h0)
connect _WIRE_54.bits.size, UInt<3>(0h0)
connect _WIRE_54.bits.param, UInt<2>(0h0)
connect _WIRE_54.bits.opcode, UInt<3>(0h0)
connect _WIRE_54.valid, UInt<1>(0h0)
connect _WIRE_54.ready, UInt<1>(0h0)
wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_55.bits, _WIRE_54.bits
connect _WIRE_55.valid, _WIRE_54.valid
connect _WIRE_55.ready, _WIRE_54.ready
connect _WIRE_55.valid, UInt<1>(0h0)
wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_56.bits.corrupt, UInt<1>(0h0)
connect _WIRE_56.bits.data, UInt<64>(0h0)
connect _WIRE_56.bits.address, UInt<32>(0h0)
connect _WIRE_56.bits.source, UInt<7>(0h0)
connect _WIRE_56.bits.size, UInt<3>(0h0)
connect _WIRE_56.bits.param, UInt<3>(0h0)
connect _WIRE_56.bits.opcode, UInt<3>(0h0)
connect _WIRE_56.valid, UInt<1>(0h0)
connect _WIRE_56.ready, UInt<1>(0h0)
wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_57.bits, _WIRE_56.bits
connect _WIRE_57.valid, _WIRE_56.valid
connect _WIRE_57.ready, _WIRE_56.ready
invalidate _WIRE_57.bits.corrupt
invalidate _WIRE_57.bits.data
invalidate _WIRE_57.bits.address
invalidate _WIRE_57.bits.source
invalidate _WIRE_57.bits.size
invalidate _WIRE_57.bits.param
invalidate _WIRE_57.bits.opcode
invalidate _WIRE_57.valid
invalidate _WIRE_57.ready
wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_58.bits.corrupt, UInt<1>(0h0)
connect _WIRE_58.bits.data, UInt<64>(0h0)
connect _WIRE_58.bits.address, UInt<32>(0h0)
connect _WIRE_58.bits.source, UInt<5>(0h0)
connect _WIRE_58.bits.size, UInt<3>(0h0)
connect _WIRE_58.bits.param, UInt<3>(0h0)
connect _WIRE_58.bits.opcode, UInt<3>(0h0)
connect _WIRE_58.valid, UInt<1>(0h0)
connect _WIRE_58.ready, UInt<1>(0h0)
wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_59.bits, _WIRE_58.bits
connect _WIRE_59.valid, _WIRE_58.valid
connect _WIRE_59.ready, _WIRE_58.ready
invalidate _WIRE_59.bits.corrupt
invalidate _WIRE_59.bits.data
invalidate _WIRE_59.bits.address
invalidate _WIRE_59.bits.source
invalidate _WIRE_59.bits.size
invalidate _WIRE_59.bits.param
invalidate _WIRE_59.bits.opcode
invalidate _WIRE_59.valid
invalidate _WIRE_59.ready
wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_60.bits.corrupt, UInt<1>(0h0)
connect _WIRE_60.bits.data, UInt<64>(0h0)
connect _WIRE_60.bits.address, UInt<32>(0h0)
connect _WIRE_60.bits.source, UInt<7>(0h0)
connect _WIRE_60.bits.size, UInt<3>(0h0)
connect _WIRE_60.bits.param, UInt<3>(0h0)
connect _WIRE_60.bits.opcode, UInt<3>(0h0)
connect _WIRE_60.valid, UInt<1>(0h0)
connect _WIRE_60.ready, UInt<1>(0h0)
wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_61.bits, _WIRE_60.bits
connect _WIRE_61.valid, _WIRE_60.valid
connect _WIRE_61.ready, _WIRE_60.ready
connect _WIRE_61.valid, UInt<1>(0h0)
wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_62.bits.corrupt, UInt<1>(0h0)
connect _WIRE_62.bits.data, UInt<64>(0h0)
connect _WIRE_62.bits.address, UInt<32>(0h0)
connect _WIRE_62.bits.source, UInt<5>(0h0)
connect _WIRE_62.bits.size, UInt<3>(0h0)
connect _WIRE_62.bits.param, UInt<3>(0h0)
connect _WIRE_62.bits.opcode, UInt<3>(0h0)
connect _WIRE_62.valid, UInt<1>(0h0)
connect _WIRE_62.ready, UInt<1>(0h0)
wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_63.bits, _WIRE_62.bits
connect _WIRE_63.valid, _WIRE_62.valid
connect _WIRE_63.ready, _WIRE_62.ready
connect _WIRE_63.ready, UInt<1>(0h1)
connect anonIn_2.d.bits.corrupt, in[2].d.bits.corrupt
connect anonIn_2.d.bits.data, in[2].d.bits.data
connect anonIn_2.d.bits.denied, in[2].d.bits.denied
connect anonIn_2.d.bits.sink, in[2].d.bits.sink
connect anonIn_2.d.bits.source, in[2].d.bits.source
connect anonIn_2.d.bits.size, in[2].d.bits.size
connect anonIn_2.d.bits.param, in[2].d.bits.param
connect anonIn_2.d.bits.opcode, in[2].d.bits.opcode
connect anonIn_2.d.valid, in[2].d.valid
connect in[2].d.ready, anonIn_2.d.ready
node _anonIn_d_bits_source_T_2 = bits(in[2].d.bits.source, 4, 0)
connect anonIn_2.d.bits.source, _anonIn_d_bits_source_T_2
wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_64.bits.sink, UInt<1>(0h0)
connect _WIRE_64.valid, UInt<1>(0h0)
connect _WIRE_64.ready, UInt<1>(0h0)
wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_65.bits, _WIRE_64.bits
connect _WIRE_65.valid, _WIRE_64.valid
connect _WIRE_65.ready, _WIRE_64.ready
invalidate _WIRE_65.bits.sink
invalidate _WIRE_65.valid
invalidate _WIRE_65.ready
wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_66.bits.sink, UInt<1>(0h0)
connect _WIRE_66.valid, UInt<1>(0h0)
connect _WIRE_66.ready, UInt<1>(0h0)
wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_67.bits, _WIRE_66.bits
connect _WIRE_67.valid, _WIRE_66.valid
connect _WIRE_67.ready, _WIRE_66.ready
invalidate _WIRE_67.bits.sink
invalidate _WIRE_67.valid
invalidate _WIRE_67.ready
wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_68.bits.sink, UInt<1>(0h0)
connect _WIRE_68.valid, UInt<1>(0h0)
connect _WIRE_68.ready, UInt<1>(0h0)
wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_69.bits, _WIRE_68.bits
connect _WIRE_69.valid, _WIRE_68.valid
connect _WIRE_69.ready, _WIRE_68.ready
connect _WIRE_69.valid, UInt<1>(0h0)
wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_70.bits.sink, UInt<1>(0h0)
connect _WIRE_70.valid, UInt<1>(0h0)
connect _WIRE_70.ready, UInt<1>(0h0)
wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_71.bits, _WIRE_70.bits
connect _WIRE_71.valid, _WIRE_70.valid
connect _WIRE_71.ready, _WIRE_70.ready
connect _WIRE_71.ready, UInt<1>(0h1)
connect in[3].a.bits.corrupt, anonIn_3.a.bits.corrupt
connect in[3].a.bits.data, anonIn_3.a.bits.data
connect in[3].a.bits.mask, anonIn_3.a.bits.mask
connect in[3].a.bits.address, anonIn_3.a.bits.address
connect in[3].a.bits.source, anonIn_3.a.bits.source
connect in[3].a.bits.size, anonIn_3.a.bits.size
connect in[3].a.bits.param, anonIn_3.a.bits.param
connect in[3].a.bits.opcode, anonIn_3.a.bits.opcode
connect in[3].a.valid, anonIn_3.a.valid
connect anonIn_3.a.ready, in[3].a.ready
node _in_3_a_bits_source_T = or(anonIn_3.a.bits.source, UInt<1>(0h0))
connect in[3].a.bits.source, _in_3_a_bits_source_T
wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_72.bits.corrupt, UInt<1>(0h0)
connect _WIRE_72.bits.data, UInt<64>(0h0)
connect _WIRE_72.bits.mask, UInt<8>(0h0)
connect _WIRE_72.bits.address, UInt<32>(0h0)
connect _WIRE_72.bits.source, UInt<7>(0h0)
connect _WIRE_72.bits.size, UInt<3>(0h0)
connect _WIRE_72.bits.param, UInt<2>(0h0)
connect _WIRE_72.bits.opcode, UInt<3>(0h0)
connect _WIRE_72.valid, UInt<1>(0h0)
connect _WIRE_72.ready, UInt<1>(0h0)
wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_73.bits, _WIRE_72.bits
connect _WIRE_73.valid, _WIRE_72.valid
connect _WIRE_73.ready, _WIRE_72.ready
invalidate _WIRE_73.bits.corrupt
invalidate _WIRE_73.bits.data
invalidate _WIRE_73.bits.mask
invalidate _WIRE_73.bits.address
invalidate _WIRE_73.bits.source
invalidate _WIRE_73.bits.size
invalidate _WIRE_73.bits.param
invalidate _WIRE_73.bits.opcode
invalidate _WIRE_73.valid
invalidate _WIRE_73.ready
wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_74.bits.corrupt, UInt<1>(0h0)
connect _WIRE_74.bits.data, UInt<64>(0h0)
connect _WIRE_74.bits.mask, UInt<8>(0h0)
connect _WIRE_74.bits.address, UInt<32>(0h0)
connect _WIRE_74.bits.source, UInt<5>(0h0)
connect _WIRE_74.bits.size, UInt<3>(0h0)
connect _WIRE_74.bits.param, UInt<2>(0h0)
connect _WIRE_74.bits.opcode, UInt<3>(0h0)
connect _WIRE_74.valid, UInt<1>(0h0)
connect _WIRE_74.ready, UInt<1>(0h0)
wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_75.bits, _WIRE_74.bits
connect _WIRE_75.valid, _WIRE_74.valid
connect _WIRE_75.ready, _WIRE_74.ready
invalidate _WIRE_75.bits.corrupt
invalidate _WIRE_75.bits.data
invalidate _WIRE_75.bits.mask
invalidate _WIRE_75.bits.address
invalidate _WIRE_75.bits.source
invalidate _WIRE_75.bits.size
invalidate _WIRE_75.bits.param
invalidate _WIRE_75.bits.opcode
invalidate _WIRE_75.valid
invalidate _WIRE_75.ready
wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_76.bits.corrupt, UInt<1>(0h0)
connect _WIRE_76.bits.data, UInt<64>(0h0)
connect _WIRE_76.bits.mask, UInt<8>(0h0)
connect _WIRE_76.bits.address, UInt<32>(0h0)
connect _WIRE_76.bits.source, UInt<7>(0h0)
connect _WIRE_76.bits.size, UInt<3>(0h0)
connect _WIRE_76.bits.param, UInt<2>(0h0)
connect _WIRE_76.bits.opcode, UInt<3>(0h0)
connect _WIRE_76.valid, UInt<1>(0h0)
connect _WIRE_76.ready, UInt<1>(0h0)
wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_77.bits, _WIRE_76.bits
connect _WIRE_77.valid, _WIRE_76.valid
connect _WIRE_77.ready, _WIRE_76.ready
connect _WIRE_77.ready, UInt<1>(0h1)
wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_78.bits.corrupt, UInt<1>(0h0)
connect _WIRE_78.bits.data, UInt<64>(0h0)
connect _WIRE_78.bits.mask, UInt<8>(0h0)
connect _WIRE_78.bits.address, UInt<32>(0h0)
connect _WIRE_78.bits.source, UInt<5>(0h0)
connect _WIRE_78.bits.size, UInt<3>(0h0)
connect _WIRE_78.bits.param, UInt<2>(0h0)
connect _WIRE_78.bits.opcode, UInt<3>(0h0)
connect _WIRE_78.valid, UInt<1>(0h0)
connect _WIRE_78.ready, UInt<1>(0h0)
wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_79.bits, _WIRE_78.bits
connect _WIRE_79.valid, _WIRE_78.valid
connect _WIRE_79.ready, _WIRE_78.ready
connect _WIRE_79.valid, UInt<1>(0h0)
wire _WIRE_80 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_80.bits.corrupt, UInt<1>(0h0)
connect _WIRE_80.bits.data, UInt<64>(0h0)
connect _WIRE_80.bits.address, UInt<32>(0h0)
connect _WIRE_80.bits.source, UInt<7>(0h0)
connect _WIRE_80.bits.size, UInt<3>(0h0)
connect _WIRE_80.bits.param, UInt<3>(0h0)
connect _WIRE_80.bits.opcode, UInt<3>(0h0)
connect _WIRE_80.valid, UInt<1>(0h0)
connect _WIRE_80.ready, UInt<1>(0h0)
wire _WIRE_81 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_81.bits, _WIRE_80.bits
connect _WIRE_81.valid, _WIRE_80.valid
connect _WIRE_81.ready, _WIRE_80.ready
invalidate _WIRE_81.bits.corrupt
invalidate _WIRE_81.bits.data
invalidate _WIRE_81.bits.address
invalidate _WIRE_81.bits.source
invalidate _WIRE_81.bits.size
invalidate _WIRE_81.bits.param
invalidate _WIRE_81.bits.opcode
invalidate _WIRE_81.valid
invalidate _WIRE_81.ready
wire _WIRE_82 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_82.bits.corrupt, UInt<1>(0h0)
connect _WIRE_82.bits.data, UInt<64>(0h0)
connect _WIRE_82.bits.address, UInt<32>(0h0)
connect _WIRE_82.bits.source, UInt<5>(0h0)
connect _WIRE_82.bits.size, UInt<3>(0h0)
connect _WIRE_82.bits.param, UInt<3>(0h0)
connect _WIRE_82.bits.opcode, UInt<3>(0h0)
connect _WIRE_82.valid, UInt<1>(0h0)
connect _WIRE_82.ready, UInt<1>(0h0)
wire _WIRE_83 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_83.bits, _WIRE_82.bits
connect _WIRE_83.valid, _WIRE_82.valid
connect _WIRE_83.ready, _WIRE_82.ready
invalidate _WIRE_83.bits.corrupt
invalidate _WIRE_83.bits.data
invalidate _WIRE_83.bits.address
invalidate _WIRE_83.bits.source
invalidate _WIRE_83.bits.size
invalidate _WIRE_83.bits.param
invalidate _WIRE_83.bits.opcode
invalidate _WIRE_83.valid
invalidate _WIRE_83.ready
wire _WIRE_84 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_84.bits.corrupt, UInt<1>(0h0)
connect _WIRE_84.bits.data, UInt<64>(0h0)
connect _WIRE_84.bits.address, UInt<32>(0h0)
connect _WIRE_84.bits.source, UInt<7>(0h0)
connect _WIRE_84.bits.size, UInt<3>(0h0)
connect _WIRE_84.bits.param, UInt<3>(0h0)
connect _WIRE_84.bits.opcode, UInt<3>(0h0)
connect _WIRE_84.valid, UInt<1>(0h0)
connect _WIRE_84.ready, UInt<1>(0h0)
wire _WIRE_85 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_85.bits, _WIRE_84.bits
connect _WIRE_85.valid, _WIRE_84.valid
connect _WIRE_85.ready, _WIRE_84.ready
connect _WIRE_85.valid, UInt<1>(0h0)
wire _WIRE_86 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_86.bits.corrupt, UInt<1>(0h0)
connect _WIRE_86.bits.data, UInt<64>(0h0)
connect _WIRE_86.bits.address, UInt<32>(0h0)
connect _WIRE_86.bits.source, UInt<5>(0h0)
connect _WIRE_86.bits.size, UInt<3>(0h0)
connect _WIRE_86.bits.param, UInt<3>(0h0)
connect _WIRE_86.bits.opcode, UInt<3>(0h0)
connect _WIRE_86.valid, UInt<1>(0h0)
connect _WIRE_86.ready, UInt<1>(0h0)
wire _WIRE_87 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_87.bits, _WIRE_86.bits
connect _WIRE_87.valid, _WIRE_86.valid
connect _WIRE_87.ready, _WIRE_86.ready
connect _WIRE_87.ready, UInt<1>(0h1)
connect anonIn_3.d.bits.corrupt, in[3].d.bits.corrupt
connect anonIn_3.d.bits.data, in[3].d.bits.data
connect anonIn_3.d.bits.denied, in[3].d.bits.denied
connect anonIn_3.d.bits.sink, in[3].d.bits.sink
connect anonIn_3.d.bits.source, in[3].d.bits.source
connect anonIn_3.d.bits.size, in[3].d.bits.size
connect anonIn_3.d.bits.param, in[3].d.bits.param
connect anonIn_3.d.bits.opcode, in[3].d.bits.opcode
connect anonIn_3.d.valid, in[3].d.valid
connect in[3].d.ready, anonIn_3.d.ready
node _anonIn_d_bits_source_T_3 = bits(in[3].d.bits.source, 4, 0)
connect anonIn_3.d.bits.source, _anonIn_d_bits_source_T_3
wire _WIRE_88 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_88.bits.sink, UInt<1>(0h0)
connect _WIRE_88.valid, UInt<1>(0h0)
connect _WIRE_88.ready, UInt<1>(0h0)
wire _WIRE_89 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_89.bits, _WIRE_88.bits
connect _WIRE_89.valid, _WIRE_88.valid
connect _WIRE_89.ready, _WIRE_88.ready
invalidate _WIRE_89.bits.sink
invalidate _WIRE_89.valid
invalidate _WIRE_89.ready
wire _WIRE_90 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_90.bits.sink, UInt<1>(0h0)
connect _WIRE_90.valid, UInt<1>(0h0)
connect _WIRE_90.ready, UInt<1>(0h0)
wire _WIRE_91 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_91.bits, _WIRE_90.bits
connect _WIRE_91.valid, _WIRE_90.valid
connect _WIRE_91.ready, _WIRE_90.ready
invalidate _WIRE_91.bits.sink
invalidate _WIRE_91.valid
invalidate _WIRE_91.ready
wire _WIRE_92 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_92.bits.sink, UInt<1>(0h0)
connect _WIRE_92.valid, UInt<1>(0h0)
connect _WIRE_92.ready, UInt<1>(0h0)
wire _WIRE_93 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_93.bits, _WIRE_92.bits
connect _WIRE_93.valid, _WIRE_92.valid
connect _WIRE_93.ready, _WIRE_92.ready
connect _WIRE_93.valid, UInt<1>(0h0)
wire _WIRE_94 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_94.bits.sink, UInt<1>(0h0)
connect _WIRE_94.valid, UInt<1>(0h0)
connect _WIRE_94.ready, UInt<1>(0h0)
wire _WIRE_95 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_95.bits, _WIRE_94.bits
connect _WIRE_95.valid, _WIRE_94.valid
connect _WIRE_95.ready, _WIRE_94.ready
connect _WIRE_95.ready, UInt<1>(0h1)
wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}[2]
connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt
connect anonOut.a.bits.data, out[0].a.bits.data
connect anonOut.a.bits.mask, out[0].a.bits.mask
connect anonOut.a.bits.address, out[0].a.bits.address
connect anonOut.a.bits.source, out[0].a.bits.source
connect anonOut.a.bits.size, out[0].a.bits.size
connect anonOut.a.bits.param, out[0].a.bits.param
connect anonOut.a.bits.opcode, out[0].a.bits.opcode
connect anonOut.a.valid, out[0].a.valid
connect out[0].a.ready, anonOut.a.ready
wire _WIRE_96 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_96.bits.corrupt, UInt<1>(0h0)
connect _WIRE_96.bits.data, UInt<64>(0h0)
connect _WIRE_96.bits.mask, UInt<8>(0h0)
connect _WIRE_96.bits.address, UInt<32>(0h0)
connect _WIRE_96.bits.source, UInt<7>(0h0)
connect _WIRE_96.bits.size, UInt<3>(0h0)
connect _WIRE_96.bits.param, UInt<2>(0h0)
connect _WIRE_96.bits.opcode, UInt<3>(0h0)
connect _WIRE_96.valid, UInt<1>(0h0)
connect _WIRE_96.ready, UInt<1>(0h0)
wire _WIRE_97 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_97.bits, _WIRE_96.bits
connect _WIRE_97.valid, _WIRE_96.valid
connect _WIRE_97.ready, _WIRE_96.ready
invalidate _WIRE_97.bits.corrupt
invalidate _WIRE_97.bits.data
invalidate _WIRE_97.bits.mask
invalidate _WIRE_97.bits.address
invalidate _WIRE_97.bits.source
invalidate _WIRE_97.bits.size
invalidate _WIRE_97.bits.param
invalidate _WIRE_97.bits.opcode
invalidate _WIRE_97.valid
invalidate _WIRE_97.ready
wire _WIRE_98 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_98.bits.corrupt, UInt<1>(0h0)
connect _WIRE_98.bits.data, UInt<64>(0h0)
connect _WIRE_98.bits.mask, UInt<8>(0h0)
connect _WIRE_98.bits.address, UInt<32>(0h0)
connect _WIRE_98.bits.source, UInt<7>(0h0)
connect _WIRE_98.bits.size, UInt<3>(0h0)
connect _WIRE_98.bits.param, UInt<2>(0h0)
connect _WIRE_98.bits.opcode, UInt<3>(0h0)
connect _WIRE_98.valid, UInt<1>(0h0)
connect _WIRE_98.ready, UInt<1>(0h0)
wire _WIRE_99 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_99.bits, _WIRE_98.bits
connect _WIRE_99.valid, _WIRE_98.valid
connect _WIRE_99.ready, _WIRE_98.ready
invalidate _WIRE_99.bits.corrupt
invalidate _WIRE_99.bits.data
invalidate _WIRE_99.bits.mask
invalidate _WIRE_99.bits.address
invalidate _WIRE_99.bits.source
invalidate _WIRE_99.bits.size
invalidate _WIRE_99.bits.param
invalidate _WIRE_99.bits.opcode
invalidate _WIRE_99.valid
invalidate _WIRE_99.ready
wire _WIRE_100 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_100.bits.corrupt, UInt<1>(0h0)
connect _WIRE_100.bits.data, UInt<64>(0h0)
connect _WIRE_100.bits.mask, UInt<8>(0h0)
connect _WIRE_100.bits.address, UInt<32>(0h0)
connect _WIRE_100.bits.source, UInt<7>(0h0)
connect _WIRE_100.bits.size, UInt<3>(0h0)
connect _WIRE_100.bits.param, UInt<2>(0h0)
connect _WIRE_100.bits.opcode, UInt<3>(0h0)
connect _WIRE_100.valid, UInt<1>(0h0)
connect _WIRE_100.ready, UInt<1>(0h0)
wire _WIRE_101 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_101.bits, _WIRE_100.bits
connect _WIRE_101.valid, _WIRE_100.valid
connect _WIRE_101.ready, _WIRE_100.ready
connect _WIRE_101.valid, UInt<1>(0h0)
wire _WIRE_102 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_102.bits.corrupt, UInt<1>(0h0)
connect _WIRE_102.bits.data, UInt<64>(0h0)
connect _WIRE_102.bits.mask, UInt<8>(0h0)
connect _WIRE_102.bits.address, UInt<32>(0h0)
connect _WIRE_102.bits.source, UInt<7>(0h0)
connect _WIRE_102.bits.size, UInt<3>(0h0)
connect _WIRE_102.bits.param, UInt<2>(0h0)
connect _WIRE_102.bits.opcode, UInt<3>(0h0)
connect _WIRE_102.valid, UInt<1>(0h0)
connect _WIRE_102.ready, UInt<1>(0h0)
wire _WIRE_103 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_103.bits, _WIRE_102.bits
connect _WIRE_103.valid, _WIRE_102.valid
connect _WIRE_103.ready, _WIRE_102.ready
connect _WIRE_103.ready, UInt<1>(0h1)
wire _WIRE_104 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_104.bits.corrupt, UInt<1>(0h0)
connect _WIRE_104.bits.data, UInt<64>(0h0)
connect _WIRE_104.bits.address, UInt<32>(0h0)
connect _WIRE_104.bits.source, UInt<7>(0h0)
connect _WIRE_104.bits.size, UInt<3>(0h0)
connect _WIRE_104.bits.param, UInt<3>(0h0)
connect _WIRE_104.bits.opcode, UInt<3>(0h0)
connect _WIRE_104.valid, UInt<1>(0h0)
connect _WIRE_104.ready, UInt<1>(0h0)
wire _WIRE_105 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_105.bits, _WIRE_104.bits
connect _WIRE_105.valid, _WIRE_104.valid
connect _WIRE_105.ready, _WIRE_104.ready
invalidate _WIRE_105.bits.corrupt
invalidate _WIRE_105.bits.data
invalidate _WIRE_105.bits.address
invalidate _WIRE_105.bits.source
invalidate _WIRE_105.bits.size
invalidate _WIRE_105.bits.param
invalidate _WIRE_105.bits.opcode
invalidate _WIRE_105.valid
invalidate _WIRE_105.ready
wire _WIRE_106 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_106.bits.corrupt, UInt<1>(0h0)
connect _WIRE_106.bits.data, UInt<64>(0h0)
connect _WIRE_106.bits.address, UInt<32>(0h0)
connect _WIRE_106.bits.source, UInt<7>(0h0)
connect _WIRE_106.bits.size, UInt<3>(0h0)
connect _WIRE_106.bits.param, UInt<3>(0h0)
connect _WIRE_106.bits.opcode, UInt<3>(0h0)
connect _WIRE_106.valid, UInt<1>(0h0)
connect _WIRE_106.ready, UInt<1>(0h0)
wire _WIRE_107 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_107.bits, _WIRE_106.bits
connect _WIRE_107.valid, _WIRE_106.valid
connect _WIRE_107.ready, _WIRE_106.ready
invalidate _WIRE_107.bits.corrupt
invalidate _WIRE_107.bits.data
invalidate _WIRE_107.bits.address
invalidate _WIRE_107.bits.source
invalidate _WIRE_107.bits.size
invalidate _WIRE_107.bits.param
invalidate _WIRE_107.bits.opcode
invalidate _WIRE_107.valid
invalidate _WIRE_107.ready
wire _WIRE_108 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_108.bits.corrupt, UInt<1>(0h0)
connect _WIRE_108.bits.data, UInt<64>(0h0)
connect _WIRE_108.bits.address, UInt<32>(0h0)
connect _WIRE_108.bits.source, UInt<7>(0h0)
connect _WIRE_108.bits.size, UInt<3>(0h0)
connect _WIRE_108.bits.param, UInt<3>(0h0)
connect _WIRE_108.bits.opcode, UInt<3>(0h0)
connect _WIRE_108.valid, UInt<1>(0h0)
connect _WIRE_108.ready, UInt<1>(0h0)
wire _WIRE_109 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_109.bits, _WIRE_108.bits
connect _WIRE_109.valid, _WIRE_108.valid
connect _WIRE_109.ready, _WIRE_108.ready
connect _WIRE_109.ready, UInt<1>(0h1)
wire _WIRE_110 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_110.bits.corrupt, UInt<1>(0h0)
connect _WIRE_110.bits.data, UInt<64>(0h0)
connect _WIRE_110.bits.address, UInt<32>(0h0)
connect _WIRE_110.bits.source, UInt<7>(0h0)
connect _WIRE_110.bits.size, UInt<3>(0h0)
connect _WIRE_110.bits.param, UInt<3>(0h0)
connect _WIRE_110.bits.opcode, UInt<3>(0h0)
connect _WIRE_110.valid, UInt<1>(0h0)
connect _WIRE_110.ready, UInt<1>(0h0)
wire _WIRE_111 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_111.bits, _WIRE_110.bits
connect _WIRE_111.valid, _WIRE_110.valid
connect _WIRE_111.ready, _WIRE_110.ready
connect _WIRE_111.valid, UInt<1>(0h0)
connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt
connect out[0].d.bits.data, anonOut.d.bits.data
connect out[0].d.bits.denied, anonOut.d.bits.denied
connect out[0].d.bits.sink, anonOut.d.bits.sink
connect out[0].d.bits.source, anonOut.d.bits.source
connect out[0].d.bits.size, anonOut.d.bits.size
connect out[0].d.bits.param, anonOut.d.bits.param
connect out[0].d.bits.opcode, anonOut.d.bits.opcode
connect out[0].d.valid, anonOut.d.valid
connect anonOut.d.ready, out[0].d.ready
node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0))
connect out[0].d.bits.sink, _out_0_d_bits_sink_T
wire _WIRE_112 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_112.bits.sink, UInt<1>(0h0)
connect _WIRE_112.valid, UInt<1>(0h0)
connect _WIRE_112.ready, UInt<1>(0h0)
wire _WIRE_113 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_113.bits, _WIRE_112.bits
connect _WIRE_113.valid, _WIRE_112.valid
connect _WIRE_113.ready, _WIRE_112.ready
invalidate _WIRE_113.bits.sink
invalidate _WIRE_113.valid
invalidate _WIRE_113.ready
wire _WIRE_114 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_114.bits.sink, UInt<1>(0h0)
connect _WIRE_114.valid, UInt<1>(0h0)
connect _WIRE_114.ready, UInt<1>(0h0)
wire _WIRE_115 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_115.bits, _WIRE_114.bits
connect _WIRE_115.valid, _WIRE_114.valid
connect _WIRE_115.ready, _WIRE_114.ready
invalidate _WIRE_115.bits.sink
invalidate _WIRE_115.valid
invalidate _WIRE_115.ready
wire _WIRE_116 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_116.bits.sink, UInt<1>(0h0)
connect _WIRE_116.valid, UInt<1>(0h0)
connect _WIRE_116.ready, UInt<1>(0h0)
wire _WIRE_117 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_117.bits, _WIRE_116.bits
connect _WIRE_117.valid, _WIRE_116.valid
connect _WIRE_117.ready, _WIRE_116.ready
connect _WIRE_117.ready, UInt<1>(0h1)
wire _WIRE_118 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_118.bits.sink, UInt<1>(0h0)
connect _WIRE_118.valid, UInt<1>(0h0)
connect _WIRE_118.ready, UInt<1>(0h0)
wire _WIRE_119 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_119.bits, _WIRE_118.bits
connect _WIRE_119.valid, _WIRE_118.valid
connect _WIRE_119.ready, _WIRE_118.ready
connect _WIRE_119.valid, UInt<1>(0h0)
connect x1_anonOut.a.bits.corrupt, out[1].a.bits.corrupt
connect x1_anonOut.a.bits.data, out[1].a.bits.data
connect x1_anonOut.a.bits.mask, out[1].a.bits.mask
connect x1_anonOut.a.bits.address, out[1].a.bits.address
connect x1_anonOut.a.bits.source, out[1].a.bits.source
connect x1_anonOut.a.bits.size, out[1].a.bits.size
connect x1_anonOut.a.bits.param, out[1].a.bits.param
connect x1_anonOut.a.bits.opcode, out[1].a.bits.opcode
connect x1_anonOut.a.valid, out[1].a.valid
connect out[1].a.ready, x1_anonOut.a.ready
wire _WIRE_120 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_120.bits.corrupt, UInt<1>(0h0)
connect _WIRE_120.bits.data, UInt<64>(0h0)
connect _WIRE_120.bits.mask, UInt<8>(0h0)
connect _WIRE_120.bits.address, UInt<32>(0h0)
connect _WIRE_120.bits.source, UInt<7>(0h0)
connect _WIRE_120.bits.size, UInt<3>(0h0)
connect _WIRE_120.bits.param, UInt<2>(0h0)
connect _WIRE_120.bits.opcode, UInt<3>(0h0)
connect _WIRE_120.valid, UInt<1>(0h0)
connect _WIRE_120.ready, UInt<1>(0h0)
wire _WIRE_121 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_121.bits, _WIRE_120.bits
connect _WIRE_121.valid, _WIRE_120.valid
connect _WIRE_121.ready, _WIRE_120.ready
invalidate _WIRE_121.bits.corrupt
invalidate _WIRE_121.bits.data
invalidate _WIRE_121.bits.mask
invalidate _WIRE_121.bits.address
invalidate _WIRE_121.bits.source
invalidate _WIRE_121.bits.size
invalidate _WIRE_121.bits.param
invalidate _WIRE_121.bits.opcode
invalidate _WIRE_121.valid
invalidate _WIRE_121.ready
wire _WIRE_122 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_122.bits.corrupt, UInt<1>(0h0)
connect _WIRE_122.bits.data, UInt<64>(0h0)
connect _WIRE_122.bits.mask, UInt<8>(0h0)
connect _WIRE_122.bits.address, UInt<28>(0h0)
connect _WIRE_122.bits.source, UInt<7>(0h0)
connect _WIRE_122.bits.size, UInt<3>(0h0)
connect _WIRE_122.bits.param, UInt<2>(0h0)
connect _WIRE_122.bits.opcode, UInt<3>(0h0)
connect _WIRE_122.valid, UInt<1>(0h0)
connect _WIRE_122.ready, UInt<1>(0h0)
wire _WIRE_123 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_123.bits, _WIRE_122.bits
connect _WIRE_123.valid, _WIRE_122.valid
connect _WIRE_123.ready, _WIRE_122.ready
invalidate _WIRE_123.bits.corrupt
invalidate _WIRE_123.bits.data
invalidate _WIRE_123.bits.mask
invalidate _WIRE_123.bits.address
invalidate _WIRE_123.bits.source
invalidate _WIRE_123.bits.size
invalidate _WIRE_123.bits.param
invalidate _WIRE_123.bits.opcode
invalidate _WIRE_123.valid
invalidate _WIRE_123.ready
wire _WIRE_124 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_124.bits.corrupt, UInt<1>(0h0)
connect _WIRE_124.bits.data, UInt<64>(0h0)
connect _WIRE_124.bits.mask, UInt<8>(0h0)
connect _WIRE_124.bits.address, UInt<32>(0h0)
connect _WIRE_124.bits.source, UInt<7>(0h0)
connect _WIRE_124.bits.size, UInt<3>(0h0)
connect _WIRE_124.bits.param, UInt<2>(0h0)
connect _WIRE_124.bits.opcode, UInt<3>(0h0)
connect _WIRE_124.valid, UInt<1>(0h0)
connect _WIRE_124.ready, UInt<1>(0h0)
wire _WIRE_125 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_125.bits, _WIRE_124.bits
connect _WIRE_125.valid, _WIRE_124.valid
connect _WIRE_125.ready, _WIRE_124.ready
connect _WIRE_125.valid, UInt<1>(0h0)
wire _WIRE_126 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_126.bits.corrupt, UInt<1>(0h0)
connect _WIRE_126.bits.data, UInt<64>(0h0)
connect _WIRE_126.bits.mask, UInt<8>(0h0)
connect _WIRE_126.bits.address, UInt<28>(0h0)
connect _WIRE_126.bits.source, UInt<7>(0h0)
connect _WIRE_126.bits.size, UInt<3>(0h0)
connect _WIRE_126.bits.param, UInt<2>(0h0)
connect _WIRE_126.bits.opcode, UInt<3>(0h0)
connect _WIRE_126.valid, UInt<1>(0h0)
connect _WIRE_126.ready, UInt<1>(0h0)
wire _WIRE_127 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_127.bits, _WIRE_126.bits
connect _WIRE_127.valid, _WIRE_126.valid
connect _WIRE_127.ready, _WIRE_126.ready
connect _WIRE_127.ready, UInt<1>(0h1)
wire _WIRE_128 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_128.bits.corrupt, UInt<1>(0h0)
connect _WIRE_128.bits.data, UInt<64>(0h0)
connect _WIRE_128.bits.address, UInt<32>(0h0)
connect _WIRE_128.bits.source, UInt<7>(0h0)
connect _WIRE_128.bits.size, UInt<3>(0h0)
connect _WIRE_128.bits.param, UInt<3>(0h0)
connect _WIRE_128.bits.opcode, UInt<3>(0h0)
connect _WIRE_128.valid, UInt<1>(0h0)
connect _WIRE_128.ready, UInt<1>(0h0)
wire _WIRE_129 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_129.bits, _WIRE_128.bits
connect _WIRE_129.valid, _WIRE_128.valid
connect _WIRE_129.ready, _WIRE_128.ready
invalidate _WIRE_129.bits.corrupt
invalidate _WIRE_129.bits.data
invalidate _WIRE_129.bits.address
invalidate _WIRE_129.bits.source
invalidate _WIRE_129.bits.size
invalidate _WIRE_129.bits.param
invalidate _WIRE_129.bits.opcode
invalidate _WIRE_129.valid
invalidate _WIRE_129.ready
wire _WIRE_130 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_130.bits.corrupt, UInt<1>(0h0)
connect _WIRE_130.bits.data, UInt<64>(0h0)
connect _WIRE_130.bits.address, UInt<28>(0h0)
connect _WIRE_130.bits.source, UInt<7>(0h0)
connect _WIRE_130.bits.size, UInt<3>(0h0)
connect _WIRE_130.bits.param, UInt<3>(0h0)
connect _WIRE_130.bits.opcode, UInt<3>(0h0)
connect _WIRE_130.valid, UInt<1>(0h0)
connect _WIRE_130.ready, UInt<1>(0h0)
wire _WIRE_131 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_131.bits, _WIRE_130.bits
connect _WIRE_131.valid, _WIRE_130.valid
connect _WIRE_131.ready, _WIRE_130.ready
invalidate _WIRE_131.bits.corrupt
invalidate _WIRE_131.bits.data
invalidate _WIRE_131.bits.address
invalidate _WIRE_131.bits.source
invalidate _WIRE_131.bits.size
invalidate _WIRE_131.bits.param
invalidate _WIRE_131.bits.opcode
invalidate _WIRE_131.valid
invalidate _WIRE_131.ready
wire _WIRE_132 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_132.bits.corrupt, UInt<1>(0h0)
connect _WIRE_132.bits.data, UInt<64>(0h0)
connect _WIRE_132.bits.address, UInt<32>(0h0)
connect _WIRE_132.bits.source, UInt<7>(0h0)
connect _WIRE_132.bits.size, UInt<3>(0h0)
connect _WIRE_132.bits.param, UInt<3>(0h0)
connect _WIRE_132.bits.opcode, UInt<3>(0h0)
connect _WIRE_132.valid, UInt<1>(0h0)
connect _WIRE_132.ready, UInt<1>(0h0)
wire _WIRE_133 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_133.bits, _WIRE_132.bits
connect _WIRE_133.valid, _WIRE_132.valid
connect _WIRE_133.ready, _WIRE_132.ready
connect _WIRE_133.ready, UInt<1>(0h1)
wire _WIRE_134 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_134.bits.corrupt, UInt<1>(0h0)
connect _WIRE_134.bits.data, UInt<64>(0h0)
connect _WIRE_134.bits.address, UInt<28>(0h0)
connect _WIRE_134.bits.source, UInt<7>(0h0)
connect _WIRE_134.bits.size, UInt<3>(0h0)
connect _WIRE_134.bits.param, UInt<3>(0h0)
connect _WIRE_134.bits.opcode, UInt<3>(0h0)
connect _WIRE_134.valid, UInt<1>(0h0)
connect _WIRE_134.ready, UInt<1>(0h0)
wire _WIRE_135 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_135.bits, _WIRE_134.bits
connect _WIRE_135.valid, _WIRE_134.valid
connect _WIRE_135.ready, _WIRE_134.ready
connect _WIRE_135.valid, UInt<1>(0h0)
connect out[1].d.bits.corrupt, x1_anonOut.d.bits.corrupt
connect out[1].d.bits.data, x1_anonOut.d.bits.data
connect out[1].d.bits.denied, x1_anonOut.d.bits.denied
connect out[1].d.bits.sink, x1_anonOut.d.bits.sink
connect out[1].d.bits.source, x1_anonOut.d.bits.source
connect out[1].d.bits.size, x1_anonOut.d.bits.size
connect out[1].d.bits.param, x1_anonOut.d.bits.param
connect out[1].d.bits.opcode, x1_anonOut.d.bits.opcode
connect out[1].d.valid, x1_anonOut.d.valid
connect x1_anonOut.d.ready, out[1].d.ready
node _out_1_d_bits_sink_T = or(x1_anonOut.d.bits.sink, UInt<1>(0h0))
connect out[1].d.bits.sink, _out_1_d_bits_sink_T
wire _WIRE_136 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_136.bits.sink, UInt<1>(0h0)
connect _WIRE_136.valid, UInt<1>(0h0)
connect _WIRE_136.ready, UInt<1>(0h0)
wire _WIRE_137 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_137.bits, _WIRE_136.bits
connect _WIRE_137.valid, _WIRE_136.valid
connect _WIRE_137.ready, _WIRE_136.ready
invalidate _WIRE_137.bits.sink
invalidate _WIRE_137.valid
invalidate _WIRE_137.ready
wire _WIRE_138 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_138.bits.sink, UInt<1>(0h0)
connect _WIRE_138.valid, UInt<1>(0h0)
connect _WIRE_138.ready, UInt<1>(0h0)
wire _WIRE_139 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_139.bits, _WIRE_138.bits
connect _WIRE_139.valid, _WIRE_138.valid
connect _WIRE_139.ready, _WIRE_138.ready
invalidate _WIRE_139.bits.sink
invalidate _WIRE_139.valid
invalidate _WIRE_139.ready
wire _WIRE_140 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_140.bits.sink, UInt<1>(0h0)
connect _WIRE_140.valid, UInt<1>(0h0)
connect _WIRE_140.ready, UInt<1>(0h0)
wire _WIRE_141 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_141.bits, _WIRE_140.bits
connect _WIRE_141.valid, _WIRE_140.valid
connect _WIRE_141.ready, _WIRE_140.ready
connect _WIRE_141.ready, UInt<1>(0h1)
wire _WIRE_142 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_142.bits.sink, UInt<1>(0h0)
connect _WIRE_142.valid, UInt<1>(0h0)
connect _WIRE_142.ready, UInt<1>(0h0)
wire _WIRE_143 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_143.bits, _WIRE_142.bits
connect _WIRE_143.valid, _WIRE_142.valid
connect _WIRE_143.ready, _WIRE_142.ready
connect _WIRE_143.valid, UInt<1>(0h0)
wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0)
connect _addressC_WIRE.bits.data, UInt<64>(0h0)
connect _addressC_WIRE.bits.address, UInt<32>(0h0)
connect _addressC_WIRE.bits.source, UInt<7>(0h0)
connect _addressC_WIRE.bits.size, UInt<3>(0h0)
connect _addressC_WIRE.bits.param, UInt<3>(0h0)
connect _addressC_WIRE.bits.opcode, UInt<3>(0h0)
connect _addressC_WIRE.valid, UInt<1>(0h0)
connect _addressC_WIRE.ready, UInt<1>(0h0)
wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE_1.bits, _addressC_WIRE.bits
connect _addressC_WIRE_1.valid, _addressC_WIRE.valid
connect _addressC_WIRE_1.ready, _addressC_WIRE.ready
wire _addressC_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _addressC_WIRE_2.bits.data, UInt<64>(0h0)
connect _addressC_WIRE_2.bits.address, UInt<32>(0h0)
connect _addressC_WIRE_2.bits.source, UInt<7>(0h0)
connect _addressC_WIRE_2.bits.size, UInt<3>(0h0)
connect _addressC_WIRE_2.bits.param, UInt<3>(0h0)
connect _addressC_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _addressC_WIRE_2.valid, UInt<1>(0h0)
connect _addressC_WIRE_2.ready, UInt<1>(0h0)
wire _addressC_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE_3.bits, _addressC_WIRE_2.bits
connect _addressC_WIRE_3.valid, _addressC_WIRE_2.valid
connect _addressC_WIRE_3.ready, _addressC_WIRE_2.ready
wire _addressC_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _addressC_WIRE_4.bits.data, UInt<64>(0h0)
connect _addressC_WIRE_4.bits.address, UInt<32>(0h0)
connect _addressC_WIRE_4.bits.source, UInt<7>(0h0)
connect _addressC_WIRE_4.bits.size, UInt<3>(0h0)
connect _addressC_WIRE_4.bits.param, UInt<3>(0h0)
connect _addressC_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _addressC_WIRE_4.valid, UInt<1>(0h0)
connect _addressC_WIRE_4.ready, UInt<1>(0h0)
wire _addressC_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE_5.bits, _addressC_WIRE_4.bits
connect _addressC_WIRE_5.valid, _addressC_WIRE_4.valid
connect _addressC_WIRE_5.ready, _addressC_WIRE_4.ready
wire _addressC_WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _addressC_WIRE_6.bits.data, UInt<64>(0h0)
connect _addressC_WIRE_6.bits.address, UInt<32>(0h0)
connect _addressC_WIRE_6.bits.source, UInt<7>(0h0)
connect _addressC_WIRE_6.bits.size, UInt<3>(0h0)
connect _addressC_WIRE_6.bits.param, UInt<3>(0h0)
connect _addressC_WIRE_6.bits.opcode, UInt<3>(0h0)
connect _addressC_WIRE_6.valid, UInt<1>(0h0)
connect _addressC_WIRE_6.ready, UInt<1>(0h0)
wire _addressC_WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _addressC_WIRE_7.bits, _addressC_WIRE_6.bits
connect _addressC_WIRE_7.valid, _addressC_WIRE_6.valid
connect _addressC_WIRE_7.ready, _addressC_WIRE_6.ready
node _requestAIO_T = xor(in[0].a.bits.address, UInt<32>(0h80000000))
node _requestAIO_T_1 = cvt(_requestAIO_T)
node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_3 = asSInt(_requestAIO_T_2)
node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0)))
node requestAIO_0_0 = or(UInt<1>(0h0), _requestAIO_T_4)
node _requestAIO_T_5 = xor(in[0].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_6 = cvt(_requestAIO_T_5)
node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_8 = asSInt(_requestAIO_T_7)
node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0)))
node requestAIO_0_1 = or(UInt<1>(0h0), _requestAIO_T_9)
node _requestAIO_T_10 = xor(in[1].a.bits.address, UInt<32>(0h80000000))
node _requestAIO_T_11 = cvt(_requestAIO_T_10)
node _requestAIO_T_12 = and(_requestAIO_T_11, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_13 = asSInt(_requestAIO_T_12)
node _requestAIO_T_14 = eq(_requestAIO_T_13, asSInt(UInt<1>(0h0)))
node requestAIO_1_0 = or(UInt<1>(0h0), _requestAIO_T_14)
node _requestAIO_T_15 = xor(in[1].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_16 = cvt(_requestAIO_T_15)
node _requestAIO_T_17 = and(_requestAIO_T_16, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_18 = asSInt(_requestAIO_T_17)
node _requestAIO_T_19 = eq(_requestAIO_T_18, asSInt(UInt<1>(0h0)))
node requestAIO_1_1 = or(UInt<1>(0h0), _requestAIO_T_19)
node _requestAIO_T_20 = xor(in[2].a.bits.address, UInt<32>(0h80000000))
node _requestAIO_T_21 = cvt(_requestAIO_T_20)
node _requestAIO_T_22 = and(_requestAIO_T_21, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_23 = asSInt(_requestAIO_T_22)
node _requestAIO_T_24 = eq(_requestAIO_T_23, asSInt(UInt<1>(0h0)))
node requestAIO_2_0 = or(UInt<1>(0h0), _requestAIO_T_24)
node _requestAIO_T_25 = xor(in[2].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_26 = cvt(_requestAIO_T_25)
node _requestAIO_T_27 = and(_requestAIO_T_26, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_28 = asSInt(_requestAIO_T_27)
node _requestAIO_T_29 = eq(_requestAIO_T_28, asSInt(UInt<1>(0h0)))
node requestAIO_2_1 = or(UInt<1>(0h0), _requestAIO_T_29)
node _requestAIO_T_30 = xor(in[3].a.bits.address, UInt<32>(0h80000000))
node _requestAIO_T_31 = cvt(_requestAIO_T_30)
node _requestAIO_T_32 = and(_requestAIO_T_31, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_33 = asSInt(_requestAIO_T_32)
node _requestAIO_T_34 = eq(_requestAIO_T_33, asSInt(UInt<1>(0h0)))
node requestAIO_3_0 = or(UInt<1>(0h0), _requestAIO_T_34)
node _requestAIO_T_35 = xor(in[3].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_36 = cvt(_requestAIO_T_35)
node _requestAIO_T_37 = and(_requestAIO_T_36, asSInt(UInt<33>(0h80000000)))
node _requestAIO_T_38 = asSInt(_requestAIO_T_37)
node _requestAIO_T_39 = eq(_requestAIO_T_38, asSInt(UInt<1>(0h0)))
node requestAIO_3_1 = or(UInt<1>(0h0), _requestAIO_T_39)
node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0))
node _requestCIO_T_1 = cvt(_requestCIO_T)
node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0)))
node _requestCIO_T_3 = asSInt(_requestCIO_T_2)
node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0)))
node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4)
node _requestCIO_T_5 = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0))
node _requestCIO_T_6 = cvt(_requestCIO_T_5)
node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0)))
node _requestCIO_T_8 = asSInt(_requestCIO_T_7)
node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0)))
node requestCIO_0_1 = or(UInt<1>(0h1), _requestCIO_T_9)
node _requestCIO_T_10 = xor(_addressC_WIRE_3.bits.address, UInt<1>(0h0))
node _requestCIO_T_11 = cvt(_requestCIO_T_10)
node _requestCIO_T_12 = and(_requestCIO_T_11, asSInt(UInt<1>(0h0)))
node _requestCIO_T_13 = asSInt(_requestCIO_T_12)
node _requestCIO_T_14 = eq(_requestCIO_T_13, asSInt(UInt<1>(0h0)))
node requestCIO_1_0 = or(UInt<1>(0h1), _requestCIO_T_14)
node _requestCIO_T_15 = xor(_addressC_WIRE_3.bits.address, UInt<1>(0h0))
node _requestCIO_T_16 = cvt(_requestCIO_T_15)
node _requestCIO_T_17 = and(_requestCIO_T_16, asSInt(UInt<1>(0h0)))
node _requestCIO_T_18 = asSInt(_requestCIO_T_17)
node _requestCIO_T_19 = eq(_requestCIO_T_18, asSInt(UInt<1>(0h0)))
node requestCIO_1_1 = or(UInt<1>(0h1), _requestCIO_T_19)
node _requestCIO_T_20 = xor(_addressC_WIRE_5.bits.address, UInt<1>(0h0))
node _requestCIO_T_21 = cvt(_requestCIO_T_20)
node _requestCIO_T_22 = and(_requestCIO_T_21, asSInt(UInt<1>(0h0)))
node _requestCIO_T_23 = asSInt(_requestCIO_T_22)
node _requestCIO_T_24 = eq(_requestCIO_T_23, asSInt(UInt<1>(0h0)))
node requestCIO_2_0 = or(UInt<1>(0h1), _requestCIO_T_24)
node _requestCIO_T_25 = xor(_addressC_WIRE_5.bits.address, UInt<1>(0h0))
node _requestCIO_T_26 = cvt(_requestCIO_T_25)
node _requestCIO_T_27 = and(_requestCIO_T_26, asSInt(UInt<1>(0h0)))
node _requestCIO_T_28 = asSInt(_requestCIO_T_27)
node _requestCIO_T_29 = eq(_requestCIO_T_28, asSInt(UInt<1>(0h0)))
node requestCIO_2_1 = or(UInt<1>(0h1), _requestCIO_T_29)
node _requestCIO_T_30 = xor(_addressC_WIRE_7.bits.address, UInt<1>(0h0))
node _requestCIO_T_31 = cvt(_requestCIO_T_30)
node _requestCIO_T_32 = and(_requestCIO_T_31, asSInt(UInt<1>(0h0)))
node _requestCIO_T_33 = asSInt(_requestCIO_T_32)
node _requestCIO_T_34 = eq(_requestCIO_T_33, asSInt(UInt<1>(0h0)))
node requestCIO_3_0 = or(UInt<1>(0h1), _requestCIO_T_34)
node _requestCIO_T_35 = xor(_addressC_WIRE_7.bits.address, UInt<1>(0h0))
node _requestCIO_T_36 = cvt(_requestCIO_T_35)
node _requestCIO_T_37 = and(_requestCIO_T_36, asSInt(UInt<1>(0h0)))
node _requestCIO_T_38 = asSInt(_requestCIO_T_37)
node _requestCIO_T_39 = eq(_requestCIO_T_38, asSInt(UInt<1>(0h0)))
node requestCIO_3_1 = or(UInt<1>(0h1), _requestCIO_T_39)
wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE.bits.address, UInt<32>(0h0)
connect _requestBOI_WIRE.bits.source, UInt<7>(0h0)
connect _requestBOI_WIRE.bits.size, UInt<3>(0h0)
connect _requestBOI_WIRE.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE.valid, UInt<1>(0h0)
connect _requestBOI_WIRE.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits
connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid
connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready
node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_1.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 4, 0)
node _requestBOI_T = shr(_requestBOI_WIRE_1.bits.source, 5)
node _requestBOI_T_1 = eq(_requestBOI_T, UInt<2>(0h3))
node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits)
node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2)
node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<5>(0h1f))
node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4)
wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE_2.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE_2.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE_2.bits.address, UInt<32>(0h0)
connect _requestBOI_WIRE_2.bits.source, UInt<7>(0h0)
connect _requestBOI_WIRE_2.bits.size, UInt<3>(0h0)
connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE_2.valid, UInt<1>(0h0)
connect _requestBOI_WIRE_2.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits
connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid
connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready
node _requestBOI_uncommonBits_T_1 = or(_requestBOI_WIRE_3.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_1 = bits(_requestBOI_uncommonBits_T_1, 4, 0)
node _requestBOI_T_5 = shr(_requestBOI_WIRE_3.bits.source, 5)
node _requestBOI_T_6 = eq(_requestBOI_T_5, UInt<2>(0h2))
node _requestBOI_T_7 = leq(UInt<1>(0h0), requestBOI_uncommonBits_1)
node _requestBOI_T_8 = and(_requestBOI_T_6, _requestBOI_T_7)
node _requestBOI_T_9 = leq(requestBOI_uncommonBits_1, UInt<5>(0h1f))
node requestBOI_0_1 = and(_requestBOI_T_8, _requestBOI_T_9)
wire _requestBOI_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE_4.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE_4.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE_4.bits.address, UInt<32>(0h0)
connect _requestBOI_WIRE_4.bits.source, UInt<7>(0h0)
connect _requestBOI_WIRE_4.bits.size, UInt<3>(0h0)
connect _requestBOI_WIRE_4.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE_4.valid, UInt<1>(0h0)
connect _requestBOI_WIRE_4.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_5.bits, _requestBOI_WIRE_4.bits
connect _requestBOI_WIRE_5.valid, _requestBOI_WIRE_4.valid
connect _requestBOI_WIRE_5.ready, _requestBOI_WIRE_4.ready
node _requestBOI_uncommonBits_T_2 = or(_requestBOI_WIRE_5.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_2 = bits(_requestBOI_uncommonBits_T_2, 4, 0)
node _requestBOI_T_10 = shr(_requestBOI_WIRE_5.bits.source, 5)
node _requestBOI_T_11 = eq(_requestBOI_T_10, UInt<1>(0h1))
node _requestBOI_T_12 = leq(UInt<1>(0h0), requestBOI_uncommonBits_2)
node _requestBOI_T_13 = and(_requestBOI_T_11, _requestBOI_T_12)
node _requestBOI_T_14 = leq(requestBOI_uncommonBits_2, UInt<5>(0h1f))
node requestBOI_0_2 = and(_requestBOI_T_13, _requestBOI_T_14)
wire _requestBOI_WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE_6.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE_6.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE_6.bits.address, UInt<32>(0h0)
connect _requestBOI_WIRE_6.bits.source, UInt<7>(0h0)
connect _requestBOI_WIRE_6.bits.size, UInt<3>(0h0)
connect _requestBOI_WIRE_6.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE_6.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE_6.valid, UInt<1>(0h0)
connect _requestBOI_WIRE_6.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_7.bits, _requestBOI_WIRE_6.bits
connect _requestBOI_WIRE_7.valid, _requestBOI_WIRE_6.valid
connect _requestBOI_WIRE_7.ready, _requestBOI_WIRE_6.ready
node _requestBOI_uncommonBits_T_3 = or(_requestBOI_WIRE_7.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_3 = bits(_requestBOI_uncommonBits_T_3, 4, 0)
node _requestBOI_T_15 = shr(_requestBOI_WIRE_7.bits.source, 5)
node _requestBOI_T_16 = eq(_requestBOI_T_15, UInt<1>(0h0))
node _requestBOI_T_17 = leq(UInt<1>(0h0), requestBOI_uncommonBits_3)
node _requestBOI_T_18 = and(_requestBOI_T_16, _requestBOI_T_17)
node _requestBOI_T_19 = leq(requestBOI_uncommonBits_3, UInt<5>(0h1f))
node requestBOI_0_3 = and(_requestBOI_T_18, _requestBOI_T_19)
wire _requestBOI_WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE_8.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE_8.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE_8.bits.address, UInt<32>(0h0)
connect _requestBOI_WIRE_8.bits.source, UInt<7>(0h0)
connect _requestBOI_WIRE_8.bits.size, UInt<3>(0h0)
connect _requestBOI_WIRE_8.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE_8.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE_8.valid, UInt<1>(0h0)
connect _requestBOI_WIRE_8.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_9.bits, _requestBOI_WIRE_8.bits
connect _requestBOI_WIRE_9.valid, _requestBOI_WIRE_8.valid
connect _requestBOI_WIRE_9.ready, _requestBOI_WIRE_8.ready
node _requestBOI_uncommonBits_T_4 = or(_requestBOI_WIRE_9.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_4 = bits(_requestBOI_uncommonBits_T_4, 4, 0)
node _requestBOI_T_20 = shr(_requestBOI_WIRE_9.bits.source, 5)
node _requestBOI_T_21 = eq(_requestBOI_T_20, UInt<2>(0h3))
node _requestBOI_T_22 = leq(UInt<1>(0h0), requestBOI_uncommonBits_4)
node _requestBOI_T_23 = and(_requestBOI_T_21, _requestBOI_T_22)
node _requestBOI_T_24 = leq(requestBOI_uncommonBits_4, UInt<5>(0h1f))
node requestBOI_1_0 = and(_requestBOI_T_23, _requestBOI_T_24)
wire _requestBOI_WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE_10.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE_10.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE_10.bits.address, UInt<32>(0h0)
connect _requestBOI_WIRE_10.bits.source, UInt<7>(0h0)
connect _requestBOI_WIRE_10.bits.size, UInt<3>(0h0)
connect _requestBOI_WIRE_10.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE_10.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE_10.valid, UInt<1>(0h0)
connect _requestBOI_WIRE_10.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_11.bits, _requestBOI_WIRE_10.bits
connect _requestBOI_WIRE_11.valid, _requestBOI_WIRE_10.valid
connect _requestBOI_WIRE_11.ready, _requestBOI_WIRE_10.ready
node _requestBOI_uncommonBits_T_5 = or(_requestBOI_WIRE_11.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_5 = bits(_requestBOI_uncommonBits_T_5, 4, 0)
node _requestBOI_T_25 = shr(_requestBOI_WIRE_11.bits.source, 5)
node _requestBOI_T_26 = eq(_requestBOI_T_25, UInt<2>(0h2))
node _requestBOI_T_27 = leq(UInt<1>(0h0), requestBOI_uncommonBits_5)
node _requestBOI_T_28 = and(_requestBOI_T_26, _requestBOI_T_27)
node _requestBOI_T_29 = leq(requestBOI_uncommonBits_5, UInt<5>(0h1f))
node requestBOI_1_1 = and(_requestBOI_T_28, _requestBOI_T_29)
wire _requestBOI_WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE_12.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE_12.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE_12.bits.address, UInt<32>(0h0)
connect _requestBOI_WIRE_12.bits.source, UInt<7>(0h0)
connect _requestBOI_WIRE_12.bits.size, UInt<3>(0h0)
connect _requestBOI_WIRE_12.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE_12.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE_12.valid, UInt<1>(0h0)
connect _requestBOI_WIRE_12.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_13.bits, _requestBOI_WIRE_12.bits
connect _requestBOI_WIRE_13.valid, _requestBOI_WIRE_12.valid
connect _requestBOI_WIRE_13.ready, _requestBOI_WIRE_12.ready
node _requestBOI_uncommonBits_T_6 = or(_requestBOI_WIRE_13.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_6 = bits(_requestBOI_uncommonBits_T_6, 4, 0)
node _requestBOI_T_30 = shr(_requestBOI_WIRE_13.bits.source, 5)
node _requestBOI_T_31 = eq(_requestBOI_T_30, UInt<1>(0h1))
node _requestBOI_T_32 = leq(UInt<1>(0h0), requestBOI_uncommonBits_6)
node _requestBOI_T_33 = and(_requestBOI_T_31, _requestBOI_T_32)
node _requestBOI_T_34 = leq(requestBOI_uncommonBits_6, UInt<5>(0h1f))
node requestBOI_1_2 = and(_requestBOI_T_33, _requestBOI_T_34)
wire _requestBOI_WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE_14.bits.data, UInt<64>(0h0)
connect _requestBOI_WIRE_14.bits.mask, UInt<8>(0h0)
connect _requestBOI_WIRE_14.bits.address, UInt<32>(0h0)
connect _requestBOI_WIRE_14.bits.source, UInt<7>(0h0)
connect _requestBOI_WIRE_14.bits.size, UInt<3>(0h0)
connect _requestBOI_WIRE_14.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE_14.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE_14.valid, UInt<1>(0h0)
connect _requestBOI_WIRE_14.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_15.bits, _requestBOI_WIRE_14.bits
connect _requestBOI_WIRE_15.valid, _requestBOI_WIRE_14.valid
connect _requestBOI_WIRE_15.ready, _requestBOI_WIRE_14.ready
node _requestBOI_uncommonBits_T_7 = or(_requestBOI_WIRE_15.bits.source, UInt<5>(0h0))
node requestBOI_uncommonBits_7 = bits(_requestBOI_uncommonBits_T_7, 4, 0)
node _requestBOI_T_35 = shr(_requestBOI_WIRE_15.bits.source, 5)
node _requestBOI_T_36 = eq(_requestBOI_T_35, UInt<1>(0h0))
node _requestBOI_T_37 = leq(UInt<1>(0h0), requestBOI_uncommonBits_7)
node _requestBOI_T_38 = and(_requestBOI_T_36, _requestBOI_T_37)
node _requestBOI_T_39 = leq(requestBOI_uncommonBits_7, UInt<5>(0h1f))
node requestBOI_1_3 = and(_requestBOI_T_38, _requestBOI_T_39)
node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 4, 0)
node _requestDOI_T = shr(out[0].d.bits.source, 5)
node _requestDOI_T_1 = eq(_requestDOI_T, UInt<2>(0h3))
node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits)
node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2)
node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<5>(0h1f))
node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4)
node _requestDOI_uncommonBits_T_1 = or(out[0].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_1 = bits(_requestDOI_uncommonBits_T_1, 4, 0)
node _requestDOI_T_5 = shr(out[0].d.bits.source, 5)
node _requestDOI_T_6 = eq(_requestDOI_T_5, UInt<2>(0h2))
node _requestDOI_T_7 = leq(UInt<1>(0h0), requestDOI_uncommonBits_1)
node _requestDOI_T_8 = and(_requestDOI_T_6, _requestDOI_T_7)
node _requestDOI_T_9 = leq(requestDOI_uncommonBits_1, UInt<5>(0h1f))
node requestDOI_0_1 = and(_requestDOI_T_8, _requestDOI_T_9)
node _requestDOI_uncommonBits_T_2 = or(out[0].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_2 = bits(_requestDOI_uncommonBits_T_2, 4, 0)
node _requestDOI_T_10 = shr(out[0].d.bits.source, 5)
node _requestDOI_T_11 = eq(_requestDOI_T_10, UInt<1>(0h1))
node _requestDOI_T_12 = leq(UInt<1>(0h0), requestDOI_uncommonBits_2)
node _requestDOI_T_13 = and(_requestDOI_T_11, _requestDOI_T_12)
node _requestDOI_T_14 = leq(requestDOI_uncommonBits_2, UInt<5>(0h1f))
node requestDOI_0_2 = and(_requestDOI_T_13, _requestDOI_T_14)
node _requestDOI_uncommonBits_T_3 = or(out[0].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_3 = bits(_requestDOI_uncommonBits_T_3, 4, 0)
node _requestDOI_T_15 = shr(out[0].d.bits.source, 5)
node _requestDOI_T_16 = eq(_requestDOI_T_15, UInt<1>(0h0))
node _requestDOI_T_17 = leq(UInt<1>(0h0), requestDOI_uncommonBits_3)
node _requestDOI_T_18 = and(_requestDOI_T_16, _requestDOI_T_17)
node _requestDOI_T_19 = leq(requestDOI_uncommonBits_3, UInt<5>(0h1f))
node requestDOI_0_3 = and(_requestDOI_T_18, _requestDOI_T_19)
node _requestDOI_uncommonBits_T_4 = or(out[1].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_4 = bits(_requestDOI_uncommonBits_T_4, 4, 0)
node _requestDOI_T_20 = shr(out[1].d.bits.source, 5)
node _requestDOI_T_21 = eq(_requestDOI_T_20, UInt<2>(0h3))
node _requestDOI_T_22 = leq(UInt<1>(0h0), requestDOI_uncommonBits_4)
node _requestDOI_T_23 = and(_requestDOI_T_21, _requestDOI_T_22)
node _requestDOI_T_24 = leq(requestDOI_uncommonBits_4, UInt<5>(0h1f))
node requestDOI_1_0 = and(_requestDOI_T_23, _requestDOI_T_24)
node _requestDOI_uncommonBits_T_5 = or(out[1].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_5 = bits(_requestDOI_uncommonBits_T_5, 4, 0)
node _requestDOI_T_25 = shr(out[1].d.bits.source, 5)
node _requestDOI_T_26 = eq(_requestDOI_T_25, UInt<2>(0h2))
node _requestDOI_T_27 = leq(UInt<1>(0h0), requestDOI_uncommonBits_5)
node _requestDOI_T_28 = and(_requestDOI_T_26, _requestDOI_T_27)
node _requestDOI_T_29 = leq(requestDOI_uncommonBits_5, UInt<5>(0h1f))
node requestDOI_1_1 = and(_requestDOI_T_28, _requestDOI_T_29)
node _requestDOI_uncommonBits_T_6 = or(out[1].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_6 = bits(_requestDOI_uncommonBits_T_6, 4, 0)
node _requestDOI_T_30 = shr(out[1].d.bits.source, 5)
node _requestDOI_T_31 = eq(_requestDOI_T_30, UInt<1>(0h1))
node _requestDOI_T_32 = leq(UInt<1>(0h0), requestDOI_uncommonBits_6)
node _requestDOI_T_33 = and(_requestDOI_T_31, _requestDOI_T_32)
node _requestDOI_T_34 = leq(requestDOI_uncommonBits_6, UInt<5>(0h1f))
node requestDOI_1_2 = and(_requestDOI_T_33, _requestDOI_T_34)
node _requestDOI_uncommonBits_T_7 = or(out[1].d.bits.source, UInt<5>(0h0))
node requestDOI_uncommonBits_7 = bits(_requestDOI_uncommonBits_T_7, 4, 0)
node _requestDOI_T_35 = shr(out[1].d.bits.source, 5)
node _requestDOI_T_36 = eq(_requestDOI_T_35, UInt<1>(0h0))
node _requestDOI_T_37 = leq(UInt<1>(0h0), requestDOI_uncommonBits_7)
node _requestDOI_T_38 = and(_requestDOI_T_36, _requestDOI_T_37)
node _requestDOI_T_39 = leq(requestDOI_uncommonBits_7, UInt<5>(0h1f))
node requestDOI_1_3 = and(_requestDOI_T_38, _requestDOI_T_39)
wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE.valid, UInt<1>(0h0)
connect _requestEIO_WIRE.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits
connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid
connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready
wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_2.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE_2.valid, UInt<1>(0h0)
connect _requestEIO_WIRE_2.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits
connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid
connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready
wire _requestEIO_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_4.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE_4.valid, UInt<1>(0h0)
connect _requestEIO_WIRE_4.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_5.bits, _requestEIO_WIRE_4.bits
connect _requestEIO_WIRE_5.valid, _requestEIO_WIRE_4.valid
connect _requestEIO_WIRE_5.ready, _requestEIO_WIRE_4.ready
wire _requestEIO_WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_6.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE_6.valid, UInt<1>(0h0)
connect _requestEIO_WIRE_6.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_7.bits, _requestEIO_WIRE_6.bits
connect _requestEIO_WIRE_7.valid, _requestEIO_WIRE_6.valid
connect _requestEIO_WIRE_7.ready, _requestEIO_WIRE_6.ready
wire _requestEIO_WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_8.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE_8.valid, UInt<1>(0h0)
connect _requestEIO_WIRE_8.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_9.bits, _requestEIO_WIRE_8.bits
connect _requestEIO_WIRE_9.valid, _requestEIO_WIRE_8.valid
connect _requestEIO_WIRE_9.ready, _requestEIO_WIRE_8.ready
wire _requestEIO_WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_10.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE_10.valid, UInt<1>(0h0)
connect _requestEIO_WIRE_10.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_11.bits, _requestEIO_WIRE_10.bits
connect _requestEIO_WIRE_11.valid, _requestEIO_WIRE_10.valid
connect _requestEIO_WIRE_11.ready, _requestEIO_WIRE_10.ready
wire _requestEIO_WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_12.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE_12.valid, UInt<1>(0h0)
connect _requestEIO_WIRE_12.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_13.bits, _requestEIO_WIRE_12.bits
connect _requestEIO_WIRE_13.valid, _requestEIO_WIRE_12.valid
connect _requestEIO_WIRE_13.ready, _requestEIO_WIRE_12.ready
wire _requestEIO_WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_14.bits.sink, UInt<1>(0h0)
connect _requestEIO_WIRE_14.valid, UInt<1>(0h0)
connect _requestEIO_WIRE_14.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _requestEIO_WIRE_15.bits, _requestEIO_WIRE_14.bits
connect _requestEIO_WIRE_15.valid, _requestEIO_WIRE_14.valid
connect _requestEIO_WIRE_15.ready, _requestEIO_WIRE_14.ready
node _beatsAI_decode_T = dshl(UInt<6>(0h3f), in[0].a.bits.size)
node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 5, 0)
node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1)
node beatsAI_decode = shr(_beatsAI_decode_T_2, 3)
node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2)
node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0))
node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0))
node _beatsAI_decode_T_3 = dshl(UInt<6>(0h3f), in[1].a.bits.size)
node _beatsAI_decode_T_4 = bits(_beatsAI_decode_T_3, 5, 0)
node _beatsAI_decode_T_5 = not(_beatsAI_decode_T_4)
node beatsAI_decode_1 = shr(_beatsAI_decode_T_5, 3)
node _beatsAI_opdata_T_1 = bits(in[1].a.bits.opcode, 2, 2)
node beatsAI_opdata_1 = eq(_beatsAI_opdata_T_1, UInt<1>(0h0))
node beatsAI_1 = mux(beatsAI_opdata_1, beatsAI_decode_1, UInt<1>(0h0))
node _beatsAI_decode_T_6 = dshl(UInt<6>(0h3f), in[2].a.bits.size)
node _beatsAI_decode_T_7 = bits(_beatsAI_decode_T_6, 5, 0)
node _beatsAI_decode_T_8 = not(_beatsAI_decode_T_7)
node beatsAI_decode_2 = shr(_beatsAI_decode_T_8, 3)
node _beatsAI_opdata_T_2 = bits(in[2].a.bits.opcode, 2, 2)
node beatsAI_opdata_2 = eq(_beatsAI_opdata_T_2, UInt<1>(0h0))
node beatsAI_2 = mux(beatsAI_opdata_2, beatsAI_decode_2, UInt<1>(0h0))
node _beatsAI_decode_T_9 = dshl(UInt<6>(0h3f), in[3].a.bits.size)
node _beatsAI_decode_T_10 = bits(_beatsAI_decode_T_9, 5, 0)
node _beatsAI_decode_T_11 = not(_beatsAI_decode_T_10)
node beatsAI_decode_3 = shr(_beatsAI_decode_T_11, 3)
node _beatsAI_opdata_T_3 = bits(in[3].a.bits.opcode, 2, 2)
node beatsAI_opdata_3 = eq(_beatsAI_opdata_T_3, UInt<1>(0h0))
node beatsAI_3 = mux(beatsAI_opdata_3, beatsAI_decode_3, UInt<1>(0h0))
wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0)
connect _beatsBO_WIRE.bits.data, UInt<64>(0h0)
connect _beatsBO_WIRE.bits.mask, UInt<8>(0h0)
connect _beatsBO_WIRE.bits.address, UInt<32>(0h0)
connect _beatsBO_WIRE.bits.source, UInt<7>(0h0)
connect _beatsBO_WIRE.bits.size, UInt<3>(0h0)
connect _beatsBO_WIRE.bits.param, UInt<2>(0h0)
connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0)
connect _beatsBO_WIRE.valid, UInt<1>(0h0)
connect _beatsBO_WIRE.ready, UInt<1>(0h0)
wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits
connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid
connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready
node _beatsBO_decode_T = dshl(UInt<6>(0h3f), _beatsBO_WIRE_1.bits.size)
node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 5, 0)
node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1)
node beatsBO_decode = shr(_beatsBO_decode_T_2, 3)
node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2)
node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0))
node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0))
wire _beatsBO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _beatsBO_WIRE_2.bits.data, UInt<64>(0h0)
connect _beatsBO_WIRE_2.bits.mask, UInt<8>(0h0)
connect _beatsBO_WIRE_2.bits.address, UInt<32>(0h0)
connect _beatsBO_WIRE_2.bits.source, UInt<7>(0h0)
connect _beatsBO_WIRE_2.bits.size, UInt<3>(0h0)
connect _beatsBO_WIRE_2.bits.param, UInt<2>(0h0)
connect _beatsBO_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _beatsBO_WIRE_2.valid, UInt<1>(0h0)
connect _beatsBO_WIRE_2.ready, UInt<1>(0h0)
wire _beatsBO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_3.bits, _beatsBO_WIRE_2.bits
connect _beatsBO_WIRE_3.valid, _beatsBO_WIRE_2.valid
connect _beatsBO_WIRE_3.ready, _beatsBO_WIRE_2.ready
node _beatsBO_decode_T_3 = dshl(UInt<6>(0h3f), _beatsBO_WIRE_3.bits.size)
node _beatsBO_decode_T_4 = bits(_beatsBO_decode_T_3, 5, 0)
node _beatsBO_decode_T_5 = not(_beatsBO_decode_T_4)
node beatsBO_decode_1 = shr(_beatsBO_decode_T_5, 3)
node _beatsBO_opdata_T_1 = bits(_beatsBO_WIRE_3.bits.opcode, 2, 2)
node beatsBO_opdata_1 = eq(_beatsBO_opdata_T_1, UInt<1>(0h0))
node beatsBO_1 = mux(UInt<1>(0h0), beatsBO_decode_1, UInt<1>(0h0))
wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.data, UInt<64>(0h0)
connect _beatsCI_WIRE.bits.address, UInt<32>(0h0)
connect _beatsCI_WIRE.bits.source, UInt<7>(0h0)
connect _beatsCI_WIRE.bits.size, UInt<3>(0h0)
connect _beatsCI_WIRE.bits.param, UInt<3>(0h0)
connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0)
connect _beatsCI_WIRE.valid, UInt<1>(0h0)
connect _beatsCI_WIRE.ready, UInt<1>(0h0)
wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits
connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid
connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready
node _beatsCI_decode_T = dshl(UInt<6>(0h3f), _beatsCI_WIRE_1.bits.size)
node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 5, 0)
node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1)
node beatsCI_decode = shr(_beatsCI_decode_T_2, 3)
node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0)
node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0))
wire _beatsCI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _beatsCI_WIRE_2.bits.data, UInt<64>(0h0)
connect _beatsCI_WIRE_2.bits.address, UInt<32>(0h0)
connect _beatsCI_WIRE_2.bits.source, UInt<7>(0h0)
connect _beatsCI_WIRE_2.bits.size, UInt<3>(0h0)
connect _beatsCI_WIRE_2.bits.param, UInt<3>(0h0)
connect _beatsCI_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _beatsCI_WIRE_2.valid, UInt<1>(0h0)
connect _beatsCI_WIRE_2.ready, UInt<1>(0h0)
wire _beatsCI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_3.bits, _beatsCI_WIRE_2.bits
connect _beatsCI_WIRE_3.valid, _beatsCI_WIRE_2.valid
connect _beatsCI_WIRE_3.ready, _beatsCI_WIRE_2.ready
node _beatsCI_decode_T_3 = dshl(UInt<6>(0h3f), _beatsCI_WIRE_3.bits.size)
node _beatsCI_decode_T_4 = bits(_beatsCI_decode_T_3, 5, 0)
node _beatsCI_decode_T_5 = not(_beatsCI_decode_T_4)
node beatsCI_decode_1 = shr(_beatsCI_decode_T_5, 3)
node beatsCI_opdata_1 = bits(_beatsCI_WIRE_3.bits.opcode, 0, 0)
node beatsCI_1 = mux(UInt<1>(0h0), beatsCI_decode_1, UInt<1>(0h0))
wire _beatsCI_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _beatsCI_WIRE_4.bits.data, UInt<64>(0h0)
connect _beatsCI_WIRE_4.bits.address, UInt<32>(0h0)
connect _beatsCI_WIRE_4.bits.source, UInt<7>(0h0)
connect _beatsCI_WIRE_4.bits.size, UInt<3>(0h0)
connect _beatsCI_WIRE_4.bits.param, UInt<3>(0h0)
connect _beatsCI_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _beatsCI_WIRE_4.valid, UInt<1>(0h0)
connect _beatsCI_WIRE_4.ready, UInt<1>(0h0)
wire _beatsCI_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_5.bits, _beatsCI_WIRE_4.bits
connect _beatsCI_WIRE_5.valid, _beatsCI_WIRE_4.valid
connect _beatsCI_WIRE_5.ready, _beatsCI_WIRE_4.ready
node _beatsCI_decode_T_6 = dshl(UInt<6>(0h3f), _beatsCI_WIRE_5.bits.size)
node _beatsCI_decode_T_7 = bits(_beatsCI_decode_T_6, 5, 0)
node _beatsCI_decode_T_8 = not(_beatsCI_decode_T_7)
node beatsCI_decode_2 = shr(_beatsCI_decode_T_8, 3)
node beatsCI_opdata_2 = bits(_beatsCI_WIRE_5.bits.opcode, 0, 0)
node beatsCI_2 = mux(UInt<1>(0h0), beatsCI_decode_2, UInt<1>(0h0))
wire _beatsCI_WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _beatsCI_WIRE_6.bits.data, UInt<64>(0h0)
connect _beatsCI_WIRE_6.bits.address, UInt<32>(0h0)
connect _beatsCI_WIRE_6.bits.source, UInt<7>(0h0)
connect _beatsCI_WIRE_6.bits.size, UInt<3>(0h0)
connect _beatsCI_WIRE_6.bits.param, UInt<3>(0h0)
connect _beatsCI_WIRE_6.bits.opcode, UInt<3>(0h0)
connect _beatsCI_WIRE_6.valid, UInt<1>(0h0)
connect _beatsCI_WIRE_6.ready, UInt<1>(0h0)
wire _beatsCI_WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_7.bits, _beatsCI_WIRE_6.bits
connect _beatsCI_WIRE_7.valid, _beatsCI_WIRE_6.valid
connect _beatsCI_WIRE_7.ready, _beatsCI_WIRE_6.ready
node _beatsCI_decode_T_9 = dshl(UInt<6>(0h3f), _beatsCI_WIRE_7.bits.size)
node _beatsCI_decode_T_10 = bits(_beatsCI_decode_T_9, 5, 0)
node _beatsCI_decode_T_11 = not(_beatsCI_decode_T_10)
node beatsCI_decode_3 = shr(_beatsCI_decode_T_11, 3)
node beatsCI_opdata_3 = bits(_beatsCI_WIRE_7.bits.opcode, 0, 0)
node beatsCI_3 = mux(UInt<1>(0h0), beatsCI_decode_3, UInt<1>(0h0))
node _beatsDO_decode_T = dshl(UInt<6>(0h3f), out[0].d.bits.size)
node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 5, 0)
node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1)
node beatsDO_decode = shr(_beatsDO_decode_T_2, 3)
node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0)
node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0))
node _beatsDO_decode_T_3 = dshl(UInt<6>(0h3f), out[1].d.bits.size)
node _beatsDO_decode_T_4 = bits(_beatsDO_decode_T_3, 5, 0)
node _beatsDO_decode_T_5 = not(_beatsDO_decode_T_4)
node beatsDO_decode_1 = shr(_beatsDO_decode_T_5, 3)
node beatsDO_opdata_1 = bits(out[1].d.bits.opcode, 0, 0)
node beatsDO_1 = mux(beatsDO_opdata_1, beatsDO_decode_1, UInt<1>(0h0))
wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE.bits.sink, UInt<1>(0h0)
connect _beatsEI_WIRE.valid, UInt<1>(0h0)
connect _beatsEI_WIRE.ready, UInt<1>(0h0)
wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits
connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid
connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready
wire _beatsEI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE_2.bits.sink, UInt<1>(0h0)
connect _beatsEI_WIRE_2.valid, UInt<1>(0h0)
connect _beatsEI_WIRE_2.ready, UInt<1>(0h0)
wire _beatsEI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE_3.bits, _beatsEI_WIRE_2.bits
connect _beatsEI_WIRE_3.valid, _beatsEI_WIRE_2.valid
connect _beatsEI_WIRE_3.ready, _beatsEI_WIRE_2.ready
wire _beatsEI_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE_4.bits.sink, UInt<1>(0h0)
connect _beatsEI_WIRE_4.valid, UInt<1>(0h0)
connect _beatsEI_WIRE_4.ready, UInt<1>(0h0)
wire _beatsEI_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE_5.bits, _beatsEI_WIRE_4.bits
connect _beatsEI_WIRE_5.valid, _beatsEI_WIRE_4.valid
connect _beatsEI_WIRE_5.ready, _beatsEI_WIRE_4.ready
wire _beatsEI_WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE_6.bits.sink, UInt<1>(0h0)
connect _beatsEI_WIRE_6.valid, UInt<1>(0h0)
connect _beatsEI_WIRE_6.ready, UInt<1>(0h0)
wire _beatsEI_WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _beatsEI_WIRE_7.bits, _beatsEI_WIRE_6.bits
connect _beatsEI_WIRE_7.valid, _beatsEI_WIRE_6.valid
connect _beatsEI_WIRE_7.ready, _beatsEI_WIRE_6.ready
wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsAOI_filtered[0].bits, in[0].a.bits
node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T)
connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1
connect portsAOI_filtered[1].bits, in[0].a.bits
node _portsAOI_filtered_1_valid_T = or(requestAIO_0_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_1_valid_T)
connect portsAOI_filtered[1].valid, _portsAOI_filtered_1_valid_T_1
node _portsAOI_in_0_a_ready_T = mux(requestAIO_0_0, portsAOI_filtered[0].ready, UInt<1>(0h0))
node _portsAOI_in_0_a_ready_T_1 = mux(requestAIO_0_1, portsAOI_filtered[1].ready, UInt<1>(0h0))
node _portsAOI_in_0_a_ready_T_2 = or(_portsAOI_in_0_a_ready_T, _portsAOI_in_0_a_ready_T_1)
wire _portsAOI_in_0_a_ready_WIRE : UInt<1>
connect _portsAOI_in_0_a_ready_WIRE, _portsAOI_in_0_a_ready_T_2
connect in[0].a.ready, _portsAOI_in_0_a_ready_WIRE
wire portsAOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsAOI_filtered_1[0].bits, in[1].a.bits
node _portsAOI_filtered_0_valid_T_2 = or(requestAIO_1_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_0_valid_T_2)
connect portsAOI_filtered_1[0].valid, _portsAOI_filtered_0_valid_T_3
connect portsAOI_filtered_1[1].bits, in[1].a.bits
node _portsAOI_filtered_1_valid_T_2 = or(requestAIO_1_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_1_valid_T_2)
connect portsAOI_filtered_1[1].valid, _portsAOI_filtered_1_valid_T_3
node _portsAOI_in_1_a_ready_T = mux(requestAIO_1_0, portsAOI_filtered_1[0].ready, UInt<1>(0h0))
node _portsAOI_in_1_a_ready_T_1 = mux(requestAIO_1_1, portsAOI_filtered_1[1].ready, UInt<1>(0h0))
node _portsAOI_in_1_a_ready_T_2 = or(_portsAOI_in_1_a_ready_T, _portsAOI_in_1_a_ready_T_1)
wire _portsAOI_in_1_a_ready_WIRE : UInt<1>
connect _portsAOI_in_1_a_ready_WIRE, _portsAOI_in_1_a_ready_T_2
connect in[1].a.ready, _portsAOI_in_1_a_ready_WIRE
wire portsAOI_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsAOI_filtered_2[0].bits, in[2].a.bits
node _portsAOI_filtered_0_valid_T_4 = or(requestAIO_2_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_5 = and(in[2].a.valid, _portsAOI_filtered_0_valid_T_4)
connect portsAOI_filtered_2[0].valid, _portsAOI_filtered_0_valid_T_5
connect portsAOI_filtered_2[1].bits, in[2].a.bits
node _portsAOI_filtered_1_valid_T_4 = or(requestAIO_2_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_5 = and(in[2].a.valid, _portsAOI_filtered_1_valid_T_4)
connect portsAOI_filtered_2[1].valid, _portsAOI_filtered_1_valid_T_5
node _portsAOI_in_2_a_ready_T = mux(requestAIO_2_0, portsAOI_filtered_2[0].ready, UInt<1>(0h0))
node _portsAOI_in_2_a_ready_T_1 = mux(requestAIO_2_1, portsAOI_filtered_2[1].ready, UInt<1>(0h0))
node _portsAOI_in_2_a_ready_T_2 = or(_portsAOI_in_2_a_ready_T, _portsAOI_in_2_a_ready_T_1)
wire _portsAOI_in_2_a_ready_WIRE : UInt<1>
connect _portsAOI_in_2_a_ready_WIRE, _portsAOI_in_2_a_ready_T_2
connect in[2].a.ready, _portsAOI_in_2_a_ready_WIRE
wire portsAOI_filtered_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsAOI_filtered_3[0].bits, in[3].a.bits
node _portsAOI_filtered_0_valid_T_6 = or(requestAIO_3_0, UInt<1>(0h0))
node _portsAOI_filtered_0_valid_T_7 = and(in[3].a.valid, _portsAOI_filtered_0_valid_T_6)
connect portsAOI_filtered_3[0].valid, _portsAOI_filtered_0_valid_T_7
connect portsAOI_filtered_3[1].bits, in[3].a.bits
node _portsAOI_filtered_1_valid_T_6 = or(requestAIO_3_1, UInt<1>(0h0))
node _portsAOI_filtered_1_valid_T_7 = and(in[3].a.valid, _portsAOI_filtered_1_valid_T_6)
connect portsAOI_filtered_3[1].valid, _portsAOI_filtered_1_valid_T_7
node _portsAOI_in_3_a_ready_T = mux(requestAIO_3_0, portsAOI_filtered_3[0].ready, UInt<1>(0h0))
node _portsAOI_in_3_a_ready_T_1 = mux(requestAIO_3_1, portsAOI_filtered_3[1].ready, UInt<1>(0h0))
node _portsAOI_in_3_a_ready_T_2 = or(_portsAOI_in_3_a_ready_T, _portsAOI_in_3_a_ready_T_1)
wire _portsAOI_in_3_a_ready_WIRE : UInt<1>
connect _portsAOI_in_3_a_ready_WIRE, _portsAOI_in_3_a_ready_T_2
connect in[3].a.ready, _portsAOI_in_3_a_ready_WIRE
wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0)
connect _portsBIO_WIRE.bits.data, UInt<64>(0h0)
connect _portsBIO_WIRE.bits.mask, UInt<8>(0h0)
connect _portsBIO_WIRE.bits.address, UInt<32>(0h0)
connect _portsBIO_WIRE.bits.source, UInt<7>(0h0)
connect _portsBIO_WIRE.bits.size, UInt<3>(0h0)
connect _portsBIO_WIRE.bits.param, UInt<2>(0h0)
connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0)
connect _portsBIO_WIRE.valid, UInt<1>(0h0)
connect _portsBIO_WIRE.ready, UInt<1>(0h0)
wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits
connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid
connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready
wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[4]
connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits
node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h0))
node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T)
connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1
connect portsBIO_filtered[1].bits, _portsBIO_WIRE_1.bits
node _portsBIO_filtered_1_valid_T = or(requestBOI_0_1, UInt<1>(0h0))
node _portsBIO_filtered_1_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_1_valid_T)
connect portsBIO_filtered[1].valid, _portsBIO_filtered_1_valid_T_1
connect portsBIO_filtered[2].bits, _portsBIO_WIRE_1.bits
node _portsBIO_filtered_2_valid_T = or(requestBOI_0_2, UInt<1>(0h0))
node _portsBIO_filtered_2_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_2_valid_T)
connect portsBIO_filtered[2].valid, _portsBIO_filtered_2_valid_T_1
connect portsBIO_filtered[3].bits, _portsBIO_WIRE_1.bits
node _portsBIO_filtered_3_valid_T = or(requestBOI_0_3, UInt<1>(0h0))
node _portsBIO_filtered_3_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_3_valid_T)
connect portsBIO_filtered[3].valid, _portsBIO_filtered_3_valid_T_1
node _portsBIO_T = mux(requestBOI_0_0, portsBIO_filtered[0].ready, UInt<1>(0h0))
node _portsBIO_T_1 = mux(requestBOI_0_1, portsBIO_filtered[1].ready, UInt<1>(0h0))
node _portsBIO_T_2 = mux(requestBOI_0_2, portsBIO_filtered[2].ready, UInt<1>(0h0))
node _portsBIO_T_3 = mux(requestBOI_0_3, portsBIO_filtered[3].ready, UInt<1>(0h0))
node _portsBIO_T_4 = or(_portsBIO_T, _portsBIO_T_1)
node _portsBIO_T_5 = or(_portsBIO_T_4, _portsBIO_T_2)
node _portsBIO_T_6 = or(_portsBIO_T_5, _portsBIO_T_3)
wire _portsBIO_WIRE_2 : UInt<1>
connect _portsBIO_WIRE_2, _portsBIO_T_6
connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE_2
wire _portsBIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_3.bits.corrupt, UInt<1>(0h0)
connect _portsBIO_WIRE_3.bits.data, UInt<64>(0h0)
connect _portsBIO_WIRE_3.bits.mask, UInt<8>(0h0)
connect _portsBIO_WIRE_3.bits.address, UInt<32>(0h0)
connect _portsBIO_WIRE_3.bits.source, UInt<7>(0h0)
connect _portsBIO_WIRE_3.bits.size, UInt<3>(0h0)
connect _portsBIO_WIRE_3.bits.param, UInt<2>(0h0)
connect _portsBIO_WIRE_3.bits.opcode, UInt<3>(0h0)
connect _portsBIO_WIRE_3.valid, UInt<1>(0h0)
connect _portsBIO_WIRE_3.ready, UInt<1>(0h0)
wire _portsBIO_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_4.bits, _portsBIO_WIRE_3.bits
connect _portsBIO_WIRE_4.valid, _portsBIO_WIRE_3.valid
connect _portsBIO_WIRE_4.ready, _portsBIO_WIRE_3.ready
wire portsBIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}[4]
connect portsBIO_filtered_1[0].bits, _portsBIO_WIRE_4.bits
node _portsBIO_filtered_0_valid_T_2 = or(requestBOI_1_0, UInt<1>(0h0))
node _portsBIO_filtered_0_valid_T_3 = and(_portsBIO_WIRE_4.valid, _portsBIO_filtered_0_valid_T_2)
connect portsBIO_filtered_1[0].valid, _portsBIO_filtered_0_valid_T_3
connect portsBIO_filtered_1[1].bits, _portsBIO_WIRE_4.bits
node _portsBIO_filtered_1_valid_T_2 = or(requestBOI_1_1, UInt<1>(0h0))
node _portsBIO_filtered_1_valid_T_3 = and(_portsBIO_WIRE_4.valid, _portsBIO_filtered_1_valid_T_2)
connect portsBIO_filtered_1[1].valid, _portsBIO_filtered_1_valid_T_3
connect portsBIO_filtered_1[2].bits, _portsBIO_WIRE_4.bits
node _portsBIO_filtered_2_valid_T_2 = or(requestBOI_1_2, UInt<1>(0h0))
node _portsBIO_filtered_2_valid_T_3 = and(_portsBIO_WIRE_4.valid, _portsBIO_filtered_2_valid_T_2)
connect portsBIO_filtered_1[2].valid, _portsBIO_filtered_2_valid_T_3
connect portsBIO_filtered_1[3].bits, _portsBIO_WIRE_4.bits
node _portsBIO_filtered_3_valid_T_2 = or(requestBOI_1_3, UInt<1>(0h0))
node _portsBIO_filtered_3_valid_T_3 = and(_portsBIO_WIRE_4.valid, _portsBIO_filtered_3_valid_T_2)
connect portsBIO_filtered_1[3].valid, _portsBIO_filtered_3_valid_T_3
node _portsBIO_T_7 = mux(requestBOI_1_0, portsBIO_filtered_1[0].ready, UInt<1>(0h0))
node _portsBIO_T_8 = mux(requestBOI_1_1, portsBIO_filtered_1[1].ready, UInt<1>(0h0))
node _portsBIO_T_9 = mux(requestBOI_1_2, portsBIO_filtered_1[2].ready, UInt<1>(0h0))
node _portsBIO_T_10 = mux(requestBOI_1_3, portsBIO_filtered_1[3].ready, UInt<1>(0h0))
node _portsBIO_T_11 = or(_portsBIO_T_7, _portsBIO_T_8)
node _portsBIO_T_12 = or(_portsBIO_T_11, _portsBIO_T_9)
node _portsBIO_T_13 = or(_portsBIO_T_12, _portsBIO_T_10)
wire _portsBIO_WIRE_5 : UInt<1>
connect _portsBIO_WIRE_5, _portsBIO_T_13
connect _portsBIO_WIRE_4.ready, _portsBIO_WIRE_5
wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.data, UInt<64>(0h0)
connect _portsCOI_WIRE.bits.address, UInt<32>(0h0)
connect _portsCOI_WIRE.bits.source, UInt<7>(0h0)
connect _portsCOI_WIRE.bits.size, UInt<3>(0h0)
connect _portsCOI_WIRE.bits.param, UInt<3>(0h0)
connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0)
connect _portsCOI_WIRE.valid, UInt<1>(0h0)
connect _portsCOI_WIRE.ready, UInt<1>(0h0)
wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits
connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid
connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready
wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits
node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T)
connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1
connect portsCOI_filtered[1].bits, _portsCOI_WIRE_1.bits
node _portsCOI_filtered_1_valid_T = or(requestCIO_0_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_1_valid_T)
connect portsCOI_filtered[1].valid, _portsCOI_filtered_1_valid_T_1
node _portsCOI_T = mux(requestCIO_0_0, portsCOI_filtered[0].ready, UInt<1>(0h0))
node _portsCOI_T_1 = mux(requestCIO_0_1, portsCOI_filtered[1].ready, UInt<1>(0h0))
node _portsCOI_T_2 = or(_portsCOI_T, _portsCOI_T_1)
wire _portsCOI_WIRE_2 : UInt<1>
connect _portsCOI_WIRE_2, _portsCOI_T_2
connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE_2
wire _portsCOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_3.bits.corrupt, UInt<1>(0h0)
connect _portsCOI_WIRE_3.bits.data, UInt<64>(0h0)
connect _portsCOI_WIRE_3.bits.address, UInt<32>(0h0)
connect _portsCOI_WIRE_3.bits.source, UInt<7>(0h0)
connect _portsCOI_WIRE_3.bits.size, UInt<3>(0h0)
connect _portsCOI_WIRE_3.bits.param, UInt<3>(0h0)
connect _portsCOI_WIRE_3.bits.opcode, UInt<3>(0h0)
connect _portsCOI_WIRE_3.valid, UInt<1>(0h0)
connect _portsCOI_WIRE_3.ready, UInt<1>(0h0)
wire _portsCOI_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_4.bits, _portsCOI_WIRE_3.bits
connect _portsCOI_WIRE_4.valid, _portsCOI_WIRE_3.valid
connect _portsCOI_WIRE_4.ready, _portsCOI_WIRE_3.ready
wire portsCOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsCOI_filtered_1[0].bits, _portsCOI_WIRE_4.bits
node _portsCOI_filtered_0_valid_T_2 = or(requestCIO_1_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_3 = and(_portsCOI_WIRE_4.valid, _portsCOI_filtered_0_valid_T_2)
connect portsCOI_filtered_1[0].valid, _portsCOI_filtered_0_valid_T_3
connect portsCOI_filtered_1[1].bits, _portsCOI_WIRE_4.bits
node _portsCOI_filtered_1_valid_T_2 = or(requestCIO_1_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_3 = and(_portsCOI_WIRE_4.valid, _portsCOI_filtered_1_valid_T_2)
connect portsCOI_filtered_1[1].valid, _portsCOI_filtered_1_valid_T_3
node _portsCOI_T_3 = mux(requestCIO_1_0, portsCOI_filtered_1[0].ready, UInt<1>(0h0))
node _portsCOI_T_4 = mux(requestCIO_1_1, portsCOI_filtered_1[1].ready, UInt<1>(0h0))
node _portsCOI_T_5 = or(_portsCOI_T_3, _portsCOI_T_4)
wire _portsCOI_WIRE_5 : UInt<1>
connect _portsCOI_WIRE_5, _portsCOI_T_5
connect _portsCOI_WIRE_4.ready, _portsCOI_WIRE_5
wire _portsCOI_WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _portsCOI_WIRE_6.bits.data, UInt<64>(0h0)
connect _portsCOI_WIRE_6.bits.address, UInt<32>(0h0)
connect _portsCOI_WIRE_6.bits.source, UInt<7>(0h0)
connect _portsCOI_WIRE_6.bits.size, UInt<3>(0h0)
connect _portsCOI_WIRE_6.bits.param, UInt<3>(0h0)
connect _portsCOI_WIRE_6.bits.opcode, UInt<3>(0h0)
connect _portsCOI_WIRE_6.valid, UInt<1>(0h0)
connect _portsCOI_WIRE_6.ready, UInt<1>(0h0)
wire _portsCOI_WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_7.bits, _portsCOI_WIRE_6.bits
connect _portsCOI_WIRE_7.valid, _portsCOI_WIRE_6.valid
connect _portsCOI_WIRE_7.ready, _portsCOI_WIRE_6.ready
wire portsCOI_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsCOI_filtered_2[0].bits, _portsCOI_WIRE_7.bits
node _portsCOI_filtered_0_valid_T_4 = or(requestCIO_2_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_5 = and(_portsCOI_WIRE_7.valid, _portsCOI_filtered_0_valid_T_4)
connect portsCOI_filtered_2[0].valid, _portsCOI_filtered_0_valid_T_5
connect portsCOI_filtered_2[1].bits, _portsCOI_WIRE_7.bits
node _portsCOI_filtered_1_valid_T_4 = or(requestCIO_2_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_5 = and(_portsCOI_WIRE_7.valid, _portsCOI_filtered_1_valid_T_4)
connect portsCOI_filtered_2[1].valid, _portsCOI_filtered_1_valid_T_5
node _portsCOI_T_6 = mux(requestCIO_2_0, portsCOI_filtered_2[0].ready, UInt<1>(0h0))
node _portsCOI_T_7 = mux(requestCIO_2_1, portsCOI_filtered_2[1].ready, UInt<1>(0h0))
node _portsCOI_T_8 = or(_portsCOI_T_6, _portsCOI_T_7)
wire _portsCOI_WIRE_8 : UInt<1>
connect _portsCOI_WIRE_8, _portsCOI_T_8
connect _portsCOI_WIRE_7.ready, _portsCOI_WIRE_8
wire _portsCOI_WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_9.bits.corrupt, UInt<1>(0h0)
connect _portsCOI_WIRE_9.bits.data, UInt<64>(0h0)
connect _portsCOI_WIRE_9.bits.address, UInt<32>(0h0)
connect _portsCOI_WIRE_9.bits.source, UInt<7>(0h0)
connect _portsCOI_WIRE_9.bits.size, UInt<3>(0h0)
connect _portsCOI_WIRE_9.bits.param, UInt<3>(0h0)
connect _portsCOI_WIRE_9.bits.opcode, UInt<3>(0h0)
connect _portsCOI_WIRE_9.valid, UInt<1>(0h0)
connect _portsCOI_WIRE_9.ready, UInt<1>(0h0)
wire _portsCOI_WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_10.bits, _portsCOI_WIRE_9.bits
connect _portsCOI_WIRE_10.valid, _portsCOI_WIRE_9.valid
connect _portsCOI_WIRE_10.ready, _portsCOI_WIRE_9.ready
wire portsCOI_filtered_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[2]
connect portsCOI_filtered_3[0].bits, _portsCOI_WIRE_10.bits
node _portsCOI_filtered_0_valid_T_6 = or(requestCIO_3_0, UInt<1>(0h0))
node _portsCOI_filtered_0_valid_T_7 = and(_portsCOI_WIRE_10.valid, _portsCOI_filtered_0_valid_T_6)
connect portsCOI_filtered_3[0].valid, _portsCOI_filtered_0_valid_T_7
connect portsCOI_filtered_3[1].bits, _portsCOI_WIRE_10.bits
node _portsCOI_filtered_1_valid_T_6 = or(requestCIO_3_1, UInt<1>(0h0))
node _portsCOI_filtered_1_valid_T_7 = and(_portsCOI_WIRE_10.valid, _portsCOI_filtered_1_valid_T_6)
connect portsCOI_filtered_3[1].valid, _portsCOI_filtered_1_valid_T_7
node _portsCOI_T_9 = mux(requestCIO_3_0, portsCOI_filtered_3[0].ready, UInt<1>(0h0))
node _portsCOI_T_10 = mux(requestCIO_3_1, portsCOI_filtered_3[1].ready, UInt<1>(0h0))
node _portsCOI_T_11 = or(_portsCOI_T_9, _portsCOI_T_10)
wire _portsCOI_WIRE_11 : UInt<1>
connect _portsCOI_WIRE_11, _portsCOI_T_11
connect _portsCOI_WIRE_10.ready, _portsCOI_WIRE_11
wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[4]
connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[0].bits.data, out[0].d.bits.data
connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[0].bits.source, out[0].d.bits.source
connect portsDIO_filtered[0].bits.size, out[0].d.bits.size
connect portsDIO_filtered[0].bits.param, out[0].d.bits.param
connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h0))
node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T)
connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1
connect portsDIO_filtered[1].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[1].bits.data, out[0].d.bits.data
connect portsDIO_filtered[1].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[1].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[1].bits.source, out[0].d.bits.source
connect portsDIO_filtered[1].bits.size, out[0].d.bits.size
connect portsDIO_filtered[1].bits.param, out[0].d.bits.param
connect portsDIO_filtered[1].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_1_valid_T = or(requestDOI_0_1, UInt<1>(0h0))
node _portsDIO_filtered_1_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_1_valid_T)
connect portsDIO_filtered[1].valid, _portsDIO_filtered_1_valid_T_1
connect portsDIO_filtered[2].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[2].bits.data, out[0].d.bits.data
connect portsDIO_filtered[2].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[2].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[2].bits.source, out[0].d.bits.source
connect portsDIO_filtered[2].bits.size, out[0].d.bits.size
connect portsDIO_filtered[2].bits.param, out[0].d.bits.param
connect portsDIO_filtered[2].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_2_valid_T = or(requestDOI_0_2, UInt<1>(0h0))
node _portsDIO_filtered_2_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_2_valid_T)
connect portsDIO_filtered[2].valid, _portsDIO_filtered_2_valid_T_1
connect portsDIO_filtered[3].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[3].bits.data, out[0].d.bits.data
connect portsDIO_filtered[3].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[3].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[3].bits.source, out[0].d.bits.source
connect portsDIO_filtered[3].bits.size, out[0].d.bits.size
connect portsDIO_filtered[3].bits.param, out[0].d.bits.param
connect portsDIO_filtered[3].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_3_valid_T = or(requestDOI_0_3, UInt<1>(0h0))
node _portsDIO_filtered_3_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_3_valid_T)
connect portsDIO_filtered[3].valid, _portsDIO_filtered_3_valid_T_1
node _portsDIO_out_0_d_ready_T = mux(requestDOI_0_0, portsDIO_filtered[0].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_1 = mux(requestDOI_0_1, portsDIO_filtered[1].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_2 = mux(requestDOI_0_2, portsDIO_filtered[2].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_3 = mux(requestDOI_0_3, portsDIO_filtered[3].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_4 = or(_portsDIO_out_0_d_ready_T, _portsDIO_out_0_d_ready_T_1)
node _portsDIO_out_0_d_ready_T_5 = or(_portsDIO_out_0_d_ready_T_4, _portsDIO_out_0_d_ready_T_2)
node _portsDIO_out_0_d_ready_T_6 = or(_portsDIO_out_0_d_ready_T_5, _portsDIO_out_0_d_ready_T_3)
wire _portsDIO_out_0_d_ready_WIRE : UInt<1>
connect _portsDIO_out_0_d_ready_WIRE, _portsDIO_out_0_d_ready_T_6
connect out[0].d.ready, _portsDIO_out_0_d_ready_WIRE
wire portsDIO_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}[4]
connect portsDIO_filtered_1[0].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[0].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[0].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[0].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[0].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[0].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[0].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[0].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_0_valid_T_2 = or(requestDOI_1_0, UInt<1>(0h0))
node _portsDIO_filtered_0_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_0_valid_T_2)
connect portsDIO_filtered_1[0].valid, _portsDIO_filtered_0_valid_T_3
connect portsDIO_filtered_1[1].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[1].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[1].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[1].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[1].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[1].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[1].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[1].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_1_valid_T_2 = or(requestDOI_1_1, UInt<1>(0h0))
node _portsDIO_filtered_1_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_1_valid_T_2)
connect portsDIO_filtered_1[1].valid, _portsDIO_filtered_1_valid_T_3
connect portsDIO_filtered_1[2].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[2].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[2].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[2].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[2].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[2].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[2].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[2].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_2_valid_T_2 = or(requestDOI_1_2, UInt<1>(0h0))
node _portsDIO_filtered_2_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_2_valid_T_2)
connect portsDIO_filtered_1[2].valid, _portsDIO_filtered_2_valid_T_3
connect portsDIO_filtered_1[3].bits.corrupt, out[1].d.bits.corrupt
connect portsDIO_filtered_1[3].bits.data, out[1].d.bits.data
connect portsDIO_filtered_1[3].bits.denied, out[1].d.bits.denied
connect portsDIO_filtered_1[3].bits.sink, out[1].d.bits.sink
connect portsDIO_filtered_1[3].bits.source, out[1].d.bits.source
connect portsDIO_filtered_1[3].bits.size, out[1].d.bits.size
connect portsDIO_filtered_1[3].bits.param, out[1].d.bits.param
connect portsDIO_filtered_1[3].bits.opcode, out[1].d.bits.opcode
node _portsDIO_filtered_3_valid_T_2 = or(requestDOI_1_3, UInt<1>(0h0))
node _portsDIO_filtered_3_valid_T_3 = and(out[1].d.valid, _portsDIO_filtered_3_valid_T_2)
connect portsDIO_filtered_1[3].valid, _portsDIO_filtered_3_valid_T_3
node _portsDIO_out_1_d_ready_T = mux(requestDOI_1_0, portsDIO_filtered_1[0].ready, UInt<1>(0h0))
node _portsDIO_out_1_d_ready_T_1 = mux(requestDOI_1_1, portsDIO_filtered_1[1].ready, UInt<1>(0h0))
node _portsDIO_out_1_d_ready_T_2 = mux(requestDOI_1_2, portsDIO_filtered_1[2].ready, UInt<1>(0h0))
node _portsDIO_out_1_d_ready_T_3 = mux(requestDOI_1_3, portsDIO_filtered_1[3].ready, UInt<1>(0h0))
node _portsDIO_out_1_d_ready_T_4 = or(_portsDIO_out_1_d_ready_T, _portsDIO_out_1_d_ready_T_1)
node _portsDIO_out_1_d_ready_T_5 = or(_portsDIO_out_1_d_ready_T_4, _portsDIO_out_1_d_ready_T_2)
node _portsDIO_out_1_d_ready_T_6 = or(_portsDIO_out_1_d_ready_T_5, _portsDIO_out_1_d_ready_T_3)
wire _portsDIO_out_1_d_ready_WIRE : UInt<1>
connect _portsDIO_out_1_d_ready_WIRE, _portsDIO_out_1_d_ready_T_6
connect out[1].d.ready, _portsDIO_out_1_d_ready_WIRE
wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE.bits.sink, UInt<1>(0h0)
connect _portsEOI_WIRE.valid, UInt<1>(0h0)
connect _portsEOI_WIRE.ready, UInt<1>(0h0)
wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits
connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid
connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready
wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[2]
connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits
node _portsEOI_filtered_0_valid_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T)
connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1
connect portsEOI_filtered[1].bits, _portsEOI_WIRE_1.bits
node _portsEOI_filtered_1_valid_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_1_valid_T)
connect portsEOI_filtered[1].valid, _portsEOI_filtered_1_valid_T_1
node _portsEOI_T = mux(UInt<1>(0h0), portsEOI_filtered[0].ready, UInt<1>(0h0))
node _portsEOI_T_1 = mux(UInt<1>(0h0), portsEOI_filtered[1].ready, UInt<1>(0h0))
node _portsEOI_T_2 = or(_portsEOI_T, _portsEOI_T_1)
wire _portsEOI_WIRE_2 : UInt<1>
connect _portsEOI_WIRE_2, _portsEOI_T_2
connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE_2
wire _portsEOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE_3.bits.sink, UInt<1>(0h0)
connect _portsEOI_WIRE_3.valid, UInt<1>(0h0)
connect _portsEOI_WIRE_3.ready, UInt<1>(0h0)
wire _portsEOI_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE_4.bits, _portsEOI_WIRE_3.bits
connect _portsEOI_WIRE_4.valid, _portsEOI_WIRE_3.valid
connect _portsEOI_WIRE_4.ready, _portsEOI_WIRE_3.ready
wire portsEOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[2]
connect portsEOI_filtered_1[0].bits, _portsEOI_WIRE_4.bits
node _portsEOI_filtered_0_valid_T_2 = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_3 = and(_portsEOI_WIRE_4.valid, _portsEOI_filtered_0_valid_T_2)
connect portsEOI_filtered_1[0].valid, _portsEOI_filtered_0_valid_T_3
connect portsEOI_filtered_1[1].bits, _portsEOI_WIRE_4.bits
node _portsEOI_filtered_1_valid_T_2 = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_3 = and(_portsEOI_WIRE_4.valid, _portsEOI_filtered_1_valid_T_2)
connect portsEOI_filtered_1[1].valid, _portsEOI_filtered_1_valid_T_3
node _portsEOI_T_3 = mux(UInt<1>(0h0), portsEOI_filtered_1[0].ready, UInt<1>(0h0))
node _portsEOI_T_4 = mux(UInt<1>(0h0), portsEOI_filtered_1[1].ready, UInt<1>(0h0))
node _portsEOI_T_5 = or(_portsEOI_T_3, _portsEOI_T_4)
wire _portsEOI_WIRE_5 : UInt<1>
connect _portsEOI_WIRE_5, _portsEOI_T_5
connect _portsEOI_WIRE_4.ready, _portsEOI_WIRE_5
wire _portsEOI_WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE_6.bits.sink, UInt<1>(0h0)
connect _portsEOI_WIRE_6.valid, UInt<1>(0h0)
connect _portsEOI_WIRE_6.ready, UInt<1>(0h0)
wire _portsEOI_WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE_7.bits, _portsEOI_WIRE_6.bits
connect _portsEOI_WIRE_7.valid, _portsEOI_WIRE_6.valid
connect _portsEOI_WIRE_7.ready, _portsEOI_WIRE_6.ready
wire portsEOI_filtered_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[2]
connect portsEOI_filtered_2[0].bits, _portsEOI_WIRE_7.bits
node _portsEOI_filtered_0_valid_T_4 = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_5 = and(_portsEOI_WIRE_7.valid, _portsEOI_filtered_0_valid_T_4)
connect portsEOI_filtered_2[0].valid, _portsEOI_filtered_0_valid_T_5
connect portsEOI_filtered_2[1].bits, _portsEOI_WIRE_7.bits
node _portsEOI_filtered_1_valid_T_4 = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_5 = and(_portsEOI_WIRE_7.valid, _portsEOI_filtered_1_valid_T_4)
connect portsEOI_filtered_2[1].valid, _portsEOI_filtered_1_valid_T_5
node _portsEOI_T_6 = mux(UInt<1>(0h0), portsEOI_filtered_2[0].ready, UInt<1>(0h0))
node _portsEOI_T_7 = mux(UInt<1>(0h0), portsEOI_filtered_2[1].ready, UInt<1>(0h0))
node _portsEOI_T_8 = or(_portsEOI_T_6, _portsEOI_T_7)
wire _portsEOI_WIRE_8 : UInt<1>
connect _portsEOI_WIRE_8, _portsEOI_T_8
connect _portsEOI_WIRE_7.ready, _portsEOI_WIRE_8
wire _portsEOI_WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE_9.bits.sink, UInt<1>(0h0)
connect _portsEOI_WIRE_9.valid, UInt<1>(0h0)
connect _portsEOI_WIRE_9.ready, UInt<1>(0h0)
wire _portsEOI_WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _portsEOI_WIRE_10.bits, _portsEOI_WIRE_9.bits
connect _portsEOI_WIRE_10.valid, _portsEOI_WIRE_9.valid
connect _portsEOI_WIRE_10.ready, _portsEOI_WIRE_9.ready
wire portsEOI_filtered_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}[2]
connect portsEOI_filtered_3[0].bits, _portsEOI_WIRE_10.bits
node _portsEOI_filtered_0_valid_T_6 = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_0_valid_T_7 = and(_portsEOI_WIRE_10.valid, _portsEOI_filtered_0_valid_T_6)
connect portsEOI_filtered_3[0].valid, _portsEOI_filtered_0_valid_T_7
connect portsEOI_filtered_3[1].bits, _portsEOI_WIRE_10.bits
node _portsEOI_filtered_1_valid_T_6 = or(UInt<1>(0h0), UInt<1>(0h0))
node _portsEOI_filtered_1_valid_T_7 = and(_portsEOI_WIRE_10.valid, _portsEOI_filtered_1_valid_T_6)
connect portsEOI_filtered_3[1].valid, _portsEOI_filtered_1_valid_T_7
node _portsEOI_T_9 = mux(UInt<1>(0h0), portsEOI_filtered_3[0].ready, UInt<1>(0h0))
node _portsEOI_T_10 = mux(UInt<1>(0h0), portsEOI_filtered_3[1].ready, UInt<1>(0h0))
node _portsEOI_T_11 = or(_portsEOI_T_9, _portsEOI_T_10)
wire _portsEOI_WIRE_11 : UInt<1>
connect _portsEOI_WIRE_11, _portsEOI_T_11
connect _portsEOI_WIRE_10.ready, _portsEOI_WIRE_11
regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0)
node idle = eq(beatsLeft, UInt<1>(0h0))
node latch = and(idle, out[0].a.ready)
node readys_lo = cat(portsAOI_filtered_1[0].valid, portsAOI_filtered[0].valid)
node readys_hi = cat(portsAOI_filtered_3[0].valid, portsAOI_filtered_2[0].valid)
node _readys_T = cat(readys_hi, readys_lo)
node readys_valid = bits(_readys_T, 3, 0)
node _readys_T_1 = eq(readys_valid, _readys_T)
node _readys_T_2 = asUInt(reset)
node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0))
when _readys_T_3 :
node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0))
when _readys_T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf
assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert
regreset readys_mask : UInt<4>, clock, reset, UInt<4>(0hf)
node _readys_filter_T = not(readys_mask)
node _readys_filter_T_1 = and(readys_valid, _readys_filter_T)
node readys_filter = cat(_readys_filter_T_1, readys_valid)
node _readys_unready_T = shr(readys_filter, 1)
node _readys_unready_T_1 = or(readys_filter, _readys_unready_T)
node _readys_unready_T_2 = shr(_readys_unready_T_1, 2)
node _readys_unready_T_3 = or(_readys_unready_T_1, _readys_unready_T_2)
node _readys_unready_T_4 = bits(_readys_unready_T_3, 7, 0)
node _readys_unready_T_5 = shr(_readys_unready_T_4, 1)
node _readys_unready_T_6 = shl(readys_mask, 4)
node readys_unready = or(_readys_unready_T_5, _readys_unready_T_6)
node _readys_readys_T = shr(readys_unready, 4)
node _readys_readys_T_1 = bits(readys_unready, 3, 0)
node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1)
node readys_readys = not(_readys_readys_T_2)
node _readys_T_5 = orr(readys_valid)
node _readys_T_6 = and(latch, _readys_T_5)
when _readys_T_6 :
node _readys_mask_T = and(readys_readys, readys_valid)
node _readys_mask_T_1 = shl(_readys_mask_T, 1)
node _readys_mask_T_2 = bits(_readys_mask_T_1, 3, 0)
node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2)
node _readys_mask_T_4 = shl(_readys_mask_T_3, 2)
node _readys_mask_T_5 = bits(_readys_mask_T_4, 3, 0)
node _readys_mask_T_6 = or(_readys_mask_T_3, _readys_mask_T_5)
node _readys_mask_T_7 = bits(_readys_mask_T_6, 3, 0)
connect readys_mask, _readys_mask_T_7
node _readys_T_7 = bits(readys_readys, 3, 0)
node _readys_T_8 = bits(_readys_T_7, 0, 0)
node _readys_T_9 = bits(_readys_T_7, 1, 1)
node _readys_T_10 = bits(_readys_T_7, 2, 2)
node _readys_T_11 = bits(_readys_T_7, 3, 3)
wire readys : UInt<1>[4]
connect readys[0], _readys_T_8
connect readys[1], _readys_T_9
connect readys[2], _readys_T_10
connect readys[3], _readys_T_11
node _winner_T = and(readys[0], portsAOI_filtered[0].valid)
node _winner_T_1 = and(readys[1], portsAOI_filtered_1[0].valid)
node _winner_T_2 = and(readys[2], portsAOI_filtered_2[0].valid)
node _winner_T_3 = and(readys[3], portsAOI_filtered_3[0].valid)
wire winner : UInt<1>[4]
connect winner[0], _winner_T
connect winner[1], _winner_T_1
connect winner[2], _winner_T_2
connect winner[3], _winner_T_3
node prefixOR_1 = or(UInt<1>(0h0), winner[0])
node prefixOR_2 = or(prefixOR_1, winner[1])
node prefixOR_3 = or(prefixOR_2, winner[2])
node _prefixOR_T = or(prefixOR_3, winner[3])
node _T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_1 = eq(winner[0], UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
node _T_3 = eq(prefixOR_1, UInt<1>(0h0))
node _T_4 = eq(winner[1], UInt<1>(0h0))
node _T_5 = or(_T_3, _T_4)
node _T_6 = eq(prefixOR_2, UInt<1>(0h0))
node _T_7 = eq(winner[2], UInt<1>(0h0))
node _T_8 = or(_T_6, _T_7)
node _T_9 = eq(prefixOR_3, UInt<1>(0h0))
node _T_10 = eq(winner[3], UInt<1>(0h0))
node _T_11 = or(_T_9, _T_10)
node _T_12 = and(_T_2, _T_5)
node _T_13 = and(_T_12, _T_8)
node _T_14 = and(_T_13, _T_11)
node _T_15 = asUInt(reset)
node _T_16 = eq(_T_15, UInt<1>(0h0))
when _T_16 :
node _T_17 = eq(_T_14, UInt<1>(0h0))
when _T_17 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf
assert(clock, _T_14, UInt<1>(0h1), "") : assert
node _T_18 = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid)
node _T_19 = or(_T_18, portsAOI_filtered_2[0].valid)
node _T_20 = or(_T_19, portsAOI_filtered_3[0].valid)
node _T_21 = eq(_T_20, UInt<1>(0h0))
node _T_22 = or(winner[0], winner[1])
node _T_23 = or(_T_22, winner[2])
node _T_24 = or(_T_23, winner[3])
node _T_25 = or(_T_21, _T_24)
node _T_26 = asUInt(reset)
node _T_27 = eq(_T_26, UInt<1>(0h0))
when _T_27 :
node _T_28 = eq(_T_25, UInt<1>(0h0))
when _T_28 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1
assert(clock, _T_25, UInt<1>(0h1), "") : assert_1
node maskedBeats_0 = mux(winner[0], beatsAI_0, UInt<1>(0h0))
node maskedBeats_1 = mux(winner[1], beatsAI_1, UInt<1>(0h0))
node maskedBeats_2 = mux(winner[2], beatsAI_2, UInt<1>(0h0))
node maskedBeats_3 = mux(winner[3], beatsAI_3, UInt<1>(0h0))
node _initBeats_T = or(maskedBeats_0, maskedBeats_1)
node _initBeats_T_1 = or(_initBeats_T, maskedBeats_2)
node initBeats = or(_initBeats_T_1, maskedBeats_3)
node _beatsLeft_T = and(out[0].a.ready, out[0].a.valid)
node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T)
node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1)
node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2)
connect beatsLeft, _beatsLeft_T_3
wire _state_WIRE : UInt<1>[4]
connect _state_WIRE[0], UInt<1>(0h0)
connect _state_WIRE[1], UInt<1>(0h0)
connect _state_WIRE[2], UInt<1>(0h0)
connect _state_WIRE[3], UInt<1>(0h0)
regreset state : UInt<1>[4], clock, reset, _state_WIRE
node muxState = mux(idle, winner, state)
connect state, muxState
node allowed = mux(idle, readys, state)
node _filtered_0_ready_T = and(out[0].a.ready, allowed[0])
connect portsAOI_filtered[0].ready, _filtered_0_ready_T
node _filtered_0_ready_T_1 = and(out[0].a.ready, allowed[1])
connect portsAOI_filtered_1[0].ready, _filtered_0_ready_T_1
node _filtered_0_ready_T_2 = and(out[0].a.ready, allowed[2])
connect portsAOI_filtered_2[0].ready, _filtered_0_ready_T_2
node _filtered_0_ready_T_3 = and(out[0].a.ready, allowed[3])
connect portsAOI_filtered_3[0].ready, _filtered_0_ready_T_3
node _out_0_a_valid_T = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid)
node _out_0_a_valid_T_1 = or(_out_0_a_valid_T, portsAOI_filtered_2[0].valid)
node _out_0_a_valid_T_2 = or(_out_0_a_valid_T_1, portsAOI_filtered_3[0].valid)
node _out_0_a_valid_T_3 = mux(state[0], portsAOI_filtered[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_4 = mux(state[1], portsAOI_filtered_1[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_5 = mux(state[2], portsAOI_filtered_2[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_6 = mux(state[3], portsAOI_filtered_3[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_7 = or(_out_0_a_valid_T_3, _out_0_a_valid_T_4)
node _out_0_a_valid_T_8 = or(_out_0_a_valid_T_7, _out_0_a_valid_T_5)
node _out_0_a_valid_T_9 = or(_out_0_a_valid_T_8, _out_0_a_valid_T_6)
wire _out_0_a_valid_WIRE : UInt<1>
connect _out_0_a_valid_WIRE, _out_0_a_valid_T_9
node _out_0_a_valid_T_10 = mux(idle, _out_0_a_valid_T_2, _out_0_a_valid_WIRE)
connect out[0].a.valid, _out_0_a_valid_T_10
wire _out_0_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _out_0_a_bits_T = mux(muxState[0], portsAOI_filtered[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_1 = mux(muxState[1], portsAOI_filtered_1[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_2 = mux(muxState[2], portsAOI_filtered_2[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_3 = mux(muxState[3], portsAOI_filtered_3[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_4 = or(_out_0_a_bits_T, _out_0_a_bits_T_1)
node _out_0_a_bits_T_5 = or(_out_0_a_bits_T_4, _out_0_a_bits_T_2)
node _out_0_a_bits_T_6 = or(_out_0_a_bits_T_5, _out_0_a_bits_T_3)
wire _out_0_a_bits_WIRE_1 : UInt<1>
connect _out_0_a_bits_WIRE_1, _out_0_a_bits_T_6
connect _out_0_a_bits_WIRE.corrupt, _out_0_a_bits_WIRE_1
node _out_0_a_bits_T_7 = mux(muxState[0], portsAOI_filtered[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_8 = mux(muxState[1], portsAOI_filtered_1[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_9 = mux(muxState[2], portsAOI_filtered_2[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_10 = mux(muxState[3], portsAOI_filtered_3[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_11 = or(_out_0_a_bits_T_7, _out_0_a_bits_T_8)
node _out_0_a_bits_T_12 = or(_out_0_a_bits_T_11, _out_0_a_bits_T_9)
node _out_0_a_bits_T_13 = or(_out_0_a_bits_T_12, _out_0_a_bits_T_10)
wire _out_0_a_bits_WIRE_2 : UInt<64>
connect _out_0_a_bits_WIRE_2, _out_0_a_bits_T_13
connect _out_0_a_bits_WIRE.data, _out_0_a_bits_WIRE_2
node _out_0_a_bits_T_14 = mux(muxState[0], portsAOI_filtered[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_15 = mux(muxState[1], portsAOI_filtered_1[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_16 = mux(muxState[2], portsAOI_filtered_2[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_17 = mux(muxState[3], portsAOI_filtered_3[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_18 = or(_out_0_a_bits_T_14, _out_0_a_bits_T_15)
node _out_0_a_bits_T_19 = or(_out_0_a_bits_T_18, _out_0_a_bits_T_16)
node _out_0_a_bits_T_20 = or(_out_0_a_bits_T_19, _out_0_a_bits_T_17)
wire _out_0_a_bits_WIRE_3 : UInt<8>
connect _out_0_a_bits_WIRE_3, _out_0_a_bits_T_20
connect _out_0_a_bits_WIRE.mask, _out_0_a_bits_WIRE_3
wire _out_0_a_bits_WIRE_4 : { }
connect _out_0_a_bits_WIRE.echo, _out_0_a_bits_WIRE_4
wire _out_0_a_bits_WIRE_5 : { }
connect _out_0_a_bits_WIRE.user, _out_0_a_bits_WIRE_5
node _out_0_a_bits_T_21 = mux(muxState[0], portsAOI_filtered[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_22 = mux(muxState[1], portsAOI_filtered_1[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_23 = mux(muxState[2], portsAOI_filtered_2[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_24 = mux(muxState[3], portsAOI_filtered_3[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_25 = or(_out_0_a_bits_T_21, _out_0_a_bits_T_22)
node _out_0_a_bits_T_26 = or(_out_0_a_bits_T_25, _out_0_a_bits_T_23)
node _out_0_a_bits_T_27 = or(_out_0_a_bits_T_26, _out_0_a_bits_T_24)
wire _out_0_a_bits_WIRE_6 : UInt<32>
connect _out_0_a_bits_WIRE_6, _out_0_a_bits_T_27
connect _out_0_a_bits_WIRE.address, _out_0_a_bits_WIRE_6
node _out_0_a_bits_T_28 = mux(muxState[0], portsAOI_filtered[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_29 = mux(muxState[1], portsAOI_filtered_1[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_30 = mux(muxState[2], portsAOI_filtered_2[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_31 = mux(muxState[3], portsAOI_filtered_3[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_32 = or(_out_0_a_bits_T_28, _out_0_a_bits_T_29)
node _out_0_a_bits_T_33 = or(_out_0_a_bits_T_32, _out_0_a_bits_T_30)
node _out_0_a_bits_T_34 = or(_out_0_a_bits_T_33, _out_0_a_bits_T_31)
wire _out_0_a_bits_WIRE_7 : UInt<7>
connect _out_0_a_bits_WIRE_7, _out_0_a_bits_T_34
connect _out_0_a_bits_WIRE.source, _out_0_a_bits_WIRE_7
node _out_0_a_bits_T_35 = mux(muxState[0], portsAOI_filtered[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_36 = mux(muxState[1], portsAOI_filtered_1[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_37 = mux(muxState[2], portsAOI_filtered_2[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_38 = mux(muxState[3], portsAOI_filtered_3[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_39 = or(_out_0_a_bits_T_35, _out_0_a_bits_T_36)
node _out_0_a_bits_T_40 = or(_out_0_a_bits_T_39, _out_0_a_bits_T_37)
node _out_0_a_bits_T_41 = or(_out_0_a_bits_T_40, _out_0_a_bits_T_38)
wire _out_0_a_bits_WIRE_8 : UInt<3>
connect _out_0_a_bits_WIRE_8, _out_0_a_bits_T_41
connect _out_0_a_bits_WIRE.size, _out_0_a_bits_WIRE_8
node _out_0_a_bits_T_42 = mux(muxState[0], portsAOI_filtered[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_43 = mux(muxState[1], portsAOI_filtered_1[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_44 = mux(muxState[2], portsAOI_filtered_2[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_45 = mux(muxState[3], portsAOI_filtered_3[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_46 = or(_out_0_a_bits_T_42, _out_0_a_bits_T_43)
node _out_0_a_bits_T_47 = or(_out_0_a_bits_T_46, _out_0_a_bits_T_44)
node _out_0_a_bits_T_48 = or(_out_0_a_bits_T_47, _out_0_a_bits_T_45)
wire _out_0_a_bits_WIRE_9 : UInt<3>
connect _out_0_a_bits_WIRE_9, _out_0_a_bits_T_48
connect _out_0_a_bits_WIRE.param, _out_0_a_bits_WIRE_9
node _out_0_a_bits_T_49 = mux(muxState[0], portsAOI_filtered[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_50 = mux(muxState[1], portsAOI_filtered_1[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_51 = mux(muxState[2], portsAOI_filtered_2[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_52 = mux(muxState[3], portsAOI_filtered_3[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_53 = or(_out_0_a_bits_T_49, _out_0_a_bits_T_50)
node _out_0_a_bits_T_54 = or(_out_0_a_bits_T_53, _out_0_a_bits_T_51)
node _out_0_a_bits_T_55 = or(_out_0_a_bits_T_54, _out_0_a_bits_T_52)
wire _out_0_a_bits_WIRE_10 : UInt<3>
connect _out_0_a_bits_WIRE_10, _out_0_a_bits_T_55
connect _out_0_a_bits_WIRE.opcode, _out_0_a_bits_WIRE_10
connect out[0].a.bits.corrupt, _out_0_a_bits_WIRE.corrupt
connect out[0].a.bits.data, _out_0_a_bits_WIRE.data
connect out[0].a.bits.mask, _out_0_a_bits_WIRE.mask
connect out[0].a.bits.address, _out_0_a_bits_WIRE.address
connect out[0].a.bits.source, _out_0_a_bits_WIRE.source
connect out[0].a.bits.size, _out_0_a_bits_WIRE.size
connect out[0].a.bits.param, _out_0_a_bits_WIRE.param
connect out[0].a.bits.opcode, _out_0_a_bits_WIRE.opcode
wire _WIRE_144 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_144.bits.corrupt, UInt<1>(0h0)
connect _WIRE_144.bits.data, UInt<64>(0h0)
connect _WIRE_144.bits.address, UInt<32>(0h0)
connect _WIRE_144.bits.source, UInt<7>(0h0)
connect _WIRE_144.bits.size, UInt<3>(0h0)
connect _WIRE_144.bits.param, UInt<3>(0h0)
connect _WIRE_144.bits.opcode, UInt<3>(0h0)
connect _WIRE_144.valid, UInt<1>(0h0)
connect _WIRE_144.ready, UInt<1>(0h0)
wire _WIRE_145 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_145.bits, _WIRE_144.bits
connect _WIRE_145.valid, _WIRE_144.valid
connect _WIRE_145.ready, _WIRE_144.ready
invalidate _WIRE_145.bits.corrupt
invalidate _WIRE_145.bits.data
invalidate _WIRE_145.bits.address
invalidate _WIRE_145.bits.source
invalidate _WIRE_145.bits.size
invalidate _WIRE_145.bits.param
invalidate _WIRE_145.bits.opcode
wire _WIRE_146 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_146.bits.sink, UInt<1>(0h0)
connect _WIRE_146.valid, UInt<1>(0h0)
connect _WIRE_146.ready, UInt<1>(0h0)
wire _WIRE_147 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_147.bits, _WIRE_146.bits
connect _WIRE_147.valid, _WIRE_146.valid
connect _WIRE_147.ready, _WIRE_146.ready
invalidate _WIRE_147.bits.sink
connect portsCOI_filtered[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_1[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_2[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_3[0].ready, UInt<1>(0h0)
connect portsEOI_filtered[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_1[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_2[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_3[0].ready, UInt<1>(0h0)
regreset beatsLeft_1 : UInt, clock, reset, UInt<1>(0h0)
node idle_1 = eq(beatsLeft_1, UInt<1>(0h0))
node latch_1 = and(idle_1, out[1].a.ready)
node readys_lo_1 = cat(portsAOI_filtered_1[1].valid, portsAOI_filtered[1].valid)
node readys_hi_1 = cat(portsAOI_filtered_3[1].valid, portsAOI_filtered_2[1].valid)
node _readys_T_12 = cat(readys_hi_1, readys_lo_1)
node readys_valid_1 = bits(_readys_T_12, 3, 0)
node _readys_T_13 = eq(readys_valid_1, _readys_T_12)
node _readys_T_14 = asUInt(reset)
node _readys_T_15 = eq(_readys_T_14, UInt<1>(0h0))
when _readys_T_15 :
node _readys_T_16 = eq(_readys_T_13, UInt<1>(0h0))
when _readys_T_16 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_1
assert(clock, _readys_T_13, UInt<1>(0h1), "") : readys_assert_1
regreset readys_mask_1 : UInt<4>, clock, reset, UInt<4>(0hf)
node _readys_filter_T_2 = not(readys_mask_1)
node _readys_filter_T_3 = and(readys_valid_1, _readys_filter_T_2)
node readys_filter_1 = cat(_readys_filter_T_3, readys_valid_1)
node _readys_unready_T_7 = shr(readys_filter_1, 1)
node _readys_unready_T_8 = or(readys_filter_1, _readys_unready_T_7)
node _readys_unready_T_9 = shr(_readys_unready_T_8, 2)
node _readys_unready_T_10 = or(_readys_unready_T_8, _readys_unready_T_9)
node _readys_unready_T_11 = bits(_readys_unready_T_10, 7, 0)
node _readys_unready_T_12 = shr(_readys_unready_T_11, 1)
node _readys_unready_T_13 = shl(readys_mask_1, 4)
node readys_unready_1 = or(_readys_unready_T_12, _readys_unready_T_13)
node _readys_readys_T_3 = shr(readys_unready_1, 4)
node _readys_readys_T_4 = bits(readys_unready_1, 3, 0)
node _readys_readys_T_5 = and(_readys_readys_T_3, _readys_readys_T_4)
node readys_readys_1 = not(_readys_readys_T_5)
node _readys_T_17 = orr(readys_valid_1)
node _readys_T_18 = and(latch_1, _readys_T_17)
when _readys_T_18 :
node _readys_mask_T_8 = and(readys_readys_1, readys_valid_1)
node _readys_mask_T_9 = shl(_readys_mask_T_8, 1)
node _readys_mask_T_10 = bits(_readys_mask_T_9, 3, 0)
node _readys_mask_T_11 = or(_readys_mask_T_8, _readys_mask_T_10)
node _readys_mask_T_12 = shl(_readys_mask_T_11, 2)
node _readys_mask_T_13 = bits(_readys_mask_T_12, 3, 0)
node _readys_mask_T_14 = or(_readys_mask_T_11, _readys_mask_T_13)
node _readys_mask_T_15 = bits(_readys_mask_T_14, 3, 0)
connect readys_mask_1, _readys_mask_T_15
node _readys_T_19 = bits(readys_readys_1, 3, 0)
node _readys_T_20 = bits(_readys_T_19, 0, 0)
node _readys_T_21 = bits(_readys_T_19, 1, 1)
node _readys_T_22 = bits(_readys_T_19, 2, 2)
node _readys_T_23 = bits(_readys_T_19, 3, 3)
wire readys_1 : UInt<1>[4]
connect readys_1[0], _readys_T_20
connect readys_1[1], _readys_T_21
connect readys_1[2], _readys_T_22
connect readys_1[3], _readys_T_23
node _winner_T_4 = and(readys_1[0], portsAOI_filtered[1].valid)
node _winner_T_5 = and(readys_1[1], portsAOI_filtered_1[1].valid)
node _winner_T_6 = and(readys_1[2], portsAOI_filtered_2[1].valid)
node _winner_T_7 = and(readys_1[3], portsAOI_filtered_3[1].valid)
wire winner_1 : UInt<1>[4]
connect winner_1[0], _winner_T_4
connect winner_1[1], _winner_T_5
connect winner_1[2], _winner_T_6
connect winner_1[3], _winner_T_7
node prefixOR_1_1 = or(UInt<1>(0h0), winner_1[0])
node prefixOR_2_1 = or(prefixOR_1_1, winner_1[1])
node prefixOR_3_1 = or(prefixOR_2_1, winner_1[2])
node _prefixOR_T_1 = or(prefixOR_3_1, winner_1[3])
node _T_29 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_30 = eq(winner_1[0], UInt<1>(0h0))
node _T_31 = or(_T_29, _T_30)
node _T_32 = eq(prefixOR_1_1, UInt<1>(0h0))
node _T_33 = eq(winner_1[1], UInt<1>(0h0))
node _T_34 = or(_T_32, _T_33)
node _T_35 = eq(prefixOR_2_1, UInt<1>(0h0))
node _T_36 = eq(winner_1[2], UInt<1>(0h0))
node _T_37 = or(_T_35, _T_36)
node _T_38 = eq(prefixOR_3_1, UInt<1>(0h0))
node _T_39 = eq(winner_1[3], UInt<1>(0h0))
node _T_40 = or(_T_38, _T_39)
node _T_41 = and(_T_31, _T_34)
node _T_42 = and(_T_41, _T_37)
node _T_43 = and(_T_42, _T_40)
node _T_44 = asUInt(reset)
node _T_45 = eq(_T_44, UInt<1>(0h0))
when _T_45 :
node _T_46 = eq(_T_43, UInt<1>(0h0))
when _T_46 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_2
assert(clock, _T_43, UInt<1>(0h1), "") : assert_2
node _T_47 = or(portsAOI_filtered[1].valid, portsAOI_filtered_1[1].valid)
node _T_48 = or(_T_47, portsAOI_filtered_2[1].valid)
node _T_49 = or(_T_48, portsAOI_filtered_3[1].valid)
node _T_50 = eq(_T_49, UInt<1>(0h0))
node _T_51 = or(winner_1[0], winner_1[1])
node _T_52 = or(_T_51, winner_1[2])
node _T_53 = or(_T_52, winner_1[3])
node _T_54 = or(_T_50, _T_53)
node _T_55 = asUInt(reset)
node _T_56 = eq(_T_55, UInt<1>(0h0))
when _T_56 :
node _T_57 = eq(_T_54, UInt<1>(0h0))
when _T_57 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_3
assert(clock, _T_54, UInt<1>(0h1), "") : assert_3
node maskedBeats_0_1 = mux(winner_1[0], beatsAI_0, UInt<1>(0h0))
node maskedBeats_1_1 = mux(winner_1[1], beatsAI_1, UInt<1>(0h0))
node maskedBeats_2_1 = mux(winner_1[2], beatsAI_2, UInt<1>(0h0))
node maskedBeats_3_1 = mux(winner_1[3], beatsAI_3, UInt<1>(0h0))
node _initBeats_T_2 = or(maskedBeats_0_1, maskedBeats_1_1)
node _initBeats_T_3 = or(_initBeats_T_2, maskedBeats_2_1)
node initBeats_1 = or(_initBeats_T_3, maskedBeats_3_1)
node _beatsLeft_T_4 = and(out[1].a.ready, out[1].a.valid)
node _beatsLeft_T_5 = sub(beatsLeft_1, _beatsLeft_T_4)
node _beatsLeft_T_6 = tail(_beatsLeft_T_5, 1)
node _beatsLeft_T_7 = mux(latch_1, initBeats_1, _beatsLeft_T_6)
connect beatsLeft_1, _beatsLeft_T_7
wire _state_WIRE_1 : UInt<1>[4]
connect _state_WIRE_1[0], UInt<1>(0h0)
connect _state_WIRE_1[1], UInt<1>(0h0)
connect _state_WIRE_1[2], UInt<1>(0h0)
connect _state_WIRE_1[3], UInt<1>(0h0)
regreset state_1 : UInt<1>[4], clock, reset, _state_WIRE_1
node muxState_1 = mux(idle_1, winner_1, state_1)
connect state_1, muxState_1
node allowed_1 = mux(idle_1, readys_1, state_1)
node _filtered_1_ready_T = and(out[1].a.ready, allowed_1[0])
connect portsAOI_filtered[1].ready, _filtered_1_ready_T
node _filtered_1_ready_T_1 = and(out[1].a.ready, allowed_1[1])
connect portsAOI_filtered_1[1].ready, _filtered_1_ready_T_1
node _filtered_1_ready_T_2 = and(out[1].a.ready, allowed_1[2])
connect portsAOI_filtered_2[1].ready, _filtered_1_ready_T_2
node _filtered_1_ready_T_3 = and(out[1].a.ready, allowed_1[3])
connect portsAOI_filtered_3[1].ready, _filtered_1_ready_T_3
node _out_1_a_valid_T = or(portsAOI_filtered[1].valid, portsAOI_filtered_1[1].valid)
node _out_1_a_valid_T_1 = or(_out_1_a_valid_T, portsAOI_filtered_2[1].valid)
node _out_1_a_valid_T_2 = or(_out_1_a_valid_T_1, portsAOI_filtered_3[1].valid)
node _out_1_a_valid_T_3 = mux(state_1[0], portsAOI_filtered[1].valid, UInt<1>(0h0))
node _out_1_a_valid_T_4 = mux(state_1[1], portsAOI_filtered_1[1].valid, UInt<1>(0h0))
node _out_1_a_valid_T_5 = mux(state_1[2], portsAOI_filtered_2[1].valid, UInt<1>(0h0))
node _out_1_a_valid_T_6 = mux(state_1[3], portsAOI_filtered_3[1].valid, UInt<1>(0h0))
node _out_1_a_valid_T_7 = or(_out_1_a_valid_T_3, _out_1_a_valid_T_4)
node _out_1_a_valid_T_8 = or(_out_1_a_valid_T_7, _out_1_a_valid_T_5)
node _out_1_a_valid_T_9 = or(_out_1_a_valid_T_8, _out_1_a_valid_T_6)
wire _out_1_a_valid_WIRE : UInt<1>
connect _out_1_a_valid_WIRE, _out_1_a_valid_T_9
node _out_1_a_valid_T_10 = mux(idle_1, _out_1_a_valid_T_2, _out_1_a_valid_WIRE)
connect out[1].a.valid, _out_1_a_valid_T_10
wire _out_1_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
node _out_1_a_bits_T = mux(muxState_1[0], portsAOI_filtered[1].bits.corrupt, UInt<1>(0h0))
node _out_1_a_bits_T_1 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.corrupt, UInt<1>(0h0))
node _out_1_a_bits_T_2 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.corrupt, UInt<1>(0h0))
node _out_1_a_bits_T_3 = mux(muxState_1[3], portsAOI_filtered_3[1].bits.corrupt, UInt<1>(0h0))
node _out_1_a_bits_T_4 = or(_out_1_a_bits_T, _out_1_a_bits_T_1)
node _out_1_a_bits_T_5 = or(_out_1_a_bits_T_4, _out_1_a_bits_T_2)
node _out_1_a_bits_T_6 = or(_out_1_a_bits_T_5, _out_1_a_bits_T_3)
wire _out_1_a_bits_WIRE_1 : UInt<1>
connect _out_1_a_bits_WIRE_1, _out_1_a_bits_T_6
connect _out_1_a_bits_WIRE.corrupt, _out_1_a_bits_WIRE_1
node _out_1_a_bits_T_7 = mux(muxState_1[0], portsAOI_filtered[1].bits.data, UInt<1>(0h0))
node _out_1_a_bits_T_8 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.data, UInt<1>(0h0))
node _out_1_a_bits_T_9 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.data, UInt<1>(0h0))
node _out_1_a_bits_T_10 = mux(muxState_1[3], portsAOI_filtered_3[1].bits.data, UInt<1>(0h0))
node _out_1_a_bits_T_11 = or(_out_1_a_bits_T_7, _out_1_a_bits_T_8)
node _out_1_a_bits_T_12 = or(_out_1_a_bits_T_11, _out_1_a_bits_T_9)
node _out_1_a_bits_T_13 = or(_out_1_a_bits_T_12, _out_1_a_bits_T_10)
wire _out_1_a_bits_WIRE_2 : UInt<64>
connect _out_1_a_bits_WIRE_2, _out_1_a_bits_T_13
connect _out_1_a_bits_WIRE.data, _out_1_a_bits_WIRE_2
node _out_1_a_bits_T_14 = mux(muxState_1[0], portsAOI_filtered[1].bits.mask, UInt<1>(0h0))
node _out_1_a_bits_T_15 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.mask, UInt<1>(0h0))
node _out_1_a_bits_T_16 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.mask, UInt<1>(0h0))
node _out_1_a_bits_T_17 = mux(muxState_1[3], portsAOI_filtered_3[1].bits.mask, UInt<1>(0h0))
node _out_1_a_bits_T_18 = or(_out_1_a_bits_T_14, _out_1_a_bits_T_15)
node _out_1_a_bits_T_19 = or(_out_1_a_bits_T_18, _out_1_a_bits_T_16)
node _out_1_a_bits_T_20 = or(_out_1_a_bits_T_19, _out_1_a_bits_T_17)
wire _out_1_a_bits_WIRE_3 : UInt<8>
connect _out_1_a_bits_WIRE_3, _out_1_a_bits_T_20
connect _out_1_a_bits_WIRE.mask, _out_1_a_bits_WIRE_3
wire _out_1_a_bits_WIRE_4 : { }
connect _out_1_a_bits_WIRE.echo, _out_1_a_bits_WIRE_4
wire _out_1_a_bits_WIRE_5 : { }
connect _out_1_a_bits_WIRE.user, _out_1_a_bits_WIRE_5
node _out_1_a_bits_T_21 = mux(muxState_1[0], portsAOI_filtered[1].bits.address, UInt<1>(0h0))
node _out_1_a_bits_T_22 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.address, UInt<1>(0h0))
node _out_1_a_bits_T_23 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.address, UInt<1>(0h0))
node _out_1_a_bits_T_24 = mux(muxState_1[3], portsAOI_filtered_3[1].bits.address, UInt<1>(0h0))
node _out_1_a_bits_T_25 = or(_out_1_a_bits_T_21, _out_1_a_bits_T_22)
node _out_1_a_bits_T_26 = or(_out_1_a_bits_T_25, _out_1_a_bits_T_23)
node _out_1_a_bits_T_27 = or(_out_1_a_bits_T_26, _out_1_a_bits_T_24)
wire _out_1_a_bits_WIRE_6 : UInt<32>
connect _out_1_a_bits_WIRE_6, _out_1_a_bits_T_27
connect _out_1_a_bits_WIRE.address, _out_1_a_bits_WIRE_6
node _out_1_a_bits_T_28 = mux(muxState_1[0], portsAOI_filtered[1].bits.source, UInt<1>(0h0))
node _out_1_a_bits_T_29 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.source, UInt<1>(0h0))
node _out_1_a_bits_T_30 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.source, UInt<1>(0h0))
node _out_1_a_bits_T_31 = mux(muxState_1[3], portsAOI_filtered_3[1].bits.source, UInt<1>(0h0))
node _out_1_a_bits_T_32 = or(_out_1_a_bits_T_28, _out_1_a_bits_T_29)
node _out_1_a_bits_T_33 = or(_out_1_a_bits_T_32, _out_1_a_bits_T_30)
node _out_1_a_bits_T_34 = or(_out_1_a_bits_T_33, _out_1_a_bits_T_31)
wire _out_1_a_bits_WIRE_7 : UInt<7>
connect _out_1_a_bits_WIRE_7, _out_1_a_bits_T_34
connect _out_1_a_bits_WIRE.source, _out_1_a_bits_WIRE_7
node _out_1_a_bits_T_35 = mux(muxState_1[0], portsAOI_filtered[1].bits.size, UInt<1>(0h0))
node _out_1_a_bits_T_36 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.size, UInt<1>(0h0))
node _out_1_a_bits_T_37 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.size, UInt<1>(0h0))
node _out_1_a_bits_T_38 = mux(muxState_1[3], portsAOI_filtered_3[1].bits.size, UInt<1>(0h0))
node _out_1_a_bits_T_39 = or(_out_1_a_bits_T_35, _out_1_a_bits_T_36)
node _out_1_a_bits_T_40 = or(_out_1_a_bits_T_39, _out_1_a_bits_T_37)
node _out_1_a_bits_T_41 = or(_out_1_a_bits_T_40, _out_1_a_bits_T_38)
wire _out_1_a_bits_WIRE_8 : UInt<3>
connect _out_1_a_bits_WIRE_8, _out_1_a_bits_T_41
connect _out_1_a_bits_WIRE.size, _out_1_a_bits_WIRE_8
node _out_1_a_bits_T_42 = mux(muxState_1[0], portsAOI_filtered[1].bits.param, UInt<1>(0h0))
node _out_1_a_bits_T_43 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.param, UInt<1>(0h0))
node _out_1_a_bits_T_44 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.param, UInt<1>(0h0))
node _out_1_a_bits_T_45 = mux(muxState_1[3], portsAOI_filtered_3[1].bits.param, UInt<1>(0h0))
node _out_1_a_bits_T_46 = or(_out_1_a_bits_T_42, _out_1_a_bits_T_43)
node _out_1_a_bits_T_47 = or(_out_1_a_bits_T_46, _out_1_a_bits_T_44)
node _out_1_a_bits_T_48 = or(_out_1_a_bits_T_47, _out_1_a_bits_T_45)
wire _out_1_a_bits_WIRE_9 : UInt<3>
connect _out_1_a_bits_WIRE_9, _out_1_a_bits_T_48
connect _out_1_a_bits_WIRE.param, _out_1_a_bits_WIRE_9
node _out_1_a_bits_T_49 = mux(muxState_1[0], portsAOI_filtered[1].bits.opcode, UInt<1>(0h0))
node _out_1_a_bits_T_50 = mux(muxState_1[1], portsAOI_filtered_1[1].bits.opcode, UInt<1>(0h0))
node _out_1_a_bits_T_51 = mux(muxState_1[2], portsAOI_filtered_2[1].bits.opcode, UInt<1>(0h0))
node _out_1_a_bits_T_52 = mux(muxState_1[3], portsAOI_filtered_3[1].bits.opcode, UInt<1>(0h0))
node _out_1_a_bits_T_53 = or(_out_1_a_bits_T_49, _out_1_a_bits_T_50)
node _out_1_a_bits_T_54 = or(_out_1_a_bits_T_53, _out_1_a_bits_T_51)
node _out_1_a_bits_T_55 = or(_out_1_a_bits_T_54, _out_1_a_bits_T_52)
wire _out_1_a_bits_WIRE_10 : UInt<3>
connect _out_1_a_bits_WIRE_10, _out_1_a_bits_T_55
connect _out_1_a_bits_WIRE.opcode, _out_1_a_bits_WIRE_10
connect out[1].a.bits.corrupt, _out_1_a_bits_WIRE.corrupt
connect out[1].a.bits.data, _out_1_a_bits_WIRE.data
connect out[1].a.bits.mask, _out_1_a_bits_WIRE.mask
connect out[1].a.bits.address, _out_1_a_bits_WIRE.address
connect out[1].a.bits.source, _out_1_a_bits_WIRE.source
connect out[1].a.bits.size, _out_1_a_bits_WIRE.size
connect out[1].a.bits.param, _out_1_a_bits_WIRE.param
connect out[1].a.bits.opcode, _out_1_a_bits_WIRE.opcode
wire _WIRE_148 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_148.bits.corrupt, UInt<1>(0h0)
connect _WIRE_148.bits.data, UInt<64>(0h0)
connect _WIRE_148.bits.address, UInt<32>(0h0)
connect _WIRE_148.bits.source, UInt<7>(0h0)
connect _WIRE_148.bits.size, UInt<3>(0h0)
connect _WIRE_148.bits.param, UInt<3>(0h0)
connect _WIRE_148.bits.opcode, UInt<3>(0h0)
connect _WIRE_148.valid, UInt<1>(0h0)
connect _WIRE_148.ready, UInt<1>(0h0)
wire _WIRE_149 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_149.bits, _WIRE_148.bits
connect _WIRE_149.valid, _WIRE_148.valid
connect _WIRE_149.ready, _WIRE_148.ready
invalidate _WIRE_149.bits.corrupt
invalidate _WIRE_149.bits.data
invalidate _WIRE_149.bits.address
invalidate _WIRE_149.bits.source
invalidate _WIRE_149.bits.size
invalidate _WIRE_149.bits.param
invalidate _WIRE_149.bits.opcode
wire _WIRE_150 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_150.bits.sink, UInt<1>(0h0)
connect _WIRE_150.valid, UInt<1>(0h0)
connect _WIRE_150.ready, UInt<1>(0h0)
wire _WIRE_151 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_151.bits, _WIRE_150.bits
connect _WIRE_151.valid, _WIRE_150.valid
connect _WIRE_151.ready, _WIRE_150.ready
invalidate _WIRE_151.bits.sink
connect portsCOI_filtered[1].ready, UInt<1>(0h0)
connect portsCOI_filtered_1[1].ready, UInt<1>(0h0)
connect portsCOI_filtered_2[1].ready, UInt<1>(0h0)
connect portsCOI_filtered_3[1].ready, UInt<1>(0h0)
connect portsEOI_filtered[1].ready, UInt<1>(0h0)
connect portsEOI_filtered_1[1].ready, UInt<1>(0h0)
connect portsEOI_filtered_2[1].ready, UInt<1>(0h0)
connect portsEOI_filtered_3[1].ready, UInt<1>(0h0)
wire _WIRE_152 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_152.bits.corrupt, UInt<1>(0h0)
connect _WIRE_152.bits.data, UInt<64>(0h0)
connect _WIRE_152.bits.mask, UInt<8>(0h0)
connect _WIRE_152.bits.address, UInt<32>(0h0)
connect _WIRE_152.bits.source, UInt<7>(0h0)
connect _WIRE_152.bits.size, UInt<3>(0h0)
connect _WIRE_152.bits.param, UInt<2>(0h0)
connect _WIRE_152.bits.opcode, UInt<3>(0h0)
connect _WIRE_152.valid, UInt<1>(0h0)
connect _WIRE_152.ready, UInt<1>(0h0)
wire _WIRE_153 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_153.bits, _WIRE_152.bits
connect _WIRE_153.valid, _WIRE_152.valid
connect _WIRE_153.ready, _WIRE_152.ready
invalidate _WIRE_153.bits.corrupt
invalidate _WIRE_153.bits.data
invalidate _WIRE_153.bits.mask
invalidate _WIRE_153.bits.address
invalidate _WIRE_153.bits.source
invalidate _WIRE_153.bits.size
invalidate _WIRE_153.bits.param
invalidate _WIRE_153.bits.opcode
regreset beatsLeft_2 : UInt, clock, reset, UInt<1>(0h0)
node idle_2 = eq(beatsLeft_2, UInt<1>(0h0))
node latch_2 = and(idle_2, in[0].d.ready)
node _readys_T_24 = cat(portsDIO_filtered_1[0].valid, portsDIO_filtered[0].valid)
node readys_valid_2 = bits(_readys_T_24, 1, 0)
node _readys_T_25 = eq(readys_valid_2, _readys_T_24)
node _readys_T_26 = asUInt(reset)
node _readys_T_27 = eq(_readys_T_26, UInt<1>(0h0))
when _readys_T_27 :
node _readys_T_28 = eq(_readys_T_25, UInt<1>(0h0))
when _readys_T_28 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_2
assert(clock, _readys_T_25, UInt<1>(0h1), "") : readys_assert_2
regreset readys_mask_2 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_4 = not(readys_mask_2)
node _readys_filter_T_5 = and(readys_valid_2, _readys_filter_T_4)
node readys_filter_2 = cat(_readys_filter_T_5, readys_valid_2)
node _readys_unready_T_14 = shr(readys_filter_2, 1)
node _readys_unready_T_15 = or(readys_filter_2, _readys_unready_T_14)
node _readys_unready_T_16 = bits(_readys_unready_T_15, 3, 0)
node _readys_unready_T_17 = shr(_readys_unready_T_16, 1)
node _readys_unready_T_18 = shl(readys_mask_2, 2)
node readys_unready_2 = or(_readys_unready_T_17, _readys_unready_T_18)
node _readys_readys_T_6 = shr(readys_unready_2, 2)
node _readys_readys_T_7 = bits(readys_unready_2, 1, 0)
node _readys_readys_T_8 = and(_readys_readys_T_6, _readys_readys_T_7)
node readys_readys_2 = not(_readys_readys_T_8)
node _readys_T_29 = orr(readys_valid_2)
node _readys_T_30 = and(latch_2, _readys_T_29)
when _readys_T_30 :
node _readys_mask_T_16 = and(readys_readys_2, readys_valid_2)
node _readys_mask_T_17 = shl(_readys_mask_T_16, 1)
node _readys_mask_T_18 = bits(_readys_mask_T_17, 1, 0)
node _readys_mask_T_19 = or(_readys_mask_T_16, _readys_mask_T_18)
node _readys_mask_T_20 = bits(_readys_mask_T_19, 1, 0)
connect readys_mask_2, _readys_mask_T_20
node _readys_T_31 = bits(readys_readys_2, 1, 0)
node _readys_T_32 = bits(_readys_T_31, 0, 0)
node _readys_T_33 = bits(_readys_T_31, 1, 1)
wire readys_2 : UInt<1>[2]
connect readys_2[0], _readys_T_32
connect readys_2[1], _readys_T_33
node _winner_T_8 = and(readys_2[0], portsDIO_filtered[0].valid)
node _winner_T_9 = and(readys_2[1], portsDIO_filtered_1[0].valid)
wire winner_2 : UInt<1>[2]
connect winner_2[0], _winner_T_8
connect winner_2[1], _winner_T_9
node prefixOR_1_2 = or(UInt<1>(0h0), winner_2[0])
node _prefixOR_T_2 = or(prefixOR_1_2, winner_2[1])
node _T_58 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_59 = eq(winner_2[0], UInt<1>(0h0))
node _T_60 = or(_T_58, _T_59)
node _T_61 = eq(prefixOR_1_2, UInt<1>(0h0))
node _T_62 = eq(winner_2[1], UInt<1>(0h0))
node _T_63 = or(_T_61, _T_62)
node _T_64 = and(_T_60, _T_63)
node _T_65 = asUInt(reset)
node _T_66 = eq(_T_65, UInt<1>(0h0))
when _T_66 :
node _T_67 = eq(_T_64, UInt<1>(0h0))
when _T_67 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_4
assert(clock, _T_64, UInt<1>(0h1), "") : assert_4
node _T_68 = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid)
node _T_69 = eq(_T_68, UInt<1>(0h0))
node _T_70 = or(winner_2[0], winner_2[1])
node _T_71 = or(_T_69, _T_70)
node _T_72 = asUInt(reset)
node _T_73 = eq(_T_72, UInt<1>(0h0))
when _T_73 :
node _T_74 = eq(_T_71, UInt<1>(0h0))
when _T_74 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_5
assert(clock, _T_71, UInt<1>(0h1), "") : assert_5
node maskedBeats_0_2 = mux(winner_2[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1_2 = mux(winner_2[1], beatsDO_1, UInt<1>(0h0))
node initBeats_2 = or(maskedBeats_0_2, maskedBeats_1_2)
node _beatsLeft_T_8 = and(in[0].d.ready, in[0].d.valid)
node _beatsLeft_T_9 = sub(beatsLeft_2, _beatsLeft_T_8)
node _beatsLeft_T_10 = tail(_beatsLeft_T_9, 1)
node _beatsLeft_T_11 = mux(latch_2, initBeats_2, _beatsLeft_T_10)
connect beatsLeft_2, _beatsLeft_T_11
wire _state_WIRE_2 : UInt<1>[2]
connect _state_WIRE_2[0], UInt<1>(0h0)
connect _state_WIRE_2[1], UInt<1>(0h0)
regreset state_2 : UInt<1>[2], clock, reset, _state_WIRE_2
node muxState_2 = mux(idle_2, winner_2, state_2)
connect state_2, muxState_2
node allowed_2 = mux(idle_2, readys_2, state_2)
node _filtered_0_ready_T_4 = and(in[0].d.ready, allowed_2[0])
connect portsDIO_filtered[0].ready, _filtered_0_ready_T_4
node _filtered_0_ready_T_5 = and(in[0].d.ready, allowed_2[1])
connect portsDIO_filtered_1[0].ready, _filtered_0_ready_T_5
node _in_0_d_valid_T = or(portsDIO_filtered[0].valid, portsDIO_filtered_1[0].valid)
node _in_0_d_valid_T_1 = mux(state_2[0], portsDIO_filtered[0].valid, UInt<1>(0h0))
node _in_0_d_valid_T_2 = mux(state_2[1], portsDIO_filtered_1[0].valid, UInt<1>(0h0))
node _in_0_d_valid_T_3 = or(_in_0_d_valid_T_1, _in_0_d_valid_T_2)
wire _in_0_d_valid_WIRE : UInt<1>
connect _in_0_d_valid_WIRE, _in_0_d_valid_T_3
node _in_0_d_valid_T_4 = mux(idle_2, _in_0_d_valid_T, _in_0_d_valid_WIRE)
connect in[0].d.valid, _in_0_d_valid_T_4
wire _in_0_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_0_d_bits_T = mux(muxState_2[0], portsDIO_filtered[0].bits.corrupt, UInt<1>(0h0))
node _in_0_d_bits_T_1 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.corrupt, UInt<1>(0h0))
node _in_0_d_bits_T_2 = or(_in_0_d_bits_T, _in_0_d_bits_T_1)
wire _in_0_d_bits_WIRE_1 : UInt<1>
connect _in_0_d_bits_WIRE_1, _in_0_d_bits_T_2
connect _in_0_d_bits_WIRE.corrupt, _in_0_d_bits_WIRE_1
node _in_0_d_bits_T_3 = mux(muxState_2[0], portsDIO_filtered[0].bits.data, UInt<1>(0h0))
node _in_0_d_bits_T_4 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.data, UInt<1>(0h0))
node _in_0_d_bits_T_5 = or(_in_0_d_bits_T_3, _in_0_d_bits_T_4)
wire _in_0_d_bits_WIRE_2 : UInt<64>
connect _in_0_d_bits_WIRE_2, _in_0_d_bits_T_5
connect _in_0_d_bits_WIRE.data, _in_0_d_bits_WIRE_2
wire _in_0_d_bits_WIRE_3 : { }
connect _in_0_d_bits_WIRE.echo, _in_0_d_bits_WIRE_3
wire _in_0_d_bits_WIRE_4 : { }
connect _in_0_d_bits_WIRE.user, _in_0_d_bits_WIRE_4
node _in_0_d_bits_T_6 = mux(muxState_2[0], portsDIO_filtered[0].bits.denied, UInt<1>(0h0))
node _in_0_d_bits_T_7 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.denied, UInt<1>(0h0))
node _in_0_d_bits_T_8 = or(_in_0_d_bits_T_6, _in_0_d_bits_T_7)
wire _in_0_d_bits_WIRE_5 : UInt<1>
connect _in_0_d_bits_WIRE_5, _in_0_d_bits_T_8
connect _in_0_d_bits_WIRE.denied, _in_0_d_bits_WIRE_5
node _in_0_d_bits_T_9 = mux(muxState_2[0], portsDIO_filtered[0].bits.sink, UInt<1>(0h0))
node _in_0_d_bits_T_10 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.sink, UInt<1>(0h0))
node _in_0_d_bits_T_11 = or(_in_0_d_bits_T_9, _in_0_d_bits_T_10)
wire _in_0_d_bits_WIRE_6 : UInt<1>
connect _in_0_d_bits_WIRE_6, _in_0_d_bits_T_11
connect _in_0_d_bits_WIRE.sink, _in_0_d_bits_WIRE_6
node _in_0_d_bits_T_12 = mux(muxState_2[0], portsDIO_filtered[0].bits.source, UInt<1>(0h0))
node _in_0_d_bits_T_13 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.source, UInt<1>(0h0))
node _in_0_d_bits_T_14 = or(_in_0_d_bits_T_12, _in_0_d_bits_T_13)
wire _in_0_d_bits_WIRE_7 : UInt<7>
connect _in_0_d_bits_WIRE_7, _in_0_d_bits_T_14
connect _in_0_d_bits_WIRE.source, _in_0_d_bits_WIRE_7
node _in_0_d_bits_T_15 = mux(muxState_2[0], portsDIO_filtered[0].bits.size, UInt<1>(0h0))
node _in_0_d_bits_T_16 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.size, UInt<1>(0h0))
node _in_0_d_bits_T_17 = or(_in_0_d_bits_T_15, _in_0_d_bits_T_16)
wire _in_0_d_bits_WIRE_8 : UInt<3>
connect _in_0_d_bits_WIRE_8, _in_0_d_bits_T_17
connect _in_0_d_bits_WIRE.size, _in_0_d_bits_WIRE_8
node _in_0_d_bits_T_18 = mux(muxState_2[0], portsDIO_filtered[0].bits.param, UInt<1>(0h0))
node _in_0_d_bits_T_19 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.param, UInt<1>(0h0))
node _in_0_d_bits_T_20 = or(_in_0_d_bits_T_18, _in_0_d_bits_T_19)
wire _in_0_d_bits_WIRE_9 : UInt<2>
connect _in_0_d_bits_WIRE_9, _in_0_d_bits_T_20
connect _in_0_d_bits_WIRE.param, _in_0_d_bits_WIRE_9
node _in_0_d_bits_T_21 = mux(muxState_2[0], portsDIO_filtered[0].bits.opcode, UInt<1>(0h0))
node _in_0_d_bits_T_22 = mux(muxState_2[1], portsDIO_filtered_1[0].bits.opcode, UInt<1>(0h0))
node _in_0_d_bits_T_23 = or(_in_0_d_bits_T_21, _in_0_d_bits_T_22)
wire _in_0_d_bits_WIRE_10 : UInt<3>
connect _in_0_d_bits_WIRE_10, _in_0_d_bits_T_23
connect _in_0_d_bits_WIRE.opcode, _in_0_d_bits_WIRE_10
connect in[0].d.bits.corrupt, _in_0_d_bits_WIRE.corrupt
connect in[0].d.bits.data, _in_0_d_bits_WIRE.data
connect in[0].d.bits.denied, _in_0_d_bits_WIRE.denied
connect in[0].d.bits.sink, _in_0_d_bits_WIRE.sink
connect in[0].d.bits.source, _in_0_d_bits_WIRE.source
connect in[0].d.bits.size, _in_0_d_bits_WIRE.size
connect in[0].d.bits.param, _in_0_d_bits_WIRE.param
connect in[0].d.bits.opcode, _in_0_d_bits_WIRE.opcode
connect portsBIO_filtered[0].ready, UInt<1>(0h0)
connect portsBIO_filtered_1[0].ready, UInt<1>(0h0)
wire _WIRE_154 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_154.bits.corrupt, UInt<1>(0h0)
connect _WIRE_154.bits.data, UInt<64>(0h0)
connect _WIRE_154.bits.mask, UInt<8>(0h0)
connect _WIRE_154.bits.address, UInt<32>(0h0)
connect _WIRE_154.bits.source, UInt<7>(0h0)
connect _WIRE_154.bits.size, UInt<3>(0h0)
connect _WIRE_154.bits.param, UInt<2>(0h0)
connect _WIRE_154.bits.opcode, UInt<3>(0h0)
connect _WIRE_154.valid, UInt<1>(0h0)
connect _WIRE_154.ready, UInt<1>(0h0)
wire _WIRE_155 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_155.bits, _WIRE_154.bits
connect _WIRE_155.valid, _WIRE_154.valid
connect _WIRE_155.ready, _WIRE_154.ready
invalidate _WIRE_155.bits.corrupt
invalidate _WIRE_155.bits.data
invalidate _WIRE_155.bits.mask
invalidate _WIRE_155.bits.address
invalidate _WIRE_155.bits.source
invalidate _WIRE_155.bits.size
invalidate _WIRE_155.bits.param
invalidate _WIRE_155.bits.opcode
regreset beatsLeft_3 : UInt, clock, reset, UInt<1>(0h0)
node idle_3 = eq(beatsLeft_3, UInt<1>(0h0))
node latch_3 = and(idle_3, in[1].d.ready)
node _readys_T_34 = cat(portsDIO_filtered_1[1].valid, portsDIO_filtered[1].valid)
node readys_valid_3 = bits(_readys_T_34, 1, 0)
node _readys_T_35 = eq(readys_valid_3, _readys_T_34)
node _readys_T_36 = asUInt(reset)
node _readys_T_37 = eq(_readys_T_36, UInt<1>(0h0))
when _readys_T_37 :
node _readys_T_38 = eq(_readys_T_35, UInt<1>(0h0))
when _readys_T_38 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_3
assert(clock, _readys_T_35, UInt<1>(0h1), "") : readys_assert_3
regreset readys_mask_3 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_6 = not(readys_mask_3)
node _readys_filter_T_7 = and(readys_valid_3, _readys_filter_T_6)
node readys_filter_3 = cat(_readys_filter_T_7, readys_valid_3)
node _readys_unready_T_19 = shr(readys_filter_3, 1)
node _readys_unready_T_20 = or(readys_filter_3, _readys_unready_T_19)
node _readys_unready_T_21 = bits(_readys_unready_T_20, 3, 0)
node _readys_unready_T_22 = shr(_readys_unready_T_21, 1)
node _readys_unready_T_23 = shl(readys_mask_3, 2)
node readys_unready_3 = or(_readys_unready_T_22, _readys_unready_T_23)
node _readys_readys_T_9 = shr(readys_unready_3, 2)
node _readys_readys_T_10 = bits(readys_unready_3, 1, 0)
node _readys_readys_T_11 = and(_readys_readys_T_9, _readys_readys_T_10)
node readys_readys_3 = not(_readys_readys_T_11)
node _readys_T_39 = orr(readys_valid_3)
node _readys_T_40 = and(latch_3, _readys_T_39)
when _readys_T_40 :
node _readys_mask_T_21 = and(readys_readys_3, readys_valid_3)
node _readys_mask_T_22 = shl(_readys_mask_T_21, 1)
node _readys_mask_T_23 = bits(_readys_mask_T_22, 1, 0)
node _readys_mask_T_24 = or(_readys_mask_T_21, _readys_mask_T_23)
node _readys_mask_T_25 = bits(_readys_mask_T_24, 1, 0)
connect readys_mask_3, _readys_mask_T_25
node _readys_T_41 = bits(readys_readys_3, 1, 0)
node _readys_T_42 = bits(_readys_T_41, 0, 0)
node _readys_T_43 = bits(_readys_T_41, 1, 1)
wire readys_3 : UInt<1>[2]
connect readys_3[0], _readys_T_42
connect readys_3[1], _readys_T_43
node _winner_T_10 = and(readys_3[0], portsDIO_filtered[1].valid)
node _winner_T_11 = and(readys_3[1], portsDIO_filtered_1[1].valid)
wire winner_3 : UInt<1>[2]
connect winner_3[0], _winner_T_10
connect winner_3[1], _winner_T_11
node prefixOR_1_3 = or(UInt<1>(0h0), winner_3[0])
node _prefixOR_T_3 = or(prefixOR_1_3, winner_3[1])
node _T_75 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_76 = eq(winner_3[0], UInt<1>(0h0))
node _T_77 = or(_T_75, _T_76)
node _T_78 = eq(prefixOR_1_3, UInt<1>(0h0))
node _T_79 = eq(winner_3[1], UInt<1>(0h0))
node _T_80 = or(_T_78, _T_79)
node _T_81 = and(_T_77, _T_80)
node _T_82 = asUInt(reset)
node _T_83 = eq(_T_82, UInt<1>(0h0))
when _T_83 :
node _T_84 = eq(_T_81, UInt<1>(0h0))
when _T_84 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_6
assert(clock, _T_81, UInt<1>(0h1), "") : assert_6
node _T_85 = or(portsDIO_filtered[1].valid, portsDIO_filtered_1[1].valid)
node _T_86 = eq(_T_85, UInt<1>(0h0))
node _T_87 = or(winner_3[0], winner_3[1])
node _T_88 = or(_T_86, _T_87)
node _T_89 = asUInt(reset)
node _T_90 = eq(_T_89, UInt<1>(0h0))
when _T_90 :
node _T_91 = eq(_T_88, UInt<1>(0h0))
when _T_91 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_7
assert(clock, _T_88, UInt<1>(0h1), "") : assert_7
node maskedBeats_0_3 = mux(winner_3[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1_3 = mux(winner_3[1], beatsDO_1, UInt<1>(0h0))
node initBeats_3 = or(maskedBeats_0_3, maskedBeats_1_3)
node _beatsLeft_T_12 = and(in[1].d.ready, in[1].d.valid)
node _beatsLeft_T_13 = sub(beatsLeft_3, _beatsLeft_T_12)
node _beatsLeft_T_14 = tail(_beatsLeft_T_13, 1)
node _beatsLeft_T_15 = mux(latch_3, initBeats_3, _beatsLeft_T_14)
connect beatsLeft_3, _beatsLeft_T_15
wire _state_WIRE_3 : UInt<1>[2]
connect _state_WIRE_3[0], UInt<1>(0h0)
connect _state_WIRE_3[1], UInt<1>(0h0)
regreset state_3 : UInt<1>[2], clock, reset, _state_WIRE_3
node muxState_3 = mux(idle_3, winner_3, state_3)
connect state_3, muxState_3
node allowed_3 = mux(idle_3, readys_3, state_3)
node _filtered_1_ready_T_4 = and(in[1].d.ready, allowed_3[0])
connect portsDIO_filtered[1].ready, _filtered_1_ready_T_4
node _filtered_1_ready_T_5 = and(in[1].d.ready, allowed_3[1])
connect portsDIO_filtered_1[1].ready, _filtered_1_ready_T_5
node _in_1_d_valid_T = or(portsDIO_filtered[1].valid, portsDIO_filtered_1[1].valid)
node _in_1_d_valid_T_1 = mux(state_3[0], portsDIO_filtered[1].valid, UInt<1>(0h0))
node _in_1_d_valid_T_2 = mux(state_3[1], portsDIO_filtered_1[1].valid, UInt<1>(0h0))
node _in_1_d_valid_T_3 = or(_in_1_d_valid_T_1, _in_1_d_valid_T_2)
wire _in_1_d_valid_WIRE : UInt<1>
connect _in_1_d_valid_WIRE, _in_1_d_valid_T_3
node _in_1_d_valid_T_4 = mux(idle_3, _in_1_d_valid_T, _in_1_d_valid_WIRE)
connect in[1].d.valid, _in_1_d_valid_T_4
wire _in_1_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_1_d_bits_T = mux(muxState_3[0], portsDIO_filtered[1].bits.corrupt, UInt<1>(0h0))
node _in_1_d_bits_T_1 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.corrupt, UInt<1>(0h0))
node _in_1_d_bits_T_2 = or(_in_1_d_bits_T, _in_1_d_bits_T_1)
wire _in_1_d_bits_WIRE_1 : UInt<1>
connect _in_1_d_bits_WIRE_1, _in_1_d_bits_T_2
connect _in_1_d_bits_WIRE.corrupt, _in_1_d_bits_WIRE_1
node _in_1_d_bits_T_3 = mux(muxState_3[0], portsDIO_filtered[1].bits.data, UInt<1>(0h0))
node _in_1_d_bits_T_4 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.data, UInt<1>(0h0))
node _in_1_d_bits_T_5 = or(_in_1_d_bits_T_3, _in_1_d_bits_T_4)
wire _in_1_d_bits_WIRE_2 : UInt<64>
connect _in_1_d_bits_WIRE_2, _in_1_d_bits_T_5
connect _in_1_d_bits_WIRE.data, _in_1_d_bits_WIRE_2
wire _in_1_d_bits_WIRE_3 : { }
connect _in_1_d_bits_WIRE.echo, _in_1_d_bits_WIRE_3
wire _in_1_d_bits_WIRE_4 : { }
connect _in_1_d_bits_WIRE.user, _in_1_d_bits_WIRE_4
node _in_1_d_bits_T_6 = mux(muxState_3[0], portsDIO_filtered[1].bits.denied, UInt<1>(0h0))
node _in_1_d_bits_T_7 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.denied, UInt<1>(0h0))
node _in_1_d_bits_T_8 = or(_in_1_d_bits_T_6, _in_1_d_bits_T_7)
wire _in_1_d_bits_WIRE_5 : UInt<1>
connect _in_1_d_bits_WIRE_5, _in_1_d_bits_T_8
connect _in_1_d_bits_WIRE.denied, _in_1_d_bits_WIRE_5
node _in_1_d_bits_T_9 = mux(muxState_3[0], portsDIO_filtered[1].bits.sink, UInt<1>(0h0))
node _in_1_d_bits_T_10 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.sink, UInt<1>(0h0))
node _in_1_d_bits_T_11 = or(_in_1_d_bits_T_9, _in_1_d_bits_T_10)
wire _in_1_d_bits_WIRE_6 : UInt<1>
connect _in_1_d_bits_WIRE_6, _in_1_d_bits_T_11
connect _in_1_d_bits_WIRE.sink, _in_1_d_bits_WIRE_6
node _in_1_d_bits_T_12 = mux(muxState_3[0], portsDIO_filtered[1].bits.source, UInt<1>(0h0))
node _in_1_d_bits_T_13 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.source, UInt<1>(0h0))
node _in_1_d_bits_T_14 = or(_in_1_d_bits_T_12, _in_1_d_bits_T_13)
wire _in_1_d_bits_WIRE_7 : UInt<7>
connect _in_1_d_bits_WIRE_7, _in_1_d_bits_T_14
connect _in_1_d_bits_WIRE.source, _in_1_d_bits_WIRE_7
node _in_1_d_bits_T_15 = mux(muxState_3[0], portsDIO_filtered[1].bits.size, UInt<1>(0h0))
node _in_1_d_bits_T_16 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.size, UInt<1>(0h0))
node _in_1_d_bits_T_17 = or(_in_1_d_bits_T_15, _in_1_d_bits_T_16)
wire _in_1_d_bits_WIRE_8 : UInt<3>
connect _in_1_d_bits_WIRE_8, _in_1_d_bits_T_17
connect _in_1_d_bits_WIRE.size, _in_1_d_bits_WIRE_8
node _in_1_d_bits_T_18 = mux(muxState_3[0], portsDIO_filtered[1].bits.param, UInt<1>(0h0))
node _in_1_d_bits_T_19 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.param, UInt<1>(0h0))
node _in_1_d_bits_T_20 = or(_in_1_d_bits_T_18, _in_1_d_bits_T_19)
wire _in_1_d_bits_WIRE_9 : UInt<2>
connect _in_1_d_bits_WIRE_9, _in_1_d_bits_T_20
connect _in_1_d_bits_WIRE.param, _in_1_d_bits_WIRE_9
node _in_1_d_bits_T_21 = mux(muxState_3[0], portsDIO_filtered[1].bits.opcode, UInt<1>(0h0))
node _in_1_d_bits_T_22 = mux(muxState_3[1], portsDIO_filtered_1[1].bits.opcode, UInt<1>(0h0))
node _in_1_d_bits_T_23 = or(_in_1_d_bits_T_21, _in_1_d_bits_T_22)
wire _in_1_d_bits_WIRE_10 : UInt<3>
connect _in_1_d_bits_WIRE_10, _in_1_d_bits_T_23
connect _in_1_d_bits_WIRE.opcode, _in_1_d_bits_WIRE_10
connect in[1].d.bits.corrupt, _in_1_d_bits_WIRE.corrupt
connect in[1].d.bits.data, _in_1_d_bits_WIRE.data
connect in[1].d.bits.denied, _in_1_d_bits_WIRE.denied
connect in[1].d.bits.sink, _in_1_d_bits_WIRE.sink
connect in[1].d.bits.source, _in_1_d_bits_WIRE.source
connect in[1].d.bits.size, _in_1_d_bits_WIRE.size
connect in[1].d.bits.param, _in_1_d_bits_WIRE.param
connect in[1].d.bits.opcode, _in_1_d_bits_WIRE.opcode
connect portsBIO_filtered[1].ready, UInt<1>(0h0)
connect portsBIO_filtered_1[1].ready, UInt<1>(0h0)
wire _WIRE_156 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_156.bits.corrupt, UInt<1>(0h0)
connect _WIRE_156.bits.data, UInt<64>(0h0)
connect _WIRE_156.bits.mask, UInt<8>(0h0)
connect _WIRE_156.bits.address, UInt<32>(0h0)
connect _WIRE_156.bits.source, UInt<7>(0h0)
connect _WIRE_156.bits.size, UInt<3>(0h0)
connect _WIRE_156.bits.param, UInt<2>(0h0)
connect _WIRE_156.bits.opcode, UInt<3>(0h0)
connect _WIRE_156.valid, UInt<1>(0h0)
connect _WIRE_156.ready, UInt<1>(0h0)
wire _WIRE_157 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_157.bits, _WIRE_156.bits
connect _WIRE_157.valid, _WIRE_156.valid
connect _WIRE_157.ready, _WIRE_156.ready
invalidate _WIRE_157.bits.corrupt
invalidate _WIRE_157.bits.data
invalidate _WIRE_157.bits.mask
invalidate _WIRE_157.bits.address
invalidate _WIRE_157.bits.source
invalidate _WIRE_157.bits.size
invalidate _WIRE_157.bits.param
invalidate _WIRE_157.bits.opcode
regreset beatsLeft_4 : UInt, clock, reset, UInt<1>(0h0)
node idle_4 = eq(beatsLeft_4, UInt<1>(0h0))
node latch_4 = and(idle_4, in[2].d.ready)
node _readys_T_44 = cat(portsDIO_filtered_1[2].valid, portsDIO_filtered[2].valid)
node readys_valid_4 = bits(_readys_T_44, 1, 0)
node _readys_T_45 = eq(readys_valid_4, _readys_T_44)
node _readys_T_46 = asUInt(reset)
node _readys_T_47 = eq(_readys_T_46, UInt<1>(0h0))
when _readys_T_47 :
node _readys_T_48 = eq(_readys_T_45, UInt<1>(0h0))
when _readys_T_48 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_4
assert(clock, _readys_T_45, UInt<1>(0h1), "") : readys_assert_4
regreset readys_mask_4 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_8 = not(readys_mask_4)
node _readys_filter_T_9 = and(readys_valid_4, _readys_filter_T_8)
node readys_filter_4 = cat(_readys_filter_T_9, readys_valid_4)
node _readys_unready_T_24 = shr(readys_filter_4, 1)
node _readys_unready_T_25 = or(readys_filter_4, _readys_unready_T_24)
node _readys_unready_T_26 = bits(_readys_unready_T_25, 3, 0)
node _readys_unready_T_27 = shr(_readys_unready_T_26, 1)
node _readys_unready_T_28 = shl(readys_mask_4, 2)
node readys_unready_4 = or(_readys_unready_T_27, _readys_unready_T_28)
node _readys_readys_T_12 = shr(readys_unready_4, 2)
node _readys_readys_T_13 = bits(readys_unready_4, 1, 0)
node _readys_readys_T_14 = and(_readys_readys_T_12, _readys_readys_T_13)
node readys_readys_4 = not(_readys_readys_T_14)
node _readys_T_49 = orr(readys_valid_4)
node _readys_T_50 = and(latch_4, _readys_T_49)
when _readys_T_50 :
node _readys_mask_T_26 = and(readys_readys_4, readys_valid_4)
node _readys_mask_T_27 = shl(_readys_mask_T_26, 1)
node _readys_mask_T_28 = bits(_readys_mask_T_27, 1, 0)
node _readys_mask_T_29 = or(_readys_mask_T_26, _readys_mask_T_28)
node _readys_mask_T_30 = bits(_readys_mask_T_29, 1, 0)
connect readys_mask_4, _readys_mask_T_30
node _readys_T_51 = bits(readys_readys_4, 1, 0)
node _readys_T_52 = bits(_readys_T_51, 0, 0)
node _readys_T_53 = bits(_readys_T_51, 1, 1)
wire readys_4 : UInt<1>[2]
connect readys_4[0], _readys_T_52
connect readys_4[1], _readys_T_53
node _winner_T_12 = and(readys_4[0], portsDIO_filtered[2].valid)
node _winner_T_13 = and(readys_4[1], portsDIO_filtered_1[2].valid)
wire winner_4 : UInt<1>[2]
connect winner_4[0], _winner_T_12
connect winner_4[1], _winner_T_13
node prefixOR_1_4 = or(UInt<1>(0h0), winner_4[0])
node _prefixOR_T_4 = or(prefixOR_1_4, winner_4[1])
node _T_92 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_93 = eq(winner_4[0], UInt<1>(0h0))
node _T_94 = or(_T_92, _T_93)
node _T_95 = eq(prefixOR_1_4, UInt<1>(0h0))
node _T_96 = eq(winner_4[1], UInt<1>(0h0))
node _T_97 = or(_T_95, _T_96)
node _T_98 = and(_T_94, _T_97)
node _T_99 = asUInt(reset)
node _T_100 = eq(_T_99, UInt<1>(0h0))
when _T_100 :
node _T_101 = eq(_T_98, UInt<1>(0h0))
when _T_101 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_8
assert(clock, _T_98, UInt<1>(0h1), "") : assert_8
node _T_102 = or(portsDIO_filtered[2].valid, portsDIO_filtered_1[2].valid)
node _T_103 = eq(_T_102, UInt<1>(0h0))
node _T_104 = or(winner_4[0], winner_4[1])
node _T_105 = or(_T_103, _T_104)
node _T_106 = asUInt(reset)
node _T_107 = eq(_T_106, UInt<1>(0h0))
when _T_107 :
node _T_108 = eq(_T_105, UInt<1>(0h0))
when _T_108 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_9
assert(clock, _T_105, UInt<1>(0h1), "") : assert_9
node maskedBeats_0_4 = mux(winner_4[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1_4 = mux(winner_4[1], beatsDO_1, UInt<1>(0h0))
node initBeats_4 = or(maskedBeats_0_4, maskedBeats_1_4)
node _beatsLeft_T_16 = and(in[2].d.ready, in[2].d.valid)
node _beatsLeft_T_17 = sub(beatsLeft_4, _beatsLeft_T_16)
node _beatsLeft_T_18 = tail(_beatsLeft_T_17, 1)
node _beatsLeft_T_19 = mux(latch_4, initBeats_4, _beatsLeft_T_18)
connect beatsLeft_4, _beatsLeft_T_19
wire _state_WIRE_4 : UInt<1>[2]
connect _state_WIRE_4[0], UInt<1>(0h0)
connect _state_WIRE_4[1], UInt<1>(0h0)
regreset state_4 : UInt<1>[2], clock, reset, _state_WIRE_4
node muxState_4 = mux(idle_4, winner_4, state_4)
connect state_4, muxState_4
node allowed_4 = mux(idle_4, readys_4, state_4)
node _filtered_2_ready_T = and(in[2].d.ready, allowed_4[0])
connect portsDIO_filtered[2].ready, _filtered_2_ready_T
node _filtered_2_ready_T_1 = and(in[2].d.ready, allowed_4[1])
connect portsDIO_filtered_1[2].ready, _filtered_2_ready_T_1
node _in_2_d_valid_T = or(portsDIO_filtered[2].valid, portsDIO_filtered_1[2].valid)
node _in_2_d_valid_T_1 = mux(state_4[0], portsDIO_filtered[2].valid, UInt<1>(0h0))
node _in_2_d_valid_T_2 = mux(state_4[1], portsDIO_filtered_1[2].valid, UInt<1>(0h0))
node _in_2_d_valid_T_3 = or(_in_2_d_valid_T_1, _in_2_d_valid_T_2)
wire _in_2_d_valid_WIRE : UInt<1>
connect _in_2_d_valid_WIRE, _in_2_d_valid_T_3
node _in_2_d_valid_T_4 = mux(idle_4, _in_2_d_valid_T, _in_2_d_valid_WIRE)
connect in[2].d.valid, _in_2_d_valid_T_4
wire _in_2_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_2_d_bits_T = mux(muxState_4[0], portsDIO_filtered[2].bits.corrupt, UInt<1>(0h0))
node _in_2_d_bits_T_1 = mux(muxState_4[1], portsDIO_filtered_1[2].bits.corrupt, UInt<1>(0h0))
node _in_2_d_bits_T_2 = or(_in_2_d_bits_T, _in_2_d_bits_T_1)
wire _in_2_d_bits_WIRE_1 : UInt<1>
connect _in_2_d_bits_WIRE_1, _in_2_d_bits_T_2
connect _in_2_d_bits_WIRE.corrupt, _in_2_d_bits_WIRE_1
node _in_2_d_bits_T_3 = mux(muxState_4[0], portsDIO_filtered[2].bits.data, UInt<1>(0h0))
node _in_2_d_bits_T_4 = mux(muxState_4[1], portsDIO_filtered_1[2].bits.data, UInt<1>(0h0))
node _in_2_d_bits_T_5 = or(_in_2_d_bits_T_3, _in_2_d_bits_T_4)
wire _in_2_d_bits_WIRE_2 : UInt<64>
connect _in_2_d_bits_WIRE_2, _in_2_d_bits_T_5
connect _in_2_d_bits_WIRE.data, _in_2_d_bits_WIRE_2
wire _in_2_d_bits_WIRE_3 : { }
connect _in_2_d_bits_WIRE.echo, _in_2_d_bits_WIRE_3
wire _in_2_d_bits_WIRE_4 : { }
connect _in_2_d_bits_WIRE.user, _in_2_d_bits_WIRE_4
node _in_2_d_bits_T_6 = mux(muxState_4[0], portsDIO_filtered[2].bits.denied, UInt<1>(0h0))
node _in_2_d_bits_T_7 = mux(muxState_4[1], portsDIO_filtered_1[2].bits.denied, UInt<1>(0h0))
node _in_2_d_bits_T_8 = or(_in_2_d_bits_T_6, _in_2_d_bits_T_7)
wire _in_2_d_bits_WIRE_5 : UInt<1>
connect _in_2_d_bits_WIRE_5, _in_2_d_bits_T_8
connect _in_2_d_bits_WIRE.denied, _in_2_d_bits_WIRE_5
node _in_2_d_bits_T_9 = mux(muxState_4[0], portsDIO_filtered[2].bits.sink, UInt<1>(0h0))
node _in_2_d_bits_T_10 = mux(muxState_4[1], portsDIO_filtered_1[2].bits.sink, UInt<1>(0h0))
node _in_2_d_bits_T_11 = or(_in_2_d_bits_T_9, _in_2_d_bits_T_10)
wire _in_2_d_bits_WIRE_6 : UInt<1>
connect _in_2_d_bits_WIRE_6, _in_2_d_bits_T_11
connect _in_2_d_bits_WIRE.sink, _in_2_d_bits_WIRE_6
node _in_2_d_bits_T_12 = mux(muxState_4[0], portsDIO_filtered[2].bits.source, UInt<1>(0h0))
node _in_2_d_bits_T_13 = mux(muxState_4[1], portsDIO_filtered_1[2].bits.source, UInt<1>(0h0))
node _in_2_d_bits_T_14 = or(_in_2_d_bits_T_12, _in_2_d_bits_T_13)
wire _in_2_d_bits_WIRE_7 : UInt<7>
connect _in_2_d_bits_WIRE_7, _in_2_d_bits_T_14
connect _in_2_d_bits_WIRE.source, _in_2_d_bits_WIRE_7
node _in_2_d_bits_T_15 = mux(muxState_4[0], portsDIO_filtered[2].bits.size, UInt<1>(0h0))
node _in_2_d_bits_T_16 = mux(muxState_4[1], portsDIO_filtered_1[2].bits.size, UInt<1>(0h0))
node _in_2_d_bits_T_17 = or(_in_2_d_bits_T_15, _in_2_d_bits_T_16)
wire _in_2_d_bits_WIRE_8 : UInt<3>
connect _in_2_d_bits_WIRE_8, _in_2_d_bits_T_17
connect _in_2_d_bits_WIRE.size, _in_2_d_bits_WIRE_8
node _in_2_d_bits_T_18 = mux(muxState_4[0], portsDIO_filtered[2].bits.param, UInt<1>(0h0))
node _in_2_d_bits_T_19 = mux(muxState_4[1], portsDIO_filtered_1[2].bits.param, UInt<1>(0h0))
node _in_2_d_bits_T_20 = or(_in_2_d_bits_T_18, _in_2_d_bits_T_19)
wire _in_2_d_bits_WIRE_9 : UInt<2>
connect _in_2_d_bits_WIRE_9, _in_2_d_bits_T_20
connect _in_2_d_bits_WIRE.param, _in_2_d_bits_WIRE_9
node _in_2_d_bits_T_21 = mux(muxState_4[0], portsDIO_filtered[2].bits.opcode, UInt<1>(0h0))
node _in_2_d_bits_T_22 = mux(muxState_4[1], portsDIO_filtered_1[2].bits.opcode, UInt<1>(0h0))
node _in_2_d_bits_T_23 = or(_in_2_d_bits_T_21, _in_2_d_bits_T_22)
wire _in_2_d_bits_WIRE_10 : UInt<3>
connect _in_2_d_bits_WIRE_10, _in_2_d_bits_T_23
connect _in_2_d_bits_WIRE.opcode, _in_2_d_bits_WIRE_10
connect in[2].d.bits.corrupt, _in_2_d_bits_WIRE.corrupt
connect in[2].d.bits.data, _in_2_d_bits_WIRE.data
connect in[2].d.bits.denied, _in_2_d_bits_WIRE.denied
connect in[2].d.bits.sink, _in_2_d_bits_WIRE.sink
connect in[2].d.bits.source, _in_2_d_bits_WIRE.source
connect in[2].d.bits.size, _in_2_d_bits_WIRE.size
connect in[2].d.bits.param, _in_2_d_bits_WIRE.param
connect in[2].d.bits.opcode, _in_2_d_bits_WIRE.opcode
connect portsBIO_filtered[2].ready, UInt<1>(0h0)
connect portsBIO_filtered_1[2].ready, UInt<1>(0h0)
wire _WIRE_158 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_158.bits.corrupt, UInt<1>(0h0)
connect _WIRE_158.bits.data, UInt<64>(0h0)
connect _WIRE_158.bits.mask, UInt<8>(0h0)
connect _WIRE_158.bits.address, UInt<32>(0h0)
connect _WIRE_158.bits.source, UInt<7>(0h0)
connect _WIRE_158.bits.size, UInt<3>(0h0)
connect _WIRE_158.bits.param, UInt<2>(0h0)
connect _WIRE_158.bits.opcode, UInt<3>(0h0)
connect _WIRE_158.valid, UInt<1>(0h0)
connect _WIRE_158.ready, UInt<1>(0h0)
wire _WIRE_159 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_159.bits, _WIRE_158.bits
connect _WIRE_159.valid, _WIRE_158.valid
connect _WIRE_159.ready, _WIRE_158.ready
invalidate _WIRE_159.bits.corrupt
invalidate _WIRE_159.bits.data
invalidate _WIRE_159.bits.mask
invalidate _WIRE_159.bits.address
invalidate _WIRE_159.bits.source
invalidate _WIRE_159.bits.size
invalidate _WIRE_159.bits.param
invalidate _WIRE_159.bits.opcode
regreset beatsLeft_5 : UInt, clock, reset, UInt<1>(0h0)
node idle_5 = eq(beatsLeft_5, UInt<1>(0h0))
node latch_5 = and(idle_5, in[3].d.ready)
node _readys_T_54 = cat(portsDIO_filtered_1[3].valid, portsDIO_filtered[3].valid)
node readys_valid_5 = bits(_readys_T_54, 1, 0)
node _readys_T_55 = eq(readys_valid_5, _readys_T_54)
node _readys_T_56 = asUInt(reset)
node _readys_T_57 = eq(_readys_T_56, UInt<1>(0h0))
when _readys_T_57 :
node _readys_T_58 = eq(_readys_T_55, UInt<1>(0h0))
when _readys_T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf_5
assert(clock, _readys_T_55, UInt<1>(0h1), "") : readys_assert_5
regreset readys_mask_5 : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T_10 = not(readys_mask_5)
node _readys_filter_T_11 = and(readys_valid_5, _readys_filter_T_10)
node readys_filter_5 = cat(_readys_filter_T_11, readys_valid_5)
node _readys_unready_T_29 = shr(readys_filter_5, 1)
node _readys_unready_T_30 = or(readys_filter_5, _readys_unready_T_29)
node _readys_unready_T_31 = bits(_readys_unready_T_30, 3, 0)
node _readys_unready_T_32 = shr(_readys_unready_T_31, 1)
node _readys_unready_T_33 = shl(readys_mask_5, 2)
node readys_unready_5 = or(_readys_unready_T_32, _readys_unready_T_33)
node _readys_readys_T_15 = shr(readys_unready_5, 2)
node _readys_readys_T_16 = bits(readys_unready_5, 1, 0)
node _readys_readys_T_17 = and(_readys_readys_T_15, _readys_readys_T_16)
node readys_readys_5 = not(_readys_readys_T_17)
node _readys_T_59 = orr(readys_valid_5)
node _readys_T_60 = and(latch_5, _readys_T_59)
when _readys_T_60 :
node _readys_mask_T_31 = and(readys_readys_5, readys_valid_5)
node _readys_mask_T_32 = shl(_readys_mask_T_31, 1)
node _readys_mask_T_33 = bits(_readys_mask_T_32, 1, 0)
node _readys_mask_T_34 = or(_readys_mask_T_31, _readys_mask_T_33)
node _readys_mask_T_35 = bits(_readys_mask_T_34, 1, 0)
connect readys_mask_5, _readys_mask_T_35
node _readys_T_61 = bits(readys_readys_5, 1, 0)
node _readys_T_62 = bits(_readys_T_61, 0, 0)
node _readys_T_63 = bits(_readys_T_61, 1, 1)
wire readys_5 : UInt<1>[2]
connect readys_5[0], _readys_T_62
connect readys_5[1], _readys_T_63
node _winner_T_14 = and(readys_5[0], portsDIO_filtered[3].valid)
node _winner_T_15 = and(readys_5[1], portsDIO_filtered_1[3].valid)
wire winner_5 : UInt<1>[2]
connect winner_5[0], _winner_T_14
connect winner_5[1], _winner_T_15
node prefixOR_1_5 = or(UInt<1>(0h0), winner_5[0])
node _prefixOR_T_5 = or(prefixOR_1_5, winner_5[1])
node _T_109 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_110 = eq(winner_5[0], UInt<1>(0h0))
node _T_111 = or(_T_109, _T_110)
node _T_112 = eq(prefixOR_1_5, UInt<1>(0h0))
node _T_113 = eq(winner_5[1], UInt<1>(0h0))
node _T_114 = or(_T_112, _T_113)
node _T_115 = and(_T_111, _T_114)
node _T_116 = asUInt(reset)
node _T_117 = eq(_T_116, UInt<1>(0h0))
when _T_117 :
node _T_118 = eq(_T_115, UInt<1>(0h0))
when _T_118 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf_10
assert(clock, _T_115, UInt<1>(0h1), "") : assert_10
node _T_119 = or(portsDIO_filtered[3].valid, portsDIO_filtered_1[3].valid)
node _T_120 = eq(_T_119, UInt<1>(0h0))
node _T_121 = or(winner_5[0], winner_5[1])
node _T_122 = or(_T_120, _T_121)
node _T_123 = asUInt(reset)
node _T_124 = eq(_T_123, UInt<1>(0h0))
when _T_124 :
node _T_125 = eq(_T_122, UInt<1>(0h0))
when _T_125 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_11
assert(clock, _T_122, UInt<1>(0h1), "") : assert_11
node maskedBeats_0_5 = mux(winner_5[0], beatsDO_0, UInt<1>(0h0))
node maskedBeats_1_5 = mux(winner_5[1], beatsDO_1, UInt<1>(0h0))
node initBeats_5 = or(maskedBeats_0_5, maskedBeats_1_5)
node _beatsLeft_T_20 = and(in[3].d.ready, in[3].d.valid)
node _beatsLeft_T_21 = sub(beatsLeft_5, _beatsLeft_T_20)
node _beatsLeft_T_22 = tail(_beatsLeft_T_21, 1)
node _beatsLeft_T_23 = mux(latch_5, initBeats_5, _beatsLeft_T_22)
connect beatsLeft_5, _beatsLeft_T_23
wire _state_WIRE_5 : UInt<1>[2]
connect _state_WIRE_5[0], UInt<1>(0h0)
connect _state_WIRE_5[1], UInt<1>(0h0)
regreset state_5 : UInt<1>[2], clock, reset, _state_WIRE_5
node muxState_5 = mux(idle_5, winner_5, state_5)
connect state_5, muxState_5
node allowed_5 = mux(idle_5, readys_5, state_5)
node _filtered_3_ready_T = and(in[3].d.ready, allowed_5[0])
connect portsDIO_filtered[3].ready, _filtered_3_ready_T
node _filtered_3_ready_T_1 = and(in[3].d.ready, allowed_5[1])
connect portsDIO_filtered_1[3].ready, _filtered_3_ready_T_1
node _in_3_d_valid_T = or(portsDIO_filtered[3].valid, portsDIO_filtered_1[3].valid)
node _in_3_d_valid_T_1 = mux(state_5[0], portsDIO_filtered[3].valid, UInt<1>(0h0))
node _in_3_d_valid_T_2 = mux(state_5[1], portsDIO_filtered_1[3].valid, UInt<1>(0h0))
node _in_3_d_valid_T_3 = or(_in_3_d_valid_T_1, _in_3_d_valid_T_2)
wire _in_3_d_valid_WIRE : UInt<1>
connect _in_3_d_valid_WIRE, _in_3_d_valid_T_3
node _in_3_d_valid_T_4 = mux(idle_5, _in_3_d_valid_T, _in_3_d_valid_WIRE)
connect in[3].d.valid, _in_3_d_valid_T_4
wire _in_3_d_bits_WIRE : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}
node _in_3_d_bits_T = mux(muxState_5[0], portsDIO_filtered[3].bits.corrupt, UInt<1>(0h0))
node _in_3_d_bits_T_1 = mux(muxState_5[1], portsDIO_filtered_1[3].bits.corrupt, UInt<1>(0h0))
node _in_3_d_bits_T_2 = or(_in_3_d_bits_T, _in_3_d_bits_T_1)
wire _in_3_d_bits_WIRE_1 : UInt<1>
connect _in_3_d_bits_WIRE_1, _in_3_d_bits_T_2
connect _in_3_d_bits_WIRE.corrupt, _in_3_d_bits_WIRE_1
node _in_3_d_bits_T_3 = mux(muxState_5[0], portsDIO_filtered[3].bits.data, UInt<1>(0h0))
node _in_3_d_bits_T_4 = mux(muxState_5[1], portsDIO_filtered_1[3].bits.data, UInt<1>(0h0))
node _in_3_d_bits_T_5 = or(_in_3_d_bits_T_3, _in_3_d_bits_T_4)
wire _in_3_d_bits_WIRE_2 : UInt<64>
connect _in_3_d_bits_WIRE_2, _in_3_d_bits_T_5
connect _in_3_d_bits_WIRE.data, _in_3_d_bits_WIRE_2
wire _in_3_d_bits_WIRE_3 : { }
connect _in_3_d_bits_WIRE.echo, _in_3_d_bits_WIRE_3
wire _in_3_d_bits_WIRE_4 : { }
connect _in_3_d_bits_WIRE.user, _in_3_d_bits_WIRE_4
node _in_3_d_bits_T_6 = mux(muxState_5[0], portsDIO_filtered[3].bits.denied, UInt<1>(0h0))
node _in_3_d_bits_T_7 = mux(muxState_5[1], portsDIO_filtered_1[3].bits.denied, UInt<1>(0h0))
node _in_3_d_bits_T_8 = or(_in_3_d_bits_T_6, _in_3_d_bits_T_7)
wire _in_3_d_bits_WIRE_5 : UInt<1>
connect _in_3_d_bits_WIRE_5, _in_3_d_bits_T_8
connect _in_3_d_bits_WIRE.denied, _in_3_d_bits_WIRE_5
node _in_3_d_bits_T_9 = mux(muxState_5[0], portsDIO_filtered[3].bits.sink, UInt<1>(0h0))
node _in_3_d_bits_T_10 = mux(muxState_5[1], portsDIO_filtered_1[3].bits.sink, UInt<1>(0h0))
node _in_3_d_bits_T_11 = or(_in_3_d_bits_T_9, _in_3_d_bits_T_10)
wire _in_3_d_bits_WIRE_6 : UInt<1>
connect _in_3_d_bits_WIRE_6, _in_3_d_bits_T_11
connect _in_3_d_bits_WIRE.sink, _in_3_d_bits_WIRE_6
node _in_3_d_bits_T_12 = mux(muxState_5[0], portsDIO_filtered[3].bits.source, UInt<1>(0h0))
node _in_3_d_bits_T_13 = mux(muxState_5[1], portsDIO_filtered_1[3].bits.source, UInt<1>(0h0))
node _in_3_d_bits_T_14 = or(_in_3_d_bits_T_12, _in_3_d_bits_T_13)
wire _in_3_d_bits_WIRE_7 : UInt<7>
connect _in_3_d_bits_WIRE_7, _in_3_d_bits_T_14
connect _in_3_d_bits_WIRE.source, _in_3_d_bits_WIRE_7
node _in_3_d_bits_T_15 = mux(muxState_5[0], portsDIO_filtered[3].bits.size, UInt<1>(0h0))
node _in_3_d_bits_T_16 = mux(muxState_5[1], portsDIO_filtered_1[3].bits.size, UInt<1>(0h0))
node _in_3_d_bits_T_17 = or(_in_3_d_bits_T_15, _in_3_d_bits_T_16)
wire _in_3_d_bits_WIRE_8 : UInt<3>
connect _in_3_d_bits_WIRE_8, _in_3_d_bits_T_17
connect _in_3_d_bits_WIRE.size, _in_3_d_bits_WIRE_8
node _in_3_d_bits_T_18 = mux(muxState_5[0], portsDIO_filtered[3].bits.param, UInt<1>(0h0))
node _in_3_d_bits_T_19 = mux(muxState_5[1], portsDIO_filtered_1[3].bits.param, UInt<1>(0h0))
node _in_3_d_bits_T_20 = or(_in_3_d_bits_T_18, _in_3_d_bits_T_19)
wire _in_3_d_bits_WIRE_9 : UInt<2>
connect _in_3_d_bits_WIRE_9, _in_3_d_bits_T_20
connect _in_3_d_bits_WIRE.param, _in_3_d_bits_WIRE_9
node _in_3_d_bits_T_21 = mux(muxState_5[0], portsDIO_filtered[3].bits.opcode, UInt<1>(0h0))
node _in_3_d_bits_T_22 = mux(muxState_5[1], portsDIO_filtered_1[3].bits.opcode, UInt<1>(0h0))
node _in_3_d_bits_T_23 = or(_in_3_d_bits_T_21, _in_3_d_bits_T_22)
wire _in_3_d_bits_WIRE_10 : UInt<3>
connect _in_3_d_bits_WIRE_10, _in_3_d_bits_T_23
connect _in_3_d_bits_WIRE.opcode, _in_3_d_bits_WIRE_10
connect in[3].d.bits.corrupt, _in_3_d_bits_WIRE.corrupt
connect in[3].d.bits.data, _in_3_d_bits_WIRE.data
connect in[3].d.bits.denied, _in_3_d_bits_WIRE.denied
connect in[3].d.bits.sink, _in_3_d_bits_WIRE.sink
connect in[3].d.bits.source, _in_3_d_bits_WIRE.source
connect in[3].d.bits.size, _in_3_d_bits_WIRE.size
connect in[3].d.bits.param, _in_3_d_bits_WIRE.param
connect in[3].d.bits.opcode, _in_3_d_bits_WIRE.opcode
connect portsBIO_filtered[3].ready, UInt<1>(0h0)
connect portsBIO_filtered_1[3].ready, UInt<1>(0h0) | module TLXbar_mbus_i4_o2_a32d64s7k1z3u( // @[Xbar.scala:74:9]
input clock, // @[Xbar.scala:74:9]
input reset, // @[Xbar.scala:74:9]
output auto_anon_in_3_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_3_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_3_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_3_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_3_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_in_3_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_3_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_3_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_3_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_3_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_3_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_3_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_3_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_3_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_3_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_3_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_3_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_3_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_3_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_3_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_2_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_2_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_2_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_2_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_2_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_in_2_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_2_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_2_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_2_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_2_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_2_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_2_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_2_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_2_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_2_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_2_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_2_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_2_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_2_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_2_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_out_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [27:0] auto_anon_out_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_1_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_out_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [6:0] auto_anon_out_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_anon_out_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_anon_out_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_0_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [6:0] auto_anon_out_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_anon_out_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_0_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire allowed_5_1; // @[Arbiter.scala:92:24]
wire allowed_5_0; // @[Arbiter.scala:92:24]
wire allowed_4_1; // @[Arbiter.scala:92:24]
wire allowed_4_0; // @[Arbiter.scala:92:24]
wire allowed_3_1; // @[Arbiter.scala:92:24]
wire allowed_3_0; // @[Arbiter.scala:92:24]
wire allowed_2_1; // @[Arbiter.scala:92:24]
wire allowed_2_0; // @[Arbiter.scala:92:24]
wire allowed_1_3; // @[Arbiter.scala:92:24]
wire allowed_1_2; // @[Arbiter.scala:92:24]
wire allowed_1_1; // @[Arbiter.scala:92:24]
wire allowed_1_0; // @[Arbiter.scala:92:24]
wire allowed_3; // @[Arbiter.scala:92:24]
wire allowed_2; // @[Arbiter.scala:92:24]
wire allowed_1; // @[Arbiter.scala:92:24]
wire allowed_0; // @[Arbiter.scala:92:24]
wire [6:0] in_0_a_bits_source = {2'h3, auto_anon_in_0_a_bits_source}; // @[Xbar.scala:166:55]
wire [6:0] in_1_a_bits_source = {2'h2, auto_anon_in_1_a_bits_source}; // @[Xbar.scala:74:9, :166:55]
wire [6:0] in_2_a_bits_source = {2'h1, auto_anon_in_2_a_bits_source}; // @[Xbar.scala:74:9, :166:29]
wire [6:0] in_3_a_bits_source = {2'h0, auto_anon_in_3_a_bits_source}; // @[Xbar.scala:74:9, :166:29]
wire requestDOI_0_1 = auto_anon_out_0_d_bits_source[6:5] == 2'h2; // @[Xbar.scala:74:9]
wire requestDOI_0_2 = auto_anon_out_0_d_bits_source[6:5] == 2'h1; // @[Xbar.scala:74:9]
wire requestDOI_0_3 = auto_anon_out_0_d_bits_source[6:5] == 2'h0; // @[Xbar.scala:74:9]
wire requestDOI_1_1 = auto_anon_out_1_d_bits_source[6:5] == 2'h2; // @[Xbar.scala:74:9]
wire requestDOI_1_2 = auto_anon_out_1_d_bits_source[6:5] == 2'h1; // @[Xbar.scala:74:9]
wire requestDOI_1_3 = auto_anon_out_1_d_bits_source[6:5] == 2'h0; // @[Xbar.scala:74:9]
wire portsAOI_filtered_0_valid = auto_anon_in_0_a_valid & auto_anon_in_0_a_bits_address[31]; // @[Xbar.scala:355:40]
wire portsAOI_filtered_1_valid = auto_anon_in_0_a_valid & ~(auto_anon_in_0_a_bits_address[31]); // @[Xbar.scala:355:40]
wire _portsAOI_in_0_a_ready_T_2 = auto_anon_in_0_a_bits_address[31] & auto_anon_out_0_a_ready & allowed_0 | ~(auto_anon_in_0_a_bits_address[31]) & auto_anon_out_1_a_ready & allowed_1_0; // @[Mux.scala:30:73]
wire portsAOI_filtered_1_0_valid = auto_anon_in_1_a_valid & auto_anon_in_1_a_bits_address[31]; // @[Xbar.scala:355:40]
wire portsAOI_filtered_1_1_valid = auto_anon_in_1_a_valid & ~(auto_anon_in_1_a_bits_address[31]); // @[Xbar.scala:355:40]
wire _portsAOI_in_1_a_ready_T_2 = auto_anon_in_1_a_bits_address[31] & auto_anon_out_0_a_ready & allowed_1 | ~(auto_anon_in_1_a_bits_address[31]) & auto_anon_out_1_a_ready & allowed_1_1; // @[Mux.scala:30:73]
wire portsAOI_filtered_2_0_valid = auto_anon_in_2_a_valid & auto_anon_in_2_a_bits_address[31]; // @[Xbar.scala:355:40]
wire portsAOI_filtered_2_1_valid = auto_anon_in_2_a_valid & ~(auto_anon_in_2_a_bits_address[31]); // @[Xbar.scala:355:40]
wire _portsAOI_in_2_a_ready_T_2 = auto_anon_in_2_a_bits_address[31] & auto_anon_out_0_a_ready & allowed_2 | ~(auto_anon_in_2_a_bits_address[31]) & auto_anon_out_1_a_ready & allowed_1_2; // @[Mux.scala:30:73]
wire portsAOI_filtered_3_0_valid = auto_anon_in_3_a_valid & auto_anon_in_3_a_bits_address[31]; // @[Xbar.scala:355:40]
wire portsAOI_filtered_3_1_valid = auto_anon_in_3_a_valid & ~(auto_anon_in_3_a_bits_address[31]); // @[Xbar.scala:355:40]
wire _portsAOI_in_3_a_ready_T_2 = auto_anon_in_3_a_bits_address[31] & auto_anon_out_0_a_ready & allowed_3 | ~(auto_anon_in_3_a_bits_address[31]) & auto_anon_out_1_a_ready & allowed_1_3; // @[Mux.scala:30:73]
wire portsDIO_filtered_0_valid = auto_anon_out_0_d_valid & (&(auto_anon_out_0_d_bits_source[6:5])); // @[Xbar.scala:355:40]
wire portsDIO_filtered_1_valid = auto_anon_out_0_d_valid & requestDOI_0_1; // @[Xbar.scala:355:40]
wire portsDIO_filtered_2_valid = auto_anon_out_0_d_valid & requestDOI_0_2; // @[Xbar.scala:355:40]
wire portsDIO_filtered_3_valid = auto_anon_out_0_d_valid & requestDOI_0_3; // @[Xbar.scala:355:40]
wire portsDIO_filtered_1_0_valid = auto_anon_out_1_d_valid & (&(auto_anon_out_1_d_bits_source[6:5])); // @[Xbar.scala:355:40]
wire portsDIO_filtered_1_1_valid = auto_anon_out_1_d_valid & requestDOI_1_1; // @[Xbar.scala:355:40]
wire portsDIO_filtered_1_2_valid = auto_anon_out_1_d_valid & requestDOI_1_2; // @[Xbar.scala:355:40]
wire portsDIO_filtered_1_3_valid = auto_anon_out_1_d_valid & requestDOI_1_3; // @[Xbar.scala:355:40]
reg [2:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 3'h0; // @[Arbiter.scala:60:30, :61:28]
wire [3:0] readys_valid = {portsAOI_filtered_3_0_valid, portsAOI_filtered_2_0_valid, portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid}; // @[Xbar.scala:355:40]
reg [3:0] readys_mask; // @[Arbiter.scala:23:23]
wire [3:0] _readys_filter_T_1 = readys_valid & ~readys_mask; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51]
wire [5:0] _GEN = {_readys_filter_T_1[2:0], portsAOI_filtered_3_0_valid, portsAOI_filtered_2_0_valid, portsAOI_filtered_1_0_valid} | {_readys_filter_T_1, portsAOI_filtered_3_0_valid, portsAOI_filtered_2_0_valid}; // @[package.scala:262:{43,48}]
wire [4:0] _GEN_0 = _GEN[4:0] | {_readys_filter_T_1[3], _GEN[5:2]}; // @[package.scala:262:{43,48}]
wire [3:0] readys_readys = ~({readys_mask[3], _readys_filter_T_1[3] | readys_mask[2], _GEN[5] | readys_mask[1], _GEN_0[4] | readys_mask[0]} & _GEN_0[3:0]); // @[package.scala:262:43]
wire winner_0 = readys_readys[0] & portsAOI_filtered_0_valid; // @[Xbar.scala:355:40]
wire winner_1 = readys_readys[1] & portsAOI_filtered_1_0_valid; // @[Xbar.scala:355:40]
wire winner_2 = readys_readys[2] & portsAOI_filtered_2_0_valid; // @[Xbar.scala:355:40]
wire winner_3 = readys_readys[3] & portsAOI_filtered_3_0_valid; // @[Xbar.scala:355:40]
wire _out_0_a_valid_T = portsAOI_filtered_0_valid | portsAOI_filtered_1_0_valid; // @[Xbar.scala:355:40]
reg state_0; // @[Arbiter.scala:88:26]
reg state_1; // @[Arbiter.scala:88:26]
reg state_2; // @[Arbiter.scala:88:26]
reg state_3; // @[Arbiter.scala:88:26]
wire muxState_0 = idle ? winner_0 : state_0; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
wire muxState_1 = idle ? winner_1 : state_1; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
wire muxState_2 = idle ? winner_2 : state_2; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
wire muxState_3 = idle ? winner_3 : state_3; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
assign allowed_0 = idle ? readys_readys[0] : state_0; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24]
assign allowed_1 = idle ? readys_readys[1] : state_1; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24]
assign allowed_2 = idle ? readys_readys[2] : state_2; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24]
assign allowed_3 = idle ? readys_readys[3] : state_3; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24]
wire out_0_a_valid = idle ? _out_0_a_valid_T | portsAOI_filtered_2_0_valid | portsAOI_filtered_3_0_valid : state_0 & portsAOI_filtered_0_valid | state_1 & portsAOI_filtered_1_0_valid | state_2 & portsAOI_filtered_2_0_valid | state_3 & portsAOI_filtered_3_0_valid; // @[Mux.scala:30:73]
reg [2:0] beatsLeft_1; // @[Arbiter.scala:60:30]
wire idle_1 = beatsLeft_1 == 3'h0; // @[Arbiter.scala:60:30, :61:28]
wire [3:0] readys_valid_1 = {portsAOI_filtered_3_1_valid, portsAOI_filtered_2_1_valid, portsAOI_filtered_1_1_valid, portsAOI_filtered_1_valid}; // @[Xbar.scala:355:40]
reg [3:0] readys_mask_1; // @[Arbiter.scala:23:23]
wire [3:0] _readys_filter_T_3 = readys_valid_1 & ~readys_mask_1; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51]
wire [5:0] _GEN_1 = {_readys_filter_T_3[2:0], portsAOI_filtered_3_1_valid, portsAOI_filtered_2_1_valid, portsAOI_filtered_1_1_valid} | {_readys_filter_T_3, portsAOI_filtered_3_1_valid, portsAOI_filtered_2_1_valid}; // @[package.scala:262:{43,48}]
wire [4:0] _GEN_2 = _GEN_1[4:0] | {_readys_filter_T_3[3], _GEN_1[5:2]}; // @[package.scala:262:{43,48}]
wire [3:0] readys_readys_1 = ~({readys_mask_1[3], _readys_filter_T_3[3] | readys_mask_1[2], _GEN_1[5] | readys_mask_1[1], _GEN_2[4] | readys_mask_1[0]} & _GEN_2[3:0]); // @[package.scala:262:43]
wire winner_1_0 = readys_readys_1[0] & portsAOI_filtered_1_valid; // @[Xbar.scala:355:40]
wire winner_1_1 = readys_readys_1[1] & portsAOI_filtered_1_1_valid; // @[Xbar.scala:355:40]
wire winner_1_2 = readys_readys_1[2] & portsAOI_filtered_2_1_valid; // @[Xbar.scala:355:40]
wire winner_1_3 = readys_readys_1[3] & portsAOI_filtered_3_1_valid; // @[Xbar.scala:355:40]
wire _out_1_a_valid_T = portsAOI_filtered_1_valid | portsAOI_filtered_1_1_valid; // @[Xbar.scala:355:40]
reg state_1_0; // @[Arbiter.scala:88:26]
reg state_1_1; // @[Arbiter.scala:88:26]
reg state_1_2; // @[Arbiter.scala:88:26]
reg state_1_3; // @[Arbiter.scala:88:26]
wire muxState_1_0 = idle_1 ? winner_1_0 : state_1_0; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
wire muxState_1_1 = idle_1 ? winner_1_1 : state_1_1; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
wire muxState_1_2 = idle_1 ? winner_1_2 : state_1_2; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
wire muxState_1_3 = idle_1 ? winner_1_3 : state_1_3; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
assign allowed_1_0 = idle_1 ? readys_readys_1[0] : state_1_0; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24]
assign allowed_1_1 = idle_1 ? readys_readys_1[1] : state_1_1; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24]
assign allowed_1_2 = idle_1 ? readys_readys_1[2] : state_1_2; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24]
assign allowed_1_3 = idle_1 ? readys_readys_1[3] : state_1_3; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24]
wire out_1_a_valid = idle_1 ? _out_1_a_valid_T | portsAOI_filtered_2_1_valid | portsAOI_filtered_3_1_valid : state_1_0 & portsAOI_filtered_1_valid | state_1_1 & portsAOI_filtered_1_1_valid | state_1_2 & portsAOI_filtered_2_1_valid | state_1_3 & portsAOI_filtered_3_1_valid; // @[Mux.scala:30:73]
reg [2:0] beatsLeft_2; // @[Arbiter.scala:60:30]
wire idle_2 = beatsLeft_2 == 3'h0; // @[Arbiter.scala:60:30, :61:28]
wire [1:0] readys_valid_2 = {portsDIO_filtered_1_0_valid, portsDIO_filtered_0_valid}; // @[Xbar.scala:355:40]
reg [1:0] readys_mask_2; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_5 = readys_valid_2 & ~readys_mask_2; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51]
wire [1:0] readys_readys_2 = ~({readys_mask_2[1], _readys_filter_T_5[1] | readys_mask_2[0]} & ({_readys_filter_T_5[0], portsDIO_filtered_1_0_valid} | _readys_filter_T_5)); // @[package.scala:262:43]
wire winner_2_0 = readys_readys_2[0] & portsDIO_filtered_0_valid; // @[Xbar.scala:355:40]
wire winner_2_1 = readys_readys_2[1] & portsDIO_filtered_1_0_valid; // @[Xbar.scala:355:40]
wire _in_0_d_valid_T = portsDIO_filtered_0_valid | portsDIO_filtered_1_0_valid; // @[Xbar.scala:355:40]
reg state_2_0; // @[Arbiter.scala:88:26]
reg state_2_1; // @[Arbiter.scala:88:26]
wire muxState_2_0 = idle_2 ? winner_2_0 : state_2_0; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
wire muxState_2_1 = idle_2 ? winner_2_1 : state_2_1; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
assign allowed_2_0 = idle_2 ? readys_readys_2[0] : state_2_0; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24]
assign allowed_2_1 = idle_2 ? readys_readys_2[1] : state_2_1; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24]
wire in_0_d_valid = idle_2 ? _in_0_d_valid_T : state_2_0 & portsDIO_filtered_0_valid | state_2_1 & portsDIO_filtered_1_0_valid; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_2 = muxState_2_0 & auto_anon_out_0_d_bits_corrupt | muxState_2_1 & auto_anon_out_1_d_bits_corrupt; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_8 = muxState_2_0 & auto_anon_out_0_d_bits_denied | muxState_2_1 & auto_anon_out_1_d_bits_denied; // @[Mux.scala:30:73]
wire _in_0_d_bits_T_10 = muxState_2_1 & auto_anon_out_1_d_bits_sink; // @[Mux.scala:30:73]
wire [4:0] _in_0_d_bits_T_14 = (muxState_2_0 ? auto_anon_out_0_d_bits_source[4:0] : 5'h0) | (muxState_2_1 ? auto_anon_out_1_d_bits_source[4:0] : 5'h0); // @[Mux.scala:30:73]
wire [2:0] _in_0_d_bits_T_17 = (muxState_2_0 ? auto_anon_out_0_d_bits_size : 3'h0) | (muxState_2_1 ? auto_anon_out_1_d_bits_size : 3'h0); // @[Mux.scala:30:73]
wire [1:0] _in_0_d_bits_T_19 = muxState_2_1 ? auto_anon_out_1_d_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [2:0] _in_0_d_bits_T_23 = (muxState_2_0 ? auto_anon_out_0_d_bits_opcode : 3'h0) | (muxState_2_1 ? auto_anon_out_1_d_bits_opcode : 3'h0); // @[Mux.scala:30:73]
reg [2:0] beatsLeft_3; // @[Arbiter.scala:60:30]
wire idle_3 = beatsLeft_3 == 3'h0; // @[Arbiter.scala:60:30, :61:28]
wire [1:0] readys_valid_3 = {portsDIO_filtered_1_1_valid, portsDIO_filtered_1_valid}; // @[Xbar.scala:355:40]
reg [1:0] readys_mask_3; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_7 = readys_valid_3 & ~readys_mask_3; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51]
wire [1:0] readys_readys_3 = ~({readys_mask_3[1], _readys_filter_T_7[1] | readys_mask_3[0]} & ({_readys_filter_T_7[0], portsDIO_filtered_1_1_valid} | _readys_filter_T_7)); // @[package.scala:262:43]
wire winner_3_0 = readys_readys_3[0] & portsDIO_filtered_1_valid; // @[Xbar.scala:355:40]
wire winner_3_1 = readys_readys_3[1] & portsDIO_filtered_1_1_valid; // @[Xbar.scala:355:40]
wire _in_1_d_valid_T = portsDIO_filtered_1_valid | portsDIO_filtered_1_1_valid; // @[Xbar.scala:355:40]
reg state_3_0; // @[Arbiter.scala:88:26]
reg state_3_1; // @[Arbiter.scala:88:26]
wire muxState_3_0 = idle_3 ? winner_3_0 : state_3_0; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
wire muxState_3_1 = idle_3 ? winner_3_1 : state_3_1; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
assign allowed_3_0 = idle_3 ? readys_readys_3[0] : state_3_0; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24]
assign allowed_3_1 = idle_3 ? readys_readys_3[1] : state_3_1; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24]
wire in_1_d_valid = idle_3 ? _in_1_d_valid_T : state_3_0 & portsDIO_filtered_1_valid | state_3_1 & portsDIO_filtered_1_1_valid; // @[Mux.scala:30:73]
wire _in_1_d_bits_T_2 = muxState_3_0 & auto_anon_out_0_d_bits_corrupt | muxState_3_1 & auto_anon_out_1_d_bits_corrupt; // @[Mux.scala:30:73]
wire _in_1_d_bits_T_8 = muxState_3_0 & auto_anon_out_0_d_bits_denied | muxState_3_1 & auto_anon_out_1_d_bits_denied; // @[Mux.scala:30:73]
wire _in_1_d_bits_T_10 = muxState_3_1 & auto_anon_out_1_d_bits_sink; // @[Mux.scala:30:73]
wire [4:0] _in_1_d_bits_T_14 = (muxState_3_0 ? auto_anon_out_0_d_bits_source[4:0] : 5'h0) | (muxState_3_1 ? auto_anon_out_1_d_bits_source[4:0] : 5'h0); // @[Mux.scala:30:73]
wire [2:0] _in_1_d_bits_T_17 = (muxState_3_0 ? auto_anon_out_0_d_bits_size : 3'h0) | (muxState_3_1 ? auto_anon_out_1_d_bits_size : 3'h0); // @[Mux.scala:30:73]
wire [1:0] _in_1_d_bits_T_19 = muxState_3_1 ? auto_anon_out_1_d_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [2:0] _in_1_d_bits_T_23 = (muxState_3_0 ? auto_anon_out_0_d_bits_opcode : 3'h0) | (muxState_3_1 ? auto_anon_out_1_d_bits_opcode : 3'h0); // @[Mux.scala:30:73]
reg [2:0] beatsLeft_4; // @[Arbiter.scala:60:30]
wire idle_4 = beatsLeft_4 == 3'h0; // @[Arbiter.scala:60:30, :61:28]
wire [1:0] readys_valid_4 = {portsDIO_filtered_1_2_valid, portsDIO_filtered_2_valid}; // @[Xbar.scala:355:40]
reg [1:0] readys_mask_4; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_9 = readys_valid_4 & ~readys_mask_4; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51]
wire [1:0] readys_readys_4 = ~({readys_mask_4[1], _readys_filter_T_9[1] | readys_mask_4[0]} & ({_readys_filter_T_9[0], portsDIO_filtered_1_2_valid} | _readys_filter_T_9)); // @[package.scala:262:43]
wire winner_4_0 = readys_readys_4[0] & portsDIO_filtered_2_valid; // @[Xbar.scala:355:40]
wire winner_4_1 = readys_readys_4[1] & portsDIO_filtered_1_2_valid; // @[Xbar.scala:355:40]
wire _in_2_d_valid_T = portsDIO_filtered_2_valid | portsDIO_filtered_1_2_valid; // @[Xbar.scala:355:40]
reg state_4_0; // @[Arbiter.scala:88:26]
reg state_4_1; // @[Arbiter.scala:88:26]
wire muxState_4_0 = idle_4 ? winner_4_0 : state_4_0; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
wire muxState_4_1 = idle_4 ? winner_4_1 : state_4_1; // @[Arbiter.scala:61:28, :71:69, :88:26, :89:25]
assign allowed_4_0 = idle_4 ? readys_readys_4[0] : state_4_0; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24]
assign allowed_4_1 = idle_4 ? readys_readys_4[1] : state_4_1; // @[Arbiter.scala:26:18, :61:28, :68:76, :88:26, :92:24]
wire in_2_d_valid = idle_4 ? _in_2_d_valid_T : state_4_0 & portsDIO_filtered_2_valid | state_4_1 & portsDIO_filtered_1_2_valid; // @[Mux.scala:30:73]
wire _in_2_d_bits_T_2 = muxState_4_0 & auto_anon_out_0_d_bits_corrupt | muxState_4_1 & auto_anon_out_1_d_bits_corrupt; // @[Mux.scala:30:73]
wire _in_2_d_bits_T_8 = muxState_4_0 & auto_anon_out_0_d_bits_denied | muxState_4_1 & auto_anon_out_1_d_bits_denied; // @[Mux.scala:30:73]
wire _in_2_d_bits_T_10 = muxState_4_1 & auto_anon_out_1_d_bits_sink; // @[Mux.scala:30:73]
wire [4:0] _in_2_d_bits_T_14 = (muxState_4_0 ? auto_anon_out_0_d_bits_source[4:0] : 5'h0) | (muxState_4_1 ? auto_anon_out_1_d_bits_source[4:0] : 5'h0); // @[Mux.scala:30:73]
wire [2:0] _in_2_d_bits_T_17 = (muxState_4_0 ? auto_anon_out_0_d_bits_size : 3'h0) | (muxState_4_1 ? auto_anon_out_1_d_bits_size : 3'h0); // @[Mux.scala:30:73]
wire [1:0] _in_2_d_bits_T_19 = muxState_4_1 ? auto_anon_out_1_d_bits_param : 2'h0; // @[Mux.scala:30:73]
wire [2:0] _in_2_d_bits_T_23 = (muxState_4_0 ? auto_anon_out_0_d_bits_opcode : 3'h0) | (muxState_4_1 ? auto_anon_out_1_d_bits_opcode : 3'h0); // @[Mux.scala:30:73]
reg [2:0] beatsLeft_5; // @[Arbiter.scala:60:30]
wire idle_5 = beatsLeft_5 == 3'h0; // @[Arbiter.scala:60:30, :61:28]
wire [1:0] readys_valid_5 = {portsDIO_filtered_1_3_valid, portsDIO_filtered_3_valid}; // @[Xbar.scala:355:40]
reg [1:0] readys_mask_5; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T_11 = readys_valid_5 & ~readys_mask_5; // @[Arbiter.scala:23:23, :24:{28,30}, :68:51]
wire [1:0] readys_readys_5 = ~({readys_mask_5[1], _readys_filter_T_11[1] | readys_mask_5[0]} & ({_readys_filter_T_11[0], portsDIO_filtered_1_3_valid} | _readys_filter_T_11)); // @[package.scala:262:43]
wire winner_5_0 = readys_readys_5[0] & portsDIO_filtered_3_valid; // @[Xbar.scala:355:40]
wire winner_5_1 = readys_readys_5[1] & portsDIO_filtered_1_3_valid; // @[Xbar.scala:355:40]
wire _in_3_d_valid_T = portsDIO_filtered_3_valid | portsDIO_filtered_1_3_valid; // @[Xbar.scala:355:40] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_514 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_514( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_27 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<4>, q : UInt<4>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_254
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
node _output_T_2 = asAsyncReset(reset)
node _output_T_3 = bits(io.d, 1, 1)
inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_255
connect output_chain_1.clock, clock
connect output_chain_1.reset, _output_T_2
connect output_chain_1.io.d, _output_T_3
wire output_1 : UInt<1>
connect output_1, output_chain_1.io.q
node _output_T_4 = asAsyncReset(reset)
node _output_T_5 = bits(io.d, 2, 2)
inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_256
connect output_chain_2.clock, clock
connect output_chain_2.reset, _output_T_4
connect output_chain_2.io.d, _output_T_5
wire output_2 : UInt<1>
connect output_2, output_chain_2.io.q
node _output_T_6 = asAsyncReset(reset)
node _output_T_7 = bits(io.d, 3, 3)
inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_257
connect output_chain_3.clock, clock
connect output_chain_3.reset, _output_T_6
connect output_chain_3.io.d, _output_T_7
wire output_3 : UInt<1>
connect output_3, output_chain_3.io.q
node io_q_lo = cat(output_1, output_0)
node io_q_hi = cat(output_3, output_2)
node _io_q_T = cat(io_q_hi, io_q_lo)
connect io.q, _io_q_T | module AsyncResetSynchronizerShiftReg_w4_d3_i0_27( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input [3:0] io_d, // @[ShiftReg.scala:36:14]
output [3:0] io_q // @[ShiftReg.scala:36:14]
);
wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21]
wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14]
wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7]
wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_1; // @[ShiftReg.scala:48:24]
wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_2; // @[ShiftReg.scala:48:24]
wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_3; // @[ShiftReg.scala:48:24]
wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14]
wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14]
assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14]
assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_254 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_255 output_chain_1 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_2), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_3), // @[SynchronizerReg.scala:87:41]
.io_q (output_1)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_256 output_chain_2 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_4), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_5), // @[SynchronizerReg.scala:87:41]
.io_q (output_2)
); // @[ShiftReg.scala:45:23]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_257 output_chain_3 ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T_6), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_7), // @[SynchronizerReg.scala:87:41]
.io_q (output_3)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TageTable_14 :
input clock : Clock
input reset : Reset
output io : { flip f1_req_valid : UInt<1>, flip f1_req_pc : UInt<40>, flip f1_req_ghist : UInt<64>, f3_resp : { valid : UInt<1>, bits : { ctr : UInt<3>, u : UInt<2>}}[4], flip update_mask : UInt<1>[4], flip update_taken : UInt<1>[4], flip update_alloc : UInt<1>[4], flip update_old_ctr : UInt<3>[4], flip update_pc : UInt, flip update_hist : UInt, flip update_u_mask : UInt<1>[4], flip update_u : UInt<2>[4]}
regreset doing_reset : UInt<1>, clock, reset, UInt<1>(0h1)
regreset reset_idx : UInt<8>, clock, reset, UInt<8>(0h0)
node _reset_idx_T = add(reset_idx, doing_reset)
node _reset_idx_T_1 = tail(_reset_idx_T, 1)
connect reset_idx, _reset_idx_T_1
node _T = eq(reset_idx, UInt<8>(0hff))
when _T :
connect doing_reset, UInt<1>(0h0)
node _T_1 = shr(io.f1_req_pc, 4)
node idx_history = bits(io.f1_req_ghist, 7, 0)
node _idx_T = xor(_T_1, idx_history)
node s1_hashed_idx = bits(_idx_T, 7, 0)
node tag_history = bits(io.f1_req_ghist, 7, 0)
node _tag_T = shr(_T_1, 8)
node _tag_T_1 = xor(_tag_T, tag_history)
node s1_tag = bits(_tag_T_1, 7, 0)
smem hi_us : UInt<1>[4] [256]
smem lo_us : UInt<1>[4] [256]
smem table : UInt<12>[4] [256]
reg s2_tag : UInt, clock
connect s2_tag, s1_tag
wire _s2_req_rtage_WIRE : UInt<8>
invalidate _s2_req_rtage_WIRE
when io.f1_req_valid :
connect _s2_req_rtage_WIRE, s1_hashed_idx
read mport s2_req_rtage_MPORT = table[_s2_req_rtage_WIRE], clock
wire _s2_req_rtage_WIRE_1 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}
wire _s2_req_rtage_WIRE_2 : UInt<12>
connect _s2_req_rtage_WIRE_2, s2_req_rtage_MPORT[0]
node _s2_req_rtage_T = bits(_s2_req_rtage_WIRE_2, 2, 0)
connect _s2_req_rtage_WIRE_1.ctr, _s2_req_rtage_T
node _s2_req_rtage_T_1 = bits(_s2_req_rtage_WIRE_2, 10, 3)
connect _s2_req_rtage_WIRE_1.tag, _s2_req_rtage_T_1
node _s2_req_rtage_T_2 = bits(_s2_req_rtage_WIRE_2, 11, 11)
connect _s2_req_rtage_WIRE_1.valid, _s2_req_rtage_T_2
wire _s2_req_rtage_WIRE_3 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}
wire _s2_req_rtage_WIRE_4 : UInt<12>
connect _s2_req_rtage_WIRE_4, s2_req_rtage_MPORT[1]
node _s2_req_rtage_T_3 = bits(_s2_req_rtage_WIRE_4, 2, 0)
connect _s2_req_rtage_WIRE_3.ctr, _s2_req_rtage_T_3
node _s2_req_rtage_T_4 = bits(_s2_req_rtage_WIRE_4, 10, 3)
connect _s2_req_rtage_WIRE_3.tag, _s2_req_rtage_T_4
node _s2_req_rtage_T_5 = bits(_s2_req_rtage_WIRE_4, 11, 11)
connect _s2_req_rtage_WIRE_3.valid, _s2_req_rtage_T_5
wire _s2_req_rtage_WIRE_5 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}
wire _s2_req_rtage_WIRE_6 : UInt<12>
connect _s2_req_rtage_WIRE_6, s2_req_rtage_MPORT[2]
node _s2_req_rtage_T_6 = bits(_s2_req_rtage_WIRE_6, 2, 0)
connect _s2_req_rtage_WIRE_5.ctr, _s2_req_rtage_T_6
node _s2_req_rtage_T_7 = bits(_s2_req_rtage_WIRE_6, 10, 3)
connect _s2_req_rtage_WIRE_5.tag, _s2_req_rtage_T_7
node _s2_req_rtage_T_8 = bits(_s2_req_rtage_WIRE_6, 11, 11)
connect _s2_req_rtage_WIRE_5.valid, _s2_req_rtage_T_8
wire _s2_req_rtage_WIRE_7 : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}
wire _s2_req_rtage_WIRE_8 : UInt<12>
connect _s2_req_rtage_WIRE_8, s2_req_rtage_MPORT[3]
node _s2_req_rtage_T_9 = bits(_s2_req_rtage_WIRE_8, 2, 0)
connect _s2_req_rtage_WIRE_7.ctr, _s2_req_rtage_T_9
node _s2_req_rtage_T_10 = bits(_s2_req_rtage_WIRE_8, 10, 3)
connect _s2_req_rtage_WIRE_7.tag, _s2_req_rtage_T_10
node _s2_req_rtage_T_11 = bits(_s2_req_rtage_WIRE_8, 11, 11)
connect _s2_req_rtage_WIRE_7.valid, _s2_req_rtage_T_11
wire s2_req_rtage : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}[4]
connect s2_req_rtage[0].ctr, _s2_req_rtage_WIRE_1.ctr
connect s2_req_rtage[0].tag, _s2_req_rtage_WIRE_1.tag
connect s2_req_rtage[0].valid, _s2_req_rtage_WIRE_1.valid
connect s2_req_rtage[1].ctr, _s2_req_rtage_WIRE_3.ctr
connect s2_req_rtage[1].tag, _s2_req_rtage_WIRE_3.tag
connect s2_req_rtage[1].valid, _s2_req_rtage_WIRE_3.valid
connect s2_req_rtage[2].ctr, _s2_req_rtage_WIRE_5.ctr
connect s2_req_rtage[2].tag, _s2_req_rtage_WIRE_5.tag
connect s2_req_rtage[2].valid, _s2_req_rtage_WIRE_5.valid
connect s2_req_rtage[3].ctr, _s2_req_rtage_WIRE_7.ctr
connect s2_req_rtage[3].tag, _s2_req_rtage_WIRE_7.tag
connect s2_req_rtage[3].valid, _s2_req_rtage_WIRE_7.valid
wire _s2_req_rhius_WIRE : UInt<8>
invalidate _s2_req_rhius_WIRE
when io.f1_req_valid :
connect _s2_req_rhius_WIRE, s1_hashed_idx
read mport s2_req_rhius = hi_us[_s2_req_rhius_WIRE], clock
wire _s2_req_rlous_WIRE : UInt<8>
invalidate _s2_req_rlous_WIRE
when io.f1_req_valid :
connect _s2_req_rlous_WIRE, s1_hashed_idx
read mport s2_req_rlous = lo_us[_s2_req_rlous_WIRE], clock
node _s2_req_rhits_T = eq(s2_req_rtage[0].tag, s2_tag)
node _s2_req_rhits_T_1 = and(s2_req_rtage[0].valid, _s2_req_rhits_T)
node _s2_req_rhits_T_2 = eq(doing_reset, UInt<1>(0h0))
node _s2_req_rhits_T_3 = and(_s2_req_rhits_T_1, _s2_req_rhits_T_2)
node _s2_req_rhits_T_4 = eq(s2_req_rtage[1].tag, s2_tag)
node _s2_req_rhits_T_5 = and(s2_req_rtage[1].valid, _s2_req_rhits_T_4)
node _s2_req_rhits_T_6 = eq(doing_reset, UInt<1>(0h0))
node _s2_req_rhits_T_7 = and(_s2_req_rhits_T_5, _s2_req_rhits_T_6)
node _s2_req_rhits_T_8 = eq(s2_req_rtage[2].tag, s2_tag)
node _s2_req_rhits_T_9 = and(s2_req_rtage[2].valid, _s2_req_rhits_T_8)
node _s2_req_rhits_T_10 = eq(doing_reset, UInt<1>(0h0))
node _s2_req_rhits_T_11 = and(_s2_req_rhits_T_9, _s2_req_rhits_T_10)
node _s2_req_rhits_T_12 = eq(s2_req_rtage[3].tag, s2_tag)
node _s2_req_rhits_T_13 = and(s2_req_rtage[3].valid, _s2_req_rhits_T_12)
node _s2_req_rhits_T_14 = eq(doing_reset, UInt<1>(0h0))
node _s2_req_rhits_T_15 = and(_s2_req_rhits_T_13, _s2_req_rhits_T_14)
wire s2_req_rhits : UInt<1>[4]
connect s2_req_rhits[0], _s2_req_rhits_T_3
connect s2_req_rhits[1], _s2_req_rhits_T_7
connect s2_req_rhits[2], _s2_req_rhits_T_11
connect s2_req_rhits[3], _s2_req_rhits_T_15
reg io_f3_resp_0_valid_REG : UInt<1>, clock
connect io_f3_resp_0_valid_REG, s2_req_rhits[0]
connect io.f3_resp[0].valid, io_f3_resp_0_valid_REG
node _io_f3_resp_0_bits_u_T = cat(s2_req_rhius[0], s2_req_rlous[0])
reg io_f3_resp_0_bits_u_REG : UInt, clock
connect io_f3_resp_0_bits_u_REG, _io_f3_resp_0_bits_u_T
connect io.f3_resp[0].bits.u, io_f3_resp_0_bits_u_REG
reg io_f3_resp_0_bits_ctr_REG : UInt, clock
connect io_f3_resp_0_bits_ctr_REG, s2_req_rtage[0].ctr
connect io.f3_resp[0].bits.ctr, io_f3_resp_0_bits_ctr_REG
reg io_f3_resp_1_valid_REG : UInt<1>, clock
connect io_f3_resp_1_valid_REG, s2_req_rhits[1]
connect io.f3_resp[1].valid, io_f3_resp_1_valid_REG
node _io_f3_resp_1_bits_u_T = cat(s2_req_rhius[1], s2_req_rlous[1])
reg io_f3_resp_1_bits_u_REG : UInt, clock
connect io_f3_resp_1_bits_u_REG, _io_f3_resp_1_bits_u_T
connect io.f3_resp[1].bits.u, io_f3_resp_1_bits_u_REG
reg io_f3_resp_1_bits_ctr_REG : UInt, clock
connect io_f3_resp_1_bits_ctr_REG, s2_req_rtage[1].ctr
connect io.f3_resp[1].bits.ctr, io_f3_resp_1_bits_ctr_REG
reg io_f3_resp_2_valid_REG : UInt<1>, clock
connect io_f3_resp_2_valid_REG, s2_req_rhits[2]
connect io.f3_resp[2].valid, io_f3_resp_2_valid_REG
node _io_f3_resp_2_bits_u_T = cat(s2_req_rhius[2], s2_req_rlous[2])
reg io_f3_resp_2_bits_u_REG : UInt, clock
connect io_f3_resp_2_bits_u_REG, _io_f3_resp_2_bits_u_T
connect io.f3_resp[2].bits.u, io_f3_resp_2_bits_u_REG
reg io_f3_resp_2_bits_ctr_REG : UInt, clock
connect io_f3_resp_2_bits_ctr_REG, s2_req_rtage[2].ctr
connect io.f3_resp[2].bits.ctr, io_f3_resp_2_bits_ctr_REG
reg io_f3_resp_3_valid_REG : UInt<1>, clock
connect io_f3_resp_3_valid_REG, s2_req_rhits[3]
connect io.f3_resp[3].valid, io_f3_resp_3_valid_REG
node _io_f3_resp_3_bits_u_T = cat(s2_req_rhius[3], s2_req_rlous[3])
reg io_f3_resp_3_bits_u_REG : UInt, clock
connect io_f3_resp_3_bits_u_REG, _io_f3_resp_3_bits_u_T
connect io.f3_resp[3].bits.u, io_f3_resp_3_bits_u_REG
reg io_f3_resp_3_bits_ctr_REG : UInt, clock
connect io_f3_resp_3_bits_ctr_REG, s2_req_rtage[3].ctr
connect io.f3_resp[3].bits.ctr, io_f3_resp_3_bits_ctr_REG
regreset clear_u_ctr : UInt<20>, clock, reset, UInt<20>(0h0)
when doing_reset :
connect clear_u_ctr, UInt<1>(0h1)
else :
node _clear_u_ctr_T = add(clear_u_ctr, UInt<1>(0h1))
node _clear_u_ctr_T_1 = tail(_clear_u_ctr_T, 1)
connect clear_u_ctr, _clear_u_ctr_T_1
node _doing_clear_u_T = bits(clear_u_ctr, 10, 0)
node doing_clear_u = eq(_doing_clear_u_T, UInt<1>(0h0))
node _doing_clear_u_hi_T = bits(clear_u_ctr, 19, 19)
node _doing_clear_u_hi_T_1 = eq(_doing_clear_u_hi_T, UInt<1>(0h1))
node doing_clear_u_hi = and(doing_clear_u, _doing_clear_u_hi_T_1)
node _doing_clear_u_lo_T = bits(clear_u_ctr, 19, 19)
node _doing_clear_u_lo_T_1 = eq(_doing_clear_u_lo_T, UInt<1>(0h0))
node doing_clear_u_lo = and(doing_clear_u, _doing_clear_u_lo_T_1)
node clear_u_idx = shr(clear_u_ctr, 11)
node _T_2 = shr(io.update_pc, 4)
node idx_history_1 = bits(io.update_hist, 7, 0)
node _idx_T_1 = xor(_T_2, idx_history_1)
node update_idx = bits(_idx_T_1, 7, 0)
node tag_history_1 = bits(io.update_hist, 7, 0)
node _tag_T_2 = shr(_T_2, 8)
node _tag_T_3 = xor(_tag_T_2, tag_history_1)
node update_tag = bits(_tag_T_3, 7, 0)
wire update_wdata : { valid : UInt<1>, tag : UInt<8>, ctr : UInt<3>}[4]
node _T_3 = mux(doing_reset, reset_idx, update_idx)
wire _WIRE : UInt<12>[4]
connect _WIRE[0], UInt<12>(0h0)
connect _WIRE[1], UInt<12>(0h0)
connect _WIRE[2], UInt<12>(0h0)
connect _WIRE[3], UInt<12>(0h0)
node hi = cat(update_wdata[0].valid, update_wdata[0].tag)
node _T_4 = cat(hi, update_wdata[0].ctr)
node hi_1 = cat(update_wdata[1].valid, update_wdata[1].tag)
node _T_5 = cat(hi_1, update_wdata[1].ctr)
node hi_2 = cat(update_wdata[2].valid, update_wdata[2].tag)
node _T_6 = cat(hi_2, update_wdata[2].ctr)
node hi_3 = cat(update_wdata[3].valid, update_wdata[3].tag)
node _T_7 = cat(hi_3, update_wdata[3].ctr)
wire _WIRE_1 : UInt<12>[4]
connect _WIRE_1[0], _T_4
connect _WIRE_1[1], _T_5
connect _WIRE_1[2], _T_6
connect _WIRE_1[3], _T_7
node _T_8 = mux(doing_reset, _WIRE, _WIRE_1)
node _T_9 = not(UInt<4>(0h0))
node lo = cat(io.update_mask[1], io.update_mask[0])
node hi_4 = cat(io.update_mask[3], io.update_mask[2])
node _T_10 = cat(hi_4, lo)
node _T_11 = mux(doing_reset, _T_9, _T_10)
node _T_12 = bits(_T_11, 0, 0)
node _T_13 = bits(_T_11, 1, 1)
node _T_14 = bits(_T_11, 2, 2)
node _T_15 = bits(_T_11, 3, 3)
write mport MPORT = table[_T_3], clock
when _T_12 :
connect MPORT[0], _T_8[0]
when _T_13 :
connect MPORT[1], _T_8[1]
when _T_14 :
connect MPORT[2], _T_8[2]
when _T_15 :
connect MPORT[3], _T_8[3]
wire update_hi_wdata : UInt<1>[4]
node _T_16 = mux(doing_clear_u_hi, clear_u_idx, update_idx)
node _T_17 = mux(doing_reset, reset_idx, _T_16)
node _T_18 = or(doing_reset, doing_clear_u_hi)
wire _WIRE_2 : UInt<1>[4]
connect _WIRE_2[0], UInt<1>(0h0)
connect _WIRE_2[1], UInt<1>(0h0)
connect _WIRE_2[2], UInt<1>(0h0)
connect _WIRE_2[3], UInt<1>(0h0)
node _T_19 = mux(_T_18, _WIRE_2, update_hi_wdata)
node _T_20 = or(doing_reset, doing_clear_u_hi)
node _T_21 = not(UInt<4>(0h0))
node lo_1 = cat(io.update_u_mask[1], io.update_u_mask[0])
node hi_5 = cat(io.update_u_mask[3], io.update_u_mask[2])
node _T_22 = cat(hi_5, lo_1)
node _T_23 = mux(_T_20, _T_21, _T_22)
node _T_24 = bits(_T_23, 0, 0)
node _T_25 = bits(_T_23, 1, 1)
node _T_26 = bits(_T_23, 2, 2)
node _T_27 = bits(_T_23, 3, 3)
node _T_28 = bits(_T_17, 7, 0)
write mport MPORT_1 = hi_us[_T_28], clock
when _T_24 :
connect MPORT_1[0], _T_19[0]
when _T_25 :
connect MPORT_1[1], _T_19[1]
when _T_26 :
connect MPORT_1[2], _T_19[2]
when _T_27 :
connect MPORT_1[3], _T_19[3]
wire update_lo_wdata : UInt<1>[4]
node _T_29 = mux(doing_clear_u_lo, clear_u_idx, update_idx)
node _T_30 = mux(doing_reset, reset_idx, _T_29)
node _T_31 = or(doing_reset, doing_clear_u_lo)
wire _WIRE_3 : UInt<1>[4]
connect _WIRE_3[0], UInt<1>(0h0)
connect _WIRE_3[1], UInt<1>(0h0)
connect _WIRE_3[2], UInt<1>(0h0)
connect _WIRE_3[3], UInt<1>(0h0)
node _T_32 = mux(_T_31, _WIRE_3, update_lo_wdata)
node _T_33 = or(doing_reset, doing_clear_u_lo)
node _T_34 = not(UInt<4>(0h0))
node lo_2 = cat(io.update_u_mask[1], io.update_u_mask[0])
node hi_6 = cat(io.update_u_mask[3], io.update_u_mask[2])
node _T_35 = cat(hi_6, lo_2)
node _T_36 = mux(_T_33, _T_34, _T_35)
node _T_37 = bits(_T_36, 0, 0)
node _T_38 = bits(_T_36, 1, 1)
node _T_39 = bits(_T_36, 2, 2)
node _T_40 = bits(_T_36, 3, 3)
node _T_41 = bits(_T_30, 7, 0)
write mport MPORT_2 = lo_us[_T_41], clock
when _T_37 :
connect MPORT_2[0], _T_32[0]
when _T_38 :
connect MPORT_2[1], _T_32[1]
when _T_39 :
connect MPORT_2[2], _T_32[2]
when _T_40 :
connect MPORT_2[3], _T_32[3]
reg wrbypass_tags : UInt<8>[2], clock
reg wrbypass_idxs : UInt<8>[2], clock
reg wrbypass : UInt<3>[4][2], clock
regreset wrbypass_enq_idx : UInt<1>, clock, reset, UInt<1>(0h0)
node _wrbypass_hits_T = eq(doing_reset, UInt<1>(0h0))
node _wrbypass_hits_T_1 = eq(wrbypass_tags[0], update_tag)
node _wrbypass_hits_T_2 = and(_wrbypass_hits_T, _wrbypass_hits_T_1)
node _wrbypass_hits_T_3 = eq(wrbypass_idxs[0], update_idx)
node _wrbypass_hits_T_4 = and(_wrbypass_hits_T_2, _wrbypass_hits_T_3)
node _wrbypass_hits_T_5 = eq(doing_reset, UInt<1>(0h0))
node _wrbypass_hits_T_6 = eq(wrbypass_tags[1], update_tag)
node _wrbypass_hits_T_7 = and(_wrbypass_hits_T_5, _wrbypass_hits_T_6)
node _wrbypass_hits_T_8 = eq(wrbypass_idxs[1], update_idx)
node _wrbypass_hits_T_9 = and(_wrbypass_hits_T_7, _wrbypass_hits_T_8)
wire wrbypass_hits : UInt<1>[2]
connect wrbypass_hits[0], _wrbypass_hits_T_4
connect wrbypass_hits[1], _wrbypass_hits_T_9
node wrbypass_hit = or(wrbypass_hits[0], wrbypass_hits[1])
node wrbypass_hit_idx = mux(wrbypass_hits[0], UInt<1>(0h0), UInt<1>(0h1))
node _update_wdata_0_ctr_T = mux(io.update_taken[0], UInt<3>(0h4), UInt<2>(0h3))
node _update_wdata_0_ctr_T_1 = eq(io.update_taken[0], UInt<1>(0h0))
node _update_wdata_0_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h0))
node _update_wdata_0_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1))
node _update_wdata_0_ctr_T_4 = tail(_update_wdata_0_ctr_T_3, 1)
node _update_wdata_0_ctr_T_5 = mux(_update_wdata_0_ctr_T_2, UInt<1>(0h0), _update_wdata_0_ctr_T_4)
node _update_wdata_0_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][0], UInt<3>(0h7))
node _update_wdata_0_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][0], UInt<1>(0h1))
node _update_wdata_0_ctr_T_8 = tail(_update_wdata_0_ctr_T_7, 1)
node _update_wdata_0_ctr_T_9 = mux(_update_wdata_0_ctr_T_6, UInt<3>(0h7), _update_wdata_0_ctr_T_8)
node _update_wdata_0_ctr_T_10 = mux(_update_wdata_0_ctr_T_1, _update_wdata_0_ctr_T_5, _update_wdata_0_ctr_T_9)
node _update_wdata_0_ctr_T_11 = eq(io.update_taken[0], UInt<1>(0h0))
node _update_wdata_0_ctr_T_12 = eq(io.update_old_ctr[0], UInt<1>(0h0))
node _update_wdata_0_ctr_T_13 = sub(io.update_old_ctr[0], UInt<1>(0h1))
node _update_wdata_0_ctr_T_14 = tail(_update_wdata_0_ctr_T_13, 1)
node _update_wdata_0_ctr_T_15 = mux(_update_wdata_0_ctr_T_12, UInt<1>(0h0), _update_wdata_0_ctr_T_14)
node _update_wdata_0_ctr_T_16 = eq(io.update_old_ctr[0], UInt<3>(0h7))
node _update_wdata_0_ctr_T_17 = add(io.update_old_ctr[0], UInt<1>(0h1))
node _update_wdata_0_ctr_T_18 = tail(_update_wdata_0_ctr_T_17, 1)
node _update_wdata_0_ctr_T_19 = mux(_update_wdata_0_ctr_T_16, UInt<3>(0h7), _update_wdata_0_ctr_T_18)
node _update_wdata_0_ctr_T_20 = mux(_update_wdata_0_ctr_T_11, _update_wdata_0_ctr_T_15, _update_wdata_0_ctr_T_19)
node _update_wdata_0_ctr_T_21 = mux(wrbypass_hit, _update_wdata_0_ctr_T_10, _update_wdata_0_ctr_T_20)
node _update_wdata_0_ctr_T_22 = mux(io.update_alloc[0], _update_wdata_0_ctr_T, _update_wdata_0_ctr_T_21)
connect update_wdata[0].ctr, _update_wdata_0_ctr_T_22
connect update_wdata[0].valid, UInt<1>(0h1)
connect update_wdata[0].tag, update_tag
node _update_hi_wdata_0_T = bits(io.update_u[0], 1, 1)
connect update_hi_wdata[0], _update_hi_wdata_0_T
node _update_lo_wdata_0_T = bits(io.update_u[0], 0, 0)
connect update_lo_wdata[0], _update_lo_wdata_0_T
node _update_wdata_1_ctr_T = mux(io.update_taken[1], UInt<3>(0h4), UInt<2>(0h3))
node _update_wdata_1_ctr_T_1 = eq(io.update_taken[1], UInt<1>(0h0))
node _update_wdata_1_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h0))
node _update_wdata_1_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1))
node _update_wdata_1_ctr_T_4 = tail(_update_wdata_1_ctr_T_3, 1)
node _update_wdata_1_ctr_T_5 = mux(_update_wdata_1_ctr_T_2, UInt<1>(0h0), _update_wdata_1_ctr_T_4)
node _update_wdata_1_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][1], UInt<3>(0h7))
node _update_wdata_1_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][1], UInt<1>(0h1))
node _update_wdata_1_ctr_T_8 = tail(_update_wdata_1_ctr_T_7, 1)
node _update_wdata_1_ctr_T_9 = mux(_update_wdata_1_ctr_T_6, UInt<3>(0h7), _update_wdata_1_ctr_T_8)
node _update_wdata_1_ctr_T_10 = mux(_update_wdata_1_ctr_T_1, _update_wdata_1_ctr_T_5, _update_wdata_1_ctr_T_9)
node _update_wdata_1_ctr_T_11 = eq(io.update_taken[1], UInt<1>(0h0))
node _update_wdata_1_ctr_T_12 = eq(io.update_old_ctr[1], UInt<1>(0h0))
node _update_wdata_1_ctr_T_13 = sub(io.update_old_ctr[1], UInt<1>(0h1))
node _update_wdata_1_ctr_T_14 = tail(_update_wdata_1_ctr_T_13, 1)
node _update_wdata_1_ctr_T_15 = mux(_update_wdata_1_ctr_T_12, UInt<1>(0h0), _update_wdata_1_ctr_T_14)
node _update_wdata_1_ctr_T_16 = eq(io.update_old_ctr[1], UInt<3>(0h7))
node _update_wdata_1_ctr_T_17 = add(io.update_old_ctr[1], UInt<1>(0h1))
node _update_wdata_1_ctr_T_18 = tail(_update_wdata_1_ctr_T_17, 1)
node _update_wdata_1_ctr_T_19 = mux(_update_wdata_1_ctr_T_16, UInt<3>(0h7), _update_wdata_1_ctr_T_18)
node _update_wdata_1_ctr_T_20 = mux(_update_wdata_1_ctr_T_11, _update_wdata_1_ctr_T_15, _update_wdata_1_ctr_T_19)
node _update_wdata_1_ctr_T_21 = mux(wrbypass_hit, _update_wdata_1_ctr_T_10, _update_wdata_1_ctr_T_20)
node _update_wdata_1_ctr_T_22 = mux(io.update_alloc[1], _update_wdata_1_ctr_T, _update_wdata_1_ctr_T_21)
connect update_wdata[1].ctr, _update_wdata_1_ctr_T_22
connect update_wdata[1].valid, UInt<1>(0h1)
connect update_wdata[1].tag, update_tag
node _update_hi_wdata_1_T = bits(io.update_u[1], 1, 1)
connect update_hi_wdata[1], _update_hi_wdata_1_T
node _update_lo_wdata_1_T = bits(io.update_u[1], 0, 0)
connect update_lo_wdata[1], _update_lo_wdata_1_T
node _update_wdata_2_ctr_T = mux(io.update_taken[2], UInt<3>(0h4), UInt<2>(0h3))
node _update_wdata_2_ctr_T_1 = eq(io.update_taken[2], UInt<1>(0h0))
node _update_wdata_2_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h0))
node _update_wdata_2_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1))
node _update_wdata_2_ctr_T_4 = tail(_update_wdata_2_ctr_T_3, 1)
node _update_wdata_2_ctr_T_5 = mux(_update_wdata_2_ctr_T_2, UInt<1>(0h0), _update_wdata_2_ctr_T_4)
node _update_wdata_2_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][2], UInt<3>(0h7))
node _update_wdata_2_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][2], UInt<1>(0h1))
node _update_wdata_2_ctr_T_8 = tail(_update_wdata_2_ctr_T_7, 1)
node _update_wdata_2_ctr_T_9 = mux(_update_wdata_2_ctr_T_6, UInt<3>(0h7), _update_wdata_2_ctr_T_8)
node _update_wdata_2_ctr_T_10 = mux(_update_wdata_2_ctr_T_1, _update_wdata_2_ctr_T_5, _update_wdata_2_ctr_T_9)
node _update_wdata_2_ctr_T_11 = eq(io.update_taken[2], UInt<1>(0h0))
node _update_wdata_2_ctr_T_12 = eq(io.update_old_ctr[2], UInt<1>(0h0))
node _update_wdata_2_ctr_T_13 = sub(io.update_old_ctr[2], UInt<1>(0h1))
node _update_wdata_2_ctr_T_14 = tail(_update_wdata_2_ctr_T_13, 1)
node _update_wdata_2_ctr_T_15 = mux(_update_wdata_2_ctr_T_12, UInt<1>(0h0), _update_wdata_2_ctr_T_14)
node _update_wdata_2_ctr_T_16 = eq(io.update_old_ctr[2], UInt<3>(0h7))
node _update_wdata_2_ctr_T_17 = add(io.update_old_ctr[2], UInt<1>(0h1))
node _update_wdata_2_ctr_T_18 = tail(_update_wdata_2_ctr_T_17, 1)
node _update_wdata_2_ctr_T_19 = mux(_update_wdata_2_ctr_T_16, UInt<3>(0h7), _update_wdata_2_ctr_T_18)
node _update_wdata_2_ctr_T_20 = mux(_update_wdata_2_ctr_T_11, _update_wdata_2_ctr_T_15, _update_wdata_2_ctr_T_19)
node _update_wdata_2_ctr_T_21 = mux(wrbypass_hit, _update_wdata_2_ctr_T_10, _update_wdata_2_ctr_T_20)
node _update_wdata_2_ctr_T_22 = mux(io.update_alloc[2], _update_wdata_2_ctr_T, _update_wdata_2_ctr_T_21)
connect update_wdata[2].ctr, _update_wdata_2_ctr_T_22
connect update_wdata[2].valid, UInt<1>(0h1)
connect update_wdata[2].tag, update_tag
node _update_hi_wdata_2_T = bits(io.update_u[2], 1, 1)
connect update_hi_wdata[2], _update_hi_wdata_2_T
node _update_lo_wdata_2_T = bits(io.update_u[2], 0, 0)
connect update_lo_wdata[2], _update_lo_wdata_2_T
node _update_wdata_3_ctr_T = mux(io.update_taken[3], UInt<3>(0h4), UInt<2>(0h3))
node _update_wdata_3_ctr_T_1 = eq(io.update_taken[3], UInt<1>(0h0))
node _update_wdata_3_ctr_T_2 = eq(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h0))
node _update_wdata_3_ctr_T_3 = sub(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1))
node _update_wdata_3_ctr_T_4 = tail(_update_wdata_3_ctr_T_3, 1)
node _update_wdata_3_ctr_T_5 = mux(_update_wdata_3_ctr_T_2, UInt<1>(0h0), _update_wdata_3_ctr_T_4)
node _update_wdata_3_ctr_T_6 = eq(wrbypass[wrbypass_hit_idx][3], UInt<3>(0h7))
node _update_wdata_3_ctr_T_7 = add(wrbypass[wrbypass_hit_idx][3], UInt<1>(0h1))
node _update_wdata_3_ctr_T_8 = tail(_update_wdata_3_ctr_T_7, 1)
node _update_wdata_3_ctr_T_9 = mux(_update_wdata_3_ctr_T_6, UInt<3>(0h7), _update_wdata_3_ctr_T_8)
node _update_wdata_3_ctr_T_10 = mux(_update_wdata_3_ctr_T_1, _update_wdata_3_ctr_T_5, _update_wdata_3_ctr_T_9)
node _update_wdata_3_ctr_T_11 = eq(io.update_taken[3], UInt<1>(0h0))
node _update_wdata_3_ctr_T_12 = eq(io.update_old_ctr[3], UInt<1>(0h0))
node _update_wdata_3_ctr_T_13 = sub(io.update_old_ctr[3], UInt<1>(0h1))
node _update_wdata_3_ctr_T_14 = tail(_update_wdata_3_ctr_T_13, 1)
node _update_wdata_3_ctr_T_15 = mux(_update_wdata_3_ctr_T_12, UInt<1>(0h0), _update_wdata_3_ctr_T_14)
node _update_wdata_3_ctr_T_16 = eq(io.update_old_ctr[3], UInt<3>(0h7))
node _update_wdata_3_ctr_T_17 = add(io.update_old_ctr[3], UInt<1>(0h1))
node _update_wdata_3_ctr_T_18 = tail(_update_wdata_3_ctr_T_17, 1)
node _update_wdata_3_ctr_T_19 = mux(_update_wdata_3_ctr_T_16, UInt<3>(0h7), _update_wdata_3_ctr_T_18)
node _update_wdata_3_ctr_T_20 = mux(_update_wdata_3_ctr_T_11, _update_wdata_3_ctr_T_15, _update_wdata_3_ctr_T_19)
node _update_wdata_3_ctr_T_21 = mux(wrbypass_hit, _update_wdata_3_ctr_T_10, _update_wdata_3_ctr_T_20)
node _update_wdata_3_ctr_T_22 = mux(io.update_alloc[3], _update_wdata_3_ctr_T, _update_wdata_3_ctr_T_21)
connect update_wdata[3].ctr, _update_wdata_3_ctr_T_22
connect update_wdata[3].valid, UInt<1>(0h1)
connect update_wdata[3].tag, update_tag
node _update_hi_wdata_3_T = bits(io.update_u[3], 1, 1)
connect update_hi_wdata[3], _update_hi_wdata_3_T
node _update_lo_wdata_3_T = bits(io.update_u[3], 0, 0)
connect update_lo_wdata[3], _update_lo_wdata_3_T
node _T_42 = or(io.update_mask[0], io.update_mask[1])
node _T_43 = or(_T_42, io.update_mask[2])
node _T_44 = or(_T_43, io.update_mask[3])
when _T_44 :
node _T_45 = or(wrbypass_hits[0], wrbypass_hits[1])
when _T_45 :
wire _WIRE_4 : UInt<3>[4]
connect _WIRE_4[0], update_wdata[0].ctr
connect _WIRE_4[1], update_wdata[1].ctr
connect _WIRE_4[2], update_wdata[2].ctr
connect _WIRE_4[3], update_wdata[3].ctr
connect wrbypass[wrbypass_hit_idx], _WIRE_4
else :
wire _WIRE_5 : UInt<3>[4]
connect _WIRE_5[0], update_wdata[0].ctr
connect _WIRE_5[1], update_wdata[1].ctr
connect _WIRE_5[2], update_wdata[2].ctr
connect _WIRE_5[3], update_wdata[3].ctr
connect wrbypass[wrbypass_enq_idx], _WIRE_5
connect wrbypass_tags[wrbypass_enq_idx], update_tag
connect wrbypass_idxs[wrbypass_enq_idx], update_idx
node _wrbypass_enq_idx_T = add(wrbypass_enq_idx, UInt<1>(0h1))
node _wrbypass_enq_idx_T_1 = tail(_wrbypass_enq_idx_T, 1)
node _wrbypass_enq_idx_T_2 = bits(_wrbypass_enq_idx_T_1, 0, 0)
connect wrbypass_enq_idx, _wrbypass_enq_idx_T_2 | module TageTable_14( // @[tage.scala:24:7]
input clock, // @[tage.scala:24:7]
input reset, // @[tage.scala:24:7]
input io_f1_req_valid, // @[tage.scala:31:14]
input [39:0] io_f1_req_pc, // @[tage.scala:31:14]
input [63:0] io_f1_req_ghist, // @[tage.scala:31:14]
output io_f3_resp_0_valid, // @[tage.scala:31:14]
output [2:0] io_f3_resp_0_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f3_resp_0_bits_u, // @[tage.scala:31:14]
output io_f3_resp_1_valid, // @[tage.scala:31:14]
output [2:0] io_f3_resp_1_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f3_resp_1_bits_u, // @[tage.scala:31:14]
output io_f3_resp_2_valid, // @[tage.scala:31:14]
output [2:0] io_f3_resp_2_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f3_resp_2_bits_u, // @[tage.scala:31:14]
output io_f3_resp_3_valid, // @[tage.scala:31:14]
output [2:0] io_f3_resp_3_bits_ctr, // @[tage.scala:31:14]
output [1:0] io_f3_resp_3_bits_u, // @[tage.scala:31:14]
input io_update_mask_0, // @[tage.scala:31:14]
input io_update_mask_1, // @[tage.scala:31:14]
input io_update_mask_2, // @[tage.scala:31:14]
input io_update_mask_3, // @[tage.scala:31:14]
input io_update_taken_0, // @[tage.scala:31:14]
input io_update_taken_1, // @[tage.scala:31:14]
input io_update_taken_2, // @[tage.scala:31:14]
input io_update_taken_3, // @[tage.scala:31:14]
input io_update_alloc_0, // @[tage.scala:31:14]
input io_update_alloc_1, // @[tage.scala:31:14]
input io_update_alloc_2, // @[tage.scala:31:14]
input io_update_alloc_3, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_0, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_1, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_2, // @[tage.scala:31:14]
input [2:0] io_update_old_ctr_3, // @[tage.scala:31:14]
input [39:0] io_update_pc, // @[tage.scala:31:14]
input [63:0] io_update_hist, // @[tage.scala:31:14]
input io_update_u_mask_0, // @[tage.scala:31:14]
input io_update_u_mask_1, // @[tage.scala:31:14]
input io_update_u_mask_2, // @[tage.scala:31:14]
input io_update_u_mask_3, // @[tage.scala:31:14]
input [1:0] io_update_u_0, // @[tage.scala:31:14]
input [1:0] io_update_u_1, // @[tage.scala:31:14]
input [1:0] io_update_u_2, // @[tage.scala:31:14]
input [1:0] io_update_u_3 // @[tage.scala:31:14]
);
wire lo_us_MPORT_2_data_3; // @[tage.scala:137:8]
wire lo_us_MPORT_2_data_2; // @[tage.scala:137:8]
wire lo_us_MPORT_2_data_1; // @[tage.scala:137:8]
wire lo_us_MPORT_2_data_0; // @[tage.scala:137:8]
wire hi_us_MPORT_1_data_3; // @[tage.scala:130:8]
wire hi_us_MPORT_1_data_2; // @[tage.scala:130:8]
wire hi_us_MPORT_1_data_1; // @[tage.scala:130:8]
wire hi_us_MPORT_1_data_0; // @[tage.scala:130:8]
wire [11:0] table_MPORT_data_3; // @[tage.scala:123:8]
wire [11:0] table_MPORT_data_2; // @[tage.scala:123:8]
wire [11:0] table_MPORT_data_1; // @[tage.scala:123:8]
wire [11:0] table_MPORT_data_0; // @[tage.scala:123:8]
wire _s2_req_rtage_WIRE_7_valid; // @[tage.scala:97:87]
wire [7:0] _s2_req_rtage_WIRE_7_tag; // @[tage.scala:97:87]
wire [2:0] _s2_req_rtage_WIRE_7_ctr; // @[tage.scala:97:87]
wire _s2_req_rtage_WIRE_5_valid; // @[tage.scala:97:87]
wire [7:0] _s2_req_rtage_WIRE_5_tag; // @[tage.scala:97:87]
wire [2:0] _s2_req_rtage_WIRE_5_ctr; // @[tage.scala:97:87]
wire _s2_req_rtage_WIRE_3_valid; // @[tage.scala:97:87]
wire [7:0] _s2_req_rtage_WIRE_3_tag; // @[tage.scala:97:87]
wire [2:0] _s2_req_rtage_WIRE_3_ctr; // @[tage.scala:97:87]
wire _s2_req_rtage_WIRE_1_valid; // @[tage.scala:97:87]
wire [7:0] _s2_req_rtage_WIRE_1_tag; // @[tage.scala:97:87]
wire [2:0] _s2_req_rtage_WIRE_1_ctr; // @[tage.scala:97:87]
wire [47:0] _table_R0_data; // @[tage.scala:91:27]
wire [3:0] _lo_us_R0_data; // @[tage.scala:90:27]
wire [3:0] _hi_us_R0_data; // @[tage.scala:89:27]
wire io_f1_req_valid_0 = io_f1_req_valid; // @[tage.scala:24:7]
wire [39:0] io_f1_req_pc_0 = io_f1_req_pc; // @[tage.scala:24:7]
wire [63:0] io_f1_req_ghist_0 = io_f1_req_ghist; // @[tage.scala:24:7]
wire io_update_mask_0_0 = io_update_mask_0; // @[tage.scala:24:7]
wire io_update_mask_1_0 = io_update_mask_1; // @[tage.scala:24:7]
wire io_update_mask_2_0 = io_update_mask_2; // @[tage.scala:24:7]
wire io_update_mask_3_0 = io_update_mask_3; // @[tage.scala:24:7]
wire io_update_taken_0_0 = io_update_taken_0; // @[tage.scala:24:7]
wire io_update_taken_1_0 = io_update_taken_1; // @[tage.scala:24:7]
wire io_update_taken_2_0 = io_update_taken_2; // @[tage.scala:24:7]
wire io_update_taken_3_0 = io_update_taken_3; // @[tage.scala:24:7]
wire io_update_alloc_0_0 = io_update_alloc_0; // @[tage.scala:24:7]
wire io_update_alloc_1_0 = io_update_alloc_1; // @[tage.scala:24:7]
wire io_update_alloc_2_0 = io_update_alloc_2; // @[tage.scala:24:7]
wire io_update_alloc_3_0 = io_update_alloc_3; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_0_0 = io_update_old_ctr_0; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_1_0 = io_update_old_ctr_1; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_2_0 = io_update_old_ctr_2; // @[tage.scala:24:7]
wire [2:0] io_update_old_ctr_3_0 = io_update_old_ctr_3; // @[tage.scala:24:7]
wire [39:0] io_update_pc_0 = io_update_pc; // @[tage.scala:24:7]
wire [63:0] io_update_hist_0 = io_update_hist; // @[tage.scala:24:7]
wire io_update_u_mask_0_0 = io_update_u_mask_0; // @[tage.scala:24:7]
wire io_update_u_mask_1_0 = io_update_u_mask_1; // @[tage.scala:24:7]
wire io_update_u_mask_2_0 = io_update_u_mask_2; // @[tage.scala:24:7]
wire io_update_u_mask_3_0 = io_update_u_mask_3; // @[tage.scala:24:7]
wire [1:0] io_update_u_0_0 = io_update_u_0; // @[tage.scala:24:7]
wire [1:0] io_update_u_1_0 = io_update_u_1; // @[tage.scala:24:7]
wire [1:0] io_update_u_2_0 = io_update_u_2; // @[tage.scala:24:7]
wire [1:0] io_update_u_3_0 = io_update_u_3; // @[tage.scala:24:7]
wire update_wdata_0_valid = 1'h1; // @[tage.scala:119:26]
wire update_wdata_1_valid = 1'h1; // @[tage.scala:119:26]
wire update_wdata_2_valid = 1'h1; // @[tage.scala:119:26]
wire update_wdata_3_valid = 1'h1; // @[tage.scala:119:26]
wire [2:0] io_f3_resp_0_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f3_resp_0_bits_u_0; // @[tage.scala:24:7]
wire io_f3_resp_0_valid_0; // @[tage.scala:24:7]
wire [2:0] io_f3_resp_1_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f3_resp_1_bits_u_0; // @[tage.scala:24:7]
wire io_f3_resp_1_valid_0; // @[tage.scala:24:7]
wire [2:0] io_f3_resp_2_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f3_resp_2_bits_u_0; // @[tage.scala:24:7]
wire io_f3_resp_2_valid_0; // @[tage.scala:24:7]
wire [2:0] io_f3_resp_3_bits_ctr_0; // @[tage.scala:24:7]
wire [1:0] io_f3_resp_3_bits_u_0; // @[tage.scala:24:7]
wire io_f3_resp_3_valid_0; // @[tage.scala:24:7]
reg doing_reset; // @[tage.scala:72:28]
reg [7:0] reset_idx; // @[tage.scala:73:26]
wire [8:0] _reset_idx_T = {1'h0, reset_idx} + {8'h0, doing_reset}; // @[tage.scala:72:28, :73:26, :74:26]
wire [7:0] _reset_idx_T_1 = _reset_idx_T[7:0]; // @[tage.scala:74:26]
wire [7:0] idx_history = io_f1_req_ghist_0[7:0]; // @[tage.scala:24:7, :53:11]
wire [7:0] tag_history = io_f1_req_ghist_0[7:0]; // @[tage.scala:24:7, :53:11]
wire [27:0] _tag_T = io_f1_req_pc_0[39:12]; // @[frontend.scala:162:35]
wire [35:0] _idx_T = {_tag_T, io_f1_req_pc_0[11:4] ^ idx_history}; // @[frontend.scala:162:35]
wire [7:0] s1_hashed_idx = _idx_T[7:0]; // @[tage.scala:60:{29,43}]
wire [7:0] _s2_req_rtage_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :97:40]
wire [7:0] _s2_req_rhius_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :98:32]
wire [7:0] _s2_req_rlous_WIRE = s1_hashed_idx; // @[tage.scala:60:43, :99:32]
wire [27:0] _tag_T_1 = {_tag_T[27:8], _tag_T[7:0] ^ tag_history}; // @[tage.scala:53:11, :62:{30,50}]
wire [7:0] s1_tag = _tag_T_1[7:0]; // @[tage.scala:62:{50,64}]
wire [11:0] _s2_req_rtage_WIRE_2 = _table_R0_data[11:0]; // @[tage.scala:91:27, :97:87]
wire [11:0] _s2_req_rtage_WIRE_4 = _table_R0_data[23:12]; // @[tage.scala:91:27, :97:87]
wire [11:0] _s2_req_rtage_WIRE_6 = _table_R0_data[35:24]; // @[tage.scala:91:27, :97:87]
wire [11:0] _s2_req_rtage_WIRE_8 = _table_R0_data[47:36]; // @[tage.scala:91:27, :97:87]
reg [7:0] s2_tag; // @[tage.scala:95:29]
wire _s2_req_rtage_T_2; // @[tage.scala:97:87]
wire [7:0] _s2_req_rtage_T_1; // @[tage.scala:97:87]
wire s2_req_rtage_0_valid = _s2_req_rtage_WIRE_1_valid; // @[tage.scala:97:{29,87}]
wire [2:0] _s2_req_rtage_T; // @[tage.scala:97:87]
wire [7:0] s2_req_rtage_0_tag = _s2_req_rtage_WIRE_1_tag; // @[tage.scala:97:{29,87}]
wire [2:0] s2_req_rtage_0_ctr = _s2_req_rtage_WIRE_1_ctr; // @[tage.scala:97:{29,87}]
assign _s2_req_rtage_T = _s2_req_rtage_WIRE_2[2:0]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_1_ctr = _s2_req_rtage_T; // @[tage.scala:97:87]
assign _s2_req_rtage_T_1 = _s2_req_rtage_WIRE_2[10:3]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_1_tag = _s2_req_rtage_T_1; // @[tage.scala:97:87]
assign _s2_req_rtage_T_2 = _s2_req_rtage_WIRE_2[11]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_1_valid = _s2_req_rtage_T_2; // @[tage.scala:97:87]
wire _s2_req_rtage_T_5; // @[tage.scala:97:87]
wire [7:0] _s2_req_rtage_T_4; // @[tage.scala:97:87]
wire s2_req_rtage_1_valid = _s2_req_rtage_WIRE_3_valid; // @[tage.scala:97:{29,87}]
wire [2:0] _s2_req_rtage_T_3; // @[tage.scala:97:87]
wire [7:0] s2_req_rtage_1_tag = _s2_req_rtage_WIRE_3_tag; // @[tage.scala:97:{29,87}]
wire [2:0] s2_req_rtage_1_ctr = _s2_req_rtage_WIRE_3_ctr; // @[tage.scala:97:{29,87}]
assign _s2_req_rtage_T_3 = _s2_req_rtage_WIRE_4[2:0]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_3_ctr = _s2_req_rtage_T_3; // @[tage.scala:97:87]
assign _s2_req_rtage_T_4 = _s2_req_rtage_WIRE_4[10:3]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_3_tag = _s2_req_rtage_T_4; // @[tage.scala:97:87]
assign _s2_req_rtage_T_5 = _s2_req_rtage_WIRE_4[11]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_3_valid = _s2_req_rtage_T_5; // @[tage.scala:97:87]
wire _s2_req_rtage_T_8; // @[tage.scala:97:87]
wire [7:0] _s2_req_rtage_T_7; // @[tage.scala:97:87]
wire s2_req_rtage_2_valid = _s2_req_rtage_WIRE_5_valid; // @[tage.scala:97:{29,87}]
wire [2:0] _s2_req_rtage_T_6; // @[tage.scala:97:87]
wire [7:0] s2_req_rtage_2_tag = _s2_req_rtage_WIRE_5_tag; // @[tage.scala:97:{29,87}]
wire [2:0] s2_req_rtage_2_ctr = _s2_req_rtage_WIRE_5_ctr; // @[tage.scala:97:{29,87}]
assign _s2_req_rtage_T_6 = _s2_req_rtage_WIRE_6[2:0]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_5_ctr = _s2_req_rtage_T_6; // @[tage.scala:97:87]
assign _s2_req_rtage_T_7 = _s2_req_rtage_WIRE_6[10:3]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_5_tag = _s2_req_rtage_T_7; // @[tage.scala:97:87]
assign _s2_req_rtage_T_8 = _s2_req_rtage_WIRE_6[11]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_5_valid = _s2_req_rtage_T_8; // @[tage.scala:97:87]
wire _s2_req_rtage_T_11; // @[tage.scala:97:87]
wire [7:0] _s2_req_rtage_T_10; // @[tage.scala:97:87]
wire s2_req_rtage_3_valid = _s2_req_rtage_WIRE_7_valid; // @[tage.scala:97:{29,87}]
wire [2:0] _s2_req_rtage_T_9; // @[tage.scala:97:87]
wire [7:0] s2_req_rtage_3_tag = _s2_req_rtage_WIRE_7_tag; // @[tage.scala:97:{29,87}]
wire [2:0] s2_req_rtage_3_ctr = _s2_req_rtage_WIRE_7_ctr; // @[tage.scala:97:{29,87}]
assign _s2_req_rtage_T_9 = _s2_req_rtage_WIRE_8[2:0]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_7_ctr = _s2_req_rtage_T_9; // @[tage.scala:97:87]
assign _s2_req_rtage_T_10 = _s2_req_rtage_WIRE_8[10:3]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_7_tag = _s2_req_rtage_T_10; // @[tage.scala:97:87]
assign _s2_req_rtage_T_11 = _s2_req_rtage_WIRE_8[11]; // @[tage.scala:97:87]
assign _s2_req_rtage_WIRE_7_valid = _s2_req_rtage_T_11; // @[tage.scala:97:87]
wire _s2_req_rhits_T = s2_req_rtage_0_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69]
wire _s2_req_rhits_T_1 = s2_req_rtage_0_valid & _s2_req_rhits_T; // @[tage.scala:97:29, :100:{60,69}]
wire _s2_req_rhits_T_2 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_3 = _s2_req_rhits_T_1 & _s2_req_rhits_T_2; // @[tage.scala:100:{60,80,83}]
wire s2_req_rhits_0 = _s2_req_rhits_T_3; // @[tage.scala:100:{29,80}]
wire _s2_req_rhits_T_4 = s2_req_rtage_1_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69]
wire _s2_req_rhits_T_5 = s2_req_rtage_1_valid & _s2_req_rhits_T_4; // @[tage.scala:97:29, :100:{60,69}]
wire _s2_req_rhits_T_6 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_7 = _s2_req_rhits_T_5 & _s2_req_rhits_T_6; // @[tage.scala:100:{60,80,83}]
wire s2_req_rhits_1 = _s2_req_rhits_T_7; // @[tage.scala:100:{29,80}]
wire _s2_req_rhits_T_8 = s2_req_rtage_2_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69]
wire _s2_req_rhits_T_9 = s2_req_rtage_2_valid & _s2_req_rhits_T_8; // @[tage.scala:97:29, :100:{60,69}]
wire _s2_req_rhits_T_10 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_11 = _s2_req_rhits_T_9 & _s2_req_rhits_T_10; // @[tage.scala:100:{60,80,83}]
wire s2_req_rhits_2 = _s2_req_rhits_T_11; // @[tage.scala:100:{29,80}]
wire _s2_req_rhits_T_12 = s2_req_rtage_3_tag == s2_tag; // @[tage.scala:95:29, :97:29, :100:69]
wire _s2_req_rhits_T_13 = s2_req_rtage_3_valid & _s2_req_rhits_T_12; // @[tage.scala:97:29, :100:{60,69}]
wire _s2_req_rhits_T_14 = ~doing_reset; // @[tage.scala:72:28, :100:83]
wire _s2_req_rhits_T_15 = _s2_req_rhits_T_13 & _s2_req_rhits_T_14; // @[tage.scala:100:{60,80,83}]
wire s2_req_rhits_3 = _s2_req_rhits_T_15; // @[tage.scala:100:{29,80}]
reg io_f3_resp_0_valid_REG; // @[tage.scala:104:38]
assign io_f3_resp_0_valid_0 = io_f3_resp_0_valid_REG; // @[tage.scala:24:7, :104:38]
wire [1:0] _io_f3_resp_0_bits_u_T = {_hi_us_R0_data[0], _lo_us_R0_data[0]}; // @[tage.scala:89:27, :90:27, :105:42]
reg [1:0] io_f3_resp_0_bits_u_REG; // @[tage.scala:105:38]
assign io_f3_resp_0_bits_u_0 = io_f3_resp_0_bits_u_REG; // @[tage.scala:24:7, :105:38]
reg [2:0] io_f3_resp_0_bits_ctr_REG; // @[tage.scala:106:38]
assign io_f3_resp_0_bits_ctr_0 = io_f3_resp_0_bits_ctr_REG; // @[tage.scala:24:7, :106:38]
reg io_f3_resp_1_valid_REG; // @[tage.scala:104:38]
assign io_f3_resp_1_valid_0 = io_f3_resp_1_valid_REG; // @[tage.scala:24:7, :104:38]
wire [1:0] _io_f3_resp_1_bits_u_T = {_hi_us_R0_data[1], _lo_us_R0_data[1]}; // @[tage.scala:89:27, :90:27, :105:42]
reg [1:0] io_f3_resp_1_bits_u_REG; // @[tage.scala:105:38]
assign io_f3_resp_1_bits_u_0 = io_f3_resp_1_bits_u_REG; // @[tage.scala:24:7, :105:38]
reg [2:0] io_f3_resp_1_bits_ctr_REG; // @[tage.scala:106:38]
assign io_f3_resp_1_bits_ctr_0 = io_f3_resp_1_bits_ctr_REG; // @[tage.scala:24:7, :106:38]
reg io_f3_resp_2_valid_REG; // @[tage.scala:104:38]
assign io_f3_resp_2_valid_0 = io_f3_resp_2_valid_REG; // @[tage.scala:24:7, :104:38]
wire [1:0] _io_f3_resp_2_bits_u_T = {_hi_us_R0_data[2], _lo_us_R0_data[2]}; // @[tage.scala:89:27, :90:27, :105:42]
reg [1:0] io_f3_resp_2_bits_u_REG; // @[tage.scala:105:38]
assign io_f3_resp_2_bits_u_0 = io_f3_resp_2_bits_u_REG; // @[tage.scala:24:7, :105:38]
reg [2:0] io_f3_resp_2_bits_ctr_REG; // @[tage.scala:106:38]
assign io_f3_resp_2_bits_ctr_0 = io_f3_resp_2_bits_ctr_REG; // @[tage.scala:24:7, :106:38]
reg io_f3_resp_3_valid_REG; // @[tage.scala:104:38]
assign io_f3_resp_3_valid_0 = io_f3_resp_3_valid_REG; // @[tage.scala:24:7, :104:38]
wire [1:0] _io_f3_resp_3_bits_u_T = {_hi_us_R0_data[3], _lo_us_R0_data[3]}; // @[tage.scala:89:27, :90:27, :105:42]
reg [1:0] io_f3_resp_3_bits_u_REG; // @[tage.scala:105:38]
assign io_f3_resp_3_bits_u_0 = io_f3_resp_3_bits_u_REG; // @[tage.scala:24:7, :105:38]
reg [2:0] io_f3_resp_3_bits_ctr_REG; // @[tage.scala:106:38]
assign io_f3_resp_3_bits_ctr_0 = io_f3_resp_3_bits_ctr_REG; // @[tage.scala:24:7, :106:38]
reg [19:0] clear_u_ctr; // @[tage.scala:109:28]
wire [20:0] _clear_u_ctr_T = {1'h0, clear_u_ctr} + 21'h1; // @[tage.scala:109:28, :110:85]
wire [19:0] _clear_u_ctr_T_1 = _clear_u_ctr_T[19:0]; // @[tage.scala:110:85]
wire [10:0] _doing_clear_u_T = clear_u_ctr[10:0]; // @[tage.scala:109:28, :112:34]
wire doing_clear_u = _doing_clear_u_T == 11'h0; // @[tage.scala:112:{34,61}]
wire _doing_clear_u_hi_T = clear_u_ctr[19]; // @[tage.scala:109:28, :113:54]
wire _doing_clear_u_lo_T = clear_u_ctr[19]; // @[tage.scala:109:28, :113:54, :114:54]
wire _doing_clear_u_hi_T_1 = _doing_clear_u_hi_T; // @[tage.scala:113:{54,95}]
wire doing_clear_u_hi = doing_clear_u & _doing_clear_u_hi_T_1; // @[tage.scala:112:61, :113:{40,95}]
wire _doing_clear_u_lo_T_1 = ~_doing_clear_u_lo_T; // @[tage.scala:114:{54,95}]
wire doing_clear_u_lo = doing_clear_u & _doing_clear_u_lo_T_1; // @[tage.scala:112:61, :114:{40,95}]
wire [8:0] clear_u_idx = clear_u_ctr[19:11]; // @[tage.scala:109:28, :115:33]
wire [7:0] idx_history_1 = io_update_hist_0[7:0]; // @[tage.scala:24:7, :53:11]
wire [7:0] tag_history_1 = io_update_hist_0[7:0]; // @[tage.scala:24:7, :53:11]
wire [27:0] _tag_T_2 = io_update_pc_0[39:12]; // @[frontend.scala:162:35]
wire [35:0] _idx_T_1 = {_tag_T_2, io_update_pc_0[11:4] ^ idx_history_1}; // @[frontend.scala:162:35]
wire [7:0] update_idx = _idx_T_1[7:0]; // @[tage.scala:60:{29,43}]
wire [27:0] _tag_T_3 = {_tag_T_2[27:8], _tag_T_2[7:0] ^ tag_history_1}; // @[tage.scala:53:11, :62:{30,50}]
wire [7:0] update_tag = _tag_T_3[7:0]; // @[tage.scala:62:{50,64}]
wire [7:0] update_wdata_0_tag = update_tag; // @[tage.scala:62:64, :119:26]
wire [7:0] update_wdata_1_tag = update_tag; // @[tage.scala:62:64, :119:26]
wire [7:0] update_wdata_2_tag = update_tag; // @[tage.scala:62:64, :119:26]
wire [7:0] update_wdata_3_tag = update_tag; // @[tage.scala:62:64, :119:26]
wire [2:0] _update_wdata_0_ctr_T_22; // @[tage.scala:155:33]
wire [2:0] _update_wdata_1_ctr_T_22; // @[tage.scala:155:33]
wire [2:0] _update_wdata_2_ctr_T_22; // @[tage.scala:155:33]
wire [2:0] _update_wdata_3_ctr_T_22; // @[tage.scala:155:33]
wire [2:0] update_wdata_0_ctr; // @[tage.scala:119:26]
wire [2:0] update_wdata_1_ctr; // @[tage.scala:119:26]
wire [2:0] update_wdata_2_ctr; // @[tage.scala:119:26]
wire [2:0] update_wdata_3_ctr; // @[tage.scala:119:26]
wire [8:0] hi = {1'h1, update_wdata_0_tag}; // @[tage.scala:119:26, :123:102]
wire [8:0] hi_1 = {1'h1, update_wdata_1_tag}; // @[tage.scala:119:26, :123:102]
wire [8:0] hi_2 = {1'h1, update_wdata_2_tag}; // @[tage.scala:119:26, :123:102]
wire [8:0] hi_3 = {1'h1, update_wdata_3_tag}; // @[tage.scala:119:26, :123:102]
assign table_MPORT_data_0 = doing_reset ? 12'h0 : {hi, update_wdata_0_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}]
assign table_MPORT_data_1 = doing_reset ? 12'h0 : {hi_1, update_wdata_1_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}]
assign table_MPORT_data_2 = doing_reset ? 12'h0 : {hi_2, update_wdata_2_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}]
assign table_MPORT_data_3 = doing_reset ? 12'h0 : {hi_3, update_wdata_3_ctr}; // @[tage.scala:72:28, :119:26, :123:{8,102}]
wire [1:0] lo = {io_update_mask_1_0, io_update_mask_0_0}; // @[tage.scala:24:7, :124:90]
wire [1:0] hi_4 = {io_update_mask_3_0, io_update_mask_2_0}; // @[tage.scala:24:7, :124:90]
wire _update_hi_wdata_0_T; // @[tage.scala:166:44]
wire _update_hi_wdata_1_T; // @[tage.scala:166:44]
wire _update_hi_wdata_2_T; // @[tage.scala:166:44]
wire _update_hi_wdata_3_T; // @[tage.scala:166:44]
wire update_hi_wdata_0; // @[tage.scala:127:29]
wire update_hi_wdata_1; // @[tage.scala:127:29]
wire update_hi_wdata_2; // @[tage.scala:127:29]
wire update_hi_wdata_3; // @[tage.scala:127:29]
wire _T_20 = doing_reset | doing_clear_u_hi; // @[tage.scala:72:28, :113:40, :130:21]
assign hi_us_MPORT_1_data_0 = ~_T_20 & update_hi_wdata_0; // @[tage.scala:127:29, :130:{8,21}]
assign hi_us_MPORT_1_data_1 = ~_T_20 & update_hi_wdata_1; // @[tage.scala:127:29, :130:{8,21}]
assign hi_us_MPORT_1_data_2 = ~_T_20 & update_hi_wdata_2; // @[tage.scala:127:29, :130:{8,21}]
assign hi_us_MPORT_1_data_3 = ~_T_20 & update_hi_wdata_3; // @[tage.scala:127:29, :130:{8,21}]
wire [1:0] _GEN = {io_update_u_mask_1_0, io_update_u_mask_0_0}; // @[tage.scala:24:7, :131:80]
wire [1:0] lo_1; // @[tage.scala:131:80]
assign lo_1 = _GEN; // @[tage.scala:131:80]
wire [1:0] lo_2; // @[tage.scala:138:80]
assign lo_2 = _GEN; // @[tage.scala:131:80, :138:80]
wire [1:0] _GEN_0 = {io_update_u_mask_3_0, io_update_u_mask_2_0}; // @[tage.scala:24:7, :131:80]
wire [1:0] hi_5; // @[tage.scala:131:80]
assign hi_5 = _GEN_0; // @[tage.scala:131:80]
wire [1:0] hi_6; // @[tage.scala:138:80]
assign hi_6 = _GEN_0; // @[tage.scala:131:80, :138:80]
wire _update_lo_wdata_0_T; // @[tage.scala:167:44]
wire _update_lo_wdata_1_T; // @[tage.scala:167:44]
wire _update_lo_wdata_2_T; // @[tage.scala:167:44]
wire _update_lo_wdata_3_T; // @[tage.scala:167:44]
wire update_lo_wdata_0; // @[tage.scala:134:29]
wire update_lo_wdata_1; // @[tage.scala:134:29]
wire update_lo_wdata_2; // @[tage.scala:134:29]
wire update_lo_wdata_3; // @[tage.scala:134:29]
wire _T_33 = doing_reset | doing_clear_u_lo; // @[tage.scala:72:28, :114:40, :137:21]
assign lo_us_MPORT_2_data_0 = ~_T_33 & update_lo_wdata_0; // @[tage.scala:134:29, :137:{8,21}]
assign lo_us_MPORT_2_data_1 = ~_T_33 & update_lo_wdata_1; // @[tage.scala:134:29, :137:{8,21}]
assign lo_us_MPORT_2_data_2 = ~_T_33 & update_lo_wdata_2; // @[tage.scala:134:29, :137:{8,21}]
assign lo_us_MPORT_2_data_3 = ~_T_33 & update_lo_wdata_3; // @[tage.scala:134:29, :137:{8,21}]
reg [7:0] wrbypass_tags_0; // @[tage.scala:141:29]
reg [7:0] wrbypass_tags_1; // @[tage.scala:141:29]
reg [7:0] wrbypass_idxs_0; // @[tage.scala:142:29]
reg [7:0] wrbypass_idxs_1; // @[tage.scala:142:29]
reg [2:0] wrbypass_0_0; // @[tage.scala:143:29]
reg [2:0] wrbypass_0_1; // @[tage.scala:143:29]
reg [2:0] wrbypass_0_2; // @[tage.scala:143:29]
reg [2:0] wrbypass_0_3; // @[tage.scala:143:29]
reg [2:0] wrbypass_1_0; // @[tage.scala:143:29]
reg [2:0] wrbypass_1_1; // @[tage.scala:143:29]
reg [2:0] wrbypass_1_2; // @[tage.scala:143:29]
reg [2:0] wrbypass_1_3; // @[tage.scala:143:29]
reg wrbypass_enq_idx; // @[tage.scala:144:33]
wire _wrbypass_hits_T = ~doing_reset; // @[tage.scala:72:28, :100:83, :147:5]
wire _wrbypass_hits_T_1 = wrbypass_tags_0 == update_tag; // @[tage.scala:62:64, :141:29, :148:22]
wire _wrbypass_hits_T_2 = _wrbypass_hits_T & _wrbypass_hits_T_1; // @[tage.scala:147:{5,18}, :148:22]
wire _wrbypass_hits_T_3 = wrbypass_idxs_0 == update_idx; // @[tage.scala:60:43, :142:29, :149:22]
wire _wrbypass_hits_T_4 = _wrbypass_hits_T_2 & _wrbypass_hits_T_3; // @[tage.scala:147:18, :148:37, :149:22]
wire wrbypass_hits_0 = _wrbypass_hits_T_4; // @[tage.scala:146:33, :148:37]
wire _wrbypass_hits_T_5 = ~doing_reset; // @[tage.scala:72:28, :100:83, :147:5]
wire _wrbypass_hits_T_6 = wrbypass_tags_1 == update_tag; // @[tage.scala:62:64, :141:29, :148:22]
wire _wrbypass_hits_T_7 = _wrbypass_hits_T_5 & _wrbypass_hits_T_6; // @[tage.scala:147:{5,18}, :148:22]
wire _wrbypass_hits_T_8 = wrbypass_idxs_1 == update_idx; // @[tage.scala:60:43, :142:29, :149:22]
wire _wrbypass_hits_T_9 = _wrbypass_hits_T_7 & _wrbypass_hits_T_8; // @[tage.scala:147:18, :148:37, :149:22]
wire wrbypass_hits_1 = _wrbypass_hits_T_9; // @[tage.scala:146:33, :148:37]
wire wrbypass_hit = wrbypass_hits_0 | wrbypass_hits_1; // @[tage.scala:146:33, :151:48]
wire wrbypass_hit_idx = ~wrbypass_hits_0; // @[Mux.scala:50:70]
wire [2:0] _update_wdata_0_ctr_T = io_update_taken_0_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10]
wire _update_wdata_0_ctr_T_1 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9]
wire [2:0] _GEN_1 = wrbypass_hit_idx ? wrbypass_1_0 : wrbypass_0_0; // @[Mux.scala:50:70]
wire [2:0] _GEN_2 = wrbypass_hit_idx ? wrbypass_1_1 : wrbypass_0_1; // @[Mux.scala:50:70]
wire [2:0] _GEN_3 = wrbypass_hit_idx ? wrbypass_1_2 : wrbypass_0_2; // @[Mux.scala:50:70]
wire [2:0] _GEN_4 = wrbypass_hit_idx ? wrbypass_1_3 : wrbypass_0_3; // @[Mux.scala:50:70]
wire _update_wdata_0_ctr_T_2 = _GEN_1 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_5 = {1'h0, _GEN_1}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_0_ctr_T_3 = _GEN_5 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_4 = _update_wdata_0_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_5 = _update_wdata_0_ctr_T_2 ? 3'h0 : _update_wdata_0_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_0_ctr_T_6 = &_GEN_1; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_0_ctr_T_7 = _GEN_5 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_0_ctr_T_8 = _update_wdata_0_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_0_ctr_T_9 = _update_wdata_0_ctr_T_6 ? 3'h7 : _update_wdata_0_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_0_ctr_T_10 = _update_wdata_0_ctr_T_1 ? _update_wdata_0_ctr_T_5 : _update_wdata_0_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_0_ctr_T_11 = ~io_update_taken_0_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_0_ctr_T_12 = io_update_old_ctr_0_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_6 = {1'h0, io_update_old_ctr_0_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_0_ctr_T_13 = _GEN_6 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_14 = _update_wdata_0_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_0_ctr_T_15 = _update_wdata_0_ctr_T_12 ? 3'h0 : _update_wdata_0_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_0_ctr_T_16 = &io_update_old_ctr_0_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_0_ctr_T_17 = _GEN_6 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_0_ctr_T_18 = _update_wdata_0_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_0_ctr_T_19 = _update_wdata_0_ctr_T_16 ? 3'h7 : _update_wdata_0_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_0_ctr_T_20 = _update_wdata_0_ctr_T_11 ? _update_wdata_0_ctr_T_15 : _update_wdata_0_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_0_ctr_T_21 = wrbypass_hit ? _update_wdata_0_ctr_T_10 : _update_wdata_0_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10]
assign _update_wdata_0_ctr_T_22 = io_update_alloc_0_0 ? _update_wdata_0_ctr_T : _update_wdata_0_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10]
assign update_wdata_0_ctr = _update_wdata_0_ctr_T_22; // @[tage.scala:119:26, :155:33]
assign _update_hi_wdata_0_T = io_update_u_0_0[1]; // @[tage.scala:24:7, :166:44]
assign update_hi_wdata_0 = _update_hi_wdata_0_T; // @[tage.scala:127:29, :166:44]
assign _update_lo_wdata_0_T = io_update_u_0_0[0]; // @[tage.scala:24:7, :167:44]
assign update_lo_wdata_0 = _update_lo_wdata_0_T; // @[tage.scala:134:29, :167:44]
wire [2:0] _update_wdata_1_ctr_T = io_update_taken_1_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10]
wire _update_wdata_1_ctr_T_1 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_1_ctr_T_2 = _GEN_2 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_7 = {1'h0, _GEN_2}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_1_ctr_T_3 = _GEN_7 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_4 = _update_wdata_1_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_5 = _update_wdata_1_ctr_T_2 ? 3'h0 : _update_wdata_1_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_1_ctr_T_6 = &_GEN_2; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_1_ctr_T_7 = _GEN_7 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_1_ctr_T_8 = _update_wdata_1_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_1_ctr_T_9 = _update_wdata_1_ctr_T_6 ? 3'h7 : _update_wdata_1_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_1_ctr_T_10 = _update_wdata_1_ctr_T_1 ? _update_wdata_1_ctr_T_5 : _update_wdata_1_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_1_ctr_T_11 = ~io_update_taken_1_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_1_ctr_T_12 = io_update_old_ctr_1_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_8 = {1'h0, io_update_old_ctr_1_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_1_ctr_T_13 = _GEN_8 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_14 = _update_wdata_1_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_1_ctr_T_15 = _update_wdata_1_ctr_T_12 ? 3'h0 : _update_wdata_1_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_1_ctr_T_16 = &io_update_old_ctr_1_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_1_ctr_T_17 = _GEN_8 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_1_ctr_T_18 = _update_wdata_1_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_1_ctr_T_19 = _update_wdata_1_ctr_T_16 ? 3'h7 : _update_wdata_1_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_1_ctr_T_20 = _update_wdata_1_ctr_T_11 ? _update_wdata_1_ctr_T_15 : _update_wdata_1_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_1_ctr_T_21 = wrbypass_hit ? _update_wdata_1_ctr_T_10 : _update_wdata_1_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10]
assign _update_wdata_1_ctr_T_22 = io_update_alloc_1_0 ? _update_wdata_1_ctr_T : _update_wdata_1_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10]
assign update_wdata_1_ctr = _update_wdata_1_ctr_T_22; // @[tage.scala:119:26, :155:33]
assign _update_hi_wdata_1_T = io_update_u_1_0[1]; // @[tage.scala:24:7, :166:44]
assign update_hi_wdata_1 = _update_hi_wdata_1_T; // @[tage.scala:127:29, :166:44]
assign _update_lo_wdata_1_T = io_update_u_1_0[0]; // @[tage.scala:24:7, :167:44]
assign update_lo_wdata_1 = _update_lo_wdata_1_T; // @[tage.scala:134:29, :167:44]
wire [2:0] _update_wdata_2_ctr_T = io_update_taken_2_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10]
wire _update_wdata_2_ctr_T_1 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_2_ctr_T_2 = _GEN_3 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_9 = {1'h0, _GEN_3}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_2_ctr_T_3 = _GEN_9 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_4 = _update_wdata_2_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_5 = _update_wdata_2_ctr_T_2 ? 3'h0 : _update_wdata_2_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_2_ctr_T_6 = &_GEN_3; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_2_ctr_T_7 = _GEN_9 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_2_ctr_T_8 = _update_wdata_2_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_2_ctr_T_9 = _update_wdata_2_ctr_T_6 ? 3'h7 : _update_wdata_2_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_2_ctr_T_10 = _update_wdata_2_ctr_T_1 ? _update_wdata_2_ctr_T_5 : _update_wdata_2_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_2_ctr_T_11 = ~io_update_taken_2_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_2_ctr_T_12 = io_update_old_ctr_2_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_10 = {1'h0, io_update_old_ctr_2_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_2_ctr_T_13 = _GEN_10 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_14 = _update_wdata_2_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_2_ctr_T_15 = _update_wdata_2_ctr_T_12 ? 3'h0 : _update_wdata_2_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_2_ctr_T_16 = &io_update_old_ctr_2_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_2_ctr_T_17 = _GEN_10 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_2_ctr_T_18 = _update_wdata_2_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_2_ctr_T_19 = _update_wdata_2_ctr_T_16 ? 3'h7 : _update_wdata_2_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_2_ctr_T_20 = _update_wdata_2_ctr_T_11 ? _update_wdata_2_ctr_T_15 : _update_wdata_2_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_2_ctr_T_21 = wrbypass_hit ? _update_wdata_2_ctr_T_10 : _update_wdata_2_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10]
assign _update_wdata_2_ctr_T_22 = io_update_alloc_2_0 ? _update_wdata_2_ctr_T : _update_wdata_2_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10]
assign update_wdata_2_ctr = _update_wdata_2_ctr_T_22; // @[tage.scala:119:26, :155:33]
assign _update_hi_wdata_2_T = io_update_u_2_0[1]; // @[tage.scala:24:7, :166:44]
assign update_hi_wdata_2 = _update_hi_wdata_2_T; // @[tage.scala:127:29, :166:44]
assign _update_lo_wdata_2_T = io_update_u_2_0[0]; // @[tage.scala:24:7, :167:44]
assign update_lo_wdata_2 = _update_lo_wdata_2_T; // @[tage.scala:134:29, :167:44]
wire [2:0] _update_wdata_3_ctr_T = io_update_taken_3_0 ? 3'h4 : 3'h3; // @[tage.scala:24:7, :156:10]
wire _update_wdata_3_ctr_T_1 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_3_ctr_T_2 = _GEN_4 == 3'h0; // @[tage.scala:67:25]
wire [3:0] _GEN_11 = {1'h0, _GEN_4}; // @[tage.scala:67:{25,43}]
wire [3:0] _update_wdata_3_ctr_T_3 = _GEN_11 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_4 = _update_wdata_3_ctr_T_3[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_5 = _update_wdata_3_ctr_T_2 ? 3'h0 : _update_wdata_3_ctr_T_4; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_3_ctr_T_6 = &_GEN_4; // @[tage.scala:67:25, :68:25]
wire [3:0] _update_wdata_3_ctr_T_7 = _GEN_11 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_3_ctr_T_8 = _update_wdata_3_ctr_T_7[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_3_ctr_T_9 = _update_wdata_3_ctr_T_6 ? 3'h7 : _update_wdata_3_ctr_T_8; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_3_ctr_T_10 = _update_wdata_3_ctr_T_1 ? _update_wdata_3_ctr_T_5 : _update_wdata_3_ctr_T_9; // @[tage.scala:67:{8,9,20}, :68:20]
wire _update_wdata_3_ctr_T_11 = ~io_update_taken_3_0; // @[tage.scala:24:7, :67:9]
wire _update_wdata_3_ctr_T_12 = io_update_old_ctr_3_0 == 3'h0; // @[tage.scala:24:7, :67:25]
wire [3:0] _GEN_12 = {1'h0, io_update_old_ctr_3_0}; // @[tage.scala:24:7, :67:43]
wire [3:0] _update_wdata_3_ctr_T_13 = _GEN_12 - 4'h1; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_14 = _update_wdata_3_ctr_T_13[2:0]; // @[tage.scala:67:43]
wire [2:0] _update_wdata_3_ctr_T_15 = _update_wdata_3_ctr_T_12 ? 3'h0 : _update_wdata_3_ctr_T_14; // @[tage.scala:67:{20,25,43}]
wire _update_wdata_3_ctr_T_16 = &io_update_old_ctr_3_0; // @[tage.scala:24:7, :68:25]
wire [3:0] _update_wdata_3_ctr_T_17 = _GEN_12 + 4'h1; // @[tage.scala:67:43, :68:43]
wire [2:0] _update_wdata_3_ctr_T_18 = _update_wdata_3_ctr_T_17[2:0]; // @[tage.scala:68:43]
wire [2:0] _update_wdata_3_ctr_T_19 = _update_wdata_3_ctr_T_16 ? 3'h7 : _update_wdata_3_ctr_T_18; // @[tage.scala:68:{20,25,43}]
wire [2:0] _update_wdata_3_ctr_T_20 = _update_wdata_3_ctr_T_11 ? _update_wdata_3_ctr_T_15 : _update_wdata_3_ctr_T_19; // @[tage.scala:67:{8,9,20}, :68:20]
wire [2:0] _update_wdata_3_ctr_T_21 = wrbypass_hit ? _update_wdata_3_ctr_T_10 : _update_wdata_3_ctr_T_20; // @[tage.scala:67:8, :151:48, :159:10]
assign _update_wdata_3_ctr_T_22 = io_update_alloc_3_0 ? _update_wdata_3_ctr_T : _update_wdata_3_ctr_T_21; // @[tage.scala:24:7, :155:33, :156:10, :159:10]
assign update_wdata_3_ctr = _update_wdata_3_ctr_T_22; // @[tage.scala:119:26, :155:33]
assign _update_hi_wdata_3_T = io_update_u_3_0[1]; // @[tage.scala:24:7, :166:44]
assign update_hi_wdata_3 = _update_hi_wdata_3_T; // @[tage.scala:127:29, :166:44]
assign _update_lo_wdata_3_T = io_update_u_3_0[0]; // @[tage.scala:24:7, :167:44]
assign update_lo_wdata_3 = _update_lo_wdata_3_T; // @[tage.scala:134:29, :167:44]
wire [1:0] _wrbypass_enq_idx_T = {1'h0, wrbypass_enq_idx} + 2'h1; // @[util.scala:203:14]
wire _wrbypass_enq_idx_T_1 = _wrbypass_enq_idx_T[0]; // @[util.scala:203:14]
wire _wrbypass_enq_idx_T_2 = _wrbypass_enq_idx_T_1; // @[util.scala:203:{14,20}]
wire _T_44 = io_update_mask_0_0 | io_update_mask_1_0 | io_update_mask_2_0 | io_update_mask_3_0; // @[tage.scala:24:7, :170:32]
wire _GEN_13 = wrbypass_hit ? wrbypass_hit_idx : wrbypass_enq_idx; // @[Mux.scala:50:70]
wire _GEN_14 = ~_T_44 | wrbypass_hit | wrbypass_enq_idx; // @[tage.scala:141:29, :143:29, :144:33, :151:48, :170:{32,38}, :171:39, :175:39]
wire _GEN_15 = ~_T_44 | wrbypass_hit | ~wrbypass_enq_idx; // @[tage.scala:141:29, :143:29, :144:33, :151:48, :170:{32,38}, :171:39, :175:39]
always @(posedge clock) begin // @[tage.scala:24:7]
if (reset) begin // @[tage.scala:24:7]
doing_reset <= 1'h1; // @[tage.scala:72:28]
reset_idx <= 8'h0; // @[tage.scala:73:26]
clear_u_ctr <= 20'h0; // @[tage.scala:109:28]
wrbypass_enq_idx <= 1'h0; // @[tage.scala:144:33]
end
else begin // @[tage.scala:24:7]
doing_reset <= reset_idx != 8'hFF & doing_reset; // @[tage.scala:72:28, :73:26, :75:{19,36,50}]
reset_idx <= _reset_idx_T_1; // @[tage.scala:73:26, :74:26]
clear_u_ctr <= doing_reset ? 20'h1 : _clear_u_ctr_T_1; // @[tage.scala:72:28, :109:28, :110:{22,36,70,85}]
if (~_T_44 | wrbypass_hit) begin // @[tage.scala:143:29, :144:33, :151:48, :170:{32,38}, :171:39]
end
else // @[tage.scala:144:33, :170:38, :171:39]
wrbypass_enq_idx <= _wrbypass_enq_idx_T_2; // @[util.scala:203:20]
end
s2_tag <= s1_tag; // @[tage.scala:62:64, :95:29]
io_f3_resp_0_valid_REG <= s2_req_rhits_0; // @[tage.scala:100:29, :104:38]
io_f3_resp_0_bits_u_REG <= _io_f3_resp_0_bits_u_T; // @[tage.scala:105:{38,42}]
io_f3_resp_0_bits_ctr_REG <= s2_req_rtage_0_ctr; // @[tage.scala:97:29, :106:38]
io_f3_resp_1_valid_REG <= s2_req_rhits_1; // @[tage.scala:100:29, :104:38]
io_f3_resp_1_bits_u_REG <= _io_f3_resp_1_bits_u_T; // @[tage.scala:105:{38,42}]
io_f3_resp_1_bits_ctr_REG <= s2_req_rtage_1_ctr; // @[tage.scala:97:29, :106:38]
io_f3_resp_2_valid_REG <= s2_req_rhits_2; // @[tage.scala:100:29, :104:38]
io_f3_resp_2_bits_u_REG <= _io_f3_resp_2_bits_u_T; // @[tage.scala:105:{38,42}]
io_f3_resp_2_bits_ctr_REG <= s2_req_rtage_2_ctr; // @[tage.scala:97:29, :106:38]
io_f3_resp_3_valid_REG <= s2_req_rhits_3; // @[tage.scala:100:29, :104:38]
io_f3_resp_3_bits_u_REG <= _io_f3_resp_3_bits_u_T; // @[tage.scala:105:{38,42}]
io_f3_resp_3_bits_ctr_REG <= s2_req_rtage_3_ctr; // @[tage.scala:97:29, :106:38]
if (_GEN_14) begin // @[tage.scala:141:29, :170:38, :171:39, :175:39]
end
else // @[tage.scala:141:29, :170:38, :171:39, :175:39]
wrbypass_tags_0 <= update_tag; // @[tage.scala:62:64, :141:29]
if (_GEN_15) begin // @[tage.scala:141:29, :170:38, :171:39, :175:39]
end
else // @[tage.scala:141:29, :170:38, :171:39, :175:39]
wrbypass_tags_1 <= update_tag; // @[tage.scala:62:64, :141:29]
if (_GEN_14) begin // @[tage.scala:141:29, :142:29, :170:38, :171:39, :175:39, :176:39]
end
else // @[tage.scala:142:29, :170:38, :171:39, :176:39]
wrbypass_idxs_0 <= update_idx; // @[tage.scala:60:43, :142:29]
if (_GEN_15) begin // @[tage.scala:141:29, :142:29, :170:38, :171:39, :175:39, :176:39]
end
else // @[tage.scala:142:29, :170:38, :171:39, :176:39]
wrbypass_idxs_1 <= update_idx; // @[tage.scala:60:43, :142:29]
if (~_T_44 | _GEN_13) begin // @[tage.scala:143:29, :170:{32,38}, :171:39, :172:34, :174:39]
end
else begin // @[tage.scala:143:29, :170:38, :171:39]
wrbypass_0_0 <= update_wdata_0_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_0_1 <= update_wdata_1_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_0_2 <= update_wdata_2_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_0_3 <= update_wdata_3_ctr; // @[tage.scala:119:26, :143:29]
end
if (_T_44 & _GEN_13) begin // @[tage.scala:143:29, :170:{32,38}, :171:39, :172:34, :174:39]
wrbypass_1_0 <= update_wdata_0_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_1_1 <= update_wdata_1_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_1_2 <= update_wdata_2_ctr; // @[tage.scala:119:26, :143:29]
wrbypass_1_3 <= update_wdata_3_ctr; // @[tage.scala:119:26, :143:29]
end
always @(posedge)
hi_us_13 hi_us ( // @[tage.scala:89:27]
.R0_addr (_s2_req_rhius_WIRE), // @[tage.scala:98:32]
.R0_en (io_f1_req_valid_0), // @[tage.scala:24:7]
.R0_clk (clock),
.R0_data (_hi_us_R0_data),
.W0_addr (doing_reset ? reset_idx : doing_clear_u_hi ? clear_u_idx[7:0] : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :113:40, :115:33, :129:{8,36}]
.W0_clk (clock),
.W0_data ({hi_us_MPORT_1_data_3, hi_us_MPORT_1_data_2, hi_us_MPORT_1_data_1, hi_us_MPORT_1_data_0}), // @[tage.scala:89:27, :130:8]
.W0_mask (_T_20 ? 4'hF : {hi_5, lo_1}) // @[tage.scala:130:21, :131:{8,80}]
); // @[tage.scala:89:27]
lo_us_13 lo_us ( // @[tage.scala:90:27]
.R0_addr (_s2_req_rlous_WIRE), // @[tage.scala:99:32]
.R0_en (io_f1_req_valid_0), // @[tage.scala:24:7]
.R0_clk (clock),
.R0_data (_lo_us_R0_data),
.W0_addr (doing_reset ? reset_idx : doing_clear_u_lo ? clear_u_idx[7:0] : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :114:40, :115:33, :136:{8,36}]
.W0_clk (clock),
.W0_data ({lo_us_MPORT_2_data_3, lo_us_MPORT_2_data_2, lo_us_MPORT_2_data_1, lo_us_MPORT_2_data_0}), // @[tage.scala:90:27, :137:8]
.W0_mask (_T_33 ? 4'hF : {hi_6, lo_2}) // @[tage.scala:137:21, :138:{8,80}]
); // @[tage.scala:90:27]
table_13 table_0 ( // @[tage.scala:91:27]
.R0_addr (_s2_req_rtage_WIRE), // @[tage.scala:97:40]
.R0_en (io_f1_req_valid_0), // @[tage.scala:24:7]
.R0_clk (clock),
.R0_data (_table_R0_data),
.W0_addr (doing_reset ? reset_idx : update_idx), // @[tage.scala:60:43, :72:28, :73:26, :122:8]
.W0_clk (clock),
.W0_data ({table_MPORT_data_3, table_MPORT_data_2, table_MPORT_data_1, table_MPORT_data_0}), // @[tage.scala:91:27, :123:8]
.W0_mask (doing_reset ? 4'hF : {hi_4, lo}) // @[tage.scala:72:28, :124:{8,90}]
); // @[tage.scala:91:27]
assign io_f3_resp_0_valid = io_f3_resp_0_valid_0; // @[tage.scala:24:7]
assign io_f3_resp_0_bits_ctr = io_f3_resp_0_bits_ctr_0; // @[tage.scala:24:7]
assign io_f3_resp_0_bits_u = io_f3_resp_0_bits_u_0; // @[tage.scala:24:7]
assign io_f3_resp_1_valid = io_f3_resp_1_valid_0; // @[tage.scala:24:7]
assign io_f3_resp_1_bits_ctr = io_f3_resp_1_bits_ctr_0; // @[tage.scala:24:7]
assign io_f3_resp_1_bits_u = io_f3_resp_1_bits_u_0; // @[tage.scala:24:7]
assign io_f3_resp_2_valid = io_f3_resp_2_valid_0; // @[tage.scala:24:7]
assign io_f3_resp_2_bits_ctr = io_f3_resp_2_bits_ctr_0; // @[tage.scala:24:7]
assign io_f3_resp_2_bits_u = io_f3_resp_2_bits_u_0; // @[tage.scala:24:7]
assign io_f3_resp_3_valid = io_f3_resp_3_valid_0; // @[tage.scala:24:7]
assign io_f3_resp_3_bits_ctr = io_f3_resp_3_bits_ctr_0; // @[tage.scala:24:7]
assign io_f3_resp_3_bits_u = io_f3_resp_3_bits_u_0; // @[tage.scala:24:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PE_136 :
input clock : Clock
input reset : Reset
output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>}
node _reg_T = eq(io.dir, UInt<1>(0h0))
node _reg_T_1 = mux(_reg_T, io.inR, io.inD)
reg reg : SInt<8>, clock
when io.en :
connect reg, _reg_T_1
connect io.outU, reg
connect io.outL, reg | module PE_136( // @[Transposer.scala:100:9]
input clock, // @[Transposer.scala:100:9]
input reset, // @[Transposer.scala:100:9]
input [7:0] io_inR, // @[Transposer.scala:101:16]
input [7:0] io_inD, // @[Transposer.scala:101:16]
output [7:0] io_outL, // @[Transposer.scala:101:16]
output [7:0] io_outU, // @[Transposer.scala:101:16]
input io_dir, // @[Transposer.scala:101:16]
input io_en // @[Transposer.scala:101:16]
);
wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9]
wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9]
wire io_dir_0 = io_dir; // @[Transposer.scala:100:9]
wire io_en_0 = io_en; // @[Transposer.scala:100:9]
wire [7:0] io_outL_0; // @[Transposer.scala:100:9]
wire [7:0] io_outU_0; // @[Transposer.scala:100:9]
wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36]
wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}]
reg [7:0] reg_0; // @[Transposer.scala:110:24]
assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24]
always @(posedge clock) begin // @[Transposer.scala:100:9]
if (io_en_0) // @[Transposer.scala:100:9]
reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}]
always @(posedge)
assign io_outL = io_outL_0; // @[Transposer.scala:100:9]
assign io_outU = io_outU_0; // @[Transposer.scala:100:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncQueueSink_Phit_10 :
input clock : Clock
input reset : Reset
output io : { deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { phit : UInt<32>}}, flip async : { mem : { phit : UInt<32>}[8], flip ridx : UInt<4>, widx : UInt<4>, safe : { flip ridx_valid : UInt<1>, widx_valid : UInt<1>, source_reset_n : UInt<1>, flip sink_reset_n : UInt<1>}}}
wire source_ready : UInt<1>
connect source_ready, UInt<1>(0h1)
node _ridx_T = asAsyncReset(reset)
node _ridx_T_1 = and(io.deq.ready, io.deq.valid)
node _ridx_T_2 = eq(source_ready, UInt<1>(0h0))
wire ridx_incremented : UInt<4>
regreset ridx_ridx_bin : UInt, clock, _ridx_T, UInt<1>(0h0)
connect ridx_ridx_bin, ridx_incremented
node _ridx_incremented_T = add(ridx_ridx_bin, _ridx_T_1)
node _ridx_incremented_T_1 = tail(_ridx_incremented_T, 1)
node _ridx_incremented_T_2 = mux(_ridx_T_2, UInt<1>(0h0), _ridx_incremented_T_1)
connect ridx_incremented, _ridx_incremented_T_2
node _ridx_T_3 = shr(ridx_incremented, 1)
node ridx = xor(ridx_incremented, _ridx_T_3)
inst widx_widx_gray of AsyncResetSynchronizerShiftReg_w4_d3_i0_21
connect widx_widx_gray.clock, clock
connect widx_widx_gray.reset, reset
connect widx_widx_gray.io.d, io.async.widx
wire widx : UInt<4>
connect widx, widx_widx_gray.io.q
node _valid_T = neq(ridx, widx)
node valid = and(source_ready, _valid_T)
node _index_T = bits(ridx, 2, 0)
node _index_T_1 = bits(ridx, 3, 3)
node _index_T_2 = shl(_index_T_1, 2)
node index = xor(_index_T, _index_T_2)
inst io_deq_bits_deq_bits_reg of ClockCrossingReg_w32_10
connect io_deq_bits_deq_bits_reg.clock, clock
connect io_deq_bits_deq_bits_reg.reset, reset
connect io_deq_bits_deq_bits_reg.io.d, io.async.mem[index].phit
connect io_deq_bits_deq_bits_reg.io.en, valid
wire _io_deq_bits_WIRE : { phit : UInt<32>}
wire _io_deq_bits_WIRE_1 : UInt<32>
connect _io_deq_bits_WIRE_1, io_deq_bits_deq_bits_reg.io.q
node _io_deq_bits_T = bits(_io_deq_bits_WIRE_1, 31, 0)
connect _io_deq_bits_WIRE.phit, _io_deq_bits_T
connect io.deq.bits, _io_deq_bits_WIRE
node _valid_reg_T = asAsyncReset(reset)
regreset valid_reg : UInt<1>, clock, _valid_reg_T, UInt<1>(0h0)
connect valid_reg, valid
node _io_deq_valid_T = and(valid_reg, source_ready)
connect io.deq.valid, _io_deq_valid_T
node _ridx_reg_T = asAsyncReset(reset)
regreset ridx_gray : UInt, clock, _ridx_reg_T, UInt<1>(0h0)
connect ridx_gray, ridx
connect io.async.ridx, ridx_gray
inst sink_valid_0 of AsyncValidSync_108
inst sink_valid_1 of AsyncValidSync_109
inst source_extend of AsyncValidSync_110
inst source_valid of AsyncValidSync_111
node _sink_valid_0_reset_T = asUInt(reset)
node _sink_valid_0_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0))
node _sink_valid_0_reset_T_2 = or(_sink_valid_0_reset_T, _sink_valid_0_reset_T_1)
node _sink_valid_0_reset_T_3 = asAsyncReset(_sink_valid_0_reset_T_2)
connect sink_valid_0.reset, _sink_valid_0_reset_T_3
node _sink_valid_1_reset_T = asUInt(reset)
node _sink_valid_1_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0))
node _sink_valid_1_reset_T_2 = or(_sink_valid_1_reset_T, _sink_valid_1_reset_T_1)
node _sink_valid_1_reset_T_3 = asAsyncReset(_sink_valid_1_reset_T_2)
connect sink_valid_1.reset, _sink_valid_1_reset_T_3
node _source_extend_reset_T = asUInt(reset)
node _source_extend_reset_T_1 = eq(io.async.safe.source_reset_n, UInt<1>(0h0))
node _source_extend_reset_T_2 = or(_source_extend_reset_T, _source_extend_reset_T_1)
node _source_extend_reset_T_3 = asAsyncReset(_source_extend_reset_T_2)
connect source_extend.reset, _source_extend_reset_T_3
node _source_valid_reset_T = asAsyncReset(reset)
connect source_valid.reset, _source_valid_reset_T
connect sink_valid_0.clock, clock
connect sink_valid_1.clock, clock
connect source_extend.clock, clock
connect source_valid.clock, clock
connect sink_valid_0.io.in, UInt<1>(0h1)
connect sink_valid_1.io.in, sink_valid_0.io.out
connect io.async.safe.ridx_valid, sink_valid_1.io.out
connect source_extend.io.in, io.async.safe.widx_valid
connect source_valid.io.in, source_extend.io.out
connect source_ready, source_valid.io.out
node _io_async_safe_sink_reset_n_T = asUInt(reset)
node _io_async_safe_sink_reset_n_T_1 = eq(_io_async_safe_sink_reset_n_T, UInt<1>(0h0))
connect io.async.safe.sink_reset_n, _io_async_safe_sink_reset_n_T_1 | module AsyncQueueSink_Phit_10( // @[AsyncQueue.scala:136:7]
input clock, // @[AsyncQueue.scala:136:7]
input reset, // @[AsyncQueue.scala:136:7]
input io_deq_ready, // @[AsyncQueue.scala:139:14]
output io_deq_valid, // @[AsyncQueue.scala:139:14]
output [31:0] io_deq_bits_phit, // @[AsyncQueue.scala:139:14]
input [31:0] io_async_mem_0_phit, // @[AsyncQueue.scala:139:14]
input [31:0] io_async_mem_1_phit, // @[AsyncQueue.scala:139:14]
input [31:0] io_async_mem_2_phit, // @[AsyncQueue.scala:139:14]
input [31:0] io_async_mem_3_phit, // @[AsyncQueue.scala:139:14]
input [31:0] io_async_mem_4_phit, // @[AsyncQueue.scala:139:14]
input [31:0] io_async_mem_5_phit, // @[AsyncQueue.scala:139:14]
input [31:0] io_async_mem_6_phit, // @[AsyncQueue.scala:139:14]
input [31:0] io_async_mem_7_phit, // @[AsyncQueue.scala:139:14]
output [3:0] io_async_ridx, // @[AsyncQueue.scala:139:14]
input [3:0] io_async_widx, // @[AsyncQueue.scala:139:14]
output io_async_safe_ridx_valid, // @[AsyncQueue.scala:139:14]
input io_async_safe_widx_valid, // @[AsyncQueue.scala:139:14]
input io_async_safe_source_reset_n, // @[AsyncQueue.scala:139:14]
output io_async_safe_sink_reset_n // @[AsyncQueue.scala:139:14]
);
wire _source_extend_io_out; // @[AsyncQueue.scala:175:31]
wire _sink_valid_0_io_out; // @[AsyncQueue.scala:172:33]
wire io_deq_ready_0 = io_deq_ready; // @[AsyncQueue.scala:136:7]
wire [31:0] io_async_mem_0_phit_0 = io_async_mem_0_phit; // @[AsyncQueue.scala:136:7]
wire [31:0] io_async_mem_1_phit_0 = io_async_mem_1_phit; // @[AsyncQueue.scala:136:7]
wire [31:0] io_async_mem_2_phit_0 = io_async_mem_2_phit; // @[AsyncQueue.scala:136:7]
wire [31:0] io_async_mem_3_phit_0 = io_async_mem_3_phit; // @[AsyncQueue.scala:136:7]
wire [31:0] io_async_mem_4_phit_0 = io_async_mem_4_phit; // @[AsyncQueue.scala:136:7]
wire [31:0] io_async_mem_5_phit_0 = io_async_mem_5_phit; // @[AsyncQueue.scala:136:7]
wire [31:0] io_async_mem_6_phit_0 = io_async_mem_6_phit; // @[AsyncQueue.scala:136:7]
wire [31:0] io_async_mem_7_phit_0 = io_async_mem_7_phit; // @[AsyncQueue.scala:136:7]
wire [3:0] io_async_widx_0 = io_async_widx; // @[AsyncQueue.scala:136:7]
wire io_async_safe_widx_valid_0 = io_async_safe_widx_valid; // @[AsyncQueue.scala:136:7]
wire io_async_safe_source_reset_n_0 = io_async_safe_source_reset_n; // @[AsyncQueue.scala:136:7]
wire _ridx_T = reset; // @[AsyncQueue.scala:148:30]
wire _valid_reg_T = reset; // @[AsyncQueue.scala:165:35]
wire _ridx_reg_T = reset; // @[AsyncQueue.scala:168:34]
wire _sink_valid_0_reset_T = reset; // @[AsyncQueue.scala:177:35]
wire _sink_valid_1_reset_T = reset; // @[AsyncQueue.scala:178:35]
wire _source_extend_reset_T = reset; // @[AsyncQueue.scala:179:35]
wire _source_valid_reset_T = reset; // @[AsyncQueue.scala:180:34]
wire _io_async_safe_sink_reset_n_T = reset; // @[AsyncQueue.scala:193:32]
wire _io_deq_valid_T; // @[AsyncQueue.scala:166:29]
wire [31:0] _io_deq_bits_WIRE_phit; // @[SynchronizerReg.scala:211:26]
wire _io_async_safe_sink_reset_n_T_1; // @[AsyncQueue.scala:193:25]
wire [31:0] io_deq_bits_phit_0; // @[AsyncQueue.scala:136:7]
wire io_deq_valid_0; // @[AsyncQueue.scala:136:7]
wire io_async_safe_ridx_valid_0; // @[AsyncQueue.scala:136:7]
wire io_async_safe_sink_reset_n_0; // @[AsyncQueue.scala:136:7]
wire [3:0] io_async_ridx_0; // @[AsyncQueue.scala:136:7]
wire source_ready; // @[AsyncQueue.scala:147:30]
wire _ridx_T_1 = io_deq_ready_0 & io_deq_valid_0; // @[Decoupled.scala:51:35]
wire _ridx_T_2 = ~source_ready; // @[AsyncQueue.scala:147:30, :148:77]
wire [3:0] _ridx_incremented_T_2; // @[AsyncQueue.scala:53:23]
wire [3:0] ridx_incremented; // @[AsyncQueue.scala:51:27]
reg [3:0] ridx_ridx_bin; // @[AsyncQueue.scala:52:25]
wire [4:0] _ridx_incremented_T = {1'h0, ridx_ridx_bin} + {4'h0, _ridx_T_1}; // @[Decoupled.scala:51:35]
wire [3:0] _ridx_incremented_T_1 = _ridx_incremented_T[3:0]; // @[AsyncQueue.scala:53:43]
assign _ridx_incremented_T_2 = _ridx_T_2 ? 4'h0 : _ridx_incremented_T_1; // @[AsyncQueue.scala:52:25, :53:{23,43}, :148:77]
assign ridx_incremented = _ridx_incremented_T_2; // @[AsyncQueue.scala:51:27, :53:23]
wire [2:0] _ridx_T_3 = ridx_incremented[3:1]; // @[AsyncQueue.scala:51:27, :54:32]
wire [3:0] ridx = {ridx_incremented[3], ridx_incremented[2:0] ^ _ridx_T_3}; // @[AsyncQueue.scala:51:27, :54:{17,32}]
wire [3:0] widx; // @[ShiftReg.scala:48:24]
wire _valid_T = ridx != widx; // @[ShiftReg.scala:48:24]
wire valid = source_ready & _valid_T; // @[AsyncQueue.scala:147:30, :150:{28,36}]
wire [2:0] _index_T = ridx[2:0]; // @[AsyncQueue.scala:54:17, :156:43]
wire _index_T_1 = ridx[3]; // @[AsyncQueue.scala:54:17, :156:62]
wire [2:0] _index_T_2 = {_index_T_1, 2'h0}; // @[AsyncQueue.scala:156:{62,75}]
wire [2:0] index = _index_T ^ _index_T_2; // @[AsyncQueue.scala:156:{43,55,75}]
wire [7:0][31:0] _GEN = {{io_async_mem_7_phit_0}, {io_async_mem_6_phit_0}, {io_async_mem_5_phit_0}, {io_async_mem_4_phit_0}, {io_async_mem_3_phit_0}, {io_async_mem_2_phit_0}, {io_async_mem_1_phit_0}, {io_async_mem_0_phit_0}}; // @[SynchronizerReg.scala:209:18]
wire [31:0] _io_deq_bits_T; // @[SynchronizerReg.scala:211:26]
assign io_deq_bits_phit_0 = _io_deq_bits_WIRE_phit; // @[SynchronizerReg.scala:211:26]
wire [31:0] _io_deq_bits_WIRE_1; // @[SynchronizerReg.scala:211:26]
assign _io_deq_bits_T = _io_deq_bits_WIRE_1; // @[SynchronizerReg.scala:211:26]
assign _io_deq_bits_WIRE_phit = _io_deq_bits_T; // @[SynchronizerReg.scala:211:26]
reg valid_reg; // @[AsyncQueue.scala:165:56]
assign _io_deq_valid_T = valid_reg & source_ready; // @[AsyncQueue.scala:147:30, :165:56, :166:29]
assign io_deq_valid_0 = _io_deq_valid_T; // @[AsyncQueue.scala:136:7, :166:29]
reg [3:0] ridx_gray; // @[AsyncQueue.scala:168:55]
assign io_async_ridx_0 = ridx_gray; // @[AsyncQueue.scala:136:7, :168:55]
wire _sink_valid_0_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45]
wire _sink_valid_0_reset_T_2 = _sink_valid_0_reset_T | _sink_valid_0_reset_T_1; // @[AsyncQueue.scala:177:{35,42,45}]
wire _sink_valid_0_reset_T_3 = _sink_valid_0_reset_T_2; // @[AsyncQueue.scala:177:{42,66}]
wire _sink_valid_1_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45, :178:45]
wire _sink_valid_1_reset_T_2 = _sink_valid_1_reset_T | _sink_valid_1_reset_T_1; // @[AsyncQueue.scala:178:{35,42,45}]
wire _sink_valid_1_reset_T_3 = _sink_valid_1_reset_T_2; // @[AsyncQueue.scala:178:{42,66}]
wire _source_extend_reset_T_1 = ~io_async_safe_source_reset_n_0; // @[AsyncQueue.scala:136:7, :177:45, :179:45]
wire _source_extend_reset_T_2 = _source_extend_reset_T | _source_extend_reset_T_1; // @[AsyncQueue.scala:179:{35,42,45}]
wire _source_extend_reset_T_3 = _source_extend_reset_T_2; // @[AsyncQueue.scala:179:{42,66}]
assign _io_async_safe_sink_reset_n_T_1 = ~_io_async_safe_sink_reset_n_T; // @[AsyncQueue.scala:193:{25,32}]
assign io_async_safe_sink_reset_n_0 = _io_async_safe_sink_reset_n_T_1; // @[AsyncQueue.scala:136:7, :193:25]
always @(posedge clock or posedge _ridx_T) begin // @[AsyncQueue.scala:136:7, :148:30]
if (_ridx_T) // @[AsyncQueue.scala:136:7, :148:30]
ridx_ridx_bin <= 4'h0; // @[AsyncQueue.scala:52:25]
else // @[AsyncQueue.scala:136:7]
ridx_ridx_bin <= ridx_incremented; // @[AsyncQueue.scala:51:27, :52:25]
always @(posedge, posedge)
always @(posedge clock or posedge _valid_reg_T) begin // @[AsyncQueue.scala:136:7, :165:35]
if (_valid_reg_T) // @[AsyncQueue.scala:136:7, :165:35]
valid_reg <= 1'h0; // @[AsyncQueue.scala:165:56]
else // @[AsyncQueue.scala:136:7]
valid_reg <= valid; // @[AsyncQueue.scala:150:28, :165:56]
always @(posedge, posedge)
always @(posedge clock or posedge _ridx_reg_T) begin // @[AsyncQueue.scala:136:7, :168:34]
if (_ridx_reg_T) // @[AsyncQueue.scala:136:7, :168:34]
ridx_gray <= 4'h0; // @[AsyncQueue.scala:52:25, :168:55]
else // @[AsyncQueue.scala:136:7]
ridx_gray <= ridx; // @[AsyncQueue.scala:54:17, :168:55]
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module BoomMSHR :
input clock : Clock
input reset : Reset
output io : { flip id : UInt, flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip clear_prefetch : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<4>, mispredict_mask : UInt<4>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<34>, target_offset : SInt}}, flip exception : UInt<1>, flip rob_pnr_idx : UInt<6>, flip rob_head_idx : UInt<6>, flip req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}, flip req_is_probe : UInt<1>, idx : { valid : UInt<1>, bits : UInt}, way : { valid : UInt<1>, bits : UInt}, tag : { valid : UInt<1>, bits : UInt}, mem_acquire : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip mem_grant : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, mem_finish : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}, flip prober_state : { valid : UInt<1>, bits : UInt<34>}, refill : { flip ready : UInt<1>, valid : UInt<1>, bits : { way_en : UInt<2>, addr : UInt<10>, wmask : UInt<1>, data : UInt<64>}}, meta_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<4>, way_en : UInt<2>, tag : UInt<22>, data : { coh : { state : UInt<2>}, tag : UInt<22>}}}, meta_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { idx : UInt<4>, way_en : UInt<2>, tag : UInt<22>}}, flip meta_resp : { valid : UInt<1>, bits : { coh : { state : UInt<2>}, tag : UInt<22>}}, wb_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { tag : UInt<22>, idx : UInt<4>, source : UInt<4>, param : UInt<3>, way_en : UInt<2>, voluntary : UInt<1>}}, commit_val : UInt<1>, commit_addr : UInt<34>, commit_coh : { state : UInt<2>}, lb_read : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, offset : UInt<3>}}, flip lb_resp : UInt<64>, lb_write : { flip ready : UInt<1>, valid : UInt<1>, bits : { id : UInt<3>, offset : UInt<3>, data : UInt<64>}}, replay : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, is_hella : UInt<1>}}, flip wb_resp : UInt<1>, probe_rdy : UInt<1>}
regreset state : UInt<5>, clock, reset, UInt<5>(0h0)
reg req : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<34>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<4>, br_tag : UInt<2>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<34>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<22>}, way_en : UInt<2>, sdq_id : UInt<5>}, clock
node req_idx = bits(req.addr, 9, 6)
node req_tag = shr(req.addr, 10)
node _req_block_addr_T = shr(req.addr, 6)
node req_block_addr = shl(_req_block_addr_T, 6)
regreset req_needs_wb : UInt<1>, clock, reset, UInt<1>(0h0)
wire new_coh_meta : { state : UInt<2>}
connect new_coh_meta.state, UInt<2>(0h0)
regreset new_coh : { state : UInt<2>}, clock, reset, new_coh_meta
node _r_T = eq(UInt<5>(0h10), UInt<5>(0h10))
node _r_T_1 = mux(_r_T, UInt<2>(0h2), UInt<2>(0h2))
node _r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _r_T_3 = mux(_r_T_2, UInt<2>(0h1), _r_T_1)
node _r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _r_T_5 = mux(_r_T_4, UInt<2>(0h0), _r_T_3)
node _r_T_6 = cat(_r_T_5, req.old_meta.coh.state)
node _r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _r_T_19 = eq(_r_T_18, _r_T_6)
node _r_T_20 = mux(_r_T_19, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_21 = mux(_r_T_19, UInt<3>(0h5), UInt<1>(0h0))
node _r_T_22 = mux(_r_T_19, UInt<2>(0h0), UInt<1>(0h0))
node _r_T_23 = eq(_r_T_17, _r_T_6)
node _r_T_24 = mux(_r_T_23, UInt<1>(0h0), _r_T_20)
node _r_T_25 = mux(_r_T_23, UInt<3>(0h2), _r_T_21)
node _r_T_26 = mux(_r_T_23, UInt<2>(0h0), _r_T_22)
node _r_T_27 = eq(_r_T_16, _r_T_6)
node _r_T_28 = mux(_r_T_27, UInt<1>(0h0), _r_T_24)
node _r_T_29 = mux(_r_T_27, UInt<3>(0h1), _r_T_25)
node _r_T_30 = mux(_r_T_27, UInt<2>(0h0), _r_T_26)
node _r_T_31 = eq(_r_T_15, _r_T_6)
node _r_T_32 = mux(_r_T_31, UInt<1>(0h1), _r_T_28)
node _r_T_33 = mux(_r_T_31, UInt<3>(0h1), _r_T_29)
node _r_T_34 = mux(_r_T_31, UInt<2>(0h0), _r_T_30)
node _r_T_35 = eq(_r_T_14, _r_T_6)
node _r_T_36 = mux(_r_T_35, UInt<1>(0h0), _r_T_32)
node _r_T_37 = mux(_r_T_35, UInt<3>(0h5), _r_T_33)
node _r_T_38 = mux(_r_T_35, UInt<2>(0h0), _r_T_34)
node _r_T_39 = eq(_r_T_13, _r_T_6)
node _r_T_40 = mux(_r_T_39, UInt<1>(0h0), _r_T_36)
node _r_T_41 = mux(_r_T_39, UInt<3>(0h4), _r_T_37)
node _r_T_42 = mux(_r_T_39, UInt<2>(0h1), _r_T_38)
node _r_T_43 = eq(_r_T_12, _r_T_6)
node _r_T_44 = mux(_r_T_43, UInt<1>(0h0), _r_T_40)
node _r_T_45 = mux(_r_T_43, UInt<3>(0h0), _r_T_41)
node _r_T_46 = mux(_r_T_43, UInt<2>(0h1), _r_T_42)
node _r_T_47 = eq(_r_T_11, _r_T_6)
node _r_T_48 = mux(_r_T_47, UInt<1>(0h1), _r_T_44)
node _r_T_49 = mux(_r_T_47, UInt<3>(0h0), _r_T_45)
node _r_T_50 = mux(_r_T_47, UInt<2>(0h1), _r_T_46)
node _r_T_51 = eq(_r_T_10, _r_T_6)
node _r_T_52 = mux(_r_T_51, UInt<1>(0h0), _r_T_48)
node _r_T_53 = mux(_r_T_51, UInt<3>(0h5), _r_T_49)
node _r_T_54 = mux(_r_T_51, UInt<2>(0h0), _r_T_50)
node _r_T_55 = eq(_r_T_9, _r_T_6)
node _r_T_56 = mux(_r_T_55, UInt<1>(0h0), _r_T_52)
node _r_T_57 = mux(_r_T_55, UInt<3>(0h4), _r_T_53)
node _r_T_58 = mux(_r_T_55, UInt<2>(0h1), _r_T_54)
node _r_T_59 = eq(_r_T_8, _r_T_6)
node _r_T_60 = mux(_r_T_59, UInt<1>(0h0), _r_T_56)
node _r_T_61 = mux(_r_T_59, UInt<3>(0h3), _r_T_57)
node _r_T_62 = mux(_r_T_59, UInt<2>(0h2), _r_T_58)
node _r_T_63 = eq(_r_T_7, _r_T_6)
node r_1 = mux(_r_T_63, UInt<1>(0h1), _r_T_60)
node shrink_param = mux(_r_T_63, UInt<3>(0h3), _r_T_61)
node r_3 = mux(_r_T_63, UInt<2>(0h2), _r_T_62)
wire coh_on_clear : { state : UInt<2>}
connect coh_on_clear.state, r_3
node _grow_param_r_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _grow_param_r_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _grow_param_r_c_cat_T_2 = or(_grow_param_r_c_cat_T, _grow_param_r_c_cat_T_1)
node _grow_param_r_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _grow_param_r_c_cat_T_4 = or(_grow_param_r_c_cat_T_2, _grow_param_r_c_cat_T_3)
node _grow_param_r_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _grow_param_r_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _grow_param_r_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _grow_param_r_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _grow_param_r_c_cat_T_9 = or(_grow_param_r_c_cat_T_5, _grow_param_r_c_cat_T_6)
node _grow_param_r_c_cat_T_10 = or(_grow_param_r_c_cat_T_9, _grow_param_r_c_cat_T_7)
node _grow_param_r_c_cat_T_11 = or(_grow_param_r_c_cat_T_10, _grow_param_r_c_cat_T_8)
node _grow_param_r_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _grow_param_r_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _grow_param_r_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _grow_param_r_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _grow_param_r_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _grow_param_r_c_cat_T_17 = or(_grow_param_r_c_cat_T_12, _grow_param_r_c_cat_T_13)
node _grow_param_r_c_cat_T_18 = or(_grow_param_r_c_cat_T_17, _grow_param_r_c_cat_T_14)
node _grow_param_r_c_cat_T_19 = or(_grow_param_r_c_cat_T_18, _grow_param_r_c_cat_T_15)
node _grow_param_r_c_cat_T_20 = or(_grow_param_r_c_cat_T_19, _grow_param_r_c_cat_T_16)
node _grow_param_r_c_cat_T_21 = or(_grow_param_r_c_cat_T_11, _grow_param_r_c_cat_T_20)
node _grow_param_r_c_cat_T_22 = or(_grow_param_r_c_cat_T_4, _grow_param_r_c_cat_T_21)
node _grow_param_r_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _grow_param_r_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _grow_param_r_c_cat_T_25 = or(_grow_param_r_c_cat_T_23, _grow_param_r_c_cat_T_24)
node _grow_param_r_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _grow_param_r_c_cat_T_27 = or(_grow_param_r_c_cat_T_25, _grow_param_r_c_cat_T_26)
node _grow_param_r_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _grow_param_r_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _grow_param_r_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _grow_param_r_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _grow_param_r_c_cat_T_32 = or(_grow_param_r_c_cat_T_28, _grow_param_r_c_cat_T_29)
node _grow_param_r_c_cat_T_33 = or(_grow_param_r_c_cat_T_32, _grow_param_r_c_cat_T_30)
node _grow_param_r_c_cat_T_34 = or(_grow_param_r_c_cat_T_33, _grow_param_r_c_cat_T_31)
node _grow_param_r_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _grow_param_r_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _grow_param_r_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _grow_param_r_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _grow_param_r_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _grow_param_r_c_cat_T_40 = or(_grow_param_r_c_cat_T_35, _grow_param_r_c_cat_T_36)
node _grow_param_r_c_cat_T_41 = or(_grow_param_r_c_cat_T_40, _grow_param_r_c_cat_T_37)
node _grow_param_r_c_cat_T_42 = or(_grow_param_r_c_cat_T_41, _grow_param_r_c_cat_T_38)
node _grow_param_r_c_cat_T_43 = or(_grow_param_r_c_cat_T_42, _grow_param_r_c_cat_T_39)
node _grow_param_r_c_cat_T_44 = or(_grow_param_r_c_cat_T_34, _grow_param_r_c_cat_T_43)
node _grow_param_r_c_cat_T_45 = or(_grow_param_r_c_cat_T_27, _grow_param_r_c_cat_T_44)
node _grow_param_r_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3))
node _grow_param_r_c_cat_T_47 = or(_grow_param_r_c_cat_T_45, _grow_param_r_c_cat_T_46)
node _grow_param_r_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _grow_param_r_c_cat_T_49 = or(_grow_param_r_c_cat_T_47, _grow_param_r_c_cat_T_48)
node grow_param_r_c = cat(_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49)
node _grow_param_r_T = cat(grow_param_r_c, new_coh.state)
node _grow_param_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_2 = cat(_grow_param_r_T_1, UInt<2>(0h3))
node _grow_param_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_4 = cat(_grow_param_r_T_3, UInt<2>(0h2))
node _grow_param_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_6 = cat(_grow_param_r_T_5, UInt<2>(0h1))
node _grow_param_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_8 = cat(_grow_param_r_T_7, UInt<2>(0h3))
node _grow_param_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_10 = cat(_grow_param_r_T_9, UInt<2>(0h2))
node _grow_param_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_12 = cat(_grow_param_r_T_11, UInt<2>(0h3))
node _grow_param_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_14 = cat(_grow_param_r_T_13, UInt<2>(0h2))
node _grow_param_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_16 = cat(_grow_param_r_T_15, UInt<2>(0h0))
node _grow_param_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_18 = cat(_grow_param_r_T_17, UInt<2>(0h1))
node _grow_param_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _grow_param_r_T_20 = cat(_grow_param_r_T_19, UInt<2>(0h0))
node _grow_param_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_22 = cat(_grow_param_r_T_21, UInt<2>(0h1))
node _grow_param_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _grow_param_r_T_24 = cat(_grow_param_r_T_23, UInt<2>(0h0))
node _grow_param_r_T_25 = eq(_grow_param_r_T_24, _grow_param_r_T)
node _grow_param_r_T_26 = mux(_grow_param_r_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _grow_param_r_T_27 = mux(_grow_param_r_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _grow_param_r_T_28 = eq(_grow_param_r_T_22, _grow_param_r_T)
node _grow_param_r_T_29 = mux(_grow_param_r_T_28, UInt<1>(0h0), _grow_param_r_T_26)
node _grow_param_r_T_30 = mux(_grow_param_r_T_28, UInt<2>(0h2), _grow_param_r_T_27)
node _grow_param_r_T_31 = eq(_grow_param_r_T_20, _grow_param_r_T)
node _grow_param_r_T_32 = mux(_grow_param_r_T_31, UInt<1>(0h0), _grow_param_r_T_29)
node _grow_param_r_T_33 = mux(_grow_param_r_T_31, UInt<2>(0h1), _grow_param_r_T_30)
node _grow_param_r_T_34 = eq(_grow_param_r_T_18, _grow_param_r_T)
node _grow_param_r_T_35 = mux(_grow_param_r_T_34, UInt<1>(0h0), _grow_param_r_T_32)
node _grow_param_r_T_36 = mux(_grow_param_r_T_34, UInt<2>(0h2), _grow_param_r_T_33)
node _grow_param_r_T_37 = eq(_grow_param_r_T_16, _grow_param_r_T)
node _grow_param_r_T_38 = mux(_grow_param_r_T_37, UInt<1>(0h0), _grow_param_r_T_35)
node _grow_param_r_T_39 = mux(_grow_param_r_T_37, UInt<2>(0h0), _grow_param_r_T_36)
node _grow_param_r_T_40 = eq(_grow_param_r_T_14, _grow_param_r_T)
node _grow_param_r_T_41 = mux(_grow_param_r_T_40, UInt<1>(0h1), _grow_param_r_T_38)
node _grow_param_r_T_42 = mux(_grow_param_r_T_40, UInt<2>(0h3), _grow_param_r_T_39)
node _grow_param_r_T_43 = eq(_grow_param_r_T_12, _grow_param_r_T)
node _grow_param_r_T_44 = mux(_grow_param_r_T_43, UInt<1>(0h1), _grow_param_r_T_41)
node _grow_param_r_T_45 = mux(_grow_param_r_T_43, UInt<2>(0h3), _grow_param_r_T_42)
node _grow_param_r_T_46 = eq(_grow_param_r_T_10, _grow_param_r_T)
node _grow_param_r_T_47 = mux(_grow_param_r_T_46, UInt<1>(0h1), _grow_param_r_T_44)
node _grow_param_r_T_48 = mux(_grow_param_r_T_46, UInt<2>(0h2), _grow_param_r_T_45)
node _grow_param_r_T_49 = eq(_grow_param_r_T_8, _grow_param_r_T)
node _grow_param_r_T_50 = mux(_grow_param_r_T_49, UInt<1>(0h1), _grow_param_r_T_47)
node _grow_param_r_T_51 = mux(_grow_param_r_T_49, UInt<2>(0h3), _grow_param_r_T_48)
node _grow_param_r_T_52 = eq(_grow_param_r_T_6, _grow_param_r_T)
node _grow_param_r_T_53 = mux(_grow_param_r_T_52, UInt<1>(0h1), _grow_param_r_T_50)
node _grow_param_r_T_54 = mux(_grow_param_r_T_52, UInt<2>(0h1), _grow_param_r_T_51)
node _grow_param_r_T_55 = eq(_grow_param_r_T_4, _grow_param_r_T)
node _grow_param_r_T_56 = mux(_grow_param_r_T_55, UInt<1>(0h1), _grow_param_r_T_53)
node _grow_param_r_T_57 = mux(_grow_param_r_T_55, UInt<2>(0h2), _grow_param_r_T_54)
node _grow_param_r_T_58 = eq(_grow_param_r_T_2, _grow_param_r_T)
node grow_param_r_1 = mux(_grow_param_r_T_58, UInt<1>(0h1), _grow_param_r_T_56)
node grow_param = mux(_grow_param_r_T_58, UInt<2>(0h3), _grow_param_r_T_57)
wire grow_param_meta : { state : UInt<2>}
connect grow_param_meta.state, grow_param
node _coh_on_grant_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _coh_on_grant_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _coh_on_grant_c_cat_T_2 = or(_coh_on_grant_c_cat_T, _coh_on_grant_c_cat_T_1)
node _coh_on_grant_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _coh_on_grant_c_cat_T_4 = or(_coh_on_grant_c_cat_T_2, _coh_on_grant_c_cat_T_3)
node _coh_on_grant_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _coh_on_grant_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _coh_on_grant_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _coh_on_grant_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _coh_on_grant_c_cat_T_9 = or(_coh_on_grant_c_cat_T_5, _coh_on_grant_c_cat_T_6)
node _coh_on_grant_c_cat_T_10 = or(_coh_on_grant_c_cat_T_9, _coh_on_grant_c_cat_T_7)
node _coh_on_grant_c_cat_T_11 = or(_coh_on_grant_c_cat_T_10, _coh_on_grant_c_cat_T_8)
node _coh_on_grant_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _coh_on_grant_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _coh_on_grant_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _coh_on_grant_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _coh_on_grant_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _coh_on_grant_c_cat_T_17 = or(_coh_on_grant_c_cat_T_12, _coh_on_grant_c_cat_T_13)
node _coh_on_grant_c_cat_T_18 = or(_coh_on_grant_c_cat_T_17, _coh_on_grant_c_cat_T_14)
node _coh_on_grant_c_cat_T_19 = or(_coh_on_grant_c_cat_T_18, _coh_on_grant_c_cat_T_15)
node _coh_on_grant_c_cat_T_20 = or(_coh_on_grant_c_cat_T_19, _coh_on_grant_c_cat_T_16)
node _coh_on_grant_c_cat_T_21 = or(_coh_on_grant_c_cat_T_11, _coh_on_grant_c_cat_T_20)
node _coh_on_grant_c_cat_T_22 = or(_coh_on_grant_c_cat_T_4, _coh_on_grant_c_cat_T_21)
node _coh_on_grant_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _coh_on_grant_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _coh_on_grant_c_cat_T_25 = or(_coh_on_grant_c_cat_T_23, _coh_on_grant_c_cat_T_24)
node _coh_on_grant_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _coh_on_grant_c_cat_T_27 = or(_coh_on_grant_c_cat_T_25, _coh_on_grant_c_cat_T_26)
node _coh_on_grant_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _coh_on_grant_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _coh_on_grant_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _coh_on_grant_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _coh_on_grant_c_cat_T_32 = or(_coh_on_grant_c_cat_T_28, _coh_on_grant_c_cat_T_29)
node _coh_on_grant_c_cat_T_33 = or(_coh_on_grant_c_cat_T_32, _coh_on_grant_c_cat_T_30)
node _coh_on_grant_c_cat_T_34 = or(_coh_on_grant_c_cat_T_33, _coh_on_grant_c_cat_T_31)
node _coh_on_grant_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _coh_on_grant_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _coh_on_grant_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _coh_on_grant_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _coh_on_grant_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _coh_on_grant_c_cat_T_40 = or(_coh_on_grant_c_cat_T_35, _coh_on_grant_c_cat_T_36)
node _coh_on_grant_c_cat_T_41 = or(_coh_on_grant_c_cat_T_40, _coh_on_grant_c_cat_T_37)
node _coh_on_grant_c_cat_T_42 = or(_coh_on_grant_c_cat_T_41, _coh_on_grant_c_cat_T_38)
node _coh_on_grant_c_cat_T_43 = or(_coh_on_grant_c_cat_T_42, _coh_on_grant_c_cat_T_39)
node _coh_on_grant_c_cat_T_44 = or(_coh_on_grant_c_cat_T_34, _coh_on_grant_c_cat_T_43)
node _coh_on_grant_c_cat_T_45 = or(_coh_on_grant_c_cat_T_27, _coh_on_grant_c_cat_T_44)
node _coh_on_grant_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3))
node _coh_on_grant_c_cat_T_47 = or(_coh_on_grant_c_cat_T_45, _coh_on_grant_c_cat_T_46)
node _coh_on_grant_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _coh_on_grant_c_cat_T_49 = or(_coh_on_grant_c_cat_T_47, _coh_on_grant_c_cat_T_48)
node coh_on_grant_c = cat(_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49)
node _coh_on_grant_T = cat(coh_on_grant_c, io.mem_grant.bits.param)
node _coh_on_grant_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _coh_on_grant_T_2 = cat(_coh_on_grant_T_1, UInt<2>(0h1))
node _coh_on_grant_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _coh_on_grant_T_4 = cat(_coh_on_grant_T_3, UInt<2>(0h0))
node _coh_on_grant_T_5 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _coh_on_grant_T_6 = cat(_coh_on_grant_T_5, UInt<2>(0h0))
node _coh_on_grant_T_7 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _coh_on_grant_T_8 = cat(_coh_on_grant_T_7, UInt<2>(0h0))
node _coh_on_grant_T_9 = eq(_coh_on_grant_T_2, _coh_on_grant_T)
node _coh_on_grant_T_10 = mux(_coh_on_grant_T_9, UInt<2>(0h1), UInt<2>(0h0))
node _coh_on_grant_T_11 = eq(_coh_on_grant_T_4, _coh_on_grant_T)
node _coh_on_grant_T_12 = mux(_coh_on_grant_T_11, UInt<2>(0h2), _coh_on_grant_T_10)
node _coh_on_grant_T_13 = eq(_coh_on_grant_T_6, _coh_on_grant_T)
node _coh_on_grant_T_14 = mux(_coh_on_grant_T_13, UInt<2>(0h2), _coh_on_grant_T_12)
node _coh_on_grant_T_15 = eq(_coh_on_grant_T_8, _coh_on_grant_T)
node _coh_on_grant_T_16 = mux(_coh_on_grant_T_15, UInt<2>(0h3), _coh_on_grant_T_14)
wire coh_on_grant : { state : UInt<2>}
connect coh_on_grant.state, _coh_on_grant_T_16
node _r1_c_cat_T = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _r1_c_cat_T_1 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _r1_c_cat_T_2 = or(_r1_c_cat_T, _r1_c_cat_T_1)
node _r1_c_cat_T_3 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _r1_c_cat_T_4 = or(_r1_c_cat_T_2, _r1_c_cat_T_3)
node _r1_c_cat_T_5 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _r1_c_cat_T_6 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _r1_c_cat_T_7 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _r1_c_cat_T_8 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _r1_c_cat_T_9 = or(_r1_c_cat_T_5, _r1_c_cat_T_6)
node _r1_c_cat_T_10 = or(_r1_c_cat_T_9, _r1_c_cat_T_7)
node _r1_c_cat_T_11 = or(_r1_c_cat_T_10, _r1_c_cat_T_8)
node _r1_c_cat_T_12 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _r1_c_cat_T_13 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _r1_c_cat_T_14 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _r1_c_cat_T_15 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _r1_c_cat_T_16 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _r1_c_cat_T_17 = or(_r1_c_cat_T_12, _r1_c_cat_T_13)
node _r1_c_cat_T_18 = or(_r1_c_cat_T_17, _r1_c_cat_T_14)
node _r1_c_cat_T_19 = or(_r1_c_cat_T_18, _r1_c_cat_T_15)
node _r1_c_cat_T_20 = or(_r1_c_cat_T_19, _r1_c_cat_T_16)
node _r1_c_cat_T_21 = or(_r1_c_cat_T_11, _r1_c_cat_T_20)
node _r1_c_cat_T_22 = or(_r1_c_cat_T_4, _r1_c_cat_T_21)
node _r1_c_cat_T_23 = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _r1_c_cat_T_24 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _r1_c_cat_T_25 = or(_r1_c_cat_T_23, _r1_c_cat_T_24)
node _r1_c_cat_T_26 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _r1_c_cat_T_27 = or(_r1_c_cat_T_25, _r1_c_cat_T_26)
node _r1_c_cat_T_28 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _r1_c_cat_T_29 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _r1_c_cat_T_30 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _r1_c_cat_T_31 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _r1_c_cat_T_32 = or(_r1_c_cat_T_28, _r1_c_cat_T_29)
node _r1_c_cat_T_33 = or(_r1_c_cat_T_32, _r1_c_cat_T_30)
node _r1_c_cat_T_34 = or(_r1_c_cat_T_33, _r1_c_cat_T_31)
node _r1_c_cat_T_35 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _r1_c_cat_T_36 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _r1_c_cat_T_37 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _r1_c_cat_T_38 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _r1_c_cat_T_39 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _r1_c_cat_T_40 = or(_r1_c_cat_T_35, _r1_c_cat_T_36)
node _r1_c_cat_T_41 = or(_r1_c_cat_T_40, _r1_c_cat_T_37)
node _r1_c_cat_T_42 = or(_r1_c_cat_T_41, _r1_c_cat_T_38)
node _r1_c_cat_T_43 = or(_r1_c_cat_T_42, _r1_c_cat_T_39)
node _r1_c_cat_T_44 = or(_r1_c_cat_T_34, _r1_c_cat_T_43)
node _r1_c_cat_T_45 = or(_r1_c_cat_T_27, _r1_c_cat_T_44)
node _r1_c_cat_T_46 = eq(req.uop.mem_cmd, UInt<2>(0h3))
node _r1_c_cat_T_47 = or(_r1_c_cat_T_45, _r1_c_cat_T_46)
node _r1_c_cat_T_48 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _r1_c_cat_T_49 = or(_r1_c_cat_T_47, _r1_c_cat_T_48)
node r1_c = cat(_r1_c_cat_T_22, _r1_c_cat_T_49)
node _r1_T = cat(r1_c, new_coh.state)
node _r1_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_2 = cat(_r1_T_1, UInt<2>(0h3))
node _r1_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_4 = cat(_r1_T_3, UInt<2>(0h2))
node _r1_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_6 = cat(_r1_T_5, UInt<2>(0h1))
node _r1_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_8 = cat(_r1_T_7, UInt<2>(0h3))
node _r1_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_10 = cat(_r1_T_9, UInt<2>(0h2))
node _r1_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_12 = cat(_r1_T_11, UInt<2>(0h3))
node _r1_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_14 = cat(_r1_T_13, UInt<2>(0h2))
node _r1_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_16 = cat(_r1_T_15, UInt<2>(0h0))
node _r1_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_18 = cat(_r1_T_17, UInt<2>(0h1))
node _r1_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r1_T_20 = cat(_r1_T_19, UInt<2>(0h0))
node _r1_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_22 = cat(_r1_T_21, UInt<2>(0h1))
node _r1_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r1_T_24 = cat(_r1_T_23, UInt<2>(0h0))
node _r1_T_25 = eq(_r1_T_24, _r1_T)
node _r1_T_26 = mux(_r1_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _r1_T_27 = mux(_r1_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _r1_T_28 = eq(_r1_T_22, _r1_T)
node _r1_T_29 = mux(_r1_T_28, UInt<1>(0h0), _r1_T_26)
node _r1_T_30 = mux(_r1_T_28, UInt<2>(0h2), _r1_T_27)
node _r1_T_31 = eq(_r1_T_20, _r1_T)
node _r1_T_32 = mux(_r1_T_31, UInt<1>(0h0), _r1_T_29)
node _r1_T_33 = mux(_r1_T_31, UInt<2>(0h1), _r1_T_30)
node _r1_T_34 = eq(_r1_T_18, _r1_T)
node _r1_T_35 = mux(_r1_T_34, UInt<1>(0h0), _r1_T_32)
node _r1_T_36 = mux(_r1_T_34, UInt<2>(0h2), _r1_T_33)
node _r1_T_37 = eq(_r1_T_16, _r1_T)
node _r1_T_38 = mux(_r1_T_37, UInt<1>(0h0), _r1_T_35)
node _r1_T_39 = mux(_r1_T_37, UInt<2>(0h0), _r1_T_36)
node _r1_T_40 = eq(_r1_T_14, _r1_T)
node _r1_T_41 = mux(_r1_T_40, UInt<1>(0h1), _r1_T_38)
node _r1_T_42 = mux(_r1_T_40, UInt<2>(0h3), _r1_T_39)
node _r1_T_43 = eq(_r1_T_12, _r1_T)
node _r1_T_44 = mux(_r1_T_43, UInt<1>(0h1), _r1_T_41)
node _r1_T_45 = mux(_r1_T_43, UInt<2>(0h3), _r1_T_42)
node _r1_T_46 = eq(_r1_T_10, _r1_T)
node _r1_T_47 = mux(_r1_T_46, UInt<1>(0h1), _r1_T_44)
node _r1_T_48 = mux(_r1_T_46, UInt<2>(0h2), _r1_T_45)
node _r1_T_49 = eq(_r1_T_8, _r1_T)
node _r1_T_50 = mux(_r1_T_49, UInt<1>(0h1), _r1_T_47)
node _r1_T_51 = mux(_r1_T_49, UInt<2>(0h3), _r1_T_48)
node _r1_T_52 = eq(_r1_T_6, _r1_T)
node _r1_T_53 = mux(_r1_T_52, UInt<1>(0h1), _r1_T_50)
node _r1_T_54 = mux(_r1_T_52, UInt<2>(0h1), _r1_T_51)
node _r1_T_55 = eq(_r1_T_4, _r1_T)
node _r1_T_56 = mux(_r1_T_55, UInt<1>(0h1), _r1_T_53)
node _r1_T_57 = mux(_r1_T_55, UInt<2>(0h2), _r1_T_54)
node _r1_T_58 = eq(_r1_T_2, _r1_T)
node r1_1 = mux(_r1_T_58, UInt<1>(0h1), _r1_T_56)
node r1_2 = mux(_r1_T_58, UInt<2>(0h3), _r1_T_57)
node _r2_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _r2_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _r2_c_cat_T_2 = or(_r2_c_cat_T, _r2_c_cat_T_1)
node _r2_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _r2_c_cat_T_4 = or(_r2_c_cat_T_2, _r2_c_cat_T_3)
node _r2_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _r2_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _r2_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _r2_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _r2_c_cat_T_9 = or(_r2_c_cat_T_5, _r2_c_cat_T_6)
node _r2_c_cat_T_10 = or(_r2_c_cat_T_9, _r2_c_cat_T_7)
node _r2_c_cat_T_11 = or(_r2_c_cat_T_10, _r2_c_cat_T_8)
node _r2_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _r2_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _r2_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _r2_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _r2_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _r2_c_cat_T_17 = or(_r2_c_cat_T_12, _r2_c_cat_T_13)
node _r2_c_cat_T_18 = or(_r2_c_cat_T_17, _r2_c_cat_T_14)
node _r2_c_cat_T_19 = or(_r2_c_cat_T_18, _r2_c_cat_T_15)
node _r2_c_cat_T_20 = or(_r2_c_cat_T_19, _r2_c_cat_T_16)
node _r2_c_cat_T_21 = or(_r2_c_cat_T_11, _r2_c_cat_T_20)
node _r2_c_cat_T_22 = or(_r2_c_cat_T_4, _r2_c_cat_T_21)
node _r2_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _r2_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _r2_c_cat_T_25 = or(_r2_c_cat_T_23, _r2_c_cat_T_24)
node _r2_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _r2_c_cat_T_27 = or(_r2_c_cat_T_25, _r2_c_cat_T_26)
node _r2_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _r2_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _r2_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _r2_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _r2_c_cat_T_32 = or(_r2_c_cat_T_28, _r2_c_cat_T_29)
node _r2_c_cat_T_33 = or(_r2_c_cat_T_32, _r2_c_cat_T_30)
node _r2_c_cat_T_34 = or(_r2_c_cat_T_33, _r2_c_cat_T_31)
node _r2_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _r2_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _r2_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _r2_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _r2_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _r2_c_cat_T_40 = or(_r2_c_cat_T_35, _r2_c_cat_T_36)
node _r2_c_cat_T_41 = or(_r2_c_cat_T_40, _r2_c_cat_T_37)
node _r2_c_cat_T_42 = or(_r2_c_cat_T_41, _r2_c_cat_T_38)
node _r2_c_cat_T_43 = or(_r2_c_cat_T_42, _r2_c_cat_T_39)
node _r2_c_cat_T_44 = or(_r2_c_cat_T_34, _r2_c_cat_T_43)
node _r2_c_cat_T_45 = or(_r2_c_cat_T_27, _r2_c_cat_T_44)
node _r2_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _r2_c_cat_T_47 = or(_r2_c_cat_T_45, _r2_c_cat_T_46)
node _r2_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _r2_c_cat_T_49 = or(_r2_c_cat_T_47, _r2_c_cat_T_48)
node r2_c = cat(_r2_c_cat_T_22, _r2_c_cat_T_49)
node _r2_T = cat(r2_c, new_coh.state)
node _r2_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_2 = cat(_r2_T_1, UInt<2>(0h3))
node _r2_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_4 = cat(_r2_T_3, UInt<2>(0h2))
node _r2_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_6 = cat(_r2_T_5, UInt<2>(0h1))
node _r2_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_8 = cat(_r2_T_7, UInt<2>(0h3))
node _r2_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_10 = cat(_r2_T_9, UInt<2>(0h2))
node _r2_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_12 = cat(_r2_T_11, UInt<2>(0h3))
node _r2_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_14 = cat(_r2_T_13, UInt<2>(0h2))
node _r2_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_16 = cat(_r2_T_15, UInt<2>(0h0))
node _r2_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_18 = cat(_r2_T_17, UInt<2>(0h1))
node _r2_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r2_T_20 = cat(_r2_T_19, UInt<2>(0h0))
node _r2_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_22 = cat(_r2_T_21, UInt<2>(0h1))
node _r2_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r2_T_24 = cat(_r2_T_23, UInt<2>(0h0))
node _r2_T_25 = eq(_r2_T_24, _r2_T)
node _r2_T_26 = mux(_r2_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _r2_T_27 = mux(_r2_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _r2_T_28 = eq(_r2_T_22, _r2_T)
node _r2_T_29 = mux(_r2_T_28, UInt<1>(0h0), _r2_T_26)
node _r2_T_30 = mux(_r2_T_28, UInt<2>(0h2), _r2_T_27)
node _r2_T_31 = eq(_r2_T_20, _r2_T)
node _r2_T_32 = mux(_r2_T_31, UInt<1>(0h0), _r2_T_29)
node _r2_T_33 = mux(_r2_T_31, UInt<2>(0h1), _r2_T_30)
node _r2_T_34 = eq(_r2_T_18, _r2_T)
node _r2_T_35 = mux(_r2_T_34, UInt<1>(0h0), _r2_T_32)
node _r2_T_36 = mux(_r2_T_34, UInt<2>(0h2), _r2_T_33)
node _r2_T_37 = eq(_r2_T_16, _r2_T)
node _r2_T_38 = mux(_r2_T_37, UInt<1>(0h0), _r2_T_35)
node _r2_T_39 = mux(_r2_T_37, UInt<2>(0h0), _r2_T_36)
node _r2_T_40 = eq(_r2_T_14, _r2_T)
node _r2_T_41 = mux(_r2_T_40, UInt<1>(0h1), _r2_T_38)
node _r2_T_42 = mux(_r2_T_40, UInt<2>(0h3), _r2_T_39)
node _r2_T_43 = eq(_r2_T_12, _r2_T)
node _r2_T_44 = mux(_r2_T_43, UInt<1>(0h1), _r2_T_41)
node _r2_T_45 = mux(_r2_T_43, UInt<2>(0h3), _r2_T_42)
node _r2_T_46 = eq(_r2_T_10, _r2_T)
node _r2_T_47 = mux(_r2_T_46, UInt<1>(0h1), _r2_T_44)
node _r2_T_48 = mux(_r2_T_46, UInt<2>(0h2), _r2_T_45)
node _r2_T_49 = eq(_r2_T_8, _r2_T)
node _r2_T_50 = mux(_r2_T_49, UInt<1>(0h1), _r2_T_47)
node _r2_T_51 = mux(_r2_T_49, UInt<2>(0h3), _r2_T_48)
node _r2_T_52 = eq(_r2_T_6, _r2_T)
node _r2_T_53 = mux(_r2_T_52, UInt<1>(0h1), _r2_T_50)
node _r2_T_54 = mux(_r2_T_52, UInt<2>(0h1), _r2_T_51)
node _r2_T_55 = eq(_r2_T_4, _r2_T)
node _r2_T_56 = mux(_r2_T_55, UInt<1>(0h1), _r2_T_53)
node _r2_T_57 = mux(_r2_T_55, UInt<2>(0h2), _r2_T_54)
node _r2_T_58 = eq(_r2_T_2, _r2_T)
node r2_1 = mux(_r2_T_58, UInt<1>(0h1), _r2_T_56)
node r2_2 = mux(_r2_T_58, UInt<2>(0h3), _r2_T_57)
node _needs_second_acq_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _needs_second_acq_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _needs_second_acq_T_2 = or(_needs_second_acq_T, _needs_second_acq_T_1)
node _needs_second_acq_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _needs_second_acq_T_4 = or(_needs_second_acq_T_2, _needs_second_acq_T_3)
node _needs_second_acq_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _needs_second_acq_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _needs_second_acq_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _needs_second_acq_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _needs_second_acq_T_9 = or(_needs_second_acq_T_5, _needs_second_acq_T_6)
node _needs_second_acq_T_10 = or(_needs_second_acq_T_9, _needs_second_acq_T_7)
node _needs_second_acq_T_11 = or(_needs_second_acq_T_10, _needs_second_acq_T_8)
node _needs_second_acq_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _needs_second_acq_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _needs_second_acq_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _needs_second_acq_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _needs_second_acq_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _needs_second_acq_T_17 = or(_needs_second_acq_T_12, _needs_second_acq_T_13)
node _needs_second_acq_T_18 = or(_needs_second_acq_T_17, _needs_second_acq_T_14)
node _needs_second_acq_T_19 = or(_needs_second_acq_T_18, _needs_second_acq_T_15)
node _needs_second_acq_T_20 = or(_needs_second_acq_T_19, _needs_second_acq_T_16)
node _needs_second_acq_T_21 = or(_needs_second_acq_T_11, _needs_second_acq_T_20)
node _needs_second_acq_T_22 = or(_needs_second_acq_T_4, _needs_second_acq_T_21)
node _needs_second_acq_T_23 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _needs_second_acq_T_24 = or(_needs_second_acq_T_22, _needs_second_acq_T_23)
node _needs_second_acq_T_25 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _needs_second_acq_T_26 = or(_needs_second_acq_T_24, _needs_second_acq_T_25)
node _needs_second_acq_T_27 = eq(req.uop.mem_cmd, UInt<1>(0h1))
node _needs_second_acq_T_28 = eq(req.uop.mem_cmd, UInt<5>(0h11))
node _needs_second_acq_T_29 = or(_needs_second_acq_T_27, _needs_second_acq_T_28)
node _needs_second_acq_T_30 = eq(req.uop.mem_cmd, UInt<3>(0h7))
node _needs_second_acq_T_31 = or(_needs_second_acq_T_29, _needs_second_acq_T_30)
node _needs_second_acq_T_32 = eq(req.uop.mem_cmd, UInt<3>(0h4))
node _needs_second_acq_T_33 = eq(req.uop.mem_cmd, UInt<4>(0h9))
node _needs_second_acq_T_34 = eq(req.uop.mem_cmd, UInt<4>(0ha))
node _needs_second_acq_T_35 = eq(req.uop.mem_cmd, UInt<4>(0hb))
node _needs_second_acq_T_36 = or(_needs_second_acq_T_32, _needs_second_acq_T_33)
node _needs_second_acq_T_37 = or(_needs_second_acq_T_36, _needs_second_acq_T_34)
node _needs_second_acq_T_38 = or(_needs_second_acq_T_37, _needs_second_acq_T_35)
node _needs_second_acq_T_39 = eq(req.uop.mem_cmd, UInt<4>(0h8))
node _needs_second_acq_T_40 = eq(req.uop.mem_cmd, UInt<4>(0hc))
node _needs_second_acq_T_41 = eq(req.uop.mem_cmd, UInt<4>(0hd))
node _needs_second_acq_T_42 = eq(req.uop.mem_cmd, UInt<4>(0he))
node _needs_second_acq_T_43 = eq(req.uop.mem_cmd, UInt<4>(0hf))
node _needs_second_acq_T_44 = or(_needs_second_acq_T_39, _needs_second_acq_T_40)
node _needs_second_acq_T_45 = or(_needs_second_acq_T_44, _needs_second_acq_T_41)
node _needs_second_acq_T_46 = or(_needs_second_acq_T_45, _needs_second_acq_T_42)
node _needs_second_acq_T_47 = or(_needs_second_acq_T_46, _needs_second_acq_T_43)
node _needs_second_acq_T_48 = or(_needs_second_acq_T_38, _needs_second_acq_T_47)
node _needs_second_acq_T_49 = or(_needs_second_acq_T_31, _needs_second_acq_T_48)
node _needs_second_acq_T_50 = eq(req.uop.mem_cmd, UInt<2>(0h3))
node _needs_second_acq_T_51 = or(_needs_second_acq_T_49, _needs_second_acq_T_50)
node _needs_second_acq_T_52 = eq(req.uop.mem_cmd, UInt<3>(0h6))
node _needs_second_acq_T_53 = or(_needs_second_acq_T_51, _needs_second_acq_T_52)
node _needs_second_acq_T_54 = eq(_needs_second_acq_T_53, UInt<1>(0h0))
node cmd_requires_second_acquire = and(_needs_second_acq_T_26, _needs_second_acq_T_54)
node is_hit_again = and(r1_1, r2_1)
node _dirties_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _dirties_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _dirties_cat_T_2 = or(_dirties_cat_T, _dirties_cat_T_1)
node _dirties_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _dirties_cat_T_4 = or(_dirties_cat_T_2, _dirties_cat_T_3)
node _dirties_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _dirties_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _dirties_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _dirties_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _dirties_cat_T_9 = or(_dirties_cat_T_5, _dirties_cat_T_6)
node _dirties_cat_T_10 = or(_dirties_cat_T_9, _dirties_cat_T_7)
node _dirties_cat_T_11 = or(_dirties_cat_T_10, _dirties_cat_T_8)
node _dirties_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _dirties_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _dirties_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _dirties_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _dirties_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _dirties_cat_T_17 = or(_dirties_cat_T_12, _dirties_cat_T_13)
node _dirties_cat_T_18 = or(_dirties_cat_T_17, _dirties_cat_T_14)
node _dirties_cat_T_19 = or(_dirties_cat_T_18, _dirties_cat_T_15)
node _dirties_cat_T_20 = or(_dirties_cat_T_19, _dirties_cat_T_16)
node _dirties_cat_T_21 = or(_dirties_cat_T_11, _dirties_cat_T_20)
node _dirties_cat_T_22 = or(_dirties_cat_T_4, _dirties_cat_T_21)
node _dirties_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _dirties_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _dirties_cat_T_25 = or(_dirties_cat_T_23, _dirties_cat_T_24)
node _dirties_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _dirties_cat_T_27 = or(_dirties_cat_T_25, _dirties_cat_T_26)
node _dirties_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _dirties_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _dirties_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _dirties_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _dirties_cat_T_32 = or(_dirties_cat_T_28, _dirties_cat_T_29)
node _dirties_cat_T_33 = or(_dirties_cat_T_32, _dirties_cat_T_30)
node _dirties_cat_T_34 = or(_dirties_cat_T_33, _dirties_cat_T_31)
node _dirties_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _dirties_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _dirties_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _dirties_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _dirties_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _dirties_cat_T_40 = or(_dirties_cat_T_35, _dirties_cat_T_36)
node _dirties_cat_T_41 = or(_dirties_cat_T_40, _dirties_cat_T_37)
node _dirties_cat_T_42 = or(_dirties_cat_T_41, _dirties_cat_T_38)
node _dirties_cat_T_43 = or(_dirties_cat_T_42, _dirties_cat_T_39)
node _dirties_cat_T_44 = or(_dirties_cat_T_34, _dirties_cat_T_43)
node _dirties_cat_T_45 = or(_dirties_cat_T_27, _dirties_cat_T_44)
node _dirties_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _dirties_cat_T_47 = or(_dirties_cat_T_45, _dirties_cat_T_46)
node _dirties_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _dirties_cat_T_49 = or(_dirties_cat_T_47, _dirties_cat_T_48)
node dirties_cat = cat(_dirties_cat_T_22, _dirties_cat_T_49)
node _dirties_T = cat(UInt<1>(0h1), UInt<1>(0h1))
node dirties = eq(dirties_cat, _dirties_T)
node biggest_grow_param = mux(dirties, r2_2, r1_2)
wire dirtier_coh : { state : UInt<2>}
connect dirtier_coh.state, biggest_grow_param
node dirtier_cmd = mux(dirties, io.req.uop.mem_cmd, req.uop.mem_cmd)
node _T = and(io.mem_grant.ready, io.mem_grant.valid)
node _r_beats1_decode_T = dshl(UInt<12>(0hfff), io.mem_grant.bits.size)
node _r_beats1_decode_T_1 = bits(_r_beats1_decode_T, 11, 0)
node _r_beats1_decode_T_2 = not(_r_beats1_decode_T_1)
node r_beats1_decode = shr(_r_beats1_decode_T_2, 3)
node r_beats1_opdata = bits(io.mem_grant.bits.opcode, 0, 0)
node r_beats1 = mux(r_beats1_opdata, r_beats1_decode, UInt<1>(0h0))
regreset r_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _r_counter1_T = sub(r_counter, UInt<1>(0h1))
node r_counter1 = tail(_r_counter1_T, 1)
node r_1_1 = eq(r_counter, UInt<1>(0h0))
node _r_last_T = eq(r_counter, UInt<1>(0h1))
node _r_last_T_1 = eq(r_beats1, UInt<1>(0h0))
node r_2 = or(_r_last_T, _r_last_T_1)
node refill_done = and(r_2, _T)
node _r_count_T = not(r_counter1)
node r_4 = and(r_beats1, _r_count_T)
when _T :
node _r_counter_T = mux(r_1_1, r_beats1, r_counter1)
connect r_counter, _r_counter_T
node refill_address_inc = shl(r_4, 3)
node _sec_rdy_T = eq(cmd_requires_second_acquire, UInt<1>(0h0))
node _sec_rdy_T_1 = eq(io.req_is_probe, UInt<1>(0h0))
node _sec_rdy_T_2 = and(_sec_rdy_T, _sec_rdy_T_1)
node _sec_rdy_T_3 = eq(state, UInt<5>(0h0))
node _sec_rdy_T_4 = eq(state, UInt<5>(0hd))
node _sec_rdy_T_5 = eq(state, UInt<5>(0he))
node _sec_rdy_T_6 = eq(state, UInt<5>(0hf))
node _sec_rdy_T_7 = or(_sec_rdy_T_3, _sec_rdy_T_4)
node _sec_rdy_T_8 = or(_sec_rdy_T_7, _sec_rdy_T_5)
node _sec_rdy_T_9 = or(_sec_rdy_T_8, _sec_rdy_T_6)
node _sec_rdy_T_10 = eq(_sec_rdy_T_9, UInt<1>(0h0))
node sec_rdy = and(_sec_rdy_T_2, _sec_rdy_T_10)
inst rpq of BranchKillableQueue
connect rpq.clock, clock
connect rpq.reset, reset
connect rpq.io.brupdate.b2.target_offset, io.brupdate.b2.target_offset
connect rpq.io.brupdate.b2.jalr_target, io.brupdate.b2.jalr_target
connect rpq.io.brupdate.b2.pc_sel, io.brupdate.b2.pc_sel
connect rpq.io.brupdate.b2.cfi_type, io.brupdate.b2.cfi_type
connect rpq.io.brupdate.b2.taken, io.brupdate.b2.taken
connect rpq.io.brupdate.b2.mispredict, io.brupdate.b2.mispredict
connect rpq.io.brupdate.b2.valid, io.brupdate.b2.valid
connect rpq.io.brupdate.b2.uop.debug_tsrc, io.brupdate.b2.uop.debug_tsrc
connect rpq.io.brupdate.b2.uop.debug_fsrc, io.brupdate.b2.uop.debug_fsrc
connect rpq.io.brupdate.b2.uop.bp_xcpt_if, io.brupdate.b2.uop.bp_xcpt_if
connect rpq.io.brupdate.b2.uop.bp_debug_if, io.brupdate.b2.uop.bp_debug_if
connect rpq.io.brupdate.b2.uop.xcpt_ma_if, io.brupdate.b2.uop.xcpt_ma_if
connect rpq.io.brupdate.b2.uop.xcpt_ae_if, io.brupdate.b2.uop.xcpt_ae_if
connect rpq.io.brupdate.b2.uop.xcpt_pf_if, io.brupdate.b2.uop.xcpt_pf_if
connect rpq.io.brupdate.b2.uop.fp_single, io.brupdate.b2.uop.fp_single
connect rpq.io.brupdate.b2.uop.fp_val, io.brupdate.b2.uop.fp_val
connect rpq.io.brupdate.b2.uop.frs3_en, io.brupdate.b2.uop.frs3_en
connect rpq.io.brupdate.b2.uop.lrs2_rtype, io.brupdate.b2.uop.lrs2_rtype
connect rpq.io.brupdate.b2.uop.lrs1_rtype, io.brupdate.b2.uop.lrs1_rtype
connect rpq.io.brupdate.b2.uop.dst_rtype, io.brupdate.b2.uop.dst_rtype
connect rpq.io.brupdate.b2.uop.ldst_val, io.brupdate.b2.uop.ldst_val
connect rpq.io.brupdate.b2.uop.lrs3, io.brupdate.b2.uop.lrs3
connect rpq.io.brupdate.b2.uop.lrs2, io.brupdate.b2.uop.lrs2
connect rpq.io.brupdate.b2.uop.lrs1, io.brupdate.b2.uop.lrs1
connect rpq.io.brupdate.b2.uop.ldst, io.brupdate.b2.uop.ldst
connect rpq.io.brupdate.b2.uop.ldst_is_rs1, io.brupdate.b2.uop.ldst_is_rs1
connect rpq.io.brupdate.b2.uop.flush_on_commit, io.brupdate.b2.uop.flush_on_commit
connect rpq.io.brupdate.b2.uop.is_unique, io.brupdate.b2.uop.is_unique
connect rpq.io.brupdate.b2.uop.is_sys_pc2epc, io.brupdate.b2.uop.is_sys_pc2epc
connect rpq.io.brupdate.b2.uop.uses_stq, io.brupdate.b2.uop.uses_stq
connect rpq.io.brupdate.b2.uop.uses_ldq, io.brupdate.b2.uop.uses_ldq
connect rpq.io.brupdate.b2.uop.is_amo, io.brupdate.b2.uop.is_amo
connect rpq.io.brupdate.b2.uop.is_fencei, io.brupdate.b2.uop.is_fencei
connect rpq.io.brupdate.b2.uop.is_fence, io.brupdate.b2.uop.is_fence
connect rpq.io.brupdate.b2.uop.mem_signed, io.brupdate.b2.uop.mem_signed
connect rpq.io.brupdate.b2.uop.mem_size, io.brupdate.b2.uop.mem_size
connect rpq.io.brupdate.b2.uop.mem_cmd, io.brupdate.b2.uop.mem_cmd
connect rpq.io.brupdate.b2.uop.bypassable, io.brupdate.b2.uop.bypassable
connect rpq.io.brupdate.b2.uop.exc_cause, io.brupdate.b2.uop.exc_cause
connect rpq.io.brupdate.b2.uop.exception, io.brupdate.b2.uop.exception
connect rpq.io.brupdate.b2.uop.stale_pdst, io.brupdate.b2.uop.stale_pdst
connect rpq.io.brupdate.b2.uop.ppred_busy, io.brupdate.b2.uop.ppred_busy
connect rpq.io.brupdate.b2.uop.prs3_busy, io.brupdate.b2.uop.prs3_busy
connect rpq.io.brupdate.b2.uop.prs2_busy, io.brupdate.b2.uop.prs2_busy
connect rpq.io.brupdate.b2.uop.prs1_busy, io.brupdate.b2.uop.prs1_busy
connect rpq.io.brupdate.b2.uop.ppred, io.brupdate.b2.uop.ppred
connect rpq.io.brupdate.b2.uop.prs3, io.brupdate.b2.uop.prs3
connect rpq.io.brupdate.b2.uop.prs2, io.brupdate.b2.uop.prs2
connect rpq.io.brupdate.b2.uop.prs1, io.brupdate.b2.uop.prs1
connect rpq.io.brupdate.b2.uop.pdst, io.brupdate.b2.uop.pdst
connect rpq.io.brupdate.b2.uop.rxq_idx, io.brupdate.b2.uop.rxq_idx
connect rpq.io.brupdate.b2.uop.stq_idx, io.brupdate.b2.uop.stq_idx
connect rpq.io.brupdate.b2.uop.ldq_idx, io.brupdate.b2.uop.ldq_idx
connect rpq.io.brupdate.b2.uop.rob_idx, io.brupdate.b2.uop.rob_idx
connect rpq.io.brupdate.b2.uop.csr_addr, io.brupdate.b2.uop.csr_addr
connect rpq.io.brupdate.b2.uop.imm_packed, io.brupdate.b2.uop.imm_packed
connect rpq.io.brupdate.b2.uop.taken, io.brupdate.b2.uop.taken
connect rpq.io.brupdate.b2.uop.pc_lob, io.brupdate.b2.uop.pc_lob
connect rpq.io.brupdate.b2.uop.edge_inst, io.brupdate.b2.uop.edge_inst
connect rpq.io.brupdate.b2.uop.ftq_idx, io.brupdate.b2.uop.ftq_idx
connect rpq.io.brupdate.b2.uop.br_tag, io.brupdate.b2.uop.br_tag
connect rpq.io.brupdate.b2.uop.br_mask, io.brupdate.b2.uop.br_mask
connect rpq.io.brupdate.b2.uop.is_sfb, io.brupdate.b2.uop.is_sfb
connect rpq.io.brupdate.b2.uop.is_jal, io.brupdate.b2.uop.is_jal
connect rpq.io.brupdate.b2.uop.is_jalr, io.brupdate.b2.uop.is_jalr
connect rpq.io.brupdate.b2.uop.is_br, io.brupdate.b2.uop.is_br
connect rpq.io.brupdate.b2.uop.iw_p2_poisoned, io.brupdate.b2.uop.iw_p2_poisoned
connect rpq.io.brupdate.b2.uop.iw_p1_poisoned, io.brupdate.b2.uop.iw_p1_poisoned
connect rpq.io.brupdate.b2.uop.iw_state, io.brupdate.b2.uop.iw_state
connect rpq.io.brupdate.b2.uop.ctrl.is_std, io.brupdate.b2.uop.ctrl.is_std
connect rpq.io.brupdate.b2.uop.ctrl.is_sta, io.brupdate.b2.uop.ctrl.is_sta
connect rpq.io.brupdate.b2.uop.ctrl.is_load, io.brupdate.b2.uop.ctrl.is_load
connect rpq.io.brupdate.b2.uop.ctrl.csr_cmd, io.brupdate.b2.uop.ctrl.csr_cmd
connect rpq.io.brupdate.b2.uop.ctrl.fcn_dw, io.brupdate.b2.uop.ctrl.fcn_dw
connect rpq.io.brupdate.b2.uop.ctrl.op_fcn, io.brupdate.b2.uop.ctrl.op_fcn
connect rpq.io.brupdate.b2.uop.ctrl.imm_sel, io.brupdate.b2.uop.ctrl.imm_sel
connect rpq.io.brupdate.b2.uop.ctrl.op2_sel, io.brupdate.b2.uop.ctrl.op2_sel
connect rpq.io.brupdate.b2.uop.ctrl.op1_sel, io.brupdate.b2.uop.ctrl.op1_sel
connect rpq.io.brupdate.b2.uop.ctrl.br_type, io.brupdate.b2.uop.ctrl.br_type
connect rpq.io.brupdate.b2.uop.fu_code, io.brupdate.b2.uop.fu_code
connect rpq.io.brupdate.b2.uop.iq_type, io.brupdate.b2.uop.iq_type
connect rpq.io.brupdate.b2.uop.debug_pc, io.brupdate.b2.uop.debug_pc
connect rpq.io.brupdate.b2.uop.is_rvc, io.brupdate.b2.uop.is_rvc
connect rpq.io.brupdate.b2.uop.debug_inst, io.brupdate.b2.uop.debug_inst
connect rpq.io.brupdate.b2.uop.inst, io.brupdate.b2.uop.inst
connect rpq.io.brupdate.b2.uop.uopc, io.brupdate.b2.uop.uopc
connect rpq.io.brupdate.b1.mispredict_mask, io.brupdate.b1.mispredict_mask
connect rpq.io.brupdate.b1.resolve_mask, io.brupdate.b1.resolve_mask
connect rpq.io.flush, io.exception
node _T_1 = eq(state, UInt<5>(0h0))
node _T_2 = eq(rpq.io.empty, UInt<1>(0h0))
node _T_3 = and(_T_1, _T_2)
node _T_4 = eq(_T_3, UInt<1>(0h0))
node _T_5 = asUInt(reset)
node _T_6 = eq(_T_5, UInt<1>(0h0))
when _T_6 :
node _T_7 = eq(_T_4, UInt<1>(0h0))
when _T_7 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:131 assert(!(state === s_invalid && !rpq.io.empty))\n") : printf
assert(clock, _T_4, UInt<1>(0h1), "") : assert
node _rpq_io_enq_valid_T = and(io.req_pri_val, io.req_pri_rdy)
node _rpq_io_enq_valid_T_1 = and(io.req_sec_val, io.req_sec_rdy)
node _rpq_io_enq_valid_T_2 = or(_rpq_io_enq_valid_T, _rpq_io_enq_valid_T_1)
node _rpq_io_enq_valid_T_3 = eq(io.req.uop.mem_cmd, UInt<2>(0h2))
node _rpq_io_enq_valid_T_4 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _rpq_io_enq_valid_T_5 = or(_rpq_io_enq_valid_T_3, _rpq_io_enq_valid_T_4)
node _rpq_io_enq_valid_T_6 = eq(_rpq_io_enq_valid_T_5, UInt<1>(0h0))
node _rpq_io_enq_valid_T_7 = and(_rpq_io_enq_valid_T_2, _rpq_io_enq_valid_T_6)
connect rpq.io.enq.valid, _rpq_io_enq_valid_T_7
connect rpq.io.enq.bits.sdq_id, io.req.sdq_id
connect rpq.io.enq.bits.way_en, io.req.way_en
connect rpq.io.enq.bits.old_meta.tag, io.req.old_meta.tag
connect rpq.io.enq.bits.old_meta.coh.state, io.req.old_meta.coh.state
connect rpq.io.enq.bits.tag_match, io.req.tag_match
connect rpq.io.enq.bits.is_hella, io.req.is_hella
connect rpq.io.enq.bits.data, io.req.data
connect rpq.io.enq.bits.addr, io.req.addr
connect rpq.io.enq.bits.uop.debug_tsrc, io.req.uop.debug_tsrc
connect rpq.io.enq.bits.uop.debug_fsrc, io.req.uop.debug_fsrc
connect rpq.io.enq.bits.uop.bp_xcpt_if, io.req.uop.bp_xcpt_if
connect rpq.io.enq.bits.uop.bp_debug_if, io.req.uop.bp_debug_if
connect rpq.io.enq.bits.uop.xcpt_ma_if, io.req.uop.xcpt_ma_if
connect rpq.io.enq.bits.uop.xcpt_ae_if, io.req.uop.xcpt_ae_if
connect rpq.io.enq.bits.uop.xcpt_pf_if, io.req.uop.xcpt_pf_if
connect rpq.io.enq.bits.uop.fp_single, io.req.uop.fp_single
connect rpq.io.enq.bits.uop.fp_val, io.req.uop.fp_val
connect rpq.io.enq.bits.uop.frs3_en, io.req.uop.frs3_en
connect rpq.io.enq.bits.uop.lrs2_rtype, io.req.uop.lrs2_rtype
connect rpq.io.enq.bits.uop.lrs1_rtype, io.req.uop.lrs1_rtype
connect rpq.io.enq.bits.uop.dst_rtype, io.req.uop.dst_rtype
connect rpq.io.enq.bits.uop.ldst_val, io.req.uop.ldst_val
connect rpq.io.enq.bits.uop.lrs3, io.req.uop.lrs3
connect rpq.io.enq.bits.uop.lrs2, io.req.uop.lrs2
connect rpq.io.enq.bits.uop.lrs1, io.req.uop.lrs1
connect rpq.io.enq.bits.uop.ldst, io.req.uop.ldst
connect rpq.io.enq.bits.uop.ldst_is_rs1, io.req.uop.ldst_is_rs1
connect rpq.io.enq.bits.uop.flush_on_commit, io.req.uop.flush_on_commit
connect rpq.io.enq.bits.uop.is_unique, io.req.uop.is_unique
connect rpq.io.enq.bits.uop.is_sys_pc2epc, io.req.uop.is_sys_pc2epc
connect rpq.io.enq.bits.uop.uses_stq, io.req.uop.uses_stq
connect rpq.io.enq.bits.uop.uses_ldq, io.req.uop.uses_ldq
connect rpq.io.enq.bits.uop.is_amo, io.req.uop.is_amo
connect rpq.io.enq.bits.uop.is_fencei, io.req.uop.is_fencei
connect rpq.io.enq.bits.uop.is_fence, io.req.uop.is_fence
connect rpq.io.enq.bits.uop.mem_signed, io.req.uop.mem_signed
connect rpq.io.enq.bits.uop.mem_size, io.req.uop.mem_size
connect rpq.io.enq.bits.uop.mem_cmd, io.req.uop.mem_cmd
connect rpq.io.enq.bits.uop.bypassable, io.req.uop.bypassable
connect rpq.io.enq.bits.uop.exc_cause, io.req.uop.exc_cause
connect rpq.io.enq.bits.uop.exception, io.req.uop.exception
connect rpq.io.enq.bits.uop.stale_pdst, io.req.uop.stale_pdst
connect rpq.io.enq.bits.uop.ppred_busy, io.req.uop.ppred_busy
connect rpq.io.enq.bits.uop.prs3_busy, io.req.uop.prs3_busy
connect rpq.io.enq.bits.uop.prs2_busy, io.req.uop.prs2_busy
connect rpq.io.enq.bits.uop.prs1_busy, io.req.uop.prs1_busy
connect rpq.io.enq.bits.uop.ppred, io.req.uop.ppred
connect rpq.io.enq.bits.uop.prs3, io.req.uop.prs3
connect rpq.io.enq.bits.uop.prs2, io.req.uop.prs2
connect rpq.io.enq.bits.uop.prs1, io.req.uop.prs1
connect rpq.io.enq.bits.uop.pdst, io.req.uop.pdst
connect rpq.io.enq.bits.uop.rxq_idx, io.req.uop.rxq_idx
connect rpq.io.enq.bits.uop.stq_idx, io.req.uop.stq_idx
connect rpq.io.enq.bits.uop.ldq_idx, io.req.uop.ldq_idx
connect rpq.io.enq.bits.uop.rob_idx, io.req.uop.rob_idx
connect rpq.io.enq.bits.uop.csr_addr, io.req.uop.csr_addr
connect rpq.io.enq.bits.uop.imm_packed, io.req.uop.imm_packed
connect rpq.io.enq.bits.uop.taken, io.req.uop.taken
connect rpq.io.enq.bits.uop.pc_lob, io.req.uop.pc_lob
connect rpq.io.enq.bits.uop.edge_inst, io.req.uop.edge_inst
connect rpq.io.enq.bits.uop.ftq_idx, io.req.uop.ftq_idx
connect rpq.io.enq.bits.uop.br_tag, io.req.uop.br_tag
connect rpq.io.enq.bits.uop.br_mask, io.req.uop.br_mask
connect rpq.io.enq.bits.uop.is_sfb, io.req.uop.is_sfb
connect rpq.io.enq.bits.uop.is_jal, io.req.uop.is_jal
connect rpq.io.enq.bits.uop.is_jalr, io.req.uop.is_jalr
connect rpq.io.enq.bits.uop.is_br, io.req.uop.is_br
connect rpq.io.enq.bits.uop.iw_p2_poisoned, io.req.uop.iw_p2_poisoned
connect rpq.io.enq.bits.uop.iw_p1_poisoned, io.req.uop.iw_p1_poisoned
connect rpq.io.enq.bits.uop.iw_state, io.req.uop.iw_state
connect rpq.io.enq.bits.uop.ctrl.is_std, io.req.uop.ctrl.is_std
connect rpq.io.enq.bits.uop.ctrl.is_sta, io.req.uop.ctrl.is_sta
connect rpq.io.enq.bits.uop.ctrl.is_load, io.req.uop.ctrl.is_load
connect rpq.io.enq.bits.uop.ctrl.csr_cmd, io.req.uop.ctrl.csr_cmd
connect rpq.io.enq.bits.uop.ctrl.fcn_dw, io.req.uop.ctrl.fcn_dw
connect rpq.io.enq.bits.uop.ctrl.op_fcn, io.req.uop.ctrl.op_fcn
connect rpq.io.enq.bits.uop.ctrl.imm_sel, io.req.uop.ctrl.imm_sel
connect rpq.io.enq.bits.uop.ctrl.op2_sel, io.req.uop.ctrl.op2_sel
connect rpq.io.enq.bits.uop.ctrl.op1_sel, io.req.uop.ctrl.op1_sel
connect rpq.io.enq.bits.uop.ctrl.br_type, io.req.uop.ctrl.br_type
connect rpq.io.enq.bits.uop.fu_code, io.req.uop.fu_code
connect rpq.io.enq.bits.uop.iq_type, io.req.uop.iq_type
connect rpq.io.enq.bits.uop.debug_pc, io.req.uop.debug_pc
connect rpq.io.enq.bits.uop.is_rvc, io.req.uop.is_rvc
connect rpq.io.enq.bits.uop.debug_inst, io.req.uop.debug_inst
connect rpq.io.enq.bits.uop.inst, io.req.uop.inst
connect rpq.io.enq.bits.uop.uopc, io.req.uop.uopc
connect rpq.io.deq.ready, UInt<1>(0h0)
reg grantack : { valid : UInt<1>, bits : { sink : UInt<3>}}, clock
reg refill_ctr : UInt<3>, clock
reg commit_line : UInt<1>, clock
reg grant_had_data : UInt<1>, clock
reg finish_to_prefetch : UInt<1>, clock
regreset meta_hazard : UInt<2>, clock, reset, UInt<2>(0h0)
node _T_8 = neq(meta_hazard, UInt<1>(0h0))
when _T_8 :
node _meta_hazard_T = add(meta_hazard, UInt<1>(0h1))
node _meta_hazard_T_1 = tail(_meta_hazard_T, 1)
connect meta_hazard, _meta_hazard_T_1
node _T_9 = and(io.meta_write.ready, io.meta_write.valid)
when _T_9 :
connect meta_hazard, UInt<1>(0h1)
node _io_probe_rdy_T = eq(meta_hazard, UInt<1>(0h0))
node _io_probe_rdy_T_1 = eq(state, UInt<5>(0h0))
node _io_probe_rdy_T_2 = eq(state, UInt<5>(0h1))
node _io_probe_rdy_T_3 = eq(state, UInt<5>(0h2))
node _io_probe_rdy_T_4 = eq(state, UInt<5>(0h3))
node _io_probe_rdy_T_5 = or(_io_probe_rdy_T_1, _io_probe_rdy_T_2)
node _io_probe_rdy_T_6 = or(_io_probe_rdy_T_5, _io_probe_rdy_T_3)
node _io_probe_rdy_T_7 = or(_io_probe_rdy_T_6, _io_probe_rdy_T_4)
node _io_probe_rdy_T_8 = eq(state, UInt<5>(0h4))
node _io_probe_rdy_T_9 = and(_io_probe_rdy_T_8, grantack.valid)
node _io_probe_rdy_T_10 = or(_io_probe_rdy_T_7, _io_probe_rdy_T_9)
node _io_probe_rdy_T_11 = and(_io_probe_rdy_T, _io_probe_rdy_T_10)
connect io.probe_rdy, _io_probe_rdy_T_11
node _io_idx_valid_T = neq(state, UInt<5>(0h0))
connect io.idx.valid, _io_idx_valid_T
node _io_tag_valid_T = neq(state, UInt<5>(0h0))
connect io.tag.valid, _io_tag_valid_T
node _io_way_valid_T = eq(state, UInt<5>(0h0))
node _io_way_valid_T_1 = eq(state, UInt<5>(0h11))
node _io_way_valid_T_2 = or(_io_way_valid_T, _io_way_valid_T_1)
node _io_way_valid_T_3 = eq(_io_way_valid_T_2, UInt<1>(0h0))
connect io.way.valid, _io_way_valid_T_3
connect io.idx.bits, req_idx
connect io.tag.bits, req_tag
connect io.way.bits, req.way_en
connect io.meta_write.valid, UInt<1>(0h0)
invalidate io.meta_write.bits.data.tag
invalidate io.meta_write.bits.data.coh.state
invalidate io.meta_write.bits.tag
invalidate io.meta_write.bits.way_en
invalidate io.meta_write.bits.idx
connect io.req_pri_rdy, UInt<1>(0h0)
node _io_req_sec_rdy_T = and(sec_rdy, rpq.io.enq.ready)
connect io.req_sec_rdy, _io_req_sec_rdy_T
connect io.mem_acquire.valid, UInt<1>(0h0)
invalidate io.mem_acquire.bits.corrupt
invalidate io.mem_acquire.bits.data
invalidate io.mem_acquire.bits.mask
invalidate io.mem_acquire.bits.address
invalidate io.mem_acquire.bits.source
invalidate io.mem_acquire.bits.size
invalidate io.mem_acquire.bits.param
invalidate io.mem_acquire.bits.opcode
connect io.refill.valid, UInt<1>(0h0)
invalidate io.refill.bits.data
invalidate io.refill.bits.wmask
invalidate io.refill.bits.addr
invalidate io.refill.bits.way_en
connect io.replay.valid, UInt<1>(0h0)
invalidate io.replay.bits.sdq_id
invalidate io.replay.bits.way_en
invalidate io.replay.bits.old_meta.tag
invalidate io.replay.bits.old_meta.coh.state
invalidate io.replay.bits.tag_match
invalidate io.replay.bits.is_hella
invalidate io.replay.bits.data
invalidate io.replay.bits.addr
invalidate io.replay.bits.uop.debug_tsrc
invalidate io.replay.bits.uop.debug_fsrc
invalidate io.replay.bits.uop.bp_xcpt_if
invalidate io.replay.bits.uop.bp_debug_if
invalidate io.replay.bits.uop.xcpt_ma_if
invalidate io.replay.bits.uop.xcpt_ae_if
invalidate io.replay.bits.uop.xcpt_pf_if
invalidate io.replay.bits.uop.fp_single
invalidate io.replay.bits.uop.fp_val
invalidate io.replay.bits.uop.frs3_en
invalidate io.replay.bits.uop.lrs2_rtype
invalidate io.replay.bits.uop.lrs1_rtype
invalidate io.replay.bits.uop.dst_rtype
invalidate io.replay.bits.uop.ldst_val
invalidate io.replay.bits.uop.lrs3
invalidate io.replay.bits.uop.lrs2
invalidate io.replay.bits.uop.lrs1
invalidate io.replay.bits.uop.ldst
invalidate io.replay.bits.uop.ldst_is_rs1
invalidate io.replay.bits.uop.flush_on_commit
invalidate io.replay.bits.uop.is_unique
invalidate io.replay.bits.uop.is_sys_pc2epc
invalidate io.replay.bits.uop.uses_stq
invalidate io.replay.bits.uop.uses_ldq
invalidate io.replay.bits.uop.is_amo
invalidate io.replay.bits.uop.is_fencei
invalidate io.replay.bits.uop.is_fence
invalidate io.replay.bits.uop.mem_signed
invalidate io.replay.bits.uop.mem_size
invalidate io.replay.bits.uop.mem_cmd
invalidate io.replay.bits.uop.bypassable
invalidate io.replay.bits.uop.exc_cause
invalidate io.replay.bits.uop.exception
invalidate io.replay.bits.uop.stale_pdst
invalidate io.replay.bits.uop.ppred_busy
invalidate io.replay.bits.uop.prs3_busy
invalidate io.replay.bits.uop.prs2_busy
invalidate io.replay.bits.uop.prs1_busy
invalidate io.replay.bits.uop.ppred
invalidate io.replay.bits.uop.prs3
invalidate io.replay.bits.uop.prs2
invalidate io.replay.bits.uop.prs1
invalidate io.replay.bits.uop.pdst
invalidate io.replay.bits.uop.rxq_idx
invalidate io.replay.bits.uop.stq_idx
invalidate io.replay.bits.uop.ldq_idx
invalidate io.replay.bits.uop.rob_idx
invalidate io.replay.bits.uop.csr_addr
invalidate io.replay.bits.uop.imm_packed
invalidate io.replay.bits.uop.taken
invalidate io.replay.bits.uop.pc_lob
invalidate io.replay.bits.uop.edge_inst
invalidate io.replay.bits.uop.ftq_idx
invalidate io.replay.bits.uop.br_tag
invalidate io.replay.bits.uop.br_mask
invalidate io.replay.bits.uop.is_sfb
invalidate io.replay.bits.uop.is_jal
invalidate io.replay.bits.uop.is_jalr
invalidate io.replay.bits.uop.is_br
invalidate io.replay.bits.uop.iw_p2_poisoned
invalidate io.replay.bits.uop.iw_p1_poisoned
invalidate io.replay.bits.uop.iw_state
invalidate io.replay.bits.uop.ctrl.is_std
invalidate io.replay.bits.uop.ctrl.is_sta
invalidate io.replay.bits.uop.ctrl.is_load
invalidate io.replay.bits.uop.ctrl.csr_cmd
invalidate io.replay.bits.uop.ctrl.fcn_dw
invalidate io.replay.bits.uop.ctrl.op_fcn
invalidate io.replay.bits.uop.ctrl.imm_sel
invalidate io.replay.bits.uop.ctrl.op2_sel
invalidate io.replay.bits.uop.ctrl.op1_sel
invalidate io.replay.bits.uop.ctrl.br_type
invalidate io.replay.bits.uop.fu_code
invalidate io.replay.bits.uop.iq_type
invalidate io.replay.bits.uop.debug_pc
invalidate io.replay.bits.uop.is_rvc
invalidate io.replay.bits.uop.debug_inst
invalidate io.replay.bits.uop.inst
invalidate io.replay.bits.uop.uopc
connect io.wb_req.valid, UInt<1>(0h0)
invalidate io.wb_req.bits.voluntary
invalidate io.wb_req.bits.way_en
invalidate io.wb_req.bits.param
invalidate io.wb_req.bits.source
invalidate io.wb_req.bits.idx
invalidate io.wb_req.bits.tag
connect io.resp.valid, UInt<1>(0h0)
invalidate io.resp.bits.is_hella
invalidate io.resp.bits.data
invalidate io.resp.bits.uop.debug_tsrc
invalidate io.resp.bits.uop.debug_fsrc
invalidate io.resp.bits.uop.bp_xcpt_if
invalidate io.resp.bits.uop.bp_debug_if
invalidate io.resp.bits.uop.xcpt_ma_if
invalidate io.resp.bits.uop.xcpt_ae_if
invalidate io.resp.bits.uop.xcpt_pf_if
invalidate io.resp.bits.uop.fp_single
invalidate io.resp.bits.uop.fp_val
invalidate io.resp.bits.uop.frs3_en
invalidate io.resp.bits.uop.lrs2_rtype
invalidate io.resp.bits.uop.lrs1_rtype
invalidate io.resp.bits.uop.dst_rtype
invalidate io.resp.bits.uop.ldst_val
invalidate io.resp.bits.uop.lrs3
invalidate io.resp.bits.uop.lrs2
invalidate io.resp.bits.uop.lrs1
invalidate io.resp.bits.uop.ldst
invalidate io.resp.bits.uop.ldst_is_rs1
invalidate io.resp.bits.uop.flush_on_commit
invalidate io.resp.bits.uop.is_unique
invalidate io.resp.bits.uop.is_sys_pc2epc
invalidate io.resp.bits.uop.uses_stq
invalidate io.resp.bits.uop.uses_ldq
invalidate io.resp.bits.uop.is_amo
invalidate io.resp.bits.uop.is_fencei
invalidate io.resp.bits.uop.is_fence
invalidate io.resp.bits.uop.mem_signed
invalidate io.resp.bits.uop.mem_size
invalidate io.resp.bits.uop.mem_cmd
invalidate io.resp.bits.uop.bypassable
invalidate io.resp.bits.uop.exc_cause
invalidate io.resp.bits.uop.exception
invalidate io.resp.bits.uop.stale_pdst
invalidate io.resp.bits.uop.ppred_busy
invalidate io.resp.bits.uop.prs3_busy
invalidate io.resp.bits.uop.prs2_busy
invalidate io.resp.bits.uop.prs1_busy
invalidate io.resp.bits.uop.ppred
invalidate io.resp.bits.uop.prs3
invalidate io.resp.bits.uop.prs2
invalidate io.resp.bits.uop.prs1
invalidate io.resp.bits.uop.pdst
invalidate io.resp.bits.uop.rxq_idx
invalidate io.resp.bits.uop.stq_idx
invalidate io.resp.bits.uop.ldq_idx
invalidate io.resp.bits.uop.rob_idx
invalidate io.resp.bits.uop.csr_addr
invalidate io.resp.bits.uop.imm_packed
invalidate io.resp.bits.uop.taken
invalidate io.resp.bits.uop.pc_lob
invalidate io.resp.bits.uop.edge_inst
invalidate io.resp.bits.uop.ftq_idx
invalidate io.resp.bits.uop.br_tag
invalidate io.resp.bits.uop.br_mask
invalidate io.resp.bits.uop.is_sfb
invalidate io.resp.bits.uop.is_jal
invalidate io.resp.bits.uop.is_jalr
invalidate io.resp.bits.uop.is_br
invalidate io.resp.bits.uop.iw_p2_poisoned
invalidate io.resp.bits.uop.iw_p1_poisoned
invalidate io.resp.bits.uop.iw_state
invalidate io.resp.bits.uop.ctrl.is_std
invalidate io.resp.bits.uop.ctrl.is_sta
invalidate io.resp.bits.uop.ctrl.is_load
invalidate io.resp.bits.uop.ctrl.csr_cmd
invalidate io.resp.bits.uop.ctrl.fcn_dw
invalidate io.resp.bits.uop.ctrl.op_fcn
invalidate io.resp.bits.uop.ctrl.imm_sel
invalidate io.resp.bits.uop.ctrl.op2_sel
invalidate io.resp.bits.uop.ctrl.op1_sel
invalidate io.resp.bits.uop.ctrl.br_type
invalidate io.resp.bits.uop.fu_code
invalidate io.resp.bits.uop.iq_type
invalidate io.resp.bits.uop.debug_pc
invalidate io.resp.bits.uop.is_rvc
invalidate io.resp.bits.uop.debug_inst
invalidate io.resp.bits.uop.inst
invalidate io.resp.bits.uop.uopc
connect io.commit_val, UInt<1>(0h0)
connect io.commit_addr, req.addr
connect io.commit_coh, coh_on_grant
connect io.meta_read.valid, UInt<1>(0h0)
invalidate io.meta_read.bits.tag
invalidate io.meta_read.bits.way_en
invalidate io.meta_read.bits.idx
connect io.mem_finish.valid, UInt<1>(0h0)
invalidate io.mem_finish.bits.sink
connect io.lb_write.valid, UInt<1>(0h0)
invalidate io.lb_write.bits.data
invalidate io.lb_write.bits.offset
invalidate io.lb_write.bits.id
connect io.lb_read.valid, UInt<1>(0h0)
invalidate io.lb_read.bits.offset
invalidate io.lb_read.bits.id
connect io.mem_grant.ready, UInt<1>(0h0)
node _T_10 = and(io.req_sec_val, io.req_sec_rdy)
when _T_10 :
connect req.uop.mem_cmd, dirtier_cmd
when is_hit_again :
connect new_coh, dirtier_coh
node _T_11 = eq(state, UInt<5>(0h0))
when _T_11 :
connect io.req_pri_rdy, UInt<1>(0h1)
connect grant_had_data, UInt<1>(0h0)
node _T_12 = and(io.req_pri_val, io.req_pri_rdy)
when _T_12 :
wire state_new_state : UInt
connect state_new_state, state
connect grantack.valid, UInt<1>(0h0)
connect refill_ctr, UInt<1>(0h0)
node _state_T = asUInt(reset)
node _state_T_1 = eq(_state_T, UInt<1>(0h0))
when _state_T_1 :
node _state_T_2 = eq(rpq.io.enq.ready, UInt<1>(0h0))
when _state_T_2 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:194 assert(rpq.io.enq.ready)\n") : state_printf
assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert
connect req, io.req
node _state_req_needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10))
node _state_req_needs_wb_r_T_1 = mux(_state_req_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2))
node _state_req_needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _state_req_needs_wb_r_T_3 = mux(_state_req_needs_wb_r_T_2, UInt<2>(0h1), _state_req_needs_wb_r_T_1)
node _state_req_needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _state_req_needs_wb_r_T_5 = mux(_state_req_needs_wb_r_T_4, UInt<2>(0h0), _state_req_needs_wb_r_T_3)
node _state_req_needs_wb_r_T_6 = cat(_state_req_needs_wb_r_T_5, io.req.old_meta.coh.state)
node _state_req_needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _state_req_needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _state_req_needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _state_req_needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _state_req_needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _state_req_needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _state_req_needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _state_req_needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _state_req_needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _state_req_needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _state_req_needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _state_req_needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _state_req_needs_wb_r_T_19 = eq(_state_req_needs_wb_r_T_18, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_20 = mux(_state_req_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0))
node _state_req_needs_wb_r_T_21 = mux(_state_req_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0))
node _state_req_needs_wb_r_T_22 = mux(_state_req_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0))
node _state_req_needs_wb_r_T_23 = eq(_state_req_needs_wb_r_T_17, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_24 = mux(_state_req_needs_wb_r_T_23, UInt<1>(0h0), _state_req_needs_wb_r_T_20)
node _state_req_needs_wb_r_T_25 = mux(_state_req_needs_wb_r_T_23, UInt<3>(0h2), _state_req_needs_wb_r_T_21)
node _state_req_needs_wb_r_T_26 = mux(_state_req_needs_wb_r_T_23, UInt<2>(0h0), _state_req_needs_wb_r_T_22)
node _state_req_needs_wb_r_T_27 = eq(_state_req_needs_wb_r_T_16, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_28 = mux(_state_req_needs_wb_r_T_27, UInt<1>(0h0), _state_req_needs_wb_r_T_24)
node _state_req_needs_wb_r_T_29 = mux(_state_req_needs_wb_r_T_27, UInt<3>(0h1), _state_req_needs_wb_r_T_25)
node _state_req_needs_wb_r_T_30 = mux(_state_req_needs_wb_r_T_27, UInt<2>(0h0), _state_req_needs_wb_r_T_26)
node _state_req_needs_wb_r_T_31 = eq(_state_req_needs_wb_r_T_15, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_32 = mux(_state_req_needs_wb_r_T_31, UInt<1>(0h1), _state_req_needs_wb_r_T_28)
node _state_req_needs_wb_r_T_33 = mux(_state_req_needs_wb_r_T_31, UInt<3>(0h1), _state_req_needs_wb_r_T_29)
node _state_req_needs_wb_r_T_34 = mux(_state_req_needs_wb_r_T_31, UInt<2>(0h0), _state_req_needs_wb_r_T_30)
node _state_req_needs_wb_r_T_35 = eq(_state_req_needs_wb_r_T_14, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_36 = mux(_state_req_needs_wb_r_T_35, UInt<1>(0h0), _state_req_needs_wb_r_T_32)
node _state_req_needs_wb_r_T_37 = mux(_state_req_needs_wb_r_T_35, UInt<3>(0h5), _state_req_needs_wb_r_T_33)
node _state_req_needs_wb_r_T_38 = mux(_state_req_needs_wb_r_T_35, UInt<2>(0h0), _state_req_needs_wb_r_T_34)
node _state_req_needs_wb_r_T_39 = eq(_state_req_needs_wb_r_T_13, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_40 = mux(_state_req_needs_wb_r_T_39, UInt<1>(0h0), _state_req_needs_wb_r_T_36)
node _state_req_needs_wb_r_T_41 = mux(_state_req_needs_wb_r_T_39, UInt<3>(0h4), _state_req_needs_wb_r_T_37)
node _state_req_needs_wb_r_T_42 = mux(_state_req_needs_wb_r_T_39, UInt<2>(0h1), _state_req_needs_wb_r_T_38)
node _state_req_needs_wb_r_T_43 = eq(_state_req_needs_wb_r_T_12, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_44 = mux(_state_req_needs_wb_r_T_43, UInt<1>(0h0), _state_req_needs_wb_r_T_40)
node _state_req_needs_wb_r_T_45 = mux(_state_req_needs_wb_r_T_43, UInt<3>(0h0), _state_req_needs_wb_r_T_41)
node _state_req_needs_wb_r_T_46 = mux(_state_req_needs_wb_r_T_43, UInt<2>(0h1), _state_req_needs_wb_r_T_42)
node _state_req_needs_wb_r_T_47 = eq(_state_req_needs_wb_r_T_11, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_48 = mux(_state_req_needs_wb_r_T_47, UInt<1>(0h1), _state_req_needs_wb_r_T_44)
node _state_req_needs_wb_r_T_49 = mux(_state_req_needs_wb_r_T_47, UInt<3>(0h0), _state_req_needs_wb_r_T_45)
node _state_req_needs_wb_r_T_50 = mux(_state_req_needs_wb_r_T_47, UInt<2>(0h1), _state_req_needs_wb_r_T_46)
node _state_req_needs_wb_r_T_51 = eq(_state_req_needs_wb_r_T_10, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_52 = mux(_state_req_needs_wb_r_T_51, UInt<1>(0h0), _state_req_needs_wb_r_T_48)
node _state_req_needs_wb_r_T_53 = mux(_state_req_needs_wb_r_T_51, UInt<3>(0h5), _state_req_needs_wb_r_T_49)
node _state_req_needs_wb_r_T_54 = mux(_state_req_needs_wb_r_T_51, UInt<2>(0h0), _state_req_needs_wb_r_T_50)
node _state_req_needs_wb_r_T_55 = eq(_state_req_needs_wb_r_T_9, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_56 = mux(_state_req_needs_wb_r_T_55, UInt<1>(0h0), _state_req_needs_wb_r_T_52)
node _state_req_needs_wb_r_T_57 = mux(_state_req_needs_wb_r_T_55, UInt<3>(0h4), _state_req_needs_wb_r_T_53)
node _state_req_needs_wb_r_T_58 = mux(_state_req_needs_wb_r_T_55, UInt<2>(0h1), _state_req_needs_wb_r_T_54)
node _state_req_needs_wb_r_T_59 = eq(_state_req_needs_wb_r_T_8, _state_req_needs_wb_r_T_6)
node _state_req_needs_wb_r_T_60 = mux(_state_req_needs_wb_r_T_59, UInt<1>(0h0), _state_req_needs_wb_r_T_56)
node _state_req_needs_wb_r_T_61 = mux(_state_req_needs_wb_r_T_59, UInt<3>(0h3), _state_req_needs_wb_r_T_57)
node _state_req_needs_wb_r_T_62 = mux(_state_req_needs_wb_r_T_59, UInt<2>(0h2), _state_req_needs_wb_r_T_58)
node _state_req_needs_wb_r_T_63 = eq(_state_req_needs_wb_r_T_7, _state_req_needs_wb_r_T_6)
node state_req_needs_wb_r_1 = mux(_state_req_needs_wb_r_T_63, UInt<1>(0h1), _state_req_needs_wb_r_T_60)
node state_req_needs_wb_r_2 = mux(_state_req_needs_wb_r_T_63, UInt<3>(0h3), _state_req_needs_wb_r_T_61)
node state_req_needs_wb_r_3 = mux(_state_req_needs_wb_r_T_63, UInt<2>(0h2), _state_req_needs_wb_r_T_62)
wire state_req_needs_wb_meta : { state : UInt<2>}
connect state_req_needs_wb_meta.state, state_req_needs_wb_r_3
connect req_needs_wb, state_req_needs_wb_r_1
when io.req.tag_match :
node _state_r_c_cat_T = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_r_c_cat_T_1 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_r_c_cat_T_2 = or(_state_r_c_cat_T, _state_r_c_cat_T_1)
node _state_r_c_cat_T_3 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_r_c_cat_T_4 = or(_state_r_c_cat_T_2, _state_r_c_cat_T_3)
node _state_r_c_cat_T_5 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_r_c_cat_T_6 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_r_c_cat_T_7 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_r_c_cat_T_8 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_r_c_cat_T_9 = or(_state_r_c_cat_T_5, _state_r_c_cat_T_6)
node _state_r_c_cat_T_10 = or(_state_r_c_cat_T_9, _state_r_c_cat_T_7)
node _state_r_c_cat_T_11 = or(_state_r_c_cat_T_10, _state_r_c_cat_T_8)
node _state_r_c_cat_T_12 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_r_c_cat_T_13 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_r_c_cat_T_14 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_r_c_cat_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_r_c_cat_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_r_c_cat_T_17 = or(_state_r_c_cat_T_12, _state_r_c_cat_T_13)
node _state_r_c_cat_T_18 = or(_state_r_c_cat_T_17, _state_r_c_cat_T_14)
node _state_r_c_cat_T_19 = or(_state_r_c_cat_T_18, _state_r_c_cat_T_15)
node _state_r_c_cat_T_20 = or(_state_r_c_cat_T_19, _state_r_c_cat_T_16)
node _state_r_c_cat_T_21 = or(_state_r_c_cat_T_11, _state_r_c_cat_T_20)
node _state_r_c_cat_T_22 = or(_state_r_c_cat_T_4, _state_r_c_cat_T_21)
node _state_r_c_cat_T_23 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_r_c_cat_T_24 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_r_c_cat_T_25 = or(_state_r_c_cat_T_23, _state_r_c_cat_T_24)
node _state_r_c_cat_T_26 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_r_c_cat_T_27 = or(_state_r_c_cat_T_25, _state_r_c_cat_T_26)
node _state_r_c_cat_T_28 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_r_c_cat_T_29 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_r_c_cat_T_30 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_r_c_cat_T_31 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_r_c_cat_T_32 = or(_state_r_c_cat_T_28, _state_r_c_cat_T_29)
node _state_r_c_cat_T_33 = or(_state_r_c_cat_T_32, _state_r_c_cat_T_30)
node _state_r_c_cat_T_34 = or(_state_r_c_cat_T_33, _state_r_c_cat_T_31)
node _state_r_c_cat_T_35 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_r_c_cat_T_36 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_r_c_cat_T_37 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_r_c_cat_T_38 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_r_c_cat_T_39 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_r_c_cat_T_40 = or(_state_r_c_cat_T_35, _state_r_c_cat_T_36)
node _state_r_c_cat_T_41 = or(_state_r_c_cat_T_40, _state_r_c_cat_T_37)
node _state_r_c_cat_T_42 = or(_state_r_c_cat_T_41, _state_r_c_cat_T_38)
node _state_r_c_cat_T_43 = or(_state_r_c_cat_T_42, _state_r_c_cat_T_39)
node _state_r_c_cat_T_44 = or(_state_r_c_cat_T_34, _state_r_c_cat_T_43)
node _state_r_c_cat_T_45 = or(_state_r_c_cat_T_27, _state_r_c_cat_T_44)
node _state_r_c_cat_T_46 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _state_r_c_cat_T_47 = or(_state_r_c_cat_T_45, _state_r_c_cat_T_46)
node _state_r_c_cat_T_48 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _state_r_c_cat_T_49 = or(_state_r_c_cat_T_47, _state_r_c_cat_T_48)
node state_r_c = cat(_state_r_c_cat_T_22, _state_r_c_cat_T_49)
node _state_r_T = cat(state_r_c, io.req.old_meta.coh.state)
node _state_r_T_1 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_2 = cat(_state_r_T_1, UInt<2>(0h3))
node _state_r_T_3 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_4 = cat(_state_r_T_3, UInt<2>(0h2))
node _state_r_T_5 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_6 = cat(_state_r_T_5, UInt<2>(0h1))
node _state_r_T_7 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_8 = cat(_state_r_T_7, UInt<2>(0h3))
node _state_r_T_9 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_10 = cat(_state_r_T_9, UInt<2>(0h2))
node _state_r_T_11 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_12 = cat(_state_r_T_11, UInt<2>(0h3))
node _state_r_T_13 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_14 = cat(_state_r_T_13, UInt<2>(0h2))
node _state_r_T_15 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_16 = cat(_state_r_T_15, UInt<2>(0h0))
node _state_r_T_17 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_18 = cat(_state_r_T_17, UInt<2>(0h1))
node _state_r_T_19 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_20 = cat(_state_r_T_19, UInt<2>(0h0))
node _state_r_T_21 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_22 = cat(_state_r_T_21, UInt<2>(0h1))
node _state_r_T_23 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_24 = cat(_state_r_T_23, UInt<2>(0h0))
node _state_r_T_25 = eq(_state_r_T_24, _state_r_T)
node _state_r_T_26 = mux(_state_r_T_25, UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_27 = mux(_state_r_T_25, UInt<2>(0h1), UInt<1>(0h0))
node _state_r_T_28 = eq(_state_r_T_22, _state_r_T)
node _state_r_T_29 = mux(_state_r_T_28, UInt<1>(0h0), _state_r_T_26)
node _state_r_T_30 = mux(_state_r_T_28, UInt<2>(0h2), _state_r_T_27)
node _state_r_T_31 = eq(_state_r_T_20, _state_r_T)
node _state_r_T_32 = mux(_state_r_T_31, UInt<1>(0h0), _state_r_T_29)
node _state_r_T_33 = mux(_state_r_T_31, UInt<2>(0h1), _state_r_T_30)
node _state_r_T_34 = eq(_state_r_T_18, _state_r_T)
node _state_r_T_35 = mux(_state_r_T_34, UInt<1>(0h0), _state_r_T_32)
node _state_r_T_36 = mux(_state_r_T_34, UInt<2>(0h2), _state_r_T_33)
node _state_r_T_37 = eq(_state_r_T_16, _state_r_T)
node _state_r_T_38 = mux(_state_r_T_37, UInt<1>(0h0), _state_r_T_35)
node _state_r_T_39 = mux(_state_r_T_37, UInt<2>(0h0), _state_r_T_36)
node _state_r_T_40 = eq(_state_r_T_14, _state_r_T)
node _state_r_T_41 = mux(_state_r_T_40, UInt<1>(0h1), _state_r_T_38)
node _state_r_T_42 = mux(_state_r_T_40, UInt<2>(0h3), _state_r_T_39)
node _state_r_T_43 = eq(_state_r_T_12, _state_r_T)
node _state_r_T_44 = mux(_state_r_T_43, UInt<1>(0h1), _state_r_T_41)
node _state_r_T_45 = mux(_state_r_T_43, UInt<2>(0h3), _state_r_T_42)
node _state_r_T_46 = eq(_state_r_T_10, _state_r_T)
node _state_r_T_47 = mux(_state_r_T_46, UInt<1>(0h1), _state_r_T_44)
node _state_r_T_48 = mux(_state_r_T_46, UInt<2>(0h2), _state_r_T_45)
node _state_r_T_49 = eq(_state_r_T_8, _state_r_T)
node _state_r_T_50 = mux(_state_r_T_49, UInt<1>(0h1), _state_r_T_47)
node _state_r_T_51 = mux(_state_r_T_49, UInt<2>(0h3), _state_r_T_48)
node _state_r_T_52 = eq(_state_r_T_6, _state_r_T)
node _state_r_T_53 = mux(_state_r_T_52, UInt<1>(0h1), _state_r_T_50)
node _state_r_T_54 = mux(_state_r_T_52, UInt<2>(0h1), _state_r_T_51)
node _state_r_T_55 = eq(_state_r_T_4, _state_r_T)
node _state_r_T_56 = mux(_state_r_T_55, UInt<1>(0h1), _state_r_T_53)
node _state_r_T_57 = mux(_state_r_T_55, UInt<2>(0h2), _state_r_T_54)
node _state_r_T_58 = eq(_state_r_T_2, _state_r_T)
node state_is_hit = mux(_state_r_T_58, UInt<1>(0h1), _state_r_T_56)
node state_r_2 = mux(_state_r_T_58, UInt<2>(0h3), _state_r_T_57)
wire state_coh_on_hit : { state : UInt<2>}
connect state_coh_on_hit.state, state_r_2
when state_is_hit :
node _state_T_3 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_T_4 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_T_5 = or(_state_T_3, _state_T_4)
node _state_T_6 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_T_7 = or(_state_T_5, _state_T_6)
node _state_T_8 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_T_9 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_T_10 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_T_11 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_T_12 = or(_state_T_8, _state_T_9)
node _state_T_13 = or(_state_T_12, _state_T_10)
node _state_T_14 = or(_state_T_13, _state_T_11)
node _state_T_15 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_T_16 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_T_17 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_T_18 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_T_19 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_T_20 = or(_state_T_15, _state_T_16)
node _state_T_21 = or(_state_T_20, _state_T_17)
node _state_T_22 = or(_state_T_21, _state_T_18)
node _state_T_23 = or(_state_T_22, _state_T_19)
node _state_T_24 = or(_state_T_14, _state_T_23)
node _state_T_25 = or(_state_T_7, _state_T_24)
node _state_T_26 = asUInt(reset)
node _state_T_27 = eq(_state_T_26, UInt<1>(0h0))
when _state_T_27 :
node _state_T_28 = eq(_state_T_25, UInt<1>(0h0))
when _state_T_28 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:201 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_1
assert(clock, _state_T_25, UInt<1>(0h1), "") : state_assert_1
connect new_coh, state_coh_on_hit
connect state_new_state, UInt<5>(0hc)
else :
connect new_coh, io.req.old_meta.coh
connect state_new_state, UInt<5>(0h1)
else :
wire state_new_coh_meta : { state : UInt<2>}
connect state_new_coh_meta.state, UInt<2>(0h0)
connect new_coh, state_new_coh_meta
connect state_new_state, UInt<5>(0h1)
connect state, state_new_state
else :
node _T_13 = eq(state, UInt<5>(0h1))
when _T_13 :
connect io.mem_acquire.valid, UInt<1>(0h1)
node _io_mem_acquire_bits_T = cat(req_tag, req_idx)
node _io_mem_acquire_bits_T_1 = shl(_io_mem_acquire_bits_T, 6)
node _io_mem_acquire_bits_legal_T = or(UInt<1>(0h0), UInt<1>(0h0))
node _io_mem_acquire_bits_legal_T_1 = xor(_io_mem_acquire_bits_T_1, UInt<1>(0h0))
node _io_mem_acquire_bits_legal_T_2 = cvt(_io_mem_acquire_bits_legal_T_1)
node _io_mem_acquire_bits_legal_T_3 = and(_io_mem_acquire_bits_legal_T_2, asSInt(UInt<33>(0h80000000)))
node _io_mem_acquire_bits_legal_T_4 = asSInt(_io_mem_acquire_bits_legal_T_3)
node _io_mem_acquire_bits_legal_T_5 = eq(_io_mem_acquire_bits_legal_T_4, asSInt(UInt<1>(0h0)))
node _io_mem_acquire_bits_legal_T_6 = and(_io_mem_acquire_bits_legal_T, _io_mem_acquire_bits_legal_T_5)
node _io_mem_acquire_bits_legal_T_7 = eq(UInt<3>(0h6), UInt<3>(0h6))
node _io_mem_acquire_bits_legal_T_8 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_7)
node _io_mem_acquire_bits_legal_T_9 = xor(_io_mem_acquire_bits_T_1, UInt<32>(0h80000000))
node _io_mem_acquire_bits_legal_T_10 = cvt(_io_mem_acquire_bits_legal_T_9)
node _io_mem_acquire_bits_legal_T_11 = and(_io_mem_acquire_bits_legal_T_10, asSInt(UInt<33>(0h80000000)))
node _io_mem_acquire_bits_legal_T_12 = asSInt(_io_mem_acquire_bits_legal_T_11)
node _io_mem_acquire_bits_legal_T_13 = eq(_io_mem_acquire_bits_legal_T_12, asSInt(UInt<1>(0h0)))
node _io_mem_acquire_bits_legal_T_14 = and(_io_mem_acquire_bits_legal_T_8, _io_mem_acquire_bits_legal_T_13)
node _io_mem_acquire_bits_legal_T_15 = or(UInt<1>(0h0), _io_mem_acquire_bits_legal_T_6)
node io_mem_acquire_bits_legal = or(_io_mem_acquire_bits_legal_T_15, _io_mem_acquire_bits_legal_T_14)
wire io_mem_acquire_bits_a : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}
connect io_mem_acquire_bits_a.opcode, UInt<3>(0h6)
connect io_mem_acquire_bits_a.param, grow_param
connect io_mem_acquire_bits_a.size, UInt<3>(0h6)
connect io_mem_acquire_bits_a.source, io.id
connect io_mem_acquire_bits_a.address, _io_mem_acquire_bits_T_1
node _io_mem_acquire_bits_a_mask_sizeOH_T = or(UInt<3>(0h6), UInt<3>(0h0))
node io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = bits(_io_mem_acquire_bits_a_mask_sizeOH_T, 1, 0)
node _io_mem_acquire_bits_a_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sizeOH_shiftAmount)
node _io_mem_acquire_bits_a_mask_sizeOH_T_2 = bits(_io_mem_acquire_bits_a_mask_sizeOH_T_1, 2, 0)
node io_mem_acquire_bits_a_mask_sizeOH = or(_io_mem_acquire_bits_a_mask_sizeOH_T_2, UInt<1>(0h1))
node io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = geq(UInt<3>(0h6), UInt<2>(0h3))
node io_mem_acquire_bits_a_mask_sub_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 2, 2)
node io_mem_acquire_bits_a_mask_sub_sub_bit = bits(_io_mem_acquire_bits_T_1, 2, 2)
node io_mem_acquire_bits_a_mask_sub_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_sub_bit, UInt<1>(0h0))
node io_mem_acquire_bits_a_mask_sub_sub_0_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_0_2)
node io_mem_acquire_bits_a_mask_sub_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T)
node io_mem_acquire_bits_a_mask_sub_sub_1_2 = and(UInt<1>(0h1), io_mem_acquire_bits_a_mask_sub_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_sub_size, io_mem_acquire_bits_a_mask_sub_sub_1_2)
node io_mem_acquire_bits_a_mask_sub_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1)
node io_mem_acquire_bits_a_mask_sub_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 1, 1)
node io_mem_acquire_bits_a_mask_sub_bit = bits(_io_mem_acquire_bits_T_1, 1, 1)
node io_mem_acquire_bits_a_mask_sub_nbit = eq(io_mem_acquire_bits_a_mask_sub_bit, UInt<1>(0h0))
node io_mem_acquire_bits_a_mask_sub_0_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_acc_T = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_0_2)
node io_mem_acquire_bits_a_mask_sub_0_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T)
node io_mem_acquire_bits_a_mask_sub_1_2 = and(io_mem_acquire_bits_a_mask_sub_sub_0_2, io_mem_acquire_bits_a_mask_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_1 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_1_2)
node io_mem_acquire_bits_a_mask_sub_1_1 = or(io_mem_acquire_bits_a_mask_sub_sub_0_1, _io_mem_acquire_bits_a_mask_sub_acc_T_1)
node io_mem_acquire_bits_a_mask_sub_2_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_nbit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_2 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_2_2)
node io_mem_acquire_bits_a_mask_sub_2_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_2)
node io_mem_acquire_bits_a_mask_sub_3_2 = and(io_mem_acquire_bits_a_mask_sub_sub_1_2, io_mem_acquire_bits_a_mask_sub_bit)
node _io_mem_acquire_bits_a_mask_sub_acc_T_3 = and(io_mem_acquire_bits_a_mask_sub_size, io_mem_acquire_bits_a_mask_sub_3_2)
node io_mem_acquire_bits_a_mask_sub_3_1 = or(io_mem_acquire_bits_a_mask_sub_sub_1_1, _io_mem_acquire_bits_a_mask_sub_acc_T_3)
node io_mem_acquire_bits_a_mask_size = bits(io_mem_acquire_bits_a_mask_sizeOH, 0, 0)
node io_mem_acquire_bits_a_mask_bit = bits(_io_mem_acquire_bits_T_1, 0, 0)
node io_mem_acquire_bits_a_mask_nbit = eq(io_mem_acquire_bits_a_mask_bit, UInt<1>(0h0))
node io_mem_acquire_bits_a_mask_eq = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq)
node io_mem_acquire_bits_a_mask_acc = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T)
node io_mem_acquire_bits_a_mask_eq_1 = and(io_mem_acquire_bits_a_mask_sub_0_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_1 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_1)
node io_mem_acquire_bits_a_mask_acc_1 = or(io_mem_acquire_bits_a_mask_sub_0_1, _io_mem_acquire_bits_a_mask_acc_T_1)
node io_mem_acquire_bits_a_mask_eq_2 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_2 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_2)
node io_mem_acquire_bits_a_mask_acc_2 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_2)
node io_mem_acquire_bits_a_mask_eq_3 = and(io_mem_acquire_bits_a_mask_sub_1_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_3 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_3)
node io_mem_acquire_bits_a_mask_acc_3 = or(io_mem_acquire_bits_a_mask_sub_1_1, _io_mem_acquire_bits_a_mask_acc_T_3)
node io_mem_acquire_bits_a_mask_eq_4 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_4 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_4)
node io_mem_acquire_bits_a_mask_acc_4 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_4)
node io_mem_acquire_bits_a_mask_eq_5 = and(io_mem_acquire_bits_a_mask_sub_2_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_5 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_5)
node io_mem_acquire_bits_a_mask_acc_5 = or(io_mem_acquire_bits_a_mask_sub_2_1, _io_mem_acquire_bits_a_mask_acc_T_5)
node io_mem_acquire_bits_a_mask_eq_6 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_nbit)
node _io_mem_acquire_bits_a_mask_acc_T_6 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_6)
node io_mem_acquire_bits_a_mask_acc_6 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_6)
node io_mem_acquire_bits_a_mask_eq_7 = and(io_mem_acquire_bits_a_mask_sub_3_2, io_mem_acquire_bits_a_mask_bit)
node _io_mem_acquire_bits_a_mask_acc_T_7 = and(io_mem_acquire_bits_a_mask_size, io_mem_acquire_bits_a_mask_eq_7)
node io_mem_acquire_bits_a_mask_acc_7 = or(io_mem_acquire_bits_a_mask_sub_3_1, _io_mem_acquire_bits_a_mask_acc_T_7)
node io_mem_acquire_bits_a_mask_lo_lo = cat(io_mem_acquire_bits_a_mask_acc_1, io_mem_acquire_bits_a_mask_acc)
node io_mem_acquire_bits_a_mask_lo_hi = cat(io_mem_acquire_bits_a_mask_acc_3, io_mem_acquire_bits_a_mask_acc_2)
node io_mem_acquire_bits_a_mask_lo = cat(io_mem_acquire_bits_a_mask_lo_hi, io_mem_acquire_bits_a_mask_lo_lo)
node io_mem_acquire_bits_a_mask_hi_lo = cat(io_mem_acquire_bits_a_mask_acc_5, io_mem_acquire_bits_a_mask_acc_4)
node io_mem_acquire_bits_a_mask_hi_hi = cat(io_mem_acquire_bits_a_mask_acc_7, io_mem_acquire_bits_a_mask_acc_6)
node io_mem_acquire_bits_a_mask_hi = cat(io_mem_acquire_bits_a_mask_hi_hi, io_mem_acquire_bits_a_mask_hi_lo)
node _io_mem_acquire_bits_a_mask_T = cat(io_mem_acquire_bits_a_mask_hi, io_mem_acquire_bits_a_mask_lo)
connect io_mem_acquire_bits_a.mask, _io_mem_acquire_bits_a_mask_T
invalidate io_mem_acquire_bits_a.data
connect io_mem_acquire_bits_a.corrupt, UInt<1>(0h0)
connect io.mem_acquire.bits, io_mem_acquire_bits_a
node _T_14 = and(io.mem_acquire.ready, io.mem_acquire.valid)
when _T_14 :
connect state, UInt<5>(0h2)
else :
node _T_15 = eq(state, UInt<5>(0h2))
when _T_15 :
node opdata = bits(io.mem_grant.bits.opcode, 0, 0)
when opdata :
connect io.mem_grant.ready, io.lb_write.ready
connect io.lb_write.valid, io.mem_grant.valid
connect io.lb_write.bits.id, io.id
node _io_lb_write_bits_offset_T = shr(refill_address_inc, 3)
connect io.lb_write.bits.offset, _io_lb_write_bits_offset_T
connect io.lb_write.bits.data, io.mem_grant.bits.data
else :
connect io.mem_grant.ready, UInt<1>(0h1)
node _T_16 = and(io.mem_grant.ready, io.mem_grant.valid)
when _T_16 :
node grant_had_data_opdata = bits(io.mem_grant.bits.opcode, 0, 0)
connect grant_had_data, grant_had_data_opdata
when refill_done :
node _grantack_valid_T = bits(io.mem_grant.bits.opcode, 2, 2)
node _grantack_valid_T_1 = bits(io.mem_grant.bits.opcode, 1, 1)
node _grantack_valid_T_2 = eq(_grantack_valid_T_1, UInt<1>(0h0))
node _grantack_valid_T_3 = and(_grantack_valid_T, _grantack_valid_T_2)
connect grantack.valid, _grantack_valid_T_3
wire grantack_bits_e : { sink : UInt<3>}
connect grantack_bits_e.sink, io.mem_grant.bits.sink
connect grantack.bits, grantack_bits_e
node _state_T_29 = mux(grant_had_data, UInt<5>(0h3), UInt<5>(0hc))
connect state, _state_T_29
node _T_17 = eq(grant_had_data, UInt<1>(0h0))
node _T_18 = and(_T_17, req_needs_wb)
node _T_19 = eq(_T_18, UInt<1>(0h0))
node _T_20 = asUInt(reset)
node _T_21 = eq(_T_20, UInt<1>(0h0))
when _T_21 :
node _T_22 = eq(_T_19, UInt<1>(0h0))
when _T_22 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:251 assert(!(!grant_had_data && req_needs_wb))\n") : printf_1
assert(clock, _T_19, UInt<1>(0h1), "") : assert_1
connect commit_line, UInt<1>(0h0)
connect new_coh, coh_on_grant
else :
node _T_23 = eq(state, UInt<5>(0h3))
when _T_23 :
node _drain_load_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h0))
node _drain_load_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h10))
node _drain_load_T_2 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6))
node _drain_load_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _drain_load_T_4 = or(_drain_load_T, _drain_load_T_1)
node _drain_load_T_5 = or(_drain_load_T_4, _drain_load_T_2)
node _drain_load_T_6 = or(_drain_load_T_5, _drain_load_T_3)
node _drain_load_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _drain_load_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _drain_load_T_9 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _drain_load_T_10 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _drain_load_T_11 = or(_drain_load_T_7, _drain_load_T_8)
node _drain_load_T_12 = or(_drain_load_T_11, _drain_load_T_9)
node _drain_load_T_13 = or(_drain_load_T_12, _drain_load_T_10)
node _drain_load_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _drain_load_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _drain_load_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _drain_load_T_17 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _drain_load_T_18 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _drain_load_T_19 = or(_drain_load_T_14, _drain_load_T_15)
node _drain_load_T_20 = or(_drain_load_T_19, _drain_load_T_16)
node _drain_load_T_21 = or(_drain_load_T_20, _drain_load_T_17)
node _drain_load_T_22 = or(_drain_load_T_21, _drain_load_T_18)
node _drain_load_T_23 = or(_drain_load_T_13, _drain_load_T_22)
node _drain_load_T_24 = or(_drain_load_T_6, _drain_load_T_23)
node _drain_load_T_25 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1))
node _drain_load_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11))
node _drain_load_T_27 = or(_drain_load_T_25, _drain_load_T_26)
node _drain_load_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _drain_load_T_29 = or(_drain_load_T_27, _drain_load_T_28)
node _drain_load_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _drain_load_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _drain_load_T_32 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _drain_load_T_33 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _drain_load_T_34 = or(_drain_load_T_30, _drain_load_T_31)
node _drain_load_T_35 = or(_drain_load_T_34, _drain_load_T_32)
node _drain_load_T_36 = or(_drain_load_T_35, _drain_load_T_33)
node _drain_load_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _drain_load_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _drain_load_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _drain_load_T_40 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _drain_load_T_41 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _drain_load_T_42 = or(_drain_load_T_37, _drain_load_T_38)
node _drain_load_T_43 = or(_drain_load_T_42, _drain_load_T_39)
node _drain_load_T_44 = or(_drain_load_T_43, _drain_load_T_40)
node _drain_load_T_45 = or(_drain_load_T_44, _drain_load_T_41)
node _drain_load_T_46 = or(_drain_load_T_36, _drain_load_T_45)
node _drain_load_T_47 = or(_drain_load_T_29, _drain_load_T_46)
node _drain_load_T_48 = eq(_drain_load_T_47, UInt<1>(0h0))
node _drain_load_T_49 = and(_drain_load_T_24, _drain_load_T_48)
node _drain_load_T_50 = neq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6))
node drain_load = and(_drain_load_T_49, _drain_load_T_50)
node _rp_addr_T = bits(rpq.io.deq.bits.addr, 5, 0)
node rp_addr_hi = cat(req_tag, req_idx)
node rp_addr = cat(rp_addr_hi, _rp_addr_T)
node _data_word_T = cat(UInt<1>(0h0), UInt<6>(0h0))
node data_word = dshr(io.lb_resp, _data_word_T)
node _T_24 = bits(rpq.io.deq.bits.addr, 5, 0)
node hi = cat(req_tag, req_idx)
node _T_25 = cat(hi, _T_24)
wire size : UInt<2>
connect size, rpq.io.deq.bits.uop.mem_size
node _rpq_io_deq_ready_T = and(io.resp.ready, io.lb_read.ready)
node _rpq_io_deq_ready_T_1 = and(_rpq_io_deq_ready_T, drain_load)
connect rpq.io.deq.ready, _rpq_io_deq_ready_T_1
node _io_lb_read_valid_T = and(rpq.io.deq.valid, drain_load)
connect io.lb_read.valid, _io_lb_read_valid_T
connect io.lb_read.bits.id, io.id
node _io_lb_read_bits_offset_T = shr(rpq.io.deq.bits.addr, 3)
connect io.lb_read.bits.offset, _io_lb_read_bits_offset_T
node _io_resp_valid_T = and(io.lb_read.ready, io.lb_read.valid)
node _io_resp_valid_T_1 = and(rpq.io.deq.valid, _io_resp_valid_T)
node _io_resp_valid_T_2 = and(_io_resp_valid_T_1, drain_load)
connect io.resp.valid, _io_resp_valid_T_2
connect io.resp.bits.uop, rpq.io.deq.bits.uop
node _io_resp_bits_data_shifted_T = bits(_T_25, 2, 2)
node _io_resp_bits_data_shifted_T_1 = bits(data_word, 63, 32)
node _io_resp_bits_data_shifted_T_2 = bits(data_word, 31, 0)
node io_resp_bits_data_shifted = mux(_io_resp_bits_data_shifted_T, _io_resp_bits_data_shifted_T_1, _io_resp_bits_data_shifted_T_2)
node io_resp_bits_data_doZero = and(UInt<1>(0h0), UInt<1>(0h0))
node io_resp_bits_data_zeroed = mux(io_resp_bits_data_doZero, UInt<1>(0h0), io_resp_bits_data_shifted)
node _io_resp_bits_data_T = eq(size, UInt<2>(0h2))
node _io_resp_bits_data_T_1 = or(_io_resp_bits_data_T, io_resp_bits_data_doZero)
node _io_resp_bits_data_T_2 = bits(io_resp_bits_data_zeroed, 31, 31)
node _io_resp_bits_data_T_3 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_2)
node _io_resp_bits_data_T_4 = mux(_io_resp_bits_data_T_3, UInt<32>(0hffffffff), UInt<32>(0h0))
node _io_resp_bits_data_T_5 = bits(data_word, 63, 32)
node _io_resp_bits_data_T_6 = mux(_io_resp_bits_data_T_1, _io_resp_bits_data_T_4, _io_resp_bits_data_T_5)
node _io_resp_bits_data_T_7 = cat(_io_resp_bits_data_T_6, io_resp_bits_data_zeroed)
node _io_resp_bits_data_shifted_T_3 = bits(_T_25, 1, 1)
node _io_resp_bits_data_shifted_T_4 = bits(_io_resp_bits_data_T_7, 31, 16)
node _io_resp_bits_data_shifted_T_5 = bits(_io_resp_bits_data_T_7, 15, 0)
node io_resp_bits_data_shifted_1 = mux(_io_resp_bits_data_shifted_T_3, _io_resp_bits_data_shifted_T_4, _io_resp_bits_data_shifted_T_5)
node io_resp_bits_data_doZero_1 = and(UInt<1>(0h0), UInt<1>(0h0))
node io_resp_bits_data_zeroed_1 = mux(io_resp_bits_data_doZero_1, UInt<1>(0h0), io_resp_bits_data_shifted_1)
node _io_resp_bits_data_T_8 = eq(size, UInt<1>(0h1))
node _io_resp_bits_data_T_9 = or(_io_resp_bits_data_T_8, io_resp_bits_data_doZero_1)
node _io_resp_bits_data_T_10 = bits(io_resp_bits_data_zeroed_1, 15, 15)
node _io_resp_bits_data_T_11 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_10)
node _io_resp_bits_data_T_12 = mux(_io_resp_bits_data_T_11, UInt<48>(0hffffffffffff), UInt<48>(0h0))
node _io_resp_bits_data_T_13 = bits(_io_resp_bits_data_T_7, 63, 16)
node _io_resp_bits_data_T_14 = mux(_io_resp_bits_data_T_9, _io_resp_bits_data_T_12, _io_resp_bits_data_T_13)
node _io_resp_bits_data_T_15 = cat(_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1)
node _io_resp_bits_data_shifted_T_6 = bits(_T_25, 0, 0)
node _io_resp_bits_data_shifted_T_7 = bits(_io_resp_bits_data_T_15, 15, 8)
node _io_resp_bits_data_shifted_T_8 = bits(_io_resp_bits_data_T_15, 7, 0)
node io_resp_bits_data_shifted_2 = mux(_io_resp_bits_data_shifted_T_6, _io_resp_bits_data_shifted_T_7, _io_resp_bits_data_shifted_T_8)
node io_resp_bits_data_doZero_2 = and(UInt<1>(0h1), UInt<1>(0h0))
node io_resp_bits_data_zeroed_2 = mux(io_resp_bits_data_doZero_2, UInt<1>(0h0), io_resp_bits_data_shifted_2)
node _io_resp_bits_data_T_16 = eq(size, UInt<1>(0h0))
node _io_resp_bits_data_T_17 = or(_io_resp_bits_data_T_16, io_resp_bits_data_doZero_2)
node _io_resp_bits_data_T_18 = bits(io_resp_bits_data_zeroed_2, 7, 7)
node _io_resp_bits_data_T_19 = and(rpq.io.deq.bits.uop.mem_signed, _io_resp_bits_data_T_18)
node _io_resp_bits_data_T_20 = mux(_io_resp_bits_data_T_19, UInt<56>(0hffffffffffffff), UInt<56>(0h0))
node _io_resp_bits_data_T_21 = bits(_io_resp_bits_data_T_15, 63, 8)
node _io_resp_bits_data_T_22 = mux(_io_resp_bits_data_T_17, _io_resp_bits_data_T_20, _io_resp_bits_data_T_21)
node _io_resp_bits_data_T_23 = cat(_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2)
connect io.resp.bits.data, _io_resp_bits_data_T_23
connect io.resp.bits.is_hella, rpq.io.deq.bits.is_hella
node _T_26 = and(rpq.io.deq.ready, rpq.io.deq.valid)
when _T_26 :
connect commit_line, UInt<1>(0h1)
else :
node _T_27 = eq(commit_line, UInt<1>(0h0))
node _T_28 = and(rpq.io.empty, _T_27)
when _T_28 :
node _T_29 = and(rpq.io.enq.ready, rpq.io.enq.valid)
node _T_30 = eq(_T_29, UInt<1>(0h0))
when _T_30 :
connect state, UInt<5>(0he)
connect finish_to_prefetch, UInt<1>(0h0)
else :
node _T_31 = eq(drain_load, UInt<1>(0h0))
node _T_32 = and(rpq.io.deq.valid, _T_31)
node _T_33 = or(rpq.io.empty, _T_32)
when _T_33 :
connect io.commit_val, UInt<1>(0h1)
connect state, UInt<5>(0h4)
else :
node _T_34 = eq(state, UInt<5>(0h4))
when _T_34 :
node _io_meta_read_valid_T = eq(io.prober_state.valid, UInt<1>(0h0))
node _io_meta_read_valid_T_1 = eq(grantack.valid, UInt<1>(0h0))
node _io_meta_read_valid_T_2 = or(_io_meta_read_valid_T, _io_meta_read_valid_T_1)
node _io_meta_read_valid_T_3 = bits(io.prober_state.bits, 9, 6)
node _io_meta_read_valid_T_4 = neq(_io_meta_read_valid_T_3, req_idx)
node _io_meta_read_valid_T_5 = or(_io_meta_read_valid_T_2, _io_meta_read_valid_T_4)
connect io.meta_read.valid, _io_meta_read_valid_T_5
connect io.meta_read.bits.idx, req_idx
connect io.meta_read.bits.tag, req_tag
connect io.meta_read.bits.way_en, req.way_en
node _T_35 = and(io.meta_read.ready, io.meta_read.valid)
when _T_35 :
connect state, UInt<5>(0h5)
else :
node _T_36 = eq(state, UInt<5>(0h5))
when _T_36 :
connect state, UInt<5>(0h6)
else :
node _T_37 = eq(state, UInt<5>(0h6))
when _T_37 :
node _needs_wb_r_T = eq(UInt<5>(0h10), UInt<5>(0h10))
node _needs_wb_r_T_1 = mux(_needs_wb_r_T, UInt<2>(0h2), UInt<2>(0h2))
node _needs_wb_r_T_2 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _needs_wb_r_T_3 = mux(_needs_wb_r_T_2, UInt<2>(0h1), _needs_wb_r_T_1)
node _needs_wb_r_T_4 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _needs_wb_r_T_5 = mux(_needs_wb_r_T_4, UInt<2>(0h0), _needs_wb_r_T_3)
node _needs_wb_r_T_6 = cat(_needs_wb_r_T_5, io.meta_resp.bits.coh.state)
node _needs_wb_r_T_7 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _needs_wb_r_T_8 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _needs_wb_r_T_9 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _needs_wb_r_T_10 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _needs_wb_r_T_11 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _needs_wb_r_T_12 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _needs_wb_r_T_13 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _needs_wb_r_T_14 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _needs_wb_r_T_15 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _needs_wb_r_T_16 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _needs_wb_r_T_17 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _needs_wb_r_T_18 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _needs_wb_r_T_19 = eq(_needs_wb_r_T_18, _needs_wb_r_T_6)
node _needs_wb_r_T_20 = mux(_needs_wb_r_T_19, UInt<1>(0h0), UInt<1>(0h0))
node _needs_wb_r_T_21 = mux(_needs_wb_r_T_19, UInt<3>(0h5), UInt<1>(0h0))
node _needs_wb_r_T_22 = mux(_needs_wb_r_T_19, UInt<2>(0h0), UInt<1>(0h0))
node _needs_wb_r_T_23 = eq(_needs_wb_r_T_17, _needs_wb_r_T_6)
node _needs_wb_r_T_24 = mux(_needs_wb_r_T_23, UInt<1>(0h0), _needs_wb_r_T_20)
node _needs_wb_r_T_25 = mux(_needs_wb_r_T_23, UInt<3>(0h2), _needs_wb_r_T_21)
node _needs_wb_r_T_26 = mux(_needs_wb_r_T_23, UInt<2>(0h0), _needs_wb_r_T_22)
node _needs_wb_r_T_27 = eq(_needs_wb_r_T_16, _needs_wb_r_T_6)
node _needs_wb_r_T_28 = mux(_needs_wb_r_T_27, UInt<1>(0h0), _needs_wb_r_T_24)
node _needs_wb_r_T_29 = mux(_needs_wb_r_T_27, UInt<3>(0h1), _needs_wb_r_T_25)
node _needs_wb_r_T_30 = mux(_needs_wb_r_T_27, UInt<2>(0h0), _needs_wb_r_T_26)
node _needs_wb_r_T_31 = eq(_needs_wb_r_T_15, _needs_wb_r_T_6)
node _needs_wb_r_T_32 = mux(_needs_wb_r_T_31, UInt<1>(0h1), _needs_wb_r_T_28)
node _needs_wb_r_T_33 = mux(_needs_wb_r_T_31, UInt<3>(0h1), _needs_wb_r_T_29)
node _needs_wb_r_T_34 = mux(_needs_wb_r_T_31, UInt<2>(0h0), _needs_wb_r_T_30)
node _needs_wb_r_T_35 = eq(_needs_wb_r_T_14, _needs_wb_r_T_6)
node _needs_wb_r_T_36 = mux(_needs_wb_r_T_35, UInt<1>(0h0), _needs_wb_r_T_32)
node _needs_wb_r_T_37 = mux(_needs_wb_r_T_35, UInt<3>(0h5), _needs_wb_r_T_33)
node _needs_wb_r_T_38 = mux(_needs_wb_r_T_35, UInt<2>(0h0), _needs_wb_r_T_34)
node _needs_wb_r_T_39 = eq(_needs_wb_r_T_13, _needs_wb_r_T_6)
node _needs_wb_r_T_40 = mux(_needs_wb_r_T_39, UInt<1>(0h0), _needs_wb_r_T_36)
node _needs_wb_r_T_41 = mux(_needs_wb_r_T_39, UInt<3>(0h4), _needs_wb_r_T_37)
node _needs_wb_r_T_42 = mux(_needs_wb_r_T_39, UInt<2>(0h1), _needs_wb_r_T_38)
node _needs_wb_r_T_43 = eq(_needs_wb_r_T_12, _needs_wb_r_T_6)
node _needs_wb_r_T_44 = mux(_needs_wb_r_T_43, UInt<1>(0h0), _needs_wb_r_T_40)
node _needs_wb_r_T_45 = mux(_needs_wb_r_T_43, UInt<3>(0h0), _needs_wb_r_T_41)
node _needs_wb_r_T_46 = mux(_needs_wb_r_T_43, UInt<2>(0h1), _needs_wb_r_T_42)
node _needs_wb_r_T_47 = eq(_needs_wb_r_T_11, _needs_wb_r_T_6)
node _needs_wb_r_T_48 = mux(_needs_wb_r_T_47, UInt<1>(0h1), _needs_wb_r_T_44)
node _needs_wb_r_T_49 = mux(_needs_wb_r_T_47, UInt<3>(0h0), _needs_wb_r_T_45)
node _needs_wb_r_T_50 = mux(_needs_wb_r_T_47, UInt<2>(0h1), _needs_wb_r_T_46)
node _needs_wb_r_T_51 = eq(_needs_wb_r_T_10, _needs_wb_r_T_6)
node _needs_wb_r_T_52 = mux(_needs_wb_r_T_51, UInt<1>(0h0), _needs_wb_r_T_48)
node _needs_wb_r_T_53 = mux(_needs_wb_r_T_51, UInt<3>(0h5), _needs_wb_r_T_49)
node _needs_wb_r_T_54 = mux(_needs_wb_r_T_51, UInt<2>(0h0), _needs_wb_r_T_50)
node _needs_wb_r_T_55 = eq(_needs_wb_r_T_9, _needs_wb_r_T_6)
node _needs_wb_r_T_56 = mux(_needs_wb_r_T_55, UInt<1>(0h0), _needs_wb_r_T_52)
node _needs_wb_r_T_57 = mux(_needs_wb_r_T_55, UInt<3>(0h4), _needs_wb_r_T_53)
node _needs_wb_r_T_58 = mux(_needs_wb_r_T_55, UInt<2>(0h1), _needs_wb_r_T_54)
node _needs_wb_r_T_59 = eq(_needs_wb_r_T_8, _needs_wb_r_T_6)
node _needs_wb_r_T_60 = mux(_needs_wb_r_T_59, UInt<1>(0h0), _needs_wb_r_T_56)
node _needs_wb_r_T_61 = mux(_needs_wb_r_T_59, UInt<3>(0h3), _needs_wb_r_T_57)
node _needs_wb_r_T_62 = mux(_needs_wb_r_T_59, UInt<2>(0h2), _needs_wb_r_T_58)
node _needs_wb_r_T_63 = eq(_needs_wb_r_T_7, _needs_wb_r_T_6)
node needs_wb = mux(_needs_wb_r_T_63, UInt<1>(0h1), _needs_wb_r_T_60)
node needs_wb_r_2 = mux(_needs_wb_r_T_63, UInt<3>(0h3), _needs_wb_r_T_61)
node needs_wb_r_3 = mux(_needs_wb_r_T_63, UInt<2>(0h2), _needs_wb_r_T_62)
wire needs_wb_meta : { state : UInt<2>}
connect needs_wb_meta.state, needs_wb_r_3
node _state_T_30 = eq(io.meta_resp.valid, UInt<1>(0h0))
node _state_T_31 = mux(needs_wb, UInt<5>(0h7), UInt<5>(0hb))
node _state_T_32 = mux(_state_T_30, UInt<5>(0h4), _state_T_31)
connect state, _state_T_32
else :
node _T_38 = eq(state, UInt<5>(0h7))
when _T_38 :
connect io.meta_write.valid, UInt<1>(0h1)
connect io.meta_write.bits.idx, req_idx
connect io.meta_write.bits.data.coh, coh_on_clear
connect io.meta_write.bits.data.tag, req_tag
connect io.meta_write.bits.way_en, req.way_en
node _T_39 = and(io.meta_write.ready, io.meta_write.valid)
when _T_39 :
connect state, UInt<5>(0h9)
else :
node _T_40 = eq(state, UInt<5>(0h9))
when _T_40 :
connect io.wb_req.valid, UInt<1>(0h1)
connect io.wb_req.bits.tag, req.old_meta.tag
connect io.wb_req.bits.idx, req_idx
connect io.wb_req.bits.param, shrink_param
connect io.wb_req.bits.way_en, req.way_en
connect io.wb_req.bits.source, io.id
connect io.wb_req.bits.voluntary, UInt<1>(0h1)
node _T_41 = and(io.wb_req.ready, io.wb_req.valid)
when _T_41 :
connect state, UInt<5>(0ha)
else :
node _T_42 = eq(state, UInt<5>(0ha))
when _T_42 :
when io.wb_resp :
connect state, UInt<5>(0hb)
else :
node _T_43 = eq(state, UInt<5>(0hb))
when _T_43 :
connect io.lb_read.valid, UInt<1>(0h1)
connect io.lb_read.bits.id, io.id
connect io.lb_read.bits.offset, refill_ctr
node _io_refill_valid_T = and(io.lb_read.ready, io.lb_read.valid)
connect io.refill.valid, _io_refill_valid_T
node _io_refill_bits_addr_T = shl(refill_ctr, 3)
node _io_refill_bits_addr_T_1 = or(req_block_addr, _io_refill_bits_addr_T)
connect io.refill.bits.addr, _io_refill_bits_addr_T_1
connect io.refill.bits.way_en, req.way_en
node _io_refill_bits_wmask_T = not(UInt<1>(0h0))
connect io.refill.bits.wmask, _io_refill_bits_wmask_T
connect io.refill.bits.data, io.lb_resp
node _T_44 = and(io.refill.ready, io.refill.valid)
when _T_44 :
node _refill_ctr_T = add(refill_ctr, UInt<1>(0h1))
node _refill_ctr_T_1 = tail(_refill_ctr_T, 1)
connect refill_ctr, _refill_ctr_T_1
node _T_45 = eq(refill_ctr, UInt<3>(0h7))
when _T_45 :
connect state, UInt<5>(0hc)
else :
node _T_46 = eq(state, UInt<5>(0hc))
when _T_46 :
connect io.replay.bits, rpq.io.deq.bits
connect io.replay.valid, rpq.io.deq.valid
connect rpq.io.deq.ready, io.replay.ready
connect io.replay.bits.way_en, req.way_en
node _io_replay_bits_addr_T = bits(rpq.io.deq.bits.addr, 5, 0)
node io_replay_bits_addr_hi = cat(req_tag, req_idx)
node _io_replay_bits_addr_T_1 = cat(io_replay_bits_addr_hi, _io_replay_bits_addr_T)
connect io.replay.bits.addr, _io_replay_bits_addr_T_1
node _T_47 = and(io.replay.ready, io.replay.valid)
node _T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1))
node _T_49 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11))
node _T_50 = or(_T_48, _T_49)
node _T_51 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _T_52 = or(_T_50, _T_51)
node _T_53 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _T_54 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _T_55 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _T_56 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _T_57 = or(_T_53, _T_54)
node _T_58 = or(_T_57, _T_55)
node _T_59 = or(_T_58, _T_56)
node _T_60 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _T_61 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _T_62 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _T_63 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _T_64 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _T_65 = or(_T_60, _T_61)
node _T_66 = or(_T_65, _T_62)
node _T_67 = or(_T_66, _T_63)
node _T_68 = or(_T_67, _T_64)
node _T_69 = or(_T_59, _T_68)
node _T_70 = or(_T_52, _T_69)
node _T_71 = and(_T_47, _T_70)
when _T_71 :
node _r_c_cat_T = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1))
node _r_c_cat_T_1 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11))
node _r_c_cat_T_2 = or(_r_c_cat_T, _r_c_cat_T_1)
node _r_c_cat_T_3 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _r_c_cat_T_4 = or(_r_c_cat_T_2, _r_c_cat_T_3)
node _r_c_cat_T_5 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _r_c_cat_T_6 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _r_c_cat_T_7 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _r_c_cat_T_8 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _r_c_cat_T_9 = or(_r_c_cat_T_5, _r_c_cat_T_6)
node _r_c_cat_T_10 = or(_r_c_cat_T_9, _r_c_cat_T_7)
node _r_c_cat_T_11 = or(_r_c_cat_T_10, _r_c_cat_T_8)
node _r_c_cat_T_12 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _r_c_cat_T_13 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _r_c_cat_T_14 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _r_c_cat_T_15 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _r_c_cat_T_16 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _r_c_cat_T_17 = or(_r_c_cat_T_12, _r_c_cat_T_13)
node _r_c_cat_T_18 = or(_r_c_cat_T_17, _r_c_cat_T_14)
node _r_c_cat_T_19 = or(_r_c_cat_T_18, _r_c_cat_T_15)
node _r_c_cat_T_20 = or(_r_c_cat_T_19, _r_c_cat_T_16)
node _r_c_cat_T_21 = or(_r_c_cat_T_11, _r_c_cat_T_20)
node _r_c_cat_T_22 = or(_r_c_cat_T_4, _r_c_cat_T_21)
node _r_c_cat_T_23 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<1>(0h1))
node _r_c_cat_T_24 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<5>(0h11))
node _r_c_cat_T_25 = or(_r_c_cat_T_23, _r_c_cat_T_24)
node _r_c_cat_T_26 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h7))
node _r_c_cat_T_27 = or(_r_c_cat_T_25, _r_c_cat_T_26)
node _r_c_cat_T_28 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h4))
node _r_c_cat_T_29 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h9))
node _r_c_cat_T_30 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0ha))
node _r_c_cat_T_31 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hb))
node _r_c_cat_T_32 = or(_r_c_cat_T_28, _r_c_cat_T_29)
node _r_c_cat_T_33 = or(_r_c_cat_T_32, _r_c_cat_T_30)
node _r_c_cat_T_34 = or(_r_c_cat_T_33, _r_c_cat_T_31)
node _r_c_cat_T_35 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0h8))
node _r_c_cat_T_36 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hc))
node _r_c_cat_T_37 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hd))
node _r_c_cat_T_38 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0he))
node _r_c_cat_T_39 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<4>(0hf))
node _r_c_cat_T_40 = or(_r_c_cat_T_35, _r_c_cat_T_36)
node _r_c_cat_T_41 = or(_r_c_cat_T_40, _r_c_cat_T_37)
node _r_c_cat_T_42 = or(_r_c_cat_T_41, _r_c_cat_T_38)
node _r_c_cat_T_43 = or(_r_c_cat_T_42, _r_c_cat_T_39)
node _r_c_cat_T_44 = or(_r_c_cat_T_34, _r_c_cat_T_43)
node _r_c_cat_T_45 = or(_r_c_cat_T_27, _r_c_cat_T_44)
node _r_c_cat_T_46 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<2>(0h3))
node _r_c_cat_T_47 = or(_r_c_cat_T_45, _r_c_cat_T_46)
node _r_c_cat_T_48 = eq(rpq.io.deq.bits.uop.mem_cmd, UInt<3>(0h6))
node _r_c_cat_T_49 = or(_r_c_cat_T_47, _r_c_cat_T_48)
node r_c = cat(_r_c_cat_T_22, _r_c_cat_T_49)
node _r_T_64 = cat(r_c, new_coh.state)
node _r_T_65 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_66 = cat(_r_T_65, UInt<2>(0h3))
node _r_T_67 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_68 = cat(_r_T_67, UInt<2>(0h2))
node _r_T_69 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_70 = cat(_r_T_69, UInt<2>(0h1))
node _r_T_71 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_72 = cat(_r_T_71, UInt<2>(0h3))
node _r_T_73 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_74 = cat(_r_T_73, UInt<2>(0h2))
node _r_T_75 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_76 = cat(_r_T_75, UInt<2>(0h3))
node _r_T_77 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_78 = cat(_r_T_77, UInt<2>(0h2))
node _r_T_79 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_80 = cat(_r_T_79, UInt<2>(0h0))
node _r_T_81 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_82 = cat(_r_T_81, UInt<2>(0h1))
node _r_T_83 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_84 = cat(_r_T_83, UInt<2>(0h0))
node _r_T_85 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_86 = cat(_r_T_85, UInt<2>(0h1))
node _r_T_87 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_88 = cat(_r_T_87, UInt<2>(0h0))
node _r_T_89 = eq(_r_T_88, _r_T_64)
node _r_T_90 = mux(_r_T_89, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_91 = mux(_r_T_89, UInt<2>(0h1), UInt<1>(0h0))
node _r_T_92 = eq(_r_T_86, _r_T_64)
node _r_T_93 = mux(_r_T_92, UInt<1>(0h0), _r_T_90)
node _r_T_94 = mux(_r_T_92, UInt<2>(0h2), _r_T_91)
node _r_T_95 = eq(_r_T_84, _r_T_64)
node _r_T_96 = mux(_r_T_95, UInt<1>(0h0), _r_T_93)
node _r_T_97 = mux(_r_T_95, UInt<2>(0h1), _r_T_94)
node _r_T_98 = eq(_r_T_82, _r_T_64)
node _r_T_99 = mux(_r_T_98, UInt<1>(0h0), _r_T_96)
node _r_T_100 = mux(_r_T_98, UInt<2>(0h2), _r_T_97)
node _r_T_101 = eq(_r_T_80, _r_T_64)
node _r_T_102 = mux(_r_T_101, UInt<1>(0h0), _r_T_99)
node _r_T_103 = mux(_r_T_101, UInt<2>(0h0), _r_T_100)
node _r_T_104 = eq(_r_T_78, _r_T_64)
node _r_T_105 = mux(_r_T_104, UInt<1>(0h1), _r_T_102)
node _r_T_106 = mux(_r_T_104, UInt<2>(0h3), _r_T_103)
node _r_T_107 = eq(_r_T_76, _r_T_64)
node _r_T_108 = mux(_r_T_107, UInt<1>(0h1), _r_T_105)
node _r_T_109 = mux(_r_T_107, UInt<2>(0h3), _r_T_106)
node _r_T_110 = eq(_r_T_74, _r_T_64)
node _r_T_111 = mux(_r_T_110, UInt<1>(0h1), _r_T_108)
node _r_T_112 = mux(_r_T_110, UInt<2>(0h2), _r_T_109)
node _r_T_113 = eq(_r_T_72, _r_T_64)
node _r_T_114 = mux(_r_T_113, UInt<1>(0h1), _r_T_111)
node _r_T_115 = mux(_r_T_113, UInt<2>(0h3), _r_T_112)
node _r_T_116 = eq(_r_T_70, _r_T_64)
node _r_T_117 = mux(_r_T_116, UInt<1>(0h1), _r_T_114)
node _r_T_118 = mux(_r_T_116, UInt<2>(0h1), _r_T_115)
node _r_T_119 = eq(_r_T_68, _r_T_64)
node _r_T_120 = mux(_r_T_119, UInt<1>(0h1), _r_T_117)
node _r_T_121 = mux(_r_T_119, UInt<2>(0h2), _r_T_118)
node _r_T_122 = eq(_r_T_66, _r_T_64)
node is_hit = mux(_r_T_122, UInt<1>(0h1), _r_T_120)
node r_2_1 = mux(_r_T_122, UInt<2>(0h3), _r_T_121)
wire coh_on_hit : { state : UInt<2>}
connect coh_on_hit.state, r_2_1
node _T_72 = asUInt(reset)
node _T_73 = eq(_T_72, UInt<1>(0h0))
when _T_73 :
node _T_74 = eq(is_hit, UInt<1>(0h0))
when _T_74 :
printf(clock, UInt<1>(0h1), "Assertion failed: We still don't have permissions for this store\n at mshrs.scala:357 assert(is_hit, \"We still don't have permissions for this store\")\n") : printf_2
assert(clock, is_hit, UInt<1>(0h1), "") : assert_2
connect new_coh, coh_on_hit
node _T_75 = eq(rpq.io.enq.valid, UInt<1>(0h0))
node _T_76 = and(rpq.io.empty, _T_75)
when _T_76 :
connect state, UInt<5>(0hd)
else :
node _T_77 = eq(state, UInt<5>(0hd))
when _T_77 :
connect io.meta_write.valid, UInt<1>(0h1)
connect io.meta_write.bits.idx, req_idx
connect io.meta_write.bits.data.coh, new_coh
connect io.meta_write.bits.data.tag, req_tag
connect io.meta_write.bits.way_en, req.way_en
node _T_78 = and(io.meta_write.ready, io.meta_write.valid)
when _T_78 :
connect state, UInt<5>(0he)
connect finish_to_prefetch, UInt<1>(0h0)
else :
node _T_79 = eq(state, UInt<5>(0he))
when _T_79 :
connect io.mem_finish.valid, grantack.valid
connect io.mem_finish.bits, grantack.bits
node _T_80 = and(io.mem_finish.ready, io.mem_finish.valid)
node _T_81 = eq(grantack.valid, UInt<1>(0h0))
node _T_82 = or(_T_80, _T_81)
when _T_82 :
connect grantack.valid, UInt<1>(0h0)
connect state, UInt<5>(0hf)
else :
node _T_83 = eq(state, UInt<5>(0hf))
when _T_83 :
node _state_T_33 = mux(finish_to_prefetch, UInt<5>(0h11), UInt<5>(0h0))
connect state, _state_T_33
else :
node _T_84 = eq(state, UInt<5>(0h11))
when _T_84 :
connect io.req_pri_rdy, UInt<1>(0h1)
node _T_85 = eq(io.req_sec_rdy, UInt<1>(0h0))
node _T_86 = and(io.req_sec_val, _T_85)
node _T_87 = or(_T_86, io.clear_prefetch)
when _T_87 :
connect state, UInt<5>(0h0)
else :
node _T_88 = and(io.req_sec_val, io.req_sec_rdy)
when _T_88 :
node _r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _r_c_cat_T_52 = or(_r_c_cat_T_50, _r_c_cat_T_51)
node _r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _r_c_cat_T_54 = or(_r_c_cat_T_52, _r_c_cat_T_53)
node _r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _r_c_cat_T_59 = or(_r_c_cat_T_55, _r_c_cat_T_56)
node _r_c_cat_T_60 = or(_r_c_cat_T_59, _r_c_cat_T_57)
node _r_c_cat_T_61 = or(_r_c_cat_T_60, _r_c_cat_T_58)
node _r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _r_c_cat_T_67 = or(_r_c_cat_T_62, _r_c_cat_T_63)
node _r_c_cat_T_68 = or(_r_c_cat_T_67, _r_c_cat_T_64)
node _r_c_cat_T_69 = or(_r_c_cat_T_68, _r_c_cat_T_65)
node _r_c_cat_T_70 = or(_r_c_cat_T_69, _r_c_cat_T_66)
node _r_c_cat_T_71 = or(_r_c_cat_T_61, _r_c_cat_T_70)
node _r_c_cat_T_72 = or(_r_c_cat_T_54, _r_c_cat_T_71)
node _r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _r_c_cat_T_75 = or(_r_c_cat_T_73, _r_c_cat_T_74)
node _r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _r_c_cat_T_77 = or(_r_c_cat_T_75, _r_c_cat_T_76)
node _r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _r_c_cat_T_82 = or(_r_c_cat_T_78, _r_c_cat_T_79)
node _r_c_cat_T_83 = or(_r_c_cat_T_82, _r_c_cat_T_80)
node _r_c_cat_T_84 = or(_r_c_cat_T_83, _r_c_cat_T_81)
node _r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _r_c_cat_T_90 = or(_r_c_cat_T_85, _r_c_cat_T_86)
node _r_c_cat_T_91 = or(_r_c_cat_T_90, _r_c_cat_T_87)
node _r_c_cat_T_92 = or(_r_c_cat_T_91, _r_c_cat_T_88)
node _r_c_cat_T_93 = or(_r_c_cat_T_92, _r_c_cat_T_89)
node _r_c_cat_T_94 = or(_r_c_cat_T_84, _r_c_cat_T_93)
node _r_c_cat_T_95 = or(_r_c_cat_T_77, _r_c_cat_T_94)
node _r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _r_c_cat_T_97 = or(_r_c_cat_T_95, _r_c_cat_T_96)
node _r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _r_c_cat_T_99 = or(_r_c_cat_T_97, _r_c_cat_T_98)
node r_c_1 = cat(_r_c_cat_T_72, _r_c_cat_T_99)
node _r_T_123 = cat(r_c_1, new_coh.state)
node _r_T_124 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_125 = cat(_r_T_124, UInt<2>(0h3))
node _r_T_126 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_127 = cat(_r_T_126, UInt<2>(0h2))
node _r_T_128 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_129 = cat(_r_T_128, UInt<2>(0h1))
node _r_T_130 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_131 = cat(_r_T_130, UInt<2>(0h3))
node _r_T_132 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_133 = cat(_r_T_132, UInt<2>(0h2))
node _r_T_134 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_135 = cat(_r_T_134, UInt<2>(0h3))
node _r_T_136 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_137 = cat(_r_T_136, UInt<2>(0h2))
node _r_T_138 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _r_T_139 = cat(_r_T_138, UInt<2>(0h0))
node _r_T_140 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_141 = cat(_r_T_140, UInt<2>(0h1))
node _r_T_142 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _r_T_143 = cat(_r_T_142, UInt<2>(0h0))
node _r_T_144 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_145 = cat(_r_T_144, UInt<2>(0h1))
node _r_T_146 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _r_T_147 = cat(_r_T_146, UInt<2>(0h0))
node _r_T_148 = eq(_r_T_147, _r_T_123)
node _r_T_149 = mux(_r_T_148, UInt<1>(0h0), UInt<1>(0h0))
node _r_T_150 = mux(_r_T_148, UInt<2>(0h1), UInt<1>(0h0))
node _r_T_151 = eq(_r_T_145, _r_T_123)
node _r_T_152 = mux(_r_T_151, UInt<1>(0h0), _r_T_149)
node _r_T_153 = mux(_r_T_151, UInt<2>(0h2), _r_T_150)
node _r_T_154 = eq(_r_T_143, _r_T_123)
node _r_T_155 = mux(_r_T_154, UInt<1>(0h0), _r_T_152)
node _r_T_156 = mux(_r_T_154, UInt<2>(0h1), _r_T_153)
node _r_T_157 = eq(_r_T_141, _r_T_123)
node _r_T_158 = mux(_r_T_157, UInt<1>(0h0), _r_T_155)
node _r_T_159 = mux(_r_T_157, UInt<2>(0h2), _r_T_156)
node _r_T_160 = eq(_r_T_139, _r_T_123)
node _r_T_161 = mux(_r_T_160, UInt<1>(0h0), _r_T_158)
node _r_T_162 = mux(_r_T_160, UInt<2>(0h0), _r_T_159)
node _r_T_163 = eq(_r_T_137, _r_T_123)
node _r_T_164 = mux(_r_T_163, UInt<1>(0h1), _r_T_161)
node _r_T_165 = mux(_r_T_163, UInt<2>(0h3), _r_T_162)
node _r_T_166 = eq(_r_T_135, _r_T_123)
node _r_T_167 = mux(_r_T_166, UInt<1>(0h1), _r_T_164)
node _r_T_168 = mux(_r_T_166, UInt<2>(0h3), _r_T_165)
node _r_T_169 = eq(_r_T_133, _r_T_123)
node _r_T_170 = mux(_r_T_169, UInt<1>(0h1), _r_T_167)
node _r_T_171 = mux(_r_T_169, UInt<2>(0h2), _r_T_168)
node _r_T_172 = eq(_r_T_131, _r_T_123)
node _r_T_173 = mux(_r_T_172, UInt<1>(0h1), _r_T_170)
node _r_T_174 = mux(_r_T_172, UInt<2>(0h3), _r_T_171)
node _r_T_175 = eq(_r_T_129, _r_T_123)
node _r_T_176 = mux(_r_T_175, UInt<1>(0h1), _r_T_173)
node _r_T_177 = mux(_r_T_175, UInt<2>(0h1), _r_T_174)
node _r_T_178 = eq(_r_T_127, _r_T_123)
node _r_T_179 = mux(_r_T_178, UInt<1>(0h1), _r_T_176)
node _r_T_180 = mux(_r_T_178, UInt<2>(0h2), _r_T_177)
node _r_T_181 = eq(_r_T_125, _r_T_123)
node is_hit_1 = mux(_r_T_181, UInt<1>(0h1), _r_T_179)
node r_2_2 = mux(_r_T_181, UInt<2>(0h3), _r_T_180)
wire coh_on_hit_1 : { state : UInt<2>}
connect coh_on_hit_1.state, r_2_2
when is_hit_1 :
connect new_coh, coh_on_hit_1
connect state, UInt<5>(0h4)
else :
wire new_coh_meta_1 : { state : UInt<2>}
connect new_coh_meta_1.state, UInt<2>(0h0)
connect new_coh, new_coh_meta_1
connect state, UInt<5>(0h1)
else :
node _T_89 = and(io.req_pri_val, io.req_pri_rdy)
when _T_89 :
connect grant_had_data, UInt<1>(0h0)
wire state_new_state_1 : UInt
connect state_new_state_1, state
connect grantack.valid, UInt<1>(0h0)
connect refill_ctr, UInt<1>(0h0)
node _state_T_34 = asUInt(reset)
node _state_T_35 = eq(_state_T_34, UInt<1>(0h0))
when _state_T_35 :
node _state_T_36 = eq(rpq.io.enq.ready, UInt<1>(0h0))
when _state_T_36 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:194 assert(rpq.io.enq.ready)\n") : state_printf_2
assert(clock, rpq.io.enq.ready, UInt<1>(0h1), "") : state_assert_2
connect req, io.req
node _state_req_needs_wb_r_T_64 = eq(UInt<5>(0h10), UInt<5>(0h10))
node _state_req_needs_wb_r_T_65 = mux(_state_req_needs_wb_r_T_64, UInt<2>(0h2), UInt<2>(0h2))
node _state_req_needs_wb_r_T_66 = eq(UInt<5>(0h12), UInt<5>(0h10))
node _state_req_needs_wb_r_T_67 = mux(_state_req_needs_wb_r_T_66, UInt<2>(0h1), _state_req_needs_wb_r_T_65)
node _state_req_needs_wb_r_T_68 = eq(UInt<5>(0h13), UInt<5>(0h10))
node _state_req_needs_wb_r_T_69 = mux(_state_req_needs_wb_r_T_68, UInt<2>(0h0), _state_req_needs_wb_r_T_67)
node _state_req_needs_wb_r_T_70 = cat(_state_req_needs_wb_r_T_69, io.req.old_meta.coh.state)
node _state_req_needs_wb_r_T_71 = cat(UInt<2>(0h0), UInt<2>(0h3))
node _state_req_needs_wb_r_T_72 = cat(UInt<2>(0h0), UInt<2>(0h2))
node _state_req_needs_wb_r_T_73 = cat(UInt<2>(0h0), UInt<2>(0h1))
node _state_req_needs_wb_r_T_74 = cat(UInt<2>(0h0), UInt<2>(0h0))
node _state_req_needs_wb_r_T_75 = cat(UInt<2>(0h1), UInt<2>(0h3))
node _state_req_needs_wb_r_T_76 = cat(UInt<2>(0h1), UInt<2>(0h2))
node _state_req_needs_wb_r_T_77 = cat(UInt<2>(0h1), UInt<2>(0h1))
node _state_req_needs_wb_r_T_78 = cat(UInt<2>(0h1), UInt<2>(0h0))
node _state_req_needs_wb_r_T_79 = cat(UInt<2>(0h2), UInt<2>(0h3))
node _state_req_needs_wb_r_T_80 = cat(UInt<2>(0h2), UInt<2>(0h2))
node _state_req_needs_wb_r_T_81 = cat(UInt<2>(0h2), UInt<2>(0h1))
node _state_req_needs_wb_r_T_82 = cat(UInt<2>(0h2), UInt<2>(0h0))
node _state_req_needs_wb_r_T_83 = eq(_state_req_needs_wb_r_T_82, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_84 = mux(_state_req_needs_wb_r_T_83, UInt<1>(0h0), UInt<1>(0h0))
node _state_req_needs_wb_r_T_85 = mux(_state_req_needs_wb_r_T_83, UInt<3>(0h5), UInt<1>(0h0))
node _state_req_needs_wb_r_T_86 = mux(_state_req_needs_wb_r_T_83, UInt<2>(0h0), UInt<1>(0h0))
node _state_req_needs_wb_r_T_87 = eq(_state_req_needs_wb_r_T_81, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_88 = mux(_state_req_needs_wb_r_T_87, UInt<1>(0h0), _state_req_needs_wb_r_T_84)
node _state_req_needs_wb_r_T_89 = mux(_state_req_needs_wb_r_T_87, UInt<3>(0h2), _state_req_needs_wb_r_T_85)
node _state_req_needs_wb_r_T_90 = mux(_state_req_needs_wb_r_T_87, UInt<2>(0h0), _state_req_needs_wb_r_T_86)
node _state_req_needs_wb_r_T_91 = eq(_state_req_needs_wb_r_T_80, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_92 = mux(_state_req_needs_wb_r_T_91, UInt<1>(0h0), _state_req_needs_wb_r_T_88)
node _state_req_needs_wb_r_T_93 = mux(_state_req_needs_wb_r_T_91, UInt<3>(0h1), _state_req_needs_wb_r_T_89)
node _state_req_needs_wb_r_T_94 = mux(_state_req_needs_wb_r_T_91, UInt<2>(0h0), _state_req_needs_wb_r_T_90)
node _state_req_needs_wb_r_T_95 = eq(_state_req_needs_wb_r_T_79, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_96 = mux(_state_req_needs_wb_r_T_95, UInt<1>(0h1), _state_req_needs_wb_r_T_92)
node _state_req_needs_wb_r_T_97 = mux(_state_req_needs_wb_r_T_95, UInt<3>(0h1), _state_req_needs_wb_r_T_93)
node _state_req_needs_wb_r_T_98 = mux(_state_req_needs_wb_r_T_95, UInt<2>(0h0), _state_req_needs_wb_r_T_94)
node _state_req_needs_wb_r_T_99 = eq(_state_req_needs_wb_r_T_78, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_100 = mux(_state_req_needs_wb_r_T_99, UInt<1>(0h0), _state_req_needs_wb_r_T_96)
node _state_req_needs_wb_r_T_101 = mux(_state_req_needs_wb_r_T_99, UInt<3>(0h5), _state_req_needs_wb_r_T_97)
node _state_req_needs_wb_r_T_102 = mux(_state_req_needs_wb_r_T_99, UInt<2>(0h0), _state_req_needs_wb_r_T_98)
node _state_req_needs_wb_r_T_103 = eq(_state_req_needs_wb_r_T_77, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_104 = mux(_state_req_needs_wb_r_T_103, UInt<1>(0h0), _state_req_needs_wb_r_T_100)
node _state_req_needs_wb_r_T_105 = mux(_state_req_needs_wb_r_T_103, UInt<3>(0h4), _state_req_needs_wb_r_T_101)
node _state_req_needs_wb_r_T_106 = mux(_state_req_needs_wb_r_T_103, UInt<2>(0h1), _state_req_needs_wb_r_T_102)
node _state_req_needs_wb_r_T_107 = eq(_state_req_needs_wb_r_T_76, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_108 = mux(_state_req_needs_wb_r_T_107, UInt<1>(0h0), _state_req_needs_wb_r_T_104)
node _state_req_needs_wb_r_T_109 = mux(_state_req_needs_wb_r_T_107, UInt<3>(0h0), _state_req_needs_wb_r_T_105)
node _state_req_needs_wb_r_T_110 = mux(_state_req_needs_wb_r_T_107, UInt<2>(0h1), _state_req_needs_wb_r_T_106)
node _state_req_needs_wb_r_T_111 = eq(_state_req_needs_wb_r_T_75, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_112 = mux(_state_req_needs_wb_r_T_111, UInt<1>(0h1), _state_req_needs_wb_r_T_108)
node _state_req_needs_wb_r_T_113 = mux(_state_req_needs_wb_r_T_111, UInt<3>(0h0), _state_req_needs_wb_r_T_109)
node _state_req_needs_wb_r_T_114 = mux(_state_req_needs_wb_r_T_111, UInt<2>(0h1), _state_req_needs_wb_r_T_110)
node _state_req_needs_wb_r_T_115 = eq(_state_req_needs_wb_r_T_74, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_116 = mux(_state_req_needs_wb_r_T_115, UInt<1>(0h0), _state_req_needs_wb_r_T_112)
node _state_req_needs_wb_r_T_117 = mux(_state_req_needs_wb_r_T_115, UInt<3>(0h5), _state_req_needs_wb_r_T_113)
node _state_req_needs_wb_r_T_118 = mux(_state_req_needs_wb_r_T_115, UInt<2>(0h0), _state_req_needs_wb_r_T_114)
node _state_req_needs_wb_r_T_119 = eq(_state_req_needs_wb_r_T_73, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_120 = mux(_state_req_needs_wb_r_T_119, UInt<1>(0h0), _state_req_needs_wb_r_T_116)
node _state_req_needs_wb_r_T_121 = mux(_state_req_needs_wb_r_T_119, UInt<3>(0h4), _state_req_needs_wb_r_T_117)
node _state_req_needs_wb_r_T_122 = mux(_state_req_needs_wb_r_T_119, UInt<2>(0h1), _state_req_needs_wb_r_T_118)
node _state_req_needs_wb_r_T_123 = eq(_state_req_needs_wb_r_T_72, _state_req_needs_wb_r_T_70)
node _state_req_needs_wb_r_T_124 = mux(_state_req_needs_wb_r_T_123, UInt<1>(0h0), _state_req_needs_wb_r_T_120)
node _state_req_needs_wb_r_T_125 = mux(_state_req_needs_wb_r_T_123, UInt<3>(0h3), _state_req_needs_wb_r_T_121)
node _state_req_needs_wb_r_T_126 = mux(_state_req_needs_wb_r_T_123, UInt<2>(0h2), _state_req_needs_wb_r_T_122)
node _state_req_needs_wb_r_T_127 = eq(_state_req_needs_wb_r_T_71, _state_req_needs_wb_r_T_70)
node state_req_needs_wb_r_1_1 = mux(_state_req_needs_wb_r_T_127, UInt<1>(0h1), _state_req_needs_wb_r_T_124)
node state_req_needs_wb_r_2_1 = mux(_state_req_needs_wb_r_T_127, UInt<3>(0h3), _state_req_needs_wb_r_T_125)
node state_req_needs_wb_r_3_1 = mux(_state_req_needs_wb_r_T_127, UInt<2>(0h2), _state_req_needs_wb_r_T_126)
wire state_req_needs_wb_meta_1 : { state : UInt<2>}
connect state_req_needs_wb_meta_1.state, state_req_needs_wb_r_3_1
connect req_needs_wb, state_req_needs_wb_r_1_1
when io.req.tag_match :
node _state_r_c_cat_T_50 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_r_c_cat_T_51 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_r_c_cat_T_52 = or(_state_r_c_cat_T_50, _state_r_c_cat_T_51)
node _state_r_c_cat_T_53 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_r_c_cat_T_54 = or(_state_r_c_cat_T_52, _state_r_c_cat_T_53)
node _state_r_c_cat_T_55 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_r_c_cat_T_56 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_r_c_cat_T_57 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_r_c_cat_T_58 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_r_c_cat_T_59 = or(_state_r_c_cat_T_55, _state_r_c_cat_T_56)
node _state_r_c_cat_T_60 = or(_state_r_c_cat_T_59, _state_r_c_cat_T_57)
node _state_r_c_cat_T_61 = or(_state_r_c_cat_T_60, _state_r_c_cat_T_58)
node _state_r_c_cat_T_62 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_r_c_cat_T_63 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_r_c_cat_T_64 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_r_c_cat_T_65 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_r_c_cat_T_66 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_r_c_cat_T_67 = or(_state_r_c_cat_T_62, _state_r_c_cat_T_63)
node _state_r_c_cat_T_68 = or(_state_r_c_cat_T_67, _state_r_c_cat_T_64)
node _state_r_c_cat_T_69 = or(_state_r_c_cat_T_68, _state_r_c_cat_T_65)
node _state_r_c_cat_T_70 = or(_state_r_c_cat_T_69, _state_r_c_cat_T_66)
node _state_r_c_cat_T_71 = or(_state_r_c_cat_T_61, _state_r_c_cat_T_70)
node _state_r_c_cat_T_72 = or(_state_r_c_cat_T_54, _state_r_c_cat_T_71)
node _state_r_c_cat_T_73 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_r_c_cat_T_74 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_r_c_cat_T_75 = or(_state_r_c_cat_T_73, _state_r_c_cat_T_74)
node _state_r_c_cat_T_76 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_r_c_cat_T_77 = or(_state_r_c_cat_T_75, _state_r_c_cat_T_76)
node _state_r_c_cat_T_78 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_r_c_cat_T_79 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_r_c_cat_T_80 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_r_c_cat_T_81 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_r_c_cat_T_82 = or(_state_r_c_cat_T_78, _state_r_c_cat_T_79)
node _state_r_c_cat_T_83 = or(_state_r_c_cat_T_82, _state_r_c_cat_T_80)
node _state_r_c_cat_T_84 = or(_state_r_c_cat_T_83, _state_r_c_cat_T_81)
node _state_r_c_cat_T_85 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_r_c_cat_T_86 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_r_c_cat_T_87 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_r_c_cat_T_88 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_r_c_cat_T_89 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_r_c_cat_T_90 = or(_state_r_c_cat_T_85, _state_r_c_cat_T_86)
node _state_r_c_cat_T_91 = or(_state_r_c_cat_T_90, _state_r_c_cat_T_87)
node _state_r_c_cat_T_92 = or(_state_r_c_cat_T_91, _state_r_c_cat_T_88)
node _state_r_c_cat_T_93 = or(_state_r_c_cat_T_92, _state_r_c_cat_T_89)
node _state_r_c_cat_T_94 = or(_state_r_c_cat_T_84, _state_r_c_cat_T_93)
node _state_r_c_cat_T_95 = or(_state_r_c_cat_T_77, _state_r_c_cat_T_94)
node _state_r_c_cat_T_96 = eq(io.req.uop.mem_cmd, UInt<2>(0h3))
node _state_r_c_cat_T_97 = or(_state_r_c_cat_T_95, _state_r_c_cat_T_96)
node _state_r_c_cat_T_98 = eq(io.req.uop.mem_cmd, UInt<3>(0h6))
node _state_r_c_cat_T_99 = or(_state_r_c_cat_T_97, _state_r_c_cat_T_98)
node state_r_c_1 = cat(_state_r_c_cat_T_72, _state_r_c_cat_T_99)
node _state_r_T_59 = cat(state_r_c_1, io.req.old_meta.coh.state)
node _state_r_T_60 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_61 = cat(_state_r_T_60, UInt<2>(0h3))
node _state_r_T_62 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_63 = cat(_state_r_T_62, UInt<2>(0h2))
node _state_r_T_64 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_65 = cat(_state_r_T_64, UInt<2>(0h1))
node _state_r_T_66 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_67 = cat(_state_r_T_66, UInt<2>(0h3))
node _state_r_T_68 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_69 = cat(_state_r_T_68, UInt<2>(0h2))
node _state_r_T_70 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_71 = cat(_state_r_T_70, UInt<2>(0h3))
node _state_r_T_72 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_73 = cat(_state_r_T_72, UInt<2>(0h2))
node _state_r_T_74 = cat(UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_75 = cat(_state_r_T_74, UInt<2>(0h0))
node _state_r_T_76 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_77 = cat(_state_r_T_76, UInt<2>(0h1))
node _state_r_T_78 = cat(UInt<1>(0h0), UInt<1>(0h1))
node _state_r_T_79 = cat(_state_r_T_78, UInt<2>(0h0))
node _state_r_T_80 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_81 = cat(_state_r_T_80, UInt<2>(0h1))
node _state_r_T_82 = cat(UInt<1>(0h1), UInt<1>(0h1))
node _state_r_T_83 = cat(_state_r_T_82, UInt<2>(0h0))
node _state_r_T_84 = eq(_state_r_T_83, _state_r_T_59)
node _state_r_T_85 = mux(_state_r_T_84, UInt<1>(0h0), UInt<1>(0h0))
node _state_r_T_86 = mux(_state_r_T_84, UInt<2>(0h1), UInt<1>(0h0))
node _state_r_T_87 = eq(_state_r_T_81, _state_r_T_59)
node _state_r_T_88 = mux(_state_r_T_87, UInt<1>(0h0), _state_r_T_85)
node _state_r_T_89 = mux(_state_r_T_87, UInt<2>(0h2), _state_r_T_86)
node _state_r_T_90 = eq(_state_r_T_79, _state_r_T_59)
node _state_r_T_91 = mux(_state_r_T_90, UInt<1>(0h0), _state_r_T_88)
node _state_r_T_92 = mux(_state_r_T_90, UInt<2>(0h1), _state_r_T_89)
node _state_r_T_93 = eq(_state_r_T_77, _state_r_T_59)
node _state_r_T_94 = mux(_state_r_T_93, UInt<1>(0h0), _state_r_T_91)
node _state_r_T_95 = mux(_state_r_T_93, UInt<2>(0h2), _state_r_T_92)
node _state_r_T_96 = eq(_state_r_T_75, _state_r_T_59)
node _state_r_T_97 = mux(_state_r_T_96, UInt<1>(0h0), _state_r_T_94)
node _state_r_T_98 = mux(_state_r_T_96, UInt<2>(0h0), _state_r_T_95)
node _state_r_T_99 = eq(_state_r_T_73, _state_r_T_59)
node _state_r_T_100 = mux(_state_r_T_99, UInt<1>(0h1), _state_r_T_97)
node _state_r_T_101 = mux(_state_r_T_99, UInt<2>(0h3), _state_r_T_98)
node _state_r_T_102 = eq(_state_r_T_71, _state_r_T_59)
node _state_r_T_103 = mux(_state_r_T_102, UInt<1>(0h1), _state_r_T_100)
node _state_r_T_104 = mux(_state_r_T_102, UInt<2>(0h3), _state_r_T_101)
node _state_r_T_105 = eq(_state_r_T_69, _state_r_T_59)
node _state_r_T_106 = mux(_state_r_T_105, UInt<1>(0h1), _state_r_T_103)
node _state_r_T_107 = mux(_state_r_T_105, UInt<2>(0h2), _state_r_T_104)
node _state_r_T_108 = eq(_state_r_T_67, _state_r_T_59)
node _state_r_T_109 = mux(_state_r_T_108, UInt<1>(0h1), _state_r_T_106)
node _state_r_T_110 = mux(_state_r_T_108, UInt<2>(0h3), _state_r_T_107)
node _state_r_T_111 = eq(_state_r_T_65, _state_r_T_59)
node _state_r_T_112 = mux(_state_r_T_111, UInt<1>(0h1), _state_r_T_109)
node _state_r_T_113 = mux(_state_r_T_111, UInt<2>(0h1), _state_r_T_110)
node _state_r_T_114 = eq(_state_r_T_63, _state_r_T_59)
node _state_r_T_115 = mux(_state_r_T_114, UInt<1>(0h1), _state_r_T_112)
node _state_r_T_116 = mux(_state_r_T_114, UInt<2>(0h2), _state_r_T_113)
node _state_r_T_117 = eq(_state_r_T_61, _state_r_T_59)
node state_is_hit_1 = mux(_state_r_T_117, UInt<1>(0h1), _state_r_T_115)
node state_r_2_1 = mux(_state_r_T_117, UInt<2>(0h3), _state_r_T_116)
wire state_coh_on_hit_1 : { state : UInt<2>}
connect state_coh_on_hit_1.state, state_r_2_1
when state_is_hit_1 :
node _state_T_37 = eq(io.req.uop.mem_cmd, UInt<1>(0h1))
node _state_T_38 = eq(io.req.uop.mem_cmd, UInt<5>(0h11))
node _state_T_39 = or(_state_T_37, _state_T_38)
node _state_T_40 = eq(io.req.uop.mem_cmd, UInt<3>(0h7))
node _state_T_41 = or(_state_T_39, _state_T_40)
node _state_T_42 = eq(io.req.uop.mem_cmd, UInt<3>(0h4))
node _state_T_43 = eq(io.req.uop.mem_cmd, UInt<4>(0h9))
node _state_T_44 = eq(io.req.uop.mem_cmd, UInt<4>(0ha))
node _state_T_45 = eq(io.req.uop.mem_cmd, UInt<4>(0hb))
node _state_T_46 = or(_state_T_42, _state_T_43)
node _state_T_47 = or(_state_T_46, _state_T_44)
node _state_T_48 = or(_state_T_47, _state_T_45)
node _state_T_49 = eq(io.req.uop.mem_cmd, UInt<4>(0h8))
node _state_T_50 = eq(io.req.uop.mem_cmd, UInt<4>(0hc))
node _state_T_51 = eq(io.req.uop.mem_cmd, UInt<4>(0hd))
node _state_T_52 = eq(io.req.uop.mem_cmd, UInt<4>(0he))
node _state_T_53 = eq(io.req.uop.mem_cmd, UInt<4>(0hf))
node _state_T_54 = or(_state_T_49, _state_T_50)
node _state_T_55 = or(_state_T_54, _state_T_51)
node _state_T_56 = or(_state_T_55, _state_T_52)
node _state_T_57 = or(_state_T_56, _state_T_53)
node _state_T_58 = or(_state_T_48, _state_T_57)
node _state_T_59 = or(_state_T_41, _state_T_58)
node _state_T_60 = asUInt(reset)
node _state_T_61 = eq(_state_T_60, UInt<1>(0h0))
when _state_T_61 :
node _state_T_62 = eq(_state_T_59, UInt<1>(0h0))
when _state_T_62 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at mshrs.scala:201 assert(isWrite(io.req.uop.mem_cmd))\n") : state_printf_3
assert(clock, _state_T_59, UInt<1>(0h1), "") : state_assert_3
connect new_coh, state_coh_on_hit_1
connect state_new_state_1, UInt<5>(0hc)
else :
connect new_coh, io.req.old_meta.coh
connect state_new_state_1, UInt<5>(0h1)
else :
wire state_new_coh_meta_1 : { state : UInt<2>}
connect state_new_coh_meta_1.state, UInt<2>(0h0)
connect new_coh, state_new_coh_meta_1
connect state_new_state_1, UInt<5>(0h1)
connect state, state_new_state_1 | module BoomMSHR( // @[mshrs.scala:36:7]
input clock, // @[mshrs.scala:36:7]
input reset, // @[mshrs.scala:36:7]
input io_req_pri_val, // @[mshrs.scala:39:14]
output io_req_pri_rdy, // @[mshrs.scala:39:14]
input io_req_sec_val, // @[mshrs.scala:39:14]
output io_req_sec_rdy, // @[mshrs.scala:39:14]
input io_clear_prefetch, // @[mshrs.scala:39:14]
input [5:0] io_rob_pnr_idx, // @[mshrs.scala:39:14]
input [5:0] io_rob_head_idx, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_uopc, // @[mshrs.scala:39:14]
input [31:0] io_req_uop_inst, // @[mshrs.scala:39:14]
input [31:0] io_req_uop_debug_inst, // @[mshrs.scala:39:14]
input io_req_uop_is_rvc, // @[mshrs.scala:39:14]
input [33:0] io_req_uop_debug_pc, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_iq_type, // @[mshrs.scala:39:14]
input [9:0] io_req_uop_fu_code, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_ctrl_br_type, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_ctrl_op1_sel, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_ctrl_op2_sel, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_ctrl_imm_sel, // @[mshrs.scala:39:14]
input [4:0] io_req_uop_ctrl_op_fcn, // @[mshrs.scala:39:14]
input io_req_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14]
input [2:0] io_req_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14]
input io_req_uop_ctrl_is_load, // @[mshrs.scala:39:14]
input io_req_uop_ctrl_is_sta, // @[mshrs.scala:39:14]
input io_req_uop_ctrl_is_std, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_iw_state, // @[mshrs.scala:39:14]
input io_req_uop_iw_p1_poisoned, // @[mshrs.scala:39:14]
input io_req_uop_iw_p2_poisoned, // @[mshrs.scala:39:14]
input io_req_uop_is_br, // @[mshrs.scala:39:14]
input io_req_uop_is_jalr, // @[mshrs.scala:39:14]
input io_req_uop_is_jal, // @[mshrs.scala:39:14]
input io_req_uop_is_sfb, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_br_mask, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_br_tag, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_ftq_idx, // @[mshrs.scala:39:14]
input io_req_uop_edge_inst, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_pc_lob, // @[mshrs.scala:39:14]
input io_req_uop_taken, // @[mshrs.scala:39:14]
input [19:0] io_req_uop_imm_packed, // @[mshrs.scala:39:14]
input [11:0] io_req_uop_csr_addr, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_rob_idx, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_ldq_idx, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_stq_idx, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_rxq_idx, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_pdst, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_prs1, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_prs2, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_prs3, // @[mshrs.scala:39:14]
input [3:0] io_req_uop_ppred, // @[mshrs.scala:39:14]
input io_req_uop_prs1_busy, // @[mshrs.scala:39:14]
input io_req_uop_prs2_busy, // @[mshrs.scala:39:14]
input io_req_uop_prs3_busy, // @[mshrs.scala:39:14]
input io_req_uop_ppred_busy, // @[mshrs.scala:39:14]
input [6:0] io_req_uop_stale_pdst, // @[mshrs.scala:39:14]
input io_req_uop_exception, // @[mshrs.scala:39:14]
input [63:0] io_req_uop_exc_cause, // @[mshrs.scala:39:14]
input io_req_uop_bypassable, // @[mshrs.scala:39:14]
input [4:0] io_req_uop_mem_cmd, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_mem_size, // @[mshrs.scala:39:14]
input io_req_uop_mem_signed, // @[mshrs.scala:39:14]
input io_req_uop_is_fence, // @[mshrs.scala:39:14]
input io_req_uop_is_fencei, // @[mshrs.scala:39:14]
input io_req_uop_is_amo, // @[mshrs.scala:39:14]
input io_req_uop_uses_ldq, // @[mshrs.scala:39:14]
input io_req_uop_uses_stq, // @[mshrs.scala:39:14]
input io_req_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
input io_req_uop_is_unique, // @[mshrs.scala:39:14]
input io_req_uop_flush_on_commit, // @[mshrs.scala:39:14]
input io_req_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_ldst, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_lrs1, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_lrs2, // @[mshrs.scala:39:14]
input [5:0] io_req_uop_lrs3, // @[mshrs.scala:39:14]
input io_req_uop_ldst_val, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_dst_rtype, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_lrs1_rtype, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_lrs2_rtype, // @[mshrs.scala:39:14]
input io_req_uop_frs3_en, // @[mshrs.scala:39:14]
input io_req_uop_fp_val, // @[mshrs.scala:39:14]
input io_req_uop_fp_single, // @[mshrs.scala:39:14]
input io_req_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
input io_req_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
input io_req_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
input io_req_uop_bp_debug_if, // @[mshrs.scala:39:14]
input io_req_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_debug_fsrc, // @[mshrs.scala:39:14]
input [1:0] io_req_uop_debug_tsrc, // @[mshrs.scala:39:14]
input [33:0] io_req_addr, // @[mshrs.scala:39:14]
input [63:0] io_req_data, // @[mshrs.scala:39:14]
input io_req_is_hella, // @[mshrs.scala:39:14]
input io_req_tag_match, // @[mshrs.scala:39:14]
input [1:0] io_req_old_meta_coh_state, // @[mshrs.scala:39:14]
input [21:0] io_req_old_meta_tag, // @[mshrs.scala:39:14]
input [1:0] io_req_way_en, // @[mshrs.scala:39:14]
input [4:0] io_req_sdq_id, // @[mshrs.scala:39:14]
input io_req_is_probe, // @[mshrs.scala:39:14]
output io_idx_valid, // @[mshrs.scala:39:14]
output [3:0] io_idx_bits, // @[mshrs.scala:39:14]
output io_way_valid, // @[mshrs.scala:39:14]
output [1:0] io_way_bits, // @[mshrs.scala:39:14]
output io_tag_valid, // @[mshrs.scala:39:14]
output [23:0] io_tag_bits, // @[mshrs.scala:39:14]
input io_mem_acquire_ready, // @[mshrs.scala:39:14]
output io_mem_acquire_valid, // @[mshrs.scala:39:14]
output [2:0] io_mem_acquire_bits_param, // @[mshrs.scala:39:14]
output [31:0] io_mem_acquire_bits_address, // @[mshrs.scala:39:14]
output io_mem_grant_ready, // @[mshrs.scala:39:14]
input io_mem_grant_valid, // @[mshrs.scala:39:14]
input [2:0] io_mem_grant_bits_opcode, // @[mshrs.scala:39:14]
input [1:0] io_mem_grant_bits_param, // @[mshrs.scala:39:14]
input [3:0] io_mem_grant_bits_size, // @[mshrs.scala:39:14]
input [3:0] io_mem_grant_bits_source, // @[mshrs.scala:39:14]
input [2:0] io_mem_grant_bits_sink, // @[mshrs.scala:39:14]
input io_mem_grant_bits_denied, // @[mshrs.scala:39:14]
input [63:0] io_mem_grant_bits_data, // @[mshrs.scala:39:14]
input io_mem_grant_bits_corrupt, // @[mshrs.scala:39:14]
input io_mem_finish_ready, // @[mshrs.scala:39:14]
output io_mem_finish_valid, // @[mshrs.scala:39:14]
output [2:0] io_mem_finish_bits_sink, // @[mshrs.scala:39:14]
input io_prober_state_valid, // @[mshrs.scala:39:14]
input [33:0] io_prober_state_bits, // @[mshrs.scala:39:14]
input io_refill_ready, // @[mshrs.scala:39:14]
output io_refill_valid, // @[mshrs.scala:39:14]
output [1:0] io_refill_bits_way_en, // @[mshrs.scala:39:14]
output [9:0] io_refill_bits_addr, // @[mshrs.scala:39:14]
output [63:0] io_refill_bits_data, // @[mshrs.scala:39:14]
input io_meta_write_ready, // @[mshrs.scala:39:14]
output io_meta_write_valid, // @[mshrs.scala:39:14]
output [3:0] io_meta_write_bits_idx, // @[mshrs.scala:39:14]
output [1:0] io_meta_write_bits_way_en, // @[mshrs.scala:39:14]
output [1:0] io_meta_write_bits_data_coh_state, // @[mshrs.scala:39:14]
output [21:0] io_meta_write_bits_data_tag, // @[mshrs.scala:39:14]
input io_meta_read_ready, // @[mshrs.scala:39:14]
output io_meta_read_valid, // @[mshrs.scala:39:14]
output [3:0] io_meta_read_bits_idx, // @[mshrs.scala:39:14]
output [1:0] io_meta_read_bits_way_en, // @[mshrs.scala:39:14]
output [21:0] io_meta_read_bits_tag, // @[mshrs.scala:39:14]
input io_meta_resp_valid, // @[mshrs.scala:39:14]
input [1:0] io_meta_resp_bits_coh_state, // @[mshrs.scala:39:14]
input [21:0] io_meta_resp_bits_tag, // @[mshrs.scala:39:14]
input io_wb_req_ready, // @[mshrs.scala:39:14]
output io_wb_req_valid, // @[mshrs.scala:39:14]
output [21:0] io_wb_req_bits_tag, // @[mshrs.scala:39:14]
output [3:0] io_wb_req_bits_idx, // @[mshrs.scala:39:14]
output [2:0] io_wb_req_bits_param, // @[mshrs.scala:39:14]
output [1:0] io_wb_req_bits_way_en, // @[mshrs.scala:39:14]
output io_commit_val, // @[mshrs.scala:39:14]
output [33:0] io_commit_addr, // @[mshrs.scala:39:14]
output [1:0] io_commit_coh_state, // @[mshrs.scala:39:14]
input io_lb_read_ready, // @[mshrs.scala:39:14]
output io_lb_read_valid, // @[mshrs.scala:39:14]
output [2:0] io_lb_read_bits_offset, // @[mshrs.scala:39:14]
input [63:0] io_lb_resp, // @[mshrs.scala:39:14]
output io_lb_write_valid, // @[mshrs.scala:39:14]
output [2:0] io_lb_write_bits_offset, // @[mshrs.scala:39:14]
output [63:0] io_lb_write_bits_data, // @[mshrs.scala:39:14]
input io_replay_ready, // @[mshrs.scala:39:14]
output io_replay_valid, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_uopc, // @[mshrs.scala:39:14]
output [31:0] io_replay_bits_uop_inst, // @[mshrs.scala:39:14]
output [31:0] io_replay_bits_uop_debug_inst, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_rvc, // @[mshrs.scala:39:14]
output [33:0] io_replay_bits_uop_debug_pc, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_iq_type, // @[mshrs.scala:39:14]
output [9:0] io_replay_bits_uop_fu_code, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14]
output [2:0] io_replay_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_iw_state, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14]
output io_replay_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_br, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_jalr, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_jal, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_sfb, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_br_mask, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_br_tag, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_ftq_idx, // @[mshrs.scala:39:14]
output io_replay_bits_uop_edge_inst, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_pc_lob, // @[mshrs.scala:39:14]
output io_replay_bits_uop_taken, // @[mshrs.scala:39:14]
output [19:0] io_replay_bits_uop_imm_packed, // @[mshrs.scala:39:14]
output [11:0] io_replay_bits_uop_csr_addr, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_rob_idx, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_ldq_idx, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_stq_idx, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_rxq_idx, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_pdst, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_prs1, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_prs2, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_prs3, // @[mshrs.scala:39:14]
output [3:0] io_replay_bits_uop_ppred, // @[mshrs.scala:39:14]
output io_replay_bits_uop_prs1_busy, // @[mshrs.scala:39:14]
output io_replay_bits_uop_prs2_busy, // @[mshrs.scala:39:14]
output io_replay_bits_uop_prs3_busy, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ppred_busy, // @[mshrs.scala:39:14]
output [6:0] io_replay_bits_uop_stale_pdst, // @[mshrs.scala:39:14]
output io_replay_bits_uop_exception, // @[mshrs.scala:39:14]
output [63:0] io_replay_bits_uop_exc_cause, // @[mshrs.scala:39:14]
output io_replay_bits_uop_bypassable, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_uop_mem_cmd, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_mem_size, // @[mshrs.scala:39:14]
output io_replay_bits_uop_mem_signed, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_fence, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_fencei, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_amo, // @[mshrs.scala:39:14]
output io_replay_bits_uop_uses_ldq, // @[mshrs.scala:39:14]
output io_replay_bits_uop_uses_stq, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
output io_replay_bits_uop_is_unique, // @[mshrs.scala:39:14]
output io_replay_bits_uop_flush_on_commit, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_ldst, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_lrs1, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_lrs2, // @[mshrs.scala:39:14]
output [5:0] io_replay_bits_uop_lrs3, // @[mshrs.scala:39:14]
output io_replay_bits_uop_ldst_val, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_dst_rtype, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14]
output io_replay_bits_uop_frs3_en, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_val, // @[mshrs.scala:39:14]
output io_replay_bits_uop_fp_single, // @[mshrs.scala:39:14]
output io_replay_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_bp_debug_if, // @[mshrs.scala:39:14]
output io_replay_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_debug_fsrc, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_uop_debug_tsrc, // @[mshrs.scala:39:14]
output [33:0] io_replay_bits_addr, // @[mshrs.scala:39:14]
output [63:0] io_replay_bits_data, // @[mshrs.scala:39:14]
output io_replay_bits_is_hella, // @[mshrs.scala:39:14]
output io_replay_bits_tag_match, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_old_meta_coh_state, // @[mshrs.scala:39:14]
output [21:0] io_replay_bits_old_meta_tag, // @[mshrs.scala:39:14]
output [1:0] io_replay_bits_way_en, // @[mshrs.scala:39:14]
output [4:0] io_replay_bits_sdq_id, // @[mshrs.scala:39:14]
input io_resp_ready, // @[mshrs.scala:39:14]
output io_resp_valid, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_uopc, // @[mshrs.scala:39:14]
output [31:0] io_resp_bits_uop_inst, // @[mshrs.scala:39:14]
output [31:0] io_resp_bits_uop_debug_inst, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_rvc, // @[mshrs.scala:39:14]
output [33:0] io_resp_bits_uop_debug_pc, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_iq_type, // @[mshrs.scala:39:14]
output [9:0] io_resp_bits_uop_fu_code, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_ctrl_br_type, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_ctrl_op1_sel, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_ctrl_op2_sel, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_ctrl_imm_sel, // @[mshrs.scala:39:14]
output [4:0] io_resp_bits_uop_ctrl_op_fcn, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ctrl_fcn_dw, // @[mshrs.scala:39:14]
output [2:0] io_resp_bits_uop_ctrl_csr_cmd, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ctrl_is_load, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ctrl_is_sta, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ctrl_is_std, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_iw_state, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iw_p1_poisoned, // @[mshrs.scala:39:14]
output io_resp_bits_uop_iw_p2_poisoned, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_br, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_jalr, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_jal, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_sfb, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_br_mask, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_br_tag, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_ftq_idx, // @[mshrs.scala:39:14]
output io_resp_bits_uop_edge_inst, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_pc_lob, // @[mshrs.scala:39:14]
output io_resp_bits_uop_taken, // @[mshrs.scala:39:14]
output [19:0] io_resp_bits_uop_imm_packed, // @[mshrs.scala:39:14]
output [11:0] io_resp_bits_uop_csr_addr, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_rob_idx, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_ldq_idx, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_stq_idx, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_rxq_idx, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_pdst, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_prs1, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_prs2, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_prs3, // @[mshrs.scala:39:14]
output [3:0] io_resp_bits_uop_ppred, // @[mshrs.scala:39:14]
output io_resp_bits_uop_prs1_busy, // @[mshrs.scala:39:14]
output io_resp_bits_uop_prs2_busy, // @[mshrs.scala:39:14]
output io_resp_bits_uop_prs3_busy, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ppred_busy, // @[mshrs.scala:39:14]
output [6:0] io_resp_bits_uop_stale_pdst, // @[mshrs.scala:39:14]
output io_resp_bits_uop_exception, // @[mshrs.scala:39:14]
output [63:0] io_resp_bits_uop_exc_cause, // @[mshrs.scala:39:14]
output io_resp_bits_uop_bypassable, // @[mshrs.scala:39:14]
output [4:0] io_resp_bits_uop_mem_cmd, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_mem_size, // @[mshrs.scala:39:14]
output io_resp_bits_uop_mem_signed, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_fence, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_fencei, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_amo, // @[mshrs.scala:39:14]
output io_resp_bits_uop_uses_ldq, // @[mshrs.scala:39:14]
output io_resp_bits_uop_uses_stq, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_sys_pc2epc, // @[mshrs.scala:39:14]
output io_resp_bits_uop_is_unique, // @[mshrs.scala:39:14]
output io_resp_bits_uop_flush_on_commit, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ldst_is_rs1, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_ldst, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_lrs1, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_lrs2, // @[mshrs.scala:39:14]
output [5:0] io_resp_bits_uop_lrs3, // @[mshrs.scala:39:14]
output io_resp_bits_uop_ldst_val, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_dst_rtype, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_lrs1_rtype, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_lrs2_rtype, // @[mshrs.scala:39:14]
output io_resp_bits_uop_frs3_en, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_val, // @[mshrs.scala:39:14]
output io_resp_bits_uop_fp_single, // @[mshrs.scala:39:14]
output io_resp_bits_uop_xcpt_pf_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_xcpt_ae_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_xcpt_ma_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_bp_debug_if, // @[mshrs.scala:39:14]
output io_resp_bits_uop_bp_xcpt_if, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_debug_fsrc, // @[mshrs.scala:39:14]
output [1:0] io_resp_bits_uop_debug_tsrc, // @[mshrs.scala:39:14]
output [63:0] io_resp_bits_data, // @[mshrs.scala:39:14]
output io_resp_bits_is_hella, // @[mshrs.scala:39:14]
input io_wb_resp, // @[mshrs.scala:39:14]
output io_probe_rdy // @[mshrs.scala:39:14]
);
wire rpq_io_deq_ready; // @[mshrs.scala:135:20, :215:30, :222:40, :233:41, :256:45]
wire _rpq_io_enq_ready; // @[mshrs.scala:128:19]
wire _rpq_io_deq_valid; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_uopc; // @[mshrs.scala:128:19]
wire [31:0] _rpq_io_deq_bits_uop_inst; // @[mshrs.scala:128:19]
wire [31:0] _rpq_io_deq_bits_uop_debug_inst; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_rvc; // @[mshrs.scala:128:19]
wire [33:0] _rpq_io_deq_bits_uop_debug_pc; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_iq_type; // @[mshrs.scala:128:19]
wire [9:0] _rpq_io_deq_bits_uop_fu_code; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_ctrl_br_type; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_ctrl_op1_sel; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_ctrl_op2_sel; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_ctrl_imm_sel; // @[mshrs.scala:128:19]
wire [4:0] _rpq_io_deq_bits_uop_ctrl_op_fcn; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ctrl_fcn_dw; // @[mshrs.scala:128:19]
wire [2:0] _rpq_io_deq_bits_uop_ctrl_csr_cmd; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ctrl_is_load; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ctrl_is_sta; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ctrl_is_std; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_iw_state; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iw_p1_poisoned; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_iw_p2_poisoned; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_br; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_jalr; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_jal; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_sfb; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_br_mask; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_br_tag; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_ftq_idx; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_edge_inst; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_pc_lob; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_taken; // @[mshrs.scala:128:19]
wire [19:0] _rpq_io_deq_bits_uop_imm_packed; // @[mshrs.scala:128:19]
wire [11:0] _rpq_io_deq_bits_uop_csr_addr; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_rob_idx; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_ldq_idx; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_stq_idx; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_rxq_idx; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_pdst; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_prs1; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_prs2; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_prs3; // @[mshrs.scala:128:19]
wire [3:0] _rpq_io_deq_bits_uop_ppred; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_prs1_busy; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_prs2_busy; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_prs3_busy; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ppred_busy; // @[mshrs.scala:128:19]
wire [6:0] _rpq_io_deq_bits_uop_stale_pdst; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_exception; // @[mshrs.scala:128:19]
wire [63:0] _rpq_io_deq_bits_uop_exc_cause; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_bypassable; // @[mshrs.scala:128:19]
wire [4:0] _rpq_io_deq_bits_uop_mem_cmd; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_mem_size; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_mem_signed; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_fence; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_fencei; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_amo; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_uses_ldq; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_uses_stq; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_sys_pc2epc; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_is_unique; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_flush_on_commit; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ldst_is_rs1; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_ldst; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_lrs1; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_lrs2; // @[mshrs.scala:128:19]
wire [5:0] _rpq_io_deq_bits_uop_lrs3; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_ldst_val; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_dst_rtype; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_lrs1_rtype; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_lrs2_rtype; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_frs3_en; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_val; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_fp_single; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_xcpt_pf_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_xcpt_ae_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_xcpt_ma_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_bp_debug_if; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_uop_bp_xcpt_if; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_debug_fsrc; // @[mshrs.scala:128:19]
wire [1:0] _rpq_io_deq_bits_uop_debug_tsrc; // @[mshrs.scala:128:19]
wire [33:0] _rpq_io_deq_bits_addr; // @[mshrs.scala:128:19]
wire _rpq_io_deq_bits_is_hella; // @[mshrs.scala:128:19]
wire _rpq_io_empty; // @[mshrs.scala:128:19]
wire io_req_pri_val_0 = io_req_pri_val; // @[mshrs.scala:36:7]
wire io_req_sec_val_0 = io_req_sec_val; // @[mshrs.scala:36:7]
wire io_clear_prefetch_0 = io_clear_prefetch; // @[mshrs.scala:36:7]
wire [5:0] io_rob_pnr_idx_0 = io_rob_pnr_idx; // @[mshrs.scala:36:7]
wire [5:0] io_rob_head_idx_0 = io_rob_head_idx; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_uopc_0 = io_req_uop_uopc; // @[mshrs.scala:36:7]
wire [31:0] io_req_uop_inst_0 = io_req_uop_inst; // @[mshrs.scala:36:7]
wire [31:0] io_req_uop_debug_inst_0 = io_req_uop_debug_inst; // @[mshrs.scala:36:7]
wire io_req_uop_is_rvc_0 = io_req_uop_is_rvc; // @[mshrs.scala:36:7]
wire [33:0] io_req_uop_debug_pc_0 = io_req_uop_debug_pc; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_iq_type_0 = io_req_uop_iq_type; // @[mshrs.scala:36:7]
wire [9:0] io_req_uop_fu_code_0 = io_req_uop_fu_code; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_ctrl_br_type_0 = io_req_uop_ctrl_br_type; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_ctrl_op1_sel_0 = io_req_uop_ctrl_op1_sel; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_ctrl_op2_sel_0 = io_req_uop_ctrl_op2_sel; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_ctrl_imm_sel_0 = io_req_uop_ctrl_imm_sel; // @[mshrs.scala:36:7]
wire [4:0] io_req_uop_ctrl_op_fcn_0 = io_req_uop_ctrl_op_fcn; // @[mshrs.scala:36:7]
wire io_req_uop_ctrl_fcn_dw_0 = io_req_uop_ctrl_fcn_dw; // @[mshrs.scala:36:7]
wire [2:0] io_req_uop_ctrl_csr_cmd_0 = io_req_uop_ctrl_csr_cmd; // @[mshrs.scala:36:7]
wire io_req_uop_ctrl_is_load_0 = io_req_uop_ctrl_is_load; // @[mshrs.scala:36:7]
wire io_req_uop_ctrl_is_sta_0 = io_req_uop_ctrl_is_sta; // @[mshrs.scala:36:7]
wire io_req_uop_ctrl_is_std_0 = io_req_uop_ctrl_is_std; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_iw_state_0 = io_req_uop_iw_state; // @[mshrs.scala:36:7]
wire io_req_uop_iw_p1_poisoned_0 = io_req_uop_iw_p1_poisoned; // @[mshrs.scala:36:7]
wire io_req_uop_iw_p2_poisoned_0 = io_req_uop_iw_p2_poisoned; // @[mshrs.scala:36:7]
wire io_req_uop_is_br_0 = io_req_uop_is_br; // @[mshrs.scala:36:7]
wire io_req_uop_is_jalr_0 = io_req_uop_is_jalr; // @[mshrs.scala:36:7]
wire io_req_uop_is_jal_0 = io_req_uop_is_jal; // @[mshrs.scala:36:7]
wire io_req_uop_is_sfb_0 = io_req_uop_is_sfb; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_br_mask_0 = io_req_uop_br_mask; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_br_tag_0 = io_req_uop_br_tag; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_ftq_idx_0 = io_req_uop_ftq_idx; // @[mshrs.scala:36:7]
wire io_req_uop_edge_inst_0 = io_req_uop_edge_inst; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_pc_lob_0 = io_req_uop_pc_lob; // @[mshrs.scala:36:7]
wire io_req_uop_taken_0 = io_req_uop_taken; // @[mshrs.scala:36:7]
wire [19:0] io_req_uop_imm_packed_0 = io_req_uop_imm_packed; // @[mshrs.scala:36:7]
wire [11:0] io_req_uop_csr_addr_0 = io_req_uop_csr_addr; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_rob_idx_0 = io_req_uop_rob_idx; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_ldq_idx_0 = io_req_uop_ldq_idx; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_stq_idx_0 = io_req_uop_stq_idx; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_rxq_idx_0 = io_req_uop_rxq_idx; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_pdst_0 = io_req_uop_pdst; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_prs1_0 = io_req_uop_prs1; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_prs2_0 = io_req_uop_prs2; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_prs3_0 = io_req_uop_prs3; // @[mshrs.scala:36:7]
wire [3:0] io_req_uop_ppred_0 = io_req_uop_ppred; // @[mshrs.scala:36:7]
wire io_req_uop_prs1_busy_0 = io_req_uop_prs1_busy; // @[mshrs.scala:36:7]
wire io_req_uop_prs2_busy_0 = io_req_uop_prs2_busy; // @[mshrs.scala:36:7]
wire io_req_uop_prs3_busy_0 = io_req_uop_prs3_busy; // @[mshrs.scala:36:7]
wire io_req_uop_ppred_busy_0 = io_req_uop_ppred_busy; // @[mshrs.scala:36:7]
wire [6:0] io_req_uop_stale_pdst_0 = io_req_uop_stale_pdst; // @[mshrs.scala:36:7]
wire io_req_uop_exception_0 = io_req_uop_exception; // @[mshrs.scala:36:7]
wire [63:0] io_req_uop_exc_cause_0 = io_req_uop_exc_cause; // @[mshrs.scala:36:7]
wire io_req_uop_bypassable_0 = io_req_uop_bypassable; // @[mshrs.scala:36:7]
wire [4:0] io_req_uop_mem_cmd_0 = io_req_uop_mem_cmd; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_mem_size_0 = io_req_uop_mem_size; // @[mshrs.scala:36:7]
wire io_req_uop_mem_signed_0 = io_req_uop_mem_signed; // @[mshrs.scala:36:7]
wire io_req_uop_is_fence_0 = io_req_uop_is_fence; // @[mshrs.scala:36:7]
wire io_req_uop_is_fencei_0 = io_req_uop_is_fencei; // @[mshrs.scala:36:7]
wire io_req_uop_is_amo_0 = io_req_uop_is_amo; // @[mshrs.scala:36:7]
wire io_req_uop_uses_ldq_0 = io_req_uop_uses_ldq; // @[mshrs.scala:36:7]
wire io_req_uop_uses_stq_0 = io_req_uop_uses_stq; // @[mshrs.scala:36:7]
wire io_req_uop_is_sys_pc2epc_0 = io_req_uop_is_sys_pc2epc; // @[mshrs.scala:36:7]
wire io_req_uop_is_unique_0 = io_req_uop_is_unique; // @[mshrs.scala:36:7]
wire io_req_uop_flush_on_commit_0 = io_req_uop_flush_on_commit; // @[mshrs.scala:36:7]
wire io_req_uop_ldst_is_rs1_0 = io_req_uop_ldst_is_rs1; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_ldst_0 = io_req_uop_ldst; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_lrs1_0 = io_req_uop_lrs1; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_lrs2_0 = io_req_uop_lrs2; // @[mshrs.scala:36:7]
wire [5:0] io_req_uop_lrs3_0 = io_req_uop_lrs3; // @[mshrs.scala:36:7]
wire io_req_uop_ldst_val_0 = io_req_uop_ldst_val; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_dst_rtype_0 = io_req_uop_dst_rtype; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_lrs1_rtype_0 = io_req_uop_lrs1_rtype; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_lrs2_rtype_0 = io_req_uop_lrs2_rtype; // @[mshrs.scala:36:7]
wire io_req_uop_frs3_en_0 = io_req_uop_frs3_en; // @[mshrs.scala:36:7]
wire io_req_uop_fp_val_0 = io_req_uop_fp_val; // @[mshrs.scala:36:7]
wire io_req_uop_fp_single_0 = io_req_uop_fp_single; // @[mshrs.scala:36:7]
wire io_req_uop_xcpt_pf_if_0 = io_req_uop_xcpt_pf_if; // @[mshrs.scala:36:7]
wire io_req_uop_xcpt_ae_if_0 = io_req_uop_xcpt_ae_if; // @[mshrs.scala:36:7]
wire io_req_uop_xcpt_ma_if_0 = io_req_uop_xcpt_ma_if; // @[mshrs.scala:36:7]
wire io_req_uop_bp_debug_if_0 = io_req_uop_bp_debug_if; // @[mshrs.scala:36:7]
wire io_req_uop_bp_xcpt_if_0 = io_req_uop_bp_xcpt_if; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_debug_fsrc_0 = io_req_uop_debug_fsrc; // @[mshrs.scala:36:7]
wire [1:0] io_req_uop_debug_tsrc_0 = io_req_uop_debug_tsrc; // @[mshrs.scala:36:7]
wire [33:0] io_req_addr_0 = io_req_addr; // @[mshrs.scala:36:7]
wire [63:0] io_req_data_0 = io_req_data; // @[mshrs.scala:36:7]
wire io_req_is_hella_0 = io_req_is_hella; // @[mshrs.scala:36:7]
wire io_req_tag_match_0 = io_req_tag_match; // @[mshrs.scala:36:7]
wire [1:0] io_req_old_meta_coh_state_0 = io_req_old_meta_coh_state; // @[mshrs.scala:36:7]
wire [21:0] io_req_old_meta_tag_0 = io_req_old_meta_tag; // @[mshrs.scala:36:7]
wire [1:0] io_req_way_en_0 = io_req_way_en; // @[mshrs.scala:36:7]
wire [4:0] io_req_sdq_id_0 = io_req_sdq_id; // @[mshrs.scala:36:7]
wire io_req_is_probe_0 = io_req_is_probe; // @[mshrs.scala:36:7]
wire io_mem_acquire_ready_0 = io_mem_acquire_ready; // @[mshrs.scala:36:7]
wire io_mem_grant_valid_0 = io_mem_grant_valid; // @[mshrs.scala:36:7]
wire [2:0] io_mem_grant_bits_opcode_0 = io_mem_grant_bits_opcode; // @[mshrs.scala:36:7]
wire [1:0] io_mem_grant_bits_param_0 = io_mem_grant_bits_param; // @[mshrs.scala:36:7]
wire [3:0] io_mem_grant_bits_size_0 = io_mem_grant_bits_size; // @[mshrs.scala:36:7]
wire [3:0] io_mem_grant_bits_source_0 = io_mem_grant_bits_source; // @[mshrs.scala:36:7]
wire [2:0] io_mem_grant_bits_sink_0 = io_mem_grant_bits_sink; // @[mshrs.scala:36:7]
wire io_mem_grant_bits_denied_0 = io_mem_grant_bits_denied; // @[mshrs.scala:36:7]
wire [63:0] io_mem_grant_bits_data_0 = io_mem_grant_bits_data; // @[mshrs.scala:36:7]
wire io_mem_grant_bits_corrupt_0 = io_mem_grant_bits_corrupt; // @[mshrs.scala:36:7]
wire io_mem_finish_ready_0 = io_mem_finish_ready; // @[mshrs.scala:36:7]
wire io_prober_state_valid_0 = io_prober_state_valid; // @[mshrs.scala:36:7]
wire [33:0] io_prober_state_bits_0 = io_prober_state_bits; // @[mshrs.scala:36:7]
wire io_refill_ready_0 = io_refill_ready; // @[mshrs.scala:36:7]
wire io_meta_write_ready_0 = io_meta_write_ready; // @[mshrs.scala:36:7]
wire io_meta_read_ready_0 = io_meta_read_ready; // @[mshrs.scala:36:7]
wire io_meta_resp_valid_0 = io_meta_resp_valid; // @[mshrs.scala:36:7]
wire [1:0] io_meta_resp_bits_coh_state_0 = io_meta_resp_bits_coh_state; // @[mshrs.scala:36:7]
wire [21:0] io_meta_resp_bits_tag_0 = io_meta_resp_bits_tag; // @[mshrs.scala:36:7]
wire io_wb_req_ready_0 = io_wb_req_ready; // @[mshrs.scala:36:7]
wire io_lb_read_ready_0 = io_lb_read_ready; // @[mshrs.scala:36:7]
wire [63:0] io_lb_resp_0 = io_lb_resp; // @[mshrs.scala:36:7]
wire io_replay_ready_0 = io_replay_ready; // @[mshrs.scala:36:7]
wire io_resp_ready_0 = io_resp_ready; // @[mshrs.scala:36:7]
wire io_wb_resp_0 = io_wb_resp; // @[mshrs.scala:36:7]
wire _state_T = reset; // @[mshrs.scala:194:11]
wire _state_T_26 = reset; // @[mshrs.scala:201:15]
wire _state_T_34 = reset; // @[mshrs.scala:194:11]
wire _state_T_60 = reset; // @[mshrs.scala:201:15]
wire [2:0] io_id = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_iq_type = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_brupdate_b2_cfi_type = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_lb_read_bits_id = 3'h0; // @[mshrs.scala:36:7]
wire [2:0] io_lb_write_bits_id = 3'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b1_resolve_mask = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b1_mispredict_mask = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_br_mask = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_ftq_idx = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_ldq_idx = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_stq_idx = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_brupdate_b2_uop_ppred = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_mem_acquire_bits_source = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] io_wb_req_bits_source = 4'h0; // @[mshrs.scala:36:7]
wire [3:0] _r_T_10 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _grow_param_r_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _coh_on_grant_T_4 = 4'h0; // @[Metadata.scala:87:10]
wire [3:0] _r1_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _r2_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _state_req_needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _state_r_T_16 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] io_mem_acquire_bits_a_source = 4'h0; // @[Edges.scala:346:17]
wire [3:0] _needs_wb_r_T_10 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _r_T_80 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _r_T_139 = 4'h0; // @[Metadata.scala:68:10]
wire [3:0] _state_req_needs_wb_r_T_74 = 4'h0; // @[Metadata.scala:125:10]
wire [3:0] _state_r_T_75 = 4'h0; // @[Metadata.scala:68:10]
wire [6:0] io_brupdate_b2_uop_uopc = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_pdst = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_prs1 = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_prs2 = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_prs3 = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst = 7'h0; // @[mshrs.scala:36:7]
wire [6:0] _data_word_T = 7'h0; // @[mshrs.scala:264:32]
wire [31:0] io_brupdate_b2_uop_inst = 32'h0; // @[mshrs.scala:36:7]
wire [31:0] io_brupdate_b2_uop_debug_inst = 32'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_rvc = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ctrl_is_load = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ctrl_is_sta = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ctrl_is_std = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iw_p1_poisoned = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_iw_p2_poisoned = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_br = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_jalr = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_jal = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_sfb = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_edge_inst = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_taken = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_prs1_busy = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_prs2_busy = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_prs3_busy = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ppred_busy = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_exception = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_bypassable = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_mem_signed = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_fence = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_fencei = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_amo = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_uses_ldq = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_uses_stq = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_sys_pc2epc = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_is_unique = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_flush_on_commit = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ldst_is_rs1 = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_ldst_val = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_frs3_en = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_val = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_fp_single = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_xcpt_pf_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_xcpt_ae_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_xcpt_ma_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_bp_debug_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_uop_bp_xcpt_if = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_valid = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_mispredict = 1'h0; // @[mshrs.scala:36:7]
wire io_brupdate_b2_taken = 1'h0; // @[mshrs.scala:36:7]
wire io_exception = 1'h0; // @[mshrs.scala:36:7]
wire io_mem_acquire_bits_corrupt = 1'h0; // @[mshrs.scala:36:7]
wire _r_T_2 = 1'h0; // @[Metadata.scala:140:24]
wire _r_T_4 = 1'h0; // @[Metadata.scala:140:24]
wire _r_T_20 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_24 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_28 = 1'h0; // @[Misc.scala:38:9]
wire _grow_param_r_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _grow_param_r_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _r1_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _r2_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _state_req_needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9]
wire _state_r_T_26 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_29 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_32 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_35 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_38 = 1'h0; // @[Misc.scala:35:9]
wire _io_mem_acquire_bits_legal_T = 1'h0; // @[Parameters.scala:684:29]
wire _io_mem_acquire_bits_legal_T_6 = 1'h0; // @[Parameters.scala:684:54]
wire _io_mem_acquire_bits_legal_T_15 = 1'h0; // @[Parameters.scala:686:26]
wire io_mem_acquire_bits_a_corrupt = 1'h0; // @[Edges.scala:346:17]
wire io_mem_acquire_bits_a_mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _io_mem_acquire_bits_a_mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38]
wire _io_mem_acquire_bits_a_mask_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38]
wire io_resp_bits_data_doZero = 1'h0; // @[AMOALU.scala:43:31]
wire io_resp_bits_data_doZero_1 = 1'h0; // @[AMOALU.scala:43:31]
wire io_resp_bits_data_doZero_2 = 1'h0; // @[AMOALU.scala:43:31]
wire _needs_wb_r_T_2 = 1'h0; // @[Metadata.scala:140:24]
wire _needs_wb_r_T_4 = 1'h0; // @[Metadata.scala:140:24]
wire _needs_wb_r_T_20 = 1'h0; // @[Misc.scala:38:9]
wire _needs_wb_r_T_24 = 1'h0; // @[Misc.scala:38:9]
wire _needs_wb_r_T_28 = 1'h0; // @[Misc.scala:38:9]
wire _r_T_90 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_93 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_96 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_99 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_102 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_149 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_152 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_155 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_158 = 1'h0; // @[Misc.scala:35:9]
wire _r_T_161 = 1'h0; // @[Misc.scala:35:9]
wire _state_req_needs_wb_r_T_66 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_68 = 1'h0; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T_84 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_88 = 1'h0; // @[Misc.scala:38:9]
wire _state_req_needs_wb_r_T_92 = 1'h0; // @[Misc.scala:38:9]
wire _state_r_T_85 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_88 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_91 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_94 = 1'h0; // @[Misc.scala:35:9]
wire _state_r_T_97 = 1'h0; // @[Misc.scala:35:9]
wire [33:0] io_brupdate_b2_uop_debug_pc = 34'h0; // @[mshrs.scala:36:7]
wire [33:0] io_brupdate_b2_jalr_target = 34'h0; // @[mshrs.scala:36:7]
wire [9:0] io_brupdate_b2_uop_fu_code = 10'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_iw_state = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_br_tag = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_mem_size = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_pc_sel = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] io_brupdate_b2_target_offset = 2'h0; // @[mshrs.scala:36:7]
wire [1:0] new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _r_T_22 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_26 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_30 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_34 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_38 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _grow_param_r_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _grow_param_r_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _coh_on_grant_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _coh_on_grant_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r1_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r2_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_req_needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_r_T_1 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_3 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_5 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_15 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] state_new_coh_meta_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _needs_wb_r_T_22 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_26 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_30 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_34 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _needs_wb_r_T_38 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _r_T_65 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_67 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_69 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_79 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_124 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_126 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_128 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _r_T_138 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20]
wire [1:0] _state_req_needs_wb_r_T_86 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_90 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_94 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_98 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_req_needs_wb_r_T_102 = 2'h0; // @[Misc.scala:38:63]
wire [1:0] _state_r_T_60 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_62 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_64 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] _state_r_T_74 = 2'h0; // @[Metadata.scala:26:15]
wire [1:0] state_new_coh_meta_1_state = 2'h0; // @[Metadata.scala:160:20]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn = 5'h0; // @[mshrs.scala:36:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd = 5'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_pc_lob = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_rob_idx = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_ldst = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_lrs1 = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_lrs2 = 6'h0; // @[mshrs.scala:36:7]
wire [5:0] io_brupdate_b2_uop_lrs3 = 6'h0; // @[mshrs.scala:36:7]
wire [19:0] io_brupdate_b2_uop_imm_packed = 20'h0; // @[mshrs.scala:36:7]
wire [11:0] io_brupdate_b2_uop_csr_addr = 12'h0; // @[mshrs.scala:36:7]
wire [63:0] io_brupdate_b2_uop_exc_cause = 64'h0; // @[mshrs.scala:36:7]
wire [63:0] io_mem_acquire_bits_data = 64'h0; // @[mshrs.scala:36:7]
wire [63:0] io_mem_acquire_bits_a_data = 64'h0; // @[Edges.scala:346:17]
wire [2:0] io_mem_acquire_bits_opcode = 3'h6; // @[mshrs.scala:36:7]
wire [2:0] io_mem_acquire_bits_a_opcode = 3'h6; // @[Edges.scala:346:17]
wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T = 3'h6; // @[Misc.scala:202:34]
wire [3:0] io_mem_acquire_bits_size = 4'h6; // @[mshrs.scala:36:7]
wire [3:0] _r_T_12 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _grow_param_r_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r1_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r2_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _state_req_needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _state_r_T_10 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] io_mem_acquire_bits_a_size = 4'h6; // @[Edges.scala:346:17]
wire [3:0] _needs_wb_r_T_12 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _r_T_74 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _r_T_133 = 4'h6; // @[Metadata.scala:64:10]
wire [3:0] _state_req_needs_wb_r_T_76 = 4'h6; // @[Metadata.scala:127:10]
wire [3:0] _state_r_T_69 = 4'h6; // @[Metadata.scala:64:10]
wire [7:0] io_mem_acquire_bits_mask = 8'hFF; // @[mshrs.scala:36:7]
wire [7:0] io_mem_acquire_bits_a_mask = 8'hFF; // @[Edges.scala:346:17]
wire [7:0] _io_mem_acquire_bits_a_mask_T = 8'hFF; // @[Misc.scala:222:10]
wire io_refill_bits_wmask = 1'h1; // @[mshrs.scala:36:7]
wire io_wb_req_bits_voluntary = 1'h1; // @[mshrs.scala:36:7]
wire io_lb_write_ready = 1'h1; // @[mshrs.scala:36:7]
wire _r_T = 1'h1; // @[Metadata.scala:140:24]
wire _state_req_needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24]
wire _io_mem_acquire_bits_legal_T_7 = 1'h1; // @[Parameters.scala:91:44]
wire _io_mem_acquire_bits_legal_T_8 = 1'h1; // @[Parameters.scala:684:29]
wire io_mem_acquire_bits_a_mask_sub_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire io_mem_acquire_bits_a_mask_sub_sub_size = 1'h1; // @[Misc.scala:209:26]
wire io_mem_acquire_bits_a_mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_2_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_sub_3_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_size = 1'h1; // @[Misc.scala:209:26]
wire io_mem_acquire_bits_a_mask_acc = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_4 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_5 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_6 = 1'h1; // @[Misc.scala:215:29]
wire io_mem_acquire_bits_a_mask_acc_7 = 1'h1; // @[Misc.scala:215:29]
wire _needs_wb_r_T = 1'h1; // @[Metadata.scala:140:24]
wire _io_refill_bits_wmask_T = 1'h1; // @[mshrs.scala:342:30]
wire _state_req_needs_wb_r_T_64 = 1'h1; // @[Metadata.scala:140:24]
wire [21:0] io_meta_write_bits_tag = 22'h0; // @[mshrs.scala:36:7]
wire [3:0] _grow_param_r_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _coh_on_grant_T_8 = 4'hC; // @[Metadata.scala:89:10]
wire [3:0] _r1_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _r2_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _state_r_T_24 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _r_T_88 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _r_T_147 = 4'hC; // @[Metadata.scala:72:10]
wire [3:0] _state_r_T_83 = 4'hC; // @[Metadata.scala:72:10]
wire [1:0] _grow_param_r_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _grow_param_r_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _coh_on_grant_T_7 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r1_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r2_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _dirties_T = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_11 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_13 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_21 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_23 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] io_mem_acquire_bits_a_mask_lo_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_lo_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_hi_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] io_mem_acquire_bits_a_mask_hi_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] _r_T_75 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_77 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_85 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_87 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_134 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_136 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_144 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _r_T_146 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_70 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_72 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_80 = 2'h3; // @[Metadata.scala:24:15]
wire [1:0] _state_r_T_82 = 2'h3; // @[Metadata.scala:24:15]
wire [3:0] _grow_param_r_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r1_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r2_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _state_r_T_22 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_86 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_145 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _state_r_T_81 = 4'hD; // @[Metadata.scala:71:10]
wire [3:0] _r_T_14 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _grow_param_r_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _coh_on_grant_T_6 = 4'h4; // @[Metadata.scala:88:10]
wire [3:0] _r1_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r2_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _state_req_needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _state_r_T_20 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _io_mem_acquire_bits_a_mask_sizeOH_T_1 = 4'h4; // @[OneHot.scala:65:12]
wire [3:0] _needs_wb_r_T_14 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _r_T_84 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r_T_143 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _state_req_needs_wb_r_T_78 = 4'h4; // @[Metadata.scala:129:10]
wire [3:0] _state_r_T_79 = 4'h4; // @[Metadata.scala:70:10]
wire [3:0] _r_T_13 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _grow_param_r_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r1_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r2_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _state_req_needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _state_r_T_18 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _needs_wb_r_T_13 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _r_T_82 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _r_T_141 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _state_req_needs_wb_r_T_77 = 4'h5; // @[Metadata.scala:128:10]
wire [3:0] _state_r_T_77 = 4'h5; // @[Metadata.scala:69:10]
wire [3:0] _grow_param_r_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r1_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r2_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _state_r_T_14 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r_T_78 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _r_T_137 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _state_r_T_73 = 4'hE; // @[Metadata.scala:66:10]
wire [3:0] _grow_param_r_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r1_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r2_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _state_r_T_12 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] io_mem_acquire_bits_a_mask_lo = 4'hF; // @[Misc.scala:222:10]
wire [3:0] io_mem_acquire_bits_a_mask_hi = 4'hF; // @[Misc.scala:222:10]
wire [3:0] _r_T_76 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r_T_135 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _state_r_T_71 = 4'hF; // @[Metadata.scala:65:10]
wire [3:0] _r_T_11 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _grow_param_r_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r1_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r2_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _state_req_needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _state_r_T_8 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _needs_wb_r_T_11 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _r_T_72 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r_T_131 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _state_req_needs_wb_r_T_75 = 4'h7; // @[Metadata.scala:126:10]
wire [3:0] _state_r_T_67 = 4'h7; // @[Metadata.scala:63:10]
wire [3:0] _r_T_9 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _grow_param_r_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _coh_on_grant_T_2 = 4'h1; // @[Metadata.scala:86:10]
wire [3:0] _r1_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r2_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _state_req_needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _state_r_T_6 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _needs_wb_r_T_9 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _r_T_70 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r_T_129 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _state_req_needs_wb_r_T_73 = 4'h1; // @[Metadata.scala:124:10]
wire [3:0] _state_r_T_65 = 4'h1; // @[Metadata.scala:62:10]
wire [3:0] _r_T_8 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _grow_param_r_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r1_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r2_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _state_req_needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _state_r_T_4 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _needs_wb_r_T_8 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _r_T_68 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r_T_127 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _state_req_needs_wb_r_T_72 = 4'h2; // @[Metadata.scala:123:10]
wire [3:0] _state_r_T_63 = 4'h2; // @[Metadata.scala:61:10]
wire [3:0] _r_T_7 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _grow_param_r_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r1_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r2_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _state_req_needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _state_r_T_2 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _needs_wb_r_T_7 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _r_T_66 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r_T_125 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _state_req_needs_wb_r_T_71 = 4'h3; // @[Metadata.scala:122:10]
wire [3:0] _state_r_T_61 = 4'h3; // @[Metadata.scala:60:10]
wire [3:0] _r_T_18 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _state_req_needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _needs_wb_r_T_18 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _state_req_needs_wb_r_T_82 = 4'h8; // @[Metadata.scala:133:10]
wire [3:0] _r_T_17 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _state_req_needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _needs_wb_r_T_17 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _state_req_needs_wb_r_T_81 = 4'h9; // @[Metadata.scala:132:10]
wire [3:0] _r_T_16 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _state_req_needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _needs_wb_r_T_16 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _state_req_needs_wb_r_T_80 = 4'hA; // @[Metadata.scala:131:10]
wire [3:0] _r_T_15 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _state_req_needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _needs_wb_r_T_15 = 4'hB; // @[Metadata.scala:130:10]
wire [3:0] _state_req_needs_wb_r_T_79 = 4'hB; // @[Metadata.scala:130:10]
wire [1:0] _r_T_1 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _r_T_3 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _r_T_5 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] io_mem_acquire_bits_a_mask_sizeOH_shiftAmount = 2'h2; // @[OneHot.scala:64:49]
wire [1:0] _needs_wb_r_T_1 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _needs_wb_r_T_3 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _needs_wb_r_T_5 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_65 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_67 = 2'h2; // @[Metadata.scala:140:24]
wire [1:0] _state_req_needs_wb_r_T_69 = 2'h2; // @[Metadata.scala:140:24]
wire [2:0] io_mem_acquire_bits_a_mask_sizeOH = 3'h5; // @[Misc.scala:202:81]
wire [2:0] _io_mem_acquire_bits_a_mask_sizeOH_T_2 = 3'h4; // @[OneHot.scala:65:27]
wire [1:0] _grow_param_r_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _grow_param_r_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _coh_on_grant_T_5 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r1_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r2_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_7 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_9 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_17 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_19 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_71 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_73 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_81 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_83 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_130 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_132 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_140 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _r_T_142 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_66 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_68 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_76 = 2'h1; // @[Metadata.scala:25:15]
wire [1:0] _state_r_T_78 = 2'h1; // @[Metadata.scala:25:15]
wire _io_req_sec_rdy_T; // @[mshrs.scala:159:37]
wire _io_idx_valid_T; // @[mshrs.scala:149:25]
wire [3:0] req_idx; // @[mshrs.scala:110:25]
wire _io_way_valid_T_3; // @[mshrs.scala:151:19]
wire _io_tag_valid_T; // @[mshrs.scala:150:25]
wire [23:0] req_tag; // @[mshrs.scala:111:26]
wire [2:0] io_mem_acquire_bits_a_param; // @[Edges.scala:346:17]
wire [31:0] io_mem_acquire_bits_a_address; // @[Edges.scala:346:17]
wire [2:0] grantack_bits_e_sink = io_mem_grant_bits_sink_0; // @[Edges.scala:451:17]
wire [63:0] io_lb_write_bits_data_0 = io_mem_grant_bits_data_0; // @[mshrs.scala:36:7]
wire [2:0] shrink_param; // @[Misc.scala:38:36]
wire [1:0] coh_on_grant_state; // @[Metadata.scala:160:20]
wire [63:0] io_refill_bits_data_0 = io_lb_resp_0; // @[mshrs.scala:36:7]
wire [63:0] data_word = io_lb_resp_0; // @[mshrs.scala:36:7, :264:26]
wire [33:0] _io_replay_bits_addr_T_1; // @[mshrs.scala:353:31]
wire [63:0] _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16]
wire _io_probe_rdy_T_11; // @[mshrs.scala:148:42]
wire io_idx_valid_0; // @[mshrs.scala:36:7]
wire [3:0] io_idx_bits_0; // @[mshrs.scala:36:7]
wire io_way_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_way_bits_0; // @[mshrs.scala:36:7]
wire io_tag_valid_0; // @[mshrs.scala:36:7]
wire [23:0] io_tag_bits_0; // @[mshrs.scala:36:7]
wire [2:0] io_mem_acquire_bits_param_0; // @[mshrs.scala:36:7]
wire [31:0] io_mem_acquire_bits_address_0; // @[mshrs.scala:36:7]
wire io_mem_acquire_valid_0; // @[mshrs.scala:36:7]
wire io_mem_grant_ready_0; // @[mshrs.scala:36:7]
wire [2:0] io_mem_finish_bits_sink_0; // @[mshrs.scala:36:7]
wire io_mem_finish_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_refill_bits_way_en_0; // @[mshrs.scala:36:7]
wire [9:0] io_refill_bits_addr_0; // @[mshrs.scala:36:7]
wire io_refill_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_meta_write_bits_data_coh_state_0; // @[mshrs.scala:36:7]
wire [21:0] io_meta_write_bits_data_tag_0; // @[mshrs.scala:36:7]
wire [3:0] io_meta_write_bits_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_meta_write_bits_way_en_0; // @[mshrs.scala:36:7]
wire io_meta_write_valid_0; // @[mshrs.scala:36:7]
wire [3:0] io_meta_read_bits_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_meta_read_bits_way_en_0; // @[mshrs.scala:36:7]
wire [21:0] io_meta_read_bits_tag_0; // @[mshrs.scala:36:7]
wire io_meta_read_valid_0; // @[mshrs.scala:36:7]
wire [21:0] io_wb_req_bits_tag_0; // @[mshrs.scala:36:7]
wire [3:0] io_wb_req_bits_idx_0; // @[mshrs.scala:36:7]
wire [2:0] io_wb_req_bits_param_0; // @[mshrs.scala:36:7]
wire [1:0] io_wb_req_bits_way_en_0; // @[mshrs.scala:36:7]
wire io_wb_req_valid_0; // @[mshrs.scala:36:7]
wire [1:0] io_commit_coh_state_0; // @[mshrs.scala:36:7]
wire [2:0] io_lb_read_bits_offset_0; // @[mshrs.scala:36:7]
wire io_lb_read_valid_0; // @[mshrs.scala:36:7]
wire [2:0] io_lb_write_bits_offset_0; // @[mshrs.scala:36:7]
wire io_lb_write_valid_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_uopc_0; // @[mshrs.scala:36:7]
wire [31:0] io_replay_bits_uop_inst_0; // @[mshrs.scala:36:7]
wire [31:0] io_replay_bits_uop_debug_inst_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_rvc_0; // @[mshrs.scala:36:7]
wire [33:0] io_replay_bits_uop_debug_pc_0; // @[mshrs.scala:36:7]
wire [2:0] io_replay_bits_uop_iq_type_0; // @[mshrs.scala:36:7]
wire [9:0] io_replay_bits_uop_fu_code_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_iw_state_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_br_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_jalr_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_jal_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_sfb_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_br_mask_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_br_tag_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_edge_inst_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_pc_lob_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_taken_0; // @[mshrs.scala:36:7]
wire [19:0] io_replay_bits_uop_imm_packed_0; // @[mshrs.scala:36:7]
wire [11:0] io_replay_bits_uop_csr_addr_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_rob_idx_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_stq_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_pdst_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_prs1_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_prs2_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_prs3_0; // @[mshrs.scala:36:7]
wire [3:0] io_replay_bits_uop_ppred_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7]
wire [6:0] io_replay_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_exception_0; // @[mshrs.scala:36:7]
wire [63:0] io_replay_bits_uop_exc_cause_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_bypassable_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_mem_size_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_mem_signed_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_fence_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_fencei_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_amo_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_uses_stq_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_is_unique_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_ldst_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_lrs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_lrs2_0; // @[mshrs.scala:36:7]
wire [5:0] io_replay_bits_uop_lrs3_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_ldst_val_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_frs3_en_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_val_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_fp_single_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7]
wire io_replay_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_old_meta_coh_state_0; // @[mshrs.scala:36:7]
wire [21:0] io_replay_bits_old_meta_tag_0; // @[mshrs.scala:36:7]
wire [33:0] io_replay_bits_addr_0; // @[mshrs.scala:36:7]
wire [63:0] io_replay_bits_data_0; // @[mshrs.scala:36:7]
wire io_replay_bits_is_hella_0; // @[mshrs.scala:36:7]
wire io_replay_bits_tag_match_0; // @[mshrs.scala:36:7]
wire [1:0] io_replay_bits_way_en_0; // @[mshrs.scala:36:7]
wire [4:0] io_replay_bits_sdq_id_0; // @[mshrs.scala:36:7]
wire io_replay_valid_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_ctrl_br_type_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_ctrl_op1_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_ctrl_op2_sel_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_ctrl_imm_sel_0; // @[mshrs.scala:36:7]
wire [4:0] io_resp_bits_uop_ctrl_op_fcn_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ctrl_fcn_dw_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_ctrl_csr_cmd_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ctrl_is_load_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ctrl_is_sta_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ctrl_is_std_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_uopc_0; // @[mshrs.scala:36:7]
wire [31:0] io_resp_bits_uop_inst_0; // @[mshrs.scala:36:7]
wire [31:0] io_resp_bits_uop_debug_inst_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_rvc_0; // @[mshrs.scala:36:7]
wire [33:0] io_resp_bits_uop_debug_pc_0; // @[mshrs.scala:36:7]
wire [2:0] io_resp_bits_uop_iq_type_0; // @[mshrs.scala:36:7]
wire [9:0] io_resp_bits_uop_fu_code_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_iw_state_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iw_p1_poisoned_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_iw_p2_poisoned_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_br_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_jalr_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_jal_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_sfb_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_br_mask_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_br_tag_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_ftq_idx_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_edge_inst_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_pc_lob_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_taken_0; // @[mshrs.scala:36:7]
wire [19:0] io_resp_bits_uop_imm_packed_0; // @[mshrs.scala:36:7]
wire [11:0] io_resp_bits_uop_csr_addr_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_rob_idx_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_ldq_idx_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_stq_idx_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_pdst_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_prs1_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_prs2_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_prs3_0; // @[mshrs.scala:36:7]
wire [3:0] io_resp_bits_uop_ppred_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_prs1_busy_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_prs2_busy_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_prs3_busy_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ppred_busy_0; // @[mshrs.scala:36:7]
wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_exception_0; // @[mshrs.scala:36:7]
wire [63:0] io_resp_bits_uop_exc_cause_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_bypassable_0; // @[mshrs.scala:36:7]
wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_mem_size_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_mem_signed_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_fence_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_fencei_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_amo_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_uses_ldq_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_uses_stq_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_sys_pc2epc_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_is_unique_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_flush_on_commit_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ldst_is_rs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_ldst_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_lrs1_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_lrs2_0; // @[mshrs.scala:36:7]
wire [5:0] io_resp_bits_uop_lrs3_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_ldst_val_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_frs3_en_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_val_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_fp_single_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_xcpt_pf_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_xcpt_ae_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_xcpt_ma_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_bp_debug_if_0; // @[mshrs.scala:36:7]
wire io_resp_bits_uop_bp_xcpt_if_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_debug_fsrc_0; // @[mshrs.scala:36:7]
wire [1:0] io_resp_bits_uop_debug_tsrc_0; // @[mshrs.scala:36:7]
wire [63:0] io_resp_bits_data_0; // @[mshrs.scala:36:7]
wire io_resp_bits_is_hella_0; // @[mshrs.scala:36:7]
wire io_resp_valid_0; // @[mshrs.scala:36:7]
wire io_req_pri_rdy_0; // @[mshrs.scala:36:7]
wire io_req_sec_rdy_0; // @[mshrs.scala:36:7]
wire io_commit_val_0; // @[mshrs.scala:36:7]
wire [33:0] io_commit_addr_0; // @[mshrs.scala:36:7]
wire io_probe_rdy_0; // @[mshrs.scala:36:7]
reg [4:0] state; // @[mshrs.scala:107:22]
reg [6:0] req_uop_uopc; // @[mshrs.scala:109:20]
reg [31:0] req_uop_inst; // @[mshrs.scala:109:20]
reg [31:0] req_uop_debug_inst; // @[mshrs.scala:109:20]
reg req_uop_is_rvc; // @[mshrs.scala:109:20]
reg [33:0] req_uop_debug_pc; // @[mshrs.scala:109:20]
reg [2:0] req_uop_iq_type; // @[mshrs.scala:109:20]
reg [9:0] req_uop_fu_code; // @[mshrs.scala:109:20]
reg [3:0] req_uop_ctrl_br_type; // @[mshrs.scala:109:20]
reg [1:0] req_uop_ctrl_op1_sel; // @[mshrs.scala:109:20]
reg [2:0] req_uop_ctrl_op2_sel; // @[mshrs.scala:109:20]
reg [2:0] req_uop_ctrl_imm_sel; // @[mshrs.scala:109:20]
reg [4:0] req_uop_ctrl_op_fcn; // @[mshrs.scala:109:20]
reg req_uop_ctrl_fcn_dw; // @[mshrs.scala:109:20]
reg [2:0] req_uop_ctrl_csr_cmd; // @[mshrs.scala:109:20]
reg req_uop_ctrl_is_load; // @[mshrs.scala:109:20]
reg req_uop_ctrl_is_sta; // @[mshrs.scala:109:20]
reg req_uop_ctrl_is_std; // @[mshrs.scala:109:20]
reg [1:0] req_uop_iw_state; // @[mshrs.scala:109:20]
reg req_uop_iw_p1_poisoned; // @[mshrs.scala:109:20]
reg req_uop_iw_p2_poisoned; // @[mshrs.scala:109:20]
reg req_uop_is_br; // @[mshrs.scala:109:20]
reg req_uop_is_jalr; // @[mshrs.scala:109:20]
reg req_uop_is_jal; // @[mshrs.scala:109:20]
reg req_uop_is_sfb; // @[mshrs.scala:109:20]
reg [3:0] req_uop_br_mask; // @[mshrs.scala:109:20]
reg [1:0] req_uop_br_tag; // @[mshrs.scala:109:20]
reg [3:0] req_uop_ftq_idx; // @[mshrs.scala:109:20]
reg req_uop_edge_inst; // @[mshrs.scala:109:20]
reg [5:0] req_uop_pc_lob; // @[mshrs.scala:109:20]
reg req_uop_taken; // @[mshrs.scala:109:20]
reg [19:0] req_uop_imm_packed; // @[mshrs.scala:109:20]
reg [11:0] req_uop_csr_addr; // @[mshrs.scala:109:20]
reg [5:0] req_uop_rob_idx; // @[mshrs.scala:109:20]
reg [3:0] req_uop_ldq_idx; // @[mshrs.scala:109:20]
reg [3:0] req_uop_stq_idx; // @[mshrs.scala:109:20]
reg [1:0] req_uop_rxq_idx; // @[mshrs.scala:109:20]
reg [6:0] req_uop_pdst; // @[mshrs.scala:109:20]
reg [6:0] req_uop_prs1; // @[mshrs.scala:109:20]
reg [6:0] req_uop_prs2; // @[mshrs.scala:109:20]
reg [6:0] req_uop_prs3; // @[mshrs.scala:109:20]
reg [3:0] req_uop_ppred; // @[mshrs.scala:109:20]
reg req_uop_prs1_busy; // @[mshrs.scala:109:20]
reg req_uop_prs2_busy; // @[mshrs.scala:109:20]
reg req_uop_prs3_busy; // @[mshrs.scala:109:20]
reg req_uop_ppred_busy; // @[mshrs.scala:109:20]
reg [6:0] req_uop_stale_pdst; // @[mshrs.scala:109:20]
reg req_uop_exception; // @[mshrs.scala:109:20]
reg [63:0] req_uop_exc_cause; // @[mshrs.scala:109:20]
reg req_uop_bypassable; // @[mshrs.scala:109:20]
reg [4:0] req_uop_mem_cmd; // @[mshrs.scala:109:20]
reg [1:0] req_uop_mem_size; // @[mshrs.scala:109:20]
reg req_uop_mem_signed; // @[mshrs.scala:109:20]
reg req_uop_is_fence; // @[mshrs.scala:109:20]
reg req_uop_is_fencei; // @[mshrs.scala:109:20]
reg req_uop_is_amo; // @[mshrs.scala:109:20]
reg req_uop_uses_ldq; // @[mshrs.scala:109:20]
reg req_uop_uses_stq; // @[mshrs.scala:109:20]
reg req_uop_is_sys_pc2epc; // @[mshrs.scala:109:20]
reg req_uop_is_unique; // @[mshrs.scala:109:20]
reg req_uop_flush_on_commit; // @[mshrs.scala:109:20]
reg req_uop_ldst_is_rs1; // @[mshrs.scala:109:20]
reg [5:0] req_uop_ldst; // @[mshrs.scala:109:20]
reg [5:0] req_uop_lrs1; // @[mshrs.scala:109:20]
reg [5:0] req_uop_lrs2; // @[mshrs.scala:109:20]
reg [5:0] req_uop_lrs3; // @[mshrs.scala:109:20]
reg req_uop_ldst_val; // @[mshrs.scala:109:20]
reg [1:0] req_uop_dst_rtype; // @[mshrs.scala:109:20]
reg [1:0] req_uop_lrs1_rtype; // @[mshrs.scala:109:20]
reg [1:0] req_uop_lrs2_rtype; // @[mshrs.scala:109:20]
reg req_uop_frs3_en; // @[mshrs.scala:109:20]
reg req_uop_fp_val; // @[mshrs.scala:109:20]
reg req_uop_fp_single; // @[mshrs.scala:109:20]
reg req_uop_xcpt_pf_if; // @[mshrs.scala:109:20]
reg req_uop_xcpt_ae_if; // @[mshrs.scala:109:20]
reg req_uop_xcpt_ma_if; // @[mshrs.scala:109:20]
reg req_uop_bp_debug_if; // @[mshrs.scala:109:20]
reg req_uop_bp_xcpt_if; // @[mshrs.scala:109:20]
reg [1:0] req_uop_debug_fsrc; // @[mshrs.scala:109:20]
reg [1:0] req_uop_debug_tsrc; // @[mshrs.scala:109:20]
reg [33:0] req_addr; // @[mshrs.scala:109:20]
assign io_commit_addr_0 = req_addr; // @[mshrs.scala:36:7, :109:20]
reg [63:0] req_data; // @[mshrs.scala:109:20]
reg req_is_hella; // @[mshrs.scala:109:20]
reg req_tag_match; // @[mshrs.scala:109:20]
reg [1:0] req_old_meta_coh_state; // @[mshrs.scala:109:20]
reg [21:0] req_old_meta_tag; // @[mshrs.scala:109:20]
assign io_wb_req_bits_tag_0 = req_old_meta_tag; // @[mshrs.scala:36:7, :109:20]
reg [1:0] req_way_en; // @[mshrs.scala:109:20]
assign io_way_bits_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_refill_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_meta_write_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_meta_read_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_wb_req_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
assign io_replay_bits_way_en_0 = req_way_en; // @[mshrs.scala:36:7, :109:20]
reg [4:0] req_sdq_id; // @[mshrs.scala:109:20]
assign req_idx = req_addr[9:6]; // @[mshrs.scala:109:20, :110:25]
assign io_idx_bits_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign io_meta_write_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign io_meta_read_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign io_wb_req_bits_idx_0 = req_idx; // @[mshrs.scala:36:7, :110:25]
assign req_tag = req_addr[33:10]; // @[mshrs.scala:109:20, :111:26]
assign io_tag_bits_0 = req_tag; // @[mshrs.scala:36:7, :111:26]
wire [27:0] _req_block_addr_T = req_addr[33:6]; // @[mshrs.scala:109:20, :112:34]
wire [33:0] req_block_addr = {_req_block_addr_T, 6'h0}; // @[mshrs.scala:112:{34,51}]
reg req_needs_wb; // @[mshrs.scala:113:29]
reg [1:0] new_coh_state; // @[mshrs.scala:115:24]
wire [3:0] _r_T_6 = {2'h2, req_old_meta_coh_state}; // @[Metadata.scala:120:19]
wire _r_T_19 = _r_T_6 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _r_T_21 = _r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _r_T_23 = _r_T_6 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _r_T_25 = _r_T_23 ? 3'h2 : _r_T_21; // @[Misc.scala:38:36, :56:20]
wire _r_T_27 = _r_T_6 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _r_T_29 = _r_T_27 ? 3'h1 : _r_T_25; // @[Misc.scala:38:36, :56:20]
wire _r_T_31 = _r_T_6 == 4'hB; // @[Misc.scala:56:20]
wire _r_T_32 = _r_T_31; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_33 = _r_T_31 ? 3'h1 : _r_T_29; // @[Misc.scala:38:36, :56:20]
wire _r_T_35 = _r_T_6 == 4'h4; // @[Misc.scala:56:20]
wire _r_T_36 = ~_r_T_35 & _r_T_32; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_37 = _r_T_35 ? 3'h5 : _r_T_33; // @[Misc.scala:38:36, :56:20]
wire _r_T_39 = _r_T_6 == 4'h5; // @[Misc.scala:56:20]
wire _r_T_40 = ~_r_T_39 & _r_T_36; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_41 = _r_T_39 ? 3'h4 : _r_T_37; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_42 = {1'h0, _r_T_39}; // @[Misc.scala:38:63, :56:20]
wire _r_T_43 = _r_T_6 == 4'h6; // @[Misc.scala:56:20]
wire _r_T_44 = ~_r_T_43 & _r_T_40; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_45 = _r_T_43 ? 3'h0 : _r_T_41; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_46 = _r_T_43 ? 2'h1 : _r_T_42; // @[Misc.scala:38:63, :56:20]
wire _r_T_47 = _r_T_6 == 4'h7; // @[Misc.scala:56:20]
wire _r_T_48 = _r_T_47 | _r_T_44; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_49 = _r_T_47 ? 3'h0 : _r_T_45; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_50 = _r_T_47 ? 2'h1 : _r_T_46; // @[Misc.scala:38:63, :56:20]
wire _r_T_51 = _r_T_6 == 4'h0; // @[Misc.scala:56:20]
wire _r_T_52 = ~_r_T_51 & _r_T_48; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_53 = _r_T_51 ? 3'h5 : _r_T_49; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_54 = _r_T_51 ? 2'h0 : _r_T_50; // @[Misc.scala:38:63, :56:20]
wire _r_T_55 = _r_T_6 == 4'h1; // @[Misc.scala:56:20]
wire _r_T_56 = ~_r_T_55 & _r_T_52; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_57 = _r_T_55 ? 3'h4 : _r_T_53; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_58 = _r_T_55 ? 2'h1 : _r_T_54; // @[Misc.scala:38:63, :56:20]
wire _r_T_59 = _r_T_6 == 4'h2; // @[Misc.scala:56:20]
wire _r_T_60 = ~_r_T_59 & _r_T_56; // @[Misc.scala:38:9, :56:20]
wire [2:0] _r_T_61 = _r_T_59 ? 3'h3 : _r_T_57; // @[Misc.scala:38:36, :56:20]
wire [1:0] _r_T_62 = _r_T_59 ? 2'h2 : _r_T_58; // @[Misc.scala:38:63, :56:20]
wire _r_T_63 = _r_T_6 == 4'h3; // @[Misc.scala:56:20]
wire r_1 = _r_T_63 | _r_T_60; // @[Misc.scala:38:9, :56:20]
assign shrink_param = _r_T_63 ? 3'h3 : _r_T_61; // @[Misc.scala:38:36, :56:20]
assign io_wb_req_bits_param_0 = shrink_param; // @[Misc.scala:38:36]
wire [1:0] r_3 = _r_T_63 ? 2'h2 : _r_T_62; // @[Misc.scala:38:63, :56:20]
wire [1:0] coh_on_clear_state = r_3; // @[Misc.scala:38:63]
wire _GEN = req_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _grow_param_r_c_cat_T; // @[Consts.scala:90:32]
assign _grow_param_r_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _grow_param_r_c_cat_T_23; // @[Consts.scala:90:32]
assign _grow_param_r_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _coh_on_grant_c_cat_T; // @[Consts.scala:90:32]
assign _coh_on_grant_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _coh_on_grant_c_cat_T_23; // @[Consts.scala:90:32]
assign _coh_on_grant_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _r1_c_cat_T; // @[Consts.scala:90:32]
assign _r1_c_cat_T = _GEN; // @[Consts.scala:90:32]
wire _r1_c_cat_T_23; // @[Consts.scala:90:32]
assign _r1_c_cat_T_23 = _GEN; // @[Consts.scala:90:32]
wire _needs_second_acq_T_27; // @[Consts.scala:90:32]
assign _needs_second_acq_T_27 = _GEN; // @[Consts.scala:90:32]
wire _GEN_0 = req_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _grow_param_r_c_cat_T_1; // @[Consts.scala:90:49]
assign _grow_param_r_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _grow_param_r_c_cat_T_24; // @[Consts.scala:90:49]
assign _grow_param_r_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:49]
assign _coh_on_grant_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:49]
assign _coh_on_grant_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _r1_c_cat_T_1; // @[Consts.scala:90:49]
assign _r1_c_cat_T_1 = _GEN_0; // @[Consts.scala:90:49]
wire _r1_c_cat_T_24; // @[Consts.scala:90:49]
assign _r1_c_cat_T_24 = _GEN_0; // @[Consts.scala:90:49]
wire _needs_second_acq_T_28; // @[Consts.scala:90:49]
assign _needs_second_acq_T_28 = _GEN_0; // @[Consts.scala:90:49]
wire _grow_param_r_c_cat_T_2 = _grow_param_r_c_cat_T | _grow_param_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _GEN_1 = req_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66]
wire _grow_param_r_c_cat_T_3; // @[Consts.scala:90:66]
assign _grow_param_r_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _grow_param_r_c_cat_T_26; // @[Consts.scala:90:66]
assign _grow_param_r_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:66]
assign _coh_on_grant_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:66]
assign _coh_on_grant_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _r1_c_cat_T_3; // @[Consts.scala:90:66]
assign _r1_c_cat_T_3 = _GEN_1; // @[Consts.scala:90:66]
wire _r1_c_cat_T_26; // @[Consts.scala:90:66]
assign _r1_c_cat_T_26 = _GEN_1; // @[Consts.scala:90:66]
wire _needs_second_acq_T_30; // @[Consts.scala:90:66]
assign _needs_second_acq_T_30 = _GEN_1; // @[Consts.scala:90:66]
wire _grow_param_r_c_cat_T_4 = _grow_param_r_c_cat_T_2 | _grow_param_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _GEN_2 = req_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_5; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_28; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_5; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_28; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _r1_c_cat_T_5; // @[package.scala:16:47]
assign _r1_c_cat_T_5 = _GEN_2; // @[package.scala:16:47]
wire _r1_c_cat_T_28; // @[package.scala:16:47]
assign _r1_c_cat_T_28 = _GEN_2; // @[package.scala:16:47]
wire _needs_second_acq_T_32; // @[package.scala:16:47]
assign _needs_second_acq_T_32 = _GEN_2; // @[package.scala:16:47]
wire _GEN_3 = req_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_6; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_29; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_6; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_29; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _r1_c_cat_T_6; // @[package.scala:16:47]
assign _r1_c_cat_T_6 = _GEN_3; // @[package.scala:16:47]
wire _r1_c_cat_T_29; // @[package.scala:16:47]
assign _r1_c_cat_T_29 = _GEN_3; // @[package.scala:16:47]
wire _needs_second_acq_T_33; // @[package.scala:16:47]
assign _needs_second_acq_T_33 = _GEN_3; // @[package.scala:16:47]
wire _GEN_4 = req_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_7; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_30; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_7; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_30; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _r1_c_cat_T_7; // @[package.scala:16:47]
assign _r1_c_cat_T_7 = _GEN_4; // @[package.scala:16:47]
wire _r1_c_cat_T_30; // @[package.scala:16:47]
assign _r1_c_cat_T_30 = _GEN_4; // @[package.scala:16:47]
wire _needs_second_acq_T_34; // @[package.scala:16:47]
assign _needs_second_acq_T_34 = _GEN_4; // @[package.scala:16:47]
wire _GEN_5 = req_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_8; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_31; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_8; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_31; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _r1_c_cat_T_8; // @[package.scala:16:47]
assign _r1_c_cat_T_8 = _GEN_5; // @[package.scala:16:47]
wire _r1_c_cat_T_31; // @[package.scala:16:47]
assign _r1_c_cat_T_31 = _GEN_5; // @[package.scala:16:47]
wire _needs_second_acq_T_35; // @[package.scala:16:47]
assign _needs_second_acq_T_35 = _GEN_5; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_9 = _grow_param_r_c_cat_T_5 | _grow_param_r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_10 = _grow_param_r_c_cat_T_9 | _grow_param_r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_11 = _grow_param_r_c_cat_T_10 | _grow_param_r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _GEN_6 = req_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_12; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_35; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_12; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_35; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _r1_c_cat_T_12; // @[package.scala:16:47]
assign _r1_c_cat_T_12 = _GEN_6; // @[package.scala:16:47]
wire _r1_c_cat_T_35; // @[package.scala:16:47]
assign _r1_c_cat_T_35 = _GEN_6; // @[package.scala:16:47]
wire _needs_second_acq_T_39; // @[package.scala:16:47]
assign _needs_second_acq_T_39 = _GEN_6; // @[package.scala:16:47]
wire _GEN_7 = req_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_13; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_36; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_13; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_36; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _r1_c_cat_T_13; // @[package.scala:16:47]
assign _r1_c_cat_T_13 = _GEN_7; // @[package.scala:16:47]
wire _r1_c_cat_T_36; // @[package.scala:16:47]
assign _r1_c_cat_T_36 = _GEN_7; // @[package.scala:16:47]
wire _needs_second_acq_T_40; // @[package.scala:16:47]
assign _needs_second_acq_T_40 = _GEN_7; // @[package.scala:16:47]
wire _GEN_8 = req_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_14; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_37; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_14; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_37; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _r1_c_cat_T_14; // @[package.scala:16:47]
assign _r1_c_cat_T_14 = _GEN_8; // @[package.scala:16:47]
wire _r1_c_cat_T_37; // @[package.scala:16:47]
assign _r1_c_cat_T_37 = _GEN_8; // @[package.scala:16:47]
wire _needs_second_acq_T_41; // @[package.scala:16:47]
assign _needs_second_acq_T_41 = _GEN_8; // @[package.scala:16:47]
wire _GEN_9 = req_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_15; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_38; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_15; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_38; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _r1_c_cat_T_15; // @[package.scala:16:47]
assign _r1_c_cat_T_15 = _GEN_9; // @[package.scala:16:47]
wire _r1_c_cat_T_38; // @[package.scala:16:47]
assign _r1_c_cat_T_38 = _GEN_9; // @[package.scala:16:47]
wire _needs_second_acq_T_42; // @[package.scala:16:47]
assign _needs_second_acq_T_42 = _GEN_9; // @[package.scala:16:47]
wire _GEN_10 = req_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_16; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_39; // @[package.scala:16:47]
assign _grow_param_r_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_16; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _coh_on_grant_c_cat_T_39; // @[package.scala:16:47]
assign _coh_on_grant_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _r1_c_cat_T_16; // @[package.scala:16:47]
assign _r1_c_cat_T_16 = _GEN_10; // @[package.scala:16:47]
wire _r1_c_cat_T_39; // @[package.scala:16:47]
assign _r1_c_cat_T_39 = _GEN_10; // @[package.scala:16:47]
wire _needs_second_acq_T_43; // @[package.scala:16:47]
assign _needs_second_acq_T_43 = _GEN_10; // @[package.scala:16:47]
wire _grow_param_r_c_cat_T_17 = _grow_param_r_c_cat_T_12 | _grow_param_r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_18 = _grow_param_r_c_cat_T_17 | _grow_param_r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_19 = _grow_param_r_c_cat_T_18 | _grow_param_r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_20 = _grow_param_r_c_cat_T_19 | _grow_param_r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_21 = _grow_param_r_c_cat_T_11 | _grow_param_r_c_cat_T_20; // @[package.scala:81:59]
wire _grow_param_r_c_cat_T_22 = _grow_param_r_c_cat_T_4 | _grow_param_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _grow_param_r_c_cat_T_25 = _grow_param_r_c_cat_T_23 | _grow_param_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _grow_param_r_c_cat_T_27 = _grow_param_r_c_cat_T_25 | _grow_param_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _grow_param_r_c_cat_T_32 = _grow_param_r_c_cat_T_28 | _grow_param_r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_33 = _grow_param_r_c_cat_T_32 | _grow_param_r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_34 = _grow_param_r_c_cat_T_33 | _grow_param_r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_40 = _grow_param_r_c_cat_T_35 | _grow_param_r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_41 = _grow_param_r_c_cat_T_40 | _grow_param_r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_42 = _grow_param_r_c_cat_T_41 | _grow_param_r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_43 = _grow_param_r_c_cat_T_42 | _grow_param_r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _grow_param_r_c_cat_T_44 = _grow_param_r_c_cat_T_34 | _grow_param_r_c_cat_T_43; // @[package.scala:81:59]
wire _grow_param_r_c_cat_T_45 = _grow_param_r_c_cat_T_27 | _grow_param_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _GEN_11 = req_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54]
wire _grow_param_r_c_cat_T_46; // @[Consts.scala:91:54]
assign _grow_param_r_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _coh_on_grant_c_cat_T_46; // @[Consts.scala:91:54]
assign _coh_on_grant_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _r1_c_cat_T_46; // @[Consts.scala:91:54]
assign _r1_c_cat_T_46 = _GEN_11; // @[Consts.scala:91:54]
wire _needs_second_acq_T_50; // @[Consts.scala:91:54]
assign _needs_second_acq_T_50 = _GEN_11; // @[Consts.scala:91:54]
wire _grow_param_r_c_cat_T_47 = _grow_param_r_c_cat_T_45 | _grow_param_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _GEN_12 = req_uop_mem_cmd == 5'h6; // @[Consts.scala:91:71]
wire _grow_param_r_c_cat_T_48; // @[Consts.scala:91:71]
assign _grow_param_r_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:71]
assign _coh_on_grant_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _r1_c_cat_T_48; // @[Consts.scala:91:71]
assign _r1_c_cat_T_48 = _GEN_12; // @[Consts.scala:91:71]
wire _needs_second_acq_T_52; // @[Consts.scala:91:71]
assign _needs_second_acq_T_52 = _GEN_12; // @[Consts.scala:91:71]
wire _grow_param_r_c_cat_T_49 = _grow_param_r_c_cat_T_47 | _grow_param_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] grow_param_r_c = {_grow_param_r_c_cat_T_22, _grow_param_r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _grow_param_r_T = {grow_param_r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _grow_param_r_T_25 = _grow_param_r_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_27 = {1'h0, _grow_param_r_T_25}; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_28 = _grow_param_r_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_30 = _grow_param_r_T_28 ? 2'h2 : _grow_param_r_T_27; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_31 = _grow_param_r_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_33 = _grow_param_r_T_31 ? 2'h1 : _grow_param_r_T_30; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_34 = _grow_param_r_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_36 = _grow_param_r_T_34 ? 2'h2 : _grow_param_r_T_33; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_37 = _grow_param_r_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _grow_param_r_T_39 = _grow_param_r_T_37 ? 2'h0 : _grow_param_r_T_36; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_40 = _grow_param_r_T == 4'hE; // @[Misc.scala:49:20]
wire _grow_param_r_T_41 = _grow_param_r_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_42 = _grow_param_r_T_40 ? 2'h3 : _grow_param_r_T_39; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_43 = &_grow_param_r_T; // @[Misc.scala:49:20]
wire _grow_param_r_T_44 = _grow_param_r_T_43 | _grow_param_r_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_45 = _grow_param_r_T_43 ? 2'h3 : _grow_param_r_T_42; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_46 = _grow_param_r_T == 4'h6; // @[Misc.scala:49:20]
wire _grow_param_r_T_47 = _grow_param_r_T_46 | _grow_param_r_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_48 = _grow_param_r_T_46 ? 2'h2 : _grow_param_r_T_45; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_49 = _grow_param_r_T == 4'h7; // @[Misc.scala:49:20]
wire _grow_param_r_T_50 = _grow_param_r_T_49 | _grow_param_r_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_51 = _grow_param_r_T_49 ? 2'h3 : _grow_param_r_T_48; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_52 = _grow_param_r_T == 4'h1; // @[Misc.scala:49:20]
wire _grow_param_r_T_53 = _grow_param_r_T_52 | _grow_param_r_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_54 = _grow_param_r_T_52 ? 2'h1 : _grow_param_r_T_51; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_55 = _grow_param_r_T == 4'h2; // @[Misc.scala:49:20]
wire _grow_param_r_T_56 = _grow_param_r_T_55 | _grow_param_r_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _grow_param_r_T_57 = _grow_param_r_T_55 ? 2'h2 : _grow_param_r_T_54; // @[Misc.scala:35:36, :49:20]
wire _grow_param_r_T_58 = _grow_param_r_T == 4'h3; // @[Misc.scala:49:20]
wire grow_param_r_1 = _grow_param_r_T_58 | _grow_param_r_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] grow_param = _grow_param_r_T_58 ? 2'h3 : _grow_param_r_T_57; // @[Misc.scala:35:36, :49:20]
wire [1:0] grow_param_meta_state = grow_param; // @[Misc.scala:35:36]
wire _coh_on_grant_c_cat_T_2 = _coh_on_grant_c_cat_T | _coh_on_grant_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _coh_on_grant_c_cat_T_4 = _coh_on_grant_c_cat_T_2 | _coh_on_grant_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _coh_on_grant_c_cat_T_9 = _coh_on_grant_c_cat_T_5 | _coh_on_grant_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_10 = _coh_on_grant_c_cat_T_9 | _coh_on_grant_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_11 = _coh_on_grant_c_cat_T_10 | _coh_on_grant_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_17 = _coh_on_grant_c_cat_T_12 | _coh_on_grant_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_18 = _coh_on_grant_c_cat_T_17 | _coh_on_grant_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_19 = _coh_on_grant_c_cat_T_18 | _coh_on_grant_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_20 = _coh_on_grant_c_cat_T_19 | _coh_on_grant_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_21 = _coh_on_grant_c_cat_T_11 | _coh_on_grant_c_cat_T_20; // @[package.scala:81:59]
wire _coh_on_grant_c_cat_T_22 = _coh_on_grant_c_cat_T_4 | _coh_on_grant_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _coh_on_grant_c_cat_T_25 = _coh_on_grant_c_cat_T_23 | _coh_on_grant_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _coh_on_grant_c_cat_T_27 = _coh_on_grant_c_cat_T_25 | _coh_on_grant_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _coh_on_grant_c_cat_T_32 = _coh_on_grant_c_cat_T_28 | _coh_on_grant_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_33 = _coh_on_grant_c_cat_T_32 | _coh_on_grant_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_34 = _coh_on_grant_c_cat_T_33 | _coh_on_grant_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_40 = _coh_on_grant_c_cat_T_35 | _coh_on_grant_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_41 = _coh_on_grant_c_cat_T_40 | _coh_on_grant_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_42 = _coh_on_grant_c_cat_T_41 | _coh_on_grant_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_43 = _coh_on_grant_c_cat_T_42 | _coh_on_grant_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _coh_on_grant_c_cat_T_44 = _coh_on_grant_c_cat_T_34 | _coh_on_grant_c_cat_T_43; // @[package.scala:81:59]
wire _coh_on_grant_c_cat_T_45 = _coh_on_grant_c_cat_T_27 | _coh_on_grant_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _coh_on_grant_c_cat_T_47 = _coh_on_grant_c_cat_T_45 | _coh_on_grant_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _coh_on_grant_c_cat_T_49 = _coh_on_grant_c_cat_T_47 | _coh_on_grant_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] coh_on_grant_c = {_coh_on_grant_c_cat_T_22, _coh_on_grant_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _coh_on_grant_T = {coh_on_grant_c, io_mem_grant_bits_param_0}; // @[Metadata.scala:29:18, :84:18]
wire _coh_on_grant_T_9 = _coh_on_grant_T == 4'h1; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_10 = {1'h0, _coh_on_grant_T_9}; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_11 = _coh_on_grant_T == 4'h0; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_12 = _coh_on_grant_T_11 ? 2'h2 : _coh_on_grant_T_10; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_13 = _coh_on_grant_T == 4'h4; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_14 = _coh_on_grant_T_13 ? 2'h2 : _coh_on_grant_T_12; // @[Metadata.scala:84:38]
wire _coh_on_grant_T_15 = _coh_on_grant_T == 4'hC; // @[Metadata.scala:84:{18,38}]
wire [1:0] _coh_on_grant_T_16 = _coh_on_grant_T_15 ? 2'h3 : _coh_on_grant_T_14; // @[Metadata.scala:84:38]
assign coh_on_grant_state = _coh_on_grant_T_16; // @[Metadata.scala:84:38, :160:20]
assign io_commit_coh_state_0 = coh_on_grant_state; // @[Metadata.scala:160:20]
wire _r1_c_cat_T_2 = _r1_c_cat_T | _r1_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _r1_c_cat_T_4 = _r1_c_cat_T_2 | _r1_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _r1_c_cat_T_9 = _r1_c_cat_T_5 | _r1_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_10 = _r1_c_cat_T_9 | _r1_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_11 = _r1_c_cat_T_10 | _r1_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_17 = _r1_c_cat_T_12 | _r1_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_18 = _r1_c_cat_T_17 | _r1_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_19 = _r1_c_cat_T_18 | _r1_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_20 = _r1_c_cat_T_19 | _r1_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_21 = _r1_c_cat_T_11 | _r1_c_cat_T_20; // @[package.scala:81:59]
wire _r1_c_cat_T_22 = _r1_c_cat_T_4 | _r1_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r1_c_cat_T_25 = _r1_c_cat_T_23 | _r1_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r1_c_cat_T_27 = _r1_c_cat_T_25 | _r1_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r1_c_cat_T_32 = _r1_c_cat_T_28 | _r1_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_33 = _r1_c_cat_T_32 | _r1_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_34 = _r1_c_cat_T_33 | _r1_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_40 = _r1_c_cat_T_35 | _r1_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_41 = _r1_c_cat_T_40 | _r1_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_42 = _r1_c_cat_T_41 | _r1_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_43 = _r1_c_cat_T_42 | _r1_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r1_c_cat_T_44 = _r1_c_cat_T_34 | _r1_c_cat_T_43; // @[package.scala:81:59]
wire _r1_c_cat_T_45 = _r1_c_cat_T_27 | _r1_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _r1_c_cat_T_47 = _r1_c_cat_T_45 | _r1_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _r1_c_cat_T_49 = _r1_c_cat_T_47 | _r1_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r1_c = {_r1_c_cat_T_22, _r1_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r1_T = {r1_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r1_T_25 = _r1_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r1_T_27 = {1'h0, _r1_T_25}; // @[Misc.scala:35:36, :49:20]
wire _r1_T_28 = _r1_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r1_T_30 = _r1_T_28 ? 2'h2 : _r1_T_27; // @[Misc.scala:35:36, :49:20]
wire _r1_T_31 = _r1_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r1_T_33 = _r1_T_31 ? 2'h1 : _r1_T_30; // @[Misc.scala:35:36, :49:20]
wire _r1_T_34 = _r1_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r1_T_36 = _r1_T_34 ? 2'h2 : _r1_T_33; // @[Misc.scala:35:36, :49:20]
wire _r1_T_37 = _r1_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r1_T_39 = _r1_T_37 ? 2'h0 : _r1_T_36; // @[Misc.scala:35:36, :49:20]
wire _r1_T_40 = _r1_T == 4'hE; // @[Misc.scala:49:20]
wire _r1_T_41 = _r1_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_42 = _r1_T_40 ? 2'h3 : _r1_T_39; // @[Misc.scala:35:36, :49:20]
wire _r1_T_43 = &_r1_T; // @[Misc.scala:49:20]
wire _r1_T_44 = _r1_T_43 | _r1_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_45 = _r1_T_43 ? 2'h3 : _r1_T_42; // @[Misc.scala:35:36, :49:20]
wire _r1_T_46 = _r1_T == 4'h6; // @[Misc.scala:49:20]
wire _r1_T_47 = _r1_T_46 | _r1_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_48 = _r1_T_46 ? 2'h2 : _r1_T_45; // @[Misc.scala:35:36, :49:20]
wire _r1_T_49 = _r1_T == 4'h7; // @[Misc.scala:49:20]
wire _r1_T_50 = _r1_T_49 | _r1_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_51 = _r1_T_49 ? 2'h3 : _r1_T_48; // @[Misc.scala:35:36, :49:20]
wire _r1_T_52 = _r1_T == 4'h1; // @[Misc.scala:49:20]
wire _r1_T_53 = _r1_T_52 | _r1_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_54 = _r1_T_52 ? 2'h1 : _r1_T_51; // @[Misc.scala:35:36, :49:20]
wire _r1_T_55 = _r1_T == 4'h2; // @[Misc.scala:49:20]
wire _r1_T_56 = _r1_T_55 | _r1_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r1_T_57 = _r1_T_55 ? 2'h2 : _r1_T_54; // @[Misc.scala:35:36, :49:20]
wire _r1_T_58 = _r1_T == 4'h3; // @[Misc.scala:49:20]
wire r1_1 = _r1_T_58 | _r1_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] r1_2 = _r1_T_58 ? 2'h3 : _r1_T_57; // @[Misc.scala:35:36, :49:20]
wire _GEN_13 = io_req_uop_mem_cmd_0 == 5'h1; // @[Consts.scala:90:32]
wire _r2_c_cat_T; // @[Consts.scala:90:32]
assign _r2_c_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _r2_c_cat_T_23; // @[Consts.scala:90:32]
assign _r2_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _needs_second_acq_T; // @[Consts.scala:90:32]
assign _needs_second_acq_T = _GEN_13; // @[Consts.scala:90:32]
wire _dirties_cat_T; // @[Consts.scala:90:32]
assign _dirties_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _dirties_cat_T_23; // @[Consts.scala:90:32]
assign _dirties_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T; // @[Consts.scala:90:32]
assign _state_r_c_cat_T = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T_23; // @[Consts.scala:90:32]
assign _state_r_c_cat_T_23 = _GEN_13; // @[Consts.scala:90:32]
wire _state_T_3; // @[Consts.scala:90:32]
assign _state_T_3 = _GEN_13; // @[Consts.scala:90:32]
wire _r_c_cat_T_50; // @[Consts.scala:90:32]
assign _r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32]
wire _r_c_cat_T_73; // @[Consts.scala:90:32]
assign _r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T_50; // @[Consts.scala:90:32]
assign _state_r_c_cat_T_50 = _GEN_13; // @[Consts.scala:90:32]
wire _state_r_c_cat_T_73; // @[Consts.scala:90:32]
assign _state_r_c_cat_T_73 = _GEN_13; // @[Consts.scala:90:32]
wire _state_T_37; // @[Consts.scala:90:32]
assign _state_T_37 = _GEN_13; // @[Consts.scala:90:32]
wire _GEN_14 = io_req_uop_mem_cmd_0 == 5'h11; // @[Consts.scala:90:49]
wire _r2_c_cat_T_1; // @[Consts.scala:90:49]
assign _r2_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _r2_c_cat_T_24; // @[Consts.scala:90:49]
assign _r2_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _needs_second_acq_T_1; // @[Consts.scala:90:49]
assign _needs_second_acq_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _dirties_cat_T_1; // @[Consts.scala:90:49]
assign _dirties_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _dirties_cat_T_24; // @[Consts.scala:90:49]
assign _dirties_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_1; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_1 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_24; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_24 = _GEN_14; // @[Consts.scala:90:49]
wire _state_T_4; // @[Consts.scala:90:49]
assign _state_T_4 = _GEN_14; // @[Consts.scala:90:49]
wire _r_c_cat_T_51; // @[Consts.scala:90:49]
assign _r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49]
wire _r_c_cat_T_74; // @[Consts.scala:90:49]
assign _r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_51; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_51 = _GEN_14; // @[Consts.scala:90:49]
wire _state_r_c_cat_T_74; // @[Consts.scala:90:49]
assign _state_r_c_cat_T_74 = _GEN_14; // @[Consts.scala:90:49]
wire _state_T_38; // @[Consts.scala:90:49]
assign _state_T_38 = _GEN_14; // @[Consts.scala:90:49]
wire _r2_c_cat_T_2 = _r2_c_cat_T | _r2_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _GEN_15 = io_req_uop_mem_cmd_0 == 5'h7; // @[Consts.scala:90:66]
wire _r2_c_cat_T_3; // @[Consts.scala:90:66]
assign _r2_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _r2_c_cat_T_26; // @[Consts.scala:90:66]
assign _r2_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _needs_second_acq_T_3; // @[Consts.scala:90:66]
assign _needs_second_acq_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _dirties_cat_T_3; // @[Consts.scala:90:66]
assign _dirties_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _dirties_cat_T_26; // @[Consts.scala:90:66]
assign _dirties_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_3; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_3 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_26; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_26 = _GEN_15; // @[Consts.scala:90:66]
wire _state_T_6; // @[Consts.scala:90:66]
assign _state_T_6 = _GEN_15; // @[Consts.scala:90:66]
wire _r_c_cat_T_53; // @[Consts.scala:90:66]
assign _r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66]
wire _r_c_cat_T_76; // @[Consts.scala:90:66]
assign _r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_53; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_53 = _GEN_15; // @[Consts.scala:90:66]
wire _state_r_c_cat_T_76; // @[Consts.scala:90:66]
assign _state_r_c_cat_T_76 = _GEN_15; // @[Consts.scala:90:66]
wire _state_T_40; // @[Consts.scala:90:66]
assign _state_T_40 = _GEN_15; // @[Consts.scala:90:66]
wire _r2_c_cat_T_4 = _r2_c_cat_T_2 | _r2_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _GEN_16 = io_req_uop_mem_cmd_0 == 5'h4; // @[package.scala:16:47]
wire _r2_c_cat_T_5; // @[package.scala:16:47]
assign _r2_c_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _r2_c_cat_T_28; // @[package.scala:16:47]
assign _r2_c_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _needs_second_acq_T_5; // @[package.scala:16:47]
assign _needs_second_acq_T_5 = _GEN_16; // @[package.scala:16:47]
wire _dirties_cat_T_5; // @[package.scala:16:47]
assign _dirties_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _dirties_cat_T_28; // @[package.scala:16:47]
assign _dirties_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_5; // @[package.scala:16:47]
assign _state_r_c_cat_T_5 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_28; // @[package.scala:16:47]
assign _state_r_c_cat_T_28 = _GEN_16; // @[package.scala:16:47]
wire _state_T_8; // @[package.scala:16:47]
assign _state_T_8 = _GEN_16; // @[package.scala:16:47]
wire _r_c_cat_T_55; // @[package.scala:16:47]
assign _r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47]
wire _r_c_cat_T_78; // @[package.scala:16:47]
assign _r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_55; // @[package.scala:16:47]
assign _state_r_c_cat_T_55 = _GEN_16; // @[package.scala:16:47]
wire _state_r_c_cat_T_78; // @[package.scala:16:47]
assign _state_r_c_cat_T_78 = _GEN_16; // @[package.scala:16:47]
wire _state_T_42; // @[package.scala:16:47]
assign _state_T_42 = _GEN_16; // @[package.scala:16:47]
wire _GEN_17 = io_req_uop_mem_cmd_0 == 5'h9; // @[package.scala:16:47]
wire _r2_c_cat_T_6; // @[package.scala:16:47]
assign _r2_c_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _r2_c_cat_T_29; // @[package.scala:16:47]
assign _r2_c_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _needs_second_acq_T_6; // @[package.scala:16:47]
assign _needs_second_acq_T_6 = _GEN_17; // @[package.scala:16:47]
wire _dirties_cat_T_6; // @[package.scala:16:47]
assign _dirties_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _dirties_cat_T_29; // @[package.scala:16:47]
assign _dirties_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_6; // @[package.scala:16:47]
assign _state_r_c_cat_T_6 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_29; // @[package.scala:16:47]
assign _state_r_c_cat_T_29 = _GEN_17; // @[package.scala:16:47]
wire _state_T_9; // @[package.scala:16:47]
assign _state_T_9 = _GEN_17; // @[package.scala:16:47]
wire _r_c_cat_T_56; // @[package.scala:16:47]
assign _r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47]
wire _r_c_cat_T_79; // @[package.scala:16:47]
assign _r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_56; // @[package.scala:16:47]
assign _state_r_c_cat_T_56 = _GEN_17; // @[package.scala:16:47]
wire _state_r_c_cat_T_79; // @[package.scala:16:47]
assign _state_r_c_cat_T_79 = _GEN_17; // @[package.scala:16:47]
wire _state_T_43; // @[package.scala:16:47]
assign _state_T_43 = _GEN_17; // @[package.scala:16:47]
wire _GEN_18 = io_req_uop_mem_cmd_0 == 5'hA; // @[package.scala:16:47]
wire _r2_c_cat_T_7; // @[package.scala:16:47]
assign _r2_c_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _r2_c_cat_T_30; // @[package.scala:16:47]
assign _r2_c_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _needs_second_acq_T_7; // @[package.scala:16:47]
assign _needs_second_acq_T_7 = _GEN_18; // @[package.scala:16:47]
wire _dirties_cat_T_7; // @[package.scala:16:47]
assign _dirties_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _dirties_cat_T_30; // @[package.scala:16:47]
assign _dirties_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_7; // @[package.scala:16:47]
assign _state_r_c_cat_T_7 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_30; // @[package.scala:16:47]
assign _state_r_c_cat_T_30 = _GEN_18; // @[package.scala:16:47]
wire _state_T_10; // @[package.scala:16:47]
assign _state_T_10 = _GEN_18; // @[package.scala:16:47]
wire _r_c_cat_T_57; // @[package.scala:16:47]
assign _r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47]
wire _r_c_cat_T_80; // @[package.scala:16:47]
assign _r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_57; // @[package.scala:16:47]
assign _state_r_c_cat_T_57 = _GEN_18; // @[package.scala:16:47]
wire _state_r_c_cat_T_80; // @[package.scala:16:47]
assign _state_r_c_cat_T_80 = _GEN_18; // @[package.scala:16:47]
wire _state_T_44; // @[package.scala:16:47]
assign _state_T_44 = _GEN_18; // @[package.scala:16:47]
wire _GEN_19 = io_req_uop_mem_cmd_0 == 5'hB; // @[package.scala:16:47]
wire _r2_c_cat_T_8; // @[package.scala:16:47]
assign _r2_c_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _r2_c_cat_T_31; // @[package.scala:16:47]
assign _r2_c_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _needs_second_acq_T_8; // @[package.scala:16:47]
assign _needs_second_acq_T_8 = _GEN_19; // @[package.scala:16:47]
wire _dirties_cat_T_8; // @[package.scala:16:47]
assign _dirties_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _dirties_cat_T_31; // @[package.scala:16:47]
assign _dirties_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_8; // @[package.scala:16:47]
assign _state_r_c_cat_T_8 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_31; // @[package.scala:16:47]
assign _state_r_c_cat_T_31 = _GEN_19; // @[package.scala:16:47]
wire _state_T_11; // @[package.scala:16:47]
assign _state_T_11 = _GEN_19; // @[package.scala:16:47]
wire _r_c_cat_T_58; // @[package.scala:16:47]
assign _r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47]
wire _r_c_cat_T_81; // @[package.scala:16:47]
assign _r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_58; // @[package.scala:16:47]
assign _state_r_c_cat_T_58 = _GEN_19; // @[package.scala:16:47]
wire _state_r_c_cat_T_81; // @[package.scala:16:47]
assign _state_r_c_cat_T_81 = _GEN_19; // @[package.scala:16:47]
wire _state_T_45; // @[package.scala:16:47]
assign _state_T_45 = _GEN_19; // @[package.scala:16:47]
wire _r2_c_cat_T_9 = _r2_c_cat_T_5 | _r2_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_10 = _r2_c_cat_T_9 | _r2_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_11 = _r2_c_cat_T_10 | _r2_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _GEN_20 = io_req_uop_mem_cmd_0 == 5'h8; // @[package.scala:16:47]
wire _r2_c_cat_T_12; // @[package.scala:16:47]
assign _r2_c_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _r2_c_cat_T_35; // @[package.scala:16:47]
assign _r2_c_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _needs_second_acq_T_12; // @[package.scala:16:47]
assign _needs_second_acq_T_12 = _GEN_20; // @[package.scala:16:47]
wire _dirties_cat_T_12; // @[package.scala:16:47]
assign _dirties_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _dirties_cat_T_35; // @[package.scala:16:47]
assign _dirties_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_12; // @[package.scala:16:47]
assign _state_r_c_cat_T_12 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_35; // @[package.scala:16:47]
assign _state_r_c_cat_T_35 = _GEN_20; // @[package.scala:16:47]
wire _state_T_15; // @[package.scala:16:47]
assign _state_T_15 = _GEN_20; // @[package.scala:16:47]
wire _r_c_cat_T_62; // @[package.scala:16:47]
assign _r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47]
wire _r_c_cat_T_85; // @[package.scala:16:47]
assign _r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_62; // @[package.scala:16:47]
assign _state_r_c_cat_T_62 = _GEN_20; // @[package.scala:16:47]
wire _state_r_c_cat_T_85; // @[package.scala:16:47]
assign _state_r_c_cat_T_85 = _GEN_20; // @[package.scala:16:47]
wire _state_T_49; // @[package.scala:16:47]
assign _state_T_49 = _GEN_20; // @[package.scala:16:47]
wire _GEN_21 = io_req_uop_mem_cmd_0 == 5'hC; // @[package.scala:16:47]
wire _r2_c_cat_T_13; // @[package.scala:16:47]
assign _r2_c_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _r2_c_cat_T_36; // @[package.scala:16:47]
assign _r2_c_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _needs_second_acq_T_13; // @[package.scala:16:47]
assign _needs_second_acq_T_13 = _GEN_21; // @[package.scala:16:47]
wire _dirties_cat_T_13; // @[package.scala:16:47]
assign _dirties_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _dirties_cat_T_36; // @[package.scala:16:47]
assign _dirties_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_13; // @[package.scala:16:47]
assign _state_r_c_cat_T_13 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_36; // @[package.scala:16:47]
assign _state_r_c_cat_T_36 = _GEN_21; // @[package.scala:16:47]
wire _state_T_16; // @[package.scala:16:47]
assign _state_T_16 = _GEN_21; // @[package.scala:16:47]
wire _r_c_cat_T_63; // @[package.scala:16:47]
assign _r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47]
wire _r_c_cat_T_86; // @[package.scala:16:47]
assign _r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_63; // @[package.scala:16:47]
assign _state_r_c_cat_T_63 = _GEN_21; // @[package.scala:16:47]
wire _state_r_c_cat_T_86; // @[package.scala:16:47]
assign _state_r_c_cat_T_86 = _GEN_21; // @[package.scala:16:47]
wire _state_T_50; // @[package.scala:16:47]
assign _state_T_50 = _GEN_21; // @[package.scala:16:47]
wire _GEN_22 = io_req_uop_mem_cmd_0 == 5'hD; // @[package.scala:16:47]
wire _r2_c_cat_T_14; // @[package.scala:16:47]
assign _r2_c_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _r2_c_cat_T_37; // @[package.scala:16:47]
assign _r2_c_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _needs_second_acq_T_14; // @[package.scala:16:47]
assign _needs_second_acq_T_14 = _GEN_22; // @[package.scala:16:47]
wire _dirties_cat_T_14; // @[package.scala:16:47]
assign _dirties_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _dirties_cat_T_37; // @[package.scala:16:47]
assign _dirties_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_14; // @[package.scala:16:47]
assign _state_r_c_cat_T_14 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_37; // @[package.scala:16:47]
assign _state_r_c_cat_T_37 = _GEN_22; // @[package.scala:16:47]
wire _state_T_17; // @[package.scala:16:47]
assign _state_T_17 = _GEN_22; // @[package.scala:16:47]
wire _r_c_cat_T_64; // @[package.scala:16:47]
assign _r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47]
wire _r_c_cat_T_87; // @[package.scala:16:47]
assign _r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_64; // @[package.scala:16:47]
assign _state_r_c_cat_T_64 = _GEN_22; // @[package.scala:16:47]
wire _state_r_c_cat_T_87; // @[package.scala:16:47]
assign _state_r_c_cat_T_87 = _GEN_22; // @[package.scala:16:47]
wire _state_T_51; // @[package.scala:16:47]
assign _state_T_51 = _GEN_22; // @[package.scala:16:47]
wire _GEN_23 = io_req_uop_mem_cmd_0 == 5'hE; // @[package.scala:16:47]
wire _r2_c_cat_T_15; // @[package.scala:16:47]
assign _r2_c_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _r2_c_cat_T_38; // @[package.scala:16:47]
assign _r2_c_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _needs_second_acq_T_15; // @[package.scala:16:47]
assign _needs_second_acq_T_15 = _GEN_23; // @[package.scala:16:47]
wire _dirties_cat_T_15; // @[package.scala:16:47]
assign _dirties_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _dirties_cat_T_38; // @[package.scala:16:47]
assign _dirties_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_15; // @[package.scala:16:47]
assign _state_r_c_cat_T_15 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_38; // @[package.scala:16:47]
assign _state_r_c_cat_T_38 = _GEN_23; // @[package.scala:16:47]
wire _state_T_18; // @[package.scala:16:47]
assign _state_T_18 = _GEN_23; // @[package.scala:16:47]
wire _r_c_cat_T_65; // @[package.scala:16:47]
assign _r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47]
wire _r_c_cat_T_88; // @[package.scala:16:47]
assign _r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_65; // @[package.scala:16:47]
assign _state_r_c_cat_T_65 = _GEN_23; // @[package.scala:16:47]
wire _state_r_c_cat_T_88; // @[package.scala:16:47]
assign _state_r_c_cat_T_88 = _GEN_23; // @[package.scala:16:47]
wire _state_T_52; // @[package.scala:16:47]
assign _state_T_52 = _GEN_23; // @[package.scala:16:47]
wire _GEN_24 = io_req_uop_mem_cmd_0 == 5'hF; // @[package.scala:16:47]
wire _r2_c_cat_T_16; // @[package.scala:16:47]
assign _r2_c_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _r2_c_cat_T_39; // @[package.scala:16:47]
assign _r2_c_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _needs_second_acq_T_16; // @[package.scala:16:47]
assign _needs_second_acq_T_16 = _GEN_24; // @[package.scala:16:47]
wire _dirties_cat_T_16; // @[package.scala:16:47]
assign _dirties_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _dirties_cat_T_39; // @[package.scala:16:47]
assign _dirties_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_16; // @[package.scala:16:47]
assign _state_r_c_cat_T_16 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_39; // @[package.scala:16:47]
assign _state_r_c_cat_T_39 = _GEN_24; // @[package.scala:16:47]
wire _state_T_19; // @[package.scala:16:47]
assign _state_T_19 = _GEN_24; // @[package.scala:16:47]
wire _r_c_cat_T_66; // @[package.scala:16:47]
assign _r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47]
wire _r_c_cat_T_89; // @[package.scala:16:47]
assign _r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_66; // @[package.scala:16:47]
assign _state_r_c_cat_T_66 = _GEN_24; // @[package.scala:16:47]
wire _state_r_c_cat_T_89; // @[package.scala:16:47]
assign _state_r_c_cat_T_89 = _GEN_24; // @[package.scala:16:47]
wire _state_T_53; // @[package.scala:16:47]
assign _state_T_53 = _GEN_24; // @[package.scala:16:47]
wire _r2_c_cat_T_17 = _r2_c_cat_T_12 | _r2_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_18 = _r2_c_cat_T_17 | _r2_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_19 = _r2_c_cat_T_18 | _r2_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_20 = _r2_c_cat_T_19 | _r2_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_21 = _r2_c_cat_T_11 | _r2_c_cat_T_20; // @[package.scala:81:59]
wire _r2_c_cat_T_22 = _r2_c_cat_T_4 | _r2_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r2_c_cat_T_25 = _r2_c_cat_T_23 | _r2_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r2_c_cat_T_27 = _r2_c_cat_T_25 | _r2_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r2_c_cat_T_32 = _r2_c_cat_T_28 | _r2_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_33 = _r2_c_cat_T_32 | _r2_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_34 = _r2_c_cat_T_33 | _r2_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_40 = _r2_c_cat_T_35 | _r2_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_41 = _r2_c_cat_T_40 | _r2_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_42 = _r2_c_cat_T_41 | _r2_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_43 = _r2_c_cat_T_42 | _r2_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r2_c_cat_T_44 = _r2_c_cat_T_34 | _r2_c_cat_T_43; // @[package.scala:81:59]
wire _r2_c_cat_T_45 = _r2_c_cat_T_27 | _r2_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _GEN_25 = io_req_uop_mem_cmd_0 == 5'h3; // @[Consts.scala:91:54]
wire _r2_c_cat_T_46; // @[Consts.scala:91:54]
assign _r2_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _needs_second_acq_T_23; // @[Consts.scala:91:54]
assign _needs_second_acq_T_23 = _GEN_25; // @[Consts.scala:91:54]
wire _dirties_cat_T_46; // @[Consts.scala:91:54]
assign _dirties_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _rpq_io_enq_valid_T_4; // @[Consts.scala:88:52]
assign _rpq_io_enq_valid_T_4 = _GEN_25; // @[Consts.scala:88:52, :91:54]
wire _state_r_c_cat_T_46; // @[Consts.scala:91:54]
assign _state_r_c_cat_T_46 = _GEN_25; // @[Consts.scala:91:54]
wire _r_c_cat_T_96; // @[Consts.scala:91:54]
assign _r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54]
wire _state_r_c_cat_T_96; // @[Consts.scala:91:54]
assign _state_r_c_cat_T_96 = _GEN_25; // @[Consts.scala:91:54]
wire _r2_c_cat_T_47 = _r2_c_cat_T_45 | _r2_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _GEN_26 = io_req_uop_mem_cmd_0 == 5'h6; // @[Consts.scala:91:71]
wire _r2_c_cat_T_48; // @[Consts.scala:91:71]
assign _r2_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _needs_second_acq_T_25; // @[Consts.scala:91:71]
assign _needs_second_acq_T_25 = _GEN_26; // @[Consts.scala:91:71]
wire _dirties_cat_T_48; // @[Consts.scala:91:71]
assign _dirties_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _state_r_c_cat_T_48; // @[Consts.scala:91:71]
assign _state_r_c_cat_T_48 = _GEN_26; // @[Consts.scala:91:71]
wire _r_c_cat_T_98; // @[Consts.scala:91:71]
assign _r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71]
wire _state_r_c_cat_T_98; // @[Consts.scala:91:71]
assign _state_r_c_cat_T_98 = _GEN_26; // @[Consts.scala:91:71]
wire _r2_c_cat_T_49 = _r2_c_cat_T_47 | _r2_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r2_c = {_r2_c_cat_T_22, _r2_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r2_T = {r2_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r2_T_25 = _r2_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r2_T_27 = {1'h0, _r2_T_25}; // @[Misc.scala:35:36, :49:20]
wire _r2_T_28 = _r2_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r2_T_30 = _r2_T_28 ? 2'h2 : _r2_T_27; // @[Misc.scala:35:36, :49:20]
wire _r2_T_31 = _r2_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r2_T_33 = _r2_T_31 ? 2'h1 : _r2_T_30; // @[Misc.scala:35:36, :49:20]
wire _r2_T_34 = _r2_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r2_T_36 = _r2_T_34 ? 2'h2 : _r2_T_33; // @[Misc.scala:35:36, :49:20]
wire _r2_T_37 = _r2_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r2_T_39 = _r2_T_37 ? 2'h0 : _r2_T_36; // @[Misc.scala:35:36, :49:20]
wire _r2_T_40 = _r2_T == 4'hE; // @[Misc.scala:49:20]
wire _r2_T_41 = _r2_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_42 = _r2_T_40 ? 2'h3 : _r2_T_39; // @[Misc.scala:35:36, :49:20]
wire _r2_T_43 = &_r2_T; // @[Misc.scala:49:20]
wire _r2_T_44 = _r2_T_43 | _r2_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_45 = _r2_T_43 ? 2'h3 : _r2_T_42; // @[Misc.scala:35:36, :49:20]
wire _r2_T_46 = _r2_T == 4'h6; // @[Misc.scala:49:20]
wire _r2_T_47 = _r2_T_46 | _r2_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_48 = _r2_T_46 ? 2'h2 : _r2_T_45; // @[Misc.scala:35:36, :49:20]
wire _r2_T_49 = _r2_T == 4'h7; // @[Misc.scala:49:20]
wire _r2_T_50 = _r2_T_49 | _r2_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_51 = _r2_T_49 ? 2'h3 : _r2_T_48; // @[Misc.scala:35:36, :49:20]
wire _r2_T_52 = _r2_T == 4'h1; // @[Misc.scala:49:20]
wire _r2_T_53 = _r2_T_52 | _r2_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_54 = _r2_T_52 ? 2'h1 : _r2_T_51; // @[Misc.scala:35:36, :49:20]
wire _r2_T_55 = _r2_T == 4'h2; // @[Misc.scala:49:20]
wire _r2_T_56 = _r2_T_55 | _r2_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r2_T_57 = _r2_T_55 ? 2'h2 : _r2_T_54; // @[Misc.scala:35:36, :49:20]
wire _r2_T_58 = _r2_T == 4'h3; // @[Misc.scala:49:20]
wire r2_1 = _r2_T_58 | _r2_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] r2_2 = _r2_T_58 ? 2'h3 : _r2_T_57; // @[Misc.scala:35:36, :49:20]
wire _needs_second_acq_T_2 = _needs_second_acq_T | _needs_second_acq_T_1; // @[Consts.scala:90:{32,42,49}]
wire _needs_second_acq_T_4 = _needs_second_acq_T_2 | _needs_second_acq_T_3; // @[Consts.scala:90:{42,59,66}]
wire _needs_second_acq_T_9 = _needs_second_acq_T_5 | _needs_second_acq_T_6; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_10 = _needs_second_acq_T_9 | _needs_second_acq_T_7; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_11 = _needs_second_acq_T_10 | _needs_second_acq_T_8; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_17 = _needs_second_acq_T_12 | _needs_second_acq_T_13; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_18 = _needs_second_acq_T_17 | _needs_second_acq_T_14; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_19 = _needs_second_acq_T_18 | _needs_second_acq_T_15; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_20 = _needs_second_acq_T_19 | _needs_second_acq_T_16; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_21 = _needs_second_acq_T_11 | _needs_second_acq_T_20; // @[package.scala:81:59]
wire _needs_second_acq_T_22 = _needs_second_acq_T_4 | _needs_second_acq_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _needs_second_acq_T_24 = _needs_second_acq_T_22 | _needs_second_acq_T_23; // @[Consts.scala:90:76, :91:{47,54}]
wire _needs_second_acq_T_26 = _needs_second_acq_T_24 | _needs_second_acq_T_25; // @[Consts.scala:91:{47,64,71}]
wire _needs_second_acq_T_29 = _needs_second_acq_T_27 | _needs_second_acq_T_28; // @[Consts.scala:90:{32,42,49}]
wire _needs_second_acq_T_31 = _needs_second_acq_T_29 | _needs_second_acq_T_30; // @[Consts.scala:90:{42,59,66}]
wire _needs_second_acq_T_36 = _needs_second_acq_T_32 | _needs_second_acq_T_33; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_37 = _needs_second_acq_T_36 | _needs_second_acq_T_34; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_38 = _needs_second_acq_T_37 | _needs_second_acq_T_35; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_44 = _needs_second_acq_T_39 | _needs_second_acq_T_40; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_45 = _needs_second_acq_T_44 | _needs_second_acq_T_41; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_46 = _needs_second_acq_T_45 | _needs_second_acq_T_42; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_47 = _needs_second_acq_T_46 | _needs_second_acq_T_43; // @[package.scala:16:47, :81:59]
wire _needs_second_acq_T_48 = _needs_second_acq_T_38 | _needs_second_acq_T_47; // @[package.scala:81:59]
wire _needs_second_acq_T_49 = _needs_second_acq_T_31 | _needs_second_acq_T_48; // @[Consts.scala:87:44, :90:{59,76}]
wire _needs_second_acq_T_51 = _needs_second_acq_T_49 | _needs_second_acq_T_50; // @[Consts.scala:90:76, :91:{47,54}]
wire _needs_second_acq_T_53 = _needs_second_acq_T_51 | _needs_second_acq_T_52; // @[Consts.scala:91:{47,64,71}]
wire _needs_second_acq_T_54 = ~_needs_second_acq_T_53; // @[Metadata.scala:104:57]
wire cmd_requires_second_acquire = _needs_second_acq_T_26 & _needs_second_acq_T_54; // @[Metadata.scala:104:{54,57}]
wire is_hit_again = r1_1 & r2_1; // @[Misc.scala:35:9]
wire _dirties_cat_T_2 = _dirties_cat_T | _dirties_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _dirties_cat_T_4 = _dirties_cat_T_2 | _dirties_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _dirties_cat_T_9 = _dirties_cat_T_5 | _dirties_cat_T_6; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_10 = _dirties_cat_T_9 | _dirties_cat_T_7; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_11 = _dirties_cat_T_10 | _dirties_cat_T_8; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_17 = _dirties_cat_T_12 | _dirties_cat_T_13; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_18 = _dirties_cat_T_17 | _dirties_cat_T_14; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_19 = _dirties_cat_T_18 | _dirties_cat_T_15; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_20 = _dirties_cat_T_19 | _dirties_cat_T_16; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_21 = _dirties_cat_T_11 | _dirties_cat_T_20; // @[package.scala:81:59]
wire _dirties_cat_T_22 = _dirties_cat_T_4 | _dirties_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _dirties_cat_T_25 = _dirties_cat_T_23 | _dirties_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _dirties_cat_T_27 = _dirties_cat_T_25 | _dirties_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _dirties_cat_T_32 = _dirties_cat_T_28 | _dirties_cat_T_29; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_33 = _dirties_cat_T_32 | _dirties_cat_T_30; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_34 = _dirties_cat_T_33 | _dirties_cat_T_31; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_40 = _dirties_cat_T_35 | _dirties_cat_T_36; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_41 = _dirties_cat_T_40 | _dirties_cat_T_37; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_42 = _dirties_cat_T_41 | _dirties_cat_T_38; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_43 = _dirties_cat_T_42 | _dirties_cat_T_39; // @[package.scala:16:47, :81:59]
wire _dirties_cat_T_44 = _dirties_cat_T_34 | _dirties_cat_T_43; // @[package.scala:81:59]
wire _dirties_cat_T_45 = _dirties_cat_T_27 | _dirties_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _dirties_cat_T_47 = _dirties_cat_T_45 | _dirties_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _dirties_cat_T_49 = _dirties_cat_T_47 | _dirties_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] dirties_cat = {_dirties_cat_T_22, _dirties_cat_T_49}; // @[Metadata.scala:29:18]
wire dirties = &dirties_cat; // @[Metadata.scala:29:18, :106:42]
wire [1:0] biggest_grow_param = dirties ? r2_2 : r1_2; // @[Misc.scala:35:36]
wire [1:0] dirtier_coh_state = biggest_grow_param; // @[Metadata.scala:107:33, :160:20]
wire [4:0] dirtier_cmd = dirties ? io_req_uop_mem_cmd_0 : req_uop_mem_cmd; // @[Metadata.scala:106:42, :109:27]
wire _T_16 = io_mem_grant_ready_0 & io_mem_grant_valid_0; // @[Decoupled.scala:51:35]
wire [26:0] _r_beats1_decode_T = 27'hFFF << io_mem_grant_bits_size_0; // @[package.scala:243:71]
wire [11:0] _r_beats1_decode_T_1 = _r_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _r_beats1_decode_T_2 = ~_r_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [8:0] r_beats1_decode = _r_beats1_decode_T_2[11:3]; // @[package.scala:243:46]
wire r_beats1_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36]
wire opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36]
wire grant_had_data_opdata = io_mem_grant_bits_opcode_0[0]; // @[Edges.scala:106:36]
wire [8:0] r_beats1 = r_beats1_opdata ? r_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14]
reg [8:0] r_counter; // @[Edges.scala:229:27]
wire [9:0] _r_counter1_T = {1'h0, r_counter} - 10'h1; // @[Edges.scala:229:27, :230:28]
wire [8:0] r_counter1 = _r_counter1_T[8:0]; // @[Edges.scala:230:28]
wire r_1_1 = r_counter == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _r_last_T = r_counter == 9'h1; // @[Edges.scala:229:27, :232:25]
wire _r_last_T_1 = r_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43]
wire r_2 = _r_last_T | _r_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire refill_done = r_2 & _T_16; // @[Decoupled.scala:51:35]
wire [8:0] _r_count_T = ~r_counter1; // @[Edges.scala:230:28, :234:27]
wire [8:0] r_4 = r_beats1 & _r_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [8:0] _r_counter_T = r_1_1 ? r_beats1 : r_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire [11:0] refill_address_inc = {r_4, 3'h0}; // @[Edges.scala:234:25, :269:29]
wire _sec_rdy_T = ~cmd_requires_second_acquire; // @[Metadata.scala:104:54]
wire _sec_rdy_T_1 = ~io_req_is_probe_0; // @[mshrs.scala:36:7, :125:50]
wire _sec_rdy_T_2 = _sec_rdy_T & _sec_rdy_T_1; // @[mshrs.scala:125:{18,47,50}]
wire _sec_rdy_T_3 = ~(|state); // @[package.scala:16:47]
wire _sec_rdy_T_4 = state == 5'hD; // @[package.scala:16:47]
wire _sec_rdy_T_5 = state == 5'hE; // @[package.scala:16:47]
wire _sec_rdy_T_6 = state == 5'hF; // @[package.scala:16:47]
wire _sec_rdy_T_7 = _sec_rdy_T_3 | _sec_rdy_T_4; // @[package.scala:16:47, :81:59]
wire _sec_rdy_T_8 = _sec_rdy_T_7 | _sec_rdy_T_5; // @[package.scala:16:47, :81:59]
wire _sec_rdy_T_9 = _sec_rdy_T_8 | _sec_rdy_T_6; // @[package.scala:16:47, :81:59]
wire _sec_rdy_T_10 = ~_sec_rdy_T_9; // @[package.scala:81:59]
wire sec_rdy = _sec_rdy_T_2 & _sec_rdy_T_10; // @[mshrs.scala:125:{47,67}, :126:18]
wire _rpq_io_enq_valid_T = io_req_pri_val_0 & io_req_pri_rdy_0; // @[mshrs.scala:36:7, :133:40]
wire _rpq_io_enq_valid_T_1 = io_req_sec_val_0 & io_req_sec_rdy_0; // @[mshrs.scala:36:7, :133:78]
wire _rpq_io_enq_valid_T_2 = _rpq_io_enq_valid_T | _rpq_io_enq_valid_T_1; // @[mshrs.scala:133:{40,59,78}]
wire _rpq_io_enq_valid_T_3 = io_req_uop_mem_cmd_0 == 5'h2; // @[Consts.scala:88:35]
wire _rpq_io_enq_valid_T_5 = _rpq_io_enq_valid_T_3 | _rpq_io_enq_valid_T_4; // @[Consts.scala:88:{35,45,52}]
wire _rpq_io_enq_valid_T_6 = ~_rpq_io_enq_valid_T_5; // @[Consts.scala:88:45]
wire _rpq_io_enq_valid_T_7 = _rpq_io_enq_valid_T_2 & _rpq_io_enq_valid_T_6; // @[mshrs.scala:133:{59,98,101}]
reg grantack_valid; // @[mshrs.scala:138:21]
reg [2:0] grantack_bits_sink; // @[mshrs.scala:138:21]
assign io_mem_finish_bits_sink_0 = grantack_bits_sink; // @[mshrs.scala:36:7, :138:21]
reg [2:0] refill_ctr; // @[mshrs.scala:139:24]
reg commit_line; // @[mshrs.scala:140:24]
reg grant_had_data; // @[mshrs.scala:141:27]
reg finish_to_prefetch; // @[mshrs.scala:142:31]
reg [1:0] meta_hazard; // @[mshrs.scala:145:28]
wire [2:0] _meta_hazard_T = {1'h0, meta_hazard} + 3'h1; // @[mshrs.scala:145:28, :146:59]
wire [1:0] _meta_hazard_T_1 = _meta_hazard_T[1:0]; // @[mshrs.scala:146:59]
wire _io_probe_rdy_T = meta_hazard == 2'h0; // @[mshrs.scala:145:28, :148:34]
wire _io_probe_rdy_T_1 = ~(|state); // @[package.scala:16:47]
wire _io_probe_rdy_T_2 = state == 5'h1; // @[package.scala:16:47]
wire _io_probe_rdy_T_3 = state == 5'h2; // @[package.scala:16:47]
wire _io_probe_rdy_T_4 = state == 5'h3; // @[package.scala:16:47]
wire _io_probe_rdy_T_5 = _io_probe_rdy_T_1 | _io_probe_rdy_T_2; // @[package.scala:16:47, :81:59]
wire _io_probe_rdy_T_6 = _io_probe_rdy_T_5 | _io_probe_rdy_T_3; // @[package.scala:16:47, :81:59]
wire _io_probe_rdy_T_7 = _io_probe_rdy_T_6 | _io_probe_rdy_T_4; // @[package.scala:16:47, :81:59]
wire _io_probe_rdy_T_8 = state == 5'h4; // @[mshrs.scala:107:22, :148:129]
wire _io_probe_rdy_T_9 = _io_probe_rdy_T_8 & grantack_valid; // @[mshrs.scala:138:21, :148:{129,145}]
wire _io_probe_rdy_T_10 = _io_probe_rdy_T_7 | _io_probe_rdy_T_9; // @[package.scala:81:59]
assign _io_probe_rdy_T_11 = _io_probe_rdy_T & _io_probe_rdy_T_10; // @[mshrs.scala:148:{34,42,119}]
assign io_probe_rdy_0 = _io_probe_rdy_T_11; // @[mshrs.scala:36:7, :148:42]
assign _io_idx_valid_T = |state; // @[package.scala:16:47]
assign io_idx_valid_0 = _io_idx_valid_T; // @[mshrs.scala:36:7, :149:25]
assign _io_tag_valid_T = |state; // @[package.scala:16:47]
assign io_tag_valid_0 = _io_tag_valid_T; // @[mshrs.scala:36:7, :150:25]
wire _io_way_valid_T = ~(|state); // @[package.scala:16:47]
wire _io_way_valid_T_1 = state == 5'h11; // @[package.scala:16:47]
wire _io_way_valid_T_2 = _io_way_valid_T | _io_way_valid_T_1; // @[package.scala:16:47, :81:59]
assign _io_way_valid_T_3 = ~_io_way_valid_T_2; // @[package.scala:81:59]
assign io_way_valid_0 = _io_way_valid_T_3; // @[mshrs.scala:36:7, :151:19]
assign _io_req_sec_rdy_T = sec_rdy & _rpq_io_enq_ready; // @[mshrs.scala:125:67, :128:19, :159:37]
assign io_req_sec_rdy_0 = _io_req_sec_rdy_T; // @[mshrs.scala:36:7, :159:37]
wire [4:0] state_new_state; // @[mshrs.scala:191:29]
wire _state_T_1 = ~_state_T; // @[mshrs.scala:194:11]
wire _state_T_2 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11]
wire [3:0] _GEN_27 = {2'h2, io_req_old_meta_coh_state_0}; // @[Metadata.scala:120:19]
wire [3:0] _state_req_needs_wb_r_T_6; // @[Metadata.scala:120:19]
assign _state_req_needs_wb_r_T_6 = _GEN_27; // @[Metadata.scala:120:19]
wire [3:0] _state_req_needs_wb_r_T_70; // @[Metadata.scala:120:19]
assign _state_req_needs_wb_r_T_70 = _GEN_27; // @[Metadata.scala:120:19]
wire _state_req_needs_wb_r_T_19 = _state_req_needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_21 = _state_req_needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_23 = _state_req_needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_25 = _state_req_needs_wb_r_T_23 ? 3'h2 : _state_req_needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_27 = _state_req_needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_29 = _state_req_needs_wb_r_T_27 ? 3'h1 : _state_req_needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_31 = _state_req_needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_32 = _state_req_needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_33 = _state_req_needs_wb_r_T_31 ? 3'h1 : _state_req_needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_35 = _state_req_needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_36 = ~_state_req_needs_wb_r_T_35 & _state_req_needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_37 = _state_req_needs_wb_r_T_35 ? 3'h5 : _state_req_needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_39 = _state_req_needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_40 = ~_state_req_needs_wb_r_T_39 & _state_req_needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_41 = _state_req_needs_wb_r_T_39 ? 3'h4 : _state_req_needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_42 = {1'h0, _state_req_needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_43 = _state_req_needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_44 = ~_state_req_needs_wb_r_T_43 & _state_req_needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_45 = _state_req_needs_wb_r_T_43 ? 3'h0 : _state_req_needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_46 = _state_req_needs_wb_r_T_43 ? 2'h1 : _state_req_needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_47 = _state_req_needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_48 = _state_req_needs_wb_r_T_47 | _state_req_needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_49 = _state_req_needs_wb_r_T_47 ? 3'h0 : _state_req_needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_50 = _state_req_needs_wb_r_T_47 ? 2'h1 : _state_req_needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_51 = _state_req_needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_52 = ~_state_req_needs_wb_r_T_51 & _state_req_needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_53 = _state_req_needs_wb_r_T_51 ? 3'h5 : _state_req_needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_54 = _state_req_needs_wb_r_T_51 ? 2'h0 : _state_req_needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_55 = _state_req_needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_56 = ~_state_req_needs_wb_r_T_55 & _state_req_needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_57 = _state_req_needs_wb_r_T_55 ? 3'h4 : _state_req_needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_58 = _state_req_needs_wb_r_T_55 ? 2'h1 : _state_req_needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_59 = _state_req_needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_60 = ~_state_req_needs_wb_r_T_59 & _state_req_needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_61 = _state_req_needs_wb_r_T_59 ? 3'h3 : _state_req_needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_62 = _state_req_needs_wb_r_T_59 ? 2'h2 : _state_req_needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_63 = _state_req_needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20]
wire state_req_needs_wb_r_1 = _state_req_needs_wb_r_T_63 | _state_req_needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20]
wire [2:0] state_req_needs_wb_r_2 = _state_req_needs_wb_r_T_63 ? 3'h3 : _state_req_needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20]
wire [1:0] state_req_needs_wb_r_3 = _state_req_needs_wb_r_T_63 ? 2'h2 : _state_req_needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20]
wire [1:0] state_req_needs_wb_meta_state = state_req_needs_wb_r_3; // @[Misc.scala:38:63]
wire _state_r_c_cat_T_2 = _state_r_c_cat_T | _state_r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_4 = _state_r_c_cat_T_2 | _state_r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_9 = _state_r_c_cat_T_5 | _state_r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_10 = _state_r_c_cat_T_9 | _state_r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_11 = _state_r_c_cat_T_10 | _state_r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_17 = _state_r_c_cat_T_12 | _state_r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_18 = _state_r_c_cat_T_17 | _state_r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_19 = _state_r_c_cat_T_18 | _state_r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_20 = _state_r_c_cat_T_19 | _state_r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_21 = _state_r_c_cat_T_11 | _state_r_c_cat_T_20; // @[package.scala:81:59]
wire _state_r_c_cat_T_22 = _state_r_c_cat_T_4 | _state_r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_25 = _state_r_c_cat_T_23 | _state_r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_27 = _state_r_c_cat_T_25 | _state_r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_32 = _state_r_c_cat_T_28 | _state_r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_33 = _state_r_c_cat_T_32 | _state_r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_34 = _state_r_c_cat_T_33 | _state_r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_40 = _state_r_c_cat_T_35 | _state_r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_41 = _state_r_c_cat_T_40 | _state_r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_42 = _state_r_c_cat_T_41 | _state_r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_43 = _state_r_c_cat_T_42 | _state_r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_44 = _state_r_c_cat_T_34 | _state_r_c_cat_T_43; // @[package.scala:81:59]
wire _state_r_c_cat_T_45 = _state_r_c_cat_T_27 | _state_r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_47 = _state_r_c_cat_T_45 | _state_r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _state_r_c_cat_T_49 = _state_r_c_cat_T_47 | _state_r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] state_r_c = {_state_r_c_cat_T_22, _state_r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _state_r_T = {state_r_c, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19]
wire _state_r_T_25 = _state_r_T == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_27 = {1'h0, _state_r_T_25}; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_28 = _state_r_T == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_30 = _state_r_T_28 ? 2'h2 : _state_r_T_27; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_31 = _state_r_T == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_33 = _state_r_T_31 ? 2'h1 : _state_r_T_30; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_34 = _state_r_T == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_36 = _state_r_T_34 ? 2'h2 : _state_r_T_33; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_37 = _state_r_T == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_39 = _state_r_T_37 ? 2'h0 : _state_r_T_36; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_40 = _state_r_T == 4'hE; // @[Misc.scala:49:20]
wire _state_r_T_41 = _state_r_T_40; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_42 = _state_r_T_40 ? 2'h3 : _state_r_T_39; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_43 = &_state_r_T; // @[Misc.scala:49:20]
wire _state_r_T_44 = _state_r_T_43 | _state_r_T_41; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_45 = _state_r_T_43 ? 2'h3 : _state_r_T_42; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_46 = _state_r_T == 4'h6; // @[Misc.scala:49:20]
wire _state_r_T_47 = _state_r_T_46 | _state_r_T_44; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_48 = _state_r_T_46 ? 2'h2 : _state_r_T_45; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_49 = _state_r_T == 4'h7; // @[Misc.scala:49:20]
wire _state_r_T_50 = _state_r_T_49 | _state_r_T_47; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_51 = _state_r_T_49 ? 2'h3 : _state_r_T_48; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_52 = _state_r_T == 4'h1; // @[Misc.scala:49:20]
wire _state_r_T_53 = _state_r_T_52 | _state_r_T_50; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_54 = _state_r_T_52 ? 2'h1 : _state_r_T_51; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_55 = _state_r_T == 4'h2; // @[Misc.scala:49:20]
wire _state_r_T_56 = _state_r_T_55 | _state_r_T_53; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_57 = _state_r_T_55 ? 2'h2 : _state_r_T_54; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_58 = _state_r_T == 4'h3; // @[Misc.scala:49:20]
wire state_is_hit = _state_r_T_58 | _state_r_T_56; // @[Misc.scala:35:9, :49:20]
wire [1:0] state_r_2 = _state_r_T_58 ? 2'h3 : _state_r_T_57; // @[Misc.scala:35:36, :49:20]
wire [1:0] state_coh_on_hit_state = state_r_2; // @[Misc.scala:35:36]
wire _state_T_5 = _state_T_3 | _state_T_4; // @[Consts.scala:90:{32,42,49}]
wire _state_T_7 = _state_T_5 | _state_T_6; // @[Consts.scala:90:{42,59,66}]
wire _state_T_12 = _state_T_8 | _state_T_9; // @[package.scala:16:47, :81:59]
wire _state_T_13 = _state_T_12 | _state_T_10; // @[package.scala:16:47, :81:59]
wire _state_T_14 = _state_T_13 | _state_T_11; // @[package.scala:16:47, :81:59]
wire _state_T_20 = _state_T_15 | _state_T_16; // @[package.scala:16:47, :81:59]
wire _state_T_21 = _state_T_20 | _state_T_17; // @[package.scala:16:47, :81:59]
wire _state_T_22 = _state_T_21 | _state_T_18; // @[package.scala:16:47, :81:59]
wire _state_T_23 = _state_T_22 | _state_T_19; // @[package.scala:16:47, :81:59]
wire _state_T_24 = _state_T_14 | _state_T_23; // @[package.scala:81:59]
wire _state_T_25 = _state_T_7 | _state_T_24; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_T_27 = ~_state_T_26; // @[mshrs.scala:201:15]
wire _state_T_28 = ~_state_T_25; // @[Consts.scala:90:76]
assign state_new_state = io_req_tag_match_0 & state_is_hit ? 5'hC : 5'h1; // @[Misc.scala:35:9]
assign io_mem_acquire_valid_0 = (|state) & _io_probe_rdy_T_2; // @[package.scala:16:47]
wire [27:0] _GEN_28 = {req_tag, req_idx}; // @[mshrs.scala:110:25, :111:26, :227:28]
wire [27:0] _io_mem_acquire_bits_T; // @[mshrs.scala:227:28]
assign _io_mem_acquire_bits_T = _GEN_28; // @[mshrs.scala:227:28]
wire [27:0] rp_addr_hi; // @[mshrs.scala:261:22]
assign rp_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :261:22]
wire [27:0] hi; // @[mshrs.scala:266:10]
assign hi = _GEN_28; // @[mshrs.scala:227:28, :266:10]
wire [27:0] io_replay_bits_addr_hi; // @[mshrs.scala:353:31]
assign io_replay_bits_addr_hi = _GEN_28; // @[mshrs.scala:227:28, :353:31]
wire [33:0] _io_mem_acquire_bits_T_1 = {_io_mem_acquire_bits_T, 6'h0}; // @[mshrs.scala:227:{28,47}]
wire [33:0] _io_mem_acquire_bits_legal_T_1 = _io_mem_acquire_bits_T_1; // @[Parameters.scala:137:31]
wire [34:0] _io_mem_acquire_bits_legal_T_2 = {1'h0, _io_mem_acquire_bits_legal_T_1}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _io_mem_acquire_bits_legal_T_3 = _io_mem_acquire_bits_legal_T_2 & 35'h80000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _io_mem_acquire_bits_legal_T_4 = _io_mem_acquire_bits_legal_T_3; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_5 = _io_mem_acquire_bits_legal_T_4 == 35'h0; // @[Parameters.scala:137:{46,59}]
assign io_mem_acquire_bits_a_address = _io_mem_acquire_bits_T_1[31:0]; // @[Edges.scala:346:17]
wire [33:0] _io_mem_acquire_bits_legal_T_9 = {_io_mem_acquire_bits_T_1[33:32], io_mem_acquire_bits_a_address ^ 32'h80000000}; // @[Edges.scala:346:17]
wire [34:0] _io_mem_acquire_bits_legal_T_10 = {1'h0, _io_mem_acquire_bits_legal_T_9}; // @[Parameters.scala:137:{31,41}]
wire [34:0] _io_mem_acquire_bits_legal_T_11 = _io_mem_acquire_bits_legal_T_10 & 35'h80000000; // @[Parameters.scala:137:{41,46}]
wire [34:0] _io_mem_acquire_bits_legal_T_12 = _io_mem_acquire_bits_legal_T_11; // @[Parameters.scala:137:46]
wire _io_mem_acquire_bits_legal_T_13 = _io_mem_acquire_bits_legal_T_12 == 35'h0; // @[Parameters.scala:137:{46,59}]
wire _io_mem_acquire_bits_legal_T_14 = _io_mem_acquire_bits_legal_T_13; // @[Parameters.scala:684:54]
wire io_mem_acquire_bits_legal = _io_mem_acquire_bits_legal_T_14; // @[Parameters.scala:684:54, :686:26]
assign io_mem_acquire_bits_param_0 = io_mem_acquire_bits_a_param; // @[Edges.scala:346:17]
assign io_mem_acquire_bits_address_0 = io_mem_acquire_bits_a_address; // @[Edges.scala:346:17]
assign io_mem_acquire_bits_a_param = {1'h0, grow_param}; // @[Misc.scala:35:36]
wire io_mem_acquire_bits_a_mask_sub_sub_bit = _io_mem_acquire_bits_T_1[2]; // @[Misc.scala:210:26]
wire io_mem_acquire_bits_a_mask_sub_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_sub_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_sub_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T = io_mem_acquire_bits_a_mask_sub_sub_0_2; // @[Misc.scala:214:27, :215:38]
wire _io_mem_acquire_bits_a_mask_sub_sub_acc_T_1 = io_mem_acquire_bits_a_mask_sub_sub_1_2; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_sub_bit = _io_mem_acquire_bits_T_1[1]; // @[Misc.scala:210:26]
wire io_mem_acquire_bits_a_mask_sub_nbit = ~io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_sub_0_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire io_mem_acquire_bits_a_mask_sub_1_2 = io_mem_acquire_bits_a_mask_sub_sub_0_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_sub_2_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire io_mem_acquire_bits_a_mask_sub_3_2 = io_mem_acquire_bits_a_mask_sub_sub_1_2 & io_mem_acquire_bits_a_mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire io_mem_acquire_bits_a_mask_bit = _io_mem_acquire_bits_T_1[0]; // @[Misc.scala:210:26]
wire io_mem_acquire_bits_a_mask_nbit = ~io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :211:20]
wire io_mem_acquire_bits_a_mask_eq = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T = io_mem_acquire_bits_a_mask_eq; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_1 = io_mem_acquire_bits_a_mask_sub_0_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_1 = io_mem_acquire_bits_a_mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_2 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_2 = io_mem_acquire_bits_a_mask_eq_2; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_3 = io_mem_acquire_bits_a_mask_sub_1_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_3 = io_mem_acquire_bits_a_mask_eq_3; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_4 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_4 = io_mem_acquire_bits_a_mask_eq_4; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_5 = io_mem_acquire_bits_a_mask_sub_2_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_5 = io_mem_acquire_bits_a_mask_eq_5; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_6 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_6 = io_mem_acquire_bits_a_mask_eq_6; // @[Misc.scala:214:27, :215:38]
wire io_mem_acquire_bits_a_mask_eq_7 = io_mem_acquire_bits_a_mask_sub_3_2 & io_mem_acquire_bits_a_mask_bit; // @[Misc.scala:210:26, :214:27]
wire _io_mem_acquire_bits_a_mask_acc_T_7 = io_mem_acquire_bits_a_mask_eq_7; // @[Misc.scala:214:27, :215:38]
wire _GEN_29 = ~(|state) | _io_probe_rdy_T_2; // @[package.scala:16:47]
assign io_lb_write_valid_0 = ~_GEN_29 & _io_probe_rdy_T_3 & opdata & io_mem_grant_valid_0; // @[package.scala:16:47]
wire [8:0] _io_lb_write_bits_offset_T = refill_address_inc[11:3]; // @[Edges.scala:269:29]
assign io_lb_write_bits_offset_0 = _io_lb_write_bits_offset_T[2:0]; // @[mshrs.scala:36:7, :238:{31,53}]
assign io_mem_grant_ready_0 = ~_GEN_29 & _io_probe_rdy_T_3; // @[package.scala:16:47]
wire _grantack_valid_T = io_mem_grant_bits_opcode_0[2]; // @[Edges.scala:71:36]
wire _grantack_valid_T_1 = io_mem_grant_bits_opcode_0[1]; // @[Edges.scala:71:52]
wire _grantack_valid_T_2 = ~_grantack_valid_T_1; // @[Edges.scala:71:{43,52}]
wire _grantack_valid_T_3 = _grantack_valid_T & _grantack_valid_T_2; // @[Edges.scala:71:{36,40,43}]
wire [4:0] _state_T_29 = grant_had_data ? 5'h3 : 5'hC; // @[mshrs.scala:141:27, :250:19]
wire _drain_load_T = _rpq_io_deq_bits_uop_mem_cmd == 5'h0; // @[package.scala:16:47]
wire _drain_load_T_1 = _rpq_io_deq_bits_uop_mem_cmd == 5'h10; // @[package.scala:16:47]
wire _GEN_30 = _rpq_io_deq_bits_uop_mem_cmd == 5'h6; // @[package.scala:16:47]
wire _drain_load_T_2; // @[package.scala:16:47]
assign _drain_load_T_2 = _GEN_30; // @[package.scala:16:47]
wire _r_c_cat_T_48; // @[Consts.scala:91:71]
assign _r_c_cat_T_48 = _GEN_30; // @[package.scala:16:47]
wire _GEN_31 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[package.scala:16:47]
wire _drain_load_T_3; // @[package.scala:16:47]
assign _drain_load_T_3 = _GEN_31; // @[package.scala:16:47]
wire _drain_load_T_28; // @[Consts.scala:90:66]
assign _drain_load_T_28 = _GEN_31; // @[package.scala:16:47]
wire _drain_load_T_4 = _drain_load_T | _drain_load_T_1; // @[package.scala:16:47, :81:59]
wire _drain_load_T_5 = _drain_load_T_4 | _drain_load_T_2; // @[package.scala:16:47, :81:59]
wire _drain_load_T_6 = _drain_load_T_5 | _drain_load_T_3; // @[package.scala:16:47, :81:59]
wire _GEN_32 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _drain_load_T_7; // @[package.scala:16:47]
assign _drain_load_T_7 = _GEN_32; // @[package.scala:16:47]
wire _drain_load_T_30; // @[package.scala:16:47]
assign _drain_load_T_30 = _GEN_32; // @[package.scala:16:47]
wire _GEN_33 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _drain_load_T_8; // @[package.scala:16:47]
assign _drain_load_T_8 = _GEN_33; // @[package.scala:16:47]
wire _drain_load_T_31; // @[package.scala:16:47]
assign _drain_load_T_31 = _GEN_33; // @[package.scala:16:47]
wire _GEN_34 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _drain_load_T_9; // @[package.scala:16:47]
assign _drain_load_T_9 = _GEN_34; // @[package.scala:16:47]
wire _drain_load_T_32; // @[package.scala:16:47]
assign _drain_load_T_32 = _GEN_34; // @[package.scala:16:47]
wire _GEN_35 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _drain_load_T_10; // @[package.scala:16:47]
assign _drain_load_T_10 = _GEN_35; // @[package.scala:16:47]
wire _drain_load_T_33; // @[package.scala:16:47]
assign _drain_load_T_33 = _GEN_35; // @[package.scala:16:47]
wire _drain_load_T_11 = _drain_load_T_7 | _drain_load_T_8; // @[package.scala:16:47, :81:59]
wire _drain_load_T_12 = _drain_load_T_11 | _drain_load_T_9; // @[package.scala:16:47, :81:59]
wire _drain_load_T_13 = _drain_load_T_12 | _drain_load_T_10; // @[package.scala:16:47, :81:59]
wire _GEN_36 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _drain_load_T_14; // @[package.scala:16:47]
assign _drain_load_T_14 = _GEN_36; // @[package.scala:16:47]
wire _drain_load_T_37; // @[package.scala:16:47]
assign _drain_load_T_37 = _GEN_36; // @[package.scala:16:47]
wire _GEN_37 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _drain_load_T_15; // @[package.scala:16:47]
assign _drain_load_T_15 = _GEN_37; // @[package.scala:16:47]
wire _drain_load_T_38; // @[package.scala:16:47]
assign _drain_load_T_38 = _GEN_37; // @[package.scala:16:47]
wire _GEN_38 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _drain_load_T_16; // @[package.scala:16:47]
assign _drain_load_T_16 = _GEN_38; // @[package.scala:16:47]
wire _drain_load_T_39; // @[package.scala:16:47]
assign _drain_load_T_39 = _GEN_38; // @[package.scala:16:47]
wire _GEN_39 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _drain_load_T_17; // @[package.scala:16:47]
assign _drain_load_T_17 = _GEN_39; // @[package.scala:16:47]
wire _drain_load_T_40; // @[package.scala:16:47]
assign _drain_load_T_40 = _GEN_39; // @[package.scala:16:47]
wire _GEN_40 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _drain_load_T_18; // @[package.scala:16:47]
assign _drain_load_T_18 = _GEN_40; // @[package.scala:16:47]
wire _drain_load_T_41; // @[package.scala:16:47]
assign _drain_load_T_41 = _GEN_40; // @[package.scala:16:47]
wire _drain_load_T_19 = _drain_load_T_14 | _drain_load_T_15; // @[package.scala:16:47, :81:59]
wire _drain_load_T_20 = _drain_load_T_19 | _drain_load_T_16; // @[package.scala:16:47, :81:59]
wire _drain_load_T_21 = _drain_load_T_20 | _drain_load_T_17; // @[package.scala:16:47, :81:59]
wire _drain_load_T_22 = _drain_load_T_21 | _drain_load_T_18; // @[package.scala:16:47, :81:59]
wire _drain_load_T_23 = _drain_load_T_13 | _drain_load_T_22; // @[package.scala:81:59]
wire _drain_load_T_24 = _drain_load_T_6 | _drain_load_T_23; // @[package.scala:81:59]
wire _drain_load_T_25 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _drain_load_T_26 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _drain_load_T_27 = _drain_load_T_25 | _drain_load_T_26; // @[Consts.scala:90:{32,42,49}]
wire _drain_load_T_29 = _drain_load_T_27 | _drain_load_T_28; // @[Consts.scala:90:{42,59,66}]
wire _drain_load_T_34 = _drain_load_T_30 | _drain_load_T_31; // @[package.scala:16:47, :81:59]
wire _drain_load_T_35 = _drain_load_T_34 | _drain_load_T_32; // @[package.scala:16:47, :81:59]
wire _drain_load_T_36 = _drain_load_T_35 | _drain_load_T_33; // @[package.scala:16:47, :81:59]
wire _drain_load_T_42 = _drain_load_T_37 | _drain_load_T_38; // @[package.scala:16:47, :81:59]
wire _drain_load_T_43 = _drain_load_T_42 | _drain_load_T_39; // @[package.scala:16:47, :81:59]
wire _drain_load_T_44 = _drain_load_T_43 | _drain_load_T_40; // @[package.scala:16:47, :81:59]
wire _drain_load_T_45 = _drain_load_T_44 | _drain_load_T_41; // @[package.scala:16:47, :81:59]
wire _drain_load_T_46 = _drain_load_T_36 | _drain_load_T_45; // @[package.scala:81:59]
wire _drain_load_T_47 = _drain_load_T_29 | _drain_load_T_46; // @[Consts.scala:87:44, :90:{59,76}]
wire _drain_load_T_48 = ~_drain_load_T_47; // @[Consts.scala:90:76]
wire _drain_load_T_49 = _drain_load_T_24 & _drain_load_T_48; // @[Consts.scala:89:68]
wire _drain_load_T_50 = _rpq_io_deq_bits_uop_mem_cmd != 5'h6; // @[mshrs.scala:128:19, :259:51]
wire drain_load = _drain_load_T_49 & _drain_load_T_50; // @[mshrs.scala:257:59, :258:60, :259:51]
wire [5:0] _rp_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :261:61]
wire [33:0] rp_addr = {rp_addr_hi, _rp_addr_T}; // @[mshrs.scala:261:{22,61}]
wire [1:0] size; // @[AMOALU.scala:11:18]
wire _rpq_io_deq_ready_T = io_resp_ready_0 & io_lb_read_ready_0; // @[mshrs.scala:36:7, :270:45]
wire _rpq_io_deq_ready_T_1 = _rpq_io_deq_ready_T & drain_load; // @[mshrs.scala:258:60, :270:{45,65}]
wire _io_lb_read_valid_T = _rpq_io_deq_valid & drain_load; // @[mshrs.scala:128:19, :258:60, :271:48]
wire [30:0] _io_lb_read_bits_offset_T = _rpq_io_deq_bits_addr[33:3]; // @[mshrs.scala:128:19, :273:52]
wire _GEN_41 = io_lb_read_ready_0 & io_lb_read_valid_0; // @[Decoupled.scala:51:35]
wire _io_resp_valid_T; // @[Decoupled.scala:51:35]
assign _io_resp_valid_T = _GEN_41; // @[Decoupled.scala:51:35]
wire _io_refill_valid_T; // @[Decoupled.scala:51:35]
assign _io_refill_valid_T = _GEN_41; // @[Decoupled.scala:51:35]
wire _io_resp_valid_T_1 = _rpq_io_deq_valid & _io_resp_valid_T; // @[Decoupled.scala:51:35]
wire _io_resp_valid_T_2 = _io_resp_valid_T_1 & drain_load; // @[mshrs.scala:258:60, :275:{43,62}]
wire _GEN_42 = ~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3; // @[package.scala:16:47]
assign io_resp_valid_0 = ~_GEN_42 & _io_probe_rdy_T_4 & _io_resp_valid_T_2; // @[package.scala:16:47]
wire _io_resp_bits_data_shifted_T = _rpq_io_deq_bits_addr[2]; // @[AMOALU.scala:42:29]
wire [31:0] _io_resp_bits_data_shifted_T_1 = data_word[63:32]; // @[AMOALU.scala:42:37]
wire [31:0] _io_resp_bits_data_T_5 = data_word[63:32]; // @[AMOALU.scala:42:37, :45:94]
wire [31:0] _io_resp_bits_data_shifted_T_2 = data_word[31:0]; // @[AMOALU.scala:42:55]
wire [31:0] io_resp_bits_data_shifted = _io_resp_bits_data_shifted_T ? _io_resp_bits_data_shifted_T_1 : _io_resp_bits_data_shifted_T_2; // @[AMOALU.scala:42:{24,29,37,55}]
wire [31:0] io_resp_bits_data_zeroed = io_resp_bits_data_shifted; // @[AMOALU.scala:42:24, :44:23]
wire _io_resp_bits_data_T = size == 2'h2; // @[AMOALU.scala:11:18, :45:26]
wire _io_resp_bits_data_T_1 = _io_resp_bits_data_T; // @[AMOALU.scala:45:{26,34}]
wire _io_resp_bits_data_T_2 = io_resp_bits_data_zeroed[31]; // @[AMOALU.scala:44:23, :45:81]
wire _io_resp_bits_data_T_3 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_2; // @[AMOALU.scala:45:{72,81}]
wire [31:0] _io_resp_bits_data_T_4 = {32{_io_resp_bits_data_T_3}}; // @[AMOALU.scala:45:{49,72}]
wire [31:0] _io_resp_bits_data_T_6 = _io_resp_bits_data_T_1 ? _io_resp_bits_data_T_4 : _io_resp_bits_data_T_5; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_resp_bits_data_T_7 = {_io_resp_bits_data_T_6, io_resp_bits_data_zeroed}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire _io_resp_bits_data_shifted_T_3 = _rpq_io_deq_bits_addr[1]; // @[AMOALU.scala:42:29]
wire [15:0] _io_resp_bits_data_shifted_T_4 = _io_resp_bits_data_T_7[31:16]; // @[AMOALU.scala:42:37, :45:16]
wire [15:0] _io_resp_bits_data_shifted_T_5 = _io_resp_bits_data_T_7[15:0]; // @[AMOALU.scala:42:55, :45:16]
wire [15:0] io_resp_bits_data_shifted_1 = _io_resp_bits_data_shifted_T_3 ? _io_resp_bits_data_shifted_T_4 : _io_resp_bits_data_shifted_T_5; // @[AMOALU.scala:42:{24,29,37,55}]
wire [15:0] io_resp_bits_data_zeroed_1 = io_resp_bits_data_shifted_1; // @[AMOALU.scala:42:24, :44:23]
wire _io_resp_bits_data_T_8 = size == 2'h1; // @[AMOALU.scala:11:18, :45:26]
wire _io_resp_bits_data_T_9 = _io_resp_bits_data_T_8; // @[AMOALU.scala:45:{26,34}]
wire _io_resp_bits_data_T_10 = io_resp_bits_data_zeroed_1[15]; // @[AMOALU.scala:44:23, :45:81]
wire _io_resp_bits_data_T_11 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_10; // @[AMOALU.scala:45:{72,81}]
wire [47:0] _io_resp_bits_data_T_12 = {48{_io_resp_bits_data_T_11}}; // @[AMOALU.scala:45:{49,72}]
wire [47:0] _io_resp_bits_data_T_13 = _io_resp_bits_data_T_7[63:16]; // @[AMOALU.scala:45:{16,94}]
wire [47:0] _io_resp_bits_data_T_14 = _io_resp_bits_data_T_9 ? _io_resp_bits_data_T_12 : _io_resp_bits_data_T_13; // @[AMOALU.scala:45:{20,34,49,94}]
wire [63:0] _io_resp_bits_data_T_15 = {_io_resp_bits_data_T_14, io_resp_bits_data_zeroed_1}; // @[AMOALU.scala:44:23, :45:{16,20}]
wire _io_resp_bits_data_shifted_T_6 = _rpq_io_deq_bits_addr[0]; // @[AMOALU.scala:42:29]
wire [7:0] _io_resp_bits_data_shifted_T_7 = _io_resp_bits_data_T_15[15:8]; // @[AMOALU.scala:42:37, :45:16]
wire [7:0] _io_resp_bits_data_shifted_T_8 = _io_resp_bits_data_T_15[7:0]; // @[AMOALU.scala:42:55, :45:16]
wire [7:0] io_resp_bits_data_shifted_2 = _io_resp_bits_data_shifted_T_6 ? _io_resp_bits_data_shifted_T_7 : _io_resp_bits_data_shifted_T_8; // @[AMOALU.scala:42:{24,29,37,55}]
wire [7:0] io_resp_bits_data_zeroed_2 = io_resp_bits_data_shifted_2; // @[AMOALU.scala:42:24, :44:23]
wire _io_resp_bits_data_T_16 = size == 2'h0; // @[AMOALU.scala:11:18, :45:26]
wire _io_resp_bits_data_T_17 = _io_resp_bits_data_T_16; // @[AMOALU.scala:45:{26,34}]
wire _io_resp_bits_data_T_18 = io_resp_bits_data_zeroed_2[7]; // @[AMOALU.scala:44:23, :45:81]
wire _io_resp_bits_data_T_19 = _rpq_io_deq_bits_uop_mem_signed & _io_resp_bits_data_T_18; // @[AMOALU.scala:45:{72,81}]
wire [55:0] _io_resp_bits_data_T_20 = {56{_io_resp_bits_data_T_19}}; // @[AMOALU.scala:45:{49,72}]
wire [55:0] _io_resp_bits_data_T_21 = _io_resp_bits_data_T_15[63:8]; // @[AMOALU.scala:45:{16,94}]
wire [55:0] _io_resp_bits_data_T_22 = _io_resp_bits_data_T_17 ? _io_resp_bits_data_T_20 : _io_resp_bits_data_T_21; // @[AMOALU.scala:45:{20,34,49,94}]
assign _io_resp_bits_data_T_23 = {_io_resp_bits_data_T_22, io_resp_bits_data_zeroed_2}; // @[AMOALU.scala:44:23, :45:{16,20}]
assign io_resp_bits_data_0 = _io_resp_bits_data_T_23; // @[AMOALU.scala:45:16]
wire _T_26 = rpq_io_deq_ready & _rpq_io_deq_valid; // @[Decoupled.scala:51:35]
wire _T_28 = _rpq_io_empty & ~commit_line; // @[mshrs.scala:128:19, :140:24, :282:{31,34}]
wire _T_33 = _rpq_io_empty | _rpq_io_deq_valid & ~drain_load; // @[mshrs.scala:128:19, :258:60, :288:{31,52,55}]
assign io_commit_val_0 = ~_GEN_42 & _io_probe_rdy_T_4 & ~(_T_26 | _T_28) & _T_33; // @[Decoupled.scala:51:35]
wire _io_meta_read_valid_T = ~io_prober_state_valid_0; // @[mshrs.scala:36:7, :295:27]
wire _io_meta_read_valid_T_1 = ~grantack_valid; // @[mshrs.scala:138:21, :295:53]
wire _io_meta_read_valid_T_2 = _io_meta_read_valid_T | _io_meta_read_valid_T_1; // @[mshrs.scala:295:{27,50,53}]
wire [3:0] _io_meta_read_valid_T_3 = io_prober_state_bits_0[9:6]; // @[mshrs.scala:36:7, :295:93]
wire _io_meta_read_valid_T_4 = _io_meta_read_valid_T_3 != req_idx; // @[mshrs.scala:110:25, :295:{93,120}]
wire _io_meta_read_valid_T_5 = _io_meta_read_valid_T_2 | _io_meta_read_valid_T_4; // @[mshrs.scala:295:{50,69,120}]
assign io_meta_read_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4) & _io_probe_rdy_T_8 & _io_meta_read_valid_T_5; // @[package.scala:16:47]
assign io_meta_write_bits_data_tag_0 = req_tag[21:0]; // @[mshrs.scala:36:7, :111:26, :297:27]
assign io_meta_read_bits_tag_0 = req_tag[21:0]; // @[mshrs.scala:36:7, :111:26, :297:27]
wire _T_36 = state == 5'h5; // @[mshrs.scala:107:22, :302:22]
wire _T_37 = state == 5'h6; // @[mshrs.scala:107:22, :304:22]
wire [3:0] _needs_wb_r_T_6 = {2'h2, io_meta_resp_bits_coh_state_0}; // @[Metadata.scala:120:19]
wire _needs_wb_r_T_19 = _needs_wb_r_T_6 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_21 = _needs_wb_r_T_19 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_23 = _needs_wb_r_T_6 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_25 = _needs_wb_r_T_23 ? 3'h2 : _needs_wb_r_T_21; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_27 = _needs_wb_r_T_6 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _needs_wb_r_T_29 = _needs_wb_r_T_27 ? 3'h1 : _needs_wb_r_T_25; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_31 = _needs_wb_r_T_6 == 4'hB; // @[Misc.scala:56:20]
wire _needs_wb_r_T_32 = _needs_wb_r_T_31; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_33 = _needs_wb_r_T_31 ? 3'h1 : _needs_wb_r_T_29; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_35 = _needs_wb_r_T_6 == 4'h4; // @[Misc.scala:56:20]
wire _needs_wb_r_T_36 = ~_needs_wb_r_T_35 & _needs_wb_r_T_32; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_37 = _needs_wb_r_T_35 ? 3'h5 : _needs_wb_r_T_33; // @[Misc.scala:38:36, :56:20]
wire _needs_wb_r_T_39 = _needs_wb_r_T_6 == 4'h5; // @[Misc.scala:56:20]
wire _needs_wb_r_T_40 = ~_needs_wb_r_T_39 & _needs_wb_r_T_36; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_41 = _needs_wb_r_T_39 ? 3'h4 : _needs_wb_r_T_37; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_42 = {1'h0, _needs_wb_r_T_39}; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_43 = _needs_wb_r_T_6 == 4'h6; // @[Misc.scala:56:20]
wire _needs_wb_r_T_44 = ~_needs_wb_r_T_43 & _needs_wb_r_T_40; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_45 = _needs_wb_r_T_43 ? 3'h0 : _needs_wb_r_T_41; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_46 = _needs_wb_r_T_43 ? 2'h1 : _needs_wb_r_T_42; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_47 = _needs_wb_r_T_6 == 4'h7; // @[Misc.scala:56:20]
wire _needs_wb_r_T_48 = _needs_wb_r_T_47 | _needs_wb_r_T_44; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_49 = _needs_wb_r_T_47 ? 3'h0 : _needs_wb_r_T_45; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_50 = _needs_wb_r_T_47 ? 2'h1 : _needs_wb_r_T_46; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_51 = _needs_wb_r_T_6 == 4'h0; // @[Misc.scala:56:20]
wire _needs_wb_r_T_52 = ~_needs_wb_r_T_51 & _needs_wb_r_T_48; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_53 = _needs_wb_r_T_51 ? 3'h5 : _needs_wb_r_T_49; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_54 = _needs_wb_r_T_51 ? 2'h0 : _needs_wb_r_T_50; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_55 = _needs_wb_r_T_6 == 4'h1; // @[Misc.scala:56:20]
wire _needs_wb_r_T_56 = ~_needs_wb_r_T_55 & _needs_wb_r_T_52; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_57 = _needs_wb_r_T_55 ? 3'h4 : _needs_wb_r_T_53; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_58 = _needs_wb_r_T_55 ? 2'h1 : _needs_wb_r_T_54; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_59 = _needs_wb_r_T_6 == 4'h2; // @[Misc.scala:56:20]
wire _needs_wb_r_T_60 = ~_needs_wb_r_T_59 & _needs_wb_r_T_56; // @[Misc.scala:38:9, :56:20]
wire [2:0] _needs_wb_r_T_61 = _needs_wb_r_T_59 ? 3'h3 : _needs_wb_r_T_57; // @[Misc.scala:38:36, :56:20]
wire [1:0] _needs_wb_r_T_62 = _needs_wb_r_T_59 ? 2'h2 : _needs_wb_r_T_58; // @[Misc.scala:38:63, :56:20]
wire _needs_wb_r_T_63 = _needs_wb_r_T_6 == 4'h3; // @[Misc.scala:56:20]
wire needs_wb = _needs_wb_r_T_63 | _needs_wb_r_T_60; // @[Misc.scala:38:9, :56:20]
wire [2:0] needs_wb_r_2 = _needs_wb_r_T_63 ? 3'h3 : _needs_wb_r_T_61; // @[Misc.scala:38:36, :56:20]
wire [1:0] needs_wb_r_3 = _needs_wb_r_T_63 ? 2'h2 : _needs_wb_r_T_62; // @[Misc.scala:38:63, :56:20]
wire [1:0] needs_wb_meta_state = needs_wb_r_3; // @[Misc.scala:38:63]
wire _state_T_30 = ~io_meta_resp_valid_0; // @[mshrs.scala:36:7, :306:18]
wire [4:0] _state_T_31 = needs_wb ? 5'h7 : 5'hB; // @[Misc.scala:38:9]
wire [4:0] _state_T_32 = _state_T_30 ? 5'h4 : _state_T_31; // @[mshrs.scala:306:{17,18}, :307:17]
wire _T_38 = state == 5'h7; // @[mshrs.scala:107:22, :308:22]
wire _T_40 = state == 5'h9; // @[mshrs.scala:107:22, :318:22]
assign io_wb_req_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38) & _T_40; // @[package.scala:16:47]
wire _T_42 = state == 5'hA; // @[mshrs.scala:107:22, :330:22]
wire _T_43 = state == 5'hB; // @[mshrs.scala:107:22, :334:22]
wire _GEN_43 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42; // @[mshrs.scala:148:129, :179:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:41]
assign io_lb_read_valid_0 = ~_GEN_42 & (_io_probe_rdy_T_4 ? _io_lb_read_valid_T : ~_GEN_43 & _T_43); // @[package.scala:16:47]
assign io_lb_read_bits_offset_0 = _io_probe_rdy_T_4 ? _io_lb_read_bits_offset_T[2:0] : refill_ctr; // @[package.scala:16:47]
wire _GEN_44 = _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _GEN_43; // @[package.scala:16:47]
assign io_refill_valid_0 = ~(~(|state) | _GEN_44) & _T_43 & _io_refill_valid_T; // @[Decoupled.scala:51:35]
wire [5:0] _io_refill_bits_addr_T = {refill_ctr, 3'h0}; // @[mshrs.scala:139:24, :340:59]
wire [33:0] _io_refill_bits_addr_T_1 = {req_block_addr[33:6], req_block_addr[5:0] | _io_refill_bits_addr_T}; // @[mshrs.scala:112:51, :340:{45,59}]
assign io_refill_bits_addr_0 = _io_refill_bits_addr_T_1[9:0]; // @[mshrs.scala:36:7, :340:{27,45}]
wire [3:0] _refill_ctr_T = {1'h0, refill_ctr} + 4'h1; // @[mshrs.scala:139:24, :345:32]
wire [2:0] _refill_ctr_T_1 = _refill_ctr_T[2:0]; // @[mshrs.scala:345:32]
wire _T_46 = state == 5'hC; // @[mshrs.scala:107:22, :350:22]
wire _GEN_45 = _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43; // @[mshrs.scala:148:129, :164:26, :294:39, :302:{22,41}, :304:{22,41}, :308:{22,40}, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:39]
wire _GEN_46 = _io_probe_rdy_T_4 | _GEN_45; // @[package.scala:16:47]
assign io_replay_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_46) & _T_46 & _rpq_io_deq_valid; // @[package.scala:16:47]
assign rpq_io_deq_ready = ~_GEN_42 & (_io_probe_rdy_T_4 ? _rpq_io_deq_ready_T_1 : ~_GEN_45 & _T_46 & io_replay_ready_0); // @[package.scala:16:47]
wire [5:0] _io_replay_bits_addr_T = _rpq_io_deq_bits_addr[5:0]; // @[mshrs.scala:128:19, :353:70]
assign _io_replay_bits_addr_T_1 = {io_replay_bits_addr_hi, _io_replay_bits_addr_T}; // @[mshrs.scala:353:{31,70}]
assign io_replay_bits_addr_0 = _io_replay_bits_addr_T_1; // @[mshrs.scala:36:7, :353:31]
wire _T_48 = _rpq_io_deq_bits_uop_mem_cmd == 5'h1; // @[Consts.scala:90:32]
wire _r_c_cat_T; // @[Consts.scala:90:32]
assign _r_c_cat_T = _T_48; // @[Consts.scala:90:32]
wire _r_c_cat_T_23; // @[Consts.scala:90:32]
assign _r_c_cat_T_23 = _T_48; // @[Consts.scala:90:32]
wire _T_49 = _rpq_io_deq_bits_uop_mem_cmd == 5'h11; // @[Consts.scala:90:49]
wire _r_c_cat_T_1; // @[Consts.scala:90:49]
assign _r_c_cat_T_1 = _T_49; // @[Consts.scala:90:49]
wire _r_c_cat_T_24; // @[Consts.scala:90:49]
assign _r_c_cat_T_24 = _T_49; // @[Consts.scala:90:49]
wire _T_51 = _rpq_io_deq_bits_uop_mem_cmd == 5'h7; // @[Consts.scala:90:66]
wire _r_c_cat_T_3; // @[Consts.scala:90:66]
assign _r_c_cat_T_3 = _T_51; // @[Consts.scala:90:66]
wire _r_c_cat_T_26; // @[Consts.scala:90:66]
assign _r_c_cat_T_26 = _T_51; // @[Consts.scala:90:66]
wire _T_53 = _rpq_io_deq_bits_uop_mem_cmd == 5'h4; // @[package.scala:16:47]
wire _r_c_cat_T_5; // @[package.scala:16:47]
assign _r_c_cat_T_5 = _T_53; // @[package.scala:16:47]
wire _r_c_cat_T_28; // @[package.scala:16:47]
assign _r_c_cat_T_28 = _T_53; // @[package.scala:16:47]
wire _T_54 = _rpq_io_deq_bits_uop_mem_cmd == 5'h9; // @[package.scala:16:47]
wire _r_c_cat_T_6; // @[package.scala:16:47]
assign _r_c_cat_T_6 = _T_54; // @[package.scala:16:47]
wire _r_c_cat_T_29; // @[package.scala:16:47]
assign _r_c_cat_T_29 = _T_54; // @[package.scala:16:47]
wire _T_55 = _rpq_io_deq_bits_uop_mem_cmd == 5'hA; // @[package.scala:16:47]
wire _r_c_cat_T_7; // @[package.scala:16:47]
assign _r_c_cat_T_7 = _T_55; // @[package.scala:16:47]
wire _r_c_cat_T_30; // @[package.scala:16:47]
assign _r_c_cat_T_30 = _T_55; // @[package.scala:16:47]
wire _T_56 = _rpq_io_deq_bits_uop_mem_cmd == 5'hB; // @[package.scala:16:47]
wire _r_c_cat_T_8; // @[package.scala:16:47]
assign _r_c_cat_T_8 = _T_56; // @[package.scala:16:47]
wire _r_c_cat_T_31; // @[package.scala:16:47]
assign _r_c_cat_T_31 = _T_56; // @[package.scala:16:47]
wire _T_60 = _rpq_io_deq_bits_uop_mem_cmd == 5'h8; // @[package.scala:16:47]
wire _r_c_cat_T_12; // @[package.scala:16:47]
assign _r_c_cat_T_12 = _T_60; // @[package.scala:16:47]
wire _r_c_cat_T_35; // @[package.scala:16:47]
assign _r_c_cat_T_35 = _T_60; // @[package.scala:16:47]
wire _T_61 = _rpq_io_deq_bits_uop_mem_cmd == 5'hC; // @[package.scala:16:47]
wire _r_c_cat_T_13; // @[package.scala:16:47]
assign _r_c_cat_T_13 = _T_61; // @[package.scala:16:47]
wire _r_c_cat_T_36; // @[package.scala:16:47]
assign _r_c_cat_T_36 = _T_61; // @[package.scala:16:47]
wire _T_62 = _rpq_io_deq_bits_uop_mem_cmd == 5'hD; // @[package.scala:16:47]
wire _r_c_cat_T_14; // @[package.scala:16:47]
assign _r_c_cat_T_14 = _T_62; // @[package.scala:16:47]
wire _r_c_cat_T_37; // @[package.scala:16:47]
assign _r_c_cat_T_37 = _T_62; // @[package.scala:16:47]
wire _T_63 = _rpq_io_deq_bits_uop_mem_cmd == 5'hE; // @[package.scala:16:47]
wire _r_c_cat_T_15; // @[package.scala:16:47]
assign _r_c_cat_T_15 = _T_63; // @[package.scala:16:47]
wire _r_c_cat_T_38; // @[package.scala:16:47]
assign _r_c_cat_T_38 = _T_63; // @[package.scala:16:47]
wire _T_64 = _rpq_io_deq_bits_uop_mem_cmd == 5'hF; // @[package.scala:16:47]
wire _r_c_cat_T_16; // @[package.scala:16:47]
assign _r_c_cat_T_16 = _T_64; // @[package.scala:16:47]
wire _r_c_cat_T_39; // @[package.scala:16:47]
assign _r_c_cat_T_39 = _T_64; // @[package.scala:16:47]
wire _T_71 = io_replay_ready_0 & io_replay_valid_0 & (_T_48 | _T_49 | _T_51 | _T_53 | _T_54 | _T_55 | _T_56 | _T_60 | _T_61 | _T_62 | _T_63 | _T_64); // @[Decoupled.scala:51:35]
wire _r_c_cat_T_2 = _r_c_cat_T | _r_c_cat_T_1; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_4 = _r_c_cat_T_2 | _r_c_cat_T_3; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_9 = _r_c_cat_T_5 | _r_c_cat_T_6; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_10 = _r_c_cat_T_9 | _r_c_cat_T_7; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_11 = _r_c_cat_T_10 | _r_c_cat_T_8; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_17 = _r_c_cat_T_12 | _r_c_cat_T_13; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_18 = _r_c_cat_T_17 | _r_c_cat_T_14; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_19 = _r_c_cat_T_18 | _r_c_cat_T_15; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_20 = _r_c_cat_T_19 | _r_c_cat_T_16; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_21 = _r_c_cat_T_11 | _r_c_cat_T_20; // @[package.scala:81:59]
wire _r_c_cat_T_22 = _r_c_cat_T_4 | _r_c_cat_T_21; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_25 = _r_c_cat_T_23 | _r_c_cat_T_24; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_27 = _r_c_cat_T_25 | _r_c_cat_T_26; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_32 = _r_c_cat_T_28 | _r_c_cat_T_29; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_33 = _r_c_cat_T_32 | _r_c_cat_T_30; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_34 = _r_c_cat_T_33 | _r_c_cat_T_31; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_40 = _r_c_cat_T_35 | _r_c_cat_T_36; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_41 = _r_c_cat_T_40 | _r_c_cat_T_37; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_42 = _r_c_cat_T_41 | _r_c_cat_T_38; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_43 = _r_c_cat_T_42 | _r_c_cat_T_39; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_44 = _r_c_cat_T_34 | _r_c_cat_T_43; // @[package.scala:81:59]
wire _r_c_cat_T_45 = _r_c_cat_T_27 | _r_c_cat_T_44; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_46 = _rpq_io_deq_bits_uop_mem_cmd == 5'h3; // @[Consts.scala:91:54]
wire _r_c_cat_T_47 = _r_c_cat_T_45 | _r_c_cat_T_46; // @[Consts.scala:90:76, :91:{47,54}]
wire _r_c_cat_T_49 = _r_c_cat_T_47 | _r_c_cat_T_48; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r_c = {_r_c_cat_T_22, _r_c_cat_T_49}; // @[Metadata.scala:29:18]
wire [3:0] _r_T_64 = {r_c, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r_T_89 = _r_T_64 == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r_T_91 = {1'h0, _r_T_89}; // @[Misc.scala:35:36, :49:20]
wire _r_T_92 = _r_T_64 == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r_T_94 = _r_T_92 ? 2'h2 : _r_T_91; // @[Misc.scala:35:36, :49:20]
wire _r_T_95 = _r_T_64 == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r_T_97 = _r_T_95 ? 2'h1 : _r_T_94; // @[Misc.scala:35:36, :49:20]
wire _r_T_98 = _r_T_64 == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r_T_100 = _r_T_98 ? 2'h2 : _r_T_97; // @[Misc.scala:35:36, :49:20]
wire _r_T_101 = _r_T_64 == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r_T_103 = _r_T_101 ? 2'h0 : _r_T_100; // @[Misc.scala:35:36, :49:20]
wire _r_T_104 = _r_T_64 == 4'hE; // @[Misc.scala:49:20]
wire _r_T_105 = _r_T_104; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_106 = _r_T_104 ? 2'h3 : _r_T_103; // @[Misc.scala:35:36, :49:20]
wire _r_T_107 = &_r_T_64; // @[Misc.scala:49:20]
wire _r_T_108 = _r_T_107 | _r_T_105; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_109 = _r_T_107 ? 2'h3 : _r_T_106; // @[Misc.scala:35:36, :49:20]
wire _r_T_110 = _r_T_64 == 4'h6; // @[Misc.scala:49:20]
wire _r_T_111 = _r_T_110 | _r_T_108; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_112 = _r_T_110 ? 2'h2 : _r_T_109; // @[Misc.scala:35:36, :49:20]
wire _r_T_113 = _r_T_64 == 4'h7; // @[Misc.scala:49:20]
wire _r_T_114 = _r_T_113 | _r_T_111; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_115 = _r_T_113 ? 2'h3 : _r_T_112; // @[Misc.scala:35:36, :49:20]
wire _r_T_116 = _r_T_64 == 4'h1; // @[Misc.scala:49:20]
wire _r_T_117 = _r_T_116 | _r_T_114; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_118 = _r_T_116 ? 2'h1 : _r_T_115; // @[Misc.scala:35:36, :49:20]
wire _r_T_119 = _r_T_64 == 4'h2; // @[Misc.scala:49:20]
wire _r_T_120 = _r_T_119 | _r_T_117; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_121 = _r_T_119 ? 2'h2 : _r_T_118; // @[Misc.scala:35:36, :49:20]
wire _r_T_122 = _r_T_64 == 4'h3; // @[Misc.scala:49:20]
wire is_hit = _r_T_122 | _r_T_120; // @[Misc.scala:35:9, :49:20]
wire [1:0] r_2_1 = _r_T_122 ? 2'h3 : _r_T_121; // @[Misc.scala:35:36, :49:20]
wire [1:0] coh_on_hit_state = r_2_1; // @[Misc.scala:35:36]
wire _GEN_47 = _T_40 | _T_42 | _T_43 | _T_46; // @[mshrs.scala:156:26, :318:{22,36}, :330:{22,37}, :334:{22,41}, :350:{22,39}, :363:44]
assign io_meta_write_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37) & (_T_38 | ~_GEN_47 & _sec_rdy_T_4); // @[package.scala:16:47]
assign io_meta_write_bits_data_coh_state_0 = _T_38 ? coh_on_clear_state : new_coh_state; // @[Metadata.scala:160:20]
wire _GEN_48 = _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43 | _T_46 | _sec_rdy_T_4; // @[package.scala:16:47]
assign io_mem_finish_valid_0 = ~(~(|state) | _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_48) & _sec_rdy_T_5 & grantack_valid; // @[package.scala:16:47]
wire [4:0] _state_T_33 = finish_to_prefetch ? 5'h11 : 5'h0; // @[mshrs.scala:142:31, :381:17]
wire _GEN_49 = _sec_rdy_T_4 | _sec_rdy_T_5 | _sec_rdy_T_6; // @[package.scala:16:47]
wire _GEN_50 = _T_46 | _GEN_49; // @[mshrs.scala:158:26, :350:{22,39}, :363:44, :373:42, :380:42, :382:38]
wire _GEN_51 = _io_probe_rdy_T_4 | _io_probe_rdy_T_8 | _T_36 | _T_37 | _T_38 | _T_40 | _T_42 | _T_43 | _GEN_50; // @[package.scala:16:47]
wire _GEN_52 = _io_probe_rdy_T_2 | _io_probe_rdy_T_3 | _GEN_51; // @[package.scala:16:47]
assign io_req_pri_rdy_0 = ~(|state) | ~_GEN_52 & _io_way_valid_T_1; // @[package.scala:16:47]
wire _T_87 = io_req_sec_val_0 & ~io_req_sec_rdy_0 | io_clear_prefetch_0; // @[mshrs.scala:36:7, :384:{27,30,47}]
wire _r_c_cat_T_52 = _r_c_cat_T_50 | _r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_54 = _r_c_cat_T_52 | _r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_59 = _r_c_cat_T_55 | _r_c_cat_T_56; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_60 = _r_c_cat_T_59 | _r_c_cat_T_57; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_61 = _r_c_cat_T_60 | _r_c_cat_T_58; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_67 = _r_c_cat_T_62 | _r_c_cat_T_63; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_68 = _r_c_cat_T_67 | _r_c_cat_T_64; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_69 = _r_c_cat_T_68 | _r_c_cat_T_65; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_70 = _r_c_cat_T_69 | _r_c_cat_T_66; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_71 = _r_c_cat_T_61 | _r_c_cat_T_70; // @[package.scala:81:59]
wire _r_c_cat_T_72 = _r_c_cat_T_54 | _r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_75 = _r_c_cat_T_73 | _r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}]
wire _r_c_cat_T_77 = _r_c_cat_T_75 | _r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}]
wire _r_c_cat_T_82 = _r_c_cat_T_78 | _r_c_cat_T_79; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_83 = _r_c_cat_T_82 | _r_c_cat_T_80; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_84 = _r_c_cat_T_83 | _r_c_cat_T_81; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_90 = _r_c_cat_T_85 | _r_c_cat_T_86; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_91 = _r_c_cat_T_90 | _r_c_cat_T_87; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_92 = _r_c_cat_T_91 | _r_c_cat_T_88; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_93 = _r_c_cat_T_92 | _r_c_cat_T_89; // @[package.scala:16:47, :81:59]
wire _r_c_cat_T_94 = _r_c_cat_T_84 | _r_c_cat_T_93; // @[package.scala:81:59]
wire _r_c_cat_T_95 = _r_c_cat_T_77 | _r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}]
wire _r_c_cat_T_97 = _r_c_cat_T_95 | _r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}]
wire _r_c_cat_T_99 = _r_c_cat_T_97 | _r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}]
wire [1:0] r_c_1 = {_r_c_cat_T_72, _r_c_cat_T_99}; // @[Metadata.scala:29:18]
wire [3:0] _r_T_123 = {r_c_1, new_coh_state}; // @[Metadata.scala:29:18, :58:19]
wire _r_T_148 = _r_T_123 == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _r_T_150 = {1'h0, _r_T_148}; // @[Misc.scala:35:36, :49:20]
wire _r_T_151 = _r_T_123 == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _r_T_153 = _r_T_151 ? 2'h2 : _r_T_150; // @[Misc.scala:35:36, :49:20]
wire _r_T_154 = _r_T_123 == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _r_T_156 = _r_T_154 ? 2'h1 : _r_T_153; // @[Misc.scala:35:36, :49:20]
wire _r_T_157 = _r_T_123 == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _r_T_159 = _r_T_157 ? 2'h2 : _r_T_156; // @[Misc.scala:35:36, :49:20]
wire _r_T_160 = _r_T_123 == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _r_T_162 = _r_T_160 ? 2'h0 : _r_T_159; // @[Misc.scala:35:36, :49:20]
wire _r_T_163 = _r_T_123 == 4'hE; // @[Misc.scala:49:20]
wire _r_T_164 = _r_T_163; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_165 = _r_T_163 ? 2'h3 : _r_T_162; // @[Misc.scala:35:36, :49:20]
wire _r_T_166 = &_r_T_123; // @[Misc.scala:49:20]
wire _r_T_167 = _r_T_166 | _r_T_164; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_168 = _r_T_166 ? 2'h3 : _r_T_165; // @[Misc.scala:35:36, :49:20]
wire _r_T_169 = _r_T_123 == 4'h6; // @[Misc.scala:49:20]
wire _r_T_170 = _r_T_169 | _r_T_167; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_171 = _r_T_169 ? 2'h2 : _r_T_168; // @[Misc.scala:35:36, :49:20]
wire _r_T_172 = _r_T_123 == 4'h7; // @[Misc.scala:49:20]
wire _r_T_173 = _r_T_172 | _r_T_170; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_174 = _r_T_172 ? 2'h3 : _r_T_171; // @[Misc.scala:35:36, :49:20]
wire _r_T_175 = _r_T_123 == 4'h1; // @[Misc.scala:49:20]
wire _r_T_176 = _r_T_175 | _r_T_173; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_177 = _r_T_175 ? 2'h1 : _r_T_174; // @[Misc.scala:35:36, :49:20]
wire _r_T_178 = _r_T_123 == 4'h2; // @[Misc.scala:49:20]
wire _r_T_179 = _r_T_178 | _r_T_176; // @[Misc.scala:35:9, :49:20]
wire [1:0] _r_T_180 = _r_T_178 ? 2'h2 : _r_T_177; // @[Misc.scala:35:36, :49:20]
wire _r_T_181 = _r_T_123 == 4'h3; // @[Misc.scala:49:20]
wire is_hit_1 = _r_T_181 | _r_T_179; // @[Misc.scala:35:9, :49:20]
wire [1:0] r_2_2 = _r_T_181 ? 2'h3 : _r_T_180; // @[Misc.scala:35:36, :49:20]
wire [1:0] coh_on_hit_1_state = r_2_2; // @[Misc.scala:35:36]
wire [4:0] state_new_state_1; // @[mshrs.scala:191:29]
wire _state_T_35 = ~_state_T_34; // @[mshrs.scala:194:11]
wire _state_T_36 = ~_rpq_io_enq_ready; // @[mshrs.scala:128:19, :194:11]
wire _state_req_needs_wb_r_T_83 = _state_req_needs_wb_r_T_70 == 4'h8; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_85 = _state_req_needs_wb_r_T_83 ? 3'h5 : 3'h0; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_87 = _state_req_needs_wb_r_T_70 == 4'h9; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_89 = _state_req_needs_wb_r_T_87 ? 3'h2 : _state_req_needs_wb_r_T_85; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_91 = _state_req_needs_wb_r_T_70 == 4'hA; // @[Misc.scala:56:20]
wire [2:0] _state_req_needs_wb_r_T_93 = _state_req_needs_wb_r_T_91 ? 3'h1 : _state_req_needs_wb_r_T_89; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_95 = _state_req_needs_wb_r_T_70 == 4'hB; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_96 = _state_req_needs_wb_r_T_95; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_97 = _state_req_needs_wb_r_T_95 ? 3'h1 : _state_req_needs_wb_r_T_93; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_99 = _state_req_needs_wb_r_T_70 == 4'h4; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_100 = ~_state_req_needs_wb_r_T_99 & _state_req_needs_wb_r_T_96; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_101 = _state_req_needs_wb_r_T_99 ? 3'h5 : _state_req_needs_wb_r_T_97; // @[Misc.scala:38:36, :56:20]
wire _state_req_needs_wb_r_T_103 = _state_req_needs_wb_r_T_70 == 4'h5; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_104 = ~_state_req_needs_wb_r_T_103 & _state_req_needs_wb_r_T_100; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_105 = _state_req_needs_wb_r_T_103 ? 3'h4 : _state_req_needs_wb_r_T_101; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_106 = {1'h0, _state_req_needs_wb_r_T_103}; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_107 = _state_req_needs_wb_r_T_70 == 4'h6; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_108 = ~_state_req_needs_wb_r_T_107 & _state_req_needs_wb_r_T_104; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_109 = _state_req_needs_wb_r_T_107 ? 3'h0 : _state_req_needs_wb_r_T_105; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_110 = _state_req_needs_wb_r_T_107 ? 2'h1 : _state_req_needs_wb_r_T_106; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_111 = _state_req_needs_wb_r_T_70 == 4'h7; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_112 = _state_req_needs_wb_r_T_111 | _state_req_needs_wb_r_T_108; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_113 = _state_req_needs_wb_r_T_111 ? 3'h0 : _state_req_needs_wb_r_T_109; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_114 = _state_req_needs_wb_r_T_111 ? 2'h1 : _state_req_needs_wb_r_T_110; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_115 = _state_req_needs_wb_r_T_70 == 4'h0; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_116 = ~_state_req_needs_wb_r_T_115 & _state_req_needs_wb_r_T_112; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_117 = _state_req_needs_wb_r_T_115 ? 3'h5 : _state_req_needs_wb_r_T_113; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_118 = _state_req_needs_wb_r_T_115 ? 2'h0 : _state_req_needs_wb_r_T_114; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_119 = _state_req_needs_wb_r_T_70 == 4'h1; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_120 = ~_state_req_needs_wb_r_T_119 & _state_req_needs_wb_r_T_116; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_121 = _state_req_needs_wb_r_T_119 ? 3'h4 : _state_req_needs_wb_r_T_117; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_122 = _state_req_needs_wb_r_T_119 ? 2'h1 : _state_req_needs_wb_r_T_118; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_123 = _state_req_needs_wb_r_T_70 == 4'h2; // @[Misc.scala:56:20]
wire _state_req_needs_wb_r_T_124 = ~_state_req_needs_wb_r_T_123 & _state_req_needs_wb_r_T_120; // @[Misc.scala:38:9, :56:20]
wire [2:0] _state_req_needs_wb_r_T_125 = _state_req_needs_wb_r_T_123 ? 3'h3 : _state_req_needs_wb_r_T_121; // @[Misc.scala:38:36, :56:20]
wire [1:0] _state_req_needs_wb_r_T_126 = _state_req_needs_wb_r_T_123 ? 2'h2 : _state_req_needs_wb_r_T_122; // @[Misc.scala:38:63, :56:20]
wire _state_req_needs_wb_r_T_127 = _state_req_needs_wb_r_T_70 == 4'h3; // @[Misc.scala:56:20]
wire state_req_needs_wb_r_1_1 = _state_req_needs_wb_r_T_127 | _state_req_needs_wb_r_T_124; // @[Misc.scala:38:9, :56:20]
wire [2:0] state_req_needs_wb_r_2_1 = _state_req_needs_wb_r_T_127 ? 3'h3 : _state_req_needs_wb_r_T_125; // @[Misc.scala:38:36, :56:20]
wire [1:0] state_req_needs_wb_r_3_1 = _state_req_needs_wb_r_T_127 ? 2'h2 : _state_req_needs_wb_r_T_126; // @[Misc.scala:38:63, :56:20]
wire [1:0] state_req_needs_wb_meta_1_state = state_req_needs_wb_r_3_1; // @[Misc.scala:38:63]
wire _state_r_c_cat_T_52 = _state_r_c_cat_T_50 | _state_r_c_cat_T_51; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_54 = _state_r_c_cat_T_52 | _state_r_c_cat_T_53; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_59 = _state_r_c_cat_T_55 | _state_r_c_cat_T_56; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_60 = _state_r_c_cat_T_59 | _state_r_c_cat_T_57; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_61 = _state_r_c_cat_T_60 | _state_r_c_cat_T_58; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_67 = _state_r_c_cat_T_62 | _state_r_c_cat_T_63; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_68 = _state_r_c_cat_T_67 | _state_r_c_cat_T_64; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_69 = _state_r_c_cat_T_68 | _state_r_c_cat_T_65; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_70 = _state_r_c_cat_T_69 | _state_r_c_cat_T_66; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_71 = _state_r_c_cat_T_61 | _state_r_c_cat_T_70; // @[package.scala:81:59]
wire _state_r_c_cat_T_72 = _state_r_c_cat_T_54 | _state_r_c_cat_T_71; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_75 = _state_r_c_cat_T_73 | _state_r_c_cat_T_74; // @[Consts.scala:90:{32,42,49}]
wire _state_r_c_cat_T_77 = _state_r_c_cat_T_75 | _state_r_c_cat_T_76; // @[Consts.scala:90:{42,59,66}]
wire _state_r_c_cat_T_82 = _state_r_c_cat_T_78 | _state_r_c_cat_T_79; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_83 = _state_r_c_cat_T_82 | _state_r_c_cat_T_80; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_84 = _state_r_c_cat_T_83 | _state_r_c_cat_T_81; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_90 = _state_r_c_cat_T_85 | _state_r_c_cat_T_86; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_91 = _state_r_c_cat_T_90 | _state_r_c_cat_T_87; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_92 = _state_r_c_cat_T_91 | _state_r_c_cat_T_88; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_93 = _state_r_c_cat_T_92 | _state_r_c_cat_T_89; // @[package.scala:16:47, :81:59]
wire _state_r_c_cat_T_94 = _state_r_c_cat_T_84 | _state_r_c_cat_T_93; // @[package.scala:81:59]
wire _state_r_c_cat_T_95 = _state_r_c_cat_T_77 | _state_r_c_cat_T_94; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_r_c_cat_T_97 = _state_r_c_cat_T_95 | _state_r_c_cat_T_96; // @[Consts.scala:90:76, :91:{47,54}]
wire _state_r_c_cat_T_99 = _state_r_c_cat_T_97 | _state_r_c_cat_T_98; // @[Consts.scala:91:{47,64,71}]
wire [1:0] state_r_c_1 = {_state_r_c_cat_T_72, _state_r_c_cat_T_99}; // @[Metadata.scala:29:18]
wire [3:0] _state_r_T_59 = {state_r_c_1, io_req_old_meta_coh_state_0}; // @[Metadata.scala:29:18, :58:19]
wire _state_r_T_84 = _state_r_T_59 == 4'hC; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_86 = {1'h0, _state_r_T_84}; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_87 = _state_r_T_59 == 4'hD; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_89 = _state_r_T_87 ? 2'h2 : _state_r_T_86; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_90 = _state_r_T_59 == 4'h4; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_92 = _state_r_T_90 ? 2'h1 : _state_r_T_89; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_93 = _state_r_T_59 == 4'h5; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_95 = _state_r_T_93 ? 2'h2 : _state_r_T_92; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_96 = _state_r_T_59 == 4'h0; // @[Misc.scala:49:20]
wire [1:0] _state_r_T_98 = _state_r_T_96 ? 2'h0 : _state_r_T_95; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_99 = _state_r_T_59 == 4'hE; // @[Misc.scala:49:20]
wire _state_r_T_100 = _state_r_T_99; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_101 = _state_r_T_99 ? 2'h3 : _state_r_T_98; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_102 = &_state_r_T_59; // @[Misc.scala:49:20]
wire _state_r_T_103 = _state_r_T_102 | _state_r_T_100; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_104 = _state_r_T_102 ? 2'h3 : _state_r_T_101; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_105 = _state_r_T_59 == 4'h6; // @[Misc.scala:49:20]
wire _state_r_T_106 = _state_r_T_105 | _state_r_T_103; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_107 = _state_r_T_105 ? 2'h2 : _state_r_T_104; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_108 = _state_r_T_59 == 4'h7; // @[Misc.scala:49:20]
wire _state_r_T_109 = _state_r_T_108 | _state_r_T_106; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_110 = _state_r_T_108 ? 2'h3 : _state_r_T_107; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_111 = _state_r_T_59 == 4'h1; // @[Misc.scala:49:20]
wire _state_r_T_112 = _state_r_T_111 | _state_r_T_109; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_113 = _state_r_T_111 ? 2'h1 : _state_r_T_110; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_114 = _state_r_T_59 == 4'h2; // @[Misc.scala:49:20]
wire _state_r_T_115 = _state_r_T_114 | _state_r_T_112; // @[Misc.scala:35:9, :49:20]
wire [1:0] _state_r_T_116 = _state_r_T_114 ? 2'h2 : _state_r_T_113; // @[Misc.scala:35:36, :49:20]
wire _state_r_T_117 = _state_r_T_59 == 4'h3; // @[Misc.scala:49:20]
wire state_is_hit_1 = _state_r_T_117 | _state_r_T_115; // @[Misc.scala:35:9, :49:20]
wire [1:0] state_r_2_1 = _state_r_T_117 ? 2'h3 : _state_r_T_116; // @[Misc.scala:35:36, :49:20]
wire [1:0] state_coh_on_hit_1_state = state_r_2_1; // @[Misc.scala:35:36]
wire _state_T_39 = _state_T_37 | _state_T_38; // @[Consts.scala:90:{32,42,49}]
wire _state_T_41 = _state_T_39 | _state_T_40; // @[Consts.scala:90:{42,59,66}]
wire _state_T_46 = _state_T_42 | _state_T_43; // @[package.scala:16:47, :81:59]
wire _state_T_47 = _state_T_46 | _state_T_44; // @[package.scala:16:47, :81:59]
wire _state_T_48 = _state_T_47 | _state_T_45; // @[package.scala:16:47, :81:59]
wire _state_T_54 = _state_T_49 | _state_T_50; // @[package.scala:16:47, :81:59]
wire _state_T_55 = _state_T_54 | _state_T_51; // @[package.scala:16:47, :81:59]
wire _state_T_56 = _state_T_55 | _state_T_52; // @[package.scala:16:47, :81:59]
wire _state_T_57 = _state_T_56 | _state_T_53; // @[package.scala:16:47, :81:59]
wire _state_T_58 = _state_T_48 | _state_T_57; // @[package.scala:81:59]
wire _state_T_59 = _state_T_41 | _state_T_58; // @[Consts.scala:87:44, :90:{59,76}]
wire _state_T_61 = ~_state_T_60; // @[mshrs.scala:201:15]
wire _state_T_62 = ~_state_T_59; // @[Consts.scala:90:76] |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_291 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_291( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_43 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0))
node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 10, 0)
node _source_ok_T = shr(io.in.a.bits.source, 11)
node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0))
node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits)
node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2)
node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<11>(0h40f))
node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4)
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T_5
node _is_aligned_mask_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 2, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _uncommonBits_T = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits = bits(_uncommonBits_T, 10, 0)
node _T_4 = shr(io.in.a.bits.source, 11)
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = leq(UInt<1>(0h0), uncommonBits)
node _T_7 = and(_T_5, _T_6)
node _T_8 = leq(uncommonBits, UInt<11>(0h40f))
node _T_9 = and(_T_7, _T_8)
node _T_10 = eq(_T_9, UInt<1>(0h0))
node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_12 = cvt(_T_11)
node _T_13 = and(_T_12, asSInt(UInt<1>(0h0)))
node _T_14 = asSInt(_T_13)
node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0)))
node _T_16 = or(_T_10, _T_15)
node _T_17 = asUInt(reset)
node _T_18 = eq(_T_17, UInt<1>(0h0))
when _T_18 :
node _T_19 = eq(_T_16, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_16, UInt<1>(0h1), "") : assert_1
node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_20 :
node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_23 = and(_T_21, _T_22)
node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_1 = bits(_uncommonBits_T_1, 10, 0)
node _T_24 = shr(io.in.a.bits.source, 11)
node _T_25 = eq(_T_24, UInt<1>(0h0))
node _T_26 = leq(UInt<1>(0h0), uncommonBits_1)
node _T_27 = and(_T_25, _T_26)
node _T_28 = leq(uncommonBits_1, UInt<11>(0h40f))
node _T_29 = and(_T_27, _T_28)
node _T_30 = and(_T_23, _T_29)
node _T_31 = or(UInt<1>(0h0), _T_30)
node _T_32 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_33 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<27>(0h4000000)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = and(_T_32, _T_37)
node _T_39 = or(UInt<1>(0h0), _T_38)
node _T_40 = and(_T_31, _T_39)
node _T_41 = asUInt(reset)
node _T_42 = eq(_T_41, UInt<1>(0h0))
when _T_42 :
node _T_43 = eq(_T_40, UInt<1>(0h0))
when _T_43 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_40, UInt<1>(0h1), "") : assert_2
node _T_44 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_45 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_46 = and(_T_44, _T_45)
node _T_47 = or(UInt<1>(0h0), _T_46)
node _T_48 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<27>(0h4000000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = and(_T_47, _T_52)
node _T_54 = or(UInt<1>(0h0), _T_53)
node _T_55 = and(UInt<1>(0h0), _T_54)
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(_T_55, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_55, UInt<1>(0h1), "") : assert_3
node _T_59 = asUInt(reset)
node _T_60 = eq(_T_59, UInt<1>(0h0))
when _T_60 :
node _T_61 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_61 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_62 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_63 = asUInt(reset)
node _T_64 = eq(_T_63, UInt<1>(0h0))
when _T_64 :
node _T_65 = eq(_T_62, UInt<1>(0h0))
when _T_65 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_62, UInt<1>(0h1), "") : assert_5
node _T_66 = asUInt(reset)
node _T_67 = eq(_T_66, UInt<1>(0h0))
when _T_67 :
node _T_68 = eq(is_aligned, UInt<1>(0h0))
when _T_68 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_69 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_70 = asUInt(reset)
node _T_71 = eq(_T_70, UInt<1>(0h0))
when _T_71 :
node _T_72 = eq(_T_69, UInt<1>(0h0))
when _T_72 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_69, UInt<1>(0h1), "") : assert_7
node _T_73 = not(io.in.a.bits.mask)
node _T_74 = eq(_T_73, UInt<1>(0h0))
node _T_75 = asUInt(reset)
node _T_76 = eq(_T_75, UInt<1>(0h0))
when _T_76 :
node _T_77 = eq(_T_74, UInt<1>(0h0))
when _T_77 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_74, UInt<1>(0h1), "") : assert_8
node _T_78 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_79 = asUInt(reset)
node _T_80 = eq(_T_79, UInt<1>(0h0))
when _T_80 :
node _T_81 = eq(_T_78, UInt<1>(0h0))
when _T_81 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_78, UInt<1>(0h1), "") : assert_9
node _T_82 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_82 :
node _T_83 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_84 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_85 = and(_T_83, _T_84)
node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_2 = bits(_uncommonBits_T_2, 10, 0)
node _T_86 = shr(io.in.a.bits.source, 11)
node _T_87 = eq(_T_86, UInt<1>(0h0))
node _T_88 = leq(UInt<1>(0h0), uncommonBits_2)
node _T_89 = and(_T_87, _T_88)
node _T_90 = leq(uncommonBits_2, UInt<11>(0h40f))
node _T_91 = and(_T_89, _T_90)
node _T_92 = and(_T_85, _T_91)
node _T_93 = or(UInt<1>(0h0), _T_92)
node _T_94 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_95 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<27>(0h4000000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(_T_93, _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_102, UInt<1>(0h1), "") : assert_10
node _T_106 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_107 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_108 = and(_T_106, _T_107)
node _T_109 = or(UInt<1>(0h0), _T_108)
node _T_110 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_111 = cvt(_T_110)
node _T_112 = and(_T_111, asSInt(UInt<27>(0h4000000)))
node _T_113 = asSInt(_T_112)
node _T_114 = eq(_T_113, asSInt(UInt<1>(0h0)))
node _T_115 = and(_T_109, _T_114)
node _T_116 = or(UInt<1>(0h0), _T_115)
node _T_117 = and(UInt<1>(0h0), _T_116)
node _T_118 = asUInt(reset)
node _T_119 = eq(_T_118, UInt<1>(0h0))
when _T_119 :
node _T_120 = eq(_T_117, UInt<1>(0h0))
when _T_120 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_117, UInt<1>(0h1), "") : assert_11
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_124 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_125 = asUInt(reset)
node _T_126 = eq(_T_125, UInt<1>(0h0))
when _T_126 :
node _T_127 = eq(_T_124, UInt<1>(0h0))
when _T_127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_124, UInt<1>(0h1), "") : assert_13
node _T_128 = asUInt(reset)
node _T_129 = eq(_T_128, UInt<1>(0h0))
when _T_129 :
node _T_130 = eq(is_aligned, UInt<1>(0h0))
when _T_130 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_131 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_132 = asUInt(reset)
node _T_133 = eq(_T_132, UInt<1>(0h0))
when _T_133 :
node _T_134 = eq(_T_131, UInt<1>(0h0))
when _T_134 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_131, UInt<1>(0h1), "") : assert_15
node _T_135 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_136 = asUInt(reset)
node _T_137 = eq(_T_136, UInt<1>(0h0))
when _T_137 :
node _T_138 = eq(_T_135, UInt<1>(0h0))
when _T_138 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_135, UInt<1>(0h1), "") : assert_16
node _T_139 = not(io.in.a.bits.mask)
node _T_140 = eq(_T_139, UInt<1>(0h0))
node _T_141 = asUInt(reset)
node _T_142 = eq(_T_141, UInt<1>(0h0))
when _T_142 :
node _T_143 = eq(_T_140, UInt<1>(0h0))
when _T_143 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_140, UInt<1>(0h1), "") : assert_17
node _T_144 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_145 = asUInt(reset)
node _T_146 = eq(_T_145, UInt<1>(0h0))
when _T_146 :
node _T_147 = eq(_T_144, UInt<1>(0h0))
when _T_147 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_144, UInt<1>(0h1), "") : assert_18
node _T_148 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_148 :
node _T_149 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_150 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_151 = and(_T_149, _T_150)
node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_3 = bits(_uncommonBits_T_3, 10, 0)
node _T_152 = shr(io.in.a.bits.source, 11)
node _T_153 = eq(_T_152, UInt<1>(0h0))
node _T_154 = leq(UInt<1>(0h0), uncommonBits_3)
node _T_155 = and(_T_153, _T_154)
node _T_156 = leq(uncommonBits_3, UInt<11>(0h40f))
node _T_157 = and(_T_155, _T_156)
node _T_158 = and(_T_151, _T_157)
node _T_159 = or(UInt<1>(0h0), _T_158)
node _T_160 = asUInt(reset)
node _T_161 = eq(_T_160, UInt<1>(0h0))
when _T_161 :
node _T_162 = eq(_T_159, UInt<1>(0h0))
when _T_162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_159, UInt<1>(0h1), "") : assert_19
node _T_163 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_164 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_165 = and(_T_163, _T_164)
node _T_166 = or(UInt<1>(0h0), _T_165)
node _T_167 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_168 = cvt(_T_167)
node _T_169 = and(_T_168, asSInt(UInt<27>(0h4000000)))
node _T_170 = asSInt(_T_169)
node _T_171 = eq(_T_170, asSInt(UInt<1>(0h0)))
node _T_172 = and(_T_166, _T_171)
node _T_173 = or(UInt<1>(0h0), _T_172)
node _T_174 = asUInt(reset)
node _T_175 = eq(_T_174, UInt<1>(0h0))
when _T_175 :
node _T_176 = eq(_T_173, UInt<1>(0h0))
when _T_176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_173, UInt<1>(0h1), "") : assert_20
node _T_177 = asUInt(reset)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
node _T_179 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_179 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_180 = asUInt(reset)
node _T_181 = eq(_T_180, UInt<1>(0h0))
when _T_181 :
node _T_182 = eq(is_aligned, UInt<1>(0h0))
when _T_182 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_183 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_T_183, UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_183, UInt<1>(0h1), "") : assert_23
node _T_187 = eq(io.in.a.bits.mask, mask)
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_187, UInt<1>(0h1), "") : assert_24
node _T_191 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_192 = asUInt(reset)
node _T_193 = eq(_T_192, UInt<1>(0h0))
when _T_193 :
node _T_194 = eq(_T_191, UInt<1>(0h0))
when _T_194 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_191, UInt<1>(0h1), "") : assert_25
node _T_195 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_195 :
node _T_196 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_197 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_198 = and(_T_196, _T_197)
node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_4 = bits(_uncommonBits_T_4, 10, 0)
node _T_199 = shr(io.in.a.bits.source, 11)
node _T_200 = eq(_T_199, UInt<1>(0h0))
node _T_201 = leq(UInt<1>(0h0), uncommonBits_4)
node _T_202 = and(_T_200, _T_201)
node _T_203 = leq(uncommonBits_4, UInt<11>(0h40f))
node _T_204 = and(_T_202, _T_203)
node _T_205 = and(_T_198, _T_204)
node _T_206 = or(UInt<1>(0h0), _T_205)
node _T_207 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_208 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_209 = and(_T_207, _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_212 = cvt(_T_211)
node _T_213 = and(_T_212, asSInt(UInt<27>(0h4000000)))
node _T_214 = asSInt(_T_213)
node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0)))
node _T_216 = and(_T_210, _T_215)
node _T_217 = or(UInt<1>(0h0), _T_216)
node _T_218 = and(_T_206, _T_217)
node _T_219 = asUInt(reset)
node _T_220 = eq(_T_219, UInt<1>(0h0))
when _T_220 :
node _T_221 = eq(_T_218, UInt<1>(0h0))
when _T_221 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_218, UInt<1>(0h1), "") : assert_26
node _T_222 = asUInt(reset)
node _T_223 = eq(_T_222, UInt<1>(0h0))
when _T_223 :
node _T_224 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_224 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_225 = asUInt(reset)
node _T_226 = eq(_T_225, UInt<1>(0h0))
when _T_226 :
node _T_227 = eq(is_aligned, UInt<1>(0h0))
when _T_227 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_228 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(_T_228, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_228, UInt<1>(0h1), "") : assert_29
node _T_232 = eq(io.in.a.bits.mask, mask)
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_232, UInt<1>(0h1), "") : assert_30
node _T_236 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_236 :
node _T_237 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_238 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_239 = and(_T_237, _T_238)
node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_5 = bits(_uncommonBits_T_5, 10, 0)
node _T_240 = shr(io.in.a.bits.source, 11)
node _T_241 = eq(_T_240, UInt<1>(0h0))
node _T_242 = leq(UInt<1>(0h0), uncommonBits_5)
node _T_243 = and(_T_241, _T_242)
node _T_244 = leq(uncommonBits_5, UInt<11>(0h40f))
node _T_245 = and(_T_243, _T_244)
node _T_246 = and(_T_239, _T_245)
node _T_247 = or(UInt<1>(0h0), _T_246)
node _T_248 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_249 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_253 = cvt(_T_252)
node _T_254 = and(_T_253, asSInt(UInt<27>(0h4000000)))
node _T_255 = asSInt(_T_254)
node _T_256 = eq(_T_255, asSInt(UInt<1>(0h0)))
node _T_257 = and(_T_251, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = and(_T_247, _T_258)
node _T_260 = asUInt(reset)
node _T_261 = eq(_T_260, UInt<1>(0h0))
when _T_261 :
node _T_262 = eq(_T_259, UInt<1>(0h0))
when _T_262 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_259, UInt<1>(0h1), "") : assert_31
node _T_263 = asUInt(reset)
node _T_264 = eq(_T_263, UInt<1>(0h0))
when _T_264 :
node _T_265 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_265 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_266 = asUInt(reset)
node _T_267 = eq(_T_266, UInt<1>(0h0))
when _T_267 :
node _T_268 = eq(is_aligned, UInt<1>(0h0))
when _T_268 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_269 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_270 = asUInt(reset)
node _T_271 = eq(_T_270, UInt<1>(0h0))
when _T_271 :
node _T_272 = eq(_T_269, UInt<1>(0h0))
when _T_272 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_269, UInt<1>(0h1), "") : assert_34
node _T_273 = not(mask)
node _T_274 = and(io.in.a.bits.mask, _T_273)
node _T_275 = eq(_T_274, UInt<1>(0h0))
node _T_276 = asUInt(reset)
node _T_277 = eq(_T_276, UInt<1>(0h0))
when _T_277 :
node _T_278 = eq(_T_275, UInt<1>(0h0))
when _T_278 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_275, UInt<1>(0h1), "") : assert_35
node _T_279 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_279 :
node _T_280 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_281 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_282 = and(_T_280, _T_281)
node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_6 = bits(_uncommonBits_T_6, 10, 0)
node _T_283 = shr(io.in.a.bits.source, 11)
node _T_284 = eq(_T_283, UInt<1>(0h0))
node _T_285 = leq(UInt<1>(0h0), uncommonBits_6)
node _T_286 = and(_T_284, _T_285)
node _T_287 = leq(uncommonBits_6, UInt<11>(0h40f))
node _T_288 = and(_T_286, _T_287)
node _T_289 = and(_T_282, _T_288)
node _T_290 = or(UInt<1>(0h0), _T_289)
node _T_291 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_292 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_293 = cvt(_T_292)
node _T_294 = and(_T_293, asSInt(UInt<27>(0h4000000)))
node _T_295 = asSInt(_T_294)
node _T_296 = eq(_T_295, asSInt(UInt<1>(0h0)))
node _T_297 = and(_T_291, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = and(_T_290, _T_298)
node _T_300 = asUInt(reset)
node _T_301 = eq(_T_300, UInt<1>(0h0))
when _T_301 :
node _T_302 = eq(_T_299, UInt<1>(0h0))
when _T_302 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_299, UInt<1>(0h1), "") : assert_36
node _T_303 = asUInt(reset)
node _T_304 = eq(_T_303, UInt<1>(0h0))
when _T_304 :
node _T_305 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_305 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(is_aligned, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_309 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_309, UInt<1>(0h1), "") : assert_39
node _T_313 = eq(io.in.a.bits.mask, mask)
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_313, UInt<1>(0h1), "") : assert_40
node _T_317 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_317 :
node _T_318 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_319 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_320 = and(_T_318, _T_319)
node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_7 = bits(_uncommonBits_T_7, 10, 0)
node _T_321 = shr(io.in.a.bits.source, 11)
node _T_322 = eq(_T_321, UInt<1>(0h0))
node _T_323 = leq(UInt<1>(0h0), uncommonBits_7)
node _T_324 = and(_T_322, _T_323)
node _T_325 = leq(uncommonBits_7, UInt<11>(0h40f))
node _T_326 = and(_T_324, _T_325)
node _T_327 = and(_T_320, _T_326)
node _T_328 = or(UInt<1>(0h0), _T_327)
node _T_329 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_330 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_331 = cvt(_T_330)
node _T_332 = and(_T_331, asSInt(UInt<27>(0h4000000)))
node _T_333 = asSInt(_T_332)
node _T_334 = eq(_T_333, asSInt(UInt<1>(0h0)))
node _T_335 = and(_T_329, _T_334)
node _T_336 = or(UInt<1>(0h0), _T_335)
node _T_337 = and(_T_328, _T_336)
node _T_338 = asUInt(reset)
node _T_339 = eq(_T_338, UInt<1>(0h0))
when _T_339 :
node _T_340 = eq(_T_337, UInt<1>(0h0))
when _T_340 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_337, UInt<1>(0h1), "") : assert_41
node _T_341 = asUInt(reset)
node _T_342 = eq(_T_341, UInt<1>(0h0))
when _T_342 :
node _T_343 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_343 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(is_aligned, UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_347 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_347, UInt<1>(0h1), "") : assert_44
node _T_351 = eq(io.in.a.bits.mask, mask)
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_351, UInt<1>(0h1), "") : assert_45
node _T_355 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_355 :
node _T_356 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_357 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_358 = and(_T_356, _T_357)
node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<11>(0h0))
node uncommonBits_8 = bits(_uncommonBits_T_8, 10, 0)
node _T_359 = shr(io.in.a.bits.source, 11)
node _T_360 = eq(_T_359, UInt<1>(0h0))
node _T_361 = leq(UInt<1>(0h0), uncommonBits_8)
node _T_362 = and(_T_360, _T_361)
node _T_363 = leq(uncommonBits_8, UInt<11>(0h40f))
node _T_364 = and(_T_362, _T_363)
node _T_365 = and(_T_358, _T_364)
node _T_366 = or(UInt<1>(0h0), _T_365)
node _T_367 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_368 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_369 = cvt(_T_368)
node _T_370 = and(_T_369, asSInt(UInt<27>(0h4000000)))
node _T_371 = asSInt(_T_370)
node _T_372 = eq(_T_371, asSInt(UInt<1>(0h0)))
node _T_373 = and(_T_367, _T_372)
node _T_374 = or(UInt<1>(0h0), _T_373)
node _T_375 = and(_T_366, _T_374)
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_T_375, UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_375, UInt<1>(0h1), "") : assert_46
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_382 = asUInt(reset)
node _T_383 = eq(_T_382, UInt<1>(0h0))
when _T_383 :
node _T_384 = eq(is_aligned, UInt<1>(0h0))
when _T_384 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_385 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_386 = asUInt(reset)
node _T_387 = eq(_T_386, UInt<1>(0h0))
when _T_387 :
node _T_388 = eq(_T_385, UInt<1>(0h0))
when _T_388 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_385, UInt<1>(0h1), "") : assert_49
node _T_389 = eq(io.in.a.bits.mask, mask)
node _T_390 = asUInt(reset)
node _T_391 = eq(_T_390, UInt<1>(0h0))
when _T_391 :
node _T_392 = eq(_T_389, UInt<1>(0h0))
when _T_392 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_389, UInt<1>(0h1), "") : assert_50
node _T_393 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_394 = asUInt(reset)
node _T_395 = eq(_T_394, UInt<1>(0h0))
when _T_395 :
node _T_396 = eq(_T_393, UInt<1>(0h0))
when _T_396 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_393, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_397 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_398 = asUInt(reset)
node _T_399 = eq(_T_398, UInt<1>(0h0))
when _T_399 :
node _T_400 = eq(_T_397, UInt<1>(0h0))
when _T_400 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_397, UInt<1>(0h1), "") : assert_52
node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<11>(0h0))
node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 10, 0)
node _source_ok_T_6 = shr(io.in.d.bits.source, 11)
node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0))
node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1)
node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8)
node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<11>(0h40f))
node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10)
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_11
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_401 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_401 :
node _T_402 = asUInt(reset)
node _T_403 = eq(_T_402, UInt<1>(0h0))
when _T_403 :
node _T_404 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_404 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_405 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_406 = asUInt(reset)
node _T_407 = eq(_T_406, UInt<1>(0h0))
when _T_407 :
node _T_408 = eq(_T_405, UInt<1>(0h0))
when _T_408 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_405, UInt<1>(0h1), "") : assert_54
node _T_409 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_409, UInt<1>(0h1), "") : assert_55
node _T_413 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_414 = asUInt(reset)
node _T_415 = eq(_T_414, UInt<1>(0h0))
when _T_415 :
node _T_416 = eq(_T_413, UInt<1>(0h0))
when _T_416 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_413, UInt<1>(0h1), "") : assert_56
node _T_417 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_418 = asUInt(reset)
node _T_419 = eq(_T_418, UInt<1>(0h0))
when _T_419 :
node _T_420 = eq(_T_417, UInt<1>(0h0))
when _T_420 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_417, UInt<1>(0h1), "") : assert_57
node _T_421 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_421 :
node _T_422 = asUInt(reset)
node _T_423 = eq(_T_422, UInt<1>(0h0))
when _T_423 :
node _T_424 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_424 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(sink_ok, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_428 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_428, UInt<1>(0h1), "") : assert_60
node _T_432 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(_T_432, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_432, UInt<1>(0h1), "") : assert_61
node _T_436 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_436, UInt<1>(0h1), "") : assert_62
node _T_440 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_441 = asUInt(reset)
node _T_442 = eq(_T_441, UInt<1>(0h0))
when _T_442 :
node _T_443 = eq(_T_440, UInt<1>(0h0))
when _T_443 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_440, UInt<1>(0h1), "") : assert_63
node _T_444 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_445 = or(UInt<1>(0h0), _T_444)
node _T_446 = asUInt(reset)
node _T_447 = eq(_T_446, UInt<1>(0h0))
when _T_447 :
node _T_448 = eq(_T_445, UInt<1>(0h0))
when _T_448 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_445, UInt<1>(0h1), "") : assert_64
node _T_449 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_449 :
node _T_450 = asUInt(reset)
node _T_451 = eq(_T_450, UInt<1>(0h0))
when _T_451 :
node _T_452 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_452 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_453 = asUInt(reset)
node _T_454 = eq(_T_453, UInt<1>(0h0))
when _T_454 :
node _T_455 = eq(sink_ok, UInt<1>(0h0))
when _T_455 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_456 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_457 = asUInt(reset)
node _T_458 = eq(_T_457, UInt<1>(0h0))
when _T_458 :
node _T_459 = eq(_T_456, UInt<1>(0h0))
when _T_459 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_456, UInt<1>(0h1), "") : assert_67
node _T_460 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_461 = asUInt(reset)
node _T_462 = eq(_T_461, UInt<1>(0h0))
when _T_462 :
node _T_463 = eq(_T_460, UInt<1>(0h0))
when _T_463 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_460, UInt<1>(0h1), "") : assert_68
node _T_464 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_465 = asUInt(reset)
node _T_466 = eq(_T_465, UInt<1>(0h0))
when _T_466 :
node _T_467 = eq(_T_464, UInt<1>(0h0))
when _T_467 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_464, UInt<1>(0h1), "") : assert_69
node _T_468 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_469 = or(_T_468, io.in.d.bits.corrupt)
node _T_470 = asUInt(reset)
node _T_471 = eq(_T_470, UInt<1>(0h0))
when _T_471 :
node _T_472 = eq(_T_469, UInt<1>(0h0))
when _T_472 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_469, UInt<1>(0h1), "") : assert_70
node _T_473 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_474 = or(UInt<1>(0h0), _T_473)
node _T_475 = asUInt(reset)
node _T_476 = eq(_T_475, UInt<1>(0h0))
when _T_476 :
node _T_477 = eq(_T_474, UInt<1>(0h0))
when _T_477 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_474, UInt<1>(0h1), "") : assert_71
node _T_478 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_478 :
node _T_479 = asUInt(reset)
node _T_480 = eq(_T_479, UInt<1>(0h0))
when _T_480 :
node _T_481 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_481 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_482 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_483 = asUInt(reset)
node _T_484 = eq(_T_483, UInt<1>(0h0))
when _T_484 :
node _T_485 = eq(_T_482, UInt<1>(0h0))
when _T_485 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_482, UInt<1>(0h1), "") : assert_73
node _T_486 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_486, UInt<1>(0h1), "") : assert_74
node _T_490 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_491 = or(UInt<1>(0h0), _T_490)
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_T_491, UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_491, UInt<1>(0h1), "") : assert_75
node _T_495 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_495 :
node _T_496 = asUInt(reset)
node _T_497 = eq(_T_496, UInt<1>(0h0))
when _T_497 :
node _T_498 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_498 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_499 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_500 = asUInt(reset)
node _T_501 = eq(_T_500, UInt<1>(0h0))
when _T_501 :
node _T_502 = eq(_T_499, UInt<1>(0h0))
when _T_502 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_499, UInt<1>(0h1), "") : assert_77
node _T_503 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_504 = or(_T_503, io.in.d.bits.corrupt)
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_504, UInt<1>(0h1), "") : assert_78
node _T_508 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = asUInt(reset)
node _T_511 = eq(_T_510, UInt<1>(0h0))
when _T_511 :
node _T_512 = eq(_T_509, UInt<1>(0h0))
when _T_512 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_509, UInt<1>(0h1), "") : assert_79
node _T_513 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_513 :
node _T_514 = asUInt(reset)
node _T_515 = eq(_T_514, UInt<1>(0h0))
when _T_515 :
node _T_516 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_516 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_517 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_518 = asUInt(reset)
node _T_519 = eq(_T_518, UInt<1>(0h0))
when _T_519 :
node _T_520 = eq(_T_517, UInt<1>(0h0))
when _T_520 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_517, UInt<1>(0h1), "") : assert_81
node _T_521 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_522 = asUInt(reset)
node _T_523 = eq(_T_522, UInt<1>(0h0))
when _T_523 :
node _T_524 = eq(_T_521, UInt<1>(0h0))
when _T_524 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_521, UInt<1>(0h1), "") : assert_82
node _T_525 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_526, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<28>(0h0)
connect _WIRE.bits.source, UInt<11>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_530 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_530, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<28>(0h0)
connect _WIRE_2.bits.source, UInt<11>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_534 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_535 = asUInt(reset)
node _T_536 = eq(_T_535, UInt<1>(0h0))
when _T_536 :
node _T_537 = eq(_T_534, UInt<1>(0h0))
when _T_537 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_534, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_538 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_539 = asUInt(reset)
node _T_540 = eq(_T_539, UInt<1>(0h0))
when _T_540 :
node _T_541 = eq(_T_538, UInt<1>(0h0))
when _T_541 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_538, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 2, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_542 = eq(a_first, UInt<1>(0h0))
node _T_543 = and(io.in.a.valid, _T_542)
when _T_543 :
node _T_544 = eq(io.in.a.bits.opcode, opcode)
node _T_545 = asUInt(reset)
node _T_546 = eq(_T_545, UInt<1>(0h0))
when _T_546 :
node _T_547 = eq(_T_544, UInt<1>(0h0))
when _T_547 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_544, UInt<1>(0h1), "") : assert_87
node _T_548 = eq(io.in.a.bits.param, param)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_548, UInt<1>(0h1), "") : assert_88
node _T_552 = eq(io.in.a.bits.size, size)
node _T_553 = asUInt(reset)
node _T_554 = eq(_T_553, UInt<1>(0h0))
when _T_554 :
node _T_555 = eq(_T_552, UInt<1>(0h0))
when _T_555 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_552, UInt<1>(0h1), "") : assert_89
node _T_556 = eq(io.in.a.bits.source, source)
node _T_557 = asUInt(reset)
node _T_558 = eq(_T_557, UInt<1>(0h0))
when _T_558 :
node _T_559 = eq(_T_556, UInt<1>(0h0))
when _T_559 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_556, UInt<1>(0h1), "") : assert_90
node _T_560 = eq(io.in.a.bits.address, address)
node _T_561 = asUInt(reset)
node _T_562 = eq(_T_561, UInt<1>(0h0))
when _T_562 :
node _T_563 = eq(_T_560, UInt<1>(0h0))
when _T_563 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_560, UInt<1>(0h1), "") : assert_91
node _T_564 = and(io.in.a.ready, io.in.a.valid)
node _T_565 = and(_T_564, a_first)
when _T_565 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 2, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_566 = eq(d_first, UInt<1>(0h0))
node _T_567 = and(io.in.d.valid, _T_566)
when _T_567 :
node _T_568 = eq(io.in.d.bits.opcode, opcode_1)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_568, UInt<1>(0h1), "") : assert_92
node _T_572 = eq(io.in.d.bits.param, param_1)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_572, UInt<1>(0h1), "") : assert_93
node _T_576 = eq(io.in.d.bits.size, size_1)
node _T_577 = asUInt(reset)
node _T_578 = eq(_T_577, UInt<1>(0h0))
when _T_578 :
node _T_579 = eq(_T_576, UInt<1>(0h0))
when _T_579 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_576, UInt<1>(0h1), "") : assert_94
node _T_580 = eq(io.in.d.bits.source, source_1)
node _T_581 = asUInt(reset)
node _T_582 = eq(_T_581, UInt<1>(0h0))
when _T_582 :
node _T_583 = eq(_T_580, UInt<1>(0h0))
when _T_583 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_580, UInt<1>(0h1), "") : assert_95
node _T_584 = eq(io.in.d.bits.sink, sink)
node _T_585 = asUInt(reset)
node _T_586 = eq(_T_585, UInt<1>(0h0))
when _T_586 :
node _T_587 = eq(_T_584, UInt<1>(0h0))
when _T_587 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_584, UInt<1>(0h1), "") : assert_96
node _T_588 = eq(io.in.d.bits.denied, denied)
node _T_589 = asUInt(reset)
node _T_590 = eq(_T_589, UInt<1>(0h0))
when _T_590 :
node _T_591 = eq(_T_588, UInt<1>(0h0))
when _T_591 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_588, UInt<1>(0h1), "") : assert_97
node _T_592 = and(io.in.d.ready, io.in.d.valid)
node _T_593 = and(_T_592, d_first)
when _T_593 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<1040>, clock, reset, UInt<1040>(0h0)
regreset inflight_opcodes : UInt<4160>, clock, reset, UInt<4160>(0h0)
regreset inflight_sizes : UInt<4160>, clock, reset, UInt<4160>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 2, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 2, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1040>
connect a_set, UInt<1040>(0h0)
wire a_set_wo_ready : UInt<1040>
connect a_set_wo_ready, UInt<1040>(0h0)
wire a_opcodes_set : UInt<4160>
connect a_opcodes_set, UInt<4160>(0h0)
wire a_sizes_set : UInt<4160>
connect a_sizes_set, UInt<4160>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_594 = and(io.in.a.valid, a_first_1)
node _T_595 = and(_T_594, UInt<1>(0h1))
when _T_595 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_596 = and(io.in.a.ready, io.in.a.valid)
node _T_597 = and(_T_596, a_first_1)
node _T_598 = and(_T_597, UInt<1>(0h1))
when _T_598 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_599 = dshr(inflight, io.in.a.bits.source)
node _T_600 = bits(_T_599, 0, 0)
node _T_601 = eq(_T_600, UInt<1>(0h0))
node _T_602 = asUInt(reset)
node _T_603 = eq(_T_602, UInt<1>(0h0))
when _T_603 :
node _T_604 = eq(_T_601, UInt<1>(0h0))
when _T_604 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_601, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1040>
connect d_clr, UInt<1040>(0h0)
wire d_clr_wo_ready : UInt<1040>
connect d_clr_wo_ready, UInt<1040>(0h0)
wire d_opcodes_clr : UInt<4160>
connect d_opcodes_clr, UInt<4160>(0h0)
wire d_sizes_clr : UInt<4160>
connect d_sizes_clr, UInt<4160>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_605 = and(io.in.d.valid, d_first_1)
node _T_606 = and(_T_605, UInt<1>(0h1))
node _T_607 = eq(d_release_ack, UInt<1>(0h0))
node _T_608 = and(_T_606, _T_607)
when _T_608 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_609 = and(io.in.d.ready, io.in.d.valid)
node _T_610 = and(_T_609, d_first_1)
node _T_611 = and(_T_610, UInt<1>(0h1))
node _T_612 = eq(d_release_ack, UInt<1>(0h0))
node _T_613 = and(_T_611, _T_612)
when _T_613 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_614 = and(io.in.d.valid, d_first_1)
node _T_615 = and(_T_614, UInt<1>(0h1))
node _T_616 = eq(d_release_ack, UInt<1>(0h0))
node _T_617 = and(_T_615, _T_616)
when _T_617 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_618 = dshr(inflight, io.in.d.bits.source)
node _T_619 = bits(_T_618, 0, 0)
node _T_620 = or(_T_619, same_cycle_resp)
node _T_621 = asUInt(reset)
node _T_622 = eq(_T_621, UInt<1>(0h0))
when _T_622 :
node _T_623 = eq(_T_620, UInt<1>(0h0))
when _T_623 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_620, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_624 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_625 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_626 = or(_T_624, _T_625)
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_626, UInt<1>(0h1), "") : assert_100
node _T_630 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_630, UInt<1>(0h1), "") : assert_101
else :
node _T_634 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_635 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_636 = or(_T_634, _T_635)
node _T_637 = asUInt(reset)
node _T_638 = eq(_T_637, UInt<1>(0h0))
when _T_638 :
node _T_639 = eq(_T_636, UInt<1>(0h0))
when _T_639 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_636, UInt<1>(0h1), "") : assert_102
node _T_640 = eq(io.in.d.bits.size, a_size_lookup)
node _T_641 = asUInt(reset)
node _T_642 = eq(_T_641, UInt<1>(0h0))
when _T_642 :
node _T_643 = eq(_T_640, UInt<1>(0h0))
when _T_643 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_640, UInt<1>(0h1), "") : assert_103
node _T_644 = and(io.in.d.valid, d_first_1)
node _T_645 = and(_T_644, a_first_1)
node _T_646 = and(_T_645, io.in.a.valid)
node _T_647 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_648 = and(_T_646, _T_647)
node _T_649 = eq(d_release_ack, UInt<1>(0h0))
node _T_650 = and(_T_648, _T_649)
when _T_650 :
node _T_651 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_652 = or(_T_651, io.in.a.ready)
node _T_653 = asUInt(reset)
node _T_654 = eq(_T_653, UInt<1>(0h0))
when _T_654 :
node _T_655 = eq(_T_652, UInt<1>(0h0))
when _T_655 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_652, UInt<1>(0h1), "") : assert_104
node _T_656 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_657 = orr(a_set_wo_ready)
node _T_658 = eq(_T_657, UInt<1>(0h0))
node _T_659 = or(_T_656, _T_658)
node _T_660 = asUInt(reset)
node _T_661 = eq(_T_660, UInt<1>(0h0))
when _T_661 :
node _T_662 = eq(_T_659, UInt<1>(0h0))
when _T_662 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_659, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_87
node _T_663 = orr(inflight)
node _T_664 = eq(_T_663, UInt<1>(0h0))
node _T_665 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_666 = or(_T_664, _T_665)
node _T_667 = lt(watchdog, plusarg_reader.out)
node _T_668 = or(_T_666, _T_667)
node _T_669 = asUInt(reset)
node _T_670 = eq(_T_669, UInt<1>(0h0))
when _T_670 :
node _T_671 = eq(_T_668, UInt<1>(0h0))
when _T_671 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_668, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_672 = and(io.in.a.ready, io.in.a.valid)
node _T_673 = and(io.in.d.ready, io.in.d.valid)
node _T_674 = or(_T_672, _T_673)
when _T_674 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<1040>, clock, reset, UInt<1040>(0h0)
regreset inflight_opcodes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0)
regreset inflight_sizes_1 : UInt<4160>, clock, reset, UInt<4160>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<28>(0h0)
connect _c_first_WIRE.bits.source, UInt<11>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<11>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<3>(0h7), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 2, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<3>(0h7), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 2, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1040>
connect c_set, UInt<1040>(0h0)
wire c_set_wo_ready : UInt<1040>
connect c_set_wo_ready, UInt<1040>(0h0)
wire c_opcodes_set : UInt<4160>
connect c_opcodes_set, UInt<4160>(0h0)
wire c_sizes_set : UInt<4160>
connect c_sizes_set, UInt<4160>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<28>(0h0)
connect _WIRE_6.bits.source, UInt<11>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_675 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<28>(0h0)
connect _WIRE_8.bits.source, UInt<11>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_676 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_677 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_678 = and(_T_676, _T_677)
node _T_679 = and(_T_675, _T_678)
when _T_679 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<11>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<28>(0h0)
connect _WIRE_10.bits.source, UInt<11>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_680 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_681 = and(_T_680, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<28>(0h0)
connect _WIRE_12.bits.source, UInt<11>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_682 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_683 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_684 = and(_T_682, _T_683)
node _T_685 = and(_T_681, _T_684)
when _T_685 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<11>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<11>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<28>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<11>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<28>(0h0)
connect _WIRE_14.bits.source, UInt<11>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_686 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_687 = bits(_T_686, 0, 0)
node _T_688 = eq(_T_687, UInt<1>(0h0))
node _T_689 = asUInt(reset)
node _T_690 = eq(_T_689, UInt<1>(0h0))
when _T_690 :
node _T_691 = eq(_T_688, UInt<1>(0h0))
when _T_691 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_688, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<11>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<28>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<11>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1040>
connect d_clr_1, UInt<1040>(0h0)
wire d_clr_wo_ready_1 : UInt<1040>
connect d_clr_wo_ready_1, UInt<1040>(0h0)
wire d_opcodes_clr_1 : UInt<4160>
connect d_opcodes_clr_1, UInt<4160>(0h0)
wire d_sizes_clr_1 : UInt<4160>
connect d_sizes_clr_1, UInt<4160>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_692 = and(io.in.d.valid, d_first_2)
node _T_693 = and(_T_692, UInt<1>(0h1))
node _T_694 = and(_T_693, d_release_ack_1)
when _T_694 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_695 = and(io.in.d.ready, io.in.d.valid)
node _T_696 = and(_T_695, d_first_2)
node _T_697 = and(_T_696, UInt<1>(0h1))
node _T_698 = and(_T_697, d_release_ack_1)
when _T_698 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_699 = and(io.in.d.valid, d_first_2)
node _T_700 = and(_T_699, UInt<1>(0h1))
node _T_701 = and(_T_700, d_release_ack_1)
when _T_701 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<28>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<11>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_702 = dshr(inflight_1, io.in.d.bits.source)
node _T_703 = bits(_T_702, 0, 0)
node _T_704 = or(_T_703, same_cycle_resp_1)
node _T_705 = asUInt(reset)
node _T_706 = eq(_T_705, UInt<1>(0h0))
when _T_706 :
node _T_707 = eq(_T_704, UInt<1>(0h0))
when _T_707 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_704, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<28>(0h0)
connect _WIRE_16.bits.source, UInt<11>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_708 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_709 = asUInt(reset)
node _T_710 = eq(_T_709, UInt<1>(0h0))
when _T_710 :
node _T_711 = eq(_T_708, UInt<1>(0h0))
when _T_711 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_708, UInt<1>(0h1), "") : assert_109
else :
node _T_712 = eq(io.in.d.bits.size, c_size_lookup)
node _T_713 = asUInt(reset)
node _T_714 = eq(_T_713, UInt<1>(0h0))
when _T_714 :
node _T_715 = eq(_T_712, UInt<1>(0h0))
when _T_715 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_712, UInt<1>(0h1), "") : assert_110
node _T_716 = and(io.in.d.valid, d_first_2)
node _T_717 = and(_T_716, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<28>(0h0)
connect _WIRE_18.bits.source, UInt<11>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_718 = and(_T_717, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<28>(0h0)
connect _WIRE_20.bits.source, UInt<11>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_719 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_720 = and(_T_718, _T_719)
node _T_721 = and(_T_720, d_release_ack_1)
node _T_722 = eq(c_probe_ack, UInt<1>(0h0))
node _T_723 = and(_T_721, _T_722)
when _T_723 :
node _T_724 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<28>(0h0)
connect _WIRE_22.bits.source, UInt<11>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_725 = or(_T_724, _WIRE_23.ready)
node _T_726 = asUInt(reset)
node _T_727 = eq(_T_726, UInt<1>(0h0))
when _T_727 :
node _T_728 = eq(_T_725, UInt<1>(0h0))
when _T_728 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_725, UInt<1>(0h1), "") : assert_111
node _T_729 = orr(c_set_wo_ready)
when _T_729 :
node _T_730 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_731 = asUInt(reset)
node _T_732 = eq(_T_731, UInt<1>(0h0))
when _T_732 :
node _T_733 = eq(_T_730, UInt<1>(0h0))
when _T_733 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_730, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_88
node _T_734 = orr(inflight_1)
node _T_735 = eq(_T_734, UInt<1>(0h0))
node _T_736 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_737 = or(_T_735, _T_736)
node _T_738 = lt(watchdog_1, plusarg_reader_1.out)
node _T_739 = or(_T_737, _T_738)
node _T_740 = asUInt(reset)
node _T_741 = eq(_T_740, UInt<1>(0h0))
when _T_741 :
node _T_742 = eq(_T_739, UInt<1>(0h0))
when _T_742 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/Plic.scala:368:35)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_739, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<28>(0h0)
connect _WIRE_24.bits.source, UInt<11>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_743 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_744 = and(io.in.d.ready, io.in.d.valid)
node _T_745 = or(_T_743, _T_744)
when _T_745 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_43( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_a_bits_source, // @[Monitor.scala:20:14]
input [27:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input [10:0] io_in_d_bits_source // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [1:0] size; // @[Monitor.scala:389:22]
reg [10:0] source; // @[Monitor.scala:390:22]
reg [27:0] address; // @[Monitor.scala:391:22]
reg d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg [10:0] source_1; // @[Monitor.scala:541:22]
reg [1039:0] inflight; // @[Monitor.scala:614:27]
reg [4159:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [4159:0] inflight_sizes; // @[Monitor.scala:618:33]
reg a_first_counter_1; // @[Edges.scala:229:27]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire [2047:0] _GEN = {2037'h0, io_in_a_bits_source}; // @[OneHot.scala:58:35]
wire _GEN_0 = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
wire [2047:0] _GEN_2 = {2037'h0, io_in_d_bits_source}; // @[OneHot.scala:58:35]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [1039:0] inflight_1; // @[Monitor.scala:726:35]
reg [4159:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg d_first_counter_2; // @[Edges.scala:229:27]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_73 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3))
node mask_sub_sub_size = bits(mask_sizeOH, 2, 2)
node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2)
node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0))
node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit)
node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2)
node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T)
node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit)
node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2)
node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1)
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit)
node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2)
node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2)
node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit)
node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2)
node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_eq_4 = and(mask_sub_2_2, mask_nbit)
node _mask_acc_T_4 = and(mask_size, mask_eq_4)
node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4)
node mask_eq_5 = and(mask_sub_2_2, mask_bit)
node _mask_acc_T_5 = and(mask_size, mask_eq_5)
node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5)
node mask_eq_6 = and(mask_sub_3_2, mask_nbit)
node _mask_acc_T_6 = and(mask_size, mask_eq_6)
node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6)
node mask_eq_7 = and(mask_sub_3_2, mask_bit)
node _mask_acc_T_7 = and(mask_size, mask_eq_7)
node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7)
node mask_lo_lo = cat(mask_acc_1, mask_acc)
node mask_lo_hi = cat(mask_acc_3, mask_acc_2)
node mask_lo = cat(mask_lo_hi, mask_lo_lo)
node mask_hi_lo = cat(mask_acc_5, mask_acc_4)
node mask_hi_hi = cat(mask_acc_7, mask_acc_6)
node mask_hi = cat(mask_hi_hi, mask_hi_lo)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_18 = and(_T_16, _T_17)
node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_20 = and(_T_18, _T_19)
node _T_21 = or(UInt<1>(0h0), _T_20)
node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_24 = cvt(_T_23)
node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000)))
node _T_26 = asSInt(_T_25)
node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0)))
node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_29 = cvt(_T_28)
node _T_30 = and(_T_29, asSInt(UInt<11>(0h400)))
node _T_31 = asSInt(_T_30)
node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0)))
node _T_33 = xor(io.in.a.bits.address, UInt<14>(0h2400))
node _T_34 = cvt(_T_33)
node _T_35 = and(_T_34, asSInt(UInt<9>(0h100)))
node _T_36 = asSInt(_T_35)
node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0)))
node _T_38 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<13>(0h1000)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_44 = cvt(_T_43)
node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000)))
node _T_46 = asSInt(_T_45)
node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0)))
node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_49 = cvt(_T_48)
node _T_50 = and(_T_49, asSInt(UInt<18>(0h2f000)))
node _T_51 = asSInt(_T_50)
node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0)))
node _T_53 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_54 = cvt(_T_53)
node _T_55 = and(_T_54, asSInt(UInt<17>(0h10000)))
node _T_56 = asSInt(_T_55)
node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0)))
node _T_58 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_59 = cvt(_T_58)
node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000)))
node _T_61 = asSInt(_T_60)
node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0)))
node _T_63 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_64 = cvt(_T_63)
node _T_65 = and(_T_64, asSInt(UInt<27>(0h4000000)))
node _T_66 = asSInt(_T_65)
node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0)))
node _T_68 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_69 = cvt(_T_68)
node _T_70 = and(_T_69, asSInt(UInt<13>(0h1000)))
node _T_71 = asSInt(_T_70)
node _T_72 = eq(_T_71, asSInt(UInt<1>(0h0)))
node _T_73 = or(_T_27, _T_32)
node _T_74 = or(_T_73, _T_37)
node _T_75 = or(_T_74, _T_42)
node _T_76 = or(_T_75, _T_47)
node _T_77 = or(_T_76, _T_52)
node _T_78 = or(_T_77, _T_57)
node _T_79 = or(_T_78, _T_62)
node _T_80 = or(_T_79, _T_67)
node _T_81 = or(_T_80, _T_72)
node _T_82 = and(_T_22, _T_81)
node _T_83 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_84 = or(UInt<1>(0h0), _T_83)
node _T_85 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_86 = cvt(_T_85)
node _T_87 = and(_T_86, asSInt(UInt<17>(0h10000)))
node _T_88 = asSInt(_T_87)
node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0)))
node _T_90 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<29>(0h10000000)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_89, _T_94)
node _T_96 = and(_T_84, _T_95)
node _T_97 = or(UInt<1>(0h0), _T_82)
node _T_98 = or(_T_97, _T_96)
node _T_99 = and(_T_21, _T_98)
node _T_100 = asUInt(reset)
node _T_101 = eq(_T_100, UInt<1>(0h0))
when _T_101 :
node _T_102 = eq(_T_99, UInt<1>(0h0))
when _T_102 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_99, UInt<1>(0h1), "") : assert_2
node _T_103 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_104 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_105 = and(_T_103, _T_104)
node _T_106 = or(UInt<1>(0h0), _T_105)
node _T_107 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_108 = cvt(_T_107)
node _T_109 = and(_T_108, asSInt(UInt<14>(0h2000)))
node _T_110 = asSInt(_T_109)
node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0)))
node _T_112 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_113 = cvt(_T_112)
node _T_114 = and(_T_113, asSInt(UInt<11>(0h400)))
node _T_115 = asSInt(_T_114)
node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0)))
node _T_117 = xor(io.in.a.bits.address, UInt<14>(0h2400))
node _T_118 = cvt(_T_117)
node _T_119 = and(_T_118, asSInt(UInt<9>(0h100)))
node _T_120 = asSInt(_T_119)
node _T_121 = eq(_T_120, asSInt(UInt<1>(0h0)))
node _T_122 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_123 = cvt(_T_122)
node _T_124 = and(_T_123, asSInt(UInt<13>(0h1000)))
node _T_125 = asSInt(_T_124)
node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0)))
node _T_127 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_128 = cvt(_T_127)
node _T_129 = and(_T_128, asSInt(UInt<17>(0h10000)))
node _T_130 = asSInt(_T_129)
node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0)))
node _T_132 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_133 = cvt(_T_132)
node _T_134 = and(_T_133, asSInt(UInt<18>(0h2f000)))
node _T_135 = asSInt(_T_134)
node _T_136 = eq(_T_135, asSInt(UInt<1>(0h0)))
node _T_137 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_138 = cvt(_T_137)
node _T_139 = and(_T_138, asSInt(UInt<17>(0h10000)))
node _T_140 = asSInt(_T_139)
node _T_141 = eq(_T_140, asSInt(UInt<1>(0h0)))
node _T_142 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_143 = cvt(_T_142)
node _T_144 = and(_T_143, asSInt(UInt<13>(0h1000)))
node _T_145 = asSInt(_T_144)
node _T_146 = eq(_T_145, asSInt(UInt<1>(0h0)))
node _T_147 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_148 = cvt(_T_147)
node _T_149 = and(_T_148, asSInt(UInt<17>(0h10000)))
node _T_150 = asSInt(_T_149)
node _T_151 = eq(_T_150, asSInt(UInt<1>(0h0)))
node _T_152 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_153 = cvt(_T_152)
node _T_154 = and(_T_153, asSInt(UInt<27>(0h4000000)))
node _T_155 = asSInt(_T_154)
node _T_156 = eq(_T_155, asSInt(UInt<1>(0h0)))
node _T_157 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_158 = cvt(_T_157)
node _T_159 = and(_T_158, asSInt(UInt<13>(0h1000)))
node _T_160 = asSInt(_T_159)
node _T_161 = eq(_T_160, asSInt(UInt<1>(0h0)))
node _T_162 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_163 = cvt(_T_162)
node _T_164 = and(_T_163, asSInt(UInt<29>(0h10000000)))
node _T_165 = asSInt(_T_164)
node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0)))
node _T_167 = or(_T_111, _T_116)
node _T_168 = or(_T_167, _T_121)
node _T_169 = or(_T_168, _T_126)
node _T_170 = or(_T_169, _T_131)
node _T_171 = or(_T_170, _T_136)
node _T_172 = or(_T_171, _T_141)
node _T_173 = or(_T_172, _T_146)
node _T_174 = or(_T_173, _T_151)
node _T_175 = or(_T_174, _T_156)
node _T_176 = or(_T_175, _T_161)
node _T_177 = or(_T_176, _T_166)
node _T_178 = and(_T_106, _T_177)
node _T_179 = or(UInt<1>(0h0), _T_178)
node _T_180 = and(UInt<1>(0h0), _T_179)
node _T_181 = asUInt(reset)
node _T_182 = eq(_T_181, UInt<1>(0h0))
when _T_182 :
node _T_183 = eq(_T_180, UInt<1>(0h0))
when _T_183 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_180, UInt<1>(0h1), "") : assert_3
node _T_184 = asUInt(reset)
node _T_185 = eq(_T_184, UInt<1>(0h0))
when _T_185 :
node _T_186 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_186 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_187 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_188 = asUInt(reset)
node _T_189 = eq(_T_188, UInt<1>(0h0))
when _T_189 :
node _T_190 = eq(_T_187, UInt<1>(0h0))
when _T_190 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_187, UInt<1>(0h1), "") : assert_5
node _T_191 = asUInt(reset)
node _T_192 = eq(_T_191, UInt<1>(0h0))
when _T_192 :
node _T_193 = eq(is_aligned, UInt<1>(0h0))
when _T_193 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_194 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_195 = asUInt(reset)
node _T_196 = eq(_T_195, UInt<1>(0h0))
when _T_196 :
node _T_197 = eq(_T_194, UInt<1>(0h0))
when _T_197 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_194, UInt<1>(0h1), "") : assert_7
node _T_198 = not(io.in.a.bits.mask)
node _T_199 = eq(_T_198, UInt<1>(0h0))
node _T_200 = asUInt(reset)
node _T_201 = eq(_T_200, UInt<1>(0h0))
when _T_201 :
node _T_202 = eq(_T_199, UInt<1>(0h0))
when _T_202 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_199, UInt<1>(0h1), "") : assert_8
node _T_203 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_204 = asUInt(reset)
node _T_205 = eq(_T_204, UInt<1>(0h0))
when _T_205 :
node _T_206 = eq(_T_203, UInt<1>(0h0))
when _T_206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_203, UInt<1>(0h1), "") : assert_9
node _T_207 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_207 :
node _T_208 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_209 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_210 = and(_T_208, _T_209)
node _T_211 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_212 = and(_T_210, _T_211)
node _T_213 = or(UInt<1>(0h0), _T_212)
node _T_214 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_215 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_216 = cvt(_T_215)
node _T_217 = and(_T_216, asSInt(UInt<14>(0h2000)))
node _T_218 = asSInt(_T_217)
node _T_219 = eq(_T_218, asSInt(UInt<1>(0h0)))
node _T_220 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_221 = cvt(_T_220)
node _T_222 = and(_T_221, asSInt(UInt<11>(0h400)))
node _T_223 = asSInt(_T_222)
node _T_224 = eq(_T_223, asSInt(UInt<1>(0h0)))
node _T_225 = xor(io.in.a.bits.address, UInt<14>(0h2400))
node _T_226 = cvt(_T_225)
node _T_227 = and(_T_226, asSInt(UInt<9>(0h100)))
node _T_228 = asSInt(_T_227)
node _T_229 = eq(_T_228, asSInt(UInt<1>(0h0)))
node _T_230 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_231 = cvt(_T_230)
node _T_232 = and(_T_231, asSInt(UInt<13>(0h1000)))
node _T_233 = asSInt(_T_232)
node _T_234 = eq(_T_233, asSInt(UInt<1>(0h0)))
node _T_235 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_236 = cvt(_T_235)
node _T_237 = and(_T_236, asSInt(UInt<17>(0h10000)))
node _T_238 = asSInt(_T_237)
node _T_239 = eq(_T_238, asSInt(UInt<1>(0h0)))
node _T_240 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_241 = cvt(_T_240)
node _T_242 = and(_T_241, asSInt(UInt<18>(0h2f000)))
node _T_243 = asSInt(_T_242)
node _T_244 = eq(_T_243, asSInt(UInt<1>(0h0)))
node _T_245 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_246 = cvt(_T_245)
node _T_247 = and(_T_246, asSInt(UInt<17>(0h10000)))
node _T_248 = asSInt(_T_247)
node _T_249 = eq(_T_248, asSInt(UInt<1>(0h0)))
node _T_250 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_251 = cvt(_T_250)
node _T_252 = and(_T_251, asSInt(UInt<13>(0h1000)))
node _T_253 = asSInt(_T_252)
node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0)))
node _T_255 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_256 = cvt(_T_255)
node _T_257 = and(_T_256, asSInt(UInt<27>(0h4000000)))
node _T_258 = asSInt(_T_257)
node _T_259 = eq(_T_258, asSInt(UInt<1>(0h0)))
node _T_260 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_261 = cvt(_T_260)
node _T_262 = and(_T_261, asSInt(UInt<13>(0h1000)))
node _T_263 = asSInt(_T_262)
node _T_264 = eq(_T_263, asSInt(UInt<1>(0h0)))
node _T_265 = or(_T_219, _T_224)
node _T_266 = or(_T_265, _T_229)
node _T_267 = or(_T_266, _T_234)
node _T_268 = or(_T_267, _T_239)
node _T_269 = or(_T_268, _T_244)
node _T_270 = or(_T_269, _T_249)
node _T_271 = or(_T_270, _T_254)
node _T_272 = or(_T_271, _T_259)
node _T_273 = or(_T_272, _T_264)
node _T_274 = and(_T_214, _T_273)
node _T_275 = eq(UInt<3>(0h6), io.in.a.bits.size)
node _T_276 = or(UInt<1>(0h0), _T_275)
node _T_277 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_278 = cvt(_T_277)
node _T_279 = and(_T_278, asSInt(UInt<17>(0h10000)))
node _T_280 = asSInt(_T_279)
node _T_281 = eq(_T_280, asSInt(UInt<1>(0h0)))
node _T_282 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_283 = cvt(_T_282)
node _T_284 = and(_T_283, asSInt(UInt<29>(0h10000000)))
node _T_285 = asSInt(_T_284)
node _T_286 = eq(_T_285, asSInt(UInt<1>(0h0)))
node _T_287 = or(_T_281, _T_286)
node _T_288 = and(_T_276, _T_287)
node _T_289 = or(UInt<1>(0h0), _T_274)
node _T_290 = or(_T_289, _T_288)
node _T_291 = and(_T_213, _T_290)
node _T_292 = asUInt(reset)
node _T_293 = eq(_T_292, UInt<1>(0h0))
when _T_293 :
node _T_294 = eq(_T_291, UInt<1>(0h0))
when _T_294 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_291, UInt<1>(0h1), "") : assert_10
node _T_295 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_296 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_297 = and(_T_295, _T_296)
node _T_298 = or(UInt<1>(0h0), _T_297)
node _T_299 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_300 = cvt(_T_299)
node _T_301 = and(_T_300, asSInt(UInt<14>(0h2000)))
node _T_302 = asSInt(_T_301)
node _T_303 = eq(_T_302, asSInt(UInt<1>(0h0)))
node _T_304 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_305 = cvt(_T_304)
node _T_306 = and(_T_305, asSInt(UInt<11>(0h400)))
node _T_307 = asSInt(_T_306)
node _T_308 = eq(_T_307, asSInt(UInt<1>(0h0)))
node _T_309 = xor(io.in.a.bits.address, UInt<14>(0h2400))
node _T_310 = cvt(_T_309)
node _T_311 = and(_T_310, asSInt(UInt<9>(0h100)))
node _T_312 = asSInt(_T_311)
node _T_313 = eq(_T_312, asSInt(UInt<1>(0h0)))
node _T_314 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_315 = cvt(_T_314)
node _T_316 = and(_T_315, asSInt(UInt<13>(0h1000)))
node _T_317 = asSInt(_T_316)
node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0)))
node _T_319 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_320 = cvt(_T_319)
node _T_321 = and(_T_320, asSInt(UInt<17>(0h10000)))
node _T_322 = asSInt(_T_321)
node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0)))
node _T_324 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_325 = cvt(_T_324)
node _T_326 = and(_T_325, asSInt(UInt<18>(0h2f000)))
node _T_327 = asSInt(_T_326)
node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0)))
node _T_329 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_330 = cvt(_T_329)
node _T_331 = and(_T_330, asSInt(UInt<17>(0h10000)))
node _T_332 = asSInt(_T_331)
node _T_333 = eq(_T_332, asSInt(UInt<1>(0h0)))
node _T_334 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_335 = cvt(_T_334)
node _T_336 = and(_T_335, asSInt(UInt<13>(0h1000)))
node _T_337 = asSInt(_T_336)
node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0)))
node _T_339 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_340 = cvt(_T_339)
node _T_341 = and(_T_340, asSInt(UInt<17>(0h10000)))
node _T_342 = asSInt(_T_341)
node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0)))
node _T_344 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_345 = cvt(_T_344)
node _T_346 = and(_T_345, asSInt(UInt<27>(0h4000000)))
node _T_347 = asSInt(_T_346)
node _T_348 = eq(_T_347, asSInt(UInt<1>(0h0)))
node _T_349 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_350 = cvt(_T_349)
node _T_351 = and(_T_350, asSInt(UInt<13>(0h1000)))
node _T_352 = asSInt(_T_351)
node _T_353 = eq(_T_352, asSInt(UInt<1>(0h0)))
node _T_354 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_355 = cvt(_T_354)
node _T_356 = and(_T_355, asSInt(UInt<29>(0h10000000)))
node _T_357 = asSInt(_T_356)
node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0)))
node _T_359 = or(_T_303, _T_308)
node _T_360 = or(_T_359, _T_313)
node _T_361 = or(_T_360, _T_318)
node _T_362 = or(_T_361, _T_323)
node _T_363 = or(_T_362, _T_328)
node _T_364 = or(_T_363, _T_333)
node _T_365 = or(_T_364, _T_338)
node _T_366 = or(_T_365, _T_343)
node _T_367 = or(_T_366, _T_348)
node _T_368 = or(_T_367, _T_353)
node _T_369 = or(_T_368, _T_358)
node _T_370 = and(_T_298, _T_369)
node _T_371 = or(UInt<1>(0h0), _T_370)
node _T_372 = and(UInt<1>(0h0), _T_371)
node _T_373 = asUInt(reset)
node _T_374 = eq(_T_373, UInt<1>(0h0))
when _T_374 :
node _T_375 = eq(_T_372, UInt<1>(0h0))
when _T_375 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_372, UInt<1>(0h1), "") : assert_11
node _T_376 = asUInt(reset)
node _T_377 = eq(_T_376, UInt<1>(0h0))
when _T_377 :
node _T_378 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_378 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_379 = geq(io.in.a.bits.size, UInt<2>(0h3))
node _T_380 = asUInt(reset)
node _T_381 = eq(_T_380, UInt<1>(0h0))
when _T_381 :
node _T_382 = eq(_T_379, UInt<1>(0h0))
when _T_382 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_379, UInt<1>(0h1), "") : assert_13
node _T_383 = asUInt(reset)
node _T_384 = eq(_T_383, UInt<1>(0h0))
when _T_384 :
node _T_385 = eq(is_aligned, UInt<1>(0h0))
when _T_385 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_386 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_387 = asUInt(reset)
node _T_388 = eq(_T_387, UInt<1>(0h0))
when _T_388 :
node _T_389 = eq(_T_386, UInt<1>(0h0))
when _T_389 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_386, UInt<1>(0h1), "") : assert_15
node _T_390 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_391 = asUInt(reset)
node _T_392 = eq(_T_391, UInt<1>(0h0))
when _T_392 :
node _T_393 = eq(_T_390, UInt<1>(0h0))
when _T_393 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_390, UInt<1>(0h1), "") : assert_16
node _T_394 = not(io.in.a.bits.mask)
node _T_395 = eq(_T_394, UInt<1>(0h0))
node _T_396 = asUInt(reset)
node _T_397 = eq(_T_396, UInt<1>(0h0))
when _T_397 :
node _T_398 = eq(_T_395, UInt<1>(0h0))
when _T_398 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_395, UInt<1>(0h1), "") : assert_17
node _T_399 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_400 = asUInt(reset)
node _T_401 = eq(_T_400, UInt<1>(0h0))
when _T_401 :
node _T_402 = eq(_T_399, UInt<1>(0h0))
when _T_402 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_399, UInt<1>(0h1), "") : assert_18
node _T_403 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_403 :
node _T_404 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_405 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_406 = and(_T_404, _T_405)
node _T_407 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_408 = and(_T_406, _T_407)
node _T_409 = or(UInt<1>(0h0), _T_408)
node _T_410 = asUInt(reset)
node _T_411 = eq(_T_410, UInt<1>(0h0))
when _T_411 :
node _T_412 = eq(_T_409, UInt<1>(0h0))
when _T_412 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_409, UInt<1>(0h1), "") : assert_19
node _T_413 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_414 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_415 = and(_T_413, _T_414)
node _T_416 = or(UInt<1>(0h0), _T_415)
node _T_417 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_418 = cvt(_T_417)
node _T_419 = and(_T_418, asSInt(UInt<13>(0h1000)))
node _T_420 = asSInt(_T_419)
node _T_421 = eq(_T_420, asSInt(UInt<1>(0h0)))
node _T_422 = and(_T_416, _T_421)
node _T_423 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_424 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_425 = and(_T_423, _T_424)
node _T_426 = or(UInt<1>(0h0), _T_425)
node _T_427 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_428 = cvt(_T_427)
node _T_429 = and(_T_428, asSInt(UInt<14>(0h2000)))
node _T_430 = asSInt(_T_429)
node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0)))
node _T_432 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_433 = cvt(_T_432)
node _T_434 = and(_T_433, asSInt(UInt<11>(0h400)))
node _T_435 = asSInt(_T_434)
node _T_436 = eq(_T_435, asSInt(UInt<1>(0h0)))
node _T_437 = xor(io.in.a.bits.address, UInt<14>(0h2400))
node _T_438 = cvt(_T_437)
node _T_439 = and(_T_438, asSInt(UInt<9>(0h100)))
node _T_440 = asSInt(_T_439)
node _T_441 = eq(_T_440, asSInt(UInt<1>(0h0)))
node _T_442 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_443 = cvt(_T_442)
node _T_444 = and(_T_443, asSInt(UInt<17>(0h10000)))
node _T_445 = asSInt(_T_444)
node _T_446 = eq(_T_445, asSInt(UInt<1>(0h0)))
node _T_447 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_448 = cvt(_T_447)
node _T_449 = and(_T_448, asSInt(UInt<18>(0h2f000)))
node _T_450 = asSInt(_T_449)
node _T_451 = eq(_T_450, asSInt(UInt<1>(0h0)))
node _T_452 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_453 = cvt(_T_452)
node _T_454 = and(_T_453, asSInt(UInt<17>(0h10000)))
node _T_455 = asSInt(_T_454)
node _T_456 = eq(_T_455, asSInt(UInt<1>(0h0)))
node _T_457 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_458 = cvt(_T_457)
node _T_459 = and(_T_458, asSInt(UInt<13>(0h1000)))
node _T_460 = asSInt(_T_459)
node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0)))
node _T_462 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_463 = cvt(_T_462)
node _T_464 = and(_T_463, asSInt(UInt<17>(0h10000)))
node _T_465 = asSInt(_T_464)
node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0)))
node _T_467 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_468 = cvt(_T_467)
node _T_469 = and(_T_468, asSInt(UInt<27>(0h4000000)))
node _T_470 = asSInt(_T_469)
node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0)))
node _T_472 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_473 = cvt(_T_472)
node _T_474 = and(_T_473, asSInt(UInt<13>(0h1000)))
node _T_475 = asSInt(_T_474)
node _T_476 = eq(_T_475, asSInt(UInt<1>(0h0)))
node _T_477 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_478 = cvt(_T_477)
node _T_479 = and(_T_478, asSInt(UInt<29>(0h10000000)))
node _T_480 = asSInt(_T_479)
node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0)))
node _T_482 = or(_T_431, _T_436)
node _T_483 = or(_T_482, _T_441)
node _T_484 = or(_T_483, _T_446)
node _T_485 = or(_T_484, _T_451)
node _T_486 = or(_T_485, _T_456)
node _T_487 = or(_T_486, _T_461)
node _T_488 = or(_T_487, _T_466)
node _T_489 = or(_T_488, _T_471)
node _T_490 = or(_T_489, _T_476)
node _T_491 = or(_T_490, _T_481)
node _T_492 = and(_T_426, _T_491)
node _T_493 = or(UInt<1>(0h0), _T_422)
node _T_494 = or(_T_493, _T_492)
node _T_495 = asUInt(reset)
node _T_496 = eq(_T_495, UInt<1>(0h0))
when _T_496 :
node _T_497 = eq(_T_494, UInt<1>(0h0))
when _T_497 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_494, UInt<1>(0h1), "") : assert_20
node _T_498 = asUInt(reset)
node _T_499 = eq(_T_498, UInt<1>(0h0))
when _T_499 :
node _T_500 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_500 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_501 = asUInt(reset)
node _T_502 = eq(_T_501, UInt<1>(0h0))
when _T_502 :
node _T_503 = eq(is_aligned, UInt<1>(0h0))
when _T_503 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_504 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_505 = asUInt(reset)
node _T_506 = eq(_T_505, UInt<1>(0h0))
when _T_506 :
node _T_507 = eq(_T_504, UInt<1>(0h0))
when _T_507 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_504, UInt<1>(0h1), "") : assert_23
node _T_508 = eq(io.in.a.bits.mask, mask)
node _T_509 = asUInt(reset)
node _T_510 = eq(_T_509, UInt<1>(0h0))
when _T_510 :
node _T_511 = eq(_T_508, UInt<1>(0h0))
when _T_511 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_508, UInt<1>(0h1), "") : assert_24
node _T_512 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_513 = asUInt(reset)
node _T_514 = eq(_T_513, UInt<1>(0h0))
when _T_514 :
node _T_515 = eq(_T_512, UInt<1>(0h0))
when _T_515 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_512, UInt<1>(0h1), "") : assert_25
node _T_516 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_516 :
node _T_517 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_518 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_519 = and(_T_517, _T_518)
node _T_520 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_521 = and(_T_519, _T_520)
node _T_522 = or(UInt<1>(0h0), _T_521)
node _T_523 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_524 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_525 = and(_T_523, _T_524)
node _T_526 = or(UInt<1>(0h0), _T_525)
node _T_527 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_528 = cvt(_T_527)
node _T_529 = and(_T_528, asSInt(UInt<13>(0h1000)))
node _T_530 = asSInt(_T_529)
node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0)))
node _T_532 = and(_T_526, _T_531)
node _T_533 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_534 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_535 = and(_T_533, _T_534)
node _T_536 = or(UInt<1>(0h0), _T_535)
node _T_537 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_538 = cvt(_T_537)
node _T_539 = and(_T_538, asSInt(UInt<14>(0h2000)))
node _T_540 = asSInt(_T_539)
node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0)))
node _T_542 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_543 = cvt(_T_542)
node _T_544 = and(_T_543, asSInt(UInt<11>(0h400)))
node _T_545 = asSInt(_T_544)
node _T_546 = eq(_T_545, asSInt(UInt<1>(0h0)))
node _T_547 = xor(io.in.a.bits.address, UInt<14>(0h2400))
node _T_548 = cvt(_T_547)
node _T_549 = and(_T_548, asSInt(UInt<9>(0h100)))
node _T_550 = asSInt(_T_549)
node _T_551 = eq(_T_550, asSInt(UInt<1>(0h0)))
node _T_552 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_553 = cvt(_T_552)
node _T_554 = and(_T_553, asSInt(UInt<18>(0h2f000)))
node _T_555 = asSInt(_T_554)
node _T_556 = eq(_T_555, asSInt(UInt<1>(0h0)))
node _T_557 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_558 = cvt(_T_557)
node _T_559 = and(_T_558, asSInt(UInt<17>(0h10000)))
node _T_560 = asSInt(_T_559)
node _T_561 = eq(_T_560, asSInt(UInt<1>(0h0)))
node _T_562 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_563 = cvt(_T_562)
node _T_564 = and(_T_563, asSInt(UInt<13>(0h1000)))
node _T_565 = asSInt(_T_564)
node _T_566 = eq(_T_565, asSInt(UInt<1>(0h0)))
node _T_567 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_568 = cvt(_T_567)
node _T_569 = and(_T_568, asSInt(UInt<17>(0h10000)))
node _T_570 = asSInt(_T_569)
node _T_571 = eq(_T_570, asSInt(UInt<1>(0h0)))
node _T_572 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_573 = cvt(_T_572)
node _T_574 = and(_T_573, asSInt(UInt<27>(0h4000000)))
node _T_575 = asSInt(_T_574)
node _T_576 = eq(_T_575, asSInt(UInt<1>(0h0)))
node _T_577 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_578 = cvt(_T_577)
node _T_579 = and(_T_578, asSInt(UInt<13>(0h1000)))
node _T_580 = asSInt(_T_579)
node _T_581 = eq(_T_580, asSInt(UInt<1>(0h0)))
node _T_582 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_583 = cvt(_T_582)
node _T_584 = and(_T_583, asSInt(UInt<29>(0h10000000)))
node _T_585 = asSInt(_T_584)
node _T_586 = eq(_T_585, asSInt(UInt<1>(0h0)))
node _T_587 = or(_T_541, _T_546)
node _T_588 = or(_T_587, _T_551)
node _T_589 = or(_T_588, _T_556)
node _T_590 = or(_T_589, _T_561)
node _T_591 = or(_T_590, _T_566)
node _T_592 = or(_T_591, _T_571)
node _T_593 = or(_T_592, _T_576)
node _T_594 = or(_T_593, _T_581)
node _T_595 = or(_T_594, _T_586)
node _T_596 = and(_T_536, _T_595)
node _T_597 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_598 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_599 = cvt(_T_598)
node _T_600 = and(_T_599, asSInt(UInt<17>(0h10000)))
node _T_601 = asSInt(_T_600)
node _T_602 = eq(_T_601, asSInt(UInt<1>(0h0)))
node _T_603 = and(_T_597, _T_602)
node _T_604 = or(UInt<1>(0h0), _T_532)
node _T_605 = or(_T_604, _T_596)
node _T_606 = or(_T_605, _T_603)
node _T_607 = and(_T_522, _T_606)
node _T_608 = asUInt(reset)
node _T_609 = eq(_T_608, UInt<1>(0h0))
when _T_609 :
node _T_610 = eq(_T_607, UInt<1>(0h0))
when _T_610 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_607, UInt<1>(0h1), "") : assert_26
node _T_611 = asUInt(reset)
node _T_612 = eq(_T_611, UInt<1>(0h0))
when _T_612 :
node _T_613 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_613 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_614 = asUInt(reset)
node _T_615 = eq(_T_614, UInt<1>(0h0))
when _T_615 :
node _T_616 = eq(is_aligned, UInt<1>(0h0))
when _T_616 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_617 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_618 = asUInt(reset)
node _T_619 = eq(_T_618, UInt<1>(0h0))
when _T_619 :
node _T_620 = eq(_T_617, UInt<1>(0h0))
when _T_620 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_617, UInt<1>(0h1), "") : assert_29
node _T_621 = eq(io.in.a.bits.mask, mask)
node _T_622 = asUInt(reset)
node _T_623 = eq(_T_622, UInt<1>(0h0))
when _T_623 :
node _T_624 = eq(_T_621, UInt<1>(0h0))
when _T_624 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_621, UInt<1>(0h1), "") : assert_30
node _T_625 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_625 :
node _T_626 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_627 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_628 = and(_T_626, _T_627)
node _T_629 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_630 = and(_T_628, _T_629)
node _T_631 = or(UInt<1>(0h0), _T_630)
node _T_632 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_633 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_634 = and(_T_632, _T_633)
node _T_635 = or(UInt<1>(0h0), _T_634)
node _T_636 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_637 = cvt(_T_636)
node _T_638 = and(_T_637, asSInt(UInt<13>(0h1000)))
node _T_639 = asSInt(_T_638)
node _T_640 = eq(_T_639, asSInt(UInt<1>(0h0)))
node _T_641 = and(_T_635, _T_640)
node _T_642 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_643 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_644 = and(_T_642, _T_643)
node _T_645 = or(UInt<1>(0h0), _T_644)
node _T_646 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_647 = cvt(_T_646)
node _T_648 = and(_T_647, asSInt(UInt<14>(0h2000)))
node _T_649 = asSInt(_T_648)
node _T_650 = eq(_T_649, asSInt(UInt<1>(0h0)))
node _T_651 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_652 = cvt(_T_651)
node _T_653 = and(_T_652, asSInt(UInt<11>(0h400)))
node _T_654 = asSInt(_T_653)
node _T_655 = eq(_T_654, asSInt(UInt<1>(0h0)))
node _T_656 = xor(io.in.a.bits.address, UInt<14>(0h2400))
node _T_657 = cvt(_T_656)
node _T_658 = and(_T_657, asSInt(UInt<9>(0h100)))
node _T_659 = asSInt(_T_658)
node _T_660 = eq(_T_659, asSInt(UInt<1>(0h0)))
node _T_661 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_662 = cvt(_T_661)
node _T_663 = and(_T_662, asSInt(UInt<18>(0h2f000)))
node _T_664 = asSInt(_T_663)
node _T_665 = eq(_T_664, asSInt(UInt<1>(0h0)))
node _T_666 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_667 = cvt(_T_666)
node _T_668 = and(_T_667, asSInt(UInt<17>(0h10000)))
node _T_669 = asSInt(_T_668)
node _T_670 = eq(_T_669, asSInt(UInt<1>(0h0)))
node _T_671 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_672 = cvt(_T_671)
node _T_673 = and(_T_672, asSInt(UInt<13>(0h1000)))
node _T_674 = asSInt(_T_673)
node _T_675 = eq(_T_674, asSInt(UInt<1>(0h0)))
node _T_676 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_677 = cvt(_T_676)
node _T_678 = and(_T_677, asSInt(UInt<17>(0h10000)))
node _T_679 = asSInt(_T_678)
node _T_680 = eq(_T_679, asSInt(UInt<1>(0h0)))
node _T_681 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_682 = cvt(_T_681)
node _T_683 = and(_T_682, asSInt(UInt<27>(0h4000000)))
node _T_684 = asSInt(_T_683)
node _T_685 = eq(_T_684, asSInt(UInt<1>(0h0)))
node _T_686 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_687 = cvt(_T_686)
node _T_688 = and(_T_687, asSInt(UInt<13>(0h1000)))
node _T_689 = asSInt(_T_688)
node _T_690 = eq(_T_689, asSInt(UInt<1>(0h0)))
node _T_691 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_692 = cvt(_T_691)
node _T_693 = and(_T_692, asSInt(UInt<29>(0h10000000)))
node _T_694 = asSInt(_T_693)
node _T_695 = eq(_T_694, asSInt(UInt<1>(0h0)))
node _T_696 = or(_T_650, _T_655)
node _T_697 = or(_T_696, _T_660)
node _T_698 = or(_T_697, _T_665)
node _T_699 = or(_T_698, _T_670)
node _T_700 = or(_T_699, _T_675)
node _T_701 = or(_T_700, _T_680)
node _T_702 = or(_T_701, _T_685)
node _T_703 = or(_T_702, _T_690)
node _T_704 = or(_T_703, _T_695)
node _T_705 = and(_T_645, _T_704)
node _T_706 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_707 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_708 = cvt(_T_707)
node _T_709 = and(_T_708, asSInt(UInt<17>(0h10000)))
node _T_710 = asSInt(_T_709)
node _T_711 = eq(_T_710, asSInt(UInt<1>(0h0)))
node _T_712 = and(_T_706, _T_711)
node _T_713 = or(UInt<1>(0h0), _T_641)
node _T_714 = or(_T_713, _T_705)
node _T_715 = or(_T_714, _T_712)
node _T_716 = and(_T_631, _T_715)
node _T_717 = asUInt(reset)
node _T_718 = eq(_T_717, UInt<1>(0h0))
when _T_718 :
node _T_719 = eq(_T_716, UInt<1>(0h0))
when _T_719 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_716, UInt<1>(0h1), "") : assert_31
node _T_720 = asUInt(reset)
node _T_721 = eq(_T_720, UInt<1>(0h0))
when _T_721 :
node _T_722 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_723 = asUInt(reset)
node _T_724 = eq(_T_723, UInt<1>(0h0))
when _T_724 :
node _T_725 = eq(is_aligned, UInt<1>(0h0))
when _T_725 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_726 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_727 = asUInt(reset)
node _T_728 = eq(_T_727, UInt<1>(0h0))
when _T_728 :
node _T_729 = eq(_T_726, UInt<1>(0h0))
when _T_729 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_726, UInt<1>(0h1), "") : assert_34
node _T_730 = not(mask)
node _T_731 = and(io.in.a.bits.mask, _T_730)
node _T_732 = eq(_T_731, UInt<1>(0h0))
node _T_733 = asUInt(reset)
node _T_734 = eq(_T_733, UInt<1>(0h0))
when _T_734 :
node _T_735 = eq(_T_732, UInt<1>(0h0))
when _T_735 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_732, UInt<1>(0h1), "") : assert_35
node _T_736 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_736 :
node _T_737 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_738 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_739 = and(_T_737, _T_738)
node _T_740 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_741 = and(_T_739, _T_740)
node _T_742 = or(UInt<1>(0h0), _T_741)
node _T_743 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_744 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_745 = and(_T_743, _T_744)
node _T_746 = or(UInt<1>(0h0), _T_745)
node _T_747 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_748 = cvt(_T_747)
node _T_749 = and(_T_748, asSInt(UInt<14>(0h2000)))
node _T_750 = asSInt(_T_749)
node _T_751 = eq(_T_750, asSInt(UInt<1>(0h0)))
node _T_752 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_753 = cvt(_T_752)
node _T_754 = and(_T_753, asSInt(UInt<11>(0h400)))
node _T_755 = asSInt(_T_754)
node _T_756 = eq(_T_755, asSInt(UInt<1>(0h0)))
node _T_757 = xor(io.in.a.bits.address, UInt<14>(0h2400))
node _T_758 = cvt(_T_757)
node _T_759 = and(_T_758, asSInt(UInt<9>(0h100)))
node _T_760 = asSInt(_T_759)
node _T_761 = eq(_T_760, asSInt(UInt<1>(0h0)))
node _T_762 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_763 = cvt(_T_762)
node _T_764 = and(_T_763, asSInt(UInt<13>(0h1000)))
node _T_765 = asSInt(_T_764)
node _T_766 = eq(_T_765, asSInt(UInt<1>(0h0)))
node _T_767 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_768 = cvt(_T_767)
node _T_769 = and(_T_768, asSInt(UInt<18>(0h2f000)))
node _T_770 = asSInt(_T_769)
node _T_771 = eq(_T_770, asSInt(UInt<1>(0h0)))
node _T_772 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_773 = cvt(_T_772)
node _T_774 = and(_T_773, asSInt(UInt<17>(0h10000)))
node _T_775 = asSInt(_T_774)
node _T_776 = eq(_T_775, asSInt(UInt<1>(0h0)))
node _T_777 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_778 = cvt(_T_777)
node _T_779 = and(_T_778, asSInt(UInt<13>(0h1000)))
node _T_780 = asSInt(_T_779)
node _T_781 = eq(_T_780, asSInt(UInt<1>(0h0)))
node _T_782 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_783 = cvt(_T_782)
node _T_784 = and(_T_783, asSInt(UInt<17>(0h10000)))
node _T_785 = asSInt(_T_784)
node _T_786 = eq(_T_785, asSInt(UInt<1>(0h0)))
node _T_787 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_788 = cvt(_T_787)
node _T_789 = and(_T_788, asSInt(UInt<27>(0h4000000)))
node _T_790 = asSInt(_T_789)
node _T_791 = eq(_T_790, asSInt(UInt<1>(0h0)))
node _T_792 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_793 = cvt(_T_792)
node _T_794 = and(_T_793, asSInt(UInt<13>(0h1000)))
node _T_795 = asSInt(_T_794)
node _T_796 = eq(_T_795, asSInt(UInt<1>(0h0)))
node _T_797 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_798 = cvt(_T_797)
node _T_799 = and(_T_798, asSInt(UInt<29>(0h10000000)))
node _T_800 = asSInt(_T_799)
node _T_801 = eq(_T_800, asSInt(UInt<1>(0h0)))
node _T_802 = or(_T_751, _T_756)
node _T_803 = or(_T_802, _T_761)
node _T_804 = or(_T_803, _T_766)
node _T_805 = or(_T_804, _T_771)
node _T_806 = or(_T_805, _T_776)
node _T_807 = or(_T_806, _T_781)
node _T_808 = or(_T_807, _T_786)
node _T_809 = or(_T_808, _T_791)
node _T_810 = or(_T_809, _T_796)
node _T_811 = or(_T_810, _T_801)
node _T_812 = and(_T_746, _T_811)
node _T_813 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_814 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_815 = cvt(_T_814)
node _T_816 = and(_T_815, asSInt(UInt<17>(0h10000)))
node _T_817 = asSInt(_T_816)
node _T_818 = eq(_T_817, asSInt(UInt<1>(0h0)))
node _T_819 = and(_T_813, _T_818)
node _T_820 = or(UInt<1>(0h0), _T_812)
node _T_821 = or(_T_820, _T_819)
node _T_822 = and(_T_742, _T_821)
node _T_823 = asUInt(reset)
node _T_824 = eq(_T_823, UInt<1>(0h0))
when _T_824 :
node _T_825 = eq(_T_822, UInt<1>(0h0))
when _T_825 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_822, UInt<1>(0h1), "") : assert_36
node _T_826 = asUInt(reset)
node _T_827 = eq(_T_826, UInt<1>(0h0))
when _T_827 :
node _T_828 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_828 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_829 = asUInt(reset)
node _T_830 = eq(_T_829, UInt<1>(0h0))
when _T_830 :
node _T_831 = eq(is_aligned, UInt<1>(0h0))
when _T_831 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_832 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_833 = asUInt(reset)
node _T_834 = eq(_T_833, UInt<1>(0h0))
when _T_834 :
node _T_835 = eq(_T_832, UInt<1>(0h0))
when _T_835 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_832, UInt<1>(0h1), "") : assert_39
node _T_836 = eq(io.in.a.bits.mask, mask)
node _T_837 = asUInt(reset)
node _T_838 = eq(_T_837, UInt<1>(0h0))
when _T_838 :
node _T_839 = eq(_T_836, UInt<1>(0h0))
when _T_839 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_836, UInt<1>(0h1), "") : assert_40
node _T_840 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_840 :
node _T_841 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_842 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_843 = and(_T_841, _T_842)
node _T_844 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_845 = and(_T_843, _T_844)
node _T_846 = or(UInt<1>(0h0), _T_845)
node _T_847 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_848 = leq(io.in.a.bits.size, UInt<2>(0h3))
node _T_849 = and(_T_847, _T_848)
node _T_850 = or(UInt<1>(0h0), _T_849)
node _T_851 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_852 = cvt(_T_851)
node _T_853 = and(_T_852, asSInt(UInt<14>(0h2000)))
node _T_854 = asSInt(_T_853)
node _T_855 = eq(_T_854, asSInt(UInt<1>(0h0)))
node _T_856 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_857 = cvt(_T_856)
node _T_858 = and(_T_857, asSInt(UInt<11>(0h400)))
node _T_859 = asSInt(_T_858)
node _T_860 = eq(_T_859, asSInt(UInt<1>(0h0)))
node _T_861 = xor(io.in.a.bits.address, UInt<14>(0h2400))
node _T_862 = cvt(_T_861)
node _T_863 = and(_T_862, asSInt(UInt<9>(0h100)))
node _T_864 = asSInt(_T_863)
node _T_865 = eq(_T_864, asSInt(UInt<1>(0h0)))
node _T_866 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_867 = cvt(_T_866)
node _T_868 = and(_T_867, asSInt(UInt<13>(0h1000)))
node _T_869 = asSInt(_T_868)
node _T_870 = eq(_T_869, asSInt(UInt<1>(0h0)))
node _T_871 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_872 = cvt(_T_871)
node _T_873 = and(_T_872, asSInt(UInt<18>(0h2f000)))
node _T_874 = asSInt(_T_873)
node _T_875 = eq(_T_874, asSInt(UInt<1>(0h0)))
node _T_876 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_877 = cvt(_T_876)
node _T_878 = and(_T_877, asSInt(UInt<17>(0h10000)))
node _T_879 = asSInt(_T_878)
node _T_880 = eq(_T_879, asSInt(UInt<1>(0h0)))
node _T_881 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_882 = cvt(_T_881)
node _T_883 = and(_T_882, asSInt(UInt<13>(0h1000)))
node _T_884 = asSInt(_T_883)
node _T_885 = eq(_T_884, asSInt(UInt<1>(0h0)))
node _T_886 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_887 = cvt(_T_886)
node _T_888 = and(_T_887, asSInt(UInt<17>(0h10000)))
node _T_889 = asSInt(_T_888)
node _T_890 = eq(_T_889, asSInt(UInt<1>(0h0)))
node _T_891 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_892 = cvt(_T_891)
node _T_893 = and(_T_892, asSInt(UInt<27>(0h4000000)))
node _T_894 = asSInt(_T_893)
node _T_895 = eq(_T_894, asSInt(UInt<1>(0h0)))
node _T_896 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_897 = cvt(_T_896)
node _T_898 = and(_T_897, asSInt(UInt<13>(0h1000)))
node _T_899 = asSInt(_T_898)
node _T_900 = eq(_T_899, asSInt(UInt<1>(0h0)))
node _T_901 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_902 = cvt(_T_901)
node _T_903 = and(_T_902, asSInt(UInt<29>(0h10000000)))
node _T_904 = asSInt(_T_903)
node _T_905 = eq(_T_904, asSInt(UInt<1>(0h0)))
node _T_906 = or(_T_855, _T_860)
node _T_907 = or(_T_906, _T_865)
node _T_908 = or(_T_907, _T_870)
node _T_909 = or(_T_908, _T_875)
node _T_910 = or(_T_909, _T_880)
node _T_911 = or(_T_910, _T_885)
node _T_912 = or(_T_911, _T_890)
node _T_913 = or(_T_912, _T_895)
node _T_914 = or(_T_913, _T_900)
node _T_915 = or(_T_914, _T_905)
node _T_916 = and(_T_850, _T_915)
node _T_917 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_918 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_919 = cvt(_T_918)
node _T_920 = and(_T_919, asSInt(UInt<17>(0h10000)))
node _T_921 = asSInt(_T_920)
node _T_922 = eq(_T_921, asSInt(UInt<1>(0h0)))
node _T_923 = and(_T_917, _T_922)
node _T_924 = or(UInt<1>(0h0), _T_916)
node _T_925 = or(_T_924, _T_923)
node _T_926 = and(_T_846, _T_925)
node _T_927 = asUInt(reset)
node _T_928 = eq(_T_927, UInt<1>(0h0))
when _T_928 :
node _T_929 = eq(_T_926, UInt<1>(0h0))
when _T_929 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_926, UInt<1>(0h1), "") : assert_41
node _T_930 = asUInt(reset)
node _T_931 = eq(_T_930, UInt<1>(0h0))
when _T_931 :
node _T_932 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_932 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_933 = asUInt(reset)
node _T_934 = eq(_T_933, UInt<1>(0h0))
when _T_934 :
node _T_935 = eq(is_aligned, UInt<1>(0h0))
when _T_935 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_936 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_937 = asUInt(reset)
node _T_938 = eq(_T_937, UInt<1>(0h0))
when _T_938 :
node _T_939 = eq(_T_936, UInt<1>(0h0))
when _T_939 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_936, UInt<1>(0h1), "") : assert_44
node _T_940 = eq(io.in.a.bits.mask, mask)
node _T_941 = asUInt(reset)
node _T_942 = eq(_T_941, UInt<1>(0h0))
when _T_942 :
node _T_943 = eq(_T_940, UInt<1>(0h0))
when _T_943 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_940, UInt<1>(0h1), "") : assert_45
node _T_944 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_944 :
node _T_945 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_946 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_947 = and(_T_945, _T_946)
node _T_948 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_949 = and(_T_947, _T_948)
node _T_950 = or(UInt<1>(0h0), _T_949)
node _T_951 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_952 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_953 = and(_T_951, _T_952)
node _T_954 = or(UInt<1>(0h0), _T_953)
node _T_955 = xor(io.in.a.bits.address, UInt<14>(0h3000))
node _T_956 = cvt(_T_955)
node _T_957 = and(_T_956, asSInt(UInt<13>(0h1000)))
node _T_958 = asSInt(_T_957)
node _T_959 = eq(_T_958, asSInt(UInt<1>(0h0)))
node _T_960 = and(_T_954, _T_959)
node _T_961 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_962 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_963 = cvt(_T_962)
node _T_964 = and(_T_963, asSInt(UInt<14>(0h2000)))
node _T_965 = asSInt(_T_964)
node _T_966 = eq(_T_965, asSInt(UInt<1>(0h0)))
node _T_967 = xor(io.in.a.bits.address, UInt<14>(0h2000))
node _T_968 = cvt(_T_967)
node _T_969 = and(_T_968, asSInt(UInt<11>(0h400)))
node _T_970 = asSInt(_T_969)
node _T_971 = eq(_T_970, asSInt(UInt<1>(0h0)))
node _T_972 = xor(io.in.a.bits.address, UInt<14>(0h2400))
node _T_973 = cvt(_T_972)
node _T_974 = and(_T_973, asSInt(UInt<9>(0h100)))
node _T_975 = asSInt(_T_974)
node _T_976 = eq(_T_975, asSInt(UInt<1>(0h0)))
node _T_977 = xor(io.in.a.bits.address, UInt<17>(0h10000))
node _T_978 = cvt(_T_977)
node _T_979 = and(_T_978, asSInt(UInt<17>(0h10000)))
node _T_980 = asSInt(_T_979)
node _T_981 = eq(_T_980, asSInt(UInt<1>(0h0)))
node _T_982 = xor(io.in.a.bits.address, UInt<21>(0h100000))
node _T_983 = cvt(_T_982)
node _T_984 = and(_T_983, asSInt(UInt<18>(0h2f000)))
node _T_985 = asSInt(_T_984)
node _T_986 = eq(_T_985, asSInt(UInt<1>(0h0)))
node _T_987 = xor(io.in.a.bits.address, UInt<26>(0h2000000))
node _T_988 = cvt(_T_987)
node _T_989 = and(_T_988, asSInt(UInt<17>(0h10000)))
node _T_990 = asSInt(_T_989)
node _T_991 = eq(_T_990, asSInt(UInt<1>(0h0)))
node _T_992 = xor(io.in.a.bits.address, UInt<26>(0h2010000))
node _T_993 = cvt(_T_992)
node _T_994 = and(_T_993, asSInt(UInt<13>(0h1000)))
node _T_995 = asSInt(_T_994)
node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0)))
node _T_997 = xor(io.in.a.bits.address, UInt<28>(0hc000000))
node _T_998 = cvt(_T_997)
node _T_999 = and(_T_998, asSInt(UInt<27>(0h4000000)))
node _T_1000 = asSInt(_T_999)
node _T_1001 = eq(_T_1000, asSInt(UInt<1>(0h0)))
node _T_1002 = xor(io.in.a.bits.address, UInt<29>(0h10020000))
node _T_1003 = cvt(_T_1002)
node _T_1004 = and(_T_1003, asSInt(UInt<13>(0h1000)))
node _T_1005 = asSInt(_T_1004)
node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0)))
node _T_1007 = or(_T_966, _T_971)
node _T_1008 = or(_T_1007, _T_976)
node _T_1009 = or(_T_1008, _T_981)
node _T_1010 = or(_T_1009, _T_986)
node _T_1011 = or(_T_1010, _T_991)
node _T_1012 = or(_T_1011, _T_996)
node _T_1013 = or(_T_1012, _T_1001)
node _T_1014 = or(_T_1013, _T_1006)
node _T_1015 = and(_T_961, _T_1014)
node _T_1016 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_1017 = leq(io.in.a.bits.size, UInt<3>(0h6))
node _T_1018 = and(_T_1016, _T_1017)
node _T_1019 = or(UInt<1>(0h0), _T_1018)
node _T_1020 = xor(io.in.a.bits.address, UInt<28>(0h8000000))
node _T_1021 = cvt(_T_1020)
node _T_1022 = and(_T_1021, asSInt(UInt<17>(0h10000)))
node _T_1023 = asSInt(_T_1022)
node _T_1024 = eq(_T_1023, asSInt(UInt<1>(0h0)))
node _T_1025 = xor(io.in.a.bits.address, UInt<32>(0h80000000))
node _T_1026 = cvt(_T_1025)
node _T_1027 = and(_T_1026, asSInt(UInt<29>(0h10000000)))
node _T_1028 = asSInt(_T_1027)
node _T_1029 = eq(_T_1028, asSInt(UInt<1>(0h0)))
node _T_1030 = or(_T_1024, _T_1029)
node _T_1031 = and(_T_1019, _T_1030)
node _T_1032 = or(UInt<1>(0h0), _T_960)
node _T_1033 = or(_T_1032, _T_1015)
node _T_1034 = or(_T_1033, _T_1031)
node _T_1035 = and(_T_950, _T_1034)
node _T_1036 = asUInt(reset)
node _T_1037 = eq(_T_1036, UInt<1>(0h0))
when _T_1037 :
node _T_1038 = eq(_T_1035, UInt<1>(0h0))
when _T_1038 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_1035, UInt<1>(0h1), "") : assert_46
node _T_1039 = asUInt(reset)
node _T_1040 = eq(_T_1039, UInt<1>(0h0))
when _T_1040 :
node _T_1041 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_1041 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_1042 = asUInt(reset)
node _T_1043 = eq(_T_1042, UInt<1>(0h0))
when _T_1043 :
node _T_1044 = eq(is_aligned, UInt<1>(0h0))
when _T_1044 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_1045 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_1046 = asUInt(reset)
node _T_1047 = eq(_T_1046, UInt<1>(0h0))
when _T_1047 :
node _T_1048 = eq(_T_1045, UInt<1>(0h0))
when _T_1048 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_1045, UInt<1>(0h1), "") : assert_49
node _T_1049 = eq(io.in.a.bits.mask, mask)
node _T_1050 = asUInt(reset)
node _T_1051 = eq(_T_1050, UInt<1>(0h0))
when _T_1051 :
node _T_1052 = eq(_T_1049, UInt<1>(0h0))
when _T_1052 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_1049, UInt<1>(0h1), "") : assert_50
node _T_1053 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_1054 = asUInt(reset)
node _T_1055 = eq(_T_1054, UInt<1>(0h0))
when _T_1055 :
node _T_1056 = eq(_T_1053, UInt<1>(0h0))
when _T_1056 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_1053, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_1057 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1058 = asUInt(reset)
node _T_1059 = eq(_T_1058, UInt<1>(0h0))
when _T_1059 :
node _T_1060 = eq(_T_1057, UInt<1>(0h0))
when _T_1060 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_1057, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8))
node _T_1061 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_1061 :
node _T_1062 = asUInt(reset)
node _T_1063 = eq(_T_1062, UInt<1>(0h0))
when _T_1063 :
node _T_1064 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1064 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_1065 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1066 = asUInt(reset)
node _T_1067 = eq(_T_1066, UInt<1>(0h0))
when _T_1067 :
node _T_1068 = eq(_T_1065, UInt<1>(0h0))
when _T_1068 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_1065, UInt<1>(0h1), "") : assert_54
node _T_1069 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1070 = asUInt(reset)
node _T_1071 = eq(_T_1070, UInt<1>(0h0))
when _T_1071 :
node _T_1072 = eq(_T_1069, UInt<1>(0h0))
when _T_1072 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_1069, UInt<1>(0h1), "") : assert_55
node _T_1073 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1074 = asUInt(reset)
node _T_1075 = eq(_T_1074, UInt<1>(0h0))
when _T_1075 :
node _T_1076 = eq(_T_1073, UInt<1>(0h0))
when _T_1076 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_1073, UInt<1>(0h1), "") : assert_56
node _T_1077 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1078 = asUInt(reset)
node _T_1079 = eq(_T_1078, UInt<1>(0h0))
when _T_1079 :
node _T_1080 = eq(_T_1077, UInt<1>(0h0))
when _T_1080 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_1077, UInt<1>(0h1), "") : assert_57
node _T_1081 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_1081 :
node _T_1082 = asUInt(reset)
node _T_1083 = eq(_T_1082, UInt<1>(0h0))
when _T_1083 :
node _T_1084 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1084 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_1085 = asUInt(reset)
node _T_1086 = eq(_T_1085, UInt<1>(0h0))
when _T_1086 :
node _T_1087 = eq(sink_ok, UInt<1>(0h0))
when _T_1087 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_1088 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1089 = asUInt(reset)
node _T_1090 = eq(_T_1089, UInt<1>(0h0))
when _T_1090 :
node _T_1091 = eq(_T_1088, UInt<1>(0h0))
when _T_1091 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_1088, UInt<1>(0h1), "") : assert_60
node _T_1092 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1093 = asUInt(reset)
node _T_1094 = eq(_T_1093, UInt<1>(0h0))
when _T_1094 :
node _T_1095 = eq(_T_1092, UInt<1>(0h0))
when _T_1095 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_1092, UInt<1>(0h1), "") : assert_61
node _T_1096 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1097 = asUInt(reset)
node _T_1098 = eq(_T_1097, UInt<1>(0h0))
when _T_1098 :
node _T_1099 = eq(_T_1096, UInt<1>(0h0))
when _T_1099 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_1096, UInt<1>(0h1), "") : assert_62
node _T_1100 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1101 = asUInt(reset)
node _T_1102 = eq(_T_1101, UInt<1>(0h0))
when _T_1102 :
node _T_1103 = eq(_T_1100, UInt<1>(0h0))
when _T_1103 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_1100, UInt<1>(0h1), "") : assert_63
node _T_1104 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1105 = or(UInt<1>(0h1), _T_1104)
node _T_1106 = asUInt(reset)
node _T_1107 = eq(_T_1106, UInt<1>(0h0))
when _T_1107 :
node _T_1108 = eq(_T_1105, UInt<1>(0h0))
when _T_1108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_1105, UInt<1>(0h1), "") : assert_64
node _T_1109 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_1109 :
node _T_1110 = asUInt(reset)
node _T_1111 = eq(_T_1110, UInt<1>(0h0))
when _T_1111 :
node _T_1112 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_1113 = asUInt(reset)
node _T_1114 = eq(_T_1113, UInt<1>(0h0))
when _T_1114 :
node _T_1115 = eq(sink_ok, UInt<1>(0h0))
when _T_1115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_1116 = geq(io.in.d.bits.size, UInt<2>(0h3))
node _T_1117 = asUInt(reset)
node _T_1118 = eq(_T_1117, UInt<1>(0h0))
when _T_1118 :
node _T_1119 = eq(_T_1116, UInt<1>(0h0))
when _T_1119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_1116, UInt<1>(0h1), "") : assert_67
node _T_1120 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1121 = asUInt(reset)
node _T_1122 = eq(_T_1121, UInt<1>(0h0))
when _T_1122 :
node _T_1123 = eq(_T_1120, UInt<1>(0h0))
when _T_1123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_1120, UInt<1>(0h1), "") : assert_68
node _T_1124 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_1125 = asUInt(reset)
node _T_1126 = eq(_T_1125, UInt<1>(0h0))
when _T_1126 :
node _T_1127 = eq(_T_1124, UInt<1>(0h0))
when _T_1127 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_1124, UInt<1>(0h1), "") : assert_69
node _T_1128 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1129 = or(_T_1128, io.in.d.bits.corrupt)
node _T_1130 = asUInt(reset)
node _T_1131 = eq(_T_1130, UInt<1>(0h0))
when _T_1131 :
node _T_1132 = eq(_T_1129, UInt<1>(0h0))
when _T_1132 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_1129, UInt<1>(0h1), "") : assert_70
node _T_1133 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1134 = or(UInt<1>(0h1), _T_1133)
node _T_1135 = asUInt(reset)
node _T_1136 = eq(_T_1135, UInt<1>(0h0))
when _T_1136 :
node _T_1137 = eq(_T_1134, UInt<1>(0h0))
when _T_1137 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_1134, UInt<1>(0h1), "") : assert_71
node _T_1138 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_1138 :
node _T_1139 = asUInt(reset)
node _T_1140 = eq(_T_1139, UInt<1>(0h0))
when _T_1140 :
node _T_1141 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1141 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_1142 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1143 = asUInt(reset)
node _T_1144 = eq(_T_1143, UInt<1>(0h0))
when _T_1144 :
node _T_1145 = eq(_T_1142, UInt<1>(0h0))
when _T_1145 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_1142, UInt<1>(0h1), "") : assert_73
node _T_1146 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1147 = asUInt(reset)
node _T_1148 = eq(_T_1147, UInt<1>(0h0))
when _T_1148 :
node _T_1149 = eq(_T_1146, UInt<1>(0h0))
when _T_1149 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_1146, UInt<1>(0h1), "") : assert_74
node _T_1150 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1151 = or(UInt<1>(0h1), _T_1150)
node _T_1152 = asUInt(reset)
node _T_1153 = eq(_T_1152, UInt<1>(0h0))
when _T_1153 :
node _T_1154 = eq(_T_1151, UInt<1>(0h0))
when _T_1154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_1151, UInt<1>(0h1), "") : assert_75
node _T_1155 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_1155 :
node _T_1156 = asUInt(reset)
node _T_1157 = eq(_T_1156, UInt<1>(0h0))
when _T_1157 :
node _T_1158 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1158 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_1159 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1160 = asUInt(reset)
node _T_1161 = eq(_T_1160, UInt<1>(0h0))
when _T_1161 :
node _T_1162 = eq(_T_1159, UInt<1>(0h0))
when _T_1162 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_1159, UInt<1>(0h1), "") : assert_77
node _T_1163 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1164 = or(_T_1163, io.in.d.bits.corrupt)
node _T_1165 = asUInt(reset)
node _T_1166 = eq(_T_1165, UInt<1>(0h0))
when _T_1166 :
node _T_1167 = eq(_T_1164, UInt<1>(0h0))
when _T_1167 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_1164, UInt<1>(0h1), "") : assert_78
node _T_1168 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1169 = or(UInt<1>(0h1), _T_1168)
node _T_1170 = asUInt(reset)
node _T_1171 = eq(_T_1170, UInt<1>(0h0))
when _T_1171 :
node _T_1172 = eq(_T_1169, UInt<1>(0h0))
when _T_1172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_1169, UInt<1>(0h1), "") : assert_79
node _T_1173 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_1173 :
node _T_1174 = asUInt(reset)
node _T_1175 = eq(_T_1174, UInt<1>(0h0))
when _T_1175 :
node _T_1176 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_1176 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_1177 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_1178 = asUInt(reset)
node _T_1179 = eq(_T_1178, UInt<1>(0h0))
when _T_1179 :
node _T_1180 = eq(_T_1177, UInt<1>(0h0))
when _T_1180 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_1177, UInt<1>(0h1), "") : assert_81
node _T_1181 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_1182 = asUInt(reset)
node _T_1183 = eq(_T_1182, UInt<1>(0h0))
when _T_1183 :
node _T_1184 = eq(_T_1181, UInt<1>(0h0))
when _T_1184 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_1181, UInt<1>(0h1), "") : assert_82
node _T_1185 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_1186 = or(UInt<1>(0h1), _T_1185)
node _T_1187 = asUInt(reset)
node _T_1188 = eq(_T_1187, UInt<1>(0h0))
when _T_1188 :
node _T_1189 = eq(_T_1186, UInt<1>(0h0))
when _T_1189 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_1186, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<64>(0h0)
connect _WIRE.bits.mask, UInt<8>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_1190 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_1191 = asUInt(reset)
node _T_1192 = eq(_T_1191, UInt<1>(0h0))
when _T_1192 :
node _T_1193 = eq(_T_1190, UInt<1>(0h0))
when _T_1193 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_1190, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<64>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_1194 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_1195 = asUInt(reset)
node _T_1196 = eq(_T_1195, UInt<1>(0h0))
when _T_1196 :
node _T_1197 = eq(_T_1194, UInt<1>(0h0))
when _T_1197 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_1194, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_4.bits.sink, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_1198 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_1199 = asUInt(reset)
node _T_1200 = eq(_T_1199, UInt<1>(0h0))
when _T_1200 :
node _T_1201 = eq(_T_1198, UInt<1>(0h0))
when _T_1201 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_1198, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_1202 = eq(a_first, UInt<1>(0h0))
node _T_1203 = and(io.in.a.valid, _T_1202)
when _T_1203 :
node _T_1204 = eq(io.in.a.bits.opcode, opcode)
node _T_1205 = asUInt(reset)
node _T_1206 = eq(_T_1205, UInt<1>(0h0))
when _T_1206 :
node _T_1207 = eq(_T_1204, UInt<1>(0h0))
when _T_1207 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_1204, UInt<1>(0h1), "") : assert_87
node _T_1208 = eq(io.in.a.bits.param, param)
node _T_1209 = asUInt(reset)
node _T_1210 = eq(_T_1209, UInt<1>(0h0))
when _T_1210 :
node _T_1211 = eq(_T_1208, UInt<1>(0h0))
when _T_1211 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_1208, UInt<1>(0h1), "") : assert_88
node _T_1212 = eq(io.in.a.bits.size, size)
node _T_1213 = asUInt(reset)
node _T_1214 = eq(_T_1213, UInt<1>(0h0))
when _T_1214 :
node _T_1215 = eq(_T_1212, UInt<1>(0h0))
when _T_1215 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_1212, UInt<1>(0h1), "") : assert_89
node _T_1216 = eq(io.in.a.bits.source, source)
node _T_1217 = asUInt(reset)
node _T_1218 = eq(_T_1217, UInt<1>(0h0))
when _T_1218 :
node _T_1219 = eq(_T_1216, UInt<1>(0h0))
when _T_1219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_1216, UInt<1>(0h1), "") : assert_90
node _T_1220 = eq(io.in.a.bits.address, address)
node _T_1221 = asUInt(reset)
node _T_1222 = eq(_T_1221, UInt<1>(0h0))
when _T_1222 :
node _T_1223 = eq(_T_1220, UInt<1>(0h0))
when _T_1223 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_1220, UInt<1>(0h1), "") : assert_91
node _T_1224 = and(io.in.a.ready, io.in.a.valid)
node _T_1225 = and(_T_1224, a_first)
when _T_1225 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_1226 = eq(d_first, UInt<1>(0h0))
node _T_1227 = and(io.in.d.valid, _T_1226)
when _T_1227 :
node _T_1228 = eq(io.in.d.bits.opcode, opcode_1)
node _T_1229 = asUInt(reset)
node _T_1230 = eq(_T_1229, UInt<1>(0h0))
when _T_1230 :
node _T_1231 = eq(_T_1228, UInt<1>(0h0))
when _T_1231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_1228, UInt<1>(0h1), "") : assert_92
node _T_1232 = eq(io.in.d.bits.param, param_1)
node _T_1233 = asUInt(reset)
node _T_1234 = eq(_T_1233, UInt<1>(0h0))
when _T_1234 :
node _T_1235 = eq(_T_1232, UInt<1>(0h0))
when _T_1235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_1232, UInt<1>(0h1), "") : assert_93
node _T_1236 = eq(io.in.d.bits.size, size_1)
node _T_1237 = asUInt(reset)
node _T_1238 = eq(_T_1237, UInt<1>(0h0))
when _T_1238 :
node _T_1239 = eq(_T_1236, UInt<1>(0h0))
when _T_1239 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_1236, UInt<1>(0h1), "") : assert_94
node _T_1240 = eq(io.in.d.bits.source, source_1)
node _T_1241 = asUInt(reset)
node _T_1242 = eq(_T_1241, UInt<1>(0h0))
when _T_1242 :
node _T_1243 = eq(_T_1240, UInt<1>(0h0))
when _T_1243 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_1240, UInt<1>(0h1), "") : assert_95
node _T_1244 = eq(io.in.d.bits.sink, sink)
node _T_1245 = asUInt(reset)
node _T_1246 = eq(_T_1245, UInt<1>(0h0))
when _T_1246 :
node _T_1247 = eq(_T_1244, UInt<1>(0h0))
when _T_1247 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_1244, UInt<1>(0h1), "") : assert_96
node _T_1248 = eq(io.in.d.bits.denied, denied)
node _T_1249 = asUInt(reset)
node _T_1250 = eq(_T_1249, UInt<1>(0h0))
when _T_1250 :
node _T_1251 = eq(_T_1248, UInt<1>(0h0))
when _T_1251 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_1248, UInt<1>(0h1), "") : assert_97
node _T_1252 = and(io.in.d.ready, io.in.d.valid)
node _T_1253 = and(_T_1252, d_first)
when _T_1253 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<8>
connect a_sizes_set, UInt<8>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<8>
connect a_size_lookup, UInt<8>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<5>
connect a_sizes_set_interm, UInt<5>(0h0)
node _T_1254 = and(io.in.a.valid, a_first_1)
node _T_1255 = and(_T_1254, UInt<1>(0h1))
when _T_1255 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_1256 = and(io.in.a.ready, io.in.a.valid)
node _T_1257 = and(_T_1256, a_first_1)
node _T_1258 = and(_T_1257, UInt<1>(0h1))
when _T_1258 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_1259 = dshr(inflight, io.in.a.bits.source)
node _T_1260 = bits(_T_1259, 0, 0)
node _T_1261 = eq(_T_1260, UInt<1>(0h0))
node _T_1262 = asUInt(reset)
node _T_1263 = eq(_T_1262, UInt<1>(0h0))
when _T_1263 :
node _T_1264 = eq(_T_1261, UInt<1>(0h0))
when _T_1264 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_1261, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<8>
connect d_sizes_clr, UInt<8>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1265 = and(io.in.d.valid, d_first_1)
node _T_1266 = and(_T_1265, UInt<1>(0h1))
node _T_1267 = eq(d_release_ack, UInt<1>(0h0))
node _T_1268 = and(_T_1266, _T_1267)
when _T_1268 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_1269 = and(io.in.d.ready, io.in.d.valid)
node _T_1270 = and(_T_1269, d_first_1)
node _T_1271 = and(_T_1270, UInt<1>(0h1))
node _T_1272 = eq(d_release_ack, UInt<1>(0h0))
node _T_1273 = and(_T_1271, _T_1272)
when _T_1273 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_1274 = and(io.in.d.valid, d_first_1)
node _T_1275 = and(_T_1274, UInt<1>(0h1))
node _T_1276 = eq(d_release_ack, UInt<1>(0h0))
node _T_1277 = and(_T_1275, _T_1276)
when _T_1277 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_1278 = dshr(inflight, io.in.d.bits.source)
node _T_1279 = bits(_T_1278, 0, 0)
node _T_1280 = or(_T_1279, same_cycle_resp)
node _T_1281 = asUInt(reset)
node _T_1282 = eq(_T_1281, UInt<1>(0h0))
when _T_1282 :
node _T_1283 = eq(_T_1280, UInt<1>(0h0))
when _T_1283 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_1280, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_1284 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_1285 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_1286 = or(_T_1284, _T_1285)
node _T_1287 = asUInt(reset)
node _T_1288 = eq(_T_1287, UInt<1>(0h0))
when _T_1288 :
node _T_1289 = eq(_T_1286, UInt<1>(0h0))
when _T_1289 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_1286, UInt<1>(0h1), "") : assert_100
node _T_1290 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_1291 = asUInt(reset)
node _T_1292 = eq(_T_1291, UInt<1>(0h0))
when _T_1292 :
node _T_1293 = eq(_T_1290, UInt<1>(0h0))
when _T_1293 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_1290, UInt<1>(0h1), "") : assert_101
else :
node _T_1294 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_1295 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_1296 = or(_T_1294, _T_1295)
node _T_1297 = asUInt(reset)
node _T_1298 = eq(_T_1297, UInt<1>(0h0))
when _T_1298 :
node _T_1299 = eq(_T_1296, UInt<1>(0h0))
when _T_1299 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_1296, UInt<1>(0h1), "") : assert_102
node _T_1300 = eq(io.in.d.bits.size, a_size_lookup)
node _T_1301 = asUInt(reset)
node _T_1302 = eq(_T_1301, UInt<1>(0h0))
when _T_1302 :
node _T_1303 = eq(_T_1300, UInt<1>(0h0))
when _T_1303 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_1300, UInt<1>(0h1), "") : assert_103
node _T_1304 = and(io.in.d.valid, d_first_1)
node _T_1305 = and(_T_1304, a_first_1)
node _T_1306 = and(_T_1305, io.in.a.valid)
node _T_1307 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_1308 = and(_T_1306, _T_1307)
node _T_1309 = eq(d_release_ack, UInt<1>(0h0))
node _T_1310 = and(_T_1308, _T_1309)
when _T_1310 :
node _T_1311 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_1312 = or(_T_1311, io.in.a.ready)
node _T_1313 = asUInt(reset)
node _T_1314 = eq(_T_1313, UInt<1>(0h0))
when _T_1314 :
node _T_1315 = eq(_T_1312, UInt<1>(0h0))
when _T_1315 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_1312, UInt<1>(0h1), "") : assert_104
node _T_1316 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_1317 = orr(a_set_wo_ready)
node _T_1318 = eq(_T_1317, UInt<1>(0h0))
node _T_1319 = or(_T_1316, _T_1318)
node _T_1320 = asUInt(reset)
node _T_1321 = eq(_T_1320, UInt<1>(0h0))
when _T_1321 :
node _T_1322 = eq(_T_1319, UInt<1>(0h0))
when _T_1322 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_1319, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_153
node _T_1323 = orr(inflight)
node _T_1324 = eq(_T_1323, UInt<1>(0h0))
node _T_1325 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_1326 = or(_T_1324, _T_1325)
node _T_1327 = lt(watchdog, plusarg_reader.out)
node _T_1328 = or(_T_1326, _T_1327)
node _T_1329 = asUInt(reset)
node _T_1330 = eq(_T_1329, UInt<1>(0h0))
when _T_1330 :
node _T_1331 = eq(_T_1328, UInt<1>(0h0))
when _T_1331 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_1328, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_1332 = and(io.in.a.ready, io.in.a.valid)
node _T_1333 = and(io.in.d.ready, io.in.d.valid)
node _T_1334 = or(_T_1332, _T_1333)
when _T_1334 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<64>(0h0)
connect _c_first_WIRE.bits.address, UInt<32>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<4>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<8>
connect c_sizes_set, UInt<8>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<8>
connect c_size_lookup, UInt<8>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<5>
connect c_sizes_set_interm, UInt<5>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<64>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_1335 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<64>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_1336 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_1337 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_1338 = and(_T_1336, _T_1337)
node _T_1339 = and(_T_1335, _T_1338)
when _T_1339 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<64>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_1340 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_1341 = and(_T_1340, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<64>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_1342 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_1343 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_1344 = and(_T_1342, _T_1343)
node _T_1345 = and(_T_1341, _T_1344)
when _T_1345 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<64>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_1346 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_1347 = bits(_T_1346, 0, 0)
node _T_1348 = eq(_T_1347, UInt<1>(0h0))
node _T_1349 = asUInt(reset)
node _T_1350 = eq(_T_1349, UInt<1>(0h0))
when _T_1350 :
node _T_1351 = eq(_T_1348, UInt<1>(0h0))
when _T_1351 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_1348, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<8>
connect d_sizes_clr_1, UInt<8>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_1352 = and(io.in.d.valid, d_first_2)
node _T_1353 = and(_T_1352, UInt<1>(0h1))
node _T_1354 = and(_T_1353, d_release_ack_1)
when _T_1354 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_1355 = and(io.in.d.ready, io.in.d.valid)
node _T_1356 = and(_T_1355, d_first_2)
node _T_1357 = and(_T_1356, UInt<1>(0h1))
node _T_1358 = and(_T_1357, d_release_ack_1)
when _T_1358 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_1359 = and(io.in.d.valid, d_first_2)
node _T_1360 = and(_T_1359, UInt<1>(0h1))
node _T_1361 = and(_T_1360, d_release_ack_1)
when _T_1361 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_1362 = dshr(inflight_1, io.in.d.bits.source)
node _T_1363 = bits(_T_1362, 0, 0)
node _T_1364 = or(_T_1363, same_cycle_resp_1)
node _T_1365 = asUInt(reset)
node _T_1366 = eq(_T_1365, UInt<1>(0h0))
when _T_1366 :
node _T_1367 = eq(_T_1364, UInt<1>(0h0))
when _T_1367 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_1364, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<64>(0h0)
connect _WIRE_16.bits.address, UInt<32>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<4>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_1368 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_1369 = asUInt(reset)
node _T_1370 = eq(_T_1369, UInt<1>(0h0))
when _T_1370 :
node _T_1371 = eq(_T_1368, UInt<1>(0h0))
when _T_1371 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_1368, UInt<1>(0h1), "") : assert_109
else :
node _T_1372 = eq(io.in.d.bits.size, c_size_lookup)
node _T_1373 = asUInt(reset)
node _T_1374 = eq(_T_1373, UInt<1>(0h0))
when _T_1374 :
node _T_1375 = eq(_T_1372, UInt<1>(0h0))
when _T_1375 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_1372, UInt<1>(0h1), "") : assert_110
node _T_1376 = and(io.in.d.valid, d_first_2)
node _T_1377 = and(_T_1376, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<64>(0h0)
connect _WIRE_18.bits.address, UInt<32>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<4>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_1378 = and(_T_1377, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<64>(0h0)
connect _WIRE_20.bits.address, UInt<32>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<4>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_1379 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_1380 = and(_T_1378, _T_1379)
node _T_1381 = and(_T_1380, d_release_ack_1)
node _T_1382 = eq(c_probe_ack, UInt<1>(0h0))
node _T_1383 = and(_T_1381, _T_1382)
when _T_1383 :
node _T_1384 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<64>(0h0)
connect _WIRE_22.bits.address, UInt<32>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<4>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_1385 = or(_T_1384, _WIRE_23.ready)
node _T_1386 = asUInt(reset)
node _T_1387 = eq(_T_1386, UInt<1>(0h0))
when _T_1387 :
node _T_1388 = eq(_T_1385, UInt<1>(0h0))
when _T_1388 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_1385, UInt<1>(0h1), "") : assert_111
node _T_1389 = orr(c_set_wo_ready)
when _T_1389 :
node _T_1390 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_1391 = asUInt(reset)
node _T_1392 = eq(_T_1391, UInt<1>(0h0))
when _T_1392 :
node _T_1393 = eq(_T_1390, UInt<1>(0h0))
when _T_1393 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_1390, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_154
node _T_1394 = orr(inflight_1)
node _T_1395 = eq(_T_1394, UInt<1>(0h0))
node _T_1396 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_1397 = or(_T_1395, _T_1396)
node _T_1398 = lt(watchdog_1, plusarg_reader_1.out)
node _T_1399 = or(_T_1397, _T_1398)
node _T_1400 = asUInt(reset)
node _T_1401 = eq(_T_1400, UInt<1>(0h0))
when _T_1401 :
node _T_1402 = eq(_T_1399, UInt<1>(0h0))
when _T_1402 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:31)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_1399, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<64>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_1403 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_1404 = and(io.in.d.ready, io.in.d.valid)
node _T_1405 = or(_T_1403, _T_1404)
when _T_1405 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_73( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14]
input io_in_a_bits_source, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14]
input io_in_a_bits_corrupt, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71]
wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg [8:0] a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [2:0] param; // @[Monitor.scala:388:22]
reg [3:0] size; // @[Monitor.scala:389:22]
reg source; // @[Monitor.scala:390:22]
reg [31:0] address; // @[Monitor.scala:391:22]
reg [8:0] d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [3:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg [2:0] sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [7:0] inflight_sizes; // @[Monitor.scala:618:33]
reg [8:0] a_first_counter_1; // @[Edges.scala:229:27]
wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [8:0] d_first_counter_1; // @[Edges.scala:229:27]
wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25]
wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg [8:0] d_first_counter_2; // @[Edges.scala:229:27]
wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_6 :
output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>}
node rawIn_exp = bits(io.in, 31, 23)
node _rawIn_isZero_T = bits(rawIn_exp, 8, 6)
node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0))
node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7)
node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3))
wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}
node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T)
connect rawIn.isNaN, _rawIn_out_isNaN_T_1
node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6)
node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0))
node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1)
connect rawIn.isInf, _rawIn_out_isInf_T_2
connect rawIn.isZero, rawIn_isZero
node _rawIn_out_sign_T = bits(io.in, 32, 32)
connect rawIn.sign, _rawIn_out_sign_T
node _rawIn_out_sExp_T = cvt(rawIn_exp)
connect rawIn.sExp, _rawIn_out_sExp_T
node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0))
node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T)
node _rawIn_out_sig_T_2 = bits(io.in, 22, 0)
node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2)
connect rawIn.sig, _rawIn_out_sig_T_3
inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is24_oe11_os53_3
node _roundAnyRawFNToRecFN_io_invalidExc_T = bits(rawIn.sig, 22, 22)
node _roundAnyRawFNToRecFN_io_invalidExc_T_1 = eq(_roundAnyRawFNToRecFN_io_invalidExc_T, UInt<1>(0h0))
node _roundAnyRawFNToRecFN_io_invalidExc_T_2 = and(rawIn.isNaN, _roundAnyRawFNToRecFN_io_invalidExc_T_1)
connect roundAnyRawFNToRecFN.io.invalidExc, _roundAnyRawFNToRecFN_io_invalidExc_T_2
connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundAnyRawFNToRecFN.io.in.sig, rawIn.sig
connect roundAnyRawFNToRecFN.io.in.sExp, rawIn.sExp
connect roundAnyRawFNToRecFN.io.in.sign, rawIn.sign
connect roundAnyRawFNToRecFN.io.in.isZero, rawIn.isZero
connect roundAnyRawFNToRecFN.io.in.isInf, rawIn.isInf
connect roundAnyRawFNToRecFN.io.in.isNaN, rawIn.isNaN
connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundAnyRawFNToRecFN.io.out
connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags | module RecFNToRecFN_6( // @[RecFNToRecFN.scala:44:5]
input [32:0] io_in, // @[RecFNToRecFN.scala:48:16]
output [64:0] io_out // @[RecFNToRecFN.scala:48:16]
);
wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5]
wire io_detectTininess = 1'h0; // @[RecFNToRecFN.scala:44:5]
wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16, :72:19]
wire [64:0] io_out_0; // @[RecFNToRecFN.scala:44:5]
wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5]
wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21]
wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28]
wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}]
wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23]
wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28]
wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}]
wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33]
wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33]
wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25]
wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27]
wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44]
wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23]
wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23]
wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23]
wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23]
wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41]
wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41]
assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}]
assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33]
wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}]
assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}]
assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33]
assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25]
assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25]
assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27]
assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27]
wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35]
wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}]
wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49]
assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}]
assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44]
wire _roundAnyRawFNToRecFN_io_invalidExc_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23]
wire _roundAnyRawFNToRecFN_io_invalidExc_T_1 = ~_roundAnyRawFNToRecFN_io_invalidExc_T; // @[common.scala:82:{49,56}]
wire _roundAnyRawFNToRecFN_io_invalidExc_T_2 = rawIn_isNaN & _roundAnyRawFNToRecFN_io_invalidExc_T_1; // @[rawFloatFromRecFN.scala:55:23]
RoundAnyRawFNToRecFN_ie8_is24_oe11_os53_3 roundAnyRawFNToRecFN ( // @[RecFNToRecFN.scala:72:19]
.io_invalidExc (_roundAnyRawFNToRecFN_io_invalidExc_T_2), // @[common.scala:82:46]
.io_in_isNaN (rawIn_isNaN), // @[rawFloatFromRecFN.scala:55:23]
.io_in_isInf (rawIn_isInf), // @[rawFloatFromRecFN.scala:55:23]
.io_in_isZero (rawIn_isZero_0), // @[rawFloatFromRecFN.scala:55:23]
.io_in_sign (rawIn_sign), // @[rawFloatFromRecFN.scala:55:23]
.io_in_sExp (rawIn_sExp), // @[rawFloatFromRecFN.scala:55:23]
.io_in_sig (rawIn_sig), // @[rawFloatFromRecFN.scala:55:23]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags)
); // @[RecFNToRecFN.scala:72:19]
assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_293 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_293( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_11 :
input clock : Clock
input reset : Reset
output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, flip grant : UInt<1>, iss_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip in_uop : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, out_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, flip brupdate : { b1 : { resolve_mask : UInt<12>, mispredict_mask : UInt<12>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip kill : UInt<1>, flip clear : UInt<1>, flip squash_grant : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip child_rebusys : UInt<2>}
regreset slot_valid : UInt<1>, clock, reset, UInt<1>(0h0)
reg slot_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock
wire next_valid : UInt<1>
connect next_valid, slot_valid
wire next_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect next_uop_out, slot_uop
node _next_uop_out_br_mask_T = not(io.brupdate.b1.resolve_mask)
node _next_uop_out_br_mask_T_1 = and(slot_uop.br_mask, _next_uop_out_br_mask_T)
connect next_uop_out.br_mask, _next_uop_out_br_mask_T_1
wire next_uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}
connect next_uop, next_uop_out
node _killed_T = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask)
node _killed_T_1 = neq(_killed_T, UInt<1>(0h0))
node killed = or(_killed_T_1, io.kill)
connect io.valid, slot_valid
connect io.out_uop, next_uop
node _io_will_be_valid_T = eq(killed, UInt<1>(0h0))
node _io_will_be_valid_T_1 = and(next_valid, _io_will_be_valid_T)
connect io.will_be_valid, _io_will_be_valid_T_1
when io.kill :
connect slot_valid, UInt<1>(0h0)
else :
when io.in_uop.valid :
connect slot_valid, UInt<1>(0h1)
else :
when io.clear :
connect slot_valid, UInt<1>(0h0)
else :
node _slot_valid_T = eq(killed, UInt<1>(0h0))
node _slot_valid_T_1 = and(next_valid, _slot_valid_T)
connect slot_valid, _slot_valid_T_1
when io.in_uop.valid :
connect slot_uop, io.in_uop.bits
node _T = eq(slot_valid, UInt<1>(0h0))
node _T_1 = or(_T, io.clear)
node _T_2 = or(_T_1, io.kill)
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:79 assert (!slot_valid || io.clear || io.kill)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
else :
connect slot_uop, next_uop
connect next_uop.iw_p1_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p2_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p3_bypass_hint, UInt<1>(0h0)
connect next_uop.iw_p1_speculative_child, UInt<1>(0h0)
connect next_uop.iw_p2_speculative_child, UInt<1>(0h0)
wire rebusied_prs1 : UInt<1>
connect rebusied_prs1, UInt<1>(0h0)
wire rebusied_prs2 : UInt<1>
connect rebusied_prs2, UInt<1>(0h0)
node rebusied = or(rebusied_prs1, rebusied_prs2)
node prs1_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs1)
node prs1_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs1)
node prs2_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs2)
node prs2_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs2)
node prs3_matches_0 = eq(io.wakeup_ports[0].bits.uop.pdst, slot_uop.prs3)
node prs3_matches_1 = eq(io.wakeup_ports[1].bits.uop.pdst, slot_uop.prs3)
node prs1_wakeups_0 = and(io.wakeup_ports[0].valid, prs1_matches_0)
node prs1_wakeups_1 = and(io.wakeup_ports[1].valid, prs1_matches_1)
node prs2_wakeups_0 = and(io.wakeup_ports[0].valid, prs2_matches_0)
node prs2_wakeups_1 = and(io.wakeup_ports[1].valid, prs2_matches_1)
node prs3_wakeups_0 = and(io.wakeup_ports[0].valid, prs3_matches_0)
node prs3_wakeups_1 = and(io.wakeup_ports[1].valid, prs3_matches_1)
node prs1_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs1_matches_0)
node prs1_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs1_matches_1)
node prs2_rebusys_0 = and(io.wakeup_ports[0].bits.rebusy, prs2_matches_0)
node prs2_rebusys_1 = and(io.wakeup_ports[1].bits.rebusy, prs2_matches_1)
node _T_6 = or(prs1_wakeups_0, prs1_wakeups_1)
when _T_6 :
connect next_uop.prs1_busy, UInt<1>(0h0)
node _next_uop_iw_p1_speculative_child_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p1_speculative_child_T_2 = or(_next_uop_iw_p1_speculative_child_T, _next_uop_iw_p1_speculative_child_T_1)
wire _next_uop_iw_p1_speculative_child_WIRE : UInt<2>
connect _next_uop_iw_p1_speculative_child_WIRE, _next_uop_iw_p1_speculative_child_T_2
connect next_uop.iw_p1_speculative_child, _next_uop_iw_p1_speculative_child_WIRE
node _next_uop_iw_p1_bypass_hint_T = mux(prs1_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_1 = mux(prs1_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p1_bypass_hint_T_2 = or(_next_uop_iw_p1_bypass_hint_T, _next_uop_iw_p1_bypass_hint_T_1)
wire _next_uop_iw_p1_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p1_bypass_hint_WIRE, _next_uop_iw_p1_bypass_hint_T_2
connect next_uop.iw_p1_bypass_hint, _next_uop_iw_p1_bypass_hint_WIRE
node _T_7 = or(prs1_rebusys_0, prs1_rebusys_1)
node _T_8 = and(io.child_rebusys, slot_uop.iw_p1_speculative_child)
node _T_9 = neq(_T_8, UInt<1>(0h0))
node _T_10 = or(_T_7, _T_9)
node _T_11 = eq(slot_uop.lrs1_rtype, UInt<2>(0h0))
node _T_12 = and(_T_10, _T_11)
when _T_12 :
connect next_uop.prs1_busy, UInt<1>(0h1)
connect rebusied_prs1, UInt<1>(0h1)
node _T_13 = or(prs2_wakeups_0, prs2_wakeups_1)
when _T_13 :
connect next_uop.prs2_busy, UInt<1>(0h0)
node _next_uop_iw_p2_speculative_child_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.speculative_mask, UInt<1>(0h0))
node _next_uop_iw_p2_speculative_child_T_2 = or(_next_uop_iw_p2_speculative_child_T, _next_uop_iw_p2_speculative_child_T_1)
wire _next_uop_iw_p2_speculative_child_WIRE : UInt<2>
connect _next_uop_iw_p2_speculative_child_WIRE, _next_uop_iw_p2_speculative_child_T_2
connect next_uop.iw_p2_speculative_child, _next_uop_iw_p2_speculative_child_WIRE
node _next_uop_iw_p2_bypass_hint_T = mux(prs2_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_1 = mux(prs2_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p2_bypass_hint_T_2 = or(_next_uop_iw_p2_bypass_hint_T, _next_uop_iw_p2_bypass_hint_T_1)
wire _next_uop_iw_p2_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p2_bypass_hint_WIRE, _next_uop_iw_p2_bypass_hint_T_2
connect next_uop.iw_p2_bypass_hint, _next_uop_iw_p2_bypass_hint_WIRE
node _T_14 = or(prs2_rebusys_0, prs2_rebusys_1)
node _T_15 = and(io.child_rebusys, slot_uop.iw_p2_speculative_child)
node _T_16 = neq(_T_15, UInt<1>(0h0))
node _T_17 = or(_T_14, _T_16)
node _T_18 = eq(slot_uop.lrs2_rtype, UInt<2>(0h0))
node _T_19 = and(_T_17, _T_18)
when _T_19 :
connect next_uop.prs2_busy, UInt<1>(0h1)
connect rebusied_prs2, UInt<1>(0h1)
node _T_20 = or(prs3_wakeups_0, prs3_wakeups_1)
when _T_20 :
connect next_uop.prs3_busy, UInt<1>(0h0)
node _next_uop_iw_p3_bypass_hint_T = mux(prs3_wakeups_0, io.wakeup_ports[0].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_1 = mux(prs3_wakeups_1, io.wakeup_ports[1].bits.bypassable, UInt<1>(0h0))
node _next_uop_iw_p3_bypass_hint_T_2 = or(_next_uop_iw_p3_bypass_hint_T, _next_uop_iw_p3_bypass_hint_T_1)
wire _next_uop_iw_p3_bypass_hint_WIRE : UInt<1>
connect _next_uop_iw_p3_bypass_hint_WIRE, _next_uop_iw_p3_bypass_hint_T_2
connect next_uop.iw_p3_bypass_hint, _next_uop_iw_p3_bypass_hint_WIRE
node _T_21 = eq(io.pred_wakeup_port.bits, slot_uop.ppred)
node _T_22 = and(io.pred_wakeup_port.valid, _T_21)
when _T_22 :
connect next_uop.ppred_busy, UInt<1>(0h0)
node _iss_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0))
node _iss_ready_T_1 = eq(slot_uop.prs2_busy, UInt<1>(0h0))
node _iss_ready_T_2 = and(_iss_ready_T, _iss_ready_T_1)
node _iss_ready_T_3 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _iss_ready_T_4 = eq(_iss_ready_T_3, UInt<1>(0h0))
node _iss_ready_T_5 = and(_iss_ready_T_2, _iss_ready_T_4)
node _iss_ready_T_6 = and(slot_uop.prs3_busy, UInt<1>(0h1))
node _iss_ready_T_7 = eq(_iss_ready_T_6, UInt<1>(0h0))
node iss_ready = and(_iss_ready_T_5, _iss_ready_T_7)
node _agen_ready_T = eq(slot_uop.prs1_busy, UInt<1>(0h0))
node _agen_ready_T_1 = and(slot_uop.fu_code[1], _agen_ready_T)
node _agen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _agen_ready_T_3 = eq(_agen_ready_T_2, UInt<1>(0h0))
node _agen_ready_T_4 = and(_agen_ready_T_1, _agen_ready_T_3)
node agen_ready = and(_agen_ready_T_4, UInt<1>(0h0))
node _dgen_ready_T = eq(slot_uop.prs2_busy, UInt<1>(0h0))
node _dgen_ready_T_1 = and(slot_uop.fu_code[2], _dgen_ready_T)
node _dgen_ready_T_2 = and(slot_uop.ppred_busy, UInt<1>(0h1))
node _dgen_ready_T_3 = eq(_dgen_ready_T_2, UInt<1>(0h0))
node _dgen_ready_T_4 = and(_dgen_ready_T_1, _dgen_ready_T_3)
node dgen_ready = and(_dgen_ready_T_4, UInt<1>(0h0))
node _io_request_T = eq(slot_uop.iw_issued, UInt<1>(0h0))
node _io_request_T_1 = and(slot_valid, _io_request_T)
node _io_request_T_2 = or(iss_ready, agen_ready)
node _io_request_T_3 = or(_io_request_T_2, dgen_ready)
node _io_request_T_4 = and(_io_request_T_1, _io_request_T_3)
connect io.request, _io_request_T_4
connect io.iss_uop, slot_uop
connect next_uop.iw_issued, UInt<1>(0h0)
connect next_uop.iw_issued_partial_agen, UInt<1>(0h0)
connect next_uop.iw_issued_partial_dgen, UInt<1>(0h0)
node _T_23 = eq(io.squash_grant, UInt<1>(0h0))
node _T_24 = and(io.grant, _T_23)
when _T_24 :
connect next_uop.iw_issued, UInt<1>(0h1)
node _T_25 = and(slot_valid, slot_uop.iw_issued)
when _T_25 :
connect next_valid, rebusied | module IssueSlot_11( // @[issue-slot.scala:49:7]
input clock, // @[issue-slot.scala:49:7]
input reset, // @[issue-slot.scala:49:7]
output io_valid, // @[issue-slot.scala:52:14]
output io_will_be_valid, // @[issue-slot.scala:52:14]
output io_request, // @[issue-slot.scala:52:14]
input io_grant, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_iss_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_iss_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_iss_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_iss_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_issued, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_iss_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [11:0] io_iss_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_br_type, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_iss_uop_is_amo, // @[issue-slot.scala:52:14]
output io_iss_uop_is_eret, // @[issue-slot.scala:52:14]
output io_iss_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_iss_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_iss_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_iss_uop_taken, // @[issue-slot.scala:52:14]
output io_iss_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_iss_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_rob_idx, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [3:0] io_iss_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_ppred, // @[issue-slot.scala:52:14]
output io_iss_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_iss_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_iss_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_iss_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_iss_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_mem_size, // @[issue-slot.scala:52:14]
output io_iss_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_iss_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_iss_uop_is_unique, // @[issue-slot.scala:52:14]
output io_iss_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_iss_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_iss_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_iss_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_iss_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_iss_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_iss_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_iss_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_iss_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_iss_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_iss_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_in_uop_valid, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:52:14]
input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iq_type_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_0, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_4, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_5, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_6, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_7, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_8, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fu_code_9, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_br_type, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfb, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_fencei, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sfence, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_amo, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_eret, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_rocc, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:52:14]
input io_in_uop_bits_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:52:14]
input io_in_uop_bits_taken, // @[issue-slot.scala:52:14]
input io_in_uop_bits_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_op2_sel, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:52:14]
input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:52:14]
input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:52:14]
input io_in_uop_bits_exception, // @[issue-slot.scala:52:14]
input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:52:14]
input io_in_uop_bits_mem_signed, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_uses_stq, // @[issue-slot.scala:52:14]
input io_in_uop_bits_is_unique, // @[issue-slot.scala:52:14]
input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_csr_cmd, // @[issue-slot.scala:52:14]
input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_in_uop_bits_frs3_en, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_in_uop_bits_fcn_op, // @[issue-slot.scala:52:14]
input io_in_uop_bits_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_in_uop_bits_fp_typ, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:52:14]
input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_inst, // @[issue-slot.scala:52:14]
output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:52:14]
output io_out_uop_is_rvc, // @[issue-slot.scala:52:14]
output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_0, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_1, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_2, // @[issue-slot.scala:52:14]
output io_out_uop_iq_type_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_0, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_1, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_2, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_3, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_4, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_5, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_6, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_7, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_8, // @[issue-slot.scala:52:14]
output io_out_uop_fu_code_9, // @[issue-slot.scala:52:14]
output io_out_uop_iw_issued, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
output io_out_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dis_col_sel, // @[issue-slot.scala:52:14]
output [11:0] io_out_uop_br_mask, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_br_type, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfb, // @[issue-slot.scala:52:14]
output io_out_uop_is_fence, // @[issue-slot.scala:52:14]
output io_out_uop_is_fencei, // @[issue-slot.scala:52:14]
output io_out_uop_is_sfence, // @[issue-slot.scala:52:14]
output io_out_uop_is_amo, // @[issue-slot.scala:52:14]
output io_out_uop_is_eret, // @[issue-slot.scala:52:14]
output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
output io_out_uop_is_rocc, // @[issue-slot.scala:52:14]
output io_out_uop_is_mov, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:52:14]
output io_out_uop_edge_inst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:52:14]
output io_out_uop_taken, // @[issue-slot.scala:52:14]
output io_out_uop_imm_rename, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_imm_sel, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_pimm, // @[issue-slot.scala:52:14]
output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_op1_sel, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_op2_sel, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
output io_out_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_rob_idx, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_ldq_idx, // @[issue-slot.scala:52:14]
output [3:0] io_out_uop_stq_idx, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_pdst, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs1, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs2, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_prs3, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_ppred, // @[issue-slot.scala:52:14]
output io_out_uop_prs1_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs2_busy, // @[issue-slot.scala:52:14]
output io_out_uop_prs3_busy, // @[issue-slot.scala:52:14]
output io_out_uop_ppred_busy, // @[issue-slot.scala:52:14]
output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:52:14]
output io_out_uop_exception, // @[issue-slot.scala:52:14]
output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:52:14]
output io_out_uop_mem_signed, // @[issue-slot.scala:52:14]
output io_out_uop_uses_ldq, // @[issue-slot.scala:52:14]
output io_out_uop_uses_stq, // @[issue-slot.scala:52:14]
output io_out_uop_is_unique, // @[issue-slot.scala:52:14]
output io_out_uop_flush_on_commit, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_csr_cmd, // @[issue-slot.scala:52:14]
output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_ldst, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:52:14]
output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
output io_out_uop_frs3_en, // @[issue-slot.scala:52:14]
output io_out_uop_fcn_dw, // @[issue-slot.scala:52:14]
output [4:0] io_out_uop_fcn_op, // @[issue-slot.scala:52:14]
output io_out_uop_fp_val, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_fp_rm, // @[issue-slot.scala:52:14]
output [1:0] io_out_uop_fp_typ, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_debug_if, // @[issue-slot.scala:52:14]
output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:52:14]
output [2:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_br_type, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_eret, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_taken, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_brupdate_b2_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_brupdate_b2_mispredict, // @[issue-slot.scala:52:14]
input io_brupdate_b2_taken, // @[issue-slot.scala:52:14]
input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:52:14]
input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:52:14]
input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:52:14]
input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:52:14]
input io_kill, // @[issue-slot.scala:52:14]
input io_clear, // @[issue-slot.scala:52:14]
input io_squash_grant, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_0_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_0_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_0_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_0_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_0_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_0_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_0_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_0_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_0_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_0_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_0_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_valid, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_inst, // @[issue-slot.scala:52:14]
input [31:0] io_wakeup_ports_1_bits_uop_debug_inst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rvc, // @[issue-slot.scala:52:14]
input [39:0] io_wakeup_ports_1_bits_uop_debug_pc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iq_type_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_0, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_4, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_5, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_6, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_7, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_8, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fu_code_9, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_agen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel, // @[issue-slot.scala:52:14]
input [11:0] io_wakeup_ports_1_bits_uop_br_mask, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_tag, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_br_type, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfb, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_fencei, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sfence, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_amo, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_eret, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_sys_pc2epc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_rocc, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_mov, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ftq_idx, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_edge_inst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_pc_lob, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_taken, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_imm_rename, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_imm_sel, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_pimm, // @[issue-slot.scala:52:14]
input [19:0] io_wakeup_ports_1_bits_uop_imm_packed, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_op1_sel, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_op2_sel, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ldst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wen, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren1, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren2, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_ren3, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap12, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_swap23, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fromint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_toint, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_fma, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_div, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_wflags, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_ctrl_vec, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_rob_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_ldq_idx, // @[issue-slot.scala:52:14]
input [3:0] io_wakeup_ports_1_bits_uop_stq_idx, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_rxq_idx, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_pdst, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs1, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs2, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_prs3, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_ppred, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs1_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs2_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_prs3_busy, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ppred_busy, // @[issue-slot.scala:52:14]
input [6:0] io_wakeup_ports_1_bits_uop_stale_pdst, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_exception, // @[issue-slot.scala:52:14]
input [63:0] io_wakeup_ports_1_bits_uop_exc_cause, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_mem_cmd, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_mem_size, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_mem_signed, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_ldq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_uses_stq, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_is_unique, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_flush_on_commit, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_csr_cmd, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_ldst_is_rs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_ldst, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs1, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs2, // @[issue-slot.scala:52:14]
input [5:0] io_wakeup_ports_1_bits_uop_lrs3, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_dst_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_frs3_en, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fcn_dw, // @[issue-slot.scala:52:14]
input [4:0] io_wakeup_ports_1_bits_uop_fcn_op, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_fp_val, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_fp_rm, // @[issue-slot.scala:52:14]
input [1:0] io_wakeup_ports_1_bits_uop_fp_typ, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_pf_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ae_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_xcpt_ma_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_debug_if, // @[issue-slot.scala:52:14]
input io_wakeup_ports_1_bits_uop_bp_xcpt_if, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc, // @[issue-slot.scala:52:14]
input [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc // @[issue-slot.scala:52:14]
);
wire [11:0] next_uop_out_br_mask; // @[util.scala:104:23]
wire io_grant_0 = io_grant; // @[issue-slot.scala:49:7]
wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_0_0 = io_in_uop_bits_iq_type_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_1_0 = io_in_uop_bits_iq_type_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_2_0 = io_in_uop_bits_iq_type_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iq_type_3_0 = io_in_uop_bits_iq_type_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_0_0 = io_in_uop_bits_fu_code_0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_1_0 = io_in_uop_bits_fu_code_1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_2_0 = io_in_uop_bits_fu_code_2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_3_0 = io_in_uop_bits_fu_code_3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_4_0 = io_in_uop_bits_fu_code_4; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_5_0 = io_in_uop_bits_fu_code_5; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_6_0 = io_in_uop_bits_fu_code_6; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_7_0 = io_in_uop_bits_fu_code_7; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_8_0 = io_in_uop_bits_fu_code_8; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fu_code_9_0 = io_in_uop_bits_fu_code_9; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_iw_p1_speculative_child_0 = io_in_uop_bits_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_iw_p2_speculative_child_0 = io_in_uop_bits_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p1_bypass_hint_0 = io_in_uop_bits_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p2_bypass_hint_0 = io_in_uop_bits_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_p3_bypass_hint_0 = io_in_uop_bits_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dis_col_sel_0 = io_in_uop_bits_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_br_type_0 = io_in_uop_bits_br_type; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sfence_0 = io_in_uop_bits_is_sfence; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_eret_0 = io_in_uop_bits_is_eret; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_rocc_0 = io_in_uop_bits_is_rocc; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_mov_0 = io_in_uop_bits_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_imm_rename_0 = io_in_uop_bits_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_imm_sel_0 = io_in_uop_bits_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_pimm_0 = io_in_uop_bits_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_op1_sel_0 = io_in_uop_bits_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_op2_sel_0 = io_in_uop_bits_op2_sel; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ldst_0 = io_in_uop_bits_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wen_0 = io_in_uop_bits_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren1_0 = io_in_uop_bits_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren2_0 = io_in_uop_bits_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_ren3_0 = io_in_uop_bits_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap12_0 = io_in_uop_bits_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_swap23_0 = io_in_uop_bits_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagIn_0 = io_in_uop_bits_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_ctrl_typeTagOut_0 = io_in_uop_bits_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fromint_0 = io_in_uop_bits_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_toint_0 = io_in_uop_bits_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fastpipe_0 = io_in_uop_bits_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_fma_0 = io_in_uop_bits_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_div_0 = io_in_uop_bits_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_sqrt_0 = io_in_uop_bits_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_wflags_0 = io_in_uop_bits_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_ctrl_vec_0 = io_in_uop_bits_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_csr_cmd_0 = io_in_uop_bits_csr_cmd; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fcn_dw_0 = io_in_uop_bits_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_in_uop_bits_fcn_op_0 = io_in_uop_bits_fcn_op; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_fp_rm_0 = io_in_uop_bits_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_in_uop_bits_fp_typ_0 = io_in_uop_bits_fp_typ; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:49:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:49:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:49:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:49:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:49:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:49:7]
wire io_kill_0 = io_kill; // @[issue-slot.scala:49:7]
wire io_clear_0 = io_clear; // @[issue-slot.scala:49:7]
wire io_squash_grant_0 = io_squash_grant; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_inst_0 = io_wakeup_ports_0_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_0_bits_uop_debug_inst_0 = io_wakeup_ports_0_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rvc_0 = io_wakeup_ports_0_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_0_bits_uop_debug_pc_0 = io_wakeup_ports_0_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_0_0 = io_wakeup_ports_0_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_1_0 = io_wakeup_ports_0_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_2_0 = io_wakeup_ports_0_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iq_type_3_0 = io_wakeup_ports_0_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_0_0 = io_wakeup_ports_0_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_1_0 = io_wakeup_ports_0_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_2_0 = io_wakeup_ports_0_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_3_0 = io_wakeup_ports_0_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_4_0 = io_wakeup_ports_0_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_5_0 = io_wakeup_ports_0_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_6_0 = io_wakeup_ports_0_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_7_0 = io_wakeup_ports_0_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_8_0 = io_wakeup_ports_0_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fu_code_9_0 = io_wakeup_ports_0_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_0 = io_wakeup_ports_0_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_0_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_0_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_0_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dis_col_sel_0 = io_wakeup_ports_0_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_0_bits_uop_br_mask_0 = io_wakeup_ports_0_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_tag_0 = io_wakeup_ports_0_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_br_type_0 = io_wakeup_ports_0_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfb_0 = io_wakeup_ports_0_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fence_0 = io_wakeup_ports_0_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_fencei_0 = io_wakeup_ports_0_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sfence_0 = io_wakeup_ports_0_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_amo_0 = io_wakeup_ports_0_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_eret_0 = io_wakeup_ports_0_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_0_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_rocc_0 = io_wakeup_ports_0_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_mov_0 = io_wakeup_ports_0_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ftq_idx_0 = io_wakeup_ports_0_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_edge_inst_0 = io_wakeup_ports_0_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_pc_lob_0 = io_wakeup_ports_0_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_taken_0 = io_wakeup_ports_0_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_imm_rename_0 = io_wakeup_ports_0_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_imm_sel_0 = io_wakeup_ports_0_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_pimm_0 = io_wakeup_ports_0_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_0_bits_uop_imm_packed_0 = io_wakeup_ports_0_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_op1_sel_0 = io_wakeup_ports_0_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_op2_sel_0 = io_wakeup_ports_0_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_0_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_rob_idx_0 = io_wakeup_ports_0_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_ldq_idx_0 = io_wakeup_ports_0_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_0_bits_uop_stq_idx_0 = io_wakeup_ports_0_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_rxq_idx_0 = io_wakeup_ports_0_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_pdst_0 = io_wakeup_ports_0_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs1_0 = io_wakeup_ports_0_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs2_0 = io_wakeup_ports_0_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_prs3_0 = io_wakeup_ports_0_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_ppred_0 = io_wakeup_ports_0_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs1_busy_0 = io_wakeup_ports_0_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs2_busy_0 = io_wakeup_ports_0_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_prs3_busy_0 = io_wakeup_ports_0_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ppred_busy_0 = io_wakeup_ports_0_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_0_bits_uop_stale_pdst_0 = io_wakeup_ports_0_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_exception_0 = io_wakeup_ports_0_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_0_bits_uop_exc_cause_0 = io_wakeup_ports_0_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_mem_cmd_0 = io_wakeup_ports_0_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_mem_size_0 = io_wakeup_ports_0_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_mem_signed_0 = io_wakeup_ports_0_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_ldq_0 = io_wakeup_ports_0_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_uses_stq_0 = io_wakeup_ports_0_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_is_unique_0 = io_wakeup_ports_0_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_flush_on_commit_0 = io_wakeup_ports_0_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_csr_cmd_0 = io_wakeup_ports_0_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_0_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_ldst_0 = io_wakeup_ports_0_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs1_0 = io_wakeup_ports_0_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs2_0 = io_wakeup_ports_0_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_0_bits_uop_lrs3_0 = io_wakeup_ports_0_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_dst_rtype_0 = io_wakeup_ports_0_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs1_rtype_0 = io_wakeup_ports_0_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_lrs2_rtype_0 = io_wakeup_ports_0_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_frs3_en_0 = io_wakeup_ports_0_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fcn_dw_0 = io_wakeup_ports_0_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_0_bits_uop_fcn_op_0 = io_wakeup_ports_0_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_fp_val_0 = io_wakeup_ports_0_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_fp_rm_0 = io_wakeup_ports_0_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_uop_fp_typ_0 = io_wakeup_ports_0_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_0_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_0_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_debug_if_0 = io_wakeup_ports_0_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_0_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_fsrc_0 = io_wakeup_ports_0_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_0_bits_uop_debug_tsrc_0 = io_wakeup_ports_0_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_inst_0 = io_wakeup_ports_1_bits_uop_inst; // @[issue-slot.scala:49:7]
wire [31:0] io_wakeup_ports_1_bits_uop_debug_inst_0 = io_wakeup_ports_1_bits_uop_debug_inst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rvc_0 = io_wakeup_ports_1_bits_uop_is_rvc; // @[issue-slot.scala:49:7]
wire [39:0] io_wakeup_ports_1_bits_uop_debug_pc_0 = io_wakeup_ports_1_bits_uop_debug_pc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_0_0 = io_wakeup_ports_1_bits_uop_iq_type_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_1_0 = io_wakeup_ports_1_bits_uop_iq_type_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_2_0 = io_wakeup_ports_1_bits_uop_iq_type_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iq_type_3_0 = io_wakeup_ports_1_bits_uop_iq_type_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_0_0 = io_wakeup_ports_1_bits_uop_fu_code_0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_1_0 = io_wakeup_ports_1_bits_uop_fu_code_1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_2_0 = io_wakeup_ports_1_bits_uop_fu_code_2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_3_0 = io_wakeup_ports_1_bits_uop_fu_code_3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_4_0 = io_wakeup_ports_1_bits_uop_fu_code_4; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_5_0 = io_wakeup_ports_1_bits_uop_fu_code_5; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_6_0 = io_wakeup_ports_1_bits_uop_fu_code_6; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_7_0 = io_wakeup_ports_1_bits_uop_fu_code_7; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_8_0 = io_wakeup_ports_1_bits_uop_fu_code_8; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fu_code_9_0 = io_wakeup_ports_1_bits_uop_fu_code_9; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_0 = io_wakeup_ports_1_bits_uop_iw_issued; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_agen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_agen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen_0 = io_wakeup_ports_1_bits_uop_iw_issued_partial_dgen; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_iw_p1_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_iw_p2_speculative_child_0 = io_wakeup_ports_1_bits_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint_0 = io_wakeup_ports_1_bits_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dis_col_sel_0 = io_wakeup_ports_1_bits_uop_dis_col_sel; // @[issue-slot.scala:49:7]
wire [11:0] io_wakeup_ports_1_bits_uop_br_mask_0 = io_wakeup_ports_1_bits_uop_br_mask; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_tag_0 = io_wakeup_ports_1_bits_uop_br_tag; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_br_type_0 = io_wakeup_ports_1_bits_uop_br_type; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfb_0 = io_wakeup_ports_1_bits_uop_is_sfb; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fence_0 = io_wakeup_ports_1_bits_uop_is_fence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_fencei_0 = io_wakeup_ports_1_bits_uop_is_fencei; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sfence_0 = io_wakeup_ports_1_bits_uop_is_sfence; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_amo_0 = io_wakeup_ports_1_bits_uop_is_amo; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_eret_0 = io_wakeup_ports_1_bits_uop_is_eret; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_sys_pc2epc_0 = io_wakeup_ports_1_bits_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_rocc_0 = io_wakeup_ports_1_bits_uop_is_rocc; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_mov_0 = io_wakeup_ports_1_bits_uop_is_mov; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ftq_idx_0 = io_wakeup_ports_1_bits_uop_ftq_idx; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_edge_inst_0 = io_wakeup_ports_1_bits_uop_edge_inst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_pc_lob_0 = io_wakeup_ports_1_bits_uop_pc_lob; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_taken_0 = io_wakeup_ports_1_bits_uop_taken; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_imm_rename_0 = io_wakeup_ports_1_bits_uop_imm_rename; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_imm_sel_0 = io_wakeup_ports_1_bits_uop_imm_sel; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_pimm_0 = io_wakeup_ports_1_bits_uop_pimm; // @[issue-slot.scala:49:7]
wire [19:0] io_wakeup_ports_1_bits_uop_imm_packed_0 = io_wakeup_ports_1_bits_uop_imm_packed; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_op1_sel_0 = io_wakeup_ports_1_bits_uop_op1_sel; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_op2_sel_0 = io_wakeup_ports_1_bits_uop_op2_sel; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ldst_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wen_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren1_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren2_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_ren3_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap12_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_swap23_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fromint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_toint_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_fma_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_div_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_div; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_wflags_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_ctrl_vec_0 = io_wakeup_ports_1_bits_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_rob_idx_0 = io_wakeup_ports_1_bits_uop_rob_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_ldq_idx_0 = io_wakeup_ports_1_bits_uop_ldq_idx; // @[issue-slot.scala:49:7]
wire [3:0] io_wakeup_ports_1_bits_uop_stq_idx_0 = io_wakeup_ports_1_bits_uop_stq_idx; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_rxq_idx_0 = io_wakeup_ports_1_bits_uop_rxq_idx; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_pdst_0 = io_wakeup_ports_1_bits_uop_pdst; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs1_0 = io_wakeup_ports_1_bits_uop_prs1; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs2_0 = io_wakeup_ports_1_bits_uop_prs2; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_prs3_0 = io_wakeup_ports_1_bits_uop_prs3; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_ppred_0 = io_wakeup_ports_1_bits_uop_ppred; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs1_busy_0 = io_wakeup_ports_1_bits_uop_prs1_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs2_busy_0 = io_wakeup_ports_1_bits_uop_prs2_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_prs3_busy_0 = io_wakeup_ports_1_bits_uop_prs3_busy; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ppred_busy_0 = io_wakeup_ports_1_bits_uop_ppred_busy; // @[issue-slot.scala:49:7]
wire [6:0] io_wakeup_ports_1_bits_uop_stale_pdst_0 = io_wakeup_ports_1_bits_uop_stale_pdst; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_exception_0 = io_wakeup_ports_1_bits_uop_exception; // @[issue-slot.scala:49:7]
wire [63:0] io_wakeup_ports_1_bits_uop_exc_cause_0 = io_wakeup_ports_1_bits_uop_exc_cause; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_mem_cmd_0 = io_wakeup_ports_1_bits_uop_mem_cmd; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_mem_size_0 = io_wakeup_ports_1_bits_uop_mem_size; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_mem_signed_0 = io_wakeup_ports_1_bits_uop_mem_signed; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_ldq_0 = io_wakeup_ports_1_bits_uop_uses_ldq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_uses_stq_0 = io_wakeup_ports_1_bits_uop_uses_stq; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_is_unique_0 = io_wakeup_ports_1_bits_uop_is_unique; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_flush_on_commit_0 = io_wakeup_ports_1_bits_uop_flush_on_commit; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_csr_cmd_0 = io_wakeup_ports_1_bits_uop_csr_cmd; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_ldst_is_rs1_0 = io_wakeup_ports_1_bits_uop_ldst_is_rs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_ldst_0 = io_wakeup_ports_1_bits_uop_ldst; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs1_0 = io_wakeup_ports_1_bits_uop_lrs1; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs2_0 = io_wakeup_ports_1_bits_uop_lrs2; // @[issue-slot.scala:49:7]
wire [5:0] io_wakeup_ports_1_bits_uop_lrs3_0 = io_wakeup_ports_1_bits_uop_lrs3; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_dst_rtype_0 = io_wakeup_ports_1_bits_uop_dst_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs1_rtype_0 = io_wakeup_ports_1_bits_uop_lrs1_rtype; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_lrs2_rtype_0 = io_wakeup_ports_1_bits_uop_lrs2_rtype; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_frs3_en_0 = io_wakeup_ports_1_bits_uop_frs3_en; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fcn_dw_0 = io_wakeup_ports_1_bits_uop_fcn_dw; // @[issue-slot.scala:49:7]
wire [4:0] io_wakeup_ports_1_bits_uop_fcn_op_0 = io_wakeup_ports_1_bits_uop_fcn_op; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_fp_val_0 = io_wakeup_ports_1_bits_uop_fp_val; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_fp_rm_0 = io_wakeup_ports_1_bits_uop_fp_rm; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_uop_fp_typ_0 = io_wakeup_ports_1_bits_uop_fp_typ; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_pf_if_0 = io_wakeup_ports_1_bits_uop_xcpt_pf_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ae_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ae_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_xcpt_ma_if_0 = io_wakeup_ports_1_bits_uop_xcpt_ma_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_debug_if_0 = io_wakeup_ports_1_bits_uop_bp_debug_if; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_uop_bp_xcpt_if_0 = io_wakeup_ports_1_bits_uop_bp_xcpt_if; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_fsrc_0 = io_wakeup_ports_1_bits_uop_debug_fsrc; // @[issue-slot.scala:49:7]
wire [2:0] io_wakeup_ports_1_bits_uop_debug_tsrc_0 = io_wakeup_ports_1_bits_uop_debug_tsrc; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_in_uop_bits_ppred_busy = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_0_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_bypassable = 1'h0; // @[issue-slot.scala:49:7]
wire io_wakeup_ports_1_bits_rebusy = 1'h0; // @[issue-slot.scala:49:7]
wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:49:7]
wire next_uop_out_iw_issued_partial_agen = 1'h0; // @[util.scala:104:23]
wire next_uop_out_iw_issued_partial_dgen = 1'h0; // @[util.scala:104:23]
wire next_uop_iw_issued_partial_agen = 1'h0; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued_partial_dgen = 1'h0; // @[issue-slot.scala:59:28]
wire rebusied_prs1 = 1'h0; // @[issue-slot.scala:92:31]
wire rebusied_prs2 = 1'h0; // @[issue-slot.scala:93:31]
wire rebusied = 1'h0; // @[issue-slot.scala:94:32]
wire prs1_rebusys_0 = 1'h0; // @[issue-slot.scala:102:91]
wire prs1_rebusys_1 = 1'h0; // @[issue-slot.scala:102:91]
wire prs2_rebusys_0 = 1'h0; // @[issue-slot.scala:103:91]
wire prs2_rebusys_1 = 1'h0; // @[issue-slot.scala:103:91]
wire _next_uop_iw_p1_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p2_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _next_uop_iw_p3_bypass_hint_T_1 = 1'h0; // @[Mux.scala:30:73]
wire agen_ready = 1'h0; // @[issue-slot.scala:137:114]
wire dgen_ready = 1'h0; // @[issue-slot.scala:138:114]
wire [1:0] io_out_uop_iw_p1_speculative_child = 2'h0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_iw_p2_speculative_child = 2'h0; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_0_bits_speculative_mask = 2'h0; // @[issue-slot.scala:49:7]
wire [1:0] io_wakeup_ports_1_bits_speculative_mask = 2'h0; // @[issue-slot.scala:49:7]
wire [1:0] io_child_rebusys = 2'h0; // @[issue-slot.scala:49:7]
wire [1:0] next_uop_iw_p1_speculative_child = 2'h0; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_iw_p2_speculative_child = 2'h0; // @[issue-slot.scala:59:28]
wire [1:0] _next_uop_iw_p1_speculative_child_T = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _next_uop_iw_p1_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _next_uop_iw_p1_speculative_child_T_2 = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _next_uop_iw_p1_speculative_child_WIRE = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _next_uop_iw_p2_speculative_child_T = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _next_uop_iw_p2_speculative_child_T_1 = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _next_uop_iw_p2_speculative_child_T_2 = 2'h0; // @[Mux.scala:30:73]
wire [1:0] _next_uop_iw_p2_speculative_child_WIRE = 2'h0; // @[Mux.scala:30:73]
wire io_wakeup_ports_0_bits_bypassable = 1'h1; // @[issue-slot.scala:49:7]
wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:49:7]
wire _io_will_be_valid_T_1; // @[issue-slot.scala:65:34]
wire _io_request_T_4; // @[issue-slot.scala:140:51]
wire [31:0] next_uop_inst; // @[issue-slot.scala:59:28]
wire [31:0] next_uop_debug_inst; // @[issue-slot.scala:59:28]
wire next_uop_is_rvc; // @[issue-slot.scala:59:28]
wire [39:0] next_uop_debug_pc; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_0; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_1; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_2; // @[issue-slot.scala:59:28]
wire next_uop_iq_type_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_0; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_1; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_2; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_3; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_4; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_5; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_6; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_7; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_8; // @[issue-slot.scala:59:28]
wire next_uop_fu_code_9; // @[issue-slot.scala:59:28]
wire next_uop_iw_issued; // @[issue-slot.scala:59:28]
wire next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:59:28]
wire next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dis_col_sel; // @[issue-slot.scala:59:28]
wire [11:0] next_uop_br_mask; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_tag; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_br_type; // @[issue-slot.scala:59:28]
wire next_uop_is_sfb; // @[issue-slot.scala:59:28]
wire next_uop_is_fence; // @[issue-slot.scala:59:28]
wire next_uop_is_fencei; // @[issue-slot.scala:59:28]
wire next_uop_is_sfence; // @[issue-slot.scala:59:28]
wire next_uop_is_amo; // @[issue-slot.scala:59:28]
wire next_uop_is_eret; // @[issue-slot.scala:59:28]
wire next_uop_is_sys_pc2epc; // @[issue-slot.scala:59:28]
wire next_uop_is_rocc; // @[issue-slot.scala:59:28]
wire next_uop_is_mov; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ftq_idx; // @[issue-slot.scala:59:28]
wire next_uop_edge_inst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_pc_lob; // @[issue-slot.scala:59:28]
wire next_uop_taken; // @[issue-slot.scala:59:28]
wire next_uop_imm_rename; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_imm_sel; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_pimm; // @[issue-slot.scala:59:28]
wire [19:0] next_uop_imm_packed; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_op1_sel; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_op2_sel; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ldst; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wen; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren1; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren2; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_ren3; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap12; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_swap23; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fromint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_toint; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_fma; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_div; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_wflags; // @[issue-slot.scala:59:28]
wire next_uop_fp_ctrl_vec; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_rob_idx; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_ldq_idx; // @[issue-slot.scala:59:28]
wire [3:0] next_uop_stq_idx; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_rxq_idx; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_pdst; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs1; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs2; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_prs3; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_ppred; // @[issue-slot.scala:59:28]
wire next_uop_prs1_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs2_busy; // @[issue-slot.scala:59:28]
wire next_uop_prs3_busy; // @[issue-slot.scala:59:28]
wire next_uop_ppred_busy; // @[issue-slot.scala:59:28]
wire [6:0] next_uop_stale_pdst; // @[issue-slot.scala:59:28]
wire next_uop_exception; // @[issue-slot.scala:59:28]
wire [63:0] next_uop_exc_cause; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_mem_cmd; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_mem_size; // @[issue-slot.scala:59:28]
wire next_uop_mem_signed; // @[issue-slot.scala:59:28]
wire next_uop_uses_ldq; // @[issue-slot.scala:59:28]
wire next_uop_uses_stq; // @[issue-slot.scala:59:28]
wire next_uop_is_unique; // @[issue-slot.scala:59:28]
wire next_uop_flush_on_commit; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_csr_cmd; // @[issue-slot.scala:59:28]
wire next_uop_ldst_is_rs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_ldst; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs1; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs2; // @[issue-slot.scala:59:28]
wire [5:0] next_uop_lrs3; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_dst_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs1_rtype; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_lrs2_rtype; // @[issue-slot.scala:59:28]
wire next_uop_frs3_en; // @[issue-slot.scala:59:28]
wire next_uop_fcn_dw; // @[issue-slot.scala:59:28]
wire [4:0] next_uop_fcn_op; // @[issue-slot.scala:59:28]
wire next_uop_fp_val; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_fp_rm; // @[issue-slot.scala:59:28]
wire [1:0] next_uop_fp_typ; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_pf_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ae_if; // @[issue-slot.scala:59:28]
wire next_uop_xcpt_ma_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_debug_if; // @[issue-slot.scala:59:28]
wire next_uop_bp_xcpt_if; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_fsrc; // @[issue-slot.scala:59:28]
wire [2:0] next_uop_debug_tsrc; // @[issue-slot.scala:59:28]
wire io_iss_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_iss_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_iss_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_iw_p1_speculative_child_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_iw_p2_speculative_child_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [11:0] io_iss_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_iss_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_iss_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_iss_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_iss_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_iss_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_iss_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_iss_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_iss_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_iss_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iq_type_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_0_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_4_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_5_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_6_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_7_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_8_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fu_code_9_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ldst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wen_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren1_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren2_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_ren3_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap12_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_swap23_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagIn_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_ctrl_typeTagOut_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fromint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_toint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fastpipe_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_fma_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_div_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_sqrt_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_wflags_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_ctrl_vec_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:49:7]
wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rvc_0; // @[issue-slot.scala:49:7]
wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_issued_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p1_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p2_bypass_hint_0; // @[issue-slot.scala:49:7]
wire io_out_uop_iw_p3_bypass_hint_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dis_col_sel_0; // @[issue-slot.scala:49:7]
wire [11:0] io_out_uop_br_mask_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_br_type_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfb_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_fencei_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sfence_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_amo_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_eret_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_rocc_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_mov_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:49:7]
wire io_out_uop_edge_inst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:49:7]
wire io_out_uop_taken_0; // @[issue-slot.scala:49:7]
wire io_out_uop_imm_rename_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_imm_sel_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_pimm_0; // @[issue-slot.scala:49:7]
wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_op1_sel_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_op2_sel_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:49:7]
wire [3:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:49:7]
wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:49:7]
wire io_out_uop_exception_0; // @[issue-slot.scala:49:7]
wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:49:7]
wire io_out_uop_mem_signed_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_uses_stq_0; // @[issue-slot.scala:49:7]
wire io_out_uop_is_unique_0; // @[issue-slot.scala:49:7]
wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_csr_cmd_0; // @[issue-slot.scala:49:7]
wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:49:7]
wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:49:7]
wire io_out_uop_frs3_en_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fcn_dw_0; // @[issue-slot.scala:49:7]
wire [4:0] io_out_uop_fcn_op_0; // @[issue-slot.scala:49:7]
wire io_out_uop_fp_val_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_fp_rm_0; // @[issue-slot.scala:49:7]
wire [1:0] io_out_uop_fp_typ_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:49:7]
wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:49:7]
wire [2:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:49:7]
wire io_valid_0; // @[issue-slot.scala:49:7]
wire io_will_be_valid_0; // @[issue-slot.scala:49:7]
wire io_request_0; // @[issue-slot.scala:49:7]
reg slot_valid; // @[issue-slot.scala:55:27]
assign io_valid_0 = slot_valid; // @[issue-slot.scala:49:7, :55:27]
reg [31:0] slot_uop_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_inst = slot_uop_inst; // @[util.scala:104:23]
reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:49:7, :56:21]
wire [31:0] next_uop_out_debug_inst = slot_uop_debug_inst; // @[util.scala:104:23]
reg slot_uop_is_rvc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rvc = slot_uop_is_rvc; // @[util.scala:104:23]
reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:49:7, :56:21]
wire [39:0] next_uop_out_debug_pc = slot_uop_debug_pc; // @[util.scala:104:23]
reg slot_uop_iq_type_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_0_0 = slot_uop_iq_type_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_0 = slot_uop_iq_type_0; // @[util.scala:104:23]
reg slot_uop_iq_type_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_1_0 = slot_uop_iq_type_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_1 = slot_uop_iq_type_1; // @[util.scala:104:23]
reg slot_uop_iq_type_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_2_0 = slot_uop_iq_type_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_2 = slot_uop_iq_type_2; // @[util.scala:104:23]
reg slot_uop_iq_type_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_iq_type_3_0 = slot_uop_iq_type_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iq_type_3 = slot_uop_iq_type_3; // @[util.scala:104:23]
reg slot_uop_fu_code_0; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_0_0 = slot_uop_fu_code_0; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_0 = slot_uop_fu_code_0; // @[util.scala:104:23]
reg slot_uop_fu_code_1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_1_0 = slot_uop_fu_code_1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_1 = slot_uop_fu_code_1; // @[util.scala:104:23]
reg slot_uop_fu_code_2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_2_0 = slot_uop_fu_code_2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_2 = slot_uop_fu_code_2; // @[util.scala:104:23]
reg slot_uop_fu_code_3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_3_0 = slot_uop_fu_code_3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_3 = slot_uop_fu_code_3; // @[util.scala:104:23]
reg slot_uop_fu_code_4; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_4_0 = slot_uop_fu_code_4; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_4 = slot_uop_fu_code_4; // @[util.scala:104:23]
reg slot_uop_fu_code_5; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_5_0 = slot_uop_fu_code_5; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_5 = slot_uop_fu_code_5; // @[util.scala:104:23]
reg slot_uop_fu_code_6; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_6_0 = slot_uop_fu_code_6; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_6 = slot_uop_fu_code_6; // @[util.scala:104:23]
reg slot_uop_fu_code_7; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_7_0 = slot_uop_fu_code_7; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_7 = slot_uop_fu_code_7; // @[util.scala:104:23]
reg slot_uop_fu_code_8; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_8_0 = slot_uop_fu_code_8; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_8 = slot_uop_fu_code_8; // @[util.scala:104:23]
reg slot_uop_fu_code_9; // @[issue-slot.scala:56:21]
assign io_iss_uop_fu_code_9_0 = slot_uop_fu_code_9; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fu_code_9 = slot_uop_fu_code_9; // @[util.scala:104:23]
reg slot_uop_iw_issued; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_issued_0 = slot_uop_iw_issued; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_issued = slot_uop_iw_issued; // @[util.scala:104:23]
reg [1:0] slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_speculative_child_0 = slot_uop_iw_p1_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_iw_p1_speculative_child = slot_uop_iw_p1_speculative_child; // @[util.scala:104:23]
reg [1:0] slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_speculative_child_0 = slot_uop_iw_p2_speculative_child; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_iw_p2_speculative_child = slot_uop_iw_p2_speculative_child; // @[util.scala:104:23]
reg slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p1_bypass_hint_0 = slot_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p1_bypass_hint = slot_uop_iw_p1_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p2_bypass_hint_0 = slot_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p2_bypass_hint = slot_uop_iw_p2_bypass_hint; // @[util.scala:104:23]
reg slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:56:21]
assign io_iss_uop_iw_p3_bypass_hint_0 = slot_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_iw_p3_bypass_hint = slot_uop_iw_p3_bypass_hint; // @[util.scala:104:23]
reg [1:0] slot_uop_dis_col_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_dis_col_sel_0 = slot_uop_dis_col_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dis_col_sel = slot_uop_dis_col_sel; // @[util.scala:104:23]
reg [11:0] slot_uop_br_mask; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:49:7, :56:21]
reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_tag = slot_uop_br_tag; // @[util.scala:104:23]
reg [3:0] slot_uop_br_type; // @[issue-slot.scala:56:21]
assign io_iss_uop_br_type_0 = slot_uop_br_type; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_br_type = slot_uop_br_type; // @[util.scala:104:23]
reg slot_uop_is_sfb; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfb = slot_uop_is_sfb; // @[util.scala:104:23]
reg slot_uop_is_fence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fence = slot_uop_is_fence; // @[util.scala:104:23]
reg slot_uop_is_fencei; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_fencei = slot_uop_is_fencei; // @[util.scala:104:23]
reg slot_uop_is_sfence; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sfence_0 = slot_uop_is_sfence; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sfence = slot_uop_is_sfence; // @[util.scala:104:23]
reg slot_uop_is_amo; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_amo = slot_uop_is_amo; // @[util.scala:104:23]
reg slot_uop_is_eret; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_eret_0 = slot_uop_is_eret; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_eret = slot_uop_is_eret; // @[util.scala:104:23]
reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_sys_pc2epc = slot_uop_is_sys_pc2epc; // @[util.scala:104:23]
reg slot_uop_is_rocc; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_rocc_0 = slot_uop_is_rocc; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_rocc = slot_uop_is_rocc; // @[util.scala:104:23]
reg slot_uop_is_mov; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_mov_0 = slot_uop_is_mov; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_mov = slot_uop_is_mov; // @[util.scala:104:23]
reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ftq_idx = slot_uop_ftq_idx; // @[util.scala:104:23]
reg slot_uop_edge_inst; // @[issue-slot.scala:56:21]
assign io_iss_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_edge_inst = slot_uop_edge_inst; // @[util.scala:104:23]
reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:56:21]
assign io_iss_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_pc_lob = slot_uop_pc_lob; // @[util.scala:104:23]
reg slot_uop_taken; // @[issue-slot.scala:56:21]
assign io_iss_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_taken = slot_uop_taken; // @[util.scala:104:23]
reg slot_uop_imm_rename; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_rename_0 = slot_uop_imm_rename; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_imm_rename = slot_uop_imm_rename; // @[util.scala:104:23]
reg [2:0] slot_uop_imm_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_sel_0 = slot_uop_imm_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_imm_sel = slot_uop_imm_sel; // @[util.scala:104:23]
reg [4:0] slot_uop_pimm; // @[issue-slot.scala:56:21]
assign io_iss_uop_pimm_0 = slot_uop_pimm; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_pimm = slot_uop_pimm; // @[util.scala:104:23]
reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:56:21]
assign io_iss_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:49:7, :56:21]
wire [19:0] next_uop_out_imm_packed = slot_uop_imm_packed; // @[util.scala:104:23]
reg [1:0] slot_uop_op1_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op1_sel_0 = slot_uop_op1_sel; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_op1_sel = slot_uop_op1_sel; // @[util.scala:104:23]
reg [2:0] slot_uop_op2_sel; // @[issue-slot.scala:56:21]
assign io_iss_uop_op2_sel_0 = slot_uop_op2_sel; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_op2_sel = slot_uop_op2_sel; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ldst_0 = slot_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ldst = slot_uop_fp_ctrl_ldst; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wen; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wen_0 = slot_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wen = slot_uop_fp_ctrl_wen; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren1_0 = slot_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren1 = slot_uop_fp_ctrl_ren1; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren2_0 = slot_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren2 = slot_uop_fp_ctrl_ren2; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_ren3_0 = slot_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_ren3 = slot_uop_fp_ctrl_ren3; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap12_0 = slot_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap12 = slot_uop_fp_ctrl_swap12; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_swap23_0 = slot_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_swap23 = slot_uop_fp_ctrl_swap23; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagIn_0 = slot_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagIn = slot_uop_fp_ctrl_typeTagIn; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_typeTagOut_0 = slot_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_ctrl_typeTagOut = slot_uop_fp_ctrl_typeTagOut; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fromint_0 = slot_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fromint = slot_uop_fp_ctrl_fromint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_toint; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_toint_0 = slot_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_toint = slot_uop_fp_ctrl_toint; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fastpipe_0 = slot_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fastpipe = slot_uop_fp_ctrl_fastpipe; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_fma; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_fma_0 = slot_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_fma = slot_uop_fp_ctrl_fma; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_div; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_div_0 = slot_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_div = slot_uop_fp_ctrl_div; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_sqrt_0 = slot_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_sqrt = slot_uop_fp_ctrl_sqrt; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_wflags_0 = slot_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_wflags = slot_uop_fp_ctrl_wflags; // @[util.scala:104:23]
reg slot_uop_fp_ctrl_vec; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_ctrl_vec_0 = slot_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_ctrl_vec = slot_uop_fp_ctrl_vec; // @[util.scala:104:23]
reg [5:0] slot_uop_rob_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_rob_idx = slot_uop_rob_idx; // @[util.scala:104:23]
reg [3:0] slot_uop_ldq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_ldq_idx = slot_uop_ldq_idx; // @[util.scala:104:23]
reg [3:0] slot_uop_stq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [3:0] next_uop_out_stq_idx = slot_uop_stq_idx; // @[util.scala:104:23]
reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:56:21]
assign io_iss_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_rxq_idx = slot_uop_rxq_idx; // @[util.scala:104:23]
reg [6:0] slot_uop_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_pdst = slot_uop_pdst; // @[util.scala:104:23]
reg [6:0] slot_uop_prs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs1 = slot_uop_prs1; // @[util.scala:104:23]
reg [6:0] slot_uop_prs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs2 = slot_uop_prs2; // @[util.scala:104:23]
reg [6:0] slot_uop_prs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_prs3 = slot_uop_prs3; // @[util.scala:104:23]
reg [4:0] slot_uop_ppred; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_ppred = slot_uop_ppred; // @[util.scala:104:23]
reg slot_uop_prs1_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs1_busy = slot_uop_prs1_busy; // @[util.scala:104:23]
reg slot_uop_prs2_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs2_busy = slot_uop_prs2_busy; // @[util.scala:104:23]
reg slot_uop_prs3_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_prs3_busy = slot_uop_prs3_busy; // @[util.scala:104:23]
wire _iss_ready_T_6 = slot_uop_prs3_busy; // @[issue-slot.scala:56:21, :136:131]
reg slot_uop_ppred_busy; // @[issue-slot.scala:56:21]
assign io_iss_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ppred_busy = slot_uop_ppred_busy; // @[util.scala:104:23]
wire _iss_ready_T_3 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :136:88]
wire _agen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :137:95]
wire _dgen_ready_T_2 = slot_uop_ppred_busy; // @[issue-slot.scala:56:21, :138:95]
reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:56:21]
assign io_iss_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:49:7, :56:21]
wire [6:0] next_uop_out_stale_pdst = slot_uop_stale_pdst; // @[util.scala:104:23]
reg slot_uop_exception; // @[issue-slot.scala:56:21]
assign io_iss_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_exception = slot_uop_exception; // @[util.scala:104:23]
reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:56:21]
assign io_iss_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:49:7, :56:21]
wire [63:0] next_uop_out_exc_cause = slot_uop_exc_cause; // @[util.scala:104:23]
reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_mem_cmd = slot_uop_mem_cmd; // @[util.scala:104:23]
reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_mem_size = slot_uop_mem_size; // @[util.scala:104:23]
reg slot_uop_mem_signed; // @[issue-slot.scala:56:21]
assign io_iss_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_mem_signed = slot_uop_mem_signed; // @[util.scala:104:23]
reg slot_uop_uses_ldq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_ldq = slot_uop_uses_ldq; // @[util.scala:104:23]
reg slot_uop_uses_stq; // @[issue-slot.scala:56:21]
assign io_iss_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_uses_stq = slot_uop_uses_stq; // @[util.scala:104:23]
reg slot_uop_is_unique; // @[issue-slot.scala:56:21]
assign io_iss_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_is_unique = slot_uop_is_unique; // @[util.scala:104:23]
reg slot_uop_flush_on_commit; // @[issue-slot.scala:56:21]
assign io_iss_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_flush_on_commit = slot_uop_flush_on_commit; // @[util.scala:104:23]
reg [2:0] slot_uop_csr_cmd; // @[issue-slot.scala:56:21]
assign io_iss_uop_csr_cmd_0 = slot_uop_csr_cmd; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_csr_cmd = slot_uop_csr_cmd; // @[util.scala:104:23]
reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_ldst_is_rs1 = slot_uop_ldst_is_rs1; // @[util.scala:104:23]
reg [5:0] slot_uop_ldst; // @[issue-slot.scala:56:21]
assign io_iss_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_ldst = slot_uop_ldst; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs1 = slot_uop_lrs1; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs2 = slot_uop_lrs2; // @[util.scala:104:23]
reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:49:7, :56:21]
wire [5:0] next_uop_out_lrs3 = slot_uop_lrs3; // @[util.scala:104:23]
reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_dst_rtype = slot_uop_dst_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs1_rtype_0 = slot_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs1_rtype = slot_uop_lrs1_rtype; // @[util.scala:104:23]
reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:56:21]
assign io_iss_uop_lrs2_rtype_0 = slot_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_lrs2_rtype = slot_uop_lrs2_rtype; // @[util.scala:104:23]
reg slot_uop_frs3_en; // @[issue-slot.scala:56:21]
assign io_iss_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_frs3_en = slot_uop_frs3_en; // @[util.scala:104:23]
reg slot_uop_fcn_dw; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_dw_0 = slot_uop_fcn_dw; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fcn_dw = slot_uop_fcn_dw; // @[util.scala:104:23]
reg [4:0] slot_uop_fcn_op; // @[issue-slot.scala:56:21]
assign io_iss_uop_fcn_op_0 = slot_uop_fcn_op; // @[issue-slot.scala:49:7, :56:21]
wire [4:0] next_uop_out_fcn_op = slot_uop_fcn_op; // @[util.scala:104:23]
reg slot_uop_fp_val; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_fp_val = slot_uop_fp_val; // @[util.scala:104:23]
reg [2:0] slot_uop_fp_rm; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_rm_0 = slot_uop_fp_rm; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_fp_rm = slot_uop_fp_rm; // @[util.scala:104:23]
reg [1:0] slot_uop_fp_typ; // @[issue-slot.scala:56:21]
assign io_iss_uop_fp_typ_0 = slot_uop_fp_typ; // @[issue-slot.scala:49:7, :56:21]
wire [1:0] next_uop_out_fp_typ = slot_uop_fp_typ; // @[util.scala:104:23]
reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_pf_if = slot_uop_xcpt_pf_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ae_if = slot_uop_xcpt_ae_if; // @[util.scala:104:23]
reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_xcpt_ma_if = slot_uop_xcpt_ma_if; // @[util.scala:104:23]
reg slot_uop_bp_debug_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_debug_if = slot_uop_bp_debug_if; // @[util.scala:104:23]
reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:56:21]
assign io_iss_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :56:21]
wire next_uop_out_bp_xcpt_if = slot_uop_bp_xcpt_if; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_fsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_fsrc = slot_uop_debug_fsrc; // @[util.scala:104:23]
reg [2:0] slot_uop_debug_tsrc; // @[issue-slot.scala:56:21]
assign io_iss_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:49:7, :56:21]
wire [2:0] next_uop_out_debug_tsrc = slot_uop_debug_tsrc; // @[util.scala:104:23]
wire next_valid; // @[issue-slot.scala:58:28]
assign next_uop_inst = next_uop_out_inst; // @[util.scala:104:23]
assign next_uop_debug_inst = next_uop_out_debug_inst; // @[util.scala:104:23]
assign next_uop_is_rvc = next_uop_out_is_rvc; // @[util.scala:104:23]
assign next_uop_debug_pc = next_uop_out_debug_pc; // @[util.scala:104:23]
assign next_uop_iq_type_0 = next_uop_out_iq_type_0; // @[util.scala:104:23]
assign next_uop_iq_type_1 = next_uop_out_iq_type_1; // @[util.scala:104:23]
assign next_uop_iq_type_2 = next_uop_out_iq_type_2; // @[util.scala:104:23]
assign next_uop_iq_type_3 = next_uop_out_iq_type_3; // @[util.scala:104:23]
assign next_uop_fu_code_0 = next_uop_out_fu_code_0; // @[util.scala:104:23]
assign next_uop_fu_code_1 = next_uop_out_fu_code_1; // @[util.scala:104:23]
assign next_uop_fu_code_2 = next_uop_out_fu_code_2; // @[util.scala:104:23]
assign next_uop_fu_code_3 = next_uop_out_fu_code_3; // @[util.scala:104:23]
assign next_uop_fu_code_4 = next_uop_out_fu_code_4; // @[util.scala:104:23]
assign next_uop_fu_code_5 = next_uop_out_fu_code_5; // @[util.scala:104:23]
assign next_uop_fu_code_6 = next_uop_out_fu_code_6; // @[util.scala:104:23]
assign next_uop_fu_code_7 = next_uop_out_fu_code_7; // @[util.scala:104:23]
assign next_uop_fu_code_8 = next_uop_out_fu_code_8; // @[util.scala:104:23]
assign next_uop_fu_code_9 = next_uop_out_fu_code_9; // @[util.scala:104:23]
wire [11:0] _next_uop_out_br_mask_T_1; // @[util.scala:93:25]
assign next_uop_dis_col_sel = next_uop_out_dis_col_sel; // @[util.scala:104:23]
assign next_uop_br_mask = next_uop_out_br_mask; // @[util.scala:104:23]
assign next_uop_br_tag = next_uop_out_br_tag; // @[util.scala:104:23]
assign next_uop_br_type = next_uop_out_br_type; // @[util.scala:104:23]
assign next_uop_is_sfb = next_uop_out_is_sfb; // @[util.scala:104:23]
assign next_uop_is_fence = next_uop_out_is_fence; // @[util.scala:104:23]
assign next_uop_is_fencei = next_uop_out_is_fencei; // @[util.scala:104:23]
assign next_uop_is_sfence = next_uop_out_is_sfence; // @[util.scala:104:23]
assign next_uop_is_amo = next_uop_out_is_amo; // @[util.scala:104:23]
assign next_uop_is_eret = next_uop_out_is_eret; // @[util.scala:104:23]
assign next_uop_is_sys_pc2epc = next_uop_out_is_sys_pc2epc; // @[util.scala:104:23]
assign next_uop_is_rocc = next_uop_out_is_rocc; // @[util.scala:104:23]
assign next_uop_is_mov = next_uop_out_is_mov; // @[util.scala:104:23]
assign next_uop_ftq_idx = next_uop_out_ftq_idx; // @[util.scala:104:23]
assign next_uop_edge_inst = next_uop_out_edge_inst; // @[util.scala:104:23]
assign next_uop_pc_lob = next_uop_out_pc_lob; // @[util.scala:104:23]
assign next_uop_taken = next_uop_out_taken; // @[util.scala:104:23]
assign next_uop_imm_rename = next_uop_out_imm_rename; // @[util.scala:104:23]
assign next_uop_imm_sel = next_uop_out_imm_sel; // @[util.scala:104:23]
assign next_uop_pimm = next_uop_out_pimm; // @[util.scala:104:23]
assign next_uop_imm_packed = next_uop_out_imm_packed; // @[util.scala:104:23]
assign next_uop_op1_sel = next_uop_out_op1_sel; // @[util.scala:104:23]
assign next_uop_op2_sel = next_uop_out_op2_sel; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ldst = next_uop_out_fp_ctrl_ldst; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wen = next_uop_out_fp_ctrl_wen; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren1 = next_uop_out_fp_ctrl_ren1; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren2 = next_uop_out_fp_ctrl_ren2; // @[util.scala:104:23]
assign next_uop_fp_ctrl_ren3 = next_uop_out_fp_ctrl_ren3; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap12 = next_uop_out_fp_ctrl_swap12; // @[util.scala:104:23]
assign next_uop_fp_ctrl_swap23 = next_uop_out_fp_ctrl_swap23; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagIn = next_uop_out_fp_ctrl_typeTagIn; // @[util.scala:104:23]
assign next_uop_fp_ctrl_typeTagOut = next_uop_out_fp_ctrl_typeTagOut; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fromint = next_uop_out_fp_ctrl_fromint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_toint = next_uop_out_fp_ctrl_toint; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fastpipe = next_uop_out_fp_ctrl_fastpipe; // @[util.scala:104:23]
assign next_uop_fp_ctrl_fma = next_uop_out_fp_ctrl_fma; // @[util.scala:104:23]
assign next_uop_fp_ctrl_div = next_uop_out_fp_ctrl_div; // @[util.scala:104:23]
assign next_uop_fp_ctrl_sqrt = next_uop_out_fp_ctrl_sqrt; // @[util.scala:104:23]
assign next_uop_fp_ctrl_wflags = next_uop_out_fp_ctrl_wflags; // @[util.scala:104:23]
assign next_uop_fp_ctrl_vec = next_uop_out_fp_ctrl_vec; // @[util.scala:104:23]
assign next_uop_rob_idx = next_uop_out_rob_idx; // @[util.scala:104:23]
assign next_uop_ldq_idx = next_uop_out_ldq_idx; // @[util.scala:104:23]
assign next_uop_stq_idx = next_uop_out_stq_idx; // @[util.scala:104:23]
assign next_uop_rxq_idx = next_uop_out_rxq_idx; // @[util.scala:104:23]
assign next_uop_pdst = next_uop_out_pdst; // @[util.scala:104:23]
assign next_uop_prs1 = next_uop_out_prs1; // @[util.scala:104:23]
assign next_uop_prs2 = next_uop_out_prs2; // @[util.scala:104:23]
assign next_uop_prs3 = next_uop_out_prs3; // @[util.scala:104:23]
assign next_uop_ppred = next_uop_out_ppred; // @[util.scala:104:23]
assign next_uop_ppred_busy = next_uop_out_ppred_busy; // @[util.scala:104:23]
assign next_uop_stale_pdst = next_uop_out_stale_pdst; // @[util.scala:104:23]
assign next_uop_exception = next_uop_out_exception; // @[util.scala:104:23]
assign next_uop_exc_cause = next_uop_out_exc_cause; // @[util.scala:104:23]
assign next_uop_mem_cmd = next_uop_out_mem_cmd; // @[util.scala:104:23]
assign next_uop_mem_size = next_uop_out_mem_size; // @[util.scala:104:23]
assign next_uop_mem_signed = next_uop_out_mem_signed; // @[util.scala:104:23]
assign next_uop_uses_ldq = next_uop_out_uses_ldq; // @[util.scala:104:23]
assign next_uop_uses_stq = next_uop_out_uses_stq; // @[util.scala:104:23]
assign next_uop_is_unique = next_uop_out_is_unique; // @[util.scala:104:23]
assign next_uop_flush_on_commit = next_uop_out_flush_on_commit; // @[util.scala:104:23]
assign next_uop_csr_cmd = next_uop_out_csr_cmd; // @[util.scala:104:23]
assign next_uop_ldst_is_rs1 = next_uop_out_ldst_is_rs1; // @[util.scala:104:23]
assign next_uop_ldst = next_uop_out_ldst; // @[util.scala:104:23]
assign next_uop_lrs1 = next_uop_out_lrs1; // @[util.scala:104:23]
assign next_uop_lrs2 = next_uop_out_lrs2; // @[util.scala:104:23]
assign next_uop_lrs3 = next_uop_out_lrs3; // @[util.scala:104:23]
assign next_uop_dst_rtype = next_uop_out_dst_rtype; // @[util.scala:104:23]
assign next_uop_lrs1_rtype = next_uop_out_lrs1_rtype; // @[util.scala:104:23]
assign next_uop_lrs2_rtype = next_uop_out_lrs2_rtype; // @[util.scala:104:23]
assign next_uop_frs3_en = next_uop_out_frs3_en; // @[util.scala:104:23]
assign next_uop_fcn_dw = next_uop_out_fcn_dw; // @[util.scala:104:23]
assign next_uop_fcn_op = next_uop_out_fcn_op; // @[util.scala:104:23]
assign next_uop_fp_val = next_uop_out_fp_val; // @[util.scala:104:23]
assign next_uop_fp_rm = next_uop_out_fp_rm; // @[util.scala:104:23]
assign next_uop_fp_typ = next_uop_out_fp_typ; // @[util.scala:104:23]
assign next_uop_xcpt_pf_if = next_uop_out_xcpt_pf_if; // @[util.scala:104:23]
assign next_uop_xcpt_ae_if = next_uop_out_xcpt_ae_if; // @[util.scala:104:23]
assign next_uop_xcpt_ma_if = next_uop_out_xcpt_ma_if; // @[util.scala:104:23]
assign next_uop_bp_debug_if = next_uop_out_bp_debug_if; // @[util.scala:104:23]
assign next_uop_bp_xcpt_if = next_uop_out_bp_xcpt_if; // @[util.scala:104:23]
assign next_uop_debug_fsrc = next_uop_out_debug_fsrc; // @[util.scala:104:23]
assign next_uop_debug_tsrc = next_uop_out_debug_tsrc; // @[util.scala:104:23]
wire [11:0] _next_uop_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27]
assign _next_uop_out_br_mask_T_1 = slot_uop_br_mask & _next_uop_out_br_mask_T; // @[util.scala:93:{25,27}]
assign next_uop_out_br_mask = _next_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23]
assign io_out_uop_inst_0 = next_uop_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_inst_0 = next_uop_debug_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rvc_0 = next_uop_is_rvc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_pc_0 = next_uop_debug_pc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_0_0 = next_uop_iq_type_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_1_0 = next_uop_iq_type_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_2_0 = next_uop_iq_type_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iq_type_3_0 = next_uop_iq_type_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_0_0 = next_uop_fu_code_0; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_1_0 = next_uop_fu_code_1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_2_0 = next_uop_fu_code_2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_3_0 = next_uop_fu_code_3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_4_0 = next_uop_fu_code_4; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_5_0 = next_uop_fu_code_5; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_6_0 = next_uop_fu_code_6; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_7_0 = next_uop_fu_code_7; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_8_0 = next_uop_fu_code_8; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fu_code_9_0 = next_uop_fu_code_9; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_issued_0 = next_uop_iw_issued; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p1_bypass_hint_0 = next_uop_iw_p1_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p2_bypass_hint_0 = next_uop_iw_p2_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_iw_p3_bypass_hint_0 = next_uop_iw_p3_bypass_hint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dis_col_sel_0 = next_uop_dis_col_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_mask_0 = next_uop_br_mask; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_tag_0 = next_uop_br_tag; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_br_type_0 = next_uop_br_type; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfb_0 = next_uop_is_sfb; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fence_0 = next_uop_is_fence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_fencei_0 = next_uop_is_fencei; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sfence_0 = next_uop_is_sfence; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_amo_0 = next_uop_is_amo; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_eret_0 = next_uop_is_eret; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_sys_pc2epc_0 = next_uop_is_sys_pc2epc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_rocc_0 = next_uop_is_rocc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_mov_0 = next_uop_is_mov; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ftq_idx_0 = next_uop_ftq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_edge_inst_0 = next_uop_edge_inst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pc_lob_0 = next_uop_pc_lob; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_taken_0 = next_uop_taken; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_rename_0 = next_uop_imm_rename; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_sel_0 = next_uop_imm_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pimm_0 = next_uop_pimm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_imm_packed_0 = next_uop_imm_packed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op1_sel_0 = next_uop_op1_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_op2_sel_0 = next_uop_op2_sel; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ldst_0 = next_uop_fp_ctrl_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wen_0 = next_uop_fp_ctrl_wen; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren1_0 = next_uop_fp_ctrl_ren1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren2_0 = next_uop_fp_ctrl_ren2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_ren3_0 = next_uop_fp_ctrl_ren3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap12_0 = next_uop_fp_ctrl_swap12; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_swap23_0 = next_uop_fp_ctrl_swap23; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagIn_0 = next_uop_fp_ctrl_typeTagIn; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_typeTagOut_0 = next_uop_fp_ctrl_typeTagOut; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fromint_0 = next_uop_fp_ctrl_fromint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_toint_0 = next_uop_fp_ctrl_toint; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fastpipe_0 = next_uop_fp_ctrl_fastpipe; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_fma_0 = next_uop_fp_ctrl_fma; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_div_0 = next_uop_fp_ctrl_div; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_sqrt_0 = next_uop_fp_ctrl_sqrt; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_wflags_0 = next_uop_fp_ctrl_wflags; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_ctrl_vec_0 = next_uop_fp_ctrl_vec; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rob_idx_0 = next_uop_rob_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldq_idx_0 = next_uop_ldq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stq_idx_0 = next_uop_stq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_rxq_idx_0 = next_uop_rxq_idx; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_pdst_0 = next_uop_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_0 = next_uop_prs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_0 = next_uop_prs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_0 = next_uop_prs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_0 = next_uop_ppred; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs1_busy_0 = next_uop_prs1_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs2_busy_0 = next_uop_prs2_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_prs3_busy_0 = next_uop_prs3_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ppred_busy_0 = next_uop_ppred_busy; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_stale_pdst_0 = next_uop_stale_pdst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exception_0 = next_uop_exception; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_exc_cause_0 = next_uop_exc_cause; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_cmd_0 = next_uop_mem_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_size_0 = next_uop_mem_size; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_mem_signed_0 = next_uop_mem_signed; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_ldq_0 = next_uop_uses_ldq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_uses_stq_0 = next_uop_uses_stq; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_is_unique_0 = next_uop_is_unique; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_flush_on_commit_0 = next_uop_flush_on_commit; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_csr_cmd_0 = next_uop_csr_cmd; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_is_rs1_0 = next_uop_ldst_is_rs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_ldst_0 = next_uop_ldst; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_0 = next_uop_lrs1; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_0 = next_uop_lrs2; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs3_0 = next_uop_lrs3; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_dst_rtype_0 = next_uop_dst_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs1_rtype_0 = next_uop_lrs1_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_lrs2_rtype_0 = next_uop_lrs2_rtype; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_frs3_en_0 = next_uop_frs3_en; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_dw_0 = next_uop_fcn_dw; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fcn_op_0 = next_uop_fcn_op; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_val_0 = next_uop_fp_val; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_rm_0 = next_uop_fp_rm; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_fp_typ_0 = next_uop_fp_typ; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_pf_if_0 = next_uop_xcpt_pf_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ae_if_0 = next_uop_xcpt_ae_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_xcpt_ma_if_0 = next_uop_xcpt_ma_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_debug_if_0 = next_uop_bp_debug_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_bp_xcpt_if_0 = next_uop_bp_xcpt_if; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_fsrc_0 = next_uop_debug_fsrc; // @[issue-slot.scala:49:7, :59:28]
assign io_out_uop_debug_tsrc_0 = next_uop_debug_tsrc; // @[issue-slot.scala:49:7, :59:28]
wire [11:0] _killed_T = io_brupdate_b1_mispredict_mask_0 & slot_uop_br_mask; // @[util.scala:126:51]
wire _killed_T_1 = |_killed_T; // @[util.scala:126:{51,59}]
wire killed = _killed_T_1 | io_kill_0; // @[util.scala:61:61, :126:59]
wire _io_will_be_valid_T = ~killed; // @[util.scala:61:61]
assign _io_will_be_valid_T_1 = next_valid & _io_will_be_valid_T; // @[issue-slot.scala:58:28, :65:{34,37}]
assign io_will_be_valid_0 = _io_will_be_valid_T_1; // @[issue-slot.scala:49:7, :65:34]
wire _slot_valid_T = ~killed; // @[util.scala:61:61]
wire _slot_valid_T_1 = next_valid & _slot_valid_T; // @[issue-slot.scala:58:28, :74:{30,33}] |
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_34 :
input clock : Clock
input reset : Reset
output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}}
regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff)
reg value_reg : { symbol : UInt<10>}, clock
connect io.output_prev.key, key_reg
connect io.output_prev.value, value_reg
connect io.output_nxt.key, key_reg
connect io.output_nxt.value, value_reg
connect io.cur_output_keyval.key, key_reg
connect io.cur_output_keyval.value, value_reg
when io.cmd.valid :
node _T = eq(UInt<1>(0h0), io.cmd.bits)
when _T :
connect key_reg, io.input_nxt.key
connect value_reg, io.input_nxt.value
else :
node _T_1 = eq(UInt<1>(0h1), io.cmd.bits)
when _T_1 :
when io.insert_here :
connect key_reg, io.cur_input_keyval.key
connect value_reg, io.cur_input_keyval.value
else :
node _T_2 = geq(key_reg, io.cur_input_keyval.key)
when _T_2 :
connect key_reg, io.input_prev.key
connect value_reg, io.input_prev.value
else :
skip | module PriorityQueueStage_34( // @[ShiftRegisterPriorityQueue.scala:21:7]
input clock, // @[ShiftRegisterPriorityQueue.scala:21:7]
input reset, // @[ShiftRegisterPriorityQueue.scala:21:7]
output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14]
input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14]
output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14]
);
wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24]
assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22]
assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30]
always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24]
else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24]
end
if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7]
if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30]
value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
else // @[ShiftRegisterPriorityQueue.scala:21:7]
value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22]
end
always @(posedge)
assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PMAChecker_12 :
input clock : Clock
input reset : Reset
output io : { flip paddr : UInt, resp : { cacheable : UInt<1>, r : UInt<1>, w : UInt<1>, pp : UInt<1>, al : UInt<1>, aa : UInt<1>, x : UInt<1>, eff : UInt<1>}}
node _legal_address_T = xor(io.paddr, UInt<1>(0h0))
node _legal_address_T_1 = cvt(_legal_address_T)
node _legal_address_T_2 = and(_legal_address_T_1, asSInt(UInt<13>(0h1000)))
node _legal_address_T_3 = asSInt(_legal_address_T_2)
node _legal_address_T_4 = eq(_legal_address_T_3, asSInt(UInt<1>(0h0)))
node _legal_address_T_5 = xor(io.paddr, UInt<13>(0h1000))
node _legal_address_T_6 = cvt(_legal_address_T_5)
node _legal_address_T_7 = and(_legal_address_T_6, asSInt(UInt<13>(0h1000)))
node _legal_address_T_8 = asSInt(_legal_address_T_7)
node _legal_address_T_9 = eq(_legal_address_T_8, asSInt(UInt<1>(0h0)))
node _legal_address_T_10 = xor(io.paddr, UInt<14>(0h3000))
node _legal_address_T_11 = cvt(_legal_address_T_10)
node _legal_address_T_12 = and(_legal_address_T_11, asSInt(UInt<13>(0h1000)))
node _legal_address_T_13 = asSInt(_legal_address_T_12)
node _legal_address_T_14 = eq(_legal_address_T_13, asSInt(UInt<1>(0h0)))
node _legal_address_T_15 = xor(io.paddr, UInt<17>(0h10000))
node _legal_address_T_16 = cvt(_legal_address_T_15)
node _legal_address_T_17 = and(_legal_address_T_16, asSInt(UInt<17>(0h10000)))
node _legal_address_T_18 = asSInt(_legal_address_T_17)
node _legal_address_T_19 = eq(_legal_address_T_18, asSInt(UInt<1>(0h0)))
node _legal_address_T_20 = xor(io.paddr, UInt<18>(0h20000))
node _legal_address_T_21 = cvt(_legal_address_T_20)
node _legal_address_T_22 = and(_legal_address_T_21, asSInt(UInt<13>(0h1000)))
node _legal_address_T_23 = asSInt(_legal_address_T_22)
node _legal_address_T_24 = eq(_legal_address_T_23, asSInt(UInt<1>(0h0)))
node _legal_address_T_25 = xor(io.paddr, UInt<18>(0h21000))
node _legal_address_T_26 = cvt(_legal_address_T_25)
node _legal_address_T_27 = and(_legal_address_T_26, asSInt(UInt<13>(0h1000)))
node _legal_address_T_28 = asSInt(_legal_address_T_27)
node _legal_address_T_29 = eq(_legal_address_T_28, asSInt(UInt<1>(0h0)))
node _legal_address_T_30 = xor(io.paddr, UInt<18>(0h22000))
node _legal_address_T_31 = cvt(_legal_address_T_30)
node _legal_address_T_32 = and(_legal_address_T_31, asSInt(UInt<13>(0h1000)))
node _legal_address_T_33 = asSInt(_legal_address_T_32)
node _legal_address_T_34 = eq(_legal_address_T_33, asSInt(UInt<1>(0h0)))
node _legal_address_T_35 = xor(io.paddr, UInt<18>(0h23000))
node _legal_address_T_36 = cvt(_legal_address_T_35)
node _legal_address_T_37 = and(_legal_address_T_36, asSInt(UInt<13>(0h1000)))
node _legal_address_T_38 = asSInt(_legal_address_T_37)
node _legal_address_T_39 = eq(_legal_address_T_38, asSInt(UInt<1>(0h0)))
node _legal_address_T_40 = xor(io.paddr, UInt<18>(0h24000))
node _legal_address_T_41 = cvt(_legal_address_T_40)
node _legal_address_T_42 = and(_legal_address_T_41, asSInt(UInt<13>(0h1000)))
node _legal_address_T_43 = asSInt(_legal_address_T_42)
node _legal_address_T_44 = eq(_legal_address_T_43, asSInt(UInt<1>(0h0)))
node _legal_address_T_45 = xor(io.paddr, UInt<21>(0h100000))
node _legal_address_T_46 = cvt(_legal_address_T_45)
node _legal_address_T_47 = and(_legal_address_T_46, asSInt(UInt<13>(0h1000)))
node _legal_address_T_48 = asSInt(_legal_address_T_47)
node _legal_address_T_49 = eq(_legal_address_T_48, asSInt(UInt<1>(0h0)))
node _legal_address_T_50 = xor(io.paddr, UInt<21>(0h110000))
node _legal_address_T_51 = cvt(_legal_address_T_50)
node _legal_address_T_52 = and(_legal_address_T_51, asSInt(UInt<13>(0h1000)))
node _legal_address_T_53 = asSInt(_legal_address_T_52)
node _legal_address_T_54 = eq(_legal_address_T_53, asSInt(UInt<1>(0h0)))
node _legal_address_T_55 = xor(io.paddr, UInt<26>(0h2000000))
node _legal_address_T_56 = cvt(_legal_address_T_55)
node _legal_address_T_57 = and(_legal_address_T_56, asSInt(UInt<17>(0h10000)))
node _legal_address_T_58 = asSInt(_legal_address_T_57)
node _legal_address_T_59 = eq(_legal_address_T_58, asSInt(UInt<1>(0h0)))
node _legal_address_T_60 = xor(io.paddr, UInt<26>(0h2010000))
node _legal_address_T_61 = cvt(_legal_address_T_60)
node _legal_address_T_62 = and(_legal_address_T_61, asSInt(UInt<13>(0h1000)))
node _legal_address_T_63 = asSInt(_legal_address_T_62)
node _legal_address_T_64 = eq(_legal_address_T_63, asSInt(UInt<1>(0h0)))
node _legal_address_T_65 = xor(io.paddr, UInt<28>(0h8000000))
node _legal_address_T_66 = cvt(_legal_address_T_65)
node _legal_address_T_67 = and(_legal_address_T_66, asSInt(UInt<17>(0h10000)))
node _legal_address_T_68 = asSInt(_legal_address_T_67)
node _legal_address_T_69 = eq(_legal_address_T_68, asSInt(UInt<1>(0h0)))
node _legal_address_T_70 = xor(io.paddr, UInt<28>(0hc000000))
node _legal_address_T_71 = cvt(_legal_address_T_70)
node _legal_address_T_72 = and(_legal_address_T_71, asSInt(UInt<27>(0h4000000)))
node _legal_address_T_73 = asSInt(_legal_address_T_72)
node _legal_address_T_74 = eq(_legal_address_T_73, asSInt(UInt<1>(0h0)))
node _legal_address_T_75 = xor(io.paddr, UInt<29>(0h10020000))
node _legal_address_T_76 = cvt(_legal_address_T_75)
node _legal_address_T_77 = and(_legal_address_T_76, asSInt(UInt<13>(0h1000)))
node _legal_address_T_78 = asSInt(_legal_address_T_77)
node _legal_address_T_79 = eq(_legal_address_T_78, asSInt(UInt<1>(0h0)))
node _legal_address_T_80 = xor(io.paddr, UInt<32>(0h80000000))
node _legal_address_T_81 = cvt(_legal_address_T_80)
node _legal_address_T_82 = and(_legal_address_T_81, asSInt(UInt<29>(0h10000000)))
node _legal_address_T_83 = asSInt(_legal_address_T_82)
node _legal_address_T_84 = eq(_legal_address_T_83, asSInt(UInt<1>(0h0)))
wire _legal_address_WIRE : UInt<1>[17]
connect _legal_address_WIRE[0], _legal_address_T_4
connect _legal_address_WIRE[1], _legal_address_T_9
connect _legal_address_WIRE[2], _legal_address_T_14
connect _legal_address_WIRE[3], _legal_address_T_19
connect _legal_address_WIRE[4], _legal_address_T_24
connect _legal_address_WIRE[5], _legal_address_T_29
connect _legal_address_WIRE[6], _legal_address_T_34
connect _legal_address_WIRE[7], _legal_address_T_39
connect _legal_address_WIRE[8], _legal_address_T_44
connect _legal_address_WIRE[9], _legal_address_T_49
connect _legal_address_WIRE[10], _legal_address_T_54
connect _legal_address_WIRE[11], _legal_address_T_59
connect _legal_address_WIRE[12], _legal_address_T_64
connect _legal_address_WIRE[13], _legal_address_T_69
connect _legal_address_WIRE[14], _legal_address_T_74
connect _legal_address_WIRE[15], _legal_address_T_79
connect _legal_address_WIRE[16], _legal_address_T_84
node _legal_address_T_85 = or(_legal_address_WIRE[0], _legal_address_WIRE[1])
node _legal_address_T_86 = or(_legal_address_T_85, _legal_address_WIRE[2])
node _legal_address_T_87 = or(_legal_address_T_86, _legal_address_WIRE[3])
node _legal_address_T_88 = or(_legal_address_T_87, _legal_address_WIRE[4])
node _legal_address_T_89 = or(_legal_address_T_88, _legal_address_WIRE[5])
node _legal_address_T_90 = or(_legal_address_T_89, _legal_address_WIRE[6])
node _legal_address_T_91 = or(_legal_address_T_90, _legal_address_WIRE[7])
node _legal_address_T_92 = or(_legal_address_T_91, _legal_address_WIRE[8])
node _legal_address_T_93 = or(_legal_address_T_92, _legal_address_WIRE[9])
node _legal_address_T_94 = or(_legal_address_T_93, _legal_address_WIRE[10])
node _legal_address_T_95 = or(_legal_address_T_94, _legal_address_WIRE[11])
node _legal_address_T_96 = or(_legal_address_T_95, _legal_address_WIRE[12])
node _legal_address_T_97 = or(_legal_address_T_96, _legal_address_WIRE[13])
node _legal_address_T_98 = or(_legal_address_T_97, _legal_address_WIRE[14])
node _legal_address_T_99 = or(_legal_address_T_98, _legal_address_WIRE[15])
node legal_address = or(_legal_address_T_99, _legal_address_WIRE[16])
node _io_resp_cacheable_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_cacheable_T_1 = cvt(_io_resp_cacheable_T)
node _io_resp_cacheable_T_2 = and(_io_resp_cacheable_T_1, asSInt(UInt<33>(0h8c020000)))
node _io_resp_cacheable_T_3 = asSInt(_io_resp_cacheable_T_2)
node _io_resp_cacheable_T_4 = eq(_io_resp_cacheable_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_5 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_cacheable_T_6 = cvt(_io_resp_cacheable_T_5)
node _io_resp_cacheable_T_7 = and(_io_resp_cacheable_T_6, asSInt(UInt<33>(0h8c031000)))
node _io_resp_cacheable_T_8 = asSInt(_io_resp_cacheable_T_7)
node _io_resp_cacheable_T_9 = eq(_io_resp_cacheable_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_10 = xor(io.paddr, UInt<18>(0h20000))
node _io_resp_cacheable_T_11 = cvt(_io_resp_cacheable_T_10)
node _io_resp_cacheable_T_12 = and(_io_resp_cacheable_T_11, asSInt(UInt<33>(0h8c030000)))
node _io_resp_cacheable_T_13 = asSInt(_io_resp_cacheable_T_12)
node _io_resp_cacheable_T_14 = eq(_io_resp_cacheable_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_15 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_cacheable_T_16 = cvt(_io_resp_cacheable_T_15)
node _io_resp_cacheable_T_17 = and(_io_resp_cacheable_T_16, asSInt(UInt<33>(0h8c000000)))
node _io_resp_cacheable_T_18 = asSInt(_io_resp_cacheable_T_17)
node _io_resp_cacheable_T_19 = eq(_io_resp_cacheable_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_20 = or(_io_resp_cacheable_T_4, _io_resp_cacheable_T_9)
node _io_resp_cacheable_T_21 = or(_io_resp_cacheable_T_20, _io_resp_cacheable_T_14)
node _io_resp_cacheable_T_22 = or(_io_resp_cacheable_T_21, _io_resp_cacheable_T_19)
node _io_resp_cacheable_T_23 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_cacheable_T_24 = cvt(_io_resp_cacheable_T_23)
node _io_resp_cacheable_T_25 = and(_io_resp_cacheable_T_24, asSInt(UInt<33>(0h8c030000)))
node _io_resp_cacheable_T_26 = asSInt(_io_resp_cacheable_T_25)
node _io_resp_cacheable_T_27 = eq(_io_resp_cacheable_T_26, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_28 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_cacheable_T_29 = cvt(_io_resp_cacheable_T_28)
node _io_resp_cacheable_T_30 = and(_io_resp_cacheable_T_29, asSInt(UInt<33>(0h80000000)))
node _io_resp_cacheable_T_31 = asSInt(_io_resp_cacheable_T_30)
node _io_resp_cacheable_T_32 = eq(_io_resp_cacheable_T_31, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_33 = or(_io_resp_cacheable_T_27, _io_resp_cacheable_T_32)
node _io_resp_cacheable_T_34 = mux(_io_resp_cacheable_T_22, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_cacheable_T_35 = mux(_io_resp_cacheable_T_33, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_cacheable_T_36 = or(_io_resp_cacheable_T_34, _io_resp_cacheable_T_35)
wire _io_resp_cacheable_WIRE : UInt<1>
connect _io_resp_cacheable_WIRE, _io_resp_cacheable_T_36
node _io_resp_cacheable_T_37 = and(legal_address, _io_resp_cacheable_WIRE)
connect io.resp.cacheable, _io_resp_cacheable_T_37
node _io_resp_r_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_r_T_1 = cvt(_io_resp_r_T)
node _io_resp_r_T_2 = and(_io_resp_r_T_1, asSInt(UInt<1>(0h0)))
node _io_resp_r_T_3 = asSInt(_io_resp_r_T_2)
node _io_resp_r_T_4 = eq(_io_resp_r_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_r_T_5 = and(legal_address, UInt<1>(0h1))
connect io.resp.r, _io_resp_r_T_5
node _io_resp_w_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_w_T_1 = cvt(_io_resp_w_T)
node _io_resp_w_T_2 = and(_io_resp_w_T_1, asSInt(UInt<33>(0hfffd8000)))
node _io_resp_w_T_3 = asSInt(_io_resp_w_T_2)
node _io_resp_w_T_4 = eq(_io_resp_w_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_5 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_w_T_6 = cvt(_io_resp_w_T_5)
node _io_resp_w_T_7 = and(_io_resp_w_T_6, asSInt(UInt<33>(0hfffe9000)))
node _io_resp_w_T_8 = asSInt(_io_resp_w_T_7)
node _io_resp_w_T_9 = eq(_io_resp_w_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_10 = xor(io.paddr, UInt<26>(0h2000000))
node _io_resp_w_T_11 = cvt(_io_resp_w_T_10)
node _io_resp_w_T_12 = and(_io_resp_w_T_11, asSInt(UInt<33>(0hffff0000)))
node _io_resp_w_T_13 = asSInt(_io_resp_w_T_12)
node _io_resp_w_T_14 = eq(_io_resp_w_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_15 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_w_T_16 = cvt(_io_resp_w_T_15)
node _io_resp_w_T_17 = and(_io_resp_w_T_16, asSInt(UInt<33>(0hffff9000)))
node _io_resp_w_T_18 = asSInt(_io_resp_w_T_17)
node _io_resp_w_T_19 = eq(_io_resp_w_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_20 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_w_T_21 = cvt(_io_resp_w_T_20)
node _io_resp_w_T_22 = and(_io_resp_w_T_21, asSInt(UInt<33>(0hffff0000)))
node _io_resp_w_T_23 = asSInt(_io_resp_w_T_22)
node _io_resp_w_T_24 = eq(_io_resp_w_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_25 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_w_T_26 = cvt(_io_resp_w_T_25)
node _io_resp_w_T_27 = and(_io_resp_w_T_26, asSInt(UInt<33>(0hfc000000)))
node _io_resp_w_T_28 = asSInt(_io_resp_w_T_27)
node _io_resp_w_T_29 = eq(_io_resp_w_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_30 = xor(io.paddr, UInt<29>(0h10020000))
node _io_resp_w_T_31 = cvt(_io_resp_w_T_30)
node _io_resp_w_T_32 = and(_io_resp_w_T_31, asSInt(UInt<33>(0hffff9000)))
node _io_resp_w_T_33 = asSInt(_io_resp_w_T_32)
node _io_resp_w_T_34 = eq(_io_resp_w_T_33, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_35 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_w_T_36 = cvt(_io_resp_w_T_35)
node _io_resp_w_T_37 = and(_io_resp_w_T_36, asSInt(UInt<33>(0hf0000000)))
node _io_resp_w_T_38 = asSInt(_io_resp_w_T_37)
node _io_resp_w_T_39 = eq(_io_resp_w_T_38, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_40 = or(_io_resp_w_T_4, _io_resp_w_T_9)
node _io_resp_w_T_41 = or(_io_resp_w_T_40, _io_resp_w_T_14)
node _io_resp_w_T_42 = or(_io_resp_w_T_41, _io_resp_w_T_19)
node _io_resp_w_T_43 = or(_io_resp_w_T_42, _io_resp_w_T_24)
node _io_resp_w_T_44 = or(_io_resp_w_T_43, _io_resp_w_T_29)
node _io_resp_w_T_45 = or(_io_resp_w_T_44, _io_resp_w_T_34)
node _io_resp_w_T_46 = or(_io_resp_w_T_45, _io_resp_w_T_39)
node _io_resp_w_T_47 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_w_T_48 = cvt(_io_resp_w_T_47)
node _io_resp_w_T_49 = and(_io_resp_w_T_48, asSInt(UInt<33>(0hffff0000)))
node _io_resp_w_T_50 = asSInt(_io_resp_w_T_49)
node _io_resp_w_T_51 = eq(_io_resp_w_T_50, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_52 = mux(_io_resp_w_T_46, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_w_T_53 = mux(_io_resp_w_T_51, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_w_T_54 = or(_io_resp_w_T_52, _io_resp_w_T_53)
wire _io_resp_w_WIRE : UInt<1>
connect _io_resp_w_WIRE, _io_resp_w_T_54
node _io_resp_w_T_55 = and(legal_address, _io_resp_w_WIRE)
connect io.resp.w, _io_resp_w_T_55
node _io_resp_pp_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_pp_T_1 = cvt(_io_resp_pp_T)
node _io_resp_pp_T_2 = and(_io_resp_pp_T_1, asSInt(UInt<33>(0hfffd8000)))
node _io_resp_pp_T_3 = asSInt(_io_resp_pp_T_2)
node _io_resp_pp_T_4 = eq(_io_resp_pp_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_5 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_pp_T_6 = cvt(_io_resp_pp_T_5)
node _io_resp_pp_T_7 = and(_io_resp_pp_T_6, asSInt(UInt<33>(0hfffe9000)))
node _io_resp_pp_T_8 = asSInt(_io_resp_pp_T_7)
node _io_resp_pp_T_9 = eq(_io_resp_pp_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_10 = xor(io.paddr, UInt<26>(0h2000000))
node _io_resp_pp_T_11 = cvt(_io_resp_pp_T_10)
node _io_resp_pp_T_12 = and(_io_resp_pp_T_11, asSInt(UInt<33>(0hffff0000)))
node _io_resp_pp_T_13 = asSInt(_io_resp_pp_T_12)
node _io_resp_pp_T_14 = eq(_io_resp_pp_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_15 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_pp_T_16 = cvt(_io_resp_pp_T_15)
node _io_resp_pp_T_17 = and(_io_resp_pp_T_16, asSInt(UInt<33>(0hffff9000)))
node _io_resp_pp_T_18 = asSInt(_io_resp_pp_T_17)
node _io_resp_pp_T_19 = eq(_io_resp_pp_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_20 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_pp_T_21 = cvt(_io_resp_pp_T_20)
node _io_resp_pp_T_22 = and(_io_resp_pp_T_21, asSInt(UInt<33>(0hffff0000)))
node _io_resp_pp_T_23 = asSInt(_io_resp_pp_T_22)
node _io_resp_pp_T_24 = eq(_io_resp_pp_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_25 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_pp_T_26 = cvt(_io_resp_pp_T_25)
node _io_resp_pp_T_27 = and(_io_resp_pp_T_26, asSInt(UInt<33>(0hfc000000)))
node _io_resp_pp_T_28 = asSInt(_io_resp_pp_T_27)
node _io_resp_pp_T_29 = eq(_io_resp_pp_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_30 = xor(io.paddr, UInt<29>(0h10020000))
node _io_resp_pp_T_31 = cvt(_io_resp_pp_T_30)
node _io_resp_pp_T_32 = and(_io_resp_pp_T_31, asSInt(UInt<33>(0hffff9000)))
node _io_resp_pp_T_33 = asSInt(_io_resp_pp_T_32)
node _io_resp_pp_T_34 = eq(_io_resp_pp_T_33, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_35 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_pp_T_36 = cvt(_io_resp_pp_T_35)
node _io_resp_pp_T_37 = and(_io_resp_pp_T_36, asSInt(UInt<33>(0hf0000000)))
node _io_resp_pp_T_38 = asSInt(_io_resp_pp_T_37)
node _io_resp_pp_T_39 = eq(_io_resp_pp_T_38, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_40 = or(_io_resp_pp_T_4, _io_resp_pp_T_9)
node _io_resp_pp_T_41 = or(_io_resp_pp_T_40, _io_resp_pp_T_14)
node _io_resp_pp_T_42 = or(_io_resp_pp_T_41, _io_resp_pp_T_19)
node _io_resp_pp_T_43 = or(_io_resp_pp_T_42, _io_resp_pp_T_24)
node _io_resp_pp_T_44 = or(_io_resp_pp_T_43, _io_resp_pp_T_29)
node _io_resp_pp_T_45 = or(_io_resp_pp_T_44, _io_resp_pp_T_34)
node _io_resp_pp_T_46 = or(_io_resp_pp_T_45, _io_resp_pp_T_39)
node _io_resp_pp_T_47 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_pp_T_48 = cvt(_io_resp_pp_T_47)
node _io_resp_pp_T_49 = and(_io_resp_pp_T_48, asSInt(UInt<33>(0hffff0000)))
node _io_resp_pp_T_50 = asSInt(_io_resp_pp_T_49)
node _io_resp_pp_T_51 = eq(_io_resp_pp_T_50, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_52 = mux(_io_resp_pp_T_46, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_pp_T_53 = mux(_io_resp_pp_T_51, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_pp_T_54 = or(_io_resp_pp_T_52, _io_resp_pp_T_53)
wire _io_resp_pp_WIRE : UInt<1>
connect _io_resp_pp_WIRE, _io_resp_pp_T_54
node _io_resp_pp_T_55 = and(legal_address, _io_resp_pp_WIRE)
connect io.resp.pp, _io_resp_pp_T_55
node _io_resp_al_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_al_T_1 = cvt(_io_resp_al_T)
node _io_resp_al_T_2 = and(_io_resp_al_T_1, asSInt(UInt<33>(0hfffd8000)))
node _io_resp_al_T_3 = asSInt(_io_resp_al_T_2)
node _io_resp_al_T_4 = eq(_io_resp_al_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_5 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_al_T_6 = cvt(_io_resp_al_T_5)
node _io_resp_al_T_7 = and(_io_resp_al_T_6, asSInt(UInt<33>(0hfffe9000)))
node _io_resp_al_T_8 = asSInt(_io_resp_al_T_7)
node _io_resp_al_T_9 = eq(_io_resp_al_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_10 = xor(io.paddr, UInt<26>(0h2000000))
node _io_resp_al_T_11 = cvt(_io_resp_al_T_10)
node _io_resp_al_T_12 = and(_io_resp_al_T_11, asSInt(UInt<33>(0hffff0000)))
node _io_resp_al_T_13 = asSInt(_io_resp_al_T_12)
node _io_resp_al_T_14 = eq(_io_resp_al_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_15 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_al_T_16 = cvt(_io_resp_al_T_15)
node _io_resp_al_T_17 = and(_io_resp_al_T_16, asSInt(UInt<33>(0hffff9000)))
node _io_resp_al_T_18 = asSInt(_io_resp_al_T_17)
node _io_resp_al_T_19 = eq(_io_resp_al_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_20 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_al_T_21 = cvt(_io_resp_al_T_20)
node _io_resp_al_T_22 = and(_io_resp_al_T_21, asSInt(UInt<33>(0hffff0000)))
node _io_resp_al_T_23 = asSInt(_io_resp_al_T_22)
node _io_resp_al_T_24 = eq(_io_resp_al_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_25 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_al_T_26 = cvt(_io_resp_al_T_25)
node _io_resp_al_T_27 = and(_io_resp_al_T_26, asSInt(UInt<33>(0hfc000000)))
node _io_resp_al_T_28 = asSInt(_io_resp_al_T_27)
node _io_resp_al_T_29 = eq(_io_resp_al_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_30 = xor(io.paddr, UInt<29>(0h10020000))
node _io_resp_al_T_31 = cvt(_io_resp_al_T_30)
node _io_resp_al_T_32 = and(_io_resp_al_T_31, asSInt(UInt<33>(0hffff9000)))
node _io_resp_al_T_33 = asSInt(_io_resp_al_T_32)
node _io_resp_al_T_34 = eq(_io_resp_al_T_33, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_35 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_al_T_36 = cvt(_io_resp_al_T_35)
node _io_resp_al_T_37 = and(_io_resp_al_T_36, asSInt(UInt<33>(0hf0000000)))
node _io_resp_al_T_38 = asSInt(_io_resp_al_T_37)
node _io_resp_al_T_39 = eq(_io_resp_al_T_38, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_40 = or(_io_resp_al_T_4, _io_resp_al_T_9)
node _io_resp_al_T_41 = or(_io_resp_al_T_40, _io_resp_al_T_14)
node _io_resp_al_T_42 = or(_io_resp_al_T_41, _io_resp_al_T_19)
node _io_resp_al_T_43 = or(_io_resp_al_T_42, _io_resp_al_T_24)
node _io_resp_al_T_44 = or(_io_resp_al_T_43, _io_resp_al_T_29)
node _io_resp_al_T_45 = or(_io_resp_al_T_44, _io_resp_al_T_34)
node _io_resp_al_T_46 = or(_io_resp_al_T_45, _io_resp_al_T_39)
node _io_resp_al_T_47 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_al_T_48 = cvt(_io_resp_al_T_47)
node _io_resp_al_T_49 = and(_io_resp_al_T_48, asSInt(UInt<33>(0hffff0000)))
node _io_resp_al_T_50 = asSInt(_io_resp_al_T_49)
node _io_resp_al_T_51 = eq(_io_resp_al_T_50, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_52 = mux(_io_resp_al_T_46, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_al_T_53 = mux(_io_resp_al_T_51, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_al_T_54 = or(_io_resp_al_T_52, _io_resp_al_T_53)
wire _io_resp_al_WIRE : UInt<1>
connect _io_resp_al_WIRE, _io_resp_al_T_54
node _io_resp_al_T_55 = and(legal_address, _io_resp_al_WIRE)
connect io.resp.al, _io_resp_al_T_55
node _io_resp_aa_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_aa_T_1 = cvt(_io_resp_aa_T)
node _io_resp_aa_T_2 = and(_io_resp_aa_T_1, asSInt(UInt<33>(0hfffd8000)))
node _io_resp_aa_T_3 = asSInt(_io_resp_aa_T_2)
node _io_resp_aa_T_4 = eq(_io_resp_aa_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_5 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_aa_T_6 = cvt(_io_resp_aa_T_5)
node _io_resp_aa_T_7 = and(_io_resp_aa_T_6, asSInt(UInt<33>(0hfffe9000)))
node _io_resp_aa_T_8 = asSInt(_io_resp_aa_T_7)
node _io_resp_aa_T_9 = eq(_io_resp_aa_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_10 = xor(io.paddr, UInt<26>(0h2000000))
node _io_resp_aa_T_11 = cvt(_io_resp_aa_T_10)
node _io_resp_aa_T_12 = and(_io_resp_aa_T_11, asSInt(UInt<33>(0hffff0000)))
node _io_resp_aa_T_13 = asSInt(_io_resp_aa_T_12)
node _io_resp_aa_T_14 = eq(_io_resp_aa_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_15 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_aa_T_16 = cvt(_io_resp_aa_T_15)
node _io_resp_aa_T_17 = and(_io_resp_aa_T_16, asSInt(UInt<33>(0hffff9000)))
node _io_resp_aa_T_18 = asSInt(_io_resp_aa_T_17)
node _io_resp_aa_T_19 = eq(_io_resp_aa_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_20 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_aa_T_21 = cvt(_io_resp_aa_T_20)
node _io_resp_aa_T_22 = and(_io_resp_aa_T_21, asSInt(UInt<33>(0hffff0000)))
node _io_resp_aa_T_23 = asSInt(_io_resp_aa_T_22)
node _io_resp_aa_T_24 = eq(_io_resp_aa_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_25 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_aa_T_26 = cvt(_io_resp_aa_T_25)
node _io_resp_aa_T_27 = and(_io_resp_aa_T_26, asSInt(UInt<33>(0hfc000000)))
node _io_resp_aa_T_28 = asSInt(_io_resp_aa_T_27)
node _io_resp_aa_T_29 = eq(_io_resp_aa_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_30 = xor(io.paddr, UInt<29>(0h10020000))
node _io_resp_aa_T_31 = cvt(_io_resp_aa_T_30)
node _io_resp_aa_T_32 = and(_io_resp_aa_T_31, asSInt(UInt<33>(0hffff9000)))
node _io_resp_aa_T_33 = asSInt(_io_resp_aa_T_32)
node _io_resp_aa_T_34 = eq(_io_resp_aa_T_33, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_35 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_aa_T_36 = cvt(_io_resp_aa_T_35)
node _io_resp_aa_T_37 = and(_io_resp_aa_T_36, asSInt(UInt<33>(0hf0000000)))
node _io_resp_aa_T_38 = asSInt(_io_resp_aa_T_37)
node _io_resp_aa_T_39 = eq(_io_resp_aa_T_38, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_40 = or(_io_resp_aa_T_4, _io_resp_aa_T_9)
node _io_resp_aa_T_41 = or(_io_resp_aa_T_40, _io_resp_aa_T_14)
node _io_resp_aa_T_42 = or(_io_resp_aa_T_41, _io_resp_aa_T_19)
node _io_resp_aa_T_43 = or(_io_resp_aa_T_42, _io_resp_aa_T_24)
node _io_resp_aa_T_44 = or(_io_resp_aa_T_43, _io_resp_aa_T_29)
node _io_resp_aa_T_45 = or(_io_resp_aa_T_44, _io_resp_aa_T_34)
node _io_resp_aa_T_46 = or(_io_resp_aa_T_45, _io_resp_aa_T_39)
node _io_resp_aa_T_47 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_aa_T_48 = cvt(_io_resp_aa_T_47)
node _io_resp_aa_T_49 = and(_io_resp_aa_T_48, asSInt(UInt<33>(0hffff0000)))
node _io_resp_aa_T_50 = asSInt(_io_resp_aa_T_49)
node _io_resp_aa_T_51 = eq(_io_resp_aa_T_50, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_52 = mux(_io_resp_aa_T_46, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_aa_T_53 = mux(_io_resp_aa_T_51, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_aa_T_54 = or(_io_resp_aa_T_52, _io_resp_aa_T_53)
wire _io_resp_aa_WIRE : UInt<1>
connect _io_resp_aa_WIRE, _io_resp_aa_T_54
node _io_resp_aa_T_55 = and(legal_address, _io_resp_aa_WIRE)
connect io.resp.aa, _io_resp_aa_T_55
node _io_resp_x_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_x_T_1 = cvt(_io_resp_x_T)
node _io_resp_x_T_2 = and(_io_resp_x_T_1, asSInt(UInt<33>(0hfffff000)))
node _io_resp_x_T_3 = asSInt(_io_resp_x_T_2)
node _io_resp_x_T_4 = eq(_io_resp_x_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_5 = xor(io.paddr, UInt<14>(0h3000))
node _io_resp_x_T_6 = cvt(_io_resp_x_T_5)
node _io_resp_x_T_7 = and(_io_resp_x_T_6, asSInt(UInt<33>(0hfffff000)))
node _io_resp_x_T_8 = asSInt(_io_resp_x_T_7)
node _io_resp_x_T_9 = eq(_io_resp_x_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_10 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_x_T_11 = cvt(_io_resp_x_T_10)
node _io_resp_x_T_12 = and(_io_resp_x_T_11, asSInt(UInt<33>(0hffff0000)))
node _io_resp_x_T_13 = asSInt(_io_resp_x_T_12)
node _io_resp_x_T_14 = eq(_io_resp_x_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_15 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_x_T_16 = cvt(_io_resp_x_T_15)
node _io_resp_x_T_17 = and(_io_resp_x_T_16, asSInt(UInt<33>(0hffff0000)))
node _io_resp_x_T_18 = asSInt(_io_resp_x_T_17)
node _io_resp_x_T_19 = eq(_io_resp_x_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_20 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_x_T_21 = cvt(_io_resp_x_T_20)
node _io_resp_x_T_22 = and(_io_resp_x_T_21, asSInt(UInt<33>(0hf0000000)))
node _io_resp_x_T_23 = asSInt(_io_resp_x_T_22)
node _io_resp_x_T_24 = eq(_io_resp_x_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_25 = or(_io_resp_x_T_4, _io_resp_x_T_9)
node _io_resp_x_T_26 = or(_io_resp_x_T_25, _io_resp_x_T_14)
node _io_resp_x_T_27 = or(_io_resp_x_T_26, _io_resp_x_T_19)
node _io_resp_x_T_28 = or(_io_resp_x_T_27, _io_resp_x_T_24)
node _io_resp_x_T_29 = xor(io.paddr, UInt<13>(0h1000))
node _io_resp_x_T_30 = cvt(_io_resp_x_T_29)
node _io_resp_x_T_31 = and(_io_resp_x_T_30, asSInt(UInt<33>(0hfffff000)))
node _io_resp_x_T_32 = asSInt(_io_resp_x_T_31)
node _io_resp_x_T_33 = eq(_io_resp_x_T_32, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_34 = xor(io.paddr, UInt<18>(0h20000))
node _io_resp_x_T_35 = cvt(_io_resp_x_T_34)
node _io_resp_x_T_36 = and(_io_resp_x_T_35, asSInt(UInt<33>(0hffffc000)))
node _io_resp_x_T_37 = asSInt(_io_resp_x_T_36)
node _io_resp_x_T_38 = eq(_io_resp_x_T_37, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_39 = xor(io.paddr, UInt<18>(0h24000))
node _io_resp_x_T_40 = cvt(_io_resp_x_T_39)
node _io_resp_x_T_41 = and(_io_resp_x_T_40, asSInt(UInt<33>(0hfffff000)))
node _io_resp_x_T_42 = asSInt(_io_resp_x_T_41)
node _io_resp_x_T_43 = eq(_io_resp_x_T_42, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_44 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_x_T_45 = cvt(_io_resp_x_T_44)
node _io_resp_x_T_46 = and(_io_resp_x_T_45, asSInt(UInt<33>(0hfffef000)))
node _io_resp_x_T_47 = asSInt(_io_resp_x_T_46)
node _io_resp_x_T_48 = eq(_io_resp_x_T_47, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_49 = xor(io.paddr, UInt<26>(0h2000000))
node _io_resp_x_T_50 = cvt(_io_resp_x_T_49)
node _io_resp_x_T_51 = and(_io_resp_x_T_50, asSInt(UInt<33>(0hffff0000)))
node _io_resp_x_T_52 = asSInt(_io_resp_x_T_51)
node _io_resp_x_T_53 = eq(_io_resp_x_T_52, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_54 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_x_T_55 = cvt(_io_resp_x_T_54)
node _io_resp_x_T_56 = and(_io_resp_x_T_55, asSInt(UInt<33>(0hfffff000)))
node _io_resp_x_T_57 = asSInt(_io_resp_x_T_56)
node _io_resp_x_T_58 = eq(_io_resp_x_T_57, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_59 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_x_T_60 = cvt(_io_resp_x_T_59)
node _io_resp_x_T_61 = and(_io_resp_x_T_60, asSInt(UInt<33>(0hfc000000)))
node _io_resp_x_T_62 = asSInt(_io_resp_x_T_61)
node _io_resp_x_T_63 = eq(_io_resp_x_T_62, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_64 = xor(io.paddr, UInt<29>(0h10020000))
node _io_resp_x_T_65 = cvt(_io_resp_x_T_64)
node _io_resp_x_T_66 = and(_io_resp_x_T_65, asSInt(UInt<33>(0hfffff000)))
node _io_resp_x_T_67 = asSInt(_io_resp_x_T_66)
node _io_resp_x_T_68 = eq(_io_resp_x_T_67, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_69 = or(_io_resp_x_T_33, _io_resp_x_T_38)
node _io_resp_x_T_70 = or(_io_resp_x_T_69, _io_resp_x_T_43)
node _io_resp_x_T_71 = or(_io_resp_x_T_70, _io_resp_x_T_48)
node _io_resp_x_T_72 = or(_io_resp_x_T_71, _io_resp_x_T_53)
node _io_resp_x_T_73 = or(_io_resp_x_T_72, _io_resp_x_T_58)
node _io_resp_x_T_74 = or(_io_resp_x_T_73, _io_resp_x_T_63)
node _io_resp_x_T_75 = or(_io_resp_x_T_74, _io_resp_x_T_68)
node _io_resp_x_T_76 = mux(_io_resp_x_T_28, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_x_T_77 = mux(_io_resp_x_T_75, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_x_T_78 = or(_io_resp_x_T_76, _io_resp_x_T_77)
wire _io_resp_x_WIRE : UInt<1>
connect _io_resp_x_WIRE, _io_resp_x_T_78
node _io_resp_x_T_79 = and(legal_address, _io_resp_x_WIRE)
connect io.resp.x, _io_resp_x_T_79
node _io_resp_eff_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_eff_T_1 = cvt(_io_resp_eff_T)
node _io_resp_eff_T_2 = and(_io_resp_eff_T_1, asSInt(UInt<33>(0hffffa000)))
node _io_resp_eff_T_3 = asSInt(_io_resp_eff_T_2)
node _io_resp_eff_T_4 = eq(_io_resp_eff_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_5 = xor(io.paddr, UInt<18>(0h20000))
node _io_resp_eff_T_6 = cvt(_io_resp_eff_T_5)
node _io_resp_eff_T_7 = and(_io_resp_eff_T_6, asSInt(UInt<33>(0hffff8000)))
node _io_resp_eff_T_8 = asSInt(_io_resp_eff_T_7)
node _io_resp_eff_T_9 = eq(_io_resp_eff_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_10 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_eff_T_11 = cvt(_io_resp_eff_T_10)
node _io_resp_eff_T_12 = and(_io_resp_eff_T_11, asSInt(UInt<33>(0hfffeb000)))
node _io_resp_eff_T_13 = asSInt(_io_resp_eff_T_12)
node _io_resp_eff_T_14 = eq(_io_resp_eff_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_15 = xor(io.paddr, UInt<26>(0h2000000))
node _io_resp_eff_T_16 = cvt(_io_resp_eff_T_15)
node _io_resp_eff_T_17 = and(_io_resp_eff_T_16, asSInt(UInt<33>(0hffff0000)))
node _io_resp_eff_T_18 = asSInt(_io_resp_eff_T_17)
node _io_resp_eff_T_19 = eq(_io_resp_eff_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_20 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_eff_T_21 = cvt(_io_resp_eff_T_20)
node _io_resp_eff_T_22 = and(_io_resp_eff_T_21, asSInt(UInt<33>(0hffffb000)))
node _io_resp_eff_T_23 = asSInt(_io_resp_eff_T_22)
node _io_resp_eff_T_24 = eq(_io_resp_eff_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_25 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_eff_T_26 = cvt(_io_resp_eff_T_25)
node _io_resp_eff_T_27 = and(_io_resp_eff_T_26, asSInt(UInt<33>(0hfc000000)))
node _io_resp_eff_T_28 = asSInt(_io_resp_eff_T_27)
node _io_resp_eff_T_29 = eq(_io_resp_eff_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_30 = xor(io.paddr, UInt<29>(0h10020000))
node _io_resp_eff_T_31 = cvt(_io_resp_eff_T_30)
node _io_resp_eff_T_32 = and(_io_resp_eff_T_31, asSInt(UInt<33>(0hffffb000)))
node _io_resp_eff_T_33 = asSInt(_io_resp_eff_T_32)
node _io_resp_eff_T_34 = eq(_io_resp_eff_T_33, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_35 = or(_io_resp_eff_T_4, _io_resp_eff_T_9)
node _io_resp_eff_T_36 = or(_io_resp_eff_T_35, _io_resp_eff_T_14)
node _io_resp_eff_T_37 = or(_io_resp_eff_T_36, _io_resp_eff_T_19)
node _io_resp_eff_T_38 = or(_io_resp_eff_T_37, _io_resp_eff_T_24)
node _io_resp_eff_T_39 = or(_io_resp_eff_T_38, _io_resp_eff_T_29)
node _io_resp_eff_T_40 = or(_io_resp_eff_T_39, _io_resp_eff_T_34)
node _io_resp_eff_T_41 = xor(io.paddr, UInt<14>(0h3000))
node _io_resp_eff_T_42 = cvt(_io_resp_eff_T_41)
node _io_resp_eff_T_43 = and(_io_resp_eff_T_42, asSInt(UInt<33>(0hffffb000)))
node _io_resp_eff_T_44 = asSInt(_io_resp_eff_T_43)
node _io_resp_eff_T_45 = eq(_io_resp_eff_T_44, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_46 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_eff_T_47 = cvt(_io_resp_eff_T_46)
node _io_resp_eff_T_48 = and(_io_resp_eff_T_47, asSInt(UInt<33>(0hffff0000)))
node _io_resp_eff_T_49 = asSInt(_io_resp_eff_T_48)
node _io_resp_eff_T_50 = eq(_io_resp_eff_T_49, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_51 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_eff_T_52 = cvt(_io_resp_eff_T_51)
node _io_resp_eff_T_53 = and(_io_resp_eff_T_52, asSInt(UInt<33>(0hffff0000)))
node _io_resp_eff_T_54 = asSInt(_io_resp_eff_T_53)
node _io_resp_eff_T_55 = eq(_io_resp_eff_T_54, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_56 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_eff_T_57 = cvt(_io_resp_eff_T_56)
node _io_resp_eff_T_58 = and(_io_resp_eff_T_57, asSInt(UInt<33>(0hf0000000)))
node _io_resp_eff_T_59 = asSInt(_io_resp_eff_T_58)
node _io_resp_eff_T_60 = eq(_io_resp_eff_T_59, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_61 = or(_io_resp_eff_T_45, _io_resp_eff_T_50)
node _io_resp_eff_T_62 = or(_io_resp_eff_T_61, _io_resp_eff_T_55)
node _io_resp_eff_T_63 = or(_io_resp_eff_T_62, _io_resp_eff_T_60)
node _io_resp_eff_T_64 = mux(_io_resp_eff_T_40, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_eff_T_65 = mux(_io_resp_eff_T_63, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_eff_T_66 = or(_io_resp_eff_T_64, _io_resp_eff_T_65)
wire _io_resp_eff_WIRE : UInt<1>
connect _io_resp_eff_WIRE, _io_resp_eff_T_66
node _io_resp_eff_T_67 = and(legal_address, _io_resp_eff_WIRE)
connect io.resp.eff, _io_resp_eff_T_67 | module PMAChecker_12( // @[PMA.scala:18:7]
input clock, // @[PMA.scala:18:7]
input reset, // @[PMA.scala:18:7]
input [39:0] io_paddr, // @[PMA.scala:19:14]
output io_resp_cacheable, // @[PMA.scala:19:14]
output io_resp_r, // @[PMA.scala:19:14]
output io_resp_w, // @[PMA.scala:19:14]
output io_resp_pp, // @[PMA.scala:19:14]
output io_resp_al, // @[PMA.scala:19:14]
output io_resp_aa, // @[PMA.scala:19:14]
output io_resp_x, // @[PMA.scala:19:14]
output io_resp_eff // @[PMA.scala:19:14]
);
wire [39:0] io_paddr_0 = io_paddr; // @[PMA.scala:18:7]
wire [40:0] _io_resp_r_T_2 = 41'h0; // @[Parameters.scala:137:46]
wire [40:0] _io_resp_r_T_3 = 41'h0; // @[Parameters.scala:137:46]
wire _io_resp_r_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire _io_resp_cacheable_T_34 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_w_T_53 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_pp_T_53 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_al_T_53 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_aa_T_53 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_x_T_77 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_eff_T_65 = 1'h0; // @[Mux.scala:30:73]
wire [39:0] _legal_address_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_cacheable_T = io_paddr_0; // @[PMA.scala:18:7]
wire _io_resp_cacheable_T_37; // @[PMA.scala:39:19]
wire [39:0] _io_resp_r_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_w_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_pp_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_al_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_aa_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_x_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_eff_T = io_paddr_0; // @[PMA.scala:18:7]
wire _io_resp_r_T_5; // @[PMA.scala:39:19]
wire _io_resp_w_T_55; // @[PMA.scala:39:19]
wire _io_resp_pp_T_55; // @[PMA.scala:39:19]
wire _io_resp_al_T_55; // @[PMA.scala:39:19]
wire _io_resp_aa_T_55; // @[PMA.scala:39:19]
wire _io_resp_x_T_79; // @[PMA.scala:39:19]
wire _io_resp_eff_T_67; // @[PMA.scala:39:19]
wire io_resp_cacheable_0; // @[PMA.scala:18:7]
wire io_resp_r_0; // @[PMA.scala:18:7]
wire io_resp_w_0; // @[PMA.scala:18:7]
wire io_resp_pp_0; // @[PMA.scala:18:7]
wire io_resp_al_0; // @[PMA.scala:18:7]
wire io_resp_aa_0; // @[PMA.scala:18:7]
wire io_resp_x_0; // @[PMA.scala:18:7]
wire io_resp_eff_0; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_1 = {1'h0, _legal_address_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_2 = _legal_address_T_1 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_3 = _legal_address_T_2; // @[Parameters.scala:137:46]
wire _legal_address_T_4 = _legal_address_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_0 = _legal_address_T_4; // @[Parameters.scala:612:40]
wire [39:0] _GEN = {io_paddr_0[39:13], io_paddr_0[12:0] ^ 13'h1000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_5; // @[Parameters.scala:137:31]
assign _legal_address_T_5 = _GEN; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_29; // @[Parameters.scala:137:31]
assign _io_resp_x_T_29 = _GEN; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_6 = {1'h0, _legal_address_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_7 = _legal_address_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_8 = _legal_address_T_7; // @[Parameters.scala:137:46]
wire _legal_address_T_9 = _legal_address_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_1 = _legal_address_T_9; // @[Parameters.scala:612:40]
wire [39:0] _GEN_0 = {io_paddr_0[39:14], io_paddr_0[13:0] ^ 14'h3000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_10; // @[Parameters.scala:137:31]
assign _legal_address_T_10 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_5; // @[Parameters.scala:137:31]
assign _io_resp_x_T_5 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_41; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_41 = _GEN_0; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_11 = {1'h0, _legal_address_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_12 = _legal_address_T_11 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_13 = _legal_address_T_12; // @[Parameters.scala:137:46]
wire _legal_address_T_14 = _legal_address_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_2 = _legal_address_T_14; // @[Parameters.scala:612:40]
wire [39:0] _GEN_1 = {io_paddr_0[39:17], io_paddr_0[16:0] ^ 17'h10000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_15; // @[Parameters.scala:137:31]
assign _legal_address_T_15 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_5; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_5 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_47; // @[Parameters.scala:137:31]
assign _io_resp_w_T_47 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_47; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_47 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_47; // @[Parameters.scala:137:31]
assign _io_resp_al_T_47 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_47; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_47 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_10; // @[Parameters.scala:137:31]
assign _io_resp_x_T_10 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_46; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_46 = _GEN_1; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_16 = {1'h0, _legal_address_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_17 = _legal_address_T_16 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_18 = _legal_address_T_17; // @[Parameters.scala:137:46]
wire _legal_address_T_19 = _legal_address_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_3 = _legal_address_T_19; // @[Parameters.scala:612:40]
wire [39:0] _GEN_2 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h20000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_20; // @[Parameters.scala:137:31]
assign _legal_address_T_20 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_10; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_10 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_34; // @[Parameters.scala:137:31]
assign _io_resp_x_T_34 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_5; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_21 = {1'h0, _legal_address_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_22 = _legal_address_T_21 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_23 = _legal_address_T_22; // @[Parameters.scala:137:46]
wire _legal_address_T_24 = _legal_address_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_4 = _legal_address_T_24; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_25 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h21000}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_26 = {1'h0, _legal_address_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_27 = _legal_address_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_28 = _legal_address_T_27; // @[Parameters.scala:137:46]
wire _legal_address_T_29 = _legal_address_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_5 = _legal_address_T_29; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_30 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h22000}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_31 = {1'h0, _legal_address_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_32 = _legal_address_T_31 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_33 = _legal_address_T_32; // @[Parameters.scala:137:46]
wire _legal_address_T_34 = _legal_address_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_6 = _legal_address_T_34; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_35 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h23000}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_36 = {1'h0, _legal_address_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_37 = _legal_address_T_36 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_38 = _legal_address_T_37; // @[Parameters.scala:137:46]
wire _legal_address_T_39 = _legal_address_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_7 = _legal_address_T_39; // @[Parameters.scala:612:40]
wire [39:0] _GEN_3 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h24000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_40; // @[Parameters.scala:137:31]
assign _legal_address_T_40 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_39; // @[Parameters.scala:137:31]
assign _io_resp_x_T_39 = _GEN_3; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_41 = {1'h0, _legal_address_T_40}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_42 = _legal_address_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_43 = _legal_address_T_42; // @[Parameters.scala:137:46]
wire _legal_address_T_44 = _legal_address_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_8 = _legal_address_T_44; // @[Parameters.scala:612:40]
wire [39:0] _GEN_4 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h100000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_45; // @[Parameters.scala:137:31]
assign _legal_address_T_45 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_5; // @[Parameters.scala:137:31]
assign _io_resp_w_T_5 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_5; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_5 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_5; // @[Parameters.scala:137:31]
assign _io_resp_al_T_5 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_5; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_5 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_44; // @[Parameters.scala:137:31]
assign _io_resp_x_T_44 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_10; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_10 = _GEN_4; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_46 = {1'h0, _legal_address_T_45}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_47 = _legal_address_T_46 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_48 = _legal_address_T_47; // @[Parameters.scala:137:46]
wire _legal_address_T_49 = _legal_address_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_9 = _legal_address_T_49; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_50 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h110000}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_51 = {1'h0, _legal_address_T_50}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_52 = _legal_address_T_51 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_53 = _legal_address_T_52; // @[Parameters.scala:137:46]
wire _legal_address_T_54 = _legal_address_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_10 = _legal_address_T_54; // @[Parameters.scala:612:40]
wire [39:0] _GEN_5 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_55; // @[Parameters.scala:137:31]
assign _legal_address_T_55 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_10; // @[Parameters.scala:137:31]
assign _io_resp_w_T_10 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_10; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_10 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_10; // @[Parameters.scala:137:31]
assign _io_resp_al_T_10 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_10; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_10 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_49; // @[Parameters.scala:137:31]
assign _io_resp_x_T_49 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_15; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_56 = {1'h0, _legal_address_T_55}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_57 = _legal_address_T_56 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_58 = _legal_address_T_57; // @[Parameters.scala:137:46]
wire _legal_address_T_59 = _legal_address_T_58 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_11 = _legal_address_T_59; // @[Parameters.scala:612:40]
wire [39:0] _GEN_6 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2010000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_60; // @[Parameters.scala:137:31]
assign _legal_address_T_60 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_15; // @[Parameters.scala:137:31]
assign _io_resp_w_T_15 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_15; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_15 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_15; // @[Parameters.scala:137:31]
assign _io_resp_al_T_15 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_15; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_15 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_54; // @[Parameters.scala:137:31]
assign _io_resp_x_T_54 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_20; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_20 = _GEN_6; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_61 = {1'h0, _legal_address_T_60}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_62 = _legal_address_T_61 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_63 = _legal_address_T_62; // @[Parameters.scala:137:46]
wire _legal_address_T_64 = _legal_address_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_12 = _legal_address_T_64; // @[Parameters.scala:612:40]
wire [39:0] _GEN_7 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h8000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_65; // @[Parameters.scala:137:31]
assign _legal_address_T_65 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_23; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_23 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_20; // @[Parameters.scala:137:31]
assign _io_resp_w_T_20 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_20; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_20 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_20; // @[Parameters.scala:137:31]
assign _io_resp_al_T_20 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_20; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_20 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_15; // @[Parameters.scala:137:31]
assign _io_resp_x_T_15 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_51; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_51 = _GEN_7; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_66 = {1'h0, _legal_address_T_65}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_67 = _legal_address_T_66 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_68 = _legal_address_T_67; // @[Parameters.scala:137:46]
wire _legal_address_T_69 = _legal_address_T_68 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_13 = _legal_address_T_69; // @[Parameters.scala:612:40]
wire [39:0] _GEN_8 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'hC000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_70; // @[Parameters.scala:137:31]
assign _legal_address_T_70 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_15; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_15 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_25; // @[Parameters.scala:137:31]
assign _io_resp_w_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_25; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_25; // @[Parameters.scala:137:31]
assign _io_resp_al_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_25; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_59; // @[Parameters.scala:137:31]
assign _io_resp_x_T_59 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_25; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_71 = {1'h0, _legal_address_T_70}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_72 = _legal_address_T_71 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_73 = _legal_address_T_72; // @[Parameters.scala:137:46]
wire _legal_address_T_74 = _legal_address_T_73 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_14 = _legal_address_T_74; // @[Parameters.scala:612:40]
wire [39:0] _GEN_9 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10020000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_75; // @[Parameters.scala:137:31]
assign _legal_address_T_75 = _GEN_9; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_30; // @[Parameters.scala:137:31]
assign _io_resp_w_T_30 = _GEN_9; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_30; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_30 = _GEN_9; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_30; // @[Parameters.scala:137:31]
assign _io_resp_al_T_30 = _GEN_9; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_30; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_30 = _GEN_9; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_64; // @[Parameters.scala:137:31]
assign _io_resp_x_T_64 = _GEN_9; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_30; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_30 = _GEN_9; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_76 = {1'h0, _legal_address_T_75}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_77 = _legal_address_T_76 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_78 = _legal_address_T_77; // @[Parameters.scala:137:46]
wire _legal_address_T_79 = _legal_address_T_78 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_15 = _legal_address_T_79; // @[Parameters.scala:612:40]
wire [39:0] _GEN_10 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h80000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_80; // @[Parameters.scala:137:31]
assign _legal_address_T_80 = _GEN_10; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_28; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_28 = _GEN_10; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_35; // @[Parameters.scala:137:31]
assign _io_resp_w_T_35 = _GEN_10; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_35; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_35 = _GEN_10; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_35; // @[Parameters.scala:137:31]
assign _io_resp_al_T_35 = _GEN_10; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_35; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_35 = _GEN_10; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_20; // @[Parameters.scala:137:31]
assign _io_resp_x_T_20 = _GEN_10; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_56; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_56 = _GEN_10; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_81 = {1'h0, _legal_address_T_80}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_82 = _legal_address_T_81 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_83 = _legal_address_T_82; // @[Parameters.scala:137:46]
wire _legal_address_T_84 = _legal_address_T_83 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_16 = _legal_address_T_84; // @[Parameters.scala:612:40]
wire _legal_address_T_85 = _legal_address_WIRE_0 | _legal_address_WIRE_1; // @[Parameters.scala:612:40]
wire _legal_address_T_86 = _legal_address_T_85 | _legal_address_WIRE_2; // @[Parameters.scala:612:40]
wire _legal_address_T_87 = _legal_address_T_86 | _legal_address_WIRE_3; // @[Parameters.scala:612:40]
wire _legal_address_T_88 = _legal_address_T_87 | _legal_address_WIRE_4; // @[Parameters.scala:612:40]
wire _legal_address_T_89 = _legal_address_T_88 | _legal_address_WIRE_5; // @[Parameters.scala:612:40]
wire _legal_address_T_90 = _legal_address_T_89 | _legal_address_WIRE_6; // @[Parameters.scala:612:40]
wire _legal_address_T_91 = _legal_address_T_90 | _legal_address_WIRE_7; // @[Parameters.scala:612:40]
wire _legal_address_T_92 = _legal_address_T_91 | _legal_address_WIRE_8; // @[Parameters.scala:612:40]
wire _legal_address_T_93 = _legal_address_T_92 | _legal_address_WIRE_9; // @[Parameters.scala:612:40]
wire _legal_address_T_94 = _legal_address_T_93 | _legal_address_WIRE_10; // @[Parameters.scala:612:40]
wire _legal_address_T_95 = _legal_address_T_94 | _legal_address_WIRE_11; // @[Parameters.scala:612:40]
wire _legal_address_T_96 = _legal_address_T_95 | _legal_address_WIRE_12; // @[Parameters.scala:612:40]
wire _legal_address_T_97 = _legal_address_T_96 | _legal_address_WIRE_13; // @[Parameters.scala:612:40]
wire _legal_address_T_98 = _legal_address_T_97 | _legal_address_WIRE_14; // @[Parameters.scala:612:40]
wire _legal_address_T_99 = _legal_address_T_98 | _legal_address_WIRE_15; // @[Parameters.scala:612:40]
wire legal_address = _legal_address_T_99 | _legal_address_WIRE_16; // @[Parameters.scala:612:40]
assign _io_resp_r_T_5 = legal_address; // @[PMA.scala:36:58, :39:19]
wire [40:0] _io_resp_cacheable_T_1 = {1'h0, _io_resp_cacheable_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_2 = _io_resp_cacheable_T_1 & 41'h8C020000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_3 = _io_resp_cacheable_T_2; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_4 = _io_resp_cacheable_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_cacheable_T_6 = {1'h0, _io_resp_cacheable_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_7 = _io_resp_cacheable_T_6 & 41'h8C031000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_8 = _io_resp_cacheable_T_7; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_9 = _io_resp_cacheable_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_cacheable_T_11 = {1'h0, _io_resp_cacheable_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_12 = _io_resp_cacheable_T_11 & 41'h8C030000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_13 = _io_resp_cacheable_T_12; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_14 = _io_resp_cacheable_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_cacheable_T_16 = {1'h0, _io_resp_cacheable_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_17 = _io_resp_cacheable_T_16 & 41'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_18 = _io_resp_cacheable_T_17; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_19 = _io_resp_cacheable_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_cacheable_T_20 = _io_resp_cacheable_T_4 | _io_resp_cacheable_T_9; // @[Parameters.scala:629:89]
wire _io_resp_cacheable_T_21 = _io_resp_cacheable_T_20 | _io_resp_cacheable_T_14; // @[Parameters.scala:629:89]
wire _io_resp_cacheable_T_22 = _io_resp_cacheable_T_21 | _io_resp_cacheable_T_19; // @[Parameters.scala:629:89]
wire [40:0] _io_resp_cacheable_T_24 = {1'h0, _io_resp_cacheable_T_23}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_25 = _io_resp_cacheable_T_24 & 41'h8C030000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_26 = _io_resp_cacheable_T_25; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_27 = _io_resp_cacheable_T_26 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_cacheable_T_29 = {1'h0, _io_resp_cacheable_T_28}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_30 = _io_resp_cacheable_T_29 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_31 = _io_resp_cacheable_T_30; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_32 = _io_resp_cacheable_T_31 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_cacheable_T_33 = _io_resp_cacheable_T_27 | _io_resp_cacheable_T_32; // @[Parameters.scala:629:89]
wire _io_resp_cacheable_T_35 = _io_resp_cacheable_T_33; // @[Mux.scala:30:73]
wire _io_resp_cacheable_T_36 = _io_resp_cacheable_T_35; // @[Mux.scala:30:73]
wire _io_resp_cacheable_WIRE = _io_resp_cacheable_T_36; // @[Mux.scala:30:73]
assign _io_resp_cacheable_T_37 = legal_address & _io_resp_cacheable_WIRE; // @[Mux.scala:30:73]
assign io_resp_cacheable_0 = _io_resp_cacheable_T_37; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_r_T_1 = {1'h0, _io_resp_r_T}; // @[Parameters.scala:137:{31,41}]
assign io_resp_r_0 = _io_resp_r_T_5; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_w_T_1 = {1'h0, _io_resp_w_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_2 = _io_resp_w_T_1 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_3 = _io_resp_w_T_2; // @[Parameters.scala:137:46]
wire _io_resp_w_T_4 = _io_resp_w_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_6 = {1'h0, _io_resp_w_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_7 = _io_resp_w_T_6 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_8 = _io_resp_w_T_7; // @[Parameters.scala:137:46]
wire _io_resp_w_T_9 = _io_resp_w_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_11 = {1'h0, _io_resp_w_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_12 = _io_resp_w_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_13 = _io_resp_w_T_12; // @[Parameters.scala:137:46]
wire _io_resp_w_T_14 = _io_resp_w_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_16 = {1'h0, _io_resp_w_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_17 = _io_resp_w_T_16 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_18 = _io_resp_w_T_17; // @[Parameters.scala:137:46]
wire _io_resp_w_T_19 = _io_resp_w_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_21 = {1'h0, _io_resp_w_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_22 = _io_resp_w_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_23 = _io_resp_w_T_22; // @[Parameters.scala:137:46]
wire _io_resp_w_T_24 = _io_resp_w_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_26 = {1'h0, _io_resp_w_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_27 = _io_resp_w_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_28 = _io_resp_w_T_27; // @[Parameters.scala:137:46]
wire _io_resp_w_T_29 = _io_resp_w_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_31 = {1'h0, _io_resp_w_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_32 = _io_resp_w_T_31 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_33 = _io_resp_w_T_32; // @[Parameters.scala:137:46]
wire _io_resp_w_T_34 = _io_resp_w_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_36 = {1'h0, _io_resp_w_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_37 = _io_resp_w_T_36 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_38 = _io_resp_w_T_37; // @[Parameters.scala:137:46]
wire _io_resp_w_T_39 = _io_resp_w_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_w_T_40 = _io_resp_w_T_4 | _io_resp_w_T_9; // @[Parameters.scala:629:89]
wire _io_resp_w_T_41 = _io_resp_w_T_40 | _io_resp_w_T_14; // @[Parameters.scala:629:89]
wire _io_resp_w_T_42 = _io_resp_w_T_41 | _io_resp_w_T_19; // @[Parameters.scala:629:89]
wire _io_resp_w_T_43 = _io_resp_w_T_42 | _io_resp_w_T_24; // @[Parameters.scala:629:89]
wire _io_resp_w_T_44 = _io_resp_w_T_43 | _io_resp_w_T_29; // @[Parameters.scala:629:89]
wire _io_resp_w_T_45 = _io_resp_w_T_44 | _io_resp_w_T_34; // @[Parameters.scala:629:89]
wire _io_resp_w_T_46 = _io_resp_w_T_45 | _io_resp_w_T_39; // @[Parameters.scala:629:89]
wire _io_resp_w_T_52 = _io_resp_w_T_46; // @[Mux.scala:30:73]
wire [40:0] _io_resp_w_T_48 = {1'h0, _io_resp_w_T_47}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_49 = _io_resp_w_T_48 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_50 = _io_resp_w_T_49; // @[Parameters.scala:137:46]
wire _io_resp_w_T_51 = _io_resp_w_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_w_T_54 = _io_resp_w_T_52; // @[Mux.scala:30:73]
wire _io_resp_w_WIRE = _io_resp_w_T_54; // @[Mux.scala:30:73]
assign _io_resp_w_T_55 = legal_address & _io_resp_w_WIRE; // @[Mux.scala:30:73]
assign io_resp_w_0 = _io_resp_w_T_55; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_pp_T_1 = {1'h0, _io_resp_pp_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_2 = _io_resp_pp_T_1 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_3 = _io_resp_pp_T_2; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_4 = _io_resp_pp_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_6 = {1'h0, _io_resp_pp_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_7 = _io_resp_pp_T_6 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_8 = _io_resp_pp_T_7; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_9 = _io_resp_pp_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_11 = {1'h0, _io_resp_pp_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_12 = _io_resp_pp_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_13 = _io_resp_pp_T_12; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_14 = _io_resp_pp_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_16 = {1'h0, _io_resp_pp_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_17 = _io_resp_pp_T_16 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_18 = _io_resp_pp_T_17; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_19 = _io_resp_pp_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_21 = {1'h0, _io_resp_pp_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_22 = _io_resp_pp_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_23 = _io_resp_pp_T_22; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_24 = _io_resp_pp_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_26 = {1'h0, _io_resp_pp_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_27 = _io_resp_pp_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_28 = _io_resp_pp_T_27; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_29 = _io_resp_pp_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_31 = {1'h0, _io_resp_pp_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_32 = _io_resp_pp_T_31 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_33 = _io_resp_pp_T_32; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_34 = _io_resp_pp_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_36 = {1'h0, _io_resp_pp_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_37 = _io_resp_pp_T_36 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_38 = _io_resp_pp_T_37; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_39 = _io_resp_pp_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_pp_T_40 = _io_resp_pp_T_4 | _io_resp_pp_T_9; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_41 = _io_resp_pp_T_40 | _io_resp_pp_T_14; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_42 = _io_resp_pp_T_41 | _io_resp_pp_T_19; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_43 = _io_resp_pp_T_42 | _io_resp_pp_T_24; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_44 = _io_resp_pp_T_43 | _io_resp_pp_T_29; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_45 = _io_resp_pp_T_44 | _io_resp_pp_T_34; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_46 = _io_resp_pp_T_45 | _io_resp_pp_T_39; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_52 = _io_resp_pp_T_46; // @[Mux.scala:30:73]
wire [40:0] _io_resp_pp_T_48 = {1'h0, _io_resp_pp_T_47}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_49 = _io_resp_pp_T_48 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_50 = _io_resp_pp_T_49; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_51 = _io_resp_pp_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_pp_T_54 = _io_resp_pp_T_52; // @[Mux.scala:30:73]
wire _io_resp_pp_WIRE = _io_resp_pp_T_54; // @[Mux.scala:30:73]
assign _io_resp_pp_T_55 = legal_address & _io_resp_pp_WIRE; // @[Mux.scala:30:73]
assign io_resp_pp_0 = _io_resp_pp_T_55; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_al_T_1 = {1'h0, _io_resp_al_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_2 = _io_resp_al_T_1 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_3 = _io_resp_al_T_2; // @[Parameters.scala:137:46]
wire _io_resp_al_T_4 = _io_resp_al_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_6 = {1'h0, _io_resp_al_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_7 = _io_resp_al_T_6 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_8 = _io_resp_al_T_7; // @[Parameters.scala:137:46]
wire _io_resp_al_T_9 = _io_resp_al_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_11 = {1'h0, _io_resp_al_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_12 = _io_resp_al_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_13 = _io_resp_al_T_12; // @[Parameters.scala:137:46]
wire _io_resp_al_T_14 = _io_resp_al_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_16 = {1'h0, _io_resp_al_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_17 = _io_resp_al_T_16 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_18 = _io_resp_al_T_17; // @[Parameters.scala:137:46]
wire _io_resp_al_T_19 = _io_resp_al_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_21 = {1'h0, _io_resp_al_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_22 = _io_resp_al_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_23 = _io_resp_al_T_22; // @[Parameters.scala:137:46]
wire _io_resp_al_T_24 = _io_resp_al_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_26 = {1'h0, _io_resp_al_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_27 = _io_resp_al_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_28 = _io_resp_al_T_27; // @[Parameters.scala:137:46]
wire _io_resp_al_T_29 = _io_resp_al_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_31 = {1'h0, _io_resp_al_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_32 = _io_resp_al_T_31 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_33 = _io_resp_al_T_32; // @[Parameters.scala:137:46]
wire _io_resp_al_T_34 = _io_resp_al_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_36 = {1'h0, _io_resp_al_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_37 = _io_resp_al_T_36 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_38 = _io_resp_al_T_37; // @[Parameters.scala:137:46]
wire _io_resp_al_T_39 = _io_resp_al_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_al_T_40 = _io_resp_al_T_4 | _io_resp_al_T_9; // @[Parameters.scala:629:89]
wire _io_resp_al_T_41 = _io_resp_al_T_40 | _io_resp_al_T_14; // @[Parameters.scala:629:89]
wire _io_resp_al_T_42 = _io_resp_al_T_41 | _io_resp_al_T_19; // @[Parameters.scala:629:89]
wire _io_resp_al_T_43 = _io_resp_al_T_42 | _io_resp_al_T_24; // @[Parameters.scala:629:89]
wire _io_resp_al_T_44 = _io_resp_al_T_43 | _io_resp_al_T_29; // @[Parameters.scala:629:89]
wire _io_resp_al_T_45 = _io_resp_al_T_44 | _io_resp_al_T_34; // @[Parameters.scala:629:89]
wire _io_resp_al_T_46 = _io_resp_al_T_45 | _io_resp_al_T_39; // @[Parameters.scala:629:89]
wire _io_resp_al_T_52 = _io_resp_al_T_46; // @[Mux.scala:30:73]
wire [40:0] _io_resp_al_T_48 = {1'h0, _io_resp_al_T_47}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_49 = _io_resp_al_T_48 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_50 = _io_resp_al_T_49; // @[Parameters.scala:137:46]
wire _io_resp_al_T_51 = _io_resp_al_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_al_T_54 = _io_resp_al_T_52; // @[Mux.scala:30:73]
wire _io_resp_al_WIRE = _io_resp_al_T_54; // @[Mux.scala:30:73]
assign _io_resp_al_T_55 = legal_address & _io_resp_al_WIRE; // @[Mux.scala:30:73]
assign io_resp_al_0 = _io_resp_al_T_55; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_aa_T_1 = {1'h0, _io_resp_aa_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_2 = _io_resp_aa_T_1 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_3 = _io_resp_aa_T_2; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_4 = _io_resp_aa_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_6 = {1'h0, _io_resp_aa_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_7 = _io_resp_aa_T_6 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_8 = _io_resp_aa_T_7; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_9 = _io_resp_aa_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_11 = {1'h0, _io_resp_aa_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_12 = _io_resp_aa_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_13 = _io_resp_aa_T_12; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_14 = _io_resp_aa_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_16 = {1'h0, _io_resp_aa_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_17 = _io_resp_aa_T_16 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_18 = _io_resp_aa_T_17; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_19 = _io_resp_aa_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_21 = {1'h0, _io_resp_aa_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_22 = _io_resp_aa_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_23 = _io_resp_aa_T_22; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_24 = _io_resp_aa_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_26 = {1'h0, _io_resp_aa_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_27 = _io_resp_aa_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_28 = _io_resp_aa_T_27; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_29 = _io_resp_aa_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_31 = {1'h0, _io_resp_aa_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_32 = _io_resp_aa_T_31 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_33 = _io_resp_aa_T_32; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_34 = _io_resp_aa_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_36 = {1'h0, _io_resp_aa_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_37 = _io_resp_aa_T_36 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_38 = _io_resp_aa_T_37; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_39 = _io_resp_aa_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_aa_T_40 = _io_resp_aa_T_4 | _io_resp_aa_T_9; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_41 = _io_resp_aa_T_40 | _io_resp_aa_T_14; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_42 = _io_resp_aa_T_41 | _io_resp_aa_T_19; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_43 = _io_resp_aa_T_42 | _io_resp_aa_T_24; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_44 = _io_resp_aa_T_43 | _io_resp_aa_T_29; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_45 = _io_resp_aa_T_44 | _io_resp_aa_T_34; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_46 = _io_resp_aa_T_45 | _io_resp_aa_T_39; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_52 = _io_resp_aa_T_46; // @[Mux.scala:30:73]
wire [40:0] _io_resp_aa_T_48 = {1'h0, _io_resp_aa_T_47}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_49 = _io_resp_aa_T_48 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_50 = _io_resp_aa_T_49; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_51 = _io_resp_aa_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_aa_T_54 = _io_resp_aa_T_52; // @[Mux.scala:30:73]
wire _io_resp_aa_WIRE = _io_resp_aa_T_54; // @[Mux.scala:30:73]
assign _io_resp_aa_T_55 = legal_address & _io_resp_aa_WIRE; // @[Mux.scala:30:73]
assign io_resp_aa_0 = _io_resp_aa_T_55; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_x_T_1 = {1'h0, _io_resp_x_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_2 = _io_resp_x_T_1 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_3 = _io_resp_x_T_2; // @[Parameters.scala:137:46]
wire _io_resp_x_T_4 = _io_resp_x_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_6 = {1'h0, _io_resp_x_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_7 = _io_resp_x_T_6 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_8 = _io_resp_x_T_7; // @[Parameters.scala:137:46]
wire _io_resp_x_T_9 = _io_resp_x_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_11 = {1'h0, _io_resp_x_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_12 = _io_resp_x_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_13 = _io_resp_x_T_12; // @[Parameters.scala:137:46]
wire _io_resp_x_T_14 = _io_resp_x_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_16 = {1'h0, _io_resp_x_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_17 = _io_resp_x_T_16 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_18 = _io_resp_x_T_17; // @[Parameters.scala:137:46]
wire _io_resp_x_T_19 = _io_resp_x_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_21 = {1'h0, _io_resp_x_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_22 = _io_resp_x_T_21 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_23 = _io_resp_x_T_22; // @[Parameters.scala:137:46]
wire _io_resp_x_T_24 = _io_resp_x_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_x_T_25 = _io_resp_x_T_4 | _io_resp_x_T_9; // @[Parameters.scala:629:89]
wire _io_resp_x_T_26 = _io_resp_x_T_25 | _io_resp_x_T_14; // @[Parameters.scala:629:89]
wire _io_resp_x_T_27 = _io_resp_x_T_26 | _io_resp_x_T_19; // @[Parameters.scala:629:89]
wire _io_resp_x_T_28 = _io_resp_x_T_27 | _io_resp_x_T_24; // @[Parameters.scala:629:89]
wire _io_resp_x_T_76 = _io_resp_x_T_28; // @[Mux.scala:30:73]
wire [40:0] _io_resp_x_T_30 = {1'h0, _io_resp_x_T_29}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_31 = _io_resp_x_T_30 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_32 = _io_resp_x_T_31; // @[Parameters.scala:137:46]
wire _io_resp_x_T_33 = _io_resp_x_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_35 = {1'h0, _io_resp_x_T_34}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_36 = _io_resp_x_T_35 & 41'hFFFFC000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_37 = _io_resp_x_T_36; // @[Parameters.scala:137:46]
wire _io_resp_x_T_38 = _io_resp_x_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_40 = {1'h0, _io_resp_x_T_39}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_41 = _io_resp_x_T_40 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_42 = _io_resp_x_T_41; // @[Parameters.scala:137:46]
wire _io_resp_x_T_43 = _io_resp_x_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_45 = {1'h0, _io_resp_x_T_44}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_46 = _io_resp_x_T_45 & 41'hFFFEF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_47 = _io_resp_x_T_46; // @[Parameters.scala:137:46]
wire _io_resp_x_T_48 = _io_resp_x_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_50 = {1'h0, _io_resp_x_T_49}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_51 = _io_resp_x_T_50 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_52 = _io_resp_x_T_51; // @[Parameters.scala:137:46]
wire _io_resp_x_T_53 = _io_resp_x_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_55 = {1'h0, _io_resp_x_T_54}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_56 = _io_resp_x_T_55 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_57 = _io_resp_x_T_56; // @[Parameters.scala:137:46]
wire _io_resp_x_T_58 = _io_resp_x_T_57 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_60 = {1'h0, _io_resp_x_T_59}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_61 = _io_resp_x_T_60 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_62 = _io_resp_x_T_61; // @[Parameters.scala:137:46]
wire _io_resp_x_T_63 = _io_resp_x_T_62 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_65 = {1'h0, _io_resp_x_T_64}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_66 = _io_resp_x_T_65 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_67 = _io_resp_x_T_66; // @[Parameters.scala:137:46]
wire _io_resp_x_T_68 = _io_resp_x_T_67 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_x_T_69 = _io_resp_x_T_33 | _io_resp_x_T_38; // @[Parameters.scala:629:89]
wire _io_resp_x_T_70 = _io_resp_x_T_69 | _io_resp_x_T_43; // @[Parameters.scala:629:89]
wire _io_resp_x_T_71 = _io_resp_x_T_70 | _io_resp_x_T_48; // @[Parameters.scala:629:89]
wire _io_resp_x_T_72 = _io_resp_x_T_71 | _io_resp_x_T_53; // @[Parameters.scala:629:89]
wire _io_resp_x_T_73 = _io_resp_x_T_72 | _io_resp_x_T_58; // @[Parameters.scala:629:89]
wire _io_resp_x_T_74 = _io_resp_x_T_73 | _io_resp_x_T_63; // @[Parameters.scala:629:89]
wire _io_resp_x_T_75 = _io_resp_x_T_74 | _io_resp_x_T_68; // @[Parameters.scala:629:89]
wire _io_resp_x_T_78 = _io_resp_x_T_76; // @[Mux.scala:30:73]
wire _io_resp_x_WIRE = _io_resp_x_T_78; // @[Mux.scala:30:73]
assign _io_resp_x_T_79 = legal_address & _io_resp_x_WIRE; // @[Mux.scala:30:73]
assign io_resp_x_0 = _io_resp_x_T_79; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_eff_T_1 = {1'h0, _io_resp_eff_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_2 = _io_resp_eff_T_1 & 41'hFFFFA000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_3 = _io_resp_eff_T_2; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_4 = _io_resp_eff_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_6 = {1'h0, _io_resp_eff_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_7 = _io_resp_eff_T_6 & 41'hFFFF8000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_8 = _io_resp_eff_T_7; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_9 = _io_resp_eff_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_11 = {1'h0, _io_resp_eff_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_12 = _io_resp_eff_T_11 & 41'hFFFEB000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_13 = _io_resp_eff_T_12; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_14 = _io_resp_eff_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_16 = {1'h0, _io_resp_eff_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_17 = _io_resp_eff_T_16 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_18 = _io_resp_eff_T_17; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_19 = _io_resp_eff_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_21 = {1'h0, _io_resp_eff_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_22 = _io_resp_eff_T_21 & 41'hFFFFB000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_23 = _io_resp_eff_T_22; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_24 = _io_resp_eff_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_26 = {1'h0, _io_resp_eff_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_27 = _io_resp_eff_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_28 = _io_resp_eff_T_27; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_29 = _io_resp_eff_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_31 = {1'h0, _io_resp_eff_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_32 = _io_resp_eff_T_31 & 41'hFFFFB000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_33 = _io_resp_eff_T_32; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_34 = _io_resp_eff_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_eff_T_35 = _io_resp_eff_T_4 | _io_resp_eff_T_9; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_36 = _io_resp_eff_T_35 | _io_resp_eff_T_14; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_37 = _io_resp_eff_T_36 | _io_resp_eff_T_19; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_38 = _io_resp_eff_T_37 | _io_resp_eff_T_24; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_39 = _io_resp_eff_T_38 | _io_resp_eff_T_29; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_40 = _io_resp_eff_T_39 | _io_resp_eff_T_34; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_64 = _io_resp_eff_T_40; // @[Mux.scala:30:73]
wire [40:0] _io_resp_eff_T_42 = {1'h0, _io_resp_eff_T_41}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_43 = _io_resp_eff_T_42 & 41'hFFFFB000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_44 = _io_resp_eff_T_43; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_45 = _io_resp_eff_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_47 = {1'h0, _io_resp_eff_T_46}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_48 = _io_resp_eff_T_47 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_49 = _io_resp_eff_T_48; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_50 = _io_resp_eff_T_49 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_52 = {1'h0, _io_resp_eff_T_51}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_53 = _io_resp_eff_T_52 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_54 = _io_resp_eff_T_53; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_55 = _io_resp_eff_T_54 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_57 = {1'h0, _io_resp_eff_T_56}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_58 = _io_resp_eff_T_57 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_59 = _io_resp_eff_T_58; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_60 = _io_resp_eff_T_59 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_eff_T_61 = _io_resp_eff_T_45 | _io_resp_eff_T_50; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_62 = _io_resp_eff_T_61 | _io_resp_eff_T_55; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_63 = _io_resp_eff_T_62 | _io_resp_eff_T_60; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_66 = _io_resp_eff_T_64; // @[Mux.scala:30:73]
wire _io_resp_eff_WIRE = _io_resp_eff_T_66; // @[Mux.scala:30:73]
assign _io_resp_eff_T_67 = legal_address & _io_resp_eff_WIRE; // @[Mux.scala:30:73]
assign io_resp_eff_0 = _io_resp_eff_T_67; // @[PMA.scala:18:7, :39:19]
assign io_resp_cacheable = io_resp_cacheable_0; // @[PMA.scala:18:7]
assign io_resp_r = io_resp_r_0; // @[PMA.scala:18:7]
assign io_resp_w = io_resp_w_0; // @[PMA.scala:18:7]
assign io_resp_pp = io_resp_pp_0; // @[PMA.scala:18:7]
assign io_resp_al = io_resp_al_0; // @[PMA.scala:18:7]
assign io_resp_aa = io_resp_aa_0; // @[PMA.scala:18:7]
assign io_resp_x = io_resp_x_0; // @[PMA.scala:18:7]
assign io_resp_eff = io_resp_eff_0; // @[PMA.scala:18:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module PMAChecker_8 :
input clock : Clock
input reset : Reset
output io : { flip paddr : UInt, resp : { cacheable : UInt<1>, r : UInt<1>, w : UInt<1>, pp : UInt<1>, al : UInt<1>, aa : UInt<1>, x : UInt<1>, eff : UInt<1>}}
node _legal_address_T = xor(io.paddr, UInt<1>(0h0))
node _legal_address_T_1 = cvt(_legal_address_T)
node _legal_address_T_2 = and(_legal_address_T_1, asSInt(UInt<13>(0h1000)))
node _legal_address_T_3 = asSInt(_legal_address_T_2)
node _legal_address_T_4 = eq(_legal_address_T_3, asSInt(UInt<1>(0h0)))
node _legal_address_T_5 = xor(io.paddr, UInt<13>(0h1000))
node _legal_address_T_6 = cvt(_legal_address_T_5)
node _legal_address_T_7 = and(_legal_address_T_6, asSInt(UInt<13>(0h1000)))
node _legal_address_T_8 = asSInt(_legal_address_T_7)
node _legal_address_T_9 = eq(_legal_address_T_8, asSInt(UInt<1>(0h0)))
node _legal_address_T_10 = xor(io.paddr, UInt<14>(0h3000))
node _legal_address_T_11 = cvt(_legal_address_T_10)
node _legal_address_T_12 = and(_legal_address_T_11, asSInt(UInt<13>(0h1000)))
node _legal_address_T_13 = asSInt(_legal_address_T_12)
node _legal_address_T_14 = eq(_legal_address_T_13, asSInt(UInt<1>(0h0)))
node _legal_address_T_15 = xor(io.paddr, UInt<17>(0h10000))
node _legal_address_T_16 = cvt(_legal_address_T_15)
node _legal_address_T_17 = and(_legal_address_T_16, asSInt(UInt<17>(0h10000)))
node _legal_address_T_18 = asSInt(_legal_address_T_17)
node _legal_address_T_19 = eq(_legal_address_T_18, asSInt(UInt<1>(0h0)))
node _legal_address_T_20 = xor(io.paddr, UInt<18>(0h20000))
node _legal_address_T_21 = cvt(_legal_address_T_20)
node _legal_address_T_22 = and(_legal_address_T_21, asSInt(UInt<13>(0h1000)))
node _legal_address_T_23 = asSInt(_legal_address_T_22)
node _legal_address_T_24 = eq(_legal_address_T_23, asSInt(UInt<1>(0h0)))
node _legal_address_T_25 = xor(io.paddr, UInt<18>(0h21000))
node _legal_address_T_26 = cvt(_legal_address_T_25)
node _legal_address_T_27 = and(_legal_address_T_26, asSInt(UInt<13>(0h1000)))
node _legal_address_T_28 = asSInt(_legal_address_T_27)
node _legal_address_T_29 = eq(_legal_address_T_28, asSInt(UInt<1>(0h0)))
node _legal_address_T_30 = xor(io.paddr, UInt<18>(0h22000))
node _legal_address_T_31 = cvt(_legal_address_T_30)
node _legal_address_T_32 = and(_legal_address_T_31, asSInt(UInt<13>(0h1000)))
node _legal_address_T_33 = asSInt(_legal_address_T_32)
node _legal_address_T_34 = eq(_legal_address_T_33, asSInt(UInt<1>(0h0)))
node _legal_address_T_35 = xor(io.paddr, UInt<18>(0h23000))
node _legal_address_T_36 = cvt(_legal_address_T_35)
node _legal_address_T_37 = and(_legal_address_T_36, asSInt(UInt<13>(0h1000)))
node _legal_address_T_38 = asSInt(_legal_address_T_37)
node _legal_address_T_39 = eq(_legal_address_T_38, asSInt(UInt<1>(0h0)))
node _legal_address_T_40 = xor(io.paddr, UInt<18>(0h24000))
node _legal_address_T_41 = cvt(_legal_address_T_40)
node _legal_address_T_42 = and(_legal_address_T_41, asSInt(UInt<13>(0h1000)))
node _legal_address_T_43 = asSInt(_legal_address_T_42)
node _legal_address_T_44 = eq(_legal_address_T_43, asSInt(UInt<1>(0h0)))
node _legal_address_T_45 = xor(io.paddr, UInt<21>(0h100000))
node _legal_address_T_46 = cvt(_legal_address_T_45)
node _legal_address_T_47 = and(_legal_address_T_46, asSInt(UInt<13>(0h1000)))
node _legal_address_T_48 = asSInt(_legal_address_T_47)
node _legal_address_T_49 = eq(_legal_address_T_48, asSInt(UInt<1>(0h0)))
node _legal_address_T_50 = xor(io.paddr, UInt<21>(0h110000))
node _legal_address_T_51 = cvt(_legal_address_T_50)
node _legal_address_T_52 = and(_legal_address_T_51, asSInt(UInt<13>(0h1000)))
node _legal_address_T_53 = asSInt(_legal_address_T_52)
node _legal_address_T_54 = eq(_legal_address_T_53, asSInt(UInt<1>(0h0)))
node _legal_address_T_55 = xor(io.paddr, UInt<26>(0h2000000))
node _legal_address_T_56 = cvt(_legal_address_T_55)
node _legal_address_T_57 = and(_legal_address_T_56, asSInt(UInt<17>(0h10000)))
node _legal_address_T_58 = asSInt(_legal_address_T_57)
node _legal_address_T_59 = eq(_legal_address_T_58, asSInt(UInt<1>(0h0)))
node _legal_address_T_60 = xor(io.paddr, UInt<26>(0h2010000))
node _legal_address_T_61 = cvt(_legal_address_T_60)
node _legal_address_T_62 = and(_legal_address_T_61, asSInt(UInt<13>(0h1000)))
node _legal_address_T_63 = asSInt(_legal_address_T_62)
node _legal_address_T_64 = eq(_legal_address_T_63, asSInt(UInt<1>(0h0)))
node _legal_address_T_65 = xor(io.paddr, UInt<28>(0h8000000))
node _legal_address_T_66 = cvt(_legal_address_T_65)
node _legal_address_T_67 = and(_legal_address_T_66, asSInt(UInt<17>(0h10000)))
node _legal_address_T_68 = asSInt(_legal_address_T_67)
node _legal_address_T_69 = eq(_legal_address_T_68, asSInt(UInt<1>(0h0)))
node _legal_address_T_70 = xor(io.paddr, UInt<28>(0hc000000))
node _legal_address_T_71 = cvt(_legal_address_T_70)
node _legal_address_T_72 = and(_legal_address_T_71, asSInt(UInt<27>(0h4000000)))
node _legal_address_T_73 = asSInt(_legal_address_T_72)
node _legal_address_T_74 = eq(_legal_address_T_73, asSInt(UInt<1>(0h0)))
node _legal_address_T_75 = xor(io.paddr, UInt<29>(0h10020000))
node _legal_address_T_76 = cvt(_legal_address_T_75)
node _legal_address_T_77 = and(_legal_address_T_76, asSInt(UInt<13>(0h1000)))
node _legal_address_T_78 = asSInt(_legal_address_T_77)
node _legal_address_T_79 = eq(_legal_address_T_78, asSInt(UInt<1>(0h0)))
node _legal_address_T_80 = xor(io.paddr, UInt<32>(0h80000000))
node _legal_address_T_81 = cvt(_legal_address_T_80)
node _legal_address_T_82 = and(_legal_address_T_81, asSInt(UInt<29>(0h10000000)))
node _legal_address_T_83 = asSInt(_legal_address_T_82)
node _legal_address_T_84 = eq(_legal_address_T_83, asSInt(UInt<1>(0h0)))
wire _legal_address_WIRE : UInt<1>[17]
connect _legal_address_WIRE[0], _legal_address_T_4
connect _legal_address_WIRE[1], _legal_address_T_9
connect _legal_address_WIRE[2], _legal_address_T_14
connect _legal_address_WIRE[3], _legal_address_T_19
connect _legal_address_WIRE[4], _legal_address_T_24
connect _legal_address_WIRE[5], _legal_address_T_29
connect _legal_address_WIRE[6], _legal_address_T_34
connect _legal_address_WIRE[7], _legal_address_T_39
connect _legal_address_WIRE[8], _legal_address_T_44
connect _legal_address_WIRE[9], _legal_address_T_49
connect _legal_address_WIRE[10], _legal_address_T_54
connect _legal_address_WIRE[11], _legal_address_T_59
connect _legal_address_WIRE[12], _legal_address_T_64
connect _legal_address_WIRE[13], _legal_address_T_69
connect _legal_address_WIRE[14], _legal_address_T_74
connect _legal_address_WIRE[15], _legal_address_T_79
connect _legal_address_WIRE[16], _legal_address_T_84
node _legal_address_T_85 = or(_legal_address_WIRE[0], _legal_address_WIRE[1])
node _legal_address_T_86 = or(_legal_address_T_85, _legal_address_WIRE[2])
node _legal_address_T_87 = or(_legal_address_T_86, _legal_address_WIRE[3])
node _legal_address_T_88 = or(_legal_address_T_87, _legal_address_WIRE[4])
node _legal_address_T_89 = or(_legal_address_T_88, _legal_address_WIRE[5])
node _legal_address_T_90 = or(_legal_address_T_89, _legal_address_WIRE[6])
node _legal_address_T_91 = or(_legal_address_T_90, _legal_address_WIRE[7])
node _legal_address_T_92 = or(_legal_address_T_91, _legal_address_WIRE[8])
node _legal_address_T_93 = or(_legal_address_T_92, _legal_address_WIRE[9])
node _legal_address_T_94 = or(_legal_address_T_93, _legal_address_WIRE[10])
node _legal_address_T_95 = or(_legal_address_T_94, _legal_address_WIRE[11])
node _legal_address_T_96 = or(_legal_address_T_95, _legal_address_WIRE[12])
node _legal_address_T_97 = or(_legal_address_T_96, _legal_address_WIRE[13])
node _legal_address_T_98 = or(_legal_address_T_97, _legal_address_WIRE[14])
node _legal_address_T_99 = or(_legal_address_T_98, _legal_address_WIRE[15])
node legal_address = or(_legal_address_T_99, _legal_address_WIRE[16])
node _io_resp_cacheable_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_cacheable_T_1 = cvt(_io_resp_cacheable_T)
node _io_resp_cacheable_T_2 = and(_io_resp_cacheable_T_1, asSInt(UInt<33>(0h8c020000)))
node _io_resp_cacheable_T_3 = asSInt(_io_resp_cacheable_T_2)
node _io_resp_cacheable_T_4 = eq(_io_resp_cacheable_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_5 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_cacheable_T_6 = cvt(_io_resp_cacheable_T_5)
node _io_resp_cacheable_T_7 = and(_io_resp_cacheable_T_6, asSInt(UInt<33>(0h8c031000)))
node _io_resp_cacheable_T_8 = asSInt(_io_resp_cacheable_T_7)
node _io_resp_cacheable_T_9 = eq(_io_resp_cacheable_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_10 = xor(io.paddr, UInt<18>(0h20000))
node _io_resp_cacheable_T_11 = cvt(_io_resp_cacheable_T_10)
node _io_resp_cacheable_T_12 = and(_io_resp_cacheable_T_11, asSInt(UInt<33>(0h8c030000)))
node _io_resp_cacheable_T_13 = asSInt(_io_resp_cacheable_T_12)
node _io_resp_cacheable_T_14 = eq(_io_resp_cacheable_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_15 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_cacheable_T_16 = cvt(_io_resp_cacheable_T_15)
node _io_resp_cacheable_T_17 = and(_io_resp_cacheable_T_16, asSInt(UInt<33>(0h8c000000)))
node _io_resp_cacheable_T_18 = asSInt(_io_resp_cacheable_T_17)
node _io_resp_cacheable_T_19 = eq(_io_resp_cacheable_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_20 = or(_io_resp_cacheable_T_4, _io_resp_cacheable_T_9)
node _io_resp_cacheable_T_21 = or(_io_resp_cacheable_T_20, _io_resp_cacheable_T_14)
node _io_resp_cacheable_T_22 = or(_io_resp_cacheable_T_21, _io_resp_cacheable_T_19)
node _io_resp_cacheable_T_23 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_cacheable_T_24 = cvt(_io_resp_cacheable_T_23)
node _io_resp_cacheable_T_25 = and(_io_resp_cacheable_T_24, asSInt(UInt<33>(0h8c030000)))
node _io_resp_cacheable_T_26 = asSInt(_io_resp_cacheable_T_25)
node _io_resp_cacheable_T_27 = eq(_io_resp_cacheable_T_26, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_28 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_cacheable_T_29 = cvt(_io_resp_cacheable_T_28)
node _io_resp_cacheable_T_30 = and(_io_resp_cacheable_T_29, asSInt(UInt<33>(0h80000000)))
node _io_resp_cacheable_T_31 = asSInt(_io_resp_cacheable_T_30)
node _io_resp_cacheable_T_32 = eq(_io_resp_cacheable_T_31, asSInt(UInt<1>(0h0)))
node _io_resp_cacheable_T_33 = or(_io_resp_cacheable_T_27, _io_resp_cacheable_T_32)
node _io_resp_cacheable_T_34 = mux(_io_resp_cacheable_T_22, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_cacheable_T_35 = mux(_io_resp_cacheable_T_33, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_cacheable_T_36 = or(_io_resp_cacheable_T_34, _io_resp_cacheable_T_35)
wire _io_resp_cacheable_WIRE : UInt<1>
connect _io_resp_cacheable_WIRE, _io_resp_cacheable_T_36
node _io_resp_cacheable_T_37 = and(legal_address, _io_resp_cacheable_WIRE)
connect io.resp.cacheable, _io_resp_cacheable_T_37
node _io_resp_r_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_r_T_1 = cvt(_io_resp_r_T)
node _io_resp_r_T_2 = and(_io_resp_r_T_1, asSInt(UInt<1>(0h0)))
node _io_resp_r_T_3 = asSInt(_io_resp_r_T_2)
node _io_resp_r_T_4 = eq(_io_resp_r_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_r_T_5 = and(legal_address, UInt<1>(0h1))
connect io.resp.r, _io_resp_r_T_5
node _io_resp_w_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_w_T_1 = cvt(_io_resp_w_T)
node _io_resp_w_T_2 = and(_io_resp_w_T_1, asSInt(UInt<33>(0hfffd8000)))
node _io_resp_w_T_3 = asSInt(_io_resp_w_T_2)
node _io_resp_w_T_4 = eq(_io_resp_w_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_5 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_w_T_6 = cvt(_io_resp_w_T_5)
node _io_resp_w_T_7 = and(_io_resp_w_T_6, asSInt(UInt<33>(0hfffe9000)))
node _io_resp_w_T_8 = asSInt(_io_resp_w_T_7)
node _io_resp_w_T_9 = eq(_io_resp_w_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_10 = xor(io.paddr, UInt<26>(0h2000000))
node _io_resp_w_T_11 = cvt(_io_resp_w_T_10)
node _io_resp_w_T_12 = and(_io_resp_w_T_11, asSInt(UInt<33>(0hffff0000)))
node _io_resp_w_T_13 = asSInt(_io_resp_w_T_12)
node _io_resp_w_T_14 = eq(_io_resp_w_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_15 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_w_T_16 = cvt(_io_resp_w_T_15)
node _io_resp_w_T_17 = and(_io_resp_w_T_16, asSInt(UInt<33>(0hffff9000)))
node _io_resp_w_T_18 = asSInt(_io_resp_w_T_17)
node _io_resp_w_T_19 = eq(_io_resp_w_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_20 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_w_T_21 = cvt(_io_resp_w_T_20)
node _io_resp_w_T_22 = and(_io_resp_w_T_21, asSInt(UInt<33>(0hffff0000)))
node _io_resp_w_T_23 = asSInt(_io_resp_w_T_22)
node _io_resp_w_T_24 = eq(_io_resp_w_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_25 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_w_T_26 = cvt(_io_resp_w_T_25)
node _io_resp_w_T_27 = and(_io_resp_w_T_26, asSInt(UInt<33>(0hfc000000)))
node _io_resp_w_T_28 = asSInt(_io_resp_w_T_27)
node _io_resp_w_T_29 = eq(_io_resp_w_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_30 = xor(io.paddr, UInt<29>(0h10020000))
node _io_resp_w_T_31 = cvt(_io_resp_w_T_30)
node _io_resp_w_T_32 = and(_io_resp_w_T_31, asSInt(UInt<33>(0hffff9000)))
node _io_resp_w_T_33 = asSInt(_io_resp_w_T_32)
node _io_resp_w_T_34 = eq(_io_resp_w_T_33, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_35 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_w_T_36 = cvt(_io_resp_w_T_35)
node _io_resp_w_T_37 = and(_io_resp_w_T_36, asSInt(UInt<33>(0hf0000000)))
node _io_resp_w_T_38 = asSInt(_io_resp_w_T_37)
node _io_resp_w_T_39 = eq(_io_resp_w_T_38, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_40 = or(_io_resp_w_T_4, _io_resp_w_T_9)
node _io_resp_w_T_41 = or(_io_resp_w_T_40, _io_resp_w_T_14)
node _io_resp_w_T_42 = or(_io_resp_w_T_41, _io_resp_w_T_19)
node _io_resp_w_T_43 = or(_io_resp_w_T_42, _io_resp_w_T_24)
node _io_resp_w_T_44 = or(_io_resp_w_T_43, _io_resp_w_T_29)
node _io_resp_w_T_45 = or(_io_resp_w_T_44, _io_resp_w_T_34)
node _io_resp_w_T_46 = or(_io_resp_w_T_45, _io_resp_w_T_39)
node _io_resp_w_T_47 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_w_T_48 = cvt(_io_resp_w_T_47)
node _io_resp_w_T_49 = and(_io_resp_w_T_48, asSInt(UInt<33>(0hffff0000)))
node _io_resp_w_T_50 = asSInt(_io_resp_w_T_49)
node _io_resp_w_T_51 = eq(_io_resp_w_T_50, asSInt(UInt<1>(0h0)))
node _io_resp_w_T_52 = mux(_io_resp_w_T_46, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_w_T_53 = mux(_io_resp_w_T_51, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_w_T_54 = or(_io_resp_w_T_52, _io_resp_w_T_53)
wire _io_resp_w_WIRE : UInt<1>
connect _io_resp_w_WIRE, _io_resp_w_T_54
node _io_resp_w_T_55 = and(legal_address, _io_resp_w_WIRE)
connect io.resp.w, _io_resp_w_T_55
node _io_resp_pp_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_pp_T_1 = cvt(_io_resp_pp_T)
node _io_resp_pp_T_2 = and(_io_resp_pp_T_1, asSInt(UInt<33>(0hfffd8000)))
node _io_resp_pp_T_3 = asSInt(_io_resp_pp_T_2)
node _io_resp_pp_T_4 = eq(_io_resp_pp_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_5 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_pp_T_6 = cvt(_io_resp_pp_T_5)
node _io_resp_pp_T_7 = and(_io_resp_pp_T_6, asSInt(UInt<33>(0hfffe9000)))
node _io_resp_pp_T_8 = asSInt(_io_resp_pp_T_7)
node _io_resp_pp_T_9 = eq(_io_resp_pp_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_10 = xor(io.paddr, UInt<26>(0h2000000))
node _io_resp_pp_T_11 = cvt(_io_resp_pp_T_10)
node _io_resp_pp_T_12 = and(_io_resp_pp_T_11, asSInt(UInt<33>(0hffff0000)))
node _io_resp_pp_T_13 = asSInt(_io_resp_pp_T_12)
node _io_resp_pp_T_14 = eq(_io_resp_pp_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_15 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_pp_T_16 = cvt(_io_resp_pp_T_15)
node _io_resp_pp_T_17 = and(_io_resp_pp_T_16, asSInt(UInt<33>(0hffff9000)))
node _io_resp_pp_T_18 = asSInt(_io_resp_pp_T_17)
node _io_resp_pp_T_19 = eq(_io_resp_pp_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_20 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_pp_T_21 = cvt(_io_resp_pp_T_20)
node _io_resp_pp_T_22 = and(_io_resp_pp_T_21, asSInt(UInt<33>(0hffff0000)))
node _io_resp_pp_T_23 = asSInt(_io_resp_pp_T_22)
node _io_resp_pp_T_24 = eq(_io_resp_pp_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_25 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_pp_T_26 = cvt(_io_resp_pp_T_25)
node _io_resp_pp_T_27 = and(_io_resp_pp_T_26, asSInt(UInt<33>(0hfc000000)))
node _io_resp_pp_T_28 = asSInt(_io_resp_pp_T_27)
node _io_resp_pp_T_29 = eq(_io_resp_pp_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_30 = xor(io.paddr, UInt<29>(0h10020000))
node _io_resp_pp_T_31 = cvt(_io_resp_pp_T_30)
node _io_resp_pp_T_32 = and(_io_resp_pp_T_31, asSInt(UInt<33>(0hffff9000)))
node _io_resp_pp_T_33 = asSInt(_io_resp_pp_T_32)
node _io_resp_pp_T_34 = eq(_io_resp_pp_T_33, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_35 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_pp_T_36 = cvt(_io_resp_pp_T_35)
node _io_resp_pp_T_37 = and(_io_resp_pp_T_36, asSInt(UInt<33>(0hf0000000)))
node _io_resp_pp_T_38 = asSInt(_io_resp_pp_T_37)
node _io_resp_pp_T_39 = eq(_io_resp_pp_T_38, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_40 = or(_io_resp_pp_T_4, _io_resp_pp_T_9)
node _io_resp_pp_T_41 = or(_io_resp_pp_T_40, _io_resp_pp_T_14)
node _io_resp_pp_T_42 = or(_io_resp_pp_T_41, _io_resp_pp_T_19)
node _io_resp_pp_T_43 = or(_io_resp_pp_T_42, _io_resp_pp_T_24)
node _io_resp_pp_T_44 = or(_io_resp_pp_T_43, _io_resp_pp_T_29)
node _io_resp_pp_T_45 = or(_io_resp_pp_T_44, _io_resp_pp_T_34)
node _io_resp_pp_T_46 = or(_io_resp_pp_T_45, _io_resp_pp_T_39)
node _io_resp_pp_T_47 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_pp_T_48 = cvt(_io_resp_pp_T_47)
node _io_resp_pp_T_49 = and(_io_resp_pp_T_48, asSInt(UInt<33>(0hffff0000)))
node _io_resp_pp_T_50 = asSInt(_io_resp_pp_T_49)
node _io_resp_pp_T_51 = eq(_io_resp_pp_T_50, asSInt(UInt<1>(0h0)))
node _io_resp_pp_T_52 = mux(_io_resp_pp_T_46, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_pp_T_53 = mux(_io_resp_pp_T_51, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_pp_T_54 = or(_io_resp_pp_T_52, _io_resp_pp_T_53)
wire _io_resp_pp_WIRE : UInt<1>
connect _io_resp_pp_WIRE, _io_resp_pp_T_54
node _io_resp_pp_T_55 = and(legal_address, _io_resp_pp_WIRE)
connect io.resp.pp, _io_resp_pp_T_55
node _io_resp_al_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_al_T_1 = cvt(_io_resp_al_T)
node _io_resp_al_T_2 = and(_io_resp_al_T_1, asSInt(UInt<33>(0hfffd8000)))
node _io_resp_al_T_3 = asSInt(_io_resp_al_T_2)
node _io_resp_al_T_4 = eq(_io_resp_al_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_5 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_al_T_6 = cvt(_io_resp_al_T_5)
node _io_resp_al_T_7 = and(_io_resp_al_T_6, asSInt(UInt<33>(0hfffe9000)))
node _io_resp_al_T_8 = asSInt(_io_resp_al_T_7)
node _io_resp_al_T_9 = eq(_io_resp_al_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_10 = xor(io.paddr, UInt<26>(0h2000000))
node _io_resp_al_T_11 = cvt(_io_resp_al_T_10)
node _io_resp_al_T_12 = and(_io_resp_al_T_11, asSInt(UInt<33>(0hffff0000)))
node _io_resp_al_T_13 = asSInt(_io_resp_al_T_12)
node _io_resp_al_T_14 = eq(_io_resp_al_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_15 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_al_T_16 = cvt(_io_resp_al_T_15)
node _io_resp_al_T_17 = and(_io_resp_al_T_16, asSInt(UInt<33>(0hffff9000)))
node _io_resp_al_T_18 = asSInt(_io_resp_al_T_17)
node _io_resp_al_T_19 = eq(_io_resp_al_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_20 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_al_T_21 = cvt(_io_resp_al_T_20)
node _io_resp_al_T_22 = and(_io_resp_al_T_21, asSInt(UInt<33>(0hffff0000)))
node _io_resp_al_T_23 = asSInt(_io_resp_al_T_22)
node _io_resp_al_T_24 = eq(_io_resp_al_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_25 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_al_T_26 = cvt(_io_resp_al_T_25)
node _io_resp_al_T_27 = and(_io_resp_al_T_26, asSInt(UInt<33>(0hfc000000)))
node _io_resp_al_T_28 = asSInt(_io_resp_al_T_27)
node _io_resp_al_T_29 = eq(_io_resp_al_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_30 = xor(io.paddr, UInt<29>(0h10020000))
node _io_resp_al_T_31 = cvt(_io_resp_al_T_30)
node _io_resp_al_T_32 = and(_io_resp_al_T_31, asSInt(UInt<33>(0hffff9000)))
node _io_resp_al_T_33 = asSInt(_io_resp_al_T_32)
node _io_resp_al_T_34 = eq(_io_resp_al_T_33, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_35 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_al_T_36 = cvt(_io_resp_al_T_35)
node _io_resp_al_T_37 = and(_io_resp_al_T_36, asSInt(UInt<33>(0hf0000000)))
node _io_resp_al_T_38 = asSInt(_io_resp_al_T_37)
node _io_resp_al_T_39 = eq(_io_resp_al_T_38, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_40 = or(_io_resp_al_T_4, _io_resp_al_T_9)
node _io_resp_al_T_41 = or(_io_resp_al_T_40, _io_resp_al_T_14)
node _io_resp_al_T_42 = or(_io_resp_al_T_41, _io_resp_al_T_19)
node _io_resp_al_T_43 = or(_io_resp_al_T_42, _io_resp_al_T_24)
node _io_resp_al_T_44 = or(_io_resp_al_T_43, _io_resp_al_T_29)
node _io_resp_al_T_45 = or(_io_resp_al_T_44, _io_resp_al_T_34)
node _io_resp_al_T_46 = or(_io_resp_al_T_45, _io_resp_al_T_39)
node _io_resp_al_T_47 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_al_T_48 = cvt(_io_resp_al_T_47)
node _io_resp_al_T_49 = and(_io_resp_al_T_48, asSInt(UInt<33>(0hffff0000)))
node _io_resp_al_T_50 = asSInt(_io_resp_al_T_49)
node _io_resp_al_T_51 = eq(_io_resp_al_T_50, asSInt(UInt<1>(0h0)))
node _io_resp_al_T_52 = mux(_io_resp_al_T_46, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_al_T_53 = mux(_io_resp_al_T_51, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_al_T_54 = or(_io_resp_al_T_52, _io_resp_al_T_53)
wire _io_resp_al_WIRE : UInt<1>
connect _io_resp_al_WIRE, _io_resp_al_T_54
node _io_resp_al_T_55 = and(legal_address, _io_resp_al_WIRE)
connect io.resp.al, _io_resp_al_T_55
node _io_resp_aa_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_aa_T_1 = cvt(_io_resp_aa_T)
node _io_resp_aa_T_2 = and(_io_resp_aa_T_1, asSInt(UInt<33>(0hfffd8000)))
node _io_resp_aa_T_3 = asSInt(_io_resp_aa_T_2)
node _io_resp_aa_T_4 = eq(_io_resp_aa_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_5 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_aa_T_6 = cvt(_io_resp_aa_T_5)
node _io_resp_aa_T_7 = and(_io_resp_aa_T_6, asSInt(UInt<33>(0hfffe9000)))
node _io_resp_aa_T_8 = asSInt(_io_resp_aa_T_7)
node _io_resp_aa_T_9 = eq(_io_resp_aa_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_10 = xor(io.paddr, UInt<26>(0h2000000))
node _io_resp_aa_T_11 = cvt(_io_resp_aa_T_10)
node _io_resp_aa_T_12 = and(_io_resp_aa_T_11, asSInt(UInt<33>(0hffff0000)))
node _io_resp_aa_T_13 = asSInt(_io_resp_aa_T_12)
node _io_resp_aa_T_14 = eq(_io_resp_aa_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_15 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_aa_T_16 = cvt(_io_resp_aa_T_15)
node _io_resp_aa_T_17 = and(_io_resp_aa_T_16, asSInt(UInt<33>(0hffff9000)))
node _io_resp_aa_T_18 = asSInt(_io_resp_aa_T_17)
node _io_resp_aa_T_19 = eq(_io_resp_aa_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_20 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_aa_T_21 = cvt(_io_resp_aa_T_20)
node _io_resp_aa_T_22 = and(_io_resp_aa_T_21, asSInt(UInt<33>(0hffff0000)))
node _io_resp_aa_T_23 = asSInt(_io_resp_aa_T_22)
node _io_resp_aa_T_24 = eq(_io_resp_aa_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_25 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_aa_T_26 = cvt(_io_resp_aa_T_25)
node _io_resp_aa_T_27 = and(_io_resp_aa_T_26, asSInt(UInt<33>(0hfc000000)))
node _io_resp_aa_T_28 = asSInt(_io_resp_aa_T_27)
node _io_resp_aa_T_29 = eq(_io_resp_aa_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_30 = xor(io.paddr, UInt<29>(0h10020000))
node _io_resp_aa_T_31 = cvt(_io_resp_aa_T_30)
node _io_resp_aa_T_32 = and(_io_resp_aa_T_31, asSInt(UInt<33>(0hffff9000)))
node _io_resp_aa_T_33 = asSInt(_io_resp_aa_T_32)
node _io_resp_aa_T_34 = eq(_io_resp_aa_T_33, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_35 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_aa_T_36 = cvt(_io_resp_aa_T_35)
node _io_resp_aa_T_37 = and(_io_resp_aa_T_36, asSInt(UInt<33>(0hf0000000)))
node _io_resp_aa_T_38 = asSInt(_io_resp_aa_T_37)
node _io_resp_aa_T_39 = eq(_io_resp_aa_T_38, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_40 = or(_io_resp_aa_T_4, _io_resp_aa_T_9)
node _io_resp_aa_T_41 = or(_io_resp_aa_T_40, _io_resp_aa_T_14)
node _io_resp_aa_T_42 = or(_io_resp_aa_T_41, _io_resp_aa_T_19)
node _io_resp_aa_T_43 = or(_io_resp_aa_T_42, _io_resp_aa_T_24)
node _io_resp_aa_T_44 = or(_io_resp_aa_T_43, _io_resp_aa_T_29)
node _io_resp_aa_T_45 = or(_io_resp_aa_T_44, _io_resp_aa_T_34)
node _io_resp_aa_T_46 = or(_io_resp_aa_T_45, _io_resp_aa_T_39)
node _io_resp_aa_T_47 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_aa_T_48 = cvt(_io_resp_aa_T_47)
node _io_resp_aa_T_49 = and(_io_resp_aa_T_48, asSInt(UInt<33>(0hffff0000)))
node _io_resp_aa_T_50 = asSInt(_io_resp_aa_T_49)
node _io_resp_aa_T_51 = eq(_io_resp_aa_T_50, asSInt(UInt<1>(0h0)))
node _io_resp_aa_T_52 = mux(_io_resp_aa_T_46, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_aa_T_53 = mux(_io_resp_aa_T_51, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_aa_T_54 = or(_io_resp_aa_T_52, _io_resp_aa_T_53)
wire _io_resp_aa_WIRE : UInt<1>
connect _io_resp_aa_WIRE, _io_resp_aa_T_54
node _io_resp_aa_T_55 = and(legal_address, _io_resp_aa_WIRE)
connect io.resp.aa, _io_resp_aa_T_55
node _io_resp_x_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_x_T_1 = cvt(_io_resp_x_T)
node _io_resp_x_T_2 = and(_io_resp_x_T_1, asSInt(UInt<33>(0hfffff000)))
node _io_resp_x_T_3 = asSInt(_io_resp_x_T_2)
node _io_resp_x_T_4 = eq(_io_resp_x_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_5 = xor(io.paddr, UInt<14>(0h3000))
node _io_resp_x_T_6 = cvt(_io_resp_x_T_5)
node _io_resp_x_T_7 = and(_io_resp_x_T_6, asSInt(UInt<33>(0hfffff000)))
node _io_resp_x_T_8 = asSInt(_io_resp_x_T_7)
node _io_resp_x_T_9 = eq(_io_resp_x_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_10 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_x_T_11 = cvt(_io_resp_x_T_10)
node _io_resp_x_T_12 = and(_io_resp_x_T_11, asSInt(UInt<33>(0hffff0000)))
node _io_resp_x_T_13 = asSInt(_io_resp_x_T_12)
node _io_resp_x_T_14 = eq(_io_resp_x_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_15 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_x_T_16 = cvt(_io_resp_x_T_15)
node _io_resp_x_T_17 = and(_io_resp_x_T_16, asSInt(UInt<33>(0hffff0000)))
node _io_resp_x_T_18 = asSInt(_io_resp_x_T_17)
node _io_resp_x_T_19 = eq(_io_resp_x_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_20 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_x_T_21 = cvt(_io_resp_x_T_20)
node _io_resp_x_T_22 = and(_io_resp_x_T_21, asSInt(UInt<33>(0hf0000000)))
node _io_resp_x_T_23 = asSInt(_io_resp_x_T_22)
node _io_resp_x_T_24 = eq(_io_resp_x_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_25 = or(_io_resp_x_T_4, _io_resp_x_T_9)
node _io_resp_x_T_26 = or(_io_resp_x_T_25, _io_resp_x_T_14)
node _io_resp_x_T_27 = or(_io_resp_x_T_26, _io_resp_x_T_19)
node _io_resp_x_T_28 = or(_io_resp_x_T_27, _io_resp_x_T_24)
node _io_resp_x_T_29 = xor(io.paddr, UInt<13>(0h1000))
node _io_resp_x_T_30 = cvt(_io_resp_x_T_29)
node _io_resp_x_T_31 = and(_io_resp_x_T_30, asSInt(UInt<33>(0hfffff000)))
node _io_resp_x_T_32 = asSInt(_io_resp_x_T_31)
node _io_resp_x_T_33 = eq(_io_resp_x_T_32, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_34 = xor(io.paddr, UInt<18>(0h20000))
node _io_resp_x_T_35 = cvt(_io_resp_x_T_34)
node _io_resp_x_T_36 = and(_io_resp_x_T_35, asSInt(UInt<33>(0hffffc000)))
node _io_resp_x_T_37 = asSInt(_io_resp_x_T_36)
node _io_resp_x_T_38 = eq(_io_resp_x_T_37, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_39 = xor(io.paddr, UInt<18>(0h24000))
node _io_resp_x_T_40 = cvt(_io_resp_x_T_39)
node _io_resp_x_T_41 = and(_io_resp_x_T_40, asSInt(UInt<33>(0hfffff000)))
node _io_resp_x_T_42 = asSInt(_io_resp_x_T_41)
node _io_resp_x_T_43 = eq(_io_resp_x_T_42, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_44 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_x_T_45 = cvt(_io_resp_x_T_44)
node _io_resp_x_T_46 = and(_io_resp_x_T_45, asSInt(UInt<33>(0hfffef000)))
node _io_resp_x_T_47 = asSInt(_io_resp_x_T_46)
node _io_resp_x_T_48 = eq(_io_resp_x_T_47, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_49 = xor(io.paddr, UInt<26>(0h2000000))
node _io_resp_x_T_50 = cvt(_io_resp_x_T_49)
node _io_resp_x_T_51 = and(_io_resp_x_T_50, asSInt(UInt<33>(0hffff0000)))
node _io_resp_x_T_52 = asSInt(_io_resp_x_T_51)
node _io_resp_x_T_53 = eq(_io_resp_x_T_52, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_54 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_x_T_55 = cvt(_io_resp_x_T_54)
node _io_resp_x_T_56 = and(_io_resp_x_T_55, asSInt(UInt<33>(0hfffff000)))
node _io_resp_x_T_57 = asSInt(_io_resp_x_T_56)
node _io_resp_x_T_58 = eq(_io_resp_x_T_57, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_59 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_x_T_60 = cvt(_io_resp_x_T_59)
node _io_resp_x_T_61 = and(_io_resp_x_T_60, asSInt(UInt<33>(0hfc000000)))
node _io_resp_x_T_62 = asSInt(_io_resp_x_T_61)
node _io_resp_x_T_63 = eq(_io_resp_x_T_62, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_64 = xor(io.paddr, UInt<29>(0h10020000))
node _io_resp_x_T_65 = cvt(_io_resp_x_T_64)
node _io_resp_x_T_66 = and(_io_resp_x_T_65, asSInt(UInt<33>(0hfffff000)))
node _io_resp_x_T_67 = asSInt(_io_resp_x_T_66)
node _io_resp_x_T_68 = eq(_io_resp_x_T_67, asSInt(UInt<1>(0h0)))
node _io_resp_x_T_69 = or(_io_resp_x_T_33, _io_resp_x_T_38)
node _io_resp_x_T_70 = or(_io_resp_x_T_69, _io_resp_x_T_43)
node _io_resp_x_T_71 = or(_io_resp_x_T_70, _io_resp_x_T_48)
node _io_resp_x_T_72 = or(_io_resp_x_T_71, _io_resp_x_T_53)
node _io_resp_x_T_73 = or(_io_resp_x_T_72, _io_resp_x_T_58)
node _io_resp_x_T_74 = or(_io_resp_x_T_73, _io_resp_x_T_63)
node _io_resp_x_T_75 = or(_io_resp_x_T_74, _io_resp_x_T_68)
node _io_resp_x_T_76 = mux(_io_resp_x_T_28, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_x_T_77 = mux(_io_resp_x_T_75, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_x_T_78 = or(_io_resp_x_T_76, _io_resp_x_T_77)
wire _io_resp_x_WIRE : UInt<1>
connect _io_resp_x_WIRE, _io_resp_x_T_78
node _io_resp_x_T_79 = and(legal_address, _io_resp_x_WIRE)
connect io.resp.x, _io_resp_x_T_79
node _io_resp_eff_T = xor(io.paddr, UInt<1>(0h0))
node _io_resp_eff_T_1 = cvt(_io_resp_eff_T)
node _io_resp_eff_T_2 = and(_io_resp_eff_T_1, asSInt(UInt<33>(0hffffa000)))
node _io_resp_eff_T_3 = asSInt(_io_resp_eff_T_2)
node _io_resp_eff_T_4 = eq(_io_resp_eff_T_3, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_5 = xor(io.paddr, UInt<18>(0h20000))
node _io_resp_eff_T_6 = cvt(_io_resp_eff_T_5)
node _io_resp_eff_T_7 = and(_io_resp_eff_T_6, asSInt(UInt<33>(0hffff8000)))
node _io_resp_eff_T_8 = asSInt(_io_resp_eff_T_7)
node _io_resp_eff_T_9 = eq(_io_resp_eff_T_8, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_10 = xor(io.paddr, UInt<21>(0h100000))
node _io_resp_eff_T_11 = cvt(_io_resp_eff_T_10)
node _io_resp_eff_T_12 = and(_io_resp_eff_T_11, asSInt(UInt<33>(0hfffeb000)))
node _io_resp_eff_T_13 = asSInt(_io_resp_eff_T_12)
node _io_resp_eff_T_14 = eq(_io_resp_eff_T_13, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_15 = xor(io.paddr, UInt<26>(0h2000000))
node _io_resp_eff_T_16 = cvt(_io_resp_eff_T_15)
node _io_resp_eff_T_17 = and(_io_resp_eff_T_16, asSInt(UInt<33>(0hffff0000)))
node _io_resp_eff_T_18 = asSInt(_io_resp_eff_T_17)
node _io_resp_eff_T_19 = eq(_io_resp_eff_T_18, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_20 = xor(io.paddr, UInt<26>(0h2010000))
node _io_resp_eff_T_21 = cvt(_io_resp_eff_T_20)
node _io_resp_eff_T_22 = and(_io_resp_eff_T_21, asSInt(UInt<33>(0hffffb000)))
node _io_resp_eff_T_23 = asSInt(_io_resp_eff_T_22)
node _io_resp_eff_T_24 = eq(_io_resp_eff_T_23, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_25 = xor(io.paddr, UInt<28>(0hc000000))
node _io_resp_eff_T_26 = cvt(_io_resp_eff_T_25)
node _io_resp_eff_T_27 = and(_io_resp_eff_T_26, asSInt(UInt<33>(0hfc000000)))
node _io_resp_eff_T_28 = asSInt(_io_resp_eff_T_27)
node _io_resp_eff_T_29 = eq(_io_resp_eff_T_28, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_30 = xor(io.paddr, UInt<29>(0h10020000))
node _io_resp_eff_T_31 = cvt(_io_resp_eff_T_30)
node _io_resp_eff_T_32 = and(_io_resp_eff_T_31, asSInt(UInt<33>(0hffffb000)))
node _io_resp_eff_T_33 = asSInt(_io_resp_eff_T_32)
node _io_resp_eff_T_34 = eq(_io_resp_eff_T_33, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_35 = or(_io_resp_eff_T_4, _io_resp_eff_T_9)
node _io_resp_eff_T_36 = or(_io_resp_eff_T_35, _io_resp_eff_T_14)
node _io_resp_eff_T_37 = or(_io_resp_eff_T_36, _io_resp_eff_T_19)
node _io_resp_eff_T_38 = or(_io_resp_eff_T_37, _io_resp_eff_T_24)
node _io_resp_eff_T_39 = or(_io_resp_eff_T_38, _io_resp_eff_T_29)
node _io_resp_eff_T_40 = or(_io_resp_eff_T_39, _io_resp_eff_T_34)
node _io_resp_eff_T_41 = xor(io.paddr, UInt<14>(0h3000))
node _io_resp_eff_T_42 = cvt(_io_resp_eff_T_41)
node _io_resp_eff_T_43 = and(_io_resp_eff_T_42, asSInt(UInt<33>(0hffffb000)))
node _io_resp_eff_T_44 = asSInt(_io_resp_eff_T_43)
node _io_resp_eff_T_45 = eq(_io_resp_eff_T_44, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_46 = xor(io.paddr, UInt<17>(0h10000))
node _io_resp_eff_T_47 = cvt(_io_resp_eff_T_46)
node _io_resp_eff_T_48 = and(_io_resp_eff_T_47, asSInt(UInt<33>(0hffff0000)))
node _io_resp_eff_T_49 = asSInt(_io_resp_eff_T_48)
node _io_resp_eff_T_50 = eq(_io_resp_eff_T_49, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_51 = xor(io.paddr, UInt<28>(0h8000000))
node _io_resp_eff_T_52 = cvt(_io_resp_eff_T_51)
node _io_resp_eff_T_53 = and(_io_resp_eff_T_52, asSInt(UInt<33>(0hffff0000)))
node _io_resp_eff_T_54 = asSInt(_io_resp_eff_T_53)
node _io_resp_eff_T_55 = eq(_io_resp_eff_T_54, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_56 = xor(io.paddr, UInt<32>(0h80000000))
node _io_resp_eff_T_57 = cvt(_io_resp_eff_T_56)
node _io_resp_eff_T_58 = and(_io_resp_eff_T_57, asSInt(UInt<33>(0hf0000000)))
node _io_resp_eff_T_59 = asSInt(_io_resp_eff_T_58)
node _io_resp_eff_T_60 = eq(_io_resp_eff_T_59, asSInt(UInt<1>(0h0)))
node _io_resp_eff_T_61 = or(_io_resp_eff_T_45, _io_resp_eff_T_50)
node _io_resp_eff_T_62 = or(_io_resp_eff_T_61, _io_resp_eff_T_55)
node _io_resp_eff_T_63 = or(_io_resp_eff_T_62, _io_resp_eff_T_60)
node _io_resp_eff_T_64 = mux(_io_resp_eff_T_40, UInt<1>(0h1), UInt<1>(0h0))
node _io_resp_eff_T_65 = mux(_io_resp_eff_T_63, UInt<1>(0h0), UInt<1>(0h0))
node _io_resp_eff_T_66 = or(_io_resp_eff_T_64, _io_resp_eff_T_65)
wire _io_resp_eff_WIRE : UInt<1>
connect _io_resp_eff_WIRE, _io_resp_eff_T_66
node _io_resp_eff_T_67 = and(legal_address, _io_resp_eff_WIRE)
connect io.resp.eff, _io_resp_eff_T_67 | module PMAChecker_8( // @[PMA.scala:18:7]
input clock, // @[PMA.scala:18:7]
input reset, // @[PMA.scala:18:7]
input [39:0] io_paddr, // @[PMA.scala:19:14]
output io_resp_cacheable, // @[PMA.scala:19:14]
output io_resp_r, // @[PMA.scala:19:14]
output io_resp_w, // @[PMA.scala:19:14]
output io_resp_pp, // @[PMA.scala:19:14]
output io_resp_al, // @[PMA.scala:19:14]
output io_resp_aa, // @[PMA.scala:19:14]
output io_resp_x, // @[PMA.scala:19:14]
output io_resp_eff // @[PMA.scala:19:14]
);
wire [39:0] io_paddr_0 = io_paddr; // @[PMA.scala:18:7]
wire [40:0] _io_resp_r_T_2 = 41'h0; // @[Parameters.scala:137:46]
wire [40:0] _io_resp_r_T_3 = 41'h0; // @[Parameters.scala:137:46]
wire _io_resp_r_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire _io_resp_cacheable_T_34 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_w_T_53 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_pp_T_53 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_al_T_53 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_aa_T_53 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_x_T_77 = 1'h0; // @[Mux.scala:30:73]
wire _io_resp_eff_T_65 = 1'h0; // @[Mux.scala:30:73]
wire [39:0] _legal_address_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_cacheable_T = io_paddr_0; // @[PMA.scala:18:7]
wire _io_resp_cacheable_T_37; // @[PMA.scala:39:19]
wire [39:0] _io_resp_r_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_w_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_pp_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_al_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_aa_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_x_T = io_paddr_0; // @[PMA.scala:18:7]
wire [39:0] _io_resp_eff_T = io_paddr_0; // @[PMA.scala:18:7]
wire _io_resp_r_T_5; // @[PMA.scala:39:19]
wire _io_resp_w_T_55; // @[PMA.scala:39:19]
wire _io_resp_pp_T_55; // @[PMA.scala:39:19]
wire _io_resp_al_T_55; // @[PMA.scala:39:19]
wire _io_resp_aa_T_55; // @[PMA.scala:39:19]
wire _io_resp_x_T_79; // @[PMA.scala:39:19]
wire _io_resp_eff_T_67; // @[PMA.scala:39:19]
wire io_resp_cacheable_0; // @[PMA.scala:18:7]
wire io_resp_r_0; // @[PMA.scala:18:7]
wire io_resp_w_0; // @[PMA.scala:18:7]
wire io_resp_pp_0; // @[PMA.scala:18:7]
wire io_resp_al_0; // @[PMA.scala:18:7]
wire io_resp_aa_0; // @[PMA.scala:18:7]
wire io_resp_x_0; // @[PMA.scala:18:7]
wire io_resp_eff_0; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_1 = {1'h0, _legal_address_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_2 = _legal_address_T_1 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_3 = _legal_address_T_2; // @[Parameters.scala:137:46]
wire _legal_address_T_4 = _legal_address_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_0 = _legal_address_T_4; // @[Parameters.scala:612:40]
wire [39:0] _GEN = {io_paddr_0[39:13], io_paddr_0[12:0] ^ 13'h1000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_5; // @[Parameters.scala:137:31]
assign _legal_address_T_5 = _GEN; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_29; // @[Parameters.scala:137:31]
assign _io_resp_x_T_29 = _GEN; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_6 = {1'h0, _legal_address_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_7 = _legal_address_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_8 = _legal_address_T_7; // @[Parameters.scala:137:46]
wire _legal_address_T_9 = _legal_address_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_1 = _legal_address_T_9; // @[Parameters.scala:612:40]
wire [39:0] _GEN_0 = {io_paddr_0[39:14], io_paddr_0[13:0] ^ 14'h3000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_10; // @[Parameters.scala:137:31]
assign _legal_address_T_10 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_5; // @[Parameters.scala:137:31]
assign _io_resp_x_T_5 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_41; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_41 = _GEN_0; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_11 = {1'h0, _legal_address_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_12 = _legal_address_T_11 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_13 = _legal_address_T_12; // @[Parameters.scala:137:46]
wire _legal_address_T_14 = _legal_address_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_2 = _legal_address_T_14; // @[Parameters.scala:612:40]
wire [39:0] _GEN_1 = {io_paddr_0[39:17], io_paddr_0[16:0] ^ 17'h10000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_15; // @[Parameters.scala:137:31]
assign _legal_address_T_15 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_5; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_5 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_47; // @[Parameters.scala:137:31]
assign _io_resp_w_T_47 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_47; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_47 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_47; // @[Parameters.scala:137:31]
assign _io_resp_al_T_47 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_47; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_47 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_10; // @[Parameters.scala:137:31]
assign _io_resp_x_T_10 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_46; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_46 = _GEN_1; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_16 = {1'h0, _legal_address_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_17 = _legal_address_T_16 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_18 = _legal_address_T_17; // @[Parameters.scala:137:46]
wire _legal_address_T_19 = _legal_address_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_3 = _legal_address_T_19; // @[Parameters.scala:612:40]
wire [39:0] _GEN_2 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h20000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_20; // @[Parameters.scala:137:31]
assign _legal_address_T_20 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_10; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_10 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_34; // @[Parameters.scala:137:31]
assign _io_resp_x_T_34 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_5; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_5 = _GEN_2; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_21 = {1'h0, _legal_address_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_22 = _legal_address_T_21 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_23 = _legal_address_T_22; // @[Parameters.scala:137:46]
wire _legal_address_T_24 = _legal_address_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_4 = _legal_address_T_24; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_25 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h21000}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_26 = {1'h0, _legal_address_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_27 = _legal_address_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_28 = _legal_address_T_27; // @[Parameters.scala:137:46]
wire _legal_address_T_29 = _legal_address_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_5 = _legal_address_T_29; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_30 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h22000}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_31 = {1'h0, _legal_address_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_32 = _legal_address_T_31 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_33 = _legal_address_T_32; // @[Parameters.scala:137:46]
wire _legal_address_T_34 = _legal_address_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_6 = _legal_address_T_34; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_35 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h23000}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_36 = {1'h0, _legal_address_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_37 = _legal_address_T_36 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_38 = _legal_address_T_37; // @[Parameters.scala:137:46]
wire _legal_address_T_39 = _legal_address_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_7 = _legal_address_T_39; // @[Parameters.scala:612:40]
wire [39:0] _GEN_3 = {io_paddr_0[39:18], io_paddr_0[17:0] ^ 18'h24000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_40; // @[Parameters.scala:137:31]
assign _legal_address_T_40 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_39; // @[Parameters.scala:137:31]
assign _io_resp_x_T_39 = _GEN_3; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_41 = {1'h0, _legal_address_T_40}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_42 = _legal_address_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_43 = _legal_address_T_42; // @[Parameters.scala:137:46]
wire _legal_address_T_44 = _legal_address_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_8 = _legal_address_T_44; // @[Parameters.scala:612:40]
wire [39:0] _GEN_4 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h100000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_45; // @[Parameters.scala:137:31]
assign _legal_address_T_45 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_5; // @[Parameters.scala:137:31]
assign _io_resp_w_T_5 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_5; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_5 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_5; // @[Parameters.scala:137:31]
assign _io_resp_al_T_5 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_5; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_5 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_44; // @[Parameters.scala:137:31]
assign _io_resp_x_T_44 = _GEN_4; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_10; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_10 = _GEN_4; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_46 = {1'h0, _legal_address_T_45}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_47 = _legal_address_T_46 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_48 = _legal_address_T_47; // @[Parameters.scala:137:46]
wire _legal_address_T_49 = _legal_address_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_9 = _legal_address_T_49; // @[Parameters.scala:612:40]
wire [39:0] _legal_address_T_50 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h110000}; // @[PMA.scala:18:7]
wire [40:0] _legal_address_T_51 = {1'h0, _legal_address_T_50}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_52 = _legal_address_T_51 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_53 = _legal_address_T_52; // @[Parameters.scala:137:46]
wire _legal_address_T_54 = _legal_address_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_10 = _legal_address_T_54; // @[Parameters.scala:612:40]
wire [39:0] _GEN_5 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_55; // @[Parameters.scala:137:31]
assign _legal_address_T_55 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_10; // @[Parameters.scala:137:31]
assign _io_resp_w_T_10 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_10; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_10 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_10; // @[Parameters.scala:137:31]
assign _io_resp_al_T_10 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_10; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_10 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_49; // @[Parameters.scala:137:31]
assign _io_resp_x_T_49 = _GEN_5; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_15; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_15 = _GEN_5; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_56 = {1'h0, _legal_address_T_55}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_57 = _legal_address_T_56 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_58 = _legal_address_T_57; // @[Parameters.scala:137:46]
wire _legal_address_T_59 = _legal_address_T_58 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_11 = _legal_address_T_59; // @[Parameters.scala:612:40]
wire [39:0] _GEN_6 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2010000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_60; // @[Parameters.scala:137:31]
assign _legal_address_T_60 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_15; // @[Parameters.scala:137:31]
assign _io_resp_w_T_15 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_15; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_15 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_15; // @[Parameters.scala:137:31]
assign _io_resp_al_T_15 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_15; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_15 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_54; // @[Parameters.scala:137:31]
assign _io_resp_x_T_54 = _GEN_6; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_20; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_20 = _GEN_6; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_61 = {1'h0, _legal_address_T_60}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_62 = _legal_address_T_61 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_63 = _legal_address_T_62; // @[Parameters.scala:137:46]
wire _legal_address_T_64 = _legal_address_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_12 = _legal_address_T_64; // @[Parameters.scala:612:40]
wire [39:0] _GEN_7 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h8000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_65; // @[Parameters.scala:137:31]
assign _legal_address_T_65 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_23; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_23 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_20; // @[Parameters.scala:137:31]
assign _io_resp_w_T_20 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_20; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_20 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_20; // @[Parameters.scala:137:31]
assign _io_resp_al_T_20 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_20; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_20 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_15; // @[Parameters.scala:137:31]
assign _io_resp_x_T_15 = _GEN_7; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_51; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_51 = _GEN_7; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_66 = {1'h0, _legal_address_T_65}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_67 = _legal_address_T_66 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_68 = _legal_address_T_67; // @[Parameters.scala:137:46]
wire _legal_address_T_69 = _legal_address_T_68 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_13 = _legal_address_T_69; // @[Parameters.scala:612:40]
wire [39:0] _GEN_8 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'hC000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_70; // @[Parameters.scala:137:31]
assign _legal_address_T_70 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_15; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_15 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_25; // @[Parameters.scala:137:31]
assign _io_resp_w_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_25; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_25; // @[Parameters.scala:137:31]
assign _io_resp_al_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_25; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_59; // @[Parameters.scala:137:31]
assign _io_resp_x_T_59 = _GEN_8; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_25; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_25 = _GEN_8; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_71 = {1'h0, _legal_address_T_70}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_72 = _legal_address_T_71 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_73 = _legal_address_T_72; // @[Parameters.scala:137:46]
wire _legal_address_T_74 = _legal_address_T_73 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_14 = _legal_address_T_74; // @[Parameters.scala:612:40]
wire [39:0] _GEN_9 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10020000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_75; // @[Parameters.scala:137:31]
assign _legal_address_T_75 = _GEN_9; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_30; // @[Parameters.scala:137:31]
assign _io_resp_w_T_30 = _GEN_9; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_30; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_30 = _GEN_9; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_30; // @[Parameters.scala:137:31]
assign _io_resp_al_T_30 = _GEN_9; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_30; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_30 = _GEN_9; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_64; // @[Parameters.scala:137:31]
assign _io_resp_x_T_64 = _GEN_9; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_30; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_30 = _GEN_9; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_76 = {1'h0, _legal_address_T_75}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_77 = _legal_address_T_76 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_78 = _legal_address_T_77; // @[Parameters.scala:137:46]
wire _legal_address_T_79 = _legal_address_T_78 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_15 = _legal_address_T_79; // @[Parameters.scala:612:40]
wire [39:0] _GEN_10 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h80000000}; // @[PMA.scala:18:7]
wire [39:0] _legal_address_T_80; // @[Parameters.scala:137:31]
assign _legal_address_T_80 = _GEN_10; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_cacheable_T_28; // @[Parameters.scala:137:31]
assign _io_resp_cacheable_T_28 = _GEN_10; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_w_T_35; // @[Parameters.scala:137:31]
assign _io_resp_w_T_35 = _GEN_10; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_pp_T_35; // @[Parameters.scala:137:31]
assign _io_resp_pp_T_35 = _GEN_10; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_al_T_35; // @[Parameters.scala:137:31]
assign _io_resp_al_T_35 = _GEN_10; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_aa_T_35; // @[Parameters.scala:137:31]
assign _io_resp_aa_T_35 = _GEN_10; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_x_T_20; // @[Parameters.scala:137:31]
assign _io_resp_x_T_20 = _GEN_10; // @[Parameters.scala:137:31]
wire [39:0] _io_resp_eff_T_56; // @[Parameters.scala:137:31]
assign _io_resp_eff_T_56 = _GEN_10; // @[Parameters.scala:137:31]
wire [40:0] _legal_address_T_81 = {1'h0, _legal_address_T_80}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _legal_address_T_82 = _legal_address_T_81 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _legal_address_T_83 = _legal_address_T_82; // @[Parameters.scala:137:46]
wire _legal_address_T_84 = _legal_address_T_83 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _legal_address_WIRE_16 = _legal_address_T_84; // @[Parameters.scala:612:40]
wire _legal_address_T_85 = _legal_address_WIRE_0 | _legal_address_WIRE_1; // @[Parameters.scala:612:40]
wire _legal_address_T_86 = _legal_address_T_85 | _legal_address_WIRE_2; // @[Parameters.scala:612:40]
wire _legal_address_T_87 = _legal_address_T_86 | _legal_address_WIRE_3; // @[Parameters.scala:612:40]
wire _legal_address_T_88 = _legal_address_T_87 | _legal_address_WIRE_4; // @[Parameters.scala:612:40]
wire _legal_address_T_89 = _legal_address_T_88 | _legal_address_WIRE_5; // @[Parameters.scala:612:40]
wire _legal_address_T_90 = _legal_address_T_89 | _legal_address_WIRE_6; // @[Parameters.scala:612:40]
wire _legal_address_T_91 = _legal_address_T_90 | _legal_address_WIRE_7; // @[Parameters.scala:612:40]
wire _legal_address_T_92 = _legal_address_T_91 | _legal_address_WIRE_8; // @[Parameters.scala:612:40]
wire _legal_address_T_93 = _legal_address_T_92 | _legal_address_WIRE_9; // @[Parameters.scala:612:40]
wire _legal_address_T_94 = _legal_address_T_93 | _legal_address_WIRE_10; // @[Parameters.scala:612:40]
wire _legal_address_T_95 = _legal_address_T_94 | _legal_address_WIRE_11; // @[Parameters.scala:612:40]
wire _legal_address_T_96 = _legal_address_T_95 | _legal_address_WIRE_12; // @[Parameters.scala:612:40]
wire _legal_address_T_97 = _legal_address_T_96 | _legal_address_WIRE_13; // @[Parameters.scala:612:40]
wire _legal_address_T_98 = _legal_address_T_97 | _legal_address_WIRE_14; // @[Parameters.scala:612:40]
wire _legal_address_T_99 = _legal_address_T_98 | _legal_address_WIRE_15; // @[Parameters.scala:612:40]
wire legal_address = _legal_address_T_99 | _legal_address_WIRE_16; // @[Parameters.scala:612:40]
assign _io_resp_r_T_5 = legal_address; // @[PMA.scala:36:58, :39:19]
wire [40:0] _io_resp_cacheable_T_1 = {1'h0, _io_resp_cacheable_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_2 = _io_resp_cacheable_T_1 & 41'h8C020000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_3 = _io_resp_cacheable_T_2; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_4 = _io_resp_cacheable_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_cacheable_T_6 = {1'h0, _io_resp_cacheable_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_7 = _io_resp_cacheable_T_6 & 41'h8C031000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_8 = _io_resp_cacheable_T_7; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_9 = _io_resp_cacheable_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_cacheable_T_11 = {1'h0, _io_resp_cacheable_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_12 = _io_resp_cacheable_T_11 & 41'h8C030000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_13 = _io_resp_cacheable_T_12; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_14 = _io_resp_cacheable_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_cacheable_T_16 = {1'h0, _io_resp_cacheable_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_17 = _io_resp_cacheable_T_16 & 41'h8C000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_18 = _io_resp_cacheable_T_17; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_19 = _io_resp_cacheable_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_cacheable_T_20 = _io_resp_cacheable_T_4 | _io_resp_cacheable_T_9; // @[Parameters.scala:629:89]
wire _io_resp_cacheable_T_21 = _io_resp_cacheable_T_20 | _io_resp_cacheable_T_14; // @[Parameters.scala:629:89]
wire _io_resp_cacheable_T_22 = _io_resp_cacheable_T_21 | _io_resp_cacheable_T_19; // @[Parameters.scala:629:89]
wire [40:0] _io_resp_cacheable_T_24 = {1'h0, _io_resp_cacheable_T_23}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_25 = _io_resp_cacheable_T_24 & 41'h8C030000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_26 = _io_resp_cacheable_T_25; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_27 = _io_resp_cacheable_T_26 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_cacheable_T_29 = {1'h0, _io_resp_cacheable_T_28}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_cacheable_T_30 = _io_resp_cacheable_T_29 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_cacheable_T_31 = _io_resp_cacheable_T_30; // @[Parameters.scala:137:46]
wire _io_resp_cacheable_T_32 = _io_resp_cacheable_T_31 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_cacheable_T_33 = _io_resp_cacheable_T_27 | _io_resp_cacheable_T_32; // @[Parameters.scala:629:89]
wire _io_resp_cacheable_T_35 = _io_resp_cacheable_T_33; // @[Mux.scala:30:73]
wire _io_resp_cacheable_T_36 = _io_resp_cacheable_T_35; // @[Mux.scala:30:73]
wire _io_resp_cacheable_WIRE = _io_resp_cacheable_T_36; // @[Mux.scala:30:73]
assign _io_resp_cacheable_T_37 = legal_address & _io_resp_cacheable_WIRE; // @[Mux.scala:30:73]
assign io_resp_cacheable_0 = _io_resp_cacheable_T_37; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_r_T_1 = {1'h0, _io_resp_r_T}; // @[Parameters.scala:137:{31,41}]
assign io_resp_r_0 = _io_resp_r_T_5; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_w_T_1 = {1'h0, _io_resp_w_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_2 = _io_resp_w_T_1 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_3 = _io_resp_w_T_2; // @[Parameters.scala:137:46]
wire _io_resp_w_T_4 = _io_resp_w_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_6 = {1'h0, _io_resp_w_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_7 = _io_resp_w_T_6 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_8 = _io_resp_w_T_7; // @[Parameters.scala:137:46]
wire _io_resp_w_T_9 = _io_resp_w_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_11 = {1'h0, _io_resp_w_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_12 = _io_resp_w_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_13 = _io_resp_w_T_12; // @[Parameters.scala:137:46]
wire _io_resp_w_T_14 = _io_resp_w_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_16 = {1'h0, _io_resp_w_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_17 = _io_resp_w_T_16 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_18 = _io_resp_w_T_17; // @[Parameters.scala:137:46]
wire _io_resp_w_T_19 = _io_resp_w_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_21 = {1'h0, _io_resp_w_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_22 = _io_resp_w_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_23 = _io_resp_w_T_22; // @[Parameters.scala:137:46]
wire _io_resp_w_T_24 = _io_resp_w_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_26 = {1'h0, _io_resp_w_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_27 = _io_resp_w_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_28 = _io_resp_w_T_27; // @[Parameters.scala:137:46]
wire _io_resp_w_T_29 = _io_resp_w_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_31 = {1'h0, _io_resp_w_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_32 = _io_resp_w_T_31 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_33 = _io_resp_w_T_32; // @[Parameters.scala:137:46]
wire _io_resp_w_T_34 = _io_resp_w_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_w_T_36 = {1'h0, _io_resp_w_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_37 = _io_resp_w_T_36 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_38 = _io_resp_w_T_37; // @[Parameters.scala:137:46]
wire _io_resp_w_T_39 = _io_resp_w_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_w_T_40 = _io_resp_w_T_4 | _io_resp_w_T_9; // @[Parameters.scala:629:89]
wire _io_resp_w_T_41 = _io_resp_w_T_40 | _io_resp_w_T_14; // @[Parameters.scala:629:89]
wire _io_resp_w_T_42 = _io_resp_w_T_41 | _io_resp_w_T_19; // @[Parameters.scala:629:89]
wire _io_resp_w_T_43 = _io_resp_w_T_42 | _io_resp_w_T_24; // @[Parameters.scala:629:89]
wire _io_resp_w_T_44 = _io_resp_w_T_43 | _io_resp_w_T_29; // @[Parameters.scala:629:89]
wire _io_resp_w_T_45 = _io_resp_w_T_44 | _io_resp_w_T_34; // @[Parameters.scala:629:89]
wire _io_resp_w_T_46 = _io_resp_w_T_45 | _io_resp_w_T_39; // @[Parameters.scala:629:89]
wire _io_resp_w_T_52 = _io_resp_w_T_46; // @[Mux.scala:30:73]
wire [40:0] _io_resp_w_T_48 = {1'h0, _io_resp_w_T_47}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_w_T_49 = _io_resp_w_T_48 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_w_T_50 = _io_resp_w_T_49; // @[Parameters.scala:137:46]
wire _io_resp_w_T_51 = _io_resp_w_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_w_T_54 = _io_resp_w_T_52; // @[Mux.scala:30:73]
wire _io_resp_w_WIRE = _io_resp_w_T_54; // @[Mux.scala:30:73]
assign _io_resp_w_T_55 = legal_address & _io_resp_w_WIRE; // @[Mux.scala:30:73]
assign io_resp_w_0 = _io_resp_w_T_55; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_pp_T_1 = {1'h0, _io_resp_pp_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_2 = _io_resp_pp_T_1 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_3 = _io_resp_pp_T_2; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_4 = _io_resp_pp_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_6 = {1'h0, _io_resp_pp_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_7 = _io_resp_pp_T_6 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_8 = _io_resp_pp_T_7; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_9 = _io_resp_pp_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_11 = {1'h0, _io_resp_pp_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_12 = _io_resp_pp_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_13 = _io_resp_pp_T_12; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_14 = _io_resp_pp_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_16 = {1'h0, _io_resp_pp_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_17 = _io_resp_pp_T_16 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_18 = _io_resp_pp_T_17; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_19 = _io_resp_pp_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_21 = {1'h0, _io_resp_pp_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_22 = _io_resp_pp_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_23 = _io_resp_pp_T_22; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_24 = _io_resp_pp_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_26 = {1'h0, _io_resp_pp_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_27 = _io_resp_pp_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_28 = _io_resp_pp_T_27; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_29 = _io_resp_pp_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_31 = {1'h0, _io_resp_pp_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_32 = _io_resp_pp_T_31 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_33 = _io_resp_pp_T_32; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_34 = _io_resp_pp_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_pp_T_36 = {1'h0, _io_resp_pp_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_37 = _io_resp_pp_T_36 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_38 = _io_resp_pp_T_37; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_39 = _io_resp_pp_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_pp_T_40 = _io_resp_pp_T_4 | _io_resp_pp_T_9; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_41 = _io_resp_pp_T_40 | _io_resp_pp_T_14; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_42 = _io_resp_pp_T_41 | _io_resp_pp_T_19; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_43 = _io_resp_pp_T_42 | _io_resp_pp_T_24; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_44 = _io_resp_pp_T_43 | _io_resp_pp_T_29; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_45 = _io_resp_pp_T_44 | _io_resp_pp_T_34; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_46 = _io_resp_pp_T_45 | _io_resp_pp_T_39; // @[Parameters.scala:629:89]
wire _io_resp_pp_T_52 = _io_resp_pp_T_46; // @[Mux.scala:30:73]
wire [40:0] _io_resp_pp_T_48 = {1'h0, _io_resp_pp_T_47}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_pp_T_49 = _io_resp_pp_T_48 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_pp_T_50 = _io_resp_pp_T_49; // @[Parameters.scala:137:46]
wire _io_resp_pp_T_51 = _io_resp_pp_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_pp_T_54 = _io_resp_pp_T_52; // @[Mux.scala:30:73]
wire _io_resp_pp_WIRE = _io_resp_pp_T_54; // @[Mux.scala:30:73]
assign _io_resp_pp_T_55 = legal_address & _io_resp_pp_WIRE; // @[Mux.scala:30:73]
assign io_resp_pp_0 = _io_resp_pp_T_55; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_al_T_1 = {1'h0, _io_resp_al_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_2 = _io_resp_al_T_1 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_3 = _io_resp_al_T_2; // @[Parameters.scala:137:46]
wire _io_resp_al_T_4 = _io_resp_al_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_6 = {1'h0, _io_resp_al_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_7 = _io_resp_al_T_6 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_8 = _io_resp_al_T_7; // @[Parameters.scala:137:46]
wire _io_resp_al_T_9 = _io_resp_al_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_11 = {1'h0, _io_resp_al_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_12 = _io_resp_al_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_13 = _io_resp_al_T_12; // @[Parameters.scala:137:46]
wire _io_resp_al_T_14 = _io_resp_al_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_16 = {1'h0, _io_resp_al_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_17 = _io_resp_al_T_16 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_18 = _io_resp_al_T_17; // @[Parameters.scala:137:46]
wire _io_resp_al_T_19 = _io_resp_al_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_21 = {1'h0, _io_resp_al_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_22 = _io_resp_al_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_23 = _io_resp_al_T_22; // @[Parameters.scala:137:46]
wire _io_resp_al_T_24 = _io_resp_al_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_26 = {1'h0, _io_resp_al_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_27 = _io_resp_al_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_28 = _io_resp_al_T_27; // @[Parameters.scala:137:46]
wire _io_resp_al_T_29 = _io_resp_al_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_31 = {1'h0, _io_resp_al_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_32 = _io_resp_al_T_31 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_33 = _io_resp_al_T_32; // @[Parameters.scala:137:46]
wire _io_resp_al_T_34 = _io_resp_al_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_al_T_36 = {1'h0, _io_resp_al_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_37 = _io_resp_al_T_36 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_38 = _io_resp_al_T_37; // @[Parameters.scala:137:46]
wire _io_resp_al_T_39 = _io_resp_al_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_al_T_40 = _io_resp_al_T_4 | _io_resp_al_T_9; // @[Parameters.scala:629:89]
wire _io_resp_al_T_41 = _io_resp_al_T_40 | _io_resp_al_T_14; // @[Parameters.scala:629:89]
wire _io_resp_al_T_42 = _io_resp_al_T_41 | _io_resp_al_T_19; // @[Parameters.scala:629:89]
wire _io_resp_al_T_43 = _io_resp_al_T_42 | _io_resp_al_T_24; // @[Parameters.scala:629:89]
wire _io_resp_al_T_44 = _io_resp_al_T_43 | _io_resp_al_T_29; // @[Parameters.scala:629:89]
wire _io_resp_al_T_45 = _io_resp_al_T_44 | _io_resp_al_T_34; // @[Parameters.scala:629:89]
wire _io_resp_al_T_46 = _io_resp_al_T_45 | _io_resp_al_T_39; // @[Parameters.scala:629:89]
wire _io_resp_al_T_52 = _io_resp_al_T_46; // @[Mux.scala:30:73]
wire [40:0] _io_resp_al_T_48 = {1'h0, _io_resp_al_T_47}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_al_T_49 = _io_resp_al_T_48 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_al_T_50 = _io_resp_al_T_49; // @[Parameters.scala:137:46]
wire _io_resp_al_T_51 = _io_resp_al_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_al_T_54 = _io_resp_al_T_52; // @[Mux.scala:30:73]
wire _io_resp_al_WIRE = _io_resp_al_T_54; // @[Mux.scala:30:73]
assign _io_resp_al_T_55 = legal_address & _io_resp_al_WIRE; // @[Mux.scala:30:73]
assign io_resp_al_0 = _io_resp_al_T_55; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_aa_T_1 = {1'h0, _io_resp_aa_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_2 = _io_resp_aa_T_1 & 41'hFFFD8000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_3 = _io_resp_aa_T_2; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_4 = _io_resp_aa_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_6 = {1'h0, _io_resp_aa_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_7 = _io_resp_aa_T_6 & 41'hFFFE9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_8 = _io_resp_aa_T_7; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_9 = _io_resp_aa_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_11 = {1'h0, _io_resp_aa_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_12 = _io_resp_aa_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_13 = _io_resp_aa_T_12; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_14 = _io_resp_aa_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_16 = {1'h0, _io_resp_aa_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_17 = _io_resp_aa_T_16 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_18 = _io_resp_aa_T_17; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_19 = _io_resp_aa_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_21 = {1'h0, _io_resp_aa_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_22 = _io_resp_aa_T_21 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_23 = _io_resp_aa_T_22; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_24 = _io_resp_aa_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_26 = {1'h0, _io_resp_aa_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_27 = _io_resp_aa_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_28 = _io_resp_aa_T_27; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_29 = _io_resp_aa_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_31 = {1'h0, _io_resp_aa_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_32 = _io_resp_aa_T_31 & 41'hFFFF9000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_33 = _io_resp_aa_T_32; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_34 = _io_resp_aa_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_aa_T_36 = {1'h0, _io_resp_aa_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_37 = _io_resp_aa_T_36 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_38 = _io_resp_aa_T_37; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_39 = _io_resp_aa_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_aa_T_40 = _io_resp_aa_T_4 | _io_resp_aa_T_9; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_41 = _io_resp_aa_T_40 | _io_resp_aa_T_14; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_42 = _io_resp_aa_T_41 | _io_resp_aa_T_19; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_43 = _io_resp_aa_T_42 | _io_resp_aa_T_24; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_44 = _io_resp_aa_T_43 | _io_resp_aa_T_29; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_45 = _io_resp_aa_T_44 | _io_resp_aa_T_34; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_46 = _io_resp_aa_T_45 | _io_resp_aa_T_39; // @[Parameters.scala:629:89]
wire _io_resp_aa_T_52 = _io_resp_aa_T_46; // @[Mux.scala:30:73]
wire [40:0] _io_resp_aa_T_48 = {1'h0, _io_resp_aa_T_47}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_aa_T_49 = _io_resp_aa_T_48 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_aa_T_50 = _io_resp_aa_T_49; // @[Parameters.scala:137:46]
wire _io_resp_aa_T_51 = _io_resp_aa_T_50 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_aa_T_54 = _io_resp_aa_T_52; // @[Mux.scala:30:73]
wire _io_resp_aa_WIRE = _io_resp_aa_T_54; // @[Mux.scala:30:73]
assign _io_resp_aa_T_55 = legal_address & _io_resp_aa_WIRE; // @[Mux.scala:30:73]
assign io_resp_aa_0 = _io_resp_aa_T_55; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_x_T_1 = {1'h0, _io_resp_x_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_2 = _io_resp_x_T_1 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_3 = _io_resp_x_T_2; // @[Parameters.scala:137:46]
wire _io_resp_x_T_4 = _io_resp_x_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_6 = {1'h0, _io_resp_x_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_7 = _io_resp_x_T_6 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_8 = _io_resp_x_T_7; // @[Parameters.scala:137:46]
wire _io_resp_x_T_9 = _io_resp_x_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_11 = {1'h0, _io_resp_x_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_12 = _io_resp_x_T_11 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_13 = _io_resp_x_T_12; // @[Parameters.scala:137:46]
wire _io_resp_x_T_14 = _io_resp_x_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_16 = {1'h0, _io_resp_x_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_17 = _io_resp_x_T_16 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_18 = _io_resp_x_T_17; // @[Parameters.scala:137:46]
wire _io_resp_x_T_19 = _io_resp_x_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_21 = {1'h0, _io_resp_x_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_22 = _io_resp_x_T_21 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_23 = _io_resp_x_T_22; // @[Parameters.scala:137:46]
wire _io_resp_x_T_24 = _io_resp_x_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_x_T_25 = _io_resp_x_T_4 | _io_resp_x_T_9; // @[Parameters.scala:629:89]
wire _io_resp_x_T_26 = _io_resp_x_T_25 | _io_resp_x_T_14; // @[Parameters.scala:629:89]
wire _io_resp_x_T_27 = _io_resp_x_T_26 | _io_resp_x_T_19; // @[Parameters.scala:629:89]
wire _io_resp_x_T_28 = _io_resp_x_T_27 | _io_resp_x_T_24; // @[Parameters.scala:629:89]
wire _io_resp_x_T_76 = _io_resp_x_T_28; // @[Mux.scala:30:73]
wire [40:0] _io_resp_x_T_30 = {1'h0, _io_resp_x_T_29}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_31 = _io_resp_x_T_30 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_32 = _io_resp_x_T_31; // @[Parameters.scala:137:46]
wire _io_resp_x_T_33 = _io_resp_x_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_35 = {1'h0, _io_resp_x_T_34}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_36 = _io_resp_x_T_35 & 41'hFFFFC000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_37 = _io_resp_x_T_36; // @[Parameters.scala:137:46]
wire _io_resp_x_T_38 = _io_resp_x_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_40 = {1'h0, _io_resp_x_T_39}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_41 = _io_resp_x_T_40 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_42 = _io_resp_x_T_41; // @[Parameters.scala:137:46]
wire _io_resp_x_T_43 = _io_resp_x_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_45 = {1'h0, _io_resp_x_T_44}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_46 = _io_resp_x_T_45 & 41'hFFFEF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_47 = _io_resp_x_T_46; // @[Parameters.scala:137:46]
wire _io_resp_x_T_48 = _io_resp_x_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_50 = {1'h0, _io_resp_x_T_49}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_51 = _io_resp_x_T_50 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_52 = _io_resp_x_T_51; // @[Parameters.scala:137:46]
wire _io_resp_x_T_53 = _io_resp_x_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_55 = {1'h0, _io_resp_x_T_54}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_56 = _io_resp_x_T_55 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_57 = _io_resp_x_T_56; // @[Parameters.scala:137:46]
wire _io_resp_x_T_58 = _io_resp_x_T_57 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_60 = {1'h0, _io_resp_x_T_59}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_61 = _io_resp_x_T_60 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_62 = _io_resp_x_T_61; // @[Parameters.scala:137:46]
wire _io_resp_x_T_63 = _io_resp_x_T_62 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_x_T_65 = {1'h0, _io_resp_x_T_64}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_x_T_66 = _io_resp_x_T_65 & 41'hFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_x_T_67 = _io_resp_x_T_66; // @[Parameters.scala:137:46]
wire _io_resp_x_T_68 = _io_resp_x_T_67 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_x_T_69 = _io_resp_x_T_33 | _io_resp_x_T_38; // @[Parameters.scala:629:89]
wire _io_resp_x_T_70 = _io_resp_x_T_69 | _io_resp_x_T_43; // @[Parameters.scala:629:89]
wire _io_resp_x_T_71 = _io_resp_x_T_70 | _io_resp_x_T_48; // @[Parameters.scala:629:89]
wire _io_resp_x_T_72 = _io_resp_x_T_71 | _io_resp_x_T_53; // @[Parameters.scala:629:89]
wire _io_resp_x_T_73 = _io_resp_x_T_72 | _io_resp_x_T_58; // @[Parameters.scala:629:89]
wire _io_resp_x_T_74 = _io_resp_x_T_73 | _io_resp_x_T_63; // @[Parameters.scala:629:89]
wire _io_resp_x_T_75 = _io_resp_x_T_74 | _io_resp_x_T_68; // @[Parameters.scala:629:89]
wire _io_resp_x_T_78 = _io_resp_x_T_76; // @[Mux.scala:30:73]
wire _io_resp_x_WIRE = _io_resp_x_T_78; // @[Mux.scala:30:73]
assign _io_resp_x_T_79 = legal_address & _io_resp_x_WIRE; // @[Mux.scala:30:73]
assign io_resp_x_0 = _io_resp_x_T_79; // @[PMA.scala:18:7, :39:19]
wire [40:0] _io_resp_eff_T_1 = {1'h0, _io_resp_eff_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_2 = _io_resp_eff_T_1 & 41'hFFFFA000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_3 = _io_resp_eff_T_2; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_4 = _io_resp_eff_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_6 = {1'h0, _io_resp_eff_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_7 = _io_resp_eff_T_6 & 41'hFFFF8000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_8 = _io_resp_eff_T_7; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_9 = _io_resp_eff_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_11 = {1'h0, _io_resp_eff_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_12 = _io_resp_eff_T_11 & 41'hFFFEB000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_13 = _io_resp_eff_T_12; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_14 = _io_resp_eff_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_16 = {1'h0, _io_resp_eff_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_17 = _io_resp_eff_T_16 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_18 = _io_resp_eff_T_17; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_19 = _io_resp_eff_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_21 = {1'h0, _io_resp_eff_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_22 = _io_resp_eff_T_21 & 41'hFFFFB000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_23 = _io_resp_eff_T_22; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_24 = _io_resp_eff_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_26 = {1'h0, _io_resp_eff_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_27 = _io_resp_eff_T_26 & 41'hFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_28 = _io_resp_eff_T_27; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_29 = _io_resp_eff_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_31 = {1'h0, _io_resp_eff_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_32 = _io_resp_eff_T_31 & 41'hFFFFB000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_33 = _io_resp_eff_T_32; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_34 = _io_resp_eff_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_eff_T_35 = _io_resp_eff_T_4 | _io_resp_eff_T_9; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_36 = _io_resp_eff_T_35 | _io_resp_eff_T_14; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_37 = _io_resp_eff_T_36 | _io_resp_eff_T_19; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_38 = _io_resp_eff_T_37 | _io_resp_eff_T_24; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_39 = _io_resp_eff_T_38 | _io_resp_eff_T_29; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_40 = _io_resp_eff_T_39 | _io_resp_eff_T_34; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_64 = _io_resp_eff_T_40; // @[Mux.scala:30:73]
wire [40:0] _io_resp_eff_T_42 = {1'h0, _io_resp_eff_T_41}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_43 = _io_resp_eff_T_42 & 41'hFFFFB000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_44 = _io_resp_eff_T_43; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_45 = _io_resp_eff_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_47 = {1'h0, _io_resp_eff_T_46}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_48 = _io_resp_eff_T_47 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_49 = _io_resp_eff_T_48; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_50 = _io_resp_eff_T_49 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_52 = {1'h0, _io_resp_eff_T_51}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_53 = _io_resp_eff_T_52 & 41'hFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_54 = _io_resp_eff_T_53; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_55 = _io_resp_eff_T_54 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _io_resp_eff_T_57 = {1'h0, _io_resp_eff_T_56}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _io_resp_eff_T_58 = _io_resp_eff_T_57 & 41'hF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _io_resp_eff_T_59 = _io_resp_eff_T_58; // @[Parameters.scala:137:46]
wire _io_resp_eff_T_60 = _io_resp_eff_T_59 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _io_resp_eff_T_61 = _io_resp_eff_T_45 | _io_resp_eff_T_50; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_62 = _io_resp_eff_T_61 | _io_resp_eff_T_55; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_63 = _io_resp_eff_T_62 | _io_resp_eff_T_60; // @[Parameters.scala:629:89]
wire _io_resp_eff_T_66 = _io_resp_eff_T_64; // @[Mux.scala:30:73]
wire _io_resp_eff_WIRE = _io_resp_eff_T_66; // @[Mux.scala:30:73]
assign _io_resp_eff_T_67 = legal_address & _io_resp_eff_WIRE; // @[Mux.scala:30:73]
assign io_resp_eff_0 = _io_resp_eff_T_67; // @[PMA.scala:18:7, :39:19]
assign io_resp_cacheable = io_resp_cacheable_0; // @[PMA.scala:18:7]
assign io_resp_r = io_resp_r_0; // @[PMA.scala:18:7]
assign io_resp_w = io_resp_w_0; // @[PMA.scala:18:7]
assign io_resp_pp = io_resp_pp_0; // @[PMA.scala:18:7]
assign io_resp_al = io_resp_al_0; // @[PMA.scala:18:7]
assign io_resp_aa = io_resp_aa_0; // @[PMA.scala:18:7]
assign io_resp_x = io_resp_x_0; // @[PMA.scala:18:7]
assign io_resp_eff = io_resp_eff_0; // @[PMA.scala:18:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e8_s24_36 :
output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>}
inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_36
connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc
connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc
connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig
connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp
connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign
connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero
connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf
connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN
connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundAnyRawFNToRecFN.io.out
connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags | module RoundRawFNToRecFN_e8_s24_36( // @[RoundAnyRawFNToRecFN.scala:295:5]
input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16]
input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [9:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16]
input [26:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [32:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16]
output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16]
);
wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [9:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [26:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [2:0] io_roundingMode = 3'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15]
wire [32:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
RoundAnyRawFNToRecFN_ie8_is26_oe8_os24_36 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15]
.io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[RoundAnyRawFNToRecFN.scala:310:15]
assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_239 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_239( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn, // @[package.scala:268:18]
output io_y_u, // @[package.scala:268:18]
output io_y_ae_ptw, // @[package.scala:268:18]
output io_y_ae_final, // @[package.scala:268:18]
output io_y_ae_stage2, // @[package.scala:268:18]
output io_y_pf, // @[package.scala:268:18]
output io_y_gf, // @[package.scala:268:18]
output io_y_sw, // @[package.scala:268:18]
output io_y_sx, // @[package.scala:268:18]
output io_y_sr, // @[package.scala:268:18]
output io_y_hw, // @[package.scala:268:18]
output io_y_hx, // @[package.scala:268:18]
output io_y_hr, // @[package.scala:268:18]
output io_y_pw, // @[package.scala:268:18]
output io_y_px, // @[package.scala:268:18]
output io_y_pr, // @[package.scala:268:18]
output io_y_ppp, // @[package.scala:268:18]
output io_y_pal, // @[package.scala:268:18]
output io_y_paa, // @[package.scala:268:18]
output io_y_eff, // @[package.scala:268:18]
output io_y_c // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
assign io_y_u = io_y_u_0; // @[package.scala:267:30]
assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30]
assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30]
assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30]
assign io_y_pf = io_y_pf_0; // @[package.scala:267:30]
assign io_y_gf = io_y_gf_0; // @[package.scala:267:30]
assign io_y_sw = io_y_sw_0; // @[package.scala:267:30]
assign io_y_sx = io_y_sx_0; // @[package.scala:267:30]
assign io_y_sr = io_y_sr_0; // @[package.scala:267:30]
assign io_y_hw = io_y_hw_0; // @[package.scala:267:30]
assign io_y_hx = io_y_hx_0; // @[package.scala:267:30]
assign io_y_hr = io_y_hr_0; // @[package.scala:267:30]
assign io_y_pw = io_y_pw_0; // @[package.scala:267:30]
assign io_y_px = io_y_px_0; // @[package.scala:267:30]
assign io_y_pr = io_y_pr_0; // @[package.scala:267:30]
assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30]
assign io_y_pal = io_y_pal_0; // @[package.scala:267:30]
assign io_y_paa = io_y_paa_0; // @[package.scala:267:30]
assign io_y_eff = io_y_eff_0; // @[package.scala:267:30]
assign io_y_c = io_y_c_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Tile_68 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_324
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_68( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0 // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
PE_324 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module SourceB :
input clock : Clock
input reset : Reset
output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}}, b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}}
regreset remain : UInt<1>, clock, reset, UInt<1>(0h0)
wire remain_set : UInt<1>
connect remain_set, UInt<1>(0h0)
wire remain_clr : UInt<1>
connect remain_clr, UInt<1>(0h0)
node _remain_T = or(remain, remain_set)
node _remain_T_1 = not(remain_clr)
node _remain_T_2 = and(_remain_T, _remain_T_1)
connect remain, _remain_T_2
node busy = orr(remain)
node todo = mux(busy, remain, io.req.bits.clients)
node _next_T = bits(todo, 0, 0)
node _next_T_1 = shl(_next_T, 1)
node _next_T_2 = not(_next_T_1)
node next = and(_next_T_2, todo)
node _T = eq(io.req.valid, UInt<1>(0h0))
node _T_1 = neq(io.req.bits.clients, UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
node _T_3 = asUInt(reset)
node _T_4 = eq(_T_3, UInt<1>(0h0))
when _T_4 :
node _T_5 = eq(_T_2, UInt<1>(0h0))
when _T_5 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at SourceB.scala:59 assert (!io.req.valid || io.req.bits.clients =/= 0.U)\n") : printf
assert(clock, _T_2, UInt<1>(0h1), "") : assert
node _io_req_ready_T = eq(busy, UInt<1>(0h0))
connect io.req.ready, _io_req_ready_T
node _T_6 = and(io.req.ready, io.req.valid)
when _T_6 :
connect remain_set, io.req.bits.clients
wire b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}
connect io.b, b
node _b_valid_T = or(busy, io.req.valid)
connect b.valid, _b_valid_T
node _T_7 = and(b.ready, b.valid)
when _T_7 :
connect remain_clr, next
node _T_8 = eq(b.ready, UInt<1>(0h0))
node _T_9 = and(b.valid, _T_8)
node _tag_T = eq(busy, UInt<1>(0h0))
node _tag_T_1 = and(io.req.ready, io.req.valid)
reg tag_r : UInt<13>, clock
when _tag_T_1 :
connect tag_r, io.req.bits.tag
node tag = mux(_tag_T, io.req.bits.tag, tag_r)
node _set_T = eq(busy, UInt<1>(0h0))
node _set_T_1 = and(io.req.ready, io.req.valid)
reg set_r : UInt<10>, clock
when _set_T_1 :
connect set_r, io.req.bits.set
node set = mux(_set_T, io.req.bits.set, set_r)
node _param_T = eq(busy, UInt<1>(0h0))
node _param_T_1 = and(io.req.ready, io.req.valid)
reg param_r : UInt<3>, clock
when _param_T_1 :
connect param_r, io.req.bits.param
node param = mux(_param_T, io.req.bits.param, param_r)
connect b.bits.opcode, UInt<3>(0h6)
connect b.bits.param, param
connect b.bits.size, UInt<3>(0h6)
node _b_bits_source_T = bits(next, 0, 0)
connect b.bits.source, UInt<6>(0h20)
node b_bits_address_base_y = or(tag, UInt<13>(0h0))
node _b_bits_address_base_T = shr(b_bits_address_base_y, 13)
node _b_bits_address_base_T_1 = eq(_b_bits_address_base_T, UInt<1>(0h0))
node _b_bits_address_base_T_2 = asUInt(reset)
node _b_bits_address_base_T_3 = eq(_b_bits_address_base_T_2, UInt<1>(0h0))
when _b_bits_address_base_T_3 :
node _b_bits_address_base_T_4 = eq(_b_bits_address_base_T_1, UInt<1>(0h0))
when _b_bits_address_base_T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : b_bits_address_base_printf
assert(clock, _b_bits_address_base_T_1, UInt<1>(0h1), "") : b_bits_address_base_assert
node _b_bits_address_base_T_5 = bits(b_bits_address_base_y, 12, 0)
node b_bits_address_base_y_1 = or(set, UInt<10>(0h0))
node _b_bits_address_base_T_6 = shr(b_bits_address_base_y_1, 10)
node _b_bits_address_base_T_7 = eq(_b_bits_address_base_T_6, UInt<1>(0h0))
node _b_bits_address_base_T_8 = asUInt(reset)
node _b_bits_address_base_T_9 = eq(_b_bits_address_base_T_8, UInt<1>(0h0))
when _b_bits_address_base_T_9 :
node _b_bits_address_base_T_10 = eq(_b_bits_address_base_T_7, UInt<1>(0h0))
when _b_bits_address_base_T_10 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : b_bits_address_base_printf_1
assert(clock, _b_bits_address_base_T_7, UInt<1>(0h1), "") : b_bits_address_base_assert_1
node _b_bits_address_base_T_11 = bits(b_bits_address_base_y_1, 9, 0)
node b_bits_address_base_y_2 = or(UInt<1>(0h0), UInt<6>(0h0))
node _b_bits_address_base_T_12 = shr(b_bits_address_base_y_2, 6)
node _b_bits_address_base_T_13 = eq(_b_bits_address_base_T_12, UInt<1>(0h0))
node _b_bits_address_base_T_14 = asUInt(reset)
node _b_bits_address_base_T_15 = eq(_b_bits_address_base_T_14, UInt<1>(0h0))
when _b_bits_address_base_T_15 :
node _b_bits_address_base_T_16 = eq(_b_bits_address_base_T_13, UInt<1>(0h0))
when _b_bits_address_base_T_16 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Parameters.scala:222 assert (y >> width === 0.U)\n") : b_bits_address_base_printf_2
assert(clock, _b_bits_address_base_T_13, UInt<1>(0h1), "") : b_bits_address_base_assert_2
node _b_bits_address_base_T_17 = bits(b_bits_address_base_y_2, 5, 0)
node b_bits_address_base_hi = cat(_b_bits_address_base_T_5, _b_bits_address_base_T_11)
node b_bits_address_base = cat(b_bits_address_base_hi, _b_bits_address_base_T_17)
node _b_bits_address_T = bits(b_bits_address_base, 0, 0)
node _b_bits_address_T_1 = bits(b_bits_address_base, 1, 1)
node _b_bits_address_T_2 = bits(b_bits_address_base, 2, 2)
node _b_bits_address_T_3 = bits(b_bits_address_base, 3, 3)
node _b_bits_address_T_4 = bits(b_bits_address_base, 4, 4)
node _b_bits_address_T_5 = bits(b_bits_address_base, 5, 5)
node _b_bits_address_T_6 = bits(b_bits_address_base, 6, 6)
node _b_bits_address_T_7 = bits(b_bits_address_base, 7, 7)
node _b_bits_address_T_8 = bits(b_bits_address_base, 8, 8)
node _b_bits_address_T_9 = bits(b_bits_address_base, 9, 9)
node _b_bits_address_T_10 = bits(b_bits_address_base, 10, 10)
node _b_bits_address_T_11 = bits(b_bits_address_base, 11, 11)
node _b_bits_address_T_12 = bits(b_bits_address_base, 12, 12)
node _b_bits_address_T_13 = bits(b_bits_address_base, 13, 13)
node _b_bits_address_T_14 = bits(b_bits_address_base, 14, 14)
node _b_bits_address_T_15 = bits(b_bits_address_base, 15, 15)
node _b_bits_address_T_16 = bits(b_bits_address_base, 16, 16)
node _b_bits_address_T_17 = bits(b_bits_address_base, 17, 17)
node _b_bits_address_T_18 = bits(b_bits_address_base, 18, 18)
node _b_bits_address_T_19 = bits(b_bits_address_base, 19, 19)
node _b_bits_address_T_20 = bits(b_bits_address_base, 20, 20)
node _b_bits_address_T_21 = bits(b_bits_address_base, 21, 21)
node _b_bits_address_T_22 = bits(b_bits_address_base, 22, 22)
node _b_bits_address_T_23 = bits(b_bits_address_base, 23, 23)
node _b_bits_address_T_24 = bits(b_bits_address_base, 24, 24)
node _b_bits_address_T_25 = bits(b_bits_address_base, 25, 25)
node _b_bits_address_T_26 = bits(b_bits_address_base, 26, 26)
node _b_bits_address_T_27 = bits(b_bits_address_base, 27, 27)
node _b_bits_address_T_28 = bits(b_bits_address_base, 28, 28)
node b_bits_address_lo_lo_lo_lo = cat(_b_bits_address_T_1, _b_bits_address_T)
node b_bits_address_lo_lo_lo_hi = cat(_b_bits_address_T_3, _b_bits_address_T_2)
node b_bits_address_lo_lo_lo = cat(b_bits_address_lo_lo_lo_hi, b_bits_address_lo_lo_lo_lo)
node b_bits_address_lo_lo_hi_lo = cat(_b_bits_address_T_5, _b_bits_address_T_4)
node b_bits_address_lo_lo_hi_hi = cat(_b_bits_address_T_7, _b_bits_address_T_6)
node b_bits_address_lo_lo_hi = cat(b_bits_address_lo_lo_hi_hi, b_bits_address_lo_lo_hi_lo)
node b_bits_address_lo_lo = cat(b_bits_address_lo_lo_hi, b_bits_address_lo_lo_lo)
node b_bits_address_lo_hi_lo_lo = cat(_b_bits_address_T_9, _b_bits_address_T_8)
node b_bits_address_lo_hi_lo_hi = cat(_b_bits_address_T_11, _b_bits_address_T_10)
node b_bits_address_lo_hi_lo = cat(b_bits_address_lo_hi_lo_hi, b_bits_address_lo_hi_lo_lo)
node b_bits_address_lo_hi_hi_lo = cat(_b_bits_address_T_13, _b_bits_address_T_12)
node b_bits_address_lo_hi_hi_hi = cat(_b_bits_address_T_15, _b_bits_address_T_14)
node b_bits_address_lo_hi_hi = cat(b_bits_address_lo_hi_hi_hi, b_bits_address_lo_hi_hi_lo)
node b_bits_address_lo_hi = cat(b_bits_address_lo_hi_hi, b_bits_address_lo_hi_lo)
node b_bits_address_lo = cat(b_bits_address_lo_hi, b_bits_address_lo_lo)
node b_bits_address_hi_lo_lo_lo = cat(_b_bits_address_T_17, _b_bits_address_T_16)
node b_bits_address_hi_lo_lo_hi = cat(_b_bits_address_T_19, _b_bits_address_T_18)
node b_bits_address_hi_lo_lo = cat(b_bits_address_hi_lo_lo_hi, b_bits_address_hi_lo_lo_lo)
node b_bits_address_hi_lo_hi_lo = cat(_b_bits_address_T_21, _b_bits_address_T_20)
node b_bits_address_hi_lo_hi_hi = cat(_b_bits_address_T_23, _b_bits_address_T_22)
node b_bits_address_hi_lo_hi = cat(b_bits_address_hi_lo_hi_hi, b_bits_address_hi_lo_hi_lo)
node b_bits_address_hi_lo = cat(b_bits_address_hi_lo_hi, b_bits_address_hi_lo_lo)
node b_bits_address_hi_hi_lo_lo = cat(_b_bits_address_T_25, _b_bits_address_T_24)
node b_bits_address_hi_hi_lo_hi = cat(_b_bits_address_T_27, _b_bits_address_T_26)
node b_bits_address_hi_hi_lo = cat(b_bits_address_hi_hi_lo_hi, b_bits_address_hi_hi_lo_lo)
node b_bits_address_hi_hi_hi_lo = cat(UInt<1>(0h0), UInt<1>(0h0))
node b_bits_address_hi_hi_hi_hi = cat(_b_bits_address_T_28, UInt<1>(0h0))
node b_bits_address_hi_hi_hi = cat(b_bits_address_hi_hi_hi_hi, b_bits_address_hi_hi_hi_lo)
node b_bits_address_hi_hi = cat(b_bits_address_hi_hi_hi, b_bits_address_hi_hi_lo)
node b_bits_address_hi = cat(b_bits_address_hi_hi, b_bits_address_hi_lo)
node _b_bits_address_T_29 = cat(b_bits_address_hi, b_bits_address_lo)
connect b.bits.address, _b_bits_address_T_29
node _b_bits_mask_T = not(UInt<8>(0h0))
connect b.bits.mask, _b_bits_mask_T
connect b.bits.data, UInt<1>(0h0)
connect b.bits.corrupt, UInt<1>(0h0) | module SourceB( // @[SourceB.scala:33:7]
input clock, // @[SourceB.scala:33:7]
input reset, // @[SourceB.scala:33:7]
output io_req_ready, // @[SourceB.scala:35:14]
input io_req_valid, // @[SourceB.scala:35:14]
input [2:0] io_req_bits_param, // @[SourceB.scala:35:14]
input [12:0] io_req_bits_tag, // @[SourceB.scala:35:14]
input [9:0] io_req_bits_set, // @[SourceB.scala:35:14]
input io_req_bits_clients, // @[SourceB.scala:35:14]
input io_b_ready, // @[SourceB.scala:35:14]
output io_b_valid, // @[SourceB.scala:35:14]
output [1:0] io_b_bits_param, // @[SourceB.scala:35:14]
output [31:0] io_b_bits_address // @[SourceB.scala:35:14]
);
reg busy; // @[SourceB.scala:46:25] |
Generate the Verilog code corresponding to this FIRRTL code module Tile_54 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_310
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_54( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0 // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
PE_310 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Tile_8 :
input clock : Clock
input reset : Reset
output io : { flip in_a : { bits : UInt<32>}[1], flip in_b : { bits : UInt<32>}[1], flip in_d : { bits : UInt<32>}[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<4>[1], flip in_last : UInt<1>[1], out_a : { bits : UInt<32>}[1], out_c : { bits : UInt<32>}[1], out_b : { bits : UInt<32>}[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<4>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_24
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a.bits, io.in_a[0].bits
connect tile_0_0.io.in_b.bits, io.in_b[0].bits
connect tile_0_0.io.in_d.bits, io.in_d[0].bits
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_8( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [31:0] io_in_a_0_bits, // @[Tile.scala:17:14]
input [31:0] io_in_b_0_bits, // @[Tile.scala:17:14]
input [31:0] io_in_d_0_bits, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [3:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [31:0] io_out_a_0_bits, // @[Tile.scala:17:14]
output [31:0] io_out_c_0_bits, // @[Tile.scala:17:14]
output [31:0] io_out_b_0_bits, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [3:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0, // @[Tile.scala:17:14]
output io_bad_dataflow // @[Tile.scala:17:14]
);
wire [31:0] io_in_a_0_bits_0 = io_in_a_0_bits; // @[Tile.scala:16:7]
wire [31:0] io_in_b_0_bits_0 = io_in_b_0_bits; // @[Tile.scala:16:7]
wire [31:0] io_in_d_0_bits_0 = io_in_d_0_bits; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [3:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire [31:0] io_out_a_0_bits_0; // @[Tile.scala:16:7]
wire [31:0] io_out_c_0_bits_0; // @[Tile.scala:16:7]
wire [31:0] io_out_b_0_bits_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [3:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
wire io_bad_dataflow_0; // @[Tile.scala:16:7]
PE_24 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a_bits (io_in_a_0_bits_0), // @[Tile.scala:16:7]
.io_in_b_bits (io_in_b_0_bits_0), // @[Tile.scala:16:7]
.io_in_d_bits (io_in_d_0_bits_0), // @[Tile.scala:16:7]
.io_out_a_bits (io_out_a_0_bits_0),
.io_out_b_bits (io_out_b_0_bits_0),
.io_out_c_bits (io_out_c_0_bits_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0),
.io_bad_dataflow (io_bad_dataflow_0)
); // @[Tile.scala:42:44]
assign io_out_a_0_bits = io_out_a_0_bits_0; // @[Tile.scala:16:7]
assign io_out_c_0_bits = io_out_c_0_bits_0; // @[Tile.scala:16:7]
assign io_out_b_0_bits = io_out_b_0_bits_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLInterconnectCoupler_fbus_from_port_named_serial_tl_0_in :
input clock : Clock
input reset : Reset
output auto : { flip buffer_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, tl_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}}
inst buffer of TLBuffer_a32d64s4k1z4u
connect buffer.clock, clock
connect buffer.reset, reset
wire tlOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate tlOut.d.bits.corrupt
invalidate tlOut.d.bits.data
invalidate tlOut.d.bits.denied
invalidate tlOut.d.bits.sink
invalidate tlOut.d.bits.source
invalidate tlOut.d.bits.size
invalidate tlOut.d.bits.param
invalidate tlOut.d.bits.opcode
invalidate tlOut.d.valid
invalidate tlOut.d.ready
invalidate tlOut.a.bits.corrupt
invalidate tlOut.a.bits.data
invalidate tlOut.a.bits.mask
invalidate tlOut.a.bits.address
invalidate tlOut.a.bits.source
invalidate tlOut.a.bits.size
invalidate tlOut.a.bits.param
invalidate tlOut.a.bits.opcode
invalidate tlOut.a.valid
invalidate tlOut.a.ready
wire tlIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}
invalidate tlIn.d.bits.corrupt
invalidate tlIn.d.bits.data
invalidate tlIn.d.bits.denied
invalidate tlIn.d.bits.sink
invalidate tlIn.d.bits.source
invalidate tlIn.d.bits.size
invalidate tlIn.d.bits.param
invalidate tlIn.d.bits.opcode
invalidate tlIn.d.valid
invalidate tlIn.d.ready
invalidate tlIn.a.bits.corrupt
invalidate tlIn.a.bits.data
invalidate tlIn.a.bits.mask
invalidate tlIn.a.bits.address
invalidate tlIn.a.bits.source
invalidate tlIn.a.bits.size
invalidate tlIn.a.bits.param
invalidate tlIn.a.bits.opcode
invalidate tlIn.a.valid
invalidate tlIn.a.ready
connect tlOut, tlIn
connect buffer.auto.out.d, tlIn.d
connect tlIn.a.bits, buffer.auto.out.a.bits
connect tlIn.a.valid, buffer.auto.out.a.valid
connect buffer.auto.out.a.ready, tlIn.a.ready
connect auto.tl_out, tlOut
connect buffer.auto.in, auto.buffer_in | module TLInterconnectCoupler_fbus_from_port_named_serial_tl_0_in( // @[LazyModuleImp.scala:138:7]
input clock, // @[LazyModuleImp.scala:138:7]
input reset, // @[LazyModuleImp.scala:138:7]
output auto_buffer_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_buffer_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_buffer_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_buffer_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_buffer_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_buffer_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_buffer_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_buffer_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_buffer_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_buffer_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_buffer_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_buffer_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_buffer_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_buffer_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output auto_buffer_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_buffer_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_buffer_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_buffer_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_tl_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_tl_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_tl_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_tl_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_tl_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_tl_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_tl_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_tl_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_tl_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_tl_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_tl_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire auto_buffer_in_a_valid_0 = auto_buffer_in_a_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_buffer_in_a_bits_opcode_0 = auto_buffer_in_a_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_buffer_in_a_bits_param_0 = auto_buffer_in_a_bits_param; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_buffer_in_a_bits_size_0 = auto_buffer_in_a_bits_size; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_buffer_in_a_bits_source_0 = auto_buffer_in_a_bits_source; // @[LazyModuleImp.scala:138:7]
wire [31:0] auto_buffer_in_a_bits_address_0 = auto_buffer_in_a_bits_address; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_buffer_in_a_bits_mask_0 = auto_buffer_in_a_bits_mask; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_buffer_in_a_bits_data_0 = auto_buffer_in_a_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_a_bits_corrupt_0 = auto_buffer_in_a_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_d_ready_0 = auto_buffer_in_d_ready; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_a_ready_0 = auto_tl_out_a_ready; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_d_valid_0 = auto_tl_out_d_valid; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_out_d_bits_opcode_0 = auto_tl_out_d_bits_opcode; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_tl_out_d_bits_param_0 = auto_tl_out_d_bits_param; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_tl_out_d_bits_size_0 = auto_tl_out_d_bits_size; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_tl_out_d_bits_source_0 = auto_tl_out_d_bits_source; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_d_bits_sink_0 = auto_tl_out_d_bits_sink; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_d_bits_denied_0 = auto_tl_out_d_bits_denied; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_out_d_bits_data_0 = auto_tl_out_d_bits_data; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_d_bits_corrupt_0 = auto_tl_out_d_bits_corrupt; // @[LazyModuleImp.scala:138:7]
wire tlOut_a_ready = auto_tl_out_a_ready_0; // @[MixedNode.scala:542:17]
wire tlOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] tlOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] tlOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] tlOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] tlOut_a_bits_data; // @[MixedNode.scala:542:17]
wire tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire tlOut_d_ready; // @[MixedNode.scala:542:17]
wire tlOut_d_valid = auto_tl_out_d_valid_0; // @[MixedNode.scala:542:17]
wire [2:0] tlOut_d_bits_opcode = auto_tl_out_d_bits_opcode_0; // @[MixedNode.scala:542:17]
wire [1:0] tlOut_d_bits_param = auto_tl_out_d_bits_param_0; // @[MixedNode.scala:542:17]
wire [3:0] tlOut_d_bits_size = auto_tl_out_d_bits_size_0; // @[MixedNode.scala:542:17]
wire [3:0] tlOut_d_bits_source = auto_tl_out_d_bits_source_0; // @[MixedNode.scala:542:17]
wire tlOut_d_bits_sink = auto_tl_out_d_bits_sink_0; // @[MixedNode.scala:542:17]
wire tlOut_d_bits_denied = auto_tl_out_d_bits_denied_0; // @[MixedNode.scala:542:17]
wire [63:0] tlOut_d_bits_data = auto_tl_out_d_bits_data_0; // @[MixedNode.scala:542:17]
wire tlOut_d_bits_corrupt = auto_tl_out_d_bits_corrupt_0; // @[MixedNode.scala:542:17]
wire auto_buffer_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_buffer_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [1:0] auto_buffer_in_d_bits_param_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_buffer_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_buffer_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_d_bits_sink_0; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_buffer_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
wire auto_buffer_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
wire [2:0] auto_tl_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_tl_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7]
wire [3:0] auto_tl_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7]
wire [31:0] auto_tl_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7]
wire [7:0] auto_tl_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7]
wire [63:0] auto_tl_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_a_valid_0; // @[LazyModuleImp.scala:138:7]
wire auto_tl_out_d_ready_0; // @[LazyModuleImp.scala:138:7]
wire tlIn_a_ready = tlOut_a_ready; // @[MixedNode.scala:542:17, :551:17]
wire tlIn_a_valid; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_valid_0 = tlOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] tlIn_a_bits_opcode; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_bits_opcode_0 = tlOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] tlIn_a_bits_param; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_bits_param_0 = tlOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] tlIn_a_bits_size; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_bits_size_0 = tlOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] tlIn_a_bits_source; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_bits_source_0 = tlOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] tlIn_a_bits_address; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_bits_address_0 = tlOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] tlIn_a_bits_mask; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_bits_mask_0 = tlOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] tlIn_a_bits_data; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_bits_data_0 = tlOut_a_bits_data; // @[MixedNode.scala:542:17]
wire tlIn_a_bits_corrupt; // @[MixedNode.scala:551:17]
assign auto_tl_out_a_bits_corrupt_0 = tlOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire tlIn_d_ready; // @[MixedNode.scala:551:17]
assign auto_tl_out_d_ready_0 = tlOut_d_ready; // @[MixedNode.scala:542:17]
wire tlIn_d_valid = tlOut_d_valid; // @[MixedNode.scala:542:17, :551:17]
wire [2:0] tlIn_d_bits_opcode = tlOut_d_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
wire [1:0] tlIn_d_bits_param = tlOut_d_bits_param; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlIn_d_bits_size = tlOut_d_bits_size; // @[MixedNode.scala:542:17, :551:17]
wire [3:0] tlIn_d_bits_source = tlOut_d_bits_source; // @[MixedNode.scala:542:17, :551:17]
wire tlIn_d_bits_sink = tlOut_d_bits_sink; // @[MixedNode.scala:542:17, :551:17]
wire tlIn_d_bits_denied = tlOut_d_bits_denied; // @[MixedNode.scala:542:17, :551:17]
wire [63:0] tlIn_d_bits_data = tlOut_d_bits_data; // @[MixedNode.scala:542:17, :551:17]
wire tlIn_d_bits_corrupt = tlOut_d_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_valid = tlIn_a_valid; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_opcode = tlIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_param = tlIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_size = tlIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_source = tlIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_address = tlIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_mask = tlIn_a_bits_mask; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_data = tlIn_a_bits_data; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_a_bits_corrupt = tlIn_a_bits_corrupt; // @[MixedNode.scala:542:17, :551:17]
assign tlOut_d_ready = tlIn_d_ready; // @[MixedNode.scala:542:17, :551:17]
TLBuffer_a32d64s4k1z4u buffer ( // @[Buffer.scala:75:28]
.clock (clock),
.reset (reset),
.auto_in_a_ready (auto_buffer_in_a_ready_0),
.auto_in_a_valid (auto_buffer_in_a_valid_0), // @[LazyModuleImp.scala:138:7]
.auto_in_a_bits_opcode (auto_buffer_in_a_bits_opcode_0), // @[LazyModuleImp.scala:138:7]
.auto_in_a_bits_param (auto_buffer_in_a_bits_param_0), // @[LazyModuleImp.scala:138:7]
.auto_in_a_bits_size (auto_buffer_in_a_bits_size_0), // @[LazyModuleImp.scala:138:7]
.auto_in_a_bits_source (auto_buffer_in_a_bits_source_0), // @[LazyModuleImp.scala:138:7]
.auto_in_a_bits_address (auto_buffer_in_a_bits_address_0), // @[LazyModuleImp.scala:138:7]
.auto_in_a_bits_mask (auto_buffer_in_a_bits_mask_0), // @[LazyModuleImp.scala:138:7]
.auto_in_a_bits_data (auto_buffer_in_a_bits_data_0), // @[LazyModuleImp.scala:138:7]
.auto_in_a_bits_corrupt (auto_buffer_in_a_bits_corrupt_0), // @[LazyModuleImp.scala:138:7]
.auto_in_d_ready (auto_buffer_in_d_ready_0), // @[LazyModuleImp.scala:138:7]
.auto_in_d_valid (auto_buffer_in_d_valid_0),
.auto_in_d_bits_opcode (auto_buffer_in_d_bits_opcode_0),
.auto_in_d_bits_param (auto_buffer_in_d_bits_param_0),
.auto_in_d_bits_size (auto_buffer_in_d_bits_size_0),
.auto_in_d_bits_source (auto_buffer_in_d_bits_source_0),
.auto_in_d_bits_sink (auto_buffer_in_d_bits_sink_0),
.auto_in_d_bits_denied (auto_buffer_in_d_bits_denied_0),
.auto_in_d_bits_data (auto_buffer_in_d_bits_data_0),
.auto_in_d_bits_corrupt (auto_buffer_in_d_bits_corrupt_0),
.auto_out_a_ready (tlIn_a_ready), // @[MixedNode.scala:551:17]
.auto_out_a_valid (tlIn_a_valid),
.auto_out_a_bits_opcode (tlIn_a_bits_opcode),
.auto_out_a_bits_param (tlIn_a_bits_param),
.auto_out_a_bits_size (tlIn_a_bits_size),
.auto_out_a_bits_source (tlIn_a_bits_source),
.auto_out_a_bits_address (tlIn_a_bits_address),
.auto_out_a_bits_mask (tlIn_a_bits_mask),
.auto_out_a_bits_data (tlIn_a_bits_data),
.auto_out_a_bits_corrupt (tlIn_a_bits_corrupt),
.auto_out_d_ready (tlIn_d_ready),
.auto_out_d_valid (tlIn_d_valid), // @[MixedNode.scala:551:17]
.auto_out_d_bits_opcode (tlIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.auto_out_d_bits_param (tlIn_d_bits_param), // @[MixedNode.scala:551:17]
.auto_out_d_bits_size (tlIn_d_bits_size), // @[MixedNode.scala:551:17]
.auto_out_d_bits_source (tlIn_d_bits_source), // @[MixedNode.scala:551:17]
.auto_out_d_bits_sink (tlIn_d_bits_sink), // @[MixedNode.scala:551:17]
.auto_out_d_bits_denied (tlIn_d_bits_denied), // @[MixedNode.scala:551:17]
.auto_out_d_bits_data (tlIn_d_bits_data), // @[MixedNode.scala:551:17]
.auto_out_d_bits_corrupt (tlIn_d_bits_corrupt) // @[MixedNode.scala:551:17]
); // @[Buffer.scala:75:28]
assign auto_buffer_in_a_ready = auto_buffer_in_a_ready_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_valid = auto_buffer_in_d_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_bits_opcode = auto_buffer_in_d_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_bits_param = auto_buffer_in_d_bits_param_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_bits_size = auto_buffer_in_d_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_bits_source = auto_buffer_in_d_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_bits_sink = auto_buffer_in_d_bits_sink_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_bits_denied = auto_buffer_in_d_bits_denied_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_bits_data = auto_buffer_in_d_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_buffer_in_d_bits_corrupt = auto_buffer_in_d_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_valid = auto_tl_out_a_valid_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_opcode = auto_tl_out_a_bits_opcode_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_param = auto_tl_out_a_bits_param_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_size = auto_tl_out_a_bits_size_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_source = auto_tl_out_a_bits_source_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_address = auto_tl_out_a_bits_address_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_mask = auto_tl_out_a_bits_mask_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_data = auto_tl_out_a_bits_data_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_a_bits_corrupt = auto_tl_out_a_bits_corrupt_0; // @[LazyModuleImp.scala:138:7]
assign auto_tl_out_d_ready = auto_tl_out_d_ready_0; // @[LazyModuleImp.scala:138:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s2k3z4c_15 :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeIn.e.bits.sink
invalidate nodeIn.e.valid
invalidate nodeIn.e.ready
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.c.bits.corrupt
invalidate nodeIn.c.bits.data
invalidate nodeIn.c.bits.address
invalidate nodeIn.c.bits.source
invalidate nodeIn.c.bits.size
invalidate nodeIn.c.bits.param
invalidate nodeIn.c.bits.opcode
invalidate nodeIn.c.valid
invalidate nodeIn.c.ready
invalidate nodeIn.b.bits.corrupt
invalidate nodeIn.b.bits.data
invalidate nodeIn.b.bits.mask
invalidate nodeIn.b.bits.address
invalidate nodeIn.b.bits.source
invalidate nodeIn.b.bits.size
invalidate nodeIn.b.bits.param
invalidate nodeIn.b.bits.opcode
invalidate nodeIn.b.valid
invalidate nodeIn.b.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_71
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink
connect monitor.io.in.e.valid, nodeIn.e.valid
connect monitor.io.in.e.ready, nodeIn.e.ready
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt
connect monitor.io.in.c.bits.data, nodeIn.c.bits.data
connect monitor.io.in.c.bits.address, nodeIn.c.bits.address
connect monitor.io.in.c.bits.source, nodeIn.c.bits.source
connect monitor.io.in.c.bits.size, nodeIn.c.bits.size
connect monitor.io.in.c.bits.param, nodeIn.c.bits.param
connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode
connect monitor.io.in.c.valid, nodeIn.c.valid
connect monitor.io.in.c.ready, nodeIn.c.ready
connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt
connect monitor.io.in.b.bits.data, nodeIn.b.bits.data
connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask
connect monitor.io.in.b.bits.address, nodeIn.b.bits.address
connect monitor.io.in.b.bits.source, nodeIn.b.bits.source
connect monitor.io.in.b.bits.size, nodeIn.b.bits.size
connect monitor.io.in.b.bits.param, nodeIn.b.bits.param
connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode
connect monitor.io.in.b.valid, nodeIn.b.valid
connect monitor.io.in.b.ready, nodeIn.b.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<2>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<2>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}
invalidate nodeOut.e.bits.sink
invalidate nodeOut.e.valid
invalidate nodeOut.e.ready
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.c.bits.corrupt
invalidate nodeOut.c.bits.data
invalidate nodeOut.c.bits.address
invalidate nodeOut.c.bits.source
invalidate nodeOut.c.bits.size
invalidate nodeOut.c.bits.param
invalidate nodeOut.c.bits.opcode
invalidate nodeOut.c.valid
invalidate nodeOut.c.ready
invalidate nodeOut.b.bits.corrupt
invalidate nodeOut.b.bits.data
invalidate nodeOut.b.bits.mask
invalidate nodeOut.b.bits.address
invalidate nodeOut.b.bits.source
invalidate nodeOut.b.bits.size
invalidate nodeOut.b.bits.param
invalidate nodeOut.b.bits.opcode
invalidate nodeOut.b.valid
invalidate nodeOut.b.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_q of Queue2_TLBundleA_a32d64s2k3z4c_7
connect nodeOut_a_q.clock, clock
connect nodeOut_a_q.reset, reset
connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid
connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data
connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address
connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source
connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size
connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param
connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready
connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid
connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_q of Queue2_TLBundleD_a32d64s2k3z4c_7
connect nodeIn_d_q.clock, clock
connect nodeIn_d_q.reset, reset
connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid
connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data
connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source
connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size
connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param
connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready
connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid
connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready
inst nodeIn_b_q of Queue2_TLBundleB_a32d64s2k3z4c_7
connect nodeIn_b_q.clock, clock
connect nodeIn_b_q.reset, reset
connect nodeIn_b_q.io.enq.valid, nodeOut.b.valid
connect nodeIn_b_q.io.enq.bits.corrupt, nodeOut.b.bits.corrupt
connect nodeIn_b_q.io.enq.bits.data, nodeOut.b.bits.data
connect nodeIn_b_q.io.enq.bits.mask, nodeOut.b.bits.mask
connect nodeIn_b_q.io.enq.bits.address, nodeOut.b.bits.address
connect nodeIn_b_q.io.enq.bits.source, nodeOut.b.bits.source
connect nodeIn_b_q.io.enq.bits.size, nodeOut.b.bits.size
connect nodeIn_b_q.io.enq.bits.param, nodeOut.b.bits.param
connect nodeIn_b_q.io.enq.bits.opcode, nodeOut.b.bits.opcode
connect nodeOut.b.ready, nodeIn_b_q.io.enq.ready
connect nodeIn.b.bits, nodeIn_b_q.io.deq.bits
connect nodeIn.b.valid, nodeIn_b_q.io.deq.valid
connect nodeIn_b_q.io.deq.ready, nodeIn.b.ready
inst nodeOut_c_q of Queue2_TLBundleC_a32d64s2k3z4c_7
connect nodeOut_c_q.clock, clock
connect nodeOut_c_q.reset, reset
connect nodeOut_c_q.io.enq.valid, nodeIn.c.valid
connect nodeOut_c_q.io.enq.bits.corrupt, nodeIn.c.bits.corrupt
connect nodeOut_c_q.io.enq.bits.data, nodeIn.c.bits.data
connect nodeOut_c_q.io.enq.bits.address, nodeIn.c.bits.address
connect nodeOut_c_q.io.enq.bits.source, nodeIn.c.bits.source
connect nodeOut_c_q.io.enq.bits.size, nodeIn.c.bits.size
connect nodeOut_c_q.io.enq.bits.param, nodeIn.c.bits.param
connect nodeOut_c_q.io.enq.bits.opcode, nodeIn.c.bits.opcode
connect nodeIn.c.ready, nodeOut_c_q.io.enq.ready
connect nodeOut.c.bits, nodeOut_c_q.io.deq.bits
connect nodeOut.c.valid, nodeOut_c_q.io.deq.valid
connect nodeOut_c_q.io.deq.ready, nodeOut.c.ready
inst nodeOut_e_q of Queue2_TLBundleE_a32d64s2k3z4c_7
connect nodeOut_e_q.clock, clock
connect nodeOut_e_q.reset, reset
connect nodeOut_e_q.io.enq.valid, nodeIn.e.valid
connect nodeOut_e_q.io.enq.bits.sink, nodeIn.e.bits.sink
connect nodeIn.e.ready, nodeOut_e_q.io.enq.ready
connect nodeOut.e.bits, nodeOut_e_q.io.deq.bits
connect nodeOut.e.valid, nodeOut_e_q.io.deq.valid
connect nodeOut_e_q.io.deq.ready, nodeOut.e.ready | module TLBuffer_a32d64s2k3z4c_15( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_e_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_b_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input [7:0] auto_out_b_bits_mask, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_b_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [63:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [1:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9]
wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9]
wire [1:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9]
wire [63:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_b_bits_opcode_0 = auto_out_b_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_b_bits_size_0 = auto_out_b_bits_size; // @[Buffer.scala:40:9]
wire [1:0] auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9]
wire [7:0] auto_out_b_bits_mask_0 = auto_out_b_bits_mask; // @[Buffer.scala:40:9]
wire [63:0] auto_out_b_bits_data_0 = auto_out_b_bits_data; // @[Buffer.scala:40:9]
wire auto_out_b_bits_corrupt_0 = auto_out_b_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [63:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_out_e_ready_0 = auto_out_e_ready; // @[Buffer.scala:40:9]
wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire auto_in_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeIn_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_b_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [7:0] nodeIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_b_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_c_ready; // @[MixedNode.scala:551:17]
wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9]
wire [63:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [63:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_e_ready; // @[MixedNode.scala:551:17]
wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [7:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_b_ready; // @[MixedNode.scala:542:17]
wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_b_bits_opcode = auto_out_b_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_b_bits_size = auto_out_b_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] nodeOut_b_bits_mask = auto_out_b_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_b_bits_data = auto_out_b_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_b_bits_corrupt = auto_out_b_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [1:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [63:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeOut_e_ready = auto_out_e_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_e_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_b_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_b_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_in_b_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_b_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_b_valid_0; // @[Buffer.scala:40:9]
wire auto_in_c_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [63:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire auto_in_e_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [7:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_b_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9]
wire [1:0] auto_out_c_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9]
wire [63:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_c_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_out_e_valid_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9]
assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9]
assign auto_in_b_bits_size_0 = nodeIn_b_bits_size; // @[Buffer.scala:40:9]
assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[Buffer.scala:40:9]
assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9]
assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask; // @[Buffer.scala:40:9]
assign auto_in_b_bits_data_0 = nodeIn_b_bits_data; // @[Buffer.scala:40:9]
assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_in_e_ready_0 = nodeIn_e_ready; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9]
assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9]
assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9]
assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9]
assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9]
assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9]
assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9]
assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9]
assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9]
TLMonitor_71 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17]
.io_in_b_bits_opcode (nodeIn_b_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17]
.io_in_b_bits_size (nodeIn_b_bits_size), // @[MixedNode.scala:551:17]
.io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17]
.io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17]
.io_in_b_bits_mask (nodeIn_b_bits_mask), // @[MixedNode.scala:551:17]
.io_in_b_bits_data (nodeIn_b_bits_data), // @[MixedNode.scala:551:17]
.io_in_b_bits_corrupt (nodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17]
.io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_e_ready (nodeIn_e_ready), // @[MixedNode.scala:551:17]
.io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a32d64s2k3z4c_7 nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a32d64s2k3z4c_7 nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleB_a32d64s2k3z4c_7 nodeIn_b_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_b_ready),
.io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_b_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_b_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_b_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_b_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_address (nodeOut_b_bits_address), // @[MixedNode.scala:542:17]
.io_enq_bits_mask (nodeOut_b_bits_mask), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_b_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_b_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_b_valid),
.io_deq_bits_opcode (nodeIn_b_bits_opcode),
.io_deq_bits_param (nodeIn_b_bits_param),
.io_deq_bits_size (nodeIn_b_bits_size),
.io_deq_bits_source (nodeIn_b_bits_source),
.io_deq_bits_address (nodeIn_b_bits_address),
.io_deq_bits_mask (nodeIn_b_bits_mask),
.io_deq_bits_data (nodeIn_b_bits_data),
.io_deq_bits_corrupt (nodeIn_b_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleC_a32d64s2k3z4c_7 nodeOut_c_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_c_ready),
.io_enq_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_c_valid),
.io_deq_bits_opcode (nodeOut_c_bits_opcode),
.io_deq_bits_param (nodeOut_c_bits_param),
.io_deq_bits_size (nodeOut_c_bits_size),
.io_deq_bits_source (nodeOut_c_bits_source),
.io_deq_bits_address (nodeOut_c_bits_address),
.io_deq_bits_data (nodeOut_c_bits_data),
.io_deq_bits_corrupt (nodeOut_c_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleE_a32d64s2k3z4c_7 nodeOut_e_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_e_ready),
.io_enq_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_e_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_e_valid),
.io_deq_bits_sink (nodeOut_e_bits_sink)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_size = auto_in_b_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_mask = auto_in_b_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_data = auto_in_b_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_in_e_ready = auto_in_e_ready_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9]
assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9]
assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d128s4k4z4c_1 :
input clock : Clock
input reset : Reset
output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}}
wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}
invalidate nodeIn.e.bits.sink
invalidate nodeIn.e.valid
invalidate nodeIn.e.ready
invalidate nodeIn.d.bits.corrupt
invalidate nodeIn.d.bits.data
invalidate nodeIn.d.bits.denied
invalidate nodeIn.d.bits.sink
invalidate nodeIn.d.bits.source
invalidate nodeIn.d.bits.size
invalidate nodeIn.d.bits.param
invalidate nodeIn.d.bits.opcode
invalidate nodeIn.d.valid
invalidate nodeIn.d.ready
invalidate nodeIn.c.bits.corrupt
invalidate nodeIn.c.bits.data
invalidate nodeIn.c.bits.address
invalidate nodeIn.c.bits.source
invalidate nodeIn.c.bits.size
invalidate nodeIn.c.bits.param
invalidate nodeIn.c.bits.opcode
invalidate nodeIn.c.valid
invalidate nodeIn.c.ready
invalidate nodeIn.b.bits.corrupt
invalidate nodeIn.b.bits.data
invalidate nodeIn.b.bits.mask
invalidate nodeIn.b.bits.address
invalidate nodeIn.b.bits.source
invalidate nodeIn.b.bits.size
invalidate nodeIn.b.bits.param
invalidate nodeIn.b.bits.opcode
invalidate nodeIn.b.valid
invalidate nodeIn.b.ready
invalidate nodeIn.a.bits.corrupt
invalidate nodeIn.a.bits.data
invalidate nodeIn.a.bits.mask
invalidate nodeIn.a.bits.address
invalidate nodeIn.a.bits.source
invalidate nodeIn.a.bits.size
invalidate nodeIn.a.bits.param
invalidate nodeIn.a.bits.opcode
invalidate nodeIn.a.valid
invalidate nodeIn.a.ready
inst monitor of TLMonitor_51
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.e.bits.sink, nodeIn.e.bits.sink
connect monitor.io.in.e.valid, nodeIn.e.valid
connect monitor.io.in.e.ready, nodeIn.e.ready
connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, nodeIn.d.bits.data
connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied
connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink
connect monitor.io.in.d.bits.source, nodeIn.d.bits.source
connect monitor.io.in.d.bits.size, nodeIn.d.bits.size
connect monitor.io.in.d.bits.param, nodeIn.d.bits.param
connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode
connect monitor.io.in.d.valid, nodeIn.d.valid
connect monitor.io.in.d.ready, nodeIn.d.ready
connect monitor.io.in.c.bits.corrupt, nodeIn.c.bits.corrupt
connect monitor.io.in.c.bits.data, nodeIn.c.bits.data
connect monitor.io.in.c.bits.address, nodeIn.c.bits.address
connect monitor.io.in.c.bits.source, nodeIn.c.bits.source
connect monitor.io.in.c.bits.size, nodeIn.c.bits.size
connect monitor.io.in.c.bits.param, nodeIn.c.bits.param
connect monitor.io.in.c.bits.opcode, nodeIn.c.bits.opcode
connect monitor.io.in.c.valid, nodeIn.c.valid
connect monitor.io.in.c.ready, nodeIn.c.ready
connect monitor.io.in.b.bits.corrupt, nodeIn.b.bits.corrupt
connect monitor.io.in.b.bits.data, nodeIn.b.bits.data
connect monitor.io.in.b.bits.mask, nodeIn.b.bits.mask
connect monitor.io.in.b.bits.address, nodeIn.b.bits.address
connect monitor.io.in.b.bits.source, nodeIn.b.bits.source
connect monitor.io.in.b.bits.size, nodeIn.b.bits.size
connect monitor.io.in.b.bits.param, nodeIn.b.bits.param
connect monitor.io.in.b.bits.opcode, nodeIn.b.bits.opcode
connect monitor.io.in.b.valid, nodeIn.b.valid
connect monitor.io.in.b.ready, nodeIn.b.ready
connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, nodeIn.a.bits.data
connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask
connect monitor.io.in.a.bits.address, nodeIn.a.bits.address
connect monitor.io.in.a.bits.source, nodeIn.a.bits.source
connect monitor.io.in.a.bits.size, nodeIn.a.bits.size
connect monitor.io.in.a.bits.param, nodeIn.a.bits.param
connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode
connect monitor.io.in.a.valid, nodeIn.a.valid
connect monitor.io.in.a.ready, nodeIn.a.ready
wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}
invalidate nodeOut.e.bits.sink
invalidate nodeOut.e.valid
invalidate nodeOut.e.ready
invalidate nodeOut.d.bits.corrupt
invalidate nodeOut.d.bits.data
invalidate nodeOut.d.bits.denied
invalidate nodeOut.d.bits.sink
invalidate nodeOut.d.bits.source
invalidate nodeOut.d.bits.size
invalidate nodeOut.d.bits.param
invalidate nodeOut.d.bits.opcode
invalidate nodeOut.d.valid
invalidate nodeOut.d.ready
invalidate nodeOut.c.bits.corrupt
invalidate nodeOut.c.bits.data
invalidate nodeOut.c.bits.address
invalidate nodeOut.c.bits.source
invalidate nodeOut.c.bits.size
invalidate nodeOut.c.bits.param
invalidate nodeOut.c.bits.opcode
invalidate nodeOut.c.valid
invalidate nodeOut.c.ready
invalidate nodeOut.b.bits.corrupt
invalidate nodeOut.b.bits.data
invalidate nodeOut.b.bits.mask
invalidate nodeOut.b.bits.address
invalidate nodeOut.b.bits.source
invalidate nodeOut.b.bits.size
invalidate nodeOut.b.bits.param
invalidate nodeOut.b.bits.opcode
invalidate nodeOut.b.valid
invalidate nodeOut.b.ready
invalidate nodeOut.a.bits.corrupt
invalidate nodeOut.a.bits.data
invalidate nodeOut.a.bits.mask
invalidate nodeOut.a.bits.address
invalidate nodeOut.a.bits.source
invalidate nodeOut.a.bits.size
invalidate nodeOut.a.bits.param
invalidate nodeOut.a.bits.opcode
invalidate nodeOut.a.valid
invalidate nodeOut.a.ready
connect auto.out, nodeOut
connect nodeIn, auto.in
inst nodeOut_a_q of Queue2_TLBundleA_a32d128s4k4z4c
connect nodeOut_a_q.clock, clock
connect nodeOut_a_q.reset, reset
connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid
connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt
connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data
connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask
connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address
connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source
connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size
connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param
connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode
connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready
connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits
connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid
connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready
inst nodeIn_d_q of Queue2_TLBundleD_a32d128s4k4z4c
connect nodeIn_d_q.clock, clock
connect nodeIn_d_q.reset, reset
connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid
connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt
connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data
connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied
connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink
connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source
connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size
connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param
connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode
connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready
connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits
connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid
connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready
inst nodeIn_b_q of Queue2_TLBundleB_a32d128s4k4z4c
connect nodeIn_b_q.clock, clock
connect nodeIn_b_q.reset, reset
connect nodeIn_b_q.io.enq.valid, nodeOut.b.valid
connect nodeIn_b_q.io.enq.bits.corrupt, nodeOut.b.bits.corrupt
connect nodeIn_b_q.io.enq.bits.data, nodeOut.b.bits.data
connect nodeIn_b_q.io.enq.bits.mask, nodeOut.b.bits.mask
connect nodeIn_b_q.io.enq.bits.address, nodeOut.b.bits.address
connect nodeIn_b_q.io.enq.bits.source, nodeOut.b.bits.source
connect nodeIn_b_q.io.enq.bits.size, nodeOut.b.bits.size
connect nodeIn_b_q.io.enq.bits.param, nodeOut.b.bits.param
connect nodeIn_b_q.io.enq.bits.opcode, nodeOut.b.bits.opcode
connect nodeOut.b.ready, nodeIn_b_q.io.enq.ready
connect nodeIn.b.bits, nodeIn_b_q.io.deq.bits
connect nodeIn.b.valid, nodeIn_b_q.io.deq.valid
connect nodeIn_b_q.io.deq.ready, nodeIn.b.ready
inst nodeOut_c_q of Queue2_TLBundleC_a32d128s4k4z4c
connect nodeOut_c_q.clock, clock
connect nodeOut_c_q.reset, reset
connect nodeOut_c_q.io.enq.valid, nodeIn.c.valid
connect nodeOut_c_q.io.enq.bits.corrupt, nodeIn.c.bits.corrupt
connect nodeOut_c_q.io.enq.bits.data, nodeIn.c.bits.data
connect nodeOut_c_q.io.enq.bits.address, nodeIn.c.bits.address
connect nodeOut_c_q.io.enq.bits.source, nodeIn.c.bits.source
connect nodeOut_c_q.io.enq.bits.size, nodeIn.c.bits.size
connect nodeOut_c_q.io.enq.bits.param, nodeIn.c.bits.param
connect nodeOut_c_q.io.enq.bits.opcode, nodeIn.c.bits.opcode
connect nodeIn.c.ready, nodeOut_c_q.io.enq.ready
connect nodeOut.c.bits, nodeOut_c_q.io.deq.bits
connect nodeOut.c.valid, nodeOut_c_q.io.deq.valid
connect nodeOut_c_q.io.deq.ready, nodeOut.c.ready
inst nodeOut_e_q of Queue2_TLBundleE_a32d128s4k4z4c
connect nodeOut_e_q.clock, clock
connect nodeOut_e_q.reset, reset
connect nodeOut_e_q.io.enq.valid, nodeIn.e.valid
connect nodeOut_e_q.io.enq.bits.sink, nodeIn.e.bits.sink
connect nodeIn.e.ready, nodeOut_e_q.io.enq.ready
connect nodeOut.e.bits, nodeOut_e_q.io.deq.bits
connect nodeOut.e.valid, nodeOut_e_q.io.deq.valid
connect nodeOut_e_q.io.deq.ready, nodeOut.e.ready | module TLBuffer_a32d128s4k4z4c_1( // @[Buffer.scala:40:9]
input clock, // @[Buffer.scala:40:9]
input reset, // @[Buffer.scala:40:9]
output auto_in_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [15:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_b_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_b_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_b_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_b_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_b_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_b_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_in_b_bits_address, // @[LazyModuleImp.scala:107:25]
output [15:0] auto_in_b_bits_mask, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_in_b_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_b_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_c_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_c_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_in_c_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_c_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_c_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_in_c_bits_address, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_in_c_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_in_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_in_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_in_e_ready, // @[LazyModuleImp.scala:107:25]
input auto_in_e_valid, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_in_e_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [15:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_b_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_b_valid, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_b_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_b_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_out_b_bits_address, // @[LazyModuleImp.scala:107:25]
input auto_out_c_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_c_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_out_c_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_c_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_out_c_bits_address, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_out_c_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_out_c_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_out_e_ready, // @[LazyModuleImp.scala:107:25]
output auto_out_e_valid, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_out_e_bits_sink // @[LazyModuleImp.scala:107:25]
);
wire auto_in_a_valid_0 = auto_in_a_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_opcode_0 = auto_in_a_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_a_bits_param_0 = auto_in_a_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_size_0 = auto_in_a_bits_size; // @[Buffer.scala:40:9]
wire [3:0] auto_in_a_bits_source_0 = auto_in_a_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_a_bits_address_0 = auto_in_a_bits_address; // @[Buffer.scala:40:9]
wire [15:0] auto_in_a_bits_mask_0 = auto_in_a_bits_mask; // @[Buffer.scala:40:9]
wire [127:0] auto_in_a_bits_data_0 = auto_in_a_bits_data; // @[Buffer.scala:40:9]
wire auto_in_b_ready_0 = auto_in_b_ready; // @[Buffer.scala:40:9]
wire auto_in_c_valid_0 = auto_in_c_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_opcode_0 = auto_in_c_bits_opcode; // @[Buffer.scala:40:9]
wire [2:0] auto_in_c_bits_param_0 = auto_in_c_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_in_c_bits_size_0 = auto_in_c_bits_size; // @[Buffer.scala:40:9]
wire [3:0] auto_in_c_bits_source_0 = auto_in_c_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_in_c_bits_address_0 = auto_in_c_bits_address; // @[Buffer.scala:40:9]
wire [127:0] auto_in_c_bits_data_0 = auto_in_c_bits_data; // @[Buffer.scala:40:9]
wire auto_in_d_ready_0 = auto_in_d_ready; // @[Buffer.scala:40:9]
wire auto_in_e_valid_0 = auto_in_e_valid; // @[Buffer.scala:40:9]
wire [3:0] auto_in_e_bits_sink_0 = auto_in_e_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_a_ready_0 = auto_out_a_ready; // @[Buffer.scala:40:9]
wire auto_out_b_valid_0 = auto_out_b_valid; // @[Buffer.scala:40:9]
wire [1:0] auto_out_b_bits_param_0 = auto_out_b_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_b_bits_source_0 = auto_out_b_bits_source; // @[Buffer.scala:40:9]
wire [31:0] auto_out_b_bits_address_0 = auto_out_b_bits_address; // @[Buffer.scala:40:9]
wire auto_out_c_ready_0 = auto_out_c_ready; // @[Buffer.scala:40:9]
wire auto_out_d_valid_0 = auto_out_d_valid; // @[Buffer.scala:40:9]
wire [2:0] auto_out_d_bits_opcode_0 = auto_out_d_bits_opcode; // @[Buffer.scala:40:9]
wire [1:0] auto_out_d_bits_param_0 = auto_out_d_bits_param; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_size_0 = auto_out_d_bits_size; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_source_0 = auto_out_d_bits_source; // @[Buffer.scala:40:9]
wire [3:0] auto_out_d_bits_sink_0 = auto_out_d_bits_sink; // @[Buffer.scala:40:9]
wire auto_out_d_bits_denied_0 = auto_out_d_bits_denied; // @[Buffer.scala:40:9]
wire [127:0] auto_out_d_bits_data_0 = auto_out_d_bits_data; // @[Buffer.scala:40:9]
wire auto_out_d_bits_corrupt_0 = auto_out_d_bits_corrupt; // @[Buffer.scala:40:9]
wire auto_out_e_ready_0 = auto_out_e_ready; // @[Buffer.scala:40:9]
wire [127:0] auto_out_b_bits_data = 128'h0; // @[Decoupled.scala:362:21]
wire [127:0] nodeOut_b_bits_data = 128'h0; // @[Decoupled.scala:362:21]
wire [15:0] auto_out_b_bits_mask = 16'hFFFF; // @[Decoupled.scala:362:21]
wire [15:0] nodeOut_b_bits_mask = 16'hFFFF; // @[Decoupled.scala:362:21]
wire [3:0] auto_out_b_bits_size = 4'h6; // @[Decoupled.scala:362:21]
wire [3:0] nodeOut_b_bits_size = 4'h6; // @[Decoupled.scala:362:21]
wire [2:0] auto_out_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21]
wire [2:0] nodeOut_b_bits_opcode = 3'h6; // @[Decoupled.scala:362:21]
wire auto_in_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire auto_in_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire auto_out_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_ready; // @[MixedNode.scala:551:17]
wire nodeIn_a_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeIn_c_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeOut_b_bits_corrupt = 1'h0; // @[Decoupled.scala:362:21]
wire nodeIn_a_valid = auto_in_a_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_opcode = auto_in_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_a_bits_param = auto_in_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_size = auto_in_a_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_a_bits_source = auto_in_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_a_bits_address = auto_in_a_bits_address_0; // @[Buffer.scala:40:9]
wire [15:0] nodeIn_a_bits_mask = auto_in_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [127:0] nodeIn_a_bits_data = auto_in_a_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_b_ready = auto_in_b_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_b_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_b_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_b_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_b_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_b_bits_source; // @[MixedNode.scala:551:17]
wire [31:0] nodeIn_b_bits_address; // @[MixedNode.scala:551:17]
wire [15:0] nodeIn_b_bits_mask; // @[MixedNode.scala:551:17]
wire [127:0] nodeIn_b_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_b_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_c_ready; // @[MixedNode.scala:551:17]
wire nodeIn_c_valid = auto_in_c_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_opcode = auto_in_c_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] nodeIn_c_bits_param = auto_in_c_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_c_bits_size = auto_in_c_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_c_bits_source = auto_in_c_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeIn_c_bits_address = auto_in_c_bits_address_0; // @[Buffer.scala:40:9]
wire [127:0] nodeIn_c_bits_data = auto_in_c_bits_data_0; // @[Buffer.scala:40:9]
wire nodeIn_d_ready = auto_in_d_ready_0; // @[Buffer.scala:40:9]
wire nodeIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] nodeIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] nodeIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] nodeIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [127:0] nodeIn_d_bits_data; // @[MixedNode.scala:551:17]
wire nodeIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire nodeIn_e_ready; // @[MixedNode.scala:551:17]
wire nodeIn_e_valid = auto_in_e_valid_0; // @[Buffer.scala:40:9]
wire [3:0] nodeIn_e_bits_sink = auto_in_e_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_a_ready = auto_out_a_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [15:0] nodeOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [127:0] nodeOut_a_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_b_ready; // @[MixedNode.scala:542:17]
wire nodeOut_b_valid = auto_out_b_valid_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_b_bits_param = auto_out_b_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_b_bits_source = auto_out_b_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] nodeOut_b_bits_address = auto_out_b_bits_address_0; // @[Buffer.scala:40:9]
wire nodeOut_c_ready = auto_out_c_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_c_valid; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] nodeOut_c_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_bits_size; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_c_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] nodeOut_c_bits_address; // @[MixedNode.scala:542:17]
wire [127:0] nodeOut_c_bits_data; // @[MixedNode.scala:542:17]
wire nodeOut_c_bits_corrupt; // @[MixedNode.scala:542:17]
wire nodeOut_d_ready; // @[MixedNode.scala:542:17]
wire nodeOut_d_valid = auto_out_d_valid_0; // @[Buffer.scala:40:9]
wire [2:0] nodeOut_d_bits_opcode = auto_out_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] nodeOut_d_bits_param = auto_out_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_size = auto_out_d_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_source = auto_out_d_bits_source_0; // @[Buffer.scala:40:9]
wire [3:0] nodeOut_d_bits_sink = auto_out_d_bits_sink_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_denied = auto_out_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [127:0] nodeOut_d_bits_data = auto_out_d_bits_data_0; // @[Buffer.scala:40:9]
wire nodeOut_d_bits_corrupt = auto_out_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire nodeOut_e_ready = auto_out_e_ready_0; // @[Buffer.scala:40:9]
wire nodeOut_e_valid; // @[MixedNode.scala:542:17]
wire [3:0] nodeOut_e_bits_sink; // @[MixedNode.scala:542:17]
wire auto_in_a_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_b_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_b_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_b_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_in_b_bits_address_0; // @[Buffer.scala:40:9]
wire [15:0] auto_in_b_bits_mask_0; // @[Buffer.scala:40:9]
wire [127:0] auto_in_b_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_b_valid_0; // @[Buffer.scala:40:9]
wire auto_in_c_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
wire [1:0] auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
wire [3:0] auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
wire [127:0] auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
wire auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_in_d_valid_0; // @[Buffer.scala:40:9]
wire auto_in_e_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
wire [15:0] auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
wire [127:0] auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_a_valid_0; // @[Buffer.scala:40:9]
wire auto_out_b_ready_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9]
wire [2:0] auto_out_c_bits_param_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_c_bits_size_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_c_bits_source_0; // @[Buffer.scala:40:9]
wire [31:0] auto_out_c_bits_address_0; // @[Buffer.scala:40:9]
wire [127:0] auto_out_c_bits_data_0; // @[Buffer.scala:40:9]
wire auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9]
wire auto_out_c_valid_0; // @[Buffer.scala:40:9]
wire auto_out_d_ready_0; // @[Buffer.scala:40:9]
wire [3:0] auto_out_e_bits_sink_0; // @[Buffer.scala:40:9]
wire auto_out_e_valid_0; // @[Buffer.scala:40:9]
assign auto_in_a_ready_0 = nodeIn_a_ready; // @[Buffer.scala:40:9]
assign auto_in_b_valid_0 = nodeIn_b_valid; // @[Buffer.scala:40:9]
assign auto_in_b_bits_opcode_0 = nodeIn_b_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_b_bits_param_0 = nodeIn_b_bits_param; // @[Buffer.scala:40:9]
assign auto_in_b_bits_size_0 = nodeIn_b_bits_size; // @[Buffer.scala:40:9]
assign auto_in_b_bits_source_0 = nodeIn_b_bits_source; // @[Buffer.scala:40:9]
assign auto_in_b_bits_address_0 = nodeIn_b_bits_address; // @[Buffer.scala:40:9]
assign auto_in_b_bits_mask_0 = nodeIn_b_bits_mask; // @[Buffer.scala:40:9]
assign auto_in_b_bits_data_0 = nodeIn_b_bits_data; // @[Buffer.scala:40:9]
assign auto_in_b_bits_corrupt_0 = nodeIn_b_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_in_c_ready_0 = nodeIn_c_ready; // @[Buffer.scala:40:9]
assign auto_in_d_valid_0 = nodeIn_d_valid; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode_0 = nodeIn_d_bits_opcode; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param_0 = nodeIn_d_bits_param; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size_0 = nodeIn_d_bits_size; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source_0 = nodeIn_d_bits_source; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink_0 = nodeIn_d_bits_sink; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied_0 = nodeIn_d_bits_denied; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data_0 = nodeIn_d_bits_data; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt_0 = nodeIn_d_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_in_e_ready_0 = nodeIn_e_ready; // @[Buffer.scala:40:9]
assign auto_out_a_valid_0 = nodeOut_a_valid; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode_0 = nodeOut_a_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param_0 = nodeOut_a_bits_param; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size_0 = nodeOut_a_bits_size; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source_0 = nodeOut_a_bits_source; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address_0 = nodeOut_a_bits_address; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask_0 = nodeOut_a_bits_mask; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data_0 = nodeOut_a_bits_data; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt_0 = nodeOut_a_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_b_ready_0 = nodeOut_b_ready; // @[Buffer.scala:40:9]
assign auto_out_c_valid_0 = nodeOut_c_valid; // @[Buffer.scala:40:9]
assign auto_out_c_bits_opcode_0 = nodeOut_c_bits_opcode; // @[Buffer.scala:40:9]
assign auto_out_c_bits_param_0 = nodeOut_c_bits_param; // @[Buffer.scala:40:9]
assign auto_out_c_bits_size_0 = nodeOut_c_bits_size; // @[Buffer.scala:40:9]
assign auto_out_c_bits_source_0 = nodeOut_c_bits_source; // @[Buffer.scala:40:9]
assign auto_out_c_bits_address_0 = nodeOut_c_bits_address; // @[Buffer.scala:40:9]
assign auto_out_c_bits_data_0 = nodeOut_c_bits_data; // @[Buffer.scala:40:9]
assign auto_out_c_bits_corrupt_0 = nodeOut_c_bits_corrupt; // @[Buffer.scala:40:9]
assign auto_out_d_ready_0 = nodeOut_d_ready; // @[Buffer.scala:40:9]
assign auto_out_e_valid_0 = nodeOut_e_valid; // @[Buffer.scala:40:9]
assign auto_out_e_bits_sink_0 = nodeOut_e_bits_sink; // @[Buffer.scala:40:9]
TLMonitor_51 monitor ( // @[Nodes.scala:27:25]
.clock (clock),
.reset (reset),
.io_in_a_ready (nodeIn_a_ready), // @[MixedNode.scala:551:17]
.io_in_a_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_in_a_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_a_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_in_a_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_in_a_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_in_a_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_in_a_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_in_a_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_in_b_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_in_b_valid (nodeIn_b_valid), // @[MixedNode.scala:551:17]
.io_in_b_bits_opcode (nodeIn_b_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_b_bits_param (nodeIn_b_bits_param), // @[MixedNode.scala:551:17]
.io_in_b_bits_size (nodeIn_b_bits_size), // @[MixedNode.scala:551:17]
.io_in_b_bits_source (nodeIn_b_bits_source), // @[MixedNode.scala:551:17]
.io_in_b_bits_address (nodeIn_b_bits_address), // @[MixedNode.scala:551:17]
.io_in_b_bits_mask (nodeIn_b_bits_mask), // @[MixedNode.scala:551:17]
.io_in_b_bits_data (nodeIn_b_bits_data), // @[MixedNode.scala:551:17]
.io_in_b_bits_corrupt (nodeIn_b_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_c_ready (nodeIn_c_ready), // @[MixedNode.scala:551:17]
.io_in_c_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_in_c_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_c_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_in_c_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_in_c_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_in_c_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_in_c_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_in_d_valid (nodeIn_d_valid), // @[MixedNode.scala:551:17]
.io_in_d_bits_opcode (nodeIn_d_bits_opcode), // @[MixedNode.scala:551:17]
.io_in_d_bits_param (nodeIn_d_bits_param), // @[MixedNode.scala:551:17]
.io_in_d_bits_size (nodeIn_d_bits_size), // @[MixedNode.scala:551:17]
.io_in_d_bits_source (nodeIn_d_bits_source), // @[MixedNode.scala:551:17]
.io_in_d_bits_sink (nodeIn_d_bits_sink), // @[MixedNode.scala:551:17]
.io_in_d_bits_denied (nodeIn_d_bits_denied), // @[MixedNode.scala:551:17]
.io_in_d_bits_data (nodeIn_d_bits_data), // @[MixedNode.scala:551:17]
.io_in_d_bits_corrupt (nodeIn_d_bits_corrupt), // @[MixedNode.scala:551:17]
.io_in_e_ready (nodeIn_e_ready), // @[MixedNode.scala:551:17]
.io_in_e_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_in_e_bits_sink (nodeIn_e_bits_sink) // @[MixedNode.scala:551:17]
); // @[Nodes.scala:27:25]
Queue2_TLBundleA_a32d128s4k4z4c nodeOut_a_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_a_ready),
.io_enq_valid (nodeIn_a_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_a_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_a_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_a_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_a_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_a_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_mask (nodeIn_a_bits_mask), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_a_bits_data), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_a_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_a_valid),
.io_deq_bits_opcode (nodeOut_a_bits_opcode),
.io_deq_bits_param (nodeOut_a_bits_param),
.io_deq_bits_size (nodeOut_a_bits_size),
.io_deq_bits_source (nodeOut_a_bits_source),
.io_deq_bits_address (nodeOut_a_bits_address),
.io_deq_bits_mask (nodeOut_a_bits_mask),
.io_deq_bits_data (nodeOut_a_bits_data),
.io_deq_bits_corrupt (nodeOut_a_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleD_a32d128s4k4z4c nodeIn_d_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_d_ready),
.io_enq_valid (nodeOut_d_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_opcode (nodeOut_d_bits_opcode), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_d_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_size (nodeOut_d_bits_size), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_d_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_sink (nodeOut_d_bits_sink), // @[MixedNode.scala:542:17]
.io_enq_bits_denied (nodeOut_d_bits_denied), // @[MixedNode.scala:542:17]
.io_enq_bits_data (nodeOut_d_bits_data), // @[MixedNode.scala:542:17]
.io_enq_bits_corrupt (nodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_d_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_d_valid),
.io_deq_bits_opcode (nodeIn_d_bits_opcode),
.io_deq_bits_param (nodeIn_d_bits_param),
.io_deq_bits_size (nodeIn_d_bits_size),
.io_deq_bits_source (nodeIn_d_bits_source),
.io_deq_bits_sink (nodeIn_d_bits_sink),
.io_deq_bits_denied (nodeIn_d_bits_denied),
.io_deq_bits_data (nodeIn_d_bits_data),
.io_deq_bits_corrupt (nodeIn_d_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleB_a32d128s4k4z4c nodeIn_b_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeOut_b_ready),
.io_enq_valid (nodeOut_b_valid), // @[MixedNode.scala:542:17]
.io_enq_bits_param (nodeOut_b_bits_param), // @[MixedNode.scala:542:17]
.io_enq_bits_source (nodeOut_b_bits_source), // @[MixedNode.scala:542:17]
.io_enq_bits_address (nodeOut_b_bits_address), // @[MixedNode.scala:542:17]
.io_deq_ready (nodeIn_b_ready), // @[MixedNode.scala:551:17]
.io_deq_valid (nodeIn_b_valid),
.io_deq_bits_opcode (nodeIn_b_bits_opcode),
.io_deq_bits_param (nodeIn_b_bits_param),
.io_deq_bits_size (nodeIn_b_bits_size),
.io_deq_bits_source (nodeIn_b_bits_source),
.io_deq_bits_address (nodeIn_b_bits_address),
.io_deq_bits_mask (nodeIn_b_bits_mask),
.io_deq_bits_data (nodeIn_b_bits_data),
.io_deq_bits_corrupt (nodeIn_b_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleC_a32d128s4k4z4c nodeOut_c_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_c_ready),
.io_enq_valid (nodeIn_c_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_opcode (nodeIn_c_bits_opcode), // @[MixedNode.scala:551:17]
.io_enq_bits_param (nodeIn_c_bits_param), // @[MixedNode.scala:551:17]
.io_enq_bits_size (nodeIn_c_bits_size), // @[MixedNode.scala:551:17]
.io_enq_bits_source (nodeIn_c_bits_source), // @[MixedNode.scala:551:17]
.io_enq_bits_address (nodeIn_c_bits_address), // @[MixedNode.scala:551:17]
.io_enq_bits_data (nodeIn_c_bits_data), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_c_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_c_valid),
.io_deq_bits_opcode (nodeOut_c_bits_opcode),
.io_deq_bits_param (nodeOut_c_bits_param),
.io_deq_bits_size (nodeOut_c_bits_size),
.io_deq_bits_source (nodeOut_c_bits_source),
.io_deq_bits_address (nodeOut_c_bits_address),
.io_deq_bits_data (nodeOut_c_bits_data),
.io_deq_bits_corrupt (nodeOut_c_bits_corrupt)
); // @[Decoupled.scala:362:21]
Queue2_TLBundleE_a32d128s4k4z4c nodeOut_e_q ( // @[Decoupled.scala:362:21]
.clock (clock),
.reset (reset),
.io_enq_ready (nodeIn_e_ready),
.io_enq_valid (nodeIn_e_valid), // @[MixedNode.scala:551:17]
.io_enq_bits_sink (nodeIn_e_bits_sink), // @[MixedNode.scala:551:17]
.io_deq_ready (nodeOut_e_ready), // @[MixedNode.scala:542:17]
.io_deq_valid (nodeOut_e_valid),
.io_deq_bits_sink (nodeOut_e_bits_sink)
); // @[Decoupled.scala:362:21]
assign auto_in_a_ready = auto_in_a_ready_0; // @[Buffer.scala:40:9]
assign auto_in_b_valid = auto_in_b_valid_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_opcode = auto_in_b_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_param = auto_in_b_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_size = auto_in_b_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_source = auto_in_b_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_address = auto_in_b_bits_address_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_mask = auto_in_b_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_data = auto_in_b_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_b_bits_corrupt = auto_in_b_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_in_c_ready = auto_in_c_ready_0; // @[Buffer.scala:40:9]
assign auto_in_d_valid = auto_in_d_valid_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_opcode = auto_in_d_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_param = auto_in_d_bits_param_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_size = auto_in_d_bits_size_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_source = auto_in_d_bits_source_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_sink = auto_in_d_bits_sink_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_denied = auto_in_d_bits_denied_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_data = auto_in_d_bits_data_0; // @[Buffer.scala:40:9]
assign auto_in_d_bits_corrupt = auto_in_d_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_in_e_ready = auto_in_e_ready_0; // @[Buffer.scala:40:9]
assign auto_out_a_valid = auto_out_a_valid_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_opcode = auto_out_a_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_param = auto_out_a_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_size = auto_out_a_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_source = auto_out_a_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_address = auto_out_a_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_mask = auto_out_a_bits_mask_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_data = auto_out_a_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_a_bits_corrupt = auto_out_a_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_b_ready = auto_out_b_ready_0; // @[Buffer.scala:40:9]
assign auto_out_c_valid = auto_out_c_valid_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_opcode = auto_out_c_bits_opcode_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_param = auto_out_c_bits_param_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_size = auto_out_c_bits_size_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_source = auto_out_c_bits_source_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_address = auto_out_c_bits_address_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_data = auto_out_c_bits_data_0; // @[Buffer.scala:40:9]
assign auto_out_c_bits_corrupt = auto_out_c_bits_corrupt_0; // @[Buffer.scala:40:9]
assign auto_out_d_ready = auto_out_d_ready_0; // @[Buffer.scala:40:9]
assign auto_out_e_valid = auto_out_e_valid_0; // @[Buffer.scala:40:9]
assign auto_out_e_bits_sink = auto_out_e_bits_sink_0; // @[Buffer.scala:40:9]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Tile_55 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>}
inst tile_0_0 of PE_311
connect tile_0_0.clock, clock
connect tile_0_0.reset, reset
connect tile_0_0.io.in_a, io.in_a[0]
connect tile_0_0.io.in_b, io.in_b[0]
connect tile_0_0.io.in_d, io.in_d[0]
connect tile_0_0.io.in_control.shift, io.in_control[0].shift
connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate
connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow
connect tile_0_0.io.in_valid, io.in_valid[0]
connect tile_0_0.io.in_id, io.in_id[0]
connect tile_0_0.io.in_last, io.in_last[0]
connect io.out_c[0], tile_0_0.io.out_c
connect io.out_control[0], tile_0_0.io.out_control
connect io.out_id[0], tile_0_0.io.out_id
connect io.out_last[0], tile_0_0.io.out_last
connect io.out_valid[0], tile_0_0.io.out_valid
connect io.out_b[0], tile_0_0.io.out_b
connect io.bad_dataflow, tile_0_0.io.bad_dataflow
connect io.out_a[0], tile_0_0.io.out_a | module Tile_55( // @[Tile.scala:16:7]
input clock, // @[Tile.scala:16:7]
input reset, // @[Tile.scala:16:7]
input [7:0] io_in_a_0, // @[Tile.scala:17:14]
input [19:0] io_in_b_0, // @[Tile.scala:17:14]
input [19:0] io_in_d_0, // @[Tile.scala:17:14]
input io_in_control_0_dataflow, // @[Tile.scala:17:14]
input io_in_control_0_propagate, // @[Tile.scala:17:14]
input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14]
input [2:0] io_in_id_0, // @[Tile.scala:17:14]
input io_in_last_0, // @[Tile.scala:17:14]
output [7:0] io_out_a_0, // @[Tile.scala:17:14]
output [19:0] io_out_c_0, // @[Tile.scala:17:14]
output [19:0] io_out_b_0, // @[Tile.scala:17:14]
output io_out_control_0_dataflow, // @[Tile.scala:17:14]
output io_out_control_0_propagate, // @[Tile.scala:17:14]
output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14]
output [2:0] io_out_id_0, // @[Tile.scala:17:14]
output io_out_last_0, // @[Tile.scala:17:14]
input io_in_valid_0, // @[Tile.scala:17:14]
output io_out_valid_0 // @[Tile.scala:17:14]
);
wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7]
wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7]
wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7]
wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7]
wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7]
wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7]
wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7]
wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7]
wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7]
wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44]
wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7]
wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7]
wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
wire io_out_control_0_propagate_0; // @[Tile.scala:16:7]
wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7]
wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7]
wire io_out_last_0_0; // @[Tile.scala:16:7]
wire io_out_valid_0_0; // @[Tile.scala:16:7]
PE_311 tile_0_0 ( // @[Tile.scala:42:44]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0_0), // @[Tile.scala:16:7]
.io_in_b (io_in_b_0_0), // @[Tile.scala:16:7]
.io_in_d (io_in_d_0_0), // @[Tile.scala:16:7]
.io_out_a (io_out_a_0_0),
.io_out_b (io_out_b_0_0),
.io_out_c (io_out_c_0_0),
.io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7]
.io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7]
.io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7]
.io_out_control_dataflow (io_out_control_0_dataflow_0),
.io_out_control_propagate (io_out_control_0_propagate_0),
.io_out_control_shift (io_out_control_0_shift_0),
.io_in_id (io_in_id_0_0), // @[Tile.scala:16:7]
.io_out_id (io_out_id_0_0),
.io_in_last (io_in_last_0_0), // @[Tile.scala:16:7]
.io_out_last (io_out_last_0_0),
.io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7]
.io_out_valid (io_out_valid_0_0)
); // @[Tile.scala:42:44]
assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7]
assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7]
assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7]
assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7]
assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7]
assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7]
assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7]
assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7]
assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module LoopBranchPredictorBank_2 :
input clock : Clock
input reset : Reset
output io : { flip f0_valid : UInt<1>, flip f0_pc : UInt<40>, flip f0_mask : UInt<4>, flip f1_ghist : UInt<64>, flip f1_lhist : UInt<1>, flip resp_in : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}[1], resp : { f1 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f2 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4], f3 : { taken : UInt<1>, is_br : UInt<1>, is_jal : UInt<1>, predicted_pc : { valid : UInt<1>, bits : UInt<40>}}[4]}, f3_meta : UInt<120>, flip f3_fire : UInt<1>, flip update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}}
connect io.resp, io.resp_in[0]
connect io.f3_meta, UInt<1>(0h0)
node s0_idx = shr(io.f0_pc, 4)
reg s1_idx : UInt, clock
connect s1_idx, s0_idx
reg s2_idx : UInt, clock
connect s2_idx, s1_idx
reg s3_idx : UInt, clock
connect s3_idx, s2_idx
reg s1_valid : UInt<1>, clock
connect s1_valid, io.f0_valid
reg s2_valid : UInt<1>, clock
connect s2_valid, s1_valid
reg s3_valid : UInt<1>, clock
connect s3_valid, s2_valid
reg s1_mask : UInt, clock
connect s1_mask, io.f0_mask
reg s2_mask : UInt, clock
connect s2_mask, s1_mask
reg s3_mask : UInt, clock
connect s3_mask, s2_mask
reg s1_pc : UInt, clock
connect s1_pc, io.f0_pc
node s0_update_idx = shr(io.update.bits.pc, 4)
reg s1_update : { valid : UInt<1>, bits : { is_mispredict_update : UInt<1>, is_repair_update : UInt<1>, btb_mispredicts : UInt<4>, pc : UInt<40>, br_mask : UInt<4>, cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_is_br : UInt<1>, cfi_is_jal : UInt<1>, cfi_is_jalr : UInt<1>, ghist : UInt<64>, lhist : UInt<1>, target : UInt<40>, meta : UInt<120>}}, clock
connect s1_update.bits.meta, io.update.bits.meta
connect s1_update.bits.target, io.update.bits.target
connect s1_update.bits.lhist, io.update.bits.lhist
connect s1_update.bits.ghist, io.update.bits.ghist
connect s1_update.bits.cfi_is_jalr, io.update.bits.cfi_is_jalr
connect s1_update.bits.cfi_is_jal, io.update.bits.cfi_is_jal
connect s1_update.bits.cfi_is_br, io.update.bits.cfi_is_br
connect s1_update.bits.cfi_mispredicted, io.update.bits.cfi_mispredicted
connect s1_update.bits.cfi_taken, io.update.bits.cfi_taken
connect s1_update.bits.cfi_idx.bits, io.update.bits.cfi_idx.bits
connect s1_update.bits.cfi_idx.valid, io.update.bits.cfi_idx.valid
connect s1_update.bits.br_mask, io.update.bits.br_mask
connect s1_update.bits.pc, io.update.bits.pc
connect s1_update.bits.btb_mispredicts, io.update.bits.btb_mispredicts
connect s1_update.bits.is_repair_update, io.update.bits.is_repair_update
connect s1_update.bits.is_mispredict_update, io.update.bits.is_mispredict_update
connect s1_update.valid, io.update.valid
reg s1_update_idx : UInt, clock
connect s1_update_idx, s0_update_idx
reg s1_update_valid : UInt<1>, clock
connect s1_update_valid, io.update.valid
inst columns_0 of LoopBranchPredictorColumn_8
connect columns_0.clock, clock
connect columns_0.reset, reset
inst columns_1 of LoopBranchPredictorColumn_9
connect columns_1.clock, clock
connect columns_1.reset, reset
inst columns_2 of LoopBranchPredictorColumn_10
connect columns_2.clock, clock
connect columns_2.reset, reset
inst columns_3 of LoopBranchPredictorColumn_11
connect columns_3.clock, clock
connect columns_3.reset, reset
wire f3_meta : { s_cnt : UInt<10>}[4]
node lo = cat(f3_meta[1].s_cnt, f3_meta[0].s_cnt)
node hi = cat(f3_meta[3].s_cnt, f3_meta[2].s_cnt)
node _T = cat(hi, lo)
wire update_meta : { s_cnt : UInt<10>}[4]
wire _update_meta_WIRE : UInt<40>
connect _update_meta_WIRE, s1_update.bits.meta
node _update_meta_T = bits(_update_meta_WIRE, 9, 0)
connect update_meta[0].s_cnt, _update_meta_T
node _update_meta_T_1 = bits(_update_meta_WIRE, 19, 10)
connect update_meta[1].s_cnt, _update_meta_T_1
node _update_meta_T_2 = bits(_update_meta_WIRE, 29, 20)
connect update_meta[2].s_cnt, _update_meta_T_2
node _update_meta_T_3 = bits(_update_meta_WIRE, 39, 30)
connect update_meta[3].s_cnt, _update_meta_T_3
connect columns_0.io.f2_req_valid, s2_valid
connect columns_0.io.f2_req_idx, s2_idx
node _columns_0_io_f3_req_fire_T = bits(s3_mask, 0, 0)
node _columns_0_io_f3_req_fire_T_1 = and(s3_valid, _columns_0_io_f3_req_fire_T)
node _columns_0_io_f3_req_fire_T_2 = and(_columns_0_io_f3_req_fire_T_1, io.f3_fire)
node _columns_0_io_f3_req_fire_T_3 = and(io.resp_in[0].f2[0].predicted_pc.valid, io.resp_in[0].f2[0].is_br)
reg columns_0_io_f3_req_fire_REG : UInt<1>, clock
connect columns_0_io_f3_req_fire_REG, _columns_0_io_f3_req_fire_T_3
node _columns_0_io_f3_req_fire_T_4 = and(_columns_0_io_f3_req_fire_T_2, columns_0_io_f3_req_fire_REG)
connect columns_0.io.f3_req_fire, _columns_0_io_f3_req_fire_T_4
connect columns_0.io.f3_pred_in, io.resp_in[0].f3[0].taken
connect io.resp.f3[0].taken, columns_0.io.f3_pred
node _columns_0_io_update_mispredict_T = bits(s1_update.bits.br_mask, 0, 0)
node _columns_0_io_update_mispredict_T_1 = and(s1_update.valid, _columns_0_io_update_mispredict_T)
node _columns_0_io_update_mispredict_T_2 = and(_columns_0_io_update_mispredict_T_1, s1_update.bits.is_mispredict_update)
node _columns_0_io_update_mispredict_T_3 = and(_columns_0_io_update_mispredict_T_2, s1_update.bits.cfi_mispredicted)
connect columns_0.io.update_mispredict, _columns_0_io_update_mispredict_T_3
node _columns_0_io_update_repair_T = bits(s1_update.bits.br_mask, 0, 0)
node _columns_0_io_update_repair_T_1 = and(s1_update.valid, _columns_0_io_update_repair_T)
node _columns_0_io_update_repair_T_2 = and(_columns_0_io_update_repair_T_1, s1_update.bits.is_repair_update)
connect columns_0.io.update_repair, _columns_0_io_update_repair_T_2
connect columns_0.io.update_idx, s1_update_idx
connect columns_0.io.update_resolve_dir, s1_update.bits.cfi_taken
connect columns_0.io.update_meta.s_cnt, update_meta[0].s_cnt
connect f3_meta[0], columns_0.io.f3_meta
connect columns_1.io.f2_req_valid, s2_valid
connect columns_1.io.f2_req_idx, s2_idx
node _columns_1_io_f3_req_fire_T = bits(s3_mask, 1, 1)
node _columns_1_io_f3_req_fire_T_1 = and(s3_valid, _columns_1_io_f3_req_fire_T)
node _columns_1_io_f3_req_fire_T_2 = and(_columns_1_io_f3_req_fire_T_1, io.f3_fire)
node _columns_1_io_f3_req_fire_T_3 = and(io.resp_in[0].f2[1].predicted_pc.valid, io.resp_in[0].f2[1].is_br)
reg columns_1_io_f3_req_fire_REG : UInt<1>, clock
connect columns_1_io_f3_req_fire_REG, _columns_1_io_f3_req_fire_T_3
node _columns_1_io_f3_req_fire_T_4 = and(_columns_1_io_f3_req_fire_T_2, columns_1_io_f3_req_fire_REG)
connect columns_1.io.f3_req_fire, _columns_1_io_f3_req_fire_T_4
connect columns_1.io.f3_pred_in, io.resp_in[0].f3[1].taken
connect io.resp.f3[1].taken, columns_1.io.f3_pred
node _columns_1_io_update_mispredict_T = bits(s1_update.bits.br_mask, 1, 1)
node _columns_1_io_update_mispredict_T_1 = and(s1_update.valid, _columns_1_io_update_mispredict_T)
node _columns_1_io_update_mispredict_T_2 = and(_columns_1_io_update_mispredict_T_1, s1_update.bits.is_mispredict_update)
node _columns_1_io_update_mispredict_T_3 = and(_columns_1_io_update_mispredict_T_2, s1_update.bits.cfi_mispredicted)
connect columns_1.io.update_mispredict, _columns_1_io_update_mispredict_T_3
node _columns_1_io_update_repair_T = bits(s1_update.bits.br_mask, 1, 1)
node _columns_1_io_update_repair_T_1 = and(s1_update.valid, _columns_1_io_update_repair_T)
node _columns_1_io_update_repair_T_2 = and(_columns_1_io_update_repair_T_1, s1_update.bits.is_repair_update)
connect columns_1.io.update_repair, _columns_1_io_update_repair_T_2
connect columns_1.io.update_idx, s1_update_idx
connect columns_1.io.update_resolve_dir, s1_update.bits.cfi_taken
connect columns_1.io.update_meta.s_cnt, update_meta[1].s_cnt
connect f3_meta[1], columns_1.io.f3_meta
connect columns_2.io.f2_req_valid, s2_valid
connect columns_2.io.f2_req_idx, s2_idx
node _columns_2_io_f3_req_fire_T = bits(s3_mask, 2, 2)
node _columns_2_io_f3_req_fire_T_1 = and(s3_valid, _columns_2_io_f3_req_fire_T)
node _columns_2_io_f3_req_fire_T_2 = and(_columns_2_io_f3_req_fire_T_1, io.f3_fire)
node _columns_2_io_f3_req_fire_T_3 = and(io.resp_in[0].f2[2].predicted_pc.valid, io.resp_in[0].f2[2].is_br)
reg columns_2_io_f3_req_fire_REG : UInt<1>, clock
connect columns_2_io_f3_req_fire_REG, _columns_2_io_f3_req_fire_T_3
node _columns_2_io_f3_req_fire_T_4 = and(_columns_2_io_f3_req_fire_T_2, columns_2_io_f3_req_fire_REG)
connect columns_2.io.f3_req_fire, _columns_2_io_f3_req_fire_T_4
connect columns_2.io.f3_pred_in, io.resp_in[0].f3[2].taken
connect io.resp.f3[2].taken, columns_2.io.f3_pred
node _columns_2_io_update_mispredict_T = bits(s1_update.bits.br_mask, 2, 2)
node _columns_2_io_update_mispredict_T_1 = and(s1_update.valid, _columns_2_io_update_mispredict_T)
node _columns_2_io_update_mispredict_T_2 = and(_columns_2_io_update_mispredict_T_1, s1_update.bits.is_mispredict_update)
node _columns_2_io_update_mispredict_T_3 = and(_columns_2_io_update_mispredict_T_2, s1_update.bits.cfi_mispredicted)
connect columns_2.io.update_mispredict, _columns_2_io_update_mispredict_T_3
node _columns_2_io_update_repair_T = bits(s1_update.bits.br_mask, 2, 2)
node _columns_2_io_update_repair_T_1 = and(s1_update.valid, _columns_2_io_update_repair_T)
node _columns_2_io_update_repair_T_2 = and(_columns_2_io_update_repair_T_1, s1_update.bits.is_repair_update)
connect columns_2.io.update_repair, _columns_2_io_update_repair_T_2
connect columns_2.io.update_idx, s1_update_idx
connect columns_2.io.update_resolve_dir, s1_update.bits.cfi_taken
connect columns_2.io.update_meta.s_cnt, update_meta[2].s_cnt
connect f3_meta[2], columns_2.io.f3_meta
connect columns_3.io.f2_req_valid, s2_valid
connect columns_3.io.f2_req_idx, s2_idx
node _columns_3_io_f3_req_fire_T = bits(s3_mask, 3, 3)
node _columns_3_io_f3_req_fire_T_1 = and(s3_valid, _columns_3_io_f3_req_fire_T)
node _columns_3_io_f3_req_fire_T_2 = and(_columns_3_io_f3_req_fire_T_1, io.f3_fire)
node _columns_3_io_f3_req_fire_T_3 = and(io.resp_in[0].f2[3].predicted_pc.valid, io.resp_in[0].f2[3].is_br)
reg columns_3_io_f3_req_fire_REG : UInt<1>, clock
connect columns_3_io_f3_req_fire_REG, _columns_3_io_f3_req_fire_T_3
node _columns_3_io_f3_req_fire_T_4 = and(_columns_3_io_f3_req_fire_T_2, columns_3_io_f3_req_fire_REG)
connect columns_3.io.f3_req_fire, _columns_3_io_f3_req_fire_T_4
connect columns_3.io.f3_pred_in, io.resp_in[0].f3[3].taken
connect io.resp.f3[3].taken, columns_3.io.f3_pred
node _columns_3_io_update_mispredict_T = bits(s1_update.bits.br_mask, 3, 3)
node _columns_3_io_update_mispredict_T_1 = and(s1_update.valid, _columns_3_io_update_mispredict_T)
node _columns_3_io_update_mispredict_T_2 = and(_columns_3_io_update_mispredict_T_1, s1_update.bits.is_mispredict_update)
node _columns_3_io_update_mispredict_T_3 = and(_columns_3_io_update_mispredict_T_2, s1_update.bits.cfi_mispredicted)
connect columns_3.io.update_mispredict, _columns_3_io_update_mispredict_T_3
node _columns_3_io_update_repair_T = bits(s1_update.bits.br_mask, 3, 3)
node _columns_3_io_update_repair_T_1 = and(s1_update.valid, _columns_3_io_update_repair_T)
node _columns_3_io_update_repair_T_2 = and(_columns_3_io_update_repair_T_1, s1_update.bits.is_repair_update)
connect columns_3.io.update_repair, _columns_3_io_update_repair_T_2
connect columns_3.io.update_idx, s1_update_idx
connect columns_3.io.update_resolve_dir, s1_update.bits.cfi_taken
connect columns_3.io.update_meta.s_cnt, update_meta[3].s_cnt
connect f3_meta[3], columns_3.io.f3_meta
node io_f3_meta_lo = cat(f3_meta[1].s_cnt, f3_meta[0].s_cnt)
node io_f3_meta_hi = cat(f3_meta[3].s_cnt, f3_meta[2].s_cnt)
node _io_f3_meta_T = cat(io_f3_meta_hi, io_f3_meta_lo)
connect io.f3_meta, _io_f3_meta_T | module LoopBranchPredictorBank_2( // @[loop.scala:20:7]
input clock, // @[loop.scala:20:7]
input reset, // @[loop.scala:20:7]
input io_f0_valid, // @[predictor.scala:140:14]
input [39:0] io_f0_pc, // @[predictor.scala:140:14]
input [3:0] io_f0_mask, // @[predictor.scala:140:14]
input [63:0] io_f1_ghist, // @[predictor.scala:140:14]
input io_resp_in_0_f1_0_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f1_0_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f1_0_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f1_0_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f1_0_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f1_1_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f1_1_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f1_1_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f1_1_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f1_1_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f1_2_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f1_2_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f1_2_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f1_2_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f1_2_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f1_3_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f1_3_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f1_3_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f1_3_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f1_3_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f2_0_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f2_0_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f2_0_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f2_0_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f2_0_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f2_1_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f2_1_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f2_1_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f2_1_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f2_1_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f2_2_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f2_2_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f2_2_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f2_2_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f2_2_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f2_3_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f2_3_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f2_3_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f2_3_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f2_3_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f3_0_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f3_0_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f3_0_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f3_0_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f3_0_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f3_1_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f3_1_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f3_1_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f3_1_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f3_1_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f3_2_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f3_2_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f3_2_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f3_2_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f3_2_predicted_pc_bits, // @[predictor.scala:140:14]
input io_resp_in_0_f3_3_taken, // @[predictor.scala:140:14]
input io_resp_in_0_f3_3_is_br, // @[predictor.scala:140:14]
input io_resp_in_0_f3_3_is_jal, // @[predictor.scala:140:14]
input io_resp_in_0_f3_3_predicted_pc_valid, // @[predictor.scala:140:14]
input [39:0] io_resp_in_0_f3_3_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_0_taken, // @[predictor.scala:140:14]
output io_resp_f1_0_is_br, // @[predictor.scala:140:14]
output io_resp_f1_0_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_0_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_0_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_1_taken, // @[predictor.scala:140:14]
output io_resp_f1_1_is_br, // @[predictor.scala:140:14]
output io_resp_f1_1_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_1_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_1_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_2_taken, // @[predictor.scala:140:14]
output io_resp_f1_2_is_br, // @[predictor.scala:140:14]
output io_resp_f1_2_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_2_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_2_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f1_3_taken, // @[predictor.scala:140:14]
output io_resp_f1_3_is_br, // @[predictor.scala:140:14]
output io_resp_f1_3_is_jal, // @[predictor.scala:140:14]
output io_resp_f1_3_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f1_3_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_0_taken, // @[predictor.scala:140:14]
output io_resp_f2_0_is_br, // @[predictor.scala:140:14]
output io_resp_f2_0_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_0_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_0_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_1_taken, // @[predictor.scala:140:14]
output io_resp_f2_1_is_br, // @[predictor.scala:140:14]
output io_resp_f2_1_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_1_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_1_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_2_taken, // @[predictor.scala:140:14]
output io_resp_f2_2_is_br, // @[predictor.scala:140:14]
output io_resp_f2_2_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_2_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_2_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f2_3_taken, // @[predictor.scala:140:14]
output io_resp_f2_3_is_br, // @[predictor.scala:140:14]
output io_resp_f2_3_is_jal, // @[predictor.scala:140:14]
output io_resp_f2_3_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f2_3_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_0_taken, // @[predictor.scala:140:14]
output io_resp_f3_0_is_br, // @[predictor.scala:140:14]
output io_resp_f3_0_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_0_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_0_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_1_taken, // @[predictor.scala:140:14]
output io_resp_f3_1_is_br, // @[predictor.scala:140:14]
output io_resp_f3_1_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_1_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_1_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_2_taken, // @[predictor.scala:140:14]
output io_resp_f3_2_is_br, // @[predictor.scala:140:14]
output io_resp_f3_2_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_2_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_2_predicted_pc_bits, // @[predictor.scala:140:14]
output io_resp_f3_3_taken, // @[predictor.scala:140:14]
output io_resp_f3_3_is_br, // @[predictor.scala:140:14]
output io_resp_f3_3_is_jal, // @[predictor.scala:140:14]
output io_resp_f3_3_predicted_pc_valid, // @[predictor.scala:140:14]
output [39:0] io_resp_f3_3_predicted_pc_bits, // @[predictor.scala:140:14]
output [119:0] io_f3_meta, // @[predictor.scala:140:14]
input io_f3_fire, // @[predictor.scala:140:14]
input io_update_valid, // @[predictor.scala:140:14]
input io_update_bits_is_mispredict_update, // @[predictor.scala:140:14]
input io_update_bits_is_repair_update, // @[predictor.scala:140:14]
input [3:0] io_update_bits_btb_mispredicts, // @[predictor.scala:140:14]
input [39:0] io_update_bits_pc, // @[predictor.scala:140:14]
input [3:0] io_update_bits_br_mask, // @[predictor.scala:140:14]
input io_update_bits_cfi_idx_valid, // @[predictor.scala:140:14]
input [1:0] io_update_bits_cfi_idx_bits, // @[predictor.scala:140:14]
input io_update_bits_cfi_taken, // @[predictor.scala:140:14]
input io_update_bits_cfi_mispredicted, // @[predictor.scala:140:14]
input io_update_bits_cfi_is_br, // @[predictor.scala:140:14]
input io_update_bits_cfi_is_jal, // @[predictor.scala:140:14]
input io_update_bits_cfi_is_jalr, // @[predictor.scala:140:14]
input [63:0] io_update_bits_ghist, // @[predictor.scala:140:14]
input io_update_bits_lhist, // @[predictor.scala:140:14]
input [39:0] io_update_bits_target, // @[predictor.scala:140:14]
input [119:0] io_update_bits_meta // @[predictor.scala:140:14]
);
wire io_f0_valid_0 = io_f0_valid; // @[loop.scala:20:7]
wire [39:0] io_f0_pc_0 = io_f0_pc; // @[loop.scala:20:7]
wire [3:0] io_f0_mask_0 = io_f0_mask; // @[loop.scala:20:7]
wire [63:0] io_f1_ghist_0 = io_f1_ghist; // @[loop.scala:20:7]
wire io_resp_in_0_f1_0_taken_0 = io_resp_in_0_f1_0_taken; // @[loop.scala:20:7]
wire io_resp_in_0_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br; // @[loop.scala:20:7]
wire io_resp_in_0_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal; // @[loop.scala:20:7]
wire io_resp_in_0_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid; // @[loop.scala:20:7]
wire [39:0] io_resp_in_0_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits; // @[loop.scala:20:7]
wire io_resp_in_0_f1_1_taken_0 = io_resp_in_0_f1_1_taken; // @[loop.scala:20:7]
wire io_resp_in_0_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br; // @[loop.scala:20:7]
wire io_resp_in_0_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal; // @[loop.scala:20:7]
wire io_resp_in_0_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid; // @[loop.scala:20:7]
wire [39:0] io_resp_in_0_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits; // @[loop.scala:20:7]
wire io_resp_in_0_f1_2_taken_0 = io_resp_in_0_f1_2_taken; // @[loop.scala:20:7]
wire io_resp_in_0_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br; // @[loop.scala:20:7]
wire io_resp_in_0_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal; // @[loop.scala:20:7]
wire io_resp_in_0_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid; // @[loop.scala:20:7]
wire [39:0] io_resp_in_0_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits; // @[loop.scala:20:7]
wire io_resp_in_0_f1_3_taken_0 = io_resp_in_0_f1_3_taken; // @[loop.scala:20:7]
wire io_resp_in_0_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br; // @[loop.scala:20:7]
wire io_resp_in_0_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal; // @[loop.scala:20:7]
wire io_resp_in_0_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid; // @[loop.scala:20:7]
wire [39:0] io_resp_in_0_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits; // @[loop.scala:20:7]
wire io_resp_in_0_f2_0_taken_0 = io_resp_in_0_f2_0_taken; // @[loop.scala:20:7]
wire io_resp_in_0_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br; // @[loop.scala:20:7]
wire io_resp_in_0_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal; // @[loop.scala:20:7]
wire io_resp_in_0_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid; // @[loop.scala:20:7]
wire [39:0] io_resp_in_0_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits; // @[loop.scala:20:7]
wire io_resp_in_0_f2_1_taken_0 = io_resp_in_0_f2_1_taken; // @[loop.scala:20:7]
wire io_resp_in_0_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br; // @[loop.scala:20:7]
wire io_resp_in_0_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal; // @[loop.scala:20:7]
wire io_resp_in_0_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid; // @[loop.scala:20:7]
wire [39:0] io_resp_in_0_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits; // @[loop.scala:20:7]
wire io_resp_in_0_f2_2_taken_0 = io_resp_in_0_f2_2_taken; // @[loop.scala:20:7]
wire io_resp_in_0_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br; // @[loop.scala:20:7]
wire io_resp_in_0_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal; // @[loop.scala:20:7]
wire io_resp_in_0_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid; // @[loop.scala:20:7]
wire [39:0] io_resp_in_0_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits; // @[loop.scala:20:7]
wire io_resp_in_0_f2_3_taken_0 = io_resp_in_0_f2_3_taken; // @[loop.scala:20:7]
wire io_resp_in_0_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br; // @[loop.scala:20:7]
wire io_resp_in_0_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal; // @[loop.scala:20:7]
wire io_resp_in_0_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid; // @[loop.scala:20:7]
wire [39:0] io_resp_in_0_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits; // @[loop.scala:20:7]
wire io_resp_in_0_f3_0_taken_0 = io_resp_in_0_f3_0_taken; // @[loop.scala:20:7]
wire io_resp_in_0_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br; // @[loop.scala:20:7]
wire io_resp_in_0_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal; // @[loop.scala:20:7]
wire io_resp_in_0_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid; // @[loop.scala:20:7]
wire [39:0] io_resp_in_0_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits; // @[loop.scala:20:7]
wire io_resp_in_0_f3_1_taken_0 = io_resp_in_0_f3_1_taken; // @[loop.scala:20:7]
wire io_resp_in_0_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br; // @[loop.scala:20:7]
wire io_resp_in_0_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal; // @[loop.scala:20:7]
wire io_resp_in_0_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid; // @[loop.scala:20:7]
wire [39:0] io_resp_in_0_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits; // @[loop.scala:20:7]
wire io_resp_in_0_f3_2_taken_0 = io_resp_in_0_f3_2_taken; // @[loop.scala:20:7]
wire io_resp_in_0_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br; // @[loop.scala:20:7]
wire io_resp_in_0_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal; // @[loop.scala:20:7]
wire io_resp_in_0_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid; // @[loop.scala:20:7]
wire [39:0] io_resp_in_0_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits; // @[loop.scala:20:7]
wire io_resp_in_0_f3_3_taken_0 = io_resp_in_0_f3_3_taken; // @[loop.scala:20:7]
wire io_resp_in_0_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br; // @[loop.scala:20:7]
wire io_resp_in_0_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal; // @[loop.scala:20:7]
wire io_resp_in_0_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid; // @[loop.scala:20:7]
wire [39:0] io_resp_in_0_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits; // @[loop.scala:20:7]
wire io_f3_fire_0 = io_f3_fire; // @[loop.scala:20:7]
wire io_update_valid_0 = io_update_valid; // @[loop.scala:20:7]
wire io_update_bits_is_mispredict_update_0 = io_update_bits_is_mispredict_update; // @[loop.scala:20:7]
wire io_update_bits_is_repair_update_0 = io_update_bits_is_repair_update; // @[loop.scala:20:7]
wire [3:0] io_update_bits_btb_mispredicts_0 = io_update_bits_btb_mispredicts; // @[loop.scala:20:7]
wire [39:0] io_update_bits_pc_0 = io_update_bits_pc; // @[loop.scala:20:7]
wire [3:0] io_update_bits_br_mask_0 = io_update_bits_br_mask; // @[loop.scala:20:7]
wire io_update_bits_cfi_idx_valid_0 = io_update_bits_cfi_idx_valid; // @[loop.scala:20:7]
wire [1:0] io_update_bits_cfi_idx_bits_0 = io_update_bits_cfi_idx_bits; // @[loop.scala:20:7]
wire io_update_bits_cfi_taken_0 = io_update_bits_cfi_taken; // @[loop.scala:20:7]
wire io_update_bits_cfi_mispredicted_0 = io_update_bits_cfi_mispredicted; // @[loop.scala:20:7]
wire io_update_bits_cfi_is_br_0 = io_update_bits_cfi_is_br; // @[loop.scala:20:7]
wire io_update_bits_cfi_is_jal_0 = io_update_bits_cfi_is_jal; // @[loop.scala:20:7]
wire io_update_bits_cfi_is_jalr_0 = io_update_bits_cfi_is_jalr; // @[loop.scala:20:7]
wire [63:0] io_update_bits_ghist_0 = io_update_bits_ghist; // @[loop.scala:20:7]
wire io_update_bits_lhist_0 = io_update_bits_lhist; // @[loop.scala:20:7]
wire [39:0] io_update_bits_target_0 = io_update_bits_target; // @[loop.scala:20:7]
wire [119:0] io_update_bits_meta_0 = io_update_bits_meta; // @[loop.scala:20:7]
wire io_f1_lhist = 1'h0; // @[predictor.scala:140:14]
wire io_resp_f1_0_taken_0 = io_resp_in_0_f1_0_taken_0; // @[loop.scala:20:7]
wire io_resp_f1_0_is_br_0 = io_resp_in_0_f1_0_is_br_0; // @[loop.scala:20:7]
wire io_resp_f1_0_is_jal_0 = io_resp_in_0_f1_0_is_jal_0; // @[loop.scala:20:7]
wire io_resp_f1_0_predicted_pc_valid_0 = io_resp_in_0_f1_0_predicted_pc_valid_0; // @[loop.scala:20:7]
wire [39:0] io_resp_f1_0_predicted_pc_bits_0 = io_resp_in_0_f1_0_predicted_pc_bits_0; // @[loop.scala:20:7]
wire io_resp_f1_1_taken_0 = io_resp_in_0_f1_1_taken_0; // @[loop.scala:20:7]
wire io_resp_f1_1_is_br_0 = io_resp_in_0_f1_1_is_br_0; // @[loop.scala:20:7]
wire io_resp_f1_1_is_jal_0 = io_resp_in_0_f1_1_is_jal_0; // @[loop.scala:20:7]
wire io_resp_f1_1_predicted_pc_valid_0 = io_resp_in_0_f1_1_predicted_pc_valid_0; // @[loop.scala:20:7]
wire [39:0] io_resp_f1_1_predicted_pc_bits_0 = io_resp_in_0_f1_1_predicted_pc_bits_0; // @[loop.scala:20:7]
wire io_resp_f1_2_taken_0 = io_resp_in_0_f1_2_taken_0; // @[loop.scala:20:7]
wire io_resp_f1_2_is_br_0 = io_resp_in_0_f1_2_is_br_0; // @[loop.scala:20:7]
wire io_resp_f1_2_is_jal_0 = io_resp_in_0_f1_2_is_jal_0; // @[loop.scala:20:7]
wire io_resp_f1_2_predicted_pc_valid_0 = io_resp_in_0_f1_2_predicted_pc_valid_0; // @[loop.scala:20:7]
wire [39:0] io_resp_f1_2_predicted_pc_bits_0 = io_resp_in_0_f1_2_predicted_pc_bits_0; // @[loop.scala:20:7]
wire io_resp_f1_3_taken_0 = io_resp_in_0_f1_3_taken_0; // @[loop.scala:20:7]
wire io_resp_f1_3_is_br_0 = io_resp_in_0_f1_3_is_br_0; // @[loop.scala:20:7]
wire io_resp_f1_3_is_jal_0 = io_resp_in_0_f1_3_is_jal_0; // @[loop.scala:20:7]
wire io_resp_f1_3_predicted_pc_valid_0 = io_resp_in_0_f1_3_predicted_pc_valid_0; // @[loop.scala:20:7]
wire [39:0] io_resp_f1_3_predicted_pc_bits_0 = io_resp_in_0_f1_3_predicted_pc_bits_0; // @[loop.scala:20:7]
wire io_resp_f2_0_taken_0 = io_resp_in_0_f2_0_taken_0; // @[loop.scala:20:7]
wire io_resp_f2_0_is_br_0 = io_resp_in_0_f2_0_is_br_0; // @[loop.scala:20:7]
wire io_resp_f2_0_is_jal_0 = io_resp_in_0_f2_0_is_jal_0; // @[loop.scala:20:7]
wire io_resp_f2_0_predicted_pc_valid_0 = io_resp_in_0_f2_0_predicted_pc_valid_0; // @[loop.scala:20:7]
wire [39:0] io_resp_f2_0_predicted_pc_bits_0 = io_resp_in_0_f2_0_predicted_pc_bits_0; // @[loop.scala:20:7]
wire io_resp_f2_1_taken_0 = io_resp_in_0_f2_1_taken_0; // @[loop.scala:20:7]
wire io_resp_f2_1_is_br_0 = io_resp_in_0_f2_1_is_br_0; // @[loop.scala:20:7]
wire io_resp_f2_1_is_jal_0 = io_resp_in_0_f2_1_is_jal_0; // @[loop.scala:20:7]
wire io_resp_f2_1_predicted_pc_valid_0 = io_resp_in_0_f2_1_predicted_pc_valid_0; // @[loop.scala:20:7]
wire [39:0] io_resp_f2_1_predicted_pc_bits_0 = io_resp_in_0_f2_1_predicted_pc_bits_0; // @[loop.scala:20:7]
wire io_resp_f2_2_taken_0 = io_resp_in_0_f2_2_taken_0; // @[loop.scala:20:7]
wire io_resp_f2_2_is_br_0 = io_resp_in_0_f2_2_is_br_0; // @[loop.scala:20:7]
wire io_resp_f2_2_is_jal_0 = io_resp_in_0_f2_2_is_jal_0; // @[loop.scala:20:7]
wire io_resp_f2_2_predicted_pc_valid_0 = io_resp_in_0_f2_2_predicted_pc_valid_0; // @[loop.scala:20:7]
wire [39:0] io_resp_f2_2_predicted_pc_bits_0 = io_resp_in_0_f2_2_predicted_pc_bits_0; // @[loop.scala:20:7]
wire io_resp_f2_3_taken_0 = io_resp_in_0_f2_3_taken_0; // @[loop.scala:20:7]
wire io_resp_f2_3_is_br_0 = io_resp_in_0_f2_3_is_br_0; // @[loop.scala:20:7]
wire io_resp_f2_3_is_jal_0 = io_resp_in_0_f2_3_is_jal_0; // @[loop.scala:20:7]
wire io_resp_f2_3_predicted_pc_valid_0 = io_resp_in_0_f2_3_predicted_pc_valid_0; // @[loop.scala:20:7]
wire [39:0] io_resp_f2_3_predicted_pc_bits_0 = io_resp_in_0_f2_3_predicted_pc_bits_0; // @[loop.scala:20:7]
wire io_resp_f3_0_is_br_0 = io_resp_in_0_f3_0_is_br_0; // @[loop.scala:20:7]
wire io_resp_f3_0_is_jal_0 = io_resp_in_0_f3_0_is_jal_0; // @[loop.scala:20:7]
wire io_resp_f3_0_predicted_pc_valid_0 = io_resp_in_0_f3_0_predicted_pc_valid_0; // @[loop.scala:20:7]
wire [39:0] io_resp_f3_0_predicted_pc_bits_0 = io_resp_in_0_f3_0_predicted_pc_bits_0; // @[loop.scala:20:7]
wire io_resp_f3_1_is_br_0 = io_resp_in_0_f3_1_is_br_0; // @[loop.scala:20:7]
wire io_resp_f3_1_is_jal_0 = io_resp_in_0_f3_1_is_jal_0; // @[loop.scala:20:7]
wire io_resp_f3_1_predicted_pc_valid_0 = io_resp_in_0_f3_1_predicted_pc_valid_0; // @[loop.scala:20:7]
wire [39:0] io_resp_f3_1_predicted_pc_bits_0 = io_resp_in_0_f3_1_predicted_pc_bits_0; // @[loop.scala:20:7]
wire io_resp_f3_2_is_br_0 = io_resp_in_0_f3_2_is_br_0; // @[loop.scala:20:7]
wire io_resp_f3_2_is_jal_0 = io_resp_in_0_f3_2_is_jal_0; // @[loop.scala:20:7]
wire io_resp_f3_2_predicted_pc_valid_0 = io_resp_in_0_f3_2_predicted_pc_valid_0; // @[loop.scala:20:7]
wire [39:0] io_resp_f3_2_predicted_pc_bits_0 = io_resp_in_0_f3_2_predicted_pc_bits_0; // @[loop.scala:20:7]
wire io_resp_f3_3_is_br_0 = io_resp_in_0_f3_3_is_br_0; // @[loop.scala:20:7]
wire io_resp_f3_3_is_jal_0 = io_resp_in_0_f3_3_is_jal_0; // @[loop.scala:20:7]
wire io_resp_f3_3_predicted_pc_valid_0 = io_resp_in_0_f3_3_predicted_pc_valid_0; // @[loop.scala:20:7]
wire [39:0] io_resp_f3_3_predicted_pc_bits_0 = io_resp_in_0_f3_3_predicted_pc_bits_0; // @[loop.scala:20:7]
wire io_resp_f3_0_taken_0; // @[loop.scala:20:7]
wire io_resp_f3_1_taken_0; // @[loop.scala:20:7]
wire io_resp_f3_2_taken_0; // @[loop.scala:20:7]
wire io_resp_f3_3_taken_0; // @[loop.scala:20:7]
wire [119:0] io_f3_meta_0; // @[loop.scala:20:7]
wire [35:0] s0_idx = io_f0_pc_0[39:4]; // @[frontend.scala:162:35]
reg [35:0] s1_idx; // @[predictor.scala:163:29]
reg [35:0] s2_idx; // @[predictor.scala:164:29]
reg [35:0] s3_idx; // @[predictor.scala:165:29]
reg s1_valid; // @[predictor.scala:168:25]
reg s2_valid; // @[predictor.scala:169:25]
reg s3_valid; // @[predictor.scala:170:25]
reg [3:0] s1_mask; // @[predictor.scala:173:24]
reg [3:0] s2_mask; // @[predictor.scala:174:24]
reg [3:0] s3_mask; // @[predictor.scala:175:24]
reg [39:0] s1_pc; // @[predictor.scala:178:22]
wire [35:0] s0_update_idx = io_update_bits_pc_0[39:4]; // @[frontend.scala:162:35]
reg s1_update_valid; // @[predictor.scala:184:30]
reg s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30]
reg s1_update_bits_is_repair_update; // @[predictor.scala:184:30]
reg [3:0] s1_update_bits_btb_mispredicts; // @[predictor.scala:184:30]
reg [39:0] s1_update_bits_pc; // @[predictor.scala:184:30]
reg [3:0] s1_update_bits_br_mask; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_idx_valid; // @[predictor.scala:184:30]
reg [1:0] s1_update_bits_cfi_idx_bits; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_taken; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_is_br; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_is_jal; // @[predictor.scala:184:30]
reg s1_update_bits_cfi_is_jalr; // @[predictor.scala:184:30]
reg [63:0] s1_update_bits_ghist; // @[predictor.scala:184:30]
reg s1_update_bits_lhist; // @[predictor.scala:184:30]
reg [39:0] s1_update_bits_target; // @[predictor.scala:184:30]
reg [119:0] s1_update_bits_meta; // @[predictor.scala:184:30]
reg [35:0] s1_update_idx; // @[predictor.scala:185:30]
reg s1_update_valid_0; // @[predictor.scala:186:32]
wire [9:0] f3_meta_0_s_cnt; // @[loop.scala:184:21]
wire [9:0] f3_meta_1_s_cnt; // @[loop.scala:184:21]
wire [9:0] f3_meta_2_s_cnt; // @[loop.scala:184:21]
wire [9:0] f3_meta_3_s_cnt; // @[loop.scala:184:21]
wire [19:0] _GEN = {f3_meta_1_s_cnt, f3_meta_0_s_cnt}; // @[loop.scala:184:21, :185:33]
wire [19:0] lo; // @[loop.scala:185:33]
assign lo = _GEN; // @[loop.scala:185:33]
wire [19:0] io_f3_meta_lo; // @[loop.scala:212:25]
assign io_f3_meta_lo = _GEN; // @[loop.scala:185:33, :212:25]
wire [19:0] _GEN_0 = {f3_meta_3_s_cnt, f3_meta_2_s_cnt}; // @[loop.scala:184:21, :185:33]
wire [19:0] hi; // @[loop.scala:185:33]
assign hi = _GEN_0; // @[loop.scala:185:33]
wire [19:0] io_f3_meta_hi; // @[loop.scala:212:25]
assign io_f3_meta_hi = _GEN_0; // @[loop.scala:185:33, :212:25]
wire [9:0] _update_meta_T; // @[loop.scala:187:49]
wire [9:0] _update_meta_T_1; // @[loop.scala:187:49]
wire [9:0] _update_meta_T_2; // @[loop.scala:187:49]
wire [9:0] _update_meta_T_3; // @[loop.scala:187:49]
wire [9:0] update_meta_0_s_cnt; // @[loop.scala:187:49]
wire [9:0] update_meta_1_s_cnt; // @[loop.scala:187:49]
wire [9:0] update_meta_2_s_cnt; // @[loop.scala:187:49]
wire [9:0] update_meta_3_s_cnt; // @[loop.scala:187:49]
wire [39:0] _update_meta_WIRE = s1_update_bits_meta[39:0]; // @[predictor.scala:184:30]
assign _update_meta_T = _update_meta_WIRE[9:0]; // @[loop.scala:187:49]
assign update_meta_0_s_cnt = _update_meta_T; // @[loop.scala:187:49]
assign _update_meta_T_1 = _update_meta_WIRE[19:10]; // @[loop.scala:187:49]
assign update_meta_1_s_cnt = _update_meta_T_1; // @[loop.scala:187:49]
assign _update_meta_T_2 = _update_meta_WIRE[29:20]; // @[loop.scala:187:49]
assign update_meta_2_s_cnt = _update_meta_T_2; // @[loop.scala:187:49]
assign _update_meta_T_3 = _update_meta_WIRE[39:30]; // @[loop.scala:187:49]
assign update_meta_3_s_cnt = _update_meta_T_3; // @[loop.scala:187:49]
wire _columns_0_io_f3_req_fire_T = s3_mask[0]; // @[predictor.scala:175:24]
wire _columns_0_io_f3_req_fire_T_1 = s3_valid & _columns_0_io_f3_req_fire_T; // @[predictor.scala:170:25]
wire _columns_0_io_f3_req_fire_T_2 = _columns_0_io_f3_req_fire_T_1 & io_f3_fire_0; // @[loop.scala:20:7, :192:{44,58}]
wire _columns_0_io_f3_req_fire_T_3 = io_resp_in_0_f2_0_predicted_pc_valid_0 & io_resp_in_0_f2_0_is_br_0; // @[loop.scala:20:7, :193:54]
reg columns_0_io_f3_req_fire_REG; // @[loop.scala:193:14]
wire _columns_0_io_f3_req_fire_T_4 = _columns_0_io_f3_req_fire_T_2 & columns_0_io_f3_req_fire_REG; // @[loop.scala:192:{58,72}, :193:14]
wire _columns_0_io_update_mispredict_T = s1_update_bits_br_mask[0]; // @[predictor.scala:184:30]
wire _columns_0_io_update_repair_T = s1_update_bits_br_mask[0]; // @[predictor.scala:184:30]
wire _columns_0_io_update_mispredict_T_1 = s1_update_valid & _columns_0_io_update_mispredict_T; // @[predictor.scala:184:30]
wire _columns_0_io_update_mispredict_T_2 = _columns_0_io_update_mispredict_T_1 & s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30]
wire _columns_0_io_update_mispredict_T_3 = _columns_0_io_update_mispredict_T_2 & s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30]
wire _columns_0_io_update_repair_T_1 = s1_update_valid & _columns_0_io_update_repair_T; // @[predictor.scala:184:30]
wire _columns_0_io_update_repair_T_2 = _columns_0_io_update_repair_T_1 & s1_update_bits_is_repair_update; // @[predictor.scala:184:30]
wire _columns_1_io_f3_req_fire_T = s3_mask[1]; // @[predictor.scala:175:24]
wire _columns_1_io_f3_req_fire_T_1 = s3_valid & _columns_1_io_f3_req_fire_T; // @[predictor.scala:170:25]
wire _columns_1_io_f3_req_fire_T_2 = _columns_1_io_f3_req_fire_T_1 & io_f3_fire_0; // @[loop.scala:20:7, :192:{44,58}]
wire _columns_1_io_f3_req_fire_T_3 = io_resp_in_0_f2_1_predicted_pc_valid_0 & io_resp_in_0_f2_1_is_br_0; // @[loop.scala:20:7, :193:54]
reg columns_1_io_f3_req_fire_REG; // @[loop.scala:193:14]
wire _columns_1_io_f3_req_fire_T_4 = _columns_1_io_f3_req_fire_T_2 & columns_1_io_f3_req_fire_REG; // @[loop.scala:192:{58,72}, :193:14]
wire _columns_1_io_update_mispredict_T = s1_update_bits_br_mask[1]; // @[predictor.scala:184:30]
wire _columns_1_io_update_repair_T = s1_update_bits_br_mask[1]; // @[predictor.scala:184:30]
wire _columns_1_io_update_mispredict_T_1 = s1_update_valid & _columns_1_io_update_mispredict_T; // @[predictor.scala:184:30]
wire _columns_1_io_update_mispredict_T_2 = _columns_1_io_update_mispredict_T_1 & s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30]
wire _columns_1_io_update_mispredict_T_3 = _columns_1_io_update_mispredict_T_2 & s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30]
wire _columns_1_io_update_repair_T_1 = s1_update_valid & _columns_1_io_update_repair_T; // @[predictor.scala:184:30]
wire _columns_1_io_update_repair_T_2 = _columns_1_io_update_repair_T_1 & s1_update_bits_is_repair_update; // @[predictor.scala:184:30]
wire _columns_2_io_f3_req_fire_T = s3_mask[2]; // @[predictor.scala:175:24]
wire _columns_2_io_f3_req_fire_T_1 = s3_valid & _columns_2_io_f3_req_fire_T; // @[predictor.scala:170:25]
wire _columns_2_io_f3_req_fire_T_2 = _columns_2_io_f3_req_fire_T_1 & io_f3_fire_0; // @[loop.scala:20:7, :192:{44,58}]
wire _columns_2_io_f3_req_fire_T_3 = io_resp_in_0_f2_2_predicted_pc_valid_0 & io_resp_in_0_f2_2_is_br_0; // @[loop.scala:20:7, :193:54]
reg columns_2_io_f3_req_fire_REG; // @[loop.scala:193:14]
wire _columns_2_io_f3_req_fire_T_4 = _columns_2_io_f3_req_fire_T_2 & columns_2_io_f3_req_fire_REG; // @[loop.scala:192:{58,72}, :193:14]
wire _columns_2_io_update_mispredict_T = s1_update_bits_br_mask[2]; // @[predictor.scala:184:30]
wire _columns_2_io_update_repair_T = s1_update_bits_br_mask[2]; // @[predictor.scala:184:30]
wire _columns_2_io_update_mispredict_T_1 = s1_update_valid & _columns_2_io_update_mispredict_T; // @[predictor.scala:184:30]
wire _columns_2_io_update_mispredict_T_2 = _columns_2_io_update_mispredict_T_1 & s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30]
wire _columns_2_io_update_mispredict_T_3 = _columns_2_io_update_mispredict_T_2 & s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30]
wire _columns_2_io_update_repair_T_1 = s1_update_valid & _columns_2_io_update_repair_T; // @[predictor.scala:184:30]
wire _columns_2_io_update_repair_T_2 = _columns_2_io_update_repair_T_1 & s1_update_bits_is_repair_update; // @[predictor.scala:184:30]
wire _columns_3_io_f3_req_fire_T = s3_mask[3]; // @[predictor.scala:175:24]
wire _columns_3_io_f3_req_fire_T_1 = s3_valid & _columns_3_io_f3_req_fire_T; // @[predictor.scala:170:25]
wire _columns_3_io_f3_req_fire_T_2 = _columns_3_io_f3_req_fire_T_1 & io_f3_fire_0; // @[loop.scala:20:7, :192:{44,58}]
wire _columns_3_io_f3_req_fire_T_3 = io_resp_in_0_f2_3_predicted_pc_valid_0 & io_resp_in_0_f2_3_is_br_0; // @[loop.scala:20:7, :193:54]
reg columns_3_io_f3_req_fire_REG; // @[loop.scala:193:14]
wire _columns_3_io_f3_req_fire_T_4 = _columns_3_io_f3_req_fire_T_2 & columns_3_io_f3_req_fire_REG; // @[loop.scala:192:{58,72}, :193:14]
wire _columns_3_io_update_mispredict_T = s1_update_bits_br_mask[3]; // @[predictor.scala:184:30]
wire _columns_3_io_update_repair_T = s1_update_bits_br_mask[3]; // @[predictor.scala:184:30]
wire _columns_3_io_update_mispredict_T_1 = s1_update_valid & _columns_3_io_update_mispredict_T; // @[predictor.scala:184:30]
wire _columns_3_io_update_mispredict_T_2 = _columns_3_io_update_mispredict_T_1 & s1_update_bits_is_mispredict_update; // @[predictor.scala:184:30]
wire _columns_3_io_update_mispredict_T_3 = _columns_3_io_update_mispredict_T_2 & s1_update_bits_cfi_mispredicted; // @[predictor.scala:184:30]
wire _columns_3_io_update_repair_T_1 = s1_update_valid & _columns_3_io_update_repair_T; // @[predictor.scala:184:30]
wire _columns_3_io_update_repair_T_2 = _columns_3_io_update_repair_T_1 & s1_update_bits_is_repair_update; // @[predictor.scala:184:30]
wire [39:0] _io_f3_meta_T = {io_f3_meta_hi, io_f3_meta_lo}; // @[loop.scala:212:25]
assign io_f3_meta_0 = {80'h0, _io_f3_meta_T}; // @[loop.scala:20:7, :212:{14,25}]
always @(posedge clock) begin // @[loop.scala:20:7]
s1_idx <= s0_idx; // @[frontend.scala:162:35]
s2_idx <= s1_idx; // @[predictor.scala:163:29, :164:29]
s3_idx <= s2_idx; // @[predictor.scala:164:29, :165:29]
s1_valid <= io_f0_valid_0; // @[predictor.scala:168:25]
s2_valid <= s1_valid; // @[predictor.scala:168:25, :169:25]
s3_valid <= s2_valid; // @[predictor.scala:169:25, :170:25]
s1_mask <= io_f0_mask_0; // @[predictor.scala:173:24]
s2_mask <= s1_mask; // @[predictor.scala:173:24, :174:24]
s3_mask <= s2_mask; // @[predictor.scala:174:24, :175:24]
s1_pc <= io_f0_pc_0; // @[predictor.scala:178:22]
s1_update_valid <= io_update_valid_0; // @[predictor.scala:184:30]
s1_update_bits_is_mispredict_update <= io_update_bits_is_mispredict_update_0; // @[predictor.scala:184:30]
s1_update_bits_is_repair_update <= io_update_bits_is_repair_update_0; // @[predictor.scala:184:30]
s1_update_bits_btb_mispredicts <= io_update_bits_btb_mispredicts_0; // @[predictor.scala:184:30]
s1_update_bits_pc <= io_update_bits_pc_0; // @[predictor.scala:184:30]
s1_update_bits_br_mask <= io_update_bits_br_mask_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_idx_valid <= io_update_bits_cfi_idx_valid_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_idx_bits <= io_update_bits_cfi_idx_bits_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_taken <= io_update_bits_cfi_taken_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_mispredicted <= io_update_bits_cfi_mispredicted_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_is_br <= io_update_bits_cfi_is_br_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_is_jal <= io_update_bits_cfi_is_jal_0; // @[predictor.scala:184:30]
s1_update_bits_cfi_is_jalr <= io_update_bits_cfi_is_jalr_0; // @[predictor.scala:184:30]
s1_update_bits_ghist <= io_update_bits_ghist_0; // @[predictor.scala:184:30]
s1_update_bits_lhist <= io_update_bits_lhist_0; // @[predictor.scala:184:30]
s1_update_bits_target <= io_update_bits_target_0; // @[predictor.scala:184:30]
s1_update_bits_meta <= io_update_bits_meta_0; // @[predictor.scala:184:30]
s1_update_idx <= s0_update_idx; // @[frontend.scala:162:35]
s1_update_valid_0 <= io_update_valid_0; // @[predictor.scala:186:32]
columns_0_io_f3_req_fire_REG <= _columns_0_io_f3_req_fire_T_3; // @[loop.scala:193:{14,54}]
columns_1_io_f3_req_fire_REG <= _columns_1_io_f3_req_fire_T_3; // @[loop.scala:193:{14,54}]
columns_2_io_f3_req_fire_REG <= _columns_2_io_f3_req_fire_T_3; // @[loop.scala:193:{14,54}]
columns_3_io_f3_req_fire_REG <= _columns_3_io_f3_req_fire_T_3; // @[loop.scala:193:{14,54}]
always @(posedge)
LoopBranchPredictorColumn_8 columns_0 ( // @[loop.scala:182:45]
.clock (clock),
.reset (reset),
.io_f2_req_valid (s2_valid), // @[predictor.scala:169:25]
.io_f2_req_idx (s2_idx), // @[predictor.scala:164:29]
.io_f3_req_fire (_columns_0_io_f3_req_fire_T_4), // @[loop.scala:192:72]
.io_f3_pred_in (io_resp_in_0_f3_0_taken_0), // @[loop.scala:20:7]
.io_f3_pred (io_resp_f3_0_taken_0),
.io_f3_meta_s_cnt (f3_meta_0_s_cnt),
.io_update_mispredict (_columns_0_io_update_mispredict_T_3), // @[loop.scala:200:82]
.io_update_repair (_columns_0_io_update_repair_T_2), // @[loop.scala:203:72]
.io_update_idx (s1_update_idx), // @[predictor.scala:185:30]
.io_update_resolve_dir (s1_update_bits_cfi_taken), // @[predictor.scala:184:30]
.io_update_meta_s_cnt (update_meta_0_s_cnt) // @[loop.scala:187:49]
); // @[loop.scala:182:45]
LoopBranchPredictorColumn_9 columns_1 ( // @[loop.scala:182:45]
.clock (clock),
.reset (reset),
.io_f2_req_valid (s2_valid), // @[predictor.scala:169:25]
.io_f2_req_idx (s2_idx), // @[predictor.scala:164:29]
.io_f3_req_fire (_columns_1_io_f3_req_fire_T_4), // @[loop.scala:192:72]
.io_f3_pred_in (io_resp_in_0_f3_1_taken_0), // @[loop.scala:20:7]
.io_f3_pred (io_resp_f3_1_taken_0),
.io_f3_meta_s_cnt (f3_meta_1_s_cnt),
.io_update_mispredict (_columns_1_io_update_mispredict_T_3), // @[loop.scala:200:82]
.io_update_repair (_columns_1_io_update_repair_T_2), // @[loop.scala:203:72]
.io_update_idx (s1_update_idx), // @[predictor.scala:185:30]
.io_update_resolve_dir (s1_update_bits_cfi_taken), // @[predictor.scala:184:30]
.io_update_meta_s_cnt (update_meta_1_s_cnt) // @[loop.scala:187:49]
); // @[loop.scala:182:45]
LoopBranchPredictorColumn_10 columns_2 ( // @[loop.scala:182:45]
.clock (clock),
.reset (reset),
.io_f2_req_valid (s2_valid), // @[predictor.scala:169:25]
.io_f2_req_idx (s2_idx), // @[predictor.scala:164:29]
.io_f3_req_fire (_columns_2_io_f3_req_fire_T_4), // @[loop.scala:192:72]
.io_f3_pred_in (io_resp_in_0_f3_2_taken_0), // @[loop.scala:20:7]
.io_f3_pred (io_resp_f3_2_taken_0),
.io_f3_meta_s_cnt (f3_meta_2_s_cnt),
.io_update_mispredict (_columns_2_io_update_mispredict_T_3), // @[loop.scala:200:82]
.io_update_repair (_columns_2_io_update_repair_T_2), // @[loop.scala:203:72]
.io_update_idx (s1_update_idx), // @[predictor.scala:185:30]
.io_update_resolve_dir (s1_update_bits_cfi_taken), // @[predictor.scala:184:30]
.io_update_meta_s_cnt (update_meta_2_s_cnt) // @[loop.scala:187:49]
); // @[loop.scala:182:45]
LoopBranchPredictorColumn_11 columns_3 ( // @[loop.scala:182:45]
.clock (clock),
.reset (reset),
.io_f2_req_valid (s2_valid), // @[predictor.scala:169:25]
.io_f2_req_idx (s2_idx), // @[predictor.scala:164:29]
.io_f3_req_fire (_columns_3_io_f3_req_fire_T_4), // @[loop.scala:192:72]
.io_f3_pred_in (io_resp_in_0_f3_3_taken_0), // @[loop.scala:20:7]
.io_f3_pred (io_resp_f3_3_taken_0),
.io_f3_meta_s_cnt (f3_meta_3_s_cnt),
.io_update_mispredict (_columns_3_io_update_mispredict_T_3), // @[loop.scala:200:82]
.io_update_repair (_columns_3_io_update_repair_T_2), // @[loop.scala:203:72]
.io_update_idx (s1_update_idx), // @[predictor.scala:185:30]
.io_update_resolve_dir (s1_update_bits_cfi_taken), // @[predictor.scala:184:30]
.io_update_meta_s_cnt (update_meta_3_s_cnt) // @[loop.scala:187:49]
); // @[loop.scala:182:45]
assign io_resp_f1_0_taken = io_resp_f1_0_taken_0; // @[loop.scala:20:7]
assign io_resp_f1_0_is_br = io_resp_f1_0_is_br_0; // @[loop.scala:20:7]
assign io_resp_f1_0_is_jal = io_resp_f1_0_is_jal_0; // @[loop.scala:20:7]
assign io_resp_f1_0_predicted_pc_valid = io_resp_f1_0_predicted_pc_valid_0; // @[loop.scala:20:7]
assign io_resp_f1_0_predicted_pc_bits = io_resp_f1_0_predicted_pc_bits_0; // @[loop.scala:20:7]
assign io_resp_f1_1_taken = io_resp_f1_1_taken_0; // @[loop.scala:20:7]
assign io_resp_f1_1_is_br = io_resp_f1_1_is_br_0; // @[loop.scala:20:7]
assign io_resp_f1_1_is_jal = io_resp_f1_1_is_jal_0; // @[loop.scala:20:7]
assign io_resp_f1_1_predicted_pc_valid = io_resp_f1_1_predicted_pc_valid_0; // @[loop.scala:20:7]
assign io_resp_f1_1_predicted_pc_bits = io_resp_f1_1_predicted_pc_bits_0; // @[loop.scala:20:7]
assign io_resp_f1_2_taken = io_resp_f1_2_taken_0; // @[loop.scala:20:7]
assign io_resp_f1_2_is_br = io_resp_f1_2_is_br_0; // @[loop.scala:20:7]
assign io_resp_f1_2_is_jal = io_resp_f1_2_is_jal_0; // @[loop.scala:20:7]
assign io_resp_f1_2_predicted_pc_valid = io_resp_f1_2_predicted_pc_valid_0; // @[loop.scala:20:7]
assign io_resp_f1_2_predicted_pc_bits = io_resp_f1_2_predicted_pc_bits_0; // @[loop.scala:20:7]
assign io_resp_f1_3_taken = io_resp_f1_3_taken_0; // @[loop.scala:20:7]
assign io_resp_f1_3_is_br = io_resp_f1_3_is_br_0; // @[loop.scala:20:7]
assign io_resp_f1_3_is_jal = io_resp_f1_3_is_jal_0; // @[loop.scala:20:7]
assign io_resp_f1_3_predicted_pc_valid = io_resp_f1_3_predicted_pc_valid_0; // @[loop.scala:20:7]
assign io_resp_f1_3_predicted_pc_bits = io_resp_f1_3_predicted_pc_bits_0; // @[loop.scala:20:7]
assign io_resp_f2_0_taken = io_resp_f2_0_taken_0; // @[loop.scala:20:7]
assign io_resp_f2_0_is_br = io_resp_f2_0_is_br_0; // @[loop.scala:20:7]
assign io_resp_f2_0_is_jal = io_resp_f2_0_is_jal_0; // @[loop.scala:20:7]
assign io_resp_f2_0_predicted_pc_valid = io_resp_f2_0_predicted_pc_valid_0; // @[loop.scala:20:7]
assign io_resp_f2_0_predicted_pc_bits = io_resp_f2_0_predicted_pc_bits_0; // @[loop.scala:20:7]
assign io_resp_f2_1_taken = io_resp_f2_1_taken_0; // @[loop.scala:20:7]
assign io_resp_f2_1_is_br = io_resp_f2_1_is_br_0; // @[loop.scala:20:7]
assign io_resp_f2_1_is_jal = io_resp_f2_1_is_jal_0; // @[loop.scala:20:7]
assign io_resp_f2_1_predicted_pc_valid = io_resp_f2_1_predicted_pc_valid_0; // @[loop.scala:20:7]
assign io_resp_f2_1_predicted_pc_bits = io_resp_f2_1_predicted_pc_bits_0; // @[loop.scala:20:7]
assign io_resp_f2_2_taken = io_resp_f2_2_taken_0; // @[loop.scala:20:7]
assign io_resp_f2_2_is_br = io_resp_f2_2_is_br_0; // @[loop.scala:20:7]
assign io_resp_f2_2_is_jal = io_resp_f2_2_is_jal_0; // @[loop.scala:20:7]
assign io_resp_f2_2_predicted_pc_valid = io_resp_f2_2_predicted_pc_valid_0; // @[loop.scala:20:7]
assign io_resp_f2_2_predicted_pc_bits = io_resp_f2_2_predicted_pc_bits_0; // @[loop.scala:20:7]
assign io_resp_f2_3_taken = io_resp_f2_3_taken_0; // @[loop.scala:20:7]
assign io_resp_f2_3_is_br = io_resp_f2_3_is_br_0; // @[loop.scala:20:7]
assign io_resp_f2_3_is_jal = io_resp_f2_3_is_jal_0; // @[loop.scala:20:7]
assign io_resp_f2_3_predicted_pc_valid = io_resp_f2_3_predicted_pc_valid_0; // @[loop.scala:20:7]
assign io_resp_f2_3_predicted_pc_bits = io_resp_f2_3_predicted_pc_bits_0; // @[loop.scala:20:7]
assign io_resp_f3_0_taken = io_resp_f3_0_taken_0; // @[loop.scala:20:7]
assign io_resp_f3_0_is_br = io_resp_f3_0_is_br_0; // @[loop.scala:20:7]
assign io_resp_f3_0_is_jal = io_resp_f3_0_is_jal_0; // @[loop.scala:20:7]
assign io_resp_f3_0_predicted_pc_valid = io_resp_f3_0_predicted_pc_valid_0; // @[loop.scala:20:7]
assign io_resp_f3_0_predicted_pc_bits = io_resp_f3_0_predicted_pc_bits_0; // @[loop.scala:20:7]
assign io_resp_f3_1_taken = io_resp_f3_1_taken_0; // @[loop.scala:20:7]
assign io_resp_f3_1_is_br = io_resp_f3_1_is_br_0; // @[loop.scala:20:7]
assign io_resp_f3_1_is_jal = io_resp_f3_1_is_jal_0; // @[loop.scala:20:7]
assign io_resp_f3_1_predicted_pc_valid = io_resp_f3_1_predicted_pc_valid_0; // @[loop.scala:20:7]
assign io_resp_f3_1_predicted_pc_bits = io_resp_f3_1_predicted_pc_bits_0; // @[loop.scala:20:7]
assign io_resp_f3_2_taken = io_resp_f3_2_taken_0; // @[loop.scala:20:7]
assign io_resp_f3_2_is_br = io_resp_f3_2_is_br_0; // @[loop.scala:20:7]
assign io_resp_f3_2_is_jal = io_resp_f3_2_is_jal_0; // @[loop.scala:20:7]
assign io_resp_f3_2_predicted_pc_valid = io_resp_f3_2_predicted_pc_valid_0; // @[loop.scala:20:7]
assign io_resp_f3_2_predicted_pc_bits = io_resp_f3_2_predicted_pc_bits_0; // @[loop.scala:20:7]
assign io_resp_f3_3_taken = io_resp_f3_3_taken_0; // @[loop.scala:20:7]
assign io_resp_f3_3_is_br = io_resp_f3_3_is_br_0; // @[loop.scala:20:7]
assign io_resp_f3_3_is_jal = io_resp_f3_3_is_jal_0; // @[loop.scala:20:7]
assign io_resp_f3_3_predicted_pc_valid = io_resp_f3_3_predicted_pc_valid_0; // @[loop.scala:20:7]
assign io_resp_f3_3_predicted_pc_bits = io_resp_f3_3_predicted_pc_bits_0; // @[loop.scala:20:7]
assign io_f3_meta = io_f3_meta_0; // @[loop.scala:20:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_90 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2))
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_lo = cat(mask_acc_1, mask_acc)
node mask_hi = cat(mask_acc_3, mask_acc_2)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_17 = and(UInt<1>(0h0), _T_16)
node _T_18 = or(UInt<1>(0h0), _T_17)
node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_20 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_21 = cvt(_T_20)
node _T_22 = and(_T_21, asSInt(UInt<7>(0h40)))
node _T_23 = asSInt(_T_22)
node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0)))
node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_26 = cvt(_T_25)
node _T_27 = and(_T_26, asSInt(UInt<5>(0h14)))
node _T_28 = asSInt(_T_27)
node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0)))
node _T_30 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_31 = cvt(_T_30)
node _T_32 = and(_T_31, asSInt(UInt<4>(0h8)))
node _T_33 = asSInt(_T_32)
node _T_34 = eq(_T_33, asSInt(UInt<1>(0h0)))
node _T_35 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_36 = cvt(_T_35)
node _T_37 = and(_T_36, asSInt(UInt<6>(0h20)))
node _T_38 = asSInt(_T_37)
node _T_39 = eq(_T_38, asSInt(UInt<1>(0h0)))
node _T_40 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_41 = cvt(_T_40)
node _T_42 = and(_T_41, asSInt(UInt<8>(0h80)))
node _T_43 = asSInt(_T_42)
node _T_44 = eq(_T_43, asSInt(UInt<1>(0h0)))
node _T_45 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_46 = cvt(_T_45)
node _T_47 = and(_T_46, asSInt(UInt<9>(0h100)))
node _T_48 = asSInt(_T_47)
node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0)))
node _T_50 = or(_T_24, _T_29)
node _T_51 = or(_T_50, _T_34)
node _T_52 = or(_T_51, _T_39)
node _T_53 = or(_T_52, _T_44)
node _T_54 = or(_T_53, _T_49)
node _T_55 = and(_T_19, _T_54)
node _T_56 = or(UInt<1>(0h0), _T_55)
node _T_57 = and(_T_18, _T_56)
node _T_58 = asUInt(reset)
node _T_59 = eq(_T_58, UInt<1>(0h0))
when _T_59 :
node _T_60 = eq(_T_57, UInt<1>(0h0))
when _T_60 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_57, UInt<1>(0h1), "") : assert_2
node _T_61 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_62 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_63 = and(_T_61, _T_62)
node _T_64 = or(UInt<1>(0h0), _T_63)
node _T_65 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_66 = cvt(_T_65)
node _T_67 = and(_T_66, asSInt(UInt<7>(0h40)))
node _T_68 = asSInt(_T_67)
node _T_69 = eq(_T_68, asSInt(UInt<1>(0h0)))
node _T_70 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_71 = cvt(_T_70)
node _T_72 = and(_T_71, asSInt(UInt<5>(0h14)))
node _T_73 = asSInt(_T_72)
node _T_74 = eq(_T_73, asSInt(UInt<1>(0h0)))
node _T_75 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_76 = cvt(_T_75)
node _T_77 = and(_T_76, asSInt(UInt<4>(0h8)))
node _T_78 = asSInt(_T_77)
node _T_79 = eq(_T_78, asSInt(UInt<1>(0h0)))
node _T_80 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_81 = cvt(_T_80)
node _T_82 = and(_T_81, asSInt(UInt<6>(0h20)))
node _T_83 = asSInt(_T_82)
node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_86 = cvt(_T_85)
node _T_87 = and(_T_86, asSInt(UInt<8>(0h80)))
node _T_88 = asSInt(_T_87)
node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0)))
node _T_90 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_91 = cvt(_T_90)
node _T_92 = and(_T_91, asSInt(UInt<9>(0h100)))
node _T_93 = asSInt(_T_92)
node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0)))
node _T_95 = or(_T_69, _T_74)
node _T_96 = or(_T_95, _T_79)
node _T_97 = or(_T_96, _T_84)
node _T_98 = or(_T_97, _T_89)
node _T_99 = or(_T_98, _T_94)
node _T_100 = and(_T_64, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(UInt<1>(0h0), _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_102, UInt<1>(0h1), "") : assert_3
node _T_106 = asUInt(reset)
node _T_107 = eq(_T_106, UInt<1>(0h0))
when _T_107 :
node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_110 = asUInt(reset)
node _T_111 = eq(_T_110, UInt<1>(0h0))
when _T_111 :
node _T_112 = eq(_T_109, UInt<1>(0h0))
when _T_112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_109, UInt<1>(0h1), "") : assert_5
node _T_113 = asUInt(reset)
node _T_114 = eq(_T_113, UInt<1>(0h0))
when _T_114 :
node _T_115 = eq(is_aligned, UInt<1>(0h0))
when _T_115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_117 = asUInt(reset)
node _T_118 = eq(_T_117, UInt<1>(0h0))
when _T_118 :
node _T_119 = eq(_T_116, UInt<1>(0h0))
when _T_119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_116, UInt<1>(0h1), "") : assert_7
node _T_120 = not(io.in.a.bits.mask)
node _T_121 = eq(_T_120, UInt<1>(0h0))
node _T_122 = asUInt(reset)
node _T_123 = eq(_T_122, UInt<1>(0h0))
when _T_123 :
node _T_124 = eq(_T_121, UInt<1>(0h0))
when _T_124 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_121, UInt<1>(0h1), "") : assert_8
node _T_125 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_126 = asUInt(reset)
node _T_127 = eq(_T_126, UInt<1>(0h0))
when _T_127 :
node _T_128 = eq(_T_125, UInt<1>(0h0))
when _T_128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_125, UInt<1>(0h1), "") : assert_9
node _T_129 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_129 :
node _T_130 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_131 = and(UInt<1>(0h0), _T_130)
node _T_132 = or(UInt<1>(0h0), _T_131)
node _T_133 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_134 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_135 = cvt(_T_134)
node _T_136 = and(_T_135, asSInt(UInt<7>(0h40)))
node _T_137 = asSInt(_T_136)
node _T_138 = eq(_T_137, asSInt(UInt<1>(0h0)))
node _T_139 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_140 = cvt(_T_139)
node _T_141 = and(_T_140, asSInt(UInt<5>(0h14)))
node _T_142 = asSInt(_T_141)
node _T_143 = eq(_T_142, asSInt(UInt<1>(0h0)))
node _T_144 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_145 = cvt(_T_144)
node _T_146 = and(_T_145, asSInt(UInt<4>(0h8)))
node _T_147 = asSInt(_T_146)
node _T_148 = eq(_T_147, asSInt(UInt<1>(0h0)))
node _T_149 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_150 = cvt(_T_149)
node _T_151 = and(_T_150, asSInt(UInt<6>(0h20)))
node _T_152 = asSInt(_T_151)
node _T_153 = eq(_T_152, asSInt(UInt<1>(0h0)))
node _T_154 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_155 = cvt(_T_154)
node _T_156 = and(_T_155, asSInt(UInt<8>(0h80)))
node _T_157 = asSInt(_T_156)
node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0)))
node _T_159 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_160 = cvt(_T_159)
node _T_161 = and(_T_160, asSInt(UInt<9>(0h100)))
node _T_162 = asSInt(_T_161)
node _T_163 = eq(_T_162, asSInt(UInt<1>(0h0)))
node _T_164 = or(_T_138, _T_143)
node _T_165 = or(_T_164, _T_148)
node _T_166 = or(_T_165, _T_153)
node _T_167 = or(_T_166, _T_158)
node _T_168 = or(_T_167, _T_163)
node _T_169 = and(_T_133, _T_168)
node _T_170 = or(UInt<1>(0h0), _T_169)
node _T_171 = and(_T_132, _T_170)
node _T_172 = asUInt(reset)
node _T_173 = eq(_T_172, UInt<1>(0h0))
when _T_173 :
node _T_174 = eq(_T_171, UInt<1>(0h0))
when _T_174 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_171, UInt<1>(0h1), "") : assert_10
node _T_175 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_176 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_177 = and(_T_175, _T_176)
node _T_178 = or(UInt<1>(0h0), _T_177)
node _T_179 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_180 = cvt(_T_179)
node _T_181 = and(_T_180, asSInt(UInt<7>(0h40)))
node _T_182 = asSInt(_T_181)
node _T_183 = eq(_T_182, asSInt(UInt<1>(0h0)))
node _T_184 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_185 = cvt(_T_184)
node _T_186 = and(_T_185, asSInt(UInt<5>(0h14)))
node _T_187 = asSInt(_T_186)
node _T_188 = eq(_T_187, asSInt(UInt<1>(0h0)))
node _T_189 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_190 = cvt(_T_189)
node _T_191 = and(_T_190, asSInt(UInt<4>(0h8)))
node _T_192 = asSInt(_T_191)
node _T_193 = eq(_T_192, asSInt(UInt<1>(0h0)))
node _T_194 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_195 = cvt(_T_194)
node _T_196 = and(_T_195, asSInt(UInt<6>(0h20)))
node _T_197 = asSInt(_T_196)
node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0)))
node _T_199 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_200 = cvt(_T_199)
node _T_201 = and(_T_200, asSInt(UInt<8>(0h80)))
node _T_202 = asSInt(_T_201)
node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0)))
node _T_204 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_205 = cvt(_T_204)
node _T_206 = and(_T_205, asSInt(UInt<9>(0h100)))
node _T_207 = asSInt(_T_206)
node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0)))
node _T_209 = or(_T_183, _T_188)
node _T_210 = or(_T_209, _T_193)
node _T_211 = or(_T_210, _T_198)
node _T_212 = or(_T_211, _T_203)
node _T_213 = or(_T_212, _T_208)
node _T_214 = and(_T_178, _T_213)
node _T_215 = or(UInt<1>(0h0), _T_214)
node _T_216 = and(UInt<1>(0h0), _T_215)
node _T_217 = asUInt(reset)
node _T_218 = eq(_T_217, UInt<1>(0h0))
when _T_218 :
node _T_219 = eq(_T_216, UInt<1>(0h0))
when _T_219 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_216, UInt<1>(0h1), "") : assert_11
node _T_220 = asUInt(reset)
node _T_221 = eq(_T_220, UInt<1>(0h0))
when _T_221 :
node _T_222 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_222 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_223 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_224 = asUInt(reset)
node _T_225 = eq(_T_224, UInt<1>(0h0))
when _T_225 :
node _T_226 = eq(_T_223, UInt<1>(0h0))
when _T_226 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_223, UInt<1>(0h1), "") : assert_13
node _T_227 = asUInt(reset)
node _T_228 = eq(_T_227, UInt<1>(0h0))
when _T_228 :
node _T_229 = eq(is_aligned, UInt<1>(0h0))
when _T_229 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_230 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_231 = asUInt(reset)
node _T_232 = eq(_T_231, UInt<1>(0h0))
when _T_232 :
node _T_233 = eq(_T_230, UInt<1>(0h0))
when _T_233 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_230, UInt<1>(0h1), "") : assert_15
node _T_234 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_235 = asUInt(reset)
node _T_236 = eq(_T_235, UInt<1>(0h0))
when _T_236 :
node _T_237 = eq(_T_234, UInt<1>(0h0))
when _T_237 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_234, UInt<1>(0h1), "") : assert_16
node _T_238 = not(io.in.a.bits.mask)
node _T_239 = eq(_T_238, UInt<1>(0h0))
node _T_240 = asUInt(reset)
node _T_241 = eq(_T_240, UInt<1>(0h0))
when _T_241 :
node _T_242 = eq(_T_239, UInt<1>(0h0))
when _T_242 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_239, UInt<1>(0h1), "") : assert_17
node _T_243 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_244 = asUInt(reset)
node _T_245 = eq(_T_244, UInt<1>(0h0))
when _T_245 :
node _T_246 = eq(_T_243, UInt<1>(0h0))
when _T_246 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_243, UInt<1>(0h1), "") : assert_18
node _T_247 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_247 :
node _T_248 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_249 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_250 = and(_T_248, _T_249)
node _T_251 = or(UInt<1>(0h0), _T_250)
node _T_252 = asUInt(reset)
node _T_253 = eq(_T_252, UInt<1>(0h0))
when _T_253 :
node _T_254 = eq(_T_251, UInt<1>(0h0))
when _T_254 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_251, UInt<1>(0h1), "") : assert_19
node _T_255 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_256 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_257 = and(_T_255, _T_256)
node _T_258 = or(UInt<1>(0h0), _T_257)
node _T_259 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_260 = cvt(_T_259)
node _T_261 = and(_T_260, asSInt(UInt<7>(0h40)))
node _T_262 = asSInt(_T_261)
node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0)))
node _T_264 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_265 = cvt(_T_264)
node _T_266 = and(_T_265, asSInt(UInt<5>(0h14)))
node _T_267 = asSInt(_T_266)
node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0)))
node _T_269 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_270 = cvt(_T_269)
node _T_271 = and(_T_270, asSInt(UInt<4>(0h8)))
node _T_272 = asSInt(_T_271)
node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0)))
node _T_274 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_275 = cvt(_T_274)
node _T_276 = and(_T_275, asSInt(UInt<6>(0h20)))
node _T_277 = asSInt(_T_276)
node _T_278 = eq(_T_277, asSInt(UInt<1>(0h0)))
node _T_279 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_280 = cvt(_T_279)
node _T_281 = and(_T_280, asSInt(UInt<8>(0h80)))
node _T_282 = asSInt(_T_281)
node _T_283 = eq(_T_282, asSInt(UInt<1>(0h0)))
node _T_284 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_285 = cvt(_T_284)
node _T_286 = and(_T_285, asSInt(UInt<9>(0h100)))
node _T_287 = asSInt(_T_286)
node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0)))
node _T_289 = or(_T_263, _T_268)
node _T_290 = or(_T_289, _T_273)
node _T_291 = or(_T_290, _T_278)
node _T_292 = or(_T_291, _T_283)
node _T_293 = or(_T_292, _T_288)
node _T_294 = and(_T_258, _T_293)
node _T_295 = or(UInt<1>(0h0), _T_294)
node _T_296 = asUInt(reset)
node _T_297 = eq(_T_296, UInt<1>(0h0))
when _T_297 :
node _T_298 = eq(_T_295, UInt<1>(0h0))
when _T_298 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_295, UInt<1>(0h1), "") : assert_20
node _T_299 = asUInt(reset)
node _T_300 = eq(_T_299, UInt<1>(0h0))
when _T_300 :
node _T_301 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_302 = asUInt(reset)
node _T_303 = eq(_T_302, UInt<1>(0h0))
when _T_303 :
node _T_304 = eq(is_aligned, UInt<1>(0h0))
when _T_304 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_305 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_306 = asUInt(reset)
node _T_307 = eq(_T_306, UInt<1>(0h0))
when _T_307 :
node _T_308 = eq(_T_305, UInt<1>(0h0))
when _T_308 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_305, UInt<1>(0h1), "") : assert_23
node _T_309 = eq(io.in.a.bits.mask, mask)
node _T_310 = asUInt(reset)
node _T_311 = eq(_T_310, UInt<1>(0h0))
when _T_311 :
node _T_312 = eq(_T_309, UInt<1>(0h0))
when _T_312 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_309, UInt<1>(0h1), "") : assert_24
node _T_313 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_314 = asUInt(reset)
node _T_315 = eq(_T_314, UInt<1>(0h0))
when _T_315 :
node _T_316 = eq(_T_313, UInt<1>(0h0))
when _T_316 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_313, UInt<1>(0h1), "") : assert_25
node _T_317 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_317 :
node _T_318 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_319 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_320 = and(_T_318, _T_319)
node _T_321 = or(UInt<1>(0h0), _T_320)
node _T_322 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_323 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_324 = and(_T_322, _T_323)
node _T_325 = or(UInt<1>(0h0), _T_324)
node _T_326 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_327 = cvt(_T_326)
node _T_328 = and(_T_327, asSInt(UInt<7>(0h40)))
node _T_329 = asSInt(_T_328)
node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0)))
node _T_331 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_332 = cvt(_T_331)
node _T_333 = and(_T_332, asSInt(UInt<5>(0h14)))
node _T_334 = asSInt(_T_333)
node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0)))
node _T_336 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_337 = cvt(_T_336)
node _T_338 = and(_T_337, asSInt(UInt<4>(0h8)))
node _T_339 = asSInt(_T_338)
node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0)))
node _T_341 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_342 = cvt(_T_341)
node _T_343 = and(_T_342, asSInt(UInt<6>(0h20)))
node _T_344 = asSInt(_T_343)
node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0)))
node _T_346 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_347 = cvt(_T_346)
node _T_348 = and(_T_347, asSInt(UInt<8>(0h80)))
node _T_349 = asSInt(_T_348)
node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0)))
node _T_351 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_352 = cvt(_T_351)
node _T_353 = and(_T_352, asSInt(UInt<9>(0h100)))
node _T_354 = asSInt(_T_353)
node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0)))
node _T_356 = or(_T_330, _T_335)
node _T_357 = or(_T_356, _T_340)
node _T_358 = or(_T_357, _T_345)
node _T_359 = or(_T_358, _T_350)
node _T_360 = or(_T_359, _T_355)
node _T_361 = and(_T_325, _T_360)
node _T_362 = or(UInt<1>(0h0), _T_361)
node _T_363 = and(_T_321, _T_362)
node _T_364 = asUInt(reset)
node _T_365 = eq(_T_364, UInt<1>(0h0))
when _T_365 :
node _T_366 = eq(_T_363, UInt<1>(0h0))
when _T_366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_363, UInt<1>(0h1), "") : assert_26
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_370 = asUInt(reset)
node _T_371 = eq(_T_370, UInt<1>(0h0))
when _T_371 :
node _T_372 = eq(is_aligned, UInt<1>(0h0))
when _T_372 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_373 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_374 = asUInt(reset)
node _T_375 = eq(_T_374, UInt<1>(0h0))
when _T_375 :
node _T_376 = eq(_T_373, UInt<1>(0h0))
when _T_376 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_373, UInt<1>(0h1), "") : assert_29
node _T_377 = eq(io.in.a.bits.mask, mask)
node _T_378 = asUInt(reset)
node _T_379 = eq(_T_378, UInt<1>(0h0))
when _T_379 :
node _T_380 = eq(_T_377, UInt<1>(0h0))
when _T_380 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_377, UInt<1>(0h1), "") : assert_30
node _T_381 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_381 :
node _T_382 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_383 = and(UInt<1>(0h0), _T_382)
node _T_384 = or(UInt<1>(0h0), _T_383)
node _T_385 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_386 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_387 = and(_T_385, _T_386)
node _T_388 = or(UInt<1>(0h0), _T_387)
node _T_389 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_390 = cvt(_T_389)
node _T_391 = and(_T_390, asSInt(UInt<7>(0h40)))
node _T_392 = asSInt(_T_391)
node _T_393 = eq(_T_392, asSInt(UInt<1>(0h0)))
node _T_394 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_395 = cvt(_T_394)
node _T_396 = and(_T_395, asSInt(UInt<5>(0h14)))
node _T_397 = asSInt(_T_396)
node _T_398 = eq(_T_397, asSInt(UInt<1>(0h0)))
node _T_399 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_400 = cvt(_T_399)
node _T_401 = and(_T_400, asSInt(UInt<4>(0h8)))
node _T_402 = asSInt(_T_401)
node _T_403 = eq(_T_402, asSInt(UInt<1>(0h0)))
node _T_404 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_405 = cvt(_T_404)
node _T_406 = and(_T_405, asSInt(UInt<6>(0h20)))
node _T_407 = asSInt(_T_406)
node _T_408 = eq(_T_407, asSInt(UInt<1>(0h0)))
node _T_409 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_410 = cvt(_T_409)
node _T_411 = and(_T_410, asSInt(UInt<8>(0h80)))
node _T_412 = asSInt(_T_411)
node _T_413 = eq(_T_412, asSInt(UInt<1>(0h0)))
node _T_414 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_415 = cvt(_T_414)
node _T_416 = and(_T_415, asSInt(UInt<9>(0h100)))
node _T_417 = asSInt(_T_416)
node _T_418 = eq(_T_417, asSInt(UInt<1>(0h0)))
node _T_419 = or(_T_393, _T_398)
node _T_420 = or(_T_419, _T_403)
node _T_421 = or(_T_420, _T_408)
node _T_422 = or(_T_421, _T_413)
node _T_423 = or(_T_422, _T_418)
node _T_424 = and(_T_388, _T_423)
node _T_425 = or(UInt<1>(0h0), _T_424)
node _T_426 = and(_T_384, _T_425)
node _T_427 = asUInt(reset)
node _T_428 = eq(_T_427, UInt<1>(0h0))
when _T_428 :
node _T_429 = eq(_T_426, UInt<1>(0h0))
when _T_429 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_426, UInt<1>(0h1), "") : assert_31
node _T_430 = asUInt(reset)
node _T_431 = eq(_T_430, UInt<1>(0h0))
when _T_431 :
node _T_432 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_432 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_433 = asUInt(reset)
node _T_434 = eq(_T_433, UInt<1>(0h0))
when _T_434 :
node _T_435 = eq(is_aligned, UInt<1>(0h0))
when _T_435 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_436 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_437 = asUInt(reset)
node _T_438 = eq(_T_437, UInt<1>(0h0))
when _T_438 :
node _T_439 = eq(_T_436, UInt<1>(0h0))
when _T_439 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_436, UInt<1>(0h1), "") : assert_34
node _T_440 = not(mask)
node _T_441 = and(io.in.a.bits.mask, _T_440)
node _T_442 = eq(_T_441, UInt<1>(0h0))
node _T_443 = asUInt(reset)
node _T_444 = eq(_T_443, UInt<1>(0h0))
when _T_444 :
node _T_445 = eq(_T_442, UInt<1>(0h0))
when _T_445 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_442, UInt<1>(0h1), "") : assert_35
node _T_446 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_446 :
node _T_447 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_448 = and(UInt<1>(0h0), _T_447)
node _T_449 = or(UInt<1>(0h0), _T_448)
node _T_450 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_451 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_452 = cvt(_T_451)
node _T_453 = and(_T_452, asSInt(UInt<7>(0h40)))
node _T_454 = asSInt(_T_453)
node _T_455 = eq(_T_454, asSInt(UInt<1>(0h0)))
node _T_456 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_457 = cvt(_T_456)
node _T_458 = and(_T_457, asSInt(UInt<5>(0h14)))
node _T_459 = asSInt(_T_458)
node _T_460 = eq(_T_459, asSInt(UInt<1>(0h0)))
node _T_461 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_462 = cvt(_T_461)
node _T_463 = and(_T_462, asSInt(UInt<4>(0h8)))
node _T_464 = asSInt(_T_463)
node _T_465 = eq(_T_464, asSInt(UInt<1>(0h0)))
node _T_466 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_467 = cvt(_T_466)
node _T_468 = and(_T_467, asSInt(UInt<6>(0h20)))
node _T_469 = asSInt(_T_468)
node _T_470 = eq(_T_469, asSInt(UInt<1>(0h0)))
node _T_471 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_472 = cvt(_T_471)
node _T_473 = and(_T_472, asSInt(UInt<8>(0h80)))
node _T_474 = asSInt(_T_473)
node _T_475 = eq(_T_474, asSInt(UInt<1>(0h0)))
node _T_476 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_477 = cvt(_T_476)
node _T_478 = and(_T_477, asSInt(UInt<9>(0h100)))
node _T_479 = asSInt(_T_478)
node _T_480 = eq(_T_479, asSInt(UInt<1>(0h0)))
node _T_481 = or(_T_455, _T_460)
node _T_482 = or(_T_481, _T_465)
node _T_483 = or(_T_482, _T_470)
node _T_484 = or(_T_483, _T_475)
node _T_485 = or(_T_484, _T_480)
node _T_486 = and(_T_450, _T_485)
node _T_487 = or(UInt<1>(0h0), _T_486)
node _T_488 = and(_T_449, _T_487)
node _T_489 = asUInt(reset)
node _T_490 = eq(_T_489, UInt<1>(0h0))
when _T_490 :
node _T_491 = eq(_T_488, UInt<1>(0h0))
when _T_491 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_488, UInt<1>(0h1), "") : assert_36
node _T_492 = asUInt(reset)
node _T_493 = eq(_T_492, UInt<1>(0h0))
when _T_493 :
node _T_494 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_494 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_495 = asUInt(reset)
node _T_496 = eq(_T_495, UInt<1>(0h0))
when _T_496 :
node _T_497 = eq(is_aligned, UInt<1>(0h0))
when _T_497 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_498 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_499 = asUInt(reset)
node _T_500 = eq(_T_499, UInt<1>(0h0))
when _T_500 :
node _T_501 = eq(_T_498, UInt<1>(0h0))
when _T_501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_498, UInt<1>(0h1), "") : assert_39
node _T_502 = eq(io.in.a.bits.mask, mask)
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_502, UInt<1>(0h1), "") : assert_40
node _T_506 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_506 :
node _T_507 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_508 = and(UInt<1>(0h0), _T_507)
node _T_509 = or(UInt<1>(0h0), _T_508)
node _T_510 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_511 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_512 = cvt(_T_511)
node _T_513 = and(_T_512, asSInt(UInt<7>(0h40)))
node _T_514 = asSInt(_T_513)
node _T_515 = eq(_T_514, asSInt(UInt<1>(0h0)))
node _T_516 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_517 = cvt(_T_516)
node _T_518 = and(_T_517, asSInt(UInt<5>(0h14)))
node _T_519 = asSInt(_T_518)
node _T_520 = eq(_T_519, asSInt(UInt<1>(0h0)))
node _T_521 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_522 = cvt(_T_521)
node _T_523 = and(_T_522, asSInt(UInt<4>(0h8)))
node _T_524 = asSInt(_T_523)
node _T_525 = eq(_T_524, asSInt(UInt<1>(0h0)))
node _T_526 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_527 = cvt(_T_526)
node _T_528 = and(_T_527, asSInt(UInt<6>(0h20)))
node _T_529 = asSInt(_T_528)
node _T_530 = eq(_T_529, asSInt(UInt<1>(0h0)))
node _T_531 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_532 = cvt(_T_531)
node _T_533 = and(_T_532, asSInt(UInt<8>(0h80)))
node _T_534 = asSInt(_T_533)
node _T_535 = eq(_T_534, asSInt(UInt<1>(0h0)))
node _T_536 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_537 = cvt(_T_536)
node _T_538 = and(_T_537, asSInt(UInt<9>(0h100)))
node _T_539 = asSInt(_T_538)
node _T_540 = eq(_T_539, asSInt(UInt<1>(0h0)))
node _T_541 = or(_T_515, _T_520)
node _T_542 = or(_T_541, _T_525)
node _T_543 = or(_T_542, _T_530)
node _T_544 = or(_T_543, _T_535)
node _T_545 = or(_T_544, _T_540)
node _T_546 = and(_T_510, _T_545)
node _T_547 = or(UInt<1>(0h0), _T_546)
node _T_548 = and(_T_509, _T_547)
node _T_549 = asUInt(reset)
node _T_550 = eq(_T_549, UInt<1>(0h0))
when _T_550 :
node _T_551 = eq(_T_548, UInt<1>(0h0))
when _T_551 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_548, UInt<1>(0h1), "") : assert_41
node _T_552 = asUInt(reset)
node _T_553 = eq(_T_552, UInt<1>(0h0))
when _T_553 :
node _T_554 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_554 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_555 = asUInt(reset)
node _T_556 = eq(_T_555, UInt<1>(0h0))
when _T_556 :
node _T_557 = eq(is_aligned, UInt<1>(0h0))
when _T_557 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_558 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_559 = asUInt(reset)
node _T_560 = eq(_T_559, UInt<1>(0h0))
when _T_560 :
node _T_561 = eq(_T_558, UInt<1>(0h0))
when _T_561 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_558, UInt<1>(0h1), "") : assert_44
node _T_562 = eq(io.in.a.bits.mask, mask)
node _T_563 = asUInt(reset)
node _T_564 = eq(_T_563, UInt<1>(0h0))
when _T_564 :
node _T_565 = eq(_T_562, UInt<1>(0h0))
when _T_565 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_562, UInt<1>(0h1), "") : assert_45
node _T_566 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_566 :
node _T_567 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_568 = and(UInt<1>(0h0), _T_567)
node _T_569 = or(UInt<1>(0h0), _T_568)
node _T_570 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_571 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_572 = cvt(_T_571)
node _T_573 = and(_T_572, asSInt(UInt<7>(0h40)))
node _T_574 = asSInt(_T_573)
node _T_575 = eq(_T_574, asSInt(UInt<1>(0h0)))
node _T_576 = xor(io.in.a.bits.address, UInt<7>(0h44))
node _T_577 = cvt(_T_576)
node _T_578 = and(_T_577, asSInt(UInt<5>(0h14)))
node _T_579 = asSInt(_T_578)
node _T_580 = eq(_T_579, asSInt(UInt<1>(0h0)))
node _T_581 = xor(io.in.a.bits.address, UInt<7>(0h58))
node _T_582 = cvt(_T_581)
node _T_583 = and(_T_582, asSInt(UInt<4>(0h8)))
node _T_584 = asSInt(_T_583)
node _T_585 = eq(_T_584, asSInt(UInt<1>(0h0)))
node _T_586 = xor(io.in.a.bits.address, UInt<7>(0h60))
node _T_587 = cvt(_T_586)
node _T_588 = and(_T_587, asSInt(UInt<6>(0h20)))
node _T_589 = asSInt(_T_588)
node _T_590 = eq(_T_589, asSInt(UInt<1>(0h0)))
node _T_591 = xor(io.in.a.bits.address, UInt<8>(0h80))
node _T_592 = cvt(_T_591)
node _T_593 = and(_T_592, asSInt(UInt<8>(0h80)))
node _T_594 = asSInt(_T_593)
node _T_595 = eq(_T_594, asSInt(UInt<1>(0h0)))
node _T_596 = xor(io.in.a.bits.address, UInt<9>(0h100))
node _T_597 = cvt(_T_596)
node _T_598 = and(_T_597, asSInt(UInt<9>(0h100)))
node _T_599 = asSInt(_T_598)
node _T_600 = eq(_T_599, asSInt(UInt<1>(0h0)))
node _T_601 = or(_T_575, _T_580)
node _T_602 = or(_T_601, _T_585)
node _T_603 = or(_T_602, _T_590)
node _T_604 = or(_T_603, _T_595)
node _T_605 = or(_T_604, _T_600)
node _T_606 = and(_T_570, _T_605)
node _T_607 = or(UInt<1>(0h0), _T_606)
node _T_608 = and(_T_569, _T_607)
node _T_609 = asUInt(reset)
node _T_610 = eq(_T_609, UInt<1>(0h0))
when _T_610 :
node _T_611 = eq(_T_608, UInt<1>(0h0))
when _T_611 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_608, UInt<1>(0h1), "") : assert_46
node _T_612 = asUInt(reset)
node _T_613 = eq(_T_612, UInt<1>(0h0))
when _T_613 :
node _T_614 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_614 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_615 = asUInt(reset)
node _T_616 = eq(_T_615, UInt<1>(0h0))
when _T_616 :
node _T_617 = eq(is_aligned, UInt<1>(0h0))
when _T_617 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_618 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_619 = asUInt(reset)
node _T_620 = eq(_T_619, UInt<1>(0h0))
when _T_620 :
node _T_621 = eq(_T_618, UInt<1>(0h0))
when _T_621 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_618, UInt<1>(0h1), "") : assert_49
node _T_622 = eq(io.in.a.bits.mask, mask)
node _T_623 = asUInt(reset)
node _T_624 = eq(_T_623, UInt<1>(0h0))
when _T_624 :
node _T_625 = eq(_T_622, UInt<1>(0h0))
when _T_625 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_622, UInt<1>(0h1), "") : assert_50
node _T_626 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_627 = asUInt(reset)
node _T_628 = eq(_T_627, UInt<1>(0h0))
when _T_628 :
node _T_629 = eq(_T_626, UInt<1>(0h0))
when _T_629 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_626, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_630 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_631 = asUInt(reset)
node _T_632 = eq(_T_631, UInt<1>(0h0))
when _T_632 :
node _T_633 = eq(_T_630, UInt<1>(0h0))
when _T_633 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_630, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0))
node _T_634 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_634 :
node _T_635 = asUInt(reset)
node _T_636 = eq(_T_635, UInt<1>(0h0))
when _T_636 :
node _T_637 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_637 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_638 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_639 = asUInt(reset)
node _T_640 = eq(_T_639, UInt<1>(0h0))
when _T_640 :
node _T_641 = eq(_T_638, UInt<1>(0h0))
when _T_641 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_638, UInt<1>(0h1), "") : assert_54
node _T_642 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_643 = asUInt(reset)
node _T_644 = eq(_T_643, UInt<1>(0h0))
when _T_644 :
node _T_645 = eq(_T_642, UInt<1>(0h0))
when _T_645 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_642, UInt<1>(0h1), "") : assert_55
node _T_646 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_647 = asUInt(reset)
node _T_648 = eq(_T_647, UInt<1>(0h0))
when _T_648 :
node _T_649 = eq(_T_646, UInt<1>(0h0))
when _T_649 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_646, UInt<1>(0h1), "") : assert_56
node _T_650 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_651 = asUInt(reset)
node _T_652 = eq(_T_651, UInt<1>(0h0))
when _T_652 :
node _T_653 = eq(_T_650, UInt<1>(0h0))
when _T_653 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_650, UInt<1>(0h1), "") : assert_57
node _T_654 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_654 :
node _T_655 = asUInt(reset)
node _T_656 = eq(_T_655, UInt<1>(0h0))
when _T_656 :
node _T_657 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_657 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_658 = asUInt(reset)
node _T_659 = eq(_T_658, UInt<1>(0h0))
when _T_659 :
node _T_660 = eq(sink_ok, UInt<1>(0h0))
when _T_660 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_661 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_662 = asUInt(reset)
node _T_663 = eq(_T_662, UInt<1>(0h0))
when _T_663 :
node _T_664 = eq(_T_661, UInt<1>(0h0))
when _T_664 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_661, UInt<1>(0h1), "") : assert_60
node _T_665 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_666 = asUInt(reset)
node _T_667 = eq(_T_666, UInt<1>(0h0))
when _T_667 :
node _T_668 = eq(_T_665, UInt<1>(0h0))
when _T_668 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_665, UInt<1>(0h1), "") : assert_61
node _T_669 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_670 = asUInt(reset)
node _T_671 = eq(_T_670, UInt<1>(0h0))
when _T_671 :
node _T_672 = eq(_T_669, UInt<1>(0h0))
when _T_672 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_669, UInt<1>(0h1), "") : assert_62
node _T_673 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_674 = asUInt(reset)
node _T_675 = eq(_T_674, UInt<1>(0h0))
when _T_675 :
node _T_676 = eq(_T_673, UInt<1>(0h0))
when _T_676 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_673, UInt<1>(0h1), "") : assert_63
node _T_677 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_678 = or(UInt<1>(0h0), _T_677)
node _T_679 = asUInt(reset)
node _T_680 = eq(_T_679, UInt<1>(0h0))
when _T_680 :
node _T_681 = eq(_T_678, UInt<1>(0h0))
when _T_681 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_678, UInt<1>(0h1), "") : assert_64
node _T_682 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_682 :
node _T_683 = asUInt(reset)
node _T_684 = eq(_T_683, UInt<1>(0h0))
when _T_684 :
node _T_685 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_685 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_686 = asUInt(reset)
node _T_687 = eq(_T_686, UInt<1>(0h0))
when _T_687 :
node _T_688 = eq(sink_ok, UInt<1>(0h0))
when _T_688 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_689 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_690 = asUInt(reset)
node _T_691 = eq(_T_690, UInt<1>(0h0))
when _T_691 :
node _T_692 = eq(_T_689, UInt<1>(0h0))
when _T_692 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_689, UInt<1>(0h1), "") : assert_67
node _T_693 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_694 = asUInt(reset)
node _T_695 = eq(_T_694, UInt<1>(0h0))
when _T_695 :
node _T_696 = eq(_T_693, UInt<1>(0h0))
when _T_696 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_693, UInt<1>(0h1), "") : assert_68
node _T_697 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_698 = asUInt(reset)
node _T_699 = eq(_T_698, UInt<1>(0h0))
when _T_699 :
node _T_700 = eq(_T_697, UInt<1>(0h0))
when _T_700 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_697, UInt<1>(0h1), "") : assert_69
node _T_701 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_702 = or(_T_701, io.in.d.bits.corrupt)
node _T_703 = asUInt(reset)
node _T_704 = eq(_T_703, UInt<1>(0h0))
when _T_704 :
node _T_705 = eq(_T_702, UInt<1>(0h0))
when _T_705 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_702, UInt<1>(0h1), "") : assert_70
node _T_706 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_707 = or(UInt<1>(0h0), _T_706)
node _T_708 = asUInt(reset)
node _T_709 = eq(_T_708, UInt<1>(0h0))
when _T_709 :
node _T_710 = eq(_T_707, UInt<1>(0h0))
when _T_710 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_707, UInt<1>(0h1), "") : assert_71
node _T_711 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_711 :
node _T_712 = asUInt(reset)
node _T_713 = eq(_T_712, UInt<1>(0h0))
when _T_713 :
node _T_714 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_714 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_715 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_716 = asUInt(reset)
node _T_717 = eq(_T_716, UInt<1>(0h0))
when _T_717 :
node _T_718 = eq(_T_715, UInt<1>(0h0))
when _T_718 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_715, UInt<1>(0h1), "") : assert_73
node _T_719 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_720 = asUInt(reset)
node _T_721 = eq(_T_720, UInt<1>(0h0))
when _T_721 :
node _T_722 = eq(_T_719, UInt<1>(0h0))
when _T_722 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_719, UInt<1>(0h1), "") : assert_74
node _T_723 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_724 = or(UInt<1>(0h0), _T_723)
node _T_725 = asUInt(reset)
node _T_726 = eq(_T_725, UInt<1>(0h0))
when _T_726 :
node _T_727 = eq(_T_724, UInt<1>(0h0))
when _T_727 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_724, UInt<1>(0h1), "") : assert_75
node _T_728 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_728 :
node _T_729 = asUInt(reset)
node _T_730 = eq(_T_729, UInt<1>(0h0))
when _T_730 :
node _T_731 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_731 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_732 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_733 = asUInt(reset)
node _T_734 = eq(_T_733, UInt<1>(0h0))
when _T_734 :
node _T_735 = eq(_T_732, UInt<1>(0h0))
when _T_735 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_732, UInt<1>(0h1), "") : assert_77
node _T_736 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_737 = or(_T_736, io.in.d.bits.corrupt)
node _T_738 = asUInt(reset)
node _T_739 = eq(_T_738, UInt<1>(0h0))
when _T_739 :
node _T_740 = eq(_T_737, UInt<1>(0h0))
when _T_740 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_737, UInt<1>(0h1), "") : assert_78
node _T_741 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_742 = or(UInt<1>(0h0), _T_741)
node _T_743 = asUInt(reset)
node _T_744 = eq(_T_743, UInt<1>(0h0))
when _T_744 :
node _T_745 = eq(_T_742, UInt<1>(0h0))
when _T_745 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_742, UInt<1>(0h1), "") : assert_79
node _T_746 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_746 :
node _T_747 = asUInt(reset)
node _T_748 = eq(_T_747, UInt<1>(0h0))
when _T_748 :
node _T_749 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_749 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_750 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_751 = asUInt(reset)
node _T_752 = eq(_T_751, UInt<1>(0h0))
when _T_752 :
node _T_753 = eq(_T_750, UInt<1>(0h0))
when _T_753 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_750, UInt<1>(0h1), "") : assert_81
node _T_754 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_755 = asUInt(reset)
node _T_756 = eq(_T_755, UInt<1>(0h0))
when _T_756 :
node _T_757 = eq(_T_754, UInt<1>(0h0))
when _T_757 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_754, UInt<1>(0h1), "") : assert_82
node _T_758 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_759 = or(UInt<1>(0h0), _T_758)
node _T_760 = asUInt(reset)
node _T_761 = eq(_T_760, UInt<1>(0h0))
when _T_761 :
node _T_762 = eq(_T_759, UInt<1>(0h0))
when _T_762 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_759, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<9>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<9>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_763 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_764 = asUInt(reset)
node _T_765 = eq(_T_764, UInt<1>(0h0))
when _T_765 :
node _T_766 = eq(_T_763, UInt<1>(0h0))
when _T_766 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_763, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.address, UInt<9>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_767 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_768 = asUInt(reset)
node _T_769 = eq(_T_768, UInt<1>(0h0))
when _T_769 :
node _T_770 = eq(_T_767, UInt<1>(0h0))
when _T_770 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_767, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_771 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_772 = asUInt(reset)
node _T_773 = eq(_T_772, UInt<1>(0h0))
when _T_773 :
node _T_774 = eq(_T_771, UInt<1>(0h0))
when _T_774 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_771, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_775 = eq(a_first, UInt<1>(0h0))
node _T_776 = and(io.in.a.valid, _T_775)
when _T_776 :
node _T_777 = eq(io.in.a.bits.opcode, opcode)
node _T_778 = asUInt(reset)
node _T_779 = eq(_T_778, UInt<1>(0h0))
when _T_779 :
node _T_780 = eq(_T_777, UInt<1>(0h0))
when _T_780 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_777, UInt<1>(0h1), "") : assert_87
node _T_781 = eq(io.in.a.bits.param, param)
node _T_782 = asUInt(reset)
node _T_783 = eq(_T_782, UInt<1>(0h0))
when _T_783 :
node _T_784 = eq(_T_781, UInt<1>(0h0))
when _T_784 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_781, UInt<1>(0h1), "") : assert_88
node _T_785 = eq(io.in.a.bits.size, size)
node _T_786 = asUInt(reset)
node _T_787 = eq(_T_786, UInt<1>(0h0))
when _T_787 :
node _T_788 = eq(_T_785, UInt<1>(0h0))
when _T_788 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_785, UInt<1>(0h1), "") : assert_89
node _T_789 = eq(io.in.a.bits.source, source)
node _T_790 = asUInt(reset)
node _T_791 = eq(_T_790, UInt<1>(0h0))
when _T_791 :
node _T_792 = eq(_T_789, UInt<1>(0h0))
when _T_792 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_789, UInt<1>(0h1), "") : assert_90
node _T_793 = eq(io.in.a.bits.address, address)
node _T_794 = asUInt(reset)
node _T_795 = eq(_T_794, UInt<1>(0h0))
when _T_795 :
node _T_796 = eq(_T_793, UInt<1>(0h0))
when _T_796 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_793, UInt<1>(0h1), "") : assert_91
node _T_797 = and(io.in.a.ready, io.in.a.valid)
node _T_798 = and(_T_797, a_first)
when _T_798 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_799 = eq(d_first, UInt<1>(0h0))
node _T_800 = and(io.in.d.valid, _T_799)
when _T_800 :
node _T_801 = eq(io.in.d.bits.opcode, opcode_1)
node _T_802 = asUInt(reset)
node _T_803 = eq(_T_802, UInt<1>(0h0))
when _T_803 :
node _T_804 = eq(_T_801, UInt<1>(0h0))
when _T_804 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_801, UInt<1>(0h1), "") : assert_92
node _T_805 = eq(io.in.d.bits.param, param_1)
node _T_806 = asUInt(reset)
node _T_807 = eq(_T_806, UInt<1>(0h0))
when _T_807 :
node _T_808 = eq(_T_805, UInt<1>(0h0))
when _T_808 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_805, UInt<1>(0h1), "") : assert_93
node _T_809 = eq(io.in.d.bits.size, size_1)
node _T_810 = asUInt(reset)
node _T_811 = eq(_T_810, UInt<1>(0h0))
when _T_811 :
node _T_812 = eq(_T_809, UInt<1>(0h0))
when _T_812 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_809, UInt<1>(0h1), "") : assert_94
node _T_813 = eq(io.in.d.bits.source, source_1)
node _T_814 = asUInt(reset)
node _T_815 = eq(_T_814, UInt<1>(0h0))
when _T_815 :
node _T_816 = eq(_T_813, UInt<1>(0h0))
when _T_816 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_813, UInt<1>(0h1), "") : assert_95
node _T_817 = eq(io.in.d.bits.sink, sink)
node _T_818 = asUInt(reset)
node _T_819 = eq(_T_818, UInt<1>(0h0))
when _T_819 :
node _T_820 = eq(_T_817, UInt<1>(0h0))
when _T_820 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_817, UInt<1>(0h1), "") : assert_96
node _T_821 = eq(io.in.d.bits.denied, denied)
node _T_822 = asUInt(reset)
node _T_823 = eq(_T_822, UInt<1>(0h0))
when _T_823 :
node _T_824 = eq(_T_821, UInt<1>(0h0))
when _T_824 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_821, UInt<1>(0h1), "") : assert_97
node _T_825 = and(io.in.d.ready, io.in.d.valid)
node _T_826 = and(_T_825, d_first)
when _T_826 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<4>
connect a_sizes_set, UInt<4>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_827 = and(io.in.a.valid, a_first_1)
node _T_828 = and(_T_827, UInt<1>(0h1))
when _T_828 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_829 = and(io.in.a.ready, io.in.a.valid)
node _T_830 = and(_T_829, a_first_1)
node _T_831 = and(_T_830, UInt<1>(0h1))
when _T_831 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_832 = dshr(inflight, io.in.a.bits.source)
node _T_833 = bits(_T_832, 0, 0)
node _T_834 = eq(_T_833, UInt<1>(0h0))
node _T_835 = asUInt(reset)
node _T_836 = eq(_T_835, UInt<1>(0h0))
when _T_836 :
node _T_837 = eq(_T_834, UInt<1>(0h0))
when _T_837 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_834, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<4>
connect d_sizes_clr, UInt<4>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_838 = and(io.in.d.valid, d_first_1)
node _T_839 = and(_T_838, UInt<1>(0h1))
node _T_840 = eq(d_release_ack, UInt<1>(0h0))
node _T_841 = and(_T_839, _T_840)
when _T_841 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_842 = and(io.in.d.ready, io.in.d.valid)
node _T_843 = and(_T_842, d_first_1)
node _T_844 = and(_T_843, UInt<1>(0h1))
node _T_845 = eq(d_release_ack, UInt<1>(0h0))
node _T_846 = and(_T_844, _T_845)
when _T_846 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_847 = and(io.in.d.valid, d_first_1)
node _T_848 = and(_T_847, UInt<1>(0h1))
node _T_849 = eq(d_release_ack, UInt<1>(0h0))
node _T_850 = and(_T_848, _T_849)
when _T_850 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_851 = dshr(inflight, io.in.d.bits.source)
node _T_852 = bits(_T_851, 0, 0)
node _T_853 = or(_T_852, same_cycle_resp)
node _T_854 = asUInt(reset)
node _T_855 = eq(_T_854, UInt<1>(0h0))
when _T_855 :
node _T_856 = eq(_T_853, UInt<1>(0h0))
when _T_856 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_853, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_857 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_858 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_859 = or(_T_857, _T_858)
node _T_860 = asUInt(reset)
node _T_861 = eq(_T_860, UInt<1>(0h0))
when _T_861 :
node _T_862 = eq(_T_859, UInt<1>(0h0))
when _T_862 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_859, UInt<1>(0h1), "") : assert_100
node _T_863 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_864 = asUInt(reset)
node _T_865 = eq(_T_864, UInt<1>(0h0))
when _T_865 :
node _T_866 = eq(_T_863, UInt<1>(0h0))
when _T_866 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_863, UInt<1>(0h1), "") : assert_101
else :
node _T_867 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_868 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_869 = or(_T_867, _T_868)
node _T_870 = asUInt(reset)
node _T_871 = eq(_T_870, UInt<1>(0h0))
when _T_871 :
node _T_872 = eq(_T_869, UInt<1>(0h0))
when _T_872 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_869, UInt<1>(0h1), "") : assert_102
node _T_873 = eq(io.in.d.bits.size, a_size_lookup)
node _T_874 = asUInt(reset)
node _T_875 = eq(_T_874, UInt<1>(0h0))
when _T_875 :
node _T_876 = eq(_T_873, UInt<1>(0h0))
when _T_876 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_873, UInt<1>(0h1), "") : assert_103
node _T_877 = and(io.in.d.valid, d_first_1)
node _T_878 = and(_T_877, a_first_1)
node _T_879 = and(_T_878, io.in.a.valid)
node _T_880 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_881 = and(_T_879, _T_880)
node _T_882 = eq(d_release_ack, UInt<1>(0h0))
node _T_883 = and(_T_881, _T_882)
when _T_883 :
node _T_884 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_885 = or(_T_884, io.in.a.ready)
node _T_886 = asUInt(reset)
node _T_887 = eq(_T_886, UInt<1>(0h0))
when _T_887 :
node _T_888 = eq(_T_885, UInt<1>(0h0))
when _T_888 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_885, UInt<1>(0h1), "") : assert_104
node _T_889 = neq(a_set_wo_ready, d_clr_wo_ready)
node _T_890 = orr(a_set_wo_ready)
node _T_891 = eq(_T_890, UInt<1>(0h0))
node _T_892 = or(_T_889, _T_891)
node _T_893 = asUInt(reset)
node _T_894 = eq(_T_893, UInt<1>(0h0))
when _T_894 :
node _T_895 = eq(_T_892, UInt<1>(0h0))
when _T_895 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105
assert(clock, _T_892, UInt<1>(0h1), "") : assert_105
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_214
node _T_896 = orr(inflight)
node _T_897 = eq(_T_896, UInt<1>(0h0))
node _T_898 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_899 = or(_T_897, _T_898)
node _T_900 = lt(watchdog, plusarg_reader.out)
node _T_901 = or(_T_899, _T_900)
node _T_902 = asUInt(reset)
node _T_903 = eq(_T_902, UInt<1>(0h0))
when _T_903 :
node _T_904 = eq(_T_901, UInt<1>(0h0))
when _T_904 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_901, UInt<1>(0h1), "") : assert_106
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_905 = and(io.in.a.ready, io.in.a.valid)
node _T_906 = and(io.in.d.ready, io.in.d.valid)
node _T_907 = or(_T_905, _T_906)
when _T_907 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<32>(0h0)
connect _c_first_WIRE.bits.address, UInt<9>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<4>
connect c_sizes_set, UInt<4>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<32>(0h0)
connect _WIRE_6.bits.address, UInt<9>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_908 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<32>(0h0)
connect _WIRE_8.bits.address, UInt<9>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_909 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_910 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_911 = and(_T_909, _T_910)
node _T_912 = and(_T_908, _T_911)
when _T_912 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<32>(0h0)
connect _WIRE_10.bits.address, UInt<9>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_913 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_914 = and(_T_913, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<32>(0h0)
connect _WIRE_12.bits.address, UInt<9>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_915 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_916 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_917 = and(_T_915, _T_916)
node _T_918 = and(_T_914, _T_917)
when _T_918 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<9>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<32>(0h0)
connect _WIRE_14.bits.address, UInt<9>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_919 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_920 = bits(_T_919, 0, 0)
node _T_921 = eq(_T_920, UInt<1>(0h0))
node _T_922 = asUInt(reset)
node _T_923 = eq(_T_922, UInt<1>(0h0))
when _T_923 :
node _T_924 = eq(_T_921, UInt<1>(0h0))
when _T_924 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107
assert(clock, _T_921, UInt<1>(0h1), "") : assert_107
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<9>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<4>
connect d_sizes_clr_1, UInt<4>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_925 = and(io.in.d.valid, d_first_2)
node _T_926 = and(_T_925, UInt<1>(0h1))
node _T_927 = and(_T_926, d_release_ack_1)
when _T_927 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_928 = and(io.in.d.ready, io.in.d.valid)
node _T_929 = and(_T_928, d_first_2)
node _T_930 = and(_T_929, UInt<1>(0h1))
node _T_931 = and(_T_930, d_release_ack_1)
when _T_931 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_932 = and(io.in.d.valid, d_first_2)
node _T_933 = and(_T_932, UInt<1>(0h1))
node _T_934 = and(_T_933, d_release_ack_1)
when _T_934 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<9>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_935 = dshr(inflight_1, io.in.d.bits.source)
node _T_936 = bits(_T_935, 0, 0)
node _T_937 = or(_T_936, same_cycle_resp_1)
node _T_938 = asUInt(reset)
node _T_939 = eq(_T_938, UInt<1>(0h0))
when _T_939 :
node _T_940 = eq(_T_937, UInt<1>(0h0))
when _T_940 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_937, UInt<1>(0h1), "") : assert_108
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<32>(0h0)
connect _WIRE_16.bits.address, UInt<9>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_941 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_942 = asUInt(reset)
node _T_943 = eq(_T_942, UInt<1>(0h0))
when _T_943 :
node _T_944 = eq(_T_941, UInt<1>(0h0))
when _T_944 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_941, UInt<1>(0h1), "") : assert_109
else :
node _T_945 = eq(io.in.d.bits.size, c_size_lookup)
node _T_946 = asUInt(reset)
node _T_947 = eq(_T_946, UInt<1>(0h0))
when _T_947 :
node _T_948 = eq(_T_945, UInt<1>(0h0))
when _T_948 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_945, UInt<1>(0h1), "") : assert_110
node _T_949 = and(io.in.d.valid, d_first_2)
node _T_950 = and(_T_949, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<32>(0h0)
connect _WIRE_18.bits.address, UInt<9>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_951 = and(_T_950, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<32>(0h0)
connect _WIRE_20.bits.address, UInt<9>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_952 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_953 = and(_T_951, _T_952)
node _T_954 = and(_T_953, d_release_ack_1)
node _T_955 = eq(c_probe_ack, UInt<1>(0h0))
node _T_956 = and(_T_954, _T_955)
when _T_956 :
node _T_957 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<32>(0h0)
connect _WIRE_22.bits.address, UInt<9>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_958 = or(_T_957, _WIRE_23.ready)
node _T_959 = asUInt(reset)
node _T_960 = eq(_T_959, UInt<1>(0h0))
when _T_960 :
node _T_961 = eq(_T_958, UInt<1>(0h0))
when _T_961 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111
assert(clock, _T_958, UInt<1>(0h1), "") : assert_111
node _T_962 = orr(c_set_wo_ready)
when _T_962 :
node _T_963 = neq(c_set_wo_ready, d_clr_wo_ready_1)
node _T_964 = asUInt(reset)
node _T_965 = eq(_T_964, UInt<1>(0h0))
when _T_965 :
node _T_966 = eq(_T_963, UInt<1>(0h0))
when _T_966 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112
assert(clock, _T_963, UInt<1>(0h1), "") : assert_112
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_215
node _T_967 = orr(inflight_1)
node _T_968 = eq(_T_967, UInt<1>(0h0))
node _T_969 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_970 = or(_T_968, _T_969)
node _T_971 = lt(watchdog_1, plusarg_reader_1.out)
node _T_972 = or(_T_970, _T_971)
node _T_973 = asUInt(reset)
node _T_974 = eq(_T_973, UInt<1>(0h0))
when _T_974 :
node _T_975 = eq(_T_972, UInt<1>(0h0))
when _T_975 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:705:46)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113
assert(clock, _T_972, UInt<1>(0h1), "") : assert_113
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<32>(0h0)
connect _WIRE_24.bits.address, UInt<9>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<9>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_976 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_977 = and(io.in.d.ready, io.in.d.valid)
node _T_978 = or(_T_976, _T_977)
when _T_978 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_90( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [8:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_source, // @[Monitor.scala:20:14]
input io_in_d_bits_sink, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35]
reg a_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [8:0] address; // @[Monitor.scala:391:22]
reg d_first_counter; // @[Edges.scala:229:27]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg source_1; // @[Monitor.scala:541:22]
reg sink; // @[Monitor.scala:542:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
reg [3:0] inflight_sizes; // @[Monitor.scala:618:33]
reg a_first_counter_1; // @[Edges.scala:229:27]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire a_set = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35]
wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46]
wire _GEN = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35]
reg d_first_counter_2; // @[Edges.scala:229:27]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_70 :
input clock : Clock
input reset : Reset
output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}}, flip vcalloc_resp : { vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}, flip out_credit_available : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}, out_virt_channel : UInt<1>}}[1], debug : { va_stall : UInt<1>, sa_stall : UInt<1>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], flip credit_return : UInt<2>, flip vc_free : UInt<2>}}
inst input_buffer of InputBuffer_70
connect input_buffer.clock, clock
connect input_buffer.reset, reset
connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id
connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id
connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node
connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id
connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node
connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id
connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload
connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail
connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head
connect input_buffer.io.enq[0].valid, io.in.flit[0].valid
connect input_buffer.io.deq[0].ready, UInt<1>(0h0)
connect input_buffer.io.deq[1].ready, UInt<1>(0h0)
inst route_arbiter of Arbiter2_RouteComputerReq_24
connect route_arbiter.clock, clock
connect route_arbiter.reset, reset
connect io.router_req.bits, route_arbiter.io.out.bits
connect io.router_req.valid, route_arbiter.io.out.valid
connect route_arbiter.io.out.ready, io.router_req.ready
reg states : { g : UInt<3>, vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<2>}[2], clock
node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head)
when _T :
node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2))
node _T_2 = asUInt(reset)
node _T_3 = eq(_T_2, UInt<1>(0h0))
when _T_3 :
node _T_4 = eq(_T_1, UInt<1>(0h0))
when _T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf
assert(clock, _T_1, UInt<1>(0h1), "") : assert
node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0))
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1
assert(clock, _T_5, UInt<1>(0h1), "") : assert_1
node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9))
node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1))
connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[1], UInt<1>(0h0)
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[0], UInt<1>(0h0)
node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id)
when _T_9 :
connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[0], UInt<1>(0h1)
connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow
node _route_arbiter_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h1))
connect route_arbiter.io.in[0].valid, _route_arbiter_io_in_0_valid_T
connect route_arbiter.io.in[0].bits.flow.egress_node_id, states[0].flow.egress_node_id
connect route_arbiter.io.in[0].bits.flow.egress_node, states[0].flow.egress_node
connect route_arbiter.io.in[0].bits.flow.ingress_node_id, states[0].flow.ingress_node_id
connect route_arbiter.io.in[0].bits.flow.ingress_node, states[0].flow.ingress_node
connect route_arbiter.io.in[0].bits.flow.vnet_id, states[0].flow.vnet_id
connect route_arbiter.io.in[0].bits.src_virt_id, UInt<1>(0h0)
node _T_10 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid)
when _T_10 :
connect states[0].g, UInt<3>(0h2)
node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1))
connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T
connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id
connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node
connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id
connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node
connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id
connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1)
node _T_11 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid)
when _T_11 :
connect states[1].g, UInt<3>(0h2)
node _T_12 = and(io.router_req.ready, io.router_req.valid)
when _T_12 :
node _T_13 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1))
node _T_14 = asUInt(reset)
node _T_15 = eq(_T_14, UInt<1>(0h0))
when _T_15 :
node _T_16 = eq(_T_13, UInt<1>(0h0))
when _T_16 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2
assert(clock, _T_13, UInt<1>(0h1), "") : assert_2
connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2)
node _T_17 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id)
when _T_17 :
connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3`
connect states[0].vc_sel.`4`, io.router_resp.vc_sel.`4`
node _T_18 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id)
when _T_18 :
connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3`
connect states[1].vc_sel.`4`, io.router_resp.vc_sel.`4`
regreset mask : UInt<2>, clock, reset, UInt<2>(0h0)
wire vcalloc_reqs : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}[2]
wire vcalloc_vals : UInt<1>[2]
node _vcalloc_filter_T = cat(vcalloc_vals[1], vcalloc_vals[0])
node _vcalloc_filter_T_1 = cat(vcalloc_vals[1], vcalloc_vals[0])
node _vcalloc_filter_T_2 = not(mask)
node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2)
node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3)
node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0)
node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1)
node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2)
node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3)
node _vcalloc_filter_T_9 = mux(_vcalloc_filter_T_8, UInt<4>(0h8), UInt<4>(0h0))
node _vcalloc_filter_T_10 = mux(_vcalloc_filter_T_7, UInt<4>(0h4), _vcalloc_filter_T_9)
node _vcalloc_filter_T_11 = mux(_vcalloc_filter_T_6, UInt<4>(0h2), _vcalloc_filter_T_10)
node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<4>(0h1), _vcalloc_filter_T_11)
node _vcalloc_sel_T = bits(vcalloc_filter, 1, 0)
node _vcalloc_sel_T_1 = shr(vcalloc_filter, 2)
node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1)
node _T_19 = and(io.router_req.ready, io.router_req.valid)
when _T_19 :
node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id)
node _mask_T_1 = sub(_mask_T, UInt<1>(0h1))
node _mask_T_2 = tail(_mask_T_1, 1)
connect mask, _mask_T_2
else :
node _T_20 = or(vcalloc_vals[0], vcalloc_vals[1])
when _T_20 :
node _mask_T_3 = not(UInt<1>(0h0))
node _mask_T_4 = not(UInt<2>(0h0))
node _mask_T_5 = bits(vcalloc_sel, 0, 0)
node _mask_T_6 = bits(vcalloc_sel, 1, 1)
node _mask_T_7 = mux(_mask_T_5, _mask_T_3, UInt<1>(0h0))
node _mask_T_8 = mux(_mask_T_6, _mask_T_4, UInt<1>(0h0))
node _mask_T_9 = or(_mask_T_7, _mask_T_8)
wire _mask_WIRE : UInt<2>
connect _mask_WIRE, _mask_T_9
connect mask, _mask_WIRE
node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1])
connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T
node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0)
node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1)
wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<1>, vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}}
wire _io_vcalloc_req_bits_WIRE_1 : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}
wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[2]
node _io_vcalloc_req_bits_T_2 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_3 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_4 = or(_io_vcalloc_req_bits_T_2, _io_vcalloc_req_bits_T_3)
wire _io_vcalloc_req_bits_WIRE_3 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_4
connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3
node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_6 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_7 = or(_io_vcalloc_req_bits_T_5, _io_vcalloc_req_bits_T_6)
wire _io_vcalloc_req_bits_WIRE_4 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_7
connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4
connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2
wire _io_vcalloc_req_bits_WIRE_5 : UInt<1>[2]
node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_10 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9)
wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_10
connect _io_vcalloc_req_bits_WIRE_5[0], _io_vcalloc_req_bits_WIRE_6
node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_13 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_12)
wire _io_vcalloc_req_bits_WIRE_7 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_13
connect _io_vcalloc_req_bits_WIRE_5[1], _io_vcalloc_req_bits_WIRE_7
connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_5
wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>[2]
node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_14, _io_vcalloc_req_bits_T_15)
wire _io_vcalloc_req_bits_WIRE_9 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_16
connect _io_vcalloc_req_bits_WIRE_8[0], _io_vcalloc_req_bits_WIRE_9
node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_18)
wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_19
connect _io_vcalloc_req_bits_WIRE_8[1], _io_vcalloc_req_bits_WIRE_10
connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_8
wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[2]
node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_21 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_21)
wire _io_vcalloc_req_bits_WIRE_12 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_22
connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12
node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[1], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_25 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24)
wire _io_vcalloc_req_bits_WIRE_13 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_25
connect _io_vcalloc_req_bits_WIRE_11[1], _io_vcalloc_req_bits_WIRE_13
connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_11
wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>[1]
node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[0], UInt<1>(0h0))
node _io_vcalloc_req_bits_T_28 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_27)
wire _io_vcalloc_req_bits_WIRE_15 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_28
connect _io_vcalloc_req_bits_WIRE_14[0], _io_vcalloc_req_bits_WIRE_15
connect _io_vcalloc_req_bits_WIRE_1.`4`, _io_vcalloc_req_bits_WIRE_14
connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1
node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_29, _io_vcalloc_req_bits_T_30)
wire _io_vcalloc_req_bits_WIRE_16 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_31
connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_16
wire _io_vcalloc_req_bits_WIRE_17 : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_33)
wire _io_vcalloc_req_bits_WIRE_18 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_34
connect _io_vcalloc_req_bits_WIRE_17.egress_node_id, _io_vcalloc_req_bits_WIRE_18
node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_36 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_36)
wire _io_vcalloc_req_bits_WIRE_19 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_37
connect _io_vcalloc_req_bits_WIRE_17.egress_node, _io_vcalloc_req_bits_WIRE_19
node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_40 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39)
wire _io_vcalloc_req_bits_WIRE_20 : UInt<2>
connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_40
connect _io_vcalloc_req_bits_WIRE_17.ingress_node_id, _io_vcalloc_req_bits_WIRE_20
node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_43 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_42)
wire _io_vcalloc_req_bits_WIRE_21 : UInt<4>
connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_43
connect _io_vcalloc_req_bits_WIRE_17.ingress_node, _io_vcalloc_req_bits_WIRE_21
node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0))
node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_44, _io_vcalloc_req_bits_T_45)
wire _io_vcalloc_req_bits_WIRE_22 : UInt<1>
connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_46
connect _io_vcalloc_req_bits_WIRE_17.vnet_id, _io_vcalloc_req_bits_WIRE_22
connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_17
connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE
node _vcalloc_vals_0_T = eq(states[0].g, UInt<3>(0h2))
node _vcalloc_vals_0_T_1 = eq(states[0].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_0_T_2 = and(_vcalloc_vals_0_T, _vcalloc_vals_0_T_1)
connect vcalloc_vals[0], _vcalloc_vals_0_T_2
connect vcalloc_reqs[0].in_vc, UInt<1>(0h0)
connect vcalloc_reqs[0].vc_sel.`0`, states[0].vc_sel.`0`
connect vcalloc_reqs[0].vc_sel.`1`, states[0].vc_sel.`1`
connect vcalloc_reqs[0].vc_sel.`2`, states[0].vc_sel.`2`
connect vcalloc_reqs[0].vc_sel.`3`, states[0].vc_sel.`3`
connect vcalloc_reqs[0].vc_sel.`4`, states[0].vc_sel.`4`
connect vcalloc_reqs[0].flow, states[0].flow
node _T_21 = bits(vcalloc_sel, 0, 0)
node _T_22 = and(vcalloc_vals[0], _T_21)
node _T_23 = and(_T_22, io.vcalloc_req.ready)
when _T_23 :
connect states[0].g, UInt<3>(0h3)
node _T_24 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid)
when _T_24 :
connect vcalloc_vals[0], UInt<1>(0h1)
connect vcalloc_reqs[0].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect vcalloc_reqs[0].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect vcalloc_reqs[0].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect vcalloc_reqs[0].vc_sel.`3`, io.router_resp.vc_sel.`3`
connect vcalloc_reqs[0].vc_sel.`4`, io.router_resp.vc_sel.`4`
node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2))
node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0))
node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1)
connect vcalloc_vals[1], _vcalloc_vals_1_T_2
connect vcalloc_reqs[1].in_vc, UInt<1>(0h1)
connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0`
connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1`
connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2`
connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3`
connect vcalloc_reqs[1].vc_sel.`4`, states[1].vc_sel.`4`
connect vcalloc_reqs[1].flow, states[1].flow
node _T_25 = bits(vcalloc_sel, 1, 1)
node _T_26 = and(vcalloc_vals[1], _T_25)
node _T_27 = and(_T_26, io.vcalloc_req.ready)
when _T_27 :
connect states[1].g, UInt<3>(0h3)
node _T_28 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid)
when _T_28 :
connect vcalloc_vals[1], UInt<1>(0h1)
connect vcalloc_reqs[1].vc_sel.`0`, io.router_resp.vc_sel.`0`
connect vcalloc_reqs[1].vc_sel.`1`, io.router_resp.vc_sel.`1`
connect vcalloc_reqs[1].vc_sel.`2`, io.router_resp.vc_sel.`2`
connect vcalloc_reqs[1].vc_sel.`3`, io.router_resp.vc_sel.`3`
connect vcalloc_reqs[1].vc_sel.`4`, io.router_resp.vc_sel.`4`
node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1])
node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0)
node _io_debug_va_stall_T_2 = sub(_io_debug_va_stall_T_1, io.vcalloc_req.ready)
node _io_debug_va_stall_T_3 = tail(_io_debug_va_stall_T_2, 1)
connect io.debug.va_stall, _io_debug_va_stall_T_3
node _T_29 = and(io.vcalloc_req.ready, io.vcalloc_req.valid)
when _T_29 :
node _T_30 = bits(vcalloc_sel, 0, 0)
when _T_30 :
connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[0].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4`
connect states[0].g, UInt<3>(0h3)
node _T_31 = bits(vcalloc_sel, 1, 1)
when _T_31 :
connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0`
connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1`
connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2`
connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3`
connect states[1].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4`
connect states[1].g, UInt<3>(0h3)
inst salloc_arb of SwitchArbiter_173
connect salloc_arb.clock, clock
connect salloc_arb.reset, reset
node _credit_available_T = cat(states[0].vc_sel.`0`[1], states[0].vc_sel.`0`[0])
node _credit_available_T_1 = cat(states[0].vc_sel.`1`[1], states[0].vc_sel.`1`[0])
node _credit_available_T_2 = cat(states[0].vc_sel.`2`[1], states[0].vc_sel.`2`[0])
node _credit_available_T_3 = cat(states[0].vc_sel.`3`[1], states[0].vc_sel.`3`[0])
node credit_available_lo = cat(_credit_available_T_1, _credit_available_T)
node credit_available_hi_hi = cat(states[0].vc_sel.`4`[0], _credit_available_T_3)
node credit_available_hi = cat(credit_available_hi_hi, _credit_available_T_2)
node _credit_available_T_4 = cat(credit_available_hi, credit_available_lo)
node _credit_available_T_5 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node _credit_available_T_6 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node _credit_available_T_7 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node _credit_available_T_8 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_1 = cat(_credit_available_T_6, _credit_available_T_5)
node credit_available_hi_hi_1 = cat(io.out_credit_available.`4`[0], _credit_available_T_8)
node credit_available_hi_1 = cat(credit_available_hi_hi_1, _credit_available_T_7)
node _credit_available_T_9 = cat(credit_available_hi_1, credit_available_lo_1)
node _credit_available_T_10 = and(_credit_available_T_4, _credit_available_T_9)
node credit_available = neq(_credit_available_T_10, UInt<1>(0h0))
node _salloc_arb_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h3))
node _salloc_arb_io_in_0_valid_T_1 = and(_salloc_arb_io_in_0_valid_T, credit_available)
node _salloc_arb_io_in_0_valid_T_2 = and(_salloc_arb_io_in_0_valid_T_1, input_buffer.io.deq[0].valid)
connect salloc_arb.io.in[0].valid, _salloc_arb_io_in_0_valid_T_2
connect salloc_arb.io.in[0].bits.vc_sel.`0`[0], states[0].vc_sel.`0`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`0`[1], states[0].vc_sel.`0`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[0], states[0].vc_sel.`1`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`1`[1], states[0].vc_sel.`1`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[0], states[0].vc_sel.`2`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`2`[1], states[0].vc_sel.`2`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[0], states[0].vc_sel.`3`[0]
connect salloc_arb.io.in[0].bits.vc_sel.`3`[1], states[0].vc_sel.`3`[1]
connect salloc_arb.io.in[0].bits.vc_sel.`4`[0], states[0].vc_sel.`4`[0]
connect salloc_arb.io.in[0].bits.tail, input_buffer.io.deq[0].bits.tail
node _T_32 = and(salloc_arb.io.in[0].ready, salloc_arb.io.in[0].valid)
node _T_33 = and(_T_32, input_buffer.io.deq[0].bits.tail)
when _T_33 :
connect states[0].g, UInt<3>(0h0)
connect input_buffer.io.deq[0].ready, salloc_arb.io.in[0].ready
node _credit_available_T_11 = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0])
node _credit_available_T_12 = cat(states[1].vc_sel.`1`[1], states[1].vc_sel.`1`[0])
node _credit_available_T_13 = cat(states[1].vc_sel.`2`[1], states[1].vc_sel.`2`[0])
node _credit_available_T_14 = cat(states[1].vc_sel.`3`[1], states[1].vc_sel.`3`[0])
node credit_available_lo_2 = cat(_credit_available_T_12, _credit_available_T_11)
node credit_available_hi_hi_2 = cat(states[1].vc_sel.`4`[0], _credit_available_T_14)
node credit_available_hi_2 = cat(credit_available_hi_hi_2, _credit_available_T_13)
node _credit_available_T_15 = cat(credit_available_hi_2, credit_available_lo_2)
node _credit_available_T_16 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0])
node _credit_available_T_17 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0])
node _credit_available_T_18 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0])
node _credit_available_T_19 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0])
node credit_available_lo_3 = cat(_credit_available_T_17, _credit_available_T_16)
node credit_available_hi_hi_3 = cat(io.out_credit_available.`4`[0], _credit_available_T_19)
node credit_available_hi_3 = cat(credit_available_hi_hi_3, _credit_available_T_18)
node _credit_available_T_20 = cat(credit_available_hi_3, credit_available_lo_3)
node _credit_available_T_21 = and(_credit_available_T_15, _credit_available_T_20)
node credit_available_1 = neq(_credit_available_T_21, UInt<1>(0h0))
node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3))
node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available_1)
node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid)
connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2
connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`2`[1], states[1].vc_sel.`2`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0]
connect salloc_arb.io.in[1].bits.vc_sel.`3`[1], states[1].vc_sel.`3`[1]
connect salloc_arb.io.in[1].bits.vc_sel.`4`[0], states[1].vc_sel.`4`[0]
connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail
node _T_34 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid)
node _T_35 = and(_T_34, input_buffer.io.deq[1].bits.tail)
when _T_35 :
connect states[1].g, UInt<3>(0h0)
connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready
node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T)
node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0))
node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2)
node _io_debug_sa_stall_T_4 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3)
node _io_debug_sa_stall_T_5 = bits(_io_debug_sa_stall_T_4, 1, 0)
connect io.debug.sa_stall, _io_debug_sa_stall_T_5
connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits
connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid
connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready
when io.block :
connect salloc_arb.io.out[0].ready, UInt<1>(0h0)
connect io.salloc_req[0].valid, UInt<1>(0h0)
wire salloc_outs : { valid : UInt<1>, vid : UInt<1>, out_vid : UInt<1>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1]
node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.credit_return, _io_in_credit_return_T_1
node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _io_in_vc_free_T_3 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_4 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _io_in_vc_free_T_5 = or(_io_in_vc_free_T_3, _io_in_vc_free_T_4)
wire _io_in_vc_free_WIRE : UInt<1>
connect _io_in_vc_free_WIRE, _io_in_vc_free_T_5
node _io_in_vc_free_T_6 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE)
node _io_in_vc_free_T_7 = mux(_io_in_vc_free_T_6, salloc_arb.io.chosen_oh[0], UInt<1>(0h0))
connect io.in.vc_free, _io_in_vc_free_T_7
node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
connect salloc_outs[0].valid, _salloc_outs_0_valid_T
node _salloc_outs_0_vid_T = bits(salloc_arb.io.chosen_oh[0], 1, 1)
connect salloc_outs[0].vid, _salloc_outs_0_vid_T
node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
wire vc_sel : { `4` : UInt<1>[1], `3` : UInt<1>[2], `2` : UInt<1>[2], `1` : UInt<1>[2], `0` : UInt<1>[2]}
wire _vc_sel_WIRE : UInt<1>[2]
node _vc_sel_T_2 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_3 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0))
node _vc_sel_T_4 = or(_vc_sel_T_2, _vc_sel_T_3)
wire _vc_sel_WIRE_1 : UInt<1>
connect _vc_sel_WIRE_1, _vc_sel_T_4
connect _vc_sel_WIRE[0], _vc_sel_WIRE_1
node _vc_sel_T_5 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_6 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0))
node _vc_sel_T_7 = or(_vc_sel_T_5, _vc_sel_T_6)
wire _vc_sel_WIRE_2 : UInt<1>
connect _vc_sel_WIRE_2, _vc_sel_T_7
connect _vc_sel_WIRE[1], _vc_sel_WIRE_2
connect vc_sel.`0`, _vc_sel_WIRE
wire _vc_sel_WIRE_3 : UInt<1>[2]
node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0))
node _vc_sel_T_10 = or(_vc_sel_T_8, _vc_sel_T_9)
wire _vc_sel_WIRE_4 : UInt<1>
connect _vc_sel_WIRE_4, _vc_sel_T_10
connect _vc_sel_WIRE_3[0], _vc_sel_WIRE_4
node _vc_sel_T_11 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_12 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0))
node _vc_sel_T_13 = or(_vc_sel_T_11, _vc_sel_T_12)
wire _vc_sel_WIRE_5 : UInt<1>
connect _vc_sel_WIRE_5, _vc_sel_T_13
connect _vc_sel_WIRE_3[1], _vc_sel_WIRE_5
connect vc_sel.`1`, _vc_sel_WIRE_3
wire _vc_sel_WIRE_6 : UInt<1>[2]
node _vc_sel_T_14 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_15 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0))
node _vc_sel_T_16 = or(_vc_sel_T_14, _vc_sel_T_15)
wire _vc_sel_WIRE_7 : UInt<1>
connect _vc_sel_WIRE_7, _vc_sel_T_16
connect _vc_sel_WIRE_6[0], _vc_sel_WIRE_7
node _vc_sel_T_17 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_18 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0))
node _vc_sel_T_19 = or(_vc_sel_T_17, _vc_sel_T_18)
wire _vc_sel_WIRE_8 : UInt<1>
connect _vc_sel_WIRE_8, _vc_sel_T_19
connect _vc_sel_WIRE_6[1], _vc_sel_WIRE_8
connect vc_sel.`2`, _vc_sel_WIRE_6
wire _vc_sel_WIRE_9 : UInt<1>[2]
node _vc_sel_T_20 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_21 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0))
node _vc_sel_T_22 = or(_vc_sel_T_20, _vc_sel_T_21)
wire _vc_sel_WIRE_10 : UInt<1>
connect _vc_sel_WIRE_10, _vc_sel_T_22
connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10
node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[1], UInt<1>(0h0))
node _vc_sel_T_25 = or(_vc_sel_T_23, _vc_sel_T_24)
wire _vc_sel_WIRE_11 : UInt<1>
connect _vc_sel_WIRE_11, _vc_sel_T_25
connect _vc_sel_WIRE_9[1], _vc_sel_WIRE_11
connect vc_sel.`3`, _vc_sel_WIRE_9
wire _vc_sel_WIRE_12 : UInt<1>[1]
node _vc_sel_T_26 = mux(_vc_sel_T, states[0].vc_sel.`4`[0], UInt<1>(0h0))
node _vc_sel_T_27 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[0], UInt<1>(0h0))
node _vc_sel_T_28 = or(_vc_sel_T_26, _vc_sel_T_27)
wire _vc_sel_WIRE_13 : UInt<1>
connect _vc_sel_WIRE_13, _vc_sel_T_28
connect _vc_sel_WIRE_12[0], _vc_sel_WIRE_13
connect vc_sel.`4`, _vc_sel_WIRE_12
node channel_oh_0 = or(vc_sel.`0`[0], vc_sel.`0`[1])
node channel_oh_1 = or(vc_sel.`1`[0], vc_sel.`1`[1])
node channel_oh_2 = or(vc_sel.`2`[0], vc_sel.`2`[1])
node channel_oh_3 = or(vc_sel.`3`[0], vc_sel.`3`[1])
node _virt_channel_T = cat(vc_sel.`0`[1], vc_sel.`0`[0])
node _virt_channel_T_1 = bits(_virt_channel_T, 1, 1)
node _virt_channel_T_2 = cat(vc_sel.`1`[1], vc_sel.`1`[0])
node _virt_channel_T_3 = bits(_virt_channel_T_2, 1, 1)
node _virt_channel_T_4 = cat(vc_sel.`2`[1], vc_sel.`2`[0])
node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1)
node _virt_channel_T_6 = cat(vc_sel.`3`[1], vc_sel.`3`[0])
node _virt_channel_T_7 = bits(_virt_channel_T_6, 1, 1)
node _virt_channel_T_8 = mux(channel_oh_0, _virt_channel_T_1, UInt<1>(0h0))
node _virt_channel_T_9 = mux(channel_oh_1, _virt_channel_T_3, UInt<1>(0h0))
node _virt_channel_T_10 = mux(channel_oh_2, _virt_channel_T_5, UInt<1>(0h0))
node _virt_channel_T_11 = mux(channel_oh_3, _virt_channel_T_7, UInt<1>(0h0))
node _virt_channel_T_12 = mux(vc_sel.`4`[0], UInt<1>(0h0), UInt<1>(0h0))
node _virt_channel_T_13 = or(_virt_channel_T_8, _virt_channel_T_9)
node _virt_channel_T_14 = or(_virt_channel_T_13, _virt_channel_T_10)
node _virt_channel_T_15 = or(_virt_channel_T_14, _virt_channel_T_11)
node _virt_channel_T_16 = or(_virt_channel_T_15, _virt_channel_T_12)
wire virt_channel : UInt<1>
connect virt_channel, _virt_channel_T_16
node _T_36 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid)
when _T_36 :
connect salloc_outs[0].out_vid, virt_channel
node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_payload_T_2 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_3 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0))
node _salloc_outs_0_flit_payload_T_4 = or(_salloc_outs_0_flit_payload_T_2, _salloc_outs_0_flit_payload_T_3)
wire _salloc_outs_0_flit_payload_WIRE : UInt<37>
connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_4
connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE
node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_head_T_2 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_3 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0))
node _salloc_outs_0_flit_head_T_4 = or(_salloc_outs_0_flit_head_T_2, _salloc_outs_0_flit_head_T_3)
wire _salloc_outs_0_flit_head_WIRE : UInt<1>
connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_4
connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE
node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
node _salloc_outs_0_flit_tail_T_2 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_3 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0))
node _salloc_outs_0_flit_tail_T_4 = or(_salloc_outs_0_flit_tail_T_2, _salloc_outs_0_flit_tail_T_3)
wire _salloc_outs_0_flit_tail_WIRE : UInt<1>
connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_4
connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE
node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0)
node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1)
wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}
node _salloc_outs_0_flit_flow_T_2 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_3 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_4 = or(_salloc_outs_0_flit_flow_T_2, _salloc_outs_0_flit_flow_T_3)
wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_4
connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1
node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_6 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_7 = or(_salloc_outs_0_flit_flow_T_5, _salloc_outs_0_flit_flow_T_6)
wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4>
connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_7
connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2
node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_10 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9)
wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2>
connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_10
connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3
node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_13 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_12)
wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4>
connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_13
connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4
node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0))
node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_14, _salloc_outs_0_flit_flow_T_15)
wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<1>
connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_16
connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5
connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE
else :
invalidate salloc_outs[0].out_vid
invalidate salloc_outs[0].flit.virt_channel_id
invalidate salloc_outs[0].flit.flow.egress_node_id
invalidate salloc_outs[0].flit.flow.egress_node
invalidate salloc_outs[0].flit.flow.ingress_node_id
invalidate salloc_outs[0].flit.flow.ingress_node
invalidate salloc_outs[0].flit.flow.vnet_id
invalidate salloc_outs[0].flit.payload
invalidate salloc_outs[0].flit.tail
invalidate salloc_outs[0].flit.head
invalidate salloc_outs[0].flit.virt_channel_id
connect io.out[0].valid, salloc_outs[0].valid
connect io.out[0].bits.flit, salloc_outs[0].flit
connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid
connect states[0].vc_sel.`0`[1], UInt<1>(0h0)
connect states[0].vc_sel.`1`[0], UInt<1>(0h0)
connect states[0].vc_sel.`1`[1], UInt<1>(0h0)
connect states[0].vc_sel.`2`[0], UInt<1>(0h0)
connect states[0].vc_sel.`2`[1], UInt<1>(0h0)
connect states[0].vc_sel.`3`[0], UInt<1>(0h0)
connect states[0].vc_sel.`3`[1], UInt<1>(0h0)
connect states[1].vc_sel.`0`[0], UInt<1>(0h0)
connect states[1].vc_sel.`1`[0], UInt<1>(0h0)
connect states[1].vc_sel.`2`[0], UInt<1>(0h0)
connect states[1].vc_sel.`2`[1], UInt<1>(0h0)
connect states[1].vc_sel.`3`[0], UInt<1>(0h0)
node _T_37 = asUInt(reset)
when _T_37 :
connect states[0].g, UInt<3>(0h0)
connect states[1].g, UInt<3>(0h0) | module InputUnit_70( // @[InputUnit.scala:158:7]
input clock, // @[InputUnit.scala:158:7]
input reset, // @[InputUnit.scala:158:7]
output io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14]
output io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_3_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14]
input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_vcalloc_req_ready, // @[InputUnit.scala:170:14]
output io_vcalloc_req_valid, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_4_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_3_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14]
output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_4_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_3_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_1_1, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_0, // @[InputUnit.scala:170:14]
input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_4_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_3_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_2_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_1_1, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_0, // @[InputUnit.scala:170:14]
input io_out_credit_available_0_1, // @[InputUnit.scala:170:14]
input io_salloc_req_0_ready, // @[InputUnit.scala:170:14]
output io_salloc_req_0_valid, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_4_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14]
output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14]
output io_out_0_valid, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14]
output [36:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14]
output io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14]
output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14]
output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14]
output io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14]
output io_debug_va_stall, // @[InputUnit.scala:170:14]
output io_debug_sa_stall, // @[InputUnit.scala:170:14]
input io_in_flit_0_valid, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14]
input [36:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14]
input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14]
input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14]
input io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14]
output [1:0] io_in_credit_return, // @[InputUnit.scala:170:14]
output [1:0] io_in_vc_free // @[InputUnit.scala:170:14]
);
wire _GEN; // @[MixedVec.scala:116:9]
wire vcalloc_reqs_1_vc_sel_3_1; // @[MixedVec.scala:116:9]
wire vcalloc_reqs_1_vc_sel_1_1; // @[MixedVec.scala:116:9]
wire vcalloc_reqs_1_vc_sel_0_1; // @[MixedVec.scala:116:9]
wire vcalloc_vals_1; // @[InputUnit.scala:266:25, :272:46, :273:29]
wire _GEN_0; // @[MixedVec.scala:116:9]
wire vcalloc_reqs_0_vc_sel_0_0; // @[MixedVec.scala:116:9]
wire vcalloc_vals_0; // @[InputUnit.scala:266:25, :272:46, :273:29]
wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26]
wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26]
wire [1:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26]
wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29]
wire _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29]
wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28]
wire [36:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28]
wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28]
wire [36:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28]
reg [2:0] states_0_g; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_4_0; // @[InputUnit.scala:192:19]
reg states_0_vc_sel_0_0; // @[InputUnit.scala:192:19]
reg states_0_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19]
reg [2:0] states_1_g; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_4_0; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_3_1; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_1_1; // @[InputUnit.scala:192:19]
reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19]
reg states_1_flow_vnet_id; // @[InputUnit.scala:192:19]
reg [3:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19]
reg [3:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19]
reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19]
wire _GEN_1 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30]
wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22]
wire _GEN_2 = _route_arbiter_io_in_1_ready & route_arbiter_io_in_1_valid; // @[Decoupled.scala:51:35] |
Generate the Verilog code corresponding to this FIRRTL code module ITLB :
input clock : Clock
input reset : Reset
output io : { flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vaddr : UInt<40>, passthrough : UInt<1>, size : UInt<2>, cmd : UInt<5>, prv : UInt<2>, v : UInt<1>}}, resp : { miss : UInt<1>, paddr : UInt<32>, gpa : UInt<40>, gpa_is_pte : UInt<1>, pf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, ma : { ld : UInt<1>, st : UInt<1>, inst : UInt<1>}, cacheable : UInt<1>, must_alloc : UInt<1>, prefetchable : UInt<1>, size : UInt<2>, cmd : UInt<5>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, ptw : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[2]}}, flip kill : UInt<1>}
invalidate io.ptw.customCSRs.csrs[0].sdata
invalidate io.ptw.customCSRs.csrs[0].set
invalidate io.ptw.customCSRs.csrs[0].stall
invalidate io.ptw.customCSRs.csrs[0].value
invalidate io.ptw.customCSRs.csrs[0].wdata
invalidate io.ptw.customCSRs.csrs[0].wen
invalidate io.ptw.customCSRs.csrs[0].ren
invalidate io.ptw.customCSRs.csrs[1].sdata
invalidate io.ptw.customCSRs.csrs[1].set
invalidate io.ptw.customCSRs.csrs[1].stall
invalidate io.ptw.customCSRs.csrs[1].value
invalidate io.ptw.customCSRs.csrs[1].wdata
invalidate io.ptw.customCSRs.csrs[1].wen
invalidate io.ptw.customCSRs.csrs[1].ren
node vpn = bits(io.req.bits.vaddr, 38, 12)
reg sectored_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[4], valid : UInt<1>[4]}[8][1], clock
reg superpage_entries : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}[4], clock
reg special_entry : { level : UInt<2>, tag_vpn : UInt<27>, tag_v : UInt<1>, data : UInt<42>[1], valid : UInt<1>[1]}, clock
regreset state : UInt<2>, clock, reset, UInt<2>(0h0)
reg r_refill_tag : UInt<27>, clock
reg r_superpage_repl_addr : UInt<2>, clock
reg r_sectored_repl_addr : UInt<3>, clock
reg r_sectored_hit : { valid : UInt<1>, bits : UInt<3>}, clock
reg r_superpage_hit : { valid : UInt<1>, bits : UInt<2>}, clock
reg r_vstage1_en : UInt<1>, clock
reg r_stage2_en : UInt<1>, clock
reg r_need_gpa : UInt<1>, clock
reg r_gpa_valid : UInt<1>, clock
reg r_gpa : UInt<39>, clock
reg r_gpa_vpn : UInt<27>, clock
reg r_gpa_is_pte : UInt<1>, clock
node priv_v = and(UInt<1>(0h0), io.req.bits.v)
node priv_s = bits(io.req.bits.prv, 0, 0)
node priv_uses_vm = leq(io.req.bits.prv, UInt<1>(0h1))
node satp = mux(priv_v, io.ptw.vsatp, io.ptw.ptbr)
node _stage1_en_T = bits(satp.mode, 3, 3)
node stage1_en = and(UInt<1>(0h1), _stage1_en_T)
node _vstage1_en_T = and(UInt<1>(0h0), priv_v)
node _vstage1_en_T_1 = bits(io.ptw.vsatp.mode, 3, 3)
node vstage1_en = and(_vstage1_en_T, _vstage1_en_T_1)
node _stage2_en_T = and(UInt<1>(0h0), priv_v)
node _stage2_en_T_1 = bits(io.ptw.hgatp.mode, 3, 3)
node stage2_en = and(_stage2_en_T, _stage2_en_T_1)
node _vm_enabled_T = or(stage1_en, stage2_en)
node _vm_enabled_T_1 = and(_vm_enabled_T, priv_uses_vm)
node _vm_enabled_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0))
node vm_enabled = and(_vm_enabled_T_1, _vm_enabled_T_2)
regreset v_entries_use_stage1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _vsatp_mode_mismatch_T = neq(vstage1_en, v_entries_use_stage1)
node _vsatp_mode_mismatch_T_1 = and(priv_v, _vsatp_mode_mismatch_T)
node _vsatp_mode_mismatch_T_2 = eq(io.req.bits.passthrough, UInt<1>(0h0))
node vsatp_mode_mismatch = and(_vsatp_mode_mismatch_T_1, _vsatp_mode_mismatch_T_2)
node refill_ppn = bits(io.ptw.resp.bits.pte.ppn, 19, 0)
node do_refill = and(UInt<1>(0h1), io.ptw.resp.valid)
node _invalidate_refill_T = eq(state, UInt<2>(0h1))
node _invalidate_refill_T_1 = eq(state, UInt<2>(0h3))
node _invalidate_refill_T_2 = or(_invalidate_refill_T, _invalidate_refill_T_1)
node invalidate_refill = or(_invalidate_refill_T_2, io.sfence.valid)
node _mpu_ppn_T = and(vm_enabled, UInt<1>(0h1))
wire _mpu_ppn_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _mpu_ppn_WIRE_1 : UInt<42>
connect _mpu_ppn_WIRE_1, special_entry.data[0]
node _mpu_ppn_T_1 = bits(_mpu_ppn_WIRE_1, 0, 0)
connect _mpu_ppn_WIRE.fragmented_superpage, _mpu_ppn_T_1
node _mpu_ppn_T_2 = bits(_mpu_ppn_WIRE_1, 1, 1)
connect _mpu_ppn_WIRE.c, _mpu_ppn_T_2
node _mpu_ppn_T_3 = bits(_mpu_ppn_WIRE_1, 2, 2)
connect _mpu_ppn_WIRE.eff, _mpu_ppn_T_3
node _mpu_ppn_T_4 = bits(_mpu_ppn_WIRE_1, 3, 3)
connect _mpu_ppn_WIRE.paa, _mpu_ppn_T_4
node _mpu_ppn_T_5 = bits(_mpu_ppn_WIRE_1, 4, 4)
connect _mpu_ppn_WIRE.pal, _mpu_ppn_T_5
node _mpu_ppn_T_6 = bits(_mpu_ppn_WIRE_1, 5, 5)
connect _mpu_ppn_WIRE.ppp, _mpu_ppn_T_6
node _mpu_ppn_T_7 = bits(_mpu_ppn_WIRE_1, 6, 6)
connect _mpu_ppn_WIRE.pr, _mpu_ppn_T_7
node _mpu_ppn_T_8 = bits(_mpu_ppn_WIRE_1, 7, 7)
connect _mpu_ppn_WIRE.px, _mpu_ppn_T_8
node _mpu_ppn_T_9 = bits(_mpu_ppn_WIRE_1, 8, 8)
connect _mpu_ppn_WIRE.pw, _mpu_ppn_T_9
node _mpu_ppn_T_10 = bits(_mpu_ppn_WIRE_1, 9, 9)
connect _mpu_ppn_WIRE.hr, _mpu_ppn_T_10
node _mpu_ppn_T_11 = bits(_mpu_ppn_WIRE_1, 10, 10)
connect _mpu_ppn_WIRE.hx, _mpu_ppn_T_11
node _mpu_ppn_T_12 = bits(_mpu_ppn_WIRE_1, 11, 11)
connect _mpu_ppn_WIRE.hw, _mpu_ppn_T_12
node _mpu_ppn_T_13 = bits(_mpu_ppn_WIRE_1, 12, 12)
connect _mpu_ppn_WIRE.sr, _mpu_ppn_T_13
node _mpu_ppn_T_14 = bits(_mpu_ppn_WIRE_1, 13, 13)
connect _mpu_ppn_WIRE.sx, _mpu_ppn_T_14
node _mpu_ppn_T_15 = bits(_mpu_ppn_WIRE_1, 14, 14)
connect _mpu_ppn_WIRE.sw, _mpu_ppn_T_15
node _mpu_ppn_T_16 = bits(_mpu_ppn_WIRE_1, 15, 15)
connect _mpu_ppn_WIRE.gf, _mpu_ppn_T_16
node _mpu_ppn_T_17 = bits(_mpu_ppn_WIRE_1, 16, 16)
connect _mpu_ppn_WIRE.pf, _mpu_ppn_T_17
node _mpu_ppn_T_18 = bits(_mpu_ppn_WIRE_1, 17, 17)
connect _mpu_ppn_WIRE.ae_stage2, _mpu_ppn_T_18
node _mpu_ppn_T_19 = bits(_mpu_ppn_WIRE_1, 18, 18)
connect _mpu_ppn_WIRE.ae_final, _mpu_ppn_T_19
node _mpu_ppn_T_20 = bits(_mpu_ppn_WIRE_1, 19, 19)
connect _mpu_ppn_WIRE.ae_ptw, _mpu_ppn_T_20
node _mpu_ppn_T_21 = bits(_mpu_ppn_WIRE_1, 20, 20)
connect _mpu_ppn_WIRE.g, _mpu_ppn_T_21
node _mpu_ppn_T_22 = bits(_mpu_ppn_WIRE_1, 21, 21)
connect _mpu_ppn_WIRE.u, _mpu_ppn_T_22
node _mpu_ppn_T_23 = bits(_mpu_ppn_WIRE_1, 41, 22)
connect _mpu_ppn_WIRE.ppn, _mpu_ppn_T_23
inst mpu_ppn_barrier of OptimizationBarrier_TLBEntryData
connect mpu_ppn_barrier.clock, clock
connect mpu_ppn_barrier.reset, reset
connect mpu_ppn_barrier.io.x.fragmented_superpage, _mpu_ppn_WIRE.fragmented_superpage
connect mpu_ppn_barrier.io.x.c, _mpu_ppn_WIRE.c
connect mpu_ppn_barrier.io.x.eff, _mpu_ppn_WIRE.eff
connect mpu_ppn_barrier.io.x.paa, _mpu_ppn_WIRE.paa
connect mpu_ppn_barrier.io.x.pal, _mpu_ppn_WIRE.pal
connect mpu_ppn_barrier.io.x.ppp, _mpu_ppn_WIRE.ppp
connect mpu_ppn_barrier.io.x.pr, _mpu_ppn_WIRE.pr
connect mpu_ppn_barrier.io.x.px, _mpu_ppn_WIRE.px
connect mpu_ppn_barrier.io.x.pw, _mpu_ppn_WIRE.pw
connect mpu_ppn_barrier.io.x.hr, _mpu_ppn_WIRE.hr
connect mpu_ppn_barrier.io.x.hx, _mpu_ppn_WIRE.hx
connect mpu_ppn_barrier.io.x.hw, _mpu_ppn_WIRE.hw
connect mpu_ppn_barrier.io.x.sr, _mpu_ppn_WIRE.sr
connect mpu_ppn_barrier.io.x.sx, _mpu_ppn_WIRE.sx
connect mpu_ppn_barrier.io.x.sw, _mpu_ppn_WIRE.sw
connect mpu_ppn_barrier.io.x.gf, _mpu_ppn_WIRE.gf
connect mpu_ppn_barrier.io.x.pf, _mpu_ppn_WIRE.pf
connect mpu_ppn_barrier.io.x.ae_stage2, _mpu_ppn_WIRE.ae_stage2
connect mpu_ppn_barrier.io.x.ae_final, _mpu_ppn_WIRE.ae_final
connect mpu_ppn_barrier.io.x.ae_ptw, _mpu_ppn_WIRE.ae_ptw
connect mpu_ppn_barrier.io.x.g, _mpu_ppn_WIRE.g
connect mpu_ppn_barrier.io.x.u, _mpu_ppn_WIRE.u
connect mpu_ppn_barrier.io.x.ppn, _mpu_ppn_WIRE.ppn
node mpu_ppn_res = shr(mpu_ppn_barrier.io.y.ppn, 18)
node _mpu_ppn_ignore_T = lt(special_entry.level, UInt<1>(0h1))
node mpu_ppn_ignore = or(_mpu_ppn_ignore_T, UInt<1>(0h0))
node _mpu_ppn_T_24 = mux(mpu_ppn_ignore, vpn, UInt<1>(0h0))
node _mpu_ppn_T_25 = or(_mpu_ppn_T_24, mpu_ppn_barrier.io.y.ppn)
node _mpu_ppn_T_26 = bits(_mpu_ppn_T_25, 17, 9)
node _mpu_ppn_T_27 = cat(mpu_ppn_res, _mpu_ppn_T_26)
node _mpu_ppn_ignore_T_1 = lt(special_entry.level, UInt<2>(0h2))
node mpu_ppn_ignore_1 = or(_mpu_ppn_ignore_T_1, UInt<1>(0h0))
node _mpu_ppn_T_28 = mux(mpu_ppn_ignore_1, vpn, UInt<1>(0h0))
node _mpu_ppn_T_29 = or(_mpu_ppn_T_28, mpu_ppn_barrier.io.y.ppn)
node _mpu_ppn_T_30 = bits(_mpu_ppn_T_29, 8, 0)
node _mpu_ppn_T_31 = cat(_mpu_ppn_T_27, _mpu_ppn_T_30)
node _mpu_ppn_T_32 = shr(io.req.bits.vaddr, 12)
node _mpu_ppn_T_33 = mux(_mpu_ppn_T, _mpu_ppn_T_31, _mpu_ppn_T_32)
node mpu_ppn = mux(do_refill, refill_ppn, _mpu_ppn_T_33)
node _mpu_physaddr_T = bits(io.req.bits.vaddr, 11, 0)
node mpu_physaddr = cat(mpu_ppn, _mpu_physaddr_T)
node _mpu_priv_T = or(do_refill, io.req.bits.passthrough)
node _mpu_priv_T_1 = and(UInt<1>(0h1), _mpu_priv_T)
node _mpu_priv_T_2 = cat(io.ptw.status.debug, io.req.bits.prv)
node mpu_priv = mux(_mpu_priv_T_1, UInt<1>(0h1), _mpu_priv_T_2)
inst pmp of PMPChecker_s3
connect pmp.clock, clock
connect pmp.reset, reset
connect pmp.io.addr, mpu_physaddr
connect pmp.io.size, io.req.bits.size
connect pmp.io.pmp[0].mask, io.ptw.pmp[0].mask
connect pmp.io.pmp[0].addr, io.ptw.pmp[0].addr
connect pmp.io.pmp[0].cfg.r, io.ptw.pmp[0].cfg.r
connect pmp.io.pmp[0].cfg.w, io.ptw.pmp[0].cfg.w
connect pmp.io.pmp[0].cfg.x, io.ptw.pmp[0].cfg.x
connect pmp.io.pmp[0].cfg.a, io.ptw.pmp[0].cfg.a
connect pmp.io.pmp[0].cfg.res, io.ptw.pmp[0].cfg.res
connect pmp.io.pmp[0].cfg.l, io.ptw.pmp[0].cfg.l
connect pmp.io.pmp[1].mask, io.ptw.pmp[1].mask
connect pmp.io.pmp[1].addr, io.ptw.pmp[1].addr
connect pmp.io.pmp[1].cfg.r, io.ptw.pmp[1].cfg.r
connect pmp.io.pmp[1].cfg.w, io.ptw.pmp[1].cfg.w
connect pmp.io.pmp[1].cfg.x, io.ptw.pmp[1].cfg.x
connect pmp.io.pmp[1].cfg.a, io.ptw.pmp[1].cfg.a
connect pmp.io.pmp[1].cfg.res, io.ptw.pmp[1].cfg.res
connect pmp.io.pmp[1].cfg.l, io.ptw.pmp[1].cfg.l
connect pmp.io.pmp[2].mask, io.ptw.pmp[2].mask
connect pmp.io.pmp[2].addr, io.ptw.pmp[2].addr
connect pmp.io.pmp[2].cfg.r, io.ptw.pmp[2].cfg.r
connect pmp.io.pmp[2].cfg.w, io.ptw.pmp[2].cfg.w
connect pmp.io.pmp[2].cfg.x, io.ptw.pmp[2].cfg.x
connect pmp.io.pmp[2].cfg.a, io.ptw.pmp[2].cfg.a
connect pmp.io.pmp[2].cfg.res, io.ptw.pmp[2].cfg.res
connect pmp.io.pmp[2].cfg.l, io.ptw.pmp[2].cfg.l
connect pmp.io.pmp[3].mask, io.ptw.pmp[3].mask
connect pmp.io.pmp[3].addr, io.ptw.pmp[3].addr
connect pmp.io.pmp[3].cfg.r, io.ptw.pmp[3].cfg.r
connect pmp.io.pmp[3].cfg.w, io.ptw.pmp[3].cfg.w
connect pmp.io.pmp[3].cfg.x, io.ptw.pmp[3].cfg.x
connect pmp.io.pmp[3].cfg.a, io.ptw.pmp[3].cfg.a
connect pmp.io.pmp[3].cfg.res, io.ptw.pmp[3].cfg.res
connect pmp.io.pmp[3].cfg.l, io.ptw.pmp[3].cfg.l
connect pmp.io.pmp[4].mask, io.ptw.pmp[4].mask
connect pmp.io.pmp[4].addr, io.ptw.pmp[4].addr
connect pmp.io.pmp[4].cfg.r, io.ptw.pmp[4].cfg.r
connect pmp.io.pmp[4].cfg.w, io.ptw.pmp[4].cfg.w
connect pmp.io.pmp[4].cfg.x, io.ptw.pmp[4].cfg.x
connect pmp.io.pmp[4].cfg.a, io.ptw.pmp[4].cfg.a
connect pmp.io.pmp[4].cfg.res, io.ptw.pmp[4].cfg.res
connect pmp.io.pmp[4].cfg.l, io.ptw.pmp[4].cfg.l
connect pmp.io.pmp[5].mask, io.ptw.pmp[5].mask
connect pmp.io.pmp[5].addr, io.ptw.pmp[5].addr
connect pmp.io.pmp[5].cfg.r, io.ptw.pmp[5].cfg.r
connect pmp.io.pmp[5].cfg.w, io.ptw.pmp[5].cfg.w
connect pmp.io.pmp[5].cfg.x, io.ptw.pmp[5].cfg.x
connect pmp.io.pmp[5].cfg.a, io.ptw.pmp[5].cfg.a
connect pmp.io.pmp[5].cfg.res, io.ptw.pmp[5].cfg.res
connect pmp.io.pmp[5].cfg.l, io.ptw.pmp[5].cfg.l
connect pmp.io.pmp[6].mask, io.ptw.pmp[6].mask
connect pmp.io.pmp[6].addr, io.ptw.pmp[6].addr
connect pmp.io.pmp[6].cfg.r, io.ptw.pmp[6].cfg.r
connect pmp.io.pmp[6].cfg.w, io.ptw.pmp[6].cfg.w
connect pmp.io.pmp[6].cfg.x, io.ptw.pmp[6].cfg.x
connect pmp.io.pmp[6].cfg.a, io.ptw.pmp[6].cfg.a
connect pmp.io.pmp[6].cfg.res, io.ptw.pmp[6].cfg.res
connect pmp.io.pmp[6].cfg.l, io.ptw.pmp[6].cfg.l
connect pmp.io.pmp[7].mask, io.ptw.pmp[7].mask
connect pmp.io.pmp[7].addr, io.ptw.pmp[7].addr
connect pmp.io.pmp[7].cfg.r, io.ptw.pmp[7].cfg.r
connect pmp.io.pmp[7].cfg.w, io.ptw.pmp[7].cfg.w
connect pmp.io.pmp[7].cfg.x, io.ptw.pmp[7].cfg.x
connect pmp.io.pmp[7].cfg.a, io.ptw.pmp[7].cfg.a
connect pmp.io.pmp[7].cfg.res, io.ptw.pmp[7].cfg.res
connect pmp.io.pmp[7].cfg.l, io.ptw.pmp[7].cfg.l
connect pmp.io.prv, mpu_priv
inst pma of PMAChecker
connect pma.clock, clock
connect pma.reset, reset
connect pma.io.paddr, mpu_physaddr
node cacheable = and(pma.io.resp.cacheable, UInt<1>(0h1))
node _homogeneous_T = xor(mpu_physaddr, UInt<1>(0h0))
node _homogeneous_T_1 = cvt(_homogeneous_T)
node _homogeneous_T_2 = and(_homogeneous_T_1, asSInt(UInt<14>(0h2000)))
node _homogeneous_T_3 = asSInt(_homogeneous_T_2)
node _homogeneous_T_4 = eq(_homogeneous_T_3, asSInt(UInt<1>(0h0)))
node _homogeneous_T_5 = xor(mpu_physaddr, UInt<14>(0h3000))
node _homogeneous_T_6 = cvt(_homogeneous_T_5)
node _homogeneous_T_7 = and(_homogeneous_T_6, asSInt(UInt<13>(0h1000)))
node _homogeneous_T_8 = asSInt(_homogeneous_T_7)
node _homogeneous_T_9 = eq(_homogeneous_T_8, asSInt(UInt<1>(0h0)))
node _homogeneous_T_10 = xor(mpu_physaddr, UInt<17>(0h10000))
node _homogeneous_T_11 = cvt(_homogeneous_T_10)
node _homogeneous_T_12 = and(_homogeneous_T_11, asSInt(UInt<17>(0h10000)))
node _homogeneous_T_13 = asSInt(_homogeneous_T_12)
node _homogeneous_T_14 = eq(_homogeneous_T_13, asSInt(UInt<1>(0h0)))
node _homogeneous_T_15 = xor(mpu_physaddr, UInt<21>(0h100000))
node _homogeneous_T_16 = cvt(_homogeneous_T_15)
node _homogeneous_T_17 = and(_homogeneous_T_16, asSInt(UInt<18>(0h2f000)))
node _homogeneous_T_18 = asSInt(_homogeneous_T_17)
node _homogeneous_T_19 = eq(_homogeneous_T_18, asSInt(UInt<1>(0h0)))
node _homogeneous_T_20 = xor(mpu_physaddr, UInt<26>(0h2000000))
node _homogeneous_T_21 = cvt(_homogeneous_T_20)
node _homogeneous_T_22 = and(_homogeneous_T_21, asSInt(UInt<17>(0h10000)))
node _homogeneous_T_23 = asSInt(_homogeneous_T_22)
node _homogeneous_T_24 = eq(_homogeneous_T_23, asSInt(UInt<1>(0h0)))
node _homogeneous_T_25 = xor(mpu_physaddr, UInt<26>(0h2010000))
node _homogeneous_T_26 = cvt(_homogeneous_T_25)
node _homogeneous_T_27 = and(_homogeneous_T_26, asSInt(UInt<13>(0h1000)))
node _homogeneous_T_28 = asSInt(_homogeneous_T_27)
node _homogeneous_T_29 = eq(_homogeneous_T_28, asSInt(UInt<1>(0h0)))
node _homogeneous_T_30 = xor(mpu_physaddr, UInt<28>(0h8000000))
node _homogeneous_T_31 = cvt(_homogeneous_T_30)
node _homogeneous_T_32 = and(_homogeneous_T_31, asSInt(UInt<17>(0h10000)))
node _homogeneous_T_33 = asSInt(_homogeneous_T_32)
node _homogeneous_T_34 = eq(_homogeneous_T_33, asSInt(UInt<1>(0h0)))
node _homogeneous_T_35 = xor(mpu_physaddr, UInt<28>(0hc000000))
node _homogeneous_T_36 = cvt(_homogeneous_T_35)
node _homogeneous_T_37 = and(_homogeneous_T_36, asSInt(UInt<27>(0h4000000)))
node _homogeneous_T_38 = asSInt(_homogeneous_T_37)
node _homogeneous_T_39 = eq(_homogeneous_T_38, asSInt(UInt<1>(0h0)))
node _homogeneous_T_40 = xor(mpu_physaddr, UInt<29>(0h10020000))
node _homogeneous_T_41 = cvt(_homogeneous_T_40)
node _homogeneous_T_42 = and(_homogeneous_T_41, asSInt(UInt<13>(0h1000)))
node _homogeneous_T_43 = asSInt(_homogeneous_T_42)
node _homogeneous_T_44 = eq(_homogeneous_T_43, asSInt(UInt<1>(0h0)))
node _homogeneous_T_45 = xor(mpu_physaddr, UInt<32>(0h80000000))
node _homogeneous_T_46 = cvt(_homogeneous_T_45)
node _homogeneous_T_47 = and(_homogeneous_T_46, asSInt(UInt<29>(0h10000000)))
node _homogeneous_T_48 = asSInt(_homogeneous_T_47)
node _homogeneous_T_49 = eq(_homogeneous_T_48, asSInt(UInt<1>(0h0)))
node _homogeneous_T_50 = or(UInt<1>(0h0), _homogeneous_T_4)
node _homogeneous_T_51 = or(_homogeneous_T_50, _homogeneous_T_9)
node _homogeneous_T_52 = or(_homogeneous_T_51, _homogeneous_T_14)
node _homogeneous_T_53 = or(_homogeneous_T_52, _homogeneous_T_19)
node _homogeneous_T_54 = or(_homogeneous_T_53, _homogeneous_T_24)
node _homogeneous_T_55 = or(_homogeneous_T_54, _homogeneous_T_29)
node _homogeneous_T_56 = or(_homogeneous_T_55, _homogeneous_T_34)
node _homogeneous_T_57 = or(_homogeneous_T_56, _homogeneous_T_39)
node _homogeneous_T_58 = or(_homogeneous_T_57, _homogeneous_T_44)
node homogeneous = or(_homogeneous_T_58, _homogeneous_T_49)
node _homogeneous_T_59 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _homogeneous_T_60 = xor(mpu_physaddr, UInt<17>(0h10000))
node _homogeneous_T_61 = cvt(_homogeneous_T_60)
node _homogeneous_T_62 = and(_homogeneous_T_61, asSInt(UInt<33>(0h8a110000)))
node _homogeneous_T_63 = asSInt(_homogeneous_T_62)
node _homogeneous_T_64 = eq(_homogeneous_T_63, asSInt(UInt<1>(0h0)))
node _homogeneous_T_65 = or(UInt<1>(0h0), _homogeneous_T_64)
node _homogeneous_T_66 = eq(_homogeneous_T_65, UInt<1>(0h0))
node _homogeneous_T_67 = xor(mpu_physaddr, UInt<1>(0h0))
node _homogeneous_T_68 = cvt(_homogeneous_T_67)
node _homogeneous_T_69 = and(_homogeneous_T_68, asSInt(UInt<33>(0h9e113000)))
node _homogeneous_T_70 = asSInt(_homogeneous_T_69)
node _homogeneous_T_71 = eq(_homogeneous_T_70, asSInt(UInt<1>(0h0)))
node _homogeneous_T_72 = xor(mpu_physaddr, UInt<14>(0h3000))
node _homogeneous_T_73 = cvt(_homogeneous_T_72)
node _homogeneous_T_74 = and(_homogeneous_T_73, asSInt(UInt<33>(0h9e113000)))
node _homogeneous_T_75 = asSInt(_homogeneous_T_74)
node _homogeneous_T_76 = eq(_homogeneous_T_75, asSInt(UInt<1>(0h0)))
node _homogeneous_T_77 = xor(mpu_physaddr, UInt<17>(0h10000))
node _homogeneous_T_78 = cvt(_homogeneous_T_77)
node _homogeneous_T_79 = and(_homogeneous_T_78, asSInt(UInt<33>(0h9e110000)))
node _homogeneous_T_80 = asSInt(_homogeneous_T_79)
node _homogeneous_T_81 = eq(_homogeneous_T_80, asSInt(UInt<1>(0h0)))
node _homogeneous_T_82 = xor(mpu_physaddr, UInt<28>(0h8000000))
node _homogeneous_T_83 = cvt(_homogeneous_T_82)
node _homogeneous_T_84 = and(_homogeneous_T_83, asSInt(UInt<33>(0h9e110000)))
node _homogeneous_T_85 = asSInt(_homogeneous_T_84)
node _homogeneous_T_86 = eq(_homogeneous_T_85, asSInt(UInt<1>(0h0)))
node _homogeneous_T_87 = xor(mpu_physaddr, UInt<32>(0h80000000))
node _homogeneous_T_88 = cvt(_homogeneous_T_87)
node _homogeneous_T_89 = and(_homogeneous_T_88, asSInt(UInt<33>(0h90000000)))
node _homogeneous_T_90 = asSInt(_homogeneous_T_89)
node _homogeneous_T_91 = eq(_homogeneous_T_90, asSInt(UInt<1>(0h0)))
node _homogeneous_T_92 = or(UInt<1>(0h0), _homogeneous_T_71)
node _homogeneous_T_93 = or(_homogeneous_T_92, _homogeneous_T_76)
node _homogeneous_T_94 = or(_homogeneous_T_93, _homogeneous_T_81)
node _homogeneous_T_95 = or(_homogeneous_T_94, _homogeneous_T_86)
node _homogeneous_T_96 = or(_homogeneous_T_95, _homogeneous_T_91)
node _homogeneous_T_97 = xor(mpu_physaddr, UInt<28>(0h8000000))
node _homogeneous_T_98 = cvt(_homogeneous_T_97)
node _homogeneous_T_99 = and(_homogeneous_T_98, asSInt(UInt<33>(0h8e000000)))
node _homogeneous_T_100 = asSInt(_homogeneous_T_99)
node _homogeneous_T_101 = eq(_homogeneous_T_100, asSInt(UInt<1>(0h0)))
node _homogeneous_T_102 = xor(mpu_physaddr, UInt<32>(0h80000000))
node _homogeneous_T_103 = cvt(_homogeneous_T_102)
node _homogeneous_T_104 = and(_homogeneous_T_103, asSInt(UInt<33>(0h80000000)))
node _homogeneous_T_105 = asSInt(_homogeneous_T_104)
node _homogeneous_T_106 = eq(_homogeneous_T_105, asSInt(UInt<1>(0h0)))
node _homogeneous_T_107 = or(UInt<1>(0h0), _homogeneous_T_101)
node _homogeneous_T_108 = or(_homogeneous_T_107, _homogeneous_T_106)
node _homogeneous_T_109 = xor(mpu_physaddr, UInt<17>(0h10000))
node _homogeneous_T_110 = cvt(_homogeneous_T_109)
node _homogeneous_T_111 = and(_homogeneous_T_110, asSInt(UInt<33>(0h8a110000)))
node _homogeneous_T_112 = asSInt(_homogeneous_T_111)
node _homogeneous_T_113 = eq(_homogeneous_T_112, asSInt(UInt<1>(0h0)))
node _homogeneous_T_114 = or(UInt<1>(0h0), _homogeneous_T_113)
node _homogeneous_T_115 = eq(_homogeneous_T_114, UInt<1>(0h0))
node _homogeneous_T_116 = xor(mpu_physaddr, UInt<17>(0h10000))
node _homogeneous_T_117 = cvt(_homogeneous_T_116)
node _homogeneous_T_118 = and(_homogeneous_T_117, asSInt(UInt<33>(0h8a110000)))
node _homogeneous_T_119 = asSInt(_homogeneous_T_118)
node _homogeneous_T_120 = eq(_homogeneous_T_119, asSInt(UInt<1>(0h0)))
node _homogeneous_T_121 = or(UInt<1>(0h0), _homogeneous_T_120)
node _homogeneous_T_122 = eq(_homogeneous_T_121, UInt<1>(0h0))
node _deny_access_to_debug_T = leq(mpu_priv, UInt<2>(0h3))
node _deny_access_to_debug_T_1 = xor(mpu_physaddr, UInt<1>(0h0))
node _deny_access_to_debug_T_2 = cvt(_deny_access_to_debug_T_1)
node _deny_access_to_debug_T_3 = and(_deny_access_to_debug_T_2, asSInt(UInt<13>(0h1000)))
node _deny_access_to_debug_T_4 = asSInt(_deny_access_to_debug_T_3)
node _deny_access_to_debug_T_5 = eq(_deny_access_to_debug_T_4, asSInt(UInt<1>(0h0)))
node deny_access_to_debug = and(_deny_access_to_debug_T, _deny_access_to_debug_T_5)
node _prot_r_T = eq(deny_access_to_debug, UInt<1>(0h0))
node _prot_r_T_1 = and(pma.io.resp.r, _prot_r_T)
node prot_r = and(_prot_r_T_1, pmp.io.r)
node _prot_w_T = eq(deny_access_to_debug, UInt<1>(0h0))
node _prot_w_T_1 = and(pma.io.resp.w, _prot_w_T)
node prot_w = and(_prot_w_T_1, pmp.io.w)
node _prot_x_T = eq(deny_access_to_debug, UInt<1>(0h0))
node _prot_x_T_1 = and(pma.io.resp.x, _prot_x_T)
node prot_x = and(_prot_x_T_1, pmp.io.x)
node _sector_hits_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1])
node _sector_hits_T_1 = or(_sector_hits_T, sectored_entries[0][0].valid[2])
node _sector_hits_T_2 = or(_sector_hits_T_1, sectored_entries[0][0].valid[3])
node _sector_hits_T_3 = xor(sectored_entries[0][0].tag_vpn, vpn)
node _sector_hits_T_4 = shr(_sector_hits_T_3, 2)
node _sector_hits_T_5 = eq(_sector_hits_T_4, UInt<1>(0h0))
node _sector_hits_T_6 = eq(sectored_entries[0][0].tag_v, priv_v)
node _sector_hits_T_7 = and(_sector_hits_T_5, _sector_hits_T_6)
node sector_hits_0 = and(_sector_hits_T_2, _sector_hits_T_7)
node _sector_hits_T_8 = or(sectored_entries[0][1].valid[0], sectored_entries[0][1].valid[1])
node _sector_hits_T_9 = or(_sector_hits_T_8, sectored_entries[0][1].valid[2])
node _sector_hits_T_10 = or(_sector_hits_T_9, sectored_entries[0][1].valid[3])
node _sector_hits_T_11 = xor(sectored_entries[0][1].tag_vpn, vpn)
node _sector_hits_T_12 = shr(_sector_hits_T_11, 2)
node _sector_hits_T_13 = eq(_sector_hits_T_12, UInt<1>(0h0))
node _sector_hits_T_14 = eq(sectored_entries[0][1].tag_v, priv_v)
node _sector_hits_T_15 = and(_sector_hits_T_13, _sector_hits_T_14)
node sector_hits_1 = and(_sector_hits_T_10, _sector_hits_T_15)
node _sector_hits_T_16 = or(sectored_entries[0][2].valid[0], sectored_entries[0][2].valid[1])
node _sector_hits_T_17 = or(_sector_hits_T_16, sectored_entries[0][2].valid[2])
node _sector_hits_T_18 = or(_sector_hits_T_17, sectored_entries[0][2].valid[3])
node _sector_hits_T_19 = xor(sectored_entries[0][2].tag_vpn, vpn)
node _sector_hits_T_20 = shr(_sector_hits_T_19, 2)
node _sector_hits_T_21 = eq(_sector_hits_T_20, UInt<1>(0h0))
node _sector_hits_T_22 = eq(sectored_entries[0][2].tag_v, priv_v)
node _sector_hits_T_23 = and(_sector_hits_T_21, _sector_hits_T_22)
node sector_hits_2 = and(_sector_hits_T_18, _sector_hits_T_23)
node _sector_hits_T_24 = or(sectored_entries[0][3].valid[0], sectored_entries[0][3].valid[1])
node _sector_hits_T_25 = or(_sector_hits_T_24, sectored_entries[0][3].valid[2])
node _sector_hits_T_26 = or(_sector_hits_T_25, sectored_entries[0][3].valid[3])
node _sector_hits_T_27 = xor(sectored_entries[0][3].tag_vpn, vpn)
node _sector_hits_T_28 = shr(_sector_hits_T_27, 2)
node _sector_hits_T_29 = eq(_sector_hits_T_28, UInt<1>(0h0))
node _sector_hits_T_30 = eq(sectored_entries[0][3].tag_v, priv_v)
node _sector_hits_T_31 = and(_sector_hits_T_29, _sector_hits_T_30)
node sector_hits_3 = and(_sector_hits_T_26, _sector_hits_T_31)
node _sector_hits_T_32 = or(sectored_entries[0][4].valid[0], sectored_entries[0][4].valid[1])
node _sector_hits_T_33 = or(_sector_hits_T_32, sectored_entries[0][4].valid[2])
node _sector_hits_T_34 = or(_sector_hits_T_33, sectored_entries[0][4].valid[3])
node _sector_hits_T_35 = xor(sectored_entries[0][4].tag_vpn, vpn)
node _sector_hits_T_36 = shr(_sector_hits_T_35, 2)
node _sector_hits_T_37 = eq(_sector_hits_T_36, UInt<1>(0h0))
node _sector_hits_T_38 = eq(sectored_entries[0][4].tag_v, priv_v)
node _sector_hits_T_39 = and(_sector_hits_T_37, _sector_hits_T_38)
node sector_hits_4 = and(_sector_hits_T_34, _sector_hits_T_39)
node _sector_hits_T_40 = or(sectored_entries[0][5].valid[0], sectored_entries[0][5].valid[1])
node _sector_hits_T_41 = or(_sector_hits_T_40, sectored_entries[0][5].valid[2])
node _sector_hits_T_42 = or(_sector_hits_T_41, sectored_entries[0][5].valid[3])
node _sector_hits_T_43 = xor(sectored_entries[0][5].tag_vpn, vpn)
node _sector_hits_T_44 = shr(_sector_hits_T_43, 2)
node _sector_hits_T_45 = eq(_sector_hits_T_44, UInt<1>(0h0))
node _sector_hits_T_46 = eq(sectored_entries[0][5].tag_v, priv_v)
node _sector_hits_T_47 = and(_sector_hits_T_45, _sector_hits_T_46)
node sector_hits_5 = and(_sector_hits_T_42, _sector_hits_T_47)
node _sector_hits_T_48 = or(sectored_entries[0][6].valid[0], sectored_entries[0][6].valid[1])
node _sector_hits_T_49 = or(_sector_hits_T_48, sectored_entries[0][6].valid[2])
node _sector_hits_T_50 = or(_sector_hits_T_49, sectored_entries[0][6].valid[3])
node _sector_hits_T_51 = xor(sectored_entries[0][6].tag_vpn, vpn)
node _sector_hits_T_52 = shr(_sector_hits_T_51, 2)
node _sector_hits_T_53 = eq(_sector_hits_T_52, UInt<1>(0h0))
node _sector_hits_T_54 = eq(sectored_entries[0][6].tag_v, priv_v)
node _sector_hits_T_55 = and(_sector_hits_T_53, _sector_hits_T_54)
node sector_hits_6 = and(_sector_hits_T_50, _sector_hits_T_55)
node _sector_hits_T_56 = or(sectored_entries[0][7].valid[0], sectored_entries[0][7].valid[1])
node _sector_hits_T_57 = or(_sector_hits_T_56, sectored_entries[0][7].valid[2])
node _sector_hits_T_58 = or(_sector_hits_T_57, sectored_entries[0][7].valid[3])
node _sector_hits_T_59 = xor(sectored_entries[0][7].tag_vpn, vpn)
node _sector_hits_T_60 = shr(_sector_hits_T_59, 2)
node _sector_hits_T_61 = eq(_sector_hits_T_60, UInt<1>(0h0))
node _sector_hits_T_62 = eq(sectored_entries[0][7].tag_v, priv_v)
node _sector_hits_T_63 = and(_sector_hits_T_61, _sector_hits_T_62)
node sector_hits_7 = and(_sector_hits_T_58, _sector_hits_T_63)
node _superpage_hits_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v)
node superpage_hits_tagMatch = and(superpage_entries[0].valid[0], _superpage_hits_tagMatch_T)
node _superpage_hits_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0))
node superpage_hits_ignore = or(_superpage_hits_ignore_T, UInt<1>(0h0))
node _superpage_hits_T = xor(superpage_entries[0].tag_vpn, vpn)
node _superpage_hits_T_1 = bits(_superpage_hits_T, 26, 18)
node _superpage_hits_T_2 = eq(_superpage_hits_T_1, UInt<1>(0h0))
node _superpage_hits_T_3 = or(superpage_hits_ignore, _superpage_hits_T_2)
node _superpage_hits_T_4 = and(superpage_hits_tagMatch, _superpage_hits_T_3)
node _superpage_hits_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1))
node superpage_hits_ignore_1 = or(_superpage_hits_ignore_T_1, UInt<1>(0h0))
node _superpage_hits_T_5 = xor(superpage_entries[0].tag_vpn, vpn)
node _superpage_hits_T_6 = bits(_superpage_hits_T_5, 17, 9)
node _superpage_hits_T_7 = eq(_superpage_hits_T_6, UInt<1>(0h0))
node _superpage_hits_T_8 = or(superpage_hits_ignore_1, _superpage_hits_T_7)
node _superpage_hits_T_9 = and(_superpage_hits_T_4, _superpage_hits_T_8)
node _superpage_hits_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2))
node superpage_hits_ignore_2 = or(_superpage_hits_ignore_T_2, UInt<1>(0h1))
node _superpage_hits_T_10 = xor(superpage_entries[0].tag_vpn, vpn)
node _superpage_hits_T_11 = bits(_superpage_hits_T_10, 8, 0)
node _superpage_hits_T_12 = eq(_superpage_hits_T_11, UInt<1>(0h0))
node _superpage_hits_T_13 = or(superpage_hits_ignore_2, _superpage_hits_T_12)
node superpage_hits_0 = and(_superpage_hits_T_9, _superpage_hits_T_13)
node _superpage_hits_tagMatch_T_1 = eq(superpage_entries[1].tag_v, priv_v)
node superpage_hits_tagMatch_1 = and(superpage_entries[1].valid[0], _superpage_hits_tagMatch_T_1)
node _superpage_hits_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0))
node superpage_hits_ignore_3 = or(_superpage_hits_ignore_T_3, UInt<1>(0h0))
node _superpage_hits_T_14 = xor(superpage_entries[1].tag_vpn, vpn)
node _superpage_hits_T_15 = bits(_superpage_hits_T_14, 26, 18)
node _superpage_hits_T_16 = eq(_superpage_hits_T_15, UInt<1>(0h0))
node _superpage_hits_T_17 = or(superpage_hits_ignore_3, _superpage_hits_T_16)
node _superpage_hits_T_18 = and(superpage_hits_tagMatch_1, _superpage_hits_T_17)
node _superpage_hits_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1))
node superpage_hits_ignore_4 = or(_superpage_hits_ignore_T_4, UInt<1>(0h0))
node _superpage_hits_T_19 = xor(superpage_entries[1].tag_vpn, vpn)
node _superpage_hits_T_20 = bits(_superpage_hits_T_19, 17, 9)
node _superpage_hits_T_21 = eq(_superpage_hits_T_20, UInt<1>(0h0))
node _superpage_hits_T_22 = or(superpage_hits_ignore_4, _superpage_hits_T_21)
node _superpage_hits_T_23 = and(_superpage_hits_T_18, _superpage_hits_T_22)
node _superpage_hits_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2))
node superpage_hits_ignore_5 = or(_superpage_hits_ignore_T_5, UInt<1>(0h1))
node _superpage_hits_T_24 = xor(superpage_entries[1].tag_vpn, vpn)
node _superpage_hits_T_25 = bits(_superpage_hits_T_24, 8, 0)
node _superpage_hits_T_26 = eq(_superpage_hits_T_25, UInt<1>(0h0))
node _superpage_hits_T_27 = or(superpage_hits_ignore_5, _superpage_hits_T_26)
node superpage_hits_1 = and(_superpage_hits_T_23, _superpage_hits_T_27)
node _superpage_hits_tagMatch_T_2 = eq(superpage_entries[2].tag_v, priv_v)
node superpage_hits_tagMatch_2 = and(superpage_entries[2].valid[0], _superpage_hits_tagMatch_T_2)
node _superpage_hits_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0))
node superpage_hits_ignore_6 = or(_superpage_hits_ignore_T_6, UInt<1>(0h0))
node _superpage_hits_T_28 = xor(superpage_entries[2].tag_vpn, vpn)
node _superpage_hits_T_29 = bits(_superpage_hits_T_28, 26, 18)
node _superpage_hits_T_30 = eq(_superpage_hits_T_29, UInt<1>(0h0))
node _superpage_hits_T_31 = or(superpage_hits_ignore_6, _superpage_hits_T_30)
node _superpage_hits_T_32 = and(superpage_hits_tagMatch_2, _superpage_hits_T_31)
node _superpage_hits_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1))
node superpage_hits_ignore_7 = or(_superpage_hits_ignore_T_7, UInt<1>(0h0))
node _superpage_hits_T_33 = xor(superpage_entries[2].tag_vpn, vpn)
node _superpage_hits_T_34 = bits(_superpage_hits_T_33, 17, 9)
node _superpage_hits_T_35 = eq(_superpage_hits_T_34, UInt<1>(0h0))
node _superpage_hits_T_36 = or(superpage_hits_ignore_7, _superpage_hits_T_35)
node _superpage_hits_T_37 = and(_superpage_hits_T_32, _superpage_hits_T_36)
node _superpage_hits_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2))
node superpage_hits_ignore_8 = or(_superpage_hits_ignore_T_8, UInt<1>(0h1))
node _superpage_hits_T_38 = xor(superpage_entries[2].tag_vpn, vpn)
node _superpage_hits_T_39 = bits(_superpage_hits_T_38, 8, 0)
node _superpage_hits_T_40 = eq(_superpage_hits_T_39, UInt<1>(0h0))
node _superpage_hits_T_41 = or(superpage_hits_ignore_8, _superpage_hits_T_40)
node superpage_hits_2 = and(_superpage_hits_T_37, _superpage_hits_T_41)
node _superpage_hits_tagMatch_T_3 = eq(superpage_entries[3].tag_v, priv_v)
node superpage_hits_tagMatch_3 = and(superpage_entries[3].valid[0], _superpage_hits_tagMatch_T_3)
node _superpage_hits_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0))
node superpage_hits_ignore_9 = or(_superpage_hits_ignore_T_9, UInt<1>(0h0))
node _superpage_hits_T_42 = xor(superpage_entries[3].tag_vpn, vpn)
node _superpage_hits_T_43 = bits(_superpage_hits_T_42, 26, 18)
node _superpage_hits_T_44 = eq(_superpage_hits_T_43, UInt<1>(0h0))
node _superpage_hits_T_45 = or(superpage_hits_ignore_9, _superpage_hits_T_44)
node _superpage_hits_T_46 = and(superpage_hits_tagMatch_3, _superpage_hits_T_45)
node _superpage_hits_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1))
node superpage_hits_ignore_10 = or(_superpage_hits_ignore_T_10, UInt<1>(0h0))
node _superpage_hits_T_47 = xor(superpage_entries[3].tag_vpn, vpn)
node _superpage_hits_T_48 = bits(_superpage_hits_T_47, 17, 9)
node _superpage_hits_T_49 = eq(_superpage_hits_T_48, UInt<1>(0h0))
node _superpage_hits_T_50 = or(superpage_hits_ignore_10, _superpage_hits_T_49)
node _superpage_hits_T_51 = and(_superpage_hits_T_46, _superpage_hits_T_50)
node _superpage_hits_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2))
node superpage_hits_ignore_11 = or(_superpage_hits_ignore_T_11, UInt<1>(0h1))
node _superpage_hits_T_52 = xor(superpage_entries[3].tag_vpn, vpn)
node _superpage_hits_T_53 = bits(_superpage_hits_T_52, 8, 0)
node _superpage_hits_T_54 = eq(_superpage_hits_T_53, UInt<1>(0h0))
node _superpage_hits_T_55 = or(superpage_hits_ignore_11, _superpage_hits_T_54)
node superpage_hits_3 = and(_superpage_hits_T_51, _superpage_hits_T_55)
node hitsVec_idx = bits(vpn, 1, 0)
node _hitsVec_T = xor(sectored_entries[0][0].tag_vpn, vpn)
node _hitsVec_T_1 = shr(_hitsVec_T, 2)
node _hitsVec_T_2 = eq(_hitsVec_T_1, UInt<1>(0h0))
node _hitsVec_T_3 = eq(sectored_entries[0][0].tag_v, priv_v)
node _hitsVec_T_4 = and(_hitsVec_T_2, _hitsVec_T_3)
node _hitsVec_T_5 = and(sectored_entries[0][0].valid[hitsVec_idx], _hitsVec_T_4)
node hitsVec_0 = and(vm_enabled, _hitsVec_T_5)
node hitsVec_idx_1 = bits(vpn, 1, 0)
node _hitsVec_T_6 = xor(sectored_entries[0][1].tag_vpn, vpn)
node _hitsVec_T_7 = shr(_hitsVec_T_6, 2)
node _hitsVec_T_8 = eq(_hitsVec_T_7, UInt<1>(0h0))
node _hitsVec_T_9 = eq(sectored_entries[0][1].tag_v, priv_v)
node _hitsVec_T_10 = and(_hitsVec_T_8, _hitsVec_T_9)
node _hitsVec_T_11 = and(sectored_entries[0][1].valid[hitsVec_idx_1], _hitsVec_T_10)
node hitsVec_1 = and(vm_enabled, _hitsVec_T_11)
node hitsVec_idx_2 = bits(vpn, 1, 0)
node _hitsVec_T_12 = xor(sectored_entries[0][2].tag_vpn, vpn)
node _hitsVec_T_13 = shr(_hitsVec_T_12, 2)
node _hitsVec_T_14 = eq(_hitsVec_T_13, UInt<1>(0h0))
node _hitsVec_T_15 = eq(sectored_entries[0][2].tag_v, priv_v)
node _hitsVec_T_16 = and(_hitsVec_T_14, _hitsVec_T_15)
node _hitsVec_T_17 = and(sectored_entries[0][2].valid[hitsVec_idx_2], _hitsVec_T_16)
node hitsVec_2 = and(vm_enabled, _hitsVec_T_17)
node hitsVec_idx_3 = bits(vpn, 1, 0)
node _hitsVec_T_18 = xor(sectored_entries[0][3].tag_vpn, vpn)
node _hitsVec_T_19 = shr(_hitsVec_T_18, 2)
node _hitsVec_T_20 = eq(_hitsVec_T_19, UInt<1>(0h0))
node _hitsVec_T_21 = eq(sectored_entries[0][3].tag_v, priv_v)
node _hitsVec_T_22 = and(_hitsVec_T_20, _hitsVec_T_21)
node _hitsVec_T_23 = and(sectored_entries[0][3].valid[hitsVec_idx_3], _hitsVec_T_22)
node hitsVec_3 = and(vm_enabled, _hitsVec_T_23)
node hitsVec_idx_4 = bits(vpn, 1, 0)
node _hitsVec_T_24 = xor(sectored_entries[0][4].tag_vpn, vpn)
node _hitsVec_T_25 = shr(_hitsVec_T_24, 2)
node _hitsVec_T_26 = eq(_hitsVec_T_25, UInt<1>(0h0))
node _hitsVec_T_27 = eq(sectored_entries[0][4].tag_v, priv_v)
node _hitsVec_T_28 = and(_hitsVec_T_26, _hitsVec_T_27)
node _hitsVec_T_29 = and(sectored_entries[0][4].valid[hitsVec_idx_4], _hitsVec_T_28)
node hitsVec_4 = and(vm_enabled, _hitsVec_T_29)
node hitsVec_idx_5 = bits(vpn, 1, 0)
node _hitsVec_T_30 = xor(sectored_entries[0][5].tag_vpn, vpn)
node _hitsVec_T_31 = shr(_hitsVec_T_30, 2)
node _hitsVec_T_32 = eq(_hitsVec_T_31, UInt<1>(0h0))
node _hitsVec_T_33 = eq(sectored_entries[0][5].tag_v, priv_v)
node _hitsVec_T_34 = and(_hitsVec_T_32, _hitsVec_T_33)
node _hitsVec_T_35 = and(sectored_entries[0][5].valid[hitsVec_idx_5], _hitsVec_T_34)
node hitsVec_5 = and(vm_enabled, _hitsVec_T_35)
node hitsVec_idx_6 = bits(vpn, 1, 0)
node _hitsVec_T_36 = xor(sectored_entries[0][6].tag_vpn, vpn)
node _hitsVec_T_37 = shr(_hitsVec_T_36, 2)
node _hitsVec_T_38 = eq(_hitsVec_T_37, UInt<1>(0h0))
node _hitsVec_T_39 = eq(sectored_entries[0][6].tag_v, priv_v)
node _hitsVec_T_40 = and(_hitsVec_T_38, _hitsVec_T_39)
node _hitsVec_T_41 = and(sectored_entries[0][6].valid[hitsVec_idx_6], _hitsVec_T_40)
node hitsVec_6 = and(vm_enabled, _hitsVec_T_41)
node hitsVec_idx_7 = bits(vpn, 1, 0)
node _hitsVec_T_42 = xor(sectored_entries[0][7].tag_vpn, vpn)
node _hitsVec_T_43 = shr(_hitsVec_T_42, 2)
node _hitsVec_T_44 = eq(_hitsVec_T_43, UInt<1>(0h0))
node _hitsVec_T_45 = eq(sectored_entries[0][7].tag_v, priv_v)
node _hitsVec_T_46 = and(_hitsVec_T_44, _hitsVec_T_45)
node _hitsVec_T_47 = and(sectored_entries[0][7].valid[hitsVec_idx_7], _hitsVec_T_46)
node hitsVec_7 = and(vm_enabled, _hitsVec_T_47)
node _hitsVec_tagMatch_T = eq(superpage_entries[0].tag_v, priv_v)
node hitsVec_tagMatch = and(superpage_entries[0].valid[0], _hitsVec_tagMatch_T)
node _hitsVec_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0))
node hitsVec_ignore = or(_hitsVec_ignore_T, UInt<1>(0h0))
node _hitsVec_T_48 = xor(superpage_entries[0].tag_vpn, vpn)
node _hitsVec_T_49 = bits(_hitsVec_T_48, 26, 18)
node _hitsVec_T_50 = eq(_hitsVec_T_49, UInt<1>(0h0))
node _hitsVec_T_51 = or(hitsVec_ignore, _hitsVec_T_50)
node _hitsVec_T_52 = and(hitsVec_tagMatch, _hitsVec_T_51)
node _hitsVec_ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1))
node hitsVec_ignore_1 = or(_hitsVec_ignore_T_1, UInt<1>(0h0))
node _hitsVec_T_53 = xor(superpage_entries[0].tag_vpn, vpn)
node _hitsVec_T_54 = bits(_hitsVec_T_53, 17, 9)
node _hitsVec_T_55 = eq(_hitsVec_T_54, UInt<1>(0h0))
node _hitsVec_T_56 = or(hitsVec_ignore_1, _hitsVec_T_55)
node _hitsVec_T_57 = and(_hitsVec_T_52, _hitsVec_T_56)
node _hitsVec_ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2))
node hitsVec_ignore_2 = or(_hitsVec_ignore_T_2, UInt<1>(0h1))
node _hitsVec_T_58 = xor(superpage_entries[0].tag_vpn, vpn)
node _hitsVec_T_59 = bits(_hitsVec_T_58, 8, 0)
node _hitsVec_T_60 = eq(_hitsVec_T_59, UInt<1>(0h0))
node _hitsVec_T_61 = or(hitsVec_ignore_2, _hitsVec_T_60)
node _hitsVec_T_62 = and(_hitsVec_T_57, _hitsVec_T_61)
node hitsVec_8 = and(vm_enabled, _hitsVec_T_62)
node _hitsVec_tagMatch_T_1 = eq(superpage_entries[1].tag_v, priv_v)
node hitsVec_tagMatch_1 = and(superpage_entries[1].valid[0], _hitsVec_tagMatch_T_1)
node _hitsVec_ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0))
node hitsVec_ignore_3 = or(_hitsVec_ignore_T_3, UInt<1>(0h0))
node _hitsVec_T_63 = xor(superpage_entries[1].tag_vpn, vpn)
node _hitsVec_T_64 = bits(_hitsVec_T_63, 26, 18)
node _hitsVec_T_65 = eq(_hitsVec_T_64, UInt<1>(0h0))
node _hitsVec_T_66 = or(hitsVec_ignore_3, _hitsVec_T_65)
node _hitsVec_T_67 = and(hitsVec_tagMatch_1, _hitsVec_T_66)
node _hitsVec_ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1))
node hitsVec_ignore_4 = or(_hitsVec_ignore_T_4, UInt<1>(0h0))
node _hitsVec_T_68 = xor(superpage_entries[1].tag_vpn, vpn)
node _hitsVec_T_69 = bits(_hitsVec_T_68, 17, 9)
node _hitsVec_T_70 = eq(_hitsVec_T_69, UInt<1>(0h0))
node _hitsVec_T_71 = or(hitsVec_ignore_4, _hitsVec_T_70)
node _hitsVec_T_72 = and(_hitsVec_T_67, _hitsVec_T_71)
node _hitsVec_ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2))
node hitsVec_ignore_5 = or(_hitsVec_ignore_T_5, UInt<1>(0h1))
node _hitsVec_T_73 = xor(superpage_entries[1].tag_vpn, vpn)
node _hitsVec_T_74 = bits(_hitsVec_T_73, 8, 0)
node _hitsVec_T_75 = eq(_hitsVec_T_74, UInt<1>(0h0))
node _hitsVec_T_76 = or(hitsVec_ignore_5, _hitsVec_T_75)
node _hitsVec_T_77 = and(_hitsVec_T_72, _hitsVec_T_76)
node hitsVec_9 = and(vm_enabled, _hitsVec_T_77)
node _hitsVec_tagMatch_T_2 = eq(superpage_entries[2].tag_v, priv_v)
node hitsVec_tagMatch_2 = and(superpage_entries[2].valid[0], _hitsVec_tagMatch_T_2)
node _hitsVec_ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0))
node hitsVec_ignore_6 = or(_hitsVec_ignore_T_6, UInt<1>(0h0))
node _hitsVec_T_78 = xor(superpage_entries[2].tag_vpn, vpn)
node _hitsVec_T_79 = bits(_hitsVec_T_78, 26, 18)
node _hitsVec_T_80 = eq(_hitsVec_T_79, UInt<1>(0h0))
node _hitsVec_T_81 = or(hitsVec_ignore_6, _hitsVec_T_80)
node _hitsVec_T_82 = and(hitsVec_tagMatch_2, _hitsVec_T_81)
node _hitsVec_ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1))
node hitsVec_ignore_7 = or(_hitsVec_ignore_T_7, UInt<1>(0h0))
node _hitsVec_T_83 = xor(superpage_entries[2].tag_vpn, vpn)
node _hitsVec_T_84 = bits(_hitsVec_T_83, 17, 9)
node _hitsVec_T_85 = eq(_hitsVec_T_84, UInt<1>(0h0))
node _hitsVec_T_86 = or(hitsVec_ignore_7, _hitsVec_T_85)
node _hitsVec_T_87 = and(_hitsVec_T_82, _hitsVec_T_86)
node _hitsVec_ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2))
node hitsVec_ignore_8 = or(_hitsVec_ignore_T_8, UInt<1>(0h1))
node _hitsVec_T_88 = xor(superpage_entries[2].tag_vpn, vpn)
node _hitsVec_T_89 = bits(_hitsVec_T_88, 8, 0)
node _hitsVec_T_90 = eq(_hitsVec_T_89, UInt<1>(0h0))
node _hitsVec_T_91 = or(hitsVec_ignore_8, _hitsVec_T_90)
node _hitsVec_T_92 = and(_hitsVec_T_87, _hitsVec_T_91)
node hitsVec_10 = and(vm_enabled, _hitsVec_T_92)
node _hitsVec_tagMatch_T_3 = eq(superpage_entries[3].tag_v, priv_v)
node hitsVec_tagMatch_3 = and(superpage_entries[3].valid[0], _hitsVec_tagMatch_T_3)
node _hitsVec_ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0))
node hitsVec_ignore_9 = or(_hitsVec_ignore_T_9, UInt<1>(0h0))
node _hitsVec_T_93 = xor(superpage_entries[3].tag_vpn, vpn)
node _hitsVec_T_94 = bits(_hitsVec_T_93, 26, 18)
node _hitsVec_T_95 = eq(_hitsVec_T_94, UInt<1>(0h0))
node _hitsVec_T_96 = or(hitsVec_ignore_9, _hitsVec_T_95)
node _hitsVec_T_97 = and(hitsVec_tagMatch_3, _hitsVec_T_96)
node _hitsVec_ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1))
node hitsVec_ignore_10 = or(_hitsVec_ignore_T_10, UInt<1>(0h0))
node _hitsVec_T_98 = xor(superpage_entries[3].tag_vpn, vpn)
node _hitsVec_T_99 = bits(_hitsVec_T_98, 17, 9)
node _hitsVec_T_100 = eq(_hitsVec_T_99, UInt<1>(0h0))
node _hitsVec_T_101 = or(hitsVec_ignore_10, _hitsVec_T_100)
node _hitsVec_T_102 = and(_hitsVec_T_97, _hitsVec_T_101)
node _hitsVec_ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2))
node hitsVec_ignore_11 = or(_hitsVec_ignore_T_11, UInt<1>(0h1))
node _hitsVec_T_103 = xor(superpage_entries[3].tag_vpn, vpn)
node _hitsVec_T_104 = bits(_hitsVec_T_103, 8, 0)
node _hitsVec_T_105 = eq(_hitsVec_T_104, UInt<1>(0h0))
node _hitsVec_T_106 = or(hitsVec_ignore_11, _hitsVec_T_105)
node _hitsVec_T_107 = and(_hitsVec_T_102, _hitsVec_T_106)
node hitsVec_11 = and(vm_enabled, _hitsVec_T_107)
node _hitsVec_tagMatch_T_4 = eq(special_entry.tag_v, priv_v)
node hitsVec_tagMatch_4 = and(special_entry.valid[0], _hitsVec_tagMatch_T_4)
node _hitsVec_ignore_T_12 = lt(special_entry.level, UInt<1>(0h0))
node hitsVec_ignore_12 = or(_hitsVec_ignore_T_12, UInt<1>(0h0))
node _hitsVec_T_108 = xor(special_entry.tag_vpn, vpn)
node _hitsVec_T_109 = bits(_hitsVec_T_108, 26, 18)
node _hitsVec_T_110 = eq(_hitsVec_T_109, UInt<1>(0h0))
node _hitsVec_T_111 = or(hitsVec_ignore_12, _hitsVec_T_110)
node _hitsVec_T_112 = and(hitsVec_tagMatch_4, _hitsVec_T_111)
node _hitsVec_ignore_T_13 = lt(special_entry.level, UInt<1>(0h1))
node hitsVec_ignore_13 = or(_hitsVec_ignore_T_13, UInt<1>(0h0))
node _hitsVec_T_113 = xor(special_entry.tag_vpn, vpn)
node _hitsVec_T_114 = bits(_hitsVec_T_113, 17, 9)
node _hitsVec_T_115 = eq(_hitsVec_T_114, UInt<1>(0h0))
node _hitsVec_T_116 = or(hitsVec_ignore_13, _hitsVec_T_115)
node _hitsVec_T_117 = and(_hitsVec_T_112, _hitsVec_T_116)
node _hitsVec_ignore_T_14 = lt(special_entry.level, UInt<2>(0h2))
node hitsVec_ignore_14 = or(_hitsVec_ignore_T_14, UInt<1>(0h0))
node _hitsVec_T_118 = xor(special_entry.tag_vpn, vpn)
node _hitsVec_T_119 = bits(_hitsVec_T_118, 8, 0)
node _hitsVec_T_120 = eq(_hitsVec_T_119, UInt<1>(0h0))
node _hitsVec_T_121 = or(hitsVec_ignore_14, _hitsVec_T_120)
node _hitsVec_T_122 = and(_hitsVec_T_117, _hitsVec_T_121)
node hitsVec_12 = and(vm_enabled, _hitsVec_T_122)
node real_hits_lo_lo_hi = cat(hitsVec_2, hitsVec_1)
node real_hits_lo_lo = cat(real_hits_lo_lo_hi, hitsVec_0)
node real_hits_lo_hi_hi = cat(hitsVec_5, hitsVec_4)
node real_hits_lo_hi = cat(real_hits_lo_hi_hi, hitsVec_3)
node real_hits_lo = cat(real_hits_lo_hi, real_hits_lo_lo)
node real_hits_hi_lo_hi = cat(hitsVec_8, hitsVec_7)
node real_hits_hi_lo = cat(real_hits_hi_lo_hi, hitsVec_6)
node real_hits_hi_hi_lo = cat(hitsVec_10, hitsVec_9)
node real_hits_hi_hi_hi = cat(hitsVec_12, hitsVec_11)
node real_hits_hi_hi = cat(real_hits_hi_hi_hi, real_hits_hi_hi_lo)
node real_hits_hi = cat(real_hits_hi_hi, real_hits_hi_lo)
node real_hits = cat(real_hits_hi, real_hits_lo)
node _hits_T = eq(vm_enabled, UInt<1>(0h0))
node hits = cat(_hits_T, real_hits)
when do_refill :
node refill_v = or(r_vstage1_en, r_stage2_en)
wire newEntry : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
connect newEntry.ppn, io.ptw.resp.bits.pte.ppn
connect newEntry.c, cacheable
connect newEntry.u, io.ptw.resp.bits.pte.u
node _newEntry_g_T = and(io.ptw.resp.bits.pte.g, io.ptw.resp.bits.pte.v)
connect newEntry.g, _newEntry_g_T
connect newEntry.ae_ptw, io.ptw.resp.bits.ae_ptw
connect newEntry.ae_final, io.ptw.resp.bits.ae_final
node _newEntry_ae_stage2_T = and(io.ptw.resp.bits.ae_final, io.ptw.resp.bits.gpa_is_pte)
node _newEntry_ae_stage2_T_1 = and(_newEntry_ae_stage2_T, r_stage2_en)
connect newEntry.ae_stage2, _newEntry_ae_stage2_T_1
connect newEntry.pf, io.ptw.resp.bits.pf
connect newEntry.gf, io.ptw.resp.bits.gf
connect newEntry.hr, io.ptw.resp.bits.hr
connect newEntry.hw, io.ptw.resp.bits.hw
connect newEntry.hx, io.ptw.resp.bits.hx
node _newEntry_sr_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0))
node _newEntry_sr_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sr_T)
node _newEntry_sr_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sr_T_1)
node _newEntry_sr_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sr_T_2)
node _newEntry_sr_T_4 = and(_newEntry_sr_T_3, io.ptw.resp.bits.pte.a)
node _newEntry_sr_T_5 = and(_newEntry_sr_T_4, io.ptw.resp.bits.pte.r)
connect newEntry.sr, _newEntry_sr_T_5
node _newEntry_sw_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0))
node _newEntry_sw_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sw_T)
node _newEntry_sw_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sw_T_1)
node _newEntry_sw_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sw_T_2)
node _newEntry_sw_T_4 = and(_newEntry_sw_T_3, io.ptw.resp.bits.pte.a)
node _newEntry_sw_T_5 = and(_newEntry_sw_T_4, io.ptw.resp.bits.pte.w)
node _newEntry_sw_T_6 = and(_newEntry_sw_T_5, io.ptw.resp.bits.pte.d)
connect newEntry.sw, _newEntry_sw_T_6
node _newEntry_sx_T = eq(io.ptw.resp.bits.pte.w, UInt<1>(0h0))
node _newEntry_sx_T_1 = and(io.ptw.resp.bits.pte.x, _newEntry_sx_T)
node _newEntry_sx_T_2 = or(io.ptw.resp.bits.pte.r, _newEntry_sx_T_1)
node _newEntry_sx_T_3 = and(io.ptw.resp.bits.pte.v, _newEntry_sx_T_2)
node _newEntry_sx_T_4 = and(_newEntry_sx_T_3, io.ptw.resp.bits.pte.a)
node _newEntry_sx_T_5 = and(_newEntry_sx_T_4, io.ptw.resp.bits.pte.x)
connect newEntry.sx, _newEntry_sx_T_5
connect newEntry.pr, prot_r
connect newEntry.pw, prot_w
connect newEntry.px, prot_x
connect newEntry.ppp, pma.io.resp.pp
connect newEntry.pal, pma.io.resp.al
connect newEntry.paa, pma.io.resp.aa
connect newEntry.eff, pma.io.resp.eff
connect newEntry.fragmented_superpage, io.ptw.resp.bits.fragmented_superpage
node _T = eq(io.ptw.resp.bits.homogeneous, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
when _T_1 :
connect special_entry.tag_vpn, r_refill_tag
connect special_entry.tag_v, refill_v
node _special_entry_level_T = bits(io.ptw.resp.bits.level, 1, 0)
connect special_entry.level, _special_entry_level_T
connect special_entry.valid[0], UInt<1>(0h1)
node special_entry_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node special_entry_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node special_entry_data_0_lo_lo_hi = cat(special_entry_data_0_lo_lo_hi_hi, newEntry.eff)
node special_entry_data_0_lo_lo = cat(special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo)
node special_entry_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node special_entry_data_0_lo_hi_lo = cat(special_entry_data_0_lo_hi_lo_hi, newEntry.ppp)
node special_entry_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node special_entry_data_0_lo_hi_hi = cat(special_entry_data_0_lo_hi_hi_hi, newEntry.pw)
node special_entry_data_0_lo_hi = cat(special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo)
node special_entry_data_0_lo = cat(special_entry_data_0_lo_hi, special_entry_data_0_lo_lo)
node special_entry_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node special_entry_data_0_hi_lo_lo = cat(special_entry_data_0_hi_lo_lo_hi, newEntry.hw)
node special_entry_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node special_entry_data_0_hi_lo_hi = cat(special_entry_data_0_hi_lo_hi_hi, newEntry.sw)
node special_entry_data_0_hi_lo = cat(special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo)
node special_entry_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node special_entry_data_0_hi_hi_lo = cat(special_entry_data_0_hi_hi_lo_hi, newEntry.ae_stage2)
node special_entry_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node special_entry_data_0_hi_hi_hi = cat(special_entry_data_0_hi_hi_hi_hi, newEntry.g)
node special_entry_data_0_hi_hi = cat(special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo)
node special_entry_data_0_hi = cat(special_entry_data_0_hi_hi, special_entry_data_0_hi_lo)
node _special_entry_data_0_T = cat(special_entry_data_0_hi, special_entry_data_0_lo)
connect special_entry.data[0], _special_entry_data_0_T
else :
node _T_2 = lt(io.ptw.resp.bits.level, UInt<2>(0h2))
when _T_2 :
node _waddr_T = and(r_superpage_hit.valid, UInt<1>(0h0))
node waddr = mux(_waddr_T, r_superpage_hit.bits, r_superpage_repl_addr)
node _T_3 = eq(r_superpage_repl_addr, UInt<1>(0h0))
when _T_3 :
connect superpage_entries[0].tag_vpn, r_refill_tag
connect superpage_entries[0].tag_v, refill_v
node _superpage_entries_0_level_T = bits(io.ptw.resp.bits.level, 0, 0)
connect superpage_entries[0].level, _superpage_entries_0_level_T
connect superpage_entries[0].valid[0], UInt<1>(0h1)
node superpage_entries_0_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node superpage_entries_0_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node superpage_entries_0_data_0_lo_lo_hi = cat(superpage_entries_0_data_0_lo_lo_hi_hi, newEntry.eff)
node superpage_entries_0_data_0_lo_lo = cat(superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo)
node superpage_entries_0_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node superpage_entries_0_data_0_lo_hi_lo = cat(superpage_entries_0_data_0_lo_hi_lo_hi, newEntry.ppp)
node superpage_entries_0_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node superpage_entries_0_data_0_lo_hi_hi = cat(superpage_entries_0_data_0_lo_hi_hi_hi, newEntry.pw)
node superpage_entries_0_data_0_lo_hi = cat(superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo)
node superpage_entries_0_data_0_lo = cat(superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo)
node superpage_entries_0_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node superpage_entries_0_data_0_hi_lo_lo = cat(superpage_entries_0_data_0_hi_lo_lo_hi, newEntry.hw)
node superpage_entries_0_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node superpage_entries_0_data_0_hi_lo_hi = cat(superpage_entries_0_data_0_hi_lo_hi_hi, newEntry.sw)
node superpage_entries_0_data_0_hi_lo = cat(superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo)
node superpage_entries_0_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node superpage_entries_0_data_0_hi_hi_lo = cat(superpage_entries_0_data_0_hi_hi_lo_hi, newEntry.ae_stage2)
node superpage_entries_0_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node superpage_entries_0_data_0_hi_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi_hi, newEntry.g)
node superpage_entries_0_data_0_hi_hi = cat(superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo)
node superpage_entries_0_data_0_hi = cat(superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo)
node _superpage_entries_0_data_0_T = cat(superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo)
connect superpage_entries[0].data[0], _superpage_entries_0_data_0_T
when invalidate_refill :
connect superpage_entries[0].valid[0], UInt<1>(0h0)
node _T_4 = eq(r_superpage_repl_addr, UInt<1>(0h1))
when _T_4 :
connect superpage_entries[1].tag_vpn, r_refill_tag
connect superpage_entries[1].tag_v, refill_v
node _superpage_entries_1_level_T = bits(io.ptw.resp.bits.level, 0, 0)
connect superpage_entries[1].level, _superpage_entries_1_level_T
connect superpage_entries[1].valid[0], UInt<1>(0h1)
node superpage_entries_1_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node superpage_entries_1_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node superpage_entries_1_data_0_lo_lo_hi = cat(superpage_entries_1_data_0_lo_lo_hi_hi, newEntry.eff)
node superpage_entries_1_data_0_lo_lo = cat(superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo)
node superpage_entries_1_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node superpage_entries_1_data_0_lo_hi_lo = cat(superpage_entries_1_data_0_lo_hi_lo_hi, newEntry.ppp)
node superpage_entries_1_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node superpage_entries_1_data_0_lo_hi_hi = cat(superpage_entries_1_data_0_lo_hi_hi_hi, newEntry.pw)
node superpage_entries_1_data_0_lo_hi = cat(superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo)
node superpage_entries_1_data_0_lo = cat(superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo)
node superpage_entries_1_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node superpage_entries_1_data_0_hi_lo_lo = cat(superpage_entries_1_data_0_hi_lo_lo_hi, newEntry.hw)
node superpage_entries_1_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node superpage_entries_1_data_0_hi_lo_hi = cat(superpage_entries_1_data_0_hi_lo_hi_hi, newEntry.sw)
node superpage_entries_1_data_0_hi_lo = cat(superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo)
node superpage_entries_1_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node superpage_entries_1_data_0_hi_hi_lo = cat(superpage_entries_1_data_0_hi_hi_lo_hi, newEntry.ae_stage2)
node superpage_entries_1_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node superpage_entries_1_data_0_hi_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi_hi, newEntry.g)
node superpage_entries_1_data_0_hi_hi = cat(superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo)
node superpage_entries_1_data_0_hi = cat(superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo)
node _superpage_entries_1_data_0_T = cat(superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo)
connect superpage_entries[1].data[0], _superpage_entries_1_data_0_T
when invalidate_refill :
connect superpage_entries[1].valid[0], UInt<1>(0h0)
node _T_5 = eq(r_superpage_repl_addr, UInt<2>(0h2))
when _T_5 :
connect superpage_entries[2].tag_vpn, r_refill_tag
connect superpage_entries[2].tag_v, refill_v
node _superpage_entries_2_level_T = bits(io.ptw.resp.bits.level, 0, 0)
connect superpage_entries[2].level, _superpage_entries_2_level_T
connect superpage_entries[2].valid[0], UInt<1>(0h1)
node superpage_entries_2_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node superpage_entries_2_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node superpage_entries_2_data_0_lo_lo_hi = cat(superpage_entries_2_data_0_lo_lo_hi_hi, newEntry.eff)
node superpage_entries_2_data_0_lo_lo = cat(superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo)
node superpage_entries_2_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node superpage_entries_2_data_0_lo_hi_lo = cat(superpage_entries_2_data_0_lo_hi_lo_hi, newEntry.ppp)
node superpage_entries_2_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node superpage_entries_2_data_0_lo_hi_hi = cat(superpage_entries_2_data_0_lo_hi_hi_hi, newEntry.pw)
node superpage_entries_2_data_0_lo_hi = cat(superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo)
node superpage_entries_2_data_0_lo = cat(superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo)
node superpage_entries_2_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node superpage_entries_2_data_0_hi_lo_lo = cat(superpage_entries_2_data_0_hi_lo_lo_hi, newEntry.hw)
node superpage_entries_2_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node superpage_entries_2_data_0_hi_lo_hi = cat(superpage_entries_2_data_0_hi_lo_hi_hi, newEntry.sw)
node superpage_entries_2_data_0_hi_lo = cat(superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo)
node superpage_entries_2_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node superpage_entries_2_data_0_hi_hi_lo = cat(superpage_entries_2_data_0_hi_hi_lo_hi, newEntry.ae_stage2)
node superpage_entries_2_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node superpage_entries_2_data_0_hi_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi_hi, newEntry.g)
node superpage_entries_2_data_0_hi_hi = cat(superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo)
node superpage_entries_2_data_0_hi = cat(superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo)
node _superpage_entries_2_data_0_T = cat(superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo)
connect superpage_entries[2].data[0], _superpage_entries_2_data_0_T
when invalidate_refill :
connect superpage_entries[2].valid[0], UInt<1>(0h0)
node _T_6 = eq(r_superpage_repl_addr, UInt<2>(0h3))
when _T_6 :
connect superpage_entries[3].tag_vpn, r_refill_tag
connect superpage_entries[3].tag_v, refill_v
node _superpage_entries_3_level_T = bits(io.ptw.resp.bits.level, 0, 0)
connect superpage_entries[3].level, _superpage_entries_3_level_T
connect superpage_entries[3].valid[0], UInt<1>(0h1)
node superpage_entries_3_data_0_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node superpage_entries_3_data_0_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node superpage_entries_3_data_0_lo_lo_hi = cat(superpage_entries_3_data_0_lo_lo_hi_hi, newEntry.eff)
node superpage_entries_3_data_0_lo_lo = cat(superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo)
node superpage_entries_3_data_0_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node superpage_entries_3_data_0_lo_hi_lo = cat(superpage_entries_3_data_0_lo_hi_lo_hi, newEntry.ppp)
node superpage_entries_3_data_0_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node superpage_entries_3_data_0_lo_hi_hi = cat(superpage_entries_3_data_0_lo_hi_hi_hi, newEntry.pw)
node superpage_entries_3_data_0_lo_hi = cat(superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo)
node superpage_entries_3_data_0_lo = cat(superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo)
node superpage_entries_3_data_0_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node superpage_entries_3_data_0_hi_lo_lo = cat(superpage_entries_3_data_0_hi_lo_lo_hi, newEntry.hw)
node superpage_entries_3_data_0_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node superpage_entries_3_data_0_hi_lo_hi = cat(superpage_entries_3_data_0_hi_lo_hi_hi, newEntry.sw)
node superpage_entries_3_data_0_hi_lo = cat(superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo)
node superpage_entries_3_data_0_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node superpage_entries_3_data_0_hi_hi_lo = cat(superpage_entries_3_data_0_hi_hi_lo_hi, newEntry.ae_stage2)
node superpage_entries_3_data_0_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node superpage_entries_3_data_0_hi_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi_hi, newEntry.g)
node superpage_entries_3_data_0_hi_hi = cat(superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo)
node superpage_entries_3_data_0_hi = cat(superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo)
node _superpage_entries_3_data_0_T = cat(superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo)
connect superpage_entries[3].data[0], _superpage_entries_3_data_0_T
when invalidate_refill :
connect superpage_entries[3].valid[0], UInt<1>(0h0)
else :
node waddr_1 = mux(r_sectored_hit.valid, r_sectored_hit.bits, r_sectored_repl_addr)
node _T_7 = eq(waddr_1, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_8 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
connect sectored_entries[0][0].tag_vpn, r_refill_tag
connect sectored_entries[0][0].tag_v, refill_v
connect sectored_entries[0][0].level, UInt<2>(0h0)
node idx = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][0].valid[idx], UInt<1>(0h1)
node sectored_entries_0_0_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_0_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_0_data_lo_lo_hi = cat(sectored_entries_0_0_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_0_data_lo_lo = cat(sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo)
node sectored_entries_0_0_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_0_data_lo_hi_lo = cat(sectored_entries_0_0_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_0_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_0_data_lo_hi_hi = cat(sectored_entries_0_0_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_0_data_lo_hi = cat(sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo)
node sectored_entries_0_0_data_lo = cat(sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo)
node sectored_entries_0_0_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_0_data_hi_lo_lo = cat(sectored_entries_0_0_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_0_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_0_data_hi_lo_hi = cat(sectored_entries_0_0_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_0_data_hi_lo = cat(sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo)
node sectored_entries_0_0_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_0_data_hi_hi_lo = cat(sectored_entries_0_0_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_0_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_0_data_hi_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_0_data_hi_hi = cat(sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo)
node sectored_entries_0_0_data_hi = cat(sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo)
node _sectored_entries_0_0_data_T = cat(sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo)
connect sectored_entries[0][0].data[idx], _sectored_entries_0_0_data_T
when invalidate_refill :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
node _T_9 = eq(waddr_1, UInt<1>(0h1))
when _T_9 :
node _T_10 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_10 :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
connect sectored_entries[0][1].tag_vpn, r_refill_tag
connect sectored_entries[0][1].tag_v, refill_v
connect sectored_entries[0][1].level, UInt<2>(0h0)
node idx_1 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][1].valid[idx_1], UInt<1>(0h1)
node sectored_entries_0_1_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_1_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_1_data_lo_lo_hi = cat(sectored_entries_0_1_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_1_data_lo_lo = cat(sectored_entries_0_1_data_lo_lo_hi, sectored_entries_0_1_data_lo_lo_lo)
node sectored_entries_0_1_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_1_data_lo_hi_lo = cat(sectored_entries_0_1_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_1_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_1_data_lo_hi_hi = cat(sectored_entries_0_1_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_1_data_lo_hi = cat(sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo)
node sectored_entries_0_1_data_lo = cat(sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo)
node sectored_entries_0_1_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_1_data_hi_lo_lo = cat(sectored_entries_0_1_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_1_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_1_data_hi_lo_hi = cat(sectored_entries_0_1_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_1_data_hi_lo = cat(sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo)
node sectored_entries_0_1_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_1_data_hi_hi_lo = cat(sectored_entries_0_1_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_1_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_1_data_hi_hi_hi = cat(sectored_entries_0_1_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_1_data_hi_hi = cat(sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo)
node sectored_entries_0_1_data_hi = cat(sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo)
node _sectored_entries_0_1_data_T = cat(sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo)
connect sectored_entries[0][1].data[idx_1], _sectored_entries_0_1_data_T
when invalidate_refill :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
node _T_11 = eq(waddr_1, UInt<2>(0h2))
when _T_11 :
node _T_12 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_12 :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
connect sectored_entries[0][2].tag_vpn, r_refill_tag
connect sectored_entries[0][2].tag_v, refill_v
connect sectored_entries[0][2].level, UInt<2>(0h0)
node idx_2 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][2].valid[idx_2], UInt<1>(0h1)
node sectored_entries_0_2_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_2_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_2_data_lo_lo_hi = cat(sectored_entries_0_2_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_2_data_lo_lo = cat(sectored_entries_0_2_data_lo_lo_hi, sectored_entries_0_2_data_lo_lo_lo)
node sectored_entries_0_2_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_2_data_lo_hi_lo = cat(sectored_entries_0_2_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_2_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_2_data_lo_hi_hi = cat(sectored_entries_0_2_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_2_data_lo_hi = cat(sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo)
node sectored_entries_0_2_data_lo = cat(sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo)
node sectored_entries_0_2_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_2_data_hi_lo_lo = cat(sectored_entries_0_2_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_2_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_2_data_hi_lo_hi = cat(sectored_entries_0_2_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_2_data_hi_lo = cat(sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo)
node sectored_entries_0_2_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_2_data_hi_hi_lo = cat(sectored_entries_0_2_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_2_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_2_data_hi_hi_hi = cat(sectored_entries_0_2_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_2_data_hi_hi = cat(sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo)
node sectored_entries_0_2_data_hi = cat(sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo)
node _sectored_entries_0_2_data_T = cat(sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo)
connect sectored_entries[0][2].data[idx_2], _sectored_entries_0_2_data_T
when invalidate_refill :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
node _T_13 = eq(waddr_1, UInt<2>(0h3))
when _T_13 :
node _T_14 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_14 :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
connect sectored_entries[0][3].tag_vpn, r_refill_tag
connect sectored_entries[0][3].tag_v, refill_v
connect sectored_entries[0][3].level, UInt<2>(0h0)
node idx_3 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][3].valid[idx_3], UInt<1>(0h1)
node sectored_entries_0_3_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_3_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_3_data_lo_lo_hi = cat(sectored_entries_0_3_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_3_data_lo_lo = cat(sectored_entries_0_3_data_lo_lo_hi, sectored_entries_0_3_data_lo_lo_lo)
node sectored_entries_0_3_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_3_data_lo_hi_lo = cat(sectored_entries_0_3_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_3_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_3_data_lo_hi_hi = cat(sectored_entries_0_3_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_3_data_lo_hi = cat(sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo)
node sectored_entries_0_3_data_lo = cat(sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo)
node sectored_entries_0_3_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_3_data_hi_lo_lo = cat(sectored_entries_0_3_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_3_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_3_data_hi_lo_hi = cat(sectored_entries_0_3_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_3_data_hi_lo = cat(sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo)
node sectored_entries_0_3_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_3_data_hi_hi_lo = cat(sectored_entries_0_3_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_3_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_3_data_hi_hi_hi = cat(sectored_entries_0_3_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_3_data_hi_hi = cat(sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo)
node sectored_entries_0_3_data_hi = cat(sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo)
node _sectored_entries_0_3_data_T = cat(sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo)
connect sectored_entries[0][3].data[idx_3], _sectored_entries_0_3_data_T
when invalidate_refill :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
node _T_15 = eq(waddr_1, UInt<3>(0h4))
when _T_15 :
node _T_16 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_16 :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
connect sectored_entries[0][4].tag_vpn, r_refill_tag
connect sectored_entries[0][4].tag_v, refill_v
connect sectored_entries[0][4].level, UInt<2>(0h0)
node idx_4 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][4].valid[idx_4], UInt<1>(0h1)
node sectored_entries_0_4_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_4_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_4_data_lo_lo_hi = cat(sectored_entries_0_4_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_4_data_lo_lo = cat(sectored_entries_0_4_data_lo_lo_hi, sectored_entries_0_4_data_lo_lo_lo)
node sectored_entries_0_4_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_4_data_lo_hi_lo = cat(sectored_entries_0_4_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_4_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_4_data_lo_hi_hi = cat(sectored_entries_0_4_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_4_data_lo_hi = cat(sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo)
node sectored_entries_0_4_data_lo = cat(sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo)
node sectored_entries_0_4_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_4_data_hi_lo_lo = cat(sectored_entries_0_4_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_4_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_4_data_hi_lo_hi = cat(sectored_entries_0_4_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_4_data_hi_lo = cat(sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo)
node sectored_entries_0_4_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_4_data_hi_hi_lo = cat(sectored_entries_0_4_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_4_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_4_data_hi_hi_hi = cat(sectored_entries_0_4_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_4_data_hi_hi = cat(sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo)
node sectored_entries_0_4_data_hi = cat(sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo)
node _sectored_entries_0_4_data_T = cat(sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo)
connect sectored_entries[0][4].data[idx_4], _sectored_entries_0_4_data_T
when invalidate_refill :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
node _T_17 = eq(waddr_1, UInt<3>(0h5))
when _T_17 :
node _T_18 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_18 :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
connect sectored_entries[0][5].tag_vpn, r_refill_tag
connect sectored_entries[0][5].tag_v, refill_v
connect sectored_entries[0][5].level, UInt<2>(0h0)
node idx_5 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][5].valid[idx_5], UInt<1>(0h1)
node sectored_entries_0_5_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_5_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_5_data_lo_lo_hi = cat(sectored_entries_0_5_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_5_data_lo_lo = cat(sectored_entries_0_5_data_lo_lo_hi, sectored_entries_0_5_data_lo_lo_lo)
node sectored_entries_0_5_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_5_data_lo_hi_lo = cat(sectored_entries_0_5_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_5_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_5_data_lo_hi_hi = cat(sectored_entries_0_5_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_5_data_lo_hi = cat(sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo)
node sectored_entries_0_5_data_lo = cat(sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo)
node sectored_entries_0_5_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_5_data_hi_lo_lo = cat(sectored_entries_0_5_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_5_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_5_data_hi_lo_hi = cat(sectored_entries_0_5_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_5_data_hi_lo = cat(sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo)
node sectored_entries_0_5_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_5_data_hi_hi_lo = cat(sectored_entries_0_5_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_5_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_5_data_hi_hi_hi = cat(sectored_entries_0_5_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_5_data_hi_hi = cat(sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo)
node sectored_entries_0_5_data_hi = cat(sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo)
node _sectored_entries_0_5_data_T = cat(sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo)
connect sectored_entries[0][5].data[idx_5], _sectored_entries_0_5_data_T
when invalidate_refill :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
node _T_19 = eq(waddr_1, UInt<3>(0h6))
when _T_19 :
node _T_20 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_20 :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
connect sectored_entries[0][6].tag_vpn, r_refill_tag
connect sectored_entries[0][6].tag_v, refill_v
connect sectored_entries[0][6].level, UInt<2>(0h0)
node idx_6 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][6].valid[idx_6], UInt<1>(0h1)
node sectored_entries_0_6_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_6_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_6_data_lo_lo_hi = cat(sectored_entries_0_6_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_6_data_lo_lo = cat(sectored_entries_0_6_data_lo_lo_hi, sectored_entries_0_6_data_lo_lo_lo)
node sectored_entries_0_6_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_6_data_lo_hi_lo = cat(sectored_entries_0_6_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_6_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_6_data_lo_hi_hi = cat(sectored_entries_0_6_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_6_data_lo_hi = cat(sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo)
node sectored_entries_0_6_data_lo = cat(sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo)
node sectored_entries_0_6_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_6_data_hi_lo_lo = cat(sectored_entries_0_6_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_6_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_6_data_hi_lo_hi = cat(sectored_entries_0_6_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_6_data_hi_lo = cat(sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo)
node sectored_entries_0_6_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_6_data_hi_hi_lo = cat(sectored_entries_0_6_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_6_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_6_data_hi_hi_hi = cat(sectored_entries_0_6_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_6_data_hi_hi = cat(sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo)
node sectored_entries_0_6_data_hi = cat(sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo)
node _sectored_entries_0_6_data_T = cat(sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo)
connect sectored_entries[0][6].data[idx_6], _sectored_entries_0_6_data_T
when invalidate_refill :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
node _T_21 = eq(waddr_1, UInt<3>(0h7))
when _T_21 :
node _T_22 = eq(r_sectored_hit.valid, UInt<1>(0h0))
when _T_22 :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
connect sectored_entries[0][7].tag_vpn, r_refill_tag
connect sectored_entries[0][7].tag_v, refill_v
connect sectored_entries[0][7].level, UInt<2>(0h0)
node idx_7 = bits(r_refill_tag, 1, 0)
connect sectored_entries[0][7].valid[idx_7], UInt<1>(0h1)
node sectored_entries_0_7_data_lo_lo_lo = cat(newEntry.c, newEntry.fragmented_superpage)
node sectored_entries_0_7_data_lo_lo_hi_hi = cat(newEntry.pal, newEntry.paa)
node sectored_entries_0_7_data_lo_lo_hi = cat(sectored_entries_0_7_data_lo_lo_hi_hi, newEntry.eff)
node sectored_entries_0_7_data_lo_lo = cat(sectored_entries_0_7_data_lo_lo_hi, sectored_entries_0_7_data_lo_lo_lo)
node sectored_entries_0_7_data_lo_hi_lo_hi = cat(newEntry.px, newEntry.pr)
node sectored_entries_0_7_data_lo_hi_lo = cat(sectored_entries_0_7_data_lo_hi_lo_hi, newEntry.ppp)
node sectored_entries_0_7_data_lo_hi_hi_hi = cat(newEntry.hx, newEntry.hr)
node sectored_entries_0_7_data_lo_hi_hi = cat(sectored_entries_0_7_data_lo_hi_hi_hi, newEntry.pw)
node sectored_entries_0_7_data_lo_hi = cat(sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo)
node sectored_entries_0_7_data_lo = cat(sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo)
node sectored_entries_0_7_data_hi_lo_lo_hi = cat(newEntry.sx, newEntry.sr)
node sectored_entries_0_7_data_hi_lo_lo = cat(sectored_entries_0_7_data_hi_lo_lo_hi, newEntry.hw)
node sectored_entries_0_7_data_hi_lo_hi_hi = cat(newEntry.pf, newEntry.gf)
node sectored_entries_0_7_data_hi_lo_hi = cat(sectored_entries_0_7_data_hi_lo_hi_hi, newEntry.sw)
node sectored_entries_0_7_data_hi_lo = cat(sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo)
node sectored_entries_0_7_data_hi_hi_lo_hi = cat(newEntry.ae_ptw, newEntry.ae_final)
node sectored_entries_0_7_data_hi_hi_lo = cat(sectored_entries_0_7_data_hi_hi_lo_hi, newEntry.ae_stage2)
node sectored_entries_0_7_data_hi_hi_hi_hi = cat(newEntry.ppn, newEntry.u)
node sectored_entries_0_7_data_hi_hi_hi = cat(sectored_entries_0_7_data_hi_hi_hi_hi, newEntry.g)
node sectored_entries_0_7_data_hi_hi = cat(sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo)
node sectored_entries_0_7_data_hi = cat(sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo)
node _sectored_entries_0_7_data_T = cat(sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo)
connect sectored_entries[0][7].data[idx_7], _sectored_entries_0_7_data_T
when invalidate_refill :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
connect r_gpa_valid, io.ptw.resp.bits.gpa.valid
connect r_gpa, io.ptw.resp.bits.gpa.bits
connect r_gpa_is_pte, io.ptw.resp.bits.gpa_is_pte
node _entries_T = bits(vpn, 1, 0)
wire _entries_WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_1 : UInt<42>
connect _entries_WIRE_1, sectored_entries[0][0].data[_entries_T]
node _entries_T_1 = bits(_entries_WIRE_1, 0, 0)
connect _entries_WIRE.fragmented_superpage, _entries_T_1
node _entries_T_2 = bits(_entries_WIRE_1, 1, 1)
connect _entries_WIRE.c, _entries_T_2
node _entries_T_3 = bits(_entries_WIRE_1, 2, 2)
connect _entries_WIRE.eff, _entries_T_3
node _entries_T_4 = bits(_entries_WIRE_1, 3, 3)
connect _entries_WIRE.paa, _entries_T_4
node _entries_T_5 = bits(_entries_WIRE_1, 4, 4)
connect _entries_WIRE.pal, _entries_T_5
node _entries_T_6 = bits(_entries_WIRE_1, 5, 5)
connect _entries_WIRE.ppp, _entries_T_6
node _entries_T_7 = bits(_entries_WIRE_1, 6, 6)
connect _entries_WIRE.pr, _entries_T_7
node _entries_T_8 = bits(_entries_WIRE_1, 7, 7)
connect _entries_WIRE.px, _entries_T_8
node _entries_T_9 = bits(_entries_WIRE_1, 8, 8)
connect _entries_WIRE.pw, _entries_T_9
node _entries_T_10 = bits(_entries_WIRE_1, 9, 9)
connect _entries_WIRE.hr, _entries_T_10
node _entries_T_11 = bits(_entries_WIRE_1, 10, 10)
connect _entries_WIRE.hx, _entries_T_11
node _entries_T_12 = bits(_entries_WIRE_1, 11, 11)
connect _entries_WIRE.hw, _entries_T_12
node _entries_T_13 = bits(_entries_WIRE_1, 12, 12)
connect _entries_WIRE.sr, _entries_T_13
node _entries_T_14 = bits(_entries_WIRE_1, 13, 13)
connect _entries_WIRE.sx, _entries_T_14
node _entries_T_15 = bits(_entries_WIRE_1, 14, 14)
connect _entries_WIRE.sw, _entries_T_15
node _entries_T_16 = bits(_entries_WIRE_1, 15, 15)
connect _entries_WIRE.gf, _entries_T_16
node _entries_T_17 = bits(_entries_WIRE_1, 16, 16)
connect _entries_WIRE.pf, _entries_T_17
node _entries_T_18 = bits(_entries_WIRE_1, 17, 17)
connect _entries_WIRE.ae_stage2, _entries_T_18
node _entries_T_19 = bits(_entries_WIRE_1, 18, 18)
connect _entries_WIRE.ae_final, _entries_T_19
node _entries_T_20 = bits(_entries_WIRE_1, 19, 19)
connect _entries_WIRE.ae_ptw, _entries_T_20
node _entries_T_21 = bits(_entries_WIRE_1, 20, 20)
connect _entries_WIRE.g, _entries_T_21
node _entries_T_22 = bits(_entries_WIRE_1, 21, 21)
connect _entries_WIRE.u, _entries_T_22
node _entries_T_23 = bits(_entries_WIRE_1, 41, 22)
connect _entries_WIRE.ppn, _entries_T_23
inst entries_barrier of OptimizationBarrier_TLBEntryData_1
connect entries_barrier.clock, clock
connect entries_barrier.reset, reset
connect entries_barrier.io.x.fragmented_superpage, _entries_WIRE.fragmented_superpage
connect entries_barrier.io.x.c, _entries_WIRE.c
connect entries_barrier.io.x.eff, _entries_WIRE.eff
connect entries_barrier.io.x.paa, _entries_WIRE.paa
connect entries_barrier.io.x.pal, _entries_WIRE.pal
connect entries_barrier.io.x.ppp, _entries_WIRE.ppp
connect entries_barrier.io.x.pr, _entries_WIRE.pr
connect entries_barrier.io.x.px, _entries_WIRE.px
connect entries_barrier.io.x.pw, _entries_WIRE.pw
connect entries_barrier.io.x.hr, _entries_WIRE.hr
connect entries_barrier.io.x.hx, _entries_WIRE.hx
connect entries_barrier.io.x.hw, _entries_WIRE.hw
connect entries_barrier.io.x.sr, _entries_WIRE.sr
connect entries_barrier.io.x.sx, _entries_WIRE.sx
connect entries_barrier.io.x.sw, _entries_WIRE.sw
connect entries_barrier.io.x.gf, _entries_WIRE.gf
connect entries_barrier.io.x.pf, _entries_WIRE.pf
connect entries_barrier.io.x.ae_stage2, _entries_WIRE.ae_stage2
connect entries_barrier.io.x.ae_final, _entries_WIRE.ae_final
connect entries_barrier.io.x.ae_ptw, _entries_WIRE.ae_ptw
connect entries_barrier.io.x.g, _entries_WIRE.g
connect entries_barrier.io.x.u, _entries_WIRE.u
connect entries_barrier.io.x.ppn, _entries_WIRE.ppn
node _entries_T_24 = bits(vpn, 1, 0)
wire _entries_WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_3 : UInt<42>
connect _entries_WIRE_3, sectored_entries[0][1].data[_entries_T_24]
node _entries_T_25 = bits(_entries_WIRE_3, 0, 0)
connect _entries_WIRE_2.fragmented_superpage, _entries_T_25
node _entries_T_26 = bits(_entries_WIRE_3, 1, 1)
connect _entries_WIRE_2.c, _entries_T_26
node _entries_T_27 = bits(_entries_WIRE_3, 2, 2)
connect _entries_WIRE_2.eff, _entries_T_27
node _entries_T_28 = bits(_entries_WIRE_3, 3, 3)
connect _entries_WIRE_2.paa, _entries_T_28
node _entries_T_29 = bits(_entries_WIRE_3, 4, 4)
connect _entries_WIRE_2.pal, _entries_T_29
node _entries_T_30 = bits(_entries_WIRE_3, 5, 5)
connect _entries_WIRE_2.ppp, _entries_T_30
node _entries_T_31 = bits(_entries_WIRE_3, 6, 6)
connect _entries_WIRE_2.pr, _entries_T_31
node _entries_T_32 = bits(_entries_WIRE_3, 7, 7)
connect _entries_WIRE_2.px, _entries_T_32
node _entries_T_33 = bits(_entries_WIRE_3, 8, 8)
connect _entries_WIRE_2.pw, _entries_T_33
node _entries_T_34 = bits(_entries_WIRE_3, 9, 9)
connect _entries_WIRE_2.hr, _entries_T_34
node _entries_T_35 = bits(_entries_WIRE_3, 10, 10)
connect _entries_WIRE_2.hx, _entries_T_35
node _entries_T_36 = bits(_entries_WIRE_3, 11, 11)
connect _entries_WIRE_2.hw, _entries_T_36
node _entries_T_37 = bits(_entries_WIRE_3, 12, 12)
connect _entries_WIRE_2.sr, _entries_T_37
node _entries_T_38 = bits(_entries_WIRE_3, 13, 13)
connect _entries_WIRE_2.sx, _entries_T_38
node _entries_T_39 = bits(_entries_WIRE_3, 14, 14)
connect _entries_WIRE_2.sw, _entries_T_39
node _entries_T_40 = bits(_entries_WIRE_3, 15, 15)
connect _entries_WIRE_2.gf, _entries_T_40
node _entries_T_41 = bits(_entries_WIRE_3, 16, 16)
connect _entries_WIRE_2.pf, _entries_T_41
node _entries_T_42 = bits(_entries_WIRE_3, 17, 17)
connect _entries_WIRE_2.ae_stage2, _entries_T_42
node _entries_T_43 = bits(_entries_WIRE_3, 18, 18)
connect _entries_WIRE_2.ae_final, _entries_T_43
node _entries_T_44 = bits(_entries_WIRE_3, 19, 19)
connect _entries_WIRE_2.ae_ptw, _entries_T_44
node _entries_T_45 = bits(_entries_WIRE_3, 20, 20)
connect _entries_WIRE_2.g, _entries_T_45
node _entries_T_46 = bits(_entries_WIRE_3, 21, 21)
connect _entries_WIRE_2.u, _entries_T_46
node _entries_T_47 = bits(_entries_WIRE_3, 41, 22)
connect _entries_WIRE_2.ppn, _entries_T_47
inst entries_barrier_1 of OptimizationBarrier_TLBEntryData_2
connect entries_barrier_1.clock, clock
connect entries_barrier_1.reset, reset
connect entries_barrier_1.io.x.fragmented_superpage, _entries_WIRE_2.fragmented_superpage
connect entries_barrier_1.io.x.c, _entries_WIRE_2.c
connect entries_barrier_1.io.x.eff, _entries_WIRE_2.eff
connect entries_barrier_1.io.x.paa, _entries_WIRE_2.paa
connect entries_barrier_1.io.x.pal, _entries_WIRE_2.pal
connect entries_barrier_1.io.x.ppp, _entries_WIRE_2.ppp
connect entries_barrier_1.io.x.pr, _entries_WIRE_2.pr
connect entries_barrier_1.io.x.px, _entries_WIRE_2.px
connect entries_barrier_1.io.x.pw, _entries_WIRE_2.pw
connect entries_barrier_1.io.x.hr, _entries_WIRE_2.hr
connect entries_barrier_1.io.x.hx, _entries_WIRE_2.hx
connect entries_barrier_1.io.x.hw, _entries_WIRE_2.hw
connect entries_barrier_1.io.x.sr, _entries_WIRE_2.sr
connect entries_barrier_1.io.x.sx, _entries_WIRE_2.sx
connect entries_barrier_1.io.x.sw, _entries_WIRE_2.sw
connect entries_barrier_1.io.x.gf, _entries_WIRE_2.gf
connect entries_barrier_1.io.x.pf, _entries_WIRE_2.pf
connect entries_barrier_1.io.x.ae_stage2, _entries_WIRE_2.ae_stage2
connect entries_barrier_1.io.x.ae_final, _entries_WIRE_2.ae_final
connect entries_barrier_1.io.x.ae_ptw, _entries_WIRE_2.ae_ptw
connect entries_barrier_1.io.x.g, _entries_WIRE_2.g
connect entries_barrier_1.io.x.u, _entries_WIRE_2.u
connect entries_barrier_1.io.x.ppn, _entries_WIRE_2.ppn
node _entries_T_48 = bits(vpn, 1, 0)
wire _entries_WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_5 : UInt<42>
connect _entries_WIRE_5, sectored_entries[0][2].data[_entries_T_48]
node _entries_T_49 = bits(_entries_WIRE_5, 0, 0)
connect _entries_WIRE_4.fragmented_superpage, _entries_T_49
node _entries_T_50 = bits(_entries_WIRE_5, 1, 1)
connect _entries_WIRE_4.c, _entries_T_50
node _entries_T_51 = bits(_entries_WIRE_5, 2, 2)
connect _entries_WIRE_4.eff, _entries_T_51
node _entries_T_52 = bits(_entries_WIRE_5, 3, 3)
connect _entries_WIRE_4.paa, _entries_T_52
node _entries_T_53 = bits(_entries_WIRE_5, 4, 4)
connect _entries_WIRE_4.pal, _entries_T_53
node _entries_T_54 = bits(_entries_WIRE_5, 5, 5)
connect _entries_WIRE_4.ppp, _entries_T_54
node _entries_T_55 = bits(_entries_WIRE_5, 6, 6)
connect _entries_WIRE_4.pr, _entries_T_55
node _entries_T_56 = bits(_entries_WIRE_5, 7, 7)
connect _entries_WIRE_4.px, _entries_T_56
node _entries_T_57 = bits(_entries_WIRE_5, 8, 8)
connect _entries_WIRE_4.pw, _entries_T_57
node _entries_T_58 = bits(_entries_WIRE_5, 9, 9)
connect _entries_WIRE_4.hr, _entries_T_58
node _entries_T_59 = bits(_entries_WIRE_5, 10, 10)
connect _entries_WIRE_4.hx, _entries_T_59
node _entries_T_60 = bits(_entries_WIRE_5, 11, 11)
connect _entries_WIRE_4.hw, _entries_T_60
node _entries_T_61 = bits(_entries_WIRE_5, 12, 12)
connect _entries_WIRE_4.sr, _entries_T_61
node _entries_T_62 = bits(_entries_WIRE_5, 13, 13)
connect _entries_WIRE_4.sx, _entries_T_62
node _entries_T_63 = bits(_entries_WIRE_5, 14, 14)
connect _entries_WIRE_4.sw, _entries_T_63
node _entries_T_64 = bits(_entries_WIRE_5, 15, 15)
connect _entries_WIRE_4.gf, _entries_T_64
node _entries_T_65 = bits(_entries_WIRE_5, 16, 16)
connect _entries_WIRE_4.pf, _entries_T_65
node _entries_T_66 = bits(_entries_WIRE_5, 17, 17)
connect _entries_WIRE_4.ae_stage2, _entries_T_66
node _entries_T_67 = bits(_entries_WIRE_5, 18, 18)
connect _entries_WIRE_4.ae_final, _entries_T_67
node _entries_T_68 = bits(_entries_WIRE_5, 19, 19)
connect _entries_WIRE_4.ae_ptw, _entries_T_68
node _entries_T_69 = bits(_entries_WIRE_5, 20, 20)
connect _entries_WIRE_4.g, _entries_T_69
node _entries_T_70 = bits(_entries_WIRE_5, 21, 21)
connect _entries_WIRE_4.u, _entries_T_70
node _entries_T_71 = bits(_entries_WIRE_5, 41, 22)
connect _entries_WIRE_4.ppn, _entries_T_71
inst entries_barrier_2 of OptimizationBarrier_TLBEntryData_3
connect entries_barrier_2.clock, clock
connect entries_barrier_2.reset, reset
connect entries_barrier_2.io.x.fragmented_superpage, _entries_WIRE_4.fragmented_superpage
connect entries_barrier_2.io.x.c, _entries_WIRE_4.c
connect entries_barrier_2.io.x.eff, _entries_WIRE_4.eff
connect entries_barrier_2.io.x.paa, _entries_WIRE_4.paa
connect entries_barrier_2.io.x.pal, _entries_WIRE_4.pal
connect entries_barrier_2.io.x.ppp, _entries_WIRE_4.ppp
connect entries_barrier_2.io.x.pr, _entries_WIRE_4.pr
connect entries_barrier_2.io.x.px, _entries_WIRE_4.px
connect entries_barrier_2.io.x.pw, _entries_WIRE_4.pw
connect entries_barrier_2.io.x.hr, _entries_WIRE_4.hr
connect entries_barrier_2.io.x.hx, _entries_WIRE_4.hx
connect entries_barrier_2.io.x.hw, _entries_WIRE_4.hw
connect entries_barrier_2.io.x.sr, _entries_WIRE_4.sr
connect entries_barrier_2.io.x.sx, _entries_WIRE_4.sx
connect entries_barrier_2.io.x.sw, _entries_WIRE_4.sw
connect entries_barrier_2.io.x.gf, _entries_WIRE_4.gf
connect entries_barrier_2.io.x.pf, _entries_WIRE_4.pf
connect entries_barrier_2.io.x.ae_stage2, _entries_WIRE_4.ae_stage2
connect entries_barrier_2.io.x.ae_final, _entries_WIRE_4.ae_final
connect entries_barrier_2.io.x.ae_ptw, _entries_WIRE_4.ae_ptw
connect entries_barrier_2.io.x.g, _entries_WIRE_4.g
connect entries_barrier_2.io.x.u, _entries_WIRE_4.u
connect entries_barrier_2.io.x.ppn, _entries_WIRE_4.ppn
node _entries_T_72 = bits(vpn, 1, 0)
wire _entries_WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_7 : UInt<42>
connect _entries_WIRE_7, sectored_entries[0][3].data[_entries_T_72]
node _entries_T_73 = bits(_entries_WIRE_7, 0, 0)
connect _entries_WIRE_6.fragmented_superpage, _entries_T_73
node _entries_T_74 = bits(_entries_WIRE_7, 1, 1)
connect _entries_WIRE_6.c, _entries_T_74
node _entries_T_75 = bits(_entries_WIRE_7, 2, 2)
connect _entries_WIRE_6.eff, _entries_T_75
node _entries_T_76 = bits(_entries_WIRE_7, 3, 3)
connect _entries_WIRE_6.paa, _entries_T_76
node _entries_T_77 = bits(_entries_WIRE_7, 4, 4)
connect _entries_WIRE_6.pal, _entries_T_77
node _entries_T_78 = bits(_entries_WIRE_7, 5, 5)
connect _entries_WIRE_6.ppp, _entries_T_78
node _entries_T_79 = bits(_entries_WIRE_7, 6, 6)
connect _entries_WIRE_6.pr, _entries_T_79
node _entries_T_80 = bits(_entries_WIRE_7, 7, 7)
connect _entries_WIRE_6.px, _entries_T_80
node _entries_T_81 = bits(_entries_WIRE_7, 8, 8)
connect _entries_WIRE_6.pw, _entries_T_81
node _entries_T_82 = bits(_entries_WIRE_7, 9, 9)
connect _entries_WIRE_6.hr, _entries_T_82
node _entries_T_83 = bits(_entries_WIRE_7, 10, 10)
connect _entries_WIRE_6.hx, _entries_T_83
node _entries_T_84 = bits(_entries_WIRE_7, 11, 11)
connect _entries_WIRE_6.hw, _entries_T_84
node _entries_T_85 = bits(_entries_WIRE_7, 12, 12)
connect _entries_WIRE_6.sr, _entries_T_85
node _entries_T_86 = bits(_entries_WIRE_7, 13, 13)
connect _entries_WIRE_6.sx, _entries_T_86
node _entries_T_87 = bits(_entries_WIRE_7, 14, 14)
connect _entries_WIRE_6.sw, _entries_T_87
node _entries_T_88 = bits(_entries_WIRE_7, 15, 15)
connect _entries_WIRE_6.gf, _entries_T_88
node _entries_T_89 = bits(_entries_WIRE_7, 16, 16)
connect _entries_WIRE_6.pf, _entries_T_89
node _entries_T_90 = bits(_entries_WIRE_7, 17, 17)
connect _entries_WIRE_6.ae_stage2, _entries_T_90
node _entries_T_91 = bits(_entries_WIRE_7, 18, 18)
connect _entries_WIRE_6.ae_final, _entries_T_91
node _entries_T_92 = bits(_entries_WIRE_7, 19, 19)
connect _entries_WIRE_6.ae_ptw, _entries_T_92
node _entries_T_93 = bits(_entries_WIRE_7, 20, 20)
connect _entries_WIRE_6.g, _entries_T_93
node _entries_T_94 = bits(_entries_WIRE_7, 21, 21)
connect _entries_WIRE_6.u, _entries_T_94
node _entries_T_95 = bits(_entries_WIRE_7, 41, 22)
connect _entries_WIRE_6.ppn, _entries_T_95
inst entries_barrier_3 of OptimizationBarrier_TLBEntryData_4
connect entries_barrier_3.clock, clock
connect entries_barrier_3.reset, reset
connect entries_barrier_3.io.x.fragmented_superpage, _entries_WIRE_6.fragmented_superpage
connect entries_barrier_3.io.x.c, _entries_WIRE_6.c
connect entries_barrier_3.io.x.eff, _entries_WIRE_6.eff
connect entries_barrier_3.io.x.paa, _entries_WIRE_6.paa
connect entries_barrier_3.io.x.pal, _entries_WIRE_6.pal
connect entries_barrier_3.io.x.ppp, _entries_WIRE_6.ppp
connect entries_barrier_3.io.x.pr, _entries_WIRE_6.pr
connect entries_barrier_3.io.x.px, _entries_WIRE_6.px
connect entries_barrier_3.io.x.pw, _entries_WIRE_6.pw
connect entries_barrier_3.io.x.hr, _entries_WIRE_6.hr
connect entries_barrier_3.io.x.hx, _entries_WIRE_6.hx
connect entries_barrier_3.io.x.hw, _entries_WIRE_6.hw
connect entries_barrier_3.io.x.sr, _entries_WIRE_6.sr
connect entries_barrier_3.io.x.sx, _entries_WIRE_6.sx
connect entries_barrier_3.io.x.sw, _entries_WIRE_6.sw
connect entries_barrier_3.io.x.gf, _entries_WIRE_6.gf
connect entries_barrier_3.io.x.pf, _entries_WIRE_6.pf
connect entries_barrier_3.io.x.ae_stage2, _entries_WIRE_6.ae_stage2
connect entries_barrier_3.io.x.ae_final, _entries_WIRE_6.ae_final
connect entries_barrier_3.io.x.ae_ptw, _entries_WIRE_6.ae_ptw
connect entries_barrier_3.io.x.g, _entries_WIRE_6.g
connect entries_barrier_3.io.x.u, _entries_WIRE_6.u
connect entries_barrier_3.io.x.ppn, _entries_WIRE_6.ppn
node _entries_T_96 = bits(vpn, 1, 0)
wire _entries_WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_9 : UInt<42>
connect _entries_WIRE_9, sectored_entries[0][4].data[_entries_T_96]
node _entries_T_97 = bits(_entries_WIRE_9, 0, 0)
connect _entries_WIRE_8.fragmented_superpage, _entries_T_97
node _entries_T_98 = bits(_entries_WIRE_9, 1, 1)
connect _entries_WIRE_8.c, _entries_T_98
node _entries_T_99 = bits(_entries_WIRE_9, 2, 2)
connect _entries_WIRE_8.eff, _entries_T_99
node _entries_T_100 = bits(_entries_WIRE_9, 3, 3)
connect _entries_WIRE_8.paa, _entries_T_100
node _entries_T_101 = bits(_entries_WIRE_9, 4, 4)
connect _entries_WIRE_8.pal, _entries_T_101
node _entries_T_102 = bits(_entries_WIRE_9, 5, 5)
connect _entries_WIRE_8.ppp, _entries_T_102
node _entries_T_103 = bits(_entries_WIRE_9, 6, 6)
connect _entries_WIRE_8.pr, _entries_T_103
node _entries_T_104 = bits(_entries_WIRE_9, 7, 7)
connect _entries_WIRE_8.px, _entries_T_104
node _entries_T_105 = bits(_entries_WIRE_9, 8, 8)
connect _entries_WIRE_8.pw, _entries_T_105
node _entries_T_106 = bits(_entries_WIRE_9, 9, 9)
connect _entries_WIRE_8.hr, _entries_T_106
node _entries_T_107 = bits(_entries_WIRE_9, 10, 10)
connect _entries_WIRE_8.hx, _entries_T_107
node _entries_T_108 = bits(_entries_WIRE_9, 11, 11)
connect _entries_WIRE_8.hw, _entries_T_108
node _entries_T_109 = bits(_entries_WIRE_9, 12, 12)
connect _entries_WIRE_8.sr, _entries_T_109
node _entries_T_110 = bits(_entries_WIRE_9, 13, 13)
connect _entries_WIRE_8.sx, _entries_T_110
node _entries_T_111 = bits(_entries_WIRE_9, 14, 14)
connect _entries_WIRE_8.sw, _entries_T_111
node _entries_T_112 = bits(_entries_WIRE_9, 15, 15)
connect _entries_WIRE_8.gf, _entries_T_112
node _entries_T_113 = bits(_entries_WIRE_9, 16, 16)
connect _entries_WIRE_8.pf, _entries_T_113
node _entries_T_114 = bits(_entries_WIRE_9, 17, 17)
connect _entries_WIRE_8.ae_stage2, _entries_T_114
node _entries_T_115 = bits(_entries_WIRE_9, 18, 18)
connect _entries_WIRE_8.ae_final, _entries_T_115
node _entries_T_116 = bits(_entries_WIRE_9, 19, 19)
connect _entries_WIRE_8.ae_ptw, _entries_T_116
node _entries_T_117 = bits(_entries_WIRE_9, 20, 20)
connect _entries_WIRE_8.g, _entries_T_117
node _entries_T_118 = bits(_entries_WIRE_9, 21, 21)
connect _entries_WIRE_8.u, _entries_T_118
node _entries_T_119 = bits(_entries_WIRE_9, 41, 22)
connect _entries_WIRE_8.ppn, _entries_T_119
inst entries_barrier_4 of OptimizationBarrier_TLBEntryData_5
connect entries_barrier_4.clock, clock
connect entries_barrier_4.reset, reset
connect entries_barrier_4.io.x.fragmented_superpage, _entries_WIRE_8.fragmented_superpage
connect entries_barrier_4.io.x.c, _entries_WIRE_8.c
connect entries_barrier_4.io.x.eff, _entries_WIRE_8.eff
connect entries_barrier_4.io.x.paa, _entries_WIRE_8.paa
connect entries_barrier_4.io.x.pal, _entries_WIRE_8.pal
connect entries_barrier_4.io.x.ppp, _entries_WIRE_8.ppp
connect entries_barrier_4.io.x.pr, _entries_WIRE_8.pr
connect entries_barrier_4.io.x.px, _entries_WIRE_8.px
connect entries_barrier_4.io.x.pw, _entries_WIRE_8.pw
connect entries_barrier_4.io.x.hr, _entries_WIRE_8.hr
connect entries_barrier_4.io.x.hx, _entries_WIRE_8.hx
connect entries_barrier_4.io.x.hw, _entries_WIRE_8.hw
connect entries_barrier_4.io.x.sr, _entries_WIRE_8.sr
connect entries_barrier_4.io.x.sx, _entries_WIRE_8.sx
connect entries_barrier_4.io.x.sw, _entries_WIRE_8.sw
connect entries_barrier_4.io.x.gf, _entries_WIRE_8.gf
connect entries_barrier_4.io.x.pf, _entries_WIRE_8.pf
connect entries_barrier_4.io.x.ae_stage2, _entries_WIRE_8.ae_stage2
connect entries_barrier_4.io.x.ae_final, _entries_WIRE_8.ae_final
connect entries_barrier_4.io.x.ae_ptw, _entries_WIRE_8.ae_ptw
connect entries_barrier_4.io.x.g, _entries_WIRE_8.g
connect entries_barrier_4.io.x.u, _entries_WIRE_8.u
connect entries_barrier_4.io.x.ppn, _entries_WIRE_8.ppn
node _entries_T_120 = bits(vpn, 1, 0)
wire _entries_WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_11 : UInt<42>
connect _entries_WIRE_11, sectored_entries[0][5].data[_entries_T_120]
node _entries_T_121 = bits(_entries_WIRE_11, 0, 0)
connect _entries_WIRE_10.fragmented_superpage, _entries_T_121
node _entries_T_122 = bits(_entries_WIRE_11, 1, 1)
connect _entries_WIRE_10.c, _entries_T_122
node _entries_T_123 = bits(_entries_WIRE_11, 2, 2)
connect _entries_WIRE_10.eff, _entries_T_123
node _entries_T_124 = bits(_entries_WIRE_11, 3, 3)
connect _entries_WIRE_10.paa, _entries_T_124
node _entries_T_125 = bits(_entries_WIRE_11, 4, 4)
connect _entries_WIRE_10.pal, _entries_T_125
node _entries_T_126 = bits(_entries_WIRE_11, 5, 5)
connect _entries_WIRE_10.ppp, _entries_T_126
node _entries_T_127 = bits(_entries_WIRE_11, 6, 6)
connect _entries_WIRE_10.pr, _entries_T_127
node _entries_T_128 = bits(_entries_WIRE_11, 7, 7)
connect _entries_WIRE_10.px, _entries_T_128
node _entries_T_129 = bits(_entries_WIRE_11, 8, 8)
connect _entries_WIRE_10.pw, _entries_T_129
node _entries_T_130 = bits(_entries_WIRE_11, 9, 9)
connect _entries_WIRE_10.hr, _entries_T_130
node _entries_T_131 = bits(_entries_WIRE_11, 10, 10)
connect _entries_WIRE_10.hx, _entries_T_131
node _entries_T_132 = bits(_entries_WIRE_11, 11, 11)
connect _entries_WIRE_10.hw, _entries_T_132
node _entries_T_133 = bits(_entries_WIRE_11, 12, 12)
connect _entries_WIRE_10.sr, _entries_T_133
node _entries_T_134 = bits(_entries_WIRE_11, 13, 13)
connect _entries_WIRE_10.sx, _entries_T_134
node _entries_T_135 = bits(_entries_WIRE_11, 14, 14)
connect _entries_WIRE_10.sw, _entries_T_135
node _entries_T_136 = bits(_entries_WIRE_11, 15, 15)
connect _entries_WIRE_10.gf, _entries_T_136
node _entries_T_137 = bits(_entries_WIRE_11, 16, 16)
connect _entries_WIRE_10.pf, _entries_T_137
node _entries_T_138 = bits(_entries_WIRE_11, 17, 17)
connect _entries_WIRE_10.ae_stage2, _entries_T_138
node _entries_T_139 = bits(_entries_WIRE_11, 18, 18)
connect _entries_WIRE_10.ae_final, _entries_T_139
node _entries_T_140 = bits(_entries_WIRE_11, 19, 19)
connect _entries_WIRE_10.ae_ptw, _entries_T_140
node _entries_T_141 = bits(_entries_WIRE_11, 20, 20)
connect _entries_WIRE_10.g, _entries_T_141
node _entries_T_142 = bits(_entries_WIRE_11, 21, 21)
connect _entries_WIRE_10.u, _entries_T_142
node _entries_T_143 = bits(_entries_WIRE_11, 41, 22)
connect _entries_WIRE_10.ppn, _entries_T_143
inst entries_barrier_5 of OptimizationBarrier_TLBEntryData_6
connect entries_barrier_5.clock, clock
connect entries_barrier_5.reset, reset
connect entries_barrier_5.io.x.fragmented_superpage, _entries_WIRE_10.fragmented_superpage
connect entries_barrier_5.io.x.c, _entries_WIRE_10.c
connect entries_barrier_5.io.x.eff, _entries_WIRE_10.eff
connect entries_barrier_5.io.x.paa, _entries_WIRE_10.paa
connect entries_barrier_5.io.x.pal, _entries_WIRE_10.pal
connect entries_barrier_5.io.x.ppp, _entries_WIRE_10.ppp
connect entries_barrier_5.io.x.pr, _entries_WIRE_10.pr
connect entries_barrier_5.io.x.px, _entries_WIRE_10.px
connect entries_barrier_5.io.x.pw, _entries_WIRE_10.pw
connect entries_barrier_5.io.x.hr, _entries_WIRE_10.hr
connect entries_barrier_5.io.x.hx, _entries_WIRE_10.hx
connect entries_barrier_5.io.x.hw, _entries_WIRE_10.hw
connect entries_barrier_5.io.x.sr, _entries_WIRE_10.sr
connect entries_barrier_5.io.x.sx, _entries_WIRE_10.sx
connect entries_barrier_5.io.x.sw, _entries_WIRE_10.sw
connect entries_barrier_5.io.x.gf, _entries_WIRE_10.gf
connect entries_barrier_5.io.x.pf, _entries_WIRE_10.pf
connect entries_barrier_5.io.x.ae_stage2, _entries_WIRE_10.ae_stage2
connect entries_barrier_5.io.x.ae_final, _entries_WIRE_10.ae_final
connect entries_barrier_5.io.x.ae_ptw, _entries_WIRE_10.ae_ptw
connect entries_barrier_5.io.x.g, _entries_WIRE_10.g
connect entries_barrier_5.io.x.u, _entries_WIRE_10.u
connect entries_barrier_5.io.x.ppn, _entries_WIRE_10.ppn
node _entries_T_144 = bits(vpn, 1, 0)
wire _entries_WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_13 : UInt<42>
connect _entries_WIRE_13, sectored_entries[0][6].data[_entries_T_144]
node _entries_T_145 = bits(_entries_WIRE_13, 0, 0)
connect _entries_WIRE_12.fragmented_superpage, _entries_T_145
node _entries_T_146 = bits(_entries_WIRE_13, 1, 1)
connect _entries_WIRE_12.c, _entries_T_146
node _entries_T_147 = bits(_entries_WIRE_13, 2, 2)
connect _entries_WIRE_12.eff, _entries_T_147
node _entries_T_148 = bits(_entries_WIRE_13, 3, 3)
connect _entries_WIRE_12.paa, _entries_T_148
node _entries_T_149 = bits(_entries_WIRE_13, 4, 4)
connect _entries_WIRE_12.pal, _entries_T_149
node _entries_T_150 = bits(_entries_WIRE_13, 5, 5)
connect _entries_WIRE_12.ppp, _entries_T_150
node _entries_T_151 = bits(_entries_WIRE_13, 6, 6)
connect _entries_WIRE_12.pr, _entries_T_151
node _entries_T_152 = bits(_entries_WIRE_13, 7, 7)
connect _entries_WIRE_12.px, _entries_T_152
node _entries_T_153 = bits(_entries_WIRE_13, 8, 8)
connect _entries_WIRE_12.pw, _entries_T_153
node _entries_T_154 = bits(_entries_WIRE_13, 9, 9)
connect _entries_WIRE_12.hr, _entries_T_154
node _entries_T_155 = bits(_entries_WIRE_13, 10, 10)
connect _entries_WIRE_12.hx, _entries_T_155
node _entries_T_156 = bits(_entries_WIRE_13, 11, 11)
connect _entries_WIRE_12.hw, _entries_T_156
node _entries_T_157 = bits(_entries_WIRE_13, 12, 12)
connect _entries_WIRE_12.sr, _entries_T_157
node _entries_T_158 = bits(_entries_WIRE_13, 13, 13)
connect _entries_WIRE_12.sx, _entries_T_158
node _entries_T_159 = bits(_entries_WIRE_13, 14, 14)
connect _entries_WIRE_12.sw, _entries_T_159
node _entries_T_160 = bits(_entries_WIRE_13, 15, 15)
connect _entries_WIRE_12.gf, _entries_T_160
node _entries_T_161 = bits(_entries_WIRE_13, 16, 16)
connect _entries_WIRE_12.pf, _entries_T_161
node _entries_T_162 = bits(_entries_WIRE_13, 17, 17)
connect _entries_WIRE_12.ae_stage2, _entries_T_162
node _entries_T_163 = bits(_entries_WIRE_13, 18, 18)
connect _entries_WIRE_12.ae_final, _entries_T_163
node _entries_T_164 = bits(_entries_WIRE_13, 19, 19)
connect _entries_WIRE_12.ae_ptw, _entries_T_164
node _entries_T_165 = bits(_entries_WIRE_13, 20, 20)
connect _entries_WIRE_12.g, _entries_T_165
node _entries_T_166 = bits(_entries_WIRE_13, 21, 21)
connect _entries_WIRE_12.u, _entries_T_166
node _entries_T_167 = bits(_entries_WIRE_13, 41, 22)
connect _entries_WIRE_12.ppn, _entries_T_167
inst entries_barrier_6 of OptimizationBarrier_TLBEntryData_7
connect entries_barrier_6.clock, clock
connect entries_barrier_6.reset, reset
connect entries_barrier_6.io.x.fragmented_superpage, _entries_WIRE_12.fragmented_superpage
connect entries_barrier_6.io.x.c, _entries_WIRE_12.c
connect entries_barrier_6.io.x.eff, _entries_WIRE_12.eff
connect entries_barrier_6.io.x.paa, _entries_WIRE_12.paa
connect entries_barrier_6.io.x.pal, _entries_WIRE_12.pal
connect entries_barrier_6.io.x.ppp, _entries_WIRE_12.ppp
connect entries_barrier_6.io.x.pr, _entries_WIRE_12.pr
connect entries_barrier_6.io.x.px, _entries_WIRE_12.px
connect entries_barrier_6.io.x.pw, _entries_WIRE_12.pw
connect entries_barrier_6.io.x.hr, _entries_WIRE_12.hr
connect entries_barrier_6.io.x.hx, _entries_WIRE_12.hx
connect entries_barrier_6.io.x.hw, _entries_WIRE_12.hw
connect entries_barrier_6.io.x.sr, _entries_WIRE_12.sr
connect entries_barrier_6.io.x.sx, _entries_WIRE_12.sx
connect entries_barrier_6.io.x.sw, _entries_WIRE_12.sw
connect entries_barrier_6.io.x.gf, _entries_WIRE_12.gf
connect entries_barrier_6.io.x.pf, _entries_WIRE_12.pf
connect entries_barrier_6.io.x.ae_stage2, _entries_WIRE_12.ae_stage2
connect entries_barrier_6.io.x.ae_final, _entries_WIRE_12.ae_final
connect entries_barrier_6.io.x.ae_ptw, _entries_WIRE_12.ae_ptw
connect entries_barrier_6.io.x.g, _entries_WIRE_12.g
connect entries_barrier_6.io.x.u, _entries_WIRE_12.u
connect entries_barrier_6.io.x.ppn, _entries_WIRE_12.ppn
node _entries_T_168 = bits(vpn, 1, 0)
wire _entries_WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_15 : UInt<42>
connect _entries_WIRE_15, sectored_entries[0][7].data[_entries_T_168]
node _entries_T_169 = bits(_entries_WIRE_15, 0, 0)
connect _entries_WIRE_14.fragmented_superpage, _entries_T_169
node _entries_T_170 = bits(_entries_WIRE_15, 1, 1)
connect _entries_WIRE_14.c, _entries_T_170
node _entries_T_171 = bits(_entries_WIRE_15, 2, 2)
connect _entries_WIRE_14.eff, _entries_T_171
node _entries_T_172 = bits(_entries_WIRE_15, 3, 3)
connect _entries_WIRE_14.paa, _entries_T_172
node _entries_T_173 = bits(_entries_WIRE_15, 4, 4)
connect _entries_WIRE_14.pal, _entries_T_173
node _entries_T_174 = bits(_entries_WIRE_15, 5, 5)
connect _entries_WIRE_14.ppp, _entries_T_174
node _entries_T_175 = bits(_entries_WIRE_15, 6, 6)
connect _entries_WIRE_14.pr, _entries_T_175
node _entries_T_176 = bits(_entries_WIRE_15, 7, 7)
connect _entries_WIRE_14.px, _entries_T_176
node _entries_T_177 = bits(_entries_WIRE_15, 8, 8)
connect _entries_WIRE_14.pw, _entries_T_177
node _entries_T_178 = bits(_entries_WIRE_15, 9, 9)
connect _entries_WIRE_14.hr, _entries_T_178
node _entries_T_179 = bits(_entries_WIRE_15, 10, 10)
connect _entries_WIRE_14.hx, _entries_T_179
node _entries_T_180 = bits(_entries_WIRE_15, 11, 11)
connect _entries_WIRE_14.hw, _entries_T_180
node _entries_T_181 = bits(_entries_WIRE_15, 12, 12)
connect _entries_WIRE_14.sr, _entries_T_181
node _entries_T_182 = bits(_entries_WIRE_15, 13, 13)
connect _entries_WIRE_14.sx, _entries_T_182
node _entries_T_183 = bits(_entries_WIRE_15, 14, 14)
connect _entries_WIRE_14.sw, _entries_T_183
node _entries_T_184 = bits(_entries_WIRE_15, 15, 15)
connect _entries_WIRE_14.gf, _entries_T_184
node _entries_T_185 = bits(_entries_WIRE_15, 16, 16)
connect _entries_WIRE_14.pf, _entries_T_185
node _entries_T_186 = bits(_entries_WIRE_15, 17, 17)
connect _entries_WIRE_14.ae_stage2, _entries_T_186
node _entries_T_187 = bits(_entries_WIRE_15, 18, 18)
connect _entries_WIRE_14.ae_final, _entries_T_187
node _entries_T_188 = bits(_entries_WIRE_15, 19, 19)
connect _entries_WIRE_14.ae_ptw, _entries_T_188
node _entries_T_189 = bits(_entries_WIRE_15, 20, 20)
connect _entries_WIRE_14.g, _entries_T_189
node _entries_T_190 = bits(_entries_WIRE_15, 21, 21)
connect _entries_WIRE_14.u, _entries_T_190
node _entries_T_191 = bits(_entries_WIRE_15, 41, 22)
connect _entries_WIRE_14.ppn, _entries_T_191
inst entries_barrier_7 of OptimizationBarrier_TLBEntryData_8
connect entries_barrier_7.clock, clock
connect entries_barrier_7.reset, reset
connect entries_barrier_7.io.x.fragmented_superpage, _entries_WIRE_14.fragmented_superpage
connect entries_barrier_7.io.x.c, _entries_WIRE_14.c
connect entries_barrier_7.io.x.eff, _entries_WIRE_14.eff
connect entries_barrier_7.io.x.paa, _entries_WIRE_14.paa
connect entries_barrier_7.io.x.pal, _entries_WIRE_14.pal
connect entries_barrier_7.io.x.ppp, _entries_WIRE_14.ppp
connect entries_barrier_7.io.x.pr, _entries_WIRE_14.pr
connect entries_barrier_7.io.x.px, _entries_WIRE_14.px
connect entries_barrier_7.io.x.pw, _entries_WIRE_14.pw
connect entries_barrier_7.io.x.hr, _entries_WIRE_14.hr
connect entries_barrier_7.io.x.hx, _entries_WIRE_14.hx
connect entries_barrier_7.io.x.hw, _entries_WIRE_14.hw
connect entries_barrier_7.io.x.sr, _entries_WIRE_14.sr
connect entries_barrier_7.io.x.sx, _entries_WIRE_14.sx
connect entries_barrier_7.io.x.sw, _entries_WIRE_14.sw
connect entries_barrier_7.io.x.gf, _entries_WIRE_14.gf
connect entries_barrier_7.io.x.pf, _entries_WIRE_14.pf
connect entries_barrier_7.io.x.ae_stage2, _entries_WIRE_14.ae_stage2
connect entries_barrier_7.io.x.ae_final, _entries_WIRE_14.ae_final
connect entries_barrier_7.io.x.ae_ptw, _entries_WIRE_14.ae_ptw
connect entries_barrier_7.io.x.g, _entries_WIRE_14.g
connect entries_barrier_7.io.x.u, _entries_WIRE_14.u
connect entries_barrier_7.io.x.ppn, _entries_WIRE_14.ppn
wire _entries_WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_17 : UInt<42>
connect _entries_WIRE_17, superpage_entries[0].data[0]
node _entries_T_192 = bits(_entries_WIRE_17, 0, 0)
connect _entries_WIRE_16.fragmented_superpage, _entries_T_192
node _entries_T_193 = bits(_entries_WIRE_17, 1, 1)
connect _entries_WIRE_16.c, _entries_T_193
node _entries_T_194 = bits(_entries_WIRE_17, 2, 2)
connect _entries_WIRE_16.eff, _entries_T_194
node _entries_T_195 = bits(_entries_WIRE_17, 3, 3)
connect _entries_WIRE_16.paa, _entries_T_195
node _entries_T_196 = bits(_entries_WIRE_17, 4, 4)
connect _entries_WIRE_16.pal, _entries_T_196
node _entries_T_197 = bits(_entries_WIRE_17, 5, 5)
connect _entries_WIRE_16.ppp, _entries_T_197
node _entries_T_198 = bits(_entries_WIRE_17, 6, 6)
connect _entries_WIRE_16.pr, _entries_T_198
node _entries_T_199 = bits(_entries_WIRE_17, 7, 7)
connect _entries_WIRE_16.px, _entries_T_199
node _entries_T_200 = bits(_entries_WIRE_17, 8, 8)
connect _entries_WIRE_16.pw, _entries_T_200
node _entries_T_201 = bits(_entries_WIRE_17, 9, 9)
connect _entries_WIRE_16.hr, _entries_T_201
node _entries_T_202 = bits(_entries_WIRE_17, 10, 10)
connect _entries_WIRE_16.hx, _entries_T_202
node _entries_T_203 = bits(_entries_WIRE_17, 11, 11)
connect _entries_WIRE_16.hw, _entries_T_203
node _entries_T_204 = bits(_entries_WIRE_17, 12, 12)
connect _entries_WIRE_16.sr, _entries_T_204
node _entries_T_205 = bits(_entries_WIRE_17, 13, 13)
connect _entries_WIRE_16.sx, _entries_T_205
node _entries_T_206 = bits(_entries_WIRE_17, 14, 14)
connect _entries_WIRE_16.sw, _entries_T_206
node _entries_T_207 = bits(_entries_WIRE_17, 15, 15)
connect _entries_WIRE_16.gf, _entries_T_207
node _entries_T_208 = bits(_entries_WIRE_17, 16, 16)
connect _entries_WIRE_16.pf, _entries_T_208
node _entries_T_209 = bits(_entries_WIRE_17, 17, 17)
connect _entries_WIRE_16.ae_stage2, _entries_T_209
node _entries_T_210 = bits(_entries_WIRE_17, 18, 18)
connect _entries_WIRE_16.ae_final, _entries_T_210
node _entries_T_211 = bits(_entries_WIRE_17, 19, 19)
connect _entries_WIRE_16.ae_ptw, _entries_T_211
node _entries_T_212 = bits(_entries_WIRE_17, 20, 20)
connect _entries_WIRE_16.g, _entries_T_212
node _entries_T_213 = bits(_entries_WIRE_17, 21, 21)
connect _entries_WIRE_16.u, _entries_T_213
node _entries_T_214 = bits(_entries_WIRE_17, 41, 22)
connect _entries_WIRE_16.ppn, _entries_T_214
inst entries_barrier_8 of OptimizationBarrier_TLBEntryData_9
connect entries_barrier_8.clock, clock
connect entries_barrier_8.reset, reset
connect entries_barrier_8.io.x.fragmented_superpage, _entries_WIRE_16.fragmented_superpage
connect entries_barrier_8.io.x.c, _entries_WIRE_16.c
connect entries_barrier_8.io.x.eff, _entries_WIRE_16.eff
connect entries_barrier_8.io.x.paa, _entries_WIRE_16.paa
connect entries_barrier_8.io.x.pal, _entries_WIRE_16.pal
connect entries_barrier_8.io.x.ppp, _entries_WIRE_16.ppp
connect entries_barrier_8.io.x.pr, _entries_WIRE_16.pr
connect entries_barrier_8.io.x.px, _entries_WIRE_16.px
connect entries_barrier_8.io.x.pw, _entries_WIRE_16.pw
connect entries_barrier_8.io.x.hr, _entries_WIRE_16.hr
connect entries_barrier_8.io.x.hx, _entries_WIRE_16.hx
connect entries_barrier_8.io.x.hw, _entries_WIRE_16.hw
connect entries_barrier_8.io.x.sr, _entries_WIRE_16.sr
connect entries_barrier_8.io.x.sx, _entries_WIRE_16.sx
connect entries_barrier_8.io.x.sw, _entries_WIRE_16.sw
connect entries_barrier_8.io.x.gf, _entries_WIRE_16.gf
connect entries_barrier_8.io.x.pf, _entries_WIRE_16.pf
connect entries_barrier_8.io.x.ae_stage2, _entries_WIRE_16.ae_stage2
connect entries_barrier_8.io.x.ae_final, _entries_WIRE_16.ae_final
connect entries_barrier_8.io.x.ae_ptw, _entries_WIRE_16.ae_ptw
connect entries_barrier_8.io.x.g, _entries_WIRE_16.g
connect entries_barrier_8.io.x.u, _entries_WIRE_16.u
connect entries_barrier_8.io.x.ppn, _entries_WIRE_16.ppn
wire _entries_WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_19 : UInt<42>
connect _entries_WIRE_19, superpage_entries[1].data[0]
node _entries_T_215 = bits(_entries_WIRE_19, 0, 0)
connect _entries_WIRE_18.fragmented_superpage, _entries_T_215
node _entries_T_216 = bits(_entries_WIRE_19, 1, 1)
connect _entries_WIRE_18.c, _entries_T_216
node _entries_T_217 = bits(_entries_WIRE_19, 2, 2)
connect _entries_WIRE_18.eff, _entries_T_217
node _entries_T_218 = bits(_entries_WIRE_19, 3, 3)
connect _entries_WIRE_18.paa, _entries_T_218
node _entries_T_219 = bits(_entries_WIRE_19, 4, 4)
connect _entries_WIRE_18.pal, _entries_T_219
node _entries_T_220 = bits(_entries_WIRE_19, 5, 5)
connect _entries_WIRE_18.ppp, _entries_T_220
node _entries_T_221 = bits(_entries_WIRE_19, 6, 6)
connect _entries_WIRE_18.pr, _entries_T_221
node _entries_T_222 = bits(_entries_WIRE_19, 7, 7)
connect _entries_WIRE_18.px, _entries_T_222
node _entries_T_223 = bits(_entries_WIRE_19, 8, 8)
connect _entries_WIRE_18.pw, _entries_T_223
node _entries_T_224 = bits(_entries_WIRE_19, 9, 9)
connect _entries_WIRE_18.hr, _entries_T_224
node _entries_T_225 = bits(_entries_WIRE_19, 10, 10)
connect _entries_WIRE_18.hx, _entries_T_225
node _entries_T_226 = bits(_entries_WIRE_19, 11, 11)
connect _entries_WIRE_18.hw, _entries_T_226
node _entries_T_227 = bits(_entries_WIRE_19, 12, 12)
connect _entries_WIRE_18.sr, _entries_T_227
node _entries_T_228 = bits(_entries_WIRE_19, 13, 13)
connect _entries_WIRE_18.sx, _entries_T_228
node _entries_T_229 = bits(_entries_WIRE_19, 14, 14)
connect _entries_WIRE_18.sw, _entries_T_229
node _entries_T_230 = bits(_entries_WIRE_19, 15, 15)
connect _entries_WIRE_18.gf, _entries_T_230
node _entries_T_231 = bits(_entries_WIRE_19, 16, 16)
connect _entries_WIRE_18.pf, _entries_T_231
node _entries_T_232 = bits(_entries_WIRE_19, 17, 17)
connect _entries_WIRE_18.ae_stage2, _entries_T_232
node _entries_T_233 = bits(_entries_WIRE_19, 18, 18)
connect _entries_WIRE_18.ae_final, _entries_T_233
node _entries_T_234 = bits(_entries_WIRE_19, 19, 19)
connect _entries_WIRE_18.ae_ptw, _entries_T_234
node _entries_T_235 = bits(_entries_WIRE_19, 20, 20)
connect _entries_WIRE_18.g, _entries_T_235
node _entries_T_236 = bits(_entries_WIRE_19, 21, 21)
connect _entries_WIRE_18.u, _entries_T_236
node _entries_T_237 = bits(_entries_WIRE_19, 41, 22)
connect _entries_WIRE_18.ppn, _entries_T_237
inst entries_barrier_9 of OptimizationBarrier_TLBEntryData_10
connect entries_barrier_9.clock, clock
connect entries_barrier_9.reset, reset
connect entries_barrier_9.io.x.fragmented_superpage, _entries_WIRE_18.fragmented_superpage
connect entries_barrier_9.io.x.c, _entries_WIRE_18.c
connect entries_barrier_9.io.x.eff, _entries_WIRE_18.eff
connect entries_barrier_9.io.x.paa, _entries_WIRE_18.paa
connect entries_barrier_9.io.x.pal, _entries_WIRE_18.pal
connect entries_barrier_9.io.x.ppp, _entries_WIRE_18.ppp
connect entries_barrier_9.io.x.pr, _entries_WIRE_18.pr
connect entries_barrier_9.io.x.px, _entries_WIRE_18.px
connect entries_barrier_9.io.x.pw, _entries_WIRE_18.pw
connect entries_barrier_9.io.x.hr, _entries_WIRE_18.hr
connect entries_barrier_9.io.x.hx, _entries_WIRE_18.hx
connect entries_barrier_9.io.x.hw, _entries_WIRE_18.hw
connect entries_barrier_9.io.x.sr, _entries_WIRE_18.sr
connect entries_barrier_9.io.x.sx, _entries_WIRE_18.sx
connect entries_barrier_9.io.x.sw, _entries_WIRE_18.sw
connect entries_barrier_9.io.x.gf, _entries_WIRE_18.gf
connect entries_barrier_9.io.x.pf, _entries_WIRE_18.pf
connect entries_barrier_9.io.x.ae_stage2, _entries_WIRE_18.ae_stage2
connect entries_barrier_9.io.x.ae_final, _entries_WIRE_18.ae_final
connect entries_barrier_9.io.x.ae_ptw, _entries_WIRE_18.ae_ptw
connect entries_barrier_9.io.x.g, _entries_WIRE_18.g
connect entries_barrier_9.io.x.u, _entries_WIRE_18.u
connect entries_barrier_9.io.x.ppn, _entries_WIRE_18.ppn
wire _entries_WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_21 : UInt<42>
connect _entries_WIRE_21, superpage_entries[2].data[0]
node _entries_T_238 = bits(_entries_WIRE_21, 0, 0)
connect _entries_WIRE_20.fragmented_superpage, _entries_T_238
node _entries_T_239 = bits(_entries_WIRE_21, 1, 1)
connect _entries_WIRE_20.c, _entries_T_239
node _entries_T_240 = bits(_entries_WIRE_21, 2, 2)
connect _entries_WIRE_20.eff, _entries_T_240
node _entries_T_241 = bits(_entries_WIRE_21, 3, 3)
connect _entries_WIRE_20.paa, _entries_T_241
node _entries_T_242 = bits(_entries_WIRE_21, 4, 4)
connect _entries_WIRE_20.pal, _entries_T_242
node _entries_T_243 = bits(_entries_WIRE_21, 5, 5)
connect _entries_WIRE_20.ppp, _entries_T_243
node _entries_T_244 = bits(_entries_WIRE_21, 6, 6)
connect _entries_WIRE_20.pr, _entries_T_244
node _entries_T_245 = bits(_entries_WIRE_21, 7, 7)
connect _entries_WIRE_20.px, _entries_T_245
node _entries_T_246 = bits(_entries_WIRE_21, 8, 8)
connect _entries_WIRE_20.pw, _entries_T_246
node _entries_T_247 = bits(_entries_WIRE_21, 9, 9)
connect _entries_WIRE_20.hr, _entries_T_247
node _entries_T_248 = bits(_entries_WIRE_21, 10, 10)
connect _entries_WIRE_20.hx, _entries_T_248
node _entries_T_249 = bits(_entries_WIRE_21, 11, 11)
connect _entries_WIRE_20.hw, _entries_T_249
node _entries_T_250 = bits(_entries_WIRE_21, 12, 12)
connect _entries_WIRE_20.sr, _entries_T_250
node _entries_T_251 = bits(_entries_WIRE_21, 13, 13)
connect _entries_WIRE_20.sx, _entries_T_251
node _entries_T_252 = bits(_entries_WIRE_21, 14, 14)
connect _entries_WIRE_20.sw, _entries_T_252
node _entries_T_253 = bits(_entries_WIRE_21, 15, 15)
connect _entries_WIRE_20.gf, _entries_T_253
node _entries_T_254 = bits(_entries_WIRE_21, 16, 16)
connect _entries_WIRE_20.pf, _entries_T_254
node _entries_T_255 = bits(_entries_WIRE_21, 17, 17)
connect _entries_WIRE_20.ae_stage2, _entries_T_255
node _entries_T_256 = bits(_entries_WIRE_21, 18, 18)
connect _entries_WIRE_20.ae_final, _entries_T_256
node _entries_T_257 = bits(_entries_WIRE_21, 19, 19)
connect _entries_WIRE_20.ae_ptw, _entries_T_257
node _entries_T_258 = bits(_entries_WIRE_21, 20, 20)
connect _entries_WIRE_20.g, _entries_T_258
node _entries_T_259 = bits(_entries_WIRE_21, 21, 21)
connect _entries_WIRE_20.u, _entries_T_259
node _entries_T_260 = bits(_entries_WIRE_21, 41, 22)
connect _entries_WIRE_20.ppn, _entries_T_260
inst entries_barrier_10 of OptimizationBarrier_TLBEntryData_11
connect entries_barrier_10.clock, clock
connect entries_barrier_10.reset, reset
connect entries_barrier_10.io.x.fragmented_superpage, _entries_WIRE_20.fragmented_superpage
connect entries_barrier_10.io.x.c, _entries_WIRE_20.c
connect entries_barrier_10.io.x.eff, _entries_WIRE_20.eff
connect entries_barrier_10.io.x.paa, _entries_WIRE_20.paa
connect entries_barrier_10.io.x.pal, _entries_WIRE_20.pal
connect entries_barrier_10.io.x.ppp, _entries_WIRE_20.ppp
connect entries_barrier_10.io.x.pr, _entries_WIRE_20.pr
connect entries_barrier_10.io.x.px, _entries_WIRE_20.px
connect entries_barrier_10.io.x.pw, _entries_WIRE_20.pw
connect entries_barrier_10.io.x.hr, _entries_WIRE_20.hr
connect entries_barrier_10.io.x.hx, _entries_WIRE_20.hx
connect entries_barrier_10.io.x.hw, _entries_WIRE_20.hw
connect entries_barrier_10.io.x.sr, _entries_WIRE_20.sr
connect entries_barrier_10.io.x.sx, _entries_WIRE_20.sx
connect entries_barrier_10.io.x.sw, _entries_WIRE_20.sw
connect entries_barrier_10.io.x.gf, _entries_WIRE_20.gf
connect entries_barrier_10.io.x.pf, _entries_WIRE_20.pf
connect entries_barrier_10.io.x.ae_stage2, _entries_WIRE_20.ae_stage2
connect entries_barrier_10.io.x.ae_final, _entries_WIRE_20.ae_final
connect entries_barrier_10.io.x.ae_ptw, _entries_WIRE_20.ae_ptw
connect entries_barrier_10.io.x.g, _entries_WIRE_20.g
connect entries_barrier_10.io.x.u, _entries_WIRE_20.u
connect entries_barrier_10.io.x.ppn, _entries_WIRE_20.ppn
wire _entries_WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_23 : UInt<42>
connect _entries_WIRE_23, superpage_entries[3].data[0]
node _entries_T_261 = bits(_entries_WIRE_23, 0, 0)
connect _entries_WIRE_22.fragmented_superpage, _entries_T_261
node _entries_T_262 = bits(_entries_WIRE_23, 1, 1)
connect _entries_WIRE_22.c, _entries_T_262
node _entries_T_263 = bits(_entries_WIRE_23, 2, 2)
connect _entries_WIRE_22.eff, _entries_T_263
node _entries_T_264 = bits(_entries_WIRE_23, 3, 3)
connect _entries_WIRE_22.paa, _entries_T_264
node _entries_T_265 = bits(_entries_WIRE_23, 4, 4)
connect _entries_WIRE_22.pal, _entries_T_265
node _entries_T_266 = bits(_entries_WIRE_23, 5, 5)
connect _entries_WIRE_22.ppp, _entries_T_266
node _entries_T_267 = bits(_entries_WIRE_23, 6, 6)
connect _entries_WIRE_22.pr, _entries_T_267
node _entries_T_268 = bits(_entries_WIRE_23, 7, 7)
connect _entries_WIRE_22.px, _entries_T_268
node _entries_T_269 = bits(_entries_WIRE_23, 8, 8)
connect _entries_WIRE_22.pw, _entries_T_269
node _entries_T_270 = bits(_entries_WIRE_23, 9, 9)
connect _entries_WIRE_22.hr, _entries_T_270
node _entries_T_271 = bits(_entries_WIRE_23, 10, 10)
connect _entries_WIRE_22.hx, _entries_T_271
node _entries_T_272 = bits(_entries_WIRE_23, 11, 11)
connect _entries_WIRE_22.hw, _entries_T_272
node _entries_T_273 = bits(_entries_WIRE_23, 12, 12)
connect _entries_WIRE_22.sr, _entries_T_273
node _entries_T_274 = bits(_entries_WIRE_23, 13, 13)
connect _entries_WIRE_22.sx, _entries_T_274
node _entries_T_275 = bits(_entries_WIRE_23, 14, 14)
connect _entries_WIRE_22.sw, _entries_T_275
node _entries_T_276 = bits(_entries_WIRE_23, 15, 15)
connect _entries_WIRE_22.gf, _entries_T_276
node _entries_T_277 = bits(_entries_WIRE_23, 16, 16)
connect _entries_WIRE_22.pf, _entries_T_277
node _entries_T_278 = bits(_entries_WIRE_23, 17, 17)
connect _entries_WIRE_22.ae_stage2, _entries_T_278
node _entries_T_279 = bits(_entries_WIRE_23, 18, 18)
connect _entries_WIRE_22.ae_final, _entries_T_279
node _entries_T_280 = bits(_entries_WIRE_23, 19, 19)
connect _entries_WIRE_22.ae_ptw, _entries_T_280
node _entries_T_281 = bits(_entries_WIRE_23, 20, 20)
connect _entries_WIRE_22.g, _entries_T_281
node _entries_T_282 = bits(_entries_WIRE_23, 21, 21)
connect _entries_WIRE_22.u, _entries_T_282
node _entries_T_283 = bits(_entries_WIRE_23, 41, 22)
connect _entries_WIRE_22.ppn, _entries_T_283
inst entries_barrier_11 of OptimizationBarrier_TLBEntryData_12
connect entries_barrier_11.clock, clock
connect entries_barrier_11.reset, reset
connect entries_barrier_11.io.x.fragmented_superpage, _entries_WIRE_22.fragmented_superpage
connect entries_barrier_11.io.x.c, _entries_WIRE_22.c
connect entries_barrier_11.io.x.eff, _entries_WIRE_22.eff
connect entries_barrier_11.io.x.paa, _entries_WIRE_22.paa
connect entries_barrier_11.io.x.pal, _entries_WIRE_22.pal
connect entries_barrier_11.io.x.ppp, _entries_WIRE_22.ppp
connect entries_barrier_11.io.x.pr, _entries_WIRE_22.pr
connect entries_barrier_11.io.x.px, _entries_WIRE_22.px
connect entries_barrier_11.io.x.pw, _entries_WIRE_22.pw
connect entries_barrier_11.io.x.hr, _entries_WIRE_22.hr
connect entries_barrier_11.io.x.hx, _entries_WIRE_22.hx
connect entries_barrier_11.io.x.hw, _entries_WIRE_22.hw
connect entries_barrier_11.io.x.sr, _entries_WIRE_22.sr
connect entries_barrier_11.io.x.sx, _entries_WIRE_22.sx
connect entries_barrier_11.io.x.sw, _entries_WIRE_22.sw
connect entries_barrier_11.io.x.gf, _entries_WIRE_22.gf
connect entries_barrier_11.io.x.pf, _entries_WIRE_22.pf
connect entries_barrier_11.io.x.ae_stage2, _entries_WIRE_22.ae_stage2
connect entries_barrier_11.io.x.ae_final, _entries_WIRE_22.ae_final
connect entries_barrier_11.io.x.ae_ptw, _entries_WIRE_22.ae_ptw
connect entries_barrier_11.io.x.g, _entries_WIRE_22.g
connect entries_barrier_11.io.x.u, _entries_WIRE_22.u
connect entries_barrier_11.io.x.ppn, _entries_WIRE_22.ppn
wire _entries_WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _entries_WIRE_25 : UInt<42>
connect _entries_WIRE_25, special_entry.data[0]
node _entries_T_284 = bits(_entries_WIRE_25, 0, 0)
connect _entries_WIRE_24.fragmented_superpage, _entries_T_284
node _entries_T_285 = bits(_entries_WIRE_25, 1, 1)
connect _entries_WIRE_24.c, _entries_T_285
node _entries_T_286 = bits(_entries_WIRE_25, 2, 2)
connect _entries_WIRE_24.eff, _entries_T_286
node _entries_T_287 = bits(_entries_WIRE_25, 3, 3)
connect _entries_WIRE_24.paa, _entries_T_287
node _entries_T_288 = bits(_entries_WIRE_25, 4, 4)
connect _entries_WIRE_24.pal, _entries_T_288
node _entries_T_289 = bits(_entries_WIRE_25, 5, 5)
connect _entries_WIRE_24.ppp, _entries_T_289
node _entries_T_290 = bits(_entries_WIRE_25, 6, 6)
connect _entries_WIRE_24.pr, _entries_T_290
node _entries_T_291 = bits(_entries_WIRE_25, 7, 7)
connect _entries_WIRE_24.px, _entries_T_291
node _entries_T_292 = bits(_entries_WIRE_25, 8, 8)
connect _entries_WIRE_24.pw, _entries_T_292
node _entries_T_293 = bits(_entries_WIRE_25, 9, 9)
connect _entries_WIRE_24.hr, _entries_T_293
node _entries_T_294 = bits(_entries_WIRE_25, 10, 10)
connect _entries_WIRE_24.hx, _entries_T_294
node _entries_T_295 = bits(_entries_WIRE_25, 11, 11)
connect _entries_WIRE_24.hw, _entries_T_295
node _entries_T_296 = bits(_entries_WIRE_25, 12, 12)
connect _entries_WIRE_24.sr, _entries_T_296
node _entries_T_297 = bits(_entries_WIRE_25, 13, 13)
connect _entries_WIRE_24.sx, _entries_T_297
node _entries_T_298 = bits(_entries_WIRE_25, 14, 14)
connect _entries_WIRE_24.sw, _entries_T_298
node _entries_T_299 = bits(_entries_WIRE_25, 15, 15)
connect _entries_WIRE_24.gf, _entries_T_299
node _entries_T_300 = bits(_entries_WIRE_25, 16, 16)
connect _entries_WIRE_24.pf, _entries_T_300
node _entries_T_301 = bits(_entries_WIRE_25, 17, 17)
connect _entries_WIRE_24.ae_stage2, _entries_T_301
node _entries_T_302 = bits(_entries_WIRE_25, 18, 18)
connect _entries_WIRE_24.ae_final, _entries_T_302
node _entries_T_303 = bits(_entries_WIRE_25, 19, 19)
connect _entries_WIRE_24.ae_ptw, _entries_T_303
node _entries_T_304 = bits(_entries_WIRE_25, 20, 20)
connect _entries_WIRE_24.g, _entries_T_304
node _entries_T_305 = bits(_entries_WIRE_25, 21, 21)
connect _entries_WIRE_24.u, _entries_T_305
node _entries_T_306 = bits(_entries_WIRE_25, 41, 22)
connect _entries_WIRE_24.ppn, _entries_T_306
inst entries_barrier_12 of OptimizationBarrier_TLBEntryData_13
connect entries_barrier_12.clock, clock
connect entries_barrier_12.reset, reset
connect entries_barrier_12.io.x.fragmented_superpage, _entries_WIRE_24.fragmented_superpage
connect entries_barrier_12.io.x.c, _entries_WIRE_24.c
connect entries_barrier_12.io.x.eff, _entries_WIRE_24.eff
connect entries_barrier_12.io.x.paa, _entries_WIRE_24.paa
connect entries_barrier_12.io.x.pal, _entries_WIRE_24.pal
connect entries_barrier_12.io.x.ppp, _entries_WIRE_24.ppp
connect entries_barrier_12.io.x.pr, _entries_WIRE_24.pr
connect entries_barrier_12.io.x.px, _entries_WIRE_24.px
connect entries_barrier_12.io.x.pw, _entries_WIRE_24.pw
connect entries_barrier_12.io.x.hr, _entries_WIRE_24.hr
connect entries_barrier_12.io.x.hx, _entries_WIRE_24.hx
connect entries_barrier_12.io.x.hw, _entries_WIRE_24.hw
connect entries_barrier_12.io.x.sr, _entries_WIRE_24.sr
connect entries_barrier_12.io.x.sx, _entries_WIRE_24.sx
connect entries_barrier_12.io.x.sw, _entries_WIRE_24.sw
connect entries_barrier_12.io.x.gf, _entries_WIRE_24.gf
connect entries_barrier_12.io.x.pf, _entries_WIRE_24.pf
connect entries_barrier_12.io.x.ae_stage2, _entries_WIRE_24.ae_stage2
connect entries_barrier_12.io.x.ae_final, _entries_WIRE_24.ae_final
connect entries_barrier_12.io.x.ae_ptw, _entries_WIRE_24.ae_ptw
connect entries_barrier_12.io.x.g, _entries_WIRE_24.g
connect entries_barrier_12.io.x.u, _entries_WIRE_24.u
connect entries_barrier_12.io.x.ppn, _entries_WIRE_24.ppn
node _ppn_T = eq(vm_enabled, UInt<1>(0h0))
node ppn_res = shr(entries_barrier_8.io.y.ppn, 18)
node _ppn_ignore_T = lt(superpage_entries[0].level, UInt<1>(0h1))
node ppn_ignore = or(_ppn_ignore_T, UInt<1>(0h0))
node _ppn_T_1 = mux(ppn_ignore, vpn, UInt<1>(0h0))
node _ppn_T_2 = or(_ppn_T_1, entries_barrier_8.io.y.ppn)
node _ppn_T_3 = bits(_ppn_T_2, 17, 9)
node _ppn_T_4 = cat(ppn_res, _ppn_T_3)
node _ppn_ignore_T_1 = lt(superpage_entries[0].level, UInt<2>(0h2))
node ppn_ignore_1 = or(_ppn_ignore_T_1, UInt<1>(0h1))
node _ppn_T_5 = mux(ppn_ignore_1, vpn, UInt<1>(0h0))
node _ppn_T_6 = or(_ppn_T_5, entries_barrier_8.io.y.ppn)
node _ppn_T_7 = bits(_ppn_T_6, 8, 0)
node _ppn_T_8 = cat(_ppn_T_4, _ppn_T_7)
node ppn_res_1 = shr(entries_barrier_9.io.y.ppn, 18)
node _ppn_ignore_T_2 = lt(superpage_entries[1].level, UInt<1>(0h1))
node ppn_ignore_2 = or(_ppn_ignore_T_2, UInt<1>(0h0))
node _ppn_T_9 = mux(ppn_ignore_2, vpn, UInt<1>(0h0))
node _ppn_T_10 = or(_ppn_T_9, entries_barrier_9.io.y.ppn)
node _ppn_T_11 = bits(_ppn_T_10, 17, 9)
node _ppn_T_12 = cat(ppn_res_1, _ppn_T_11)
node _ppn_ignore_T_3 = lt(superpage_entries[1].level, UInt<2>(0h2))
node ppn_ignore_3 = or(_ppn_ignore_T_3, UInt<1>(0h1))
node _ppn_T_13 = mux(ppn_ignore_3, vpn, UInt<1>(0h0))
node _ppn_T_14 = or(_ppn_T_13, entries_barrier_9.io.y.ppn)
node _ppn_T_15 = bits(_ppn_T_14, 8, 0)
node _ppn_T_16 = cat(_ppn_T_12, _ppn_T_15)
node ppn_res_2 = shr(entries_barrier_10.io.y.ppn, 18)
node _ppn_ignore_T_4 = lt(superpage_entries[2].level, UInt<1>(0h1))
node ppn_ignore_4 = or(_ppn_ignore_T_4, UInt<1>(0h0))
node _ppn_T_17 = mux(ppn_ignore_4, vpn, UInt<1>(0h0))
node _ppn_T_18 = or(_ppn_T_17, entries_barrier_10.io.y.ppn)
node _ppn_T_19 = bits(_ppn_T_18, 17, 9)
node _ppn_T_20 = cat(ppn_res_2, _ppn_T_19)
node _ppn_ignore_T_5 = lt(superpage_entries[2].level, UInt<2>(0h2))
node ppn_ignore_5 = or(_ppn_ignore_T_5, UInt<1>(0h1))
node _ppn_T_21 = mux(ppn_ignore_5, vpn, UInt<1>(0h0))
node _ppn_T_22 = or(_ppn_T_21, entries_barrier_10.io.y.ppn)
node _ppn_T_23 = bits(_ppn_T_22, 8, 0)
node _ppn_T_24 = cat(_ppn_T_20, _ppn_T_23)
node ppn_res_3 = shr(entries_barrier_11.io.y.ppn, 18)
node _ppn_ignore_T_6 = lt(superpage_entries[3].level, UInt<1>(0h1))
node ppn_ignore_6 = or(_ppn_ignore_T_6, UInt<1>(0h0))
node _ppn_T_25 = mux(ppn_ignore_6, vpn, UInt<1>(0h0))
node _ppn_T_26 = or(_ppn_T_25, entries_barrier_11.io.y.ppn)
node _ppn_T_27 = bits(_ppn_T_26, 17, 9)
node _ppn_T_28 = cat(ppn_res_3, _ppn_T_27)
node _ppn_ignore_T_7 = lt(superpage_entries[3].level, UInt<2>(0h2))
node ppn_ignore_7 = or(_ppn_ignore_T_7, UInt<1>(0h1))
node _ppn_T_29 = mux(ppn_ignore_7, vpn, UInt<1>(0h0))
node _ppn_T_30 = or(_ppn_T_29, entries_barrier_11.io.y.ppn)
node _ppn_T_31 = bits(_ppn_T_30, 8, 0)
node _ppn_T_32 = cat(_ppn_T_28, _ppn_T_31)
node ppn_res_4 = shr(entries_barrier_12.io.y.ppn, 18)
node _ppn_ignore_T_8 = lt(special_entry.level, UInt<1>(0h1))
node ppn_ignore_8 = or(_ppn_ignore_T_8, UInt<1>(0h0))
node _ppn_T_33 = mux(ppn_ignore_8, vpn, UInt<1>(0h0))
node _ppn_T_34 = or(_ppn_T_33, entries_barrier_12.io.y.ppn)
node _ppn_T_35 = bits(_ppn_T_34, 17, 9)
node _ppn_T_36 = cat(ppn_res_4, _ppn_T_35)
node _ppn_ignore_T_9 = lt(special_entry.level, UInt<2>(0h2))
node ppn_ignore_9 = or(_ppn_ignore_T_9, UInt<1>(0h0))
node _ppn_T_37 = mux(ppn_ignore_9, vpn, UInt<1>(0h0))
node _ppn_T_38 = or(_ppn_T_37, entries_barrier_12.io.y.ppn)
node _ppn_T_39 = bits(_ppn_T_38, 8, 0)
node _ppn_T_40 = cat(_ppn_T_36, _ppn_T_39)
node _ppn_T_41 = bits(vpn, 19, 0)
node _ppn_T_42 = mux(hitsVec_0, entries_barrier.io.y.ppn, UInt<1>(0h0))
node _ppn_T_43 = mux(hitsVec_1, entries_barrier_1.io.y.ppn, UInt<1>(0h0))
node _ppn_T_44 = mux(hitsVec_2, entries_barrier_2.io.y.ppn, UInt<1>(0h0))
node _ppn_T_45 = mux(hitsVec_3, entries_barrier_3.io.y.ppn, UInt<1>(0h0))
node _ppn_T_46 = mux(hitsVec_4, entries_barrier_4.io.y.ppn, UInt<1>(0h0))
node _ppn_T_47 = mux(hitsVec_5, entries_barrier_5.io.y.ppn, UInt<1>(0h0))
node _ppn_T_48 = mux(hitsVec_6, entries_barrier_6.io.y.ppn, UInt<1>(0h0))
node _ppn_T_49 = mux(hitsVec_7, entries_barrier_7.io.y.ppn, UInt<1>(0h0))
node _ppn_T_50 = mux(hitsVec_8, _ppn_T_8, UInt<1>(0h0))
node _ppn_T_51 = mux(hitsVec_9, _ppn_T_16, UInt<1>(0h0))
node _ppn_T_52 = mux(hitsVec_10, _ppn_T_24, UInt<1>(0h0))
node _ppn_T_53 = mux(hitsVec_11, _ppn_T_32, UInt<1>(0h0))
node _ppn_T_54 = mux(hitsVec_12, _ppn_T_40, UInt<1>(0h0))
node _ppn_T_55 = mux(_ppn_T, _ppn_T_41, UInt<1>(0h0))
node _ppn_T_56 = or(_ppn_T_42, _ppn_T_43)
node _ppn_T_57 = or(_ppn_T_56, _ppn_T_44)
node _ppn_T_58 = or(_ppn_T_57, _ppn_T_45)
node _ppn_T_59 = or(_ppn_T_58, _ppn_T_46)
node _ppn_T_60 = or(_ppn_T_59, _ppn_T_47)
node _ppn_T_61 = or(_ppn_T_60, _ppn_T_48)
node _ppn_T_62 = or(_ppn_T_61, _ppn_T_49)
node _ppn_T_63 = or(_ppn_T_62, _ppn_T_50)
node _ppn_T_64 = or(_ppn_T_63, _ppn_T_51)
node _ppn_T_65 = or(_ppn_T_64, _ppn_T_52)
node _ppn_T_66 = or(_ppn_T_65, _ppn_T_53)
node _ppn_T_67 = or(_ppn_T_66, _ppn_T_54)
node _ppn_T_68 = or(_ppn_T_67, _ppn_T_55)
wire ppn : UInt<20>
connect ppn, _ppn_T_68
node ptw_ae_array_lo_lo_hi = cat(entries_barrier_2.io.y.ae_ptw, entries_barrier_1.io.y.ae_ptw)
node ptw_ae_array_lo_lo = cat(ptw_ae_array_lo_lo_hi, entries_barrier.io.y.ae_ptw)
node ptw_ae_array_lo_hi_hi = cat(entries_barrier_5.io.y.ae_ptw, entries_barrier_4.io.y.ae_ptw)
node ptw_ae_array_lo_hi = cat(ptw_ae_array_lo_hi_hi, entries_barrier_3.io.y.ae_ptw)
node ptw_ae_array_lo = cat(ptw_ae_array_lo_hi, ptw_ae_array_lo_lo)
node ptw_ae_array_hi_lo_hi = cat(entries_barrier_8.io.y.ae_ptw, entries_barrier_7.io.y.ae_ptw)
node ptw_ae_array_hi_lo = cat(ptw_ae_array_hi_lo_hi, entries_barrier_6.io.y.ae_ptw)
node ptw_ae_array_hi_hi_lo = cat(entries_barrier_10.io.y.ae_ptw, entries_barrier_9.io.y.ae_ptw)
node ptw_ae_array_hi_hi_hi = cat(entries_barrier_12.io.y.ae_ptw, entries_barrier_11.io.y.ae_ptw)
node ptw_ae_array_hi_hi = cat(ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo)
node ptw_ae_array_hi = cat(ptw_ae_array_hi_hi, ptw_ae_array_hi_lo)
node _ptw_ae_array_T = cat(ptw_ae_array_hi, ptw_ae_array_lo)
node ptw_ae_array = cat(UInt<1>(0h0), _ptw_ae_array_T)
node final_ae_array_lo_lo_hi = cat(entries_barrier_2.io.y.ae_final, entries_barrier_1.io.y.ae_final)
node final_ae_array_lo_lo = cat(final_ae_array_lo_lo_hi, entries_barrier.io.y.ae_final)
node final_ae_array_lo_hi_hi = cat(entries_barrier_5.io.y.ae_final, entries_barrier_4.io.y.ae_final)
node final_ae_array_lo_hi = cat(final_ae_array_lo_hi_hi, entries_barrier_3.io.y.ae_final)
node final_ae_array_lo = cat(final_ae_array_lo_hi, final_ae_array_lo_lo)
node final_ae_array_hi_lo_hi = cat(entries_barrier_8.io.y.ae_final, entries_barrier_7.io.y.ae_final)
node final_ae_array_hi_lo = cat(final_ae_array_hi_lo_hi, entries_barrier_6.io.y.ae_final)
node final_ae_array_hi_hi_lo = cat(entries_barrier_10.io.y.ae_final, entries_barrier_9.io.y.ae_final)
node final_ae_array_hi_hi_hi = cat(entries_barrier_12.io.y.ae_final, entries_barrier_11.io.y.ae_final)
node final_ae_array_hi_hi = cat(final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo)
node final_ae_array_hi = cat(final_ae_array_hi_hi, final_ae_array_hi_lo)
node _final_ae_array_T = cat(final_ae_array_hi, final_ae_array_lo)
node final_ae_array = cat(UInt<1>(0h0), _final_ae_array_T)
node ptw_pf_array_lo_lo_hi = cat(entries_barrier_2.io.y.pf, entries_barrier_1.io.y.pf)
node ptw_pf_array_lo_lo = cat(ptw_pf_array_lo_lo_hi, entries_barrier.io.y.pf)
node ptw_pf_array_lo_hi_hi = cat(entries_barrier_5.io.y.pf, entries_barrier_4.io.y.pf)
node ptw_pf_array_lo_hi = cat(ptw_pf_array_lo_hi_hi, entries_barrier_3.io.y.pf)
node ptw_pf_array_lo = cat(ptw_pf_array_lo_hi, ptw_pf_array_lo_lo)
node ptw_pf_array_hi_lo_hi = cat(entries_barrier_8.io.y.pf, entries_barrier_7.io.y.pf)
node ptw_pf_array_hi_lo = cat(ptw_pf_array_hi_lo_hi, entries_barrier_6.io.y.pf)
node ptw_pf_array_hi_hi_lo = cat(entries_barrier_10.io.y.pf, entries_barrier_9.io.y.pf)
node ptw_pf_array_hi_hi_hi = cat(entries_barrier_12.io.y.pf, entries_barrier_11.io.y.pf)
node ptw_pf_array_hi_hi = cat(ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo)
node ptw_pf_array_hi = cat(ptw_pf_array_hi_hi, ptw_pf_array_hi_lo)
node _ptw_pf_array_T = cat(ptw_pf_array_hi, ptw_pf_array_lo)
node ptw_pf_array = cat(UInt<1>(0h0), _ptw_pf_array_T)
node ptw_gf_array_lo_lo_hi = cat(entries_barrier_2.io.y.gf, entries_barrier_1.io.y.gf)
node ptw_gf_array_lo_lo = cat(ptw_gf_array_lo_lo_hi, entries_barrier.io.y.gf)
node ptw_gf_array_lo_hi_hi = cat(entries_barrier_5.io.y.gf, entries_barrier_4.io.y.gf)
node ptw_gf_array_lo_hi = cat(ptw_gf_array_lo_hi_hi, entries_barrier_3.io.y.gf)
node ptw_gf_array_lo = cat(ptw_gf_array_lo_hi, ptw_gf_array_lo_lo)
node ptw_gf_array_hi_lo_hi = cat(entries_barrier_8.io.y.gf, entries_barrier_7.io.y.gf)
node ptw_gf_array_hi_lo = cat(ptw_gf_array_hi_lo_hi, entries_barrier_6.io.y.gf)
node ptw_gf_array_hi_hi_lo = cat(entries_barrier_10.io.y.gf, entries_barrier_9.io.y.gf)
node ptw_gf_array_hi_hi_hi = cat(entries_barrier_12.io.y.gf, entries_barrier_11.io.y.gf)
node ptw_gf_array_hi_hi = cat(ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo)
node ptw_gf_array_hi = cat(ptw_gf_array_hi_hi, ptw_gf_array_hi_lo)
node _ptw_gf_array_T = cat(ptw_gf_array_hi, ptw_gf_array_lo)
node ptw_gf_array = cat(UInt<1>(0h0), _ptw_gf_array_T)
node sum = mux(priv_v, io.ptw.gstatus.sum, io.ptw.status.sum)
node _priv_rw_ok_T = eq(priv_s, UInt<1>(0h0))
node _priv_rw_ok_T_1 = or(_priv_rw_ok_T, sum)
node priv_rw_ok_lo_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u)
node priv_rw_ok_lo_lo = cat(priv_rw_ok_lo_lo_hi, entries_barrier.io.y.u)
node priv_rw_ok_lo_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u)
node priv_rw_ok_lo_hi = cat(priv_rw_ok_lo_hi_hi, entries_barrier_3.io.y.u)
node priv_rw_ok_lo = cat(priv_rw_ok_lo_hi, priv_rw_ok_lo_lo)
node priv_rw_ok_hi_lo_hi = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u)
node priv_rw_ok_hi_lo = cat(priv_rw_ok_hi_lo_hi, entries_barrier_6.io.y.u)
node priv_rw_ok_hi_hi_lo = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u)
node priv_rw_ok_hi_hi_hi = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u)
node priv_rw_ok_hi_hi = cat(priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo)
node priv_rw_ok_hi = cat(priv_rw_ok_hi_hi, priv_rw_ok_hi_lo)
node _priv_rw_ok_T_2 = cat(priv_rw_ok_hi, priv_rw_ok_lo)
node _priv_rw_ok_T_3 = mux(_priv_rw_ok_T_1, _priv_rw_ok_T_2, UInt<1>(0h0))
node priv_rw_ok_lo_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u)
node priv_rw_ok_lo_lo_1 = cat(priv_rw_ok_lo_lo_hi_1, entries_barrier.io.y.u)
node priv_rw_ok_lo_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u)
node priv_rw_ok_lo_hi_1 = cat(priv_rw_ok_lo_hi_hi_1, entries_barrier_3.io.y.u)
node priv_rw_ok_lo_1 = cat(priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1)
node priv_rw_ok_hi_lo_hi_1 = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u)
node priv_rw_ok_hi_lo_1 = cat(priv_rw_ok_hi_lo_hi_1, entries_barrier_6.io.y.u)
node priv_rw_ok_hi_hi_lo_1 = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u)
node priv_rw_ok_hi_hi_hi_1 = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u)
node priv_rw_ok_hi_hi_1 = cat(priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1)
node priv_rw_ok_hi_1 = cat(priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1)
node _priv_rw_ok_T_4 = cat(priv_rw_ok_hi_1, priv_rw_ok_lo_1)
node _priv_rw_ok_T_5 = not(_priv_rw_ok_T_4)
node _priv_rw_ok_T_6 = mux(priv_s, _priv_rw_ok_T_5, UInt<1>(0h0))
node priv_rw_ok = or(_priv_rw_ok_T_3, _priv_rw_ok_T_6)
node priv_x_ok_lo_lo_hi = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u)
node priv_x_ok_lo_lo = cat(priv_x_ok_lo_lo_hi, entries_barrier.io.y.u)
node priv_x_ok_lo_hi_hi = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u)
node priv_x_ok_lo_hi = cat(priv_x_ok_lo_hi_hi, entries_barrier_3.io.y.u)
node priv_x_ok_lo = cat(priv_x_ok_lo_hi, priv_x_ok_lo_lo)
node priv_x_ok_hi_lo_hi = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u)
node priv_x_ok_hi_lo = cat(priv_x_ok_hi_lo_hi, entries_barrier_6.io.y.u)
node priv_x_ok_hi_hi_lo = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u)
node priv_x_ok_hi_hi_hi = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u)
node priv_x_ok_hi_hi = cat(priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo)
node priv_x_ok_hi = cat(priv_x_ok_hi_hi, priv_x_ok_hi_lo)
node _priv_x_ok_T = cat(priv_x_ok_hi, priv_x_ok_lo)
node _priv_x_ok_T_1 = not(_priv_x_ok_T)
node priv_x_ok_lo_lo_hi_1 = cat(entries_barrier_2.io.y.u, entries_barrier_1.io.y.u)
node priv_x_ok_lo_lo_1 = cat(priv_x_ok_lo_lo_hi_1, entries_barrier.io.y.u)
node priv_x_ok_lo_hi_hi_1 = cat(entries_barrier_5.io.y.u, entries_barrier_4.io.y.u)
node priv_x_ok_lo_hi_1 = cat(priv_x_ok_lo_hi_hi_1, entries_barrier_3.io.y.u)
node priv_x_ok_lo_1 = cat(priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1)
node priv_x_ok_hi_lo_hi_1 = cat(entries_barrier_8.io.y.u, entries_barrier_7.io.y.u)
node priv_x_ok_hi_lo_1 = cat(priv_x_ok_hi_lo_hi_1, entries_barrier_6.io.y.u)
node priv_x_ok_hi_hi_lo_1 = cat(entries_barrier_10.io.y.u, entries_barrier_9.io.y.u)
node priv_x_ok_hi_hi_hi_1 = cat(entries_barrier_12.io.y.u, entries_barrier_11.io.y.u)
node priv_x_ok_hi_hi_1 = cat(priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1)
node priv_x_ok_hi_1 = cat(priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1)
node _priv_x_ok_T_2 = cat(priv_x_ok_hi_1, priv_x_ok_lo_1)
node priv_x_ok = mux(priv_s, _priv_x_ok_T_1, _priv_x_ok_T_2)
node _stage1_bypass_T = mux(UInt<1>(0h0), UInt<13>(0h1fff), UInt<13>(0h0))
node _stage1_bypass_T_1 = eq(stage1_en, UInt<1>(0h0))
node _stage1_bypass_T_2 = mux(_stage1_bypass_T_1, UInt<13>(0h1fff), UInt<13>(0h0))
node stage1_bypass_lo_lo_hi = cat(entries_barrier_2.io.y.ae_stage2, entries_barrier_1.io.y.ae_stage2)
node stage1_bypass_lo_lo = cat(stage1_bypass_lo_lo_hi, entries_barrier.io.y.ae_stage2)
node stage1_bypass_lo_hi_hi = cat(entries_barrier_5.io.y.ae_stage2, entries_barrier_4.io.y.ae_stage2)
node stage1_bypass_lo_hi = cat(stage1_bypass_lo_hi_hi, entries_barrier_3.io.y.ae_stage2)
node stage1_bypass_lo = cat(stage1_bypass_lo_hi, stage1_bypass_lo_lo)
node stage1_bypass_hi_lo_hi = cat(entries_barrier_8.io.y.ae_stage2, entries_barrier_7.io.y.ae_stage2)
node stage1_bypass_hi_lo = cat(stage1_bypass_hi_lo_hi, entries_barrier_6.io.y.ae_stage2)
node stage1_bypass_hi_hi_lo = cat(entries_barrier_10.io.y.ae_stage2, entries_barrier_9.io.y.ae_stage2)
node stage1_bypass_hi_hi_hi = cat(entries_barrier_12.io.y.ae_stage2, entries_barrier_11.io.y.ae_stage2)
node stage1_bypass_hi_hi = cat(stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo)
node stage1_bypass_hi = cat(stage1_bypass_hi_hi, stage1_bypass_hi_lo)
node _stage1_bypass_T_3 = cat(stage1_bypass_hi, stage1_bypass_lo)
node _stage1_bypass_T_4 = or(_stage1_bypass_T_2, _stage1_bypass_T_3)
node stage1_bypass = and(_stage1_bypass_T, _stage1_bypass_T_4)
node _mxr_T = mux(priv_v, io.ptw.gstatus.mxr, UInt<1>(0h0))
node mxr = or(io.ptw.status.mxr, _mxr_T)
node r_array_lo_lo_hi = cat(entries_barrier_2.io.y.sr, entries_barrier_1.io.y.sr)
node r_array_lo_lo = cat(r_array_lo_lo_hi, entries_barrier.io.y.sr)
node r_array_lo_hi_hi = cat(entries_barrier_5.io.y.sr, entries_barrier_4.io.y.sr)
node r_array_lo_hi = cat(r_array_lo_hi_hi, entries_barrier_3.io.y.sr)
node r_array_lo = cat(r_array_lo_hi, r_array_lo_lo)
node r_array_hi_lo_hi = cat(entries_barrier_8.io.y.sr, entries_barrier_7.io.y.sr)
node r_array_hi_lo = cat(r_array_hi_lo_hi, entries_barrier_6.io.y.sr)
node r_array_hi_hi_lo = cat(entries_barrier_10.io.y.sr, entries_barrier_9.io.y.sr)
node r_array_hi_hi_hi = cat(entries_barrier_12.io.y.sr, entries_barrier_11.io.y.sr)
node r_array_hi_hi = cat(r_array_hi_hi_hi, r_array_hi_hi_lo)
node r_array_hi = cat(r_array_hi_hi, r_array_hi_lo)
node _r_array_T = cat(r_array_hi, r_array_lo)
node r_array_lo_lo_hi_1 = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx)
node r_array_lo_lo_1 = cat(r_array_lo_lo_hi_1, entries_barrier.io.y.sx)
node r_array_lo_hi_hi_1 = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx)
node r_array_lo_hi_1 = cat(r_array_lo_hi_hi_1, entries_barrier_3.io.y.sx)
node r_array_lo_1 = cat(r_array_lo_hi_1, r_array_lo_lo_1)
node r_array_hi_lo_hi_1 = cat(entries_barrier_8.io.y.sx, entries_barrier_7.io.y.sx)
node r_array_hi_lo_1 = cat(r_array_hi_lo_hi_1, entries_barrier_6.io.y.sx)
node r_array_hi_hi_lo_1 = cat(entries_barrier_10.io.y.sx, entries_barrier_9.io.y.sx)
node r_array_hi_hi_hi_1 = cat(entries_barrier_12.io.y.sx, entries_barrier_11.io.y.sx)
node r_array_hi_hi_1 = cat(r_array_hi_hi_hi_1, r_array_hi_hi_lo_1)
node r_array_hi_1 = cat(r_array_hi_hi_1, r_array_hi_lo_1)
node _r_array_T_1 = cat(r_array_hi_1, r_array_lo_1)
node _r_array_T_2 = mux(mxr, _r_array_T_1, UInt<1>(0h0))
node _r_array_T_3 = or(_r_array_T, _r_array_T_2)
node _r_array_T_4 = and(priv_rw_ok, _r_array_T_3)
node _r_array_T_5 = or(_r_array_T_4, stage1_bypass)
node r_array = cat(UInt<1>(0h1), _r_array_T_5)
node w_array_lo_lo_hi = cat(entries_barrier_2.io.y.sw, entries_barrier_1.io.y.sw)
node w_array_lo_lo = cat(w_array_lo_lo_hi, entries_barrier.io.y.sw)
node w_array_lo_hi_hi = cat(entries_barrier_5.io.y.sw, entries_barrier_4.io.y.sw)
node w_array_lo_hi = cat(w_array_lo_hi_hi, entries_barrier_3.io.y.sw)
node w_array_lo = cat(w_array_lo_hi, w_array_lo_lo)
node w_array_hi_lo_hi = cat(entries_barrier_8.io.y.sw, entries_barrier_7.io.y.sw)
node w_array_hi_lo = cat(w_array_hi_lo_hi, entries_barrier_6.io.y.sw)
node w_array_hi_hi_lo = cat(entries_barrier_10.io.y.sw, entries_barrier_9.io.y.sw)
node w_array_hi_hi_hi = cat(entries_barrier_12.io.y.sw, entries_barrier_11.io.y.sw)
node w_array_hi_hi = cat(w_array_hi_hi_hi, w_array_hi_hi_lo)
node w_array_hi = cat(w_array_hi_hi, w_array_hi_lo)
node _w_array_T = cat(w_array_hi, w_array_lo)
node _w_array_T_1 = and(priv_rw_ok, _w_array_T)
node _w_array_T_2 = or(_w_array_T_1, stage1_bypass)
node w_array = cat(UInt<1>(0h1), _w_array_T_2)
node x_array_lo_lo_hi = cat(entries_barrier_2.io.y.sx, entries_barrier_1.io.y.sx)
node x_array_lo_lo = cat(x_array_lo_lo_hi, entries_barrier.io.y.sx)
node x_array_lo_hi_hi = cat(entries_barrier_5.io.y.sx, entries_barrier_4.io.y.sx)
node x_array_lo_hi = cat(x_array_lo_hi_hi, entries_barrier_3.io.y.sx)
node x_array_lo = cat(x_array_lo_hi, x_array_lo_lo)
node x_array_hi_lo_hi = cat(entries_barrier_8.io.y.sx, entries_barrier_7.io.y.sx)
node x_array_hi_lo = cat(x_array_hi_lo_hi, entries_barrier_6.io.y.sx)
node x_array_hi_hi_lo = cat(entries_barrier_10.io.y.sx, entries_barrier_9.io.y.sx)
node x_array_hi_hi_hi = cat(entries_barrier_12.io.y.sx, entries_barrier_11.io.y.sx)
node x_array_hi_hi = cat(x_array_hi_hi_hi, x_array_hi_hi_lo)
node x_array_hi = cat(x_array_hi_hi, x_array_hi_lo)
node _x_array_T = cat(x_array_hi, x_array_lo)
node _x_array_T_1 = and(priv_x_ok, _x_array_T)
node _x_array_T_2 = or(_x_array_T_1, stage1_bypass)
node x_array = cat(UInt<1>(0h1), _x_array_T_2)
node _stage2_bypass_T = eq(stage2_en, UInt<1>(0h0))
node stage2_bypass = mux(_stage2_bypass_T, UInt<13>(0h1fff), UInt<13>(0h0))
node hr_array_lo_lo_hi = cat(entries_barrier_2.io.y.hr, entries_barrier_1.io.y.hr)
node hr_array_lo_lo = cat(hr_array_lo_lo_hi, entries_barrier.io.y.hr)
node hr_array_lo_hi_hi = cat(entries_barrier_5.io.y.hr, entries_barrier_4.io.y.hr)
node hr_array_lo_hi = cat(hr_array_lo_hi_hi, entries_barrier_3.io.y.hr)
node hr_array_lo = cat(hr_array_lo_hi, hr_array_lo_lo)
node hr_array_hi_lo_hi = cat(entries_barrier_8.io.y.hr, entries_barrier_7.io.y.hr)
node hr_array_hi_lo = cat(hr_array_hi_lo_hi, entries_barrier_6.io.y.hr)
node hr_array_hi_hi_lo = cat(entries_barrier_10.io.y.hr, entries_barrier_9.io.y.hr)
node hr_array_hi_hi_hi = cat(entries_barrier_12.io.y.hr, entries_barrier_11.io.y.hr)
node hr_array_hi_hi = cat(hr_array_hi_hi_hi, hr_array_hi_hi_lo)
node hr_array_hi = cat(hr_array_hi_hi, hr_array_hi_lo)
node _hr_array_T = cat(hr_array_hi, hr_array_lo)
node hr_array_lo_lo_hi_1 = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx)
node hr_array_lo_lo_1 = cat(hr_array_lo_lo_hi_1, entries_barrier.io.y.hx)
node hr_array_lo_hi_hi_1 = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx)
node hr_array_lo_hi_1 = cat(hr_array_lo_hi_hi_1, entries_barrier_3.io.y.hx)
node hr_array_lo_1 = cat(hr_array_lo_hi_1, hr_array_lo_lo_1)
node hr_array_hi_lo_hi_1 = cat(entries_barrier_8.io.y.hx, entries_barrier_7.io.y.hx)
node hr_array_hi_lo_1 = cat(hr_array_hi_lo_hi_1, entries_barrier_6.io.y.hx)
node hr_array_hi_hi_lo_1 = cat(entries_barrier_10.io.y.hx, entries_barrier_9.io.y.hx)
node hr_array_hi_hi_hi_1 = cat(entries_barrier_12.io.y.hx, entries_barrier_11.io.y.hx)
node hr_array_hi_hi_1 = cat(hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1)
node hr_array_hi_1 = cat(hr_array_hi_hi_1, hr_array_hi_lo_1)
node _hr_array_T_1 = cat(hr_array_hi_1, hr_array_lo_1)
node _hr_array_T_2 = mux(io.ptw.status.mxr, _hr_array_T_1, UInt<1>(0h0))
node _hr_array_T_3 = or(_hr_array_T, _hr_array_T_2)
node _hr_array_T_4 = or(_hr_array_T_3, stage2_bypass)
node hr_array = cat(UInt<1>(0h1), _hr_array_T_4)
node hw_array_lo_lo_hi = cat(entries_barrier_2.io.y.hw, entries_barrier_1.io.y.hw)
node hw_array_lo_lo = cat(hw_array_lo_lo_hi, entries_barrier.io.y.hw)
node hw_array_lo_hi_hi = cat(entries_barrier_5.io.y.hw, entries_barrier_4.io.y.hw)
node hw_array_lo_hi = cat(hw_array_lo_hi_hi, entries_barrier_3.io.y.hw)
node hw_array_lo = cat(hw_array_lo_hi, hw_array_lo_lo)
node hw_array_hi_lo_hi = cat(entries_barrier_8.io.y.hw, entries_barrier_7.io.y.hw)
node hw_array_hi_lo = cat(hw_array_hi_lo_hi, entries_barrier_6.io.y.hw)
node hw_array_hi_hi_lo = cat(entries_barrier_10.io.y.hw, entries_barrier_9.io.y.hw)
node hw_array_hi_hi_hi = cat(entries_barrier_12.io.y.hw, entries_barrier_11.io.y.hw)
node hw_array_hi_hi = cat(hw_array_hi_hi_hi, hw_array_hi_hi_lo)
node hw_array_hi = cat(hw_array_hi_hi, hw_array_hi_lo)
node _hw_array_T = cat(hw_array_hi, hw_array_lo)
node _hw_array_T_1 = or(_hw_array_T, stage2_bypass)
node hw_array = cat(UInt<1>(0h1), _hw_array_T_1)
node hx_array_lo_lo_hi = cat(entries_barrier_2.io.y.hx, entries_barrier_1.io.y.hx)
node hx_array_lo_lo = cat(hx_array_lo_lo_hi, entries_barrier.io.y.hx)
node hx_array_lo_hi_hi = cat(entries_barrier_5.io.y.hx, entries_barrier_4.io.y.hx)
node hx_array_lo_hi = cat(hx_array_lo_hi_hi, entries_barrier_3.io.y.hx)
node hx_array_lo = cat(hx_array_lo_hi, hx_array_lo_lo)
node hx_array_hi_lo_hi = cat(entries_barrier_8.io.y.hx, entries_barrier_7.io.y.hx)
node hx_array_hi_lo = cat(hx_array_hi_lo_hi, entries_barrier_6.io.y.hx)
node hx_array_hi_hi_lo = cat(entries_barrier_10.io.y.hx, entries_barrier_9.io.y.hx)
node hx_array_hi_hi_hi = cat(entries_barrier_12.io.y.hx, entries_barrier_11.io.y.hx)
node hx_array_hi_hi = cat(hx_array_hi_hi_hi, hx_array_hi_hi_lo)
node hx_array_hi = cat(hx_array_hi_hi, hx_array_hi_lo)
node _hx_array_T = cat(hx_array_hi, hx_array_lo)
node _hx_array_T_1 = or(_hx_array_T, stage2_bypass)
node hx_array = cat(UInt<1>(0h1), _hx_array_T_1)
node _pr_array_T = mux(prot_r, UInt<2>(0h3), UInt<2>(0h0))
node pr_array_lo_lo_hi = cat(entries_barrier_2.io.y.pr, entries_barrier_1.io.y.pr)
node pr_array_lo_lo = cat(pr_array_lo_lo_hi, entries_barrier.io.y.pr)
node pr_array_lo_hi_hi = cat(entries_barrier_5.io.y.pr, entries_barrier_4.io.y.pr)
node pr_array_lo_hi = cat(pr_array_lo_hi_hi, entries_barrier_3.io.y.pr)
node pr_array_lo = cat(pr_array_lo_hi, pr_array_lo_lo)
node pr_array_hi_lo_hi = cat(entries_barrier_8.io.y.pr, entries_barrier_7.io.y.pr)
node pr_array_hi_lo = cat(pr_array_hi_lo_hi, entries_barrier_6.io.y.pr)
node pr_array_hi_hi_hi = cat(entries_barrier_11.io.y.pr, entries_barrier_10.io.y.pr)
node pr_array_hi_hi = cat(pr_array_hi_hi_hi, entries_barrier_9.io.y.pr)
node pr_array_hi = cat(pr_array_hi_hi, pr_array_hi_lo)
node _pr_array_T_1 = cat(pr_array_hi, pr_array_lo)
node _pr_array_T_2 = cat(_pr_array_T, _pr_array_T_1)
node _pr_array_T_3 = or(ptw_ae_array, final_ae_array)
node _pr_array_T_4 = not(_pr_array_T_3)
node pr_array = and(_pr_array_T_2, _pr_array_T_4)
node _pw_array_T = mux(prot_w, UInt<2>(0h3), UInt<2>(0h0))
node pw_array_lo_lo_hi = cat(entries_barrier_2.io.y.pw, entries_barrier_1.io.y.pw)
node pw_array_lo_lo = cat(pw_array_lo_lo_hi, entries_barrier.io.y.pw)
node pw_array_lo_hi_hi = cat(entries_barrier_5.io.y.pw, entries_barrier_4.io.y.pw)
node pw_array_lo_hi = cat(pw_array_lo_hi_hi, entries_barrier_3.io.y.pw)
node pw_array_lo = cat(pw_array_lo_hi, pw_array_lo_lo)
node pw_array_hi_lo_hi = cat(entries_barrier_8.io.y.pw, entries_barrier_7.io.y.pw)
node pw_array_hi_lo = cat(pw_array_hi_lo_hi, entries_barrier_6.io.y.pw)
node pw_array_hi_hi_hi = cat(entries_barrier_11.io.y.pw, entries_barrier_10.io.y.pw)
node pw_array_hi_hi = cat(pw_array_hi_hi_hi, entries_barrier_9.io.y.pw)
node pw_array_hi = cat(pw_array_hi_hi, pw_array_hi_lo)
node _pw_array_T_1 = cat(pw_array_hi, pw_array_lo)
node _pw_array_T_2 = cat(_pw_array_T, _pw_array_T_1)
node _pw_array_T_3 = or(ptw_ae_array, final_ae_array)
node _pw_array_T_4 = not(_pw_array_T_3)
node pw_array = and(_pw_array_T_2, _pw_array_T_4)
node _px_array_T = mux(prot_x, UInt<2>(0h3), UInt<2>(0h0))
node px_array_lo_lo_hi = cat(entries_barrier_2.io.y.px, entries_barrier_1.io.y.px)
node px_array_lo_lo = cat(px_array_lo_lo_hi, entries_barrier.io.y.px)
node px_array_lo_hi_hi = cat(entries_barrier_5.io.y.px, entries_barrier_4.io.y.px)
node px_array_lo_hi = cat(px_array_lo_hi_hi, entries_barrier_3.io.y.px)
node px_array_lo = cat(px_array_lo_hi, px_array_lo_lo)
node px_array_hi_lo_hi = cat(entries_barrier_8.io.y.px, entries_barrier_7.io.y.px)
node px_array_hi_lo = cat(px_array_hi_lo_hi, entries_barrier_6.io.y.px)
node px_array_hi_hi_hi = cat(entries_barrier_11.io.y.px, entries_barrier_10.io.y.px)
node px_array_hi_hi = cat(px_array_hi_hi_hi, entries_barrier_9.io.y.px)
node px_array_hi = cat(px_array_hi_hi, px_array_hi_lo)
node _px_array_T_1 = cat(px_array_hi, px_array_lo)
node _px_array_T_2 = cat(_px_array_T, _px_array_T_1)
node _px_array_T_3 = or(ptw_ae_array, final_ae_array)
node _px_array_T_4 = not(_px_array_T_3)
node px_array = and(_px_array_T_2, _px_array_T_4)
node _eff_array_T = mux(pma.io.resp.eff, UInt<2>(0h3), UInt<2>(0h0))
node eff_array_lo_lo_hi = cat(entries_barrier_2.io.y.eff, entries_barrier_1.io.y.eff)
node eff_array_lo_lo = cat(eff_array_lo_lo_hi, entries_barrier.io.y.eff)
node eff_array_lo_hi_hi = cat(entries_barrier_5.io.y.eff, entries_barrier_4.io.y.eff)
node eff_array_lo_hi = cat(eff_array_lo_hi_hi, entries_barrier_3.io.y.eff)
node eff_array_lo = cat(eff_array_lo_hi, eff_array_lo_lo)
node eff_array_hi_lo_hi = cat(entries_barrier_8.io.y.eff, entries_barrier_7.io.y.eff)
node eff_array_hi_lo = cat(eff_array_hi_lo_hi, entries_barrier_6.io.y.eff)
node eff_array_hi_hi_hi = cat(entries_barrier_11.io.y.eff, entries_barrier_10.io.y.eff)
node eff_array_hi_hi = cat(eff_array_hi_hi_hi, entries_barrier_9.io.y.eff)
node eff_array_hi = cat(eff_array_hi_hi, eff_array_hi_lo)
node _eff_array_T_1 = cat(eff_array_hi, eff_array_lo)
node eff_array = cat(_eff_array_T, _eff_array_T_1)
node _c_array_T = mux(cacheable, UInt<2>(0h3), UInt<2>(0h0))
node c_array_lo_lo_hi = cat(entries_barrier_2.io.y.c, entries_barrier_1.io.y.c)
node c_array_lo_lo = cat(c_array_lo_lo_hi, entries_barrier.io.y.c)
node c_array_lo_hi_hi = cat(entries_barrier_5.io.y.c, entries_barrier_4.io.y.c)
node c_array_lo_hi = cat(c_array_lo_hi_hi, entries_barrier_3.io.y.c)
node c_array_lo = cat(c_array_lo_hi, c_array_lo_lo)
node c_array_hi_lo_hi = cat(entries_barrier_8.io.y.c, entries_barrier_7.io.y.c)
node c_array_hi_lo = cat(c_array_hi_lo_hi, entries_barrier_6.io.y.c)
node c_array_hi_hi_hi = cat(entries_barrier_11.io.y.c, entries_barrier_10.io.y.c)
node c_array_hi_hi = cat(c_array_hi_hi_hi, entries_barrier_9.io.y.c)
node c_array_hi = cat(c_array_hi_hi, c_array_hi_lo)
node _c_array_T_1 = cat(c_array_hi, c_array_lo)
node c_array = cat(_c_array_T, _c_array_T_1)
node _ppp_array_T = mux(pma.io.resp.pp, UInt<2>(0h3), UInt<2>(0h0))
node ppp_array_lo_lo_hi = cat(entries_barrier_2.io.y.ppp, entries_barrier_1.io.y.ppp)
node ppp_array_lo_lo = cat(ppp_array_lo_lo_hi, entries_barrier.io.y.ppp)
node ppp_array_lo_hi_hi = cat(entries_barrier_5.io.y.ppp, entries_barrier_4.io.y.ppp)
node ppp_array_lo_hi = cat(ppp_array_lo_hi_hi, entries_barrier_3.io.y.ppp)
node ppp_array_lo = cat(ppp_array_lo_hi, ppp_array_lo_lo)
node ppp_array_hi_lo_hi = cat(entries_barrier_8.io.y.ppp, entries_barrier_7.io.y.ppp)
node ppp_array_hi_lo = cat(ppp_array_hi_lo_hi, entries_barrier_6.io.y.ppp)
node ppp_array_hi_hi_hi = cat(entries_barrier_11.io.y.ppp, entries_barrier_10.io.y.ppp)
node ppp_array_hi_hi = cat(ppp_array_hi_hi_hi, entries_barrier_9.io.y.ppp)
node ppp_array_hi = cat(ppp_array_hi_hi, ppp_array_hi_lo)
node _ppp_array_T_1 = cat(ppp_array_hi, ppp_array_lo)
node ppp_array = cat(_ppp_array_T, _ppp_array_T_1)
node _paa_array_T = mux(pma.io.resp.aa, UInt<2>(0h3), UInt<2>(0h0))
node paa_array_lo_lo_hi = cat(entries_barrier_2.io.y.paa, entries_barrier_1.io.y.paa)
node paa_array_lo_lo = cat(paa_array_lo_lo_hi, entries_barrier.io.y.paa)
node paa_array_lo_hi_hi = cat(entries_barrier_5.io.y.paa, entries_barrier_4.io.y.paa)
node paa_array_lo_hi = cat(paa_array_lo_hi_hi, entries_barrier_3.io.y.paa)
node paa_array_lo = cat(paa_array_lo_hi, paa_array_lo_lo)
node paa_array_hi_lo_hi = cat(entries_barrier_8.io.y.paa, entries_barrier_7.io.y.paa)
node paa_array_hi_lo = cat(paa_array_hi_lo_hi, entries_barrier_6.io.y.paa)
node paa_array_hi_hi_hi = cat(entries_barrier_11.io.y.paa, entries_barrier_10.io.y.paa)
node paa_array_hi_hi = cat(paa_array_hi_hi_hi, entries_barrier_9.io.y.paa)
node paa_array_hi = cat(paa_array_hi_hi, paa_array_hi_lo)
node _paa_array_T_1 = cat(paa_array_hi, paa_array_lo)
node paa_array = cat(_paa_array_T, _paa_array_T_1)
node _pal_array_T = mux(pma.io.resp.al, UInt<2>(0h3), UInt<2>(0h0))
node pal_array_lo_lo_hi = cat(entries_barrier_2.io.y.pal, entries_barrier_1.io.y.pal)
node pal_array_lo_lo = cat(pal_array_lo_lo_hi, entries_barrier.io.y.pal)
node pal_array_lo_hi_hi = cat(entries_barrier_5.io.y.pal, entries_barrier_4.io.y.pal)
node pal_array_lo_hi = cat(pal_array_lo_hi_hi, entries_barrier_3.io.y.pal)
node pal_array_lo = cat(pal_array_lo_hi, pal_array_lo_lo)
node pal_array_hi_lo_hi = cat(entries_barrier_8.io.y.pal, entries_barrier_7.io.y.pal)
node pal_array_hi_lo = cat(pal_array_hi_lo_hi, entries_barrier_6.io.y.pal)
node pal_array_hi_hi_hi = cat(entries_barrier_11.io.y.pal, entries_barrier_10.io.y.pal)
node pal_array_hi_hi = cat(pal_array_hi_hi_hi, entries_barrier_9.io.y.pal)
node pal_array_hi = cat(pal_array_hi_hi, pal_array_hi_lo)
node _pal_array_T_1 = cat(pal_array_hi, pal_array_lo)
node pal_array = cat(_pal_array_T, _pal_array_T_1)
node ppp_array_if_cached = or(ppp_array, c_array)
node paa_array_if_cached = or(paa_array, c_array)
node pal_array_if_cached = or(pal_array, c_array)
node _prefetchable_array_T = and(cacheable, homogeneous)
node _prefetchable_array_T_1 = shl(_prefetchable_array_T, 1)
node prefetchable_array_lo_lo_hi = cat(entries_barrier_2.io.y.c, entries_barrier_1.io.y.c)
node prefetchable_array_lo_lo = cat(prefetchable_array_lo_lo_hi, entries_barrier.io.y.c)
node prefetchable_array_lo_hi_hi = cat(entries_barrier_5.io.y.c, entries_barrier_4.io.y.c)
node prefetchable_array_lo_hi = cat(prefetchable_array_lo_hi_hi, entries_barrier_3.io.y.c)
node prefetchable_array_lo = cat(prefetchable_array_lo_hi, prefetchable_array_lo_lo)
node prefetchable_array_hi_lo_hi = cat(entries_barrier_8.io.y.c, entries_barrier_7.io.y.c)
node prefetchable_array_hi_lo = cat(prefetchable_array_hi_lo_hi, entries_barrier_6.io.y.c)
node prefetchable_array_hi_hi_hi = cat(entries_barrier_11.io.y.c, entries_barrier_10.io.y.c)
node prefetchable_array_hi_hi = cat(prefetchable_array_hi_hi_hi, entries_barrier_9.io.y.c)
node prefetchable_array_hi = cat(prefetchable_array_hi_hi, prefetchable_array_hi_lo)
node _prefetchable_array_T_2 = cat(prefetchable_array_hi, prefetchable_array_lo)
node prefetchable_array = cat(_prefetchable_array_T_1, _prefetchable_array_T_2)
node _misaligned_T = dshl(UInt<1>(0h1), io.req.bits.size)
node _misaligned_T_1 = sub(_misaligned_T, UInt<1>(0h1))
node _misaligned_T_2 = tail(_misaligned_T_1, 1)
node _misaligned_T_3 = and(io.req.bits.vaddr, _misaligned_T_2)
node misaligned = orr(_misaligned_T_3)
node _bad_va_T = and(vm_enabled, stage1_en)
node bad_va_maskedVAddr = and(io.req.bits.vaddr, UInt<40>(0hc000000000))
node _bad_va_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0))
node _bad_va_T_2 = eq(bad_va_maskedVAddr, UInt<1>(0h0))
node _bad_va_T_3 = eq(bad_va_maskedVAddr, UInt<40>(0hc000000000))
node _bad_va_T_4 = and(UInt<1>(0h1), _bad_va_T_3)
node _bad_va_T_5 = or(_bad_va_T_2, _bad_va_T_4)
node _bad_va_T_6 = eq(_bad_va_T_5, UInt<1>(0h0))
node _bad_va_T_7 = and(_bad_va_T_1, _bad_va_T_6)
node bad_va = and(_bad_va_T, _bad_va_T_7)
node _cmd_lrsc_T = eq(io.req.bits.cmd, UInt<3>(0h6))
node _cmd_lrsc_T_1 = eq(io.req.bits.cmd, UInt<3>(0h7))
node _cmd_lrsc_T_2 = or(_cmd_lrsc_T, _cmd_lrsc_T_1)
node cmd_lrsc = and(UInt<1>(0h1), _cmd_lrsc_T_2)
node _cmd_amo_logical_T = eq(io.req.bits.cmd, UInt<3>(0h4))
node _cmd_amo_logical_T_1 = eq(io.req.bits.cmd, UInt<4>(0h9))
node _cmd_amo_logical_T_2 = eq(io.req.bits.cmd, UInt<4>(0ha))
node _cmd_amo_logical_T_3 = eq(io.req.bits.cmd, UInt<4>(0hb))
node _cmd_amo_logical_T_4 = or(_cmd_amo_logical_T, _cmd_amo_logical_T_1)
node _cmd_amo_logical_T_5 = or(_cmd_amo_logical_T_4, _cmd_amo_logical_T_2)
node _cmd_amo_logical_T_6 = or(_cmd_amo_logical_T_5, _cmd_amo_logical_T_3)
node cmd_amo_logical = and(UInt<1>(0h1), _cmd_amo_logical_T_6)
node _cmd_amo_arithmetic_T = eq(io.req.bits.cmd, UInt<4>(0h8))
node _cmd_amo_arithmetic_T_1 = eq(io.req.bits.cmd, UInt<4>(0hc))
node _cmd_amo_arithmetic_T_2 = eq(io.req.bits.cmd, UInt<4>(0hd))
node _cmd_amo_arithmetic_T_3 = eq(io.req.bits.cmd, UInt<4>(0he))
node _cmd_amo_arithmetic_T_4 = eq(io.req.bits.cmd, UInt<4>(0hf))
node _cmd_amo_arithmetic_T_5 = or(_cmd_amo_arithmetic_T, _cmd_amo_arithmetic_T_1)
node _cmd_amo_arithmetic_T_6 = or(_cmd_amo_arithmetic_T_5, _cmd_amo_arithmetic_T_2)
node _cmd_amo_arithmetic_T_7 = or(_cmd_amo_arithmetic_T_6, _cmd_amo_arithmetic_T_3)
node _cmd_amo_arithmetic_T_8 = or(_cmd_amo_arithmetic_T_7, _cmd_amo_arithmetic_T_4)
node cmd_amo_arithmetic = and(UInt<1>(0h1), _cmd_amo_arithmetic_T_8)
node cmd_put_partial = eq(io.req.bits.cmd, UInt<5>(0h11))
node _cmd_read_T = eq(io.req.bits.cmd, UInt<1>(0h0))
node _cmd_read_T_1 = eq(io.req.bits.cmd, UInt<5>(0h10))
node _cmd_read_T_2 = eq(io.req.bits.cmd, UInt<3>(0h6))
node _cmd_read_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7))
node _cmd_read_T_4 = or(_cmd_read_T, _cmd_read_T_1)
node _cmd_read_T_5 = or(_cmd_read_T_4, _cmd_read_T_2)
node _cmd_read_T_6 = or(_cmd_read_T_5, _cmd_read_T_3)
node _cmd_read_T_7 = eq(io.req.bits.cmd, UInt<3>(0h4))
node _cmd_read_T_8 = eq(io.req.bits.cmd, UInt<4>(0h9))
node _cmd_read_T_9 = eq(io.req.bits.cmd, UInt<4>(0ha))
node _cmd_read_T_10 = eq(io.req.bits.cmd, UInt<4>(0hb))
node _cmd_read_T_11 = or(_cmd_read_T_7, _cmd_read_T_8)
node _cmd_read_T_12 = or(_cmd_read_T_11, _cmd_read_T_9)
node _cmd_read_T_13 = or(_cmd_read_T_12, _cmd_read_T_10)
node _cmd_read_T_14 = eq(io.req.bits.cmd, UInt<4>(0h8))
node _cmd_read_T_15 = eq(io.req.bits.cmd, UInt<4>(0hc))
node _cmd_read_T_16 = eq(io.req.bits.cmd, UInt<4>(0hd))
node _cmd_read_T_17 = eq(io.req.bits.cmd, UInt<4>(0he))
node _cmd_read_T_18 = eq(io.req.bits.cmd, UInt<4>(0hf))
node _cmd_read_T_19 = or(_cmd_read_T_14, _cmd_read_T_15)
node _cmd_read_T_20 = or(_cmd_read_T_19, _cmd_read_T_16)
node _cmd_read_T_21 = or(_cmd_read_T_20, _cmd_read_T_17)
node _cmd_read_T_22 = or(_cmd_read_T_21, _cmd_read_T_18)
node _cmd_read_T_23 = or(_cmd_read_T_13, _cmd_read_T_22)
node cmd_read = or(_cmd_read_T_6, _cmd_read_T_23)
node _cmd_readx_T = eq(io.req.bits.cmd, UInt<5>(0h10))
node cmd_readx = and(UInt<1>(0h0), _cmd_readx_T)
node _cmd_write_T = eq(io.req.bits.cmd, UInt<1>(0h1))
node _cmd_write_T_1 = eq(io.req.bits.cmd, UInt<5>(0h11))
node _cmd_write_T_2 = or(_cmd_write_T, _cmd_write_T_1)
node _cmd_write_T_3 = eq(io.req.bits.cmd, UInt<3>(0h7))
node _cmd_write_T_4 = or(_cmd_write_T_2, _cmd_write_T_3)
node _cmd_write_T_5 = eq(io.req.bits.cmd, UInt<3>(0h4))
node _cmd_write_T_6 = eq(io.req.bits.cmd, UInt<4>(0h9))
node _cmd_write_T_7 = eq(io.req.bits.cmd, UInt<4>(0ha))
node _cmd_write_T_8 = eq(io.req.bits.cmd, UInt<4>(0hb))
node _cmd_write_T_9 = or(_cmd_write_T_5, _cmd_write_T_6)
node _cmd_write_T_10 = or(_cmd_write_T_9, _cmd_write_T_7)
node _cmd_write_T_11 = or(_cmd_write_T_10, _cmd_write_T_8)
node _cmd_write_T_12 = eq(io.req.bits.cmd, UInt<4>(0h8))
node _cmd_write_T_13 = eq(io.req.bits.cmd, UInt<4>(0hc))
node _cmd_write_T_14 = eq(io.req.bits.cmd, UInt<4>(0hd))
node _cmd_write_T_15 = eq(io.req.bits.cmd, UInt<4>(0he))
node _cmd_write_T_16 = eq(io.req.bits.cmd, UInt<4>(0hf))
node _cmd_write_T_17 = or(_cmd_write_T_12, _cmd_write_T_13)
node _cmd_write_T_18 = or(_cmd_write_T_17, _cmd_write_T_14)
node _cmd_write_T_19 = or(_cmd_write_T_18, _cmd_write_T_15)
node _cmd_write_T_20 = or(_cmd_write_T_19, _cmd_write_T_16)
node _cmd_write_T_21 = or(_cmd_write_T_11, _cmd_write_T_20)
node cmd_write = or(_cmd_write_T_4, _cmd_write_T_21)
node _cmd_write_perms_T = eq(io.req.bits.cmd, UInt<3>(0h5))
node _cmd_write_perms_T_1 = eq(io.req.bits.cmd, UInt<5>(0h17))
node _cmd_write_perms_T_2 = or(_cmd_write_perms_T, _cmd_write_perms_T_1)
node cmd_write_perms = or(cmd_write, _cmd_write_perms_T_2)
node lrscAllowed = mux(UInt<1>(0h0), UInt<1>(0h0), c_array)
node _ae_array_T = mux(misaligned, eff_array, UInt<1>(0h0))
node _ae_array_T_1 = not(lrscAllowed)
node _ae_array_T_2 = mux(cmd_lrsc, _ae_array_T_1, UInt<1>(0h0))
node ae_array = or(_ae_array_T, _ae_array_T_2)
node _ae_ld_array_T = not(pr_array)
node _ae_ld_array_T_1 = or(ae_array, _ae_ld_array_T)
node ae_ld_array = mux(cmd_read, _ae_ld_array_T_1, UInt<1>(0h0))
node _ae_st_array_T = not(pw_array)
node _ae_st_array_T_1 = or(ae_array, _ae_st_array_T)
node _ae_st_array_T_2 = mux(cmd_write_perms, _ae_st_array_T_1, UInt<1>(0h0))
node _ae_st_array_T_3 = not(ppp_array_if_cached)
node _ae_st_array_T_4 = mux(cmd_put_partial, _ae_st_array_T_3, UInt<1>(0h0))
node _ae_st_array_T_5 = or(_ae_st_array_T_2, _ae_st_array_T_4)
node _ae_st_array_T_6 = not(pal_array_if_cached)
node _ae_st_array_T_7 = mux(cmd_amo_logical, _ae_st_array_T_6, UInt<1>(0h0))
node _ae_st_array_T_8 = or(_ae_st_array_T_5, _ae_st_array_T_7)
node _ae_st_array_T_9 = not(paa_array_if_cached)
node _ae_st_array_T_10 = mux(cmd_amo_arithmetic, _ae_st_array_T_9, UInt<1>(0h0))
node ae_st_array = or(_ae_st_array_T_8, _ae_st_array_T_10)
node _must_alloc_array_T = not(ppp_array)
node _must_alloc_array_T_1 = mux(cmd_put_partial, _must_alloc_array_T, UInt<1>(0h0))
node _must_alloc_array_T_2 = not(pal_array)
node _must_alloc_array_T_3 = mux(cmd_amo_logical, _must_alloc_array_T_2, UInt<1>(0h0))
node _must_alloc_array_T_4 = or(_must_alloc_array_T_1, _must_alloc_array_T_3)
node _must_alloc_array_T_5 = not(paa_array)
node _must_alloc_array_T_6 = mux(cmd_amo_arithmetic, _must_alloc_array_T_5, UInt<1>(0h0))
node _must_alloc_array_T_7 = or(_must_alloc_array_T_4, _must_alloc_array_T_6)
node _must_alloc_array_T_8 = not(UInt<14>(0h0))
node _must_alloc_array_T_9 = mux(cmd_lrsc, _must_alloc_array_T_8, UInt<1>(0h0))
node must_alloc_array = or(_must_alloc_array_T_7, _must_alloc_array_T_9)
node _pf_ld_array_T = mux(cmd_readx, x_array, r_array)
node _pf_ld_array_T_1 = not(_pf_ld_array_T)
node _pf_ld_array_T_2 = not(ptw_ae_array)
node _pf_ld_array_T_3 = and(_pf_ld_array_T_1, _pf_ld_array_T_2)
node _pf_ld_array_T_4 = or(_pf_ld_array_T_3, ptw_pf_array)
node _pf_ld_array_T_5 = not(ptw_gf_array)
node _pf_ld_array_T_6 = and(_pf_ld_array_T_4, _pf_ld_array_T_5)
node pf_ld_array = mux(cmd_read, _pf_ld_array_T_6, UInt<1>(0h0))
node _pf_st_array_T = not(w_array)
node _pf_st_array_T_1 = not(ptw_ae_array)
node _pf_st_array_T_2 = and(_pf_st_array_T, _pf_st_array_T_1)
node _pf_st_array_T_3 = or(_pf_st_array_T_2, ptw_pf_array)
node _pf_st_array_T_4 = not(ptw_gf_array)
node _pf_st_array_T_5 = and(_pf_st_array_T_3, _pf_st_array_T_4)
node pf_st_array = mux(cmd_write_perms, _pf_st_array_T_5, UInt<1>(0h0))
node _pf_inst_array_T = not(x_array)
node _pf_inst_array_T_1 = not(ptw_ae_array)
node _pf_inst_array_T_2 = and(_pf_inst_array_T, _pf_inst_array_T_1)
node _pf_inst_array_T_3 = or(_pf_inst_array_T_2, ptw_pf_array)
node _pf_inst_array_T_4 = not(ptw_gf_array)
node pf_inst_array = and(_pf_inst_array_T_3, _pf_inst_array_T_4)
node _gf_ld_array_T = and(priv_v, cmd_read)
node _gf_ld_array_T_1 = mux(cmd_readx, hx_array, hr_array)
node _gf_ld_array_T_2 = not(_gf_ld_array_T_1)
node _gf_ld_array_T_3 = or(_gf_ld_array_T_2, ptw_gf_array)
node _gf_ld_array_T_4 = not(ptw_ae_array)
node _gf_ld_array_T_5 = and(_gf_ld_array_T_3, _gf_ld_array_T_4)
node gf_ld_array = mux(_gf_ld_array_T, _gf_ld_array_T_5, UInt<1>(0h0))
node _gf_st_array_T = and(priv_v, cmd_write_perms)
node _gf_st_array_T_1 = not(hw_array)
node _gf_st_array_T_2 = or(_gf_st_array_T_1, ptw_gf_array)
node _gf_st_array_T_3 = not(ptw_ae_array)
node _gf_st_array_T_4 = and(_gf_st_array_T_2, _gf_st_array_T_3)
node gf_st_array = mux(_gf_st_array_T, _gf_st_array_T_4, UInt<1>(0h0))
node _gf_inst_array_T = not(hx_array)
node _gf_inst_array_T_1 = or(_gf_inst_array_T, ptw_gf_array)
node _gf_inst_array_T_2 = not(ptw_ae_array)
node _gf_inst_array_T_3 = and(_gf_inst_array_T_1, _gf_inst_array_T_2)
node gf_inst_array = mux(priv_v, _gf_inst_array_T_3, UInt<1>(0h0))
node _gpa_hits_hit_mask_T = eq(r_gpa_vpn, vpn)
node _gpa_hits_hit_mask_T_1 = and(r_gpa_valid, _gpa_hits_hit_mask_T)
node _gpa_hits_hit_mask_T_2 = mux(_gpa_hits_hit_mask_T_1, UInt<12>(0hfff), UInt<12>(0h0))
node _gpa_hits_hit_mask_T_3 = eq(vstage1_en, UInt<1>(0h0))
node _gpa_hits_hit_mask_T_4 = mux(_gpa_hits_hit_mask_T_3, UInt<13>(0h1fff), UInt<13>(0h0))
node gpa_hits_hit_mask = or(_gpa_hits_hit_mask_T_2, _gpa_hits_hit_mask_T_4)
node _gpa_hits_T = bits(gf_inst_array, 12, 0)
node _gpa_hits_T_1 = not(_gpa_hits_T)
node gpa_hits = or(gpa_hits_hit_mask, _gpa_hits_T_1)
node tlb_hit_if_not_gpa_miss = orr(real_hits)
node _tlb_hit_T = and(real_hits, gpa_hits)
node tlb_hit = orr(_tlb_hit_T)
node _tlb_miss_T = eq(vsatp_mode_mismatch, UInt<1>(0h0))
node _tlb_miss_T_1 = and(vm_enabled, _tlb_miss_T)
node _tlb_miss_T_2 = eq(bad_va, UInt<1>(0h0))
node _tlb_miss_T_3 = and(_tlb_miss_T_1, _tlb_miss_T_2)
node _tlb_miss_T_4 = eq(tlb_hit, UInt<1>(0h0))
node tlb_miss = and(_tlb_miss_T_3, _tlb_miss_T_4)
regreset state_reg : UInt<7>, clock, reset, UInt<7>(0h0)
wire _state_vec_WIRE : UInt<7>[1]
connect _state_vec_WIRE[0], UInt<7>(0h0)
regreset state_vec : UInt<7>[1], clock, reset, _state_vec_WIRE
regreset state_reg_1 : UInt<3>, clock, reset, UInt<3>(0h0)
node _T_23 = and(io.req.valid, vm_enabled)
when _T_23 :
node _T_24 = or(sector_hits_0, sector_hits_1)
node _T_25 = or(_T_24, sector_hits_2)
node _T_26 = or(_T_25, sector_hits_3)
node _T_27 = or(_T_26, sector_hits_4)
node _T_28 = or(_T_27, sector_hits_5)
node _T_29 = or(_T_28, sector_hits_6)
node _T_30 = or(_T_29, sector_hits_7)
when _T_30 :
node lo_lo = cat(sector_hits_1, sector_hits_0)
node lo_hi = cat(sector_hits_3, sector_hits_2)
node lo = cat(lo_hi, lo_lo)
node hi_lo = cat(sector_hits_5, sector_hits_4)
node hi_hi = cat(sector_hits_7, sector_hits_6)
node hi = cat(hi_hi, hi_lo)
node _T_31 = cat(hi, lo)
node hi_1 = bits(_T_31, 7, 4)
node lo_1 = bits(_T_31, 3, 0)
node _T_32 = orr(hi_1)
node _T_33 = or(hi_1, lo_1)
node hi_2 = bits(_T_33, 3, 2)
node lo_2 = bits(_T_33, 1, 0)
node _T_34 = orr(hi_2)
node _T_35 = or(hi_2, lo_2)
node _T_36 = bits(_T_35, 1, 1)
node _T_37 = cat(_T_34, _T_36)
node _T_38 = cat(_T_32, _T_37)
node state_vec_0_touch_way_sized = bits(_T_38, 2, 0)
node _state_vec_0_set_left_older_T = bits(state_vec_0_touch_way_sized, 2, 2)
node state_vec_0_set_left_older = eq(_state_vec_0_set_left_older_T, UInt<1>(0h0))
node state_vec_0_left_subtree_state = bits(state_vec[0], 5, 3)
node state_vec_0_right_subtree_state = bits(state_vec[0], 2, 0)
node _state_vec_0_T = bits(state_vec_0_touch_way_sized, 1, 0)
node _state_vec_0_set_left_older_T_1 = bits(_state_vec_0_T, 1, 1)
node state_vec_0_set_left_older_1 = eq(_state_vec_0_set_left_older_T_1, UInt<1>(0h0))
node state_vec_0_left_subtree_state_1 = bits(state_vec_0_left_subtree_state, 1, 1)
node state_vec_0_right_subtree_state_1 = bits(state_vec_0_left_subtree_state, 0, 0)
node _state_vec_0_T_1 = bits(_state_vec_0_T, 0, 0)
node _state_vec_0_T_2 = bits(_state_vec_0_T_1, 0, 0)
node _state_vec_0_T_3 = eq(_state_vec_0_T_2, UInt<1>(0h0))
node _state_vec_0_T_4 = mux(state_vec_0_set_left_older_1, state_vec_0_left_subtree_state_1, _state_vec_0_T_3)
node _state_vec_0_T_5 = bits(_state_vec_0_T, 0, 0)
node _state_vec_0_T_6 = bits(_state_vec_0_T_5, 0, 0)
node _state_vec_0_T_7 = eq(_state_vec_0_T_6, UInt<1>(0h0))
node _state_vec_0_T_8 = mux(state_vec_0_set_left_older_1, _state_vec_0_T_7, state_vec_0_right_subtree_state_1)
node state_vec_0_hi = cat(state_vec_0_set_left_older_1, _state_vec_0_T_4)
node _state_vec_0_T_9 = cat(state_vec_0_hi, _state_vec_0_T_8)
node _state_vec_0_T_10 = mux(state_vec_0_set_left_older, state_vec_0_left_subtree_state, _state_vec_0_T_9)
node _state_vec_0_T_11 = bits(state_vec_0_touch_way_sized, 1, 0)
node _state_vec_0_set_left_older_T_2 = bits(_state_vec_0_T_11, 1, 1)
node state_vec_0_set_left_older_2 = eq(_state_vec_0_set_left_older_T_2, UInt<1>(0h0))
node state_vec_0_left_subtree_state_2 = bits(state_vec_0_right_subtree_state, 1, 1)
node state_vec_0_right_subtree_state_2 = bits(state_vec_0_right_subtree_state, 0, 0)
node _state_vec_0_T_12 = bits(_state_vec_0_T_11, 0, 0)
node _state_vec_0_T_13 = bits(_state_vec_0_T_12, 0, 0)
node _state_vec_0_T_14 = eq(_state_vec_0_T_13, UInt<1>(0h0))
node _state_vec_0_T_15 = mux(state_vec_0_set_left_older_2, state_vec_0_left_subtree_state_2, _state_vec_0_T_14)
node _state_vec_0_T_16 = bits(_state_vec_0_T_11, 0, 0)
node _state_vec_0_T_17 = bits(_state_vec_0_T_16, 0, 0)
node _state_vec_0_T_18 = eq(_state_vec_0_T_17, UInt<1>(0h0))
node _state_vec_0_T_19 = mux(state_vec_0_set_left_older_2, _state_vec_0_T_18, state_vec_0_right_subtree_state_2)
node state_vec_0_hi_1 = cat(state_vec_0_set_left_older_2, _state_vec_0_T_15)
node _state_vec_0_T_20 = cat(state_vec_0_hi_1, _state_vec_0_T_19)
node _state_vec_0_T_21 = mux(state_vec_0_set_left_older, _state_vec_0_T_20, state_vec_0_right_subtree_state)
node state_vec_0_hi_2 = cat(state_vec_0_set_left_older, _state_vec_0_T_10)
node _state_vec_0_T_22 = cat(state_vec_0_hi_2, _state_vec_0_T_21)
connect state_vec[0], _state_vec_0_T_22
node _T_39 = or(superpage_hits_0, superpage_hits_1)
node _T_40 = or(_T_39, superpage_hits_2)
node _T_41 = or(_T_40, superpage_hits_3)
when _T_41 :
node lo_3 = cat(superpage_hits_1, superpage_hits_0)
node hi_3 = cat(superpage_hits_3, superpage_hits_2)
node _T_42 = cat(hi_3, lo_3)
node hi_4 = bits(_T_42, 3, 2)
node lo_4 = bits(_T_42, 1, 0)
node _T_43 = orr(hi_4)
node _T_44 = or(hi_4, lo_4)
node _T_45 = bits(_T_44, 1, 1)
node _T_46 = cat(_T_43, _T_45)
node state_reg_touch_way_sized = bits(_T_46, 1, 0)
node _state_reg_set_left_older_T = bits(state_reg_touch_way_sized, 1, 1)
node state_reg_set_left_older = eq(_state_reg_set_left_older_T, UInt<1>(0h0))
node state_reg_left_subtree_state = bits(state_reg_1, 1, 1)
node state_reg_right_subtree_state = bits(state_reg_1, 0, 0)
node _state_reg_T = bits(state_reg_touch_way_sized, 0, 0)
node _state_reg_T_1 = bits(_state_reg_T, 0, 0)
node _state_reg_T_2 = eq(_state_reg_T_1, UInt<1>(0h0))
node _state_reg_T_3 = mux(state_reg_set_left_older, state_reg_left_subtree_state, _state_reg_T_2)
node _state_reg_T_4 = bits(state_reg_touch_way_sized, 0, 0)
node _state_reg_T_5 = bits(_state_reg_T_4, 0, 0)
node _state_reg_T_6 = eq(_state_reg_T_5, UInt<1>(0h0))
node _state_reg_T_7 = mux(state_reg_set_left_older, _state_reg_T_6, state_reg_right_subtree_state)
node state_reg_hi = cat(state_reg_set_left_older, _state_reg_T_3)
node _state_reg_T_8 = cat(state_reg_hi, _state_reg_T_7)
connect state_reg_1, _state_reg_T_8
node _multipleHits_T = bits(real_hits, 5, 0)
node _multipleHits_T_1 = bits(_multipleHits_T, 2, 0)
node _multipleHits_T_2 = bits(_multipleHits_T_1, 0, 0)
node multipleHits_leftOne = bits(_multipleHits_T_2, 0, 0)
node _multipleHits_T_3 = bits(_multipleHits_T_1, 2, 1)
node _multipleHits_T_4 = bits(_multipleHits_T_3, 0, 0)
node multipleHits_leftOne_1 = bits(_multipleHits_T_4, 0, 0)
node _multipleHits_T_5 = bits(_multipleHits_T_3, 1, 1)
node multipleHits_rightOne = bits(_multipleHits_T_5, 0, 0)
node multipleHits_rightOne_1 = or(multipleHits_leftOne_1, multipleHits_rightOne)
node _multipleHits_T_6 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_7 = and(multipleHits_leftOne_1, multipleHits_rightOne)
node multipleHits_rightTwo = or(_multipleHits_T_6, _multipleHits_T_7)
node multipleHits_leftOne_2 = or(multipleHits_leftOne, multipleHits_rightOne_1)
node _multipleHits_T_8 = or(UInt<1>(0h0), multipleHits_rightTwo)
node _multipleHits_T_9 = and(multipleHits_leftOne, multipleHits_rightOne_1)
node multipleHits_leftTwo = or(_multipleHits_T_8, _multipleHits_T_9)
node _multipleHits_T_10 = bits(_multipleHits_T, 5, 3)
node _multipleHits_T_11 = bits(_multipleHits_T_10, 0, 0)
node multipleHits_leftOne_3 = bits(_multipleHits_T_11, 0, 0)
node _multipleHits_T_12 = bits(_multipleHits_T_10, 2, 1)
node _multipleHits_T_13 = bits(_multipleHits_T_12, 0, 0)
node multipleHits_leftOne_4 = bits(_multipleHits_T_13, 0, 0)
node _multipleHits_T_14 = bits(_multipleHits_T_12, 1, 1)
node multipleHits_rightOne_2 = bits(_multipleHits_T_14, 0, 0)
node multipleHits_rightOne_3 = or(multipleHits_leftOne_4, multipleHits_rightOne_2)
node _multipleHits_T_15 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_16 = and(multipleHits_leftOne_4, multipleHits_rightOne_2)
node multipleHits_rightTwo_1 = or(_multipleHits_T_15, _multipleHits_T_16)
node multipleHits_rightOne_4 = or(multipleHits_leftOne_3, multipleHits_rightOne_3)
node _multipleHits_T_17 = or(UInt<1>(0h0), multipleHits_rightTwo_1)
node _multipleHits_T_18 = and(multipleHits_leftOne_3, multipleHits_rightOne_3)
node multipleHits_rightTwo_2 = or(_multipleHits_T_17, _multipleHits_T_18)
node multipleHits_leftOne_5 = or(multipleHits_leftOne_2, multipleHits_rightOne_4)
node _multipleHits_T_19 = or(multipleHits_leftTwo, multipleHits_rightTwo_2)
node _multipleHits_T_20 = and(multipleHits_leftOne_2, multipleHits_rightOne_4)
node multipleHits_leftTwo_1 = or(_multipleHits_T_19, _multipleHits_T_20)
node _multipleHits_T_21 = bits(real_hits, 12, 6)
node _multipleHits_T_22 = bits(_multipleHits_T_21, 2, 0)
node _multipleHits_T_23 = bits(_multipleHits_T_22, 0, 0)
node multipleHits_leftOne_6 = bits(_multipleHits_T_23, 0, 0)
node _multipleHits_T_24 = bits(_multipleHits_T_22, 2, 1)
node _multipleHits_T_25 = bits(_multipleHits_T_24, 0, 0)
node multipleHits_leftOne_7 = bits(_multipleHits_T_25, 0, 0)
node _multipleHits_T_26 = bits(_multipleHits_T_24, 1, 1)
node multipleHits_rightOne_5 = bits(_multipleHits_T_26, 0, 0)
node multipleHits_rightOne_6 = or(multipleHits_leftOne_7, multipleHits_rightOne_5)
node _multipleHits_T_27 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_28 = and(multipleHits_leftOne_7, multipleHits_rightOne_5)
node multipleHits_rightTwo_3 = or(_multipleHits_T_27, _multipleHits_T_28)
node multipleHits_leftOne_8 = or(multipleHits_leftOne_6, multipleHits_rightOne_6)
node _multipleHits_T_29 = or(UInt<1>(0h0), multipleHits_rightTwo_3)
node _multipleHits_T_30 = and(multipleHits_leftOne_6, multipleHits_rightOne_6)
node multipleHits_leftTwo_2 = or(_multipleHits_T_29, _multipleHits_T_30)
node _multipleHits_T_31 = bits(_multipleHits_T_21, 6, 3)
node _multipleHits_T_32 = bits(_multipleHits_T_31, 1, 0)
node _multipleHits_T_33 = bits(_multipleHits_T_32, 0, 0)
node multipleHits_leftOne_9 = bits(_multipleHits_T_33, 0, 0)
node _multipleHits_T_34 = bits(_multipleHits_T_32, 1, 1)
node multipleHits_rightOne_7 = bits(_multipleHits_T_34, 0, 0)
node multipleHits_leftOne_10 = or(multipleHits_leftOne_9, multipleHits_rightOne_7)
node _multipleHits_T_35 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_36 = and(multipleHits_leftOne_9, multipleHits_rightOne_7)
node multipleHits_leftTwo_3 = or(_multipleHits_T_35, _multipleHits_T_36)
node _multipleHits_T_37 = bits(_multipleHits_T_31, 3, 2)
node _multipleHits_T_38 = bits(_multipleHits_T_37, 0, 0)
node multipleHits_leftOne_11 = bits(_multipleHits_T_38, 0, 0)
node _multipleHits_T_39 = bits(_multipleHits_T_37, 1, 1)
node multipleHits_rightOne_8 = bits(_multipleHits_T_39, 0, 0)
node multipleHits_rightOne_9 = or(multipleHits_leftOne_11, multipleHits_rightOne_8)
node _multipleHits_T_40 = or(UInt<1>(0h0), UInt<1>(0h0))
node _multipleHits_T_41 = and(multipleHits_leftOne_11, multipleHits_rightOne_8)
node multipleHits_rightTwo_4 = or(_multipleHits_T_40, _multipleHits_T_41)
node multipleHits_rightOne_10 = or(multipleHits_leftOne_10, multipleHits_rightOne_9)
node _multipleHits_T_42 = or(multipleHits_leftTwo_3, multipleHits_rightTwo_4)
node _multipleHits_T_43 = and(multipleHits_leftOne_10, multipleHits_rightOne_9)
node multipleHits_rightTwo_5 = or(_multipleHits_T_42, _multipleHits_T_43)
node multipleHits_rightOne_11 = or(multipleHits_leftOne_8, multipleHits_rightOne_10)
node _multipleHits_T_44 = or(multipleHits_leftTwo_2, multipleHits_rightTwo_5)
node _multipleHits_T_45 = and(multipleHits_leftOne_8, multipleHits_rightOne_10)
node multipleHits_rightTwo_6 = or(_multipleHits_T_44, _multipleHits_T_45)
node _multipleHits_T_46 = or(multipleHits_leftOne_5, multipleHits_rightOne_11)
node _multipleHits_T_47 = or(multipleHits_leftTwo_1, multipleHits_rightTwo_6)
node _multipleHits_T_48 = and(multipleHits_leftOne_5, multipleHits_rightOne_11)
node multipleHits = or(_multipleHits_T_47, _multipleHits_T_48)
node _io_req_ready_T = eq(state, UInt<2>(0h0))
connect io.req.ready, _io_req_ready_T
node _io_resp_pf_ld_T = and(bad_va, cmd_read)
node _io_resp_pf_ld_T_1 = and(pf_ld_array, hits)
node _io_resp_pf_ld_T_2 = orr(_io_resp_pf_ld_T_1)
node _io_resp_pf_ld_T_3 = or(_io_resp_pf_ld_T, _io_resp_pf_ld_T_2)
connect io.resp.pf.ld, _io_resp_pf_ld_T_3
node _io_resp_pf_st_T = and(bad_va, cmd_write_perms)
node _io_resp_pf_st_T_1 = and(pf_st_array, hits)
node _io_resp_pf_st_T_2 = orr(_io_resp_pf_st_T_1)
node _io_resp_pf_st_T_3 = or(_io_resp_pf_st_T, _io_resp_pf_st_T_2)
connect io.resp.pf.st, _io_resp_pf_st_T_3
node _io_resp_pf_inst_T = and(pf_inst_array, hits)
node _io_resp_pf_inst_T_1 = orr(_io_resp_pf_inst_T)
node _io_resp_pf_inst_T_2 = or(bad_va, _io_resp_pf_inst_T_1)
connect io.resp.pf.inst, _io_resp_pf_inst_T_2
node _io_resp_gf_ld_T = and(UInt<1>(0h0), cmd_read)
node _io_resp_gf_ld_T_1 = and(gf_ld_array, hits)
node _io_resp_gf_ld_T_2 = orr(_io_resp_gf_ld_T_1)
node _io_resp_gf_ld_T_3 = or(_io_resp_gf_ld_T, _io_resp_gf_ld_T_2)
connect io.resp.gf.ld, _io_resp_gf_ld_T_3
node _io_resp_gf_st_T = and(UInt<1>(0h0), cmd_write_perms)
node _io_resp_gf_st_T_1 = and(gf_st_array, hits)
node _io_resp_gf_st_T_2 = orr(_io_resp_gf_st_T_1)
node _io_resp_gf_st_T_3 = or(_io_resp_gf_st_T, _io_resp_gf_st_T_2)
connect io.resp.gf.st, _io_resp_gf_st_T_3
node _io_resp_gf_inst_T = and(gf_inst_array, hits)
node _io_resp_gf_inst_T_1 = orr(_io_resp_gf_inst_T)
node _io_resp_gf_inst_T_2 = or(UInt<1>(0h0), _io_resp_gf_inst_T_1)
connect io.resp.gf.inst, _io_resp_gf_inst_T_2
node _io_resp_ae_ld_T = and(ae_ld_array, hits)
node _io_resp_ae_ld_T_1 = orr(_io_resp_ae_ld_T)
connect io.resp.ae.ld, _io_resp_ae_ld_T_1
node _io_resp_ae_st_T = and(ae_st_array, hits)
node _io_resp_ae_st_T_1 = orr(_io_resp_ae_st_T)
connect io.resp.ae.st, _io_resp_ae_st_T_1
node _io_resp_ae_inst_T = not(px_array)
node _io_resp_ae_inst_T_1 = and(_io_resp_ae_inst_T, hits)
node _io_resp_ae_inst_T_2 = orr(_io_resp_ae_inst_T_1)
connect io.resp.ae.inst, _io_resp_ae_inst_T_2
node _io_resp_ma_ld_T = and(misaligned, cmd_read)
connect io.resp.ma.ld, _io_resp_ma_ld_T
node _io_resp_ma_st_T = and(misaligned, cmd_write)
connect io.resp.ma.st, _io_resp_ma_st_T
connect io.resp.ma.inst, UInt<1>(0h0)
node _io_resp_cacheable_T = and(c_array, hits)
node _io_resp_cacheable_T_1 = orr(_io_resp_cacheable_T)
connect io.resp.cacheable, _io_resp_cacheable_T_1
node _io_resp_must_alloc_T = and(must_alloc_array, hits)
node _io_resp_must_alloc_T_1 = orr(_io_resp_must_alloc_T)
connect io.resp.must_alloc, _io_resp_must_alloc_T_1
node _io_resp_prefetchable_T = and(prefetchable_array, hits)
node _io_resp_prefetchable_T_1 = orr(_io_resp_prefetchable_T)
node _io_resp_prefetchable_T_2 = and(_io_resp_prefetchable_T_1, UInt<1>(0h1))
connect io.resp.prefetchable, _io_resp_prefetchable_T_2
node _io_resp_miss_T = or(do_refill, vsatp_mode_mismatch)
node _io_resp_miss_T_1 = or(_io_resp_miss_T, tlb_miss)
node _io_resp_miss_T_2 = or(_io_resp_miss_T_1, multipleHits)
connect io.resp.miss, _io_resp_miss_T_2
node _io_resp_paddr_T = bits(io.req.bits.vaddr, 11, 0)
node _io_resp_paddr_T_1 = cat(ppn, _io_resp_paddr_T)
connect io.resp.paddr, _io_resp_paddr_T_1
connect io.resp.size, io.req.bits.size
connect io.resp.cmd, io.req.bits.cmd
node _io_resp_gpa_is_pte_T = and(vstage1_en, r_gpa_is_pte)
connect io.resp.gpa_is_pte, _io_resp_gpa_is_pte_T
node _io_resp_gpa_page_T = eq(vstage1_en, UInt<1>(0h0))
node _io_resp_gpa_page_T_1 = cat(UInt<1>(0h0), vpn)
node _io_resp_gpa_page_T_2 = shr(r_gpa, 12)
node io_resp_gpa_page = mux(_io_resp_gpa_page_T, _io_resp_gpa_page_T_1, _io_resp_gpa_page_T_2)
node _io_resp_gpa_offset_T = bits(r_gpa, 11, 0)
node _io_resp_gpa_offset_T_1 = bits(io.req.bits.vaddr, 11, 0)
node io_resp_gpa_offset = mux(io.resp.gpa_is_pte, _io_resp_gpa_offset_T, _io_resp_gpa_offset_T_1)
node _io_resp_gpa_T = cat(io_resp_gpa_page, io_resp_gpa_offset)
connect io.resp.gpa, _io_resp_gpa_T
node _io_ptw_req_valid_T = eq(state, UInt<2>(0h1))
connect io.ptw.req.valid, _io_ptw_req_valid_T
node _io_ptw_req_bits_valid_T = eq(io.kill, UInt<1>(0h0))
connect io.ptw.req.bits.valid, _io_ptw_req_bits_valid_T
connect io.ptw.req.bits.bits.addr, r_refill_tag
connect io.ptw.req.bits.bits.vstage1, r_vstage1_en
connect io.ptw.req.bits.bits.stage2, r_stage2_en
connect io.ptw.req.bits.bits.need_gpa, r_need_gpa
node _T_47 = and(io.ptw.req.ready, io.ptw.req.valid)
node _T_48 = and(_T_47, io.ptw.req.bits.valid)
when _T_48 :
connect r_gpa_valid, UInt<1>(0h0)
connect r_gpa_vpn, r_refill_tag
node _T_49 = and(io.req.ready, io.req.valid)
node _T_50 = and(_T_49, tlb_miss)
when _T_50 :
connect state, UInt<2>(0h1)
connect r_refill_tag, vpn
connect r_need_gpa, tlb_hit_if_not_gpa_miss
connect r_vstage1_en, vstage1_en
connect r_stage2_en, stage2_en
node r_superpage_repl_addr_left_subtree_older = bits(state_reg_1, 2, 2)
node r_superpage_repl_addr_left_subtree_state = bits(state_reg_1, 1, 1)
node r_superpage_repl_addr_right_subtree_state = bits(state_reg_1, 0, 0)
node _r_superpage_repl_addr_T = bits(r_superpage_repl_addr_left_subtree_state, 0, 0)
node _r_superpage_repl_addr_T_1 = bits(r_superpage_repl_addr_right_subtree_state, 0, 0)
node _r_superpage_repl_addr_T_2 = mux(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T, _r_superpage_repl_addr_T_1)
node _r_superpage_repl_addr_T_3 = cat(r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2)
node r_superpage_repl_addr_valids_lo = cat(superpage_entries[1].valid[0], superpage_entries[0].valid[0])
node r_superpage_repl_addr_valids_hi = cat(superpage_entries[3].valid[0], superpage_entries[2].valid[0])
node r_superpage_repl_addr_valids = cat(r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo)
node _r_superpage_repl_addr_T_4 = andr(r_superpage_repl_addr_valids)
node _r_superpage_repl_addr_T_5 = not(r_superpage_repl_addr_valids)
node _r_superpage_repl_addr_T_6 = bits(_r_superpage_repl_addr_T_5, 0, 0)
node _r_superpage_repl_addr_T_7 = bits(_r_superpage_repl_addr_T_5, 1, 1)
node _r_superpage_repl_addr_T_8 = bits(_r_superpage_repl_addr_T_5, 2, 2)
node _r_superpage_repl_addr_T_9 = bits(_r_superpage_repl_addr_T_5, 3, 3)
node _r_superpage_repl_addr_T_10 = mux(_r_superpage_repl_addr_T_8, UInt<2>(0h2), UInt<2>(0h3))
node _r_superpage_repl_addr_T_11 = mux(_r_superpage_repl_addr_T_7, UInt<1>(0h1), _r_superpage_repl_addr_T_10)
node _r_superpage_repl_addr_T_12 = mux(_r_superpage_repl_addr_T_6, UInt<1>(0h0), _r_superpage_repl_addr_T_11)
node _r_superpage_repl_addr_T_13 = mux(_r_superpage_repl_addr_T_4, _r_superpage_repl_addr_T_3, _r_superpage_repl_addr_T_12)
connect r_superpage_repl_addr, _r_superpage_repl_addr_T_13
node r_sectored_repl_addr_left_subtree_older = bits(state_vec[0], 6, 6)
node r_sectored_repl_addr_left_subtree_state = bits(state_vec[0], 5, 3)
node r_sectored_repl_addr_right_subtree_state = bits(state_vec[0], 2, 0)
node r_sectored_repl_addr_left_subtree_older_1 = bits(r_sectored_repl_addr_left_subtree_state, 2, 2)
node r_sectored_repl_addr_left_subtree_state_1 = bits(r_sectored_repl_addr_left_subtree_state, 1, 1)
node r_sectored_repl_addr_right_subtree_state_1 = bits(r_sectored_repl_addr_left_subtree_state, 0, 0)
node _r_sectored_repl_addr_T = bits(r_sectored_repl_addr_left_subtree_state_1, 0, 0)
node _r_sectored_repl_addr_T_1 = bits(r_sectored_repl_addr_right_subtree_state_1, 0, 0)
node _r_sectored_repl_addr_T_2 = mux(r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T, _r_sectored_repl_addr_T_1)
node _r_sectored_repl_addr_T_3 = cat(r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T_2)
node r_sectored_repl_addr_left_subtree_older_2 = bits(r_sectored_repl_addr_right_subtree_state, 2, 2)
node r_sectored_repl_addr_left_subtree_state_2 = bits(r_sectored_repl_addr_right_subtree_state, 1, 1)
node r_sectored_repl_addr_right_subtree_state_2 = bits(r_sectored_repl_addr_right_subtree_state, 0, 0)
node _r_sectored_repl_addr_T_4 = bits(r_sectored_repl_addr_left_subtree_state_2, 0, 0)
node _r_sectored_repl_addr_T_5 = bits(r_sectored_repl_addr_right_subtree_state_2, 0, 0)
node _r_sectored_repl_addr_T_6 = mux(r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_4, _r_sectored_repl_addr_T_5)
node _r_sectored_repl_addr_T_7 = cat(r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_6)
node _r_sectored_repl_addr_T_8 = mux(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_3, _r_sectored_repl_addr_T_7)
node _r_sectored_repl_addr_T_9 = cat(r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_8)
node _r_sectored_repl_addr_valids_T = or(sectored_entries[0][0].valid[0], sectored_entries[0][0].valid[1])
node _r_sectored_repl_addr_valids_T_1 = or(_r_sectored_repl_addr_valids_T, sectored_entries[0][0].valid[2])
node _r_sectored_repl_addr_valids_T_2 = or(_r_sectored_repl_addr_valids_T_1, sectored_entries[0][0].valid[3])
node _r_sectored_repl_addr_valids_T_3 = or(sectored_entries[0][1].valid[0], sectored_entries[0][1].valid[1])
node _r_sectored_repl_addr_valids_T_4 = or(_r_sectored_repl_addr_valids_T_3, sectored_entries[0][1].valid[2])
node _r_sectored_repl_addr_valids_T_5 = or(_r_sectored_repl_addr_valids_T_4, sectored_entries[0][1].valid[3])
node _r_sectored_repl_addr_valids_T_6 = or(sectored_entries[0][2].valid[0], sectored_entries[0][2].valid[1])
node _r_sectored_repl_addr_valids_T_7 = or(_r_sectored_repl_addr_valids_T_6, sectored_entries[0][2].valid[2])
node _r_sectored_repl_addr_valids_T_8 = or(_r_sectored_repl_addr_valids_T_7, sectored_entries[0][2].valid[3])
node _r_sectored_repl_addr_valids_T_9 = or(sectored_entries[0][3].valid[0], sectored_entries[0][3].valid[1])
node _r_sectored_repl_addr_valids_T_10 = or(_r_sectored_repl_addr_valids_T_9, sectored_entries[0][3].valid[2])
node _r_sectored_repl_addr_valids_T_11 = or(_r_sectored_repl_addr_valids_T_10, sectored_entries[0][3].valid[3])
node _r_sectored_repl_addr_valids_T_12 = or(sectored_entries[0][4].valid[0], sectored_entries[0][4].valid[1])
node _r_sectored_repl_addr_valids_T_13 = or(_r_sectored_repl_addr_valids_T_12, sectored_entries[0][4].valid[2])
node _r_sectored_repl_addr_valids_T_14 = or(_r_sectored_repl_addr_valids_T_13, sectored_entries[0][4].valid[3])
node _r_sectored_repl_addr_valids_T_15 = or(sectored_entries[0][5].valid[0], sectored_entries[0][5].valid[1])
node _r_sectored_repl_addr_valids_T_16 = or(_r_sectored_repl_addr_valids_T_15, sectored_entries[0][5].valid[2])
node _r_sectored_repl_addr_valids_T_17 = or(_r_sectored_repl_addr_valids_T_16, sectored_entries[0][5].valid[3])
node _r_sectored_repl_addr_valids_T_18 = or(sectored_entries[0][6].valid[0], sectored_entries[0][6].valid[1])
node _r_sectored_repl_addr_valids_T_19 = or(_r_sectored_repl_addr_valids_T_18, sectored_entries[0][6].valid[2])
node _r_sectored_repl_addr_valids_T_20 = or(_r_sectored_repl_addr_valids_T_19, sectored_entries[0][6].valid[3])
node _r_sectored_repl_addr_valids_T_21 = or(sectored_entries[0][7].valid[0], sectored_entries[0][7].valid[1])
node _r_sectored_repl_addr_valids_T_22 = or(_r_sectored_repl_addr_valids_T_21, sectored_entries[0][7].valid[2])
node _r_sectored_repl_addr_valids_T_23 = or(_r_sectored_repl_addr_valids_T_22, sectored_entries[0][7].valid[3])
node r_sectored_repl_addr_valids_lo_lo = cat(_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2)
node r_sectored_repl_addr_valids_lo_hi = cat(_r_sectored_repl_addr_valids_T_11, _r_sectored_repl_addr_valids_T_8)
node r_sectored_repl_addr_valids_lo = cat(r_sectored_repl_addr_valids_lo_hi, r_sectored_repl_addr_valids_lo_lo)
node r_sectored_repl_addr_valids_hi_lo = cat(_r_sectored_repl_addr_valids_T_17, _r_sectored_repl_addr_valids_T_14)
node r_sectored_repl_addr_valids_hi_hi = cat(_r_sectored_repl_addr_valids_T_23, _r_sectored_repl_addr_valids_T_20)
node r_sectored_repl_addr_valids_hi = cat(r_sectored_repl_addr_valids_hi_hi, r_sectored_repl_addr_valids_hi_lo)
node r_sectored_repl_addr_valids = cat(r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo)
node _r_sectored_repl_addr_T_10 = andr(r_sectored_repl_addr_valids)
node _r_sectored_repl_addr_T_11 = not(r_sectored_repl_addr_valids)
node _r_sectored_repl_addr_T_12 = bits(_r_sectored_repl_addr_T_11, 0, 0)
node _r_sectored_repl_addr_T_13 = bits(_r_sectored_repl_addr_T_11, 1, 1)
node _r_sectored_repl_addr_T_14 = bits(_r_sectored_repl_addr_T_11, 2, 2)
node _r_sectored_repl_addr_T_15 = bits(_r_sectored_repl_addr_T_11, 3, 3)
node _r_sectored_repl_addr_T_16 = bits(_r_sectored_repl_addr_T_11, 4, 4)
node _r_sectored_repl_addr_T_17 = bits(_r_sectored_repl_addr_T_11, 5, 5)
node _r_sectored_repl_addr_T_18 = bits(_r_sectored_repl_addr_T_11, 6, 6)
node _r_sectored_repl_addr_T_19 = bits(_r_sectored_repl_addr_T_11, 7, 7)
node _r_sectored_repl_addr_T_20 = mux(_r_sectored_repl_addr_T_18, UInt<3>(0h6), UInt<3>(0h7))
node _r_sectored_repl_addr_T_21 = mux(_r_sectored_repl_addr_T_17, UInt<3>(0h5), _r_sectored_repl_addr_T_20)
node _r_sectored_repl_addr_T_22 = mux(_r_sectored_repl_addr_T_16, UInt<3>(0h4), _r_sectored_repl_addr_T_21)
node _r_sectored_repl_addr_T_23 = mux(_r_sectored_repl_addr_T_15, UInt<2>(0h3), _r_sectored_repl_addr_T_22)
node _r_sectored_repl_addr_T_24 = mux(_r_sectored_repl_addr_T_14, UInt<2>(0h2), _r_sectored_repl_addr_T_23)
node _r_sectored_repl_addr_T_25 = mux(_r_sectored_repl_addr_T_13, UInt<1>(0h1), _r_sectored_repl_addr_T_24)
node _r_sectored_repl_addr_T_26 = mux(_r_sectored_repl_addr_T_12, UInt<1>(0h0), _r_sectored_repl_addr_T_25)
node _r_sectored_repl_addr_T_27 = mux(_r_sectored_repl_addr_T_10, _r_sectored_repl_addr_T_9, _r_sectored_repl_addr_T_26)
connect r_sectored_repl_addr, _r_sectored_repl_addr_T_27
node _r_sectored_hit_valid_T = or(sector_hits_0, sector_hits_1)
node _r_sectored_hit_valid_T_1 = or(_r_sectored_hit_valid_T, sector_hits_2)
node _r_sectored_hit_valid_T_2 = or(_r_sectored_hit_valid_T_1, sector_hits_3)
node _r_sectored_hit_valid_T_3 = or(_r_sectored_hit_valid_T_2, sector_hits_4)
node _r_sectored_hit_valid_T_4 = or(_r_sectored_hit_valid_T_3, sector_hits_5)
node _r_sectored_hit_valid_T_5 = or(_r_sectored_hit_valid_T_4, sector_hits_6)
node _r_sectored_hit_valid_T_6 = or(_r_sectored_hit_valid_T_5, sector_hits_7)
connect r_sectored_hit.valid, _r_sectored_hit_valid_T_6
node r_sectored_hit_bits_lo_lo = cat(sector_hits_1, sector_hits_0)
node r_sectored_hit_bits_lo_hi = cat(sector_hits_3, sector_hits_2)
node r_sectored_hit_bits_lo = cat(r_sectored_hit_bits_lo_hi, r_sectored_hit_bits_lo_lo)
node r_sectored_hit_bits_hi_lo = cat(sector_hits_5, sector_hits_4)
node r_sectored_hit_bits_hi_hi = cat(sector_hits_7, sector_hits_6)
node r_sectored_hit_bits_hi = cat(r_sectored_hit_bits_hi_hi, r_sectored_hit_bits_hi_lo)
node _r_sectored_hit_bits_T = cat(r_sectored_hit_bits_hi, r_sectored_hit_bits_lo)
node r_sectored_hit_bits_hi_1 = bits(_r_sectored_hit_bits_T, 7, 4)
node r_sectored_hit_bits_lo_1 = bits(_r_sectored_hit_bits_T, 3, 0)
node _r_sectored_hit_bits_T_1 = orr(r_sectored_hit_bits_hi_1)
node _r_sectored_hit_bits_T_2 = or(r_sectored_hit_bits_hi_1, r_sectored_hit_bits_lo_1)
node r_sectored_hit_bits_hi_2 = bits(_r_sectored_hit_bits_T_2, 3, 2)
node r_sectored_hit_bits_lo_2 = bits(_r_sectored_hit_bits_T_2, 1, 0)
node _r_sectored_hit_bits_T_3 = orr(r_sectored_hit_bits_hi_2)
node _r_sectored_hit_bits_T_4 = or(r_sectored_hit_bits_hi_2, r_sectored_hit_bits_lo_2)
node _r_sectored_hit_bits_T_5 = bits(_r_sectored_hit_bits_T_4, 1, 1)
node _r_sectored_hit_bits_T_6 = cat(_r_sectored_hit_bits_T_3, _r_sectored_hit_bits_T_5)
node _r_sectored_hit_bits_T_7 = cat(_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_6)
connect r_sectored_hit.bits, _r_sectored_hit_bits_T_7
node _r_superpage_hit_valid_T = or(superpage_hits_0, superpage_hits_1)
node _r_superpage_hit_valid_T_1 = or(_r_superpage_hit_valid_T, superpage_hits_2)
node _r_superpage_hit_valid_T_2 = or(_r_superpage_hit_valid_T_1, superpage_hits_3)
connect r_superpage_hit.valid, _r_superpage_hit_valid_T_2
node r_superpage_hit_bits_lo = cat(superpage_hits_1, superpage_hits_0)
node r_superpage_hit_bits_hi = cat(superpage_hits_3, superpage_hits_2)
node _r_superpage_hit_bits_T = cat(r_superpage_hit_bits_hi, r_superpage_hit_bits_lo)
node r_superpage_hit_bits_hi_1 = bits(_r_superpage_hit_bits_T, 3, 2)
node r_superpage_hit_bits_lo_1 = bits(_r_superpage_hit_bits_T, 1, 0)
node _r_superpage_hit_bits_T_1 = orr(r_superpage_hit_bits_hi_1)
node _r_superpage_hit_bits_T_2 = or(r_superpage_hit_bits_hi_1, r_superpage_hit_bits_lo_1)
node _r_superpage_hit_bits_T_3 = bits(_r_superpage_hit_bits_T_2, 1, 1)
node _r_superpage_hit_bits_T_4 = cat(_r_superpage_hit_bits_T_1, _r_superpage_hit_bits_T_3)
connect r_superpage_hit.bits, _r_superpage_hit_bits_T_4
node _T_51 = eq(state, UInt<2>(0h1))
when _T_51 :
when io.sfence.valid :
connect state, UInt<2>(0h0)
when io.ptw.req.ready :
node _state_T = mux(io.sfence.valid, UInt<2>(0h3), UInt<2>(0h2))
connect state, _state_T
when io.kill :
connect state, UInt<2>(0h0)
node _T_52 = eq(state, UInt<2>(0h2))
node _T_53 = and(_T_52, io.sfence.valid)
when _T_53 :
connect state, UInt<2>(0h3)
when io.ptw.resp.valid :
connect state, UInt<2>(0h0)
when io.sfence.valid :
node _T_54 = eq(io.sfence.bits.rs1, UInt<1>(0h0))
node _T_55 = shr(io.sfence.bits.addr, 12)
node _T_56 = eq(_T_55, vpn)
node _T_57 = or(_T_54, _T_56)
node _T_58 = asUInt(reset)
node _T_59 = eq(_T_58, UInt<1>(0h0))
when _T_59 :
node _T_60 = eq(_T_57, UInt<1>(0h0))
when _T_60 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at TLB.scala:719 assert(!io.sfence.bits.rs1 || (io.sfence.bits.addr >> pgIdxBits) === vpn)\n") : printf
assert(clock, _T_57, UInt<1>(0h1), "") : assert
node hv = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_61 = eq(hg, UInt<1>(0h0))
node _T_62 = and(_T_61, io.sfence.bits.rs1)
when _T_62 :
node _T_63 = xor(sectored_entries[0][0].tag_vpn, vpn)
node _T_64 = shr(_T_63, 2)
node _T_65 = eq(_T_64, UInt<1>(0h0))
node _T_66 = eq(sectored_entries[0][0].tag_v, hv)
node _T_67 = and(_T_65, _T_66)
when _T_67 :
wire _WIRE : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_1 : UInt<42>
connect _WIRE_1, sectored_entries[0][0].data[0]
node _T_68 = bits(_WIRE_1, 0, 0)
connect _WIRE.fragmented_superpage, _T_68
node _T_69 = bits(_WIRE_1, 1, 1)
connect _WIRE.c, _T_69
node _T_70 = bits(_WIRE_1, 2, 2)
connect _WIRE.eff, _T_70
node _T_71 = bits(_WIRE_1, 3, 3)
connect _WIRE.paa, _T_71
node _T_72 = bits(_WIRE_1, 4, 4)
connect _WIRE.pal, _T_72
node _T_73 = bits(_WIRE_1, 5, 5)
connect _WIRE.ppp, _T_73
node _T_74 = bits(_WIRE_1, 6, 6)
connect _WIRE.pr, _T_74
node _T_75 = bits(_WIRE_1, 7, 7)
connect _WIRE.px, _T_75
node _T_76 = bits(_WIRE_1, 8, 8)
connect _WIRE.pw, _T_76
node _T_77 = bits(_WIRE_1, 9, 9)
connect _WIRE.hr, _T_77
node _T_78 = bits(_WIRE_1, 10, 10)
connect _WIRE.hx, _T_78
node _T_79 = bits(_WIRE_1, 11, 11)
connect _WIRE.hw, _T_79
node _T_80 = bits(_WIRE_1, 12, 12)
connect _WIRE.sr, _T_80
node _T_81 = bits(_WIRE_1, 13, 13)
connect _WIRE.sx, _T_81
node _T_82 = bits(_WIRE_1, 14, 14)
connect _WIRE.sw, _T_82
node _T_83 = bits(_WIRE_1, 15, 15)
connect _WIRE.gf, _T_83
node _T_84 = bits(_WIRE_1, 16, 16)
connect _WIRE.pf, _T_84
node _T_85 = bits(_WIRE_1, 17, 17)
connect _WIRE.ae_stage2, _T_85
node _T_86 = bits(_WIRE_1, 18, 18)
connect _WIRE.ae_final, _T_86
node _T_87 = bits(_WIRE_1, 19, 19)
connect _WIRE.ae_ptw, _T_87
node _T_88 = bits(_WIRE_1, 20, 20)
connect _WIRE.g, _T_88
node _T_89 = bits(_WIRE_1, 21, 21)
connect _WIRE.u, _T_89
node _T_90 = bits(_WIRE_1, 41, 22)
connect _WIRE.ppn, _T_90
wire _WIRE_2 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_3 : UInt<42>
connect _WIRE_3, sectored_entries[0][0].data[1]
node _T_91 = bits(_WIRE_3, 0, 0)
connect _WIRE_2.fragmented_superpage, _T_91
node _T_92 = bits(_WIRE_3, 1, 1)
connect _WIRE_2.c, _T_92
node _T_93 = bits(_WIRE_3, 2, 2)
connect _WIRE_2.eff, _T_93
node _T_94 = bits(_WIRE_3, 3, 3)
connect _WIRE_2.paa, _T_94
node _T_95 = bits(_WIRE_3, 4, 4)
connect _WIRE_2.pal, _T_95
node _T_96 = bits(_WIRE_3, 5, 5)
connect _WIRE_2.ppp, _T_96
node _T_97 = bits(_WIRE_3, 6, 6)
connect _WIRE_2.pr, _T_97
node _T_98 = bits(_WIRE_3, 7, 7)
connect _WIRE_2.px, _T_98
node _T_99 = bits(_WIRE_3, 8, 8)
connect _WIRE_2.pw, _T_99
node _T_100 = bits(_WIRE_3, 9, 9)
connect _WIRE_2.hr, _T_100
node _T_101 = bits(_WIRE_3, 10, 10)
connect _WIRE_2.hx, _T_101
node _T_102 = bits(_WIRE_3, 11, 11)
connect _WIRE_2.hw, _T_102
node _T_103 = bits(_WIRE_3, 12, 12)
connect _WIRE_2.sr, _T_103
node _T_104 = bits(_WIRE_3, 13, 13)
connect _WIRE_2.sx, _T_104
node _T_105 = bits(_WIRE_3, 14, 14)
connect _WIRE_2.sw, _T_105
node _T_106 = bits(_WIRE_3, 15, 15)
connect _WIRE_2.gf, _T_106
node _T_107 = bits(_WIRE_3, 16, 16)
connect _WIRE_2.pf, _T_107
node _T_108 = bits(_WIRE_3, 17, 17)
connect _WIRE_2.ae_stage2, _T_108
node _T_109 = bits(_WIRE_3, 18, 18)
connect _WIRE_2.ae_final, _T_109
node _T_110 = bits(_WIRE_3, 19, 19)
connect _WIRE_2.ae_ptw, _T_110
node _T_111 = bits(_WIRE_3, 20, 20)
connect _WIRE_2.g, _T_111
node _T_112 = bits(_WIRE_3, 21, 21)
connect _WIRE_2.u, _T_112
node _T_113 = bits(_WIRE_3, 41, 22)
connect _WIRE_2.ppn, _T_113
wire _WIRE_4 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_5 : UInt<42>
connect _WIRE_5, sectored_entries[0][0].data[2]
node _T_114 = bits(_WIRE_5, 0, 0)
connect _WIRE_4.fragmented_superpage, _T_114
node _T_115 = bits(_WIRE_5, 1, 1)
connect _WIRE_4.c, _T_115
node _T_116 = bits(_WIRE_5, 2, 2)
connect _WIRE_4.eff, _T_116
node _T_117 = bits(_WIRE_5, 3, 3)
connect _WIRE_4.paa, _T_117
node _T_118 = bits(_WIRE_5, 4, 4)
connect _WIRE_4.pal, _T_118
node _T_119 = bits(_WIRE_5, 5, 5)
connect _WIRE_4.ppp, _T_119
node _T_120 = bits(_WIRE_5, 6, 6)
connect _WIRE_4.pr, _T_120
node _T_121 = bits(_WIRE_5, 7, 7)
connect _WIRE_4.px, _T_121
node _T_122 = bits(_WIRE_5, 8, 8)
connect _WIRE_4.pw, _T_122
node _T_123 = bits(_WIRE_5, 9, 9)
connect _WIRE_4.hr, _T_123
node _T_124 = bits(_WIRE_5, 10, 10)
connect _WIRE_4.hx, _T_124
node _T_125 = bits(_WIRE_5, 11, 11)
connect _WIRE_4.hw, _T_125
node _T_126 = bits(_WIRE_5, 12, 12)
connect _WIRE_4.sr, _T_126
node _T_127 = bits(_WIRE_5, 13, 13)
connect _WIRE_4.sx, _T_127
node _T_128 = bits(_WIRE_5, 14, 14)
connect _WIRE_4.sw, _T_128
node _T_129 = bits(_WIRE_5, 15, 15)
connect _WIRE_4.gf, _T_129
node _T_130 = bits(_WIRE_5, 16, 16)
connect _WIRE_4.pf, _T_130
node _T_131 = bits(_WIRE_5, 17, 17)
connect _WIRE_4.ae_stage2, _T_131
node _T_132 = bits(_WIRE_5, 18, 18)
connect _WIRE_4.ae_final, _T_132
node _T_133 = bits(_WIRE_5, 19, 19)
connect _WIRE_4.ae_ptw, _T_133
node _T_134 = bits(_WIRE_5, 20, 20)
connect _WIRE_4.g, _T_134
node _T_135 = bits(_WIRE_5, 21, 21)
connect _WIRE_4.u, _T_135
node _T_136 = bits(_WIRE_5, 41, 22)
connect _WIRE_4.ppn, _T_136
wire _WIRE_6 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_7 : UInt<42>
connect _WIRE_7, sectored_entries[0][0].data[3]
node _T_137 = bits(_WIRE_7, 0, 0)
connect _WIRE_6.fragmented_superpage, _T_137
node _T_138 = bits(_WIRE_7, 1, 1)
connect _WIRE_6.c, _T_138
node _T_139 = bits(_WIRE_7, 2, 2)
connect _WIRE_6.eff, _T_139
node _T_140 = bits(_WIRE_7, 3, 3)
connect _WIRE_6.paa, _T_140
node _T_141 = bits(_WIRE_7, 4, 4)
connect _WIRE_6.pal, _T_141
node _T_142 = bits(_WIRE_7, 5, 5)
connect _WIRE_6.ppp, _T_142
node _T_143 = bits(_WIRE_7, 6, 6)
connect _WIRE_6.pr, _T_143
node _T_144 = bits(_WIRE_7, 7, 7)
connect _WIRE_6.px, _T_144
node _T_145 = bits(_WIRE_7, 8, 8)
connect _WIRE_6.pw, _T_145
node _T_146 = bits(_WIRE_7, 9, 9)
connect _WIRE_6.hr, _T_146
node _T_147 = bits(_WIRE_7, 10, 10)
connect _WIRE_6.hx, _T_147
node _T_148 = bits(_WIRE_7, 11, 11)
connect _WIRE_6.hw, _T_148
node _T_149 = bits(_WIRE_7, 12, 12)
connect _WIRE_6.sr, _T_149
node _T_150 = bits(_WIRE_7, 13, 13)
connect _WIRE_6.sx, _T_150
node _T_151 = bits(_WIRE_7, 14, 14)
connect _WIRE_6.sw, _T_151
node _T_152 = bits(_WIRE_7, 15, 15)
connect _WIRE_6.gf, _T_152
node _T_153 = bits(_WIRE_7, 16, 16)
connect _WIRE_6.pf, _T_153
node _T_154 = bits(_WIRE_7, 17, 17)
connect _WIRE_6.ae_stage2, _T_154
node _T_155 = bits(_WIRE_7, 18, 18)
connect _WIRE_6.ae_final, _T_155
node _T_156 = bits(_WIRE_7, 19, 19)
connect _WIRE_6.ae_ptw, _T_156
node _T_157 = bits(_WIRE_7, 20, 20)
connect _WIRE_6.g, _T_157
node _T_158 = bits(_WIRE_7, 21, 21)
connect _WIRE_6.u, _T_158
node _T_159 = bits(_WIRE_7, 41, 22)
connect _WIRE_6.ppn, _T_159
node _T_160 = eq(sectored_entries[0][0].tag_v, hv)
node _T_161 = bits(vpn, 1, 0)
node _T_162 = eq(UInt<1>(0h0), _T_161)
node _T_163 = and(_T_160, _T_162)
when _T_163 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
node _T_164 = eq(sectored_entries[0][0].tag_v, hv)
node _T_165 = bits(vpn, 1, 0)
node _T_166 = eq(UInt<1>(0h1), _T_165)
node _T_167 = and(_T_164, _T_166)
when _T_167 :
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
node _T_168 = eq(sectored_entries[0][0].tag_v, hv)
node _T_169 = bits(vpn, 1, 0)
node _T_170 = eq(UInt<2>(0h2), _T_169)
node _T_171 = and(_T_168, _T_170)
when _T_171 :
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
node _T_172 = eq(sectored_entries[0][0].tag_v, hv)
node _T_173 = bits(vpn, 1, 0)
node _T_174 = eq(UInt<2>(0h3), _T_173)
node _T_175 = and(_T_172, _T_174)
when _T_175 :
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
node _T_176 = xor(sectored_entries[0][0].tag_vpn, vpn)
node _T_177 = shr(_T_176, 18)
node _T_178 = eq(_T_177, UInt<1>(0h0))
when _T_178 :
wire _WIRE_8 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_9 : UInt<42>
connect _WIRE_9, sectored_entries[0][0].data[0]
node _T_179 = bits(_WIRE_9, 0, 0)
connect _WIRE_8.fragmented_superpage, _T_179
node _T_180 = bits(_WIRE_9, 1, 1)
connect _WIRE_8.c, _T_180
node _T_181 = bits(_WIRE_9, 2, 2)
connect _WIRE_8.eff, _T_181
node _T_182 = bits(_WIRE_9, 3, 3)
connect _WIRE_8.paa, _T_182
node _T_183 = bits(_WIRE_9, 4, 4)
connect _WIRE_8.pal, _T_183
node _T_184 = bits(_WIRE_9, 5, 5)
connect _WIRE_8.ppp, _T_184
node _T_185 = bits(_WIRE_9, 6, 6)
connect _WIRE_8.pr, _T_185
node _T_186 = bits(_WIRE_9, 7, 7)
connect _WIRE_8.px, _T_186
node _T_187 = bits(_WIRE_9, 8, 8)
connect _WIRE_8.pw, _T_187
node _T_188 = bits(_WIRE_9, 9, 9)
connect _WIRE_8.hr, _T_188
node _T_189 = bits(_WIRE_9, 10, 10)
connect _WIRE_8.hx, _T_189
node _T_190 = bits(_WIRE_9, 11, 11)
connect _WIRE_8.hw, _T_190
node _T_191 = bits(_WIRE_9, 12, 12)
connect _WIRE_8.sr, _T_191
node _T_192 = bits(_WIRE_9, 13, 13)
connect _WIRE_8.sx, _T_192
node _T_193 = bits(_WIRE_9, 14, 14)
connect _WIRE_8.sw, _T_193
node _T_194 = bits(_WIRE_9, 15, 15)
connect _WIRE_8.gf, _T_194
node _T_195 = bits(_WIRE_9, 16, 16)
connect _WIRE_8.pf, _T_195
node _T_196 = bits(_WIRE_9, 17, 17)
connect _WIRE_8.ae_stage2, _T_196
node _T_197 = bits(_WIRE_9, 18, 18)
connect _WIRE_8.ae_final, _T_197
node _T_198 = bits(_WIRE_9, 19, 19)
connect _WIRE_8.ae_ptw, _T_198
node _T_199 = bits(_WIRE_9, 20, 20)
connect _WIRE_8.g, _T_199
node _T_200 = bits(_WIRE_9, 21, 21)
connect _WIRE_8.u, _T_200
node _T_201 = bits(_WIRE_9, 41, 22)
connect _WIRE_8.ppn, _T_201
wire _WIRE_10 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_11 : UInt<42>
connect _WIRE_11, sectored_entries[0][0].data[1]
node _T_202 = bits(_WIRE_11, 0, 0)
connect _WIRE_10.fragmented_superpage, _T_202
node _T_203 = bits(_WIRE_11, 1, 1)
connect _WIRE_10.c, _T_203
node _T_204 = bits(_WIRE_11, 2, 2)
connect _WIRE_10.eff, _T_204
node _T_205 = bits(_WIRE_11, 3, 3)
connect _WIRE_10.paa, _T_205
node _T_206 = bits(_WIRE_11, 4, 4)
connect _WIRE_10.pal, _T_206
node _T_207 = bits(_WIRE_11, 5, 5)
connect _WIRE_10.ppp, _T_207
node _T_208 = bits(_WIRE_11, 6, 6)
connect _WIRE_10.pr, _T_208
node _T_209 = bits(_WIRE_11, 7, 7)
connect _WIRE_10.px, _T_209
node _T_210 = bits(_WIRE_11, 8, 8)
connect _WIRE_10.pw, _T_210
node _T_211 = bits(_WIRE_11, 9, 9)
connect _WIRE_10.hr, _T_211
node _T_212 = bits(_WIRE_11, 10, 10)
connect _WIRE_10.hx, _T_212
node _T_213 = bits(_WIRE_11, 11, 11)
connect _WIRE_10.hw, _T_213
node _T_214 = bits(_WIRE_11, 12, 12)
connect _WIRE_10.sr, _T_214
node _T_215 = bits(_WIRE_11, 13, 13)
connect _WIRE_10.sx, _T_215
node _T_216 = bits(_WIRE_11, 14, 14)
connect _WIRE_10.sw, _T_216
node _T_217 = bits(_WIRE_11, 15, 15)
connect _WIRE_10.gf, _T_217
node _T_218 = bits(_WIRE_11, 16, 16)
connect _WIRE_10.pf, _T_218
node _T_219 = bits(_WIRE_11, 17, 17)
connect _WIRE_10.ae_stage2, _T_219
node _T_220 = bits(_WIRE_11, 18, 18)
connect _WIRE_10.ae_final, _T_220
node _T_221 = bits(_WIRE_11, 19, 19)
connect _WIRE_10.ae_ptw, _T_221
node _T_222 = bits(_WIRE_11, 20, 20)
connect _WIRE_10.g, _T_222
node _T_223 = bits(_WIRE_11, 21, 21)
connect _WIRE_10.u, _T_223
node _T_224 = bits(_WIRE_11, 41, 22)
connect _WIRE_10.ppn, _T_224
wire _WIRE_12 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_13 : UInt<42>
connect _WIRE_13, sectored_entries[0][0].data[2]
node _T_225 = bits(_WIRE_13, 0, 0)
connect _WIRE_12.fragmented_superpage, _T_225
node _T_226 = bits(_WIRE_13, 1, 1)
connect _WIRE_12.c, _T_226
node _T_227 = bits(_WIRE_13, 2, 2)
connect _WIRE_12.eff, _T_227
node _T_228 = bits(_WIRE_13, 3, 3)
connect _WIRE_12.paa, _T_228
node _T_229 = bits(_WIRE_13, 4, 4)
connect _WIRE_12.pal, _T_229
node _T_230 = bits(_WIRE_13, 5, 5)
connect _WIRE_12.ppp, _T_230
node _T_231 = bits(_WIRE_13, 6, 6)
connect _WIRE_12.pr, _T_231
node _T_232 = bits(_WIRE_13, 7, 7)
connect _WIRE_12.px, _T_232
node _T_233 = bits(_WIRE_13, 8, 8)
connect _WIRE_12.pw, _T_233
node _T_234 = bits(_WIRE_13, 9, 9)
connect _WIRE_12.hr, _T_234
node _T_235 = bits(_WIRE_13, 10, 10)
connect _WIRE_12.hx, _T_235
node _T_236 = bits(_WIRE_13, 11, 11)
connect _WIRE_12.hw, _T_236
node _T_237 = bits(_WIRE_13, 12, 12)
connect _WIRE_12.sr, _T_237
node _T_238 = bits(_WIRE_13, 13, 13)
connect _WIRE_12.sx, _T_238
node _T_239 = bits(_WIRE_13, 14, 14)
connect _WIRE_12.sw, _T_239
node _T_240 = bits(_WIRE_13, 15, 15)
connect _WIRE_12.gf, _T_240
node _T_241 = bits(_WIRE_13, 16, 16)
connect _WIRE_12.pf, _T_241
node _T_242 = bits(_WIRE_13, 17, 17)
connect _WIRE_12.ae_stage2, _T_242
node _T_243 = bits(_WIRE_13, 18, 18)
connect _WIRE_12.ae_final, _T_243
node _T_244 = bits(_WIRE_13, 19, 19)
connect _WIRE_12.ae_ptw, _T_244
node _T_245 = bits(_WIRE_13, 20, 20)
connect _WIRE_12.g, _T_245
node _T_246 = bits(_WIRE_13, 21, 21)
connect _WIRE_12.u, _T_246
node _T_247 = bits(_WIRE_13, 41, 22)
connect _WIRE_12.ppn, _T_247
wire _WIRE_14 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_15 : UInt<42>
connect _WIRE_15, sectored_entries[0][0].data[3]
node _T_248 = bits(_WIRE_15, 0, 0)
connect _WIRE_14.fragmented_superpage, _T_248
node _T_249 = bits(_WIRE_15, 1, 1)
connect _WIRE_14.c, _T_249
node _T_250 = bits(_WIRE_15, 2, 2)
connect _WIRE_14.eff, _T_250
node _T_251 = bits(_WIRE_15, 3, 3)
connect _WIRE_14.paa, _T_251
node _T_252 = bits(_WIRE_15, 4, 4)
connect _WIRE_14.pal, _T_252
node _T_253 = bits(_WIRE_15, 5, 5)
connect _WIRE_14.ppp, _T_253
node _T_254 = bits(_WIRE_15, 6, 6)
connect _WIRE_14.pr, _T_254
node _T_255 = bits(_WIRE_15, 7, 7)
connect _WIRE_14.px, _T_255
node _T_256 = bits(_WIRE_15, 8, 8)
connect _WIRE_14.pw, _T_256
node _T_257 = bits(_WIRE_15, 9, 9)
connect _WIRE_14.hr, _T_257
node _T_258 = bits(_WIRE_15, 10, 10)
connect _WIRE_14.hx, _T_258
node _T_259 = bits(_WIRE_15, 11, 11)
connect _WIRE_14.hw, _T_259
node _T_260 = bits(_WIRE_15, 12, 12)
connect _WIRE_14.sr, _T_260
node _T_261 = bits(_WIRE_15, 13, 13)
connect _WIRE_14.sx, _T_261
node _T_262 = bits(_WIRE_15, 14, 14)
connect _WIRE_14.sw, _T_262
node _T_263 = bits(_WIRE_15, 15, 15)
connect _WIRE_14.gf, _T_263
node _T_264 = bits(_WIRE_15, 16, 16)
connect _WIRE_14.pf, _T_264
node _T_265 = bits(_WIRE_15, 17, 17)
connect _WIRE_14.ae_stage2, _T_265
node _T_266 = bits(_WIRE_15, 18, 18)
connect _WIRE_14.ae_final, _T_266
node _T_267 = bits(_WIRE_15, 19, 19)
connect _WIRE_14.ae_ptw, _T_267
node _T_268 = bits(_WIRE_15, 20, 20)
connect _WIRE_14.g, _T_268
node _T_269 = bits(_WIRE_15, 21, 21)
connect _WIRE_14.u, _T_269
node _T_270 = bits(_WIRE_15, 41, 22)
connect _WIRE_14.ppn, _T_270
node _T_271 = eq(sectored_entries[0][0].tag_v, hv)
node _T_272 = and(_T_271, _WIRE_8.fragmented_superpage)
when _T_272 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
node _T_273 = eq(sectored_entries[0][0].tag_v, hv)
node _T_274 = and(_T_273, _WIRE_10.fragmented_superpage)
when _T_274 :
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
node _T_275 = eq(sectored_entries[0][0].tag_v, hv)
node _T_276 = and(_T_275, _WIRE_12.fragmented_superpage)
when _T_276 :
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
node _T_277 = eq(sectored_entries[0][0].tag_v, hv)
node _T_278 = and(_T_277, _WIRE_14.fragmented_superpage)
when _T_278 :
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
else :
node _T_279 = eq(hg, UInt<1>(0h0))
node _T_280 = and(_T_279, io.sfence.bits.rs2)
when _T_280 :
wire _WIRE_16 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_17 : UInt<42>
connect _WIRE_17, sectored_entries[0][0].data[0]
node _T_281 = bits(_WIRE_17, 0, 0)
connect _WIRE_16.fragmented_superpage, _T_281
node _T_282 = bits(_WIRE_17, 1, 1)
connect _WIRE_16.c, _T_282
node _T_283 = bits(_WIRE_17, 2, 2)
connect _WIRE_16.eff, _T_283
node _T_284 = bits(_WIRE_17, 3, 3)
connect _WIRE_16.paa, _T_284
node _T_285 = bits(_WIRE_17, 4, 4)
connect _WIRE_16.pal, _T_285
node _T_286 = bits(_WIRE_17, 5, 5)
connect _WIRE_16.ppp, _T_286
node _T_287 = bits(_WIRE_17, 6, 6)
connect _WIRE_16.pr, _T_287
node _T_288 = bits(_WIRE_17, 7, 7)
connect _WIRE_16.px, _T_288
node _T_289 = bits(_WIRE_17, 8, 8)
connect _WIRE_16.pw, _T_289
node _T_290 = bits(_WIRE_17, 9, 9)
connect _WIRE_16.hr, _T_290
node _T_291 = bits(_WIRE_17, 10, 10)
connect _WIRE_16.hx, _T_291
node _T_292 = bits(_WIRE_17, 11, 11)
connect _WIRE_16.hw, _T_292
node _T_293 = bits(_WIRE_17, 12, 12)
connect _WIRE_16.sr, _T_293
node _T_294 = bits(_WIRE_17, 13, 13)
connect _WIRE_16.sx, _T_294
node _T_295 = bits(_WIRE_17, 14, 14)
connect _WIRE_16.sw, _T_295
node _T_296 = bits(_WIRE_17, 15, 15)
connect _WIRE_16.gf, _T_296
node _T_297 = bits(_WIRE_17, 16, 16)
connect _WIRE_16.pf, _T_297
node _T_298 = bits(_WIRE_17, 17, 17)
connect _WIRE_16.ae_stage2, _T_298
node _T_299 = bits(_WIRE_17, 18, 18)
connect _WIRE_16.ae_final, _T_299
node _T_300 = bits(_WIRE_17, 19, 19)
connect _WIRE_16.ae_ptw, _T_300
node _T_301 = bits(_WIRE_17, 20, 20)
connect _WIRE_16.g, _T_301
node _T_302 = bits(_WIRE_17, 21, 21)
connect _WIRE_16.u, _T_302
node _T_303 = bits(_WIRE_17, 41, 22)
connect _WIRE_16.ppn, _T_303
wire _WIRE_18 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_19 : UInt<42>
connect _WIRE_19, sectored_entries[0][0].data[1]
node _T_304 = bits(_WIRE_19, 0, 0)
connect _WIRE_18.fragmented_superpage, _T_304
node _T_305 = bits(_WIRE_19, 1, 1)
connect _WIRE_18.c, _T_305
node _T_306 = bits(_WIRE_19, 2, 2)
connect _WIRE_18.eff, _T_306
node _T_307 = bits(_WIRE_19, 3, 3)
connect _WIRE_18.paa, _T_307
node _T_308 = bits(_WIRE_19, 4, 4)
connect _WIRE_18.pal, _T_308
node _T_309 = bits(_WIRE_19, 5, 5)
connect _WIRE_18.ppp, _T_309
node _T_310 = bits(_WIRE_19, 6, 6)
connect _WIRE_18.pr, _T_310
node _T_311 = bits(_WIRE_19, 7, 7)
connect _WIRE_18.px, _T_311
node _T_312 = bits(_WIRE_19, 8, 8)
connect _WIRE_18.pw, _T_312
node _T_313 = bits(_WIRE_19, 9, 9)
connect _WIRE_18.hr, _T_313
node _T_314 = bits(_WIRE_19, 10, 10)
connect _WIRE_18.hx, _T_314
node _T_315 = bits(_WIRE_19, 11, 11)
connect _WIRE_18.hw, _T_315
node _T_316 = bits(_WIRE_19, 12, 12)
connect _WIRE_18.sr, _T_316
node _T_317 = bits(_WIRE_19, 13, 13)
connect _WIRE_18.sx, _T_317
node _T_318 = bits(_WIRE_19, 14, 14)
connect _WIRE_18.sw, _T_318
node _T_319 = bits(_WIRE_19, 15, 15)
connect _WIRE_18.gf, _T_319
node _T_320 = bits(_WIRE_19, 16, 16)
connect _WIRE_18.pf, _T_320
node _T_321 = bits(_WIRE_19, 17, 17)
connect _WIRE_18.ae_stage2, _T_321
node _T_322 = bits(_WIRE_19, 18, 18)
connect _WIRE_18.ae_final, _T_322
node _T_323 = bits(_WIRE_19, 19, 19)
connect _WIRE_18.ae_ptw, _T_323
node _T_324 = bits(_WIRE_19, 20, 20)
connect _WIRE_18.g, _T_324
node _T_325 = bits(_WIRE_19, 21, 21)
connect _WIRE_18.u, _T_325
node _T_326 = bits(_WIRE_19, 41, 22)
connect _WIRE_18.ppn, _T_326
wire _WIRE_20 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_21 : UInt<42>
connect _WIRE_21, sectored_entries[0][0].data[2]
node _T_327 = bits(_WIRE_21, 0, 0)
connect _WIRE_20.fragmented_superpage, _T_327
node _T_328 = bits(_WIRE_21, 1, 1)
connect _WIRE_20.c, _T_328
node _T_329 = bits(_WIRE_21, 2, 2)
connect _WIRE_20.eff, _T_329
node _T_330 = bits(_WIRE_21, 3, 3)
connect _WIRE_20.paa, _T_330
node _T_331 = bits(_WIRE_21, 4, 4)
connect _WIRE_20.pal, _T_331
node _T_332 = bits(_WIRE_21, 5, 5)
connect _WIRE_20.ppp, _T_332
node _T_333 = bits(_WIRE_21, 6, 6)
connect _WIRE_20.pr, _T_333
node _T_334 = bits(_WIRE_21, 7, 7)
connect _WIRE_20.px, _T_334
node _T_335 = bits(_WIRE_21, 8, 8)
connect _WIRE_20.pw, _T_335
node _T_336 = bits(_WIRE_21, 9, 9)
connect _WIRE_20.hr, _T_336
node _T_337 = bits(_WIRE_21, 10, 10)
connect _WIRE_20.hx, _T_337
node _T_338 = bits(_WIRE_21, 11, 11)
connect _WIRE_20.hw, _T_338
node _T_339 = bits(_WIRE_21, 12, 12)
connect _WIRE_20.sr, _T_339
node _T_340 = bits(_WIRE_21, 13, 13)
connect _WIRE_20.sx, _T_340
node _T_341 = bits(_WIRE_21, 14, 14)
connect _WIRE_20.sw, _T_341
node _T_342 = bits(_WIRE_21, 15, 15)
connect _WIRE_20.gf, _T_342
node _T_343 = bits(_WIRE_21, 16, 16)
connect _WIRE_20.pf, _T_343
node _T_344 = bits(_WIRE_21, 17, 17)
connect _WIRE_20.ae_stage2, _T_344
node _T_345 = bits(_WIRE_21, 18, 18)
connect _WIRE_20.ae_final, _T_345
node _T_346 = bits(_WIRE_21, 19, 19)
connect _WIRE_20.ae_ptw, _T_346
node _T_347 = bits(_WIRE_21, 20, 20)
connect _WIRE_20.g, _T_347
node _T_348 = bits(_WIRE_21, 21, 21)
connect _WIRE_20.u, _T_348
node _T_349 = bits(_WIRE_21, 41, 22)
connect _WIRE_20.ppn, _T_349
wire _WIRE_22 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_23 : UInt<42>
connect _WIRE_23, sectored_entries[0][0].data[3]
node _T_350 = bits(_WIRE_23, 0, 0)
connect _WIRE_22.fragmented_superpage, _T_350
node _T_351 = bits(_WIRE_23, 1, 1)
connect _WIRE_22.c, _T_351
node _T_352 = bits(_WIRE_23, 2, 2)
connect _WIRE_22.eff, _T_352
node _T_353 = bits(_WIRE_23, 3, 3)
connect _WIRE_22.paa, _T_353
node _T_354 = bits(_WIRE_23, 4, 4)
connect _WIRE_22.pal, _T_354
node _T_355 = bits(_WIRE_23, 5, 5)
connect _WIRE_22.ppp, _T_355
node _T_356 = bits(_WIRE_23, 6, 6)
connect _WIRE_22.pr, _T_356
node _T_357 = bits(_WIRE_23, 7, 7)
connect _WIRE_22.px, _T_357
node _T_358 = bits(_WIRE_23, 8, 8)
connect _WIRE_22.pw, _T_358
node _T_359 = bits(_WIRE_23, 9, 9)
connect _WIRE_22.hr, _T_359
node _T_360 = bits(_WIRE_23, 10, 10)
connect _WIRE_22.hx, _T_360
node _T_361 = bits(_WIRE_23, 11, 11)
connect _WIRE_22.hw, _T_361
node _T_362 = bits(_WIRE_23, 12, 12)
connect _WIRE_22.sr, _T_362
node _T_363 = bits(_WIRE_23, 13, 13)
connect _WIRE_22.sx, _T_363
node _T_364 = bits(_WIRE_23, 14, 14)
connect _WIRE_22.sw, _T_364
node _T_365 = bits(_WIRE_23, 15, 15)
connect _WIRE_22.gf, _T_365
node _T_366 = bits(_WIRE_23, 16, 16)
connect _WIRE_22.pf, _T_366
node _T_367 = bits(_WIRE_23, 17, 17)
connect _WIRE_22.ae_stage2, _T_367
node _T_368 = bits(_WIRE_23, 18, 18)
connect _WIRE_22.ae_final, _T_368
node _T_369 = bits(_WIRE_23, 19, 19)
connect _WIRE_22.ae_ptw, _T_369
node _T_370 = bits(_WIRE_23, 20, 20)
connect _WIRE_22.g, _T_370
node _T_371 = bits(_WIRE_23, 21, 21)
connect _WIRE_22.u, _T_371
node _T_372 = bits(_WIRE_23, 41, 22)
connect _WIRE_22.ppn, _T_372
node _T_373 = eq(sectored_entries[0][0].tag_v, hv)
node _T_374 = eq(_WIRE_16.g, UInt<1>(0h0))
node _T_375 = and(_T_373, _T_374)
when _T_375 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
node _T_376 = eq(sectored_entries[0][0].tag_v, hv)
node _T_377 = eq(_WIRE_18.g, UInt<1>(0h0))
node _T_378 = and(_T_376, _T_377)
when _T_378 :
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
node _T_379 = eq(sectored_entries[0][0].tag_v, hv)
node _T_380 = eq(_WIRE_20.g, UInt<1>(0h0))
node _T_381 = and(_T_379, _T_380)
when _T_381 :
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
node _T_382 = eq(sectored_entries[0][0].tag_v, hv)
node _T_383 = eq(_WIRE_22.g, UInt<1>(0h0))
node _T_384 = and(_T_382, _T_383)
when _T_384 :
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
else :
node _T_385 = or(hv, hg)
wire _WIRE_24 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_25 : UInt<42>
connect _WIRE_25, sectored_entries[0][0].data[0]
node _T_386 = bits(_WIRE_25, 0, 0)
connect _WIRE_24.fragmented_superpage, _T_386
node _T_387 = bits(_WIRE_25, 1, 1)
connect _WIRE_24.c, _T_387
node _T_388 = bits(_WIRE_25, 2, 2)
connect _WIRE_24.eff, _T_388
node _T_389 = bits(_WIRE_25, 3, 3)
connect _WIRE_24.paa, _T_389
node _T_390 = bits(_WIRE_25, 4, 4)
connect _WIRE_24.pal, _T_390
node _T_391 = bits(_WIRE_25, 5, 5)
connect _WIRE_24.ppp, _T_391
node _T_392 = bits(_WIRE_25, 6, 6)
connect _WIRE_24.pr, _T_392
node _T_393 = bits(_WIRE_25, 7, 7)
connect _WIRE_24.px, _T_393
node _T_394 = bits(_WIRE_25, 8, 8)
connect _WIRE_24.pw, _T_394
node _T_395 = bits(_WIRE_25, 9, 9)
connect _WIRE_24.hr, _T_395
node _T_396 = bits(_WIRE_25, 10, 10)
connect _WIRE_24.hx, _T_396
node _T_397 = bits(_WIRE_25, 11, 11)
connect _WIRE_24.hw, _T_397
node _T_398 = bits(_WIRE_25, 12, 12)
connect _WIRE_24.sr, _T_398
node _T_399 = bits(_WIRE_25, 13, 13)
connect _WIRE_24.sx, _T_399
node _T_400 = bits(_WIRE_25, 14, 14)
connect _WIRE_24.sw, _T_400
node _T_401 = bits(_WIRE_25, 15, 15)
connect _WIRE_24.gf, _T_401
node _T_402 = bits(_WIRE_25, 16, 16)
connect _WIRE_24.pf, _T_402
node _T_403 = bits(_WIRE_25, 17, 17)
connect _WIRE_24.ae_stage2, _T_403
node _T_404 = bits(_WIRE_25, 18, 18)
connect _WIRE_24.ae_final, _T_404
node _T_405 = bits(_WIRE_25, 19, 19)
connect _WIRE_24.ae_ptw, _T_405
node _T_406 = bits(_WIRE_25, 20, 20)
connect _WIRE_24.g, _T_406
node _T_407 = bits(_WIRE_25, 21, 21)
connect _WIRE_24.u, _T_407
node _T_408 = bits(_WIRE_25, 41, 22)
connect _WIRE_24.ppn, _T_408
wire _WIRE_26 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_27 : UInt<42>
connect _WIRE_27, sectored_entries[0][0].data[1]
node _T_409 = bits(_WIRE_27, 0, 0)
connect _WIRE_26.fragmented_superpage, _T_409
node _T_410 = bits(_WIRE_27, 1, 1)
connect _WIRE_26.c, _T_410
node _T_411 = bits(_WIRE_27, 2, 2)
connect _WIRE_26.eff, _T_411
node _T_412 = bits(_WIRE_27, 3, 3)
connect _WIRE_26.paa, _T_412
node _T_413 = bits(_WIRE_27, 4, 4)
connect _WIRE_26.pal, _T_413
node _T_414 = bits(_WIRE_27, 5, 5)
connect _WIRE_26.ppp, _T_414
node _T_415 = bits(_WIRE_27, 6, 6)
connect _WIRE_26.pr, _T_415
node _T_416 = bits(_WIRE_27, 7, 7)
connect _WIRE_26.px, _T_416
node _T_417 = bits(_WIRE_27, 8, 8)
connect _WIRE_26.pw, _T_417
node _T_418 = bits(_WIRE_27, 9, 9)
connect _WIRE_26.hr, _T_418
node _T_419 = bits(_WIRE_27, 10, 10)
connect _WIRE_26.hx, _T_419
node _T_420 = bits(_WIRE_27, 11, 11)
connect _WIRE_26.hw, _T_420
node _T_421 = bits(_WIRE_27, 12, 12)
connect _WIRE_26.sr, _T_421
node _T_422 = bits(_WIRE_27, 13, 13)
connect _WIRE_26.sx, _T_422
node _T_423 = bits(_WIRE_27, 14, 14)
connect _WIRE_26.sw, _T_423
node _T_424 = bits(_WIRE_27, 15, 15)
connect _WIRE_26.gf, _T_424
node _T_425 = bits(_WIRE_27, 16, 16)
connect _WIRE_26.pf, _T_425
node _T_426 = bits(_WIRE_27, 17, 17)
connect _WIRE_26.ae_stage2, _T_426
node _T_427 = bits(_WIRE_27, 18, 18)
connect _WIRE_26.ae_final, _T_427
node _T_428 = bits(_WIRE_27, 19, 19)
connect _WIRE_26.ae_ptw, _T_428
node _T_429 = bits(_WIRE_27, 20, 20)
connect _WIRE_26.g, _T_429
node _T_430 = bits(_WIRE_27, 21, 21)
connect _WIRE_26.u, _T_430
node _T_431 = bits(_WIRE_27, 41, 22)
connect _WIRE_26.ppn, _T_431
wire _WIRE_28 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_29 : UInt<42>
connect _WIRE_29, sectored_entries[0][0].data[2]
node _T_432 = bits(_WIRE_29, 0, 0)
connect _WIRE_28.fragmented_superpage, _T_432
node _T_433 = bits(_WIRE_29, 1, 1)
connect _WIRE_28.c, _T_433
node _T_434 = bits(_WIRE_29, 2, 2)
connect _WIRE_28.eff, _T_434
node _T_435 = bits(_WIRE_29, 3, 3)
connect _WIRE_28.paa, _T_435
node _T_436 = bits(_WIRE_29, 4, 4)
connect _WIRE_28.pal, _T_436
node _T_437 = bits(_WIRE_29, 5, 5)
connect _WIRE_28.ppp, _T_437
node _T_438 = bits(_WIRE_29, 6, 6)
connect _WIRE_28.pr, _T_438
node _T_439 = bits(_WIRE_29, 7, 7)
connect _WIRE_28.px, _T_439
node _T_440 = bits(_WIRE_29, 8, 8)
connect _WIRE_28.pw, _T_440
node _T_441 = bits(_WIRE_29, 9, 9)
connect _WIRE_28.hr, _T_441
node _T_442 = bits(_WIRE_29, 10, 10)
connect _WIRE_28.hx, _T_442
node _T_443 = bits(_WIRE_29, 11, 11)
connect _WIRE_28.hw, _T_443
node _T_444 = bits(_WIRE_29, 12, 12)
connect _WIRE_28.sr, _T_444
node _T_445 = bits(_WIRE_29, 13, 13)
connect _WIRE_28.sx, _T_445
node _T_446 = bits(_WIRE_29, 14, 14)
connect _WIRE_28.sw, _T_446
node _T_447 = bits(_WIRE_29, 15, 15)
connect _WIRE_28.gf, _T_447
node _T_448 = bits(_WIRE_29, 16, 16)
connect _WIRE_28.pf, _T_448
node _T_449 = bits(_WIRE_29, 17, 17)
connect _WIRE_28.ae_stage2, _T_449
node _T_450 = bits(_WIRE_29, 18, 18)
connect _WIRE_28.ae_final, _T_450
node _T_451 = bits(_WIRE_29, 19, 19)
connect _WIRE_28.ae_ptw, _T_451
node _T_452 = bits(_WIRE_29, 20, 20)
connect _WIRE_28.g, _T_452
node _T_453 = bits(_WIRE_29, 21, 21)
connect _WIRE_28.u, _T_453
node _T_454 = bits(_WIRE_29, 41, 22)
connect _WIRE_28.ppn, _T_454
wire _WIRE_30 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_31 : UInt<42>
connect _WIRE_31, sectored_entries[0][0].data[3]
node _T_455 = bits(_WIRE_31, 0, 0)
connect _WIRE_30.fragmented_superpage, _T_455
node _T_456 = bits(_WIRE_31, 1, 1)
connect _WIRE_30.c, _T_456
node _T_457 = bits(_WIRE_31, 2, 2)
connect _WIRE_30.eff, _T_457
node _T_458 = bits(_WIRE_31, 3, 3)
connect _WIRE_30.paa, _T_458
node _T_459 = bits(_WIRE_31, 4, 4)
connect _WIRE_30.pal, _T_459
node _T_460 = bits(_WIRE_31, 5, 5)
connect _WIRE_30.ppp, _T_460
node _T_461 = bits(_WIRE_31, 6, 6)
connect _WIRE_30.pr, _T_461
node _T_462 = bits(_WIRE_31, 7, 7)
connect _WIRE_30.px, _T_462
node _T_463 = bits(_WIRE_31, 8, 8)
connect _WIRE_30.pw, _T_463
node _T_464 = bits(_WIRE_31, 9, 9)
connect _WIRE_30.hr, _T_464
node _T_465 = bits(_WIRE_31, 10, 10)
connect _WIRE_30.hx, _T_465
node _T_466 = bits(_WIRE_31, 11, 11)
connect _WIRE_30.hw, _T_466
node _T_467 = bits(_WIRE_31, 12, 12)
connect _WIRE_30.sr, _T_467
node _T_468 = bits(_WIRE_31, 13, 13)
connect _WIRE_30.sx, _T_468
node _T_469 = bits(_WIRE_31, 14, 14)
connect _WIRE_30.sw, _T_469
node _T_470 = bits(_WIRE_31, 15, 15)
connect _WIRE_30.gf, _T_470
node _T_471 = bits(_WIRE_31, 16, 16)
connect _WIRE_30.pf, _T_471
node _T_472 = bits(_WIRE_31, 17, 17)
connect _WIRE_30.ae_stage2, _T_472
node _T_473 = bits(_WIRE_31, 18, 18)
connect _WIRE_30.ae_final, _T_473
node _T_474 = bits(_WIRE_31, 19, 19)
connect _WIRE_30.ae_ptw, _T_474
node _T_475 = bits(_WIRE_31, 20, 20)
connect _WIRE_30.g, _T_475
node _T_476 = bits(_WIRE_31, 21, 21)
connect _WIRE_30.u, _T_476
node _T_477 = bits(_WIRE_31, 41, 22)
connect _WIRE_30.ppn, _T_477
node _T_478 = eq(sectored_entries[0][0].tag_v, _T_385)
when _T_478 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
node _T_479 = eq(sectored_entries[0][0].tag_v, _T_385)
when _T_479 :
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
node _T_480 = eq(sectored_entries[0][0].tag_v, _T_385)
when _T_480 :
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
node _T_481 = eq(sectored_entries[0][0].tag_v, _T_385)
when _T_481 :
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
node hv_1 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_1 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_482 = eq(hg_1, UInt<1>(0h0))
node _T_483 = and(_T_482, io.sfence.bits.rs1)
when _T_483 :
node _T_484 = xor(sectored_entries[0][1].tag_vpn, vpn)
node _T_485 = shr(_T_484, 2)
node _T_486 = eq(_T_485, UInt<1>(0h0))
node _T_487 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_488 = and(_T_486, _T_487)
when _T_488 :
wire _WIRE_32 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_33 : UInt<42>
connect _WIRE_33, sectored_entries[0][1].data[0]
node _T_489 = bits(_WIRE_33, 0, 0)
connect _WIRE_32.fragmented_superpage, _T_489
node _T_490 = bits(_WIRE_33, 1, 1)
connect _WIRE_32.c, _T_490
node _T_491 = bits(_WIRE_33, 2, 2)
connect _WIRE_32.eff, _T_491
node _T_492 = bits(_WIRE_33, 3, 3)
connect _WIRE_32.paa, _T_492
node _T_493 = bits(_WIRE_33, 4, 4)
connect _WIRE_32.pal, _T_493
node _T_494 = bits(_WIRE_33, 5, 5)
connect _WIRE_32.ppp, _T_494
node _T_495 = bits(_WIRE_33, 6, 6)
connect _WIRE_32.pr, _T_495
node _T_496 = bits(_WIRE_33, 7, 7)
connect _WIRE_32.px, _T_496
node _T_497 = bits(_WIRE_33, 8, 8)
connect _WIRE_32.pw, _T_497
node _T_498 = bits(_WIRE_33, 9, 9)
connect _WIRE_32.hr, _T_498
node _T_499 = bits(_WIRE_33, 10, 10)
connect _WIRE_32.hx, _T_499
node _T_500 = bits(_WIRE_33, 11, 11)
connect _WIRE_32.hw, _T_500
node _T_501 = bits(_WIRE_33, 12, 12)
connect _WIRE_32.sr, _T_501
node _T_502 = bits(_WIRE_33, 13, 13)
connect _WIRE_32.sx, _T_502
node _T_503 = bits(_WIRE_33, 14, 14)
connect _WIRE_32.sw, _T_503
node _T_504 = bits(_WIRE_33, 15, 15)
connect _WIRE_32.gf, _T_504
node _T_505 = bits(_WIRE_33, 16, 16)
connect _WIRE_32.pf, _T_505
node _T_506 = bits(_WIRE_33, 17, 17)
connect _WIRE_32.ae_stage2, _T_506
node _T_507 = bits(_WIRE_33, 18, 18)
connect _WIRE_32.ae_final, _T_507
node _T_508 = bits(_WIRE_33, 19, 19)
connect _WIRE_32.ae_ptw, _T_508
node _T_509 = bits(_WIRE_33, 20, 20)
connect _WIRE_32.g, _T_509
node _T_510 = bits(_WIRE_33, 21, 21)
connect _WIRE_32.u, _T_510
node _T_511 = bits(_WIRE_33, 41, 22)
connect _WIRE_32.ppn, _T_511
wire _WIRE_34 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_35 : UInt<42>
connect _WIRE_35, sectored_entries[0][1].data[1]
node _T_512 = bits(_WIRE_35, 0, 0)
connect _WIRE_34.fragmented_superpage, _T_512
node _T_513 = bits(_WIRE_35, 1, 1)
connect _WIRE_34.c, _T_513
node _T_514 = bits(_WIRE_35, 2, 2)
connect _WIRE_34.eff, _T_514
node _T_515 = bits(_WIRE_35, 3, 3)
connect _WIRE_34.paa, _T_515
node _T_516 = bits(_WIRE_35, 4, 4)
connect _WIRE_34.pal, _T_516
node _T_517 = bits(_WIRE_35, 5, 5)
connect _WIRE_34.ppp, _T_517
node _T_518 = bits(_WIRE_35, 6, 6)
connect _WIRE_34.pr, _T_518
node _T_519 = bits(_WIRE_35, 7, 7)
connect _WIRE_34.px, _T_519
node _T_520 = bits(_WIRE_35, 8, 8)
connect _WIRE_34.pw, _T_520
node _T_521 = bits(_WIRE_35, 9, 9)
connect _WIRE_34.hr, _T_521
node _T_522 = bits(_WIRE_35, 10, 10)
connect _WIRE_34.hx, _T_522
node _T_523 = bits(_WIRE_35, 11, 11)
connect _WIRE_34.hw, _T_523
node _T_524 = bits(_WIRE_35, 12, 12)
connect _WIRE_34.sr, _T_524
node _T_525 = bits(_WIRE_35, 13, 13)
connect _WIRE_34.sx, _T_525
node _T_526 = bits(_WIRE_35, 14, 14)
connect _WIRE_34.sw, _T_526
node _T_527 = bits(_WIRE_35, 15, 15)
connect _WIRE_34.gf, _T_527
node _T_528 = bits(_WIRE_35, 16, 16)
connect _WIRE_34.pf, _T_528
node _T_529 = bits(_WIRE_35, 17, 17)
connect _WIRE_34.ae_stage2, _T_529
node _T_530 = bits(_WIRE_35, 18, 18)
connect _WIRE_34.ae_final, _T_530
node _T_531 = bits(_WIRE_35, 19, 19)
connect _WIRE_34.ae_ptw, _T_531
node _T_532 = bits(_WIRE_35, 20, 20)
connect _WIRE_34.g, _T_532
node _T_533 = bits(_WIRE_35, 21, 21)
connect _WIRE_34.u, _T_533
node _T_534 = bits(_WIRE_35, 41, 22)
connect _WIRE_34.ppn, _T_534
wire _WIRE_36 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_37 : UInt<42>
connect _WIRE_37, sectored_entries[0][1].data[2]
node _T_535 = bits(_WIRE_37, 0, 0)
connect _WIRE_36.fragmented_superpage, _T_535
node _T_536 = bits(_WIRE_37, 1, 1)
connect _WIRE_36.c, _T_536
node _T_537 = bits(_WIRE_37, 2, 2)
connect _WIRE_36.eff, _T_537
node _T_538 = bits(_WIRE_37, 3, 3)
connect _WIRE_36.paa, _T_538
node _T_539 = bits(_WIRE_37, 4, 4)
connect _WIRE_36.pal, _T_539
node _T_540 = bits(_WIRE_37, 5, 5)
connect _WIRE_36.ppp, _T_540
node _T_541 = bits(_WIRE_37, 6, 6)
connect _WIRE_36.pr, _T_541
node _T_542 = bits(_WIRE_37, 7, 7)
connect _WIRE_36.px, _T_542
node _T_543 = bits(_WIRE_37, 8, 8)
connect _WIRE_36.pw, _T_543
node _T_544 = bits(_WIRE_37, 9, 9)
connect _WIRE_36.hr, _T_544
node _T_545 = bits(_WIRE_37, 10, 10)
connect _WIRE_36.hx, _T_545
node _T_546 = bits(_WIRE_37, 11, 11)
connect _WIRE_36.hw, _T_546
node _T_547 = bits(_WIRE_37, 12, 12)
connect _WIRE_36.sr, _T_547
node _T_548 = bits(_WIRE_37, 13, 13)
connect _WIRE_36.sx, _T_548
node _T_549 = bits(_WIRE_37, 14, 14)
connect _WIRE_36.sw, _T_549
node _T_550 = bits(_WIRE_37, 15, 15)
connect _WIRE_36.gf, _T_550
node _T_551 = bits(_WIRE_37, 16, 16)
connect _WIRE_36.pf, _T_551
node _T_552 = bits(_WIRE_37, 17, 17)
connect _WIRE_36.ae_stage2, _T_552
node _T_553 = bits(_WIRE_37, 18, 18)
connect _WIRE_36.ae_final, _T_553
node _T_554 = bits(_WIRE_37, 19, 19)
connect _WIRE_36.ae_ptw, _T_554
node _T_555 = bits(_WIRE_37, 20, 20)
connect _WIRE_36.g, _T_555
node _T_556 = bits(_WIRE_37, 21, 21)
connect _WIRE_36.u, _T_556
node _T_557 = bits(_WIRE_37, 41, 22)
connect _WIRE_36.ppn, _T_557
wire _WIRE_38 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_39 : UInt<42>
connect _WIRE_39, sectored_entries[0][1].data[3]
node _T_558 = bits(_WIRE_39, 0, 0)
connect _WIRE_38.fragmented_superpage, _T_558
node _T_559 = bits(_WIRE_39, 1, 1)
connect _WIRE_38.c, _T_559
node _T_560 = bits(_WIRE_39, 2, 2)
connect _WIRE_38.eff, _T_560
node _T_561 = bits(_WIRE_39, 3, 3)
connect _WIRE_38.paa, _T_561
node _T_562 = bits(_WIRE_39, 4, 4)
connect _WIRE_38.pal, _T_562
node _T_563 = bits(_WIRE_39, 5, 5)
connect _WIRE_38.ppp, _T_563
node _T_564 = bits(_WIRE_39, 6, 6)
connect _WIRE_38.pr, _T_564
node _T_565 = bits(_WIRE_39, 7, 7)
connect _WIRE_38.px, _T_565
node _T_566 = bits(_WIRE_39, 8, 8)
connect _WIRE_38.pw, _T_566
node _T_567 = bits(_WIRE_39, 9, 9)
connect _WIRE_38.hr, _T_567
node _T_568 = bits(_WIRE_39, 10, 10)
connect _WIRE_38.hx, _T_568
node _T_569 = bits(_WIRE_39, 11, 11)
connect _WIRE_38.hw, _T_569
node _T_570 = bits(_WIRE_39, 12, 12)
connect _WIRE_38.sr, _T_570
node _T_571 = bits(_WIRE_39, 13, 13)
connect _WIRE_38.sx, _T_571
node _T_572 = bits(_WIRE_39, 14, 14)
connect _WIRE_38.sw, _T_572
node _T_573 = bits(_WIRE_39, 15, 15)
connect _WIRE_38.gf, _T_573
node _T_574 = bits(_WIRE_39, 16, 16)
connect _WIRE_38.pf, _T_574
node _T_575 = bits(_WIRE_39, 17, 17)
connect _WIRE_38.ae_stage2, _T_575
node _T_576 = bits(_WIRE_39, 18, 18)
connect _WIRE_38.ae_final, _T_576
node _T_577 = bits(_WIRE_39, 19, 19)
connect _WIRE_38.ae_ptw, _T_577
node _T_578 = bits(_WIRE_39, 20, 20)
connect _WIRE_38.g, _T_578
node _T_579 = bits(_WIRE_39, 21, 21)
connect _WIRE_38.u, _T_579
node _T_580 = bits(_WIRE_39, 41, 22)
connect _WIRE_38.ppn, _T_580
node _T_581 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_582 = bits(vpn, 1, 0)
node _T_583 = eq(UInt<1>(0h0), _T_582)
node _T_584 = and(_T_581, _T_583)
when _T_584 :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
node _T_585 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_586 = bits(vpn, 1, 0)
node _T_587 = eq(UInt<1>(0h1), _T_586)
node _T_588 = and(_T_585, _T_587)
when _T_588 :
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
node _T_589 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_590 = bits(vpn, 1, 0)
node _T_591 = eq(UInt<2>(0h2), _T_590)
node _T_592 = and(_T_589, _T_591)
when _T_592 :
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
node _T_593 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_594 = bits(vpn, 1, 0)
node _T_595 = eq(UInt<2>(0h3), _T_594)
node _T_596 = and(_T_593, _T_595)
when _T_596 :
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
node _T_597 = xor(sectored_entries[0][1].tag_vpn, vpn)
node _T_598 = shr(_T_597, 18)
node _T_599 = eq(_T_598, UInt<1>(0h0))
when _T_599 :
wire _WIRE_40 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_41 : UInt<42>
connect _WIRE_41, sectored_entries[0][1].data[0]
node _T_600 = bits(_WIRE_41, 0, 0)
connect _WIRE_40.fragmented_superpage, _T_600
node _T_601 = bits(_WIRE_41, 1, 1)
connect _WIRE_40.c, _T_601
node _T_602 = bits(_WIRE_41, 2, 2)
connect _WIRE_40.eff, _T_602
node _T_603 = bits(_WIRE_41, 3, 3)
connect _WIRE_40.paa, _T_603
node _T_604 = bits(_WIRE_41, 4, 4)
connect _WIRE_40.pal, _T_604
node _T_605 = bits(_WIRE_41, 5, 5)
connect _WIRE_40.ppp, _T_605
node _T_606 = bits(_WIRE_41, 6, 6)
connect _WIRE_40.pr, _T_606
node _T_607 = bits(_WIRE_41, 7, 7)
connect _WIRE_40.px, _T_607
node _T_608 = bits(_WIRE_41, 8, 8)
connect _WIRE_40.pw, _T_608
node _T_609 = bits(_WIRE_41, 9, 9)
connect _WIRE_40.hr, _T_609
node _T_610 = bits(_WIRE_41, 10, 10)
connect _WIRE_40.hx, _T_610
node _T_611 = bits(_WIRE_41, 11, 11)
connect _WIRE_40.hw, _T_611
node _T_612 = bits(_WIRE_41, 12, 12)
connect _WIRE_40.sr, _T_612
node _T_613 = bits(_WIRE_41, 13, 13)
connect _WIRE_40.sx, _T_613
node _T_614 = bits(_WIRE_41, 14, 14)
connect _WIRE_40.sw, _T_614
node _T_615 = bits(_WIRE_41, 15, 15)
connect _WIRE_40.gf, _T_615
node _T_616 = bits(_WIRE_41, 16, 16)
connect _WIRE_40.pf, _T_616
node _T_617 = bits(_WIRE_41, 17, 17)
connect _WIRE_40.ae_stage2, _T_617
node _T_618 = bits(_WIRE_41, 18, 18)
connect _WIRE_40.ae_final, _T_618
node _T_619 = bits(_WIRE_41, 19, 19)
connect _WIRE_40.ae_ptw, _T_619
node _T_620 = bits(_WIRE_41, 20, 20)
connect _WIRE_40.g, _T_620
node _T_621 = bits(_WIRE_41, 21, 21)
connect _WIRE_40.u, _T_621
node _T_622 = bits(_WIRE_41, 41, 22)
connect _WIRE_40.ppn, _T_622
wire _WIRE_42 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_43 : UInt<42>
connect _WIRE_43, sectored_entries[0][1].data[1]
node _T_623 = bits(_WIRE_43, 0, 0)
connect _WIRE_42.fragmented_superpage, _T_623
node _T_624 = bits(_WIRE_43, 1, 1)
connect _WIRE_42.c, _T_624
node _T_625 = bits(_WIRE_43, 2, 2)
connect _WIRE_42.eff, _T_625
node _T_626 = bits(_WIRE_43, 3, 3)
connect _WIRE_42.paa, _T_626
node _T_627 = bits(_WIRE_43, 4, 4)
connect _WIRE_42.pal, _T_627
node _T_628 = bits(_WIRE_43, 5, 5)
connect _WIRE_42.ppp, _T_628
node _T_629 = bits(_WIRE_43, 6, 6)
connect _WIRE_42.pr, _T_629
node _T_630 = bits(_WIRE_43, 7, 7)
connect _WIRE_42.px, _T_630
node _T_631 = bits(_WIRE_43, 8, 8)
connect _WIRE_42.pw, _T_631
node _T_632 = bits(_WIRE_43, 9, 9)
connect _WIRE_42.hr, _T_632
node _T_633 = bits(_WIRE_43, 10, 10)
connect _WIRE_42.hx, _T_633
node _T_634 = bits(_WIRE_43, 11, 11)
connect _WIRE_42.hw, _T_634
node _T_635 = bits(_WIRE_43, 12, 12)
connect _WIRE_42.sr, _T_635
node _T_636 = bits(_WIRE_43, 13, 13)
connect _WIRE_42.sx, _T_636
node _T_637 = bits(_WIRE_43, 14, 14)
connect _WIRE_42.sw, _T_637
node _T_638 = bits(_WIRE_43, 15, 15)
connect _WIRE_42.gf, _T_638
node _T_639 = bits(_WIRE_43, 16, 16)
connect _WIRE_42.pf, _T_639
node _T_640 = bits(_WIRE_43, 17, 17)
connect _WIRE_42.ae_stage2, _T_640
node _T_641 = bits(_WIRE_43, 18, 18)
connect _WIRE_42.ae_final, _T_641
node _T_642 = bits(_WIRE_43, 19, 19)
connect _WIRE_42.ae_ptw, _T_642
node _T_643 = bits(_WIRE_43, 20, 20)
connect _WIRE_42.g, _T_643
node _T_644 = bits(_WIRE_43, 21, 21)
connect _WIRE_42.u, _T_644
node _T_645 = bits(_WIRE_43, 41, 22)
connect _WIRE_42.ppn, _T_645
wire _WIRE_44 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_45 : UInt<42>
connect _WIRE_45, sectored_entries[0][1].data[2]
node _T_646 = bits(_WIRE_45, 0, 0)
connect _WIRE_44.fragmented_superpage, _T_646
node _T_647 = bits(_WIRE_45, 1, 1)
connect _WIRE_44.c, _T_647
node _T_648 = bits(_WIRE_45, 2, 2)
connect _WIRE_44.eff, _T_648
node _T_649 = bits(_WIRE_45, 3, 3)
connect _WIRE_44.paa, _T_649
node _T_650 = bits(_WIRE_45, 4, 4)
connect _WIRE_44.pal, _T_650
node _T_651 = bits(_WIRE_45, 5, 5)
connect _WIRE_44.ppp, _T_651
node _T_652 = bits(_WIRE_45, 6, 6)
connect _WIRE_44.pr, _T_652
node _T_653 = bits(_WIRE_45, 7, 7)
connect _WIRE_44.px, _T_653
node _T_654 = bits(_WIRE_45, 8, 8)
connect _WIRE_44.pw, _T_654
node _T_655 = bits(_WIRE_45, 9, 9)
connect _WIRE_44.hr, _T_655
node _T_656 = bits(_WIRE_45, 10, 10)
connect _WIRE_44.hx, _T_656
node _T_657 = bits(_WIRE_45, 11, 11)
connect _WIRE_44.hw, _T_657
node _T_658 = bits(_WIRE_45, 12, 12)
connect _WIRE_44.sr, _T_658
node _T_659 = bits(_WIRE_45, 13, 13)
connect _WIRE_44.sx, _T_659
node _T_660 = bits(_WIRE_45, 14, 14)
connect _WIRE_44.sw, _T_660
node _T_661 = bits(_WIRE_45, 15, 15)
connect _WIRE_44.gf, _T_661
node _T_662 = bits(_WIRE_45, 16, 16)
connect _WIRE_44.pf, _T_662
node _T_663 = bits(_WIRE_45, 17, 17)
connect _WIRE_44.ae_stage2, _T_663
node _T_664 = bits(_WIRE_45, 18, 18)
connect _WIRE_44.ae_final, _T_664
node _T_665 = bits(_WIRE_45, 19, 19)
connect _WIRE_44.ae_ptw, _T_665
node _T_666 = bits(_WIRE_45, 20, 20)
connect _WIRE_44.g, _T_666
node _T_667 = bits(_WIRE_45, 21, 21)
connect _WIRE_44.u, _T_667
node _T_668 = bits(_WIRE_45, 41, 22)
connect _WIRE_44.ppn, _T_668
wire _WIRE_46 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_47 : UInt<42>
connect _WIRE_47, sectored_entries[0][1].data[3]
node _T_669 = bits(_WIRE_47, 0, 0)
connect _WIRE_46.fragmented_superpage, _T_669
node _T_670 = bits(_WIRE_47, 1, 1)
connect _WIRE_46.c, _T_670
node _T_671 = bits(_WIRE_47, 2, 2)
connect _WIRE_46.eff, _T_671
node _T_672 = bits(_WIRE_47, 3, 3)
connect _WIRE_46.paa, _T_672
node _T_673 = bits(_WIRE_47, 4, 4)
connect _WIRE_46.pal, _T_673
node _T_674 = bits(_WIRE_47, 5, 5)
connect _WIRE_46.ppp, _T_674
node _T_675 = bits(_WIRE_47, 6, 6)
connect _WIRE_46.pr, _T_675
node _T_676 = bits(_WIRE_47, 7, 7)
connect _WIRE_46.px, _T_676
node _T_677 = bits(_WIRE_47, 8, 8)
connect _WIRE_46.pw, _T_677
node _T_678 = bits(_WIRE_47, 9, 9)
connect _WIRE_46.hr, _T_678
node _T_679 = bits(_WIRE_47, 10, 10)
connect _WIRE_46.hx, _T_679
node _T_680 = bits(_WIRE_47, 11, 11)
connect _WIRE_46.hw, _T_680
node _T_681 = bits(_WIRE_47, 12, 12)
connect _WIRE_46.sr, _T_681
node _T_682 = bits(_WIRE_47, 13, 13)
connect _WIRE_46.sx, _T_682
node _T_683 = bits(_WIRE_47, 14, 14)
connect _WIRE_46.sw, _T_683
node _T_684 = bits(_WIRE_47, 15, 15)
connect _WIRE_46.gf, _T_684
node _T_685 = bits(_WIRE_47, 16, 16)
connect _WIRE_46.pf, _T_685
node _T_686 = bits(_WIRE_47, 17, 17)
connect _WIRE_46.ae_stage2, _T_686
node _T_687 = bits(_WIRE_47, 18, 18)
connect _WIRE_46.ae_final, _T_687
node _T_688 = bits(_WIRE_47, 19, 19)
connect _WIRE_46.ae_ptw, _T_688
node _T_689 = bits(_WIRE_47, 20, 20)
connect _WIRE_46.g, _T_689
node _T_690 = bits(_WIRE_47, 21, 21)
connect _WIRE_46.u, _T_690
node _T_691 = bits(_WIRE_47, 41, 22)
connect _WIRE_46.ppn, _T_691
node _T_692 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_693 = and(_T_692, _WIRE_40.fragmented_superpage)
when _T_693 :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
node _T_694 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_695 = and(_T_694, _WIRE_42.fragmented_superpage)
when _T_695 :
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
node _T_696 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_697 = and(_T_696, _WIRE_44.fragmented_superpage)
when _T_697 :
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
node _T_698 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_699 = and(_T_698, _WIRE_46.fragmented_superpage)
when _T_699 :
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
else :
node _T_700 = eq(hg_1, UInt<1>(0h0))
node _T_701 = and(_T_700, io.sfence.bits.rs2)
when _T_701 :
wire _WIRE_48 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_49 : UInt<42>
connect _WIRE_49, sectored_entries[0][1].data[0]
node _T_702 = bits(_WIRE_49, 0, 0)
connect _WIRE_48.fragmented_superpage, _T_702
node _T_703 = bits(_WIRE_49, 1, 1)
connect _WIRE_48.c, _T_703
node _T_704 = bits(_WIRE_49, 2, 2)
connect _WIRE_48.eff, _T_704
node _T_705 = bits(_WIRE_49, 3, 3)
connect _WIRE_48.paa, _T_705
node _T_706 = bits(_WIRE_49, 4, 4)
connect _WIRE_48.pal, _T_706
node _T_707 = bits(_WIRE_49, 5, 5)
connect _WIRE_48.ppp, _T_707
node _T_708 = bits(_WIRE_49, 6, 6)
connect _WIRE_48.pr, _T_708
node _T_709 = bits(_WIRE_49, 7, 7)
connect _WIRE_48.px, _T_709
node _T_710 = bits(_WIRE_49, 8, 8)
connect _WIRE_48.pw, _T_710
node _T_711 = bits(_WIRE_49, 9, 9)
connect _WIRE_48.hr, _T_711
node _T_712 = bits(_WIRE_49, 10, 10)
connect _WIRE_48.hx, _T_712
node _T_713 = bits(_WIRE_49, 11, 11)
connect _WIRE_48.hw, _T_713
node _T_714 = bits(_WIRE_49, 12, 12)
connect _WIRE_48.sr, _T_714
node _T_715 = bits(_WIRE_49, 13, 13)
connect _WIRE_48.sx, _T_715
node _T_716 = bits(_WIRE_49, 14, 14)
connect _WIRE_48.sw, _T_716
node _T_717 = bits(_WIRE_49, 15, 15)
connect _WIRE_48.gf, _T_717
node _T_718 = bits(_WIRE_49, 16, 16)
connect _WIRE_48.pf, _T_718
node _T_719 = bits(_WIRE_49, 17, 17)
connect _WIRE_48.ae_stage2, _T_719
node _T_720 = bits(_WIRE_49, 18, 18)
connect _WIRE_48.ae_final, _T_720
node _T_721 = bits(_WIRE_49, 19, 19)
connect _WIRE_48.ae_ptw, _T_721
node _T_722 = bits(_WIRE_49, 20, 20)
connect _WIRE_48.g, _T_722
node _T_723 = bits(_WIRE_49, 21, 21)
connect _WIRE_48.u, _T_723
node _T_724 = bits(_WIRE_49, 41, 22)
connect _WIRE_48.ppn, _T_724
wire _WIRE_50 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_51 : UInt<42>
connect _WIRE_51, sectored_entries[0][1].data[1]
node _T_725 = bits(_WIRE_51, 0, 0)
connect _WIRE_50.fragmented_superpage, _T_725
node _T_726 = bits(_WIRE_51, 1, 1)
connect _WIRE_50.c, _T_726
node _T_727 = bits(_WIRE_51, 2, 2)
connect _WIRE_50.eff, _T_727
node _T_728 = bits(_WIRE_51, 3, 3)
connect _WIRE_50.paa, _T_728
node _T_729 = bits(_WIRE_51, 4, 4)
connect _WIRE_50.pal, _T_729
node _T_730 = bits(_WIRE_51, 5, 5)
connect _WIRE_50.ppp, _T_730
node _T_731 = bits(_WIRE_51, 6, 6)
connect _WIRE_50.pr, _T_731
node _T_732 = bits(_WIRE_51, 7, 7)
connect _WIRE_50.px, _T_732
node _T_733 = bits(_WIRE_51, 8, 8)
connect _WIRE_50.pw, _T_733
node _T_734 = bits(_WIRE_51, 9, 9)
connect _WIRE_50.hr, _T_734
node _T_735 = bits(_WIRE_51, 10, 10)
connect _WIRE_50.hx, _T_735
node _T_736 = bits(_WIRE_51, 11, 11)
connect _WIRE_50.hw, _T_736
node _T_737 = bits(_WIRE_51, 12, 12)
connect _WIRE_50.sr, _T_737
node _T_738 = bits(_WIRE_51, 13, 13)
connect _WIRE_50.sx, _T_738
node _T_739 = bits(_WIRE_51, 14, 14)
connect _WIRE_50.sw, _T_739
node _T_740 = bits(_WIRE_51, 15, 15)
connect _WIRE_50.gf, _T_740
node _T_741 = bits(_WIRE_51, 16, 16)
connect _WIRE_50.pf, _T_741
node _T_742 = bits(_WIRE_51, 17, 17)
connect _WIRE_50.ae_stage2, _T_742
node _T_743 = bits(_WIRE_51, 18, 18)
connect _WIRE_50.ae_final, _T_743
node _T_744 = bits(_WIRE_51, 19, 19)
connect _WIRE_50.ae_ptw, _T_744
node _T_745 = bits(_WIRE_51, 20, 20)
connect _WIRE_50.g, _T_745
node _T_746 = bits(_WIRE_51, 21, 21)
connect _WIRE_50.u, _T_746
node _T_747 = bits(_WIRE_51, 41, 22)
connect _WIRE_50.ppn, _T_747
wire _WIRE_52 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_53 : UInt<42>
connect _WIRE_53, sectored_entries[0][1].data[2]
node _T_748 = bits(_WIRE_53, 0, 0)
connect _WIRE_52.fragmented_superpage, _T_748
node _T_749 = bits(_WIRE_53, 1, 1)
connect _WIRE_52.c, _T_749
node _T_750 = bits(_WIRE_53, 2, 2)
connect _WIRE_52.eff, _T_750
node _T_751 = bits(_WIRE_53, 3, 3)
connect _WIRE_52.paa, _T_751
node _T_752 = bits(_WIRE_53, 4, 4)
connect _WIRE_52.pal, _T_752
node _T_753 = bits(_WIRE_53, 5, 5)
connect _WIRE_52.ppp, _T_753
node _T_754 = bits(_WIRE_53, 6, 6)
connect _WIRE_52.pr, _T_754
node _T_755 = bits(_WIRE_53, 7, 7)
connect _WIRE_52.px, _T_755
node _T_756 = bits(_WIRE_53, 8, 8)
connect _WIRE_52.pw, _T_756
node _T_757 = bits(_WIRE_53, 9, 9)
connect _WIRE_52.hr, _T_757
node _T_758 = bits(_WIRE_53, 10, 10)
connect _WIRE_52.hx, _T_758
node _T_759 = bits(_WIRE_53, 11, 11)
connect _WIRE_52.hw, _T_759
node _T_760 = bits(_WIRE_53, 12, 12)
connect _WIRE_52.sr, _T_760
node _T_761 = bits(_WIRE_53, 13, 13)
connect _WIRE_52.sx, _T_761
node _T_762 = bits(_WIRE_53, 14, 14)
connect _WIRE_52.sw, _T_762
node _T_763 = bits(_WIRE_53, 15, 15)
connect _WIRE_52.gf, _T_763
node _T_764 = bits(_WIRE_53, 16, 16)
connect _WIRE_52.pf, _T_764
node _T_765 = bits(_WIRE_53, 17, 17)
connect _WIRE_52.ae_stage2, _T_765
node _T_766 = bits(_WIRE_53, 18, 18)
connect _WIRE_52.ae_final, _T_766
node _T_767 = bits(_WIRE_53, 19, 19)
connect _WIRE_52.ae_ptw, _T_767
node _T_768 = bits(_WIRE_53, 20, 20)
connect _WIRE_52.g, _T_768
node _T_769 = bits(_WIRE_53, 21, 21)
connect _WIRE_52.u, _T_769
node _T_770 = bits(_WIRE_53, 41, 22)
connect _WIRE_52.ppn, _T_770
wire _WIRE_54 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_55 : UInt<42>
connect _WIRE_55, sectored_entries[0][1].data[3]
node _T_771 = bits(_WIRE_55, 0, 0)
connect _WIRE_54.fragmented_superpage, _T_771
node _T_772 = bits(_WIRE_55, 1, 1)
connect _WIRE_54.c, _T_772
node _T_773 = bits(_WIRE_55, 2, 2)
connect _WIRE_54.eff, _T_773
node _T_774 = bits(_WIRE_55, 3, 3)
connect _WIRE_54.paa, _T_774
node _T_775 = bits(_WIRE_55, 4, 4)
connect _WIRE_54.pal, _T_775
node _T_776 = bits(_WIRE_55, 5, 5)
connect _WIRE_54.ppp, _T_776
node _T_777 = bits(_WIRE_55, 6, 6)
connect _WIRE_54.pr, _T_777
node _T_778 = bits(_WIRE_55, 7, 7)
connect _WIRE_54.px, _T_778
node _T_779 = bits(_WIRE_55, 8, 8)
connect _WIRE_54.pw, _T_779
node _T_780 = bits(_WIRE_55, 9, 9)
connect _WIRE_54.hr, _T_780
node _T_781 = bits(_WIRE_55, 10, 10)
connect _WIRE_54.hx, _T_781
node _T_782 = bits(_WIRE_55, 11, 11)
connect _WIRE_54.hw, _T_782
node _T_783 = bits(_WIRE_55, 12, 12)
connect _WIRE_54.sr, _T_783
node _T_784 = bits(_WIRE_55, 13, 13)
connect _WIRE_54.sx, _T_784
node _T_785 = bits(_WIRE_55, 14, 14)
connect _WIRE_54.sw, _T_785
node _T_786 = bits(_WIRE_55, 15, 15)
connect _WIRE_54.gf, _T_786
node _T_787 = bits(_WIRE_55, 16, 16)
connect _WIRE_54.pf, _T_787
node _T_788 = bits(_WIRE_55, 17, 17)
connect _WIRE_54.ae_stage2, _T_788
node _T_789 = bits(_WIRE_55, 18, 18)
connect _WIRE_54.ae_final, _T_789
node _T_790 = bits(_WIRE_55, 19, 19)
connect _WIRE_54.ae_ptw, _T_790
node _T_791 = bits(_WIRE_55, 20, 20)
connect _WIRE_54.g, _T_791
node _T_792 = bits(_WIRE_55, 21, 21)
connect _WIRE_54.u, _T_792
node _T_793 = bits(_WIRE_55, 41, 22)
connect _WIRE_54.ppn, _T_793
node _T_794 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_795 = eq(_WIRE_48.g, UInt<1>(0h0))
node _T_796 = and(_T_794, _T_795)
when _T_796 :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
node _T_797 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_798 = eq(_WIRE_50.g, UInt<1>(0h0))
node _T_799 = and(_T_797, _T_798)
when _T_799 :
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
node _T_800 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_801 = eq(_WIRE_52.g, UInt<1>(0h0))
node _T_802 = and(_T_800, _T_801)
when _T_802 :
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
node _T_803 = eq(sectored_entries[0][1].tag_v, hv_1)
node _T_804 = eq(_WIRE_54.g, UInt<1>(0h0))
node _T_805 = and(_T_803, _T_804)
when _T_805 :
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
else :
node _T_806 = or(hv_1, hg_1)
wire _WIRE_56 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_57 : UInt<42>
connect _WIRE_57, sectored_entries[0][1].data[0]
node _T_807 = bits(_WIRE_57, 0, 0)
connect _WIRE_56.fragmented_superpage, _T_807
node _T_808 = bits(_WIRE_57, 1, 1)
connect _WIRE_56.c, _T_808
node _T_809 = bits(_WIRE_57, 2, 2)
connect _WIRE_56.eff, _T_809
node _T_810 = bits(_WIRE_57, 3, 3)
connect _WIRE_56.paa, _T_810
node _T_811 = bits(_WIRE_57, 4, 4)
connect _WIRE_56.pal, _T_811
node _T_812 = bits(_WIRE_57, 5, 5)
connect _WIRE_56.ppp, _T_812
node _T_813 = bits(_WIRE_57, 6, 6)
connect _WIRE_56.pr, _T_813
node _T_814 = bits(_WIRE_57, 7, 7)
connect _WIRE_56.px, _T_814
node _T_815 = bits(_WIRE_57, 8, 8)
connect _WIRE_56.pw, _T_815
node _T_816 = bits(_WIRE_57, 9, 9)
connect _WIRE_56.hr, _T_816
node _T_817 = bits(_WIRE_57, 10, 10)
connect _WIRE_56.hx, _T_817
node _T_818 = bits(_WIRE_57, 11, 11)
connect _WIRE_56.hw, _T_818
node _T_819 = bits(_WIRE_57, 12, 12)
connect _WIRE_56.sr, _T_819
node _T_820 = bits(_WIRE_57, 13, 13)
connect _WIRE_56.sx, _T_820
node _T_821 = bits(_WIRE_57, 14, 14)
connect _WIRE_56.sw, _T_821
node _T_822 = bits(_WIRE_57, 15, 15)
connect _WIRE_56.gf, _T_822
node _T_823 = bits(_WIRE_57, 16, 16)
connect _WIRE_56.pf, _T_823
node _T_824 = bits(_WIRE_57, 17, 17)
connect _WIRE_56.ae_stage2, _T_824
node _T_825 = bits(_WIRE_57, 18, 18)
connect _WIRE_56.ae_final, _T_825
node _T_826 = bits(_WIRE_57, 19, 19)
connect _WIRE_56.ae_ptw, _T_826
node _T_827 = bits(_WIRE_57, 20, 20)
connect _WIRE_56.g, _T_827
node _T_828 = bits(_WIRE_57, 21, 21)
connect _WIRE_56.u, _T_828
node _T_829 = bits(_WIRE_57, 41, 22)
connect _WIRE_56.ppn, _T_829
wire _WIRE_58 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_59 : UInt<42>
connect _WIRE_59, sectored_entries[0][1].data[1]
node _T_830 = bits(_WIRE_59, 0, 0)
connect _WIRE_58.fragmented_superpage, _T_830
node _T_831 = bits(_WIRE_59, 1, 1)
connect _WIRE_58.c, _T_831
node _T_832 = bits(_WIRE_59, 2, 2)
connect _WIRE_58.eff, _T_832
node _T_833 = bits(_WIRE_59, 3, 3)
connect _WIRE_58.paa, _T_833
node _T_834 = bits(_WIRE_59, 4, 4)
connect _WIRE_58.pal, _T_834
node _T_835 = bits(_WIRE_59, 5, 5)
connect _WIRE_58.ppp, _T_835
node _T_836 = bits(_WIRE_59, 6, 6)
connect _WIRE_58.pr, _T_836
node _T_837 = bits(_WIRE_59, 7, 7)
connect _WIRE_58.px, _T_837
node _T_838 = bits(_WIRE_59, 8, 8)
connect _WIRE_58.pw, _T_838
node _T_839 = bits(_WIRE_59, 9, 9)
connect _WIRE_58.hr, _T_839
node _T_840 = bits(_WIRE_59, 10, 10)
connect _WIRE_58.hx, _T_840
node _T_841 = bits(_WIRE_59, 11, 11)
connect _WIRE_58.hw, _T_841
node _T_842 = bits(_WIRE_59, 12, 12)
connect _WIRE_58.sr, _T_842
node _T_843 = bits(_WIRE_59, 13, 13)
connect _WIRE_58.sx, _T_843
node _T_844 = bits(_WIRE_59, 14, 14)
connect _WIRE_58.sw, _T_844
node _T_845 = bits(_WIRE_59, 15, 15)
connect _WIRE_58.gf, _T_845
node _T_846 = bits(_WIRE_59, 16, 16)
connect _WIRE_58.pf, _T_846
node _T_847 = bits(_WIRE_59, 17, 17)
connect _WIRE_58.ae_stage2, _T_847
node _T_848 = bits(_WIRE_59, 18, 18)
connect _WIRE_58.ae_final, _T_848
node _T_849 = bits(_WIRE_59, 19, 19)
connect _WIRE_58.ae_ptw, _T_849
node _T_850 = bits(_WIRE_59, 20, 20)
connect _WIRE_58.g, _T_850
node _T_851 = bits(_WIRE_59, 21, 21)
connect _WIRE_58.u, _T_851
node _T_852 = bits(_WIRE_59, 41, 22)
connect _WIRE_58.ppn, _T_852
wire _WIRE_60 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_61 : UInt<42>
connect _WIRE_61, sectored_entries[0][1].data[2]
node _T_853 = bits(_WIRE_61, 0, 0)
connect _WIRE_60.fragmented_superpage, _T_853
node _T_854 = bits(_WIRE_61, 1, 1)
connect _WIRE_60.c, _T_854
node _T_855 = bits(_WIRE_61, 2, 2)
connect _WIRE_60.eff, _T_855
node _T_856 = bits(_WIRE_61, 3, 3)
connect _WIRE_60.paa, _T_856
node _T_857 = bits(_WIRE_61, 4, 4)
connect _WIRE_60.pal, _T_857
node _T_858 = bits(_WIRE_61, 5, 5)
connect _WIRE_60.ppp, _T_858
node _T_859 = bits(_WIRE_61, 6, 6)
connect _WIRE_60.pr, _T_859
node _T_860 = bits(_WIRE_61, 7, 7)
connect _WIRE_60.px, _T_860
node _T_861 = bits(_WIRE_61, 8, 8)
connect _WIRE_60.pw, _T_861
node _T_862 = bits(_WIRE_61, 9, 9)
connect _WIRE_60.hr, _T_862
node _T_863 = bits(_WIRE_61, 10, 10)
connect _WIRE_60.hx, _T_863
node _T_864 = bits(_WIRE_61, 11, 11)
connect _WIRE_60.hw, _T_864
node _T_865 = bits(_WIRE_61, 12, 12)
connect _WIRE_60.sr, _T_865
node _T_866 = bits(_WIRE_61, 13, 13)
connect _WIRE_60.sx, _T_866
node _T_867 = bits(_WIRE_61, 14, 14)
connect _WIRE_60.sw, _T_867
node _T_868 = bits(_WIRE_61, 15, 15)
connect _WIRE_60.gf, _T_868
node _T_869 = bits(_WIRE_61, 16, 16)
connect _WIRE_60.pf, _T_869
node _T_870 = bits(_WIRE_61, 17, 17)
connect _WIRE_60.ae_stage2, _T_870
node _T_871 = bits(_WIRE_61, 18, 18)
connect _WIRE_60.ae_final, _T_871
node _T_872 = bits(_WIRE_61, 19, 19)
connect _WIRE_60.ae_ptw, _T_872
node _T_873 = bits(_WIRE_61, 20, 20)
connect _WIRE_60.g, _T_873
node _T_874 = bits(_WIRE_61, 21, 21)
connect _WIRE_60.u, _T_874
node _T_875 = bits(_WIRE_61, 41, 22)
connect _WIRE_60.ppn, _T_875
wire _WIRE_62 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_63 : UInt<42>
connect _WIRE_63, sectored_entries[0][1].data[3]
node _T_876 = bits(_WIRE_63, 0, 0)
connect _WIRE_62.fragmented_superpage, _T_876
node _T_877 = bits(_WIRE_63, 1, 1)
connect _WIRE_62.c, _T_877
node _T_878 = bits(_WIRE_63, 2, 2)
connect _WIRE_62.eff, _T_878
node _T_879 = bits(_WIRE_63, 3, 3)
connect _WIRE_62.paa, _T_879
node _T_880 = bits(_WIRE_63, 4, 4)
connect _WIRE_62.pal, _T_880
node _T_881 = bits(_WIRE_63, 5, 5)
connect _WIRE_62.ppp, _T_881
node _T_882 = bits(_WIRE_63, 6, 6)
connect _WIRE_62.pr, _T_882
node _T_883 = bits(_WIRE_63, 7, 7)
connect _WIRE_62.px, _T_883
node _T_884 = bits(_WIRE_63, 8, 8)
connect _WIRE_62.pw, _T_884
node _T_885 = bits(_WIRE_63, 9, 9)
connect _WIRE_62.hr, _T_885
node _T_886 = bits(_WIRE_63, 10, 10)
connect _WIRE_62.hx, _T_886
node _T_887 = bits(_WIRE_63, 11, 11)
connect _WIRE_62.hw, _T_887
node _T_888 = bits(_WIRE_63, 12, 12)
connect _WIRE_62.sr, _T_888
node _T_889 = bits(_WIRE_63, 13, 13)
connect _WIRE_62.sx, _T_889
node _T_890 = bits(_WIRE_63, 14, 14)
connect _WIRE_62.sw, _T_890
node _T_891 = bits(_WIRE_63, 15, 15)
connect _WIRE_62.gf, _T_891
node _T_892 = bits(_WIRE_63, 16, 16)
connect _WIRE_62.pf, _T_892
node _T_893 = bits(_WIRE_63, 17, 17)
connect _WIRE_62.ae_stage2, _T_893
node _T_894 = bits(_WIRE_63, 18, 18)
connect _WIRE_62.ae_final, _T_894
node _T_895 = bits(_WIRE_63, 19, 19)
connect _WIRE_62.ae_ptw, _T_895
node _T_896 = bits(_WIRE_63, 20, 20)
connect _WIRE_62.g, _T_896
node _T_897 = bits(_WIRE_63, 21, 21)
connect _WIRE_62.u, _T_897
node _T_898 = bits(_WIRE_63, 41, 22)
connect _WIRE_62.ppn, _T_898
node _T_899 = eq(sectored_entries[0][1].tag_v, _T_806)
when _T_899 :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
node _T_900 = eq(sectored_entries[0][1].tag_v, _T_806)
when _T_900 :
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
node _T_901 = eq(sectored_entries[0][1].tag_v, _T_806)
when _T_901 :
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
node _T_902 = eq(sectored_entries[0][1].tag_v, _T_806)
when _T_902 :
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
node hv_2 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_2 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_903 = eq(hg_2, UInt<1>(0h0))
node _T_904 = and(_T_903, io.sfence.bits.rs1)
when _T_904 :
node _T_905 = xor(sectored_entries[0][2].tag_vpn, vpn)
node _T_906 = shr(_T_905, 2)
node _T_907 = eq(_T_906, UInt<1>(0h0))
node _T_908 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_909 = and(_T_907, _T_908)
when _T_909 :
wire _WIRE_64 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_65 : UInt<42>
connect _WIRE_65, sectored_entries[0][2].data[0]
node _T_910 = bits(_WIRE_65, 0, 0)
connect _WIRE_64.fragmented_superpage, _T_910
node _T_911 = bits(_WIRE_65, 1, 1)
connect _WIRE_64.c, _T_911
node _T_912 = bits(_WIRE_65, 2, 2)
connect _WIRE_64.eff, _T_912
node _T_913 = bits(_WIRE_65, 3, 3)
connect _WIRE_64.paa, _T_913
node _T_914 = bits(_WIRE_65, 4, 4)
connect _WIRE_64.pal, _T_914
node _T_915 = bits(_WIRE_65, 5, 5)
connect _WIRE_64.ppp, _T_915
node _T_916 = bits(_WIRE_65, 6, 6)
connect _WIRE_64.pr, _T_916
node _T_917 = bits(_WIRE_65, 7, 7)
connect _WIRE_64.px, _T_917
node _T_918 = bits(_WIRE_65, 8, 8)
connect _WIRE_64.pw, _T_918
node _T_919 = bits(_WIRE_65, 9, 9)
connect _WIRE_64.hr, _T_919
node _T_920 = bits(_WIRE_65, 10, 10)
connect _WIRE_64.hx, _T_920
node _T_921 = bits(_WIRE_65, 11, 11)
connect _WIRE_64.hw, _T_921
node _T_922 = bits(_WIRE_65, 12, 12)
connect _WIRE_64.sr, _T_922
node _T_923 = bits(_WIRE_65, 13, 13)
connect _WIRE_64.sx, _T_923
node _T_924 = bits(_WIRE_65, 14, 14)
connect _WIRE_64.sw, _T_924
node _T_925 = bits(_WIRE_65, 15, 15)
connect _WIRE_64.gf, _T_925
node _T_926 = bits(_WIRE_65, 16, 16)
connect _WIRE_64.pf, _T_926
node _T_927 = bits(_WIRE_65, 17, 17)
connect _WIRE_64.ae_stage2, _T_927
node _T_928 = bits(_WIRE_65, 18, 18)
connect _WIRE_64.ae_final, _T_928
node _T_929 = bits(_WIRE_65, 19, 19)
connect _WIRE_64.ae_ptw, _T_929
node _T_930 = bits(_WIRE_65, 20, 20)
connect _WIRE_64.g, _T_930
node _T_931 = bits(_WIRE_65, 21, 21)
connect _WIRE_64.u, _T_931
node _T_932 = bits(_WIRE_65, 41, 22)
connect _WIRE_64.ppn, _T_932
wire _WIRE_66 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_67 : UInt<42>
connect _WIRE_67, sectored_entries[0][2].data[1]
node _T_933 = bits(_WIRE_67, 0, 0)
connect _WIRE_66.fragmented_superpage, _T_933
node _T_934 = bits(_WIRE_67, 1, 1)
connect _WIRE_66.c, _T_934
node _T_935 = bits(_WIRE_67, 2, 2)
connect _WIRE_66.eff, _T_935
node _T_936 = bits(_WIRE_67, 3, 3)
connect _WIRE_66.paa, _T_936
node _T_937 = bits(_WIRE_67, 4, 4)
connect _WIRE_66.pal, _T_937
node _T_938 = bits(_WIRE_67, 5, 5)
connect _WIRE_66.ppp, _T_938
node _T_939 = bits(_WIRE_67, 6, 6)
connect _WIRE_66.pr, _T_939
node _T_940 = bits(_WIRE_67, 7, 7)
connect _WIRE_66.px, _T_940
node _T_941 = bits(_WIRE_67, 8, 8)
connect _WIRE_66.pw, _T_941
node _T_942 = bits(_WIRE_67, 9, 9)
connect _WIRE_66.hr, _T_942
node _T_943 = bits(_WIRE_67, 10, 10)
connect _WIRE_66.hx, _T_943
node _T_944 = bits(_WIRE_67, 11, 11)
connect _WIRE_66.hw, _T_944
node _T_945 = bits(_WIRE_67, 12, 12)
connect _WIRE_66.sr, _T_945
node _T_946 = bits(_WIRE_67, 13, 13)
connect _WIRE_66.sx, _T_946
node _T_947 = bits(_WIRE_67, 14, 14)
connect _WIRE_66.sw, _T_947
node _T_948 = bits(_WIRE_67, 15, 15)
connect _WIRE_66.gf, _T_948
node _T_949 = bits(_WIRE_67, 16, 16)
connect _WIRE_66.pf, _T_949
node _T_950 = bits(_WIRE_67, 17, 17)
connect _WIRE_66.ae_stage2, _T_950
node _T_951 = bits(_WIRE_67, 18, 18)
connect _WIRE_66.ae_final, _T_951
node _T_952 = bits(_WIRE_67, 19, 19)
connect _WIRE_66.ae_ptw, _T_952
node _T_953 = bits(_WIRE_67, 20, 20)
connect _WIRE_66.g, _T_953
node _T_954 = bits(_WIRE_67, 21, 21)
connect _WIRE_66.u, _T_954
node _T_955 = bits(_WIRE_67, 41, 22)
connect _WIRE_66.ppn, _T_955
wire _WIRE_68 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_69 : UInt<42>
connect _WIRE_69, sectored_entries[0][2].data[2]
node _T_956 = bits(_WIRE_69, 0, 0)
connect _WIRE_68.fragmented_superpage, _T_956
node _T_957 = bits(_WIRE_69, 1, 1)
connect _WIRE_68.c, _T_957
node _T_958 = bits(_WIRE_69, 2, 2)
connect _WIRE_68.eff, _T_958
node _T_959 = bits(_WIRE_69, 3, 3)
connect _WIRE_68.paa, _T_959
node _T_960 = bits(_WIRE_69, 4, 4)
connect _WIRE_68.pal, _T_960
node _T_961 = bits(_WIRE_69, 5, 5)
connect _WIRE_68.ppp, _T_961
node _T_962 = bits(_WIRE_69, 6, 6)
connect _WIRE_68.pr, _T_962
node _T_963 = bits(_WIRE_69, 7, 7)
connect _WIRE_68.px, _T_963
node _T_964 = bits(_WIRE_69, 8, 8)
connect _WIRE_68.pw, _T_964
node _T_965 = bits(_WIRE_69, 9, 9)
connect _WIRE_68.hr, _T_965
node _T_966 = bits(_WIRE_69, 10, 10)
connect _WIRE_68.hx, _T_966
node _T_967 = bits(_WIRE_69, 11, 11)
connect _WIRE_68.hw, _T_967
node _T_968 = bits(_WIRE_69, 12, 12)
connect _WIRE_68.sr, _T_968
node _T_969 = bits(_WIRE_69, 13, 13)
connect _WIRE_68.sx, _T_969
node _T_970 = bits(_WIRE_69, 14, 14)
connect _WIRE_68.sw, _T_970
node _T_971 = bits(_WIRE_69, 15, 15)
connect _WIRE_68.gf, _T_971
node _T_972 = bits(_WIRE_69, 16, 16)
connect _WIRE_68.pf, _T_972
node _T_973 = bits(_WIRE_69, 17, 17)
connect _WIRE_68.ae_stage2, _T_973
node _T_974 = bits(_WIRE_69, 18, 18)
connect _WIRE_68.ae_final, _T_974
node _T_975 = bits(_WIRE_69, 19, 19)
connect _WIRE_68.ae_ptw, _T_975
node _T_976 = bits(_WIRE_69, 20, 20)
connect _WIRE_68.g, _T_976
node _T_977 = bits(_WIRE_69, 21, 21)
connect _WIRE_68.u, _T_977
node _T_978 = bits(_WIRE_69, 41, 22)
connect _WIRE_68.ppn, _T_978
wire _WIRE_70 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_71 : UInt<42>
connect _WIRE_71, sectored_entries[0][2].data[3]
node _T_979 = bits(_WIRE_71, 0, 0)
connect _WIRE_70.fragmented_superpage, _T_979
node _T_980 = bits(_WIRE_71, 1, 1)
connect _WIRE_70.c, _T_980
node _T_981 = bits(_WIRE_71, 2, 2)
connect _WIRE_70.eff, _T_981
node _T_982 = bits(_WIRE_71, 3, 3)
connect _WIRE_70.paa, _T_982
node _T_983 = bits(_WIRE_71, 4, 4)
connect _WIRE_70.pal, _T_983
node _T_984 = bits(_WIRE_71, 5, 5)
connect _WIRE_70.ppp, _T_984
node _T_985 = bits(_WIRE_71, 6, 6)
connect _WIRE_70.pr, _T_985
node _T_986 = bits(_WIRE_71, 7, 7)
connect _WIRE_70.px, _T_986
node _T_987 = bits(_WIRE_71, 8, 8)
connect _WIRE_70.pw, _T_987
node _T_988 = bits(_WIRE_71, 9, 9)
connect _WIRE_70.hr, _T_988
node _T_989 = bits(_WIRE_71, 10, 10)
connect _WIRE_70.hx, _T_989
node _T_990 = bits(_WIRE_71, 11, 11)
connect _WIRE_70.hw, _T_990
node _T_991 = bits(_WIRE_71, 12, 12)
connect _WIRE_70.sr, _T_991
node _T_992 = bits(_WIRE_71, 13, 13)
connect _WIRE_70.sx, _T_992
node _T_993 = bits(_WIRE_71, 14, 14)
connect _WIRE_70.sw, _T_993
node _T_994 = bits(_WIRE_71, 15, 15)
connect _WIRE_70.gf, _T_994
node _T_995 = bits(_WIRE_71, 16, 16)
connect _WIRE_70.pf, _T_995
node _T_996 = bits(_WIRE_71, 17, 17)
connect _WIRE_70.ae_stage2, _T_996
node _T_997 = bits(_WIRE_71, 18, 18)
connect _WIRE_70.ae_final, _T_997
node _T_998 = bits(_WIRE_71, 19, 19)
connect _WIRE_70.ae_ptw, _T_998
node _T_999 = bits(_WIRE_71, 20, 20)
connect _WIRE_70.g, _T_999
node _T_1000 = bits(_WIRE_71, 21, 21)
connect _WIRE_70.u, _T_1000
node _T_1001 = bits(_WIRE_71, 41, 22)
connect _WIRE_70.ppn, _T_1001
node _T_1002 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1003 = bits(vpn, 1, 0)
node _T_1004 = eq(UInt<1>(0h0), _T_1003)
node _T_1005 = and(_T_1002, _T_1004)
when _T_1005 :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
node _T_1006 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1007 = bits(vpn, 1, 0)
node _T_1008 = eq(UInt<1>(0h1), _T_1007)
node _T_1009 = and(_T_1006, _T_1008)
when _T_1009 :
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
node _T_1010 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1011 = bits(vpn, 1, 0)
node _T_1012 = eq(UInt<2>(0h2), _T_1011)
node _T_1013 = and(_T_1010, _T_1012)
when _T_1013 :
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
node _T_1014 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1015 = bits(vpn, 1, 0)
node _T_1016 = eq(UInt<2>(0h3), _T_1015)
node _T_1017 = and(_T_1014, _T_1016)
when _T_1017 :
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
node _T_1018 = xor(sectored_entries[0][2].tag_vpn, vpn)
node _T_1019 = shr(_T_1018, 18)
node _T_1020 = eq(_T_1019, UInt<1>(0h0))
when _T_1020 :
wire _WIRE_72 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_73 : UInt<42>
connect _WIRE_73, sectored_entries[0][2].data[0]
node _T_1021 = bits(_WIRE_73, 0, 0)
connect _WIRE_72.fragmented_superpage, _T_1021
node _T_1022 = bits(_WIRE_73, 1, 1)
connect _WIRE_72.c, _T_1022
node _T_1023 = bits(_WIRE_73, 2, 2)
connect _WIRE_72.eff, _T_1023
node _T_1024 = bits(_WIRE_73, 3, 3)
connect _WIRE_72.paa, _T_1024
node _T_1025 = bits(_WIRE_73, 4, 4)
connect _WIRE_72.pal, _T_1025
node _T_1026 = bits(_WIRE_73, 5, 5)
connect _WIRE_72.ppp, _T_1026
node _T_1027 = bits(_WIRE_73, 6, 6)
connect _WIRE_72.pr, _T_1027
node _T_1028 = bits(_WIRE_73, 7, 7)
connect _WIRE_72.px, _T_1028
node _T_1029 = bits(_WIRE_73, 8, 8)
connect _WIRE_72.pw, _T_1029
node _T_1030 = bits(_WIRE_73, 9, 9)
connect _WIRE_72.hr, _T_1030
node _T_1031 = bits(_WIRE_73, 10, 10)
connect _WIRE_72.hx, _T_1031
node _T_1032 = bits(_WIRE_73, 11, 11)
connect _WIRE_72.hw, _T_1032
node _T_1033 = bits(_WIRE_73, 12, 12)
connect _WIRE_72.sr, _T_1033
node _T_1034 = bits(_WIRE_73, 13, 13)
connect _WIRE_72.sx, _T_1034
node _T_1035 = bits(_WIRE_73, 14, 14)
connect _WIRE_72.sw, _T_1035
node _T_1036 = bits(_WIRE_73, 15, 15)
connect _WIRE_72.gf, _T_1036
node _T_1037 = bits(_WIRE_73, 16, 16)
connect _WIRE_72.pf, _T_1037
node _T_1038 = bits(_WIRE_73, 17, 17)
connect _WIRE_72.ae_stage2, _T_1038
node _T_1039 = bits(_WIRE_73, 18, 18)
connect _WIRE_72.ae_final, _T_1039
node _T_1040 = bits(_WIRE_73, 19, 19)
connect _WIRE_72.ae_ptw, _T_1040
node _T_1041 = bits(_WIRE_73, 20, 20)
connect _WIRE_72.g, _T_1041
node _T_1042 = bits(_WIRE_73, 21, 21)
connect _WIRE_72.u, _T_1042
node _T_1043 = bits(_WIRE_73, 41, 22)
connect _WIRE_72.ppn, _T_1043
wire _WIRE_74 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_75 : UInt<42>
connect _WIRE_75, sectored_entries[0][2].data[1]
node _T_1044 = bits(_WIRE_75, 0, 0)
connect _WIRE_74.fragmented_superpage, _T_1044
node _T_1045 = bits(_WIRE_75, 1, 1)
connect _WIRE_74.c, _T_1045
node _T_1046 = bits(_WIRE_75, 2, 2)
connect _WIRE_74.eff, _T_1046
node _T_1047 = bits(_WIRE_75, 3, 3)
connect _WIRE_74.paa, _T_1047
node _T_1048 = bits(_WIRE_75, 4, 4)
connect _WIRE_74.pal, _T_1048
node _T_1049 = bits(_WIRE_75, 5, 5)
connect _WIRE_74.ppp, _T_1049
node _T_1050 = bits(_WIRE_75, 6, 6)
connect _WIRE_74.pr, _T_1050
node _T_1051 = bits(_WIRE_75, 7, 7)
connect _WIRE_74.px, _T_1051
node _T_1052 = bits(_WIRE_75, 8, 8)
connect _WIRE_74.pw, _T_1052
node _T_1053 = bits(_WIRE_75, 9, 9)
connect _WIRE_74.hr, _T_1053
node _T_1054 = bits(_WIRE_75, 10, 10)
connect _WIRE_74.hx, _T_1054
node _T_1055 = bits(_WIRE_75, 11, 11)
connect _WIRE_74.hw, _T_1055
node _T_1056 = bits(_WIRE_75, 12, 12)
connect _WIRE_74.sr, _T_1056
node _T_1057 = bits(_WIRE_75, 13, 13)
connect _WIRE_74.sx, _T_1057
node _T_1058 = bits(_WIRE_75, 14, 14)
connect _WIRE_74.sw, _T_1058
node _T_1059 = bits(_WIRE_75, 15, 15)
connect _WIRE_74.gf, _T_1059
node _T_1060 = bits(_WIRE_75, 16, 16)
connect _WIRE_74.pf, _T_1060
node _T_1061 = bits(_WIRE_75, 17, 17)
connect _WIRE_74.ae_stage2, _T_1061
node _T_1062 = bits(_WIRE_75, 18, 18)
connect _WIRE_74.ae_final, _T_1062
node _T_1063 = bits(_WIRE_75, 19, 19)
connect _WIRE_74.ae_ptw, _T_1063
node _T_1064 = bits(_WIRE_75, 20, 20)
connect _WIRE_74.g, _T_1064
node _T_1065 = bits(_WIRE_75, 21, 21)
connect _WIRE_74.u, _T_1065
node _T_1066 = bits(_WIRE_75, 41, 22)
connect _WIRE_74.ppn, _T_1066
wire _WIRE_76 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_77 : UInt<42>
connect _WIRE_77, sectored_entries[0][2].data[2]
node _T_1067 = bits(_WIRE_77, 0, 0)
connect _WIRE_76.fragmented_superpage, _T_1067
node _T_1068 = bits(_WIRE_77, 1, 1)
connect _WIRE_76.c, _T_1068
node _T_1069 = bits(_WIRE_77, 2, 2)
connect _WIRE_76.eff, _T_1069
node _T_1070 = bits(_WIRE_77, 3, 3)
connect _WIRE_76.paa, _T_1070
node _T_1071 = bits(_WIRE_77, 4, 4)
connect _WIRE_76.pal, _T_1071
node _T_1072 = bits(_WIRE_77, 5, 5)
connect _WIRE_76.ppp, _T_1072
node _T_1073 = bits(_WIRE_77, 6, 6)
connect _WIRE_76.pr, _T_1073
node _T_1074 = bits(_WIRE_77, 7, 7)
connect _WIRE_76.px, _T_1074
node _T_1075 = bits(_WIRE_77, 8, 8)
connect _WIRE_76.pw, _T_1075
node _T_1076 = bits(_WIRE_77, 9, 9)
connect _WIRE_76.hr, _T_1076
node _T_1077 = bits(_WIRE_77, 10, 10)
connect _WIRE_76.hx, _T_1077
node _T_1078 = bits(_WIRE_77, 11, 11)
connect _WIRE_76.hw, _T_1078
node _T_1079 = bits(_WIRE_77, 12, 12)
connect _WIRE_76.sr, _T_1079
node _T_1080 = bits(_WIRE_77, 13, 13)
connect _WIRE_76.sx, _T_1080
node _T_1081 = bits(_WIRE_77, 14, 14)
connect _WIRE_76.sw, _T_1081
node _T_1082 = bits(_WIRE_77, 15, 15)
connect _WIRE_76.gf, _T_1082
node _T_1083 = bits(_WIRE_77, 16, 16)
connect _WIRE_76.pf, _T_1083
node _T_1084 = bits(_WIRE_77, 17, 17)
connect _WIRE_76.ae_stage2, _T_1084
node _T_1085 = bits(_WIRE_77, 18, 18)
connect _WIRE_76.ae_final, _T_1085
node _T_1086 = bits(_WIRE_77, 19, 19)
connect _WIRE_76.ae_ptw, _T_1086
node _T_1087 = bits(_WIRE_77, 20, 20)
connect _WIRE_76.g, _T_1087
node _T_1088 = bits(_WIRE_77, 21, 21)
connect _WIRE_76.u, _T_1088
node _T_1089 = bits(_WIRE_77, 41, 22)
connect _WIRE_76.ppn, _T_1089
wire _WIRE_78 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_79 : UInt<42>
connect _WIRE_79, sectored_entries[0][2].data[3]
node _T_1090 = bits(_WIRE_79, 0, 0)
connect _WIRE_78.fragmented_superpage, _T_1090
node _T_1091 = bits(_WIRE_79, 1, 1)
connect _WIRE_78.c, _T_1091
node _T_1092 = bits(_WIRE_79, 2, 2)
connect _WIRE_78.eff, _T_1092
node _T_1093 = bits(_WIRE_79, 3, 3)
connect _WIRE_78.paa, _T_1093
node _T_1094 = bits(_WIRE_79, 4, 4)
connect _WIRE_78.pal, _T_1094
node _T_1095 = bits(_WIRE_79, 5, 5)
connect _WIRE_78.ppp, _T_1095
node _T_1096 = bits(_WIRE_79, 6, 6)
connect _WIRE_78.pr, _T_1096
node _T_1097 = bits(_WIRE_79, 7, 7)
connect _WIRE_78.px, _T_1097
node _T_1098 = bits(_WIRE_79, 8, 8)
connect _WIRE_78.pw, _T_1098
node _T_1099 = bits(_WIRE_79, 9, 9)
connect _WIRE_78.hr, _T_1099
node _T_1100 = bits(_WIRE_79, 10, 10)
connect _WIRE_78.hx, _T_1100
node _T_1101 = bits(_WIRE_79, 11, 11)
connect _WIRE_78.hw, _T_1101
node _T_1102 = bits(_WIRE_79, 12, 12)
connect _WIRE_78.sr, _T_1102
node _T_1103 = bits(_WIRE_79, 13, 13)
connect _WIRE_78.sx, _T_1103
node _T_1104 = bits(_WIRE_79, 14, 14)
connect _WIRE_78.sw, _T_1104
node _T_1105 = bits(_WIRE_79, 15, 15)
connect _WIRE_78.gf, _T_1105
node _T_1106 = bits(_WIRE_79, 16, 16)
connect _WIRE_78.pf, _T_1106
node _T_1107 = bits(_WIRE_79, 17, 17)
connect _WIRE_78.ae_stage2, _T_1107
node _T_1108 = bits(_WIRE_79, 18, 18)
connect _WIRE_78.ae_final, _T_1108
node _T_1109 = bits(_WIRE_79, 19, 19)
connect _WIRE_78.ae_ptw, _T_1109
node _T_1110 = bits(_WIRE_79, 20, 20)
connect _WIRE_78.g, _T_1110
node _T_1111 = bits(_WIRE_79, 21, 21)
connect _WIRE_78.u, _T_1111
node _T_1112 = bits(_WIRE_79, 41, 22)
connect _WIRE_78.ppn, _T_1112
node _T_1113 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1114 = and(_T_1113, _WIRE_72.fragmented_superpage)
when _T_1114 :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
node _T_1115 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1116 = and(_T_1115, _WIRE_74.fragmented_superpage)
when _T_1116 :
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
node _T_1117 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1118 = and(_T_1117, _WIRE_76.fragmented_superpage)
when _T_1118 :
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
node _T_1119 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1120 = and(_T_1119, _WIRE_78.fragmented_superpage)
when _T_1120 :
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
else :
node _T_1121 = eq(hg_2, UInt<1>(0h0))
node _T_1122 = and(_T_1121, io.sfence.bits.rs2)
when _T_1122 :
wire _WIRE_80 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_81 : UInt<42>
connect _WIRE_81, sectored_entries[0][2].data[0]
node _T_1123 = bits(_WIRE_81, 0, 0)
connect _WIRE_80.fragmented_superpage, _T_1123
node _T_1124 = bits(_WIRE_81, 1, 1)
connect _WIRE_80.c, _T_1124
node _T_1125 = bits(_WIRE_81, 2, 2)
connect _WIRE_80.eff, _T_1125
node _T_1126 = bits(_WIRE_81, 3, 3)
connect _WIRE_80.paa, _T_1126
node _T_1127 = bits(_WIRE_81, 4, 4)
connect _WIRE_80.pal, _T_1127
node _T_1128 = bits(_WIRE_81, 5, 5)
connect _WIRE_80.ppp, _T_1128
node _T_1129 = bits(_WIRE_81, 6, 6)
connect _WIRE_80.pr, _T_1129
node _T_1130 = bits(_WIRE_81, 7, 7)
connect _WIRE_80.px, _T_1130
node _T_1131 = bits(_WIRE_81, 8, 8)
connect _WIRE_80.pw, _T_1131
node _T_1132 = bits(_WIRE_81, 9, 9)
connect _WIRE_80.hr, _T_1132
node _T_1133 = bits(_WIRE_81, 10, 10)
connect _WIRE_80.hx, _T_1133
node _T_1134 = bits(_WIRE_81, 11, 11)
connect _WIRE_80.hw, _T_1134
node _T_1135 = bits(_WIRE_81, 12, 12)
connect _WIRE_80.sr, _T_1135
node _T_1136 = bits(_WIRE_81, 13, 13)
connect _WIRE_80.sx, _T_1136
node _T_1137 = bits(_WIRE_81, 14, 14)
connect _WIRE_80.sw, _T_1137
node _T_1138 = bits(_WIRE_81, 15, 15)
connect _WIRE_80.gf, _T_1138
node _T_1139 = bits(_WIRE_81, 16, 16)
connect _WIRE_80.pf, _T_1139
node _T_1140 = bits(_WIRE_81, 17, 17)
connect _WIRE_80.ae_stage2, _T_1140
node _T_1141 = bits(_WIRE_81, 18, 18)
connect _WIRE_80.ae_final, _T_1141
node _T_1142 = bits(_WIRE_81, 19, 19)
connect _WIRE_80.ae_ptw, _T_1142
node _T_1143 = bits(_WIRE_81, 20, 20)
connect _WIRE_80.g, _T_1143
node _T_1144 = bits(_WIRE_81, 21, 21)
connect _WIRE_80.u, _T_1144
node _T_1145 = bits(_WIRE_81, 41, 22)
connect _WIRE_80.ppn, _T_1145
wire _WIRE_82 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_83 : UInt<42>
connect _WIRE_83, sectored_entries[0][2].data[1]
node _T_1146 = bits(_WIRE_83, 0, 0)
connect _WIRE_82.fragmented_superpage, _T_1146
node _T_1147 = bits(_WIRE_83, 1, 1)
connect _WIRE_82.c, _T_1147
node _T_1148 = bits(_WIRE_83, 2, 2)
connect _WIRE_82.eff, _T_1148
node _T_1149 = bits(_WIRE_83, 3, 3)
connect _WIRE_82.paa, _T_1149
node _T_1150 = bits(_WIRE_83, 4, 4)
connect _WIRE_82.pal, _T_1150
node _T_1151 = bits(_WIRE_83, 5, 5)
connect _WIRE_82.ppp, _T_1151
node _T_1152 = bits(_WIRE_83, 6, 6)
connect _WIRE_82.pr, _T_1152
node _T_1153 = bits(_WIRE_83, 7, 7)
connect _WIRE_82.px, _T_1153
node _T_1154 = bits(_WIRE_83, 8, 8)
connect _WIRE_82.pw, _T_1154
node _T_1155 = bits(_WIRE_83, 9, 9)
connect _WIRE_82.hr, _T_1155
node _T_1156 = bits(_WIRE_83, 10, 10)
connect _WIRE_82.hx, _T_1156
node _T_1157 = bits(_WIRE_83, 11, 11)
connect _WIRE_82.hw, _T_1157
node _T_1158 = bits(_WIRE_83, 12, 12)
connect _WIRE_82.sr, _T_1158
node _T_1159 = bits(_WIRE_83, 13, 13)
connect _WIRE_82.sx, _T_1159
node _T_1160 = bits(_WIRE_83, 14, 14)
connect _WIRE_82.sw, _T_1160
node _T_1161 = bits(_WIRE_83, 15, 15)
connect _WIRE_82.gf, _T_1161
node _T_1162 = bits(_WIRE_83, 16, 16)
connect _WIRE_82.pf, _T_1162
node _T_1163 = bits(_WIRE_83, 17, 17)
connect _WIRE_82.ae_stage2, _T_1163
node _T_1164 = bits(_WIRE_83, 18, 18)
connect _WIRE_82.ae_final, _T_1164
node _T_1165 = bits(_WIRE_83, 19, 19)
connect _WIRE_82.ae_ptw, _T_1165
node _T_1166 = bits(_WIRE_83, 20, 20)
connect _WIRE_82.g, _T_1166
node _T_1167 = bits(_WIRE_83, 21, 21)
connect _WIRE_82.u, _T_1167
node _T_1168 = bits(_WIRE_83, 41, 22)
connect _WIRE_82.ppn, _T_1168
wire _WIRE_84 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_85 : UInt<42>
connect _WIRE_85, sectored_entries[0][2].data[2]
node _T_1169 = bits(_WIRE_85, 0, 0)
connect _WIRE_84.fragmented_superpage, _T_1169
node _T_1170 = bits(_WIRE_85, 1, 1)
connect _WIRE_84.c, _T_1170
node _T_1171 = bits(_WIRE_85, 2, 2)
connect _WIRE_84.eff, _T_1171
node _T_1172 = bits(_WIRE_85, 3, 3)
connect _WIRE_84.paa, _T_1172
node _T_1173 = bits(_WIRE_85, 4, 4)
connect _WIRE_84.pal, _T_1173
node _T_1174 = bits(_WIRE_85, 5, 5)
connect _WIRE_84.ppp, _T_1174
node _T_1175 = bits(_WIRE_85, 6, 6)
connect _WIRE_84.pr, _T_1175
node _T_1176 = bits(_WIRE_85, 7, 7)
connect _WIRE_84.px, _T_1176
node _T_1177 = bits(_WIRE_85, 8, 8)
connect _WIRE_84.pw, _T_1177
node _T_1178 = bits(_WIRE_85, 9, 9)
connect _WIRE_84.hr, _T_1178
node _T_1179 = bits(_WIRE_85, 10, 10)
connect _WIRE_84.hx, _T_1179
node _T_1180 = bits(_WIRE_85, 11, 11)
connect _WIRE_84.hw, _T_1180
node _T_1181 = bits(_WIRE_85, 12, 12)
connect _WIRE_84.sr, _T_1181
node _T_1182 = bits(_WIRE_85, 13, 13)
connect _WIRE_84.sx, _T_1182
node _T_1183 = bits(_WIRE_85, 14, 14)
connect _WIRE_84.sw, _T_1183
node _T_1184 = bits(_WIRE_85, 15, 15)
connect _WIRE_84.gf, _T_1184
node _T_1185 = bits(_WIRE_85, 16, 16)
connect _WIRE_84.pf, _T_1185
node _T_1186 = bits(_WIRE_85, 17, 17)
connect _WIRE_84.ae_stage2, _T_1186
node _T_1187 = bits(_WIRE_85, 18, 18)
connect _WIRE_84.ae_final, _T_1187
node _T_1188 = bits(_WIRE_85, 19, 19)
connect _WIRE_84.ae_ptw, _T_1188
node _T_1189 = bits(_WIRE_85, 20, 20)
connect _WIRE_84.g, _T_1189
node _T_1190 = bits(_WIRE_85, 21, 21)
connect _WIRE_84.u, _T_1190
node _T_1191 = bits(_WIRE_85, 41, 22)
connect _WIRE_84.ppn, _T_1191
wire _WIRE_86 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_87 : UInt<42>
connect _WIRE_87, sectored_entries[0][2].data[3]
node _T_1192 = bits(_WIRE_87, 0, 0)
connect _WIRE_86.fragmented_superpage, _T_1192
node _T_1193 = bits(_WIRE_87, 1, 1)
connect _WIRE_86.c, _T_1193
node _T_1194 = bits(_WIRE_87, 2, 2)
connect _WIRE_86.eff, _T_1194
node _T_1195 = bits(_WIRE_87, 3, 3)
connect _WIRE_86.paa, _T_1195
node _T_1196 = bits(_WIRE_87, 4, 4)
connect _WIRE_86.pal, _T_1196
node _T_1197 = bits(_WIRE_87, 5, 5)
connect _WIRE_86.ppp, _T_1197
node _T_1198 = bits(_WIRE_87, 6, 6)
connect _WIRE_86.pr, _T_1198
node _T_1199 = bits(_WIRE_87, 7, 7)
connect _WIRE_86.px, _T_1199
node _T_1200 = bits(_WIRE_87, 8, 8)
connect _WIRE_86.pw, _T_1200
node _T_1201 = bits(_WIRE_87, 9, 9)
connect _WIRE_86.hr, _T_1201
node _T_1202 = bits(_WIRE_87, 10, 10)
connect _WIRE_86.hx, _T_1202
node _T_1203 = bits(_WIRE_87, 11, 11)
connect _WIRE_86.hw, _T_1203
node _T_1204 = bits(_WIRE_87, 12, 12)
connect _WIRE_86.sr, _T_1204
node _T_1205 = bits(_WIRE_87, 13, 13)
connect _WIRE_86.sx, _T_1205
node _T_1206 = bits(_WIRE_87, 14, 14)
connect _WIRE_86.sw, _T_1206
node _T_1207 = bits(_WIRE_87, 15, 15)
connect _WIRE_86.gf, _T_1207
node _T_1208 = bits(_WIRE_87, 16, 16)
connect _WIRE_86.pf, _T_1208
node _T_1209 = bits(_WIRE_87, 17, 17)
connect _WIRE_86.ae_stage2, _T_1209
node _T_1210 = bits(_WIRE_87, 18, 18)
connect _WIRE_86.ae_final, _T_1210
node _T_1211 = bits(_WIRE_87, 19, 19)
connect _WIRE_86.ae_ptw, _T_1211
node _T_1212 = bits(_WIRE_87, 20, 20)
connect _WIRE_86.g, _T_1212
node _T_1213 = bits(_WIRE_87, 21, 21)
connect _WIRE_86.u, _T_1213
node _T_1214 = bits(_WIRE_87, 41, 22)
connect _WIRE_86.ppn, _T_1214
node _T_1215 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1216 = eq(_WIRE_80.g, UInt<1>(0h0))
node _T_1217 = and(_T_1215, _T_1216)
when _T_1217 :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
node _T_1218 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1219 = eq(_WIRE_82.g, UInt<1>(0h0))
node _T_1220 = and(_T_1218, _T_1219)
when _T_1220 :
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
node _T_1221 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1222 = eq(_WIRE_84.g, UInt<1>(0h0))
node _T_1223 = and(_T_1221, _T_1222)
when _T_1223 :
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
node _T_1224 = eq(sectored_entries[0][2].tag_v, hv_2)
node _T_1225 = eq(_WIRE_86.g, UInt<1>(0h0))
node _T_1226 = and(_T_1224, _T_1225)
when _T_1226 :
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
else :
node _T_1227 = or(hv_2, hg_2)
wire _WIRE_88 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_89 : UInt<42>
connect _WIRE_89, sectored_entries[0][2].data[0]
node _T_1228 = bits(_WIRE_89, 0, 0)
connect _WIRE_88.fragmented_superpage, _T_1228
node _T_1229 = bits(_WIRE_89, 1, 1)
connect _WIRE_88.c, _T_1229
node _T_1230 = bits(_WIRE_89, 2, 2)
connect _WIRE_88.eff, _T_1230
node _T_1231 = bits(_WIRE_89, 3, 3)
connect _WIRE_88.paa, _T_1231
node _T_1232 = bits(_WIRE_89, 4, 4)
connect _WIRE_88.pal, _T_1232
node _T_1233 = bits(_WIRE_89, 5, 5)
connect _WIRE_88.ppp, _T_1233
node _T_1234 = bits(_WIRE_89, 6, 6)
connect _WIRE_88.pr, _T_1234
node _T_1235 = bits(_WIRE_89, 7, 7)
connect _WIRE_88.px, _T_1235
node _T_1236 = bits(_WIRE_89, 8, 8)
connect _WIRE_88.pw, _T_1236
node _T_1237 = bits(_WIRE_89, 9, 9)
connect _WIRE_88.hr, _T_1237
node _T_1238 = bits(_WIRE_89, 10, 10)
connect _WIRE_88.hx, _T_1238
node _T_1239 = bits(_WIRE_89, 11, 11)
connect _WIRE_88.hw, _T_1239
node _T_1240 = bits(_WIRE_89, 12, 12)
connect _WIRE_88.sr, _T_1240
node _T_1241 = bits(_WIRE_89, 13, 13)
connect _WIRE_88.sx, _T_1241
node _T_1242 = bits(_WIRE_89, 14, 14)
connect _WIRE_88.sw, _T_1242
node _T_1243 = bits(_WIRE_89, 15, 15)
connect _WIRE_88.gf, _T_1243
node _T_1244 = bits(_WIRE_89, 16, 16)
connect _WIRE_88.pf, _T_1244
node _T_1245 = bits(_WIRE_89, 17, 17)
connect _WIRE_88.ae_stage2, _T_1245
node _T_1246 = bits(_WIRE_89, 18, 18)
connect _WIRE_88.ae_final, _T_1246
node _T_1247 = bits(_WIRE_89, 19, 19)
connect _WIRE_88.ae_ptw, _T_1247
node _T_1248 = bits(_WIRE_89, 20, 20)
connect _WIRE_88.g, _T_1248
node _T_1249 = bits(_WIRE_89, 21, 21)
connect _WIRE_88.u, _T_1249
node _T_1250 = bits(_WIRE_89, 41, 22)
connect _WIRE_88.ppn, _T_1250
wire _WIRE_90 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_91 : UInt<42>
connect _WIRE_91, sectored_entries[0][2].data[1]
node _T_1251 = bits(_WIRE_91, 0, 0)
connect _WIRE_90.fragmented_superpage, _T_1251
node _T_1252 = bits(_WIRE_91, 1, 1)
connect _WIRE_90.c, _T_1252
node _T_1253 = bits(_WIRE_91, 2, 2)
connect _WIRE_90.eff, _T_1253
node _T_1254 = bits(_WIRE_91, 3, 3)
connect _WIRE_90.paa, _T_1254
node _T_1255 = bits(_WIRE_91, 4, 4)
connect _WIRE_90.pal, _T_1255
node _T_1256 = bits(_WIRE_91, 5, 5)
connect _WIRE_90.ppp, _T_1256
node _T_1257 = bits(_WIRE_91, 6, 6)
connect _WIRE_90.pr, _T_1257
node _T_1258 = bits(_WIRE_91, 7, 7)
connect _WIRE_90.px, _T_1258
node _T_1259 = bits(_WIRE_91, 8, 8)
connect _WIRE_90.pw, _T_1259
node _T_1260 = bits(_WIRE_91, 9, 9)
connect _WIRE_90.hr, _T_1260
node _T_1261 = bits(_WIRE_91, 10, 10)
connect _WIRE_90.hx, _T_1261
node _T_1262 = bits(_WIRE_91, 11, 11)
connect _WIRE_90.hw, _T_1262
node _T_1263 = bits(_WIRE_91, 12, 12)
connect _WIRE_90.sr, _T_1263
node _T_1264 = bits(_WIRE_91, 13, 13)
connect _WIRE_90.sx, _T_1264
node _T_1265 = bits(_WIRE_91, 14, 14)
connect _WIRE_90.sw, _T_1265
node _T_1266 = bits(_WIRE_91, 15, 15)
connect _WIRE_90.gf, _T_1266
node _T_1267 = bits(_WIRE_91, 16, 16)
connect _WIRE_90.pf, _T_1267
node _T_1268 = bits(_WIRE_91, 17, 17)
connect _WIRE_90.ae_stage2, _T_1268
node _T_1269 = bits(_WIRE_91, 18, 18)
connect _WIRE_90.ae_final, _T_1269
node _T_1270 = bits(_WIRE_91, 19, 19)
connect _WIRE_90.ae_ptw, _T_1270
node _T_1271 = bits(_WIRE_91, 20, 20)
connect _WIRE_90.g, _T_1271
node _T_1272 = bits(_WIRE_91, 21, 21)
connect _WIRE_90.u, _T_1272
node _T_1273 = bits(_WIRE_91, 41, 22)
connect _WIRE_90.ppn, _T_1273
wire _WIRE_92 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_93 : UInt<42>
connect _WIRE_93, sectored_entries[0][2].data[2]
node _T_1274 = bits(_WIRE_93, 0, 0)
connect _WIRE_92.fragmented_superpage, _T_1274
node _T_1275 = bits(_WIRE_93, 1, 1)
connect _WIRE_92.c, _T_1275
node _T_1276 = bits(_WIRE_93, 2, 2)
connect _WIRE_92.eff, _T_1276
node _T_1277 = bits(_WIRE_93, 3, 3)
connect _WIRE_92.paa, _T_1277
node _T_1278 = bits(_WIRE_93, 4, 4)
connect _WIRE_92.pal, _T_1278
node _T_1279 = bits(_WIRE_93, 5, 5)
connect _WIRE_92.ppp, _T_1279
node _T_1280 = bits(_WIRE_93, 6, 6)
connect _WIRE_92.pr, _T_1280
node _T_1281 = bits(_WIRE_93, 7, 7)
connect _WIRE_92.px, _T_1281
node _T_1282 = bits(_WIRE_93, 8, 8)
connect _WIRE_92.pw, _T_1282
node _T_1283 = bits(_WIRE_93, 9, 9)
connect _WIRE_92.hr, _T_1283
node _T_1284 = bits(_WIRE_93, 10, 10)
connect _WIRE_92.hx, _T_1284
node _T_1285 = bits(_WIRE_93, 11, 11)
connect _WIRE_92.hw, _T_1285
node _T_1286 = bits(_WIRE_93, 12, 12)
connect _WIRE_92.sr, _T_1286
node _T_1287 = bits(_WIRE_93, 13, 13)
connect _WIRE_92.sx, _T_1287
node _T_1288 = bits(_WIRE_93, 14, 14)
connect _WIRE_92.sw, _T_1288
node _T_1289 = bits(_WIRE_93, 15, 15)
connect _WIRE_92.gf, _T_1289
node _T_1290 = bits(_WIRE_93, 16, 16)
connect _WIRE_92.pf, _T_1290
node _T_1291 = bits(_WIRE_93, 17, 17)
connect _WIRE_92.ae_stage2, _T_1291
node _T_1292 = bits(_WIRE_93, 18, 18)
connect _WIRE_92.ae_final, _T_1292
node _T_1293 = bits(_WIRE_93, 19, 19)
connect _WIRE_92.ae_ptw, _T_1293
node _T_1294 = bits(_WIRE_93, 20, 20)
connect _WIRE_92.g, _T_1294
node _T_1295 = bits(_WIRE_93, 21, 21)
connect _WIRE_92.u, _T_1295
node _T_1296 = bits(_WIRE_93, 41, 22)
connect _WIRE_92.ppn, _T_1296
wire _WIRE_94 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_95 : UInt<42>
connect _WIRE_95, sectored_entries[0][2].data[3]
node _T_1297 = bits(_WIRE_95, 0, 0)
connect _WIRE_94.fragmented_superpage, _T_1297
node _T_1298 = bits(_WIRE_95, 1, 1)
connect _WIRE_94.c, _T_1298
node _T_1299 = bits(_WIRE_95, 2, 2)
connect _WIRE_94.eff, _T_1299
node _T_1300 = bits(_WIRE_95, 3, 3)
connect _WIRE_94.paa, _T_1300
node _T_1301 = bits(_WIRE_95, 4, 4)
connect _WIRE_94.pal, _T_1301
node _T_1302 = bits(_WIRE_95, 5, 5)
connect _WIRE_94.ppp, _T_1302
node _T_1303 = bits(_WIRE_95, 6, 6)
connect _WIRE_94.pr, _T_1303
node _T_1304 = bits(_WIRE_95, 7, 7)
connect _WIRE_94.px, _T_1304
node _T_1305 = bits(_WIRE_95, 8, 8)
connect _WIRE_94.pw, _T_1305
node _T_1306 = bits(_WIRE_95, 9, 9)
connect _WIRE_94.hr, _T_1306
node _T_1307 = bits(_WIRE_95, 10, 10)
connect _WIRE_94.hx, _T_1307
node _T_1308 = bits(_WIRE_95, 11, 11)
connect _WIRE_94.hw, _T_1308
node _T_1309 = bits(_WIRE_95, 12, 12)
connect _WIRE_94.sr, _T_1309
node _T_1310 = bits(_WIRE_95, 13, 13)
connect _WIRE_94.sx, _T_1310
node _T_1311 = bits(_WIRE_95, 14, 14)
connect _WIRE_94.sw, _T_1311
node _T_1312 = bits(_WIRE_95, 15, 15)
connect _WIRE_94.gf, _T_1312
node _T_1313 = bits(_WIRE_95, 16, 16)
connect _WIRE_94.pf, _T_1313
node _T_1314 = bits(_WIRE_95, 17, 17)
connect _WIRE_94.ae_stage2, _T_1314
node _T_1315 = bits(_WIRE_95, 18, 18)
connect _WIRE_94.ae_final, _T_1315
node _T_1316 = bits(_WIRE_95, 19, 19)
connect _WIRE_94.ae_ptw, _T_1316
node _T_1317 = bits(_WIRE_95, 20, 20)
connect _WIRE_94.g, _T_1317
node _T_1318 = bits(_WIRE_95, 21, 21)
connect _WIRE_94.u, _T_1318
node _T_1319 = bits(_WIRE_95, 41, 22)
connect _WIRE_94.ppn, _T_1319
node _T_1320 = eq(sectored_entries[0][2].tag_v, _T_1227)
when _T_1320 :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
node _T_1321 = eq(sectored_entries[0][2].tag_v, _T_1227)
when _T_1321 :
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
node _T_1322 = eq(sectored_entries[0][2].tag_v, _T_1227)
when _T_1322 :
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
node _T_1323 = eq(sectored_entries[0][2].tag_v, _T_1227)
when _T_1323 :
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
node hv_3 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_3 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_1324 = eq(hg_3, UInt<1>(0h0))
node _T_1325 = and(_T_1324, io.sfence.bits.rs1)
when _T_1325 :
node _T_1326 = xor(sectored_entries[0][3].tag_vpn, vpn)
node _T_1327 = shr(_T_1326, 2)
node _T_1328 = eq(_T_1327, UInt<1>(0h0))
node _T_1329 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1330 = and(_T_1328, _T_1329)
when _T_1330 :
wire _WIRE_96 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_97 : UInt<42>
connect _WIRE_97, sectored_entries[0][3].data[0]
node _T_1331 = bits(_WIRE_97, 0, 0)
connect _WIRE_96.fragmented_superpage, _T_1331
node _T_1332 = bits(_WIRE_97, 1, 1)
connect _WIRE_96.c, _T_1332
node _T_1333 = bits(_WIRE_97, 2, 2)
connect _WIRE_96.eff, _T_1333
node _T_1334 = bits(_WIRE_97, 3, 3)
connect _WIRE_96.paa, _T_1334
node _T_1335 = bits(_WIRE_97, 4, 4)
connect _WIRE_96.pal, _T_1335
node _T_1336 = bits(_WIRE_97, 5, 5)
connect _WIRE_96.ppp, _T_1336
node _T_1337 = bits(_WIRE_97, 6, 6)
connect _WIRE_96.pr, _T_1337
node _T_1338 = bits(_WIRE_97, 7, 7)
connect _WIRE_96.px, _T_1338
node _T_1339 = bits(_WIRE_97, 8, 8)
connect _WIRE_96.pw, _T_1339
node _T_1340 = bits(_WIRE_97, 9, 9)
connect _WIRE_96.hr, _T_1340
node _T_1341 = bits(_WIRE_97, 10, 10)
connect _WIRE_96.hx, _T_1341
node _T_1342 = bits(_WIRE_97, 11, 11)
connect _WIRE_96.hw, _T_1342
node _T_1343 = bits(_WIRE_97, 12, 12)
connect _WIRE_96.sr, _T_1343
node _T_1344 = bits(_WIRE_97, 13, 13)
connect _WIRE_96.sx, _T_1344
node _T_1345 = bits(_WIRE_97, 14, 14)
connect _WIRE_96.sw, _T_1345
node _T_1346 = bits(_WIRE_97, 15, 15)
connect _WIRE_96.gf, _T_1346
node _T_1347 = bits(_WIRE_97, 16, 16)
connect _WIRE_96.pf, _T_1347
node _T_1348 = bits(_WIRE_97, 17, 17)
connect _WIRE_96.ae_stage2, _T_1348
node _T_1349 = bits(_WIRE_97, 18, 18)
connect _WIRE_96.ae_final, _T_1349
node _T_1350 = bits(_WIRE_97, 19, 19)
connect _WIRE_96.ae_ptw, _T_1350
node _T_1351 = bits(_WIRE_97, 20, 20)
connect _WIRE_96.g, _T_1351
node _T_1352 = bits(_WIRE_97, 21, 21)
connect _WIRE_96.u, _T_1352
node _T_1353 = bits(_WIRE_97, 41, 22)
connect _WIRE_96.ppn, _T_1353
wire _WIRE_98 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_99 : UInt<42>
connect _WIRE_99, sectored_entries[0][3].data[1]
node _T_1354 = bits(_WIRE_99, 0, 0)
connect _WIRE_98.fragmented_superpage, _T_1354
node _T_1355 = bits(_WIRE_99, 1, 1)
connect _WIRE_98.c, _T_1355
node _T_1356 = bits(_WIRE_99, 2, 2)
connect _WIRE_98.eff, _T_1356
node _T_1357 = bits(_WIRE_99, 3, 3)
connect _WIRE_98.paa, _T_1357
node _T_1358 = bits(_WIRE_99, 4, 4)
connect _WIRE_98.pal, _T_1358
node _T_1359 = bits(_WIRE_99, 5, 5)
connect _WIRE_98.ppp, _T_1359
node _T_1360 = bits(_WIRE_99, 6, 6)
connect _WIRE_98.pr, _T_1360
node _T_1361 = bits(_WIRE_99, 7, 7)
connect _WIRE_98.px, _T_1361
node _T_1362 = bits(_WIRE_99, 8, 8)
connect _WIRE_98.pw, _T_1362
node _T_1363 = bits(_WIRE_99, 9, 9)
connect _WIRE_98.hr, _T_1363
node _T_1364 = bits(_WIRE_99, 10, 10)
connect _WIRE_98.hx, _T_1364
node _T_1365 = bits(_WIRE_99, 11, 11)
connect _WIRE_98.hw, _T_1365
node _T_1366 = bits(_WIRE_99, 12, 12)
connect _WIRE_98.sr, _T_1366
node _T_1367 = bits(_WIRE_99, 13, 13)
connect _WIRE_98.sx, _T_1367
node _T_1368 = bits(_WIRE_99, 14, 14)
connect _WIRE_98.sw, _T_1368
node _T_1369 = bits(_WIRE_99, 15, 15)
connect _WIRE_98.gf, _T_1369
node _T_1370 = bits(_WIRE_99, 16, 16)
connect _WIRE_98.pf, _T_1370
node _T_1371 = bits(_WIRE_99, 17, 17)
connect _WIRE_98.ae_stage2, _T_1371
node _T_1372 = bits(_WIRE_99, 18, 18)
connect _WIRE_98.ae_final, _T_1372
node _T_1373 = bits(_WIRE_99, 19, 19)
connect _WIRE_98.ae_ptw, _T_1373
node _T_1374 = bits(_WIRE_99, 20, 20)
connect _WIRE_98.g, _T_1374
node _T_1375 = bits(_WIRE_99, 21, 21)
connect _WIRE_98.u, _T_1375
node _T_1376 = bits(_WIRE_99, 41, 22)
connect _WIRE_98.ppn, _T_1376
wire _WIRE_100 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_101 : UInt<42>
connect _WIRE_101, sectored_entries[0][3].data[2]
node _T_1377 = bits(_WIRE_101, 0, 0)
connect _WIRE_100.fragmented_superpage, _T_1377
node _T_1378 = bits(_WIRE_101, 1, 1)
connect _WIRE_100.c, _T_1378
node _T_1379 = bits(_WIRE_101, 2, 2)
connect _WIRE_100.eff, _T_1379
node _T_1380 = bits(_WIRE_101, 3, 3)
connect _WIRE_100.paa, _T_1380
node _T_1381 = bits(_WIRE_101, 4, 4)
connect _WIRE_100.pal, _T_1381
node _T_1382 = bits(_WIRE_101, 5, 5)
connect _WIRE_100.ppp, _T_1382
node _T_1383 = bits(_WIRE_101, 6, 6)
connect _WIRE_100.pr, _T_1383
node _T_1384 = bits(_WIRE_101, 7, 7)
connect _WIRE_100.px, _T_1384
node _T_1385 = bits(_WIRE_101, 8, 8)
connect _WIRE_100.pw, _T_1385
node _T_1386 = bits(_WIRE_101, 9, 9)
connect _WIRE_100.hr, _T_1386
node _T_1387 = bits(_WIRE_101, 10, 10)
connect _WIRE_100.hx, _T_1387
node _T_1388 = bits(_WIRE_101, 11, 11)
connect _WIRE_100.hw, _T_1388
node _T_1389 = bits(_WIRE_101, 12, 12)
connect _WIRE_100.sr, _T_1389
node _T_1390 = bits(_WIRE_101, 13, 13)
connect _WIRE_100.sx, _T_1390
node _T_1391 = bits(_WIRE_101, 14, 14)
connect _WIRE_100.sw, _T_1391
node _T_1392 = bits(_WIRE_101, 15, 15)
connect _WIRE_100.gf, _T_1392
node _T_1393 = bits(_WIRE_101, 16, 16)
connect _WIRE_100.pf, _T_1393
node _T_1394 = bits(_WIRE_101, 17, 17)
connect _WIRE_100.ae_stage2, _T_1394
node _T_1395 = bits(_WIRE_101, 18, 18)
connect _WIRE_100.ae_final, _T_1395
node _T_1396 = bits(_WIRE_101, 19, 19)
connect _WIRE_100.ae_ptw, _T_1396
node _T_1397 = bits(_WIRE_101, 20, 20)
connect _WIRE_100.g, _T_1397
node _T_1398 = bits(_WIRE_101, 21, 21)
connect _WIRE_100.u, _T_1398
node _T_1399 = bits(_WIRE_101, 41, 22)
connect _WIRE_100.ppn, _T_1399
wire _WIRE_102 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_103 : UInt<42>
connect _WIRE_103, sectored_entries[0][3].data[3]
node _T_1400 = bits(_WIRE_103, 0, 0)
connect _WIRE_102.fragmented_superpage, _T_1400
node _T_1401 = bits(_WIRE_103, 1, 1)
connect _WIRE_102.c, _T_1401
node _T_1402 = bits(_WIRE_103, 2, 2)
connect _WIRE_102.eff, _T_1402
node _T_1403 = bits(_WIRE_103, 3, 3)
connect _WIRE_102.paa, _T_1403
node _T_1404 = bits(_WIRE_103, 4, 4)
connect _WIRE_102.pal, _T_1404
node _T_1405 = bits(_WIRE_103, 5, 5)
connect _WIRE_102.ppp, _T_1405
node _T_1406 = bits(_WIRE_103, 6, 6)
connect _WIRE_102.pr, _T_1406
node _T_1407 = bits(_WIRE_103, 7, 7)
connect _WIRE_102.px, _T_1407
node _T_1408 = bits(_WIRE_103, 8, 8)
connect _WIRE_102.pw, _T_1408
node _T_1409 = bits(_WIRE_103, 9, 9)
connect _WIRE_102.hr, _T_1409
node _T_1410 = bits(_WIRE_103, 10, 10)
connect _WIRE_102.hx, _T_1410
node _T_1411 = bits(_WIRE_103, 11, 11)
connect _WIRE_102.hw, _T_1411
node _T_1412 = bits(_WIRE_103, 12, 12)
connect _WIRE_102.sr, _T_1412
node _T_1413 = bits(_WIRE_103, 13, 13)
connect _WIRE_102.sx, _T_1413
node _T_1414 = bits(_WIRE_103, 14, 14)
connect _WIRE_102.sw, _T_1414
node _T_1415 = bits(_WIRE_103, 15, 15)
connect _WIRE_102.gf, _T_1415
node _T_1416 = bits(_WIRE_103, 16, 16)
connect _WIRE_102.pf, _T_1416
node _T_1417 = bits(_WIRE_103, 17, 17)
connect _WIRE_102.ae_stage2, _T_1417
node _T_1418 = bits(_WIRE_103, 18, 18)
connect _WIRE_102.ae_final, _T_1418
node _T_1419 = bits(_WIRE_103, 19, 19)
connect _WIRE_102.ae_ptw, _T_1419
node _T_1420 = bits(_WIRE_103, 20, 20)
connect _WIRE_102.g, _T_1420
node _T_1421 = bits(_WIRE_103, 21, 21)
connect _WIRE_102.u, _T_1421
node _T_1422 = bits(_WIRE_103, 41, 22)
connect _WIRE_102.ppn, _T_1422
node _T_1423 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1424 = bits(vpn, 1, 0)
node _T_1425 = eq(UInt<1>(0h0), _T_1424)
node _T_1426 = and(_T_1423, _T_1425)
when _T_1426 :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
node _T_1427 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1428 = bits(vpn, 1, 0)
node _T_1429 = eq(UInt<1>(0h1), _T_1428)
node _T_1430 = and(_T_1427, _T_1429)
when _T_1430 :
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
node _T_1431 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1432 = bits(vpn, 1, 0)
node _T_1433 = eq(UInt<2>(0h2), _T_1432)
node _T_1434 = and(_T_1431, _T_1433)
when _T_1434 :
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
node _T_1435 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1436 = bits(vpn, 1, 0)
node _T_1437 = eq(UInt<2>(0h3), _T_1436)
node _T_1438 = and(_T_1435, _T_1437)
when _T_1438 :
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
node _T_1439 = xor(sectored_entries[0][3].tag_vpn, vpn)
node _T_1440 = shr(_T_1439, 18)
node _T_1441 = eq(_T_1440, UInt<1>(0h0))
when _T_1441 :
wire _WIRE_104 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_105 : UInt<42>
connect _WIRE_105, sectored_entries[0][3].data[0]
node _T_1442 = bits(_WIRE_105, 0, 0)
connect _WIRE_104.fragmented_superpage, _T_1442
node _T_1443 = bits(_WIRE_105, 1, 1)
connect _WIRE_104.c, _T_1443
node _T_1444 = bits(_WIRE_105, 2, 2)
connect _WIRE_104.eff, _T_1444
node _T_1445 = bits(_WIRE_105, 3, 3)
connect _WIRE_104.paa, _T_1445
node _T_1446 = bits(_WIRE_105, 4, 4)
connect _WIRE_104.pal, _T_1446
node _T_1447 = bits(_WIRE_105, 5, 5)
connect _WIRE_104.ppp, _T_1447
node _T_1448 = bits(_WIRE_105, 6, 6)
connect _WIRE_104.pr, _T_1448
node _T_1449 = bits(_WIRE_105, 7, 7)
connect _WIRE_104.px, _T_1449
node _T_1450 = bits(_WIRE_105, 8, 8)
connect _WIRE_104.pw, _T_1450
node _T_1451 = bits(_WIRE_105, 9, 9)
connect _WIRE_104.hr, _T_1451
node _T_1452 = bits(_WIRE_105, 10, 10)
connect _WIRE_104.hx, _T_1452
node _T_1453 = bits(_WIRE_105, 11, 11)
connect _WIRE_104.hw, _T_1453
node _T_1454 = bits(_WIRE_105, 12, 12)
connect _WIRE_104.sr, _T_1454
node _T_1455 = bits(_WIRE_105, 13, 13)
connect _WIRE_104.sx, _T_1455
node _T_1456 = bits(_WIRE_105, 14, 14)
connect _WIRE_104.sw, _T_1456
node _T_1457 = bits(_WIRE_105, 15, 15)
connect _WIRE_104.gf, _T_1457
node _T_1458 = bits(_WIRE_105, 16, 16)
connect _WIRE_104.pf, _T_1458
node _T_1459 = bits(_WIRE_105, 17, 17)
connect _WIRE_104.ae_stage2, _T_1459
node _T_1460 = bits(_WIRE_105, 18, 18)
connect _WIRE_104.ae_final, _T_1460
node _T_1461 = bits(_WIRE_105, 19, 19)
connect _WIRE_104.ae_ptw, _T_1461
node _T_1462 = bits(_WIRE_105, 20, 20)
connect _WIRE_104.g, _T_1462
node _T_1463 = bits(_WIRE_105, 21, 21)
connect _WIRE_104.u, _T_1463
node _T_1464 = bits(_WIRE_105, 41, 22)
connect _WIRE_104.ppn, _T_1464
wire _WIRE_106 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_107 : UInt<42>
connect _WIRE_107, sectored_entries[0][3].data[1]
node _T_1465 = bits(_WIRE_107, 0, 0)
connect _WIRE_106.fragmented_superpage, _T_1465
node _T_1466 = bits(_WIRE_107, 1, 1)
connect _WIRE_106.c, _T_1466
node _T_1467 = bits(_WIRE_107, 2, 2)
connect _WIRE_106.eff, _T_1467
node _T_1468 = bits(_WIRE_107, 3, 3)
connect _WIRE_106.paa, _T_1468
node _T_1469 = bits(_WIRE_107, 4, 4)
connect _WIRE_106.pal, _T_1469
node _T_1470 = bits(_WIRE_107, 5, 5)
connect _WIRE_106.ppp, _T_1470
node _T_1471 = bits(_WIRE_107, 6, 6)
connect _WIRE_106.pr, _T_1471
node _T_1472 = bits(_WIRE_107, 7, 7)
connect _WIRE_106.px, _T_1472
node _T_1473 = bits(_WIRE_107, 8, 8)
connect _WIRE_106.pw, _T_1473
node _T_1474 = bits(_WIRE_107, 9, 9)
connect _WIRE_106.hr, _T_1474
node _T_1475 = bits(_WIRE_107, 10, 10)
connect _WIRE_106.hx, _T_1475
node _T_1476 = bits(_WIRE_107, 11, 11)
connect _WIRE_106.hw, _T_1476
node _T_1477 = bits(_WIRE_107, 12, 12)
connect _WIRE_106.sr, _T_1477
node _T_1478 = bits(_WIRE_107, 13, 13)
connect _WIRE_106.sx, _T_1478
node _T_1479 = bits(_WIRE_107, 14, 14)
connect _WIRE_106.sw, _T_1479
node _T_1480 = bits(_WIRE_107, 15, 15)
connect _WIRE_106.gf, _T_1480
node _T_1481 = bits(_WIRE_107, 16, 16)
connect _WIRE_106.pf, _T_1481
node _T_1482 = bits(_WIRE_107, 17, 17)
connect _WIRE_106.ae_stage2, _T_1482
node _T_1483 = bits(_WIRE_107, 18, 18)
connect _WIRE_106.ae_final, _T_1483
node _T_1484 = bits(_WIRE_107, 19, 19)
connect _WIRE_106.ae_ptw, _T_1484
node _T_1485 = bits(_WIRE_107, 20, 20)
connect _WIRE_106.g, _T_1485
node _T_1486 = bits(_WIRE_107, 21, 21)
connect _WIRE_106.u, _T_1486
node _T_1487 = bits(_WIRE_107, 41, 22)
connect _WIRE_106.ppn, _T_1487
wire _WIRE_108 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_109 : UInt<42>
connect _WIRE_109, sectored_entries[0][3].data[2]
node _T_1488 = bits(_WIRE_109, 0, 0)
connect _WIRE_108.fragmented_superpage, _T_1488
node _T_1489 = bits(_WIRE_109, 1, 1)
connect _WIRE_108.c, _T_1489
node _T_1490 = bits(_WIRE_109, 2, 2)
connect _WIRE_108.eff, _T_1490
node _T_1491 = bits(_WIRE_109, 3, 3)
connect _WIRE_108.paa, _T_1491
node _T_1492 = bits(_WIRE_109, 4, 4)
connect _WIRE_108.pal, _T_1492
node _T_1493 = bits(_WIRE_109, 5, 5)
connect _WIRE_108.ppp, _T_1493
node _T_1494 = bits(_WIRE_109, 6, 6)
connect _WIRE_108.pr, _T_1494
node _T_1495 = bits(_WIRE_109, 7, 7)
connect _WIRE_108.px, _T_1495
node _T_1496 = bits(_WIRE_109, 8, 8)
connect _WIRE_108.pw, _T_1496
node _T_1497 = bits(_WIRE_109, 9, 9)
connect _WIRE_108.hr, _T_1497
node _T_1498 = bits(_WIRE_109, 10, 10)
connect _WIRE_108.hx, _T_1498
node _T_1499 = bits(_WIRE_109, 11, 11)
connect _WIRE_108.hw, _T_1499
node _T_1500 = bits(_WIRE_109, 12, 12)
connect _WIRE_108.sr, _T_1500
node _T_1501 = bits(_WIRE_109, 13, 13)
connect _WIRE_108.sx, _T_1501
node _T_1502 = bits(_WIRE_109, 14, 14)
connect _WIRE_108.sw, _T_1502
node _T_1503 = bits(_WIRE_109, 15, 15)
connect _WIRE_108.gf, _T_1503
node _T_1504 = bits(_WIRE_109, 16, 16)
connect _WIRE_108.pf, _T_1504
node _T_1505 = bits(_WIRE_109, 17, 17)
connect _WIRE_108.ae_stage2, _T_1505
node _T_1506 = bits(_WIRE_109, 18, 18)
connect _WIRE_108.ae_final, _T_1506
node _T_1507 = bits(_WIRE_109, 19, 19)
connect _WIRE_108.ae_ptw, _T_1507
node _T_1508 = bits(_WIRE_109, 20, 20)
connect _WIRE_108.g, _T_1508
node _T_1509 = bits(_WIRE_109, 21, 21)
connect _WIRE_108.u, _T_1509
node _T_1510 = bits(_WIRE_109, 41, 22)
connect _WIRE_108.ppn, _T_1510
wire _WIRE_110 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_111 : UInt<42>
connect _WIRE_111, sectored_entries[0][3].data[3]
node _T_1511 = bits(_WIRE_111, 0, 0)
connect _WIRE_110.fragmented_superpage, _T_1511
node _T_1512 = bits(_WIRE_111, 1, 1)
connect _WIRE_110.c, _T_1512
node _T_1513 = bits(_WIRE_111, 2, 2)
connect _WIRE_110.eff, _T_1513
node _T_1514 = bits(_WIRE_111, 3, 3)
connect _WIRE_110.paa, _T_1514
node _T_1515 = bits(_WIRE_111, 4, 4)
connect _WIRE_110.pal, _T_1515
node _T_1516 = bits(_WIRE_111, 5, 5)
connect _WIRE_110.ppp, _T_1516
node _T_1517 = bits(_WIRE_111, 6, 6)
connect _WIRE_110.pr, _T_1517
node _T_1518 = bits(_WIRE_111, 7, 7)
connect _WIRE_110.px, _T_1518
node _T_1519 = bits(_WIRE_111, 8, 8)
connect _WIRE_110.pw, _T_1519
node _T_1520 = bits(_WIRE_111, 9, 9)
connect _WIRE_110.hr, _T_1520
node _T_1521 = bits(_WIRE_111, 10, 10)
connect _WIRE_110.hx, _T_1521
node _T_1522 = bits(_WIRE_111, 11, 11)
connect _WIRE_110.hw, _T_1522
node _T_1523 = bits(_WIRE_111, 12, 12)
connect _WIRE_110.sr, _T_1523
node _T_1524 = bits(_WIRE_111, 13, 13)
connect _WIRE_110.sx, _T_1524
node _T_1525 = bits(_WIRE_111, 14, 14)
connect _WIRE_110.sw, _T_1525
node _T_1526 = bits(_WIRE_111, 15, 15)
connect _WIRE_110.gf, _T_1526
node _T_1527 = bits(_WIRE_111, 16, 16)
connect _WIRE_110.pf, _T_1527
node _T_1528 = bits(_WIRE_111, 17, 17)
connect _WIRE_110.ae_stage2, _T_1528
node _T_1529 = bits(_WIRE_111, 18, 18)
connect _WIRE_110.ae_final, _T_1529
node _T_1530 = bits(_WIRE_111, 19, 19)
connect _WIRE_110.ae_ptw, _T_1530
node _T_1531 = bits(_WIRE_111, 20, 20)
connect _WIRE_110.g, _T_1531
node _T_1532 = bits(_WIRE_111, 21, 21)
connect _WIRE_110.u, _T_1532
node _T_1533 = bits(_WIRE_111, 41, 22)
connect _WIRE_110.ppn, _T_1533
node _T_1534 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1535 = and(_T_1534, _WIRE_104.fragmented_superpage)
when _T_1535 :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
node _T_1536 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1537 = and(_T_1536, _WIRE_106.fragmented_superpage)
when _T_1537 :
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
node _T_1538 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1539 = and(_T_1538, _WIRE_108.fragmented_superpage)
when _T_1539 :
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
node _T_1540 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1541 = and(_T_1540, _WIRE_110.fragmented_superpage)
when _T_1541 :
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
else :
node _T_1542 = eq(hg_3, UInt<1>(0h0))
node _T_1543 = and(_T_1542, io.sfence.bits.rs2)
when _T_1543 :
wire _WIRE_112 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_113 : UInt<42>
connect _WIRE_113, sectored_entries[0][3].data[0]
node _T_1544 = bits(_WIRE_113, 0, 0)
connect _WIRE_112.fragmented_superpage, _T_1544
node _T_1545 = bits(_WIRE_113, 1, 1)
connect _WIRE_112.c, _T_1545
node _T_1546 = bits(_WIRE_113, 2, 2)
connect _WIRE_112.eff, _T_1546
node _T_1547 = bits(_WIRE_113, 3, 3)
connect _WIRE_112.paa, _T_1547
node _T_1548 = bits(_WIRE_113, 4, 4)
connect _WIRE_112.pal, _T_1548
node _T_1549 = bits(_WIRE_113, 5, 5)
connect _WIRE_112.ppp, _T_1549
node _T_1550 = bits(_WIRE_113, 6, 6)
connect _WIRE_112.pr, _T_1550
node _T_1551 = bits(_WIRE_113, 7, 7)
connect _WIRE_112.px, _T_1551
node _T_1552 = bits(_WIRE_113, 8, 8)
connect _WIRE_112.pw, _T_1552
node _T_1553 = bits(_WIRE_113, 9, 9)
connect _WIRE_112.hr, _T_1553
node _T_1554 = bits(_WIRE_113, 10, 10)
connect _WIRE_112.hx, _T_1554
node _T_1555 = bits(_WIRE_113, 11, 11)
connect _WIRE_112.hw, _T_1555
node _T_1556 = bits(_WIRE_113, 12, 12)
connect _WIRE_112.sr, _T_1556
node _T_1557 = bits(_WIRE_113, 13, 13)
connect _WIRE_112.sx, _T_1557
node _T_1558 = bits(_WIRE_113, 14, 14)
connect _WIRE_112.sw, _T_1558
node _T_1559 = bits(_WIRE_113, 15, 15)
connect _WIRE_112.gf, _T_1559
node _T_1560 = bits(_WIRE_113, 16, 16)
connect _WIRE_112.pf, _T_1560
node _T_1561 = bits(_WIRE_113, 17, 17)
connect _WIRE_112.ae_stage2, _T_1561
node _T_1562 = bits(_WIRE_113, 18, 18)
connect _WIRE_112.ae_final, _T_1562
node _T_1563 = bits(_WIRE_113, 19, 19)
connect _WIRE_112.ae_ptw, _T_1563
node _T_1564 = bits(_WIRE_113, 20, 20)
connect _WIRE_112.g, _T_1564
node _T_1565 = bits(_WIRE_113, 21, 21)
connect _WIRE_112.u, _T_1565
node _T_1566 = bits(_WIRE_113, 41, 22)
connect _WIRE_112.ppn, _T_1566
wire _WIRE_114 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_115 : UInt<42>
connect _WIRE_115, sectored_entries[0][3].data[1]
node _T_1567 = bits(_WIRE_115, 0, 0)
connect _WIRE_114.fragmented_superpage, _T_1567
node _T_1568 = bits(_WIRE_115, 1, 1)
connect _WIRE_114.c, _T_1568
node _T_1569 = bits(_WIRE_115, 2, 2)
connect _WIRE_114.eff, _T_1569
node _T_1570 = bits(_WIRE_115, 3, 3)
connect _WIRE_114.paa, _T_1570
node _T_1571 = bits(_WIRE_115, 4, 4)
connect _WIRE_114.pal, _T_1571
node _T_1572 = bits(_WIRE_115, 5, 5)
connect _WIRE_114.ppp, _T_1572
node _T_1573 = bits(_WIRE_115, 6, 6)
connect _WIRE_114.pr, _T_1573
node _T_1574 = bits(_WIRE_115, 7, 7)
connect _WIRE_114.px, _T_1574
node _T_1575 = bits(_WIRE_115, 8, 8)
connect _WIRE_114.pw, _T_1575
node _T_1576 = bits(_WIRE_115, 9, 9)
connect _WIRE_114.hr, _T_1576
node _T_1577 = bits(_WIRE_115, 10, 10)
connect _WIRE_114.hx, _T_1577
node _T_1578 = bits(_WIRE_115, 11, 11)
connect _WIRE_114.hw, _T_1578
node _T_1579 = bits(_WIRE_115, 12, 12)
connect _WIRE_114.sr, _T_1579
node _T_1580 = bits(_WIRE_115, 13, 13)
connect _WIRE_114.sx, _T_1580
node _T_1581 = bits(_WIRE_115, 14, 14)
connect _WIRE_114.sw, _T_1581
node _T_1582 = bits(_WIRE_115, 15, 15)
connect _WIRE_114.gf, _T_1582
node _T_1583 = bits(_WIRE_115, 16, 16)
connect _WIRE_114.pf, _T_1583
node _T_1584 = bits(_WIRE_115, 17, 17)
connect _WIRE_114.ae_stage2, _T_1584
node _T_1585 = bits(_WIRE_115, 18, 18)
connect _WIRE_114.ae_final, _T_1585
node _T_1586 = bits(_WIRE_115, 19, 19)
connect _WIRE_114.ae_ptw, _T_1586
node _T_1587 = bits(_WIRE_115, 20, 20)
connect _WIRE_114.g, _T_1587
node _T_1588 = bits(_WIRE_115, 21, 21)
connect _WIRE_114.u, _T_1588
node _T_1589 = bits(_WIRE_115, 41, 22)
connect _WIRE_114.ppn, _T_1589
wire _WIRE_116 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_117 : UInt<42>
connect _WIRE_117, sectored_entries[0][3].data[2]
node _T_1590 = bits(_WIRE_117, 0, 0)
connect _WIRE_116.fragmented_superpage, _T_1590
node _T_1591 = bits(_WIRE_117, 1, 1)
connect _WIRE_116.c, _T_1591
node _T_1592 = bits(_WIRE_117, 2, 2)
connect _WIRE_116.eff, _T_1592
node _T_1593 = bits(_WIRE_117, 3, 3)
connect _WIRE_116.paa, _T_1593
node _T_1594 = bits(_WIRE_117, 4, 4)
connect _WIRE_116.pal, _T_1594
node _T_1595 = bits(_WIRE_117, 5, 5)
connect _WIRE_116.ppp, _T_1595
node _T_1596 = bits(_WIRE_117, 6, 6)
connect _WIRE_116.pr, _T_1596
node _T_1597 = bits(_WIRE_117, 7, 7)
connect _WIRE_116.px, _T_1597
node _T_1598 = bits(_WIRE_117, 8, 8)
connect _WIRE_116.pw, _T_1598
node _T_1599 = bits(_WIRE_117, 9, 9)
connect _WIRE_116.hr, _T_1599
node _T_1600 = bits(_WIRE_117, 10, 10)
connect _WIRE_116.hx, _T_1600
node _T_1601 = bits(_WIRE_117, 11, 11)
connect _WIRE_116.hw, _T_1601
node _T_1602 = bits(_WIRE_117, 12, 12)
connect _WIRE_116.sr, _T_1602
node _T_1603 = bits(_WIRE_117, 13, 13)
connect _WIRE_116.sx, _T_1603
node _T_1604 = bits(_WIRE_117, 14, 14)
connect _WIRE_116.sw, _T_1604
node _T_1605 = bits(_WIRE_117, 15, 15)
connect _WIRE_116.gf, _T_1605
node _T_1606 = bits(_WIRE_117, 16, 16)
connect _WIRE_116.pf, _T_1606
node _T_1607 = bits(_WIRE_117, 17, 17)
connect _WIRE_116.ae_stage2, _T_1607
node _T_1608 = bits(_WIRE_117, 18, 18)
connect _WIRE_116.ae_final, _T_1608
node _T_1609 = bits(_WIRE_117, 19, 19)
connect _WIRE_116.ae_ptw, _T_1609
node _T_1610 = bits(_WIRE_117, 20, 20)
connect _WIRE_116.g, _T_1610
node _T_1611 = bits(_WIRE_117, 21, 21)
connect _WIRE_116.u, _T_1611
node _T_1612 = bits(_WIRE_117, 41, 22)
connect _WIRE_116.ppn, _T_1612
wire _WIRE_118 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_119 : UInt<42>
connect _WIRE_119, sectored_entries[0][3].data[3]
node _T_1613 = bits(_WIRE_119, 0, 0)
connect _WIRE_118.fragmented_superpage, _T_1613
node _T_1614 = bits(_WIRE_119, 1, 1)
connect _WIRE_118.c, _T_1614
node _T_1615 = bits(_WIRE_119, 2, 2)
connect _WIRE_118.eff, _T_1615
node _T_1616 = bits(_WIRE_119, 3, 3)
connect _WIRE_118.paa, _T_1616
node _T_1617 = bits(_WIRE_119, 4, 4)
connect _WIRE_118.pal, _T_1617
node _T_1618 = bits(_WIRE_119, 5, 5)
connect _WIRE_118.ppp, _T_1618
node _T_1619 = bits(_WIRE_119, 6, 6)
connect _WIRE_118.pr, _T_1619
node _T_1620 = bits(_WIRE_119, 7, 7)
connect _WIRE_118.px, _T_1620
node _T_1621 = bits(_WIRE_119, 8, 8)
connect _WIRE_118.pw, _T_1621
node _T_1622 = bits(_WIRE_119, 9, 9)
connect _WIRE_118.hr, _T_1622
node _T_1623 = bits(_WIRE_119, 10, 10)
connect _WIRE_118.hx, _T_1623
node _T_1624 = bits(_WIRE_119, 11, 11)
connect _WIRE_118.hw, _T_1624
node _T_1625 = bits(_WIRE_119, 12, 12)
connect _WIRE_118.sr, _T_1625
node _T_1626 = bits(_WIRE_119, 13, 13)
connect _WIRE_118.sx, _T_1626
node _T_1627 = bits(_WIRE_119, 14, 14)
connect _WIRE_118.sw, _T_1627
node _T_1628 = bits(_WIRE_119, 15, 15)
connect _WIRE_118.gf, _T_1628
node _T_1629 = bits(_WIRE_119, 16, 16)
connect _WIRE_118.pf, _T_1629
node _T_1630 = bits(_WIRE_119, 17, 17)
connect _WIRE_118.ae_stage2, _T_1630
node _T_1631 = bits(_WIRE_119, 18, 18)
connect _WIRE_118.ae_final, _T_1631
node _T_1632 = bits(_WIRE_119, 19, 19)
connect _WIRE_118.ae_ptw, _T_1632
node _T_1633 = bits(_WIRE_119, 20, 20)
connect _WIRE_118.g, _T_1633
node _T_1634 = bits(_WIRE_119, 21, 21)
connect _WIRE_118.u, _T_1634
node _T_1635 = bits(_WIRE_119, 41, 22)
connect _WIRE_118.ppn, _T_1635
node _T_1636 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1637 = eq(_WIRE_112.g, UInt<1>(0h0))
node _T_1638 = and(_T_1636, _T_1637)
when _T_1638 :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
node _T_1639 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1640 = eq(_WIRE_114.g, UInt<1>(0h0))
node _T_1641 = and(_T_1639, _T_1640)
when _T_1641 :
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
node _T_1642 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1643 = eq(_WIRE_116.g, UInt<1>(0h0))
node _T_1644 = and(_T_1642, _T_1643)
when _T_1644 :
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
node _T_1645 = eq(sectored_entries[0][3].tag_v, hv_3)
node _T_1646 = eq(_WIRE_118.g, UInt<1>(0h0))
node _T_1647 = and(_T_1645, _T_1646)
when _T_1647 :
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
else :
node _T_1648 = or(hv_3, hg_3)
wire _WIRE_120 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_121 : UInt<42>
connect _WIRE_121, sectored_entries[0][3].data[0]
node _T_1649 = bits(_WIRE_121, 0, 0)
connect _WIRE_120.fragmented_superpage, _T_1649
node _T_1650 = bits(_WIRE_121, 1, 1)
connect _WIRE_120.c, _T_1650
node _T_1651 = bits(_WIRE_121, 2, 2)
connect _WIRE_120.eff, _T_1651
node _T_1652 = bits(_WIRE_121, 3, 3)
connect _WIRE_120.paa, _T_1652
node _T_1653 = bits(_WIRE_121, 4, 4)
connect _WIRE_120.pal, _T_1653
node _T_1654 = bits(_WIRE_121, 5, 5)
connect _WIRE_120.ppp, _T_1654
node _T_1655 = bits(_WIRE_121, 6, 6)
connect _WIRE_120.pr, _T_1655
node _T_1656 = bits(_WIRE_121, 7, 7)
connect _WIRE_120.px, _T_1656
node _T_1657 = bits(_WIRE_121, 8, 8)
connect _WIRE_120.pw, _T_1657
node _T_1658 = bits(_WIRE_121, 9, 9)
connect _WIRE_120.hr, _T_1658
node _T_1659 = bits(_WIRE_121, 10, 10)
connect _WIRE_120.hx, _T_1659
node _T_1660 = bits(_WIRE_121, 11, 11)
connect _WIRE_120.hw, _T_1660
node _T_1661 = bits(_WIRE_121, 12, 12)
connect _WIRE_120.sr, _T_1661
node _T_1662 = bits(_WIRE_121, 13, 13)
connect _WIRE_120.sx, _T_1662
node _T_1663 = bits(_WIRE_121, 14, 14)
connect _WIRE_120.sw, _T_1663
node _T_1664 = bits(_WIRE_121, 15, 15)
connect _WIRE_120.gf, _T_1664
node _T_1665 = bits(_WIRE_121, 16, 16)
connect _WIRE_120.pf, _T_1665
node _T_1666 = bits(_WIRE_121, 17, 17)
connect _WIRE_120.ae_stage2, _T_1666
node _T_1667 = bits(_WIRE_121, 18, 18)
connect _WIRE_120.ae_final, _T_1667
node _T_1668 = bits(_WIRE_121, 19, 19)
connect _WIRE_120.ae_ptw, _T_1668
node _T_1669 = bits(_WIRE_121, 20, 20)
connect _WIRE_120.g, _T_1669
node _T_1670 = bits(_WIRE_121, 21, 21)
connect _WIRE_120.u, _T_1670
node _T_1671 = bits(_WIRE_121, 41, 22)
connect _WIRE_120.ppn, _T_1671
wire _WIRE_122 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_123 : UInt<42>
connect _WIRE_123, sectored_entries[0][3].data[1]
node _T_1672 = bits(_WIRE_123, 0, 0)
connect _WIRE_122.fragmented_superpage, _T_1672
node _T_1673 = bits(_WIRE_123, 1, 1)
connect _WIRE_122.c, _T_1673
node _T_1674 = bits(_WIRE_123, 2, 2)
connect _WIRE_122.eff, _T_1674
node _T_1675 = bits(_WIRE_123, 3, 3)
connect _WIRE_122.paa, _T_1675
node _T_1676 = bits(_WIRE_123, 4, 4)
connect _WIRE_122.pal, _T_1676
node _T_1677 = bits(_WIRE_123, 5, 5)
connect _WIRE_122.ppp, _T_1677
node _T_1678 = bits(_WIRE_123, 6, 6)
connect _WIRE_122.pr, _T_1678
node _T_1679 = bits(_WIRE_123, 7, 7)
connect _WIRE_122.px, _T_1679
node _T_1680 = bits(_WIRE_123, 8, 8)
connect _WIRE_122.pw, _T_1680
node _T_1681 = bits(_WIRE_123, 9, 9)
connect _WIRE_122.hr, _T_1681
node _T_1682 = bits(_WIRE_123, 10, 10)
connect _WIRE_122.hx, _T_1682
node _T_1683 = bits(_WIRE_123, 11, 11)
connect _WIRE_122.hw, _T_1683
node _T_1684 = bits(_WIRE_123, 12, 12)
connect _WIRE_122.sr, _T_1684
node _T_1685 = bits(_WIRE_123, 13, 13)
connect _WIRE_122.sx, _T_1685
node _T_1686 = bits(_WIRE_123, 14, 14)
connect _WIRE_122.sw, _T_1686
node _T_1687 = bits(_WIRE_123, 15, 15)
connect _WIRE_122.gf, _T_1687
node _T_1688 = bits(_WIRE_123, 16, 16)
connect _WIRE_122.pf, _T_1688
node _T_1689 = bits(_WIRE_123, 17, 17)
connect _WIRE_122.ae_stage2, _T_1689
node _T_1690 = bits(_WIRE_123, 18, 18)
connect _WIRE_122.ae_final, _T_1690
node _T_1691 = bits(_WIRE_123, 19, 19)
connect _WIRE_122.ae_ptw, _T_1691
node _T_1692 = bits(_WIRE_123, 20, 20)
connect _WIRE_122.g, _T_1692
node _T_1693 = bits(_WIRE_123, 21, 21)
connect _WIRE_122.u, _T_1693
node _T_1694 = bits(_WIRE_123, 41, 22)
connect _WIRE_122.ppn, _T_1694
wire _WIRE_124 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_125 : UInt<42>
connect _WIRE_125, sectored_entries[0][3].data[2]
node _T_1695 = bits(_WIRE_125, 0, 0)
connect _WIRE_124.fragmented_superpage, _T_1695
node _T_1696 = bits(_WIRE_125, 1, 1)
connect _WIRE_124.c, _T_1696
node _T_1697 = bits(_WIRE_125, 2, 2)
connect _WIRE_124.eff, _T_1697
node _T_1698 = bits(_WIRE_125, 3, 3)
connect _WIRE_124.paa, _T_1698
node _T_1699 = bits(_WIRE_125, 4, 4)
connect _WIRE_124.pal, _T_1699
node _T_1700 = bits(_WIRE_125, 5, 5)
connect _WIRE_124.ppp, _T_1700
node _T_1701 = bits(_WIRE_125, 6, 6)
connect _WIRE_124.pr, _T_1701
node _T_1702 = bits(_WIRE_125, 7, 7)
connect _WIRE_124.px, _T_1702
node _T_1703 = bits(_WIRE_125, 8, 8)
connect _WIRE_124.pw, _T_1703
node _T_1704 = bits(_WIRE_125, 9, 9)
connect _WIRE_124.hr, _T_1704
node _T_1705 = bits(_WIRE_125, 10, 10)
connect _WIRE_124.hx, _T_1705
node _T_1706 = bits(_WIRE_125, 11, 11)
connect _WIRE_124.hw, _T_1706
node _T_1707 = bits(_WIRE_125, 12, 12)
connect _WIRE_124.sr, _T_1707
node _T_1708 = bits(_WIRE_125, 13, 13)
connect _WIRE_124.sx, _T_1708
node _T_1709 = bits(_WIRE_125, 14, 14)
connect _WIRE_124.sw, _T_1709
node _T_1710 = bits(_WIRE_125, 15, 15)
connect _WIRE_124.gf, _T_1710
node _T_1711 = bits(_WIRE_125, 16, 16)
connect _WIRE_124.pf, _T_1711
node _T_1712 = bits(_WIRE_125, 17, 17)
connect _WIRE_124.ae_stage2, _T_1712
node _T_1713 = bits(_WIRE_125, 18, 18)
connect _WIRE_124.ae_final, _T_1713
node _T_1714 = bits(_WIRE_125, 19, 19)
connect _WIRE_124.ae_ptw, _T_1714
node _T_1715 = bits(_WIRE_125, 20, 20)
connect _WIRE_124.g, _T_1715
node _T_1716 = bits(_WIRE_125, 21, 21)
connect _WIRE_124.u, _T_1716
node _T_1717 = bits(_WIRE_125, 41, 22)
connect _WIRE_124.ppn, _T_1717
wire _WIRE_126 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_127 : UInt<42>
connect _WIRE_127, sectored_entries[0][3].data[3]
node _T_1718 = bits(_WIRE_127, 0, 0)
connect _WIRE_126.fragmented_superpage, _T_1718
node _T_1719 = bits(_WIRE_127, 1, 1)
connect _WIRE_126.c, _T_1719
node _T_1720 = bits(_WIRE_127, 2, 2)
connect _WIRE_126.eff, _T_1720
node _T_1721 = bits(_WIRE_127, 3, 3)
connect _WIRE_126.paa, _T_1721
node _T_1722 = bits(_WIRE_127, 4, 4)
connect _WIRE_126.pal, _T_1722
node _T_1723 = bits(_WIRE_127, 5, 5)
connect _WIRE_126.ppp, _T_1723
node _T_1724 = bits(_WIRE_127, 6, 6)
connect _WIRE_126.pr, _T_1724
node _T_1725 = bits(_WIRE_127, 7, 7)
connect _WIRE_126.px, _T_1725
node _T_1726 = bits(_WIRE_127, 8, 8)
connect _WIRE_126.pw, _T_1726
node _T_1727 = bits(_WIRE_127, 9, 9)
connect _WIRE_126.hr, _T_1727
node _T_1728 = bits(_WIRE_127, 10, 10)
connect _WIRE_126.hx, _T_1728
node _T_1729 = bits(_WIRE_127, 11, 11)
connect _WIRE_126.hw, _T_1729
node _T_1730 = bits(_WIRE_127, 12, 12)
connect _WIRE_126.sr, _T_1730
node _T_1731 = bits(_WIRE_127, 13, 13)
connect _WIRE_126.sx, _T_1731
node _T_1732 = bits(_WIRE_127, 14, 14)
connect _WIRE_126.sw, _T_1732
node _T_1733 = bits(_WIRE_127, 15, 15)
connect _WIRE_126.gf, _T_1733
node _T_1734 = bits(_WIRE_127, 16, 16)
connect _WIRE_126.pf, _T_1734
node _T_1735 = bits(_WIRE_127, 17, 17)
connect _WIRE_126.ae_stage2, _T_1735
node _T_1736 = bits(_WIRE_127, 18, 18)
connect _WIRE_126.ae_final, _T_1736
node _T_1737 = bits(_WIRE_127, 19, 19)
connect _WIRE_126.ae_ptw, _T_1737
node _T_1738 = bits(_WIRE_127, 20, 20)
connect _WIRE_126.g, _T_1738
node _T_1739 = bits(_WIRE_127, 21, 21)
connect _WIRE_126.u, _T_1739
node _T_1740 = bits(_WIRE_127, 41, 22)
connect _WIRE_126.ppn, _T_1740
node _T_1741 = eq(sectored_entries[0][3].tag_v, _T_1648)
when _T_1741 :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
node _T_1742 = eq(sectored_entries[0][3].tag_v, _T_1648)
when _T_1742 :
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
node _T_1743 = eq(sectored_entries[0][3].tag_v, _T_1648)
when _T_1743 :
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
node _T_1744 = eq(sectored_entries[0][3].tag_v, _T_1648)
when _T_1744 :
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
node hv_4 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_4 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_1745 = eq(hg_4, UInt<1>(0h0))
node _T_1746 = and(_T_1745, io.sfence.bits.rs1)
when _T_1746 :
node _T_1747 = xor(sectored_entries[0][4].tag_vpn, vpn)
node _T_1748 = shr(_T_1747, 2)
node _T_1749 = eq(_T_1748, UInt<1>(0h0))
node _T_1750 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1751 = and(_T_1749, _T_1750)
when _T_1751 :
wire _WIRE_128 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_129 : UInt<42>
connect _WIRE_129, sectored_entries[0][4].data[0]
node _T_1752 = bits(_WIRE_129, 0, 0)
connect _WIRE_128.fragmented_superpage, _T_1752
node _T_1753 = bits(_WIRE_129, 1, 1)
connect _WIRE_128.c, _T_1753
node _T_1754 = bits(_WIRE_129, 2, 2)
connect _WIRE_128.eff, _T_1754
node _T_1755 = bits(_WIRE_129, 3, 3)
connect _WIRE_128.paa, _T_1755
node _T_1756 = bits(_WIRE_129, 4, 4)
connect _WIRE_128.pal, _T_1756
node _T_1757 = bits(_WIRE_129, 5, 5)
connect _WIRE_128.ppp, _T_1757
node _T_1758 = bits(_WIRE_129, 6, 6)
connect _WIRE_128.pr, _T_1758
node _T_1759 = bits(_WIRE_129, 7, 7)
connect _WIRE_128.px, _T_1759
node _T_1760 = bits(_WIRE_129, 8, 8)
connect _WIRE_128.pw, _T_1760
node _T_1761 = bits(_WIRE_129, 9, 9)
connect _WIRE_128.hr, _T_1761
node _T_1762 = bits(_WIRE_129, 10, 10)
connect _WIRE_128.hx, _T_1762
node _T_1763 = bits(_WIRE_129, 11, 11)
connect _WIRE_128.hw, _T_1763
node _T_1764 = bits(_WIRE_129, 12, 12)
connect _WIRE_128.sr, _T_1764
node _T_1765 = bits(_WIRE_129, 13, 13)
connect _WIRE_128.sx, _T_1765
node _T_1766 = bits(_WIRE_129, 14, 14)
connect _WIRE_128.sw, _T_1766
node _T_1767 = bits(_WIRE_129, 15, 15)
connect _WIRE_128.gf, _T_1767
node _T_1768 = bits(_WIRE_129, 16, 16)
connect _WIRE_128.pf, _T_1768
node _T_1769 = bits(_WIRE_129, 17, 17)
connect _WIRE_128.ae_stage2, _T_1769
node _T_1770 = bits(_WIRE_129, 18, 18)
connect _WIRE_128.ae_final, _T_1770
node _T_1771 = bits(_WIRE_129, 19, 19)
connect _WIRE_128.ae_ptw, _T_1771
node _T_1772 = bits(_WIRE_129, 20, 20)
connect _WIRE_128.g, _T_1772
node _T_1773 = bits(_WIRE_129, 21, 21)
connect _WIRE_128.u, _T_1773
node _T_1774 = bits(_WIRE_129, 41, 22)
connect _WIRE_128.ppn, _T_1774
wire _WIRE_130 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_131 : UInt<42>
connect _WIRE_131, sectored_entries[0][4].data[1]
node _T_1775 = bits(_WIRE_131, 0, 0)
connect _WIRE_130.fragmented_superpage, _T_1775
node _T_1776 = bits(_WIRE_131, 1, 1)
connect _WIRE_130.c, _T_1776
node _T_1777 = bits(_WIRE_131, 2, 2)
connect _WIRE_130.eff, _T_1777
node _T_1778 = bits(_WIRE_131, 3, 3)
connect _WIRE_130.paa, _T_1778
node _T_1779 = bits(_WIRE_131, 4, 4)
connect _WIRE_130.pal, _T_1779
node _T_1780 = bits(_WIRE_131, 5, 5)
connect _WIRE_130.ppp, _T_1780
node _T_1781 = bits(_WIRE_131, 6, 6)
connect _WIRE_130.pr, _T_1781
node _T_1782 = bits(_WIRE_131, 7, 7)
connect _WIRE_130.px, _T_1782
node _T_1783 = bits(_WIRE_131, 8, 8)
connect _WIRE_130.pw, _T_1783
node _T_1784 = bits(_WIRE_131, 9, 9)
connect _WIRE_130.hr, _T_1784
node _T_1785 = bits(_WIRE_131, 10, 10)
connect _WIRE_130.hx, _T_1785
node _T_1786 = bits(_WIRE_131, 11, 11)
connect _WIRE_130.hw, _T_1786
node _T_1787 = bits(_WIRE_131, 12, 12)
connect _WIRE_130.sr, _T_1787
node _T_1788 = bits(_WIRE_131, 13, 13)
connect _WIRE_130.sx, _T_1788
node _T_1789 = bits(_WIRE_131, 14, 14)
connect _WIRE_130.sw, _T_1789
node _T_1790 = bits(_WIRE_131, 15, 15)
connect _WIRE_130.gf, _T_1790
node _T_1791 = bits(_WIRE_131, 16, 16)
connect _WIRE_130.pf, _T_1791
node _T_1792 = bits(_WIRE_131, 17, 17)
connect _WIRE_130.ae_stage2, _T_1792
node _T_1793 = bits(_WIRE_131, 18, 18)
connect _WIRE_130.ae_final, _T_1793
node _T_1794 = bits(_WIRE_131, 19, 19)
connect _WIRE_130.ae_ptw, _T_1794
node _T_1795 = bits(_WIRE_131, 20, 20)
connect _WIRE_130.g, _T_1795
node _T_1796 = bits(_WIRE_131, 21, 21)
connect _WIRE_130.u, _T_1796
node _T_1797 = bits(_WIRE_131, 41, 22)
connect _WIRE_130.ppn, _T_1797
wire _WIRE_132 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_133 : UInt<42>
connect _WIRE_133, sectored_entries[0][4].data[2]
node _T_1798 = bits(_WIRE_133, 0, 0)
connect _WIRE_132.fragmented_superpage, _T_1798
node _T_1799 = bits(_WIRE_133, 1, 1)
connect _WIRE_132.c, _T_1799
node _T_1800 = bits(_WIRE_133, 2, 2)
connect _WIRE_132.eff, _T_1800
node _T_1801 = bits(_WIRE_133, 3, 3)
connect _WIRE_132.paa, _T_1801
node _T_1802 = bits(_WIRE_133, 4, 4)
connect _WIRE_132.pal, _T_1802
node _T_1803 = bits(_WIRE_133, 5, 5)
connect _WIRE_132.ppp, _T_1803
node _T_1804 = bits(_WIRE_133, 6, 6)
connect _WIRE_132.pr, _T_1804
node _T_1805 = bits(_WIRE_133, 7, 7)
connect _WIRE_132.px, _T_1805
node _T_1806 = bits(_WIRE_133, 8, 8)
connect _WIRE_132.pw, _T_1806
node _T_1807 = bits(_WIRE_133, 9, 9)
connect _WIRE_132.hr, _T_1807
node _T_1808 = bits(_WIRE_133, 10, 10)
connect _WIRE_132.hx, _T_1808
node _T_1809 = bits(_WIRE_133, 11, 11)
connect _WIRE_132.hw, _T_1809
node _T_1810 = bits(_WIRE_133, 12, 12)
connect _WIRE_132.sr, _T_1810
node _T_1811 = bits(_WIRE_133, 13, 13)
connect _WIRE_132.sx, _T_1811
node _T_1812 = bits(_WIRE_133, 14, 14)
connect _WIRE_132.sw, _T_1812
node _T_1813 = bits(_WIRE_133, 15, 15)
connect _WIRE_132.gf, _T_1813
node _T_1814 = bits(_WIRE_133, 16, 16)
connect _WIRE_132.pf, _T_1814
node _T_1815 = bits(_WIRE_133, 17, 17)
connect _WIRE_132.ae_stage2, _T_1815
node _T_1816 = bits(_WIRE_133, 18, 18)
connect _WIRE_132.ae_final, _T_1816
node _T_1817 = bits(_WIRE_133, 19, 19)
connect _WIRE_132.ae_ptw, _T_1817
node _T_1818 = bits(_WIRE_133, 20, 20)
connect _WIRE_132.g, _T_1818
node _T_1819 = bits(_WIRE_133, 21, 21)
connect _WIRE_132.u, _T_1819
node _T_1820 = bits(_WIRE_133, 41, 22)
connect _WIRE_132.ppn, _T_1820
wire _WIRE_134 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_135 : UInt<42>
connect _WIRE_135, sectored_entries[0][4].data[3]
node _T_1821 = bits(_WIRE_135, 0, 0)
connect _WIRE_134.fragmented_superpage, _T_1821
node _T_1822 = bits(_WIRE_135, 1, 1)
connect _WIRE_134.c, _T_1822
node _T_1823 = bits(_WIRE_135, 2, 2)
connect _WIRE_134.eff, _T_1823
node _T_1824 = bits(_WIRE_135, 3, 3)
connect _WIRE_134.paa, _T_1824
node _T_1825 = bits(_WIRE_135, 4, 4)
connect _WIRE_134.pal, _T_1825
node _T_1826 = bits(_WIRE_135, 5, 5)
connect _WIRE_134.ppp, _T_1826
node _T_1827 = bits(_WIRE_135, 6, 6)
connect _WIRE_134.pr, _T_1827
node _T_1828 = bits(_WIRE_135, 7, 7)
connect _WIRE_134.px, _T_1828
node _T_1829 = bits(_WIRE_135, 8, 8)
connect _WIRE_134.pw, _T_1829
node _T_1830 = bits(_WIRE_135, 9, 9)
connect _WIRE_134.hr, _T_1830
node _T_1831 = bits(_WIRE_135, 10, 10)
connect _WIRE_134.hx, _T_1831
node _T_1832 = bits(_WIRE_135, 11, 11)
connect _WIRE_134.hw, _T_1832
node _T_1833 = bits(_WIRE_135, 12, 12)
connect _WIRE_134.sr, _T_1833
node _T_1834 = bits(_WIRE_135, 13, 13)
connect _WIRE_134.sx, _T_1834
node _T_1835 = bits(_WIRE_135, 14, 14)
connect _WIRE_134.sw, _T_1835
node _T_1836 = bits(_WIRE_135, 15, 15)
connect _WIRE_134.gf, _T_1836
node _T_1837 = bits(_WIRE_135, 16, 16)
connect _WIRE_134.pf, _T_1837
node _T_1838 = bits(_WIRE_135, 17, 17)
connect _WIRE_134.ae_stage2, _T_1838
node _T_1839 = bits(_WIRE_135, 18, 18)
connect _WIRE_134.ae_final, _T_1839
node _T_1840 = bits(_WIRE_135, 19, 19)
connect _WIRE_134.ae_ptw, _T_1840
node _T_1841 = bits(_WIRE_135, 20, 20)
connect _WIRE_134.g, _T_1841
node _T_1842 = bits(_WIRE_135, 21, 21)
connect _WIRE_134.u, _T_1842
node _T_1843 = bits(_WIRE_135, 41, 22)
connect _WIRE_134.ppn, _T_1843
node _T_1844 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1845 = bits(vpn, 1, 0)
node _T_1846 = eq(UInt<1>(0h0), _T_1845)
node _T_1847 = and(_T_1844, _T_1846)
when _T_1847 :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
node _T_1848 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1849 = bits(vpn, 1, 0)
node _T_1850 = eq(UInt<1>(0h1), _T_1849)
node _T_1851 = and(_T_1848, _T_1850)
when _T_1851 :
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
node _T_1852 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1853 = bits(vpn, 1, 0)
node _T_1854 = eq(UInt<2>(0h2), _T_1853)
node _T_1855 = and(_T_1852, _T_1854)
when _T_1855 :
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
node _T_1856 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1857 = bits(vpn, 1, 0)
node _T_1858 = eq(UInt<2>(0h3), _T_1857)
node _T_1859 = and(_T_1856, _T_1858)
when _T_1859 :
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
node _T_1860 = xor(sectored_entries[0][4].tag_vpn, vpn)
node _T_1861 = shr(_T_1860, 18)
node _T_1862 = eq(_T_1861, UInt<1>(0h0))
when _T_1862 :
wire _WIRE_136 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_137 : UInt<42>
connect _WIRE_137, sectored_entries[0][4].data[0]
node _T_1863 = bits(_WIRE_137, 0, 0)
connect _WIRE_136.fragmented_superpage, _T_1863
node _T_1864 = bits(_WIRE_137, 1, 1)
connect _WIRE_136.c, _T_1864
node _T_1865 = bits(_WIRE_137, 2, 2)
connect _WIRE_136.eff, _T_1865
node _T_1866 = bits(_WIRE_137, 3, 3)
connect _WIRE_136.paa, _T_1866
node _T_1867 = bits(_WIRE_137, 4, 4)
connect _WIRE_136.pal, _T_1867
node _T_1868 = bits(_WIRE_137, 5, 5)
connect _WIRE_136.ppp, _T_1868
node _T_1869 = bits(_WIRE_137, 6, 6)
connect _WIRE_136.pr, _T_1869
node _T_1870 = bits(_WIRE_137, 7, 7)
connect _WIRE_136.px, _T_1870
node _T_1871 = bits(_WIRE_137, 8, 8)
connect _WIRE_136.pw, _T_1871
node _T_1872 = bits(_WIRE_137, 9, 9)
connect _WIRE_136.hr, _T_1872
node _T_1873 = bits(_WIRE_137, 10, 10)
connect _WIRE_136.hx, _T_1873
node _T_1874 = bits(_WIRE_137, 11, 11)
connect _WIRE_136.hw, _T_1874
node _T_1875 = bits(_WIRE_137, 12, 12)
connect _WIRE_136.sr, _T_1875
node _T_1876 = bits(_WIRE_137, 13, 13)
connect _WIRE_136.sx, _T_1876
node _T_1877 = bits(_WIRE_137, 14, 14)
connect _WIRE_136.sw, _T_1877
node _T_1878 = bits(_WIRE_137, 15, 15)
connect _WIRE_136.gf, _T_1878
node _T_1879 = bits(_WIRE_137, 16, 16)
connect _WIRE_136.pf, _T_1879
node _T_1880 = bits(_WIRE_137, 17, 17)
connect _WIRE_136.ae_stage2, _T_1880
node _T_1881 = bits(_WIRE_137, 18, 18)
connect _WIRE_136.ae_final, _T_1881
node _T_1882 = bits(_WIRE_137, 19, 19)
connect _WIRE_136.ae_ptw, _T_1882
node _T_1883 = bits(_WIRE_137, 20, 20)
connect _WIRE_136.g, _T_1883
node _T_1884 = bits(_WIRE_137, 21, 21)
connect _WIRE_136.u, _T_1884
node _T_1885 = bits(_WIRE_137, 41, 22)
connect _WIRE_136.ppn, _T_1885
wire _WIRE_138 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_139 : UInt<42>
connect _WIRE_139, sectored_entries[0][4].data[1]
node _T_1886 = bits(_WIRE_139, 0, 0)
connect _WIRE_138.fragmented_superpage, _T_1886
node _T_1887 = bits(_WIRE_139, 1, 1)
connect _WIRE_138.c, _T_1887
node _T_1888 = bits(_WIRE_139, 2, 2)
connect _WIRE_138.eff, _T_1888
node _T_1889 = bits(_WIRE_139, 3, 3)
connect _WIRE_138.paa, _T_1889
node _T_1890 = bits(_WIRE_139, 4, 4)
connect _WIRE_138.pal, _T_1890
node _T_1891 = bits(_WIRE_139, 5, 5)
connect _WIRE_138.ppp, _T_1891
node _T_1892 = bits(_WIRE_139, 6, 6)
connect _WIRE_138.pr, _T_1892
node _T_1893 = bits(_WIRE_139, 7, 7)
connect _WIRE_138.px, _T_1893
node _T_1894 = bits(_WIRE_139, 8, 8)
connect _WIRE_138.pw, _T_1894
node _T_1895 = bits(_WIRE_139, 9, 9)
connect _WIRE_138.hr, _T_1895
node _T_1896 = bits(_WIRE_139, 10, 10)
connect _WIRE_138.hx, _T_1896
node _T_1897 = bits(_WIRE_139, 11, 11)
connect _WIRE_138.hw, _T_1897
node _T_1898 = bits(_WIRE_139, 12, 12)
connect _WIRE_138.sr, _T_1898
node _T_1899 = bits(_WIRE_139, 13, 13)
connect _WIRE_138.sx, _T_1899
node _T_1900 = bits(_WIRE_139, 14, 14)
connect _WIRE_138.sw, _T_1900
node _T_1901 = bits(_WIRE_139, 15, 15)
connect _WIRE_138.gf, _T_1901
node _T_1902 = bits(_WIRE_139, 16, 16)
connect _WIRE_138.pf, _T_1902
node _T_1903 = bits(_WIRE_139, 17, 17)
connect _WIRE_138.ae_stage2, _T_1903
node _T_1904 = bits(_WIRE_139, 18, 18)
connect _WIRE_138.ae_final, _T_1904
node _T_1905 = bits(_WIRE_139, 19, 19)
connect _WIRE_138.ae_ptw, _T_1905
node _T_1906 = bits(_WIRE_139, 20, 20)
connect _WIRE_138.g, _T_1906
node _T_1907 = bits(_WIRE_139, 21, 21)
connect _WIRE_138.u, _T_1907
node _T_1908 = bits(_WIRE_139, 41, 22)
connect _WIRE_138.ppn, _T_1908
wire _WIRE_140 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_141 : UInt<42>
connect _WIRE_141, sectored_entries[0][4].data[2]
node _T_1909 = bits(_WIRE_141, 0, 0)
connect _WIRE_140.fragmented_superpage, _T_1909
node _T_1910 = bits(_WIRE_141, 1, 1)
connect _WIRE_140.c, _T_1910
node _T_1911 = bits(_WIRE_141, 2, 2)
connect _WIRE_140.eff, _T_1911
node _T_1912 = bits(_WIRE_141, 3, 3)
connect _WIRE_140.paa, _T_1912
node _T_1913 = bits(_WIRE_141, 4, 4)
connect _WIRE_140.pal, _T_1913
node _T_1914 = bits(_WIRE_141, 5, 5)
connect _WIRE_140.ppp, _T_1914
node _T_1915 = bits(_WIRE_141, 6, 6)
connect _WIRE_140.pr, _T_1915
node _T_1916 = bits(_WIRE_141, 7, 7)
connect _WIRE_140.px, _T_1916
node _T_1917 = bits(_WIRE_141, 8, 8)
connect _WIRE_140.pw, _T_1917
node _T_1918 = bits(_WIRE_141, 9, 9)
connect _WIRE_140.hr, _T_1918
node _T_1919 = bits(_WIRE_141, 10, 10)
connect _WIRE_140.hx, _T_1919
node _T_1920 = bits(_WIRE_141, 11, 11)
connect _WIRE_140.hw, _T_1920
node _T_1921 = bits(_WIRE_141, 12, 12)
connect _WIRE_140.sr, _T_1921
node _T_1922 = bits(_WIRE_141, 13, 13)
connect _WIRE_140.sx, _T_1922
node _T_1923 = bits(_WIRE_141, 14, 14)
connect _WIRE_140.sw, _T_1923
node _T_1924 = bits(_WIRE_141, 15, 15)
connect _WIRE_140.gf, _T_1924
node _T_1925 = bits(_WIRE_141, 16, 16)
connect _WIRE_140.pf, _T_1925
node _T_1926 = bits(_WIRE_141, 17, 17)
connect _WIRE_140.ae_stage2, _T_1926
node _T_1927 = bits(_WIRE_141, 18, 18)
connect _WIRE_140.ae_final, _T_1927
node _T_1928 = bits(_WIRE_141, 19, 19)
connect _WIRE_140.ae_ptw, _T_1928
node _T_1929 = bits(_WIRE_141, 20, 20)
connect _WIRE_140.g, _T_1929
node _T_1930 = bits(_WIRE_141, 21, 21)
connect _WIRE_140.u, _T_1930
node _T_1931 = bits(_WIRE_141, 41, 22)
connect _WIRE_140.ppn, _T_1931
wire _WIRE_142 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_143 : UInt<42>
connect _WIRE_143, sectored_entries[0][4].data[3]
node _T_1932 = bits(_WIRE_143, 0, 0)
connect _WIRE_142.fragmented_superpage, _T_1932
node _T_1933 = bits(_WIRE_143, 1, 1)
connect _WIRE_142.c, _T_1933
node _T_1934 = bits(_WIRE_143, 2, 2)
connect _WIRE_142.eff, _T_1934
node _T_1935 = bits(_WIRE_143, 3, 3)
connect _WIRE_142.paa, _T_1935
node _T_1936 = bits(_WIRE_143, 4, 4)
connect _WIRE_142.pal, _T_1936
node _T_1937 = bits(_WIRE_143, 5, 5)
connect _WIRE_142.ppp, _T_1937
node _T_1938 = bits(_WIRE_143, 6, 6)
connect _WIRE_142.pr, _T_1938
node _T_1939 = bits(_WIRE_143, 7, 7)
connect _WIRE_142.px, _T_1939
node _T_1940 = bits(_WIRE_143, 8, 8)
connect _WIRE_142.pw, _T_1940
node _T_1941 = bits(_WIRE_143, 9, 9)
connect _WIRE_142.hr, _T_1941
node _T_1942 = bits(_WIRE_143, 10, 10)
connect _WIRE_142.hx, _T_1942
node _T_1943 = bits(_WIRE_143, 11, 11)
connect _WIRE_142.hw, _T_1943
node _T_1944 = bits(_WIRE_143, 12, 12)
connect _WIRE_142.sr, _T_1944
node _T_1945 = bits(_WIRE_143, 13, 13)
connect _WIRE_142.sx, _T_1945
node _T_1946 = bits(_WIRE_143, 14, 14)
connect _WIRE_142.sw, _T_1946
node _T_1947 = bits(_WIRE_143, 15, 15)
connect _WIRE_142.gf, _T_1947
node _T_1948 = bits(_WIRE_143, 16, 16)
connect _WIRE_142.pf, _T_1948
node _T_1949 = bits(_WIRE_143, 17, 17)
connect _WIRE_142.ae_stage2, _T_1949
node _T_1950 = bits(_WIRE_143, 18, 18)
connect _WIRE_142.ae_final, _T_1950
node _T_1951 = bits(_WIRE_143, 19, 19)
connect _WIRE_142.ae_ptw, _T_1951
node _T_1952 = bits(_WIRE_143, 20, 20)
connect _WIRE_142.g, _T_1952
node _T_1953 = bits(_WIRE_143, 21, 21)
connect _WIRE_142.u, _T_1953
node _T_1954 = bits(_WIRE_143, 41, 22)
connect _WIRE_142.ppn, _T_1954
node _T_1955 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1956 = and(_T_1955, _WIRE_136.fragmented_superpage)
when _T_1956 :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
node _T_1957 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1958 = and(_T_1957, _WIRE_138.fragmented_superpage)
when _T_1958 :
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
node _T_1959 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1960 = and(_T_1959, _WIRE_140.fragmented_superpage)
when _T_1960 :
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
node _T_1961 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_1962 = and(_T_1961, _WIRE_142.fragmented_superpage)
when _T_1962 :
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
else :
node _T_1963 = eq(hg_4, UInt<1>(0h0))
node _T_1964 = and(_T_1963, io.sfence.bits.rs2)
when _T_1964 :
wire _WIRE_144 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_145 : UInt<42>
connect _WIRE_145, sectored_entries[0][4].data[0]
node _T_1965 = bits(_WIRE_145, 0, 0)
connect _WIRE_144.fragmented_superpage, _T_1965
node _T_1966 = bits(_WIRE_145, 1, 1)
connect _WIRE_144.c, _T_1966
node _T_1967 = bits(_WIRE_145, 2, 2)
connect _WIRE_144.eff, _T_1967
node _T_1968 = bits(_WIRE_145, 3, 3)
connect _WIRE_144.paa, _T_1968
node _T_1969 = bits(_WIRE_145, 4, 4)
connect _WIRE_144.pal, _T_1969
node _T_1970 = bits(_WIRE_145, 5, 5)
connect _WIRE_144.ppp, _T_1970
node _T_1971 = bits(_WIRE_145, 6, 6)
connect _WIRE_144.pr, _T_1971
node _T_1972 = bits(_WIRE_145, 7, 7)
connect _WIRE_144.px, _T_1972
node _T_1973 = bits(_WIRE_145, 8, 8)
connect _WIRE_144.pw, _T_1973
node _T_1974 = bits(_WIRE_145, 9, 9)
connect _WIRE_144.hr, _T_1974
node _T_1975 = bits(_WIRE_145, 10, 10)
connect _WIRE_144.hx, _T_1975
node _T_1976 = bits(_WIRE_145, 11, 11)
connect _WIRE_144.hw, _T_1976
node _T_1977 = bits(_WIRE_145, 12, 12)
connect _WIRE_144.sr, _T_1977
node _T_1978 = bits(_WIRE_145, 13, 13)
connect _WIRE_144.sx, _T_1978
node _T_1979 = bits(_WIRE_145, 14, 14)
connect _WIRE_144.sw, _T_1979
node _T_1980 = bits(_WIRE_145, 15, 15)
connect _WIRE_144.gf, _T_1980
node _T_1981 = bits(_WIRE_145, 16, 16)
connect _WIRE_144.pf, _T_1981
node _T_1982 = bits(_WIRE_145, 17, 17)
connect _WIRE_144.ae_stage2, _T_1982
node _T_1983 = bits(_WIRE_145, 18, 18)
connect _WIRE_144.ae_final, _T_1983
node _T_1984 = bits(_WIRE_145, 19, 19)
connect _WIRE_144.ae_ptw, _T_1984
node _T_1985 = bits(_WIRE_145, 20, 20)
connect _WIRE_144.g, _T_1985
node _T_1986 = bits(_WIRE_145, 21, 21)
connect _WIRE_144.u, _T_1986
node _T_1987 = bits(_WIRE_145, 41, 22)
connect _WIRE_144.ppn, _T_1987
wire _WIRE_146 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_147 : UInt<42>
connect _WIRE_147, sectored_entries[0][4].data[1]
node _T_1988 = bits(_WIRE_147, 0, 0)
connect _WIRE_146.fragmented_superpage, _T_1988
node _T_1989 = bits(_WIRE_147, 1, 1)
connect _WIRE_146.c, _T_1989
node _T_1990 = bits(_WIRE_147, 2, 2)
connect _WIRE_146.eff, _T_1990
node _T_1991 = bits(_WIRE_147, 3, 3)
connect _WIRE_146.paa, _T_1991
node _T_1992 = bits(_WIRE_147, 4, 4)
connect _WIRE_146.pal, _T_1992
node _T_1993 = bits(_WIRE_147, 5, 5)
connect _WIRE_146.ppp, _T_1993
node _T_1994 = bits(_WIRE_147, 6, 6)
connect _WIRE_146.pr, _T_1994
node _T_1995 = bits(_WIRE_147, 7, 7)
connect _WIRE_146.px, _T_1995
node _T_1996 = bits(_WIRE_147, 8, 8)
connect _WIRE_146.pw, _T_1996
node _T_1997 = bits(_WIRE_147, 9, 9)
connect _WIRE_146.hr, _T_1997
node _T_1998 = bits(_WIRE_147, 10, 10)
connect _WIRE_146.hx, _T_1998
node _T_1999 = bits(_WIRE_147, 11, 11)
connect _WIRE_146.hw, _T_1999
node _T_2000 = bits(_WIRE_147, 12, 12)
connect _WIRE_146.sr, _T_2000
node _T_2001 = bits(_WIRE_147, 13, 13)
connect _WIRE_146.sx, _T_2001
node _T_2002 = bits(_WIRE_147, 14, 14)
connect _WIRE_146.sw, _T_2002
node _T_2003 = bits(_WIRE_147, 15, 15)
connect _WIRE_146.gf, _T_2003
node _T_2004 = bits(_WIRE_147, 16, 16)
connect _WIRE_146.pf, _T_2004
node _T_2005 = bits(_WIRE_147, 17, 17)
connect _WIRE_146.ae_stage2, _T_2005
node _T_2006 = bits(_WIRE_147, 18, 18)
connect _WIRE_146.ae_final, _T_2006
node _T_2007 = bits(_WIRE_147, 19, 19)
connect _WIRE_146.ae_ptw, _T_2007
node _T_2008 = bits(_WIRE_147, 20, 20)
connect _WIRE_146.g, _T_2008
node _T_2009 = bits(_WIRE_147, 21, 21)
connect _WIRE_146.u, _T_2009
node _T_2010 = bits(_WIRE_147, 41, 22)
connect _WIRE_146.ppn, _T_2010
wire _WIRE_148 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_149 : UInt<42>
connect _WIRE_149, sectored_entries[0][4].data[2]
node _T_2011 = bits(_WIRE_149, 0, 0)
connect _WIRE_148.fragmented_superpage, _T_2011
node _T_2012 = bits(_WIRE_149, 1, 1)
connect _WIRE_148.c, _T_2012
node _T_2013 = bits(_WIRE_149, 2, 2)
connect _WIRE_148.eff, _T_2013
node _T_2014 = bits(_WIRE_149, 3, 3)
connect _WIRE_148.paa, _T_2014
node _T_2015 = bits(_WIRE_149, 4, 4)
connect _WIRE_148.pal, _T_2015
node _T_2016 = bits(_WIRE_149, 5, 5)
connect _WIRE_148.ppp, _T_2016
node _T_2017 = bits(_WIRE_149, 6, 6)
connect _WIRE_148.pr, _T_2017
node _T_2018 = bits(_WIRE_149, 7, 7)
connect _WIRE_148.px, _T_2018
node _T_2019 = bits(_WIRE_149, 8, 8)
connect _WIRE_148.pw, _T_2019
node _T_2020 = bits(_WIRE_149, 9, 9)
connect _WIRE_148.hr, _T_2020
node _T_2021 = bits(_WIRE_149, 10, 10)
connect _WIRE_148.hx, _T_2021
node _T_2022 = bits(_WIRE_149, 11, 11)
connect _WIRE_148.hw, _T_2022
node _T_2023 = bits(_WIRE_149, 12, 12)
connect _WIRE_148.sr, _T_2023
node _T_2024 = bits(_WIRE_149, 13, 13)
connect _WIRE_148.sx, _T_2024
node _T_2025 = bits(_WIRE_149, 14, 14)
connect _WIRE_148.sw, _T_2025
node _T_2026 = bits(_WIRE_149, 15, 15)
connect _WIRE_148.gf, _T_2026
node _T_2027 = bits(_WIRE_149, 16, 16)
connect _WIRE_148.pf, _T_2027
node _T_2028 = bits(_WIRE_149, 17, 17)
connect _WIRE_148.ae_stage2, _T_2028
node _T_2029 = bits(_WIRE_149, 18, 18)
connect _WIRE_148.ae_final, _T_2029
node _T_2030 = bits(_WIRE_149, 19, 19)
connect _WIRE_148.ae_ptw, _T_2030
node _T_2031 = bits(_WIRE_149, 20, 20)
connect _WIRE_148.g, _T_2031
node _T_2032 = bits(_WIRE_149, 21, 21)
connect _WIRE_148.u, _T_2032
node _T_2033 = bits(_WIRE_149, 41, 22)
connect _WIRE_148.ppn, _T_2033
wire _WIRE_150 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_151 : UInt<42>
connect _WIRE_151, sectored_entries[0][4].data[3]
node _T_2034 = bits(_WIRE_151, 0, 0)
connect _WIRE_150.fragmented_superpage, _T_2034
node _T_2035 = bits(_WIRE_151, 1, 1)
connect _WIRE_150.c, _T_2035
node _T_2036 = bits(_WIRE_151, 2, 2)
connect _WIRE_150.eff, _T_2036
node _T_2037 = bits(_WIRE_151, 3, 3)
connect _WIRE_150.paa, _T_2037
node _T_2038 = bits(_WIRE_151, 4, 4)
connect _WIRE_150.pal, _T_2038
node _T_2039 = bits(_WIRE_151, 5, 5)
connect _WIRE_150.ppp, _T_2039
node _T_2040 = bits(_WIRE_151, 6, 6)
connect _WIRE_150.pr, _T_2040
node _T_2041 = bits(_WIRE_151, 7, 7)
connect _WIRE_150.px, _T_2041
node _T_2042 = bits(_WIRE_151, 8, 8)
connect _WIRE_150.pw, _T_2042
node _T_2043 = bits(_WIRE_151, 9, 9)
connect _WIRE_150.hr, _T_2043
node _T_2044 = bits(_WIRE_151, 10, 10)
connect _WIRE_150.hx, _T_2044
node _T_2045 = bits(_WIRE_151, 11, 11)
connect _WIRE_150.hw, _T_2045
node _T_2046 = bits(_WIRE_151, 12, 12)
connect _WIRE_150.sr, _T_2046
node _T_2047 = bits(_WIRE_151, 13, 13)
connect _WIRE_150.sx, _T_2047
node _T_2048 = bits(_WIRE_151, 14, 14)
connect _WIRE_150.sw, _T_2048
node _T_2049 = bits(_WIRE_151, 15, 15)
connect _WIRE_150.gf, _T_2049
node _T_2050 = bits(_WIRE_151, 16, 16)
connect _WIRE_150.pf, _T_2050
node _T_2051 = bits(_WIRE_151, 17, 17)
connect _WIRE_150.ae_stage2, _T_2051
node _T_2052 = bits(_WIRE_151, 18, 18)
connect _WIRE_150.ae_final, _T_2052
node _T_2053 = bits(_WIRE_151, 19, 19)
connect _WIRE_150.ae_ptw, _T_2053
node _T_2054 = bits(_WIRE_151, 20, 20)
connect _WIRE_150.g, _T_2054
node _T_2055 = bits(_WIRE_151, 21, 21)
connect _WIRE_150.u, _T_2055
node _T_2056 = bits(_WIRE_151, 41, 22)
connect _WIRE_150.ppn, _T_2056
node _T_2057 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_2058 = eq(_WIRE_144.g, UInt<1>(0h0))
node _T_2059 = and(_T_2057, _T_2058)
when _T_2059 :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
node _T_2060 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_2061 = eq(_WIRE_146.g, UInt<1>(0h0))
node _T_2062 = and(_T_2060, _T_2061)
when _T_2062 :
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
node _T_2063 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_2064 = eq(_WIRE_148.g, UInt<1>(0h0))
node _T_2065 = and(_T_2063, _T_2064)
when _T_2065 :
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
node _T_2066 = eq(sectored_entries[0][4].tag_v, hv_4)
node _T_2067 = eq(_WIRE_150.g, UInt<1>(0h0))
node _T_2068 = and(_T_2066, _T_2067)
when _T_2068 :
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
else :
node _T_2069 = or(hv_4, hg_4)
wire _WIRE_152 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_153 : UInt<42>
connect _WIRE_153, sectored_entries[0][4].data[0]
node _T_2070 = bits(_WIRE_153, 0, 0)
connect _WIRE_152.fragmented_superpage, _T_2070
node _T_2071 = bits(_WIRE_153, 1, 1)
connect _WIRE_152.c, _T_2071
node _T_2072 = bits(_WIRE_153, 2, 2)
connect _WIRE_152.eff, _T_2072
node _T_2073 = bits(_WIRE_153, 3, 3)
connect _WIRE_152.paa, _T_2073
node _T_2074 = bits(_WIRE_153, 4, 4)
connect _WIRE_152.pal, _T_2074
node _T_2075 = bits(_WIRE_153, 5, 5)
connect _WIRE_152.ppp, _T_2075
node _T_2076 = bits(_WIRE_153, 6, 6)
connect _WIRE_152.pr, _T_2076
node _T_2077 = bits(_WIRE_153, 7, 7)
connect _WIRE_152.px, _T_2077
node _T_2078 = bits(_WIRE_153, 8, 8)
connect _WIRE_152.pw, _T_2078
node _T_2079 = bits(_WIRE_153, 9, 9)
connect _WIRE_152.hr, _T_2079
node _T_2080 = bits(_WIRE_153, 10, 10)
connect _WIRE_152.hx, _T_2080
node _T_2081 = bits(_WIRE_153, 11, 11)
connect _WIRE_152.hw, _T_2081
node _T_2082 = bits(_WIRE_153, 12, 12)
connect _WIRE_152.sr, _T_2082
node _T_2083 = bits(_WIRE_153, 13, 13)
connect _WIRE_152.sx, _T_2083
node _T_2084 = bits(_WIRE_153, 14, 14)
connect _WIRE_152.sw, _T_2084
node _T_2085 = bits(_WIRE_153, 15, 15)
connect _WIRE_152.gf, _T_2085
node _T_2086 = bits(_WIRE_153, 16, 16)
connect _WIRE_152.pf, _T_2086
node _T_2087 = bits(_WIRE_153, 17, 17)
connect _WIRE_152.ae_stage2, _T_2087
node _T_2088 = bits(_WIRE_153, 18, 18)
connect _WIRE_152.ae_final, _T_2088
node _T_2089 = bits(_WIRE_153, 19, 19)
connect _WIRE_152.ae_ptw, _T_2089
node _T_2090 = bits(_WIRE_153, 20, 20)
connect _WIRE_152.g, _T_2090
node _T_2091 = bits(_WIRE_153, 21, 21)
connect _WIRE_152.u, _T_2091
node _T_2092 = bits(_WIRE_153, 41, 22)
connect _WIRE_152.ppn, _T_2092
wire _WIRE_154 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_155 : UInt<42>
connect _WIRE_155, sectored_entries[0][4].data[1]
node _T_2093 = bits(_WIRE_155, 0, 0)
connect _WIRE_154.fragmented_superpage, _T_2093
node _T_2094 = bits(_WIRE_155, 1, 1)
connect _WIRE_154.c, _T_2094
node _T_2095 = bits(_WIRE_155, 2, 2)
connect _WIRE_154.eff, _T_2095
node _T_2096 = bits(_WIRE_155, 3, 3)
connect _WIRE_154.paa, _T_2096
node _T_2097 = bits(_WIRE_155, 4, 4)
connect _WIRE_154.pal, _T_2097
node _T_2098 = bits(_WIRE_155, 5, 5)
connect _WIRE_154.ppp, _T_2098
node _T_2099 = bits(_WIRE_155, 6, 6)
connect _WIRE_154.pr, _T_2099
node _T_2100 = bits(_WIRE_155, 7, 7)
connect _WIRE_154.px, _T_2100
node _T_2101 = bits(_WIRE_155, 8, 8)
connect _WIRE_154.pw, _T_2101
node _T_2102 = bits(_WIRE_155, 9, 9)
connect _WIRE_154.hr, _T_2102
node _T_2103 = bits(_WIRE_155, 10, 10)
connect _WIRE_154.hx, _T_2103
node _T_2104 = bits(_WIRE_155, 11, 11)
connect _WIRE_154.hw, _T_2104
node _T_2105 = bits(_WIRE_155, 12, 12)
connect _WIRE_154.sr, _T_2105
node _T_2106 = bits(_WIRE_155, 13, 13)
connect _WIRE_154.sx, _T_2106
node _T_2107 = bits(_WIRE_155, 14, 14)
connect _WIRE_154.sw, _T_2107
node _T_2108 = bits(_WIRE_155, 15, 15)
connect _WIRE_154.gf, _T_2108
node _T_2109 = bits(_WIRE_155, 16, 16)
connect _WIRE_154.pf, _T_2109
node _T_2110 = bits(_WIRE_155, 17, 17)
connect _WIRE_154.ae_stage2, _T_2110
node _T_2111 = bits(_WIRE_155, 18, 18)
connect _WIRE_154.ae_final, _T_2111
node _T_2112 = bits(_WIRE_155, 19, 19)
connect _WIRE_154.ae_ptw, _T_2112
node _T_2113 = bits(_WIRE_155, 20, 20)
connect _WIRE_154.g, _T_2113
node _T_2114 = bits(_WIRE_155, 21, 21)
connect _WIRE_154.u, _T_2114
node _T_2115 = bits(_WIRE_155, 41, 22)
connect _WIRE_154.ppn, _T_2115
wire _WIRE_156 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_157 : UInt<42>
connect _WIRE_157, sectored_entries[0][4].data[2]
node _T_2116 = bits(_WIRE_157, 0, 0)
connect _WIRE_156.fragmented_superpage, _T_2116
node _T_2117 = bits(_WIRE_157, 1, 1)
connect _WIRE_156.c, _T_2117
node _T_2118 = bits(_WIRE_157, 2, 2)
connect _WIRE_156.eff, _T_2118
node _T_2119 = bits(_WIRE_157, 3, 3)
connect _WIRE_156.paa, _T_2119
node _T_2120 = bits(_WIRE_157, 4, 4)
connect _WIRE_156.pal, _T_2120
node _T_2121 = bits(_WIRE_157, 5, 5)
connect _WIRE_156.ppp, _T_2121
node _T_2122 = bits(_WIRE_157, 6, 6)
connect _WIRE_156.pr, _T_2122
node _T_2123 = bits(_WIRE_157, 7, 7)
connect _WIRE_156.px, _T_2123
node _T_2124 = bits(_WIRE_157, 8, 8)
connect _WIRE_156.pw, _T_2124
node _T_2125 = bits(_WIRE_157, 9, 9)
connect _WIRE_156.hr, _T_2125
node _T_2126 = bits(_WIRE_157, 10, 10)
connect _WIRE_156.hx, _T_2126
node _T_2127 = bits(_WIRE_157, 11, 11)
connect _WIRE_156.hw, _T_2127
node _T_2128 = bits(_WIRE_157, 12, 12)
connect _WIRE_156.sr, _T_2128
node _T_2129 = bits(_WIRE_157, 13, 13)
connect _WIRE_156.sx, _T_2129
node _T_2130 = bits(_WIRE_157, 14, 14)
connect _WIRE_156.sw, _T_2130
node _T_2131 = bits(_WIRE_157, 15, 15)
connect _WIRE_156.gf, _T_2131
node _T_2132 = bits(_WIRE_157, 16, 16)
connect _WIRE_156.pf, _T_2132
node _T_2133 = bits(_WIRE_157, 17, 17)
connect _WIRE_156.ae_stage2, _T_2133
node _T_2134 = bits(_WIRE_157, 18, 18)
connect _WIRE_156.ae_final, _T_2134
node _T_2135 = bits(_WIRE_157, 19, 19)
connect _WIRE_156.ae_ptw, _T_2135
node _T_2136 = bits(_WIRE_157, 20, 20)
connect _WIRE_156.g, _T_2136
node _T_2137 = bits(_WIRE_157, 21, 21)
connect _WIRE_156.u, _T_2137
node _T_2138 = bits(_WIRE_157, 41, 22)
connect _WIRE_156.ppn, _T_2138
wire _WIRE_158 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_159 : UInt<42>
connect _WIRE_159, sectored_entries[0][4].data[3]
node _T_2139 = bits(_WIRE_159, 0, 0)
connect _WIRE_158.fragmented_superpage, _T_2139
node _T_2140 = bits(_WIRE_159, 1, 1)
connect _WIRE_158.c, _T_2140
node _T_2141 = bits(_WIRE_159, 2, 2)
connect _WIRE_158.eff, _T_2141
node _T_2142 = bits(_WIRE_159, 3, 3)
connect _WIRE_158.paa, _T_2142
node _T_2143 = bits(_WIRE_159, 4, 4)
connect _WIRE_158.pal, _T_2143
node _T_2144 = bits(_WIRE_159, 5, 5)
connect _WIRE_158.ppp, _T_2144
node _T_2145 = bits(_WIRE_159, 6, 6)
connect _WIRE_158.pr, _T_2145
node _T_2146 = bits(_WIRE_159, 7, 7)
connect _WIRE_158.px, _T_2146
node _T_2147 = bits(_WIRE_159, 8, 8)
connect _WIRE_158.pw, _T_2147
node _T_2148 = bits(_WIRE_159, 9, 9)
connect _WIRE_158.hr, _T_2148
node _T_2149 = bits(_WIRE_159, 10, 10)
connect _WIRE_158.hx, _T_2149
node _T_2150 = bits(_WIRE_159, 11, 11)
connect _WIRE_158.hw, _T_2150
node _T_2151 = bits(_WIRE_159, 12, 12)
connect _WIRE_158.sr, _T_2151
node _T_2152 = bits(_WIRE_159, 13, 13)
connect _WIRE_158.sx, _T_2152
node _T_2153 = bits(_WIRE_159, 14, 14)
connect _WIRE_158.sw, _T_2153
node _T_2154 = bits(_WIRE_159, 15, 15)
connect _WIRE_158.gf, _T_2154
node _T_2155 = bits(_WIRE_159, 16, 16)
connect _WIRE_158.pf, _T_2155
node _T_2156 = bits(_WIRE_159, 17, 17)
connect _WIRE_158.ae_stage2, _T_2156
node _T_2157 = bits(_WIRE_159, 18, 18)
connect _WIRE_158.ae_final, _T_2157
node _T_2158 = bits(_WIRE_159, 19, 19)
connect _WIRE_158.ae_ptw, _T_2158
node _T_2159 = bits(_WIRE_159, 20, 20)
connect _WIRE_158.g, _T_2159
node _T_2160 = bits(_WIRE_159, 21, 21)
connect _WIRE_158.u, _T_2160
node _T_2161 = bits(_WIRE_159, 41, 22)
connect _WIRE_158.ppn, _T_2161
node _T_2162 = eq(sectored_entries[0][4].tag_v, _T_2069)
when _T_2162 :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
node _T_2163 = eq(sectored_entries[0][4].tag_v, _T_2069)
when _T_2163 :
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
node _T_2164 = eq(sectored_entries[0][4].tag_v, _T_2069)
when _T_2164 :
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
node _T_2165 = eq(sectored_entries[0][4].tag_v, _T_2069)
when _T_2165 :
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
node hv_5 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_5 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_2166 = eq(hg_5, UInt<1>(0h0))
node _T_2167 = and(_T_2166, io.sfence.bits.rs1)
when _T_2167 :
node _T_2168 = xor(sectored_entries[0][5].tag_vpn, vpn)
node _T_2169 = shr(_T_2168, 2)
node _T_2170 = eq(_T_2169, UInt<1>(0h0))
node _T_2171 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2172 = and(_T_2170, _T_2171)
when _T_2172 :
wire _WIRE_160 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_161 : UInt<42>
connect _WIRE_161, sectored_entries[0][5].data[0]
node _T_2173 = bits(_WIRE_161, 0, 0)
connect _WIRE_160.fragmented_superpage, _T_2173
node _T_2174 = bits(_WIRE_161, 1, 1)
connect _WIRE_160.c, _T_2174
node _T_2175 = bits(_WIRE_161, 2, 2)
connect _WIRE_160.eff, _T_2175
node _T_2176 = bits(_WIRE_161, 3, 3)
connect _WIRE_160.paa, _T_2176
node _T_2177 = bits(_WIRE_161, 4, 4)
connect _WIRE_160.pal, _T_2177
node _T_2178 = bits(_WIRE_161, 5, 5)
connect _WIRE_160.ppp, _T_2178
node _T_2179 = bits(_WIRE_161, 6, 6)
connect _WIRE_160.pr, _T_2179
node _T_2180 = bits(_WIRE_161, 7, 7)
connect _WIRE_160.px, _T_2180
node _T_2181 = bits(_WIRE_161, 8, 8)
connect _WIRE_160.pw, _T_2181
node _T_2182 = bits(_WIRE_161, 9, 9)
connect _WIRE_160.hr, _T_2182
node _T_2183 = bits(_WIRE_161, 10, 10)
connect _WIRE_160.hx, _T_2183
node _T_2184 = bits(_WIRE_161, 11, 11)
connect _WIRE_160.hw, _T_2184
node _T_2185 = bits(_WIRE_161, 12, 12)
connect _WIRE_160.sr, _T_2185
node _T_2186 = bits(_WIRE_161, 13, 13)
connect _WIRE_160.sx, _T_2186
node _T_2187 = bits(_WIRE_161, 14, 14)
connect _WIRE_160.sw, _T_2187
node _T_2188 = bits(_WIRE_161, 15, 15)
connect _WIRE_160.gf, _T_2188
node _T_2189 = bits(_WIRE_161, 16, 16)
connect _WIRE_160.pf, _T_2189
node _T_2190 = bits(_WIRE_161, 17, 17)
connect _WIRE_160.ae_stage2, _T_2190
node _T_2191 = bits(_WIRE_161, 18, 18)
connect _WIRE_160.ae_final, _T_2191
node _T_2192 = bits(_WIRE_161, 19, 19)
connect _WIRE_160.ae_ptw, _T_2192
node _T_2193 = bits(_WIRE_161, 20, 20)
connect _WIRE_160.g, _T_2193
node _T_2194 = bits(_WIRE_161, 21, 21)
connect _WIRE_160.u, _T_2194
node _T_2195 = bits(_WIRE_161, 41, 22)
connect _WIRE_160.ppn, _T_2195
wire _WIRE_162 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_163 : UInt<42>
connect _WIRE_163, sectored_entries[0][5].data[1]
node _T_2196 = bits(_WIRE_163, 0, 0)
connect _WIRE_162.fragmented_superpage, _T_2196
node _T_2197 = bits(_WIRE_163, 1, 1)
connect _WIRE_162.c, _T_2197
node _T_2198 = bits(_WIRE_163, 2, 2)
connect _WIRE_162.eff, _T_2198
node _T_2199 = bits(_WIRE_163, 3, 3)
connect _WIRE_162.paa, _T_2199
node _T_2200 = bits(_WIRE_163, 4, 4)
connect _WIRE_162.pal, _T_2200
node _T_2201 = bits(_WIRE_163, 5, 5)
connect _WIRE_162.ppp, _T_2201
node _T_2202 = bits(_WIRE_163, 6, 6)
connect _WIRE_162.pr, _T_2202
node _T_2203 = bits(_WIRE_163, 7, 7)
connect _WIRE_162.px, _T_2203
node _T_2204 = bits(_WIRE_163, 8, 8)
connect _WIRE_162.pw, _T_2204
node _T_2205 = bits(_WIRE_163, 9, 9)
connect _WIRE_162.hr, _T_2205
node _T_2206 = bits(_WIRE_163, 10, 10)
connect _WIRE_162.hx, _T_2206
node _T_2207 = bits(_WIRE_163, 11, 11)
connect _WIRE_162.hw, _T_2207
node _T_2208 = bits(_WIRE_163, 12, 12)
connect _WIRE_162.sr, _T_2208
node _T_2209 = bits(_WIRE_163, 13, 13)
connect _WIRE_162.sx, _T_2209
node _T_2210 = bits(_WIRE_163, 14, 14)
connect _WIRE_162.sw, _T_2210
node _T_2211 = bits(_WIRE_163, 15, 15)
connect _WIRE_162.gf, _T_2211
node _T_2212 = bits(_WIRE_163, 16, 16)
connect _WIRE_162.pf, _T_2212
node _T_2213 = bits(_WIRE_163, 17, 17)
connect _WIRE_162.ae_stage2, _T_2213
node _T_2214 = bits(_WIRE_163, 18, 18)
connect _WIRE_162.ae_final, _T_2214
node _T_2215 = bits(_WIRE_163, 19, 19)
connect _WIRE_162.ae_ptw, _T_2215
node _T_2216 = bits(_WIRE_163, 20, 20)
connect _WIRE_162.g, _T_2216
node _T_2217 = bits(_WIRE_163, 21, 21)
connect _WIRE_162.u, _T_2217
node _T_2218 = bits(_WIRE_163, 41, 22)
connect _WIRE_162.ppn, _T_2218
wire _WIRE_164 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_165 : UInt<42>
connect _WIRE_165, sectored_entries[0][5].data[2]
node _T_2219 = bits(_WIRE_165, 0, 0)
connect _WIRE_164.fragmented_superpage, _T_2219
node _T_2220 = bits(_WIRE_165, 1, 1)
connect _WIRE_164.c, _T_2220
node _T_2221 = bits(_WIRE_165, 2, 2)
connect _WIRE_164.eff, _T_2221
node _T_2222 = bits(_WIRE_165, 3, 3)
connect _WIRE_164.paa, _T_2222
node _T_2223 = bits(_WIRE_165, 4, 4)
connect _WIRE_164.pal, _T_2223
node _T_2224 = bits(_WIRE_165, 5, 5)
connect _WIRE_164.ppp, _T_2224
node _T_2225 = bits(_WIRE_165, 6, 6)
connect _WIRE_164.pr, _T_2225
node _T_2226 = bits(_WIRE_165, 7, 7)
connect _WIRE_164.px, _T_2226
node _T_2227 = bits(_WIRE_165, 8, 8)
connect _WIRE_164.pw, _T_2227
node _T_2228 = bits(_WIRE_165, 9, 9)
connect _WIRE_164.hr, _T_2228
node _T_2229 = bits(_WIRE_165, 10, 10)
connect _WIRE_164.hx, _T_2229
node _T_2230 = bits(_WIRE_165, 11, 11)
connect _WIRE_164.hw, _T_2230
node _T_2231 = bits(_WIRE_165, 12, 12)
connect _WIRE_164.sr, _T_2231
node _T_2232 = bits(_WIRE_165, 13, 13)
connect _WIRE_164.sx, _T_2232
node _T_2233 = bits(_WIRE_165, 14, 14)
connect _WIRE_164.sw, _T_2233
node _T_2234 = bits(_WIRE_165, 15, 15)
connect _WIRE_164.gf, _T_2234
node _T_2235 = bits(_WIRE_165, 16, 16)
connect _WIRE_164.pf, _T_2235
node _T_2236 = bits(_WIRE_165, 17, 17)
connect _WIRE_164.ae_stage2, _T_2236
node _T_2237 = bits(_WIRE_165, 18, 18)
connect _WIRE_164.ae_final, _T_2237
node _T_2238 = bits(_WIRE_165, 19, 19)
connect _WIRE_164.ae_ptw, _T_2238
node _T_2239 = bits(_WIRE_165, 20, 20)
connect _WIRE_164.g, _T_2239
node _T_2240 = bits(_WIRE_165, 21, 21)
connect _WIRE_164.u, _T_2240
node _T_2241 = bits(_WIRE_165, 41, 22)
connect _WIRE_164.ppn, _T_2241
wire _WIRE_166 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_167 : UInt<42>
connect _WIRE_167, sectored_entries[0][5].data[3]
node _T_2242 = bits(_WIRE_167, 0, 0)
connect _WIRE_166.fragmented_superpage, _T_2242
node _T_2243 = bits(_WIRE_167, 1, 1)
connect _WIRE_166.c, _T_2243
node _T_2244 = bits(_WIRE_167, 2, 2)
connect _WIRE_166.eff, _T_2244
node _T_2245 = bits(_WIRE_167, 3, 3)
connect _WIRE_166.paa, _T_2245
node _T_2246 = bits(_WIRE_167, 4, 4)
connect _WIRE_166.pal, _T_2246
node _T_2247 = bits(_WIRE_167, 5, 5)
connect _WIRE_166.ppp, _T_2247
node _T_2248 = bits(_WIRE_167, 6, 6)
connect _WIRE_166.pr, _T_2248
node _T_2249 = bits(_WIRE_167, 7, 7)
connect _WIRE_166.px, _T_2249
node _T_2250 = bits(_WIRE_167, 8, 8)
connect _WIRE_166.pw, _T_2250
node _T_2251 = bits(_WIRE_167, 9, 9)
connect _WIRE_166.hr, _T_2251
node _T_2252 = bits(_WIRE_167, 10, 10)
connect _WIRE_166.hx, _T_2252
node _T_2253 = bits(_WIRE_167, 11, 11)
connect _WIRE_166.hw, _T_2253
node _T_2254 = bits(_WIRE_167, 12, 12)
connect _WIRE_166.sr, _T_2254
node _T_2255 = bits(_WIRE_167, 13, 13)
connect _WIRE_166.sx, _T_2255
node _T_2256 = bits(_WIRE_167, 14, 14)
connect _WIRE_166.sw, _T_2256
node _T_2257 = bits(_WIRE_167, 15, 15)
connect _WIRE_166.gf, _T_2257
node _T_2258 = bits(_WIRE_167, 16, 16)
connect _WIRE_166.pf, _T_2258
node _T_2259 = bits(_WIRE_167, 17, 17)
connect _WIRE_166.ae_stage2, _T_2259
node _T_2260 = bits(_WIRE_167, 18, 18)
connect _WIRE_166.ae_final, _T_2260
node _T_2261 = bits(_WIRE_167, 19, 19)
connect _WIRE_166.ae_ptw, _T_2261
node _T_2262 = bits(_WIRE_167, 20, 20)
connect _WIRE_166.g, _T_2262
node _T_2263 = bits(_WIRE_167, 21, 21)
connect _WIRE_166.u, _T_2263
node _T_2264 = bits(_WIRE_167, 41, 22)
connect _WIRE_166.ppn, _T_2264
node _T_2265 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2266 = bits(vpn, 1, 0)
node _T_2267 = eq(UInt<1>(0h0), _T_2266)
node _T_2268 = and(_T_2265, _T_2267)
when _T_2268 :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
node _T_2269 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2270 = bits(vpn, 1, 0)
node _T_2271 = eq(UInt<1>(0h1), _T_2270)
node _T_2272 = and(_T_2269, _T_2271)
when _T_2272 :
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
node _T_2273 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2274 = bits(vpn, 1, 0)
node _T_2275 = eq(UInt<2>(0h2), _T_2274)
node _T_2276 = and(_T_2273, _T_2275)
when _T_2276 :
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
node _T_2277 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2278 = bits(vpn, 1, 0)
node _T_2279 = eq(UInt<2>(0h3), _T_2278)
node _T_2280 = and(_T_2277, _T_2279)
when _T_2280 :
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
node _T_2281 = xor(sectored_entries[0][5].tag_vpn, vpn)
node _T_2282 = shr(_T_2281, 18)
node _T_2283 = eq(_T_2282, UInt<1>(0h0))
when _T_2283 :
wire _WIRE_168 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_169 : UInt<42>
connect _WIRE_169, sectored_entries[0][5].data[0]
node _T_2284 = bits(_WIRE_169, 0, 0)
connect _WIRE_168.fragmented_superpage, _T_2284
node _T_2285 = bits(_WIRE_169, 1, 1)
connect _WIRE_168.c, _T_2285
node _T_2286 = bits(_WIRE_169, 2, 2)
connect _WIRE_168.eff, _T_2286
node _T_2287 = bits(_WIRE_169, 3, 3)
connect _WIRE_168.paa, _T_2287
node _T_2288 = bits(_WIRE_169, 4, 4)
connect _WIRE_168.pal, _T_2288
node _T_2289 = bits(_WIRE_169, 5, 5)
connect _WIRE_168.ppp, _T_2289
node _T_2290 = bits(_WIRE_169, 6, 6)
connect _WIRE_168.pr, _T_2290
node _T_2291 = bits(_WIRE_169, 7, 7)
connect _WIRE_168.px, _T_2291
node _T_2292 = bits(_WIRE_169, 8, 8)
connect _WIRE_168.pw, _T_2292
node _T_2293 = bits(_WIRE_169, 9, 9)
connect _WIRE_168.hr, _T_2293
node _T_2294 = bits(_WIRE_169, 10, 10)
connect _WIRE_168.hx, _T_2294
node _T_2295 = bits(_WIRE_169, 11, 11)
connect _WIRE_168.hw, _T_2295
node _T_2296 = bits(_WIRE_169, 12, 12)
connect _WIRE_168.sr, _T_2296
node _T_2297 = bits(_WIRE_169, 13, 13)
connect _WIRE_168.sx, _T_2297
node _T_2298 = bits(_WIRE_169, 14, 14)
connect _WIRE_168.sw, _T_2298
node _T_2299 = bits(_WIRE_169, 15, 15)
connect _WIRE_168.gf, _T_2299
node _T_2300 = bits(_WIRE_169, 16, 16)
connect _WIRE_168.pf, _T_2300
node _T_2301 = bits(_WIRE_169, 17, 17)
connect _WIRE_168.ae_stage2, _T_2301
node _T_2302 = bits(_WIRE_169, 18, 18)
connect _WIRE_168.ae_final, _T_2302
node _T_2303 = bits(_WIRE_169, 19, 19)
connect _WIRE_168.ae_ptw, _T_2303
node _T_2304 = bits(_WIRE_169, 20, 20)
connect _WIRE_168.g, _T_2304
node _T_2305 = bits(_WIRE_169, 21, 21)
connect _WIRE_168.u, _T_2305
node _T_2306 = bits(_WIRE_169, 41, 22)
connect _WIRE_168.ppn, _T_2306
wire _WIRE_170 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_171 : UInt<42>
connect _WIRE_171, sectored_entries[0][5].data[1]
node _T_2307 = bits(_WIRE_171, 0, 0)
connect _WIRE_170.fragmented_superpage, _T_2307
node _T_2308 = bits(_WIRE_171, 1, 1)
connect _WIRE_170.c, _T_2308
node _T_2309 = bits(_WIRE_171, 2, 2)
connect _WIRE_170.eff, _T_2309
node _T_2310 = bits(_WIRE_171, 3, 3)
connect _WIRE_170.paa, _T_2310
node _T_2311 = bits(_WIRE_171, 4, 4)
connect _WIRE_170.pal, _T_2311
node _T_2312 = bits(_WIRE_171, 5, 5)
connect _WIRE_170.ppp, _T_2312
node _T_2313 = bits(_WIRE_171, 6, 6)
connect _WIRE_170.pr, _T_2313
node _T_2314 = bits(_WIRE_171, 7, 7)
connect _WIRE_170.px, _T_2314
node _T_2315 = bits(_WIRE_171, 8, 8)
connect _WIRE_170.pw, _T_2315
node _T_2316 = bits(_WIRE_171, 9, 9)
connect _WIRE_170.hr, _T_2316
node _T_2317 = bits(_WIRE_171, 10, 10)
connect _WIRE_170.hx, _T_2317
node _T_2318 = bits(_WIRE_171, 11, 11)
connect _WIRE_170.hw, _T_2318
node _T_2319 = bits(_WIRE_171, 12, 12)
connect _WIRE_170.sr, _T_2319
node _T_2320 = bits(_WIRE_171, 13, 13)
connect _WIRE_170.sx, _T_2320
node _T_2321 = bits(_WIRE_171, 14, 14)
connect _WIRE_170.sw, _T_2321
node _T_2322 = bits(_WIRE_171, 15, 15)
connect _WIRE_170.gf, _T_2322
node _T_2323 = bits(_WIRE_171, 16, 16)
connect _WIRE_170.pf, _T_2323
node _T_2324 = bits(_WIRE_171, 17, 17)
connect _WIRE_170.ae_stage2, _T_2324
node _T_2325 = bits(_WIRE_171, 18, 18)
connect _WIRE_170.ae_final, _T_2325
node _T_2326 = bits(_WIRE_171, 19, 19)
connect _WIRE_170.ae_ptw, _T_2326
node _T_2327 = bits(_WIRE_171, 20, 20)
connect _WIRE_170.g, _T_2327
node _T_2328 = bits(_WIRE_171, 21, 21)
connect _WIRE_170.u, _T_2328
node _T_2329 = bits(_WIRE_171, 41, 22)
connect _WIRE_170.ppn, _T_2329
wire _WIRE_172 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_173 : UInt<42>
connect _WIRE_173, sectored_entries[0][5].data[2]
node _T_2330 = bits(_WIRE_173, 0, 0)
connect _WIRE_172.fragmented_superpage, _T_2330
node _T_2331 = bits(_WIRE_173, 1, 1)
connect _WIRE_172.c, _T_2331
node _T_2332 = bits(_WIRE_173, 2, 2)
connect _WIRE_172.eff, _T_2332
node _T_2333 = bits(_WIRE_173, 3, 3)
connect _WIRE_172.paa, _T_2333
node _T_2334 = bits(_WIRE_173, 4, 4)
connect _WIRE_172.pal, _T_2334
node _T_2335 = bits(_WIRE_173, 5, 5)
connect _WIRE_172.ppp, _T_2335
node _T_2336 = bits(_WIRE_173, 6, 6)
connect _WIRE_172.pr, _T_2336
node _T_2337 = bits(_WIRE_173, 7, 7)
connect _WIRE_172.px, _T_2337
node _T_2338 = bits(_WIRE_173, 8, 8)
connect _WIRE_172.pw, _T_2338
node _T_2339 = bits(_WIRE_173, 9, 9)
connect _WIRE_172.hr, _T_2339
node _T_2340 = bits(_WIRE_173, 10, 10)
connect _WIRE_172.hx, _T_2340
node _T_2341 = bits(_WIRE_173, 11, 11)
connect _WIRE_172.hw, _T_2341
node _T_2342 = bits(_WIRE_173, 12, 12)
connect _WIRE_172.sr, _T_2342
node _T_2343 = bits(_WIRE_173, 13, 13)
connect _WIRE_172.sx, _T_2343
node _T_2344 = bits(_WIRE_173, 14, 14)
connect _WIRE_172.sw, _T_2344
node _T_2345 = bits(_WIRE_173, 15, 15)
connect _WIRE_172.gf, _T_2345
node _T_2346 = bits(_WIRE_173, 16, 16)
connect _WIRE_172.pf, _T_2346
node _T_2347 = bits(_WIRE_173, 17, 17)
connect _WIRE_172.ae_stage2, _T_2347
node _T_2348 = bits(_WIRE_173, 18, 18)
connect _WIRE_172.ae_final, _T_2348
node _T_2349 = bits(_WIRE_173, 19, 19)
connect _WIRE_172.ae_ptw, _T_2349
node _T_2350 = bits(_WIRE_173, 20, 20)
connect _WIRE_172.g, _T_2350
node _T_2351 = bits(_WIRE_173, 21, 21)
connect _WIRE_172.u, _T_2351
node _T_2352 = bits(_WIRE_173, 41, 22)
connect _WIRE_172.ppn, _T_2352
wire _WIRE_174 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_175 : UInt<42>
connect _WIRE_175, sectored_entries[0][5].data[3]
node _T_2353 = bits(_WIRE_175, 0, 0)
connect _WIRE_174.fragmented_superpage, _T_2353
node _T_2354 = bits(_WIRE_175, 1, 1)
connect _WIRE_174.c, _T_2354
node _T_2355 = bits(_WIRE_175, 2, 2)
connect _WIRE_174.eff, _T_2355
node _T_2356 = bits(_WIRE_175, 3, 3)
connect _WIRE_174.paa, _T_2356
node _T_2357 = bits(_WIRE_175, 4, 4)
connect _WIRE_174.pal, _T_2357
node _T_2358 = bits(_WIRE_175, 5, 5)
connect _WIRE_174.ppp, _T_2358
node _T_2359 = bits(_WIRE_175, 6, 6)
connect _WIRE_174.pr, _T_2359
node _T_2360 = bits(_WIRE_175, 7, 7)
connect _WIRE_174.px, _T_2360
node _T_2361 = bits(_WIRE_175, 8, 8)
connect _WIRE_174.pw, _T_2361
node _T_2362 = bits(_WIRE_175, 9, 9)
connect _WIRE_174.hr, _T_2362
node _T_2363 = bits(_WIRE_175, 10, 10)
connect _WIRE_174.hx, _T_2363
node _T_2364 = bits(_WIRE_175, 11, 11)
connect _WIRE_174.hw, _T_2364
node _T_2365 = bits(_WIRE_175, 12, 12)
connect _WIRE_174.sr, _T_2365
node _T_2366 = bits(_WIRE_175, 13, 13)
connect _WIRE_174.sx, _T_2366
node _T_2367 = bits(_WIRE_175, 14, 14)
connect _WIRE_174.sw, _T_2367
node _T_2368 = bits(_WIRE_175, 15, 15)
connect _WIRE_174.gf, _T_2368
node _T_2369 = bits(_WIRE_175, 16, 16)
connect _WIRE_174.pf, _T_2369
node _T_2370 = bits(_WIRE_175, 17, 17)
connect _WIRE_174.ae_stage2, _T_2370
node _T_2371 = bits(_WIRE_175, 18, 18)
connect _WIRE_174.ae_final, _T_2371
node _T_2372 = bits(_WIRE_175, 19, 19)
connect _WIRE_174.ae_ptw, _T_2372
node _T_2373 = bits(_WIRE_175, 20, 20)
connect _WIRE_174.g, _T_2373
node _T_2374 = bits(_WIRE_175, 21, 21)
connect _WIRE_174.u, _T_2374
node _T_2375 = bits(_WIRE_175, 41, 22)
connect _WIRE_174.ppn, _T_2375
node _T_2376 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2377 = and(_T_2376, _WIRE_168.fragmented_superpage)
when _T_2377 :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
node _T_2378 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2379 = and(_T_2378, _WIRE_170.fragmented_superpage)
when _T_2379 :
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
node _T_2380 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2381 = and(_T_2380, _WIRE_172.fragmented_superpage)
when _T_2381 :
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
node _T_2382 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2383 = and(_T_2382, _WIRE_174.fragmented_superpage)
when _T_2383 :
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
else :
node _T_2384 = eq(hg_5, UInt<1>(0h0))
node _T_2385 = and(_T_2384, io.sfence.bits.rs2)
when _T_2385 :
wire _WIRE_176 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_177 : UInt<42>
connect _WIRE_177, sectored_entries[0][5].data[0]
node _T_2386 = bits(_WIRE_177, 0, 0)
connect _WIRE_176.fragmented_superpage, _T_2386
node _T_2387 = bits(_WIRE_177, 1, 1)
connect _WIRE_176.c, _T_2387
node _T_2388 = bits(_WIRE_177, 2, 2)
connect _WIRE_176.eff, _T_2388
node _T_2389 = bits(_WIRE_177, 3, 3)
connect _WIRE_176.paa, _T_2389
node _T_2390 = bits(_WIRE_177, 4, 4)
connect _WIRE_176.pal, _T_2390
node _T_2391 = bits(_WIRE_177, 5, 5)
connect _WIRE_176.ppp, _T_2391
node _T_2392 = bits(_WIRE_177, 6, 6)
connect _WIRE_176.pr, _T_2392
node _T_2393 = bits(_WIRE_177, 7, 7)
connect _WIRE_176.px, _T_2393
node _T_2394 = bits(_WIRE_177, 8, 8)
connect _WIRE_176.pw, _T_2394
node _T_2395 = bits(_WIRE_177, 9, 9)
connect _WIRE_176.hr, _T_2395
node _T_2396 = bits(_WIRE_177, 10, 10)
connect _WIRE_176.hx, _T_2396
node _T_2397 = bits(_WIRE_177, 11, 11)
connect _WIRE_176.hw, _T_2397
node _T_2398 = bits(_WIRE_177, 12, 12)
connect _WIRE_176.sr, _T_2398
node _T_2399 = bits(_WIRE_177, 13, 13)
connect _WIRE_176.sx, _T_2399
node _T_2400 = bits(_WIRE_177, 14, 14)
connect _WIRE_176.sw, _T_2400
node _T_2401 = bits(_WIRE_177, 15, 15)
connect _WIRE_176.gf, _T_2401
node _T_2402 = bits(_WIRE_177, 16, 16)
connect _WIRE_176.pf, _T_2402
node _T_2403 = bits(_WIRE_177, 17, 17)
connect _WIRE_176.ae_stage2, _T_2403
node _T_2404 = bits(_WIRE_177, 18, 18)
connect _WIRE_176.ae_final, _T_2404
node _T_2405 = bits(_WIRE_177, 19, 19)
connect _WIRE_176.ae_ptw, _T_2405
node _T_2406 = bits(_WIRE_177, 20, 20)
connect _WIRE_176.g, _T_2406
node _T_2407 = bits(_WIRE_177, 21, 21)
connect _WIRE_176.u, _T_2407
node _T_2408 = bits(_WIRE_177, 41, 22)
connect _WIRE_176.ppn, _T_2408
wire _WIRE_178 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_179 : UInt<42>
connect _WIRE_179, sectored_entries[0][5].data[1]
node _T_2409 = bits(_WIRE_179, 0, 0)
connect _WIRE_178.fragmented_superpage, _T_2409
node _T_2410 = bits(_WIRE_179, 1, 1)
connect _WIRE_178.c, _T_2410
node _T_2411 = bits(_WIRE_179, 2, 2)
connect _WIRE_178.eff, _T_2411
node _T_2412 = bits(_WIRE_179, 3, 3)
connect _WIRE_178.paa, _T_2412
node _T_2413 = bits(_WIRE_179, 4, 4)
connect _WIRE_178.pal, _T_2413
node _T_2414 = bits(_WIRE_179, 5, 5)
connect _WIRE_178.ppp, _T_2414
node _T_2415 = bits(_WIRE_179, 6, 6)
connect _WIRE_178.pr, _T_2415
node _T_2416 = bits(_WIRE_179, 7, 7)
connect _WIRE_178.px, _T_2416
node _T_2417 = bits(_WIRE_179, 8, 8)
connect _WIRE_178.pw, _T_2417
node _T_2418 = bits(_WIRE_179, 9, 9)
connect _WIRE_178.hr, _T_2418
node _T_2419 = bits(_WIRE_179, 10, 10)
connect _WIRE_178.hx, _T_2419
node _T_2420 = bits(_WIRE_179, 11, 11)
connect _WIRE_178.hw, _T_2420
node _T_2421 = bits(_WIRE_179, 12, 12)
connect _WIRE_178.sr, _T_2421
node _T_2422 = bits(_WIRE_179, 13, 13)
connect _WIRE_178.sx, _T_2422
node _T_2423 = bits(_WIRE_179, 14, 14)
connect _WIRE_178.sw, _T_2423
node _T_2424 = bits(_WIRE_179, 15, 15)
connect _WIRE_178.gf, _T_2424
node _T_2425 = bits(_WIRE_179, 16, 16)
connect _WIRE_178.pf, _T_2425
node _T_2426 = bits(_WIRE_179, 17, 17)
connect _WIRE_178.ae_stage2, _T_2426
node _T_2427 = bits(_WIRE_179, 18, 18)
connect _WIRE_178.ae_final, _T_2427
node _T_2428 = bits(_WIRE_179, 19, 19)
connect _WIRE_178.ae_ptw, _T_2428
node _T_2429 = bits(_WIRE_179, 20, 20)
connect _WIRE_178.g, _T_2429
node _T_2430 = bits(_WIRE_179, 21, 21)
connect _WIRE_178.u, _T_2430
node _T_2431 = bits(_WIRE_179, 41, 22)
connect _WIRE_178.ppn, _T_2431
wire _WIRE_180 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_181 : UInt<42>
connect _WIRE_181, sectored_entries[0][5].data[2]
node _T_2432 = bits(_WIRE_181, 0, 0)
connect _WIRE_180.fragmented_superpage, _T_2432
node _T_2433 = bits(_WIRE_181, 1, 1)
connect _WIRE_180.c, _T_2433
node _T_2434 = bits(_WIRE_181, 2, 2)
connect _WIRE_180.eff, _T_2434
node _T_2435 = bits(_WIRE_181, 3, 3)
connect _WIRE_180.paa, _T_2435
node _T_2436 = bits(_WIRE_181, 4, 4)
connect _WIRE_180.pal, _T_2436
node _T_2437 = bits(_WIRE_181, 5, 5)
connect _WIRE_180.ppp, _T_2437
node _T_2438 = bits(_WIRE_181, 6, 6)
connect _WIRE_180.pr, _T_2438
node _T_2439 = bits(_WIRE_181, 7, 7)
connect _WIRE_180.px, _T_2439
node _T_2440 = bits(_WIRE_181, 8, 8)
connect _WIRE_180.pw, _T_2440
node _T_2441 = bits(_WIRE_181, 9, 9)
connect _WIRE_180.hr, _T_2441
node _T_2442 = bits(_WIRE_181, 10, 10)
connect _WIRE_180.hx, _T_2442
node _T_2443 = bits(_WIRE_181, 11, 11)
connect _WIRE_180.hw, _T_2443
node _T_2444 = bits(_WIRE_181, 12, 12)
connect _WIRE_180.sr, _T_2444
node _T_2445 = bits(_WIRE_181, 13, 13)
connect _WIRE_180.sx, _T_2445
node _T_2446 = bits(_WIRE_181, 14, 14)
connect _WIRE_180.sw, _T_2446
node _T_2447 = bits(_WIRE_181, 15, 15)
connect _WIRE_180.gf, _T_2447
node _T_2448 = bits(_WIRE_181, 16, 16)
connect _WIRE_180.pf, _T_2448
node _T_2449 = bits(_WIRE_181, 17, 17)
connect _WIRE_180.ae_stage2, _T_2449
node _T_2450 = bits(_WIRE_181, 18, 18)
connect _WIRE_180.ae_final, _T_2450
node _T_2451 = bits(_WIRE_181, 19, 19)
connect _WIRE_180.ae_ptw, _T_2451
node _T_2452 = bits(_WIRE_181, 20, 20)
connect _WIRE_180.g, _T_2452
node _T_2453 = bits(_WIRE_181, 21, 21)
connect _WIRE_180.u, _T_2453
node _T_2454 = bits(_WIRE_181, 41, 22)
connect _WIRE_180.ppn, _T_2454
wire _WIRE_182 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_183 : UInt<42>
connect _WIRE_183, sectored_entries[0][5].data[3]
node _T_2455 = bits(_WIRE_183, 0, 0)
connect _WIRE_182.fragmented_superpage, _T_2455
node _T_2456 = bits(_WIRE_183, 1, 1)
connect _WIRE_182.c, _T_2456
node _T_2457 = bits(_WIRE_183, 2, 2)
connect _WIRE_182.eff, _T_2457
node _T_2458 = bits(_WIRE_183, 3, 3)
connect _WIRE_182.paa, _T_2458
node _T_2459 = bits(_WIRE_183, 4, 4)
connect _WIRE_182.pal, _T_2459
node _T_2460 = bits(_WIRE_183, 5, 5)
connect _WIRE_182.ppp, _T_2460
node _T_2461 = bits(_WIRE_183, 6, 6)
connect _WIRE_182.pr, _T_2461
node _T_2462 = bits(_WIRE_183, 7, 7)
connect _WIRE_182.px, _T_2462
node _T_2463 = bits(_WIRE_183, 8, 8)
connect _WIRE_182.pw, _T_2463
node _T_2464 = bits(_WIRE_183, 9, 9)
connect _WIRE_182.hr, _T_2464
node _T_2465 = bits(_WIRE_183, 10, 10)
connect _WIRE_182.hx, _T_2465
node _T_2466 = bits(_WIRE_183, 11, 11)
connect _WIRE_182.hw, _T_2466
node _T_2467 = bits(_WIRE_183, 12, 12)
connect _WIRE_182.sr, _T_2467
node _T_2468 = bits(_WIRE_183, 13, 13)
connect _WIRE_182.sx, _T_2468
node _T_2469 = bits(_WIRE_183, 14, 14)
connect _WIRE_182.sw, _T_2469
node _T_2470 = bits(_WIRE_183, 15, 15)
connect _WIRE_182.gf, _T_2470
node _T_2471 = bits(_WIRE_183, 16, 16)
connect _WIRE_182.pf, _T_2471
node _T_2472 = bits(_WIRE_183, 17, 17)
connect _WIRE_182.ae_stage2, _T_2472
node _T_2473 = bits(_WIRE_183, 18, 18)
connect _WIRE_182.ae_final, _T_2473
node _T_2474 = bits(_WIRE_183, 19, 19)
connect _WIRE_182.ae_ptw, _T_2474
node _T_2475 = bits(_WIRE_183, 20, 20)
connect _WIRE_182.g, _T_2475
node _T_2476 = bits(_WIRE_183, 21, 21)
connect _WIRE_182.u, _T_2476
node _T_2477 = bits(_WIRE_183, 41, 22)
connect _WIRE_182.ppn, _T_2477
node _T_2478 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2479 = eq(_WIRE_176.g, UInt<1>(0h0))
node _T_2480 = and(_T_2478, _T_2479)
when _T_2480 :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
node _T_2481 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2482 = eq(_WIRE_178.g, UInt<1>(0h0))
node _T_2483 = and(_T_2481, _T_2482)
when _T_2483 :
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
node _T_2484 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2485 = eq(_WIRE_180.g, UInt<1>(0h0))
node _T_2486 = and(_T_2484, _T_2485)
when _T_2486 :
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
node _T_2487 = eq(sectored_entries[0][5].tag_v, hv_5)
node _T_2488 = eq(_WIRE_182.g, UInt<1>(0h0))
node _T_2489 = and(_T_2487, _T_2488)
when _T_2489 :
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
else :
node _T_2490 = or(hv_5, hg_5)
wire _WIRE_184 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_185 : UInt<42>
connect _WIRE_185, sectored_entries[0][5].data[0]
node _T_2491 = bits(_WIRE_185, 0, 0)
connect _WIRE_184.fragmented_superpage, _T_2491
node _T_2492 = bits(_WIRE_185, 1, 1)
connect _WIRE_184.c, _T_2492
node _T_2493 = bits(_WIRE_185, 2, 2)
connect _WIRE_184.eff, _T_2493
node _T_2494 = bits(_WIRE_185, 3, 3)
connect _WIRE_184.paa, _T_2494
node _T_2495 = bits(_WIRE_185, 4, 4)
connect _WIRE_184.pal, _T_2495
node _T_2496 = bits(_WIRE_185, 5, 5)
connect _WIRE_184.ppp, _T_2496
node _T_2497 = bits(_WIRE_185, 6, 6)
connect _WIRE_184.pr, _T_2497
node _T_2498 = bits(_WIRE_185, 7, 7)
connect _WIRE_184.px, _T_2498
node _T_2499 = bits(_WIRE_185, 8, 8)
connect _WIRE_184.pw, _T_2499
node _T_2500 = bits(_WIRE_185, 9, 9)
connect _WIRE_184.hr, _T_2500
node _T_2501 = bits(_WIRE_185, 10, 10)
connect _WIRE_184.hx, _T_2501
node _T_2502 = bits(_WIRE_185, 11, 11)
connect _WIRE_184.hw, _T_2502
node _T_2503 = bits(_WIRE_185, 12, 12)
connect _WIRE_184.sr, _T_2503
node _T_2504 = bits(_WIRE_185, 13, 13)
connect _WIRE_184.sx, _T_2504
node _T_2505 = bits(_WIRE_185, 14, 14)
connect _WIRE_184.sw, _T_2505
node _T_2506 = bits(_WIRE_185, 15, 15)
connect _WIRE_184.gf, _T_2506
node _T_2507 = bits(_WIRE_185, 16, 16)
connect _WIRE_184.pf, _T_2507
node _T_2508 = bits(_WIRE_185, 17, 17)
connect _WIRE_184.ae_stage2, _T_2508
node _T_2509 = bits(_WIRE_185, 18, 18)
connect _WIRE_184.ae_final, _T_2509
node _T_2510 = bits(_WIRE_185, 19, 19)
connect _WIRE_184.ae_ptw, _T_2510
node _T_2511 = bits(_WIRE_185, 20, 20)
connect _WIRE_184.g, _T_2511
node _T_2512 = bits(_WIRE_185, 21, 21)
connect _WIRE_184.u, _T_2512
node _T_2513 = bits(_WIRE_185, 41, 22)
connect _WIRE_184.ppn, _T_2513
wire _WIRE_186 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_187 : UInt<42>
connect _WIRE_187, sectored_entries[0][5].data[1]
node _T_2514 = bits(_WIRE_187, 0, 0)
connect _WIRE_186.fragmented_superpage, _T_2514
node _T_2515 = bits(_WIRE_187, 1, 1)
connect _WIRE_186.c, _T_2515
node _T_2516 = bits(_WIRE_187, 2, 2)
connect _WIRE_186.eff, _T_2516
node _T_2517 = bits(_WIRE_187, 3, 3)
connect _WIRE_186.paa, _T_2517
node _T_2518 = bits(_WIRE_187, 4, 4)
connect _WIRE_186.pal, _T_2518
node _T_2519 = bits(_WIRE_187, 5, 5)
connect _WIRE_186.ppp, _T_2519
node _T_2520 = bits(_WIRE_187, 6, 6)
connect _WIRE_186.pr, _T_2520
node _T_2521 = bits(_WIRE_187, 7, 7)
connect _WIRE_186.px, _T_2521
node _T_2522 = bits(_WIRE_187, 8, 8)
connect _WIRE_186.pw, _T_2522
node _T_2523 = bits(_WIRE_187, 9, 9)
connect _WIRE_186.hr, _T_2523
node _T_2524 = bits(_WIRE_187, 10, 10)
connect _WIRE_186.hx, _T_2524
node _T_2525 = bits(_WIRE_187, 11, 11)
connect _WIRE_186.hw, _T_2525
node _T_2526 = bits(_WIRE_187, 12, 12)
connect _WIRE_186.sr, _T_2526
node _T_2527 = bits(_WIRE_187, 13, 13)
connect _WIRE_186.sx, _T_2527
node _T_2528 = bits(_WIRE_187, 14, 14)
connect _WIRE_186.sw, _T_2528
node _T_2529 = bits(_WIRE_187, 15, 15)
connect _WIRE_186.gf, _T_2529
node _T_2530 = bits(_WIRE_187, 16, 16)
connect _WIRE_186.pf, _T_2530
node _T_2531 = bits(_WIRE_187, 17, 17)
connect _WIRE_186.ae_stage2, _T_2531
node _T_2532 = bits(_WIRE_187, 18, 18)
connect _WIRE_186.ae_final, _T_2532
node _T_2533 = bits(_WIRE_187, 19, 19)
connect _WIRE_186.ae_ptw, _T_2533
node _T_2534 = bits(_WIRE_187, 20, 20)
connect _WIRE_186.g, _T_2534
node _T_2535 = bits(_WIRE_187, 21, 21)
connect _WIRE_186.u, _T_2535
node _T_2536 = bits(_WIRE_187, 41, 22)
connect _WIRE_186.ppn, _T_2536
wire _WIRE_188 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_189 : UInt<42>
connect _WIRE_189, sectored_entries[0][5].data[2]
node _T_2537 = bits(_WIRE_189, 0, 0)
connect _WIRE_188.fragmented_superpage, _T_2537
node _T_2538 = bits(_WIRE_189, 1, 1)
connect _WIRE_188.c, _T_2538
node _T_2539 = bits(_WIRE_189, 2, 2)
connect _WIRE_188.eff, _T_2539
node _T_2540 = bits(_WIRE_189, 3, 3)
connect _WIRE_188.paa, _T_2540
node _T_2541 = bits(_WIRE_189, 4, 4)
connect _WIRE_188.pal, _T_2541
node _T_2542 = bits(_WIRE_189, 5, 5)
connect _WIRE_188.ppp, _T_2542
node _T_2543 = bits(_WIRE_189, 6, 6)
connect _WIRE_188.pr, _T_2543
node _T_2544 = bits(_WIRE_189, 7, 7)
connect _WIRE_188.px, _T_2544
node _T_2545 = bits(_WIRE_189, 8, 8)
connect _WIRE_188.pw, _T_2545
node _T_2546 = bits(_WIRE_189, 9, 9)
connect _WIRE_188.hr, _T_2546
node _T_2547 = bits(_WIRE_189, 10, 10)
connect _WIRE_188.hx, _T_2547
node _T_2548 = bits(_WIRE_189, 11, 11)
connect _WIRE_188.hw, _T_2548
node _T_2549 = bits(_WIRE_189, 12, 12)
connect _WIRE_188.sr, _T_2549
node _T_2550 = bits(_WIRE_189, 13, 13)
connect _WIRE_188.sx, _T_2550
node _T_2551 = bits(_WIRE_189, 14, 14)
connect _WIRE_188.sw, _T_2551
node _T_2552 = bits(_WIRE_189, 15, 15)
connect _WIRE_188.gf, _T_2552
node _T_2553 = bits(_WIRE_189, 16, 16)
connect _WIRE_188.pf, _T_2553
node _T_2554 = bits(_WIRE_189, 17, 17)
connect _WIRE_188.ae_stage2, _T_2554
node _T_2555 = bits(_WIRE_189, 18, 18)
connect _WIRE_188.ae_final, _T_2555
node _T_2556 = bits(_WIRE_189, 19, 19)
connect _WIRE_188.ae_ptw, _T_2556
node _T_2557 = bits(_WIRE_189, 20, 20)
connect _WIRE_188.g, _T_2557
node _T_2558 = bits(_WIRE_189, 21, 21)
connect _WIRE_188.u, _T_2558
node _T_2559 = bits(_WIRE_189, 41, 22)
connect _WIRE_188.ppn, _T_2559
wire _WIRE_190 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_191 : UInt<42>
connect _WIRE_191, sectored_entries[0][5].data[3]
node _T_2560 = bits(_WIRE_191, 0, 0)
connect _WIRE_190.fragmented_superpage, _T_2560
node _T_2561 = bits(_WIRE_191, 1, 1)
connect _WIRE_190.c, _T_2561
node _T_2562 = bits(_WIRE_191, 2, 2)
connect _WIRE_190.eff, _T_2562
node _T_2563 = bits(_WIRE_191, 3, 3)
connect _WIRE_190.paa, _T_2563
node _T_2564 = bits(_WIRE_191, 4, 4)
connect _WIRE_190.pal, _T_2564
node _T_2565 = bits(_WIRE_191, 5, 5)
connect _WIRE_190.ppp, _T_2565
node _T_2566 = bits(_WIRE_191, 6, 6)
connect _WIRE_190.pr, _T_2566
node _T_2567 = bits(_WIRE_191, 7, 7)
connect _WIRE_190.px, _T_2567
node _T_2568 = bits(_WIRE_191, 8, 8)
connect _WIRE_190.pw, _T_2568
node _T_2569 = bits(_WIRE_191, 9, 9)
connect _WIRE_190.hr, _T_2569
node _T_2570 = bits(_WIRE_191, 10, 10)
connect _WIRE_190.hx, _T_2570
node _T_2571 = bits(_WIRE_191, 11, 11)
connect _WIRE_190.hw, _T_2571
node _T_2572 = bits(_WIRE_191, 12, 12)
connect _WIRE_190.sr, _T_2572
node _T_2573 = bits(_WIRE_191, 13, 13)
connect _WIRE_190.sx, _T_2573
node _T_2574 = bits(_WIRE_191, 14, 14)
connect _WIRE_190.sw, _T_2574
node _T_2575 = bits(_WIRE_191, 15, 15)
connect _WIRE_190.gf, _T_2575
node _T_2576 = bits(_WIRE_191, 16, 16)
connect _WIRE_190.pf, _T_2576
node _T_2577 = bits(_WIRE_191, 17, 17)
connect _WIRE_190.ae_stage2, _T_2577
node _T_2578 = bits(_WIRE_191, 18, 18)
connect _WIRE_190.ae_final, _T_2578
node _T_2579 = bits(_WIRE_191, 19, 19)
connect _WIRE_190.ae_ptw, _T_2579
node _T_2580 = bits(_WIRE_191, 20, 20)
connect _WIRE_190.g, _T_2580
node _T_2581 = bits(_WIRE_191, 21, 21)
connect _WIRE_190.u, _T_2581
node _T_2582 = bits(_WIRE_191, 41, 22)
connect _WIRE_190.ppn, _T_2582
node _T_2583 = eq(sectored_entries[0][5].tag_v, _T_2490)
when _T_2583 :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
node _T_2584 = eq(sectored_entries[0][5].tag_v, _T_2490)
when _T_2584 :
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
node _T_2585 = eq(sectored_entries[0][5].tag_v, _T_2490)
when _T_2585 :
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
node _T_2586 = eq(sectored_entries[0][5].tag_v, _T_2490)
when _T_2586 :
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
node hv_6 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_6 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_2587 = eq(hg_6, UInt<1>(0h0))
node _T_2588 = and(_T_2587, io.sfence.bits.rs1)
when _T_2588 :
node _T_2589 = xor(sectored_entries[0][6].tag_vpn, vpn)
node _T_2590 = shr(_T_2589, 2)
node _T_2591 = eq(_T_2590, UInt<1>(0h0))
node _T_2592 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2593 = and(_T_2591, _T_2592)
when _T_2593 :
wire _WIRE_192 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_193 : UInt<42>
connect _WIRE_193, sectored_entries[0][6].data[0]
node _T_2594 = bits(_WIRE_193, 0, 0)
connect _WIRE_192.fragmented_superpage, _T_2594
node _T_2595 = bits(_WIRE_193, 1, 1)
connect _WIRE_192.c, _T_2595
node _T_2596 = bits(_WIRE_193, 2, 2)
connect _WIRE_192.eff, _T_2596
node _T_2597 = bits(_WIRE_193, 3, 3)
connect _WIRE_192.paa, _T_2597
node _T_2598 = bits(_WIRE_193, 4, 4)
connect _WIRE_192.pal, _T_2598
node _T_2599 = bits(_WIRE_193, 5, 5)
connect _WIRE_192.ppp, _T_2599
node _T_2600 = bits(_WIRE_193, 6, 6)
connect _WIRE_192.pr, _T_2600
node _T_2601 = bits(_WIRE_193, 7, 7)
connect _WIRE_192.px, _T_2601
node _T_2602 = bits(_WIRE_193, 8, 8)
connect _WIRE_192.pw, _T_2602
node _T_2603 = bits(_WIRE_193, 9, 9)
connect _WIRE_192.hr, _T_2603
node _T_2604 = bits(_WIRE_193, 10, 10)
connect _WIRE_192.hx, _T_2604
node _T_2605 = bits(_WIRE_193, 11, 11)
connect _WIRE_192.hw, _T_2605
node _T_2606 = bits(_WIRE_193, 12, 12)
connect _WIRE_192.sr, _T_2606
node _T_2607 = bits(_WIRE_193, 13, 13)
connect _WIRE_192.sx, _T_2607
node _T_2608 = bits(_WIRE_193, 14, 14)
connect _WIRE_192.sw, _T_2608
node _T_2609 = bits(_WIRE_193, 15, 15)
connect _WIRE_192.gf, _T_2609
node _T_2610 = bits(_WIRE_193, 16, 16)
connect _WIRE_192.pf, _T_2610
node _T_2611 = bits(_WIRE_193, 17, 17)
connect _WIRE_192.ae_stage2, _T_2611
node _T_2612 = bits(_WIRE_193, 18, 18)
connect _WIRE_192.ae_final, _T_2612
node _T_2613 = bits(_WIRE_193, 19, 19)
connect _WIRE_192.ae_ptw, _T_2613
node _T_2614 = bits(_WIRE_193, 20, 20)
connect _WIRE_192.g, _T_2614
node _T_2615 = bits(_WIRE_193, 21, 21)
connect _WIRE_192.u, _T_2615
node _T_2616 = bits(_WIRE_193, 41, 22)
connect _WIRE_192.ppn, _T_2616
wire _WIRE_194 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_195 : UInt<42>
connect _WIRE_195, sectored_entries[0][6].data[1]
node _T_2617 = bits(_WIRE_195, 0, 0)
connect _WIRE_194.fragmented_superpage, _T_2617
node _T_2618 = bits(_WIRE_195, 1, 1)
connect _WIRE_194.c, _T_2618
node _T_2619 = bits(_WIRE_195, 2, 2)
connect _WIRE_194.eff, _T_2619
node _T_2620 = bits(_WIRE_195, 3, 3)
connect _WIRE_194.paa, _T_2620
node _T_2621 = bits(_WIRE_195, 4, 4)
connect _WIRE_194.pal, _T_2621
node _T_2622 = bits(_WIRE_195, 5, 5)
connect _WIRE_194.ppp, _T_2622
node _T_2623 = bits(_WIRE_195, 6, 6)
connect _WIRE_194.pr, _T_2623
node _T_2624 = bits(_WIRE_195, 7, 7)
connect _WIRE_194.px, _T_2624
node _T_2625 = bits(_WIRE_195, 8, 8)
connect _WIRE_194.pw, _T_2625
node _T_2626 = bits(_WIRE_195, 9, 9)
connect _WIRE_194.hr, _T_2626
node _T_2627 = bits(_WIRE_195, 10, 10)
connect _WIRE_194.hx, _T_2627
node _T_2628 = bits(_WIRE_195, 11, 11)
connect _WIRE_194.hw, _T_2628
node _T_2629 = bits(_WIRE_195, 12, 12)
connect _WIRE_194.sr, _T_2629
node _T_2630 = bits(_WIRE_195, 13, 13)
connect _WIRE_194.sx, _T_2630
node _T_2631 = bits(_WIRE_195, 14, 14)
connect _WIRE_194.sw, _T_2631
node _T_2632 = bits(_WIRE_195, 15, 15)
connect _WIRE_194.gf, _T_2632
node _T_2633 = bits(_WIRE_195, 16, 16)
connect _WIRE_194.pf, _T_2633
node _T_2634 = bits(_WIRE_195, 17, 17)
connect _WIRE_194.ae_stage2, _T_2634
node _T_2635 = bits(_WIRE_195, 18, 18)
connect _WIRE_194.ae_final, _T_2635
node _T_2636 = bits(_WIRE_195, 19, 19)
connect _WIRE_194.ae_ptw, _T_2636
node _T_2637 = bits(_WIRE_195, 20, 20)
connect _WIRE_194.g, _T_2637
node _T_2638 = bits(_WIRE_195, 21, 21)
connect _WIRE_194.u, _T_2638
node _T_2639 = bits(_WIRE_195, 41, 22)
connect _WIRE_194.ppn, _T_2639
wire _WIRE_196 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_197 : UInt<42>
connect _WIRE_197, sectored_entries[0][6].data[2]
node _T_2640 = bits(_WIRE_197, 0, 0)
connect _WIRE_196.fragmented_superpage, _T_2640
node _T_2641 = bits(_WIRE_197, 1, 1)
connect _WIRE_196.c, _T_2641
node _T_2642 = bits(_WIRE_197, 2, 2)
connect _WIRE_196.eff, _T_2642
node _T_2643 = bits(_WIRE_197, 3, 3)
connect _WIRE_196.paa, _T_2643
node _T_2644 = bits(_WIRE_197, 4, 4)
connect _WIRE_196.pal, _T_2644
node _T_2645 = bits(_WIRE_197, 5, 5)
connect _WIRE_196.ppp, _T_2645
node _T_2646 = bits(_WIRE_197, 6, 6)
connect _WIRE_196.pr, _T_2646
node _T_2647 = bits(_WIRE_197, 7, 7)
connect _WIRE_196.px, _T_2647
node _T_2648 = bits(_WIRE_197, 8, 8)
connect _WIRE_196.pw, _T_2648
node _T_2649 = bits(_WIRE_197, 9, 9)
connect _WIRE_196.hr, _T_2649
node _T_2650 = bits(_WIRE_197, 10, 10)
connect _WIRE_196.hx, _T_2650
node _T_2651 = bits(_WIRE_197, 11, 11)
connect _WIRE_196.hw, _T_2651
node _T_2652 = bits(_WIRE_197, 12, 12)
connect _WIRE_196.sr, _T_2652
node _T_2653 = bits(_WIRE_197, 13, 13)
connect _WIRE_196.sx, _T_2653
node _T_2654 = bits(_WIRE_197, 14, 14)
connect _WIRE_196.sw, _T_2654
node _T_2655 = bits(_WIRE_197, 15, 15)
connect _WIRE_196.gf, _T_2655
node _T_2656 = bits(_WIRE_197, 16, 16)
connect _WIRE_196.pf, _T_2656
node _T_2657 = bits(_WIRE_197, 17, 17)
connect _WIRE_196.ae_stage2, _T_2657
node _T_2658 = bits(_WIRE_197, 18, 18)
connect _WIRE_196.ae_final, _T_2658
node _T_2659 = bits(_WIRE_197, 19, 19)
connect _WIRE_196.ae_ptw, _T_2659
node _T_2660 = bits(_WIRE_197, 20, 20)
connect _WIRE_196.g, _T_2660
node _T_2661 = bits(_WIRE_197, 21, 21)
connect _WIRE_196.u, _T_2661
node _T_2662 = bits(_WIRE_197, 41, 22)
connect _WIRE_196.ppn, _T_2662
wire _WIRE_198 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_199 : UInt<42>
connect _WIRE_199, sectored_entries[0][6].data[3]
node _T_2663 = bits(_WIRE_199, 0, 0)
connect _WIRE_198.fragmented_superpage, _T_2663
node _T_2664 = bits(_WIRE_199, 1, 1)
connect _WIRE_198.c, _T_2664
node _T_2665 = bits(_WIRE_199, 2, 2)
connect _WIRE_198.eff, _T_2665
node _T_2666 = bits(_WIRE_199, 3, 3)
connect _WIRE_198.paa, _T_2666
node _T_2667 = bits(_WIRE_199, 4, 4)
connect _WIRE_198.pal, _T_2667
node _T_2668 = bits(_WIRE_199, 5, 5)
connect _WIRE_198.ppp, _T_2668
node _T_2669 = bits(_WIRE_199, 6, 6)
connect _WIRE_198.pr, _T_2669
node _T_2670 = bits(_WIRE_199, 7, 7)
connect _WIRE_198.px, _T_2670
node _T_2671 = bits(_WIRE_199, 8, 8)
connect _WIRE_198.pw, _T_2671
node _T_2672 = bits(_WIRE_199, 9, 9)
connect _WIRE_198.hr, _T_2672
node _T_2673 = bits(_WIRE_199, 10, 10)
connect _WIRE_198.hx, _T_2673
node _T_2674 = bits(_WIRE_199, 11, 11)
connect _WIRE_198.hw, _T_2674
node _T_2675 = bits(_WIRE_199, 12, 12)
connect _WIRE_198.sr, _T_2675
node _T_2676 = bits(_WIRE_199, 13, 13)
connect _WIRE_198.sx, _T_2676
node _T_2677 = bits(_WIRE_199, 14, 14)
connect _WIRE_198.sw, _T_2677
node _T_2678 = bits(_WIRE_199, 15, 15)
connect _WIRE_198.gf, _T_2678
node _T_2679 = bits(_WIRE_199, 16, 16)
connect _WIRE_198.pf, _T_2679
node _T_2680 = bits(_WIRE_199, 17, 17)
connect _WIRE_198.ae_stage2, _T_2680
node _T_2681 = bits(_WIRE_199, 18, 18)
connect _WIRE_198.ae_final, _T_2681
node _T_2682 = bits(_WIRE_199, 19, 19)
connect _WIRE_198.ae_ptw, _T_2682
node _T_2683 = bits(_WIRE_199, 20, 20)
connect _WIRE_198.g, _T_2683
node _T_2684 = bits(_WIRE_199, 21, 21)
connect _WIRE_198.u, _T_2684
node _T_2685 = bits(_WIRE_199, 41, 22)
connect _WIRE_198.ppn, _T_2685
node _T_2686 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2687 = bits(vpn, 1, 0)
node _T_2688 = eq(UInt<1>(0h0), _T_2687)
node _T_2689 = and(_T_2686, _T_2688)
when _T_2689 :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
node _T_2690 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2691 = bits(vpn, 1, 0)
node _T_2692 = eq(UInt<1>(0h1), _T_2691)
node _T_2693 = and(_T_2690, _T_2692)
when _T_2693 :
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
node _T_2694 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2695 = bits(vpn, 1, 0)
node _T_2696 = eq(UInt<2>(0h2), _T_2695)
node _T_2697 = and(_T_2694, _T_2696)
when _T_2697 :
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
node _T_2698 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2699 = bits(vpn, 1, 0)
node _T_2700 = eq(UInt<2>(0h3), _T_2699)
node _T_2701 = and(_T_2698, _T_2700)
when _T_2701 :
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
node _T_2702 = xor(sectored_entries[0][6].tag_vpn, vpn)
node _T_2703 = shr(_T_2702, 18)
node _T_2704 = eq(_T_2703, UInt<1>(0h0))
when _T_2704 :
wire _WIRE_200 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_201 : UInt<42>
connect _WIRE_201, sectored_entries[0][6].data[0]
node _T_2705 = bits(_WIRE_201, 0, 0)
connect _WIRE_200.fragmented_superpage, _T_2705
node _T_2706 = bits(_WIRE_201, 1, 1)
connect _WIRE_200.c, _T_2706
node _T_2707 = bits(_WIRE_201, 2, 2)
connect _WIRE_200.eff, _T_2707
node _T_2708 = bits(_WIRE_201, 3, 3)
connect _WIRE_200.paa, _T_2708
node _T_2709 = bits(_WIRE_201, 4, 4)
connect _WIRE_200.pal, _T_2709
node _T_2710 = bits(_WIRE_201, 5, 5)
connect _WIRE_200.ppp, _T_2710
node _T_2711 = bits(_WIRE_201, 6, 6)
connect _WIRE_200.pr, _T_2711
node _T_2712 = bits(_WIRE_201, 7, 7)
connect _WIRE_200.px, _T_2712
node _T_2713 = bits(_WIRE_201, 8, 8)
connect _WIRE_200.pw, _T_2713
node _T_2714 = bits(_WIRE_201, 9, 9)
connect _WIRE_200.hr, _T_2714
node _T_2715 = bits(_WIRE_201, 10, 10)
connect _WIRE_200.hx, _T_2715
node _T_2716 = bits(_WIRE_201, 11, 11)
connect _WIRE_200.hw, _T_2716
node _T_2717 = bits(_WIRE_201, 12, 12)
connect _WIRE_200.sr, _T_2717
node _T_2718 = bits(_WIRE_201, 13, 13)
connect _WIRE_200.sx, _T_2718
node _T_2719 = bits(_WIRE_201, 14, 14)
connect _WIRE_200.sw, _T_2719
node _T_2720 = bits(_WIRE_201, 15, 15)
connect _WIRE_200.gf, _T_2720
node _T_2721 = bits(_WIRE_201, 16, 16)
connect _WIRE_200.pf, _T_2721
node _T_2722 = bits(_WIRE_201, 17, 17)
connect _WIRE_200.ae_stage2, _T_2722
node _T_2723 = bits(_WIRE_201, 18, 18)
connect _WIRE_200.ae_final, _T_2723
node _T_2724 = bits(_WIRE_201, 19, 19)
connect _WIRE_200.ae_ptw, _T_2724
node _T_2725 = bits(_WIRE_201, 20, 20)
connect _WIRE_200.g, _T_2725
node _T_2726 = bits(_WIRE_201, 21, 21)
connect _WIRE_200.u, _T_2726
node _T_2727 = bits(_WIRE_201, 41, 22)
connect _WIRE_200.ppn, _T_2727
wire _WIRE_202 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_203 : UInt<42>
connect _WIRE_203, sectored_entries[0][6].data[1]
node _T_2728 = bits(_WIRE_203, 0, 0)
connect _WIRE_202.fragmented_superpage, _T_2728
node _T_2729 = bits(_WIRE_203, 1, 1)
connect _WIRE_202.c, _T_2729
node _T_2730 = bits(_WIRE_203, 2, 2)
connect _WIRE_202.eff, _T_2730
node _T_2731 = bits(_WIRE_203, 3, 3)
connect _WIRE_202.paa, _T_2731
node _T_2732 = bits(_WIRE_203, 4, 4)
connect _WIRE_202.pal, _T_2732
node _T_2733 = bits(_WIRE_203, 5, 5)
connect _WIRE_202.ppp, _T_2733
node _T_2734 = bits(_WIRE_203, 6, 6)
connect _WIRE_202.pr, _T_2734
node _T_2735 = bits(_WIRE_203, 7, 7)
connect _WIRE_202.px, _T_2735
node _T_2736 = bits(_WIRE_203, 8, 8)
connect _WIRE_202.pw, _T_2736
node _T_2737 = bits(_WIRE_203, 9, 9)
connect _WIRE_202.hr, _T_2737
node _T_2738 = bits(_WIRE_203, 10, 10)
connect _WIRE_202.hx, _T_2738
node _T_2739 = bits(_WIRE_203, 11, 11)
connect _WIRE_202.hw, _T_2739
node _T_2740 = bits(_WIRE_203, 12, 12)
connect _WIRE_202.sr, _T_2740
node _T_2741 = bits(_WIRE_203, 13, 13)
connect _WIRE_202.sx, _T_2741
node _T_2742 = bits(_WIRE_203, 14, 14)
connect _WIRE_202.sw, _T_2742
node _T_2743 = bits(_WIRE_203, 15, 15)
connect _WIRE_202.gf, _T_2743
node _T_2744 = bits(_WIRE_203, 16, 16)
connect _WIRE_202.pf, _T_2744
node _T_2745 = bits(_WIRE_203, 17, 17)
connect _WIRE_202.ae_stage2, _T_2745
node _T_2746 = bits(_WIRE_203, 18, 18)
connect _WIRE_202.ae_final, _T_2746
node _T_2747 = bits(_WIRE_203, 19, 19)
connect _WIRE_202.ae_ptw, _T_2747
node _T_2748 = bits(_WIRE_203, 20, 20)
connect _WIRE_202.g, _T_2748
node _T_2749 = bits(_WIRE_203, 21, 21)
connect _WIRE_202.u, _T_2749
node _T_2750 = bits(_WIRE_203, 41, 22)
connect _WIRE_202.ppn, _T_2750
wire _WIRE_204 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_205 : UInt<42>
connect _WIRE_205, sectored_entries[0][6].data[2]
node _T_2751 = bits(_WIRE_205, 0, 0)
connect _WIRE_204.fragmented_superpage, _T_2751
node _T_2752 = bits(_WIRE_205, 1, 1)
connect _WIRE_204.c, _T_2752
node _T_2753 = bits(_WIRE_205, 2, 2)
connect _WIRE_204.eff, _T_2753
node _T_2754 = bits(_WIRE_205, 3, 3)
connect _WIRE_204.paa, _T_2754
node _T_2755 = bits(_WIRE_205, 4, 4)
connect _WIRE_204.pal, _T_2755
node _T_2756 = bits(_WIRE_205, 5, 5)
connect _WIRE_204.ppp, _T_2756
node _T_2757 = bits(_WIRE_205, 6, 6)
connect _WIRE_204.pr, _T_2757
node _T_2758 = bits(_WIRE_205, 7, 7)
connect _WIRE_204.px, _T_2758
node _T_2759 = bits(_WIRE_205, 8, 8)
connect _WIRE_204.pw, _T_2759
node _T_2760 = bits(_WIRE_205, 9, 9)
connect _WIRE_204.hr, _T_2760
node _T_2761 = bits(_WIRE_205, 10, 10)
connect _WIRE_204.hx, _T_2761
node _T_2762 = bits(_WIRE_205, 11, 11)
connect _WIRE_204.hw, _T_2762
node _T_2763 = bits(_WIRE_205, 12, 12)
connect _WIRE_204.sr, _T_2763
node _T_2764 = bits(_WIRE_205, 13, 13)
connect _WIRE_204.sx, _T_2764
node _T_2765 = bits(_WIRE_205, 14, 14)
connect _WIRE_204.sw, _T_2765
node _T_2766 = bits(_WIRE_205, 15, 15)
connect _WIRE_204.gf, _T_2766
node _T_2767 = bits(_WIRE_205, 16, 16)
connect _WIRE_204.pf, _T_2767
node _T_2768 = bits(_WIRE_205, 17, 17)
connect _WIRE_204.ae_stage2, _T_2768
node _T_2769 = bits(_WIRE_205, 18, 18)
connect _WIRE_204.ae_final, _T_2769
node _T_2770 = bits(_WIRE_205, 19, 19)
connect _WIRE_204.ae_ptw, _T_2770
node _T_2771 = bits(_WIRE_205, 20, 20)
connect _WIRE_204.g, _T_2771
node _T_2772 = bits(_WIRE_205, 21, 21)
connect _WIRE_204.u, _T_2772
node _T_2773 = bits(_WIRE_205, 41, 22)
connect _WIRE_204.ppn, _T_2773
wire _WIRE_206 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_207 : UInt<42>
connect _WIRE_207, sectored_entries[0][6].data[3]
node _T_2774 = bits(_WIRE_207, 0, 0)
connect _WIRE_206.fragmented_superpage, _T_2774
node _T_2775 = bits(_WIRE_207, 1, 1)
connect _WIRE_206.c, _T_2775
node _T_2776 = bits(_WIRE_207, 2, 2)
connect _WIRE_206.eff, _T_2776
node _T_2777 = bits(_WIRE_207, 3, 3)
connect _WIRE_206.paa, _T_2777
node _T_2778 = bits(_WIRE_207, 4, 4)
connect _WIRE_206.pal, _T_2778
node _T_2779 = bits(_WIRE_207, 5, 5)
connect _WIRE_206.ppp, _T_2779
node _T_2780 = bits(_WIRE_207, 6, 6)
connect _WIRE_206.pr, _T_2780
node _T_2781 = bits(_WIRE_207, 7, 7)
connect _WIRE_206.px, _T_2781
node _T_2782 = bits(_WIRE_207, 8, 8)
connect _WIRE_206.pw, _T_2782
node _T_2783 = bits(_WIRE_207, 9, 9)
connect _WIRE_206.hr, _T_2783
node _T_2784 = bits(_WIRE_207, 10, 10)
connect _WIRE_206.hx, _T_2784
node _T_2785 = bits(_WIRE_207, 11, 11)
connect _WIRE_206.hw, _T_2785
node _T_2786 = bits(_WIRE_207, 12, 12)
connect _WIRE_206.sr, _T_2786
node _T_2787 = bits(_WIRE_207, 13, 13)
connect _WIRE_206.sx, _T_2787
node _T_2788 = bits(_WIRE_207, 14, 14)
connect _WIRE_206.sw, _T_2788
node _T_2789 = bits(_WIRE_207, 15, 15)
connect _WIRE_206.gf, _T_2789
node _T_2790 = bits(_WIRE_207, 16, 16)
connect _WIRE_206.pf, _T_2790
node _T_2791 = bits(_WIRE_207, 17, 17)
connect _WIRE_206.ae_stage2, _T_2791
node _T_2792 = bits(_WIRE_207, 18, 18)
connect _WIRE_206.ae_final, _T_2792
node _T_2793 = bits(_WIRE_207, 19, 19)
connect _WIRE_206.ae_ptw, _T_2793
node _T_2794 = bits(_WIRE_207, 20, 20)
connect _WIRE_206.g, _T_2794
node _T_2795 = bits(_WIRE_207, 21, 21)
connect _WIRE_206.u, _T_2795
node _T_2796 = bits(_WIRE_207, 41, 22)
connect _WIRE_206.ppn, _T_2796
node _T_2797 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2798 = and(_T_2797, _WIRE_200.fragmented_superpage)
when _T_2798 :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
node _T_2799 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2800 = and(_T_2799, _WIRE_202.fragmented_superpage)
when _T_2800 :
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
node _T_2801 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2802 = and(_T_2801, _WIRE_204.fragmented_superpage)
when _T_2802 :
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
node _T_2803 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2804 = and(_T_2803, _WIRE_206.fragmented_superpage)
when _T_2804 :
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
else :
node _T_2805 = eq(hg_6, UInt<1>(0h0))
node _T_2806 = and(_T_2805, io.sfence.bits.rs2)
when _T_2806 :
wire _WIRE_208 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_209 : UInt<42>
connect _WIRE_209, sectored_entries[0][6].data[0]
node _T_2807 = bits(_WIRE_209, 0, 0)
connect _WIRE_208.fragmented_superpage, _T_2807
node _T_2808 = bits(_WIRE_209, 1, 1)
connect _WIRE_208.c, _T_2808
node _T_2809 = bits(_WIRE_209, 2, 2)
connect _WIRE_208.eff, _T_2809
node _T_2810 = bits(_WIRE_209, 3, 3)
connect _WIRE_208.paa, _T_2810
node _T_2811 = bits(_WIRE_209, 4, 4)
connect _WIRE_208.pal, _T_2811
node _T_2812 = bits(_WIRE_209, 5, 5)
connect _WIRE_208.ppp, _T_2812
node _T_2813 = bits(_WIRE_209, 6, 6)
connect _WIRE_208.pr, _T_2813
node _T_2814 = bits(_WIRE_209, 7, 7)
connect _WIRE_208.px, _T_2814
node _T_2815 = bits(_WIRE_209, 8, 8)
connect _WIRE_208.pw, _T_2815
node _T_2816 = bits(_WIRE_209, 9, 9)
connect _WIRE_208.hr, _T_2816
node _T_2817 = bits(_WIRE_209, 10, 10)
connect _WIRE_208.hx, _T_2817
node _T_2818 = bits(_WIRE_209, 11, 11)
connect _WIRE_208.hw, _T_2818
node _T_2819 = bits(_WIRE_209, 12, 12)
connect _WIRE_208.sr, _T_2819
node _T_2820 = bits(_WIRE_209, 13, 13)
connect _WIRE_208.sx, _T_2820
node _T_2821 = bits(_WIRE_209, 14, 14)
connect _WIRE_208.sw, _T_2821
node _T_2822 = bits(_WIRE_209, 15, 15)
connect _WIRE_208.gf, _T_2822
node _T_2823 = bits(_WIRE_209, 16, 16)
connect _WIRE_208.pf, _T_2823
node _T_2824 = bits(_WIRE_209, 17, 17)
connect _WIRE_208.ae_stage2, _T_2824
node _T_2825 = bits(_WIRE_209, 18, 18)
connect _WIRE_208.ae_final, _T_2825
node _T_2826 = bits(_WIRE_209, 19, 19)
connect _WIRE_208.ae_ptw, _T_2826
node _T_2827 = bits(_WIRE_209, 20, 20)
connect _WIRE_208.g, _T_2827
node _T_2828 = bits(_WIRE_209, 21, 21)
connect _WIRE_208.u, _T_2828
node _T_2829 = bits(_WIRE_209, 41, 22)
connect _WIRE_208.ppn, _T_2829
wire _WIRE_210 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_211 : UInt<42>
connect _WIRE_211, sectored_entries[0][6].data[1]
node _T_2830 = bits(_WIRE_211, 0, 0)
connect _WIRE_210.fragmented_superpage, _T_2830
node _T_2831 = bits(_WIRE_211, 1, 1)
connect _WIRE_210.c, _T_2831
node _T_2832 = bits(_WIRE_211, 2, 2)
connect _WIRE_210.eff, _T_2832
node _T_2833 = bits(_WIRE_211, 3, 3)
connect _WIRE_210.paa, _T_2833
node _T_2834 = bits(_WIRE_211, 4, 4)
connect _WIRE_210.pal, _T_2834
node _T_2835 = bits(_WIRE_211, 5, 5)
connect _WIRE_210.ppp, _T_2835
node _T_2836 = bits(_WIRE_211, 6, 6)
connect _WIRE_210.pr, _T_2836
node _T_2837 = bits(_WIRE_211, 7, 7)
connect _WIRE_210.px, _T_2837
node _T_2838 = bits(_WIRE_211, 8, 8)
connect _WIRE_210.pw, _T_2838
node _T_2839 = bits(_WIRE_211, 9, 9)
connect _WIRE_210.hr, _T_2839
node _T_2840 = bits(_WIRE_211, 10, 10)
connect _WIRE_210.hx, _T_2840
node _T_2841 = bits(_WIRE_211, 11, 11)
connect _WIRE_210.hw, _T_2841
node _T_2842 = bits(_WIRE_211, 12, 12)
connect _WIRE_210.sr, _T_2842
node _T_2843 = bits(_WIRE_211, 13, 13)
connect _WIRE_210.sx, _T_2843
node _T_2844 = bits(_WIRE_211, 14, 14)
connect _WIRE_210.sw, _T_2844
node _T_2845 = bits(_WIRE_211, 15, 15)
connect _WIRE_210.gf, _T_2845
node _T_2846 = bits(_WIRE_211, 16, 16)
connect _WIRE_210.pf, _T_2846
node _T_2847 = bits(_WIRE_211, 17, 17)
connect _WIRE_210.ae_stage2, _T_2847
node _T_2848 = bits(_WIRE_211, 18, 18)
connect _WIRE_210.ae_final, _T_2848
node _T_2849 = bits(_WIRE_211, 19, 19)
connect _WIRE_210.ae_ptw, _T_2849
node _T_2850 = bits(_WIRE_211, 20, 20)
connect _WIRE_210.g, _T_2850
node _T_2851 = bits(_WIRE_211, 21, 21)
connect _WIRE_210.u, _T_2851
node _T_2852 = bits(_WIRE_211, 41, 22)
connect _WIRE_210.ppn, _T_2852
wire _WIRE_212 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_213 : UInt<42>
connect _WIRE_213, sectored_entries[0][6].data[2]
node _T_2853 = bits(_WIRE_213, 0, 0)
connect _WIRE_212.fragmented_superpage, _T_2853
node _T_2854 = bits(_WIRE_213, 1, 1)
connect _WIRE_212.c, _T_2854
node _T_2855 = bits(_WIRE_213, 2, 2)
connect _WIRE_212.eff, _T_2855
node _T_2856 = bits(_WIRE_213, 3, 3)
connect _WIRE_212.paa, _T_2856
node _T_2857 = bits(_WIRE_213, 4, 4)
connect _WIRE_212.pal, _T_2857
node _T_2858 = bits(_WIRE_213, 5, 5)
connect _WIRE_212.ppp, _T_2858
node _T_2859 = bits(_WIRE_213, 6, 6)
connect _WIRE_212.pr, _T_2859
node _T_2860 = bits(_WIRE_213, 7, 7)
connect _WIRE_212.px, _T_2860
node _T_2861 = bits(_WIRE_213, 8, 8)
connect _WIRE_212.pw, _T_2861
node _T_2862 = bits(_WIRE_213, 9, 9)
connect _WIRE_212.hr, _T_2862
node _T_2863 = bits(_WIRE_213, 10, 10)
connect _WIRE_212.hx, _T_2863
node _T_2864 = bits(_WIRE_213, 11, 11)
connect _WIRE_212.hw, _T_2864
node _T_2865 = bits(_WIRE_213, 12, 12)
connect _WIRE_212.sr, _T_2865
node _T_2866 = bits(_WIRE_213, 13, 13)
connect _WIRE_212.sx, _T_2866
node _T_2867 = bits(_WIRE_213, 14, 14)
connect _WIRE_212.sw, _T_2867
node _T_2868 = bits(_WIRE_213, 15, 15)
connect _WIRE_212.gf, _T_2868
node _T_2869 = bits(_WIRE_213, 16, 16)
connect _WIRE_212.pf, _T_2869
node _T_2870 = bits(_WIRE_213, 17, 17)
connect _WIRE_212.ae_stage2, _T_2870
node _T_2871 = bits(_WIRE_213, 18, 18)
connect _WIRE_212.ae_final, _T_2871
node _T_2872 = bits(_WIRE_213, 19, 19)
connect _WIRE_212.ae_ptw, _T_2872
node _T_2873 = bits(_WIRE_213, 20, 20)
connect _WIRE_212.g, _T_2873
node _T_2874 = bits(_WIRE_213, 21, 21)
connect _WIRE_212.u, _T_2874
node _T_2875 = bits(_WIRE_213, 41, 22)
connect _WIRE_212.ppn, _T_2875
wire _WIRE_214 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_215 : UInt<42>
connect _WIRE_215, sectored_entries[0][6].data[3]
node _T_2876 = bits(_WIRE_215, 0, 0)
connect _WIRE_214.fragmented_superpage, _T_2876
node _T_2877 = bits(_WIRE_215, 1, 1)
connect _WIRE_214.c, _T_2877
node _T_2878 = bits(_WIRE_215, 2, 2)
connect _WIRE_214.eff, _T_2878
node _T_2879 = bits(_WIRE_215, 3, 3)
connect _WIRE_214.paa, _T_2879
node _T_2880 = bits(_WIRE_215, 4, 4)
connect _WIRE_214.pal, _T_2880
node _T_2881 = bits(_WIRE_215, 5, 5)
connect _WIRE_214.ppp, _T_2881
node _T_2882 = bits(_WIRE_215, 6, 6)
connect _WIRE_214.pr, _T_2882
node _T_2883 = bits(_WIRE_215, 7, 7)
connect _WIRE_214.px, _T_2883
node _T_2884 = bits(_WIRE_215, 8, 8)
connect _WIRE_214.pw, _T_2884
node _T_2885 = bits(_WIRE_215, 9, 9)
connect _WIRE_214.hr, _T_2885
node _T_2886 = bits(_WIRE_215, 10, 10)
connect _WIRE_214.hx, _T_2886
node _T_2887 = bits(_WIRE_215, 11, 11)
connect _WIRE_214.hw, _T_2887
node _T_2888 = bits(_WIRE_215, 12, 12)
connect _WIRE_214.sr, _T_2888
node _T_2889 = bits(_WIRE_215, 13, 13)
connect _WIRE_214.sx, _T_2889
node _T_2890 = bits(_WIRE_215, 14, 14)
connect _WIRE_214.sw, _T_2890
node _T_2891 = bits(_WIRE_215, 15, 15)
connect _WIRE_214.gf, _T_2891
node _T_2892 = bits(_WIRE_215, 16, 16)
connect _WIRE_214.pf, _T_2892
node _T_2893 = bits(_WIRE_215, 17, 17)
connect _WIRE_214.ae_stage2, _T_2893
node _T_2894 = bits(_WIRE_215, 18, 18)
connect _WIRE_214.ae_final, _T_2894
node _T_2895 = bits(_WIRE_215, 19, 19)
connect _WIRE_214.ae_ptw, _T_2895
node _T_2896 = bits(_WIRE_215, 20, 20)
connect _WIRE_214.g, _T_2896
node _T_2897 = bits(_WIRE_215, 21, 21)
connect _WIRE_214.u, _T_2897
node _T_2898 = bits(_WIRE_215, 41, 22)
connect _WIRE_214.ppn, _T_2898
node _T_2899 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2900 = eq(_WIRE_208.g, UInt<1>(0h0))
node _T_2901 = and(_T_2899, _T_2900)
when _T_2901 :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
node _T_2902 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2903 = eq(_WIRE_210.g, UInt<1>(0h0))
node _T_2904 = and(_T_2902, _T_2903)
when _T_2904 :
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
node _T_2905 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2906 = eq(_WIRE_212.g, UInt<1>(0h0))
node _T_2907 = and(_T_2905, _T_2906)
when _T_2907 :
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
node _T_2908 = eq(sectored_entries[0][6].tag_v, hv_6)
node _T_2909 = eq(_WIRE_214.g, UInt<1>(0h0))
node _T_2910 = and(_T_2908, _T_2909)
when _T_2910 :
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
else :
node _T_2911 = or(hv_6, hg_6)
wire _WIRE_216 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_217 : UInt<42>
connect _WIRE_217, sectored_entries[0][6].data[0]
node _T_2912 = bits(_WIRE_217, 0, 0)
connect _WIRE_216.fragmented_superpage, _T_2912
node _T_2913 = bits(_WIRE_217, 1, 1)
connect _WIRE_216.c, _T_2913
node _T_2914 = bits(_WIRE_217, 2, 2)
connect _WIRE_216.eff, _T_2914
node _T_2915 = bits(_WIRE_217, 3, 3)
connect _WIRE_216.paa, _T_2915
node _T_2916 = bits(_WIRE_217, 4, 4)
connect _WIRE_216.pal, _T_2916
node _T_2917 = bits(_WIRE_217, 5, 5)
connect _WIRE_216.ppp, _T_2917
node _T_2918 = bits(_WIRE_217, 6, 6)
connect _WIRE_216.pr, _T_2918
node _T_2919 = bits(_WIRE_217, 7, 7)
connect _WIRE_216.px, _T_2919
node _T_2920 = bits(_WIRE_217, 8, 8)
connect _WIRE_216.pw, _T_2920
node _T_2921 = bits(_WIRE_217, 9, 9)
connect _WIRE_216.hr, _T_2921
node _T_2922 = bits(_WIRE_217, 10, 10)
connect _WIRE_216.hx, _T_2922
node _T_2923 = bits(_WIRE_217, 11, 11)
connect _WIRE_216.hw, _T_2923
node _T_2924 = bits(_WIRE_217, 12, 12)
connect _WIRE_216.sr, _T_2924
node _T_2925 = bits(_WIRE_217, 13, 13)
connect _WIRE_216.sx, _T_2925
node _T_2926 = bits(_WIRE_217, 14, 14)
connect _WIRE_216.sw, _T_2926
node _T_2927 = bits(_WIRE_217, 15, 15)
connect _WIRE_216.gf, _T_2927
node _T_2928 = bits(_WIRE_217, 16, 16)
connect _WIRE_216.pf, _T_2928
node _T_2929 = bits(_WIRE_217, 17, 17)
connect _WIRE_216.ae_stage2, _T_2929
node _T_2930 = bits(_WIRE_217, 18, 18)
connect _WIRE_216.ae_final, _T_2930
node _T_2931 = bits(_WIRE_217, 19, 19)
connect _WIRE_216.ae_ptw, _T_2931
node _T_2932 = bits(_WIRE_217, 20, 20)
connect _WIRE_216.g, _T_2932
node _T_2933 = bits(_WIRE_217, 21, 21)
connect _WIRE_216.u, _T_2933
node _T_2934 = bits(_WIRE_217, 41, 22)
connect _WIRE_216.ppn, _T_2934
wire _WIRE_218 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_219 : UInt<42>
connect _WIRE_219, sectored_entries[0][6].data[1]
node _T_2935 = bits(_WIRE_219, 0, 0)
connect _WIRE_218.fragmented_superpage, _T_2935
node _T_2936 = bits(_WIRE_219, 1, 1)
connect _WIRE_218.c, _T_2936
node _T_2937 = bits(_WIRE_219, 2, 2)
connect _WIRE_218.eff, _T_2937
node _T_2938 = bits(_WIRE_219, 3, 3)
connect _WIRE_218.paa, _T_2938
node _T_2939 = bits(_WIRE_219, 4, 4)
connect _WIRE_218.pal, _T_2939
node _T_2940 = bits(_WIRE_219, 5, 5)
connect _WIRE_218.ppp, _T_2940
node _T_2941 = bits(_WIRE_219, 6, 6)
connect _WIRE_218.pr, _T_2941
node _T_2942 = bits(_WIRE_219, 7, 7)
connect _WIRE_218.px, _T_2942
node _T_2943 = bits(_WIRE_219, 8, 8)
connect _WIRE_218.pw, _T_2943
node _T_2944 = bits(_WIRE_219, 9, 9)
connect _WIRE_218.hr, _T_2944
node _T_2945 = bits(_WIRE_219, 10, 10)
connect _WIRE_218.hx, _T_2945
node _T_2946 = bits(_WIRE_219, 11, 11)
connect _WIRE_218.hw, _T_2946
node _T_2947 = bits(_WIRE_219, 12, 12)
connect _WIRE_218.sr, _T_2947
node _T_2948 = bits(_WIRE_219, 13, 13)
connect _WIRE_218.sx, _T_2948
node _T_2949 = bits(_WIRE_219, 14, 14)
connect _WIRE_218.sw, _T_2949
node _T_2950 = bits(_WIRE_219, 15, 15)
connect _WIRE_218.gf, _T_2950
node _T_2951 = bits(_WIRE_219, 16, 16)
connect _WIRE_218.pf, _T_2951
node _T_2952 = bits(_WIRE_219, 17, 17)
connect _WIRE_218.ae_stage2, _T_2952
node _T_2953 = bits(_WIRE_219, 18, 18)
connect _WIRE_218.ae_final, _T_2953
node _T_2954 = bits(_WIRE_219, 19, 19)
connect _WIRE_218.ae_ptw, _T_2954
node _T_2955 = bits(_WIRE_219, 20, 20)
connect _WIRE_218.g, _T_2955
node _T_2956 = bits(_WIRE_219, 21, 21)
connect _WIRE_218.u, _T_2956
node _T_2957 = bits(_WIRE_219, 41, 22)
connect _WIRE_218.ppn, _T_2957
wire _WIRE_220 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_221 : UInt<42>
connect _WIRE_221, sectored_entries[0][6].data[2]
node _T_2958 = bits(_WIRE_221, 0, 0)
connect _WIRE_220.fragmented_superpage, _T_2958
node _T_2959 = bits(_WIRE_221, 1, 1)
connect _WIRE_220.c, _T_2959
node _T_2960 = bits(_WIRE_221, 2, 2)
connect _WIRE_220.eff, _T_2960
node _T_2961 = bits(_WIRE_221, 3, 3)
connect _WIRE_220.paa, _T_2961
node _T_2962 = bits(_WIRE_221, 4, 4)
connect _WIRE_220.pal, _T_2962
node _T_2963 = bits(_WIRE_221, 5, 5)
connect _WIRE_220.ppp, _T_2963
node _T_2964 = bits(_WIRE_221, 6, 6)
connect _WIRE_220.pr, _T_2964
node _T_2965 = bits(_WIRE_221, 7, 7)
connect _WIRE_220.px, _T_2965
node _T_2966 = bits(_WIRE_221, 8, 8)
connect _WIRE_220.pw, _T_2966
node _T_2967 = bits(_WIRE_221, 9, 9)
connect _WIRE_220.hr, _T_2967
node _T_2968 = bits(_WIRE_221, 10, 10)
connect _WIRE_220.hx, _T_2968
node _T_2969 = bits(_WIRE_221, 11, 11)
connect _WIRE_220.hw, _T_2969
node _T_2970 = bits(_WIRE_221, 12, 12)
connect _WIRE_220.sr, _T_2970
node _T_2971 = bits(_WIRE_221, 13, 13)
connect _WIRE_220.sx, _T_2971
node _T_2972 = bits(_WIRE_221, 14, 14)
connect _WIRE_220.sw, _T_2972
node _T_2973 = bits(_WIRE_221, 15, 15)
connect _WIRE_220.gf, _T_2973
node _T_2974 = bits(_WIRE_221, 16, 16)
connect _WIRE_220.pf, _T_2974
node _T_2975 = bits(_WIRE_221, 17, 17)
connect _WIRE_220.ae_stage2, _T_2975
node _T_2976 = bits(_WIRE_221, 18, 18)
connect _WIRE_220.ae_final, _T_2976
node _T_2977 = bits(_WIRE_221, 19, 19)
connect _WIRE_220.ae_ptw, _T_2977
node _T_2978 = bits(_WIRE_221, 20, 20)
connect _WIRE_220.g, _T_2978
node _T_2979 = bits(_WIRE_221, 21, 21)
connect _WIRE_220.u, _T_2979
node _T_2980 = bits(_WIRE_221, 41, 22)
connect _WIRE_220.ppn, _T_2980
wire _WIRE_222 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_223 : UInt<42>
connect _WIRE_223, sectored_entries[0][6].data[3]
node _T_2981 = bits(_WIRE_223, 0, 0)
connect _WIRE_222.fragmented_superpage, _T_2981
node _T_2982 = bits(_WIRE_223, 1, 1)
connect _WIRE_222.c, _T_2982
node _T_2983 = bits(_WIRE_223, 2, 2)
connect _WIRE_222.eff, _T_2983
node _T_2984 = bits(_WIRE_223, 3, 3)
connect _WIRE_222.paa, _T_2984
node _T_2985 = bits(_WIRE_223, 4, 4)
connect _WIRE_222.pal, _T_2985
node _T_2986 = bits(_WIRE_223, 5, 5)
connect _WIRE_222.ppp, _T_2986
node _T_2987 = bits(_WIRE_223, 6, 6)
connect _WIRE_222.pr, _T_2987
node _T_2988 = bits(_WIRE_223, 7, 7)
connect _WIRE_222.px, _T_2988
node _T_2989 = bits(_WIRE_223, 8, 8)
connect _WIRE_222.pw, _T_2989
node _T_2990 = bits(_WIRE_223, 9, 9)
connect _WIRE_222.hr, _T_2990
node _T_2991 = bits(_WIRE_223, 10, 10)
connect _WIRE_222.hx, _T_2991
node _T_2992 = bits(_WIRE_223, 11, 11)
connect _WIRE_222.hw, _T_2992
node _T_2993 = bits(_WIRE_223, 12, 12)
connect _WIRE_222.sr, _T_2993
node _T_2994 = bits(_WIRE_223, 13, 13)
connect _WIRE_222.sx, _T_2994
node _T_2995 = bits(_WIRE_223, 14, 14)
connect _WIRE_222.sw, _T_2995
node _T_2996 = bits(_WIRE_223, 15, 15)
connect _WIRE_222.gf, _T_2996
node _T_2997 = bits(_WIRE_223, 16, 16)
connect _WIRE_222.pf, _T_2997
node _T_2998 = bits(_WIRE_223, 17, 17)
connect _WIRE_222.ae_stage2, _T_2998
node _T_2999 = bits(_WIRE_223, 18, 18)
connect _WIRE_222.ae_final, _T_2999
node _T_3000 = bits(_WIRE_223, 19, 19)
connect _WIRE_222.ae_ptw, _T_3000
node _T_3001 = bits(_WIRE_223, 20, 20)
connect _WIRE_222.g, _T_3001
node _T_3002 = bits(_WIRE_223, 21, 21)
connect _WIRE_222.u, _T_3002
node _T_3003 = bits(_WIRE_223, 41, 22)
connect _WIRE_222.ppn, _T_3003
node _T_3004 = eq(sectored_entries[0][6].tag_v, _T_2911)
when _T_3004 :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
node _T_3005 = eq(sectored_entries[0][6].tag_v, _T_2911)
when _T_3005 :
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
node _T_3006 = eq(sectored_entries[0][6].tag_v, _T_2911)
when _T_3006 :
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
node _T_3007 = eq(sectored_entries[0][6].tag_v, _T_2911)
when _T_3007 :
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
node hv_7 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_7 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_3008 = eq(hg_7, UInt<1>(0h0))
node _T_3009 = and(_T_3008, io.sfence.bits.rs1)
when _T_3009 :
node _T_3010 = xor(sectored_entries[0][7].tag_vpn, vpn)
node _T_3011 = shr(_T_3010, 2)
node _T_3012 = eq(_T_3011, UInt<1>(0h0))
node _T_3013 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3014 = and(_T_3012, _T_3013)
when _T_3014 :
wire _WIRE_224 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_225 : UInt<42>
connect _WIRE_225, sectored_entries[0][7].data[0]
node _T_3015 = bits(_WIRE_225, 0, 0)
connect _WIRE_224.fragmented_superpage, _T_3015
node _T_3016 = bits(_WIRE_225, 1, 1)
connect _WIRE_224.c, _T_3016
node _T_3017 = bits(_WIRE_225, 2, 2)
connect _WIRE_224.eff, _T_3017
node _T_3018 = bits(_WIRE_225, 3, 3)
connect _WIRE_224.paa, _T_3018
node _T_3019 = bits(_WIRE_225, 4, 4)
connect _WIRE_224.pal, _T_3019
node _T_3020 = bits(_WIRE_225, 5, 5)
connect _WIRE_224.ppp, _T_3020
node _T_3021 = bits(_WIRE_225, 6, 6)
connect _WIRE_224.pr, _T_3021
node _T_3022 = bits(_WIRE_225, 7, 7)
connect _WIRE_224.px, _T_3022
node _T_3023 = bits(_WIRE_225, 8, 8)
connect _WIRE_224.pw, _T_3023
node _T_3024 = bits(_WIRE_225, 9, 9)
connect _WIRE_224.hr, _T_3024
node _T_3025 = bits(_WIRE_225, 10, 10)
connect _WIRE_224.hx, _T_3025
node _T_3026 = bits(_WIRE_225, 11, 11)
connect _WIRE_224.hw, _T_3026
node _T_3027 = bits(_WIRE_225, 12, 12)
connect _WIRE_224.sr, _T_3027
node _T_3028 = bits(_WIRE_225, 13, 13)
connect _WIRE_224.sx, _T_3028
node _T_3029 = bits(_WIRE_225, 14, 14)
connect _WIRE_224.sw, _T_3029
node _T_3030 = bits(_WIRE_225, 15, 15)
connect _WIRE_224.gf, _T_3030
node _T_3031 = bits(_WIRE_225, 16, 16)
connect _WIRE_224.pf, _T_3031
node _T_3032 = bits(_WIRE_225, 17, 17)
connect _WIRE_224.ae_stage2, _T_3032
node _T_3033 = bits(_WIRE_225, 18, 18)
connect _WIRE_224.ae_final, _T_3033
node _T_3034 = bits(_WIRE_225, 19, 19)
connect _WIRE_224.ae_ptw, _T_3034
node _T_3035 = bits(_WIRE_225, 20, 20)
connect _WIRE_224.g, _T_3035
node _T_3036 = bits(_WIRE_225, 21, 21)
connect _WIRE_224.u, _T_3036
node _T_3037 = bits(_WIRE_225, 41, 22)
connect _WIRE_224.ppn, _T_3037
wire _WIRE_226 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_227 : UInt<42>
connect _WIRE_227, sectored_entries[0][7].data[1]
node _T_3038 = bits(_WIRE_227, 0, 0)
connect _WIRE_226.fragmented_superpage, _T_3038
node _T_3039 = bits(_WIRE_227, 1, 1)
connect _WIRE_226.c, _T_3039
node _T_3040 = bits(_WIRE_227, 2, 2)
connect _WIRE_226.eff, _T_3040
node _T_3041 = bits(_WIRE_227, 3, 3)
connect _WIRE_226.paa, _T_3041
node _T_3042 = bits(_WIRE_227, 4, 4)
connect _WIRE_226.pal, _T_3042
node _T_3043 = bits(_WIRE_227, 5, 5)
connect _WIRE_226.ppp, _T_3043
node _T_3044 = bits(_WIRE_227, 6, 6)
connect _WIRE_226.pr, _T_3044
node _T_3045 = bits(_WIRE_227, 7, 7)
connect _WIRE_226.px, _T_3045
node _T_3046 = bits(_WIRE_227, 8, 8)
connect _WIRE_226.pw, _T_3046
node _T_3047 = bits(_WIRE_227, 9, 9)
connect _WIRE_226.hr, _T_3047
node _T_3048 = bits(_WIRE_227, 10, 10)
connect _WIRE_226.hx, _T_3048
node _T_3049 = bits(_WIRE_227, 11, 11)
connect _WIRE_226.hw, _T_3049
node _T_3050 = bits(_WIRE_227, 12, 12)
connect _WIRE_226.sr, _T_3050
node _T_3051 = bits(_WIRE_227, 13, 13)
connect _WIRE_226.sx, _T_3051
node _T_3052 = bits(_WIRE_227, 14, 14)
connect _WIRE_226.sw, _T_3052
node _T_3053 = bits(_WIRE_227, 15, 15)
connect _WIRE_226.gf, _T_3053
node _T_3054 = bits(_WIRE_227, 16, 16)
connect _WIRE_226.pf, _T_3054
node _T_3055 = bits(_WIRE_227, 17, 17)
connect _WIRE_226.ae_stage2, _T_3055
node _T_3056 = bits(_WIRE_227, 18, 18)
connect _WIRE_226.ae_final, _T_3056
node _T_3057 = bits(_WIRE_227, 19, 19)
connect _WIRE_226.ae_ptw, _T_3057
node _T_3058 = bits(_WIRE_227, 20, 20)
connect _WIRE_226.g, _T_3058
node _T_3059 = bits(_WIRE_227, 21, 21)
connect _WIRE_226.u, _T_3059
node _T_3060 = bits(_WIRE_227, 41, 22)
connect _WIRE_226.ppn, _T_3060
wire _WIRE_228 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_229 : UInt<42>
connect _WIRE_229, sectored_entries[0][7].data[2]
node _T_3061 = bits(_WIRE_229, 0, 0)
connect _WIRE_228.fragmented_superpage, _T_3061
node _T_3062 = bits(_WIRE_229, 1, 1)
connect _WIRE_228.c, _T_3062
node _T_3063 = bits(_WIRE_229, 2, 2)
connect _WIRE_228.eff, _T_3063
node _T_3064 = bits(_WIRE_229, 3, 3)
connect _WIRE_228.paa, _T_3064
node _T_3065 = bits(_WIRE_229, 4, 4)
connect _WIRE_228.pal, _T_3065
node _T_3066 = bits(_WIRE_229, 5, 5)
connect _WIRE_228.ppp, _T_3066
node _T_3067 = bits(_WIRE_229, 6, 6)
connect _WIRE_228.pr, _T_3067
node _T_3068 = bits(_WIRE_229, 7, 7)
connect _WIRE_228.px, _T_3068
node _T_3069 = bits(_WIRE_229, 8, 8)
connect _WIRE_228.pw, _T_3069
node _T_3070 = bits(_WIRE_229, 9, 9)
connect _WIRE_228.hr, _T_3070
node _T_3071 = bits(_WIRE_229, 10, 10)
connect _WIRE_228.hx, _T_3071
node _T_3072 = bits(_WIRE_229, 11, 11)
connect _WIRE_228.hw, _T_3072
node _T_3073 = bits(_WIRE_229, 12, 12)
connect _WIRE_228.sr, _T_3073
node _T_3074 = bits(_WIRE_229, 13, 13)
connect _WIRE_228.sx, _T_3074
node _T_3075 = bits(_WIRE_229, 14, 14)
connect _WIRE_228.sw, _T_3075
node _T_3076 = bits(_WIRE_229, 15, 15)
connect _WIRE_228.gf, _T_3076
node _T_3077 = bits(_WIRE_229, 16, 16)
connect _WIRE_228.pf, _T_3077
node _T_3078 = bits(_WIRE_229, 17, 17)
connect _WIRE_228.ae_stage2, _T_3078
node _T_3079 = bits(_WIRE_229, 18, 18)
connect _WIRE_228.ae_final, _T_3079
node _T_3080 = bits(_WIRE_229, 19, 19)
connect _WIRE_228.ae_ptw, _T_3080
node _T_3081 = bits(_WIRE_229, 20, 20)
connect _WIRE_228.g, _T_3081
node _T_3082 = bits(_WIRE_229, 21, 21)
connect _WIRE_228.u, _T_3082
node _T_3083 = bits(_WIRE_229, 41, 22)
connect _WIRE_228.ppn, _T_3083
wire _WIRE_230 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_231 : UInt<42>
connect _WIRE_231, sectored_entries[0][7].data[3]
node _T_3084 = bits(_WIRE_231, 0, 0)
connect _WIRE_230.fragmented_superpage, _T_3084
node _T_3085 = bits(_WIRE_231, 1, 1)
connect _WIRE_230.c, _T_3085
node _T_3086 = bits(_WIRE_231, 2, 2)
connect _WIRE_230.eff, _T_3086
node _T_3087 = bits(_WIRE_231, 3, 3)
connect _WIRE_230.paa, _T_3087
node _T_3088 = bits(_WIRE_231, 4, 4)
connect _WIRE_230.pal, _T_3088
node _T_3089 = bits(_WIRE_231, 5, 5)
connect _WIRE_230.ppp, _T_3089
node _T_3090 = bits(_WIRE_231, 6, 6)
connect _WIRE_230.pr, _T_3090
node _T_3091 = bits(_WIRE_231, 7, 7)
connect _WIRE_230.px, _T_3091
node _T_3092 = bits(_WIRE_231, 8, 8)
connect _WIRE_230.pw, _T_3092
node _T_3093 = bits(_WIRE_231, 9, 9)
connect _WIRE_230.hr, _T_3093
node _T_3094 = bits(_WIRE_231, 10, 10)
connect _WIRE_230.hx, _T_3094
node _T_3095 = bits(_WIRE_231, 11, 11)
connect _WIRE_230.hw, _T_3095
node _T_3096 = bits(_WIRE_231, 12, 12)
connect _WIRE_230.sr, _T_3096
node _T_3097 = bits(_WIRE_231, 13, 13)
connect _WIRE_230.sx, _T_3097
node _T_3098 = bits(_WIRE_231, 14, 14)
connect _WIRE_230.sw, _T_3098
node _T_3099 = bits(_WIRE_231, 15, 15)
connect _WIRE_230.gf, _T_3099
node _T_3100 = bits(_WIRE_231, 16, 16)
connect _WIRE_230.pf, _T_3100
node _T_3101 = bits(_WIRE_231, 17, 17)
connect _WIRE_230.ae_stage2, _T_3101
node _T_3102 = bits(_WIRE_231, 18, 18)
connect _WIRE_230.ae_final, _T_3102
node _T_3103 = bits(_WIRE_231, 19, 19)
connect _WIRE_230.ae_ptw, _T_3103
node _T_3104 = bits(_WIRE_231, 20, 20)
connect _WIRE_230.g, _T_3104
node _T_3105 = bits(_WIRE_231, 21, 21)
connect _WIRE_230.u, _T_3105
node _T_3106 = bits(_WIRE_231, 41, 22)
connect _WIRE_230.ppn, _T_3106
node _T_3107 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3108 = bits(vpn, 1, 0)
node _T_3109 = eq(UInt<1>(0h0), _T_3108)
node _T_3110 = and(_T_3107, _T_3109)
when _T_3110 :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
node _T_3111 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3112 = bits(vpn, 1, 0)
node _T_3113 = eq(UInt<1>(0h1), _T_3112)
node _T_3114 = and(_T_3111, _T_3113)
when _T_3114 :
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
node _T_3115 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3116 = bits(vpn, 1, 0)
node _T_3117 = eq(UInt<2>(0h2), _T_3116)
node _T_3118 = and(_T_3115, _T_3117)
when _T_3118 :
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
node _T_3119 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3120 = bits(vpn, 1, 0)
node _T_3121 = eq(UInt<2>(0h3), _T_3120)
node _T_3122 = and(_T_3119, _T_3121)
when _T_3122 :
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
node _T_3123 = xor(sectored_entries[0][7].tag_vpn, vpn)
node _T_3124 = shr(_T_3123, 18)
node _T_3125 = eq(_T_3124, UInt<1>(0h0))
when _T_3125 :
wire _WIRE_232 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_233 : UInt<42>
connect _WIRE_233, sectored_entries[0][7].data[0]
node _T_3126 = bits(_WIRE_233, 0, 0)
connect _WIRE_232.fragmented_superpage, _T_3126
node _T_3127 = bits(_WIRE_233, 1, 1)
connect _WIRE_232.c, _T_3127
node _T_3128 = bits(_WIRE_233, 2, 2)
connect _WIRE_232.eff, _T_3128
node _T_3129 = bits(_WIRE_233, 3, 3)
connect _WIRE_232.paa, _T_3129
node _T_3130 = bits(_WIRE_233, 4, 4)
connect _WIRE_232.pal, _T_3130
node _T_3131 = bits(_WIRE_233, 5, 5)
connect _WIRE_232.ppp, _T_3131
node _T_3132 = bits(_WIRE_233, 6, 6)
connect _WIRE_232.pr, _T_3132
node _T_3133 = bits(_WIRE_233, 7, 7)
connect _WIRE_232.px, _T_3133
node _T_3134 = bits(_WIRE_233, 8, 8)
connect _WIRE_232.pw, _T_3134
node _T_3135 = bits(_WIRE_233, 9, 9)
connect _WIRE_232.hr, _T_3135
node _T_3136 = bits(_WIRE_233, 10, 10)
connect _WIRE_232.hx, _T_3136
node _T_3137 = bits(_WIRE_233, 11, 11)
connect _WIRE_232.hw, _T_3137
node _T_3138 = bits(_WIRE_233, 12, 12)
connect _WIRE_232.sr, _T_3138
node _T_3139 = bits(_WIRE_233, 13, 13)
connect _WIRE_232.sx, _T_3139
node _T_3140 = bits(_WIRE_233, 14, 14)
connect _WIRE_232.sw, _T_3140
node _T_3141 = bits(_WIRE_233, 15, 15)
connect _WIRE_232.gf, _T_3141
node _T_3142 = bits(_WIRE_233, 16, 16)
connect _WIRE_232.pf, _T_3142
node _T_3143 = bits(_WIRE_233, 17, 17)
connect _WIRE_232.ae_stage2, _T_3143
node _T_3144 = bits(_WIRE_233, 18, 18)
connect _WIRE_232.ae_final, _T_3144
node _T_3145 = bits(_WIRE_233, 19, 19)
connect _WIRE_232.ae_ptw, _T_3145
node _T_3146 = bits(_WIRE_233, 20, 20)
connect _WIRE_232.g, _T_3146
node _T_3147 = bits(_WIRE_233, 21, 21)
connect _WIRE_232.u, _T_3147
node _T_3148 = bits(_WIRE_233, 41, 22)
connect _WIRE_232.ppn, _T_3148
wire _WIRE_234 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_235 : UInt<42>
connect _WIRE_235, sectored_entries[0][7].data[1]
node _T_3149 = bits(_WIRE_235, 0, 0)
connect _WIRE_234.fragmented_superpage, _T_3149
node _T_3150 = bits(_WIRE_235, 1, 1)
connect _WIRE_234.c, _T_3150
node _T_3151 = bits(_WIRE_235, 2, 2)
connect _WIRE_234.eff, _T_3151
node _T_3152 = bits(_WIRE_235, 3, 3)
connect _WIRE_234.paa, _T_3152
node _T_3153 = bits(_WIRE_235, 4, 4)
connect _WIRE_234.pal, _T_3153
node _T_3154 = bits(_WIRE_235, 5, 5)
connect _WIRE_234.ppp, _T_3154
node _T_3155 = bits(_WIRE_235, 6, 6)
connect _WIRE_234.pr, _T_3155
node _T_3156 = bits(_WIRE_235, 7, 7)
connect _WIRE_234.px, _T_3156
node _T_3157 = bits(_WIRE_235, 8, 8)
connect _WIRE_234.pw, _T_3157
node _T_3158 = bits(_WIRE_235, 9, 9)
connect _WIRE_234.hr, _T_3158
node _T_3159 = bits(_WIRE_235, 10, 10)
connect _WIRE_234.hx, _T_3159
node _T_3160 = bits(_WIRE_235, 11, 11)
connect _WIRE_234.hw, _T_3160
node _T_3161 = bits(_WIRE_235, 12, 12)
connect _WIRE_234.sr, _T_3161
node _T_3162 = bits(_WIRE_235, 13, 13)
connect _WIRE_234.sx, _T_3162
node _T_3163 = bits(_WIRE_235, 14, 14)
connect _WIRE_234.sw, _T_3163
node _T_3164 = bits(_WIRE_235, 15, 15)
connect _WIRE_234.gf, _T_3164
node _T_3165 = bits(_WIRE_235, 16, 16)
connect _WIRE_234.pf, _T_3165
node _T_3166 = bits(_WIRE_235, 17, 17)
connect _WIRE_234.ae_stage2, _T_3166
node _T_3167 = bits(_WIRE_235, 18, 18)
connect _WIRE_234.ae_final, _T_3167
node _T_3168 = bits(_WIRE_235, 19, 19)
connect _WIRE_234.ae_ptw, _T_3168
node _T_3169 = bits(_WIRE_235, 20, 20)
connect _WIRE_234.g, _T_3169
node _T_3170 = bits(_WIRE_235, 21, 21)
connect _WIRE_234.u, _T_3170
node _T_3171 = bits(_WIRE_235, 41, 22)
connect _WIRE_234.ppn, _T_3171
wire _WIRE_236 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_237 : UInt<42>
connect _WIRE_237, sectored_entries[0][7].data[2]
node _T_3172 = bits(_WIRE_237, 0, 0)
connect _WIRE_236.fragmented_superpage, _T_3172
node _T_3173 = bits(_WIRE_237, 1, 1)
connect _WIRE_236.c, _T_3173
node _T_3174 = bits(_WIRE_237, 2, 2)
connect _WIRE_236.eff, _T_3174
node _T_3175 = bits(_WIRE_237, 3, 3)
connect _WIRE_236.paa, _T_3175
node _T_3176 = bits(_WIRE_237, 4, 4)
connect _WIRE_236.pal, _T_3176
node _T_3177 = bits(_WIRE_237, 5, 5)
connect _WIRE_236.ppp, _T_3177
node _T_3178 = bits(_WIRE_237, 6, 6)
connect _WIRE_236.pr, _T_3178
node _T_3179 = bits(_WIRE_237, 7, 7)
connect _WIRE_236.px, _T_3179
node _T_3180 = bits(_WIRE_237, 8, 8)
connect _WIRE_236.pw, _T_3180
node _T_3181 = bits(_WIRE_237, 9, 9)
connect _WIRE_236.hr, _T_3181
node _T_3182 = bits(_WIRE_237, 10, 10)
connect _WIRE_236.hx, _T_3182
node _T_3183 = bits(_WIRE_237, 11, 11)
connect _WIRE_236.hw, _T_3183
node _T_3184 = bits(_WIRE_237, 12, 12)
connect _WIRE_236.sr, _T_3184
node _T_3185 = bits(_WIRE_237, 13, 13)
connect _WIRE_236.sx, _T_3185
node _T_3186 = bits(_WIRE_237, 14, 14)
connect _WIRE_236.sw, _T_3186
node _T_3187 = bits(_WIRE_237, 15, 15)
connect _WIRE_236.gf, _T_3187
node _T_3188 = bits(_WIRE_237, 16, 16)
connect _WIRE_236.pf, _T_3188
node _T_3189 = bits(_WIRE_237, 17, 17)
connect _WIRE_236.ae_stage2, _T_3189
node _T_3190 = bits(_WIRE_237, 18, 18)
connect _WIRE_236.ae_final, _T_3190
node _T_3191 = bits(_WIRE_237, 19, 19)
connect _WIRE_236.ae_ptw, _T_3191
node _T_3192 = bits(_WIRE_237, 20, 20)
connect _WIRE_236.g, _T_3192
node _T_3193 = bits(_WIRE_237, 21, 21)
connect _WIRE_236.u, _T_3193
node _T_3194 = bits(_WIRE_237, 41, 22)
connect _WIRE_236.ppn, _T_3194
wire _WIRE_238 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_239 : UInt<42>
connect _WIRE_239, sectored_entries[0][7].data[3]
node _T_3195 = bits(_WIRE_239, 0, 0)
connect _WIRE_238.fragmented_superpage, _T_3195
node _T_3196 = bits(_WIRE_239, 1, 1)
connect _WIRE_238.c, _T_3196
node _T_3197 = bits(_WIRE_239, 2, 2)
connect _WIRE_238.eff, _T_3197
node _T_3198 = bits(_WIRE_239, 3, 3)
connect _WIRE_238.paa, _T_3198
node _T_3199 = bits(_WIRE_239, 4, 4)
connect _WIRE_238.pal, _T_3199
node _T_3200 = bits(_WIRE_239, 5, 5)
connect _WIRE_238.ppp, _T_3200
node _T_3201 = bits(_WIRE_239, 6, 6)
connect _WIRE_238.pr, _T_3201
node _T_3202 = bits(_WIRE_239, 7, 7)
connect _WIRE_238.px, _T_3202
node _T_3203 = bits(_WIRE_239, 8, 8)
connect _WIRE_238.pw, _T_3203
node _T_3204 = bits(_WIRE_239, 9, 9)
connect _WIRE_238.hr, _T_3204
node _T_3205 = bits(_WIRE_239, 10, 10)
connect _WIRE_238.hx, _T_3205
node _T_3206 = bits(_WIRE_239, 11, 11)
connect _WIRE_238.hw, _T_3206
node _T_3207 = bits(_WIRE_239, 12, 12)
connect _WIRE_238.sr, _T_3207
node _T_3208 = bits(_WIRE_239, 13, 13)
connect _WIRE_238.sx, _T_3208
node _T_3209 = bits(_WIRE_239, 14, 14)
connect _WIRE_238.sw, _T_3209
node _T_3210 = bits(_WIRE_239, 15, 15)
connect _WIRE_238.gf, _T_3210
node _T_3211 = bits(_WIRE_239, 16, 16)
connect _WIRE_238.pf, _T_3211
node _T_3212 = bits(_WIRE_239, 17, 17)
connect _WIRE_238.ae_stage2, _T_3212
node _T_3213 = bits(_WIRE_239, 18, 18)
connect _WIRE_238.ae_final, _T_3213
node _T_3214 = bits(_WIRE_239, 19, 19)
connect _WIRE_238.ae_ptw, _T_3214
node _T_3215 = bits(_WIRE_239, 20, 20)
connect _WIRE_238.g, _T_3215
node _T_3216 = bits(_WIRE_239, 21, 21)
connect _WIRE_238.u, _T_3216
node _T_3217 = bits(_WIRE_239, 41, 22)
connect _WIRE_238.ppn, _T_3217
node _T_3218 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3219 = and(_T_3218, _WIRE_232.fragmented_superpage)
when _T_3219 :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
node _T_3220 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3221 = and(_T_3220, _WIRE_234.fragmented_superpage)
when _T_3221 :
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
node _T_3222 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3223 = and(_T_3222, _WIRE_236.fragmented_superpage)
when _T_3223 :
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
node _T_3224 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3225 = and(_T_3224, _WIRE_238.fragmented_superpage)
when _T_3225 :
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
else :
node _T_3226 = eq(hg_7, UInt<1>(0h0))
node _T_3227 = and(_T_3226, io.sfence.bits.rs2)
when _T_3227 :
wire _WIRE_240 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_241 : UInt<42>
connect _WIRE_241, sectored_entries[0][7].data[0]
node _T_3228 = bits(_WIRE_241, 0, 0)
connect _WIRE_240.fragmented_superpage, _T_3228
node _T_3229 = bits(_WIRE_241, 1, 1)
connect _WIRE_240.c, _T_3229
node _T_3230 = bits(_WIRE_241, 2, 2)
connect _WIRE_240.eff, _T_3230
node _T_3231 = bits(_WIRE_241, 3, 3)
connect _WIRE_240.paa, _T_3231
node _T_3232 = bits(_WIRE_241, 4, 4)
connect _WIRE_240.pal, _T_3232
node _T_3233 = bits(_WIRE_241, 5, 5)
connect _WIRE_240.ppp, _T_3233
node _T_3234 = bits(_WIRE_241, 6, 6)
connect _WIRE_240.pr, _T_3234
node _T_3235 = bits(_WIRE_241, 7, 7)
connect _WIRE_240.px, _T_3235
node _T_3236 = bits(_WIRE_241, 8, 8)
connect _WIRE_240.pw, _T_3236
node _T_3237 = bits(_WIRE_241, 9, 9)
connect _WIRE_240.hr, _T_3237
node _T_3238 = bits(_WIRE_241, 10, 10)
connect _WIRE_240.hx, _T_3238
node _T_3239 = bits(_WIRE_241, 11, 11)
connect _WIRE_240.hw, _T_3239
node _T_3240 = bits(_WIRE_241, 12, 12)
connect _WIRE_240.sr, _T_3240
node _T_3241 = bits(_WIRE_241, 13, 13)
connect _WIRE_240.sx, _T_3241
node _T_3242 = bits(_WIRE_241, 14, 14)
connect _WIRE_240.sw, _T_3242
node _T_3243 = bits(_WIRE_241, 15, 15)
connect _WIRE_240.gf, _T_3243
node _T_3244 = bits(_WIRE_241, 16, 16)
connect _WIRE_240.pf, _T_3244
node _T_3245 = bits(_WIRE_241, 17, 17)
connect _WIRE_240.ae_stage2, _T_3245
node _T_3246 = bits(_WIRE_241, 18, 18)
connect _WIRE_240.ae_final, _T_3246
node _T_3247 = bits(_WIRE_241, 19, 19)
connect _WIRE_240.ae_ptw, _T_3247
node _T_3248 = bits(_WIRE_241, 20, 20)
connect _WIRE_240.g, _T_3248
node _T_3249 = bits(_WIRE_241, 21, 21)
connect _WIRE_240.u, _T_3249
node _T_3250 = bits(_WIRE_241, 41, 22)
connect _WIRE_240.ppn, _T_3250
wire _WIRE_242 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_243 : UInt<42>
connect _WIRE_243, sectored_entries[0][7].data[1]
node _T_3251 = bits(_WIRE_243, 0, 0)
connect _WIRE_242.fragmented_superpage, _T_3251
node _T_3252 = bits(_WIRE_243, 1, 1)
connect _WIRE_242.c, _T_3252
node _T_3253 = bits(_WIRE_243, 2, 2)
connect _WIRE_242.eff, _T_3253
node _T_3254 = bits(_WIRE_243, 3, 3)
connect _WIRE_242.paa, _T_3254
node _T_3255 = bits(_WIRE_243, 4, 4)
connect _WIRE_242.pal, _T_3255
node _T_3256 = bits(_WIRE_243, 5, 5)
connect _WIRE_242.ppp, _T_3256
node _T_3257 = bits(_WIRE_243, 6, 6)
connect _WIRE_242.pr, _T_3257
node _T_3258 = bits(_WIRE_243, 7, 7)
connect _WIRE_242.px, _T_3258
node _T_3259 = bits(_WIRE_243, 8, 8)
connect _WIRE_242.pw, _T_3259
node _T_3260 = bits(_WIRE_243, 9, 9)
connect _WIRE_242.hr, _T_3260
node _T_3261 = bits(_WIRE_243, 10, 10)
connect _WIRE_242.hx, _T_3261
node _T_3262 = bits(_WIRE_243, 11, 11)
connect _WIRE_242.hw, _T_3262
node _T_3263 = bits(_WIRE_243, 12, 12)
connect _WIRE_242.sr, _T_3263
node _T_3264 = bits(_WIRE_243, 13, 13)
connect _WIRE_242.sx, _T_3264
node _T_3265 = bits(_WIRE_243, 14, 14)
connect _WIRE_242.sw, _T_3265
node _T_3266 = bits(_WIRE_243, 15, 15)
connect _WIRE_242.gf, _T_3266
node _T_3267 = bits(_WIRE_243, 16, 16)
connect _WIRE_242.pf, _T_3267
node _T_3268 = bits(_WIRE_243, 17, 17)
connect _WIRE_242.ae_stage2, _T_3268
node _T_3269 = bits(_WIRE_243, 18, 18)
connect _WIRE_242.ae_final, _T_3269
node _T_3270 = bits(_WIRE_243, 19, 19)
connect _WIRE_242.ae_ptw, _T_3270
node _T_3271 = bits(_WIRE_243, 20, 20)
connect _WIRE_242.g, _T_3271
node _T_3272 = bits(_WIRE_243, 21, 21)
connect _WIRE_242.u, _T_3272
node _T_3273 = bits(_WIRE_243, 41, 22)
connect _WIRE_242.ppn, _T_3273
wire _WIRE_244 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_245 : UInt<42>
connect _WIRE_245, sectored_entries[0][7].data[2]
node _T_3274 = bits(_WIRE_245, 0, 0)
connect _WIRE_244.fragmented_superpage, _T_3274
node _T_3275 = bits(_WIRE_245, 1, 1)
connect _WIRE_244.c, _T_3275
node _T_3276 = bits(_WIRE_245, 2, 2)
connect _WIRE_244.eff, _T_3276
node _T_3277 = bits(_WIRE_245, 3, 3)
connect _WIRE_244.paa, _T_3277
node _T_3278 = bits(_WIRE_245, 4, 4)
connect _WIRE_244.pal, _T_3278
node _T_3279 = bits(_WIRE_245, 5, 5)
connect _WIRE_244.ppp, _T_3279
node _T_3280 = bits(_WIRE_245, 6, 6)
connect _WIRE_244.pr, _T_3280
node _T_3281 = bits(_WIRE_245, 7, 7)
connect _WIRE_244.px, _T_3281
node _T_3282 = bits(_WIRE_245, 8, 8)
connect _WIRE_244.pw, _T_3282
node _T_3283 = bits(_WIRE_245, 9, 9)
connect _WIRE_244.hr, _T_3283
node _T_3284 = bits(_WIRE_245, 10, 10)
connect _WIRE_244.hx, _T_3284
node _T_3285 = bits(_WIRE_245, 11, 11)
connect _WIRE_244.hw, _T_3285
node _T_3286 = bits(_WIRE_245, 12, 12)
connect _WIRE_244.sr, _T_3286
node _T_3287 = bits(_WIRE_245, 13, 13)
connect _WIRE_244.sx, _T_3287
node _T_3288 = bits(_WIRE_245, 14, 14)
connect _WIRE_244.sw, _T_3288
node _T_3289 = bits(_WIRE_245, 15, 15)
connect _WIRE_244.gf, _T_3289
node _T_3290 = bits(_WIRE_245, 16, 16)
connect _WIRE_244.pf, _T_3290
node _T_3291 = bits(_WIRE_245, 17, 17)
connect _WIRE_244.ae_stage2, _T_3291
node _T_3292 = bits(_WIRE_245, 18, 18)
connect _WIRE_244.ae_final, _T_3292
node _T_3293 = bits(_WIRE_245, 19, 19)
connect _WIRE_244.ae_ptw, _T_3293
node _T_3294 = bits(_WIRE_245, 20, 20)
connect _WIRE_244.g, _T_3294
node _T_3295 = bits(_WIRE_245, 21, 21)
connect _WIRE_244.u, _T_3295
node _T_3296 = bits(_WIRE_245, 41, 22)
connect _WIRE_244.ppn, _T_3296
wire _WIRE_246 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_247 : UInt<42>
connect _WIRE_247, sectored_entries[0][7].data[3]
node _T_3297 = bits(_WIRE_247, 0, 0)
connect _WIRE_246.fragmented_superpage, _T_3297
node _T_3298 = bits(_WIRE_247, 1, 1)
connect _WIRE_246.c, _T_3298
node _T_3299 = bits(_WIRE_247, 2, 2)
connect _WIRE_246.eff, _T_3299
node _T_3300 = bits(_WIRE_247, 3, 3)
connect _WIRE_246.paa, _T_3300
node _T_3301 = bits(_WIRE_247, 4, 4)
connect _WIRE_246.pal, _T_3301
node _T_3302 = bits(_WIRE_247, 5, 5)
connect _WIRE_246.ppp, _T_3302
node _T_3303 = bits(_WIRE_247, 6, 6)
connect _WIRE_246.pr, _T_3303
node _T_3304 = bits(_WIRE_247, 7, 7)
connect _WIRE_246.px, _T_3304
node _T_3305 = bits(_WIRE_247, 8, 8)
connect _WIRE_246.pw, _T_3305
node _T_3306 = bits(_WIRE_247, 9, 9)
connect _WIRE_246.hr, _T_3306
node _T_3307 = bits(_WIRE_247, 10, 10)
connect _WIRE_246.hx, _T_3307
node _T_3308 = bits(_WIRE_247, 11, 11)
connect _WIRE_246.hw, _T_3308
node _T_3309 = bits(_WIRE_247, 12, 12)
connect _WIRE_246.sr, _T_3309
node _T_3310 = bits(_WIRE_247, 13, 13)
connect _WIRE_246.sx, _T_3310
node _T_3311 = bits(_WIRE_247, 14, 14)
connect _WIRE_246.sw, _T_3311
node _T_3312 = bits(_WIRE_247, 15, 15)
connect _WIRE_246.gf, _T_3312
node _T_3313 = bits(_WIRE_247, 16, 16)
connect _WIRE_246.pf, _T_3313
node _T_3314 = bits(_WIRE_247, 17, 17)
connect _WIRE_246.ae_stage2, _T_3314
node _T_3315 = bits(_WIRE_247, 18, 18)
connect _WIRE_246.ae_final, _T_3315
node _T_3316 = bits(_WIRE_247, 19, 19)
connect _WIRE_246.ae_ptw, _T_3316
node _T_3317 = bits(_WIRE_247, 20, 20)
connect _WIRE_246.g, _T_3317
node _T_3318 = bits(_WIRE_247, 21, 21)
connect _WIRE_246.u, _T_3318
node _T_3319 = bits(_WIRE_247, 41, 22)
connect _WIRE_246.ppn, _T_3319
node _T_3320 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3321 = eq(_WIRE_240.g, UInt<1>(0h0))
node _T_3322 = and(_T_3320, _T_3321)
when _T_3322 :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
node _T_3323 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3324 = eq(_WIRE_242.g, UInt<1>(0h0))
node _T_3325 = and(_T_3323, _T_3324)
when _T_3325 :
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
node _T_3326 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3327 = eq(_WIRE_244.g, UInt<1>(0h0))
node _T_3328 = and(_T_3326, _T_3327)
when _T_3328 :
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
node _T_3329 = eq(sectored_entries[0][7].tag_v, hv_7)
node _T_3330 = eq(_WIRE_246.g, UInt<1>(0h0))
node _T_3331 = and(_T_3329, _T_3330)
when _T_3331 :
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
else :
node _T_3332 = or(hv_7, hg_7)
wire _WIRE_248 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_249 : UInt<42>
connect _WIRE_249, sectored_entries[0][7].data[0]
node _T_3333 = bits(_WIRE_249, 0, 0)
connect _WIRE_248.fragmented_superpage, _T_3333
node _T_3334 = bits(_WIRE_249, 1, 1)
connect _WIRE_248.c, _T_3334
node _T_3335 = bits(_WIRE_249, 2, 2)
connect _WIRE_248.eff, _T_3335
node _T_3336 = bits(_WIRE_249, 3, 3)
connect _WIRE_248.paa, _T_3336
node _T_3337 = bits(_WIRE_249, 4, 4)
connect _WIRE_248.pal, _T_3337
node _T_3338 = bits(_WIRE_249, 5, 5)
connect _WIRE_248.ppp, _T_3338
node _T_3339 = bits(_WIRE_249, 6, 6)
connect _WIRE_248.pr, _T_3339
node _T_3340 = bits(_WIRE_249, 7, 7)
connect _WIRE_248.px, _T_3340
node _T_3341 = bits(_WIRE_249, 8, 8)
connect _WIRE_248.pw, _T_3341
node _T_3342 = bits(_WIRE_249, 9, 9)
connect _WIRE_248.hr, _T_3342
node _T_3343 = bits(_WIRE_249, 10, 10)
connect _WIRE_248.hx, _T_3343
node _T_3344 = bits(_WIRE_249, 11, 11)
connect _WIRE_248.hw, _T_3344
node _T_3345 = bits(_WIRE_249, 12, 12)
connect _WIRE_248.sr, _T_3345
node _T_3346 = bits(_WIRE_249, 13, 13)
connect _WIRE_248.sx, _T_3346
node _T_3347 = bits(_WIRE_249, 14, 14)
connect _WIRE_248.sw, _T_3347
node _T_3348 = bits(_WIRE_249, 15, 15)
connect _WIRE_248.gf, _T_3348
node _T_3349 = bits(_WIRE_249, 16, 16)
connect _WIRE_248.pf, _T_3349
node _T_3350 = bits(_WIRE_249, 17, 17)
connect _WIRE_248.ae_stage2, _T_3350
node _T_3351 = bits(_WIRE_249, 18, 18)
connect _WIRE_248.ae_final, _T_3351
node _T_3352 = bits(_WIRE_249, 19, 19)
connect _WIRE_248.ae_ptw, _T_3352
node _T_3353 = bits(_WIRE_249, 20, 20)
connect _WIRE_248.g, _T_3353
node _T_3354 = bits(_WIRE_249, 21, 21)
connect _WIRE_248.u, _T_3354
node _T_3355 = bits(_WIRE_249, 41, 22)
connect _WIRE_248.ppn, _T_3355
wire _WIRE_250 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_251 : UInt<42>
connect _WIRE_251, sectored_entries[0][7].data[1]
node _T_3356 = bits(_WIRE_251, 0, 0)
connect _WIRE_250.fragmented_superpage, _T_3356
node _T_3357 = bits(_WIRE_251, 1, 1)
connect _WIRE_250.c, _T_3357
node _T_3358 = bits(_WIRE_251, 2, 2)
connect _WIRE_250.eff, _T_3358
node _T_3359 = bits(_WIRE_251, 3, 3)
connect _WIRE_250.paa, _T_3359
node _T_3360 = bits(_WIRE_251, 4, 4)
connect _WIRE_250.pal, _T_3360
node _T_3361 = bits(_WIRE_251, 5, 5)
connect _WIRE_250.ppp, _T_3361
node _T_3362 = bits(_WIRE_251, 6, 6)
connect _WIRE_250.pr, _T_3362
node _T_3363 = bits(_WIRE_251, 7, 7)
connect _WIRE_250.px, _T_3363
node _T_3364 = bits(_WIRE_251, 8, 8)
connect _WIRE_250.pw, _T_3364
node _T_3365 = bits(_WIRE_251, 9, 9)
connect _WIRE_250.hr, _T_3365
node _T_3366 = bits(_WIRE_251, 10, 10)
connect _WIRE_250.hx, _T_3366
node _T_3367 = bits(_WIRE_251, 11, 11)
connect _WIRE_250.hw, _T_3367
node _T_3368 = bits(_WIRE_251, 12, 12)
connect _WIRE_250.sr, _T_3368
node _T_3369 = bits(_WIRE_251, 13, 13)
connect _WIRE_250.sx, _T_3369
node _T_3370 = bits(_WIRE_251, 14, 14)
connect _WIRE_250.sw, _T_3370
node _T_3371 = bits(_WIRE_251, 15, 15)
connect _WIRE_250.gf, _T_3371
node _T_3372 = bits(_WIRE_251, 16, 16)
connect _WIRE_250.pf, _T_3372
node _T_3373 = bits(_WIRE_251, 17, 17)
connect _WIRE_250.ae_stage2, _T_3373
node _T_3374 = bits(_WIRE_251, 18, 18)
connect _WIRE_250.ae_final, _T_3374
node _T_3375 = bits(_WIRE_251, 19, 19)
connect _WIRE_250.ae_ptw, _T_3375
node _T_3376 = bits(_WIRE_251, 20, 20)
connect _WIRE_250.g, _T_3376
node _T_3377 = bits(_WIRE_251, 21, 21)
connect _WIRE_250.u, _T_3377
node _T_3378 = bits(_WIRE_251, 41, 22)
connect _WIRE_250.ppn, _T_3378
wire _WIRE_252 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_253 : UInt<42>
connect _WIRE_253, sectored_entries[0][7].data[2]
node _T_3379 = bits(_WIRE_253, 0, 0)
connect _WIRE_252.fragmented_superpage, _T_3379
node _T_3380 = bits(_WIRE_253, 1, 1)
connect _WIRE_252.c, _T_3380
node _T_3381 = bits(_WIRE_253, 2, 2)
connect _WIRE_252.eff, _T_3381
node _T_3382 = bits(_WIRE_253, 3, 3)
connect _WIRE_252.paa, _T_3382
node _T_3383 = bits(_WIRE_253, 4, 4)
connect _WIRE_252.pal, _T_3383
node _T_3384 = bits(_WIRE_253, 5, 5)
connect _WIRE_252.ppp, _T_3384
node _T_3385 = bits(_WIRE_253, 6, 6)
connect _WIRE_252.pr, _T_3385
node _T_3386 = bits(_WIRE_253, 7, 7)
connect _WIRE_252.px, _T_3386
node _T_3387 = bits(_WIRE_253, 8, 8)
connect _WIRE_252.pw, _T_3387
node _T_3388 = bits(_WIRE_253, 9, 9)
connect _WIRE_252.hr, _T_3388
node _T_3389 = bits(_WIRE_253, 10, 10)
connect _WIRE_252.hx, _T_3389
node _T_3390 = bits(_WIRE_253, 11, 11)
connect _WIRE_252.hw, _T_3390
node _T_3391 = bits(_WIRE_253, 12, 12)
connect _WIRE_252.sr, _T_3391
node _T_3392 = bits(_WIRE_253, 13, 13)
connect _WIRE_252.sx, _T_3392
node _T_3393 = bits(_WIRE_253, 14, 14)
connect _WIRE_252.sw, _T_3393
node _T_3394 = bits(_WIRE_253, 15, 15)
connect _WIRE_252.gf, _T_3394
node _T_3395 = bits(_WIRE_253, 16, 16)
connect _WIRE_252.pf, _T_3395
node _T_3396 = bits(_WIRE_253, 17, 17)
connect _WIRE_252.ae_stage2, _T_3396
node _T_3397 = bits(_WIRE_253, 18, 18)
connect _WIRE_252.ae_final, _T_3397
node _T_3398 = bits(_WIRE_253, 19, 19)
connect _WIRE_252.ae_ptw, _T_3398
node _T_3399 = bits(_WIRE_253, 20, 20)
connect _WIRE_252.g, _T_3399
node _T_3400 = bits(_WIRE_253, 21, 21)
connect _WIRE_252.u, _T_3400
node _T_3401 = bits(_WIRE_253, 41, 22)
connect _WIRE_252.ppn, _T_3401
wire _WIRE_254 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_255 : UInt<42>
connect _WIRE_255, sectored_entries[0][7].data[3]
node _T_3402 = bits(_WIRE_255, 0, 0)
connect _WIRE_254.fragmented_superpage, _T_3402
node _T_3403 = bits(_WIRE_255, 1, 1)
connect _WIRE_254.c, _T_3403
node _T_3404 = bits(_WIRE_255, 2, 2)
connect _WIRE_254.eff, _T_3404
node _T_3405 = bits(_WIRE_255, 3, 3)
connect _WIRE_254.paa, _T_3405
node _T_3406 = bits(_WIRE_255, 4, 4)
connect _WIRE_254.pal, _T_3406
node _T_3407 = bits(_WIRE_255, 5, 5)
connect _WIRE_254.ppp, _T_3407
node _T_3408 = bits(_WIRE_255, 6, 6)
connect _WIRE_254.pr, _T_3408
node _T_3409 = bits(_WIRE_255, 7, 7)
connect _WIRE_254.px, _T_3409
node _T_3410 = bits(_WIRE_255, 8, 8)
connect _WIRE_254.pw, _T_3410
node _T_3411 = bits(_WIRE_255, 9, 9)
connect _WIRE_254.hr, _T_3411
node _T_3412 = bits(_WIRE_255, 10, 10)
connect _WIRE_254.hx, _T_3412
node _T_3413 = bits(_WIRE_255, 11, 11)
connect _WIRE_254.hw, _T_3413
node _T_3414 = bits(_WIRE_255, 12, 12)
connect _WIRE_254.sr, _T_3414
node _T_3415 = bits(_WIRE_255, 13, 13)
connect _WIRE_254.sx, _T_3415
node _T_3416 = bits(_WIRE_255, 14, 14)
connect _WIRE_254.sw, _T_3416
node _T_3417 = bits(_WIRE_255, 15, 15)
connect _WIRE_254.gf, _T_3417
node _T_3418 = bits(_WIRE_255, 16, 16)
connect _WIRE_254.pf, _T_3418
node _T_3419 = bits(_WIRE_255, 17, 17)
connect _WIRE_254.ae_stage2, _T_3419
node _T_3420 = bits(_WIRE_255, 18, 18)
connect _WIRE_254.ae_final, _T_3420
node _T_3421 = bits(_WIRE_255, 19, 19)
connect _WIRE_254.ae_ptw, _T_3421
node _T_3422 = bits(_WIRE_255, 20, 20)
connect _WIRE_254.g, _T_3422
node _T_3423 = bits(_WIRE_255, 21, 21)
connect _WIRE_254.u, _T_3423
node _T_3424 = bits(_WIRE_255, 41, 22)
connect _WIRE_254.ppn, _T_3424
node _T_3425 = eq(sectored_entries[0][7].tag_v, _T_3332)
when _T_3425 :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
node _T_3426 = eq(sectored_entries[0][7].tag_v, _T_3332)
when _T_3426 :
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
node _T_3427 = eq(sectored_entries[0][7].tag_v, _T_3332)
when _T_3427 :
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
node _T_3428 = eq(sectored_entries[0][7].tag_v, _T_3332)
when _T_3428 :
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
node hv_8 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_8 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_3429 = eq(hg_8, UInt<1>(0h0))
node _T_3430 = and(_T_3429, io.sfence.bits.rs1)
when _T_3430 :
node _tagMatch_T = eq(superpage_entries[0].tag_v, hv_8)
node tagMatch = and(superpage_entries[0].valid[0], _tagMatch_T)
node _ignore_T = lt(superpage_entries[0].level, UInt<1>(0h0))
node ignore = or(_ignore_T, UInt<1>(0h0))
node _T_3431 = xor(superpage_entries[0].tag_vpn, vpn)
node _T_3432 = bits(_T_3431, 26, 18)
node _T_3433 = eq(_T_3432, UInt<1>(0h0))
node _T_3434 = or(ignore, _T_3433)
node _T_3435 = and(tagMatch, _T_3434)
node _ignore_T_1 = lt(superpage_entries[0].level, UInt<1>(0h1))
node ignore_1 = or(_ignore_T_1, UInt<1>(0h0))
node _T_3436 = xor(superpage_entries[0].tag_vpn, vpn)
node _T_3437 = bits(_T_3436, 17, 9)
node _T_3438 = eq(_T_3437, UInt<1>(0h0))
node _T_3439 = or(ignore_1, _T_3438)
node _T_3440 = and(_T_3435, _T_3439)
node _ignore_T_2 = lt(superpage_entries[0].level, UInt<2>(0h2))
node ignore_2 = or(_ignore_T_2, UInt<1>(0h1))
node _T_3441 = xor(superpage_entries[0].tag_vpn, vpn)
node _T_3442 = bits(_T_3441, 8, 0)
node _T_3443 = eq(_T_3442, UInt<1>(0h0))
node _T_3444 = or(ignore_2, _T_3443)
node _T_3445 = and(_T_3440, _T_3444)
when _T_3445 :
connect superpage_entries[0].valid[0], UInt<1>(0h0)
node _T_3446 = xor(superpage_entries[0].tag_vpn, vpn)
node _T_3447 = shr(_T_3446, 18)
node _T_3448 = eq(_T_3447, UInt<1>(0h0))
when _T_3448 :
wire _WIRE_256 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_257 : UInt<42>
connect _WIRE_257, superpage_entries[0].data[0]
node _T_3449 = bits(_WIRE_257, 0, 0)
connect _WIRE_256.fragmented_superpage, _T_3449
node _T_3450 = bits(_WIRE_257, 1, 1)
connect _WIRE_256.c, _T_3450
node _T_3451 = bits(_WIRE_257, 2, 2)
connect _WIRE_256.eff, _T_3451
node _T_3452 = bits(_WIRE_257, 3, 3)
connect _WIRE_256.paa, _T_3452
node _T_3453 = bits(_WIRE_257, 4, 4)
connect _WIRE_256.pal, _T_3453
node _T_3454 = bits(_WIRE_257, 5, 5)
connect _WIRE_256.ppp, _T_3454
node _T_3455 = bits(_WIRE_257, 6, 6)
connect _WIRE_256.pr, _T_3455
node _T_3456 = bits(_WIRE_257, 7, 7)
connect _WIRE_256.px, _T_3456
node _T_3457 = bits(_WIRE_257, 8, 8)
connect _WIRE_256.pw, _T_3457
node _T_3458 = bits(_WIRE_257, 9, 9)
connect _WIRE_256.hr, _T_3458
node _T_3459 = bits(_WIRE_257, 10, 10)
connect _WIRE_256.hx, _T_3459
node _T_3460 = bits(_WIRE_257, 11, 11)
connect _WIRE_256.hw, _T_3460
node _T_3461 = bits(_WIRE_257, 12, 12)
connect _WIRE_256.sr, _T_3461
node _T_3462 = bits(_WIRE_257, 13, 13)
connect _WIRE_256.sx, _T_3462
node _T_3463 = bits(_WIRE_257, 14, 14)
connect _WIRE_256.sw, _T_3463
node _T_3464 = bits(_WIRE_257, 15, 15)
connect _WIRE_256.gf, _T_3464
node _T_3465 = bits(_WIRE_257, 16, 16)
connect _WIRE_256.pf, _T_3465
node _T_3466 = bits(_WIRE_257, 17, 17)
connect _WIRE_256.ae_stage2, _T_3466
node _T_3467 = bits(_WIRE_257, 18, 18)
connect _WIRE_256.ae_final, _T_3467
node _T_3468 = bits(_WIRE_257, 19, 19)
connect _WIRE_256.ae_ptw, _T_3468
node _T_3469 = bits(_WIRE_257, 20, 20)
connect _WIRE_256.g, _T_3469
node _T_3470 = bits(_WIRE_257, 21, 21)
connect _WIRE_256.u, _T_3470
node _T_3471 = bits(_WIRE_257, 41, 22)
connect _WIRE_256.ppn, _T_3471
node _T_3472 = eq(superpage_entries[0].tag_v, hv_8)
node _T_3473 = and(_T_3472, _WIRE_256.fragmented_superpage)
when _T_3473 :
connect superpage_entries[0].valid[0], UInt<1>(0h0)
else :
node _T_3474 = eq(hg_8, UInt<1>(0h0))
node _T_3475 = and(_T_3474, io.sfence.bits.rs2)
when _T_3475 :
wire _WIRE_258 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_259 : UInt<42>
connect _WIRE_259, superpage_entries[0].data[0]
node _T_3476 = bits(_WIRE_259, 0, 0)
connect _WIRE_258.fragmented_superpage, _T_3476
node _T_3477 = bits(_WIRE_259, 1, 1)
connect _WIRE_258.c, _T_3477
node _T_3478 = bits(_WIRE_259, 2, 2)
connect _WIRE_258.eff, _T_3478
node _T_3479 = bits(_WIRE_259, 3, 3)
connect _WIRE_258.paa, _T_3479
node _T_3480 = bits(_WIRE_259, 4, 4)
connect _WIRE_258.pal, _T_3480
node _T_3481 = bits(_WIRE_259, 5, 5)
connect _WIRE_258.ppp, _T_3481
node _T_3482 = bits(_WIRE_259, 6, 6)
connect _WIRE_258.pr, _T_3482
node _T_3483 = bits(_WIRE_259, 7, 7)
connect _WIRE_258.px, _T_3483
node _T_3484 = bits(_WIRE_259, 8, 8)
connect _WIRE_258.pw, _T_3484
node _T_3485 = bits(_WIRE_259, 9, 9)
connect _WIRE_258.hr, _T_3485
node _T_3486 = bits(_WIRE_259, 10, 10)
connect _WIRE_258.hx, _T_3486
node _T_3487 = bits(_WIRE_259, 11, 11)
connect _WIRE_258.hw, _T_3487
node _T_3488 = bits(_WIRE_259, 12, 12)
connect _WIRE_258.sr, _T_3488
node _T_3489 = bits(_WIRE_259, 13, 13)
connect _WIRE_258.sx, _T_3489
node _T_3490 = bits(_WIRE_259, 14, 14)
connect _WIRE_258.sw, _T_3490
node _T_3491 = bits(_WIRE_259, 15, 15)
connect _WIRE_258.gf, _T_3491
node _T_3492 = bits(_WIRE_259, 16, 16)
connect _WIRE_258.pf, _T_3492
node _T_3493 = bits(_WIRE_259, 17, 17)
connect _WIRE_258.ae_stage2, _T_3493
node _T_3494 = bits(_WIRE_259, 18, 18)
connect _WIRE_258.ae_final, _T_3494
node _T_3495 = bits(_WIRE_259, 19, 19)
connect _WIRE_258.ae_ptw, _T_3495
node _T_3496 = bits(_WIRE_259, 20, 20)
connect _WIRE_258.g, _T_3496
node _T_3497 = bits(_WIRE_259, 21, 21)
connect _WIRE_258.u, _T_3497
node _T_3498 = bits(_WIRE_259, 41, 22)
connect _WIRE_258.ppn, _T_3498
node _T_3499 = eq(superpage_entries[0].tag_v, hv_8)
node _T_3500 = eq(_WIRE_258.g, UInt<1>(0h0))
node _T_3501 = and(_T_3499, _T_3500)
when _T_3501 :
connect superpage_entries[0].valid[0], UInt<1>(0h0)
else :
node _T_3502 = or(hv_8, hg_8)
wire _WIRE_260 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_261 : UInt<42>
connect _WIRE_261, superpage_entries[0].data[0]
node _T_3503 = bits(_WIRE_261, 0, 0)
connect _WIRE_260.fragmented_superpage, _T_3503
node _T_3504 = bits(_WIRE_261, 1, 1)
connect _WIRE_260.c, _T_3504
node _T_3505 = bits(_WIRE_261, 2, 2)
connect _WIRE_260.eff, _T_3505
node _T_3506 = bits(_WIRE_261, 3, 3)
connect _WIRE_260.paa, _T_3506
node _T_3507 = bits(_WIRE_261, 4, 4)
connect _WIRE_260.pal, _T_3507
node _T_3508 = bits(_WIRE_261, 5, 5)
connect _WIRE_260.ppp, _T_3508
node _T_3509 = bits(_WIRE_261, 6, 6)
connect _WIRE_260.pr, _T_3509
node _T_3510 = bits(_WIRE_261, 7, 7)
connect _WIRE_260.px, _T_3510
node _T_3511 = bits(_WIRE_261, 8, 8)
connect _WIRE_260.pw, _T_3511
node _T_3512 = bits(_WIRE_261, 9, 9)
connect _WIRE_260.hr, _T_3512
node _T_3513 = bits(_WIRE_261, 10, 10)
connect _WIRE_260.hx, _T_3513
node _T_3514 = bits(_WIRE_261, 11, 11)
connect _WIRE_260.hw, _T_3514
node _T_3515 = bits(_WIRE_261, 12, 12)
connect _WIRE_260.sr, _T_3515
node _T_3516 = bits(_WIRE_261, 13, 13)
connect _WIRE_260.sx, _T_3516
node _T_3517 = bits(_WIRE_261, 14, 14)
connect _WIRE_260.sw, _T_3517
node _T_3518 = bits(_WIRE_261, 15, 15)
connect _WIRE_260.gf, _T_3518
node _T_3519 = bits(_WIRE_261, 16, 16)
connect _WIRE_260.pf, _T_3519
node _T_3520 = bits(_WIRE_261, 17, 17)
connect _WIRE_260.ae_stage2, _T_3520
node _T_3521 = bits(_WIRE_261, 18, 18)
connect _WIRE_260.ae_final, _T_3521
node _T_3522 = bits(_WIRE_261, 19, 19)
connect _WIRE_260.ae_ptw, _T_3522
node _T_3523 = bits(_WIRE_261, 20, 20)
connect _WIRE_260.g, _T_3523
node _T_3524 = bits(_WIRE_261, 21, 21)
connect _WIRE_260.u, _T_3524
node _T_3525 = bits(_WIRE_261, 41, 22)
connect _WIRE_260.ppn, _T_3525
node _T_3526 = eq(superpage_entries[0].tag_v, _T_3502)
when _T_3526 :
connect superpage_entries[0].valid[0], UInt<1>(0h0)
node hv_9 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_9 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_3527 = eq(hg_9, UInt<1>(0h0))
node _T_3528 = and(_T_3527, io.sfence.bits.rs1)
when _T_3528 :
node _tagMatch_T_1 = eq(superpage_entries[1].tag_v, hv_9)
node tagMatch_1 = and(superpage_entries[1].valid[0], _tagMatch_T_1)
node _ignore_T_3 = lt(superpage_entries[1].level, UInt<1>(0h0))
node ignore_3 = or(_ignore_T_3, UInt<1>(0h0))
node _T_3529 = xor(superpage_entries[1].tag_vpn, vpn)
node _T_3530 = bits(_T_3529, 26, 18)
node _T_3531 = eq(_T_3530, UInt<1>(0h0))
node _T_3532 = or(ignore_3, _T_3531)
node _T_3533 = and(tagMatch_1, _T_3532)
node _ignore_T_4 = lt(superpage_entries[1].level, UInt<1>(0h1))
node ignore_4 = or(_ignore_T_4, UInt<1>(0h0))
node _T_3534 = xor(superpage_entries[1].tag_vpn, vpn)
node _T_3535 = bits(_T_3534, 17, 9)
node _T_3536 = eq(_T_3535, UInt<1>(0h0))
node _T_3537 = or(ignore_4, _T_3536)
node _T_3538 = and(_T_3533, _T_3537)
node _ignore_T_5 = lt(superpage_entries[1].level, UInt<2>(0h2))
node ignore_5 = or(_ignore_T_5, UInt<1>(0h1))
node _T_3539 = xor(superpage_entries[1].tag_vpn, vpn)
node _T_3540 = bits(_T_3539, 8, 0)
node _T_3541 = eq(_T_3540, UInt<1>(0h0))
node _T_3542 = or(ignore_5, _T_3541)
node _T_3543 = and(_T_3538, _T_3542)
when _T_3543 :
connect superpage_entries[1].valid[0], UInt<1>(0h0)
node _T_3544 = xor(superpage_entries[1].tag_vpn, vpn)
node _T_3545 = shr(_T_3544, 18)
node _T_3546 = eq(_T_3545, UInt<1>(0h0))
when _T_3546 :
wire _WIRE_262 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_263 : UInt<42>
connect _WIRE_263, superpage_entries[1].data[0]
node _T_3547 = bits(_WIRE_263, 0, 0)
connect _WIRE_262.fragmented_superpage, _T_3547
node _T_3548 = bits(_WIRE_263, 1, 1)
connect _WIRE_262.c, _T_3548
node _T_3549 = bits(_WIRE_263, 2, 2)
connect _WIRE_262.eff, _T_3549
node _T_3550 = bits(_WIRE_263, 3, 3)
connect _WIRE_262.paa, _T_3550
node _T_3551 = bits(_WIRE_263, 4, 4)
connect _WIRE_262.pal, _T_3551
node _T_3552 = bits(_WIRE_263, 5, 5)
connect _WIRE_262.ppp, _T_3552
node _T_3553 = bits(_WIRE_263, 6, 6)
connect _WIRE_262.pr, _T_3553
node _T_3554 = bits(_WIRE_263, 7, 7)
connect _WIRE_262.px, _T_3554
node _T_3555 = bits(_WIRE_263, 8, 8)
connect _WIRE_262.pw, _T_3555
node _T_3556 = bits(_WIRE_263, 9, 9)
connect _WIRE_262.hr, _T_3556
node _T_3557 = bits(_WIRE_263, 10, 10)
connect _WIRE_262.hx, _T_3557
node _T_3558 = bits(_WIRE_263, 11, 11)
connect _WIRE_262.hw, _T_3558
node _T_3559 = bits(_WIRE_263, 12, 12)
connect _WIRE_262.sr, _T_3559
node _T_3560 = bits(_WIRE_263, 13, 13)
connect _WIRE_262.sx, _T_3560
node _T_3561 = bits(_WIRE_263, 14, 14)
connect _WIRE_262.sw, _T_3561
node _T_3562 = bits(_WIRE_263, 15, 15)
connect _WIRE_262.gf, _T_3562
node _T_3563 = bits(_WIRE_263, 16, 16)
connect _WIRE_262.pf, _T_3563
node _T_3564 = bits(_WIRE_263, 17, 17)
connect _WIRE_262.ae_stage2, _T_3564
node _T_3565 = bits(_WIRE_263, 18, 18)
connect _WIRE_262.ae_final, _T_3565
node _T_3566 = bits(_WIRE_263, 19, 19)
connect _WIRE_262.ae_ptw, _T_3566
node _T_3567 = bits(_WIRE_263, 20, 20)
connect _WIRE_262.g, _T_3567
node _T_3568 = bits(_WIRE_263, 21, 21)
connect _WIRE_262.u, _T_3568
node _T_3569 = bits(_WIRE_263, 41, 22)
connect _WIRE_262.ppn, _T_3569
node _T_3570 = eq(superpage_entries[1].tag_v, hv_9)
node _T_3571 = and(_T_3570, _WIRE_262.fragmented_superpage)
when _T_3571 :
connect superpage_entries[1].valid[0], UInt<1>(0h0)
else :
node _T_3572 = eq(hg_9, UInt<1>(0h0))
node _T_3573 = and(_T_3572, io.sfence.bits.rs2)
when _T_3573 :
wire _WIRE_264 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_265 : UInt<42>
connect _WIRE_265, superpage_entries[1].data[0]
node _T_3574 = bits(_WIRE_265, 0, 0)
connect _WIRE_264.fragmented_superpage, _T_3574
node _T_3575 = bits(_WIRE_265, 1, 1)
connect _WIRE_264.c, _T_3575
node _T_3576 = bits(_WIRE_265, 2, 2)
connect _WIRE_264.eff, _T_3576
node _T_3577 = bits(_WIRE_265, 3, 3)
connect _WIRE_264.paa, _T_3577
node _T_3578 = bits(_WIRE_265, 4, 4)
connect _WIRE_264.pal, _T_3578
node _T_3579 = bits(_WIRE_265, 5, 5)
connect _WIRE_264.ppp, _T_3579
node _T_3580 = bits(_WIRE_265, 6, 6)
connect _WIRE_264.pr, _T_3580
node _T_3581 = bits(_WIRE_265, 7, 7)
connect _WIRE_264.px, _T_3581
node _T_3582 = bits(_WIRE_265, 8, 8)
connect _WIRE_264.pw, _T_3582
node _T_3583 = bits(_WIRE_265, 9, 9)
connect _WIRE_264.hr, _T_3583
node _T_3584 = bits(_WIRE_265, 10, 10)
connect _WIRE_264.hx, _T_3584
node _T_3585 = bits(_WIRE_265, 11, 11)
connect _WIRE_264.hw, _T_3585
node _T_3586 = bits(_WIRE_265, 12, 12)
connect _WIRE_264.sr, _T_3586
node _T_3587 = bits(_WIRE_265, 13, 13)
connect _WIRE_264.sx, _T_3587
node _T_3588 = bits(_WIRE_265, 14, 14)
connect _WIRE_264.sw, _T_3588
node _T_3589 = bits(_WIRE_265, 15, 15)
connect _WIRE_264.gf, _T_3589
node _T_3590 = bits(_WIRE_265, 16, 16)
connect _WIRE_264.pf, _T_3590
node _T_3591 = bits(_WIRE_265, 17, 17)
connect _WIRE_264.ae_stage2, _T_3591
node _T_3592 = bits(_WIRE_265, 18, 18)
connect _WIRE_264.ae_final, _T_3592
node _T_3593 = bits(_WIRE_265, 19, 19)
connect _WIRE_264.ae_ptw, _T_3593
node _T_3594 = bits(_WIRE_265, 20, 20)
connect _WIRE_264.g, _T_3594
node _T_3595 = bits(_WIRE_265, 21, 21)
connect _WIRE_264.u, _T_3595
node _T_3596 = bits(_WIRE_265, 41, 22)
connect _WIRE_264.ppn, _T_3596
node _T_3597 = eq(superpage_entries[1].tag_v, hv_9)
node _T_3598 = eq(_WIRE_264.g, UInt<1>(0h0))
node _T_3599 = and(_T_3597, _T_3598)
when _T_3599 :
connect superpage_entries[1].valid[0], UInt<1>(0h0)
else :
node _T_3600 = or(hv_9, hg_9)
wire _WIRE_266 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_267 : UInt<42>
connect _WIRE_267, superpage_entries[1].data[0]
node _T_3601 = bits(_WIRE_267, 0, 0)
connect _WIRE_266.fragmented_superpage, _T_3601
node _T_3602 = bits(_WIRE_267, 1, 1)
connect _WIRE_266.c, _T_3602
node _T_3603 = bits(_WIRE_267, 2, 2)
connect _WIRE_266.eff, _T_3603
node _T_3604 = bits(_WIRE_267, 3, 3)
connect _WIRE_266.paa, _T_3604
node _T_3605 = bits(_WIRE_267, 4, 4)
connect _WIRE_266.pal, _T_3605
node _T_3606 = bits(_WIRE_267, 5, 5)
connect _WIRE_266.ppp, _T_3606
node _T_3607 = bits(_WIRE_267, 6, 6)
connect _WIRE_266.pr, _T_3607
node _T_3608 = bits(_WIRE_267, 7, 7)
connect _WIRE_266.px, _T_3608
node _T_3609 = bits(_WIRE_267, 8, 8)
connect _WIRE_266.pw, _T_3609
node _T_3610 = bits(_WIRE_267, 9, 9)
connect _WIRE_266.hr, _T_3610
node _T_3611 = bits(_WIRE_267, 10, 10)
connect _WIRE_266.hx, _T_3611
node _T_3612 = bits(_WIRE_267, 11, 11)
connect _WIRE_266.hw, _T_3612
node _T_3613 = bits(_WIRE_267, 12, 12)
connect _WIRE_266.sr, _T_3613
node _T_3614 = bits(_WIRE_267, 13, 13)
connect _WIRE_266.sx, _T_3614
node _T_3615 = bits(_WIRE_267, 14, 14)
connect _WIRE_266.sw, _T_3615
node _T_3616 = bits(_WIRE_267, 15, 15)
connect _WIRE_266.gf, _T_3616
node _T_3617 = bits(_WIRE_267, 16, 16)
connect _WIRE_266.pf, _T_3617
node _T_3618 = bits(_WIRE_267, 17, 17)
connect _WIRE_266.ae_stage2, _T_3618
node _T_3619 = bits(_WIRE_267, 18, 18)
connect _WIRE_266.ae_final, _T_3619
node _T_3620 = bits(_WIRE_267, 19, 19)
connect _WIRE_266.ae_ptw, _T_3620
node _T_3621 = bits(_WIRE_267, 20, 20)
connect _WIRE_266.g, _T_3621
node _T_3622 = bits(_WIRE_267, 21, 21)
connect _WIRE_266.u, _T_3622
node _T_3623 = bits(_WIRE_267, 41, 22)
connect _WIRE_266.ppn, _T_3623
node _T_3624 = eq(superpage_entries[1].tag_v, _T_3600)
when _T_3624 :
connect superpage_entries[1].valid[0], UInt<1>(0h0)
node hv_10 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_10 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_3625 = eq(hg_10, UInt<1>(0h0))
node _T_3626 = and(_T_3625, io.sfence.bits.rs1)
when _T_3626 :
node _tagMatch_T_2 = eq(superpage_entries[2].tag_v, hv_10)
node tagMatch_2 = and(superpage_entries[2].valid[0], _tagMatch_T_2)
node _ignore_T_6 = lt(superpage_entries[2].level, UInt<1>(0h0))
node ignore_6 = or(_ignore_T_6, UInt<1>(0h0))
node _T_3627 = xor(superpage_entries[2].tag_vpn, vpn)
node _T_3628 = bits(_T_3627, 26, 18)
node _T_3629 = eq(_T_3628, UInt<1>(0h0))
node _T_3630 = or(ignore_6, _T_3629)
node _T_3631 = and(tagMatch_2, _T_3630)
node _ignore_T_7 = lt(superpage_entries[2].level, UInt<1>(0h1))
node ignore_7 = or(_ignore_T_7, UInt<1>(0h0))
node _T_3632 = xor(superpage_entries[2].tag_vpn, vpn)
node _T_3633 = bits(_T_3632, 17, 9)
node _T_3634 = eq(_T_3633, UInt<1>(0h0))
node _T_3635 = or(ignore_7, _T_3634)
node _T_3636 = and(_T_3631, _T_3635)
node _ignore_T_8 = lt(superpage_entries[2].level, UInt<2>(0h2))
node ignore_8 = or(_ignore_T_8, UInt<1>(0h1))
node _T_3637 = xor(superpage_entries[2].tag_vpn, vpn)
node _T_3638 = bits(_T_3637, 8, 0)
node _T_3639 = eq(_T_3638, UInt<1>(0h0))
node _T_3640 = or(ignore_8, _T_3639)
node _T_3641 = and(_T_3636, _T_3640)
when _T_3641 :
connect superpage_entries[2].valid[0], UInt<1>(0h0)
node _T_3642 = xor(superpage_entries[2].tag_vpn, vpn)
node _T_3643 = shr(_T_3642, 18)
node _T_3644 = eq(_T_3643, UInt<1>(0h0))
when _T_3644 :
wire _WIRE_268 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_269 : UInt<42>
connect _WIRE_269, superpage_entries[2].data[0]
node _T_3645 = bits(_WIRE_269, 0, 0)
connect _WIRE_268.fragmented_superpage, _T_3645
node _T_3646 = bits(_WIRE_269, 1, 1)
connect _WIRE_268.c, _T_3646
node _T_3647 = bits(_WIRE_269, 2, 2)
connect _WIRE_268.eff, _T_3647
node _T_3648 = bits(_WIRE_269, 3, 3)
connect _WIRE_268.paa, _T_3648
node _T_3649 = bits(_WIRE_269, 4, 4)
connect _WIRE_268.pal, _T_3649
node _T_3650 = bits(_WIRE_269, 5, 5)
connect _WIRE_268.ppp, _T_3650
node _T_3651 = bits(_WIRE_269, 6, 6)
connect _WIRE_268.pr, _T_3651
node _T_3652 = bits(_WIRE_269, 7, 7)
connect _WIRE_268.px, _T_3652
node _T_3653 = bits(_WIRE_269, 8, 8)
connect _WIRE_268.pw, _T_3653
node _T_3654 = bits(_WIRE_269, 9, 9)
connect _WIRE_268.hr, _T_3654
node _T_3655 = bits(_WIRE_269, 10, 10)
connect _WIRE_268.hx, _T_3655
node _T_3656 = bits(_WIRE_269, 11, 11)
connect _WIRE_268.hw, _T_3656
node _T_3657 = bits(_WIRE_269, 12, 12)
connect _WIRE_268.sr, _T_3657
node _T_3658 = bits(_WIRE_269, 13, 13)
connect _WIRE_268.sx, _T_3658
node _T_3659 = bits(_WIRE_269, 14, 14)
connect _WIRE_268.sw, _T_3659
node _T_3660 = bits(_WIRE_269, 15, 15)
connect _WIRE_268.gf, _T_3660
node _T_3661 = bits(_WIRE_269, 16, 16)
connect _WIRE_268.pf, _T_3661
node _T_3662 = bits(_WIRE_269, 17, 17)
connect _WIRE_268.ae_stage2, _T_3662
node _T_3663 = bits(_WIRE_269, 18, 18)
connect _WIRE_268.ae_final, _T_3663
node _T_3664 = bits(_WIRE_269, 19, 19)
connect _WIRE_268.ae_ptw, _T_3664
node _T_3665 = bits(_WIRE_269, 20, 20)
connect _WIRE_268.g, _T_3665
node _T_3666 = bits(_WIRE_269, 21, 21)
connect _WIRE_268.u, _T_3666
node _T_3667 = bits(_WIRE_269, 41, 22)
connect _WIRE_268.ppn, _T_3667
node _T_3668 = eq(superpage_entries[2].tag_v, hv_10)
node _T_3669 = and(_T_3668, _WIRE_268.fragmented_superpage)
when _T_3669 :
connect superpage_entries[2].valid[0], UInt<1>(0h0)
else :
node _T_3670 = eq(hg_10, UInt<1>(0h0))
node _T_3671 = and(_T_3670, io.sfence.bits.rs2)
when _T_3671 :
wire _WIRE_270 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_271 : UInt<42>
connect _WIRE_271, superpage_entries[2].data[0]
node _T_3672 = bits(_WIRE_271, 0, 0)
connect _WIRE_270.fragmented_superpage, _T_3672
node _T_3673 = bits(_WIRE_271, 1, 1)
connect _WIRE_270.c, _T_3673
node _T_3674 = bits(_WIRE_271, 2, 2)
connect _WIRE_270.eff, _T_3674
node _T_3675 = bits(_WIRE_271, 3, 3)
connect _WIRE_270.paa, _T_3675
node _T_3676 = bits(_WIRE_271, 4, 4)
connect _WIRE_270.pal, _T_3676
node _T_3677 = bits(_WIRE_271, 5, 5)
connect _WIRE_270.ppp, _T_3677
node _T_3678 = bits(_WIRE_271, 6, 6)
connect _WIRE_270.pr, _T_3678
node _T_3679 = bits(_WIRE_271, 7, 7)
connect _WIRE_270.px, _T_3679
node _T_3680 = bits(_WIRE_271, 8, 8)
connect _WIRE_270.pw, _T_3680
node _T_3681 = bits(_WIRE_271, 9, 9)
connect _WIRE_270.hr, _T_3681
node _T_3682 = bits(_WIRE_271, 10, 10)
connect _WIRE_270.hx, _T_3682
node _T_3683 = bits(_WIRE_271, 11, 11)
connect _WIRE_270.hw, _T_3683
node _T_3684 = bits(_WIRE_271, 12, 12)
connect _WIRE_270.sr, _T_3684
node _T_3685 = bits(_WIRE_271, 13, 13)
connect _WIRE_270.sx, _T_3685
node _T_3686 = bits(_WIRE_271, 14, 14)
connect _WIRE_270.sw, _T_3686
node _T_3687 = bits(_WIRE_271, 15, 15)
connect _WIRE_270.gf, _T_3687
node _T_3688 = bits(_WIRE_271, 16, 16)
connect _WIRE_270.pf, _T_3688
node _T_3689 = bits(_WIRE_271, 17, 17)
connect _WIRE_270.ae_stage2, _T_3689
node _T_3690 = bits(_WIRE_271, 18, 18)
connect _WIRE_270.ae_final, _T_3690
node _T_3691 = bits(_WIRE_271, 19, 19)
connect _WIRE_270.ae_ptw, _T_3691
node _T_3692 = bits(_WIRE_271, 20, 20)
connect _WIRE_270.g, _T_3692
node _T_3693 = bits(_WIRE_271, 21, 21)
connect _WIRE_270.u, _T_3693
node _T_3694 = bits(_WIRE_271, 41, 22)
connect _WIRE_270.ppn, _T_3694
node _T_3695 = eq(superpage_entries[2].tag_v, hv_10)
node _T_3696 = eq(_WIRE_270.g, UInt<1>(0h0))
node _T_3697 = and(_T_3695, _T_3696)
when _T_3697 :
connect superpage_entries[2].valid[0], UInt<1>(0h0)
else :
node _T_3698 = or(hv_10, hg_10)
wire _WIRE_272 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_273 : UInt<42>
connect _WIRE_273, superpage_entries[2].data[0]
node _T_3699 = bits(_WIRE_273, 0, 0)
connect _WIRE_272.fragmented_superpage, _T_3699
node _T_3700 = bits(_WIRE_273, 1, 1)
connect _WIRE_272.c, _T_3700
node _T_3701 = bits(_WIRE_273, 2, 2)
connect _WIRE_272.eff, _T_3701
node _T_3702 = bits(_WIRE_273, 3, 3)
connect _WIRE_272.paa, _T_3702
node _T_3703 = bits(_WIRE_273, 4, 4)
connect _WIRE_272.pal, _T_3703
node _T_3704 = bits(_WIRE_273, 5, 5)
connect _WIRE_272.ppp, _T_3704
node _T_3705 = bits(_WIRE_273, 6, 6)
connect _WIRE_272.pr, _T_3705
node _T_3706 = bits(_WIRE_273, 7, 7)
connect _WIRE_272.px, _T_3706
node _T_3707 = bits(_WIRE_273, 8, 8)
connect _WIRE_272.pw, _T_3707
node _T_3708 = bits(_WIRE_273, 9, 9)
connect _WIRE_272.hr, _T_3708
node _T_3709 = bits(_WIRE_273, 10, 10)
connect _WIRE_272.hx, _T_3709
node _T_3710 = bits(_WIRE_273, 11, 11)
connect _WIRE_272.hw, _T_3710
node _T_3711 = bits(_WIRE_273, 12, 12)
connect _WIRE_272.sr, _T_3711
node _T_3712 = bits(_WIRE_273, 13, 13)
connect _WIRE_272.sx, _T_3712
node _T_3713 = bits(_WIRE_273, 14, 14)
connect _WIRE_272.sw, _T_3713
node _T_3714 = bits(_WIRE_273, 15, 15)
connect _WIRE_272.gf, _T_3714
node _T_3715 = bits(_WIRE_273, 16, 16)
connect _WIRE_272.pf, _T_3715
node _T_3716 = bits(_WIRE_273, 17, 17)
connect _WIRE_272.ae_stage2, _T_3716
node _T_3717 = bits(_WIRE_273, 18, 18)
connect _WIRE_272.ae_final, _T_3717
node _T_3718 = bits(_WIRE_273, 19, 19)
connect _WIRE_272.ae_ptw, _T_3718
node _T_3719 = bits(_WIRE_273, 20, 20)
connect _WIRE_272.g, _T_3719
node _T_3720 = bits(_WIRE_273, 21, 21)
connect _WIRE_272.u, _T_3720
node _T_3721 = bits(_WIRE_273, 41, 22)
connect _WIRE_272.ppn, _T_3721
node _T_3722 = eq(superpage_entries[2].tag_v, _T_3698)
when _T_3722 :
connect superpage_entries[2].valid[0], UInt<1>(0h0)
node hv_11 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_11 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_3723 = eq(hg_11, UInt<1>(0h0))
node _T_3724 = and(_T_3723, io.sfence.bits.rs1)
when _T_3724 :
node _tagMatch_T_3 = eq(superpage_entries[3].tag_v, hv_11)
node tagMatch_3 = and(superpage_entries[3].valid[0], _tagMatch_T_3)
node _ignore_T_9 = lt(superpage_entries[3].level, UInt<1>(0h0))
node ignore_9 = or(_ignore_T_9, UInt<1>(0h0))
node _T_3725 = xor(superpage_entries[3].tag_vpn, vpn)
node _T_3726 = bits(_T_3725, 26, 18)
node _T_3727 = eq(_T_3726, UInt<1>(0h0))
node _T_3728 = or(ignore_9, _T_3727)
node _T_3729 = and(tagMatch_3, _T_3728)
node _ignore_T_10 = lt(superpage_entries[3].level, UInt<1>(0h1))
node ignore_10 = or(_ignore_T_10, UInt<1>(0h0))
node _T_3730 = xor(superpage_entries[3].tag_vpn, vpn)
node _T_3731 = bits(_T_3730, 17, 9)
node _T_3732 = eq(_T_3731, UInt<1>(0h0))
node _T_3733 = or(ignore_10, _T_3732)
node _T_3734 = and(_T_3729, _T_3733)
node _ignore_T_11 = lt(superpage_entries[3].level, UInt<2>(0h2))
node ignore_11 = or(_ignore_T_11, UInt<1>(0h1))
node _T_3735 = xor(superpage_entries[3].tag_vpn, vpn)
node _T_3736 = bits(_T_3735, 8, 0)
node _T_3737 = eq(_T_3736, UInt<1>(0h0))
node _T_3738 = or(ignore_11, _T_3737)
node _T_3739 = and(_T_3734, _T_3738)
when _T_3739 :
connect superpage_entries[3].valid[0], UInt<1>(0h0)
node _T_3740 = xor(superpage_entries[3].tag_vpn, vpn)
node _T_3741 = shr(_T_3740, 18)
node _T_3742 = eq(_T_3741, UInt<1>(0h0))
when _T_3742 :
wire _WIRE_274 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_275 : UInt<42>
connect _WIRE_275, superpage_entries[3].data[0]
node _T_3743 = bits(_WIRE_275, 0, 0)
connect _WIRE_274.fragmented_superpage, _T_3743
node _T_3744 = bits(_WIRE_275, 1, 1)
connect _WIRE_274.c, _T_3744
node _T_3745 = bits(_WIRE_275, 2, 2)
connect _WIRE_274.eff, _T_3745
node _T_3746 = bits(_WIRE_275, 3, 3)
connect _WIRE_274.paa, _T_3746
node _T_3747 = bits(_WIRE_275, 4, 4)
connect _WIRE_274.pal, _T_3747
node _T_3748 = bits(_WIRE_275, 5, 5)
connect _WIRE_274.ppp, _T_3748
node _T_3749 = bits(_WIRE_275, 6, 6)
connect _WIRE_274.pr, _T_3749
node _T_3750 = bits(_WIRE_275, 7, 7)
connect _WIRE_274.px, _T_3750
node _T_3751 = bits(_WIRE_275, 8, 8)
connect _WIRE_274.pw, _T_3751
node _T_3752 = bits(_WIRE_275, 9, 9)
connect _WIRE_274.hr, _T_3752
node _T_3753 = bits(_WIRE_275, 10, 10)
connect _WIRE_274.hx, _T_3753
node _T_3754 = bits(_WIRE_275, 11, 11)
connect _WIRE_274.hw, _T_3754
node _T_3755 = bits(_WIRE_275, 12, 12)
connect _WIRE_274.sr, _T_3755
node _T_3756 = bits(_WIRE_275, 13, 13)
connect _WIRE_274.sx, _T_3756
node _T_3757 = bits(_WIRE_275, 14, 14)
connect _WIRE_274.sw, _T_3757
node _T_3758 = bits(_WIRE_275, 15, 15)
connect _WIRE_274.gf, _T_3758
node _T_3759 = bits(_WIRE_275, 16, 16)
connect _WIRE_274.pf, _T_3759
node _T_3760 = bits(_WIRE_275, 17, 17)
connect _WIRE_274.ae_stage2, _T_3760
node _T_3761 = bits(_WIRE_275, 18, 18)
connect _WIRE_274.ae_final, _T_3761
node _T_3762 = bits(_WIRE_275, 19, 19)
connect _WIRE_274.ae_ptw, _T_3762
node _T_3763 = bits(_WIRE_275, 20, 20)
connect _WIRE_274.g, _T_3763
node _T_3764 = bits(_WIRE_275, 21, 21)
connect _WIRE_274.u, _T_3764
node _T_3765 = bits(_WIRE_275, 41, 22)
connect _WIRE_274.ppn, _T_3765
node _T_3766 = eq(superpage_entries[3].tag_v, hv_11)
node _T_3767 = and(_T_3766, _WIRE_274.fragmented_superpage)
when _T_3767 :
connect superpage_entries[3].valid[0], UInt<1>(0h0)
else :
node _T_3768 = eq(hg_11, UInt<1>(0h0))
node _T_3769 = and(_T_3768, io.sfence.bits.rs2)
when _T_3769 :
wire _WIRE_276 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_277 : UInt<42>
connect _WIRE_277, superpage_entries[3].data[0]
node _T_3770 = bits(_WIRE_277, 0, 0)
connect _WIRE_276.fragmented_superpage, _T_3770
node _T_3771 = bits(_WIRE_277, 1, 1)
connect _WIRE_276.c, _T_3771
node _T_3772 = bits(_WIRE_277, 2, 2)
connect _WIRE_276.eff, _T_3772
node _T_3773 = bits(_WIRE_277, 3, 3)
connect _WIRE_276.paa, _T_3773
node _T_3774 = bits(_WIRE_277, 4, 4)
connect _WIRE_276.pal, _T_3774
node _T_3775 = bits(_WIRE_277, 5, 5)
connect _WIRE_276.ppp, _T_3775
node _T_3776 = bits(_WIRE_277, 6, 6)
connect _WIRE_276.pr, _T_3776
node _T_3777 = bits(_WIRE_277, 7, 7)
connect _WIRE_276.px, _T_3777
node _T_3778 = bits(_WIRE_277, 8, 8)
connect _WIRE_276.pw, _T_3778
node _T_3779 = bits(_WIRE_277, 9, 9)
connect _WIRE_276.hr, _T_3779
node _T_3780 = bits(_WIRE_277, 10, 10)
connect _WIRE_276.hx, _T_3780
node _T_3781 = bits(_WIRE_277, 11, 11)
connect _WIRE_276.hw, _T_3781
node _T_3782 = bits(_WIRE_277, 12, 12)
connect _WIRE_276.sr, _T_3782
node _T_3783 = bits(_WIRE_277, 13, 13)
connect _WIRE_276.sx, _T_3783
node _T_3784 = bits(_WIRE_277, 14, 14)
connect _WIRE_276.sw, _T_3784
node _T_3785 = bits(_WIRE_277, 15, 15)
connect _WIRE_276.gf, _T_3785
node _T_3786 = bits(_WIRE_277, 16, 16)
connect _WIRE_276.pf, _T_3786
node _T_3787 = bits(_WIRE_277, 17, 17)
connect _WIRE_276.ae_stage2, _T_3787
node _T_3788 = bits(_WIRE_277, 18, 18)
connect _WIRE_276.ae_final, _T_3788
node _T_3789 = bits(_WIRE_277, 19, 19)
connect _WIRE_276.ae_ptw, _T_3789
node _T_3790 = bits(_WIRE_277, 20, 20)
connect _WIRE_276.g, _T_3790
node _T_3791 = bits(_WIRE_277, 21, 21)
connect _WIRE_276.u, _T_3791
node _T_3792 = bits(_WIRE_277, 41, 22)
connect _WIRE_276.ppn, _T_3792
node _T_3793 = eq(superpage_entries[3].tag_v, hv_11)
node _T_3794 = eq(_WIRE_276.g, UInt<1>(0h0))
node _T_3795 = and(_T_3793, _T_3794)
when _T_3795 :
connect superpage_entries[3].valid[0], UInt<1>(0h0)
else :
node _T_3796 = or(hv_11, hg_11)
wire _WIRE_278 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_279 : UInt<42>
connect _WIRE_279, superpage_entries[3].data[0]
node _T_3797 = bits(_WIRE_279, 0, 0)
connect _WIRE_278.fragmented_superpage, _T_3797
node _T_3798 = bits(_WIRE_279, 1, 1)
connect _WIRE_278.c, _T_3798
node _T_3799 = bits(_WIRE_279, 2, 2)
connect _WIRE_278.eff, _T_3799
node _T_3800 = bits(_WIRE_279, 3, 3)
connect _WIRE_278.paa, _T_3800
node _T_3801 = bits(_WIRE_279, 4, 4)
connect _WIRE_278.pal, _T_3801
node _T_3802 = bits(_WIRE_279, 5, 5)
connect _WIRE_278.ppp, _T_3802
node _T_3803 = bits(_WIRE_279, 6, 6)
connect _WIRE_278.pr, _T_3803
node _T_3804 = bits(_WIRE_279, 7, 7)
connect _WIRE_278.px, _T_3804
node _T_3805 = bits(_WIRE_279, 8, 8)
connect _WIRE_278.pw, _T_3805
node _T_3806 = bits(_WIRE_279, 9, 9)
connect _WIRE_278.hr, _T_3806
node _T_3807 = bits(_WIRE_279, 10, 10)
connect _WIRE_278.hx, _T_3807
node _T_3808 = bits(_WIRE_279, 11, 11)
connect _WIRE_278.hw, _T_3808
node _T_3809 = bits(_WIRE_279, 12, 12)
connect _WIRE_278.sr, _T_3809
node _T_3810 = bits(_WIRE_279, 13, 13)
connect _WIRE_278.sx, _T_3810
node _T_3811 = bits(_WIRE_279, 14, 14)
connect _WIRE_278.sw, _T_3811
node _T_3812 = bits(_WIRE_279, 15, 15)
connect _WIRE_278.gf, _T_3812
node _T_3813 = bits(_WIRE_279, 16, 16)
connect _WIRE_278.pf, _T_3813
node _T_3814 = bits(_WIRE_279, 17, 17)
connect _WIRE_278.ae_stage2, _T_3814
node _T_3815 = bits(_WIRE_279, 18, 18)
connect _WIRE_278.ae_final, _T_3815
node _T_3816 = bits(_WIRE_279, 19, 19)
connect _WIRE_278.ae_ptw, _T_3816
node _T_3817 = bits(_WIRE_279, 20, 20)
connect _WIRE_278.g, _T_3817
node _T_3818 = bits(_WIRE_279, 21, 21)
connect _WIRE_278.u, _T_3818
node _T_3819 = bits(_WIRE_279, 41, 22)
connect _WIRE_278.ppn, _T_3819
node _T_3820 = eq(superpage_entries[3].tag_v, _T_3796)
when _T_3820 :
connect superpage_entries[3].valid[0], UInt<1>(0h0)
node hv_12 = and(UInt<1>(0h0), io.sfence.bits.hv)
node hg_12 = and(UInt<1>(0h0), io.sfence.bits.hg)
node _T_3821 = eq(hg_12, UInt<1>(0h0))
node _T_3822 = and(_T_3821, io.sfence.bits.rs1)
when _T_3822 :
node _tagMatch_T_4 = eq(special_entry.tag_v, hv_12)
node tagMatch_4 = and(special_entry.valid[0], _tagMatch_T_4)
node _ignore_T_12 = lt(special_entry.level, UInt<1>(0h0))
node ignore_12 = or(_ignore_T_12, UInt<1>(0h0))
node _T_3823 = xor(special_entry.tag_vpn, vpn)
node _T_3824 = bits(_T_3823, 26, 18)
node _T_3825 = eq(_T_3824, UInt<1>(0h0))
node _T_3826 = or(ignore_12, _T_3825)
node _T_3827 = and(tagMatch_4, _T_3826)
node _ignore_T_13 = lt(special_entry.level, UInt<1>(0h1))
node ignore_13 = or(_ignore_T_13, UInt<1>(0h0))
node _T_3828 = xor(special_entry.tag_vpn, vpn)
node _T_3829 = bits(_T_3828, 17, 9)
node _T_3830 = eq(_T_3829, UInt<1>(0h0))
node _T_3831 = or(ignore_13, _T_3830)
node _T_3832 = and(_T_3827, _T_3831)
node _ignore_T_14 = lt(special_entry.level, UInt<2>(0h2))
node ignore_14 = or(_ignore_T_14, UInt<1>(0h0))
node _T_3833 = xor(special_entry.tag_vpn, vpn)
node _T_3834 = bits(_T_3833, 8, 0)
node _T_3835 = eq(_T_3834, UInt<1>(0h0))
node _T_3836 = or(ignore_14, _T_3835)
node _T_3837 = and(_T_3832, _T_3836)
when _T_3837 :
connect special_entry.valid[0], UInt<1>(0h0)
node _T_3838 = xor(special_entry.tag_vpn, vpn)
node _T_3839 = shr(_T_3838, 18)
node _T_3840 = eq(_T_3839, UInt<1>(0h0))
when _T_3840 :
wire _WIRE_280 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_281 : UInt<42>
connect _WIRE_281, special_entry.data[0]
node _T_3841 = bits(_WIRE_281, 0, 0)
connect _WIRE_280.fragmented_superpage, _T_3841
node _T_3842 = bits(_WIRE_281, 1, 1)
connect _WIRE_280.c, _T_3842
node _T_3843 = bits(_WIRE_281, 2, 2)
connect _WIRE_280.eff, _T_3843
node _T_3844 = bits(_WIRE_281, 3, 3)
connect _WIRE_280.paa, _T_3844
node _T_3845 = bits(_WIRE_281, 4, 4)
connect _WIRE_280.pal, _T_3845
node _T_3846 = bits(_WIRE_281, 5, 5)
connect _WIRE_280.ppp, _T_3846
node _T_3847 = bits(_WIRE_281, 6, 6)
connect _WIRE_280.pr, _T_3847
node _T_3848 = bits(_WIRE_281, 7, 7)
connect _WIRE_280.px, _T_3848
node _T_3849 = bits(_WIRE_281, 8, 8)
connect _WIRE_280.pw, _T_3849
node _T_3850 = bits(_WIRE_281, 9, 9)
connect _WIRE_280.hr, _T_3850
node _T_3851 = bits(_WIRE_281, 10, 10)
connect _WIRE_280.hx, _T_3851
node _T_3852 = bits(_WIRE_281, 11, 11)
connect _WIRE_280.hw, _T_3852
node _T_3853 = bits(_WIRE_281, 12, 12)
connect _WIRE_280.sr, _T_3853
node _T_3854 = bits(_WIRE_281, 13, 13)
connect _WIRE_280.sx, _T_3854
node _T_3855 = bits(_WIRE_281, 14, 14)
connect _WIRE_280.sw, _T_3855
node _T_3856 = bits(_WIRE_281, 15, 15)
connect _WIRE_280.gf, _T_3856
node _T_3857 = bits(_WIRE_281, 16, 16)
connect _WIRE_280.pf, _T_3857
node _T_3858 = bits(_WIRE_281, 17, 17)
connect _WIRE_280.ae_stage2, _T_3858
node _T_3859 = bits(_WIRE_281, 18, 18)
connect _WIRE_280.ae_final, _T_3859
node _T_3860 = bits(_WIRE_281, 19, 19)
connect _WIRE_280.ae_ptw, _T_3860
node _T_3861 = bits(_WIRE_281, 20, 20)
connect _WIRE_280.g, _T_3861
node _T_3862 = bits(_WIRE_281, 21, 21)
connect _WIRE_280.u, _T_3862
node _T_3863 = bits(_WIRE_281, 41, 22)
connect _WIRE_280.ppn, _T_3863
node _T_3864 = eq(special_entry.tag_v, hv_12)
node _T_3865 = and(_T_3864, _WIRE_280.fragmented_superpage)
when _T_3865 :
connect special_entry.valid[0], UInt<1>(0h0)
else :
node _T_3866 = eq(hg_12, UInt<1>(0h0))
node _T_3867 = and(_T_3866, io.sfence.bits.rs2)
when _T_3867 :
wire _WIRE_282 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_283 : UInt<42>
connect _WIRE_283, special_entry.data[0]
node _T_3868 = bits(_WIRE_283, 0, 0)
connect _WIRE_282.fragmented_superpage, _T_3868
node _T_3869 = bits(_WIRE_283, 1, 1)
connect _WIRE_282.c, _T_3869
node _T_3870 = bits(_WIRE_283, 2, 2)
connect _WIRE_282.eff, _T_3870
node _T_3871 = bits(_WIRE_283, 3, 3)
connect _WIRE_282.paa, _T_3871
node _T_3872 = bits(_WIRE_283, 4, 4)
connect _WIRE_282.pal, _T_3872
node _T_3873 = bits(_WIRE_283, 5, 5)
connect _WIRE_282.ppp, _T_3873
node _T_3874 = bits(_WIRE_283, 6, 6)
connect _WIRE_282.pr, _T_3874
node _T_3875 = bits(_WIRE_283, 7, 7)
connect _WIRE_282.px, _T_3875
node _T_3876 = bits(_WIRE_283, 8, 8)
connect _WIRE_282.pw, _T_3876
node _T_3877 = bits(_WIRE_283, 9, 9)
connect _WIRE_282.hr, _T_3877
node _T_3878 = bits(_WIRE_283, 10, 10)
connect _WIRE_282.hx, _T_3878
node _T_3879 = bits(_WIRE_283, 11, 11)
connect _WIRE_282.hw, _T_3879
node _T_3880 = bits(_WIRE_283, 12, 12)
connect _WIRE_282.sr, _T_3880
node _T_3881 = bits(_WIRE_283, 13, 13)
connect _WIRE_282.sx, _T_3881
node _T_3882 = bits(_WIRE_283, 14, 14)
connect _WIRE_282.sw, _T_3882
node _T_3883 = bits(_WIRE_283, 15, 15)
connect _WIRE_282.gf, _T_3883
node _T_3884 = bits(_WIRE_283, 16, 16)
connect _WIRE_282.pf, _T_3884
node _T_3885 = bits(_WIRE_283, 17, 17)
connect _WIRE_282.ae_stage2, _T_3885
node _T_3886 = bits(_WIRE_283, 18, 18)
connect _WIRE_282.ae_final, _T_3886
node _T_3887 = bits(_WIRE_283, 19, 19)
connect _WIRE_282.ae_ptw, _T_3887
node _T_3888 = bits(_WIRE_283, 20, 20)
connect _WIRE_282.g, _T_3888
node _T_3889 = bits(_WIRE_283, 21, 21)
connect _WIRE_282.u, _T_3889
node _T_3890 = bits(_WIRE_283, 41, 22)
connect _WIRE_282.ppn, _T_3890
node _T_3891 = eq(special_entry.tag_v, hv_12)
node _T_3892 = eq(_WIRE_282.g, UInt<1>(0h0))
node _T_3893 = and(_T_3891, _T_3892)
when _T_3893 :
connect special_entry.valid[0], UInt<1>(0h0)
else :
node _T_3894 = or(hv_12, hg_12)
wire _WIRE_284 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_285 : UInt<42>
connect _WIRE_285, special_entry.data[0]
node _T_3895 = bits(_WIRE_285, 0, 0)
connect _WIRE_284.fragmented_superpage, _T_3895
node _T_3896 = bits(_WIRE_285, 1, 1)
connect _WIRE_284.c, _T_3896
node _T_3897 = bits(_WIRE_285, 2, 2)
connect _WIRE_284.eff, _T_3897
node _T_3898 = bits(_WIRE_285, 3, 3)
connect _WIRE_284.paa, _T_3898
node _T_3899 = bits(_WIRE_285, 4, 4)
connect _WIRE_284.pal, _T_3899
node _T_3900 = bits(_WIRE_285, 5, 5)
connect _WIRE_284.ppp, _T_3900
node _T_3901 = bits(_WIRE_285, 6, 6)
connect _WIRE_284.pr, _T_3901
node _T_3902 = bits(_WIRE_285, 7, 7)
connect _WIRE_284.px, _T_3902
node _T_3903 = bits(_WIRE_285, 8, 8)
connect _WIRE_284.pw, _T_3903
node _T_3904 = bits(_WIRE_285, 9, 9)
connect _WIRE_284.hr, _T_3904
node _T_3905 = bits(_WIRE_285, 10, 10)
connect _WIRE_284.hx, _T_3905
node _T_3906 = bits(_WIRE_285, 11, 11)
connect _WIRE_284.hw, _T_3906
node _T_3907 = bits(_WIRE_285, 12, 12)
connect _WIRE_284.sr, _T_3907
node _T_3908 = bits(_WIRE_285, 13, 13)
connect _WIRE_284.sx, _T_3908
node _T_3909 = bits(_WIRE_285, 14, 14)
connect _WIRE_284.sw, _T_3909
node _T_3910 = bits(_WIRE_285, 15, 15)
connect _WIRE_284.gf, _T_3910
node _T_3911 = bits(_WIRE_285, 16, 16)
connect _WIRE_284.pf, _T_3911
node _T_3912 = bits(_WIRE_285, 17, 17)
connect _WIRE_284.ae_stage2, _T_3912
node _T_3913 = bits(_WIRE_285, 18, 18)
connect _WIRE_284.ae_final, _T_3913
node _T_3914 = bits(_WIRE_285, 19, 19)
connect _WIRE_284.ae_ptw, _T_3914
node _T_3915 = bits(_WIRE_285, 20, 20)
connect _WIRE_284.g, _T_3915
node _T_3916 = bits(_WIRE_285, 21, 21)
connect _WIRE_284.u, _T_3916
node _T_3917 = bits(_WIRE_285, 41, 22)
connect _WIRE_284.ppn, _T_3917
node _T_3918 = eq(special_entry.tag_v, _T_3894)
when _T_3918 :
connect special_entry.valid[0], UInt<1>(0h0)
node _T_3919 = and(io.req.ready, io.req.valid)
node _T_3920 = and(_T_3919, vsatp_mode_mismatch)
when _T_3920 :
wire _WIRE_286 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_287 : UInt<42>
connect _WIRE_287, sectored_entries[0][0].data[0]
node _T_3921 = bits(_WIRE_287, 0, 0)
connect _WIRE_286.fragmented_superpage, _T_3921
node _T_3922 = bits(_WIRE_287, 1, 1)
connect _WIRE_286.c, _T_3922
node _T_3923 = bits(_WIRE_287, 2, 2)
connect _WIRE_286.eff, _T_3923
node _T_3924 = bits(_WIRE_287, 3, 3)
connect _WIRE_286.paa, _T_3924
node _T_3925 = bits(_WIRE_287, 4, 4)
connect _WIRE_286.pal, _T_3925
node _T_3926 = bits(_WIRE_287, 5, 5)
connect _WIRE_286.ppp, _T_3926
node _T_3927 = bits(_WIRE_287, 6, 6)
connect _WIRE_286.pr, _T_3927
node _T_3928 = bits(_WIRE_287, 7, 7)
connect _WIRE_286.px, _T_3928
node _T_3929 = bits(_WIRE_287, 8, 8)
connect _WIRE_286.pw, _T_3929
node _T_3930 = bits(_WIRE_287, 9, 9)
connect _WIRE_286.hr, _T_3930
node _T_3931 = bits(_WIRE_287, 10, 10)
connect _WIRE_286.hx, _T_3931
node _T_3932 = bits(_WIRE_287, 11, 11)
connect _WIRE_286.hw, _T_3932
node _T_3933 = bits(_WIRE_287, 12, 12)
connect _WIRE_286.sr, _T_3933
node _T_3934 = bits(_WIRE_287, 13, 13)
connect _WIRE_286.sx, _T_3934
node _T_3935 = bits(_WIRE_287, 14, 14)
connect _WIRE_286.sw, _T_3935
node _T_3936 = bits(_WIRE_287, 15, 15)
connect _WIRE_286.gf, _T_3936
node _T_3937 = bits(_WIRE_287, 16, 16)
connect _WIRE_286.pf, _T_3937
node _T_3938 = bits(_WIRE_287, 17, 17)
connect _WIRE_286.ae_stage2, _T_3938
node _T_3939 = bits(_WIRE_287, 18, 18)
connect _WIRE_286.ae_final, _T_3939
node _T_3940 = bits(_WIRE_287, 19, 19)
connect _WIRE_286.ae_ptw, _T_3940
node _T_3941 = bits(_WIRE_287, 20, 20)
connect _WIRE_286.g, _T_3941
node _T_3942 = bits(_WIRE_287, 21, 21)
connect _WIRE_286.u, _T_3942
node _T_3943 = bits(_WIRE_287, 41, 22)
connect _WIRE_286.ppn, _T_3943
wire _WIRE_288 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_289 : UInt<42>
connect _WIRE_289, sectored_entries[0][0].data[1]
node _T_3944 = bits(_WIRE_289, 0, 0)
connect _WIRE_288.fragmented_superpage, _T_3944
node _T_3945 = bits(_WIRE_289, 1, 1)
connect _WIRE_288.c, _T_3945
node _T_3946 = bits(_WIRE_289, 2, 2)
connect _WIRE_288.eff, _T_3946
node _T_3947 = bits(_WIRE_289, 3, 3)
connect _WIRE_288.paa, _T_3947
node _T_3948 = bits(_WIRE_289, 4, 4)
connect _WIRE_288.pal, _T_3948
node _T_3949 = bits(_WIRE_289, 5, 5)
connect _WIRE_288.ppp, _T_3949
node _T_3950 = bits(_WIRE_289, 6, 6)
connect _WIRE_288.pr, _T_3950
node _T_3951 = bits(_WIRE_289, 7, 7)
connect _WIRE_288.px, _T_3951
node _T_3952 = bits(_WIRE_289, 8, 8)
connect _WIRE_288.pw, _T_3952
node _T_3953 = bits(_WIRE_289, 9, 9)
connect _WIRE_288.hr, _T_3953
node _T_3954 = bits(_WIRE_289, 10, 10)
connect _WIRE_288.hx, _T_3954
node _T_3955 = bits(_WIRE_289, 11, 11)
connect _WIRE_288.hw, _T_3955
node _T_3956 = bits(_WIRE_289, 12, 12)
connect _WIRE_288.sr, _T_3956
node _T_3957 = bits(_WIRE_289, 13, 13)
connect _WIRE_288.sx, _T_3957
node _T_3958 = bits(_WIRE_289, 14, 14)
connect _WIRE_288.sw, _T_3958
node _T_3959 = bits(_WIRE_289, 15, 15)
connect _WIRE_288.gf, _T_3959
node _T_3960 = bits(_WIRE_289, 16, 16)
connect _WIRE_288.pf, _T_3960
node _T_3961 = bits(_WIRE_289, 17, 17)
connect _WIRE_288.ae_stage2, _T_3961
node _T_3962 = bits(_WIRE_289, 18, 18)
connect _WIRE_288.ae_final, _T_3962
node _T_3963 = bits(_WIRE_289, 19, 19)
connect _WIRE_288.ae_ptw, _T_3963
node _T_3964 = bits(_WIRE_289, 20, 20)
connect _WIRE_288.g, _T_3964
node _T_3965 = bits(_WIRE_289, 21, 21)
connect _WIRE_288.u, _T_3965
node _T_3966 = bits(_WIRE_289, 41, 22)
connect _WIRE_288.ppn, _T_3966
wire _WIRE_290 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_291 : UInt<42>
connect _WIRE_291, sectored_entries[0][0].data[2]
node _T_3967 = bits(_WIRE_291, 0, 0)
connect _WIRE_290.fragmented_superpage, _T_3967
node _T_3968 = bits(_WIRE_291, 1, 1)
connect _WIRE_290.c, _T_3968
node _T_3969 = bits(_WIRE_291, 2, 2)
connect _WIRE_290.eff, _T_3969
node _T_3970 = bits(_WIRE_291, 3, 3)
connect _WIRE_290.paa, _T_3970
node _T_3971 = bits(_WIRE_291, 4, 4)
connect _WIRE_290.pal, _T_3971
node _T_3972 = bits(_WIRE_291, 5, 5)
connect _WIRE_290.ppp, _T_3972
node _T_3973 = bits(_WIRE_291, 6, 6)
connect _WIRE_290.pr, _T_3973
node _T_3974 = bits(_WIRE_291, 7, 7)
connect _WIRE_290.px, _T_3974
node _T_3975 = bits(_WIRE_291, 8, 8)
connect _WIRE_290.pw, _T_3975
node _T_3976 = bits(_WIRE_291, 9, 9)
connect _WIRE_290.hr, _T_3976
node _T_3977 = bits(_WIRE_291, 10, 10)
connect _WIRE_290.hx, _T_3977
node _T_3978 = bits(_WIRE_291, 11, 11)
connect _WIRE_290.hw, _T_3978
node _T_3979 = bits(_WIRE_291, 12, 12)
connect _WIRE_290.sr, _T_3979
node _T_3980 = bits(_WIRE_291, 13, 13)
connect _WIRE_290.sx, _T_3980
node _T_3981 = bits(_WIRE_291, 14, 14)
connect _WIRE_290.sw, _T_3981
node _T_3982 = bits(_WIRE_291, 15, 15)
connect _WIRE_290.gf, _T_3982
node _T_3983 = bits(_WIRE_291, 16, 16)
connect _WIRE_290.pf, _T_3983
node _T_3984 = bits(_WIRE_291, 17, 17)
connect _WIRE_290.ae_stage2, _T_3984
node _T_3985 = bits(_WIRE_291, 18, 18)
connect _WIRE_290.ae_final, _T_3985
node _T_3986 = bits(_WIRE_291, 19, 19)
connect _WIRE_290.ae_ptw, _T_3986
node _T_3987 = bits(_WIRE_291, 20, 20)
connect _WIRE_290.g, _T_3987
node _T_3988 = bits(_WIRE_291, 21, 21)
connect _WIRE_290.u, _T_3988
node _T_3989 = bits(_WIRE_291, 41, 22)
connect _WIRE_290.ppn, _T_3989
wire _WIRE_292 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_293 : UInt<42>
connect _WIRE_293, sectored_entries[0][0].data[3]
node _T_3990 = bits(_WIRE_293, 0, 0)
connect _WIRE_292.fragmented_superpage, _T_3990
node _T_3991 = bits(_WIRE_293, 1, 1)
connect _WIRE_292.c, _T_3991
node _T_3992 = bits(_WIRE_293, 2, 2)
connect _WIRE_292.eff, _T_3992
node _T_3993 = bits(_WIRE_293, 3, 3)
connect _WIRE_292.paa, _T_3993
node _T_3994 = bits(_WIRE_293, 4, 4)
connect _WIRE_292.pal, _T_3994
node _T_3995 = bits(_WIRE_293, 5, 5)
connect _WIRE_292.ppp, _T_3995
node _T_3996 = bits(_WIRE_293, 6, 6)
connect _WIRE_292.pr, _T_3996
node _T_3997 = bits(_WIRE_293, 7, 7)
connect _WIRE_292.px, _T_3997
node _T_3998 = bits(_WIRE_293, 8, 8)
connect _WIRE_292.pw, _T_3998
node _T_3999 = bits(_WIRE_293, 9, 9)
connect _WIRE_292.hr, _T_3999
node _T_4000 = bits(_WIRE_293, 10, 10)
connect _WIRE_292.hx, _T_4000
node _T_4001 = bits(_WIRE_293, 11, 11)
connect _WIRE_292.hw, _T_4001
node _T_4002 = bits(_WIRE_293, 12, 12)
connect _WIRE_292.sr, _T_4002
node _T_4003 = bits(_WIRE_293, 13, 13)
connect _WIRE_292.sx, _T_4003
node _T_4004 = bits(_WIRE_293, 14, 14)
connect _WIRE_292.sw, _T_4004
node _T_4005 = bits(_WIRE_293, 15, 15)
connect _WIRE_292.gf, _T_4005
node _T_4006 = bits(_WIRE_293, 16, 16)
connect _WIRE_292.pf, _T_4006
node _T_4007 = bits(_WIRE_293, 17, 17)
connect _WIRE_292.ae_stage2, _T_4007
node _T_4008 = bits(_WIRE_293, 18, 18)
connect _WIRE_292.ae_final, _T_4008
node _T_4009 = bits(_WIRE_293, 19, 19)
connect _WIRE_292.ae_ptw, _T_4009
node _T_4010 = bits(_WIRE_293, 20, 20)
connect _WIRE_292.g, _T_4010
node _T_4011 = bits(_WIRE_293, 21, 21)
connect _WIRE_292.u, _T_4011
node _T_4012 = bits(_WIRE_293, 41, 22)
connect _WIRE_292.ppn, _T_4012
node _T_4013 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1))
when _T_4013 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
node _T_4014 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1))
when _T_4014 :
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
node _T_4015 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1))
when _T_4015 :
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
node _T_4016 = eq(sectored_entries[0][0].tag_v, UInt<1>(0h1))
when _T_4016 :
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
wire _WIRE_294 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_295 : UInt<42>
connect _WIRE_295, sectored_entries[0][1].data[0]
node _T_4017 = bits(_WIRE_295, 0, 0)
connect _WIRE_294.fragmented_superpage, _T_4017
node _T_4018 = bits(_WIRE_295, 1, 1)
connect _WIRE_294.c, _T_4018
node _T_4019 = bits(_WIRE_295, 2, 2)
connect _WIRE_294.eff, _T_4019
node _T_4020 = bits(_WIRE_295, 3, 3)
connect _WIRE_294.paa, _T_4020
node _T_4021 = bits(_WIRE_295, 4, 4)
connect _WIRE_294.pal, _T_4021
node _T_4022 = bits(_WIRE_295, 5, 5)
connect _WIRE_294.ppp, _T_4022
node _T_4023 = bits(_WIRE_295, 6, 6)
connect _WIRE_294.pr, _T_4023
node _T_4024 = bits(_WIRE_295, 7, 7)
connect _WIRE_294.px, _T_4024
node _T_4025 = bits(_WIRE_295, 8, 8)
connect _WIRE_294.pw, _T_4025
node _T_4026 = bits(_WIRE_295, 9, 9)
connect _WIRE_294.hr, _T_4026
node _T_4027 = bits(_WIRE_295, 10, 10)
connect _WIRE_294.hx, _T_4027
node _T_4028 = bits(_WIRE_295, 11, 11)
connect _WIRE_294.hw, _T_4028
node _T_4029 = bits(_WIRE_295, 12, 12)
connect _WIRE_294.sr, _T_4029
node _T_4030 = bits(_WIRE_295, 13, 13)
connect _WIRE_294.sx, _T_4030
node _T_4031 = bits(_WIRE_295, 14, 14)
connect _WIRE_294.sw, _T_4031
node _T_4032 = bits(_WIRE_295, 15, 15)
connect _WIRE_294.gf, _T_4032
node _T_4033 = bits(_WIRE_295, 16, 16)
connect _WIRE_294.pf, _T_4033
node _T_4034 = bits(_WIRE_295, 17, 17)
connect _WIRE_294.ae_stage2, _T_4034
node _T_4035 = bits(_WIRE_295, 18, 18)
connect _WIRE_294.ae_final, _T_4035
node _T_4036 = bits(_WIRE_295, 19, 19)
connect _WIRE_294.ae_ptw, _T_4036
node _T_4037 = bits(_WIRE_295, 20, 20)
connect _WIRE_294.g, _T_4037
node _T_4038 = bits(_WIRE_295, 21, 21)
connect _WIRE_294.u, _T_4038
node _T_4039 = bits(_WIRE_295, 41, 22)
connect _WIRE_294.ppn, _T_4039
wire _WIRE_296 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_297 : UInt<42>
connect _WIRE_297, sectored_entries[0][1].data[1]
node _T_4040 = bits(_WIRE_297, 0, 0)
connect _WIRE_296.fragmented_superpage, _T_4040
node _T_4041 = bits(_WIRE_297, 1, 1)
connect _WIRE_296.c, _T_4041
node _T_4042 = bits(_WIRE_297, 2, 2)
connect _WIRE_296.eff, _T_4042
node _T_4043 = bits(_WIRE_297, 3, 3)
connect _WIRE_296.paa, _T_4043
node _T_4044 = bits(_WIRE_297, 4, 4)
connect _WIRE_296.pal, _T_4044
node _T_4045 = bits(_WIRE_297, 5, 5)
connect _WIRE_296.ppp, _T_4045
node _T_4046 = bits(_WIRE_297, 6, 6)
connect _WIRE_296.pr, _T_4046
node _T_4047 = bits(_WIRE_297, 7, 7)
connect _WIRE_296.px, _T_4047
node _T_4048 = bits(_WIRE_297, 8, 8)
connect _WIRE_296.pw, _T_4048
node _T_4049 = bits(_WIRE_297, 9, 9)
connect _WIRE_296.hr, _T_4049
node _T_4050 = bits(_WIRE_297, 10, 10)
connect _WIRE_296.hx, _T_4050
node _T_4051 = bits(_WIRE_297, 11, 11)
connect _WIRE_296.hw, _T_4051
node _T_4052 = bits(_WIRE_297, 12, 12)
connect _WIRE_296.sr, _T_4052
node _T_4053 = bits(_WIRE_297, 13, 13)
connect _WIRE_296.sx, _T_4053
node _T_4054 = bits(_WIRE_297, 14, 14)
connect _WIRE_296.sw, _T_4054
node _T_4055 = bits(_WIRE_297, 15, 15)
connect _WIRE_296.gf, _T_4055
node _T_4056 = bits(_WIRE_297, 16, 16)
connect _WIRE_296.pf, _T_4056
node _T_4057 = bits(_WIRE_297, 17, 17)
connect _WIRE_296.ae_stage2, _T_4057
node _T_4058 = bits(_WIRE_297, 18, 18)
connect _WIRE_296.ae_final, _T_4058
node _T_4059 = bits(_WIRE_297, 19, 19)
connect _WIRE_296.ae_ptw, _T_4059
node _T_4060 = bits(_WIRE_297, 20, 20)
connect _WIRE_296.g, _T_4060
node _T_4061 = bits(_WIRE_297, 21, 21)
connect _WIRE_296.u, _T_4061
node _T_4062 = bits(_WIRE_297, 41, 22)
connect _WIRE_296.ppn, _T_4062
wire _WIRE_298 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_299 : UInt<42>
connect _WIRE_299, sectored_entries[0][1].data[2]
node _T_4063 = bits(_WIRE_299, 0, 0)
connect _WIRE_298.fragmented_superpage, _T_4063
node _T_4064 = bits(_WIRE_299, 1, 1)
connect _WIRE_298.c, _T_4064
node _T_4065 = bits(_WIRE_299, 2, 2)
connect _WIRE_298.eff, _T_4065
node _T_4066 = bits(_WIRE_299, 3, 3)
connect _WIRE_298.paa, _T_4066
node _T_4067 = bits(_WIRE_299, 4, 4)
connect _WIRE_298.pal, _T_4067
node _T_4068 = bits(_WIRE_299, 5, 5)
connect _WIRE_298.ppp, _T_4068
node _T_4069 = bits(_WIRE_299, 6, 6)
connect _WIRE_298.pr, _T_4069
node _T_4070 = bits(_WIRE_299, 7, 7)
connect _WIRE_298.px, _T_4070
node _T_4071 = bits(_WIRE_299, 8, 8)
connect _WIRE_298.pw, _T_4071
node _T_4072 = bits(_WIRE_299, 9, 9)
connect _WIRE_298.hr, _T_4072
node _T_4073 = bits(_WIRE_299, 10, 10)
connect _WIRE_298.hx, _T_4073
node _T_4074 = bits(_WIRE_299, 11, 11)
connect _WIRE_298.hw, _T_4074
node _T_4075 = bits(_WIRE_299, 12, 12)
connect _WIRE_298.sr, _T_4075
node _T_4076 = bits(_WIRE_299, 13, 13)
connect _WIRE_298.sx, _T_4076
node _T_4077 = bits(_WIRE_299, 14, 14)
connect _WIRE_298.sw, _T_4077
node _T_4078 = bits(_WIRE_299, 15, 15)
connect _WIRE_298.gf, _T_4078
node _T_4079 = bits(_WIRE_299, 16, 16)
connect _WIRE_298.pf, _T_4079
node _T_4080 = bits(_WIRE_299, 17, 17)
connect _WIRE_298.ae_stage2, _T_4080
node _T_4081 = bits(_WIRE_299, 18, 18)
connect _WIRE_298.ae_final, _T_4081
node _T_4082 = bits(_WIRE_299, 19, 19)
connect _WIRE_298.ae_ptw, _T_4082
node _T_4083 = bits(_WIRE_299, 20, 20)
connect _WIRE_298.g, _T_4083
node _T_4084 = bits(_WIRE_299, 21, 21)
connect _WIRE_298.u, _T_4084
node _T_4085 = bits(_WIRE_299, 41, 22)
connect _WIRE_298.ppn, _T_4085
wire _WIRE_300 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_301 : UInt<42>
connect _WIRE_301, sectored_entries[0][1].data[3]
node _T_4086 = bits(_WIRE_301, 0, 0)
connect _WIRE_300.fragmented_superpage, _T_4086
node _T_4087 = bits(_WIRE_301, 1, 1)
connect _WIRE_300.c, _T_4087
node _T_4088 = bits(_WIRE_301, 2, 2)
connect _WIRE_300.eff, _T_4088
node _T_4089 = bits(_WIRE_301, 3, 3)
connect _WIRE_300.paa, _T_4089
node _T_4090 = bits(_WIRE_301, 4, 4)
connect _WIRE_300.pal, _T_4090
node _T_4091 = bits(_WIRE_301, 5, 5)
connect _WIRE_300.ppp, _T_4091
node _T_4092 = bits(_WIRE_301, 6, 6)
connect _WIRE_300.pr, _T_4092
node _T_4093 = bits(_WIRE_301, 7, 7)
connect _WIRE_300.px, _T_4093
node _T_4094 = bits(_WIRE_301, 8, 8)
connect _WIRE_300.pw, _T_4094
node _T_4095 = bits(_WIRE_301, 9, 9)
connect _WIRE_300.hr, _T_4095
node _T_4096 = bits(_WIRE_301, 10, 10)
connect _WIRE_300.hx, _T_4096
node _T_4097 = bits(_WIRE_301, 11, 11)
connect _WIRE_300.hw, _T_4097
node _T_4098 = bits(_WIRE_301, 12, 12)
connect _WIRE_300.sr, _T_4098
node _T_4099 = bits(_WIRE_301, 13, 13)
connect _WIRE_300.sx, _T_4099
node _T_4100 = bits(_WIRE_301, 14, 14)
connect _WIRE_300.sw, _T_4100
node _T_4101 = bits(_WIRE_301, 15, 15)
connect _WIRE_300.gf, _T_4101
node _T_4102 = bits(_WIRE_301, 16, 16)
connect _WIRE_300.pf, _T_4102
node _T_4103 = bits(_WIRE_301, 17, 17)
connect _WIRE_300.ae_stage2, _T_4103
node _T_4104 = bits(_WIRE_301, 18, 18)
connect _WIRE_300.ae_final, _T_4104
node _T_4105 = bits(_WIRE_301, 19, 19)
connect _WIRE_300.ae_ptw, _T_4105
node _T_4106 = bits(_WIRE_301, 20, 20)
connect _WIRE_300.g, _T_4106
node _T_4107 = bits(_WIRE_301, 21, 21)
connect _WIRE_300.u, _T_4107
node _T_4108 = bits(_WIRE_301, 41, 22)
connect _WIRE_300.ppn, _T_4108
node _T_4109 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1))
when _T_4109 :
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
node _T_4110 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1))
when _T_4110 :
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
node _T_4111 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1))
when _T_4111 :
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
node _T_4112 = eq(sectored_entries[0][1].tag_v, UInt<1>(0h1))
when _T_4112 :
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
wire _WIRE_302 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_303 : UInt<42>
connect _WIRE_303, sectored_entries[0][2].data[0]
node _T_4113 = bits(_WIRE_303, 0, 0)
connect _WIRE_302.fragmented_superpage, _T_4113
node _T_4114 = bits(_WIRE_303, 1, 1)
connect _WIRE_302.c, _T_4114
node _T_4115 = bits(_WIRE_303, 2, 2)
connect _WIRE_302.eff, _T_4115
node _T_4116 = bits(_WIRE_303, 3, 3)
connect _WIRE_302.paa, _T_4116
node _T_4117 = bits(_WIRE_303, 4, 4)
connect _WIRE_302.pal, _T_4117
node _T_4118 = bits(_WIRE_303, 5, 5)
connect _WIRE_302.ppp, _T_4118
node _T_4119 = bits(_WIRE_303, 6, 6)
connect _WIRE_302.pr, _T_4119
node _T_4120 = bits(_WIRE_303, 7, 7)
connect _WIRE_302.px, _T_4120
node _T_4121 = bits(_WIRE_303, 8, 8)
connect _WIRE_302.pw, _T_4121
node _T_4122 = bits(_WIRE_303, 9, 9)
connect _WIRE_302.hr, _T_4122
node _T_4123 = bits(_WIRE_303, 10, 10)
connect _WIRE_302.hx, _T_4123
node _T_4124 = bits(_WIRE_303, 11, 11)
connect _WIRE_302.hw, _T_4124
node _T_4125 = bits(_WIRE_303, 12, 12)
connect _WIRE_302.sr, _T_4125
node _T_4126 = bits(_WIRE_303, 13, 13)
connect _WIRE_302.sx, _T_4126
node _T_4127 = bits(_WIRE_303, 14, 14)
connect _WIRE_302.sw, _T_4127
node _T_4128 = bits(_WIRE_303, 15, 15)
connect _WIRE_302.gf, _T_4128
node _T_4129 = bits(_WIRE_303, 16, 16)
connect _WIRE_302.pf, _T_4129
node _T_4130 = bits(_WIRE_303, 17, 17)
connect _WIRE_302.ae_stage2, _T_4130
node _T_4131 = bits(_WIRE_303, 18, 18)
connect _WIRE_302.ae_final, _T_4131
node _T_4132 = bits(_WIRE_303, 19, 19)
connect _WIRE_302.ae_ptw, _T_4132
node _T_4133 = bits(_WIRE_303, 20, 20)
connect _WIRE_302.g, _T_4133
node _T_4134 = bits(_WIRE_303, 21, 21)
connect _WIRE_302.u, _T_4134
node _T_4135 = bits(_WIRE_303, 41, 22)
connect _WIRE_302.ppn, _T_4135
wire _WIRE_304 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_305 : UInt<42>
connect _WIRE_305, sectored_entries[0][2].data[1]
node _T_4136 = bits(_WIRE_305, 0, 0)
connect _WIRE_304.fragmented_superpage, _T_4136
node _T_4137 = bits(_WIRE_305, 1, 1)
connect _WIRE_304.c, _T_4137
node _T_4138 = bits(_WIRE_305, 2, 2)
connect _WIRE_304.eff, _T_4138
node _T_4139 = bits(_WIRE_305, 3, 3)
connect _WIRE_304.paa, _T_4139
node _T_4140 = bits(_WIRE_305, 4, 4)
connect _WIRE_304.pal, _T_4140
node _T_4141 = bits(_WIRE_305, 5, 5)
connect _WIRE_304.ppp, _T_4141
node _T_4142 = bits(_WIRE_305, 6, 6)
connect _WIRE_304.pr, _T_4142
node _T_4143 = bits(_WIRE_305, 7, 7)
connect _WIRE_304.px, _T_4143
node _T_4144 = bits(_WIRE_305, 8, 8)
connect _WIRE_304.pw, _T_4144
node _T_4145 = bits(_WIRE_305, 9, 9)
connect _WIRE_304.hr, _T_4145
node _T_4146 = bits(_WIRE_305, 10, 10)
connect _WIRE_304.hx, _T_4146
node _T_4147 = bits(_WIRE_305, 11, 11)
connect _WIRE_304.hw, _T_4147
node _T_4148 = bits(_WIRE_305, 12, 12)
connect _WIRE_304.sr, _T_4148
node _T_4149 = bits(_WIRE_305, 13, 13)
connect _WIRE_304.sx, _T_4149
node _T_4150 = bits(_WIRE_305, 14, 14)
connect _WIRE_304.sw, _T_4150
node _T_4151 = bits(_WIRE_305, 15, 15)
connect _WIRE_304.gf, _T_4151
node _T_4152 = bits(_WIRE_305, 16, 16)
connect _WIRE_304.pf, _T_4152
node _T_4153 = bits(_WIRE_305, 17, 17)
connect _WIRE_304.ae_stage2, _T_4153
node _T_4154 = bits(_WIRE_305, 18, 18)
connect _WIRE_304.ae_final, _T_4154
node _T_4155 = bits(_WIRE_305, 19, 19)
connect _WIRE_304.ae_ptw, _T_4155
node _T_4156 = bits(_WIRE_305, 20, 20)
connect _WIRE_304.g, _T_4156
node _T_4157 = bits(_WIRE_305, 21, 21)
connect _WIRE_304.u, _T_4157
node _T_4158 = bits(_WIRE_305, 41, 22)
connect _WIRE_304.ppn, _T_4158
wire _WIRE_306 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_307 : UInt<42>
connect _WIRE_307, sectored_entries[0][2].data[2]
node _T_4159 = bits(_WIRE_307, 0, 0)
connect _WIRE_306.fragmented_superpage, _T_4159
node _T_4160 = bits(_WIRE_307, 1, 1)
connect _WIRE_306.c, _T_4160
node _T_4161 = bits(_WIRE_307, 2, 2)
connect _WIRE_306.eff, _T_4161
node _T_4162 = bits(_WIRE_307, 3, 3)
connect _WIRE_306.paa, _T_4162
node _T_4163 = bits(_WIRE_307, 4, 4)
connect _WIRE_306.pal, _T_4163
node _T_4164 = bits(_WIRE_307, 5, 5)
connect _WIRE_306.ppp, _T_4164
node _T_4165 = bits(_WIRE_307, 6, 6)
connect _WIRE_306.pr, _T_4165
node _T_4166 = bits(_WIRE_307, 7, 7)
connect _WIRE_306.px, _T_4166
node _T_4167 = bits(_WIRE_307, 8, 8)
connect _WIRE_306.pw, _T_4167
node _T_4168 = bits(_WIRE_307, 9, 9)
connect _WIRE_306.hr, _T_4168
node _T_4169 = bits(_WIRE_307, 10, 10)
connect _WIRE_306.hx, _T_4169
node _T_4170 = bits(_WIRE_307, 11, 11)
connect _WIRE_306.hw, _T_4170
node _T_4171 = bits(_WIRE_307, 12, 12)
connect _WIRE_306.sr, _T_4171
node _T_4172 = bits(_WIRE_307, 13, 13)
connect _WIRE_306.sx, _T_4172
node _T_4173 = bits(_WIRE_307, 14, 14)
connect _WIRE_306.sw, _T_4173
node _T_4174 = bits(_WIRE_307, 15, 15)
connect _WIRE_306.gf, _T_4174
node _T_4175 = bits(_WIRE_307, 16, 16)
connect _WIRE_306.pf, _T_4175
node _T_4176 = bits(_WIRE_307, 17, 17)
connect _WIRE_306.ae_stage2, _T_4176
node _T_4177 = bits(_WIRE_307, 18, 18)
connect _WIRE_306.ae_final, _T_4177
node _T_4178 = bits(_WIRE_307, 19, 19)
connect _WIRE_306.ae_ptw, _T_4178
node _T_4179 = bits(_WIRE_307, 20, 20)
connect _WIRE_306.g, _T_4179
node _T_4180 = bits(_WIRE_307, 21, 21)
connect _WIRE_306.u, _T_4180
node _T_4181 = bits(_WIRE_307, 41, 22)
connect _WIRE_306.ppn, _T_4181
wire _WIRE_308 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_309 : UInt<42>
connect _WIRE_309, sectored_entries[0][2].data[3]
node _T_4182 = bits(_WIRE_309, 0, 0)
connect _WIRE_308.fragmented_superpage, _T_4182
node _T_4183 = bits(_WIRE_309, 1, 1)
connect _WIRE_308.c, _T_4183
node _T_4184 = bits(_WIRE_309, 2, 2)
connect _WIRE_308.eff, _T_4184
node _T_4185 = bits(_WIRE_309, 3, 3)
connect _WIRE_308.paa, _T_4185
node _T_4186 = bits(_WIRE_309, 4, 4)
connect _WIRE_308.pal, _T_4186
node _T_4187 = bits(_WIRE_309, 5, 5)
connect _WIRE_308.ppp, _T_4187
node _T_4188 = bits(_WIRE_309, 6, 6)
connect _WIRE_308.pr, _T_4188
node _T_4189 = bits(_WIRE_309, 7, 7)
connect _WIRE_308.px, _T_4189
node _T_4190 = bits(_WIRE_309, 8, 8)
connect _WIRE_308.pw, _T_4190
node _T_4191 = bits(_WIRE_309, 9, 9)
connect _WIRE_308.hr, _T_4191
node _T_4192 = bits(_WIRE_309, 10, 10)
connect _WIRE_308.hx, _T_4192
node _T_4193 = bits(_WIRE_309, 11, 11)
connect _WIRE_308.hw, _T_4193
node _T_4194 = bits(_WIRE_309, 12, 12)
connect _WIRE_308.sr, _T_4194
node _T_4195 = bits(_WIRE_309, 13, 13)
connect _WIRE_308.sx, _T_4195
node _T_4196 = bits(_WIRE_309, 14, 14)
connect _WIRE_308.sw, _T_4196
node _T_4197 = bits(_WIRE_309, 15, 15)
connect _WIRE_308.gf, _T_4197
node _T_4198 = bits(_WIRE_309, 16, 16)
connect _WIRE_308.pf, _T_4198
node _T_4199 = bits(_WIRE_309, 17, 17)
connect _WIRE_308.ae_stage2, _T_4199
node _T_4200 = bits(_WIRE_309, 18, 18)
connect _WIRE_308.ae_final, _T_4200
node _T_4201 = bits(_WIRE_309, 19, 19)
connect _WIRE_308.ae_ptw, _T_4201
node _T_4202 = bits(_WIRE_309, 20, 20)
connect _WIRE_308.g, _T_4202
node _T_4203 = bits(_WIRE_309, 21, 21)
connect _WIRE_308.u, _T_4203
node _T_4204 = bits(_WIRE_309, 41, 22)
connect _WIRE_308.ppn, _T_4204
node _T_4205 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1))
when _T_4205 :
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
node _T_4206 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1))
when _T_4206 :
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
node _T_4207 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1))
when _T_4207 :
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
node _T_4208 = eq(sectored_entries[0][2].tag_v, UInt<1>(0h1))
when _T_4208 :
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
wire _WIRE_310 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_311 : UInt<42>
connect _WIRE_311, sectored_entries[0][3].data[0]
node _T_4209 = bits(_WIRE_311, 0, 0)
connect _WIRE_310.fragmented_superpage, _T_4209
node _T_4210 = bits(_WIRE_311, 1, 1)
connect _WIRE_310.c, _T_4210
node _T_4211 = bits(_WIRE_311, 2, 2)
connect _WIRE_310.eff, _T_4211
node _T_4212 = bits(_WIRE_311, 3, 3)
connect _WIRE_310.paa, _T_4212
node _T_4213 = bits(_WIRE_311, 4, 4)
connect _WIRE_310.pal, _T_4213
node _T_4214 = bits(_WIRE_311, 5, 5)
connect _WIRE_310.ppp, _T_4214
node _T_4215 = bits(_WIRE_311, 6, 6)
connect _WIRE_310.pr, _T_4215
node _T_4216 = bits(_WIRE_311, 7, 7)
connect _WIRE_310.px, _T_4216
node _T_4217 = bits(_WIRE_311, 8, 8)
connect _WIRE_310.pw, _T_4217
node _T_4218 = bits(_WIRE_311, 9, 9)
connect _WIRE_310.hr, _T_4218
node _T_4219 = bits(_WIRE_311, 10, 10)
connect _WIRE_310.hx, _T_4219
node _T_4220 = bits(_WIRE_311, 11, 11)
connect _WIRE_310.hw, _T_4220
node _T_4221 = bits(_WIRE_311, 12, 12)
connect _WIRE_310.sr, _T_4221
node _T_4222 = bits(_WIRE_311, 13, 13)
connect _WIRE_310.sx, _T_4222
node _T_4223 = bits(_WIRE_311, 14, 14)
connect _WIRE_310.sw, _T_4223
node _T_4224 = bits(_WIRE_311, 15, 15)
connect _WIRE_310.gf, _T_4224
node _T_4225 = bits(_WIRE_311, 16, 16)
connect _WIRE_310.pf, _T_4225
node _T_4226 = bits(_WIRE_311, 17, 17)
connect _WIRE_310.ae_stage2, _T_4226
node _T_4227 = bits(_WIRE_311, 18, 18)
connect _WIRE_310.ae_final, _T_4227
node _T_4228 = bits(_WIRE_311, 19, 19)
connect _WIRE_310.ae_ptw, _T_4228
node _T_4229 = bits(_WIRE_311, 20, 20)
connect _WIRE_310.g, _T_4229
node _T_4230 = bits(_WIRE_311, 21, 21)
connect _WIRE_310.u, _T_4230
node _T_4231 = bits(_WIRE_311, 41, 22)
connect _WIRE_310.ppn, _T_4231
wire _WIRE_312 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_313 : UInt<42>
connect _WIRE_313, sectored_entries[0][3].data[1]
node _T_4232 = bits(_WIRE_313, 0, 0)
connect _WIRE_312.fragmented_superpage, _T_4232
node _T_4233 = bits(_WIRE_313, 1, 1)
connect _WIRE_312.c, _T_4233
node _T_4234 = bits(_WIRE_313, 2, 2)
connect _WIRE_312.eff, _T_4234
node _T_4235 = bits(_WIRE_313, 3, 3)
connect _WIRE_312.paa, _T_4235
node _T_4236 = bits(_WIRE_313, 4, 4)
connect _WIRE_312.pal, _T_4236
node _T_4237 = bits(_WIRE_313, 5, 5)
connect _WIRE_312.ppp, _T_4237
node _T_4238 = bits(_WIRE_313, 6, 6)
connect _WIRE_312.pr, _T_4238
node _T_4239 = bits(_WIRE_313, 7, 7)
connect _WIRE_312.px, _T_4239
node _T_4240 = bits(_WIRE_313, 8, 8)
connect _WIRE_312.pw, _T_4240
node _T_4241 = bits(_WIRE_313, 9, 9)
connect _WIRE_312.hr, _T_4241
node _T_4242 = bits(_WIRE_313, 10, 10)
connect _WIRE_312.hx, _T_4242
node _T_4243 = bits(_WIRE_313, 11, 11)
connect _WIRE_312.hw, _T_4243
node _T_4244 = bits(_WIRE_313, 12, 12)
connect _WIRE_312.sr, _T_4244
node _T_4245 = bits(_WIRE_313, 13, 13)
connect _WIRE_312.sx, _T_4245
node _T_4246 = bits(_WIRE_313, 14, 14)
connect _WIRE_312.sw, _T_4246
node _T_4247 = bits(_WIRE_313, 15, 15)
connect _WIRE_312.gf, _T_4247
node _T_4248 = bits(_WIRE_313, 16, 16)
connect _WIRE_312.pf, _T_4248
node _T_4249 = bits(_WIRE_313, 17, 17)
connect _WIRE_312.ae_stage2, _T_4249
node _T_4250 = bits(_WIRE_313, 18, 18)
connect _WIRE_312.ae_final, _T_4250
node _T_4251 = bits(_WIRE_313, 19, 19)
connect _WIRE_312.ae_ptw, _T_4251
node _T_4252 = bits(_WIRE_313, 20, 20)
connect _WIRE_312.g, _T_4252
node _T_4253 = bits(_WIRE_313, 21, 21)
connect _WIRE_312.u, _T_4253
node _T_4254 = bits(_WIRE_313, 41, 22)
connect _WIRE_312.ppn, _T_4254
wire _WIRE_314 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_315 : UInt<42>
connect _WIRE_315, sectored_entries[0][3].data[2]
node _T_4255 = bits(_WIRE_315, 0, 0)
connect _WIRE_314.fragmented_superpage, _T_4255
node _T_4256 = bits(_WIRE_315, 1, 1)
connect _WIRE_314.c, _T_4256
node _T_4257 = bits(_WIRE_315, 2, 2)
connect _WIRE_314.eff, _T_4257
node _T_4258 = bits(_WIRE_315, 3, 3)
connect _WIRE_314.paa, _T_4258
node _T_4259 = bits(_WIRE_315, 4, 4)
connect _WIRE_314.pal, _T_4259
node _T_4260 = bits(_WIRE_315, 5, 5)
connect _WIRE_314.ppp, _T_4260
node _T_4261 = bits(_WIRE_315, 6, 6)
connect _WIRE_314.pr, _T_4261
node _T_4262 = bits(_WIRE_315, 7, 7)
connect _WIRE_314.px, _T_4262
node _T_4263 = bits(_WIRE_315, 8, 8)
connect _WIRE_314.pw, _T_4263
node _T_4264 = bits(_WIRE_315, 9, 9)
connect _WIRE_314.hr, _T_4264
node _T_4265 = bits(_WIRE_315, 10, 10)
connect _WIRE_314.hx, _T_4265
node _T_4266 = bits(_WIRE_315, 11, 11)
connect _WIRE_314.hw, _T_4266
node _T_4267 = bits(_WIRE_315, 12, 12)
connect _WIRE_314.sr, _T_4267
node _T_4268 = bits(_WIRE_315, 13, 13)
connect _WIRE_314.sx, _T_4268
node _T_4269 = bits(_WIRE_315, 14, 14)
connect _WIRE_314.sw, _T_4269
node _T_4270 = bits(_WIRE_315, 15, 15)
connect _WIRE_314.gf, _T_4270
node _T_4271 = bits(_WIRE_315, 16, 16)
connect _WIRE_314.pf, _T_4271
node _T_4272 = bits(_WIRE_315, 17, 17)
connect _WIRE_314.ae_stage2, _T_4272
node _T_4273 = bits(_WIRE_315, 18, 18)
connect _WIRE_314.ae_final, _T_4273
node _T_4274 = bits(_WIRE_315, 19, 19)
connect _WIRE_314.ae_ptw, _T_4274
node _T_4275 = bits(_WIRE_315, 20, 20)
connect _WIRE_314.g, _T_4275
node _T_4276 = bits(_WIRE_315, 21, 21)
connect _WIRE_314.u, _T_4276
node _T_4277 = bits(_WIRE_315, 41, 22)
connect _WIRE_314.ppn, _T_4277
wire _WIRE_316 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_317 : UInt<42>
connect _WIRE_317, sectored_entries[0][3].data[3]
node _T_4278 = bits(_WIRE_317, 0, 0)
connect _WIRE_316.fragmented_superpage, _T_4278
node _T_4279 = bits(_WIRE_317, 1, 1)
connect _WIRE_316.c, _T_4279
node _T_4280 = bits(_WIRE_317, 2, 2)
connect _WIRE_316.eff, _T_4280
node _T_4281 = bits(_WIRE_317, 3, 3)
connect _WIRE_316.paa, _T_4281
node _T_4282 = bits(_WIRE_317, 4, 4)
connect _WIRE_316.pal, _T_4282
node _T_4283 = bits(_WIRE_317, 5, 5)
connect _WIRE_316.ppp, _T_4283
node _T_4284 = bits(_WIRE_317, 6, 6)
connect _WIRE_316.pr, _T_4284
node _T_4285 = bits(_WIRE_317, 7, 7)
connect _WIRE_316.px, _T_4285
node _T_4286 = bits(_WIRE_317, 8, 8)
connect _WIRE_316.pw, _T_4286
node _T_4287 = bits(_WIRE_317, 9, 9)
connect _WIRE_316.hr, _T_4287
node _T_4288 = bits(_WIRE_317, 10, 10)
connect _WIRE_316.hx, _T_4288
node _T_4289 = bits(_WIRE_317, 11, 11)
connect _WIRE_316.hw, _T_4289
node _T_4290 = bits(_WIRE_317, 12, 12)
connect _WIRE_316.sr, _T_4290
node _T_4291 = bits(_WIRE_317, 13, 13)
connect _WIRE_316.sx, _T_4291
node _T_4292 = bits(_WIRE_317, 14, 14)
connect _WIRE_316.sw, _T_4292
node _T_4293 = bits(_WIRE_317, 15, 15)
connect _WIRE_316.gf, _T_4293
node _T_4294 = bits(_WIRE_317, 16, 16)
connect _WIRE_316.pf, _T_4294
node _T_4295 = bits(_WIRE_317, 17, 17)
connect _WIRE_316.ae_stage2, _T_4295
node _T_4296 = bits(_WIRE_317, 18, 18)
connect _WIRE_316.ae_final, _T_4296
node _T_4297 = bits(_WIRE_317, 19, 19)
connect _WIRE_316.ae_ptw, _T_4297
node _T_4298 = bits(_WIRE_317, 20, 20)
connect _WIRE_316.g, _T_4298
node _T_4299 = bits(_WIRE_317, 21, 21)
connect _WIRE_316.u, _T_4299
node _T_4300 = bits(_WIRE_317, 41, 22)
connect _WIRE_316.ppn, _T_4300
node _T_4301 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1))
when _T_4301 :
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
node _T_4302 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1))
when _T_4302 :
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
node _T_4303 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1))
when _T_4303 :
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
node _T_4304 = eq(sectored_entries[0][3].tag_v, UInt<1>(0h1))
when _T_4304 :
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
wire _WIRE_318 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_319 : UInt<42>
connect _WIRE_319, sectored_entries[0][4].data[0]
node _T_4305 = bits(_WIRE_319, 0, 0)
connect _WIRE_318.fragmented_superpage, _T_4305
node _T_4306 = bits(_WIRE_319, 1, 1)
connect _WIRE_318.c, _T_4306
node _T_4307 = bits(_WIRE_319, 2, 2)
connect _WIRE_318.eff, _T_4307
node _T_4308 = bits(_WIRE_319, 3, 3)
connect _WIRE_318.paa, _T_4308
node _T_4309 = bits(_WIRE_319, 4, 4)
connect _WIRE_318.pal, _T_4309
node _T_4310 = bits(_WIRE_319, 5, 5)
connect _WIRE_318.ppp, _T_4310
node _T_4311 = bits(_WIRE_319, 6, 6)
connect _WIRE_318.pr, _T_4311
node _T_4312 = bits(_WIRE_319, 7, 7)
connect _WIRE_318.px, _T_4312
node _T_4313 = bits(_WIRE_319, 8, 8)
connect _WIRE_318.pw, _T_4313
node _T_4314 = bits(_WIRE_319, 9, 9)
connect _WIRE_318.hr, _T_4314
node _T_4315 = bits(_WIRE_319, 10, 10)
connect _WIRE_318.hx, _T_4315
node _T_4316 = bits(_WIRE_319, 11, 11)
connect _WIRE_318.hw, _T_4316
node _T_4317 = bits(_WIRE_319, 12, 12)
connect _WIRE_318.sr, _T_4317
node _T_4318 = bits(_WIRE_319, 13, 13)
connect _WIRE_318.sx, _T_4318
node _T_4319 = bits(_WIRE_319, 14, 14)
connect _WIRE_318.sw, _T_4319
node _T_4320 = bits(_WIRE_319, 15, 15)
connect _WIRE_318.gf, _T_4320
node _T_4321 = bits(_WIRE_319, 16, 16)
connect _WIRE_318.pf, _T_4321
node _T_4322 = bits(_WIRE_319, 17, 17)
connect _WIRE_318.ae_stage2, _T_4322
node _T_4323 = bits(_WIRE_319, 18, 18)
connect _WIRE_318.ae_final, _T_4323
node _T_4324 = bits(_WIRE_319, 19, 19)
connect _WIRE_318.ae_ptw, _T_4324
node _T_4325 = bits(_WIRE_319, 20, 20)
connect _WIRE_318.g, _T_4325
node _T_4326 = bits(_WIRE_319, 21, 21)
connect _WIRE_318.u, _T_4326
node _T_4327 = bits(_WIRE_319, 41, 22)
connect _WIRE_318.ppn, _T_4327
wire _WIRE_320 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_321 : UInt<42>
connect _WIRE_321, sectored_entries[0][4].data[1]
node _T_4328 = bits(_WIRE_321, 0, 0)
connect _WIRE_320.fragmented_superpage, _T_4328
node _T_4329 = bits(_WIRE_321, 1, 1)
connect _WIRE_320.c, _T_4329
node _T_4330 = bits(_WIRE_321, 2, 2)
connect _WIRE_320.eff, _T_4330
node _T_4331 = bits(_WIRE_321, 3, 3)
connect _WIRE_320.paa, _T_4331
node _T_4332 = bits(_WIRE_321, 4, 4)
connect _WIRE_320.pal, _T_4332
node _T_4333 = bits(_WIRE_321, 5, 5)
connect _WIRE_320.ppp, _T_4333
node _T_4334 = bits(_WIRE_321, 6, 6)
connect _WIRE_320.pr, _T_4334
node _T_4335 = bits(_WIRE_321, 7, 7)
connect _WIRE_320.px, _T_4335
node _T_4336 = bits(_WIRE_321, 8, 8)
connect _WIRE_320.pw, _T_4336
node _T_4337 = bits(_WIRE_321, 9, 9)
connect _WIRE_320.hr, _T_4337
node _T_4338 = bits(_WIRE_321, 10, 10)
connect _WIRE_320.hx, _T_4338
node _T_4339 = bits(_WIRE_321, 11, 11)
connect _WIRE_320.hw, _T_4339
node _T_4340 = bits(_WIRE_321, 12, 12)
connect _WIRE_320.sr, _T_4340
node _T_4341 = bits(_WIRE_321, 13, 13)
connect _WIRE_320.sx, _T_4341
node _T_4342 = bits(_WIRE_321, 14, 14)
connect _WIRE_320.sw, _T_4342
node _T_4343 = bits(_WIRE_321, 15, 15)
connect _WIRE_320.gf, _T_4343
node _T_4344 = bits(_WIRE_321, 16, 16)
connect _WIRE_320.pf, _T_4344
node _T_4345 = bits(_WIRE_321, 17, 17)
connect _WIRE_320.ae_stage2, _T_4345
node _T_4346 = bits(_WIRE_321, 18, 18)
connect _WIRE_320.ae_final, _T_4346
node _T_4347 = bits(_WIRE_321, 19, 19)
connect _WIRE_320.ae_ptw, _T_4347
node _T_4348 = bits(_WIRE_321, 20, 20)
connect _WIRE_320.g, _T_4348
node _T_4349 = bits(_WIRE_321, 21, 21)
connect _WIRE_320.u, _T_4349
node _T_4350 = bits(_WIRE_321, 41, 22)
connect _WIRE_320.ppn, _T_4350
wire _WIRE_322 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_323 : UInt<42>
connect _WIRE_323, sectored_entries[0][4].data[2]
node _T_4351 = bits(_WIRE_323, 0, 0)
connect _WIRE_322.fragmented_superpage, _T_4351
node _T_4352 = bits(_WIRE_323, 1, 1)
connect _WIRE_322.c, _T_4352
node _T_4353 = bits(_WIRE_323, 2, 2)
connect _WIRE_322.eff, _T_4353
node _T_4354 = bits(_WIRE_323, 3, 3)
connect _WIRE_322.paa, _T_4354
node _T_4355 = bits(_WIRE_323, 4, 4)
connect _WIRE_322.pal, _T_4355
node _T_4356 = bits(_WIRE_323, 5, 5)
connect _WIRE_322.ppp, _T_4356
node _T_4357 = bits(_WIRE_323, 6, 6)
connect _WIRE_322.pr, _T_4357
node _T_4358 = bits(_WIRE_323, 7, 7)
connect _WIRE_322.px, _T_4358
node _T_4359 = bits(_WIRE_323, 8, 8)
connect _WIRE_322.pw, _T_4359
node _T_4360 = bits(_WIRE_323, 9, 9)
connect _WIRE_322.hr, _T_4360
node _T_4361 = bits(_WIRE_323, 10, 10)
connect _WIRE_322.hx, _T_4361
node _T_4362 = bits(_WIRE_323, 11, 11)
connect _WIRE_322.hw, _T_4362
node _T_4363 = bits(_WIRE_323, 12, 12)
connect _WIRE_322.sr, _T_4363
node _T_4364 = bits(_WIRE_323, 13, 13)
connect _WIRE_322.sx, _T_4364
node _T_4365 = bits(_WIRE_323, 14, 14)
connect _WIRE_322.sw, _T_4365
node _T_4366 = bits(_WIRE_323, 15, 15)
connect _WIRE_322.gf, _T_4366
node _T_4367 = bits(_WIRE_323, 16, 16)
connect _WIRE_322.pf, _T_4367
node _T_4368 = bits(_WIRE_323, 17, 17)
connect _WIRE_322.ae_stage2, _T_4368
node _T_4369 = bits(_WIRE_323, 18, 18)
connect _WIRE_322.ae_final, _T_4369
node _T_4370 = bits(_WIRE_323, 19, 19)
connect _WIRE_322.ae_ptw, _T_4370
node _T_4371 = bits(_WIRE_323, 20, 20)
connect _WIRE_322.g, _T_4371
node _T_4372 = bits(_WIRE_323, 21, 21)
connect _WIRE_322.u, _T_4372
node _T_4373 = bits(_WIRE_323, 41, 22)
connect _WIRE_322.ppn, _T_4373
wire _WIRE_324 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_325 : UInt<42>
connect _WIRE_325, sectored_entries[0][4].data[3]
node _T_4374 = bits(_WIRE_325, 0, 0)
connect _WIRE_324.fragmented_superpage, _T_4374
node _T_4375 = bits(_WIRE_325, 1, 1)
connect _WIRE_324.c, _T_4375
node _T_4376 = bits(_WIRE_325, 2, 2)
connect _WIRE_324.eff, _T_4376
node _T_4377 = bits(_WIRE_325, 3, 3)
connect _WIRE_324.paa, _T_4377
node _T_4378 = bits(_WIRE_325, 4, 4)
connect _WIRE_324.pal, _T_4378
node _T_4379 = bits(_WIRE_325, 5, 5)
connect _WIRE_324.ppp, _T_4379
node _T_4380 = bits(_WIRE_325, 6, 6)
connect _WIRE_324.pr, _T_4380
node _T_4381 = bits(_WIRE_325, 7, 7)
connect _WIRE_324.px, _T_4381
node _T_4382 = bits(_WIRE_325, 8, 8)
connect _WIRE_324.pw, _T_4382
node _T_4383 = bits(_WIRE_325, 9, 9)
connect _WIRE_324.hr, _T_4383
node _T_4384 = bits(_WIRE_325, 10, 10)
connect _WIRE_324.hx, _T_4384
node _T_4385 = bits(_WIRE_325, 11, 11)
connect _WIRE_324.hw, _T_4385
node _T_4386 = bits(_WIRE_325, 12, 12)
connect _WIRE_324.sr, _T_4386
node _T_4387 = bits(_WIRE_325, 13, 13)
connect _WIRE_324.sx, _T_4387
node _T_4388 = bits(_WIRE_325, 14, 14)
connect _WIRE_324.sw, _T_4388
node _T_4389 = bits(_WIRE_325, 15, 15)
connect _WIRE_324.gf, _T_4389
node _T_4390 = bits(_WIRE_325, 16, 16)
connect _WIRE_324.pf, _T_4390
node _T_4391 = bits(_WIRE_325, 17, 17)
connect _WIRE_324.ae_stage2, _T_4391
node _T_4392 = bits(_WIRE_325, 18, 18)
connect _WIRE_324.ae_final, _T_4392
node _T_4393 = bits(_WIRE_325, 19, 19)
connect _WIRE_324.ae_ptw, _T_4393
node _T_4394 = bits(_WIRE_325, 20, 20)
connect _WIRE_324.g, _T_4394
node _T_4395 = bits(_WIRE_325, 21, 21)
connect _WIRE_324.u, _T_4395
node _T_4396 = bits(_WIRE_325, 41, 22)
connect _WIRE_324.ppn, _T_4396
node _T_4397 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1))
when _T_4397 :
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
node _T_4398 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1))
when _T_4398 :
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
node _T_4399 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1))
when _T_4399 :
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
node _T_4400 = eq(sectored_entries[0][4].tag_v, UInt<1>(0h1))
when _T_4400 :
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
wire _WIRE_326 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_327 : UInt<42>
connect _WIRE_327, sectored_entries[0][5].data[0]
node _T_4401 = bits(_WIRE_327, 0, 0)
connect _WIRE_326.fragmented_superpage, _T_4401
node _T_4402 = bits(_WIRE_327, 1, 1)
connect _WIRE_326.c, _T_4402
node _T_4403 = bits(_WIRE_327, 2, 2)
connect _WIRE_326.eff, _T_4403
node _T_4404 = bits(_WIRE_327, 3, 3)
connect _WIRE_326.paa, _T_4404
node _T_4405 = bits(_WIRE_327, 4, 4)
connect _WIRE_326.pal, _T_4405
node _T_4406 = bits(_WIRE_327, 5, 5)
connect _WIRE_326.ppp, _T_4406
node _T_4407 = bits(_WIRE_327, 6, 6)
connect _WIRE_326.pr, _T_4407
node _T_4408 = bits(_WIRE_327, 7, 7)
connect _WIRE_326.px, _T_4408
node _T_4409 = bits(_WIRE_327, 8, 8)
connect _WIRE_326.pw, _T_4409
node _T_4410 = bits(_WIRE_327, 9, 9)
connect _WIRE_326.hr, _T_4410
node _T_4411 = bits(_WIRE_327, 10, 10)
connect _WIRE_326.hx, _T_4411
node _T_4412 = bits(_WIRE_327, 11, 11)
connect _WIRE_326.hw, _T_4412
node _T_4413 = bits(_WIRE_327, 12, 12)
connect _WIRE_326.sr, _T_4413
node _T_4414 = bits(_WIRE_327, 13, 13)
connect _WIRE_326.sx, _T_4414
node _T_4415 = bits(_WIRE_327, 14, 14)
connect _WIRE_326.sw, _T_4415
node _T_4416 = bits(_WIRE_327, 15, 15)
connect _WIRE_326.gf, _T_4416
node _T_4417 = bits(_WIRE_327, 16, 16)
connect _WIRE_326.pf, _T_4417
node _T_4418 = bits(_WIRE_327, 17, 17)
connect _WIRE_326.ae_stage2, _T_4418
node _T_4419 = bits(_WIRE_327, 18, 18)
connect _WIRE_326.ae_final, _T_4419
node _T_4420 = bits(_WIRE_327, 19, 19)
connect _WIRE_326.ae_ptw, _T_4420
node _T_4421 = bits(_WIRE_327, 20, 20)
connect _WIRE_326.g, _T_4421
node _T_4422 = bits(_WIRE_327, 21, 21)
connect _WIRE_326.u, _T_4422
node _T_4423 = bits(_WIRE_327, 41, 22)
connect _WIRE_326.ppn, _T_4423
wire _WIRE_328 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_329 : UInt<42>
connect _WIRE_329, sectored_entries[0][5].data[1]
node _T_4424 = bits(_WIRE_329, 0, 0)
connect _WIRE_328.fragmented_superpage, _T_4424
node _T_4425 = bits(_WIRE_329, 1, 1)
connect _WIRE_328.c, _T_4425
node _T_4426 = bits(_WIRE_329, 2, 2)
connect _WIRE_328.eff, _T_4426
node _T_4427 = bits(_WIRE_329, 3, 3)
connect _WIRE_328.paa, _T_4427
node _T_4428 = bits(_WIRE_329, 4, 4)
connect _WIRE_328.pal, _T_4428
node _T_4429 = bits(_WIRE_329, 5, 5)
connect _WIRE_328.ppp, _T_4429
node _T_4430 = bits(_WIRE_329, 6, 6)
connect _WIRE_328.pr, _T_4430
node _T_4431 = bits(_WIRE_329, 7, 7)
connect _WIRE_328.px, _T_4431
node _T_4432 = bits(_WIRE_329, 8, 8)
connect _WIRE_328.pw, _T_4432
node _T_4433 = bits(_WIRE_329, 9, 9)
connect _WIRE_328.hr, _T_4433
node _T_4434 = bits(_WIRE_329, 10, 10)
connect _WIRE_328.hx, _T_4434
node _T_4435 = bits(_WIRE_329, 11, 11)
connect _WIRE_328.hw, _T_4435
node _T_4436 = bits(_WIRE_329, 12, 12)
connect _WIRE_328.sr, _T_4436
node _T_4437 = bits(_WIRE_329, 13, 13)
connect _WIRE_328.sx, _T_4437
node _T_4438 = bits(_WIRE_329, 14, 14)
connect _WIRE_328.sw, _T_4438
node _T_4439 = bits(_WIRE_329, 15, 15)
connect _WIRE_328.gf, _T_4439
node _T_4440 = bits(_WIRE_329, 16, 16)
connect _WIRE_328.pf, _T_4440
node _T_4441 = bits(_WIRE_329, 17, 17)
connect _WIRE_328.ae_stage2, _T_4441
node _T_4442 = bits(_WIRE_329, 18, 18)
connect _WIRE_328.ae_final, _T_4442
node _T_4443 = bits(_WIRE_329, 19, 19)
connect _WIRE_328.ae_ptw, _T_4443
node _T_4444 = bits(_WIRE_329, 20, 20)
connect _WIRE_328.g, _T_4444
node _T_4445 = bits(_WIRE_329, 21, 21)
connect _WIRE_328.u, _T_4445
node _T_4446 = bits(_WIRE_329, 41, 22)
connect _WIRE_328.ppn, _T_4446
wire _WIRE_330 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_331 : UInt<42>
connect _WIRE_331, sectored_entries[0][5].data[2]
node _T_4447 = bits(_WIRE_331, 0, 0)
connect _WIRE_330.fragmented_superpage, _T_4447
node _T_4448 = bits(_WIRE_331, 1, 1)
connect _WIRE_330.c, _T_4448
node _T_4449 = bits(_WIRE_331, 2, 2)
connect _WIRE_330.eff, _T_4449
node _T_4450 = bits(_WIRE_331, 3, 3)
connect _WIRE_330.paa, _T_4450
node _T_4451 = bits(_WIRE_331, 4, 4)
connect _WIRE_330.pal, _T_4451
node _T_4452 = bits(_WIRE_331, 5, 5)
connect _WIRE_330.ppp, _T_4452
node _T_4453 = bits(_WIRE_331, 6, 6)
connect _WIRE_330.pr, _T_4453
node _T_4454 = bits(_WIRE_331, 7, 7)
connect _WIRE_330.px, _T_4454
node _T_4455 = bits(_WIRE_331, 8, 8)
connect _WIRE_330.pw, _T_4455
node _T_4456 = bits(_WIRE_331, 9, 9)
connect _WIRE_330.hr, _T_4456
node _T_4457 = bits(_WIRE_331, 10, 10)
connect _WIRE_330.hx, _T_4457
node _T_4458 = bits(_WIRE_331, 11, 11)
connect _WIRE_330.hw, _T_4458
node _T_4459 = bits(_WIRE_331, 12, 12)
connect _WIRE_330.sr, _T_4459
node _T_4460 = bits(_WIRE_331, 13, 13)
connect _WIRE_330.sx, _T_4460
node _T_4461 = bits(_WIRE_331, 14, 14)
connect _WIRE_330.sw, _T_4461
node _T_4462 = bits(_WIRE_331, 15, 15)
connect _WIRE_330.gf, _T_4462
node _T_4463 = bits(_WIRE_331, 16, 16)
connect _WIRE_330.pf, _T_4463
node _T_4464 = bits(_WIRE_331, 17, 17)
connect _WIRE_330.ae_stage2, _T_4464
node _T_4465 = bits(_WIRE_331, 18, 18)
connect _WIRE_330.ae_final, _T_4465
node _T_4466 = bits(_WIRE_331, 19, 19)
connect _WIRE_330.ae_ptw, _T_4466
node _T_4467 = bits(_WIRE_331, 20, 20)
connect _WIRE_330.g, _T_4467
node _T_4468 = bits(_WIRE_331, 21, 21)
connect _WIRE_330.u, _T_4468
node _T_4469 = bits(_WIRE_331, 41, 22)
connect _WIRE_330.ppn, _T_4469
wire _WIRE_332 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_333 : UInt<42>
connect _WIRE_333, sectored_entries[0][5].data[3]
node _T_4470 = bits(_WIRE_333, 0, 0)
connect _WIRE_332.fragmented_superpage, _T_4470
node _T_4471 = bits(_WIRE_333, 1, 1)
connect _WIRE_332.c, _T_4471
node _T_4472 = bits(_WIRE_333, 2, 2)
connect _WIRE_332.eff, _T_4472
node _T_4473 = bits(_WIRE_333, 3, 3)
connect _WIRE_332.paa, _T_4473
node _T_4474 = bits(_WIRE_333, 4, 4)
connect _WIRE_332.pal, _T_4474
node _T_4475 = bits(_WIRE_333, 5, 5)
connect _WIRE_332.ppp, _T_4475
node _T_4476 = bits(_WIRE_333, 6, 6)
connect _WIRE_332.pr, _T_4476
node _T_4477 = bits(_WIRE_333, 7, 7)
connect _WIRE_332.px, _T_4477
node _T_4478 = bits(_WIRE_333, 8, 8)
connect _WIRE_332.pw, _T_4478
node _T_4479 = bits(_WIRE_333, 9, 9)
connect _WIRE_332.hr, _T_4479
node _T_4480 = bits(_WIRE_333, 10, 10)
connect _WIRE_332.hx, _T_4480
node _T_4481 = bits(_WIRE_333, 11, 11)
connect _WIRE_332.hw, _T_4481
node _T_4482 = bits(_WIRE_333, 12, 12)
connect _WIRE_332.sr, _T_4482
node _T_4483 = bits(_WIRE_333, 13, 13)
connect _WIRE_332.sx, _T_4483
node _T_4484 = bits(_WIRE_333, 14, 14)
connect _WIRE_332.sw, _T_4484
node _T_4485 = bits(_WIRE_333, 15, 15)
connect _WIRE_332.gf, _T_4485
node _T_4486 = bits(_WIRE_333, 16, 16)
connect _WIRE_332.pf, _T_4486
node _T_4487 = bits(_WIRE_333, 17, 17)
connect _WIRE_332.ae_stage2, _T_4487
node _T_4488 = bits(_WIRE_333, 18, 18)
connect _WIRE_332.ae_final, _T_4488
node _T_4489 = bits(_WIRE_333, 19, 19)
connect _WIRE_332.ae_ptw, _T_4489
node _T_4490 = bits(_WIRE_333, 20, 20)
connect _WIRE_332.g, _T_4490
node _T_4491 = bits(_WIRE_333, 21, 21)
connect _WIRE_332.u, _T_4491
node _T_4492 = bits(_WIRE_333, 41, 22)
connect _WIRE_332.ppn, _T_4492
node _T_4493 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1))
when _T_4493 :
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
node _T_4494 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1))
when _T_4494 :
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
node _T_4495 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1))
when _T_4495 :
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
node _T_4496 = eq(sectored_entries[0][5].tag_v, UInt<1>(0h1))
when _T_4496 :
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
wire _WIRE_334 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_335 : UInt<42>
connect _WIRE_335, sectored_entries[0][6].data[0]
node _T_4497 = bits(_WIRE_335, 0, 0)
connect _WIRE_334.fragmented_superpage, _T_4497
node _T_4498 = bits(_WIRE_335, 1, 1)
connect _WIRE_334.c, _T_4498
node _T_4499 = bits(_WIRE_335, 2, 2)
connect _WIRE_334.eff, _T_4499
node _T_4500 = bits(_WIRE_335, 3, 3)
connect _WIRE_334.paa, _T_4500
node _T_4501 = bits(_WIRE_335, 4, 4)
connect _WIRE_334.pal, _T_4501
node _T_4502 = bits(_WIRE_335, 5, 5)
connect _WIRE_334.ppp, _T_4502
node _T_4503 = bits(_WIRE_335, 6, 6)
connect _WIRE_334.pr, _T_4503
node _T_4504 = bits(_WIRE_335, 7, 7)
connect _WIRE_334.px, _T_4504
node _T_4505 = bits(_WIRE_335, 8, 8)
connect _WIRE_334.pw, _T_4505
node _T_4506 = bits(_WIRE_335, 9, 9)
connect _WIRE_334.hr, _T_4506
node _T_4507 = bits(_WIRE_335, 10, 10)
connect _WIRE_334.hx, _T_4507
node _T_4508 = bits(_WIRE_335, 11, 11)
connect _WIRE_334.hw, _T_4508
node _T_4509 = bits(_WIRE_335, 12, 12)
connect _WIRE_334.sr, _T_4509
node _T_4510 = bits(_WIRE_335, 13, 13)
connect _WIRE_334.sx, _T_4510
node _T_4511 = bits(_WIRE_335, 14, 14)
connect _WIRE_334.sw, _T_4511
node _T_4512 = bits(_WIRE_335, 15, 15)
connect _WIRE_334.gf, _T_4512
node _T_4513 = bits(_WIRE_335, 16, 16)
connect _WIRE_334.pf, _T_4513
node _T_4514 = bits(_WIRE_335, 17, 17)
connect _WIRE_334.ae_stage2, _T_4514
node _T_4515 = bits(_WIRE_335, 18, 18)
connect _WIRE_334.ae_final, _T_4515
node _T_4516 = bits(_WIRE_335, 19, 19)
connect _WIRE_334.ae_ptw, _T_4516
node _T_4517 = bits(_WIRE_335, 20, 20)
connect _WIRE_334.g, _T_4517
node _T_4518 = bits(_WIRE_335, 21, 21)
connect _WIRE_334.u, _T_4518
node _T_4519 = bits(_WIRE_335, 41, 22)
connect _WIRE_334.ppn, _T_4519
wire _WIRE_336 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_337 : UInt<42>
connect _WIRE_337, sectored_entries[0][6].data[1]
node _T_4520 = bits(_WIRE_337, 0, 0)
connect _WIRE_336.fragmented_superpage, _T_4520
node _T_4521 = bits(_WIRE_337, 1, 1)
connect _WIRE_336.c, _T_4521
node _T_4522 = bits(_WIRE_337, 2, 2)
connect _WIRE_336.eff, _T_4522
node _T_4523 = bits(_WIRE_337, 3, 3)
connect _WIRE_336.paa, _T_4523
node _T_4524 = bits(_WIRE_337, 4, 4)
connect _WIRE_336.pal, _T_4524
node _T_4525 = bits(_WIRE_337, 5, 5)
connect _WIRE_336.ppp, _T_4525
node _T_4526 = bits(_WIRE_337, 6, 6)
connect _WIRE_336.pr, _T_4526
node _T_4527 = bits(_WIRE_337, 7, 7)
connect _WIRE_336.px, _T_4527
node _T_4528 = bits(_WIRE_337, 8, 8)
connect _WIRE_336.pw, _T_4528
node _T_4529 = bits(_WIRE_337, 9, 9)
connect _WIRE_336.hr, _T_4529
node _T_4530 = bits(_WIRE_337, 10, 10)
connect _WIRE_336.hx, _T_4530
node _T_4531 = bits(_WIRE_337, 11, 11)
connect _WIRE_336.hw, _T_4531
node _T_4532 = bits(_WIRE_337, 12, 12)
connect _WIRE_336.sr, _T_4532
node _T_4533 = bits(_WIRE_337, 13, 13)
connect _WIRE_336.sx, _T_4533
node _T_4534 = bits(_WIRE_337, 14, 14)
connect _WIRE_336.sw, _T_4534
node _T_4535 = bits(_WIRE_337, 15, 15)
connect _WIRE_336.gf, _T_4535
node _T_4536 = bits(_WIRE_337, 16, 16)
connect _WIRE_336.pf, _T_4536
node _T_4537 = bits(_WIRE_337, 17, 17)
connect _WIRE_336.ae_stage2, _T_4537
node _T_4538 = bits(_WIRE_337, 18, 18)
connect _WIRE_336.ae_final, _T_4538
node _T_4539 = bits(_WIRE_337, 19, 19)
connect _WIRE_336.ae_ptw, _T_4539
node _T_4540 = bits(_WIRE_337, 20, 20)
connect _WIRE_336.g, _T_4540
node _T_4541 = bits(_WIRE_337, 21, 21)
connect _WIRE_336.u, _T_4541
node _T_4542 = bits(_WIRE_337, 41, 22)
connect _WIRE_336.ppn, _T_4542
wire _WIRE_338 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_339 : UInt<42>
connect _WIRE_339, sectored_entries[0][6].data[2]
node _T_4543 = bits(_WIRE_339, 0, 0)
connect _WIRE_338.fragmented_superpage, _T_4543
node _T_4544 = bits(_WIRE_339, 1, 1)
connect _WIRE_338.c, _T_4544
node _T_4545 = bits(_WIRE_339, 2, 2)
connect _WIRE_338.eff, _T_4545
node _T_4546 = bits(_WIRE_339, 3, 3)
connect _WIRE_338.paa, _T_4546
node _T_4547 = bits(_WIRE_339, 4, 4)
connect _WIRE_338.pal, _T_4547
node _T_4548 = bits(_WIRE_339, 5, 5)
connect _WIRE_338.ppp, _T_4548
node _T_4549 = bits(_WIRE_339, 6, 6)
connect _WIRE_338.pr, _T_4549
node _T_4550 = bits(_WIRE_339, 7, 7)
connect _WIRE_338.px, _T_4550
node _T_4551 = bits(_WIRE_339, 8, 8)
connect _WIRE_338.pw, _T_4551
node _T_4552 = bits(_WIRE_339, 9, 9)
connect _WIRE_338.hr, _T_4552
node _T_4553 = bits(_WIRE_339, 10, 10)
connect _WIRE_338.hx, _T_4553
node _T_4554 = bits(_WIRE_339, 11, 11)
connect _WIRE_338.hw, _T_4554
node _T_4555 = bits(_WIRE_339, 12, 12)
connect _WIRE_338.sr, _T_4555
node _T_4556 = bits(_WIRE_339, 13, 13)
connect _WIRE_338.sx, _T_4556
node _T_4557 = bits(_WIRE_339, 14, 14)
connect _WIRE_338.sw, _T_4557
node _T_4558 = bits(_WIRE_339, 15, 15)
connect _WIRE_338.gf, _T_4558
node _T_4559 = bits(_WIRE_339, 16, 16)
connect _WIRE_338.pf, _T_4559
node _T_4560 = bits(_WIRE_339, 17, 17)
connect _WIRE_338.ae_stage2, _T_4560
node _T_4561 = bits(_WIRE_339, 18, 18)
connect _WIRE_338.ae_final, _T_4561
node _T_4562 = bits(_WIRE_339, 19, 19)
connect _WIRE_338.ae_ptw, _T_4562
node _T_4563 = bits(_WIRE_339, 20, 20)
connect _WIRE_338.g, _T_4563
node _T_4564 = bits(_WIRE_339, 21, 21)
connect _WIRE_338.u, _T_4564
node _T_4565 = bits(_WIRE_339, 41, 22)
connect _WIRE_338.ppn, _T_4565
wire _WIRE_340 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_341 : UInt<42>
connect _WIRE_341, sectored_entries[0][6].data[3]
node _T_4566 = bits(_WIRE_341, 0, 0)
connect _WIRE_340.fragmented_superpage, _T_4566
node _T_4567 = bits(_WIRE_341, 1, 1)
connect _WIRE_340.c, _T_4567
node _T_4568 = bits(_WIRE_341, 2, 2)
connect _WIRE_340.eff, _T_4568
node _T_4569 = bits(_WIRE_341, 3, 3)
connect _WIRE_340.paa, _T_4569
node _T_4570 = bits(_WIRE_341, 4, 4)
connect _WIRE_340.pal, _T_4570
node _T_4571 = bits(_WIRE_341, 5, 5)
connect _WIRE_340.ppp, _T_4571
node _T_4572 = bits(_WIRE_341, 6, 6)
connect _WIRE_340.pr, _T_4572
node _T_4573 = bits(_WIRE_341, 7, 7)
connect _WIRE_340.px, _T_4573
node _T_4574 = bits(_WIRE_341, 8, 8)
connect _WIRE_340.pw, _T_4574
node _T_4575 = bits(_WIRE_341, 9, 9)
connect _WIRE_340.hr, _T_4575
node _T_4576 = bits(_WIRE_341, 10, 10)
connect _WIRE_340.hx, _T_4576
node _T_4577 = bits(_WIRE_341, 11, 11)
connect _WIRE_340.hw, _T_4577
node _T_4578 = bits(_WIRE_341, 12, 12)
connect _WIRE_340.sr, _T_4578
node _T_4579 = bits(_WIRE_341, 13, 13)
connect _WIRE_340.sx, _T_4579
node _T_4580 = bits(_WIRE_341, 14, 14)
connect _WIRE_340.sw, _T_4580
node _T_4581 = bits(_WIRE_341, 15, 15)
connect _WIRE_340.gf, _T_4581
node _T_4582 = bits(_WIRE_341, 16, 16)
connect _WIRE_340.pf, _T_4582
node _T_4583 = bits(_WIRE_341, 17, 17)
connect _WIRE_340.ae_stage2, _T_4583
node _T_4584 = bits(_WIRE_341, 18, 18)
connect _WIRE_340.ae_final, _T_4584
node _T_4585 = bits(_WIRE_341, 19, 19)
connect _WIRE_340.ae_ptw, _T_4585
node _T_4586 = bits(_WIRE_341, 20, 20)
connect _WIRE_340.g, _T_4586
node _T_4587 = bits(_WIRE_341, 21, 21)
connect _WIRE_340.u, _T_4587
node _T_4588 = bits(_WIRE_341, 41, 22)
connect _WIRE_340.ppn, _T_4588
node _T_4589 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1))
when _T_4589 :
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
node _T_4590 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1))
when _T_4590 :
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
node _T_4591 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1))
when _T_4591 :
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
node _T_4592 = eq(sectored_entries[0][6].tag_v, UInt<1>(0h1))
when _T_4592 :
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
wire _WIRE_342 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_343 : UInt<42>
connect _WIRE_343, sectored_entries[0][7].data[0]
node _T_4593 = bits(_WIRE_343, 0, 0)
connect _WIRE_342.fragmented_superpage, _T_4593
node _T_4594 = bits(_WIRE_343, 1, 1)
connect _WIRE_342.c, _T_4594
node _T_4595 = bits(_WIRE_343, 2, 2)
connect _WIRE_342.eff, _T_4595
node _T_4596 = bits(_WIRE_343, 3, 3)
connect _WIRE_342.paa, _T_4596
node _T_4597 = bits(_WIRE_343, 4, 4)
connect _WIRE_342.pal, _T_4597
node _T_4598 = bits(_WIRE_343, 5, 5)
connect _WIRE_342.ppp, _T_4598
node _T_4599 = bits(_WIRE_343, 6, 6)
connect _WIRE_342.pr, _T_4599
node _T_4600 = bits(_WIRE_343, 7, 7)
connect _WIRE_342.px, _T_4600
node _T_4601 = bits(_WIRE_343, 8, 8)
connect _WIRE_342.pw, _T_4601
node _T_4602 = bits(_WIRE_343, 9, 9)
connect _WIRE_342.hr, _T_4602
node _T_4603 = bits(_WIRE_343, 10, 10)
connect _WIRE_342.hx, _T_4603
node _T_4604 = bits(_WIRE_343, 11, 11)
connect _WIRE_342.hw, _T_4604
node _T_4605 = bits(_WIRE_343, 12, 12)
connect _WIRE_342.sr, _T_4605
node _T_4606 = bits(_WIRE_343, 13, 13)
connect _WIRE_342.sx, _T_4606
node _T_4607 = bits(_WIRE_343, 14, 14)
connect _WIRE_342.sw, _T_4607
node _T_4608 = bits(_WIRE_343, 15, 15)
connect _WIRE_342.gf, _T_4608
node _T_4609 = bits(_WIRE_343, 16, 16)
connect _WIRE_342.pf, _T_4609
node _T_4610 = bits(_WIRE_343, 17, 17)
connect _WIRE_342.ae_stage2, _T_4610
node _T_4611 = bits(_WIRE_343, 18, 18)
connect _WIRE_342.ae_final, _T_4611
node _T_4612 = bits(_WIRE_343, 19, 19)
connect _WIRE_342.ae_ptw, _T_4612
node _T_4613 = bits(_WIRE_343, 20, 20)
connect _WIRE_342.g, _T_4613
node _T_4614 = bits(_WIRE_343, 21, 21)
connect _WIRE_342.u, _T_4614
node _T_4615 = bits(_WIRE_343, 41, 22)
connect _WIRE_342.ppn, _T_4615
wire _WIRE_344 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_345 : UInt<42>
connect _WIRE_345, sectored_entries[0][7].data[1]
node _T_4616 = bits(_WIRE_345, 0, 0)
connect _WIRE_344.fragmented_superpage, _T_4616
node _T_4617 = bits(_WIRE_345, 1, 1)
connect _WIRE_344.c, _T_4617
node _T_4618 = bits(_WIRE_345, 2, 2)
connect _WIRE_344.eff, _T_4618
node _T_4619 = bits(_WIRE_345, 3, 3)
connect _WIRE_344.paa, _T_4619
node _T_4620 = bits(_WIRE_345, 4, 4)
connect _WIRE_344.pal, _T_4620
node _T_4621 = bits(_WIRE_345, 5, 5)
connect _WIRE_344.ppp, _T_4621
node _T_4622 = bits(_WIRE_345, 6, 6)
connect _WIRE_344.pr, _T_4622
node _T_4623 = bits(_WIRE_345, 7, 7)
connect _WIRE_344.px, _T_4623
node _T_4624 = bits(_WIRE_345, 8, 8)
connect _WIRE_344.pw, _T_4624
node _T_4625 = bits(_WIRE_345, 9, 9)
connect _WIRE_344.hr, _T_4625
node _T_4626 = bits(_WIRE_345, 10, 10)
connect _WIRE_344.hx, _T_4626
node _T_4627 = bits(_WIRE_345, 11, 11)
connect _WIRE_344.hw, _T_4627
node _T_4628 = bits(_WIRE_345, 12, 12)
connect _WIRE_344.sr, _T_4628
node _T_4629 = bits(_WIRE_345, 13, 13)
connect _WIRE_344.sx, _T_4629
node _T_4630 = bits(_WIRE_345, 14, 14)
connect _WIRE_344.sw, _T_4630
node _T_4631 = bits(_WIRE_345, 15, 15)
connect _WIRE_344.gf, _T_4631
node _T_4632 = bits(_WIRE_345, 16, 16)
connect _WIRE_344.pf, _T_4632
node _T_4633 = bits(_WIRE_345, 17, 17)
connect _WIRE_344.ae_stage2, _T_4633
node _T_4634 = bits(_WIRE_345, 18, 18)
connect _WIRE_344.ae_final, _T_4634
node _T_4635 = bits(_WIRE_345, 19, 19)
connect _WIRE_344.ae_ptw, _T_4635
node _T_4636 = bits(_WIRE_345, 20, 20)
connect _WIRE_344.g, _T_4636
node _T_4637 = bits(_WIRE_345, 21, 21)
connect _WIRE_344.u, _T_4637
node _T_4638 = bits(_WIRE_345, 41, 22)
connect _WIRE_344.ppn, _T_4638
wire _WIRE_346 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_347 : UInt<42>
connect _WIRE_347, sectored_entries[0][7].data[2]
node _T_4639 = bits(_WIRE_347, 0, 0)
connect _WIRE_346.fragmented_superpage, _T_4639
node _T_4640 = bits(_WIRE_347, 1, 1)
connect _WIRE_346.c, _T_4640
node _T_4641 = bits(_WIRE_347, 2, 2)
connect _WIRE_346.eff, _T_4641
node _T_4642 = bits(_WIRE_347, 3, 3)
connect _WIRE_346.paa, _T_4642
node _T_4643 = bits(_WIRE_347, 4, 4)
connect _WIRE_346.pal, _T_4643
node _T_4644 = bits(_WIRE_347, 5, 5)
connect _WIRE_346.ppp, _T_4644
node _T_4645 = bits(_WIRE_347, 6, 6)
connect _WIRE_346.pr, _T_4645
node _T_4646 = bits(_WIRE_347, 7, 7)
connect _WIRE_346.px, _T_4646
node _T_4647 = bits(_WIRE_347, 8, 8)
connect _WIRE_346.pw, _T_4647
node _T_4648 = bits(_WIRE_347, 9, 9)
connect _WIRE_346.hr, _T_4648
node _T_4649 = bits(_WIRE_347, 10, 10)
connect _WIRE_346.hx, _T_4649
node _T_4650 = bits(_WIRE_347, 11, 11)
connect _WIRE_346.hw, _T_4650
node _T_4651 = bits(_WIRE_347, 12, 12)
connect _WIRE_346.sr, _T_4651
node _T_4652 = bits(_WIRE_347, 13, 13)
connect _WIRE_346.sx, _T_4652
node _T_4653 = bits(_WIRE_347, 14, 14)
connect _WIRE_346.sw, _T_4653
node _T_4654 = bits(_WIRE_347, 15, 15)
connect _WIRE_346.gf, _T_4654
node _T_4655 = bits(_WIRE_347, 16, 16)
connect _WIRE_346.pf, _T_4655
node _T_4656 = bits(_WIRE_347, 17, 17)
connect _WIRE_346.ae_stage2, _T_4656
node _T_4657 = bits(_WIRE_347, 18, 18)
connect _WIRE_346.ae_final, _T_4657
node _T_4658 = bits(_WIRE_347, 19, 19)
connect _WIRE_346.ae_ptw, _T_4658
node _T_4659 = bits(_WIRE_347, 20, 20)
connect _WIRE_346.g, _T_4659
node _T_4660 = bits(_WIRE_347, 21, 21)
connect _WIRE_346.u, _T_4660
node _T_4661 = bits(_WIRE_347, 41, 22)
connect _WIRE_346.ppn, _T_4661
wire _WIRE_348 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_349 : UInt<42>
connect _WIRE_349, sectored_entries[0][7].data[3]
node _T_4662 = bits(_WIRE_349, 0, 0)
connect _WIRE_348.fragmented_superpage, _T_4662
node _T_4663 = bits(_WIRE_349, 1, 1)
connect _WIRE_348.c, _T_4663
node _T_4664 = bits(_WIRE_349, 2, 2)
connect _WIRE_348.eff, _T_4664
node _T_4665 = bits(_WIRE_349, 3, 3)
connect _WIRE_348.paa, _T_4665
node _T_4666 = bits(_WIRE_349, 4, 4)
connect _WIRE_348.pal, _T_4666
node _T_4667 = bits(_WIRE_349, 5, 5)
connect _WIRE_348.ppp, _T_4667
node _T_4668 = bits(_WIRE_349, 6, 6)
connect _WIRE_348.pr, _T_4668
node _T_4669 = bits(_WIRE_349, 7, 7)
connect _WIRE_348.px, _T_4669
node _T_4670 = bits(_WIRE_349, 8, 8)
connect _WIRE_348.pw, _T_4670
node _T_4671 = bits(_WIRE_349, 9, 9)
connect _WIRE_348.hr, _T_4671
node _T_4672 = bits(_WIRE_349, 10, 10)
connect _WIRE_348.hx, _T_4672
node _T_4673 = bits(_WIRE_349, 11, 11)
connect _WIRE_348.hw, _T_4673
node _T_4674 = bits(_WIRE_349, 12, 12)
connect _WIRE_348.sr, _T_4674
node _T_4675 = bits(_WIRE_349, 13, 13)
connect _WIRE_348.sx, _T_4675
node _T_4676 = bits(_WIRE_349, 14, 14)
connect _WIRE_348.sw, _T_4676
node _T_4677 = bits(_WIRE_349, 15, 15)
connect _WIRE_348.gf, _T_4677
node _T_4678 = bits(_WIRE_349, 16, 16)
connect _WIRE_348.pf, _T_4678
node _T_4679 = bits(_WIRE_349, 17, 17)
connect _WIRE_348.ae_stage2, _T_4679
node _T_4680 = bits(_WIRE_349, 18, 18)
connect _WIRE_348.ae_final, _T_4680
node _T_4681 = bits(_WIRE_349, 19, 19)
connect _WIRE_348.ae_ptw, _T_4681
node _T_4682 = bits(_WIRE_349, 20, 20)
connect _WIRE_348.g, _T_4682
node _T_4683 = bits(_WIRE_349, 21, 21)
connect _WIRE_348.u, _T_4683
node _T_4684 = bits(_WIRE_349, 41, 22)
connect _WIRE_348.ppn, _T_4684
node _T_4685 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1))
when _T_4685 :
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
node _T_4686 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1))
when _T_4686 :
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
node _T_4687 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1))
when _T_4687 :
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
node _T_4688 = eq(sectored_entries[0][7].tag_v, UInt<1>(0h1))
when _T_4688 :
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
wire _WIRE_350 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_351 : UInt<42>
connect _WIRE_351, superpage_entries[0].data[0]
node _T_4689 = bits(_WIRE_351, 0, 0)
connect _WIRE_350.fragmented_superpage, _T_4689
node _T_4690 = bits(_WIRE_351, 1, 1)
connect _WIRE_350.c, _T_4690
node _T_4691 = bits(_WIRE_351, 2, 2)
connect _WIRE_350.eff, _T_4691
node _T_4692 = bits(_WIRE_351, 3, 3)
connect _WIRE_350.paa, _T_4692
node _T_4693 = bits(_WIRE_351, 4, 4)
connect _WIRE_350.pal, _T_4693
node _T_4694 = bits(_WIRE_351, 5, 5)
connect _WIRE_350.ppp, _T_4694
node _T_4695 = bits(_WIRE_351, 6, 6)
connect _WIRE_350.pr, _T_4695
node _T_4696 = bits(_WIRE_351, 7, 7)
connect _WIRE_350.px, _T_4696
node _T_4697 = bits(_WIRE_351, 8, 8)
connect _WIRE_350.pw, _T_4697
node _T_4698 = bits(_WIRE_351, 9, 9)
connect _WIRE_350.hr, _T_4698
node _T_4699 = bits(_WIRE_351, 10, 10)
connect _WIRE_350.hx, _T_4699
node _T_4700 = bits(_WIRE_351, 11, 11)
connect _WIRE_350.hw, _T_4700
node _T_4701 = bits(_WIRE_351, 12, 12)
connect _WIRE_350.sr, _T_4701
node _T_4702 = bits(_WIRE_351, 13, 13)
connect _WIRE_350.sx, _T_4702
node _T_4703 = bits(_WIRE_351, 14, 14)
connect _WIRE_350.sw, _T_4703
node _T_4704 = bits(_WIRE_351, 15, 15)
connect _WIRE_350.gf, _T_4704
node _T_4705 = bits(_WIRE_351, 16, 16)
connect _WIRE_350.pf, _T_4705
node _T_4706 = bits(_WIRE_351, 17, 17)
connect _WIRE_350.ae_stage2, _T_4706
node _T_4707 = bits(_WIRE_351, 18, 18)
connect _WIRE_350.ae_final, _T_4707
node _T_4708 = bits(_WIRE_351, 19, 19)
connect _WIRE_350.ae_ptw, _T_4708
node _T_4709 = bits(_WIRE_351, 20, 20)
connect _WIRE_350.g, _T_4709
node _T_4710 = bits(_WIRE_351, 21, 21)
connect _WIRE_350.u, _T_4710
node _T_4711 = bits(_WIRE_351, 41, 22)
connect _WIRE_350.ppn, _T_4711
node _T_4712 = eq(superpage_entries[0].tag_v, UInt<1>(0h1))
when _T_4712 :
connect superpage_entries[0].valid[0], UInt<1>(0h0)
wire _WIRE_352 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_353 : UInt<42>
connect _WIRE_353, superpage_entries[1].data[0]
node _T_4713 = bits(_WIRE_353, 0, 0)
connect _WIRE_352.fragmented_superpage, _T_4713
node _T_4714 = bits(_WIRE_353, 1, 1)
connect _WIRE_352.c, _T_4714
node _T_4715 = bits(_WIRE_353, 2, 2)
connect _WIRE_352.eff, _T_4715
node _T_4716 = bits(_WIRE_353, 3, 3)
connect _WIRE_352.paa, _T_4716
node _T_4717 = bits(_WIRE_353, 4, 4)
connect _WIRE_352.pal, _T_4717
node _T_4718 = bits(_WIRE_353, 5, 5)
connect _WIRE_352.ppp, _T_4718
node _T_4719 = bits(_WIRE_353, 6, 6)
connect _WIRE_352.pr, _T_4719
node _T_4720 = bits(_WIRE_353, 7, 7)
connect _WIRE_352.px, _T_4720
node _T_4721 = bits(_WIRE_353, 8, 8)
connect _WIRE_352.pw, _T_4721
node _T_4722 = bits(_WIRE_353, 9, 9)
connect _WIRE_352.hr, _T_4722
node _T_4723 = bits(_WIRE_353, 10, 10)
connect _WIRE_352.hx, _T_4723
node _T_4724 = bits(_WIRE_353, 11, 11)
connect _WIRE_352.hw, _T_4724
node _T_4725 = bits(_WIRE_353, 12, 12)
connect _WIRE_352.sr, _T_4725
node _T_4726 = bits(_WIRE_353, 13, 13)
connect _WIRE_352.sx, _T_4726
node _T_4727 = bits(_WIRE_353, 14, 14)
connect _WIRE_352.sw, _T_4727
node _T_4728 = bits(_WIRE_353, 15, 15)
connect _WIRE_352.gf, _T_4728
node _T_4729 = bits(_WIRE_353, 16, 16)
connect _WIRE_352.pf, _T_4729
node _T_4730 = bits(_WIRE_353, 17, 17)
connect _WIRE_352.ae_stage2, _T_4730
node _T_4731 = bits(_WIRE_353, 18, 18)
connect _WIRE_352.ae_final, _T_4731
node _T_4732 = bits(_WIRE_353, 19, 19)
connect _WIRE_352.ae_ptw, _T_4732
node _T_4733 = bits(_WIRE_353, 20, 20)
connect _WIRE_352.g, _T_4733
node _T_4734 = bits(_WIRE_353, 21, 21)
connect _WIRE_352.u, _T_4734
node _T_4735 = bits(_WIRE_353, 41, 22)
connect _WIRE_352.ppn, _T_4735
node _T_4736 = eq(superpage_entries[1].tag_v, UInt<1>(0h1))
when _T_4736 :
connect superpage_entries[1].valid[0], UInt<1>(0h0)
wire _WIRE_354 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_355 : UInt<42>
connect _WIRE_355, superpage_entries[2].data[0]
node _T_4737 = bits(_WIRE_355, 0, 0)
connect _WIRE_354.fragmented_superpage, _T_4737
node _T_4738 = bits(_WIRE_355, 1, 1)
connect _WIRE_354.c, _T_4738
node _T_4739 = bits(_WIRE_355, 2, 2)
connect _WIRE_354.eff, _T_4739
node _T_4740 = bits(_WIRE_355, 3, 3)
connect _WIRE_354.paa, _T_4740
node _T_4741 = bits(_WIRE_355, 4, 4)
connect _WIRE_354.pal, _T_4741
node _T_4742 = bits(_WIRE_355, 5, 5)
connect _WIRE_354.ppp, _T_4742
node _T_4743 = bits(_WIRE_355, 6, 6)
connect _WIRE_354.pr, _T_4743
node _T_4744 = bits(_WIRE_355, 7, 7)
connect _WIRE_354.px, _T_4744
node _T_4745 = bits(_WIRE_355, 8, 8)
connect _WIRE_354.pw, _T_4745
node _T_4746 = bits(_WIRE_355, 9, 9)
connect _WIRE_354.hr, _T_4746
node _T_4747 = bits(_WIRE_355, 10, 10)
connect _WIRE_354.hx, _T_4747
node _T_4748 = bits(_WIRE_355, 11, 11)
connect _WIRE_354.hw, _T_4748
node _T_4749 = bits(_WIRE_355, 12, 12)
connect _WIRE_354.sr, _T_4749
node _T_4750 = bits(_WIRE_355, 13, 13)
connect _WIRE_354.sx, _T_4750
node _T_4751 = bits(_WIRE_355, 14, 14)
connect _WIRE_354.sw, _T_4751
node _T_4752 = bits(_WIRE_355, 15, 15)
connect _WIRE_354.gf, _T_4752
node _T_4753 = bits(_WIRE_355, 16, 16)
connect _WIRE_354.pf, _T_4753
node _T_4754 = bits(_WIRE_355, 17, 17)
connect _WIRE_354.ae_stage2, _T_4754
node _T_4755 = bits(_WIRE_355, 18, 18)
connect _WIRE_354.ae_final, _T_4755
node _T_4756 = bits(_WIRE_355, 19, 19)
connect _WIRE_354.ae_ptw, _T_4756
node _T_4757 = bits(_WIRE_355, 20, 20)
connect _WIRE_354.g, _T_4757
node _T_4758 = bits(_WIRE_355, 21, 21)
connect _WIRE_354.u, _T_4758
node _T_4759 = bits(_WIRE_355, 41, 22)
connect _WIRE_354.ppn, _T_4759
node _T_4760 = eq(superpage_entries[2].tag_v, UInt<1>(0h1))
when _T_4760 :
connect superpage_entries[2].valid[0], UInt<1>(0h0)
wire _WIRE_356 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_357 : UInt<42>
connect _WIRE_357, superpage_entries[3].data[0]
node _T_4761 = bits(_WIRE_357, 0, 0)
connect _WIRE_356.fragmented_superpage, _T_4761
node _T_4762 = bits(_WIRE_357, 1, 1)
connect _WIRE_356.c, _T_4762
node _T_4763 = bits(_WIRE_357, 2, 2)
connect _WIRE_356.eff, _T_4763
node _T_4764 = bits(_WIRE_357, 3, 3)
connect _WIRE_356.paa, _T_4764
node _T_4765 = bits(_WIRE_357, 4, 4)
connect _WIRE_356.pal, _T_4765
node _T_4766 = bits(_WIRE_357, 5, 5)
connect _WIRE_356.ppp, _T_4766
node _T_4767 = bits(_WIRE_357, 6, 6)
connect _WIRE_356.pr, _T_4767
node _T_4768 = bits(_WIRE_357, 7, 7)
connect _WIRE_356.px, _T_4768
node _T_4769 = bits(_WIRE_357, 8, 8)
connect _WIRE_356.pw, _T_4769
node _T_4770 = bits(_WIRE_357, 9, 9)
connect _WIRE_356.hr, _T_4770
node _T_4771 = bits(_WIRE_357, 10, 10)
connect _WIRE_356.hx, _T_4771
node _T_4772 = bits(_WIRE_357, 11, 11)
connect _WIRE_356.hw, _T_4772
node _T_4773 = bits(_WIRE_357, 12, 12)
connect _WIRE_356.sr, _T_4773
node _T_4774 = bits(_WIRE_357, 13, 13)
connect _WIRE_356.sx, _T_4774
node _T_4775 = bits(_WIRE_357, 14, 14)
connect _WIRE_356.sw, _T_4775
node _T_4776 = bits(_WIRE_357, 15, 15)
connect _WIRE_356.gf, _T_4776
node _T_4777 = bits(_WIRE_357, 16, 16)
connect _WIRE_356.pf, _T_4777
node _T_4778 = bits(_WIRE_357, 17, 17)
connect _WIRE_356.ae_stage2, _T_4778
node _T_4779 = bits(_WIRE_357, 18, 18)
connect _WIRE_356.ae_final, _T_4779
node _T_4780 = bits(_WIRE_357, 19, 19)
connect _WIRE_356.ae_ptw, _T_4780
node _T_4781 = bits(_WIRE_357, 20, 20)
connect _WIRE_356.g, _T_4781
node _T_4782 = bits(_WIRE_357, 21, 21)
connect _WIRE_356.u, _T_4782
node _T_4783 = bits(_WIRE_357, 41, 22)
connect _WIRE_356.ppn, _T_4783
node _T_4784 = eq(superpage_entries[3].tag_v, UInt<1>(0h1))
when _T_4784 :
connect superpage_entries[3].valid[0], UInt<1>(0h0)
wire _WIRE_358 : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}
wire _WIRE_359 : UInt<42>
connect _WIRE_359, special_entry.data[0]
node _T_4785 = bits(_WIRE_359, 0, 0)
connect _WIRE_358.fragmented_superpage, _T_4785
node _T_4786 = bits(_WIRE_359, 1, 1)
connect _WIRE_358.c, _T_4786
node _T_4787 = bits(_WIRE_359, 2, 2)
connect _WIRE_358.eff, _T_4787
node _T_4788 = bits(_WIRE_359, 3, 3)
connect _WIRE_358.paa, _T_4788
node _T_4789 = bits(_WIRE_359, 4, 4)
connect _WIRE_358.pal, _T_4789
node _T_4790 = bits(_WIRE_359, 5, 5)
connect _WIRE_358.ppp, _T_4790
node _T_4791 = bits(_WIRE_359, 6, 6)
connect _WIRE_358.pr, _T_4791
node _T_4792 = bits(_WIRE_359, 7, 7)
connect _WIRE_358.px, _T_4792
node _T_4793 = bits(_WIRE_359, 8, 8)
connect _WIRE_358.pw, _T_4793
node _T_4794 = bits(_WIRE_359, 9, 9)
connect _WIRE_358.hr, _T_4794
node _T_4795 = bits(_WIRE_359, 10, 10)
connect _WIRE_358.hx, _T_4795
node _T_4796 = bits(_WIRE_359, 11, 11)
connect _WIRE_358.hw, _T_4796
node _T_4797 = bits(_WIRE_359, 12, 12)
connect _WIRE_358.sr, _T_4797
node _T_4798 = bits(_WIRE_359, 13, 13)
connect _WIRE_358.sx, _T_4798
node _T_4799 = bits(_WIRE_359, 14, 14)
connect _WIRE_358.sw, _T_4799
node _T_4800 = bits(_WIRE_359, 15, 15)
connect _WIRE_358.gf, _T_4800
node _T_4801 = bits(_WIRE_359, 16, 16)
connect _WIRE_358.pf, _T_4801
node _T_4802 = bits(_WIRE_359, 17, 17)
connect _WIRE_358.ae_stage2, _T_4802
node _T_4803 = bits(_WIRE_359, 18, 18)
connect _WIRE_358.ae_final, _T_4803
node _T_4804 = bits(_WIRE_359, 19, 19)
connect _WIRE_358.ae_ptw, _T_4804
node _T_4805 = bits(_WIRE_359, 20, 20)
connect _WIRE_358.g, _T_4805
node _T_4806 = bits(_WIRE_359, 21, 21)
connect _WIRE_358.u, _T_4806
node _T_4807 = bits(_WIRE_359, 41, 22)
connect _WIRE_358.ppn, _T_4807
node _T_4808 = eq(special_entry.tag_v, UInt<1>(0h1))
when _T_4808 :
connect special_entry.valid[0], UInt<1>(0h0)
connect v_entries_use_stage1, vstage1_en
node _T_4809 = asUInt(reset)
node _T_4810 = or(multipleHits, _T_4809)
when _T_4810 :
connect sectored_entries[0][0].valid[0], UInt<1>(0h0)
connect sectored_entries[0][0].valid[1], UInt<1>(0h0)
connect sectored_entries[0][0].valid[2], UInt<1>(0h0)
connect sectored_entries[0][0].valid[3], UInt<1>(0h0)
connect sectored_entries[0][1].valid[0], UInt<1>(0h0)
connect sectored_entries[0][1].valid[1], UInt<1>(0h0)
connect sectored_entries[0][1].valid[2], UInt<1>(0h0)
connect sectored_entries[0][1].valid[3], UInt<1>(0h0)
connect sectored_entries[0][2].valid[0], UInt<1>(0h0)
connect sectored_entries[0][2].valid[1], UInt<1>(0h0)
connect sectored_entries[0][2].valid[2], UInt<1>(0h0)
connect sectored_entries[0][2].valid[3], UInt<1>(0h0)
connect sectored_entries[0][3].valid[0], UInt<1>(0h0)
connect sectored_entries[0][3].valid[1], UInt<1>(0h0)
connect sectored_entries[0][3].valid[2], UInt<1>(0h0)
connect sectored_entries[0][3].valid[3], UInt<1>(0h0)
connect sectored_entries[0][4].valid[0], UInt<1>(0h0)
connect sectored_entries[0][4].valid[1], UInt<1>(0h0)
connect sectored_entries[0][4].valid[2], UInt<1>(0h0)
connect sectored_entries[0][4].valid[3], UInt<1>(0h0)
connect sectored_entries[0][5].valid[0], UInt<1>(0h0)
connect sectored_entries[0][5].valid[1], UInt<1>(0h0)
connect sectored_entries[0][5].valid[2], UInt<1>(0h0)
connect sectored_entries[0][5].valid[3], UInt<1>(0h0)
connect sectored_entries[0][6].valid[0], UInt<1>(0h0)
connect sectored_entries[0][6].valid[1], UInt<1>(0h0)
connect sectored_entries[0][6].valid[2], UInt<1>(0h0)
connect sectored_entries[0][6].valid[3], UInt<1>(0h0)
connect sectored_entries[0][7].valid[0], UInt<1>(0h0)
connect sectored_entries[0][7].valid[1], UInt<1>(0h0)
connect sectored_entries[0][7].valid[2], UInt<1>(0h0)
connect sectored_entries[0][7].valid[3], UInt<1>(0h0)
connect superpage_entries[0].valid[0], UInt<1>(0h0)
connect superpage_entries[1].valid[0], UInt<1>(0h0)
connect superpage_entries[2].valid[0], UInt<1>(0h0)
connect superpage_entries[3].valid[0], UInt<1>(0h0)
connect special_entry.valid[0], UInt<1>(0h0)
node _T_4811 = and(io.ptw.req.ready, io.ptw.req.valid)
node _T_4812 = eq(io.ptw.req.ready, UInt<1>(0h0))
node _T_4813 = and(io.ptw.req.valid, _T_4812)
node _T_4814 = eq(state, UInt<2>(0h3))
node _T_4815 = eq(io.sfence.bits.rs1, UInt<1>(0h0))
node _T_4816 = and(io.sfence.valid, _T_4815)
node _T_4817 = eq(io.sfence.bits.rs2, UInt<1>(0h0))
node _T_4818 = and(_T_4816, _T_4817)
node _T_4819 = eq(io.sfence.bits.rs1, UInt<1>(0h0))
node _T_4820 = and(io.sfence.valid, _T_4819)
node _T_4821 = and(_T_4820, io.sfence.bits.rs2)
node _T_4822 = and(io.sfence.valid, io.sfence.bits.rs1)
node _T_4823 = eq(io.sfence.bits.rs2, UInt<1>(0h0))
node _T_4824 = and(_T_4822, _T_4823)
node _T_4825 = and(io.sfence.valid, io.sfence.bits.rs1)
node _T_4826 = and(_T_4825, io.sfence.bits.rs2) | module ITLB( // @[TLB.scala:318:7]
input clock, // @[TLB.scala:318:7]
input reset, // @[TLB.scala:318:7]
input io_req_valid, // @[TLB.scala:320:14]
input [39:0] io_req_bits_vaddr, // @[TLB.scala:320:14]
input [1:0] io_req_bits_prv, // @[TLB.scala:320:14]
input io_req_bits_v, // @[TLB.scala:320:14]
output io_resp_miss, // @[TLB.scala:320:14]
output [31:0] io_resp_paddr, // @[TLB.scala:320:14]
output [39:0] io_resp_gpa, // @[TLB.scala:320:14]
output io_resp_pf_ld, // @[TLB.scala:320:14]
output io_resp_pf_inst, // @[TLB.scala:320:14]
output io_resp_ae_ld, // @[TLB.scala:320:14]
output io_resp_ae_inst, // @[TLB.scala:320:14]
output io_resp_ma_ld, // @[TLB.scala:320:14]
output io_resp_cacheable, // @[TLB.scala:320:14]
output io_resp_prefetchable, // @[TLB.scala:320:14]
input io_sfence_valid, // @[TLB.scala:320:14]
input io_sfence_bits_rs1, // @[TLB.scala:320:14]
input io_sfence_bits_rs2, // @[TLB.scala:320:14]
input [38:0] io_sfence_bits_addr, // @[TLB.scala:320:14]
input io_sfence_bits_asid, // @[TLB.scala:320:14]
input io_sfence_bits_hv, // @[TLB.scala:320:14]
input io_sfence_bits_hg, // @[TLB.scala:320:14]
input io_ptw_req_ready, // @[TLB.scala:320:14]
output io_ptw_req_valid, // @[TLB.scala:320:14]
output [26:0] io_ptw_req_bits_bits_addr, // @[TLB.scala:320:14]
output io_ptw_req_bits_bits_need_gpa, // @[TLB.scala:320:14]
input io_ptw_resp_valid, // @[TLB.scala:320:14]
input io_ptw_resp_bits_ae_ptw, // @[TLB.scala:320:14]
input io_ptw_resp_bits_ae_final, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pf, // @[TLB.scala:320:14]
input io_ptw_resp_bits_gf, // @[TLB.scala:320:14]
input io_ptw_resp_bits_hr, // @[TLB.scala:320:14]
input io_ptw_resp_bits_hw, // @[TLB.scala:320:14]
input io_ptw_resp_bits_hx, // @[TLB.scala:320:14]
input [9:0] io_ptw_resp_bits_pte_reserved_for_future, // @[TLB.scala:320:14]
input [43:0] io_ptw_resp_bits_pte_ppn, // @[TLB.scala:320:14]
input [1:0] io_ptw_resp_bits_pte_reserved_for_software, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_d, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_a, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_g, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_u, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_x, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_w, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_r, // @[TLB.scala:320:14]
input io_ptw_resp_bits_pte_v, // @[TLB.scala:320:14]
input [1:0] io_ptw_resp_bits_level, // @[TLB.scala:320:14]
input io_ptw_resp_bits_homogeneous, // @[TLB.scala:320:14]
input io_ptw_resp_bits_gpa_valid, // @[TLB.scala:320:14]
input [38:0] io_ptw_resp_bits_gpa_bits, // @[TLB.scala:320:14]
input io_ptw_resp_bits_gpa_is_pte, // @[TLB.scala:320:14]
input [3:0] io_ptw_ptbr_mode, // @[TLB.scala:320:14]
input [43:0] io_ptw_ptbr_ppn, // @[TLB.scala:320:14]
input io_ptw_status_debug, // @[TLB.scala:320:14]
input io_ptw_status_cease, // @[TLB.scala:320:14]
input io_ptw_status_wfi, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_dprv, // @[TLB.scala:320:14]
input io_ptw_status_dv, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_prv, // @[TLB.scala:320:14]
input io_ptw_status_v, // @[TLB.scala:320:14]
input io_ptw_status_sd, // @[TLB.scala:320:14]
input io_ptw_status_mpv, // @[TLB.scala:320:14]
input io_ptw_status_gva, // @[TLB.scala:320:14]
input io_ptw_status_tsr, // @[TLB.scala:320:14]
input io_ptw_status_tw, // @[TLB.scala:320:14]
input io_ptw_status_tvm, // @[TLB.scala:320:14]
input io_ptw_status_mxr, // @[TLB.scala:320:14]
input io_ptw_status_sum, // @[TLB.scala:320:14]
input io_ptw_status_mprv, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_fs, // @[TLB.scala:320:14]
input [1:0] io_ptw_status_mpp, // @[TLB.scala:320:14]
input io_ptw_status_spp, // @[TLB.scala:320:14]
input io_ptw_status_mpie, // @[TLB.scala:320:14]
input io_ptw_status_spie, // @[TLB.scala:320:14]
input io_ptw_status_mie, // @[TLB.scala:320:14]
input io_ptw_status_sie, // @[TLB.scala:320:14]
input io_ptw_pmp_0_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_0_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_0_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_0_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_0_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_0_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_0_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_1_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_1_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_1_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_1_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_1_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_1_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_1_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_2_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_2_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_2_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_2_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_2_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_2_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_2_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_3_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_3_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_3_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_3_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_3_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_3_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_3_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_4_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_4_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_4_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_4_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_4_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_4_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_4_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_5_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_5_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_5_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_5_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_5_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_5_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_5_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_6_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_6_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_6_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_6_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_6_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_6_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_6_mask, // @[TLB.scala:320:14]
input io_ptw_pmp_7_cfg_l, // @[TLB.scala:320:14]
input [1:0] io_ptw_pmp_7_cfg_a, // @[TLB.scala:320:14]
input io_ptw_pmp_7_cfg_x, // @[TLB.scala:320:14]
input io_ptw_pmp_7_cfg_w, // @[TLB.scala:320:14]
input io_ptw_pmp_7_cfg_r, // @[TLB.scala:320:14]
input [29:0] io_ptw_pmp_7_addr, // @[TLB.scala:320:14]
input [31:0] io_ptw_pmp_7_mask // @[TLB.scala:320:14]
);
wire [19:0] _entries_barrier_12_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_12_io_y_hr; // @[package.scala:267:25]
wire [19:0] _entries_barrier_11_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_11_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_10_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_10_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_9_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_9_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_8_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_8_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_7_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_7_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_6_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_6_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_5_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_5_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_4_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_4_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_3_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_3_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_2_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_2_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_1_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_1_io_y_c; // @[package.scala:267:25]
wire [19:0] _entries_barrier_io_y_ppn; // @[package.scala:267:25]
wire _entries_barrier_io_y_u; // @[package.scala:267:25]
wire _entries_barrier_io_y_ae_ptw; // @[package.scala:267:25]
wire _entries_barrier_io_y_ae_final; // @[package.scala:267:25]
wire _entries_barrier_io_y_ae_stage2; // @[package.scala:267:25]
wire _entries_barrier_io_y_pf; // @[package.scala:267:25]
wire _entries_barrier_io_y_gf; // @[package.scala:267:25]
wire _entries_barrier_io_y_sw; // @[package.scala:267:25]
wire _entries_barrier_io_y_sx; // @[package.scala:267:25]
wire _entries_barrier_io_y_sr; // @[package.scala:267:25]
wire _entries_barrier_io_y_hw; // @[package.scala:267:25]
wire _entries_barrier_io_y_hx; // @[package.scala:267:25]
wire _entries_barrier_io_y_hr; // @[package.scala:267:25]
wire _entries_barrier_io_y_pw; // @[package.scala:267:25]
wire _entries_barrier_io_y_px; // @[package.scala:267:25]
wire _entries_barrier_io_y_pr; // @[package.scala:267:25]
wire _entries_barrier_io_y_ppp; // @[package.scala:267:25]
wire _entries_barrier_io_y_pal; // @[package.scala:267:25]
wire _entries_barrier_io_y_paa; // @[package.scala:267:25]
wire _entries_barrier_io_y_eff; // @[package.scala:267:25]
wire _entries_barrier_io_y_c; // @[package.scala:267:25]
wire _pma_io_resp_r; // @[TLB.scala:422:19]
wire _pma_io_resp_w; // @[TLB.scala:422:19]
wire _pma_io_resp_pp; // @[TLB.scala:422:19]
wire _pma_io_resp_al; // @[TLB.scala:422:19]
wire _pma_io_resp_aa; // @[TLB.scala:422:19]
wire _pma_io_resp_x; // @[TLB.scala:422:19]
wire _pma_io_resp_eff; // @[TLB.scala:422:19]
wire _pmp_io_r; // @[TLB.scala:416:19]
wire _pmp_io_w; // @[TLB.scala:416:19]
wire _pmp_io_x; // @[TLB.scala:416:19]
wire [19:0] _mpu_ppn_barrier_io_y_ppn; // @[package.scala:267:25]
wire io_req_valid_0 = io_req_valid; // @[TLB.scala:318:7]
wire [39:0] io_req_bits_vaddr_0 = io_req_bits_vaddr; // @[TLB.scala:318:7]
wire [1:0] io_req_bits_prv_0 = io_req_bits_prv; // @[TLB.scala:318:7]
wire io_req_bits_v_0 = io_req_bits_v; // @[TLB.scala:318:7]
wire io_sfence_valid_0 = io_sfence_valid; // @[TLB.scala:318:7]
wire io_sfence_bits_rs1_0 = io_sfence_bits_rs1; // @[TLB.scala:318:7]
wire io_sfence_bits_rs2_0 = io_sfence_bits_rs2; // @[TLB.scala:318:7]
wire [38:0] io_sfence_bits_addr_0 = io_sfence_bits_addr; // @[TLB.scala:318:7]
wire io_sfence_bits_asid_0 = io_sfence_bits_asid; // @[TLB.scala:318:7]
wire io_sfence_bits_hv_0 = io_sfence_bits_hv; // @[TLB.scala:318:7]
wire io_sfence_bits_hg_0 = io_sfence_bits_hg; // @[TLB.scala:318:7]
wire io_ptw_req_ready_0 = io_ptw_req_ready; // @[TLB.scala:318:7]
wire io_ptw_resp_valid_0 = io_ptw_resp_valid; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_ae_ptw_0 = io_ptw_resp_bits_ae_ptw; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_ae_final_0 = io_ptw_resp_bits_ae_final; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pf_0 = io_ptw_resp_bits_pf; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_gf_0 = io_ptw_resp_bits_gf; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_hr_0 = io_ptw_resp_bits_hr; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_hw_0 = io_ptw_resp_bits_hw; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_hx_0 = io_ptw_resp_bits_hx; // @[TLB.scala:318:7]
wire [9:0] io_ptw_resp_bits_pte_reserved_for_future_0 = io_ptw_resp_bits_pte_reserved_for_future; // @[TLB.scala:318:7]
wire [43:0] io_ptw_resp_bits_pte_ppn_0 = io_ptw_resp_bits_pte_ppn; // @[TLB.scala:318:7]
wire [1:0] io_ptw_resp_bits_pte_reserved_for_software_0 = io_ptw_resp_bits_pte_reserved_for_software; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_d_0 = io_ptw_resp_bits_pte_d; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_a_0 = io_ptw_resp_bits_pte_a; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_g_0 = io_ptw_resp_bits_pte_g; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_u_0 = io_ptw_resp_bits_pte_u; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_x_0 = io_ptw_resp_bits_pte_x; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_w_0 = io_ptw_resp_bits_pte_w; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_r_0 = io_ptw_resp_bits_pte_r; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_pte_v_0 = io_ptw_resp_bits_pte_v; // @[TLB.scala:318:7]
wire [1:0] io_ptw_resp_bits_level_0 = io_ptw_resp_bits_level; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_homogeneous_0 = io_ptw_resp_bits_homogeneous; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_gpa_valid_0 = io_ptw_resp_bits_gpa_valid; // @[TLB.scala:318:7]
wire [38:0] io_ptw_resp_bits_gpa_bits_0 = io_ptw_resp_bits_gpa_bits; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_gpa_is_pte_0 = io_ptw_resp_bits_gpa_is_pte; // @[TLB.scala:318:7]
wire [3:0] io_ptw_ptbr_mode_0 = io_ptw_ptbr_mode; // @[TLB.scala:318:7]
wire [43:0] io_ptw_ptbr_ppn_0 = io_ptw_ptbr_ppn; // @[TLB.scala:318:7]
wire io_ptw_status_debug_0 = io_ptw_status_debug; // @[TLB.scala:318:7]
wire io_ptw_status_cease_0 = io_ptw_status_cease; // @[TLB.scala:318:7]
wire io_ptw_status_wfi_0 = io_ptw_status_wfi; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_dprv_0 = io_ptw_status_dprv; // @[TLB.scala:318:7]
wire io_ptw_status_dv_0 = io_ptw_status_dv; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_prv_0 = io_ptw_status_prv; // @[TLB.scala:318:7]
wire io_ptw_status_v_0 = io_ptw_status_v; // @[TLB.scala:318:7]
wire io_ptw_status_sd_0 = io_ptw_status_sd; // @[TLB.scala:318:7]
wire io_ptw_status_mpv_0 = io_ptw_status_mpv; // @[TLB.scala:318:7]
wire io_ptw_status_gva_0 = io_ptw_status_gva; // @[TLB.scala:318:7]
wire io_ptw_status_tsr_0 = io_ptw_status_tsr; // @[TLB.scala:318:7]
wire io_ptw_status_tw_0 = io_ptw_status_tw; // @[TLB.scala:318:7]
wire io_ptw_status_tvm_0 = io_ptw_status_tvm; // @[TLB.scala:318:7]
wire io_ptw_status_mxr_0 = io_ptw_status_mxr; // @[TLB.scala:318:7]
wire io_ptw_status_sum_0 = io_ptw_status_sum; // @[TLB.scala:318:7]
wire io_ptw_status_mprv_0 = io_ptw_status_mprv; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_fs_0 = io_ptw_status_fs; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_mpp_0 = io_ptw_status_mpp; // @[TLB.scala:318:7]
wire io_ptw_status_spp_0 = io_ptw_status_spp; // @[TLB.scala:318:7]
wire io_ptw_status_mpie_0 = io_ptw_status_mpie; // @[TLB.scala:318:7]
wire io_ptw_status_spie_0 = io_ptw_status_spie; // @[TLB.scala:318:7]
wire io_ptw_status_mie_0 = io_ptw_status_mie; // @[TLB.scala:318:7]
wire io_ptw_status_sie_0 = io_ptw_status_sie; // @[TLB.scala:318:7]
wire io_ptw_pmp_0_cfg_l_0 = io_ptw_pmp_0_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_0_cfg_a_0 = io_ptw_pmp_0_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_0_cfg_x_0 = io_ptw_pmp_0_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_0_cfg_w_0 = io_ptw_pmp_0_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_0_cfg_r_0 = io_ptw_pmp_0_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_0_addr_0 = io_ptw_pmp_0_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_0_mask_0 = io_ptw_pmp_0_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_1_cfg_l_0 = io_ptw_pmp_1_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_1_cfg_a_0 = io_ptw_pmp_1_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_1_cfg_x_0 = io_ptw_pmp_1_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_1_cfg_w_0 = io_ptw_pmp_1_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_1_cfg_r_0 = io_ptw_pmp_1_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_1_addr_0 = io_ptw_pmp_1_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_1_mask_0 = io_ptw_pmp_1_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_2_cfg_l_0 = io_ptw_pmp_2_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_2_cfg_a_0 = io_ptw_pmp_2_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_2_cfg_x_0 = io_ptw_pmp_2_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_2_cfg_w_0 = io_ptw_pmp_2_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_2_cfg_r_0 = io_ptw_pmp_2_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_2_addr_0 = io_ptw_pmp_2_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_2_mask_0 = io_ptw_pmp_2_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_3_cfg_l_0 = io_ptw_pmp_3_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_3_cfg_a_0 = io_ptw_pmp_3_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_3_cfg_x_0 = io_ptw_pmp_3_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_3_cfg_w_0 = io_ptw_pmp_3_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_3_cfg_r_0 = io_ptw_pmp_3_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_3_addr_0 = io_ptw_pmp_3_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_3_mask_0 = io_ptw_pmp_3_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_4_cfg_l_0 = io_ptw_pmp_4_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_4_cfg_a_0 = io_ptw_pmp_4_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_4_cfg_x_0 = io_ptw_pmp_4_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_4_cfg_w_0 = io_ptw_pmp_4_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_4_cfg_r_0 = io_ptw_pmp_4_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_4_addr_0 = io_ptw_pmp_4_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_4_mask_0 = io_ptw_pmp_4_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_5_cfg_l_0 = io_ptw_pmp_5_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_5_cfg_a_0 = io_ptw_pmp_5_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_5_cfg_x_0 = io_ptw_pmp_5_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_5_cfg_w_0 = io_ptw_pmp_5_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_5_cfg_r_0 = io_ptw_pmp_5_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_5_addr_0 = io_ptw_pmp_5_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_5_mask_0 = io_ptw_pmp_5_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_6_cfg_l_0 = io_ptw_pmp_6_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_6_cfg_a_0 = io_ptw_pmp_6_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_6_cfg_x_0 = io_ptw_pmp_6_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_6_cfg_w_0 = io_ptw_pmp_6_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_6_cfg_r_0 = io_ptw_pmp_6_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_6_addr_0 = io_ptw_pmp_6_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_6_mask_0 = io_ptw_pmp_6_mask; // @[TLB.scala:318:7]
wire io_ptw_pmp_7_cfg_l_0 = io_ptw_pmp_7_cfg_l; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_7_cfg_a_0 = io_ptw_pmp_7_cfg_a; // @[TLB.scala:318:7]
wire io_ptw_pmp_7_cfg_x_0 = io_ptw_pmp_7_cfg_x; // @[TLB.scala:318:7]
wire io_ptw_pmp_7_cfg_w_0 = io_ptw_pmp_7_cfg_w; // @[TLB.scala:318:7]
wire io_ptw_pmp_7_cfg_r_0 = io_ptw_pmp_7_cfg_r; // @[TLB.scala:318:7]
wire [29:0] io_ptw_pmp_7_addr_0 = io_ptw_pmp_7_addr; // @[TLB.scala:318:7]
wire [31:0] io_ptw_pmp_7_mask_0 = io_ptw_pmp_7_mask; // @[TLB.scala:318:7]
wire io_req_bits_passthrough = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gpa_is_pte = 1'h0; // @[TLB.scala:318:7]
wire io_resp_pf_st = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gf_ld = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gf_st = 1'h0; // @[TLB.scala:318:7]
wire io_resp_gf_inst = 1'h0; // @[TLB.scala:318:7]
wire io_resp_ae_st = 1'h0; // @[TLB.scala:318:7]
wire io_resp_ma_st = 1'h0; // @[TLB.scala:318:7]
wire io_resp_ma_inst = 1'h0; // @[TLB.scala:318:7]
wire io_resp_must_alloc = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_bits_vstage1 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_bits_stage2 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_resp_bits_fragmented_superpage = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_mbe = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_sbe = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_sd_rv32 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_ube = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_upie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_hie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_status_uie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vtsr = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vtw = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vtvm = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_hu = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_spvp = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_spv = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_gva = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_hstatus_vsbe = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_debug = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_cease = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_wfi = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_dv = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_v = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sd = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mpv = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_gva = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mbe = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sbe = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_tsr = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_tw = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_tvm = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mxr = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sum = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mprv = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_spp = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mpie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_ube = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_spie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_upie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_mie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_hie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_sie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_gstatus_uie = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[TLB.scala:318:7]
wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[TLB.scala:318:7]
wire io_kill = 1'h0; // @[TLB.scala:318:7]
wire priv_v = 1'h0; // @[TLB.scala:369:34]
wire _vstage1_en_T = 1'h0; // @[TLB.scala:376:38]
wire _vstage1_en_T_1 = 1'h0; // @[TLB.scala:376:68]
wire vstage1_en = 1'h0; // @[TLB.scala:376:48]
wire _stage2_en_T = 1'h0; // @[TLB.scala:378:38]
wire _stage2_en_T_1 = 1'h0; // @[TLB.scala:378:68]
wire stage2_en = 1'h0; // @[TLB.scala:378:48]
wire _vsatp_mode_mismatch_T = 1'h0; // @[TLB.scala:403:52]
wire _vsatp_mode_mismatch_T_1 = 1'h0; // @[TLB.scala:403:37]
wire vsatp_mode_mismatch = 1'h0; // @[TLB.scala:403:78]
wire _superpage_hits_ignore_T = 1'h0; // @[TLB.scala:182:28]
wire superpage_hits_ignore = 1'h0; // @[TLB.scala:182:34]
wire _superpage_hits_ignore_T_3 = 1'h0; // @[TLB.scala:182:28]
wire superpage_hits_ignore_3 = 1'h0; // @[TLB.scala:182:34]
wire _superpage_hits_ignore_T_6 = 1'h0; // @[TLB.scala:182:28]
wire superpage_hits_ignore_6 = 1'h0; // @[TLB.scala:182:34]
wire _superpage_hits_ignore_T_9 = 1'h0; // @[TLB.scala:182:28]
wire superpage_hits_ignore_9 = 1'h0; // @[TLB.scala:182:34]
wire _hitsVec_ignore_T = 1'h0; // @[TLB.scala:182:28]
wire hitsVec_ignore = 1'h0; // @[TLB.scala:182:34]
wire _hitsVec_ignore_T_3 = 1'h0; // @[TLB.scala:182:28]
wire hitsVec_ignore_3 = 1'h0; // @[TLB.scala:182:34]
wire _hitsVec_ignore_T_6 = 1'h0; // @[TLB.scala:182:28]
wire hitsVec_ignore_6 = 1'h0; // @[TLB.scala:182:34]
wire _hitsVec_ignore_T_9 = 1'h0; // @[TLB.scala:182:28]
wire hitsVec_ignore_9 = 1'h0; // @[TLB.scala:182:34]
wire _hitsVec_ignore_T_12 = 1'h0; // @[TLB.scala:182:28]
wire hitsVec_ignore_12 = 1'h0; // @[TLB.scala:182:34]
wire refill_v = 1'h0; // @[TLB.scala:448:33]
wire newEntry_ae_stage2 = 1'h0; // @[TLB.scala:449:24]
wire newEntry_fragmented_superpage = 1'h0; // @[TLB.scala:449:24]
wire _newEntry_ae_stage2_T_1 = 1'h0; // @[TLB.scala:456:84]
wire _waddr_T = 1'h0; // @[TLB.scala:477:45]
wire _mxr_T = 1'h0; // @[TLB.scala:518:36]
wire _cmd_lrsc_T = 1'h0; // @[package.scala:16:47]
wire _cmd_lrsc_T_1 = 1'h0; // @[package.scala:16:47]
wire _cmd_lrsc_T_2 = 1'h0; // @[package.scala:81:59]
wire cmd_lrsc = 1'h0; // @[TLB.scala:570:33]
wire _cmd_amo_logical_T = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_logical_T_1 = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_logical_T_2 = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_logical_T_3 = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_logical_T_4 = 1'h0; // @[package.scala:81:59]
wire _cmd_amo_logical_T_5 = 1'h0; // @[package.scala:81:59]
wire _cmd_amo_logical_T_6 = 1'h0; // @[package.scala:81:59]
wire cmd_amo_logical = 1'h0; // @[TLB.scala:571:40]
wire _cmd_amo_arithmetic_T = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_1 = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_2 = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_3 = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_4 = 1'h0; // @[package.scala:16:47]
wire _cmd_amo_arithmetic_T_5 = 1'h0; // @[package.scala:81:59]
wire _cmd_amo_arithmetic_T_6 = 1'h0; // @[package.scala:81:59]
wire _cmd_amo_arithmetic_T_7 = 1'h0; // @[package.scala:81:59]
wire _cmd_amo_arithmetic_T_8 = 1'h0; // @[package.scala:81:59]
wire cmd_amo_arithmetic = 1'h0; // @[TLB.scala:572:43]
wire cmd_put_partial = 1'h0; // @[TLB.scala:573:41]
wire _cmd_read_T_1 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_2 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_3 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_7 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_8 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_9 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_10 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_11 = 1'h0; // @[package.scala:81:59]
wire _cmd_read_T_12 = 1'h0; // @[package.scala:81:59]
wire _cmd_read_T_13 = 1'h0; // @[package.scala:81:59]
wire _cmd_read_T_14 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_15 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_16 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_17 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_18 = 1'h0; // @[package.scala:16:47]
wire _cmd_read_T_19 = 1'h0; // @[package.scala:81:59]
wire _cmd_read_T_20 = 1'h0; // @[package.scala:81:59]
wire _cmd_read_T_21 = 1'h0; // @[package.scala:81:59]
wire _cmd_read_T_22 = 1'h0; // @[package.scala:81:59]
wire _cmd_read_T_23 = 1'h0; // @[Consts.scala:87:44]
wire _cmd_readx_T = 1'h0; // @[TLB.scala:575:56]
wire cmd_readx = 1'h0; // @[TLB.scala:575:37]
wire _cmd_write_T = 1'h0; // @[Consts.scala:90:32]
wire _cmd_write_T_1 = 1'h0; // @[Consts.scala:90:49]
wire _cmd_write_T_2 = 1'h0; // @[Consts.scala:90:42]
wire _cmd_write_T_3 = 1'h0; // @[Consts.scala:90:66]
wire _cmd_write_T_4 = 1'h0; // @[Consts.scala:90:59]
wire _cmd_write_T_5 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_6 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_7 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_8 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_9 = 1'h0; // @[package.scala:81:59]
wire _cmd_write_T_10 = 1'h0; // @[package.scala:81:59]
wire _cmd_write_T_11 = 1'h0; // @[package.scala:81:59]
wire _cmd_write_T_12 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_13 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_14 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_15 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_16 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_T_17 = 1'h0; // @[package.scala:81:59]
wire _cmd_write_T_18 = 1'h0; // @[package.scala:81:59]
wire _cmd_write_T_19 = 1'h0; // @[package.scala:81:59]
wire _cmd_write_T_20 = 1'h0; // @[package.scala:81:59]
wire _cmd_write_T_21 = 1'h0; // @[Consts.scala:87:44]
wire cmd_write = 1'h0; // @[Consts.scala:90:76]
wire _cmd_write_perms_T = 1'h0; // @[package.scala:16:47]
wire _cmd_write_perms_T_1 = 1'h0; // @[package.scala:16:47]
wire _cmd_write_perms_T_2 = 1'h0; // @[package.scala:81:59]
wire cmd_write_perms = 1'h0; // @[TLB.scala:577:35]
wire _gf_ld_array_T = 1'h0; // @[TLB.scala:600:32]
wire _gf_st_array_T = 1'h0; // @[TLB.scala:601:32]
wire _multipleHits_T_6 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_15 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_27 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_35 = 1'h0; // @[Misc.scala:183:37]
wire _multipleHits_T_40 = 1'h0; // @[Misc.scala:183:37]
wire _io_resp_pf_st_T = 1'h0; // @[TLB.scala:634:28]
wire _io_resp_pf_st_T_2 = 1'h0; // @[TLB.scala:634:72]
wire _io_resp_pf_st_T_3 = 1'h0; // @[TLB.scala:634:48]
wire _io_resp_gf_ld_T = 1'h0; // @[TLB.scala:637:29]
wire _io_resp_gf_ld_T_2 = 1'h0; // @[TLB.scala:637:66]
wire _io_resp_gf_ld_T_3 = 1'h0; // @[TLB.scala:637:42]
wire _io_resp_gf_st_T = 1'h0; // @[TLB.scala:638:29]
wire _io_resp_gf_st_T_2 = 1'h0; // @[TLB.scala:638:73]
wire _io_resp_gf_st_T_3 = 1'h0; // @[TLB.scala:638:49]
wire _io_resp_gf_inst_T_1 = 1'h0; // @[TLB.scala:639:56]
wire _io_resp_gf_inst_T_2 = 1'h0; // @[TLB.scala:639:30]
wire _io_resp_ae_st_T_1 = 1'h0; // @[TLB.scala:642:41]
wire _io_resp_ma_st_T = 1'h0; // @[TLB.scala:646:31]
wire _io_resp_must_alloc_T_1 = 1'h0; // @[TLB.scala:649:51]
wire _io_resp_gpa_is_pte_T = 1'h0; // @[TLB.scala:655:36]
wire hv = 1'h0; // @[TLB.scala:721:36]
wire hg = 1'h0; // @[TLB.scala:722:36]
wire hv_1 = 1'h0; // @[TLB.scala:721:36]
wire hg_1 = 1'h0; // @[TLB.scala:722:36]
wire hv_2 = 1'h0; // @[TLB.scala:721:36]
wire hg_2 = 1'h0; // @[TLB.scala:722:36]
wire hv_3 = 1'h0; // @[TLB.scala:721:36]
wire hg_3 = 1'h0; // @[TLB.scala:722:36]
wire hv_4 = 1'h0; // @[TLB.scala:721:36]
wire hg_4 = 1'h0; // @[TLB.scala:722:36]
wire hv_5 = 1'h0; // @[TLB.scala:721:36]
wire hg_5 = 1'h0; // @[TLB.scala:722:36]
wire hv_6 = 1'h0; // @[TLB.scala:721:36]
wire hg_6 = 1'h0; // @[TLB.scala:722:36]
wire hv_7 = 1'h0; // @[TLB.scala:721:36]
wire hg_7 = 1'h0; // @[TLB.scala:722:36]
wire hv_8 = 1'h0; // @[TLB.scala:721:36]
wire hg_8 = 1'h0; // @[TLB.scala:722:36]
wire _ignore_T = 1'h0; // @[TLB.scala:182:28]
wire ignore = 1'h0; // @[TLB.scala:182:34]
wire hv_9 = 1'h0; // @[TLB.scala:721:36]
wire hg_9 = 1'h0; // @[TLB.scala:722:36]
wire _ignore_T_3 = 1'h0; // @[TLB.scala:182:28]
wire ignore_3 = 1'h0; // @[TLB.scala:182:34]
wire hv_10 = 1'h0; // @[TLB.scala:721:36]
wire hg_10 = 1'h0; // @[TLB.scala:722:36]
wire _ignore_T_6 = 1'h0; // @[TLB.scala:182:28]
wire ignore_6 = 1'h0; // @[TLB.scala:182:34]
wire hv_11 = 1'h0; // @[TLB.scala:721:36]
wire hg_11 = 1'h0; // @[TLB.scala:722:36]
wire _ignore_T_9 = 1'h0; // @[TLB.scala:182:28]
wire ignore_9 = 1'h0; // @[TLB.scala:182:34]
wire hv_12 = 1'h0; // @[TLB.scala:721:36]
wire hg_12 = 1'h0; // @[TLB.scala:722:36]
wire _ignore_T_12 = 1'h0; // @[TLB.scala:182:28]
wire ignore_12 = 1'h0; // @[TLB.scala:182:34]
wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[TLB.scala:318:7]
wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[TLB.scala:318:7]
wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[TLB.scala:318:7]
wire [15:0] satp_asid = 16'h0; // @[TLB.scala:373:17]
wire [31:0] io_ptw_status_isa = 32'h14112D; // @[TLB.scala:318:7]
wire [22:0] io_ptw_status_zero2 = 23'h0; // @[TLB.scala:318:7]
wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[TLB.scala:318:7]
wire [7:0] io_ptw_status_zero1 = 8'h0; // @[TLB.scala:318:7]
wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_xs = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_vs = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[TLB.scala:318:7]
wire [1:0] io_req_bits_size = 2'h3; // @[TLB.scala:318:7]
wire [1:0] io_resp_size = 2'h3; // @[TLB.scala:318:7]
wire [4:0] io_req_bits_cmd = 5'h0; // @[TLB.scala:318:7]
wire [4:0] io_resp_cmd = 5'h0; // @[TLB.scala:318:7]
wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_valid = 1'h1; // @[TLB.scala:318:7]
wire _vm_enabled_T_2 = 1'h1; // @[TLB.scala:399:64]
wire _vsatp_mode_mismatch_T_2 = 1'h1; // @[TLB.scala:403:81]
wire _homogeneous_T_59 = 1'h1; // @[TLBPermissions.scala:87:22]
wire superpage_hits_ignore_2 = 1'h1; // @[TLB.scala:182:34]
wire _superpage_hits_T_13 = 1'h1; // @[TLB.scala:183:40]
wire superpage_hits_ignore_5 = 1'h1; // @[TLB.scala:182:34]
wire _superpage_hits_T_27 = 1'h1; // @[TLB.scala:183:40]
wire superpage_hits_ignore_8 = 1'h1; // @[TLB.scala:182:34]
wire _superpage_hits_T_41 = 1'h1; // @[TLB.scala:183:40]
wire superpage_hits_ignore_11 = 1'h1; // @[TLB.scala:182:34]
wire _superpage_hits_T_55 = 1'h1; // @[TLB.scala:183:40]
wire hitsVec_ignore_2 = 1'h1; // @[TLB.scala:182:34]
wire _hitsVec_T_61 = 1'h1; // @[TLB.scala:183:40]
wire hitsVec_ignore_5 = 1'h1; // @[TLB.scala:182:34]
wire _hitsVec_T_76 = 1'h1; // @[TLB.scala:183:40]
wire hitsVec_ignore_8 = 1'h1; // @[TLB.scala:182:34]
wire _hitsVec_T_91 = 1'h1; // @[TLB.scala:183:40]
wire hitsVec_ignore_11 = 1'h1; // @[TLB.scala:182:34]
wire _hitsVec_T_106 = 1'h1; // @[TLB.scala:183:40]
wire ppn_ignore_1 = 1'h1; // @[TLB.scala:197:34]
wire ppn_ignore_3 = 1'h1; // @[TLB.scala:197:34]
wire ppn_ignore_5 = 1'h1; // @[TLB.scala:197:34]
wire ppn_ignore_7 = 1'h1; // @[TLB.scala:197:34]
wire _stage2_bypass_T = 1'h1; // @[TLB.scala:523:42]
wire _bad_va_T_1 = 1'h1; // @[TLB.scala:560:26]
wire _cmd_read_T = 1'h1; // @[package.scala:16:47]
wire _cmd_read_T_4 = 1'h1; // @[package.scala:81:59]
wire _cmd_read_T_5 = 1'h1; // @[package.scala:81:59]
wire _cmd_read_T_6 = 1'h1; // @[package.scala:81:59]
wire cmd_read = 1'h1; // @[Consts.scala:89:68]
wire _gpa_hits_hit_mask_T_3 = 1'h1; // @[TLB.scala:606:107]
wire _tlb_miss_T = 1'h1; // @[TLB.scala:613:32]
wire _io_resp_gpa_page_T = 1'h1; // @[TLB.scala:657:20]
wire _io_ptw_req_bits_valid_T = 1'h1; // @[TLB.scala:663:28]
wire ignore_2 = 1'h1; // @[TLB.scala:182:34]
wire ignore_5 = 1'h1; // @[TLB.scala:182:34]
wire ignore_8 = 1'h1; // @[TLB.scala:182:34]
wire ignore_11 = 1'h1; // @[TLB.scala:182:34]
wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[TLB.scala:318:7]
wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[TLB.scala:318:7]
wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[TLB.scala:318:7]
wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_sxl = 2'h2; // @[TLB.scala:318:7]
wire [1:0] io_ptw_status_uxl = 2'h2; // @[TLB.scala:318:7]
wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[TLB.scala:318:7]
wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[TLB.scala:318:7]
wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[TLB.scala:318:7]
wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_0_value = 64'h0; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_1_value = 64'h0; // @[TLB.scala:318:7]
wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[TLB.scala:318:7]
wire [13:0] _ae_array_T_2 = 14'h0; // @[TLB.scala:583:8]
wire [13:0] _ae_st_array_T_2 = 14'h0; // @[TLB.scala:588:8]
wire [13:0] _ae_st_array_T_4 = 14'h0; // @[TLB.scala:589:8]
wire [13:0] _ae_st_array_T_5 = 14'h0; // @[TLB.scala:588:53]
wire [13:0] _ae_st_array_T_7 = 14'h0; // @[TLB.scala:590:8]
wire [13:0] _ae_st_array_T_8 = 14'h0; // @[TLB.scala:589:53]
wire [13:0] _ae_st_array_T_10 = 14'h0; // @[TLB.scala:591:8]
wire [13:0] ae_st_array = 14'h0; // @[TLB.scala:590:53]
wire [13:0] _must_alloc_array_T_1 = 14'h0; // @[TLB.scala:593:8]
wire [13:0] _must_alloc_array_T_3 = 14'h0; // @[TLB.scala:594:8]
wire [13:0] _must_alloc_array_T_4 = 14'h0; // @[TLB.scala:593:43]
wire [13:0] _must_alloc_array_T_6 = 14'h0; // @[TLB.scala:595:8]
wire [13:0] _must_alloc_array_T_7 = 14'h0; // @[TLB.scala:594:43]
wire [13:0] _must_alloc_array_T_9 = 14'h0; // @[TLB.scala:596:8]
wire [13:0] must_alloc_array = 14'h0; // @[TLB.scala:595:46]
wire [13:0] pf_st_array = 14'h0; // @[TLB.scala:598:24]
wire [13:0] _gf_ld_array_T_2 = 14'h0; // @[TLB.scala:600:46]
wire [13:0] gf_ld_array = 14'h0; // @[TLB.scala:600:24]
wire [13:0] _gf_st_array_T_1 = 14'h0; // @[TLB.scala:601:53]
wire [13:0] gf_st_array = 14'h0; // @[TLB.scala:601:24]
wire [13:0] _gf_inst_array_T = 14'h0; // @[TLB.scala:602:36]
wire [13:0] gf_inst_array = 14'h0; // @[TLB.scala:602:26]
wire [13:0] _io_resp_pf_st_T_1 = 14'h0; // @[TLB.scala:634:64]
wire [13:0] _io_resp_gf_ld_T_1 = 14'h0; // @[TLB.scala:637:58]
wire [13:0] _io_resp_gf_st_T_1 = 14'h0; // @[TLB.scala:638:65]
wire [13:0] _io_resp_gf_inst_T = 14'h0; // @[TLB.scala:639:48]
wire [13:0] _io_resp_ae_st_T = 14'h0; // @[TLB.scala:642:33]
wire [13:0] _io_resp_must_alloc_T = 14'h0; // @[TLB.scala:649:43]
wire [6:0] _state_vec_WIRE_0 = 7'h0; // @[Replacement.scala:305:25]
wire [12:0] stage2_bypass = 13'h1FFF; // @[TLB.scala:523:27]
wire [12:0] _hr_array_T_4 = 13'h1FFF; // @[TLB.scala:524:111]
wire [12:0] _hw_array_T_1 = 13'h1FFF; // @[TLB.scala:525:55]
wire [12:0] _hx_array_T_1 = 13'h1FFF; // @[TLB.scala:526:55]
wire [12:0] _gpa_hits_hit_mask_T_4 = 13'h1FFF; // @[TLB.scala:606:88]
wire [12:0] gpa_hits_hit_mask = 13'h1FFF; // @[TLB.scala:606:82]
wire [12:0] _gpa_hits_T_1 = 13'h1FFF; // @[TLB.scala:607:16]
wire [12:0] gpa_hits = 13'h1FFF; // @[TLB.scala:607:14]
wire [12:0] _stage1_bypass_T = 13'h0; // @[TLB.scala:517:27]
wire [12:0] stage1_bypass = 13'h0; // @[TLB.scala:517:61]
wire [12:0] _gpa_hits_T = 13'h0; // @[TLB.scala:607:30]
wire [13:0] hr_array = 14'h3FFF; // @[TLB.scala:524:21]
wire [13:0] hw_array = 14'h3FFF; // @[TLB.scala:525:21]
wire [13:0] hx_array = 14'h3FFF; // @[TLB.scala:526:21]
wire [13:0] _must_alloc_array_T_8 = 14'h3FFF; // @[TLB.scala:596:19]
wire [13:0] _gf_ld_array_T_1 = 14'h3FFF; // @[TLB.scala:600:50]
wire [3:0] _misaligned_T_2 = 4'h7; // @[TLB.scala:550:69]
wire [4:0] _misaligned_T_1 = 5'h7; // @[TLB.scala:550:69]
wire [3:0] _misaligned_T = 4'h8; // @[OneHot.scala:58:35]
wire _io_req_ready_T; // @[TLB.scala:631:25]
wire _io_resp_miss_T_2; // @[TLB.scala:651:64]
wire [31:0] _io_resp_paddr_T_1; // @[TLB.scala:652:23]
wire [39:0] _io_resp_gpa_T; // @[TLB.scala:659:8]
wire _io_resp_pf_ld_T_3; // @[TLB.scala:633:41]
wire _io_resp_pf_inst_T_2; // @[TLB.scala:635:29]
wire _io_resp_ae_ld_T_1; // @[TLB.scala:641:41]
wire _io_resp_ae_inst_T_2; // @[TLB.scala:643:41]
wire _io_resp_ma_ld_T; // @[TLB.scala:645:31]
wire _io_resp_cacheable_T_1; // @[TLB.scala:648:41]
wire _io_resp_prefetchable_T_2; // @[TLB.scala:650:59]
wire _io_ptw_req_valid_T; // @[TLB.scala:662:29]
wire do_refill = io_ptw_resp_valid_0; // @[TLB.scala:318:7, :408:29]
wire newEntry_ae_ptw = io_ptw_resp_bits_ae_ptw_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_ae_final = io_ptw_resp_bits_ae_final_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_pf = io_ptw_resp_bits_pf_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_gf = io_ptw_resp_bits_gf_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_hr = io_ptw_resp_bits_hr_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_hw = io_ptw_resp_bits_hw_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_hx = io_ptw_resp_bits_hx_0; // @[TLB.scala:318:7, :449:24]
wire newEntry_u = io_ptw_resp_bits_pte_u_0; // @[TLB.scala:318:7, :449:24]
wire [1:0] _special_entry_level_T = io_ptw_resp_bits_level_0; // @[package.scala:163:13]
wire [3:0] satp_mode = io_ptw_ptbr_mode_0; // @[TLB.scala:318:7, :373:17]
wire [43:0] satp_ppn = io_ptw_ptbr_ppn_0; // @[TLB.scala:318:7, :373:17]
wire mxr = io_ptw_status_mxr_0; // @[TLB.scala:318:7, :518:31]
wire sum = io_ptw_status_sum_0; // @[TLB.scala:318:7, :510:16]
wire io_req_ready; // @[TLB.scala:318:7]
wire io_resp_pf_ld_0; // @[TLB.scala:318:7]
wire io_resp_pf_inst_0; // @[TLB.scala:318:7]
wire io_resp_ae_ld_0; // @[TLB.scala:318:7]
wire io_resp_ae_inst_0; // @[TLB.scala:318:7]
wire io_resp_ma_ld_0; // @[TLB.scala:318:7]
wire io_resp_miss_0; // @[TLB.scala:318:7]
wire [31:0] io_resp_paddr_0; // @[TLB.scala:318:7]
wire [39:0] io_resp_gpa_0; // @[TLB.scala:318:7]
wire io_resp_cacheable_0; // @[TLB.scala:318:7]
wire io_resp_prefetchable_0; // @[TLB.scala:318:7]
wire [26:0] io_ptw_req_bits_bits_addr_0; // @[TLB.scala:318:7]
wire io_ptw_req_bits_bits_need_gpa_0; // @[TLB.scala:318:7]
wire io_ptw_req_valid_0; // @[TLB.scala:318:7]
wire [26:0] vpn = io_req_bits_vaddr_0[38:12]; // @[TLB.scala:318:7, :335:30]
wire [26:0] _ppn_T_5 = vpn; // @[TLB.scala:198:28, :335:30]
wire [26:0] _ppn_T_13 = vpn; // @[TLB.scala:198:28, :335:30]
wire [26:0] _ppn_T_21 = vpn; // @[TLB.scala:198:28, :335:30]
wire [26:0] _ppn_T_29 = vpn; // @[TLB.scala:198:28, :335:30]
reg [1:0] sectored_entries_0_0_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_0_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_0_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_0_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_0_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_0_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_0_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_0_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_0_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_0_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_0_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_1_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_1_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_1_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_1_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_1_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_1_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_1_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_1_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_1_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_1_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_1_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_2_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_2_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_2_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_2_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_2_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_2_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_2_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_2_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_2_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_2_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_2_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_3_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_3_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_3_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_3_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_3_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_3_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_3_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_3_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_3_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_3_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_3_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_4_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_4_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_4_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_4_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_4_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_4_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_4_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_4_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_4_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_4_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_4_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_5_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_5_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_5_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_5_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_5_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_5_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_5_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_5_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_5_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_5_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_5_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_6_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_6_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_6_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_6_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_6_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_6_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_6_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_6_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_6_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_6_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_6_valid_3; // @[TLB.scala:339:29]
reg [1:0] sectored_entries_0_7_level; // @[TLB.scala:339:29]
reg [26:0] sectored_entries_0_7_tag_vpn; // @[TLB.scala:339:29]
reg sectored_entries_0_7_tag_v; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_7_data_0; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_7_data_1; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_7_data_2; // @[TLB.scala:339:29]
reg [41:0] sectored_entries_0_7_data_3; // @[TLB.scala:339:29]
reg sectored_entries_0_7_valid_0; // @[TLB.scala:339:29]
reg sectored_entries_0_7_valid_1; // @[TLB.scala:339:29]
reg sectored_entries_0_7_valid_2; // @[TLB.scala:339:29]
reg sectored_entries_0_7_valid_3; // @[TLB.scala:339:29]
reg [1:0] superpage_entries_0_level; // @[TLB.scala:341:30]
reg [26:0] superpage_entries_0_tag_vpn; // @[TLB.scala:341:30]
reg superpage_entries_0_tag_v; // @[TLB.scala:341:30]
reg [41:0] superpage_entries_0_data_0; // @[TLB.scala:341:30]
wire [41:0] _entries_WIRE_17 = superpage_entries_0_data_0; // @[TLB.scala:170:77, :341:30]
reg superpage_entries_0_valid_0; // @[TLB.scala:341:30]
reg [1:0] superpage_entries_1_level; // @[TLB.scala:341:30]
reg [26:0] superpage_entries_1_tag_vpn; // @[TLB.scala:341:30]
reg superpage_entries_1_tag_v; // @[TLB.scala:341:30]
reg [41:0] superpage_entries_1_data_0; // @[TLB.scala:341:30]
wire [41:0] _entries_WIRE_19 = superpage_entries_1_data_0; // @[TLB.scala:170:77, :341:30]
reg superpage_entries_1_valid_0; // @[TLB.scala:341:30]
reg [1:0] superpage_entries_2_level; // @[TLB.scala:341:30]
reg [26:0] superpage_entries_2_tag_vpn; // @[TLB.scala:341:30]
reg superpage_entries_2_tag_v; // @[TLB.scala:341:30]
reg [41:0] superpage_entries_2_data_0; // @[TLB.scala:341:30]
wire [41:0] _entries_WIRE_21 = superpage_entries_2_data_0; // @[TLB.scala:170:77, :341:30]
reg superpage_entries_2_valid_0; // @[TLB.scala:341:30]
reg [1:0] superpage_entries_3_level; // @[TLB.scala:341:30]
reg [26:0] superpage_entries_3_tag_vpn; // @[TLB.scala:341:30]
reg superpage_entries_3_tag_v; // @[TLB.scala:341:30]
reg [41:0] superpage_entries_3_data_0; // @[TLB.scala:341:30]
wire [41:0] _entries_WIRE_23 = superpage_entries_3_data_0; // @[TLB.scala:170:77, :341:30]
reg superpage_entries_3_valid_0; // @[TLB.scala:341:30]
reg [1:0] special_entry_level; // @[TLB.scala:346:56]
reg [26:0] special_entry_tag_vpn; // @[TLB.scala:346:56]
reg special_entry_tag_v; // @[TLB.scala:346:56]
reg [41:0] special_entry_data_0; // @[TLB.scala:346:56]
wire [41:0] _mpu_ppn_WIRE_1 = special_entry_data_0; // @[TLB.scala:170:77, :346:56]
wire [41:0] _entries_WIRE_25 = special_entry_data_0; // @[TLB.scala:170:77, :346:56]
reg special_entry_valid_0; // @[TLB.scala:346:56]
reg [1:0] state; // @[TLB.scala:352:22]
reg [26:0] r_refill_tag; // @[TLB.scala:354:25]
assign io_ptw_req_bits_bits_addr_0 = r_refill_tag; // @[TLB.scala:318:7, :354:25]
reg [1:0] r_superpage_repl_addr; // @[TLB.scala:355:34]
wire [1:0] waddr = r_superpage_repl_addr; // @[TLB.scala:355:34, :477:22]
reg [2:0] r_sectored_repl_addr; // @[TLB.scala:356:33]
reg r_sectored_hit_valid; // @[TLB.scala:357:27]
reg [2:0] r_sectored_hit_bits; // @[TLB.scala:357:27]
reg r_superpage_hit_valid; // @[TLB.scala:358:28]
reg [1:0] r_superpage_hit_bits; // @[TLB.scala:358:28]
reg r_need_gpa; // @[TLB.scala:361:23]
assign io_ptw_req_bits_bits_need_gpa_0 = r_need_gpa; // @[TLB.scala:318:7, :361:23]
reg r_gpa_valid; // @[TLB.scala:362:24]
reg [38:0] r_gpa; // @[TLB.scala:363:18]
reg [26:0] r_gpa_vpn; // @[TLB.scala:364:22]
reg r_gpa_is_pte; // @[TLB.scala:365:25]
wire priv_s = io_req_bits_prv_0[0]; // @[TLB.scala:318:7, :370:20]
wire priv_uses_vm = ~(io_req_bits_prv_0[1]); // @[TLB.scala:318:7, :372:27]
wire _stage1_en_T = satp_mode[3]; // @[TLB.scala:373:17, :374:41]
wire stage1_en = _stage1_en_T; // @[TLB.scala:374:{29,41}]
wire _vm_enabled_T = stage1_en; // @[TLB.scala:374:29, :399:31]
wire _vm_enabled_T_1 = _vm_enabled_T & priv_uses_vm; // @[TLB.scala:372:27, :399:{31,45}]
wire vm_enabled = _vm_enabled_T_1; // @[TLB.scala:399:{45,61}]
wire _mpu_ppn_T = vm_enabled; // @[TLB.scala:399:61, :413:32]
wire _tlb_miss_T_1 = vm_enabled; // @[TLB.scala:399:61, :613:29]
wire [19:0] refill_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44]
wire [19:0] newEntry_ppn = io_ptw_resp_bits_pte_ppn_0[19:0]; // @[TLB.scala:318:7, :406:44, :449:24]
wire _mpu_priv_T = do_refill; // @[TLB.scala:408:29, :415:52]
wire _io_resp_miss_T = do_refill; // @[TLB.scala:408:29, :651:29]
wire _T_51 = state == 2'h1; // @[package.scala:16:47]
wire _invalidate_refill_T; // @[package.scala:16:47]
assign _invalidate_refill_T = _T_51; // @[package.scala:16:47]
assign _io_ptw_req_valid_T = _T_51; // @[package.scala:16:47]
wire _invalidate_refill_T_1 = &state; // @[package.scala:16:47]
wire _invalidate_refill_T_2 = _invalidate_refill_T | _invalidate_refill_T_1; // @[package.scala:16:47, :81:59]
wire invalidate_refill = _invalidate_refill_T_2 | io_sfence_valid_0; // @[package.scala:81:59]
wire [19:0] _mpu_ppn_T_23; // @[TLB.scala:170:77]
wire _mpu_ppn_T_22; // @[TLB.scala:170:77]
wire _mpu_ppn_T_21; // @[TLB.scala:170:77]
wire _mpu_ppn_T_20; // @[TLB.scala:170:77]
wire _mpu_ppn_T_19; // @[TLB.scala:170:77]
wire _mpu_ppn_T_18; // @[TLB.scala:170:77]
wire _mpu_ppn_T_17; // @[TLB.scala:170:77]
wire _mpu_ppn_T_16; // @[TLB.scala:170:77]
wire _mpu_ppn_T_15; // @[TLB.scala:170:77]
wire _mpu_ppn_T_14; // @[TLB.scala:170:77]
wire _mpu_ppn_T_13; // @[TLB.scala:170:77]
wire _mpu_ppn_T_12; // @[TLB.scala:170:77]
wire _mpu_ppn_T_11; // @[TLB.scala:170:77]
wire _mpu_ppn_T_10; // @[TLB.scala:170:77]
wire _mpu_ppn_T_9; // @[TLB.scala:170:77]
wire _mpu_ppn_T_8; // @[TLB.scala:170:77]
wire _mpu_ppn_T_7; // @[TLB.scala:170:77]
wire _mpu_ppn_T_6; // @[TLB.scala:170:77]
wire _mpu_ppn_T_5; // @[TLB.scala:170:77]
wire _mpu_ppn_T_4; // @[TLB.scala:170:77]
wire _mpu_ppn_T_3; // @[TLB.scala:170:77]
wire _mpu_ppn_T_2; // @[TLB.scala:170:77]
wire _mpu_ppn_T_1; // @[TLB.scala:170:77]
assign _mpu_ppn_T_1 = _mpu_ppn_WIRE_1[0]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_fragmented_superpage = _mpu_ppn_T_1; // @[TLB.scala:170:77]
assign _mpu_ppn_T_2 = _mpu_ppn_WIRE_1[1]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_c = _mpu_ppn_T_2; // @[TLB.scala:170:77]
assign _mpu_ppn_T_3 = _mpu_ppn_WIRE_1[2]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_eff = _mpu_ppn_T_3; // @[TLB.scala:170:77]
assign _mpu_ppn_T_4 = _mpu_ppn_WIRE_1[3]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_paa = _mpu_ppn_T_4; // @[TLB.scala:170:77]
assign _mpu_ppn_T_5 = _mpu_ppn_WIRE_1[4]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pal = _mpu_ppn_T_5; // @[TLB.scala:170:77]
assign _mpu_ppn_T_6 = _mpu_ppn_WIRE_1[5]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ppp = _mpu_ppn_T_6; // @[TLB.scala:170:77]
assign _mpu_ppn_T_7 = _mpu_ppn_WIRE_1[6]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pr = _mpu_ppn_T_7; // @[TLB.scala:170:77]
assign _mpu_ppn_T_8 = _mpu_ppn_WIRE_1[7]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_px = _mpu_ppn_T_8; // @[TLB.scala:170:77]
assign _mpu_ppn_T_9 = _mpu_ppn_WIRE_1[8]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pw = _mpu_ppn_T_9; // @[TLB.scala:170:77]
assign _mpu_ppn_T_10 = _mpu_ppn_WIRE_1[9]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_hr = _mpu_ppn_T_10; // @[TLB.scala:170:77]
assign _mpu_ppn_T_11 = _mpu_ppn_WIRE_1[10]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_hx = _mpu_ppn_T_11; // @[TLB.scala:170:77]
assign _mpu_ppn_T_12 = _mpu_ppn_WIRE_1[11]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_hw = _mpu_ppn_T_12; // @[TLB.scala:170:77]
assign _mpu_ppn_T_13 = _mpu_ppn_WIRE_1[12]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_sr = _mpu_ppn_T_13; // @[TLB.scala:170:77]
assign _mpu_ppn_T_14 = _mpu_ppn_WIRE_1[13]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_sx = _mpu_ppn_T_14; // @[TLB.scala:170:77]
assign _mpu_ppn_T_15 = _mpu_ppn_WIRE_1[14]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_sw = _mpu_ppn_T_15; // @[TLB.scala:170:77]
assign _mpu_ppn_T_16 = _mpu_ppn_WIRE_1[15]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_gf = _mpu_ppn_T_16; // @[TLB.scala:170:77]
assign _mpu_ppn_T_17 = _mpu_ppn_WIRE_1[16]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_pf = _mpu_ppn_T_17; // @[TLB.scala:170:77]
assign _mpu_ppn_T_18 = _mpu_ppn_WIRE_1[17]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ae_stage2 = _mpu_ppn_T_18; // @[TLB.scala:170:77]
assign _mpu_ppn_T_19 = _mpu_ppn_WIRE_1[18]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ae_final = _mpu_ppn_T_19; // @[TLB.scala:170:77]
assign _mpu_ppn_T_20 = _mpu_ppn_WIRE_1[19]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_ae_ptw = _mpu_ppn_T_20; // @[TLB.scala:170:77]
assign _mpu_ppn_T_21 = _mpu_ppn_WIRE_1[20]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_g = _mpu_ppn_T_21; // @[TLB.scala:170:77]
assign _mpu_ppn_T_22 = _mpu_ppn_WIRE_1[21]; // @[TLB.scala:170:77]
wire _mpu_ppn_WIRE_u = _mpu_ppn_T_22; // @[TLB.scala:170:77]
assign _mpu_ppn_T_23 = _mpu_ppn_WIRE_1[41:22]; // @[TLB.scala:170:77]
wire [19:0] _mpu_ppn_WIRE_ppn = _mpu_ppn_T_23; // @[TLB.scala:170:77]
wire [1:0] mpu_ppn_res = _mpu_ppn_barrier_io_y_ppn[19:18]; // @[package.scala:267:25]
wire _GEN = special_entry_level == 2'h0; // @[TLB.scala:197:28, :346:56]
wire _mpu_ppn_ignore_T; // @[TLB.scala:197:28]
assign _mpu_ppn_ignore_T = _GEN; // @[TLB.scala:197:28]
wire _hitsVec_ignore_T_13; // @[TLB.scala:182:28]
assign _hitsVec_ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28]
wire _ppn_ignore_T_8; // @[TLB.scala:197:28]
assign _ppn_ignore_T_8 = _GEN; // @[TLB.scala:197:28]
wire _ignore_T_13; // @[TLB.scala:182:28]
assign _ignore_T_13 = _GEN; // @[TLB.scala:182:28, :197:28]
wire mpu_ppn_ignore = _mpu_ppn_ignore_T; // @[TLB.scala:197:{28,34}]
wire [26:0] _mpu_ppn_T_24 = mpu_ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _mpu_ppn_T_25 = {_mpu_ppn_T_24[26:20], _mpu_ppn_T_24[19:0] | _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _mpu_ppn_T_26 = _mpu_ppn_T_25[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _mpu_ppn_T_27 = {mpu_ppn_res, _mpu_ppn_T_26}; // @[TLB.scala:195:26, :198:{18,58}]
wire _mpu_ppn_ignore_T_1 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56]
wire mpu_ppn_ignore_1 = _mpu_ppn_ignore_T_1; // @[TLB.scala:197:{28,34}]
wire [26:0] _mpu_ppn_T_28 = mpu_ppn_ignore_1 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _mpu_ppn_T_29 = {_mpu_ppn_T_28[26:20], _mpu_ppn_T_28[19:0] | _mpu_ppn_barrier_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _mpu_ppn_T_30 = _mpu_ppn_T_29[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _mpu_ppn_T_31 = {_mpu_ppn_T_27, _mpu_ppn_T_30}; // @[TLB.scala:198:{18,58}]
wire [27:0] _mpu_ppn_T_32 = io_req_bits_vaddr_0[39:12]; // @[TLB.scala:318:7, :413:146]
wire [27:0] _mpu_ppn_T_33 = _mpu_ppn_T ? {8'h0, _mpu_ppn_T_31} : _mpu_ppn_T_32; // @[TLB.scala:198:18, :413:{20,32,146}]
wire [27:0] mpu_ppn = do_refill ? {8'h0, refill_ppn} : _mpu_ppn_T_33; // @[TLB.scala:406:44, :408:29, :412:20, :413:20]
wire [11:0] _mpu_physaddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52]
wire [11:0] _io_resp_paddr_T = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :652:46]
wire [11:0] _io_resp_gpa_offset_T_1 = io_req_bits_vaddr_0[11:0]; // @[TLB.scala:318:7, :414:52, :658:82]
wire [39:0] mpu_physaddr = {mpu_ppn, _mpu_physaddr_T}; // @[TLB.scala:412:20, :414:{25,52}]
wire [39:0] _homogeneous_T = mpu_physaddr; // @[TLB.scala:414:25]
wire [39:0] _homogeneous_T_67 = mpu_physaddr; // @[TLB.scala:414:25]
wire [39:0] _deny_access_to_debug_T_1 = mpu_physaddr; // @[TLB.scala:414:25]
wire _mpu_priv_T_1 = _mpu_priv_T; // @[TLB.scala:415:{38,52}]
wire [2:0] _mpu_priv_T_2 = {io_ptw_status_debug_0, io_req_bits_prv_0}; // @[TLB.scala:318:7, :415:103]
wire [2:0] mpu_priv = _mpu_priv_T_1 ? 3'h1 : _mpu_priv_T_2; // @[TLB.scala:415:{27,38,103}]
wire cacheable; // @[TLB.scala:425:41]
wire newEntry_c = cacheable; // @[TLB.scala:425:41, :449:24]
wire [40:0] _homogeneous_T_1 = {1'h0, _homogeneous_T}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_2 = _homogeneous_T_1 & 41'h1FFFFFFE000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_3 = _homogeneous_T_2; // @[Parameters.scala:137:46]
wire _homogeneous_T_4 = _homogeneous_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_50 = _homogeneous_T_4; // @[TLBPermissions.scala:101:65]
wire [39:0] _GEN_0 = {mpu_physaddr[39:14], mpu_physaddr[13:0] ^ 14'h3000}; // @[TLB.scala:414:25]
wire [39:0] _homogeneous_T_5; // @[Parameters.scala:137:31]
assign _homogeneous_T_5 = _GEN_0; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_72; // @[Parameters.scala:137:31]
assign _homogeneous_T_72 = _GEN_0; // @[Parameters.scala:137:31]
wire [40:0] _homogeneous_T_6 = {1'h0, _homogeneous_T_5}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_7 = _homogeneous_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_8 = _homogeneous_T_7; // @[Parameters.scala:137:46]
wire _homogeneous_T_9 = _homogeneous_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_1 = {mpu_physaddr[39:17], mpu_physaddr[16:0] ^ 17'h10000}; // @[TLB.scala:414:25]
wire [39:0] _homogeneous_T_10; // @[Parameters.scala:137:31]
assign _homogeneous_T_10 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_60; // @[Parameters.scala:137:31]
assign _homogeneous_T_60 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_77; // @[Parameters.scala:137:31]
assign _homogeneous_T_77 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_109; // @[Parameters.scala:137:31]
assign _homogeneous_T_109 = _GEN_1; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_116; // @[Parameters.scala:137:31]
assign _homogeneous_T_116 = _GEN_1; // @[Parameters.scala:137:31]
wire [40:0] _homogeneous_T_11 = {1'h0, _homogeneous_T_10}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_12 = _homogeneous_T_11 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_13 = _homogeneous_T_12; // @[Parameters.scala:137:46]
wire _homogeneous_T_14 = _homogeneous_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_15 = {mpu_physaddr[39:21], mpu_physaddr[20:0] ^ 21'h100000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_16 = {1'h0, _homogeneous_T_15}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_17 = _homogeneous_T_16 & 41'h1FFFFFEF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_18 = _homogeneous_T_17; // @[Parameters.scala:137:46]
wire _homogeneous_T_19 = _homogeneous_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_20 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2000000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_21 = {1'h0, _homogeneous_T_20}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_22 = _homogeneous_T_21 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_23 = _homogeneous_T_22; // @[Parameters.scala:137:46]
wire _homogeneous_T_24 = _homogeneous_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_25 = {mpu_physaddr[39:26], mpu_physaddr[25:0] ^ 26'h2010000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_26 = {1'h0, _homogeneous_T_25}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_27 = _homogeneous_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_28 = _homogeneous_T_27; // @[Parameters.scala:137:46]
wire _homogeneous_T_29 = _homogeneous_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_2 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'h8000000}; // @[TLB.scala:414:25]
wire [39:0] _homogeneous_T_30; // @[Parameters.scala:137:31]
assign _homogeneous_T_30 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_82; // @[Parameters.scala:137:31]
assign _homogeneous_T_82 = _GEN_2; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_97; // @[Parameters.scala:137:31]
assign _homogeneous_T_97 = _GEN_2; // @[Parameters.scala:137:31]
wire [40:0] _homogeneous_T_31 = {1'h0, _homogeneous_T_30}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_32 = _homogeneous_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_33 = _homogeneous_T_32; // @[Parameters.scala:137:46]
wire _homogeneous_T_34 = _homogeneous_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_35 = {mpu_physaddr[39:28], mpu_physaddr[27:0] ^ 28'hC000000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_36 = {1'h0, _homogeneous_T_35}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_37 = _homogeneous_T_36 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_38 = _homogeneous_T_37; // @[Parameters.scala:137:46]
wire _homogeneous_T_39 = _homogeneous_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _homogeneous_T_40 = {mpu_physaddr[39:29], mpu_physaddr[28:0] ^ 29'h10020000}; // @[TLB.scala:414:25]
wire [40:0] _homogeneous_T_41 = {1'h0, _homogeneous_T_40}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_42 = _homogeneous_T_41 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_43 = _homogeneous_T_42; // @[Parameters.scala:137:46]
wire _homogeneous_T_44 = _homogeneous_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [39:0] _GEN_3 = {mpu_physaddr[39:32], mpu_physaddr[31:0] ^ 32'h80000000}; // @[TLB.scala:414:25, :417:15]
wire [39:0] _homogeneous_T_45; // @[Parameters.scala:137:31]
assign _homogeneous_T_45 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_87; // @[Parameters.scala:137:31]
assign _homogeneous_T_87 = _GEN_3; // @[Parameters.scala:137:31]
wire [39:0] _homogeneous_T_102; // @[Parameters.scala:137:31]
assign _homogeneous_T_102 = _GEN_3; // @[Parameters.scala:137:31]
wire [40:0] _homogeneous_T_46 = {1'h0, _homogeneous_T_45}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_47 = _homogeneous_T_46 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_48 = _homogeneous_T_47; // @[Parameters.scala:137:46]
wire _homogeneous_T_49 = _homogeneous_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_51 = _homogeneous_T_50 | _homogeneous_T_9; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_52 = _homogeneous_T_51 | _homogeneous_T_14; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_53 = _homogeneous_T_52 | _homogeneous_T_19; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_54 = _homogeneous_T_53 | _homogeneous_T_24; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_55 = _homogeneous_T_54 | _homogeneous_T_29; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_56 = _homogeneous_T_55 | _homogeneous_T_34; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_57 = _homogeneous_T_56 | _homogeneous_T_39; // @[TLBPermissions.scala:101:65]
wire _homogeneous_T_58 = _homogeneous_T_57 | _homogeneous_T_44; // @[TLBPermissions.scala:101:65]
wire homogeneous = _homogeneous_T_58 | _homogeneous_T_49; // @[TLBPermissions.scala:101:65]
wire [40:0] _homogeneous_T_61 = {1'h0, _homogeneous_T_60}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_62 = _homogeneous_T_61 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_63 = _homogeneous_T_62; // @[Parameters.scala:137:46]
wire _homogeneous_T_64 = _homogeneous_T_63 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_65 = _homogeneous_T_64; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_66 = ~_homogeneous_T_65; // @[TLBPermissions.scala:87:{22,66}]
wire [40:0] _homogeneous_T_68 = {1'h0, _homogeneous_T_67}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_69 = _homogeneous_T_68 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_70 = _homogeneous_T_69; // @[Parameters.scala:137:46]
wire _homogeneous_T_71 = _homogeneous_T_70 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_92 = _homogeneous_T_71; // @[TLBPermissions.scala:85:66]
wire [40:0] _homogeneous_T_73 = {1'h0, _homogeneous_T_72}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_74 = _homogeneous_T_73 & 41'h9E113000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_75 = _homogeneous_T_74; // @[Parameters.scala:137:46]
wire _homogeneous_T_76 = _homogeneous_T_75 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _homogeneous_T_78 = {1'h0, _homogeneous_T_77}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_79 = _homogeneous_T_78 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_80 = _homogeneous_T_79; // @[Parameters.scala:137:46]
wire _homogeneous_T_81 = _homogeneous_T_80 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _homogeneous_T_83 = {1'h0, _homogeneous_T_82}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_84 = _homogeneous_T_83 & 41'h9E110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_85 = _homogeneous_T_84; // @[Parameters.scala:137:46]
wire _homogeneous_T_86 = _homogeneous_T_85 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire [40:0] _homogeneous_T_88 = {1'h0, _homogeneous_T_87}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_89 = _homogeneous_T_88 & 41'h90000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_90 = _homogeneous_T_89; // @[Parameters.scala:137:46]
wire _homogeneous_T_91 = _homogeneous_T_90 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_93 = _homogeneous_T_92 | _homogeneous_T_76; // @[TLBPermissions.scala:85:66]
wire _homogeneous_T_94 = _homogeneous_T_93 | _homogeneous_T_81; // @[TLBPermissions.scala:85:66]
wire _homogeneous_T_95 = _homogeneous_T_94 | _homogeneous_T_86; // @[TLBPermissions.scala:85:66]
wire _homogeneous_T_96 = _homogeneous_T_95 | _homogeneous_T_91; // @[TLBPermissions.scala:85:66]
wire [40:0] _homogeneous_T_98 = {1'h0, _homogeneous_T_97}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_99 = _homogeneous_T_98 & 41'h8E000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_100 = _homogeneous_T_99; // @[Parameters.scala:137:46]
wire _homogeneous_T_101 = _homogeneous_T_100 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_107 = _homogeneous_T_101; // @[TLBPermissions.scala:85:66]
wire [40:0] _homogeneous_T_103 = {1'h0, _homogeneous_T_102}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_104 = _homogeneous_T_103 & 41'h80000000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_105 = _homogeneous_T_104; // @[Parameters.scala:137:46]
wire _homogeneous_T_106 = _homogeneous_T_105 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_108 = _homogeneous_T_107 | _homogeneous_T_106; // @[TLBPermissions.scala:85:66]
wire [40:0] _homogeneous_T_110 = {1'h0, _homogeneous_T_109}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_111 = _homogeneous_T_110 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_112 = _homogeneous_T_111; // @[Parameters.scala:137:46]
wire _homogeneous_T_113 = _homogeneous_T_112 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_114 = _homogeneous_T_113; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_115 = ~_homogeneous_T_114; // @[TLBPermissions.scala:87:{22,66}]
wire [40:0] _homogeneous_T_117 = {1'h0, _homogeneous_T_116}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _homogeneous_T_118 = _homogeneous_T_117 & 41'h8A110000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _homogeneous_T_119 = _homogeneous_T_118; // @[Parameters.scala:137:46]
wire _homogeneous_T_120 = _homogeneous_T_119 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire _homogeneous_T_121 = _homogeneous_T_120; // @[TLBPermissions.scala:87:66]
wire _homogeneous_T_122 = ~_homogeneous_T_121; // @[TLBPermissions.scala:87:{22,66}]
wire _deny_access_to_debug_T = ~(mpu_priv[2]); // @[TLB.scala:415:27, :428:39]
wire [40:0] _deny_access_to_debug_T_2 = {1'h0, _deny_access_to_debug_T_1}; // @[Parameters.scala:137:{31,41}]
wire [40:0] _deny_access_to_debug_T_3 = _deny_access_to_debug_T_2 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}]
wire [40:0] _deny_access_to_debug_T_4 = _deny_access_to_debug_T_3; // @[Parameters.scala:137:46]
wire _deny_access_to_debug_T_5 = _deny_access_to_debug_T_4 == 41'h0; // @[Parameters.scala:137:{46,59}]
wire deny_access_to_debug = _deny_access_to_debug_T & _deny_access_to_debug_T_5; // @[TLB.scala:428:{39,50}]
wire _prot_r_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33]
wire _prot_r_T_1 = _pma_io_resp_r & _prot_r_T; // @[TLB.scala:422:19, :429:{30,33}]
wire prot_r = _prot_r_T_1 & _pmp_io_r; // @[TLB.scala:416:19, :429:{30,55}]
wire newEntry_pr = prot_r; // @[TLB.scala:429:55, :449:24]
wire _prot_w_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :430:33]
wire _prot_w_T_1 = _pma_io_resp_w & _prot_w_T; // @[TLB.scala:422:19, :430:{30,33}]
wire prot_w = _prot_w_T_1 & _pmp_io_w; // @[TLB.scala:416:19, :430:{30,55}]
wire newEntry_pw = prot_w; // @[TLB.scala:430:55, :449:24]
wire _prot_x_T = ~deny_access_to_debug; // @[TLB.scala:428:50, :429:33, :434:33]
wire _prot_x_T_1 = _pma_io_resp_x & _prot_x_T; // @[TLB.scala:422:19, :434:{30,33}]
wire prot_x = _prot_x_T_1 & _pmp_io_x; // @[TLB.scala:416:19, :434:{30,55}]
wire newEntry_px = prot_x; // @[TLB.scala:434:55, :449:24]
wire _GEN_4 = sectored_entries_0_0_valid_0 | sectored_entries_0_0_valid_1; // @[package.scala:81:59]
wire _sector_hits_T; // @[package.scala:81:59]
assign _sector_hits_T = _GEN_4; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T = _GEN_4; // @[package.scala:81:59]
wire _sector_hits_T_1 = _sector_hits_T | sectored_entries_0_0_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_2 = _sector_hits_T_1 | sectored_entries_0_0_valid_3; // @[package.scala:81:59]
wire [26:0] _T_176 = sectored_entries_0_0_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_3; // @[TLB.scala:174:61]
assign _sector_hits_T_3 = _T_176; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T; // @[TLB.scala:174:61]
assign _hitsVec_T = _T_176; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_4 = _sector_hits_T_3[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_5 = _sector_hits_T_4 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_6 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_7 = _sector_hits_T_5 & _sector_hits_T_6; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_0 = _sector_hits_T_2 & _sector_hits_T_7; // @[package.scala:81:59]
wire _GEN_5 = sectored_entries_0_1_valid_0 | sectored_entries_0_1_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_8; // @[package.scala:81:59]
assign _sector_hits_T_8 = _GEN_5; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_3; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_3 = _GEN_5; // @[package.scala:81:59]
wire _sector_hits_T_9 = _sector_hits_T_8 | sectored_entries_0_1_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_10 = _sector_hits_T_9 | sectored_entries_0_1_valid_3; // @[package.scala:81:59]
wire [26:0] _T_597 = sectored_entries_0_1_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_11; // @[TLB.scala:174:61]
assign _sector_hits_T_11 = _T_597; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_6; // @[TLB.scala:174:61]
assign _hitsVec_T_6 = _T_597; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_12 = _sector_hits_T_11[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_13 = _sector_hits_T_12 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_14 = ~sectored_entries_0_1_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_15 = _sector_hits_T_13 & _sector_hits_T_14; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_1 = _sector_hits_T_10 & _sector_hits_T_15; // @[package.scala:81:59]
wire _GEN_6 = sectored_entries_0_2_valid_0 | sectored_entries_0_2_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_16; // @[package.scala:81:59]
assign _sector_hits_T_16 = _GEN_6; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_6; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_6 = _GEN_6; // @[package.scala:81:59]
wire _sector_hits_T_17 = _sector_hits_T_16 | sectored_entries_0_2_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_18 = _sector_hits_T_17 | sectored_entries_0_2_valid_3; // @[package.scala:81:59]
wire [26:0] _T_1018 = sectored_entries_0_2_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_19; // @[TLB.scala:174:61]
assign _sector_hits_T_19 = _T_1018; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_12; // @[TLB.scala:174:61]
assign _hitsVec_T_12 = _T_1018; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_20 = _sector_hits_T_19[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_21 = _sector_hits_T_20 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_22 = ~sectored_entries_0_2_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_23 = _sector_hits_T_21 & _sector_hits_T_22; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_2 = _sector_hits_T_18 & _sector_hits_T_23; // @[package.scala:81:59]
wire _GEN_7 = sectored_entries_0_3_valid_0 | sectored_entries_0_3_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_24; // @[package.scala:81:59]
assign _sector_hits_T_24 = _GEN_7; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_9; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_9 = _GEN_7; // @[package.scala:81:59]
wire _sector_hits_T_25 = _sector_hits_T_24 | sectored_entries_0_3_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_26 = _sector_hits_T_25 | sectored_entries_0_3_valid_3; // @[package.scala:81:59]
wire [26:0] _T_1439 = sectored_entries_0_3_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_27; // @[TLB.scala:174:61]
assign _sector_hits_T_27 = _T_1439; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_18; // @[TLB.scala:174:61]
assign _hitsVec_T_18 = _T_1439; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_28 = _sector_hits_T_27[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_29 = _sector_hits_T_28 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_30 = ~sectored_entries_0_3_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_31 = _sector_hits_T_29 & _sector_hits_T_30; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_3 = _sector_hits_T_26 & _sector_hits_T_31; // @[package.scala:81:59]
wire _GEN_8 = sectored_entries_0_4_valid_0 | sectored_entries_0_4_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_32; // @[package.scala:81:59]
assign _sector_hits_T_32 = _GEN_8; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_12; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_12 = _GEN_8; // @[package.scala:81:59]
wire _sector_hits_T_33 = _sector_hits_T_32 | sectored_entries_0_4_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_34 = _sector_hits_T_33 | sectored_entries_0_4_valid_3; // @[package.scala:81:59]
wire [26:0] _T_1860 = sectored_entries_0_4_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_35; // @[TLB.scala:174:61]
assign _sector_hits_T_35 = _T_1860; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_24; // @[TLB.scala:174:61]
assign _hitsVec_T_24 = _T_1860; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_36 = _sector_hits_T_35[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_37 = _sector_hits_T_36 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_38 = ~sectored_entries_0_4_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_39 = _sector_hits_T_37 & _sector_hits_T_38; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_4 = _sector_hits_T_34 & _sector_hits_T_39; // @[package.scala:81:59]
wire _GEN_9 = sectored_entries_0_5_valid_0 | sectored_entries_0_5_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_40; // @[package.scala:81:59]
assign _sector_hits_T_40 = _GEN_9; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_15; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_15 = _GEN_9; // @[package.scala:81:59]
wire _sector_hits_T_41 = _sector_hits_T_40 | sectored_entries_0_5_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_42 = _sector_hits_T_41 | sectored_entries_0_5_valid_3; // @[package.scala:81:59]
wire [26:0] _T_2281 = sectored_entries_0_5_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_43; // @[TLB.scala:174:61]
assign _sector_hits_T_43 = _T_2281; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_30; // @[TLB.scala:174:61]
assign _hitsVec_T_30 = _T_2281; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_44 = _sector_hits_T_43[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_45 = _sector_hits_T_44 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_46 = ~sectored_entries_0_5_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_47 = _sector_hits_T_45 & _sector_hits_T_46; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_5 = _sector_hits_T_42 & _sector_hits_T_47; // @[package.scala:81:59]
wire _GEN_10 = sectored_entries_0_6_valid_0 | sectored_entries_0_6_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_48; // @[package.scala:81:59]
assign _sector_hits_T_48 = _GEN_10; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_18; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_18 = _GEN_10; // @[package.scala:81:59]
wire _sector_hits_T_49 = _sector_hits_T_48 | sectored_entries_0_6_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_50 = _sector_hits_T_49 | sectored_entries_0_6_valid_3; // @[package.scala:81:59]
wire [26:0] _T_2702 = sectored_entries_0_6_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_51; // @[TLB.scala:174:61]
assign _sector_hits_T_51 = _T_2702; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_36; // @[TLB.scala:174:61]
assign _hitsVec_T_36 = _T_2702; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_52 = _sector_hits_T_51[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_53 = _sector_hits_T_52 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_54 = ~sectored_entries_0_6_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_55 = _sector_hits_T_53 & _sector_hits_T_54; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_6 = _sector_hits_T_50 & _sector_hits_T_55; // @[package.scala:81:59]
wire _GEN_11 = sectored_entries_0_7_valid_0 | sectored_entries_0_7_valid_1; // @[package.scala:81:59]
wire _sector_hits_T_56; // @[package.scala:81:59]
assign _sector_hits_T_56 = _GEN_11; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_21; // @[package.scala:81:59]
assign _r_sectored_repl_addr_valids_T_21 = _GEN_11; // @[package.scala:81:59]
wire _sector_hits_T_57 = _sector_hits_T_56 | sectored_entries_0_7_valid_2; // @[package.scala:81:59]
wire _sector_hits_T_58 = _sector_hits_T_57 | sectored_entries_0_7_valid_3; // @[package.scala:81:59]
wire [26:0] _T_3123 = sectored_entries_0_7_tag_vpn ^ vpn; // @[TLB.scala:174:61, :335:30, :339:29]
wire [26:0] _sector_hits_T_59; // @[TLB.scala:174:61]
assign _sector_hits_T_59 = _T_3123; // @[TLB.scala:174:61]
wire [26:0] _hitsVec_T_42; // @[TLB.scala:174:61]
assign _hitsVec_T_42 = _T_3123; // @[TLB.scala:174:61]
wire [24:0] _sector_hits_T_60 = _sector_hits_T_59[26:2]; // @[TLB.scala:174:{61,68}]
wire _sector_hits_T_61 = _sector_hits_T_60 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _sector_hits_T_62 = ~sectored_entries_0_7_tag_v; // @[TLB.scala:174:105, :339:29]
wire _sector_hits_T_63 = _sector_hits_T_61 & _sector_hits_T_62; // @[TLB.scala:174:{86,95,105}]
wire sector_hits_7 = _sector_hits_T_58 & _sector_hits_T_63; // @[package.scala:81:59]
wire _superpage_hits_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30]
wire superpage_hits_tagMatch = superpage_entries_0_valid_0 & _superpage_hits_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30]
wire [26:0] _T_3446 = superpage_entries_0_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30]
wire [26:0] _superpage_hits_T; // @[TLB.scala:183:52]
assign _superpage_hits_T = _T_3446; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_5; // @[TLB.scala:183:52]
assign _superpage_hits_T_5 = _T_3446; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_10; // @[TLB.scala:183:52]
assign _superpage_hits_T_10 = _T_3446; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_48; // @[TLB.scala:183:52]
assign _hitsVec_T_48 = _T_3446; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_53; // @[TLB.scala:183:52]
assign _hitsVec_T_53 = _T_3446; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_58; // @[TLB.scala:183:52]
assign _hitsVec_T_58 = _T_3446; // @[TLB.scala:183:52]
wire [8:0] _superpage_hits_T_1 = _superpage_hits_T[26:18]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_2 = _superpage_hits_T_1 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_3 = _superpage_hits_T_2; // @[TLB.scala:183:{40,79}]
wire _superpage_hits_T_4 = superpage_hits_tagMatch & _superpage_hits_T_3; // @[TLB.scala:178:33, :183:{29,40}]
wire _GEN_12 = superpage_entries_0_level == 2'h0; // @[TLB.scala:182:28, :341:30]
wire _superpage_hits_ignore_T_1; // @[TLB.scala:182:28]
assign _superpage_hits_ignore_T_1 = _GEN_12; // @[TLB.scala:182:28]
wire _hitsVec_ignore_T_1; // @[TLB.scala:182:28]
assign _hitsVec_ignore_T_1 = _GEN_12; // @[TLB.scala:182:28]
wire _ppn_ignore_T; // @[TLB.scala:197:28]
assign _ppn_ignore_T = _GEN_12; // @[TLB.scala:182:28, :197:28]
wire _ignore_T_1; // @[TLB.scala:182:28]
assign _ignore_T_1 = _GEN_12; // @[TLB.scala:182:28]
wire superpage_hits_ignore_1 = _superpage_hits_ignore_T_1; // @[TLB.scala:182:{28,34}]
wire [8:0] _superpage_hits_T_6 = _superpage_hits_T_5[17:9]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_7 = _superpage_hits_T_6 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_8 = superpage_hits_ignore_1 | _superpage_hits_T_7; // @[TLB.scala:182:34, :183:{40,79}]
wire _superpage_hits_T_9 = _superpage_hits_T_4 & _superpage_hits_T_8; // @[TLB.scala:183:{29,40}]
wire superpage_hits_0 = _superpage_hits_T_9; // @[TLB.scala:183:29]
wire _superpage_hits_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _superpage_hits_T_11 = _superpage_hits_T_10[8:0]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_12 = _superpage_hits_T_11 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30]
wire superpage_hits_tagMatch_1 = superpage_entries_1_valid_0 & _superpage_hits_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30]
wire [26:0] _T_3544 = superpage_entries_1_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30]
wire [26:0] _superpage_hits_T_14; // @[TLB.scala:183:52]
assign _superpage_hits_T_14 = _T_3544; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_19; // @[TLB.scala:183:52]
assign _superpage_hits_T_19 = _T_3544; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_24; // @[TLB.scala:183:52]
assign _superpage_hits_T_24 = _T_3544; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_63; // @[TLB.scala:183:52]
assign _hitsVec_T_63 = _T_3544; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_68; // @[TLB.scala:183:52]
assign _hitsVec_T_68 = _T_3544; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_73; // @[TLB.scala:183:52]
assign _hitsVec_T_73 = _T_3544; // @[TLB.scala:183:52]
wire [8:0] _superpage_hits_T_15 = _superpage_hits_T_14[26:18]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_16 = _superpage_hits_T_15 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_17 = _superpage_hits_T_16; // @[TLB.scala:183:{40,79}]
wire _superpage_hits_T_18 = superpage_hits_tagMatch_1 & _superpage_hits_T_17; // @[TLB.scala:178:33, :183:{29,40}]
wire _GEN_13 = superpage_entries_1_level == 2'h0; // @[TLB.scala:182:28, :341:30]
wire _superpage_hits_ignore_T_4; // @[TLB.scala:182:28]
assign _superpage_hits_ignore_T_4 = _GEN_13; // @[TLB.scala:182:28]
wire _hitsVec_ignore_T_4; // @[TLB.scala:182:28]
assign _hitsVec_ignore_T_4 = _GEN_13; // @[TLB.scala:182:28]
wire _ppn_ignore_T_2; // @[TLB.scala:197:28]
assign _ppn_ignore_T_2 = _GEN_13; // @[TLB.scala:182:28, :197:28]
wire _ignore_T_4; // @[TLB.scala:182:28]
assign _ignore_T_4 = _GEN_13; // @[TLB.scala:182:28]
wire superpage_hits_ignore_4 = _superpage_hits_ignore_T_4; // @[TLB.scala:182:{28,34}]
wire [8:0] _superpage_hits_T_20 = _superpage_hits_T_19[17:9]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_21 = _superpage_hits_T_20 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_22 = superpage_hits_ignore_4 | _superpage_hits_T_21; // @[TLB.scala:182:34, :183:{40,79}]
wire _superpage_hits_T_23 = _superpage_hits_T_18 & _superpage_hits_T_22; // @[TLB.scala:183:{29,40}]
wire superpage_hits_1 = _superpage_hits_T_23; // @[TLB.scala:183:29]
wire _superpage_hits_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _superpage_hits_T_25 = _superpage_hits_T_24[8:0]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_26 = _superpage_hits_T_25 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30]
wire superpage_hits_tagMatch_2 = superpage_entries_2_valid_0 & _superpage_hits_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30]
wire [26:0] _T_3642 = superpage_entries_2_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30]
wire [26:0] _superpage_hits_T_28; // @[TLB.scala:183:52]
assign _superpage_hits_T_28 = _T_3642; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_33; // @[TLB.scala:183:52]
assign _superpage_hits_T_33 = _T_3642; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_38; // @[TLB.scala:183:52]
assign _superpage_hits_T_38 = _T_3642; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_78; // @[TLB.scala:183:52]
assign _hitsVec_T_78 = _T_3642; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_83; // @[TLB.scala:183:52]
assign _hitsVec_T_83 = _T_3642; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_88; // @[TLB.scala:183:52]
assign _hitsVec_T_88 = _T_3642; // @[TLB.scala:183:52]
wire [8:0] _superpage_hits_T_29 = _superpage_hits_T_28[26:18]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_30 = _superpage_hits_T_29 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_31 = _superpage_hits_T_30; // @[TLB.scala:183:{40,79}]
wire _superpage_hits_T_32 = superpage_hits_tagMatch_2 & _superpage_hits_T_31; // @[TLB.scala:178:33, :183:{29,40}]
wire _GEN_14 = superpage_entries_2_level == 2'h0; // @[TLB.scala:182:28, :341:30]
wire _superpage_hits_ignore_T_7; // @[TLB.scala:182:28]
assign _superpage_hits_ignore_T_7 = _GEN_14; // @[TLB.scala:182:28]
wire _hitsVec_ignore_T_7; // @[TLB.scala:182:28]
assign _hitsVec_ignore_T_7 = _GEN_14; // @[TLB.scala:182:28]
wire _ppn_ignore_T_4; // @[TLB.scala:197:28]
assign _ppn_ignore_T_4 = _GEN_14; // @[TLB.scala:182:28, :197:28]
wire _ignore_T_7; // @[TLB.scala:182:28]
assign _ignore_T_7 = _GEN_14; // @[TLB.scala:182:28]
wire superpage_hits_ignore_7 = _superpage_hits_ignore_T_7; // @[TLB.scala:182:{28,34}]
wire [8:0] _superpage_hits_T_34 = _superpage_hits_T_33[17:9]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_35 = _superpage_hits_T_34 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_36 = superpage_hits_ignore_7 | _superpage_hits_T_35; // @[TLB.scala:182:34, :183:{40,79}]
wire _superpage_hits_T_37 = _superpage_hits_T_32 & _superpage_hits_T_36; // @[TLB.scala:183:{29,40}]
wire superpage_hits_2 = _superpage_hits_T_37; // @[TLB.scala:183:29]
wire _superpage_hits_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _superpage_hits_T_39 = _superpage_hits_T_38[8:0]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_40 = _superpage_hits_T_39 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30]
wire superpage_hits_tagMatch_3 = superpage_entries_3_valid_0 & _superpage_hits_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30]
wire [26:0] _T_3740 = superpage_entries_3_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :341:30]
wire [26:0] _superpage_hits_T_42; // @[TLB.scala:183:52]
assign _superpage_hits_T_42 = _T_3740; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_47; // @[TLB.scala:183:52]
assign _superpage_hits_T_47 = _T_3740; // @[TLB.scala:183:52]
wire [26:0] _superpage_hits_T_52; // @[TLB.scala:183:52]
assign _superpage_hits_T_52 = _T_3740; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_93; // @[TLB.scala:183:52]
assign _hitsVec_T_93 = _T_3740; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_98; // @[TLB.scala:183:52]
assign _hitsVec_T_98 = _T_3740; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_103; // @[TLB.scala:183:52]
assign _hitsVec_T_103 = _T_3740; // @[TLB.scala:183:52]
wire [8:0] _superpage_hits_T_43 = _superpage_hits_T_42[26:18]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_44 = _superpage_hits_T_43 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_45 = _superpage_hits_T_44; // @[TLB.scala:183:{40,79}]
wire _superpage_hits_T_46 = superpage_hits_tagMatch_3 & _superpage_hits_T_45; // @[TLB.scala:178:33, :183:{29,40}]
wire _GEN_15 = superpage_entries_3_level == 2'h0; // @[TLB.scala:182:28, :341:30]
wire _superpage_hits_ignore_T_10; // @[TLB.scala:182:28]
assign _superpage_hits_ignore_T_10 = _GEN_15; // @[TLB.scala:182:28]
wire _hitsVec_ignore_T_10; // @[TLB.scala:182:28]
assign _hitsVec_ignore_T_10 = _GEN_15; // @[TLB.scala:182:28]
wire _ppn_ignore_T_6; // @[TLB.scala:197:28]
assign _ppn_ignore_T_6 = _GEN_15; // @[TLB.scala:182:28, :197:28]
wire _ignore_T_10; // @[TLB.scala:182:28]
assign _ignore_T_10 = _GEN_15; // @[TLB.scala:182:28]
wire superpage_hits_ignore_10 = _superpage_hits_ignore_T_10; // @[TLB.scala:182:{28,34}]
wire [8:0] _superpage_hits_T_48 = _superpage_hits_T_47[17:9]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_49 = _superpage_hits_T_48 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _superpage_hits_T_50 = superpage_hits_ignore_10 | _superpage_hits_T_49; // @[TLB.scala:182:34, :183:{40,79}]
wire _superpage_hits_T_51 = _superpage_hits_T_46 & _superpage_hits_T_50; // @[TLB.scala:183:{29,40}]
wire superpage_hits_3 = _superpage_hits_T_51; // @[TLB.scala:183:29]
wire _superpage_hits_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _superpage_hits_T_53 = _superpage_hits_T_52[8:0]; // @[TLB.scala:183:{52,58}]
wire _superpage_hits_T_54 = _superpage_hits_T_53 == 9'h0; // @[TLB.scala:183:{58,79}]
wire [1:0] hitsVec_idx = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_1 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_2 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_3 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_4 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_5 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_6 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] hitsVec_idx_7 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_24 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_48 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_72 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_96 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_120 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_144 = vpn[1:0]; // @[package.scala:163:13]
wire [1:0] _entries_T_168 = vpn[1:0]; // @[package.scala:163:13]
wire [24:0] _hitsVec_T_1 = _hitsVec_T[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_2 = _hitsVec_T_1 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_3 = ~sectored_entries_0_0_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_4 = _hitsVec_T_2 & _hitsVec_T_3; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_16 = {{sectored_entries_0_0_valid_3}, {sectored_entries_0_0_valid_2}, {sectored_entries_0_0_valid_1}, {sectored_entries_0_0_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_5 = _GEN_16[hitsVec_idx] & _hitsVec_T_4; // @[package.scala:163:13]
wire hitsVec_0 = vm_enabled & _hitsVec_T_5; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_7 = _hitsVec_T_6[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_8 = _hitsVec_T_7 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_9 = ~sectored_entries_0_1_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_10 = _hitsVec_T_8 & _hitsVec_T_9; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_17 = {{sectored_entries_0_1_valid_3}, {sectored_entries_0_1_valid_2}, {sectored_entries_0_1_valid_1}, {sectored_entries_0_1_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_11 = _GEN_17[hitsVec_idx_1] & _hitsVec_T_10; // @[package.scala:163:13]
wire hitsVec_1 = vm_enabled & _hitsVec_T_11; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_13 = _hitsVec_T_12[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_14 = _hitsVec_T_13 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_15 = ~sectored_entries_0_2_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_16 = _hitsVec_T_14 & _hitsVec_T_15; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_18 = {{sectored_entries_0_2_valid_3}, {sectored_entries_0_2_valid_2}, {sectored_entries_0_2_valid_1}, {sectored_entries_0_2_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_17 = _GEN_18[hitsVec_idx_2] & _hitsVec_T_16; // @[package.scala:163:13]
wire hitsVec_2 = vm_enabled & _hitsVec_T_17; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_19 = _hitsVec_T_18[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_20 = _hitsVec_T_19 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_21 = ~sectored_entries_0_3_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_22 = _hitsVec_T_20 & _hitsVec_T_21; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_19 = {{sectored_entries_0_3_valid_3}, {sectored_entries_0_3_valid_2}, {sectored_entries_0_3_valid_1}, {sectored_entries_0_3_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_23 = _GEN_19[hitsVec_idx_3] & _hitsVec_T_22; // @[package.scala:163:13]
wire hitsVec_3 = vm_enabled & _hitsVec_T_23; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_25 = _hitsVec_T_24[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_26 = _hitsVec_T_25 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_27 = ~sectored_entries_0_4_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_28 = _hitsVec_T_26 & _hitsVec_T_27; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_20 = {{sectored_entries_0_4_valid_3}, {sectored_entries_0_4_valid_2}, {sectored_entries_0_4_valid_1}, {sectored_entries_0_4_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_29 = _GEN_20[hitsVec_idx_4] & _hitsVec_T_28; // @[package.scala:163:13]
wire hitsVec_4 = vm_enabled & _hitsVec_T_29; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_31 = _hitsVec_T_30[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_32 = _hitsVec_T_31 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_33 = ~sectored_entries_0_5_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_34 = _hitsVec_T_32 & _hitsVec_T_33; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_21 = {{sectored_entries_0_5_valid_3}, {sectored_entries_0_5_valid_2}, {sectored_entries_0_5_valid_1}, {sectored_entries_0_5_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_35 = _GEN_21[hitsVec_idx_5] & _hitsVec_T_34; // @[package.scala:163:13]
wire hitsVec_5 = vm_enabled & _hitsVec_T_35; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_37 = _hitsVec_T_36[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_38 = _hitsVec_T_37 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_39 = ~sectored_entries_0_6_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_40 = _hitsVec_T_38 & _hitsVec_T_39; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_22 = {{sectored_entries_0_6_valid_3}, {sectored_entries_0_6_valid_2}, {sectored_entries_0_6_valid_1}, {sectored_entries_0_6_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_41 = _GEN_22[hitsVec_idx_6] & _hitsVec_T_40; // @[package.scala:163:13]
wire hitsVec_6 = vm_enabled & _hitsVec_T_41; // @[TLB.scala:188:18, :399:61, :440:44]
wire [24:0] _hitsVec_T_43 = _hitsVec_T_42[26:2]; // @[TLB.scala:174:{61,68}]
wire _hitsVec_T_44 = _hitsVec_T_43 == 25'h0; // @[TLB.scala:174:{68,86}]
wire _hitsVec_T_45 = ~sectored_entries_0_7_tag_v; // @[TLB.scala:174:105, :339:29]
wire _hitsVec_T_46 = _hitsVec_T_44 & _hitsVec_T_45; // @[TLB.scala:174:{86,95,105}]
wire [3:0] _GEN_23 = {{sectored_entries_0_7_valid_3}, {sectored_entries_0_7_valid_2}, {sectored_entries_0_7_valid_1}, {sectored_entries_0_7_valid_0}}; // @[TLB.scala:188:18, :339:29]
wire _hitsVec_T_47 = _GEN_23[hitsVec_idx_7] & _hitsVec_T_46; // @[package.scala:163:13]
wire hitsVec_7 = vm_enabled & _hitsVec_T_47; // @[TLB.scala:188:18, :399:61, :440:44]
wire _hitsVec_tagMatch_T = ~superpage_entries_0_tag_v; // @[TLB.scala:178:43, :341:30]
wire hitsVec_tagMatch = superpage_entries_0_valid_0 & _hitsVec_tagMatch_T; // @[TLB.scala:178:{33,43}, :341:30]
wire [8:0] _hitsVec_T_49 = _hitsVec_T_48[26:18]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_50 = _hitsVec_T_49 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_51 = _hitsVec_T_50; // @[TLB.scala:183:{40,79}]
wire _hitsVec_T_52 = hitsVec_tagMatch & _hitsVec_T_51; // @[TLB.scala:178:33, :183:{29,40}]
wire hitsVec_ignore_1 = _hitsVec_ignore_T_1; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_54 = _hitsVec_T_53[17:9]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_55 = _hitsVec_T_54 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_56 = hitsVec_ignore_1 | _hitsVec_T_55; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_57 = _hitsVec_T_52 & _hitsVec_T_56; // @[TLB.scala:183:{29,40}]
wire _hitsVec_T_62 = _hitsVec_T_57; // @[TLB.scala:183:29]
wire _hitsVec_ignore_T_2 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _hitsVec_T_59 = _hitsVec_T_58[8:0]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_60 = _hitsVec_T_59 == 9'h0; // @[TLB.scala:183:{58,79}]
wire hitsVec_8 = vm_enabled & _hitsVec_T_62; // @[TLB.scala:183:29, :399:61, :440:44]
wire _hitsVec_tagMatch_T_1 = ~superpage_entries_1_tag_v; // @[TLB.scala:178:43, :341:30]
wire hitsVec_tagMatch_1 = superpage_entries_1_valid_0 & _hitsVec_tagMatch_T_1; // @[TLB.scala:178:{33,43}, :341:30]
wire [8:0] _hitsVec_T_64 = _hitsVec_T_63[26:18]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_65 = _hitsVec_T_64 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_66 = _hitsVec_T_65; // @[TLB.scala:183:{40,79}]
wire _hitsVec_T_67 = hitsVec_tagMatch_1 & _hitsVec_T_66; // @[TLB.scala:178:33, :183:{29,40}]
wire hitsVec_ignore_4 = _hitsVec_ignore_T_4; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_69 = _hitsVec_T_68[17:9]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_70 = _hitsVec_T_69 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_71 = hitsVec_ignore_4 | _hitsVec_T_70; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_72 = _hitsVec_T_67 & _hitsVec_T_71; // @[TLB.scala:183:{29,40}]
wire _hitsVec_T_77 = _hitsVec_T_72; // @[TLB.scala:183:29]
wire _hitsVec_ignore_T_5 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _hitsVec_T_74 = _hitsVec_T_73[8:0]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_75 = _hitsVec_T_74 == 9'h0; // @[TLB.scala:183:{58,79}]
wire hitsVec_9 = vm_enabled & _hitsVec_T_77; // @[TLB.scala:183:29, :399:61, :440:44]
wire _hitsVec_tagMatch_T_2 = ~superpage_entries_2_tag_v; // @[TLB.scala:178:43, :341:30]
wire hitsVec_tagMatch_2 = superpage_entries_2_valid_0 & _hitsVec_tagMatch_T_2; // @[TLB.scala:178:{33,43}, :341:30]
wire [8:0] _hitsVec_T_79 = _hitsVec_T_78[26:18]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_80 = _hitsVec_T_79 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_81 = _hitsVec_T_80; // @[TLB.scala:183:{40,79}]
wire _hitsVec_T_82 = hitsVec_tagMatch_2 & _hitsVec_T_81; // @[TLB.scala:178:33, :183:{29,40}]
wire hitsVec_ignore_7 = _hitsVec_ignore_T_7; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_84 = _hitsVec_T_83[17:9]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_85 = _hitsVec_T_84 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_86 = hitsVec_ignore_7 | _hitsVec_T_85; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_87 = _hitsVec_T_82 & _hitsVec_T_86; // @[TLB.scala:183:{29,40}]
wire _hitsVec_T_92 = _hitsVec_T_87; // @[TLB.scala:183:29]
wire _hitsVec_ignore_T_8 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _hitsVec_T_89 = _hitsVec_T_88[8:0]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_90 = _hitsVec_T_89 == 9'h0; // @[TLB.scala:183:{58,79}]
wire hitsVec_10 = vm_enabled & _hitsVec_T_92; // @[TLB.scala:183:29, :399:61, :440:44]
wire _hitsVec_tagMatch_T_3 = ~superpage_entries_3_tag_v; // @[TLB.scala:178:43, :341:30]
wire hitsVec_tagMatch_3 = superpage_entries_3_valid_0 & _hitsVec_tagMatch_T_3; // @[TLB.scala:178:{33,43}, :341:30]
wire [8:0] _hitsVec_T_94 = _hitsVec_T_93[26:18]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_95 = _hitsVec_T_94 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_96 = _hitsVec_T_95; // @[TLB.scala:183:{40,79}]
wire _hitsVec_T_97 = hitsVec_tagMatch_3 & _hitsVec_T_96; // @[TLB.scala:178:33, :183:{29,40}]
wire hitsVec_ignore_10 = _hitsVec_ignore_T_10; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_99 = _hitsVec_T_98[17:9]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_100 = _hitsVec_T_99 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_101 = hitsVec_ignore_10 | _hitsVec_T_100; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_102 = _hitsVec_T_97 & _hitsVec_T_101; // @[TLB.scala:183:{29,40}]
wire _hitsVec_T_107 = _hitsVec_T_102; // @[TLB.scala:183:29]
wire _hitsVec_ignore_T_11 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :341:30]
wire [8:0] _hitsVec_T_104 = _hitsVec_T_103[8:0]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_105 = _hitsVec_T_104 == 9'h0; // @[TLB.scala:183:{58,79}]
wire hitsVec_11 = vm_enabled & _hitsVec_T_107; // @[TLB.scala:183:29, :399:61, :440:44]
wire _hitsVec_tagMatch_T_4 = ~special_entry_tag_v; // @[TLB.scala:178:43, :346:56]
wire hitsVec_tagMatch_4 = special_entry_valid_0 & _hitsVec_tagMatch_T_4; // @[TLB.scala:178:{33,43}, :346:56]
wire [26:0] _T_3838 = special_entry_tag_vpn ^ vpn; // @[TLB.scala:183:52, :335:30, :346:56]
wire [26:0] _hitsVec_T_108; // @[TLB.scala:183:52]
assign _hitsVec_T_108 = _T_3838; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_113; // @[TLB.scala:183:52]
assign _hitsVec_T_113 = _T_3838; // @[TLB.scala:183:52]
wire [26:0] _hitsVec_T_118; // @[TLB.scala:183:52]
assign _hitsVec_T_118 = _T_3838; // @[TLB.scala:183:52]
wire [8:0] _hitsVec_T_109 = _hitsVec_T_108[26:18]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_110 = _hitsVec_T_109 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_111 = _hitsVec_T_110; // @[TLB.scala:183:{40,79}]
wire _hitsVec_T_112 = hitsVec_tagMatch_4 & _hitsVec_T_111; // @[TLB.scala:178:33, :183:{29,40}]
wire hitsVec_ignore_13 = _hitsVec_ignore_T_13; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_114 = _hitsVec_T_113[17:9]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_115 = _hitsVec_T_114 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_116 = hitsVec_ignore_13 | _hitsVec_T_115; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_117 = _hitsVec_T_112 & _hitsVec_T_116; // @[TLB.scala:183:{29,40}]
wire _hitsVec_ignore_T_14 = ~(special_entry_level[1]); // @[TLB.scala:182:28, :197:28, :346:56]
wire hitsVec_ignore_14 = _hitsVec_ignore_T_14; // @[TLB.scala:182:{28,34}]
wire [8:0] _hitsVec_T_119 = _hitsVec_T_118[8:0]; // @[TLB.scala:183:{52,58}]
wire _hitsVec_T_120 = _hitsVec_T_119 == 9'h0; // @[TLB.scala:183:{58,79}]
wire _hitsVec_T_121 = hitsVec_ignore_14 | _hitsVec_T_120; // @[TLB.scala:182:34, :183:{40,79}]
wire _hitsVec_T_122 = _hitsVec_T_117 & _hitsVec_T_121; // @[TLB.scala:183:{29,40}]
wire hitsVec_12 = vm_enabled & _hitsVec_T_122; // @[TLB.scala:183:29, :399:61, :440:44]
wire [1:0] real_hits_lo_lo_hi = {hitsVec_2, hitsVec_1}; // @[package.scala:45:27]
wire [2:0] real_hits_lo_lo = {real_hits_lo_lo_hi, hitsVec_0}; // @[package.scala:45:27]
wire [1:0] real_hits_lo_hi_hi = {hitsVec_5, hitsVec_4}; // @[package.scala:45:27]
wire [2:0] real_hits_lo_hi = {real_hits_lo_hi_hi, hitsVec_3}; // @[package.scala:45:27]
wire [5:0] real_hits_lo = {real_hits_lo_hi, real_hits_lo_lo}; // @[package.scala:45:27]
wire [1:0] real_hits_hi_lo_hi = {hitsVec_8, hitsVec_7}; // @[package.scala:45:27]
wire [2:0] real_hits_hi_lo = {real_hits_hi_lo_hi, hitsVec_6}; // @[package.scala:45:27]
wire [1:0] real_hits_hi_hi_lo = {hitsVec_10, hitsVec_9}; // @[package.scala:45:27]
wire [1:0] real_hits_hi_hi_hi = {hitsVec_12, hitsVec_11}; // @[package.scala:45:27]
wire [3:0] real_hits_hi_hi = {real_hits_hi_hi_hi, real_hits_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] real_hits_hi = {real_hits_hi_hi, real_hits_hi_lo}; // @[package.scala:45:27]
wire [12:0] real_hits = {real_hits_hi, real_hits_lo}; // @[package.scala:45:27]
wire [12:0] _tlb_hit_T = real_hits; // @[package.scala:45:27]
wire _hits_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18]
wire [13:0] hits = {_hits_T, real_hits}; // @[package.scala:45:27]
wire _newEntry_g_T; // @[TLB.scala:453:25]
wire _newEntry_sw_T_6; // @[PTW.scala:151:40]
wire _newEntry_sx_T_5; // @[PTW.scala:153:35]
wire _newEntry_sr_T_5; // @[PTW.scala:149:35]
wire newEntry_g; // @[TLB.scala:449:24]
wire newEntry_sw; // @[TLB.scala:449:24]
wire newEntry_sx; // @[TLB.scala:449:24]
wire newEntry_sr; // @[TLB.scala:449:24]
wire newEntry_ppp; // @[TLB.scala:449:24]
wire newEntry_pal; // @[TLB.scala:449:24]
wire newEntry_paa; // @[TLB.scala:449:24]
wire newEntry_eff; // @[TLB.scala:449:24]
assign _newEntry_g_T = io_ptw_resp_bits_pte_g_0 & io_ptw_resp_bits_pte_v_0; // @[TLB.scala:318:7, :453:25]
assign newEntry_g = _newEntry_g_T; // @[TLB.scala:449:24, :453:25]
wire _newEntry_ae_stage2_T = io_ptw_resp_bits_ae_final_0 & io_ptw_resp_bits_gpa_is_pte_0; // @[TLB.scala:318:7, :456:53]
wire _newEntry_sr_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
wire _newEntry_sr_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sr_T; // @[TLB.scala:318:7]
wire _newEntry_sr_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sr_T_1; // @[TLB.scala:318:7]
wire _newEntry_sr_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sr_T_2; // @[TLB.scala:318:7]
wire _newEntry_sr_T_4 = _newEntry_sr_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7]
assign _newEntry_sr_T_5 = _newEntry_sr_T_4 & io_ptw_resp_bits_pte_r_0; // @[TLB.scala:318:7]
assign newEntry_sr = _newEntry_sr_T_5; // @[TLB.scala:449:24]
wire _newEntry_sw_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
wire _newEntry_sw_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sw_T; // @[TLB.scala:318:7]
wire _newEntry_sw_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sw_T_1; // @[TLB.scala:318:7]
wire _newEntry_sw_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sw_T_2; // @[TLB.scala:318:7]
wire _newEntry_sw_T_4 = _newEntry_sw_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7]
wire _newEntry_sw_T_5 = _newEntry_sw_T_4 & io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
assign _newEntry_sw_T_6 = _newEntry_sw_T_5 & io_ptw_resp_bits_pte_d_0; // @[TLB.scala:318:7]
assign newEntry_sw = _newEntry_sw_T_6; // @[TLB.scala:449:24]
wire _newEntry_sx_T = ~io_ptw_resp_bits_pte_w_0; // @[TLB.scala:318:7]
wire _newEntry_sx_T_1 = io_ptw_resp_bits_pte_x_0 & _newEntry_sx_T; // @[TLB.scala:318:7]
wire _newEntry_sx_T_2 = io_ptw_resp_bits_pte_r_0 | _newEntry_sx_T_1; // @[TLB.scala:318:7]
wire _newEntry_sx_T_3 = io_ptw_resp_bits_pte_v_0 & _newEntry_sx_T_2; // @[TLB.scala:318:7]
wire _newEntry_sx_T_4 = _newEntry_sx_T_3 & io_ptw_resp_bits_pte_a_0; // @[TLB.scala:318:7]
assign _newEntry_sx_T_5 = _newEntry_sx_T_4 & io_ptw_resp_bits_pte_x_0; // @[TLB.scala:318:7]
assign newEntry_sx = _newEntry_sx_T_5; // @[TLB.scala:449:24]
wire [1:0] _GEN_24 = {newEntry_c, 1'h0}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_lo_lo_lo; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_lo_lo_lo; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_lo_lo_lo = _GEN_24; // @[TLB.scala:217:24]
wire [1:0] _GEN_25 = {newEntry_pal, newEntry_paa}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_lo_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_lo_lo_hi_hi = _GEN_25; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_lo_lo_hi = {special_entry_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] special_entry_data_0_lo_lo = {special_entry_data_0_lo_lo_hi, special_entry_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [1:0] _GEN_26 = {newEntry_px, newEntry_pr}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_lo_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_lo_hi_lo_hi = _GEN_26; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_lo_hi_lo = {special_entry_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [1:0] _GEN_27 = {newEntry_hx, newEntry_hr}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_lo_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_lo_hi_hi_hi = _GEN_27; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_lo_hi_hi = {special_entry_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] special_entry_data_0_lo_hi = {special_entry_data_0_lo_hi_hi, special_entry_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] special_entry_data_0_lo = {special_entry_data_0_lo_hi, special_entry_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [1:0] _GEN_28 = {newEntry_sx, newEntry_sr}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_hi_lo_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_hi_lo_lo_hi = _GEN_28; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_hi_lo_lo = {special_entry_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [1:0] _GEN_29 = {newEntry_pf, newEntry_gf}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_hi_lo_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_hi_lo_hi_hi = _GEN_29; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_hi_lo_hi = {special_entry_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] special_entry_data_0_hi_lo = {special_entry_data_0_hi_lo_hi, special_entry_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [1:0] _GEN_30 = {newEntry_ae_ptw, newEntry_ae_final}; // @[TLB.scala:217:24, :449:24]
wire [1:0] special_entry_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_0_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_1_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_2_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] superpage_entries_3_data_0_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_0_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_1_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_2_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_3_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_4_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_5_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_6_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [1:0] sectored_entries_0_7_data_hi_hi_lo_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_hi_hi_lo_hi = _GEN_30; // @[TLB.scala:217:24]
wire [2:0] special_entry_data_0_hi_hi_lo = {special_entry_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [20:0] _GEN_31 = {newEntry_ppn, newEntry_u}; // @[TLB.scala:217:24, :449:24]
wire [20:0] special_entry_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign special_entry_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_0_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_0_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_1_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_1_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_2_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_2_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] superpage_entries_3_data_0_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign superpage_entries_3_data_0_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_0_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_0_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_1_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_1_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_2_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_2_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_3_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_3_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_4_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_4_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_5_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_5_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_6_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_6_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [20:0] sectored_entries_0_7_data_hi_hi_hi_hi; // @[TLB.scala:217:24]
assign sectored_entries_0_7_data_hi_hi_hi_hi = _GEN_31; // @[TLB.scala:217:24]
wire [21:0] special_entry_data_0_hi_hi_hi = {special_entry_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] special_entry_data_0_hi_hi = {special_entry_data_0_hi_hi_hi, special_entry_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] special_entry_data_0_hi = {special_entry_data_0_hi_hi, special_entry_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _special_entry_data_0_T = {special_entry_data_0_hi, special_entry_data_0_lo}; // @[TLB.scala:217:24]
wire _superpage_entries_0_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire _superpage_entries_1_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire _superpage_entries_2_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire _superpage_entries_3_level_T = io_ptw_resp_bits_level_0[0]; // @[package.scala:163:13]
wire [2:0] superpage_entries_0_data_0_lo_lo_hi = {superpage_entries_0_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_0_data_0_lo_lo = {superpage_entries_0_data_0_lo_lo_hi, superpage_entries_0_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_0_data_0_lo_hi_lo = {superpage_entries_0_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_0_data_0_lo_hi_hi = {superpage_entries_0_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_0_data_0_lo_hi = {superpage_entries_0_data_0_lo_hi_hi, superpage_entries_0_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_0_data_0_lo = {superpage_entries_0_data_0_lo_hi, superpage_entries_0_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_0_data_0_hi_lo_lo = {superpage_entries_0_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_0_data_0_hi_lo_hi = {superpage_entries_0_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_0_data_0_hi_lo = {superpage_entries_0_data_0_hi_lo_hi, superpage_entries_0_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_0_data_0_hi_hi_lo = {superpage_entries_0_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] superpage_entries_0_data_0_hi_hi_hi = {superpage_entries_0_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_0_data_0_hi_hi = {superpage_entries_0_data_0_hi_hi_hi, superpage_entries_0_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_0_data_0_hi = {superpage_entries_0_data_0_hi_hi, superpage_entries_0_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_0_data_0_T = {superpage_entries_0_data_0_hi, superpage_entries_0_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_1_data_0_lo_lo_hi = {superpage_entries_1_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_1_data_0_lo_lo = {superpage_entries_1_data_0_lo_lo_hi, superpage_entries_1_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_1_data_0_lo_hi_lo = {superpage_entries_1_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_1_data_0_lo_hi_hi = {superpage_entries_1_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_1_data_0_lo_hi = {superpage_entries_1_data_0_lo_hi_hi, superpage_entries_1_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_1_data_0_lo = {superpage_entries_1_data_0_lo_hi, superpage_entries_1_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_1_data_0_hi_lo_lo = {superpage_entries_1_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_1_data_0_hi_lo_hi = {superpage_entries_1_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_1_data_0_hi_lo = {superpage_entries_1_data_0_hi_lo_hi, superpage_entries_1_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_1_data_0_hi_hi_lo = {superpage_entries_1_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] superpage_entries_1_data_0_hi_hi_hi = {superpage_entries_1_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_1_data_0_hi_hi = {superpage_entries_1_data_0_hi_hi_hi, superpage_entries_1_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_1_data_0_hi = {superpage_entries_1_data_0_hi_hi, superpage_entries_1_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_1_data_0_T = {superpage_entries_1_data_0_hi, superpage_entries_1_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_2_data_0_lo_lo_hi = {superpage_entries_2_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_2_data_0_lo_lo = {superpage_entries_2_data_0_lo_lo_hi, superpage_entries_2_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_2_data_0_lo_hi_lo = {superpage_entries_2_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_2_data_0_lo_hi_hi = {superpage_entries_2_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_2_data_0_lo_hi = {superpage_entries_2_data_0_lo_hi_hi, superpage_entries_2_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_2_data_0_lo = {superpage_entries_2_data_0_lo_hi, superpage_entries_2_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_2_data_0_hi_lo_lo = {superpage_entries_2_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_2_data_0_hi_lo_hi = {superpage_entries_2_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_2_data_0_hi_lo = {superpage_entries_2_data_0_hi_lo_hi, superpage_entries_2_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_2_data_0_hi_hi_lo = {superpage_entries_2_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] superpage_entries_2_data_0_hi_hi_hi = {superpage_entries_2_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_2_data_0_hi_hi = {superpage_entries_2_data_0_hi_hi_hi, superpage_entries_2_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_2_data_0_hi = {superpage_entries_2_data_0_hi_hi, superpage_entries_2_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_2_data_0_T = {superpage_entries_2_data_0_hi, superpage_entries_2_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_3_data_0_lo_lo_hi = {superpage_entries_3_data_0_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] superpage_entries_3_data_0_lo_lo = {superpage_entries_3_data_0_lo_lo_hi, superpage_entries_3_data_0_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_3_data_0_lo_hi_lo = {superpage_entries_3_data_0_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_3_data_0_lo_hi_hi = {superpage_entries_3_data_0_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_3_data_0_lo_hi = {superpage_entries_3_data_0_lo_hi_hi, superpage_entries_3_data_0_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] superpage_entries_3_data_0_lo = {superpage_entries_3_data_0_lo_hi, superpage_entries_3_data_0_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_3_data_0_hi_lo_lo = {superpage_entries_3_data_0_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] superpage_entries_3_data_0_hi_lo_hi = {superpage_entries_3_data_0_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] superpage_entries_3_data_0_hi_lo = {superpage_entries_3_data_0_hi_lo_hi, superpage_entries_3_data_0_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] superpage_entries_3_data_0_hi_hi_lo = {superpage_entries_3_data_0_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] superpage_entries_3_data_0_hi_hi_hi = {superpage_entries_3_data_0_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] superpage_entries_3_data_0_hi_hi = {superpage_entries_3_data_0_hi_hi_hi, superpage_entries_3_data_0_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] superpage_entries_3_data_0_hi = {superpage_entries_3_data_0_hi_hi, superpage_entries_3_data_0_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _superpage_entries_3_data_0_T = {superpage_entries_3_data_0_hi, superpage_entries_3_data_0_lo}; // @[TLB.scala:217:24]
wire [2:0] waddr_1 = r_sectored_hit_valid ? r_sectored_hit_bits : r_sectored_repl_addr; // @[TLB.scala:356:33, :357:27, :485:22]
wire [1:0] idx = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_1 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_2 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_3 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_4 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_5 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_6 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [1:0] idx_7 = r_refill_tag[1:0]; // @[package.scala:163:13]
wire [2:0] sectored_entries_0_0_data_lo_lo_hi = {sectored_entries_0_0_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_0_data_lo_lo = {sectored_entries_0_0_data_lo_lo_hi, sectored_entries_0_0_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_0_data_lo_hi_lo = {sectored_entries_0_0_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_0_data_lo_hi_hi = {sectored_entries_0_0_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_0_data_lo_hi = {sectored_entries_0_0_data_lo_hi_hi, sectored_entries_0_0_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_0_data_lo = {sectored_entries_0_0_data_lo_hi, sectored_entries_0_0_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_0_data_hi_lo_lo = {sectored_entries_0_0_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_0_data_hi_lo_hi = {sectored_entries_0_0_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_0_data_hi_lo = {sectored_entries_0_0_data_hi_lo_hi, sectored_entries_0_0_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_0_data_hi_hi_lo = {sectored_entries_0_0_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_0_data_hi_hi_hi = {sectored_entries_0_0_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_0_data_hi_hi = {sectored_entries_0_0_data_hi_hi_hi, sectored_entries_0_0_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_0_data_hi = {sectored_entries_0_0_data_hi_hi, sectored_entries_0_0_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_0_data_T = {sectored_entries_0_0_data_hi, sectored_entries_0_0_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_1_data_lo_lo_hi = {sectored_entries_0_1_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_1_data_lo_lo = {sectored_entries_0_1_data_lo_lo_hi, sectored_entries_0_1_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_1_data_lo_hi_lo = {sectored_entries_0_1_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_1_data_lo_hi_hi = {sectored_entries_0_1_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_1_data_lo_hi = {sectored_entries_0_1_data_lo_hi_hi, sectored_entries_0_1_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_1_data_lo = {sectored_entries_0_1_data_lo_hi, sectored_entries_0_1_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_1_data_hi_lo_lo = {sectored_entries_0_1_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_1_data_hi_lo_hi = {sectored_entries_0_1_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_1_data_hi_lo = {sectored_entries_0_1_data_hi_lo_hi, sectored_entries_0_1_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_1_data_hi_hi_lo = {sectored_entries_0_1_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_1_data_hi_hi_hi = {sectored_entries_0_1_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_1_data_hi_hi = {sectored_entries_0_1_data_hi_hi_hi, sectored_entries_0_1_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_1_data_hi = {sectored_entries_0_1_data_hi_hi, sectored_entries_0_1_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_1_data_T = {sectored_entries_0_1_data_hi, sectored_entries_0_1_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_2_data_lo_lo_hi = {sectored_entries_0_2_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_2_data_lo_lo = {sectored_entries_0_2_data_lo_lo_hi, sectored_entries_0_2_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_2_data_lo_hi_lo = {sectored_entries_0_2_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_2_data_lo_hi_hi = {sectored_entries_0_2_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_2_data_lo_hi = {sectored_entries_0_2_data_lo_hi_hi, sectored_entries_0_2_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_2_data_lo = {sectored_entries_0_2_data_lo_hi, sectored_entries_0_2_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_2_data_hi_lo_lo = {sectored_entries_0_2_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_2_data_hi_lo_hi = {sectored_entries_0_2_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_2_data_hi_lo = {sectored_entries_0_2_data_hi_lo_hi, sectored_entries_0_2_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_2_data_hi_hi_lo = {sectored_entries_0_2_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_2_data_hi_hi_hi = {sectored_entries_0_2_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_2_data_hi_hi = {sectored_entries_0_2_data_hi_hi_hi, sectored_entries_0_2_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_2_data_hi = {sectored_entries_0_2_data_hi_hi, sectored_entries_0_2_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_2_data_T = {sectored_entries_0_2_data_hi, sectored_entries_0_2_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_3_data_lo_lo_hi = {sectored_entries_0_3_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_3_data_lo_lo = {sectored_entries_0_3_data_lo_lo_hi, sectored_entries_0_3_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_3_data_lo_hi_lo = {sectored_entries_0_3_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_3_data_lo_hi_hi = {sectored_entries_0_3_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_3_data_lo_hi = {sectored_entries_0_3_data_lo_hi_hi, sectored_entries_0_3_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_3_data_lo = {sectored_entries_0_3_data_lo_hi, sectored_entries_0_3_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_3_data_hi_lo_lo = {sectored_entries_0_3_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_3_data_hi_lo_hi = {sectored_entries_0_3_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_3_data_hi_lo = {sectored_entries_0_3_data_hi_lo_hi, sectored_entries_0_3_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_3_data_hi_hi_lo = {sectored_entries_0_3_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_3_data_hi_hi_hi = {sectored_entries_0_3_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_3_data_hi_hi = {sectored_entries_0_3_data_hi_hi_hi, sectored_entries_0_3_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_3_data_hi = {sectored_entries_0_3_data_hi_hi, sectored_entries_0_3_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_3_data_T = {sectored_entries_0_3_data_hi, sectored_entries_0_3_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_4_data_lo_lo_hi = {sectored_entries_0_4_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_4_data_lo_lo = {sectored_entries_0_4_data_lo_lo_hi, sectored_entries_0_4_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_4_data_lo_hi_lo = {sectored_entries_0_4_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_4_data_lo_hi_hi = {sectored_entries_0_4_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_4_data_lo_hi = {sectored_entries_0_4_data_lo_hi_hi, sectored_entries_0_4_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_4_data_lo = {sectored_entries_0_4_data_lo_hi, sectored_entries_0_4_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_4_data_hi_lo_lo = {sectored_entries_0_4_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_4_data_hi_lo_hi = {sectored_entries_0_4_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_4_data_hi_lo = {sectored_entries_0_4_data_hi_lo_hi, sectored_entries_0_4_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_4_data_hi_hi_lo = {sectored_entries_0_4_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_4_data_hi_hi_hi = {sectored_entries_0_4_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_4_data_hi_hi = {sectored_entries_0_4_data_hi_hi_hi, sectored_entries_0_4_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_4_data_hi = {sectored_entries_0_4_data_hi_hi, sectored_entries_0_4_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_4_data_T = {sectored_entries_0_4_data_hi, sectored_entries_0_4_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_5_data_lo_lo_hi = {sectored_entries_0_5_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_5_data_lo_lo = {sectored_entries_0_5_data_lo_lo_hi, sectored_entries_0_5_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_5_data_lo_hi_lo = {sectored_entries_0_5_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_5_data_lo_hi_hi = {sectored_entries_0_5_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_5_data_lo_hi = {sectored_entries_0_5_data_lo_hi_hi, sectored_entries_0_5_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_5_data_lo = {sectored_entries_0_5_data_lo_hi, sectored_entries_0_5_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_5_data_hi_lo_lo = {sectored_entries_0_5_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_5_data_hi_lo_hi = {sectored_entries_0_5_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_5_data_hi_lo = {sectored_entries_0_5_data_hi_lo_hi, sectored_entries_0_5_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_5_data_hi_hi_lo = {sectored_entries_0_5_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_5_data_hi_hi_hi = {sectored_entries_0_5_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_5_data_hi_hi = {sectored_entries_0_5_data_hi_hi_hi, sectored_entries_0_5_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_5_data_hi = {sectored_entries_0_5_data_hi_hi, sectored_entries_0_5_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_5_data_T = {sectored_entries_0_5_data_hi, sectored_entries_0_5_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_6_data_lo_lo_hi = {sectored_entries_0_6_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_6_data_lo_lo = {sectored_entries_0_6_data_lo_lo_hi, sectored_entries_0_6_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_6_data_lo_hi_lo = {sectored_entries_0_6_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_6_data_lo_hi_hi = {sectored_entries_0_6_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_6_data_lo_hi = {sectored_entries_0_6_data_lo_hi_hi, sectored_entries_0_6_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_6_data_lo = {sectored_entries_0_6_data_lo_hi, sectored_entries_0_6_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_6_data_hi_lo_lo = {sectored_entries_0_6_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_6_data_hi_lo_hi = {sectored_entries_0_6_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_6_data_hi_lo = {sectored_entries_0_6_data_hi_lo_hi, sectored_entries_0_6_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_6_data_hi_hi_lo = {sectored_entries_0_6_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_6_data_hi_hi_hi = {sectored_entries_0_6_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_6_data_hi_hi = {sectored_entries_0_6_data_hi_hi_hi, sectored_entries_0_6_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_6_data_hi = {sectored_entries_0_6_data_hi_hi, sectored_entries_0_6_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_6_data_T = {sectored_entries_0_6_data_hi, sectored_entries_0_6_data_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_7_data_lo_lo_hi = {sectored_entries_0_7_data_lo_lo_hi_hi, newEntry_eff}; // @[TLB.scala:217:24, :449:24]
wire [4:0] sectored_entries_0_7_data_lo_lo = {sectored_entries_0_7_data_lo_lo_hi, sectored_entries_0_7_data_lo_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_7_data_lo_hi_lo = {sectored_entries_0_7_data_lo_hi_lo_hi, newEntry_ppp}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_7_data_lo_hi_hi = {sectored_entries_0_7_data_lo_hi_hi_hi, newEntry_pw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_7_data_lo_hi = {sectored_entries_0_7_data_lo_hi_hi, sectored_entries_0_7_data_lo_hi_lo}; // @[TLB.scala:217:24]
wire [10:0] sectored_entries_0_7_data_lo = {sectored_entries_0_7_data_lo_hi, sectored_entries_0_7_data_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_7_data_hi_lo_lo = {sectored_entries_0_7_data_hi_lo_lo_hi, newEntry_hw}; // @[TLB.scala:217:24, :449:24]
wire [2:0] sectored_entries_0_7_data_hi_lo_hi = {sectored_entries_0_7_data_hi_lo_hi_hi, newEntry_sw}; // @[TLB.scala:217:24, :449:24]
wire [5:0] sectored_entries_0_7_data_hi_lo = {sectored_entries_0_7_data_hi_lo_hi, sectored_entries_0_7_data_hi_lo_lo}; // @[TLB.scala:217:24]
wire [2:0] sectored_entries_0_7_data_hi_hi_lo = {sectored_entries_0_7_data_hi_hi_lo_hi, 1'h0}; // @[TLB.scala:217:24]
wire [21:0] sectored_entries_0_7_data_hi_hi_hi = {sectored_entries_0_7_data_hi_hi_hi_hi, newEntry_g}; // @[TLB.scala:217:24, :449:24]
wire [24:0] sectored_entries_0_7_data_hi_hi = {sectored_entries_0_7_data_hi_hi_hi, sectored_entries_0_7_data_hi_hi_lo}; // @[TLB.scala:217:24]
wire [30:0] sectored_entries_0_7_data_hi = {sectored_entries_0_7_data_hi_hi, sectored_entries_0_7_data_hi_lo}; // @[TLB.scala:217:24]
wire [41:0] _sectored_entries_0_7_data_T = {sectored_entries_0_7_data_hi, sectored_entries_0_7_data_lo}; // @[TLB.scala:217:24]
wire [19:0] _entries_T_23; // @[TLB.scala:170:77]
wire _entries_T_22; // @[TLB.scala:170:77]
wire _entries_T_21; // @[TLB.scala:170:77]
wire _entries_T_20; // @[TLB.scala:170:77]
wire _entries_T_19; // @[TLB.scala:170:77]
wire _entries_T_18; // @[TLB.scala:170:77]
wire _entries_T_17; // @[TLB.scala:170:77]
wire _entries_T_16; // @[TLB.scala:170:77]
wire _entries_T_15; // @[TLB.scala:170:77]
wire _entries_T_14; // @[TLB.scala:170:77]
wire _entries_T_13; // @[TLB.scala:170:77]
wire _entries_T_12; // @[TLB.scala:170:77]
wire _entries_T_11; // @[TLB.scala:170:77]
wire _entries_T_10; // @[TLB.scala:170:77]
wire _entries_T_9; // @[TLB.scala:170:77]
wire _entries_T_8; // @[TLB.scala:170:77]
wire _entries_T_7; // @[TLB.scala:170:77]
wire _entries_T_6; // @[TLB.scala:170:77]
wire _entries_T_5; // @[TLB.scala:170:77]
wire _entries_T_4; // @[TLB.scala:170:77]
wire _entries_T_3; // @[TLB.scala:170:77]
wire _entries_T_2; // @[TLB.scala:170:77]
wire _entries_T_1; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_32 = {{sectored_entries_0_0_data_3}, {sectored_entries_0_0_data_2}, {sectored_entries_0_0_data_1}, {sectored_entries_0_0_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_1 = _GEN_32[_entries_T]; // @[package.scala:163:13]
assign _entries_T_1 = _entries_WIRE_1[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_fragmented_superpage = _entries_T_1; // @[TLB.scala:170:77]
assign _entries_T_2 = _entries_WIRE_1[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_c = _entries_T_2; // @[TLB.scala:170:77]
assign _entries_T_3 = _entries_WIRE_1[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_eff = _entries_T_3; // @[TLB.scala:170:77]
assign _entries_T_4 = _entries_WIRE_1[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_paa = _entries_T_4; // @[TLB.scala:170:77]
assign _entries_T_5 = _entries_WIRE_1[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_pal = _entries_T_5; // @[TLB.scala:170:77]
assign _entries_T_6 = _entries_WIRE_1[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_ppp = _entries_T_6; // @[TLB.scala:170:77]
assign _entries_T_7 = _entries_WIRE_1[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_pr = _entries_T_7; // @[TLB.scala:170:77]
assign _entries_T_8 = _entries_WIRE_1[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_px = _entries_T_8; // @[TLB.scala:170:77]
assign _entries_T_9 = _entries_WIRE_1[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_pw = _entries_T_9; // @[TLB.scala:170:77]
assign _entries_T_10 = _entries_WIRE_1[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_hr = _entries_T_10; // @[TLB.scala:170:77]
assign _entries_T_11 = _entries_WIRE_1[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_hx = _entries_T_11; // @[TLB.scala:170:77]
assign _entries_T_12 = _entries_WIRE_1[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_hw = _entries_T_12; // @[TLB.scala:170:77]
assign _entries_T_13 = _entries_WIRE_1[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_sr = _entries_T_13; // @[TLB.scala:170:77]
assign _entries_T_14 = _entries_WIRE_1[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_sx = _entries_T_14; // @[TLB.scala:170:77]
assign _entries_T_15 = _entries_WIRE_1[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_sw = _entries_T_15; // @[TLB.scala:170:77]
assign _entries_T_16 = _entries_WIRE_1[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_gf = _entries_T_16; // @[TLB.scala:170:77]
assign _entries_T_17 = _entries_WIRE_1[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_pf = _entries_T_17; // @[TLB.scala:170:77]
assign _entries_T_18 = _entries_WIRE_1[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_ae_stage2 = _entries_T_18; // @[TLB.scala:170:77]
assign _entries_T_19 = _entries_WIRE_1[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_ae_final = _entries_T_19; // @[TLB.scala:170:77]
assign _entries_T_20 = _entries_WIRE_1[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_ae_ptw = _entries_T_20; // @[TLB.scala:170:77]
assign _entries_T_21 = _entries_WIRE_1[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_g = _entries_T_21; // @[TLB.scala:170:77]
assign _entries_T_22 = _entries_WIRE_1[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_u = _entries_T_22; // @[TLB.scala:170:77]
assign _entries_T_23 = _entries_WIRE_1[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_ppn = _entries_T_23; // @[TLB.scala:170:77]
wire [19:0] _entries_T_47; // @[TLB.scala:170:77]
wire _entries_T_46; // @[TLB.scala:170:77]
wire _entries_T_45; // @[TLB.scala:170:77]
wire _entries_T_44; // @[TLB.scala:170:77]
wire _entries_T_43; // @[TLB.scala:170:77]
wire _entries_T_42; // @[TLB.scala:170:77]
wire _entries_T_41; // @[TLB.scala:170:77]
wire _entries_T_40; // @[TLB.scala:170:77]
wire _entries_T_39; // @[TLB.scala:170:77]
wire _entries_T_38; // @[TLB.scala:170:77]
wire _entries_T_37; // @[TLB.scala:170:77]
wire _entries_T_36; // @[TLB.scala:170:77]
wire _entries_T_35; // @[TLB.scala:170:77]
wire _entries_T_34; // @[TLB.scala:170:77]
wire _entries_T_33; // @[TLB.scala:170:77]
wire _entries_T_32; // @[TLB.scala:170:77]
wire _entries_T_31; // @[TLB.scala:170:77]
wire _entries_T_30; // @[TLB.scala:170:77]
wire _entries_T_29; // @[TLB.scala:170:77]
wire _entries_T_28; // @[TLB.scala:170:77]
wire _entries_T_27; // @[TLB.scala:170:77]
wire _entries_T_26; // @[TLB.scala:170:77]
wire _entries_T_25; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_33 = {{sectored_entries_0_1_data_3}, {sectored_entries_0_1_data_2}, {sectored_entries_0_1_data_1}, {sectored_entries_0_1_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_3 = _GEN_33[_entries_T_24]; // @[package.scala:163:13]
assign _entries_T_25 = _entries_WIRE_3[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_fragmented_superpage = _entries_T_25; // @[TLB.scala:170:77]
assign _entries_T_26 = _entries_WIRE_3[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_c = _entries_T_26; // @[TLB.scala:170:77]
assign _entries_T_27 = _entries_WIRE_3[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_eff = _entries_T_27; // @[TLB.scala:170:77]
assign _entries_T_28 = _entries_WIRE_3[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_paa = _entries_T_28; // @[TLB.scala:170:77]
assign _entries_T_29 = _entries_WIRE_3[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pal = _entries_T_29; // @[TLB.scala:170:77]
assign _entries_T_30 = _entries_WIRE_3[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ppp = _entries_T_30; // @[TLB.scala:170:77]
assign _entries_T_31 = _entries_WIRE_3[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pr = _entries_T_31; // @[TLB.scala:170:77]
assign _entries_T_32 = _entries_WIRE_3[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_px = _entries_T_32; // @[TLB.scala:170:77]
assign _entries_T_33 = _entries_WIRE_3[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pw = _entries_T_33; // @[TLB.scala:170:77]
assign _entries_T_34 = _entries_WIRE_3[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_hr = _entries_T_34; // @[TLB.scala:170:77]
assign _entries_T_35 = _entries_WIRE_3[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_hx = _entries_T_35; // @[TLB.scala:170:77]
assign _entries_T_36 = _entries_WIRE_3[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_hw = _entries_T_36; // @[TLB.scala:170:77]
assign _entries_T_37 = _entries_WIRE_3[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_sr = _entries_T_37; // @[TLB.scala:170:77]
assign _entries_T_38 = _entries_WIRE_3[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_sx = _entries_T_38; // @[TLB.scala:170:77]
assign _entries_T_39 = _entries_WIRE_3[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_sw = _entries_T_39; // @[TLB.scala:170:77]
assign _entries_T_40 = _entries_WIRE_3[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_gf = _entries_T_40; // @[TLB.scala:170:77]
assign _entries_T_41 = _entries_WIRE_3[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_pf = _entries_T_41; // @[TLB.scala:170:77]
assign _entries_T_42 = _entries_WIRE_3[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ae_stage2 = _entries_T_42; // @[TLB.scala:170:77]
assign _entries_T_43 = _entries_WIRE_3[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ae_final = _entries_T_43; // @[TLB.scala:170:77]
assign _entries_T_44 = _entries_WIRE_3[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_ae_ptw = _entries_T_44; // @[TLB.scala:170:77]
assign _entries_T_45 = _entries_WIRE_3[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_g = _entries_T_45; // @[TLB.scala:170:77]
assign _entries_T_46 = _entries_WIRE_3[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_2_u = _entries_T_46; // @[TLB.scala:170:77]
assign _entries_T_47 = _entries_WIRE_3[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_2_ppn = _entries_T_47; // @[TLB.scala:170:77]
wire [19:0] _entries_T_71; // @[TLB.scala:170:77]
wire _entries_T_70; // @[TLB.scala:170:77]
wire _entries_T_69; // @[TLB.scala:170:77]
wire _entries_T_68; // @[TLB.scala:170:77]
wire _entries_T_67; // @[TLB.scala:170:77]
wire _entries_T_66; // @[TLB.scala:170:77]
wire _entries_T_65; // @[TLB.scala:170:77]
wire _entries_T_64; // @[TLB.scala:170:77]
wire _entries_T_63; // @[TLB.scala:170:77]
wire _entries_T_62; // @[TLB.scala:170:77]
wire _entries_T_61; // @[TLB.scala:170:77]
wire _entries_T_60; // @[TLB.scala:170:77]
wire _entries_T_59; // @[TLB.scala:170:77]
wire _entries_T_58; // @[TLB.scala:170:77]
wire _entries_T_57; // @[TLB.scala:170:77]
wire _entries_T_56; // @[TLB.scala:170:77]
wire _entries_T_55; // @[TLB.scala:170:77]
wire _entries_T_54; // @[TLB.scala:170:77]
wire _entries_T_53; // @[TLB.scala:170:77]
wire _entries_T_52; // @[TLB.scala:170:77]
wire _entries_T_51; // @[TLB.scala:170:77]
wire _entries_T_50; // @[TLB.scala:170:77]
wire _entries_T_49; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_34 = {{sectored_entries_0_2_data_3}, {sectored_entries_0_2_data_2}, {sectored_entries_0_2_data_1}, {sectored_entries_0_2_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_5 = _GEN_34[_entries_T_48]; // @[package.scala:163:13]
assign _entries_T_49 = _entries_WIRE_5[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_fragmented_superpage = _entries_T_49; // @[TLB.scala:170:77]
assign _entries_T_50 = _entries_WIRE_5[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_c = _entries_T_50; // @[TLB.scala:170:77]
assign _entries_T_51 = _entries_WIRE_5[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_eff = _entries_T_51; // @[TLB.scala:170:77]
assign _entries_T_52 = _entries_WIRE_5[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_paa = _entries_T_52; // @[TLB.scala:170:77]
assign _entries_T_53 = _entries_WIRE_5[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pal = _entries_T_53; // @[TLB.scala:170:77]
assign _entries_T_54 = _entries_WIRE_5[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ppp = _entries_T_54; // @[TLB.scala:170:77]
assign _entries_T_55 = _entries_WIRE_5[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pr = _entries_T_55; // @[TLB.scala:170:77]
assign _entries_T_56 = _entries_WIRE_5[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_px = _entries_T_56; // @[TLB.scala:170:77]
assign _entries_T_57 = _entries_WIRE_5[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pw = _entries_T_57; // @[TLB.scala:170:77]
assign _entries_T_58 = _entries_WIRE_5[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_hr = _entries_T_58; // @[TLB.scala:170:77]
assign _entries_T_59 = _entries_WIRE_5[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_hx = _entries_T_59; // @[TLB.scala:170:77]
assign _entries_T_60 = _entries_WIRE_5[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_hw = _entries_T_60; // @[TLB.scala:170:77]
assign _entries_T_61 = _entries_WIRE_5[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_sr = _entries_T_61; // @[TLB.scala:170:77]
assign _entries_T_62 = _entries_WIRE_5[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_sx = _entries_T_62; // @[TLB.scala:170:77]
assign _entries_T_63 = _entries_WIRE_5[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_sw = _entries_T_63; // @[TLB.scala:170:77]
assign _entries_T_64 = _entries_WIRE_5[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_gf = _entries_T_64; // @[TLB.scala:170:77]
assign _entries_T_65 = _entries_WIRE_5[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_pf = _entries_T_65; // @[TLB.scala:170:77]
assign _entries_T_66 = _entries_WIRE_5[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ae_stage2 = _entries_T_66; // @[TLB.scala:170:77]
assign _entries_T_67 = _entries_WIRE_5[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ae_final = _entries_T_67; // @[TLB.scala:170:77]
assign _entries_T_68 = _entries_WIRE_5[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_ae_ptw = _entries_T_68; // @[TLB.scala:170:77]
assign _entries_T_69 = _entries_WIRE_5[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_g = _entries_T_69; // @[TLB.scala:170:77]
assign _entries_T_70 = _entries_WIRE_5[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_4_u = _entries_T_70; // @[TLB.scala:170:77]
assign _entries_T_71 = _entries_WIRE_5[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_4_ppn = _entries_T_71; // @[TLB.scala:170:77]
wire [19:0] _entries_T_95; // @[TLB.scala:170:77]
wire _entries_T_94; // @[TLB.scala:170:77]
wire _entries_T_93; // @[TLB.scala:170:77]
wire _entries_T_92; // @[TLB.scala:170:77]
wire _entries_T_91; // @[TLB.scala:170:77]
wire _entries_T_90; // @[TLB.scala:170:77]
wire _entries_T_89; // @[TLB.scala:170:77]
wire _entries_T_88; // @[TLB.scala:170:77]
wire _entries_T_87; // @[TLB.scala:170:77]
wire _entries_T_86; // @[TLB.scala:170:77]
wire _entries_T_85; // @[TLB.scala:170:77]
wire _entries_T_84; // @[TLB.scala:170:77]
wire _entries_T_83; // @[TLB.scala:170:77]
wire _entries_T_82; // @[TLB.scala:170:77]
wire _entries_T_81; // @[TLB.scala:170:77]
wire _entries_T_80; // @[TLB.scala:170:77]
wire _entries_T_79; // @[TLB.scala:170:77]
wire _entries_T_78; // @[TLB.scala:170:77]
wire _entries_T_77; // @[TLB.scala:170:77]
wire _entries_T_76; // @[TLB.scala:170:77]
wire _entries_T_75; // @[TLB.scala:170:77]
wire _entries_T_74; // @[TLB.scala:170:77]
wire _entries_T_73; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_35 = {{sectored_entries_0_3_data_3}, {sectored_entries_0_3_data_2}, {sectored_entries_0_3_data_1}, {sectored_entries_0_3_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_7 = _GEN_35[_entries_T_72]; // @[package.scala:163:13]
assign _entries_T_73 = _entries_WIRE_7[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_fragmented_superpage = _entries_T_73; // @[TLB.scala:170:77]
assign _entries_T_74 = _entries_WIRE_7[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_c = _entries_T_74; // @[TLB.scala:170:77]
assign _entries_T_75 = _entries_WIRE_7[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_eff = _entries_T_75; // @[TLB.scala:170:77]
assign _entries_T_76 = _entries_WIRE_7[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_paa = _entries_T_76; // @[TLB.scala:170:77]
assign _entries_T_77 = _entries_WIRE_7[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pal = _entries_T_77; // @[TLB.scala:170:77]
assign _entries_T_78 = _entries_WIRE_7[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ppp = _entries_T_78; // @[TLB.scala:170:77]
assign _entries_T_79 = _entries_WIRE_7[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pr = _entries_T_79; // @[TLB.scala:170:77]
assign _entries_T_80 = _entries_WIRE_7[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_px = _entries_T_80; // @[TLB.scala:170:77]
assign _entries_T_81 = _entries_WIRE_7[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pw = _entries_T_81; // @[TLB.scala:170:77]
assign _entries_T_82 = _entries_WIRE_7[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_hr = _entries_T_82; // @[TLB.scala:170:77]
assign _entries_T_83 = _entries_WIRE_7[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_hx = _entries_T_83; // @[TLB.scala:170:77]
assign _entries_T_84 = _entries_WIRE_7[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_hw = _entries_T_84; // @[TLB.scala:170:77]
assign _entries_T_85 = _entries_WIRE_7[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_sr = _entries_T_85; // @[TLB.scala:170:77]
assign _entries_T_86 = _entries_WIRE_7[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_sx = _entries_T_86; // @[TLB.scala:170:77]
assign _entries_T_87 = _entries_WIRE_7[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_sw = _entries_T_87; // @[TLB.scala:170:77]
assign _entries_T_88 = _entries_WIRE_7[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_gf = _entries_T_88; // @[TLB.scala:170:77]
assign _entries_T_89 = _entries_WIRE_7[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_pf = _entries_T_89; // @[TLB.scala:170:77]
assign _entries_T_90 = _entries_WIRE_7[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ae_stage2 = _entries_T_90; // @[TLB.scala:170:77]
assign _entries_T_91 = _entries_WIRE_7[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ae_final = _entries_T_91; // @[TLB.scala:170:77]
assign _entries_T_92 = _entries_WIRE_7[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_ae_ptw = _entries_T_92; // @[TLB.scala:170:77]
assign _entries_T_93 = _entries_WIRE_7[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_g = _entries_T_93; // @[TLB.scala:170:77]
assign _entries_T_94 = _entries_WIRE_7[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_6_u = _entries_T_94; // @[TLB.scala:170:77]
assign _entries_T_95 = _entries_WIRE_7[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_6_ppn = _entries_T_95; // @[TLB.scala:170:77]
wire [19:0] _entries_T_119; // @[TLB.scala:170:77]
wire _entries_T_118; // @[TLB.scala:170:77]
wire _entries_T_117; // @[TLB.scala:170:77]
wire _entries_T_116; // @[TLB.scala:170:77]
wire _entries_T_115; // @[TLB.scala:170:77]
wire _entries_T_114; // @[TLB.scala:170:77]
wire _entries_T_113; // @[TLB.scala:170:77]
wire _entries_T_112; // @[TLB.scala:170:77]
wire _entries_T_111; // @[TLB.scala:170:77]
wire _entries_T_110; // @[TLB.scala:170:77]
wire _entries_T_109; // @[TLB.scala:170:77]
wire _entries_T_108; // @[TLB.scala:170:77]
wire _entries_T_107; // @[TLB.scala:170:77]
wire _entries_T_106; // @[TLB.scala:170:77]
wire _entries_T_105; // @[TLB.scala:170:77]
wire _entries_T_104; // @[TLB.scala:170:77]
wire _entries_T_103; // @[TLB.scala:170:77]
wire _entries_T_102; // @[TLB.scala:170:77]
wire _entries_T_101; // @[TLB.scala:170:77]
wire _entries_T_100; // @[TLB.scala:170:77]
wire _entries_T_99; // @[TLB.scala:170:77]
wire _entries_T_98; // @[TLB.scala:170:77]
wire _entries_T_97; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_36 = {{sectored_entries_0_4_data_3}, {sectored_entries_0_4_data_2}, {sectored_entries_0_4_data_1}, {sectored_entries_0_4_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_9 = _GEN_36[_entries_T_96]; // @[package.scala:163:13]
assign _entries_T_97 = _entries_WIRE_9[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_fragmented_superpage = _entries_T_97; // @[TLB.scala:170:77]
assign _entries_T_98 = _entries_WIRE_9[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_c = _entries_T_98; // @[TLB.scala:170:77]
assign _entries_T_99 = _entries_WIRE_9[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_eff = _entries_T_99; // @[TLB.scala:170:77]
assign _entries_T_100 = _entries_WIRE_9[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_paa = _entries_T_100; // @[TLB.scala:170:77]
assign _entries_T_101 = _entries_WIRE_9[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pal = _entries_T_101; // @[TLB.scala:170:77]
assign _entries_T_102 = _entries_WIRE_9[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ppp = _entries_T_102; // @[TLB.scala:170:77]
assign _entries_T_103 = _entries_WIRE_9[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pr = _entries_T_103; // @[TLB.scala:170:77]
assign _entries_T_104 = _entries_WIRE_9[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_px = _entries_T_104; // @[TLB.scala:170:77]
assign _entries_T_105 = _entries_WIRE_9[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pw = _entries_T_105; // @[TLB.scala:170:77]
assign _entries_T_106 = _entries_WIRE_9[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_hr = _entries_T_106; // @[TLB.scala:170:77]
assign _entries_T_107 = _entries_WIRE_9[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_hx = _entries_T_107; // @[TLB.scala:170:77]
assign _entries_T_108 = _entries_WIRE_9[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_hw = _entries_T_108; // @[TLB.scala:170:77]
assign _entries_T_109 = _entries_WIRE_9[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_sr = _entries_T_109; // @[TLB.scala:170:77]
assign _entries_T_110 = _entries_WIRE_9[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_sx = _entries_T_110; // @[TLB.scala:170:77]
assign _entries_T_111 = _entries_WIRE_9[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_sw = _entries_T_111; // @[TLB.scala:170:77]
assign _entries_T_112 = _entries_WIRE_9[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_gf = _entries_T_112; // @[TLB.scala:170:77]
assign _entries_T_113 = _entries_WIRE_9[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_pf = _entries_T_113; // @[TLB.scala:170:77]
assign _entries_T_114 = _entries_WIRE_9[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ae_stage2 = _entries_T_114; // @[TLB.scala:170:77]
assign _entries_T_115 = _entries_WIRE_9[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ae_final = _entries_T_115; // @[TLB.scala:170:77]
assign _entries_T_116 = _entries_WIRE_9[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_ae_ptw = _entries_T_116; // @[TLB.scala:170:77]
assign _entries_T_117 = _entries_WIRE_9[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_g = _entries_T_117; // @[TLB.scala:170:77]
assign _entries_T_118 = _entries_WIRE_9[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_8_u = _entries_T_118; // @[TLB.scala:170:77]
assign _entries_T_119 = _entries_WIRE_9[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_8_ppn = _entries_T_119; // @[TLB.scala:170:77]
wire [19:0] _entries_T_143; // @[TLB.scala:170:77]
wire _entries_T_142; // @[TLB.scala:170:77]
wire _entries_T_141; // @[TLB.scala:170:77]
wire _entries_T_140; // @[TLB.scala:170:77]
wire _entries_T_139; // @[TLB.scala:170:77]
wire _entries_T_138; // @[TLB.scala:170:77]
wire _entries_T_137; // @[TLB.scala:170:77]
wire _entries_T_136; // @[TLB.scala:170:77]
wire _entries_T_135; // @[TLB.scala:170:77]
wire _entries_T_134; // @[TLB.scala:170:77]
wire _entries_T_133; // @[TLB.scala:170:77]
wire _entries_T_132; // @[TLB.scala:170:77]
wire _entries_T_131; // @[TLB.scala:170:77]
wire _entries_T_130; // @[TLB.scala:170:77]
wire _entries_T_129; // @[TLB.scala:170:77]
wire _entries_T_128; // @[TLB.scala:170:77]
wire _entries_T_127; // @[TLB.scala:170:77]
wire _entries_T_126; // @[TLB.scala:170:77]
wire _entries_T_125; // @[TLB.scala:170:77]
wire _entries_T_124; // @[TLB.scala:170:77]
wire _entries_T_123; // @[TLB.scala:170:77]
wire _entries_T_122; // @[TLB.scala:170:77]
wire _entries_T_121; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_37 = {{sectored_entries_0_5_data_3}, {sectored_entries_0_5_data_2}, {sectored_entries_0_5_data_1}, {sectored_entries_0_5_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_11 = _GEN_37[_entries_T_120]; // @[package.scala:163:13]
assign _entries_T_121 = _entries_WIRE_11[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_fragmented_superpage = _entries_T_121; // @[TLB.scala:170:77]
assign _entries_T_122 = _entries_WIRE_11[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_c = _entries_T_122; // @[TLB.scala:170:77]
assign _entries_T_123 = _entries_WIRE_11[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_eff = _entries_T_123; // @[TLB.scala:170:77]
assign _entries_T_124 = _entries_WIRE_11[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_paa = _entries_T_124; // @[TLB.scala:170:77]
assign _entries_T_125 = _entries_WIRE_11[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pal = _entries_T_125; // @[TLB.scala:170:77]
assign _entries_T_126 = _entries_WIRE_11[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ppp = _entries_T_126; // @[TLB.scala:170:77]
assign _entries_T_127 = _entries_WIRE_11[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pr = _entries_T_127; // @[TLB.scala:170:77]
assign _entries_T_128 = _entries_WIRE_11[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_px = _entries_T_128; // @[TLB.scala:170:77]
assign _entries_T_129 = _entries_WIRE_11[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pw = _entries_T_129; // @[TLB.scala:170:77]
assign _entries_T_130 = _entries_WIRE_11[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_hr = _entries_T_130; // @[TLB.scala:170:77]
assign _entries_T_131 = _entries_WIRE_11[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_hx = _entries_T_131; // @[TLB.scala:170:77]
assign _entries_T_132 = _entries_WIRE_11[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_hw = _entries_T_132; // @[TLB.scala:170:77]
assign _entries_T_133 = _entries_WIRE_11[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_sr = _entries_T_133; // @[TLB.scala:170:77]
assign _entries_T_134 = _entries_WIRE_11[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_sx = _entries_T_134; // @[TLB.scala:170:77]
assign _entries_T_135 = _entries_WIRE_11[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_sw = _entries_T_135; // @[TLB.scala:170:77]
assign _entries_T_136 = _entries_WIRE_11[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_gf = _entries_T_136; // @[TLB.scala:170:77]
assign _entries_T_137 = _entries_WIRE_11[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_pf = _entries_T_137; // @[TLB.scala:170:77]
assign _entries_T_138 = _entries_WIRE_11[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ae_stage2 = _entries_T_138; // @[TLB.scala:170:77]
assign _entries_T_139 = _entries_WIRE_11[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ae_final = _entries_T_139; // @[TLB.scala:170:77]
assign _entries_T_140 = _entries_WIRE_11[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_ae_ptw = _entries_T_140; // @[TLB.scala:170:77]
assign _entries_T_141 = _entries_WIRE_11[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_g = _entries_T_141; // @[TLB.scala:170:77]
assign _entries_T_142 = _entries_WIRE_11[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_10_u = _entries_T_142; // @[TLB.scala:170:77]
assign _entries_T_143 = _entries_WIRE_11[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_10_ppn = _entries_T_143; // @[TLB.scala:170:77]
wire [19:0] _entries_T_167; // @[TLB.scala:170:77]
wire _entries_T_166; // @[TLB.scala:170:77]
wire _entries_T_165; // @[TLB.scala:170:77]
wire _entries_T_164; // @[TLB.scala:170:77]
wire _entries_T_163; // @[TLB.scala:170:77]
wire _entries_T_162; // @[TLB.scala:170:77]
wire _entries_T_161; // @[TLB.scala:170:77]
wire _entries_T_160; // @[TLB.scala:170:77]
wire _entries_T_159; // @[TLB.scala:170:77]
wire _entries_T_158; // @[TLB.scala:170:77]
wire _entries_T_157; // @[TLB.scala:170:77]
wire _entries_T_156; // @[TLB.scala:170:77]
wire _entries_T_155; // @[TLB.scala:170:77]
wire _entries_T_154; // @[TLB.scala:170:77]
wire _entries_T_153; // @[TLB.scala:170:77]
wire _entries_T_152; // @[TLB.scala:170:77]
wire _entries_T_151; // @[TLB.scala:170:77]
wire _entries_T_150; // @[TLB.scala:170:77]
wire _entries_T_149; // @[TLB.scala:170:77]
wire _entries_T_148; // @[TLB.scala:170:77]
wire _entries_T_147; // @[TLB.scala:170:77]
wire _entries_T_146; // @[TLB.scala:170:77]
wire _entries_T_145; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_38 = {{sectored_entries_0_6_data_3}, {sectored_entries_0_6_data_2}, {sectored_entries_0_6_data_1}, {sectored_entries_0_6_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_13 = _GEN_38[_entries_T_144]; // @[package.scala:163:13]
assign _entries_T_145 = _entries_WIRE_13[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_fragmented_superpage = _entries_T_145; // @[TLB.scala:170:77]
assign _entries_T_146 = _entries_WIRE_13[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_c = _entries_T_146; // @[TLB.scala:170:77]
assign _entries_T_147 = _entries_WIRE_13[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_eff = _entries_T_147; // @[TLB.scala:170:77]
assign _entries_T_148 = _entries_WIRE_13[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_paa = _entries_T_148; // @[TLB.scala:170:77]
assign _entries_T_149 = _entries_WIRE_13[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_pal = _entries_T_149; // @[TLB.scala:170:77]
assign _entries_T_150 = _entries_WIRE_13[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_ppp = _entries_T_150; // @[TLB.scala:170:77]
assign _entries_T_151 = _entries_WIRE_13[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_pr = _entries_T_151; // @[TLB.scala:170:77]
assign _entries_T_152 = _entries_WIRE_13[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_px = _entries_T_152; // @[TLB.scala:170:77]
assign _entries_T_153 = _entries_WIRE_13[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_pw = _entries_T_153; // @[TLB.scala:170:77]
assign _entries_T_154 = _entries_WIRE_13[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_hr = _entries_T_154; // @[TLB.scala:170:77]
assign _entries_T_155 = _entries_WIRE_13[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_hx = _entries_T_155; // @[TLB.scala:170:77]
assign _entries_T_156 = _entries_WIRE_13[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_hw = _entries_T_156; // @[TLB.scala:170:77]
assign _entries_T_157 = _entries_WIRE_13[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_sr = _entries_T_157; // @[TLB.scala:170:77]
assign _entries_T_158 = _entries_WIRE_13[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_sx = _entries_T_158; // @[TLB.scala:170:77]
assign _entries_T_159 = _entries_WIRE_13[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_sw = _entries_T_159; // @[TLB.scala:170:77]
assign _entries_T_160 = _entries_WIRE_13[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_gf = _entries_T_160; // @[TLB.scala:170:77]
assign _entries_T_161 = _entries_WIRE_13[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_pf = _entries_T_161; // @[TLB.scala:170:77]
assign _entries_T_162 = _entries_WIRE_13[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_ae_stage2 = _entries_T_162; // @[TLB.scala:170:77]
assign _entries_T_163 = _entries_WIRE_13[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_ae_final = _entries_T_163; // @[TLB.scala:170:77]
assign _entries_T_164 = _entries_WIRE_13[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_ae_ptw = _entries_T_164; // @[TLB.scala:170:77]
assign _entries_T_165 = _entries_WIRE_13[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_g = _entries_T_165; // @[TLB.scala:170:77]
assign _entries_T_166 = _entries_WIRE_13[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_12_u = _entries_T_166; // @[TLB.scala:170:77]
assign _entries_T_167 = _entries_WIRE_13[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_12_ppn = _entries_T_167; // @[TLB.scala:170:77]
wire [19:0] _entries_T_191; // @[TLB.scala:170:77]
wire _entries_T_190; // @[TLB.scala:170:77]
wire _entries_T_189; // @[TLB.scala:170:77]
wire _entries_T_188; // @[TLB.scala:170:77]
wire _entries_T_187; // @[TLB.scala:170:77]
wire _entries_T_186; // @[TLB.scala:170:77]
wire _entries_T_185; // @[TLB.scala:170:77]
wire _entries_T_184; // @[TLB.scala:170:77]
wire _entries_T_183; // @[TLB.scala:170:77]
wire _entries_T_182; // @[TLB.scala:170:77]
wire _entries_T_181; // @[TLB.scala:170:77]
wire _entries_T_180; // @[TLB.scala:170:77]
wire _entries_T_179; // @[TLB.scala:170:77]
wire _entries_T_178; // @[TLB.scala:170:77]
wire _entries_T_177; // @[TLB.scala:170:77]
wire _entries_T_176; // @[TLB.scala:170:77]
wire _entries_T_175; // @[TLB.scala:170:77]
wire _entries_T_174; // @[TLB.scala:170:77]
wire _entries_T_173; // @[TLB.scala:170:77]
wire _entries_T_172; // @[TLB.scala:170:77]
wire _entries_T_171; // @[TLB.scala:170:77]
wire _entries_T_170; // @[TLB.scala:170:77]
wire _entries_T_169; // @[TLB.scala:170:77]
wire [3:0][41:0] _GEN_39 = {{sectored_entries_0_7_data_3}, {sectored_entries_0_7_data_2}, {sectored_entries_0_7_data_1}, {sectored_entries_0_7_data_0}}; // @[TLB.scala:170:77, :339:29]
wire [41:0] _entries_WIRE_15 = _GEN_39[_entries_T_168]; // @[package.scala:163:13]
assign _entries_T_169 = _entries_WIRE_15[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_fragmented_superpage = _entries_T_169; // @[TLB.scala:170:77]
assign _entries_T_170 = _entries_WIRE_15[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_c = _entries_T_170; // @[TLB.scala:170:77]
assign _entries_T_171 = _entries_WIRE_15[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_eff = _entries_T_171; // @[TLB.scala:170:77]
assign _entries_T_172 = _entries_WIRE_15[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_paa = _entries_T_172; // @[TLB.scala:170:77]
assign _entries_T_173 = _entries_WIRE_15[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_pal = _entries_T_173; // @[TLB.scala:170:77]
assign _entries_T_174 = _entries_WIRE_15[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_ppp = _entries_T_174; // @[TLB.scala:170:77]
assign _entries_T_175 = _entries_WIRE_15[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_pr = _entries_T_175; // @[TLB.scala:170:77]
assign _entries_T_176 = _entries_WIRE_15[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_px = _entries_T_176; // @[TLB.scala:170:77]
assign _entries_T_177 = _entries_WIRE_15[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_pw = _entries_T_177; // @[TLB.scala:170:77]
assign _entries_T_178 = _entries_WIRE_15[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_hr = _entries_T_178; // @[TLB.scala:170:77]
assign _entries_T_179 = _entries_WIRE_15[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_hx = _entries_T_179; // @[TLB.scala:170:77]
assign _entries_T_180 = _entries_WIRE_15[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_hw = _entries_T_180; // @[TLB.scala:170:77]
assign _entries_T_181 = _entries_WIRE_15[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_sr = _entries_T_181; // @[TLB.scala:170:77]
assign _entries_T_182 = _entries_WIRE_15[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_sx = _entries_T_182; // @[TLB.scala:170:77]
assign _entries_T_183 = _entries_WIRE_15[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_sw = _entries_T_183; // @[TLB.scala:170:77]
assign _entries_T_184 = _entries_WIRE_15[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_gf = _entries_T_184; // @[TLB.scala:170:77]
assign _entries_T_185 = _entries_WIRE_15[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_pf = _entries_T_185; // @[TLB.scala:170:77]
assign _entries_T_186 = _entries_WIRE_15[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_ae_stage2 = _entries_T_186; // @[TLB.scala:170:77]
assign _entries_T_187 = _entries_WIRE_15[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_ae_final = _entries_T_187; // @[TLB.scala:170:77]
assign _entries_T_188 = _entries_WIRE_15[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_ae_ptw = _entries_T_188; // @[TLB.scala:170:77]
assign _entries_T_189 = _entries_WIRE_15[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_g = _entries_T_189; // @[TLB.scala:170:77]
assign _entries_T_190 = _entries_WIRE_15[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_14_u = _entries_T_190; // @[TLB.scala:170:77]
assign _entries_T_191 = _entries_WIRE_15[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_14_ppn = _entries_T_191; // @[TLB.scala:170:77]
wire [19:0] _entries_T_214; // @[TLB.scala:170:77]
wire _entries_T_213; // @[TLB.scala:170:77]
wire _entries_T_212; // @[TLB.scala:170:77]
wire _entries_T_211; // @[TLB.scala:170:77]
wire _entries_T_210; // @[TLB.scala:170:77]
wire _entries_T_209; // @[TLB.scala:170:77]
wire _entries_T_208; // @[TLB.scala:170:77]
wire _entries_T_207; // @[TLB.scala:170:77]
wire _entries_T_206; // @[TLB.scala:170:77]
wire _entries_T_205; // @[TLB.scala:170:77]
wire _entries_T_204; // @[TLB.scala:170:77]
wire _entries_T_203; // @[TLB.scala:170:77]
wire _entries_T_202; // @[TLB.scala:170:77]
wire _entries_T_201; // @[TLB.scala:170:77]
wire _entries_T_200; // @[TLB.scala:170:77]
wire _entries_T_199; // @[TLB.scala:170:77]
wire _entries_T_198; // @[TLB.scala:170:77]
wire _entries_T_197; // @[TLB.scala:170:77]
wire _entries_T_196; // @[TLB.scala:170:77]
wire _entries_T_195; // @[TLB.scala:170:77]
wire _entries_T_194; // @[TLB.scala:170:77]
wire _entries_T_193; // @[TLB.scala:170:77]
wire _entries_T_192; // @[TLB.scala:170:77]
assign _entries_T_192 = _entries_WIRE_17[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_fragmented_superpage = _entries_T_192; // @[TLB.scala:170:77]
assign _entries_T_193 = _entries_WIRE_17[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_c = _entries_T_193; // @[TLB.scala:170:77]
assign _entries_T_194 = _entries_WIRE_17[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_eff = _entries_T_194; // @[TLB.scala:170:77]
assign _entries_T_195 = _entries_WIRE_17[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_paa = _entries_T_195; // @[TLB.scala:170:77]
assign _entries_T_196 = _entries_WIRE_17[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_pal = _entries_T_196; // @[TLB.scala:170:77]
assign _entries_T_197 = _entries_WIRE_17[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_ppp = _entries_T_197; // @[TLB.scala:170:77]
assign _entries_T_198 = _entries_WIRE_17[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_pr = _entries_T_198; // @[TLB.scala:170:77]
assign _entries_T_199 = _entries_WIRE_17[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_px = _entries_T_199; // @[TLB.scala:170:77]
assign _entries_T_200 = _entries_WIRE_17[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_pw = _entries_T_200; // @[TLB.scala:170:77]
assign _entries_T_201 = _entries_WIRE_17[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_hr = _entries_T_201; // @[TLB.scala:170:77]
assign _entries_T_202 = _entries_WIRE_17[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_hx = _entries_T_202; // @[TLB.scala:170:77]
assign _entries_T_203 = _entries_WIRE_17[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_hw = _entries_T_203; // @[TLB.scala:170:77]
assign _entries_T_204 = _entries_WIRE_17[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_sr = _entries_T_204; // @[TLB.scala:170:77]
assign _entries_T_205 = _entries_WIRE_17[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_sx = _entries_T_205; // @[TLB.scala:170:77]
assign _entries_T_206 = _entries_WIRE_17[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_sw = _entries_T_206; // @[TLB.scala:170:77]
assign _entries_T_207 = _entries_WIRE_17[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_gf = _entries_T_207; // @[TLB.scala:170:77]
assign _entries_T_208 = _entries_WIRE_17[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_pf = _entries_T_208; // @[TLB.scala:170:77]
assign _entries_T_209 = _entries_WIRE_17[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_ae_stage2 = _entries_T_209; // @[TLB.scala:170:77]
assign _entries_T_210 = _entries_WIRE_17[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_ae_final = _entries_T_210; // @[TLB.scala:170:77]
assign _entries_T_211 = _entries_WIRE_17[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_ae_ptw = _entries_T_211; // @[TLB.scala:170:77]
assign _entries_T_212 = _entries_WIRE_17[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_g = _entries_T_212; // @[TLB.scala:170:77]
assign _entries_T_213 = _entries_WIRE_17[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_16_u = _entries_T_213; // @[TLB.scala:170:77]
assign _entries_T_214 = _entries_WIRE_17[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_16_ppn = _entries_T_214; // @[TLB.scala:170:77]
wire [19:0] _entries_T_237; // @[TLB.scala:170:77]
wire _entries_T_236; // @[TLB.scala:170:77]
wire _entries_T_235; // @[TLB.scala:170:77]
wire _entries_T_234; // @[TLB.scala:170:77]
wire _entries_T_233; // @[TLB.scala:170:77]
wire _entries_T_232; // @[TLB.scala:170:77]
wire _entries_T_231; // @[TLB.scala:170:77]
wire _entries_T_230; // @[TLB.scala:170:77]
wire _entries_T_229; // @[TLB.scala:170:77]
wire _entries_T_228; // @[TLB.scala:170:77]
wire _entries_T_227; // @[TLB.scala:170:77]
wire _entries_T_226; // @[TLB.scala:170:77]
wire _entries_T_225; // @[TLB.scala:170:77]
wire _entries_T_224; // @[TLB.scala:170:77]
wire _entries_T_223; // @[TLB.scala:170:77]
wire _entries_T_222; // @[TLB.scala:170:77]
wire _entries_T_221; // @[TLB.scala:170:77]
wire _entries_T_220; // @[TLB.scala:170:77]
wire _entries_T_219; // @[TLB.scala:170:77]
wire _entries_T_218; // @[TLB.scala:170:77]
wire _entries_T_217; // @[TLB.scala:170:77]
wire _entries_T_216; // @[TLB.scala:170:77]
wire _entries_T_215; // @[TLB.scala:170:77]
assign _entries_T_215 = _entries_WIRE_19[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_fragmented_superpage = _entries_T_215; // @[TLB.scala:170:77]
assign _entries_T_216 = _entries_WIRE_19[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_c = _entries_T_216; // @[TLB.scala:170:77]
assign _entries_T_217 = _entries_WIRE_19[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_eff = _entries_T_217; // @[TLB.scala:170:77]
assign _entries_T_218 = _entries_WIRE_19[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_paa = _entries_T_218; // @[TLB.scala:170:77]
assign _entries_T_219 = _entries_WIRE_19[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_pal = _entries_T_219; // @[TLB.scala:170:77]
assign _entries_T_220 = _entries_WIRE_19[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_ppp = _entries_T_220; // @[TLB.scala:170:77]
assign _entries_T_221 = _entries_WIRE_19[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_pr = _entries_T_221; // @[TLB.scala:170:77]
assign _entries_T_222 = _entries_WIRE_19[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_px = _entries_T_222; // @[TLB.scala:170:77]
assign _entries_T_223 = _entries_WIRE_19[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_pw = _entries_T_223; // @[TLB.scala:170:77]
assign _entries_T_224 = _entries_WIRE_19[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_hr = _entries_T_224; // @[TLB.scala:170:77]
assign _entries_T_225 = _entries_WIRE_19[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_hx = _entries_T_225; // @[TLB.scala:170:77]
assign _entries_T_226 = _entries_WIRE_19[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_hw = _entries_T_226; // @[TLB.scala:170:77]
assign _entries_T_227 = _entries_WIRE_19[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_sr = _entries_T_227; // @[TLB.scala:170:77]
assign _entries_T_228 = _entries_WIRE_19[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_sx = _entries_T_228; // @[TLB.scala:170:77]
assign _entries_T_229 = _entries_WIRE_19[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_sw = _entries_T_229; // @[TLB.scala:170:77]
assign _entries_T_230 = _entries_WIRE_19[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_gf = _entries_T_230; // @[TLB.scala:170:77]
assign _entries_T_231 = _entries_WIRE_19[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_pf = _entries_T_231; // @[TLB.scala:170:77]
assign _entries_T_232 = _entries_WIRE_19[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_ae_stage2 = _entries_T_232; // @[TLB.scala:170:77]
assign _entries_T_233 = _entries_WIRE_19[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_ae_final = _entries_T_233; // @[TLB.scala:170:77]
assign _entries_T_234 = _entries_WIRE_19[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_ae_ptw = _entries_T_234; // @[TLB.scala:170:77]
assign _entries_T_235 = _entries_WIRE_19[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_g = _entries_T_235; // @[TLB.scala:170:77]
assign _entries_T_236 = _entries_WIRE_19[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_18_u = _entries_T_236; // @[TLB.scala:170:77]
assign _entries_T_237 = _entries_WIRE_19[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_18_ppn = _entries_T_237; // @[TLB.scala:170:77]
wire [19:0] _entries_T_260; // @[TLB.scala:170:77]
wire _entries_T_259; // @[TLB.scala:170:77]
wire _entries_T_258; // @[TLB.scala:170:77]
wire _entries_T_257; // @[TLB.scala:170:77]
wire _entries_T_256; // @[TLB.scala:170:77]
wire _entries_T_255; // @[TLB.scala:170:77]
wire _entries_T_254; // @[TLB.scala:170:77]
wire _entries_T_253; // @[TLB.scala:170:77]
wire _entries_T_252; // @[TLB.scala:170:77]
wire _entries_T_251; // @[TLB.scala:170:77]
wire _entries_T_250; // @[TLB.scala:170:77]
wire _entries_T_249; // @[TLB.scala:170:77]
wire _entries_T_248; // @[TLB.scala:170:77]
wire _entries_T_247; // @[TLB.scala:170:77]
wire _entries_T_246; // @[TLB.scala:170:77]
wire _entries_T_245; // @[TLB.scala:170:77]
wire _entries_T_244; // @[TLB.scala:170:77]
wire _entries_T_243; // @[TLB.scala:170:77]
wire _entries_T_242; // @[TLB.scala:170:77]
wire _entries_T_241; // @[TLB.scala:170:77]
wire _entries_T_240; // @[TLB.scala:170:77]
wire _entries_T_239; // @[TLB.scala:170:77]
wire _entries_T_238; // @[TLB.scala:170:77]
assign _entries_T_238 = _entries_WIRE_21[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_fragmented_superpage = _entries_T_238; // @[TLB.scala:170:77]
assign _entries_T_239 = _entries_WIRE_21[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_c = _entries_T_239; // @[TLB.scala:170:77]
assign _entries_T_240 = _entries_WIRE_21[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_eff = _entries_T_240; // @[TLB.scala:170:77]
assign _entries_T_241 = _entries_WIRE_21[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_paa = _entries_T_241; // @[TLB.scala:170:77]
assign _entries_T_242 = _entries_WIRE_21[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_pal = _entries_T_242; // @[TLB.scala:170:77]
assign _entries_T_243 = _entries_WIRE_21[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_ppp = _entries_T_243; // @[TLB.scala:170:77]
assign _entries_T_244 = _entries_WIRE_21[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_pr = _entries_T_244; // @[TLB.scala:170:77]
assign _entries_T_245 = _entries_WIRE_21[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_px = _entries_T_245; // @[TLB.scala:170:77]
assign _entries_T_246 = _entries_WIRE_21[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_pw = _entries_T_246; // @[TLB.scala:170:77]
assign _entries_T_247 = _entries_WIRE_21[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_hr = _entries_T_247; // @[TLB.scala:170:77]
assign _entries_T_248 = _entries_WIRE_21[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_hx = _entries_T_248; // @[TLB.scala:170:77]
assign _entries_T_249 = _entries_WIRE_21[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_hw = _entries_T_249; // @[TLB.scala:170:77]
assign _entries_T_250 = _entries_WIRE_21[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_sr = _entries_T_250; // @[TLB.scala:170:77]
assign _entries_T_251 = _entries_WIRE_21[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_sx = _entries_T_251; // @[TLB.scala:170:77]
assign _entries_T_252 = _entries_WIRE_21[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_sw = _entries_T_252; // @[TLB.scala:170:77]
assign _entries_T_253 = _entries_WIRE_21[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_gf = _entries_T_253; // @[TLB.scala:170:77]
assign _entries_T_254 = _entries_WIRE_21[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_pf = _entries_T_254; // @[TLB.scala:170:77]
assign _entries_T_255 = _entries_WIRE_21[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_ae_stage2 = _entries_T_255; // @[TLB.scala:170:77]
assign _entries_T_256 = _entries_WIRE_21[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_ae_final = _entries_T_256; // @[TLB.scala:170:77]
assign _entries_T_257 = _entries_WIRE_21[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_ae_ptw = _entries_T_257; // @[TLB.scala:170:77]
assign _entries_T_258 = _entries_WIRE_21[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_g = _entries_T_258; // @[TLB.scala:170:77]
assign _entries_T_259 = _entries_WIRE_21[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_20_u = _entries_T_259; // @[TLB.scala:170:77]
assign _entries_T_260 = _entries_WIRE_21[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_20_ppn = _entries_T_260; // @[TLB.scala:170:77]
wire [19:0] _entries_T_283; // @[TLB.scala:170:77]
wire _entries_T_282; // @[TLB.scala:170:77]
wire _entries_T_281; // @[TLB.scala:170:77]
wire _entries_T_280; // @[TLB.scala:170:77]
wire _entries_T_279; // @[TLB.scala:170:77]
wire _entries_T_278; // @[TLB.scala:170:77]
wire _entries_T_277; // @[TLB.scala:170:77]
wire _entries_T_276; // @[TLB.scala:170:77]
wire _entries_T_275; // @[TLB.scala:170:77]
wire _entries_T_274; // @[TLB.scala:170:77]
wire _entries_T_273; // @[TLB.scala:170:77]
wire _entries_T_272; // @[TLB.scala:170:77]
wire _entries_T_271; // @[TLB.scala:170:77]
wire _entries_T_270; // @[TLB.scala:170:77]
wire _entries_T_269; // @[TLB.scala:170:77]
wire _entries_T_268; // @[TLB.scala:170:77]
wire _entries_T_267; // @[TLB.scala:170:77]
wire _entries_T_266; // @[TLB.scala:170:77]
wire _entries_T_265; // @[TLB.scala:170:77]
wire _entries_T_264; // @[TLB.scala:170:77]
wire _entries_T_263; // @[TLB.scala:170:77]
wire _entries_T_262; // @[TLB.scala:170:77]
wire _entries_T_261; // @[TLB.scala:170:77]
assign _entries_T_261 = _entries_WIRE_23[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_fragmented_superpage = _entries_T_261; // @[TLB.scala:170:77]
assign _entries_T_262 = _entries_WIRE_23[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_c = _entries_T_262; // @[TLB.scala:170:77]
assign _entries_T_263 = _entries_WIRE_23[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_eff = _entries_T_263; // @[TLB.scala:170:77]
assign _entries_T_264 = _entries_WIRE_23[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_paa = _entries_T_264; // @[TLB.scala:170:77]
assign _entries_T_265 = _entries_WIRE_23[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_pal = _entries_T_265; // @[TLB.scala:170:77]
assign _entries_T_266 = _entries_WIRE_23[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_ppp = _entries_T_266; // @[TLB.scala:170:77]
assign _entries_T_267 = _entries_WIRE_23[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_pr = _entries_T_267; // @[TLB.scala:170:77]
assign _entries_T_268 = _entries_WIRE_23[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_px = _entries_T_268; // @[TLB.scala:170:77]
assign _entries_T_269 = _entries_WIRE_23[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_pw = _entries_T_269; // @[TLB.scala:170:77]
assign _entries_T_270 = _entries_WIRE_23[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_hr = _entries_T_270; // @[TLB.scala:170:77]
assign _entries_T_271 = _entries_WIRE_23[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_hx = _entries_T_271; // @[TLB.scala:170:77]
assign _entries_T_272 = _entries_WIRE_23[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_hw = _entries_T_272; // @[TLB.scala:170:77]
assign _entries_T_273 = _entries_WIRE_23[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_sr = _entries_T_273; // @[TLB.scala:170:77]
assign _entries_T_274 = _entries_WIRE_23[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_sx = _entries_T_274; // @[TLB.scala:170:77]
assign _entries_T_275 = _entries_WIRE_23[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_sw = _entries_T_275; // @[TLB.scala:170:77]
assign _entries_T_276 = _entries_WIRE_23[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_gf = _entries_T_276; // @[TLB.scala:170:77]
assign _entries_T_277 = _entries_WIRE_23[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_pf = _entries_T_277; // @[TLB.scala:170:77]
assign _entries_T_278 = _entries_WIRE_23[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_ae_stage2 = _entries_T_278; // @[TLB.scala:170:77]
assign _entries_T_279 = _entries_WIRE_23[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_ae_final = _entries_T_279; // @[TLB.scala:170:77]
assign _entries_T_280 = _entries_WIRE_23[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_ae_ptw = _entries_T_280; // @[TLB.scala:170:77]
assign _entries_T_281 = _entries_WIRE_23[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_g = _entries_T_281; // @[TLB.scala:170:77]
assign _entries_T_282 = _entries_WIRE_23[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_22_u = _entries_T_282; // @[TLB.scala:170:77]
assign _entries_T_283 = _entries_WIRE_23[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_22_ppn = _entries_T_283; // @[TLB.scala:170:77]
wire [19:0] _entries_T_306; // @[TLB.scala:170:77]
wire _entries_T_305; // @[TLB.scala:170:77]
wire _entries_T_304; // @[TLB.scala:170:77]
wire _entries_T_303; // @[TLB.scala:170:77]
wire _entries_T_302; // @[TLB.scala:170:77]
wire _entries_T_301; // @[TLB.scala:170:77]
wire _entries_T_300; // @[TLB.scala:170:77]
wire _entries_T_299; // @[TLB.scala:170:77]
wire _entries_T_298; // @[TLB.scala:170:77]
wire _entries_T_297; // @[TLB.scala:170:77]
wire _entries_T_296; // @[TLB.scala:170:77]
wire _entries_T_295; // @[TLB.scala:170:77]
wire _entries_T_294; // @[TLB.scala:170:77]
wire _entries_T_293; // @[TLB.scala:170:77]
wire _entries_T_292; // @[TLB.scala:170:77]
wire _entries_T_291; // @[TLB.scala:170:77]
wire _entries_T_290; // @[TLB.scala:170:77]
wire _entries_T_289; // @[TLB.scala:170:77]
wire _entries_T_288; // @[TLB.scala:170:77]
wire _entries_T_287; // @[TLB.scala:170:77]
wire _entries_T_286; // @[TLB.scala:170:77]
wire _entries_T_285; // @[TLB.scala:170:77]
wire _entries_T_284; // @[TLB.scala:170:77]
assign _entries_T_284 = _entries_WIRE_25[0]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_fragmented_superpage = _entries_T_284; // @[TLB.scala:170:77]
assign _entries_T_285 = _entries_WIRE_25[1]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_c = _entries_T_285; // @[TLB.scala:170:77]
assign _entries_T_286 = _entries_WIRE_25[2]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_eff = _entries_T_286; // @[TLB.scala:170:77]
assign _entries_T_287 = _entries_WIRE_25[3]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_paa = _entries_T_287; // @[TLB.scala:170:77]
assign _entries_T_288 = _entries_WIRE_25[4]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_pal = _entries_T_288; // @[TLB.scala:170:77]
assign _entries_T_289 = _entries_WIRE_25[5]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_ppp = _entries_T_289; // @[TLB.scala:170:77]
assign _entries_T_290 = _entries_WIRE_25[6]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_pr = _entries_T_290; // @[TLB.scala:170:77]
assign _entries_T_291 = _entries_WIRE_25[7]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_px = _entries_T_291; // @[TLB.scala:170:77]
assign _entries_T_292 = _entries_WIRE_25[8]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_pw = _entries_T_292; // @[TLB.scala:170:77]
assign _entries_T_293 = _entries_WIRE_25[9]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_hr = _entries_T_293; // @[TLB.scala:170:77]
assign _entries_T_294 = _entries_WIRE_25[10]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_hx = _entries_T_294; // @[TLB.scala:170:77]
assign _entries_T_295 = _entries_WIRE_25[11]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_hw = _entries_T_295; // @[TLB.scala:170:77]
assign _entries_T_296 = _entries_WIRE_25[12]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_sr = _entries_T_296; // @[TLB.scala:170:77]
assign _entries_T_297 = _entries_WIRE_25[13]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_sx = _entries_T_297; // @[TLB.scala:170:77]
assign _entries_T_298 = _entries_WIRE_25[14]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_sw = _entries_T_298; // @[TLB.scala:170:77]
assign _entries_T_299 = _entries_WIRE_25[15]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_gf = _entries_T_299; // @[TLB.scala:170:77]
assign _entries_T_300 = _entries_WIRE_25[16]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_pf = _entries_T_300; // @[TLB.scala:170:77]
assign _entries_T_301 = _entries_WIRE_25[17]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_ae_stage2 = _entries_T_301; // @[TLB.scala:170:77]
assign _entries_T_302 = _entries_WIRE_25[18]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_ae_final = _entries_T_302; // @[TLB.scala:170:77]
assign _entries_T_303 = _entries_WIRE_25[19]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_ae_ptw = _entries_T_303; // @[TLB.scala:170:77]
assign _entries_T_304 = _entries_WIRE_25[20]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_g = _entries_T_304; // @[TLB.scala:170:77]
assign _entries_T_305 = _entries_WIRE_25[21]; // @[TLB.scala:170:77]
wire _entries_WIRE_24_u = _entries_T_305; // @[TLB.scala:170:77]
assign _entries_T_306 = _entries_WIRE_25[41:22]; // @[TLB.scala:170:77]
wire [19:0] _entries_WIRE_24_ppn = _entries_T_306; // @[TLB.scala:170:77]
wire _ppn_T = ~vm_enabled; // @[TLB.scala:399:61, :442:18, :502:30]
wire [1:0] ppn_res = _entries_barrier_8_io_y_ppn[19:18]; // @[package.scala:267:25]
wire ppn_ignore = _ppn_ignore_T; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_1 = ppn_ignore ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_2 = {_ppn_T_1[26:20], _ppn_T_1[19:0] | _entries_barrier_8_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_3 = _ppn_T_2[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _ppn_T_4 = {ppn_res, _ppn_T_3}; // @[TLB.scala:195:26, :198:{18,58}]
wire _ppn_ignore_T_1 = ~(superpage_entries_0_level[1]); // @[TLB.scala:182:28, :197:28, :341:30]
wire [26:0] _ppn_T_6 = {_ppn_T_5[26:20], _ppn_T_5[19:0] | _entries_barrier_8_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_7 = _ppn_T_6[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _ppn_T_8 = {_ppn_T_4, _ppn_T_7}; // @[TLB.scala:198:{18,58}]
wire [1:0] ppn_res_1 = _entries_barrier_9_io_y_ppn[19:18]; // @[package.scala:267:25]
wire ppn_ignore_2 = _ppn_ignore_T_2; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_9 = ppn_ignore_2 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_10 = {_ppn_T_9[26:20], _ppn_T_9[19:0] | _entries_barrier_9_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_11 = _ppn_T_10[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _ppn_T_12 = {ppn_res_1, _ppn_T_11}; // @[TLB.scala:195:26, :198:{18,58}]
wire _ppn_ignore_T_3 = ~(superpage_entries_1_level[1]); // @[TLB.scala:182:28, :197:28, :341:30]
wire [26:0] _ppn_T_14 = {_ppn_T_13[26:20], _ppn_T_13[19:0] | _entries_barrier_9_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_15 = _ppn_T_14[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _ppn_T_16 = {_ppn_T_12, _ppn_T_15}; // @[TLB.scala:198:{18,58}]
wire [1:0] ppn_res_2 = _entries_barrier_10_io_y_ppn[19:18]; // @[package.scala:267:25]
wire ppn_ignore_4 = _ppn_ignore_T_4; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_17 = ppn_ignore_4 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_18 = {_ppn_T_17[26:20], _ppn_T_17[19:0] | _entries_barrier_10_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_19 = _ppn_T_18[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _ppn_T_20 = {ppn_res_2, _ppn_T_19}; // @[TLB.scala:195:26, :198:{18,58}]
wire _ppn_ignore_T_5 = ~(superpage_entries_2_level[1]); // @[TLB.scala:182:28, :197:28, :341:30]
wire [26:0] _ppn_T_22 = {_ppn_T_21[26:20], _ppn_T_21[19:0] | _entries_barrier_10_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_23 = _ppn_T_22[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _ppn_T_24 = {_ppn_T_20, _ppn_T_23}; // @[TLB.scala:198:{18,58}]
wire [1:0] ppn_res_3 = _entries_barrier_11_io_y_ppn[19:18]; // @[package.scala:267:25]
wire ppn_ignore_6 = _ppn_ignore_T_6; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_25 = ppn_ignore_6 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_26 = {_ppn_T_25[26:20], _ppn_T_25[19:0] | _entries_barrier_11_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_27 = _ppn_T_26[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _ppn_T_28 = {ppn_res_3, _ppn_T_27}; // @[TLB.scala:195:26, :198:{18,58}]
wire _ppn_ignore_T_7 = ~(superpage_entries_3_level[1]); // @[TLB.scala:182:28, :197:28, :341:30]
wire [26:0] _ppn_T_30 = {_ppn_T_29[26:20], _ppn_T_29[19:0] | _entries_barrier_11_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_31 = _ppn_T_30[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _ppn_T_32 = {_ppn_T_28, _ppn_T_31}; // @[TLB.scala:198:{18,58}]
wire [1:0] ppn_res_4 = _entries_barrier_12_io_y_ppn[19:18]; // @[package.scala:267:25]
wire ppn_ignore_8 = _ppn_ignore_T_8; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_33 = ppn_ignore_8 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_34 = {_ppn_T_33[26:20], _ppn_T_33[19:0] | _entries_barrier_12_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_35 = _ppn_T_34[17:9]; // @[TLB.scala:198:{47,58}]
wire [10:0] _ppn_T_36 = {ppn_res_4, _ppn_T_35}; // @[TLB.scala:195:26, :198:{18,58}]
wire _ppn_ignore_T_9 = ~(special_entry_level[1]); // @[TLB.scala:197:28, :346:56]
wire ppn_ignore_9 = _ppn_ignore_T_9; // @[TLB.scala:197:{28,34}]
wire [26:0] _ppn_T_37 = ppn_ignore_9 ? vpn : 27'h0; // @[TLB.scala:197:34, :198:28, :335:30]
wire [26:0] _ppn_T_38 = {_ppn_T_37[26:20], _ppn_T_37[19:0] | _entries_barrier_12_io_y_ppn}; // @[package.scala:267:25]
wire [8:0] _ppn_T_39 = _ppn_T_38[8:0]; // @[TLB.scala:198:{47,58}]
wire [19:0] _ppn_T_40 = {_ppn_T_36, _ppn_T_39}; // @[TLB.scala:198:{18,58}]
wire [19:0] _ppn_T_41 = vpn[19:0]; // @[TLB.scala:335:30, :502:125]
wire [19:0] _ppn_T_42 = hitsVec_0 ? _entries_barrier_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_43 = hitsVec_1 ? _entries_barrier_1_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_44 = hitsVec_2 ? _entries_barrier_2_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_45 = hitsVec_3 ? _entries_barrier_3_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_46 = hitsVec_4 ? _entries_barrier_4_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_47 = hitsVec_5 ? _entries_barrier_5_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_48 = hitsVec_6 ? _entries_barrier_6_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_49 = hitsVec_7 ? _entries_barrier_7_io_y_ppn : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_50 = hitsVec_8 ? _ppn_T_8 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_51 = hitsVec_9 ? _ppn_T_16 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_52 = hitsVec_10 ? _ppn_T_24 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_53 = hitsVec_11 ? _ppn_T_32 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_54 = hitsVec_12 ? _ppn_T_40 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_55 = _ppn_T ? _ppn_T_41 : 20'h0; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_56 = _ppn_T_42 | _ppn_T_43; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_57 = _ppn_T_56 | _ppn_T_44; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_58 = _ppn_T_57 | _ppn_T_45; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_59 = _ppn_T_58 | _ppn_T_46; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_60 = _ppn_T_59 | _ppn_T_47; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_61 = _ppn_T_60 | _ppn_T_48; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_62 = _ppn_T_61 | _ppn_T_49; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_63 = _ppn_T_62 | _ppn_T_50; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_64 = _ppn_T_63 | _ppn_T_51; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_65 = _ppn_T_64 | _ppn_T_52; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_66 = _ppn_T_65 | _ppn_T_53; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_67 = _ppn_T_66 | _ppn_T_54; // @[Mux.scala:30:73]
wire [19:0] _ppn_T_68 = _ppn_T_67 | _ppn_T_55; // @[Mux.scala:30:73]
wire [19:0] ppn = _ppn_T_68; // @[Mux.scala:30:73]
wire [1:0] ptw_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_ptw, _entries_barrier_1_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_ae_array_lo_lo = {ptw_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_ptw, _entries_barrier_4_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_ae_array_lo_hi = {ptw_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [5:0] ptw_ae_array_lo = {ptw_ae_array_lo_hi, ptw_ae_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ptw_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_ptw, _entries_barrier_7_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_ae_array_hi_lo = {ptw_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_ptw, _entries_barrier_9_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_ptw, _entries_barrier_11_io_y_ae_ptw}; // @[package.scala:45:27, :267:25]
wire [3:0] ptw_ae_array_hi_hi = {ptw_ae_array_hi_hi_hi, ptw_ae_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] ptw_ae_array_hi = {ptw_ae_array_hi_hi, ptw_ae_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _ptw_ae_array_T = {ptw_ae_array_hi, ptw_ae_array_lo}; // @[package.scala:45:27]
wire [13:0] ptw_ae_array = {1'h0, _ptw_ae_array_T}; // @[package.scala:45:27]
wire [1:0] final_ae_array_lo_lo_hi = {_entries_barrier_2_io_y_ae_final, _entries_barrier_1_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] final_ae_array_lo_lo = {final_ae_array_lo_lo_hi, _entries_barrier_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] final_ae_array_lo_hi_hi = {_entries_barrier_5_io_y_ae_final, _entries_barrier_4_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] final_ae_array_lo_hi = {final_ae_array_lo_hi_hi, _entries_barrier_3_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [5:0] final_ae_array_lo = {final_ae_array_lo_hi, final_ae_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] final_ae_array_hi_lo_hi = {_entries_barrier_8_io_y_ae_final, _entries_barrier_7_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [2:0] final_ae_array_hi_lo = {final_ae_array_hi_lo_hi, _entries_barrier_6_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] final_ae_array_hi_hi_lo = {_entries_barrier_10_io_y_ae_final, _entries_barrier_9_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [1:0] final_ae_array_hi_hi_hi = {_entries_barrier_12_io_y_ae_final, _entries_barrier_11_io_y_ae_final}; // @[package.scala:45:27, :267:25]
wire [3:0] final_ae_array_hi_hi = {final_ae_array_hi_hi_hi, final_ae_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] final_ae_array_hi = {final_ae_array_hi_hi, final_ae_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _final_ae_array_T = {final_ae_array_hi, final_ae_array_lo}; // @[package.scala:45:27]
wire [13:0] final_ae_array = {1'h0, _final_ae_array_T}; // @[package.scala:45:27]
wire [1:0] ptw_pf_array_lo_lo_hi = {_entries_barrier_2_io_y_pf, _entries_barrier_1_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_pf_array_lo_lo = {ptw_pf_array_lo_lo_hi, _entries_barrier_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_pf_array_lo_hi_hi = {_entries_barrier_5_io_y_pf, _entries_barrier_4_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_pf_array_lo_hi = {ptw_pf_array_lo_hi_hi, _entries_barrier_3_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [5:0] ptw_pf_array_lo = {ptw_pf_array_lo_hi, ptw_pf_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ptw_pf_array_hi_lo_hi = {_entries_barrier_8_io_y_pf, _entries_barrier_7_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_pf_array_hi_lo = {ptw_pf_array_hi_lo_hi, _entries_barrier_6_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_pf_array_hi_hi_lo = {_entries_barrier_10_io_y_pf, _entries_barrier_9_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_pf_array_hi_hi_hi = {_entries_barrier_12_io_y_pf, _entries_barrier_11_io_y_pf}; // @[package.scala:45:27, :267:25]
wire [3:0] ptw_pf_array_hi_hi = {ptw_pf_array_hi_hi_hi, ptw_pf_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] ptw_pf_array_hi = {ptw_pf_array_hi_hi, ptw_pf_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _ptw_pf_array_T = {ptw_pf_array_hi, ptw_pf_array_lo}; // @[package.scala:45:27]
wire [13:0] ptw_pf_array = {1'h0, _ptw_pf_array_T}; // @[package.scala:45:27]
wire [1:0] ptw_gf_array_lo_lo_hi = {_entries_barrier_2_io_y_gf, _entries_barrier_1_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_gf_array_lo_lo = {ptw_gf_array_lo_lo_hi, _entries_barrier_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_gf_array_lo_hi_hi = {_entries_barrier_5_io_y_gf, _entries_barrier_4_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_gf_array_lo_hi = {ptw_gf_array_lo_hi_hi, _entries_barrier_3_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [5:0] ptw_gf_array_lo = {ptw_gf_array_lo_hi, ptw_gf_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ptw_gf_array_hi_lo_hi = {_entries_barrier_8_io_y_gf, _entries_barrier_7_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [2:0] ptw_gf_array_hi_lo = {ptw_gf_array_hi_lo_hi, _entries_barrier_6_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_gf_array_hi_hi_lo = {_entries_barrier_10_io_y_gf, _entries_barrier_9_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [1:0] ptw_gf_array_hi_hi_hi = {_entries_barrier_12_io_y_gf, _entries_barrier_11_io_y_gf}; // @[package.scala:45:27, :267:25]
wire [3:0] ptw_gf_array_hi_hi = {ptw_gf_array_hi_hi_hi, ptw_gf_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] ptw_gf_array_hi = {ptw_gf_array_hi_hi, ptw_gf_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _ptw_gf_array_T = {ptw_gf_array_hi, ptw_gf_array_lo}; // @[package.scala:45:27]
wire [13:0] ptw_gf_array = {1'h0, _ptw_gf_array_T}; // @[package.scala:45:27]
wire [13:0] _gf_ld_array_T_3 = ptw_gf_array; // @[TLB.scala:509:25, :600:82]
wire [13:0] _gf_st_array_T_2 = ptw_gf_array; // @[TLB.scala:509:25, :601:63]
wire [13:0] _gf_inst_array_T_1 = ptw_gf_array; // @[TLB.scala:509:25, :602:46]
wire _priv_rw_ok_T = ~priv_s; // @[TLB.scala:370:20, :513:24]
wire _priv_rw_ok_T_1 = _priv_rw_ok_T | sum; // @[TLB.scala:510:16, :513:{24,32}]
wire [1:0] _GEN_40 = {_entries_barrier_2_io_y_u, _entries_barrier_1_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_lo_lo_hi; // @[package.scala:45:27]
assign priv_rw_ok_lo_lo_hi = _GEN_40; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_lo_lo_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_lo_lo_hi_1 = _GEN_40; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_lo_hi; // @[package.scala:45:27]
assign priv_x_ok_lo_lo_hi = _GEN_40; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_lo_hi_1; // @[package.scala:45:27]
assign priv_x_ok_lo_lo_hi_1 = _GEN_40; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_lo_lo = {priv_rw_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_41 = {_entries_barrier_5_io_y_u, _entries_barrier_4_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_lo_hi_hi; // @[package.scala:45:27]
assign priv_rw_ok_lo_hi_hi = _GEN_41; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_lo_hi_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_lo_hi_hi_1 = _GEN_41; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_hi_hi; // @[package.scala:45:27]
assign priv_x_ok_lo_hi_hi = _GEN_41; // @[package.scala:45:27]
wire [1:0] priv_x_ok_lo_hi_hi_1; // @[package.scala:45:27]
assign priv_x_ok_lo_hi_hi_1 = _GEN_41; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_lo_hi = {priv_rw_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] priv_rw_ok_lo = {priv_rw_ok_lo_hi, priv_rw_ok_lo_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_42 = {_entries_barrier_8_io_y_u, _entries_barrier_7_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_hi_lo_hi; // @[package.scala:45:27]
assign priv_rw_ok_hi_lo_hi = _GEN_42; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_lo_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_hi_lo_hi_1 = _GEN_42; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_lo_hi; // @[package.scala:45:27]
assign priv_x_ok_hi_lo_hi = _GEN_42; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_lo_hi_1; // @[package.scala:45:27]
assign priv_x_ok_hi_lo_hi_1 = _GEN_42; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_hi_lo = {priv_rw_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_43 = {_entries_barrier_10_io_y_u, _entries_barrier_9_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_hi_hi_lo; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_lo = _GEN_43; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_hi_lo_1; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_lo_1 = _GEN_43; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_lo; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_lo = _GEN_43; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_lo_1; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_lo_1 = _GEN_43; // @[package.scala:45:27]
wire [1:0] _GEN_44 = {_entries_barrier_12_io_y_u, _entries_barrier_11_io_y_u}; // @[package.scala:45:27, :267:25]
wire [1:0] priv_rw_ok_hi_hi_hi; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_hi = _GEN_44; // @[package.scala:45:27]
wire [1:0] priv_rw_ok_hi_hi_hi_1; // @[package.scala:45:27]
assign priv_rw_ok_hi_hi_hi_1 = _GEN_44; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_hi; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_hi = _GEN_44; // @[package.scala:45:27]
wire [1:0] priv_x_ok_hi_hi_hi_1; // @[package.scala:45:27]
assign priv_x_ok_hi_hi_hi_1 = _GEN_44; // @[package.scala:45:27]
wire [3:0] priv_rw_ok_hi_hi = {priv_rw_ok_hi_hi_hi, priv_rw_ok_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] priv_rw_ok_hi = {priv_rw_ok_hi_hi, priv_rw_ok_hi_lo}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_2 = {priv_rw_ok_hi, priv_rw_ok_lo}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_3 = _priv_rw_ok_T_1 ? _priv_rw_ok_T_2 : 13'h0; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_lo_lo_1 = {priv_rw_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] priv_rw_ok_lo_hi_1 = {priv_rw_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] priv_rw_ok_lo_1 = {priv_rw_ok_lo_hi_1, priv_rw_ok_lo_lo_1}; // @[package.scala:45:27]
wire [2:0] priv_rw_ok_hi_lo_1 = {priv_rw_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] priv_rw_ok_hi_hi_1 = {priv_rw_ok_hi_hi_hi_1, priv_rw_ok_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] priv_rw_ok_hi_1 = {priv_rw_ok_hi_hi_1, priv_rw_ok_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_4 = {priv_rw_ok_hi_1, priv_rw_ok_lo_1}; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_5 = ~_priv_rw_ok_T_4; // @[package.scala:45:27]
wire [12:0] _priv_rw_ok_T_6 = priv_s ? _priv_rw_ok_T_5 : 13'h0; // @[TLB.scala:370:20, :513:{75,84}]
wire [12:0] priv_rw_ok = _priv_rw_ok_T_3 | _priv_rw_ok_T_6; // @[TLB.scala:513:{23,70,75}]
wire [2:0] priv_x_ok_lo_lo = {priv_x_ok_lo_lo_hi, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] priv_x_ok_lo_hi = {priv_x_ok_lo_hi_hi, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] priv_x_ok_lo = {priv_x_ok_lo_hi, priv_x_ok_lo_lo}; // @[package.scala:45:27]
wire [2:0] priv_x_ok_hi_lo = {priv_x_ok_hi_lo_hi, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] priv_x_ok_hi_hi = {priv_x_ok_hi_hi_hi, priv_x_ok_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] priv_x_ok_hi = {priv_x_ok_hi_hi, priv_x_ok_hi_lo}; // @[package.scala:45:27]
wire [12:0] _priv_x_ok_T = {priv_x_ok_hi, priv_x_ok_lo}; // @[package.scala:45:27]
wire [12:0] _priv_x_ok_T_1 = ~_priv_x_ok_T; // @[package.scala:45:27]
wire [2:0] priv_x_ok_lo_lo_1 = {priv_x_ok_lo_lo_hi_1, _entries_barrier_io_y_u}; // @[package.scala:45:27, :267:25]
wire [2:0] priv_x_ok_lo_hi_1 = {priv_x_ok_lo_hi_hi_1, _entries_barrier_3_io_y_u}; // @[package.scala:45:27, :267:25]
wire [5:0] priv_x_ok_lo_1 = {priv_x_ok_lo_hi_1, priv_x_ok_lo_lo_1}; // @[package.scala:45:27]
wire [2:0] priv_x_ok_hi_lo_1 = {priv_x_ok_hi_lo_hi_1, _entries_barrier_6_io_y_u}; // @[package.scala:45:27, :267:25]
wire [3:0] priv_x_ok_hi_hi_1 = {priv_x_ok_hi_hi_hi_1, priv_x_ok_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] priv_x_ok_hi_1 = {priv_x_ok_hi_hi_1, priv_x_ok_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _priv_x_ok_T_2 = {priv_x_ok_hi_1, priv_x_ok_lo_1}; // @[package.scala:45:27]
wire [12:0] priv_x_ok = priv_s ? _priv_x_ok_T_1 : _priv_x_ok_T_2; // @[package.scala:45:27]
wire _stage1_bypass_T_1 = ~stage1_en; // @[TLB.scala:374:29, :517:83]
wire [12:0] _stage1_bypass_T_2 = {13{_stage1_bypass_T_1}}; // @[TLB.scala:517:{68,83}]
wire [1:0] stage1_bypass_lo_lo_hi = {_entries_barrier_2_io_y_ae_stage2, _entries_barrier_1_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] stage1_bypass_lo_lo = {stage1_bypass_lo_lo_hi, _entries_barrier_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] stage1_bypass_lo_hi_hi = {_entries_barrier_5_io_y_ae_stage2, _entries_barrier_4_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] stage1_bypass_lo_hi = {stage1_bypass_lo_hi_hi, _entries_barrier_3_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [5:0] stage1_bypass_lo = {stage1_bypass_lo_hi, stage1_bypass_lo_lo}; // @[package.scala:45:27]
wire [1:0] stage1_bypass_hi_lo_hi = {_entries_barrier_8_io_y_ae_stage2, _entries_barrier_7_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [2:0] stage1_bypass_hi_lo = {stage1_bypass_hi_lo_hi, _entries_barrier_6_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] stage1_bypass_hi_hi_lo = {_entries_barrier_10_io_y_ae_stage2, _entries_barrier_9_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [1:0] stage1_bypass_hi_hi_hi = {_entries_barrier_12_io_y_ae_stage2, _entries_barrier_11_io_y_ae_stage2}; // @[package.scala:45:27, :267:25]
wire [3:0] stage1_bypass_hi_hi = {stage1_bypass_hi_hi_hi, stage1_bypass_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] stage1_bypass_hi = {stage1_bypass_hi_hi, stage1_bypass_hi_lo}; // @[package.scala:45:27]
wire [12:0] _stage1_bypass_T_3 = {stage1_bypass_hi, stage1_bypass_lo}; // @[package.scala:45:27]
wire [12:0] _stage1_bypass_T_4 = _stage1_bypass_T_2 | _stage1_bypass_T_3; // @[package.scala:45:27]
wire [1:0] r_array_lo_lo_hi = {_entries_barrier_2_io_y_sr, _entries_barrier_1_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] r_array_lo_lo = {r_array_lo_lo_hi, _entries_barrier_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_lo_hi_hi = {_entries_barrier_5_io_y_sr, _entries_barrier_4_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] r_array_lo_hi = {r_array_lo_hi_hi, _entries_barrier_3_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [5:0] r_array_lo = {r_array_lo_hi, r_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] r_array_hi_lo_hi = {_entries_barrier_8_io_y_sr, _entries_barrier_7_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [2:0] r_array_hi_lo = {r_array_hi_lo_hi, _entries_barrier_6_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_lo = {_entries_barrier_10_io_y_sr, _entries_barrier_9_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_hi = {_entries_barrier_12_io_y_sr, _entries_barrier_11_io_y_sr}; // @[package.scala:45:27, :267:25]
wire [3:0] r_array_hi_hi = {r_array_hi_hi_hi, r_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] r_array_hi = {r_array_hi_hi, r_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _r_array_T = {r_array_hi, r_array_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_45 = {_entries_barrier_2_io_y_sx, _entries_barrier_1_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_lo_lo_hi_1; // @[package.scala:45:27]
assign r_array_lo_lo_hi_1 = _GEN_45; // @[package.scala:45:27]
wire [1:0] x_array_lo_lo_hi; // @[package.scala:45:27]
assign x_array_lo_lo_hi = _GEN_45; // @[package.scala:45:27]
wire [2:0] r_array_lo_lo_1 = {r_array_lo_lo_hi_1, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_46 = {_entries_barrier_5_io_y_sx, _entries_barrier_4_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_lo_hi_hi_1; // @[package.scala:45:27]
assign r_array_lo_hi_hi_1 = _GEN_46; // @[package.scala:45:27]
wire [1:0] x_array_lo_hi_hi; // @[package.scala:45:27]
assign x_array_lo_hi_hi = _GEN_46; // @[package.scala:45:27]
wire [2:0] r_array_lo_hi_1 = {r_array_lo_hi_hi_1, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [5:0] r_array_lo_1 = {r_array_lo_hi_1, r_array_lo_lo_1}; // @[package.scala:45:27]
wire [1:0] _GEN_47 = {_entries_barrier_8_io_y_sx, _entries_barrier_7_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_lo_hi_1; // @[package.scala:45:27]
assign r_array_hi_lo_hi_1 = _GEN_47; // @[package.scala:45:27]
wire [1:0] x_array_hi_lo_hi; // @[package.scala:45:27]
assign x_array_hi_lo_hi = _GEN_47; // @[package.scala:45:27]
wire [2:0] r_array_hi_lo_1 = {r_array_hi_lo_hi_1, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_48 = {_entries_barrier_10_io_y_sx, _entries_barrier_9_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_lo_1; // @[package.scala:45:27]
assign r_array_hi_hi_lo_1 = _GEN_48; // @[package.scala:45:27]
wire [1:0] x_array_hi_hi_lo; // @[package.scala:45:27]
assign x_array_hi_hi_lo = _GEN_48; // @[package.scala:45:27]
wire [1:0] _GEN_49 = {_entries_barrier_12_io_y_sx, _entries_barrier_11_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [1:0] r_array_hi_hi_hi_1; // @[package.scala:45:27]
assign r_array_hi_hi_hi_1 = _GEN_49; // @[package.scala:45:27]
wire [1:0] x_array_hi_hi_hi; // @[package.scala:45:27]
assign x_array_hi_hi_hi = _GEN_49; // @[package.scala:45:27]
wire [3:0] r_array_hi_hi_1 = {r_array_hi_hi_hi_1, r_array_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] r_array_hi_1 = {r_array_hi_hi_1, r_array_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _r_array_T_1 = {r_array_hi_1, r_array_lo_1}; // @[package.scala:45:27]
wire [12:0] _r_array_T_2 = mxr ? _r_array_T_1 : 13'h0; // @[package.scala:45:27]
wire [12:0] _r_array_T_3 = _r_array_T | _r_array_T_2; // @[package.scala:45:27]
wire [12:0] _r_array_T_4 = priv_rw_ok & _r_array_T_3; // @[TLB.scala:513:70, :520:{41,69}]
wire [12:0] _r_array_T_5 = _r_array_T_4; // @[TLB.scala:520:{41,113}]
wire [13:0] r_array = {1'h1, _r_array_T_5}; // @[TLB.scala:520:{20,113}]
wire [13:0] _pf_ld_array_T = r_array; // @[TLB.scala:520:20, :597:41]
wire [1:0] w_array_lo_lo_hi = {_entries_barrier_2_io_y_sw, _entries_barrier_1_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] w_array_lo_lo = {w_array_lo_lo_hi, _entries_barrier_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] w_array_lo_hi_hi = {_entries_barrier_5_io_y_sw, _entries_barrier_4_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] w_array_lo_hi = {w_array_lo_hi_hi, _entries_barrier_3_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [5:0] w_array_lo = {w_array_lo_hi, w_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] w_array_hi_lo_hi = {_entries_barrier_8_io_y_sw, _entries_barrier_7_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [2:0] w_array_hi_lo = {w_array_hi_lo_hi, _entries_barrier_6_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] w_array_hi_hi_lo = {_entries_barrier_10_io_y_sw, _entries_barrier_9_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [1:0] w_array_hi_hi_hi = {_entries_barrier_12_io_y_sw, _entries_barrier_11_io_y_sw}; // @[package.scala:45:27, :267:25]
wire [3:0] w_array_hi_hi = {w_array_hi_hi_hi, w_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] w_array_hi = {w_array_hi_hi, w_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _w_array_T = {w_array_hi, w_array_lo}; // @[package.scala:45:27]
wire [12:0] _w_array_T_1 = priv_rw_ok & _w_array_T; // @[package.scala:45:27]
wire [12:0] _w_array_T_2 = _w_array_T_1; // @[TLB.scala:521:{41,69}]
wire [13:0] w_array = {1'h1, _w_array_T_2}; // @[TLB.scala:521:{20,69}]
wire [2:0] x_array_lo_lo = {x_array_lo_lo_hi, _entries_barrier_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [2:0] x_array_lo_hi = {x_array_lo_hi_hi, _entries_barrier_3_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [5:0] x_array_lo = {x_array_lo_hi, x_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] x_array_hi_lo = {x_array_hi_lo_hi, _entries_barrier_6_io_y_sx}; // @[package.scala:45:27, :267:25]
wire [3:0] x_array_hi_hi = {x_array_hi_hi_hi, x_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] x_array_hi = {x_array_hi_hi, x_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _x_array_T = {x_array_hi, x_array_lo}; // @[package.scala:45:27]
wire [12:0] _x_array_T_1 = priv_x_ok & _x_array_T; // @[package.scala:45:27]
wire [12:0] _x_array_T_2 = _x_array_T_1; // @[TLB.scala:522:{40,68}]
wire [13:0] x_array = {1'h1, _x_array_T_2}; // @[TLB.scala:522:{20,68}]
wire [1:0] hr_array_lo_lo_hi = {_entries_barrier_2_io_y_hr, _entries_barrier_1_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] hr_array_lo_lo = {hr_array_lo_lo_hi, _entries_barrier_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_lo_hi_hi = {_entries_barrier_5_io_y_hr, _entries_barrier_4_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] hr_array_lo_hi = {hr_array_lo_hi_hi, _entries_barrier_3_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [5:0] hr_array_lo = {hr_array_lo_hi, hr_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] hr_array_hi_lo_hi = {_entries_barrier_8_io_y_hr, _entries_barrier_7_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [2:0] hr_array_hi_lo = {hr_array_hi_lo_hi, _entries_barrier_6_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_lo = {_entries_barrier_10_io_y_hr, _entries_barrier_9_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_hi = {_entries_barrier_12_io_y_hr, _entries_barrier_11_io_y_hr}; // @[package.scala:45:27, :267:25]
wire [3:0] hr_array_hi_hi = {hr_array_hi_hi_hi, hr_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] hr_array_hi = {hr_array_hi_hi, hr_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _hr_array_T = {hr_array_hi, hr_array_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_50 = {_entries_barrier_2_io_y_hx, _entries_barrier_1_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_lo_lo_hi_1; // @[package.scala:45:27]
assign hr_array_lo_lo_hi_1 = _GEN_50; // @[package.scala:45:27]
wire [1:0] hx_array_lo_lo_hi; // @[package.scala:45:27]
assign hx_array_lo_lo_hi = _GEN_50; // @[package.scala:45:27]
wire [2:0] hr_array_lo_lo_1 = {hr_array_lo_lo_hi_1, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_51 = {_entries_barrier_5_io_y_hx, _entries_barrier_4_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_lo_hi_hi_1; // @[package.scala:45:27]
assign hr_array_lo_hi_hi_1 = _GEN_51; // @[package.scala:45:27]
wire [1:0] hx_array_lo_hi_hi; // @[package.scala:45:27]
assign hx_array_lo_hi_hi = _GEN_51; // @[package.scala:45:27]
wire [2:0] hr_array_lo_hi_1 = {hr_array_lo_hi_hi_1, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [5:0] hr_array_lo_1 = {hr_array_lo_hi_1, hr_array_lo_lo_1}; // @[package.scala:45:27]
wire [1:0] _GEN_52 = {_entries_barrier_8_io_y_hx, _entries_barrier_7_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_lo_hi_1; // @[package.scala:45:27]
assign hr_array_hi_lo_hi_1 = _GEN_52; // @[package.scala:45:27]
wire [1:0] hx_array_hi_lo_hi; // @[package.scala:45:27]
assign hx_array_hi_lo_hi = _GEN_52; // @[package.scala:45:27]
wire [2:0] hr_array_hi_lo_1 = {hr_array_hi_lo_hi_1, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_53 = {_entries_barrier_10_io_y_hx, _entries_barrier_9_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_lo_1; // @[package.scala:45:27]
assign hr_array_hi_hi_lo_1 = _GEN_53; // @[package.scala:45:27]
wire [1:0] hx_array_hi_hi_lo; // @[package.scala:45:27]
assign hx_array_hi_hi_lo = _GEN_53; // @[package.scala:45:27]
wire [1:0] _GEN_54 = {_entries_barrier_12_io_y_hx, _entries_barrier_11_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [1:0] hr_array_hi_hi_hi_1; // @[package.scala:45:27]
assign hr_array_hi_hi_hi_1 = _GEN_54; // @[package.scala:45:27]
wire [1:0] hx_array_hi_hi_hi; // @[package.scala:45:27]
assign hx_array_hi_hi_hi = _GEN_54; // @[package.scala:45:27]
wire [3:0] hr_array_hi_hi_1 = {hr_array_hi_hi_hi_1, hr_array_hi_hi_lo_1}; // @[package.scala:45:27]
wire [6:0] hr_array_hi_1 = {hr_array_hi_hi_1, hr_array_hi_lo_1}; // @[package.scala:45:27]
wire [12:0] _hr_array_T_1 = {hr_array_hi_1, hr_array_lo_1}; // @[package.scala:45:27]
wire [12:0] _hr_array_T_2 = io_ptw_status_mxr_0 ? _hr_array_T_1 : 13'h0; // @[package.scala:45:27]
wire [12:0] _hr_array_T_3 = _hr_array_T | _hr_array_T_2; // @[package.scala:45:27]
wire [1:0] hw_array_lo_lo_hi = {_entries_barrier_2_io_y_hw, _entries_barrier_1_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] hw_array_lo_lo = {hw_array_lo_lo_hi, _entries_barrier_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] hw_array_lo_hi_hi = {_entries_barrier_5_io_y_hw, _entries_barrier_4_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] hw_array_lo_hi = {hw_array_lo_hi_hi, _entries_barrier_3_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [5:0] hw_array_lo = {hw_array_lo_hi, hw_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] hw_array_hi_lo_hi = {_entries_barrier_8_io_y_hw, _entries_barrier_7_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [2:0] hw_array_hi_lo = {hw_array_hi_lo_hi, _entries_barrier_6_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] hw_array_hi_hi_lo = {_entries_barrier_10_io_y_hw, _entries_barrier_9_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [1:0] hw_array_hi_hi_hi = {_entries_barrier_12_io_y_hw, _entries_barrier_11_io_y_hw}; // @[package.scala:45:27, :267:25]
wire [3:0] hw_array_hi_hi = {hw_array_hi_hi_hi, hw_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] hw_array_hi = {hw_array_hi_hi, hw_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _hw_array_T = {hw_array_hi, hw_array_lo}; // @[package.scala:45:27]
wire [2:0] hx_array_lo_lo = {hx_array_lo_lo_hi, _entries_barrier_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [2:0] hx_array_lo_hi = {hx_array_lo_hi_hi, _entries_barrier_3_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [5:0] hx_array_lo = {hx_array_lo_hi, hx_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] hx_array_hi_lo = {hx_array_hi_lo_hi, _entries_barrier_6_io_y_hx}; // @[package.scala:45:27, :267:25]
wire [3:0] hx_array_hi_hi = {hx_array_hi_hi_hi, hx_array_hi_hi_lo}; // @[package.scala:45:27]
wire [6:0] hx_array_hi = {hx_array_hi_hi, hx_array_hi_lo}; // @[package.scala:45:27]
wire [12:0] _hx_array_T = {hx_array_hi, hx_array_lo}; // @[package.scala:45:27]
wire [1:0] _pr_array_T = {2{prot_r}}; // @[TLB.scala:429:55, :529:26]
wire [1:0] pr_array_lo_lo_hi = {_entries_barrier_2_io_y_pr, _entries_barrier_1_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_lo_lo = {pr_array_lo_lo_hi, _entries_barrier_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [1:0] pr_array_lo_hi_hi = {_entries_barrier_5_io_y_pr, _entries_barrier_4_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_lo_hi = {pr_array_lo_hi_hi, _entries_barrier_3_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [5:0] pr_array_lo = {pr_array_lo_hi, pr_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pr_array_hi_lo_hi = {_entries_barrier_8_io_y_pr, _entries_barrier_7_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_hi_lo = {pr_array_hi_lo_hi, _entries_barrier_6_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [1:0] pr_array_hi_hi_hi = {_entries_barrier_11_io_y_pr, _entries_barrier_10_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [2:0] pr_array_hi_hi = {pr_array_hi_hi_hi, _entries_barrier_9_io_y_pr}; // @[package.scala:45:27, :267:25]
wire [5:0] pr_array_hi = {pr_array_hi_hi, pr_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _pr_array_T_1 = {pr_array_hi, pr_array_lo}; // @[package.scala:45:27]
wire [13:0] _pr_array_T_2 = {_pr_array_T, _pr_array_T_1}; // @[package.scala:45:27]
wire [13:0] _GEN_55 = ptw_ae_array | final_ae_array; // @[TLB.scala:506:25, :507:27, :529:104]
wire [13:0] _pr_array_T_3; // @[TLB.scala:529:104]
assign _pr_array_T_3 = _GEN_55; // @[TLB.scala:529:104]
wire [13:0] _pw_array_T_3; // @[TLB.scala:531:104]
assign _pw_array_T_3 = _GEN_55; // @[TLB.scala:529:104, :531:104]
wire [13:0] _px_array_T_3; // @[TLB.scala:533:104]
assign _px_array_T_3 = _GEN_55; // @[TLB.scala:529:104, :533:104]
wire [13:0] _pr_array_T_4 = ~_pr_array_T_3; // @[TLB.scala:529:{89,104}]
wire [13:0] pr_array = _pr_array_T_2 & _pr_array_T_4; // @[TLB.scala:529:{21,87,89}]
wire [1:0] _pw_array_T = {2{prot_w}}; // @[TLB.scala:430:55, :531:26]
wire [1:0] pw_array_lo_lo_hi = {_entries_barrier_2_io_y_pw, _entries_barrier_1_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_lo_lo = {pw_array_lo_lo_hi, _entries_barrier_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [1:0] pw_array_lo_hi_hi = {_entries_barrier_5_io_y_pw, _entries_barrier_4_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_lo_hi = {pw_array_lo_hi_hi, _entries_barrier_3_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [5:0] pw_array_lo = {pw_array_lo_hi, pw_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pw_array_hi_lo_hi = {_entries_barrier_8_io_y_pw, _entries_barrier_7_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_hi_lo = {pw_array_hi_lo_hi, _entries_barrier_6_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [1:0] pw_array_hi_hi_hi = {_entries_barrier_11_io_y_pw, _entries_barrier_10_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [2:0] pw_array_hi_hi = {pw_array_hi_hi_hi, _entries_barrier_9_io_y_pw}; // @[package.scala:45:27, :267:25]
wire [5:0] pw_array_hi = {pw_array_hi_hi, pw_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _pw_array_T_1 = {pw_array_hi, pw_array_lo}; // @[package.scala:45:27]
wire [13:0] _pw_array_T_2 = {_pw_array_T, _pw_array_T_1}; // @[package.scala:45:27]
wire [13:0] _pw_array_T_4 = ~_pw_array_T_3; // @[TLB.scala:531:{89,104}]
wire [13:0] pw_array = _pw_array_T_2 & _pw_array_T_4; // @[TLB.scala:531:{21,87,89}]
wire [1:0] _px_array_T = {2{prot_x}}; // @[TLB.scala:434:55, :533:26]
wire [1:0] px_array_lo_lo_hi = {_entries_barrier_2_io_y_px, _entries_barrier_1_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_lo_lo = {px_array_lo_lo_hi, _entries_barrier_io_y_px}; // @[package.scala:45:27, :267:25]
wire [1:0] px_array_lo_hi_hi = {_entries_barrier_5_io_y_px, _entries_barrier_4_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_lo_hi = {px_array_lo_hi_hi, _entries_barrier_3_io_y_px}; // @[package.scala:45:27, :267:25]
wire [5:0] px_array_lo = {px_array_lo_hi, px_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] px_array_hi_lo_hi = {_entries_barrier_8_io_y_px, _entries_barrier_7_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_hi_lo = {px_array_hi_lo_hi, _entries_barrier_6_io_y_px}; // @[package.scala:45:27, :267:25]
wire [1:0] px_array_hi_hi_hi = {_entries_barrier_11_io_y_px, _entries_barrier_10_io_y_px}; // @[package.scala:45:27, :267:25]
wire [2:0] px_array_hi_hi = {px_array_hi_hi_hi, _entries_barrier_9_io_y_px}; // @[package.scala:45:27, :267:25]
wire [5:0] px_array_hi = {px_array_hi_hi, px_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _px_array_T_1 = {px_array_hi, px_array_lo}; // @[package.scala:45:27]
wire [13:0] _px_array_T_2 = {_px_array_T, _px_array_T_1}; // @[package.scala:45:27]
wire [13:0] _px_array_T_4 = ~_px_array_T_3; // @[TLB.scala:533:{89,104}]
wire [13:0] px_array = _px_array_T_2 & _px_array_T_4; // @[TLB.scala:533:{21,87,89}]
wire [1:0] _eff_array_T = {2{_pma_io_resp_eff}}; // @[TLB.scala:422:19, :535:27]
wire [1:0] eff_array_lo_lo_hi = {_entries_barrier_2_io_y_eff, _entries_barrier_1_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_lo_lo = {eff_array_lo_lo_hi, _entries_barrier_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [1:0] eff_array_lo_hi_hi = {_entries_barrier_5_io_y_eff, _entries_barrier_4_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_lo_hi = {eff_array_lo_hi_hi, _entries_barrier_3_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [5:0] eff_array_lo = {eff_array_lo_hi, eff_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] eff_array_hi_lo_hi = {_entries_barrier_8_io_y_eff, _entries_barrier_7_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_hi_lo = {eff_array_hi_lo_hi, _entries_barrier_6_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [1:0] eff_array_hi_hi_hi = {_entries_barrier_11_io_y_eff, _entries_barrier_10_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [2:0] eff_array_hi_hi = {eff_array_hi_hi_hi, _entries_barrier_9_io_y_eff}; // @[package.scala:45:27, :267:25]
wire [5:0] eff_array_hi = {eff_array_hi_hi, eff_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _eff_array_T_1 = {eff_array_hi, eff_array_lo}; // @[package.scala:45:27]
wire [13:0] eff_array = {_eff_array_T, _eff_array_T_1}; // @[package.scala:45:27]
wire [1:0] _c_array_T = {2{cacheable}}; // @[TLB.scala:425:41, :537:25]
wire [1:0] _GEN_56 = {_entries_barrier_2_io_y_c, _entries_barrier_1_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_lo_lo_hi; // @[package.scala:45:27]
assign c_array_lo_lo_hi = _GEN_56; // @[package.scala:45:27]
wire [1:0] prefetchable_array_lo_lo_hi; // @[package.scala:45:27]
assign prefetchable_array_lo_lo_hi = _GEN_56; // @[package.scala:45:27]
wire [2:0] c_array_lo_lo = {c_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_57 = {_entries_barrier_5_io_y_c, _entries_barrier_4_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_lo_hi_hi; // @[package.scala:45:27]
assign c_array_lo_hi_hi = _GEN_57; // @[package.scala:45:27]
wire [1:0] prefetchable_array_lo_hi_hi; // @[package.scala:45:27]
assign prefetchable_array_lo_hi_hi = _GEN_57; // @[package.scala:45:27]
wire [2:0] c_array_lo_hi = {c_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] c_array_lo = {c_array_lo_hi, c_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] _GEN_58 = {_entries_barrier_8_io_y_c, _entries_barrier_7_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_hi_lo_hi; // @[package.scala:45:27]
assign c_array_hi_lo_hi = _GEN_58; // @[package.scala:45:27]
wire [1:0] prefetchable_array_hi_lo_hi; // @[package.scala:45:27]
assign prefetchable_array_hi_lo_hi = _GEN_58; // @[package.scala:45:27]
wire [2:0] c_array_hi_lo = {c_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] _GEN_59 = {_entries_barrier_11_io_y_c, _entries_barrier_10_io_y_c}; // @[package.scala:45:27, :267:25]
wire [1:0] c_array_hi_hi_hi; // @[package.scala:45:27]
assign c_array_hi_hi_hi = _GEN_59; // @[package.scala:45:27]
wire [1:0] prefetchable_array_hi_hi_hi; // @[package.scala:45:27]
assign prefetchable_array_hi_hi_hi = _GEN_59; // @[package.scala:45:27]
wire [2:0] c_array_hi_hi = {c_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] c_array_hi = {c_array_hi_hi, c_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _c_array_T_1 = {c_array_hi, c_array_lo}; // @[package.scala:45:27]
wire [13:0] c_array = {_c_array_T, _c_array_T_1}; // @[package.scala:45:27]
wire [13:0] lrscAllowed = c_array; // @[TLB.scala:537:20, :580:24]
wire [1:0] _ppp_array_T = {2{_pma_io_resp_pp}}; // @[TLB.scala:422:19, :539:27]
wire [1:0] ppp_array_lo_lo_hi = {_entries_barrier_2_io_y_ppp, _entries_barrier_1_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_lo_lo = {ppp_array_lo_lo_hi, _entries_barrier_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [1:0] ppp_array_lo_hi_hi = {_entries_barrier_5_io_y_ppp, _entries_barrier_4_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_lo_hi = {ppp_array_lo_hi_hi, _entries_barrier_3_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [5:0] ppp_array_lo = {ppp_array_lo_hi, ppp_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] ppp_array_hi_lo_hi = {_entries_barrier_8_io_y_ppp, _entries_barrier_7_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_hi_lo = {ppp_array_hi_lo_hi, _entries_barrier_6_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [1:0] ppp_array_hi_hi_hi = {_entries_barrier_11_io_y_ppp, _entries_barrier_10_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [2:0] ppp_array_hi_hi = {ppp_array_hi_hi_hi, _entries_barrier_9_io_y_ppp}; // @[package.scala:45:27, :267:25]
wire [5:0] ppp_array_hi = {ppp_array_hi_hi, ppp_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _ppp_array_T_1 = {ppp_array_hi, ppp_array_lo}; // @[package.scala:45:27]
wire [13:0] ppp_array = {_ppp_array_T, _ppp_array_T_1}; // @[package.scala:45:27]
wire [1:0] _paa_array_T = {2{_pma_io_resp_aa}}; // @[TLB.scala:422:19, :541:27]
wire [1:0] paa_array_lo_lo_hi = {_entries_barrier_2_io_y_paa, _entries_barrier_1_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_lo_lo = {paa_array_lo_lo_hi, _entries_barrier_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [1:0] paa_array_lo_hi_hi = {_entries_barrier_5_io_y_paa, _entries_barrier_4_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_lo_hi = {paa_array_lo_hi_hi, _entries_barrier_3_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [5:0] paa_array_lo = {paa_array_lo_hi, paa_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] paa_array_hi_lo_hi = {_entries_barrier_8_io_y_paa, _entries_barrier_7_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_hi_lo = {paa_array_hi_lo_hi, _entries_barrier_6_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [1:0] paa_array_hi_hi_hi = {_entries_barrier_11_io_y_paa, _entries_barrier_10_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [2:0] paa_array_hi_hi = {paa_array_hi_hi_hi, _entries_barrier_9_io_y_paa}; // @[package.scala:45:27, :267:25]
wire [5:0] paa_array_hi = {paa_array_hi_hi, paa_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _paa_array_T_1 = {paa_array_hi, paa_array_lo}; // @[package.scala:45:27]
wire [13:0] paa_array = {_paa_array_T, _paa_array_T_1}; // @[package.scala:45:27]
wire [1:0] _pal_array_T = {2{_pma_io_resp_al}}; // @[TLB.scala:422:19, :543:27]
wire [1:0] pal_array_lo_lo_hi = {_entries_barrier_2_io_y_pal, _entries_barrier_1_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_lo_lo = {pal_array_lo_lo_hi, _entries_barrier_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [1:0] pal_array_lo_hi_hi = {_entries_barrier_5_io_y_pal, _entries_barrier_4_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_lo_hi = {pal_array_lo_hi_hi, _entries_barrier_3_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [5:0] pal_array_lo = {pal_array_lo_hi, pal_array_lo_lo}; // @[package.scala:45:27]
wire [1:0] pal_array_hi_lo_hi = {_entries_barrier_8_io_y_pal, _entries_barrier_7_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_hi_lo = {pal_array_hi_lo_hi, _entries_barrier_6_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [1:0] pal_array_hi_hi_hi = {_entries_barrier_11_io_y_pal, _entries_barrier_10_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [2:0] pal_array_hi_hi = {pal_array_hi_hi_hi, _entries_barrier_9_io_y_pal}; // @[package.scala:45:27, :267:25]
wire [5:0] pal_array_hi = {pal_array_hi_hi, pal_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _pal_array_T_1 = {pal_array_hi, pal_array_lo}; // @[package.scala:45:27]
wire [13:0] pal_array = {_pal_array_T, _pal_array_T_1}; // @[package.scala:45:27]
wire [13:0] ppp_array_if_cached = ppp_array | c_array; // @[TLB.scala:537:20, :539:22, :544:39]
wire [13:0] paa_array_if_cached = paa_array | c_array; // @[TLB.scala:537:20, :541:22, :545:39]
wire [13:0] pal_array_if_cached = pal_array | c_array; // @[TLB.scala:537:20, :543:22, :546:39]
wire _prefetchable_array_T = cacheable & homogeneous; // @[TLBPermissions.scala:101:65]
wire [1:0] _prefetchable_array_T_1 = {_prefetchable_array_T, 1'h0}; // @[TLB.scala:547:{43,59}]
wire [2:0] prefetchable_array_lo_lo = {prefetchable_array_lo_lo_hi, _entries_barrier_io_y_c}; // @[package.scala:45:27, :267:25]
wire [2:0] prefetchable_array_lo_hi = {prefetchable_array_lo_hi_hi, _entries_barrier_3_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] prefetchable_array_lo = {prefetchable_array_lo_hi, prefetchable_array_lo_lo}; // @[package.scala:45:27]
wire [2:0] prefetchable_array_hi_lo = {prefetchable_array_hi_lo_hi, _entries_barrier_6_io_y_c}; // @[package.scala:45:27, :267:25]
wire [2:0] prefetchable_array_hi_hi = {prefetchable_array_hi_hi_hi, _entries_barrier_9_io_y_c}; // @[package.scala:45:27, :267:25]
wire [5:0] prefetchable_array_hi = {prefetchable_array_hi_hi, prefetchable_array_hi_lo}; // @[package.scala:45:27]
wire [11:0] _prefetchable_array_T_2 = {prefetchable_array_hi, prefetchable_array_lo}; // @[package.scala:45:27]
wire [13:0] prefetchable_array = {_prefetchable_array_T_1, _prefetchable_array_T_2}; // @[package.scala:45:27]
wire [39:0] _misaligned_T_3 = {37'h0, io_req_bits_vaddr_0[2:0]}; // @[TLB.scala:318:7, :550:39]
wire misaligned = |_misaligned_T_3; // @[TLB.scala:550:{39,77}]
assign _io_resp_ma_ld_T = misaligned; // @[TLB.scala:550:77, :645:31]
wire _bad_va_T = vm_enabled & stage1_en; // @[TLB.scala:374:29, :399:61, :568:21]
wire [39:0] bad_va_maskedVAddr = io_req_bits_vaddr_0 & 40'hC000000000; // @[TLB.scala:318:7, :559:43]
wire _bad_va_T_2 = bad_va_maskedVAddr == 40'h0; // @[TLB.scala:559:43, :560:51]
wire _bad_va_T_3 = bad_va_maskedVAddr == 40'hC000000000; // @[TLB.scala:559:43, :560:86]
wire _bad_va_T_4 = _bad_va_T_3; // @[TLB.scala:560:{71,86}]
wire _bad_va_T_5 = _bad_va_T_2 | _bad_va_T_4; // @[TLB.scala:560:{51,59,71}]
wire _bad_va_T_6 = ~_bad_va_T_5; // @[TLB.scala:560:{37,59}]
wire _bad_va_T_7 = _bad_va_T_6; // @[TLB.scala:560:{34,37}]
wire bad_va = _bad_va_T & _bad_va_T_7; // @[TLB.scala:560:34, :568:{21,34}]
wire _io_resp_pf_ld_T = bad_va; // @[TLB.scala:568:34, :633:28]
wire [13:0] _ae_array_T = misaligned ? eff_array : 14'h0; // @[TLB.scala:535:22, :550:77, :582:8]
wire [13:0] ae_array = _ae_array_T; // @[TLB.scala:582:{8,37}]
wire [13:0] _ae_array_T_1 = ~lrscAllowed; // @[TLB.scala:580:24, :583:19]
wire [13:0] _ae_ld_array_T = ~pr_array; // @[TLB.scala:529:87, :586:46]
wire [13:0] _ae_ld_array_T_1 = ae_array | _ae_ld_array_T; // @[TLB.scala:582:37, :586:{44,46}]
wire [13:0] ae_ld_array = _ae_ld_array_T_1; // @[TLB.scala:586:{24,44}]
wire [13:0] _ae_st_array_T = ~pw_array; // @[TLB.scala:531:87, :588:37]
wire [13:0] _ae_st_array_T_1 = ae_array | _ae_st_array_T; // @[TLB.scala:582:37, :588:{35,37}]
wire [13:0] _ae_st_array_T_3 = ~ppp_array_if_cached; // @[TLB.scala:544:39, :589:26]
wire [13:0] _ae_st_array_T_6 = ~pal_array_if_cached; // @[TLB.scala:546:39, :590:26]
wire [13:0] _ae_st_array_T_9 = ~paa_array_if_cached; // @[TLB.scala:545:39, :591:29]
wire [13:0] _must_alloc_array_T = ~ppp_array; // @[TLB.scala:539:22, :593:26]
wire [13:0] _must_alloc_array_T_2 = ~pal_array; // @[TLB.scala:543:22, :594:26]
wire [13:0] _must_alloc_array_T_5 = ~paa_array; // @[TLB.scala:541:22, :595:29]
wire [13:0] _pf_ld_array_T_1 = ~_pf_ld_array_T; // @[TLB.scala:597:{37,41}]
wire [13:0] _pf_ld_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73]
wire [13:0] _pf_ld_array_T_3 = _pf_ld_array_T_1 & _pf_ld_array_T_2; // @[TLB.scala:597:{37,71,73}]
wire [13:0] _pf_ld_array_T_4 = _pf_ld_array_T_3 | ptw_pf_array; // @[TLB.scala:508:25, :597:{71,88}]
wire [13:0] _pf_ld_array_T_5 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106]
wire [13:0] _pf_ld_array_T_6 = _pf_ld_array_T_4 & _pf_ld_array_T_5; // @[TLB.scala:597:{88,104,106}]
wire [13:0] pf_ld_array = _pf_ld_array_T_6; // @[TLB.scala:597:{24,104}]
wire [13:0] _pf_st_array_T = ~w_array; // @[TLB.scala:521:20, :598:44]
wire [13:0] _pf_st_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :598:55]
wire [13:0] _pf_st_array_T_2 = _pf_st_array_T & _pf_st_array_T_1; // @[TLB.scala:598:{44,53,55}]
wire [13:0] _pf_st_array_T_3 = _pf_st_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :598:{53,70}]
wire [13:0] _pf_st_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :598:88]
wire [13:0] _pf_st_array_T_5 = _pf_st_array_T_3 & _pf_st_array_T_4; // @[TLB.scala:598:{70,86,88}]
wire [13:0] _pf_inst_array_T = ~x_array; // @[TLB.scala:522:20, :599:25]
wire [13:0] _pf_inst_array_T_1 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :599:36]
wire [13:0] _pf_inst_array_T_2 = _pf_inst_array_T & _pf_inst_array_T_1; // @[TLB.scala:599:{25,34,36}]
wire [13:0] _pf_inst_array_T_3 = _pf_inst_array_T_2 | ptw_pf_array; // @[TLB.scala:508:25, :599:{34,51}]
wire [13:0] _pf_inst_array_T_4 = ~ptw_gf_array; // @[TLB.scala:509:25, :597:106, :599:69]
wire [13:0] pf_inst_array = _pf_inst_array_T_3 & _pf_inst_array_T_4; // @[TLB.scala:599:{51,67,69}]
wire [13:0] _gf_ld_array_T_4 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :600:100]
wire [13:0] _gf_ld_array_T_5 = _gf_ld_array_T_3 & _gf_ld_array_T_4; // @[TLB.scala:600:{82,98,100}]
wire [13:0] _gf_st_array_T_3 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :601:81]
wire [13:0] _gf_st_array_T_4 = _gf_st_array_T_2 & _gf_st_array_T_3; // @[TLB.scala:601:{63,79,81}]
wire [13:0] _gf_inst_array_T_2 = ~ptw_ae_array; // @[TLB.scala:506:25, :597:73, :602:64]
wire [13:0] _gf_inst_array_T_3 = _gf_inst_array_T_1 & _gf_inst_array_T_2; // @[TLB.scala:602:{46,62,64}]
wire _gpa_hits_hit_mask_T = r_gpa_vpn == vpn; // @[TLB.scala:335:30, :364:22, :606:73]
wire _gpa_hits_hit_mask_T_1 = r_gpa_valid & _gpa_hits_hit_mask_T; // @[TLB.scala:362:24, :606:{60,73}]
wire [11:0] _gpa_hits_hit_mask_T_2 = {12{_gpa_hits_hit_mask_T_1}}; // @[TLB.scala:606:{24,60}]
wire tlb_hit_if_not_gpa_miss = |real_hits; // @[package.scala:45:27]
wire tlb_hit = |_tlb_hit_T; // @[TLB.scala:611:{28,40}]
wire _tlb_miss_T_2 = ~bad_va; // @[TLB.scala:568:34, :613:56]
wire _tlb_miss_T_3 = _tlb_miss_T_1 & _tlb_miss_T_2; // @[TLB.scala:613:{29,53,56}]
wire _tlb_miss_T_4 = ~tlb_hit; // @[TLB.scala:611:40, :613:67]
wire tlb_miss = _tlb_miss_T_3 & _tlb_miss_T_4; // @[TLB.scala:613:{53,64,67}]
reg [6:0] state_vec_0; // @[Replacement.scala:305:17]
reg [2:0] state_reg_1; // @[Replacement.scala:168:70]
wire [1:0] _GEN_60 = {sector_hits_1, sector_hits_0}; // @[OneHot.scala:21:45]
wire [1:0] lo_lo; // @[OneHot.scala:21:45]
assign lo_lo = _GEN_60; // @[OneHot.scala:21:45]
wire [1:0] r_sectored_hit_bits_lo_lo; // @[OneHot.scala:21:45]
assign r_sectored_hit_bits_lo_lo = _GEN_60; // @[OneHot.scala:21:45]
wire [1:0] _GEN_61 = {sector_hits_3, sector_hits_2}; // @[OneHot.scala:21:45]
wire [1:0] lo_hi; // @[OneHot.scala:21:45]
assign lo_hi = _GEN_61; // @[OneHot.scala:21:45]
wire [1:0] r_sectored_hit_bits_lo_hi; // @[OneHot.scala:21:45]
assign r_sectored_hit_bits_lo_hi = _GEN_61; // @[OneHot.scala:21:45]
wire [3:0] lo = {lo_hi, lo_lo}; // @[OneHot.scala:21:45]
wire [3:0] lo_1 = lo; // @[OneHot.scala:21:45, :31:18]
wire [1:0] _GEN_62 = {sector_hits_5, sector_hits_4}; // @[OneHot.scala:21:45]
wire [1:0] hi_lo; // @[OneHot.scala:21:45]
assign hi_lo = _GEN_62; // @[OneHot.scala:21:45]
wire [1:0] r_sectored_hit_bits_hi_lo; // @[OneHot.scala:21:45]
assign r_sectored_hit_bits_hi_lo = _GEN_62; // @[OneHot.scala:21:45]
wire [1:0] _GEN_63 = {sector_hits_7, sector_hits_6}; // @[OneHot.scala:21:45]
wire [1:0] hi_hi; // @[OneHot.scala:21:45]
assign hi_hi = _GEN_63; // @[OneHot.scala:21:45]
wire [1:0] r_sectored_hit_bits_hi_hi; // @[OneHot.scala:21:45]
assign r_sectored_hit_bits_hi_hi = _GEN_63; // @[OneHot.scala:21:45]
wire [3:0] hi = {hi_hi, hi_lo}; // @[OneHot.scala:21:45]
wire [3:0] hi_1 = hi; // @[OneHot.scala:21:45, :30:18]
wire [3:0] _T_33 = hi_1 | lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] hi_2 = _T_33[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] lo_2 = _T_33[1:0]; // @[OneHot.scala:31:18, :32:28]
wire [2:0] state_vec_0_touch_way_sized = {|hi_1, |hi_2, hi_2[1] | lo_2[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire _state_vec_0_set_left_older_T = state_vec_0_touch_way_sized[2]; // @[package.scala:163:13]
wire state_vec_0_set_left_older = ~_state_vec_0_set_left_older_T; // @[Replacement.scala:196:{33,43}]
wire [2:0] state_vec_0_left_subtree_state = state_vec_0[5:3]; // @[package.scala:163:13]
wire [2:0] r_sectored_repl_addr_left_subtree_state = state_vec_0[5:3]; // @[package.scala:163:13]
wire [2:0] state_vec_0_right_subtree_state = state_vec_0[2:0]; // @[Replacement.scala:198:38, :305:17]
wire [2:0] r_sectored_repl_addr_right_subtree_state = state_vec_0[2:0]; // @[Replacement.scala:198:38, :245:38, :305:17]
wire [1:0] _state_vec_0_T = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13]
wire [1:0] _state_vec_0_T_11 = state_vec_0_touch_way_sized[1:0]; // @[package.scala:163:13]
wire _state_vec_0_set_left_older_T_1 = _state_vec_0_T[1]; // @[package.scala:163:13]
wire state_vec_0_set_left_older_1 = ~_state_vec_0_set_left_older_T_1; // @[Replacement.scala:196:{33,43}]
wire state_vec_0_left_subtree_state_1 = state_vec_0_left_subtree_state[1]; // @[package.scala:163:13]
wire state_vec_0_right_subtree_state_1 = state_vec_0_left_subtree_state[0]; // @[package.scala:163:13]
wire _state_vec_0_T_1 = _state_vec_0_T[0]; // @[package.scala:163:13]
wire _state_vec_0_T_5 = _state_vec_0_T[0]; // @[package.scala:163:13]
wire _state_vec_0_T_2 = _state_vec_0_T_1; // @[package.scala:163:13]
wire _state_vec_0_T_3 = ~_state_vec_0_T_2; // @[Replacement.scala:218:{7,17}]
wire _state_vec_0_T_4 = state_vec_0_set_left_older_1 ? state_vec_0_left_subtree_state_1 : _state_vec_0_T_3; // @[package.scala:163:13]
wire _state_vec_0_T_6 = _state_vec_0_T_5; // @[Replacement.scala:207:62, :218:17]
wire _state_vec_0_T_7 = ~_state_vec_0_T_6; // @[Replacement.scala:218:{7,17}]
wire _state_vec_0_T_8 = state_vec_0_set_left_older_1 ? _state_vec_0_T_7 : state_vec_0_right_subtree_state_1; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_vec_0_hi = {state_vec_0_set_left_older_1, _state_vec_0_T_4}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_vec_0_T_9 = {state_vec_0_hi, _state_vec_0_T_8}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_vec_0_T_10 = state_vec_0_set_left_older ? state_vec_0_left_subtree_state : _state_vec_0_T_9; // @[package.scala:163:13]
wire _state_vec_0_set_left_older_T_2 = _state_vec_0_T_11[1]; // @[Replacement.scala:196:43, :207:62]
wire state_vec_0_set_left_older_2 = ~_state_vec_0_set_left_older_T_2; // @[Replacement.scala:196:{33,43}]
wire state_vec_0_left_subtree_state_2 = state_vec_0_right_subtree_state[1]; // @[package.scala:163:13]
wire state_vec_0_right_subtree_state_2 = state_vec_0_right_subtree_state[0]; // @[Replacement.scala:198:38]
wire _state_vec_0_T_12 = _state_vec_0_T_11[0]; // @[package.scala:163:13]
wire _state_vec_0_T_16 = _state_vec_0_T_11[0]; // @[package.scala:163:13]
wire _state_vec_0_T_13 = _state_vec_0_T_12; // @[package.scala:163:13]
wire _state_vec_0_T_14 = ~_state_vec_0_T_13; // @[Replacement.scala:218:{7,17}]
wire _state_vec_0_T_15 = state_vec_0_set_left_older_2 ? state_vec_0_left_subtree_state_2 : _state_vec_0_T_14; // @[package.scala:163:13]
wire _state_vec_0_T_17 = _state_vec_0_T_16; // @[Replacement.scala:207:62, :218:17]
wire _state_vec_0_T_18 = ~_state_vec_0_T_17; // @[Replacement.scala:218:{7,17}]
wire _state_vec_0_T_19 = state_vec_0_set_left_older_2 ? _state_vec_0_T_18 : state_vec_0_right_subtree_state_2; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_vec_0_hi_1 = {state_vec_0_set_left_older_2, _state_vec_0_T_15}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_vec_0_T_20 = {state_vec_0_hi_1, _state_vec_0_T_19}; // @[Replacement.scala:202:12, :206:16]
wire [2:0] _state_vec_0_T_21 = state_vec_0_set_left_older ? _state_vec_0_T_20 : state_vec_0_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :202:12, :206:16]
wire [3:0] state_vec_0_hi_2 = {state_vec_0_set_left_older, _state_vec_0_T_10}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [6:0] _state_vec_0_T_22 = {state_vec_0_hi_2, _state_vec_0_T_21}; // @[Replacement.scala:202:12, :206:16]
wire [1:0] _GEN_64 = {superpage_hits_1, superpage_hits_0}; // @[OneHot.scala:21:45]
wire [1:0] lo_3; // @[OneHot.scala:21:45]
assign lo_3 = _GEN_64; // @[OneHot.scala:21:45]
wire [1:0] r_superpage_hit_bits_lo; // @[OneHot.scala:21:45]
assign r_superpage_hit_bits_lo = _GEN_64; // @[OneHot.scala:21:45]
wire [1:0] lo_4 = lo_3; // @[OneHot.scala:21:45, :31:18]
wire [1:0] _GEN_65 = {superpage_hits_3, superpage_hits_2}; // @[OneHot.scala:21:45]
wire [1:0] hi_3; // @[OneHot.scala:21:45]
assign hi_3 = _GEN_65; // @[OneHot.scala:21:45]
wire [1:0] r_superpage_hit_bits_hi; // @[OneHot.scala:21:45]
assign r_superpage_hit_bits_hi = _GEN_65; // @[OneHot.scala:21:45]
wire [1:0] hi_4 = hi_3; // @[OneHot.scala:21:45, :30:18]
wire [1:0] state_reg_touch_way_sized = {|hi_4, hi_4[1] | lo_4[1]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}]
wire _state_reg_set_left_older_T = state_reg_touch_way_sized[1]; // @[package.scala:163:13]
wire state_reg_set_left_older = ~_state_reg_set_left_older_T; // @[Replacement.scala:196:{33,43}]
wire state_reg_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13]
wire r_superpage_repl_addr_left_subtree_state = state_reg_1[1]; // @[package.scala:163:13]
wire state_reg_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38]
wire r_superpage_repl_addr_right_subtree_state = state_reg_1[0]; // @[Replacement.scala:168:70, :198:38, :245:38]
wire _state_reg_T = state_reg_touch_way_sized[0]; // @[package.scala:163:13]
wire _state_reg_T_4 = state_reg_touch_way_sized[0]; // @[package.scala:163:13]
wire _state_reg_T_1 = _state_reg_T; // @[package.scala:163:13]
wire _state_reg_T_2 = ~_state_reg_T_1; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_3 = state_reg_set_left_older ? state_reg_left_subtree_state : _state_reg_T_2; // @[package.scala:163:13]
wire _state_reg_T_5 = _state_reg_T_4; // @[Replacement.scala:207:62, :218:17]
wire _state_reg_T_6 = ~_state_reg_T_5; // @[Replacement.scala:218:{7,17}]
wire _state_reg_T_7 = state_reg_set_left_older ? _state_reg_T_6 : state_reg_right_subtree_state; // @[Replacement.scala:196:33, :198:38, :206:16, :218:7]
wire [1:0] state_reg_hi = {state_reg_set_left_older, _state_reg_T_3}; // @[Replacement.scala:196:33, :202:12, :203:16]
wire [2:0] _state_reg_T_8 = {state_reg_hi, _state_reg_T_7}; // @[Replacement.scala:202:12, :206:16]
wire [5:0] _multipleHits_T = real_hits[5:0]; // @[package.scala:45:27]
wire [2:0] _multipleHits_T_1 = _multipleHits_T[2:0]; // @[Misc.scala:181:37]
wire _multipleHits_T_2 = _multipleHits_T_1[0]; // @[Misc.scala:181:37]
wire multipleHits_leftOne = _multipleHits_T_2; // @[Misc.scala:178:18, :181:37]
wire [1:0] _multipleHits_T_3 = _multipleHits_T_1[2:1]; // @[Misc.scala:181:37, :182:39]
wire _multipleHits_T_4 = _multipleHits_T_3[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_1 = _multipleHits_T_4; // @[Misc.scala:178:18, :181:37]
wire _multipleHits_T_5 = _multipleHits_T_3[1]; // @[Misc.scala:182:39]
wire multipleHits_rightOne = _multipleHits_T_5; // @[Misc.scala:178:18, :182:39]
wire multipleHits_rightOne_1 = multipleHits_leftOne_1 | multipleHits_rightOne; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_7 = multipleHits_leftOne_1 & multipleHits_rightOne; // @[Misc.scala:178:18, :183:61]
wire multipleHits_rightTwo = _multipleHits_T_7; // @[Misc.scala:183:{49,61}]
wire _multipleHits_T_8 = multipleHits_rightTwo; // @[Misc.scala:183:{37,49}]
wire multipleHits_leftOne_2 = multipleHits_leftOne | multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_9 = multipleHits_leftOne & multipleHits_rightOne_1; // @[Misc.scala:178:18, :183:{16,61}]
wire multipleHits_leftTwo = _multipleHits_T_8 | _multipleHits_T_9; // @[Misc.scala:183:{37,49,61}]
wire [2:0] _multipleHits_T_10 = _multipleHits_T[5:3]; // @[Misc.scala:181:37, :182:39]
wire _multipleHits_T_11 = _multipleHits_T_10[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_3 = _multipleHits_T_11; // @[Misc.scala:178:18, :181:37]
wire [1:0] _multipleHits_T_12 = _multipleHits_T_10[2:1]; // @[Misc.scala:182:39]
wire _multipleHits_T_13 = _multipleHits_T_12[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_4 = _multipleHits_T_13; // @[Misc.scala:178:18, :181:37]
wire _multipleHits_T_14 = _multipleHits_T_12[1]; // @[Misc.scala:182:39]
wire multipleHits_rightOne_2 = _multipleHits_T_14; // @[Misc.scala:178:18, :182:39]
wire multipleHits_rightOne_3 = multipleHits_leftOne_4 | multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_16 = multipleHits_leftOne_4 & multipleHits_rightOne_2; // @[Misc.scala:178:18, :183:61]
wire multipleHits_rightTwo_1 = _multipleHits_T_16; // @[Misc.scala:183:{49,61}]
wire _multipleHits_T_17 = multipleHits_rightTwo_1; // @[Misc.scala:183:{37,49}]
wire multipleHits_rightOne_4 = multipleHits_leftOne_3 | multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_18 = multipleHits_leftOne_3 & multipleHits_rightOne_3; // @[Misc.scala:178:18, :183:{16,61}]
wire multipleHits_rightTwo_2 = _multipleHits_T_17 | _multipleHits_T_18; // @[Misc.scala:183:{37,49,61}]
wire multipleHits_leftOne_5 = multipleHits_leftOne_2 | multipleHits_rightOne_4; // @[Misc.scala:183:16]
wire _multipleHits_T_19 = multipleHits_leftTwo | multipleHits_rightTwo_2; // @[Misc.scala:183:{37,49}]
wire _multipleHits_T_20 = multipleHits_leftOne_2 & multipleHits_rightOne_4; // @[Misc.scala:183:{16,61}]
wire multipleHits_leftTwo_1 = _multipleHits_T_19 | _multipleHits_T_20; // @[Misc.scala:183:{37,49,61}]
wire [6:0] _multipleHits_T_21 = real_hits[12:6]; // @[package.scala:45:27]
wire [2:0] _multipleHits_T_22 = _multipleHits_T_21[2:0]; // @[Misc.scala:181:37, :182:39]
wire _multipleHits_T_23 = _multipleHits_T_22[0]; // @[Misc.scala:181:37]
wire multipleHits_leftOne_6 = _multipleHits_T_23; // @[Misc.scala:178:18, :181:37]
wire [1:0] _multipleHits_T_24 = _multipleHits_T_22[2:1]; // @[Misc.scala:181:37, :182:39]
wire _multipleHits_T_25 = _multipleHits_T_24[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_7 = _multipleHits_T_25; // @[Misc.scala:178:18, :181:37]
wire _multipleHits_T_26 = _multipleHits_T_24[1]; // @[Misc.scala:182:39]
wire multipleHits_rightOne_5 = _multipleHits_T_26; // @[Misc.scala:178:18, :182:39]
wire multipleHits_rightOne_6 = multipleHits_leftOne_7 | multipleHits_rightOne_5; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_28 = multipleHits_leftOne_7 & multipleHits_rightOne_5; // @[Misc.scala:178:18, :183:61]
wire multipleHits_rightTwo_3 = _multipleHits_T_28; // @[Misc.scala:183:{49,61}]
wire _multipleHits_T_29 = multipleHits_rightTwo_3; // @[Misc.scala:183:{37,49}]
wire multipleHits_leftOne_8 = multipleHits_leftOne_6 | multipleHits_rightOne_6; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_30 = multipleHits_leftOne_6 & multipleHits_rightOne_6; // @[Misc.scala:178:18, :183:{16,61}]
wire multipleHits_leftTwo_2 = _multipleHits_T_29 | _multipleHits_T_30; // @[Misc.scala:183:{37,49,61}]
wire [3:0] _multipleHits_T_31 = _multipleHits_T_21[6:3]; // @[Misc.scala:182:39]
wire [1:0] _multipleHits_T_32 = _multipleHits_T_31[1:0]; // @[Misc.scala:181:37, :182:39]
wire _multipleHits_T_33 = _multipleHits_T_32[0]; // @[Misc.scala:181:37]
wire multipleHits_leftOne_9 = _multipleHits_T_33; // @[Misc.scala:178:18, :181:37]
wire _multipleHits_T_34 = _multipleHits_T_32[1]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_rightOne_7 = _multipleHits_T_34; // @[Misc.scala:178:18, :182:39]
wire multipleHits_leftOne_10 = multipleHits_leftOne_9 | multipleHits_rightOne_7; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_36 = multipleHits_leftOne_9 & multipleHits_rightOne_7; // @[Misc.scala:178:18, :183:61]
wire multipleHits_leftTwo_3 = _multipleHits_T_36; // @[Misc.scala:183:{49,61}]
wire [1:0] _multipleHits_T_37 = _multipleHits_T_31[3:2]; // @[Misc.scala:182:39]
wire _multipleHits_T_38 = _multipleHits_T_37[0]; // @[Misc.scala:181:37, :182:39]
wire multipleHits_leftOne_11 = _multipleHits_T_38; // @[Misc.scala:178:18, :181:37]
wire _multipleHits_T_39 = _multipleHits_T_37[1]; // @[Misc.scala:182:39]
wire multipleHits_rightOne_8 = _multipleHits_T_39; // @[Misc.scala:178:18, :182:39]
wire multipleHits_rightOne_9 = multipleHits_leftOne_11 | multipleHits_rightOne_8; // @[Misc.scala:178:18, :183:16]
wire _multipleHits_T_41 = multipleHits_leftOne_11 & multipleHits_rightOne_8; // @[Misc.scala:178:18, :183:61]
wire multipleHits_rightTwo_4 = _multipleHits_T_41; // @[Misc.scala:183:{49,61}]
wire multipleHits_rightOne_10 = multipleHits_leftOne_10 | multipleHits_rightOne_9; // @[Misc.scala:183:16]
wire _multipleHits_T_42 = multipleHits_leftTwo_3 | multipleHits_rightTwo_4; // @[Misc.scala:183:{37,49}]
wire _multipleHits_T_43 = multipleHits_leftOne_10 & multipleHits_rightOne_9; // @[Misc.scala:183:{16,61}]
wire multipleHits_rightTwo_5 = _multipleHits_T_42 | _multipleHits_T_43; // @[Misc.scala:183:{37,49,61}]
wire multipleHits_rightOne_11 = multipleHits_leftOne_8 | multipleHits_rightOne_10; // @[Misc.scala:183:16]
wire _multipleHits_T_44 = multipleHits_leftTwo_2 | multipleHits_rightTwo_5; // @[Misc.scala:183:{37,49}]
wire _multipleHits_T_45 = multipleHits_leftOne_8 & multipleHits_rightOne_10; // @[Misc.scala:183:{16,61}]
wire multipleHits_rightTwo_6 = _multipleHits_T_44 | _multipleHits_T_45; // @[Misc.scala:183:{37,49,61}]
wire _multipleHits_T_46 = multipleHits_leftOne_5 | multipleHits_rightOne_11; // @[Misc.scala:183:16]
wire _multipleHits_T_47 = multipleHits_leftTwo_1 | multipleHits_rightTwo_6; // @[Misc.scala:183:{37,49}]
wire _multipleHits_T_48 = multipleHits_leftOne_5 & multipleHits_rightOne_11; // @[Misc.scala:183:{16,61}]
wire multipleHits = _multipleHits_T_47 | _multipleHits_T_48; // @[Misc.scala:183:{37,49,61}]
assign _io_req_ready_T = state == 2'h0; // @[TLB.scala:352:22, :631:25]
assign io_req_ready = _io_req_ready_T; // @[TLB.scala:318:7, :631:25]
wire [13:0] _io_resp_pf_ld_T_1 = pf_ld_array & hits; // @[TLB.scala:442:17, :597:24, :633:57]
wire _io_resp_pf_ld_T_2 = |_io_resp_pf_ld_T_1; // @[TLB.scala:633:{57,65}]
assign _io_resp_pf_ld_T_3 = _io_resp_pf_ld_T | _io_resp_pf_ld_T_2; // @[TLB.scala:633:{28,41,65}]
assign io_resp_pf_ld_0 = _io_resp_pf_ld_T_3; // @[TLB.scala:318:7, :633:41]
wire [13:0] _io_resp_pf_inst_T = pf_inst_array & hits; // @[TLB.scala:442:17, :599:67, :635:47]
wire _io_resp_pf_inst_T_1 = |_io_resp_pf_inst_T; // @[TLB.scala:635:{47,55}]
assign _io_resp_pf_inst_T_2 = bad_va | _io_resp_pf_inst_T_1; // @[TLB.scala:568:34, :635:{29,55}]
assign io_resp_pf_inst_0 = _io_resp_pf_inst_T_2; // @[TLB.scala:318:7, :635:29]
wire [13:0] _io_resp_ae_ld_T = ae_ld_array & hits; // @[TLB.scala:442:17, :586:24, :641:33]
assign _io_resp_ae_ld_T_1 = |_io_resp_ae_ld_T; // @[TLB.scala:641:{33,41}]
assign io_resp_ae_ld_0 = _io_resp_ae_ld_T_1; // @[TLB.scala:318:7, :641:41]
wire [13:0] _io_resp_ae_inst_T = ~px_array; // @[TLB.scala:533:87, :643:23]
wire [13:0] _io_resp_ae_inst_T_1 = _io_resp_ae_inst_T & hits; // @[TLB.scala:442:17, :643:{23,33}]
assign _io_resp_ae_inst_T_2 = |_io_resp_ae_inst_T_1; // @[TLB.scala:643:{33,41}]
assign io_resp_ae_inst_0 = _io_resp_ae_inst_T_2; // @[TLB.scala:318:7, :643:41]
assign io_resp_ma_ld_0 = _io_resp_ma_ld_T; // @[TLB.scala:318:7, :645:31]
wire [13:0] _io_resp_cacheable_T = c_array & hits; // @[TLB.scala:442:17, :537:20, :648:33]
assign _io_resp_cacheable_T_1 = |_io_resp_cacheable_T; // @[TLB.scala:648:{33,41}]
assign io_resp_cacheable_0 = _io_resp_cacheable_T_1; // @[TLB.scala:318:7, :648:41]
wire [13:0] _io_resp_prefetchable_T = prefetchable_array & hits; // @[TLB.scala:442:17, :547:31, :650:47]
wire _io_resp_prefetchable_T_1 = |_io_resp_prefetchable_T; // @[TLB.scala:650:{47,55}]
assign _io_resp_prefetchable_T_2 = _io_resp_prefetchable_T_1; // @[TLB.scala:650:{55,59}]
assign io_resp_prefetchable_0 = _io_resp_prefetchable_T_2; // @[TLB.scala:318:7, :650:59]
wire _io_resp_miss_T_1 = _io_resp_miss_T | tlb_miss; // @[TLB.scala:613:64, :651:{29,52}]
assign _io_resp_miss_T_2 = _io_resp_miss_T_1 | multipleHits; // @[Misc.scala:183:49]
assign io_resp_miss_0 = _io_resp_miss_T_2; // @[TLB.scala:318:7, :651:64]
assign _io_resp_paddr_T_1 = {ppn, _io_resp_paddr_T}; // @[Mux.scala:30:73]
assign io_resp_paddr_0 = _io_resp_paddr_T_1; // @[TLB.scala:318:7, :652:23]
wire [27:0] _io_resp_gpa_page_T_1 = {1'h0, vpn}; // @[TLB.scala:335:30, :657:36]
wire [27:0] io_resp_gpa_page = _io_resp_gpa_page_T_1; // @[TLB.scala:657:{19,36}]
wire [26:0] _io_resp_gpa_page_T_2 = r_gpa[38:12]; // @[TLB.scala:363:18, :657:58]
wire [11:0] _io_resp_gpa_offset_T = r_gpa[11:0]; // @[TLB.scala:363:18, :658:47]
wire [11:0] io_resp_gpa_offset = _io_resp_gpa_offset_T_1; // @[TLB.scala:658:{21,82}]
assign _io_resp_gpa_T = {io_resp_gpa_page, io_resp_gpa_offset}; // @[TLB.scala:657:19, :658:21, :659:8]
assign io_resp_gpa_0 = _io_resp_gpa_T; // @[TLB.scala:318:7, :659:8]
assign io_ptw_req_valid_0 = _io_ptw_req_valid_T; // @[TLB.scala:318:7, :662:29]
wire r_superpage_repl_addr_left_subtree_older = state_reg_1[2]; // @[Replacement.scala:168:70, :243:38]
wire _r_superpage_repl_addr_T = r_superpage_repl_addr_left_subtree_state; // @[package.scala:163:13]
wire _r_superpage_repl_addr_T_1 = r_superpage_repl_addr_right_subtree_state; // @[Replacement.scala:245:38, :262:12]
wire _r_superpage_repl_addr_T_2 = r_superpage_repl_addr_left_subtree_older ? _r_superpage_repl_addr_T : _r_superpage_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_superpage_repl_addr_T_3 = {r_superpage_repl_addr_left_subtree_older, _r_superpage_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [1:0] r_superpage_repl_addr_valids_lo = {superpage_entries_1_valid_0, superpage_entries_0_valid_0}; // @[package.scala:45:27]
wire [1:0] r_superpage_repl_addr_valids_hi = {superpage_entries_3_valid_0, superpage_entries_2_valid_0}; // @[package.scala:45:27]
wire [3:0] r_superpage_repl_addr_valids = {r_superpage_repl_addr_valids_hi, r_superpage_repl_addr_valids_lo}; // @[package.scala:45:27]
wire _r_superpage_repl_addr_T_4 = &r_superpage_repl_addr_valids; // @[package.scala:45:27]
wire [3:0] _r_superpage_repl_addr_T_5 = ~r_superpage_repl_addr_valids; // @[package.scala:45:27]
wire _r_superpage_repl_addr_T_6 = _r_superpage_repl_addr_T_5[0]; // @[OneHot.scala:48:45]
wire _r_superpage_repl_addr_T_7 = _r_superpage_repl_addr_T_5[1]; // @[OneHot.scala:48:45]
wire _r_superpage_repl_addr_T_8 = _r_superpage_repl_addr_T_5[2]; // @[OneHot.scala:48:45]
wire _r_superpage_repl_addr_T_9 = _r_superpage_repl_addr_T_5[3]; // @[OneHot.scala:48:45]
wire [1:0] _r_superpage_repl_addr_T_10 = {1'h1, ~_r_superpage_repl_addr_T_8}; // @[OneHot.scala:48:45]
wire [1:0] _r_superpage_repl_addr_T_11 = _r_superpage_repl_addr_T_7 ? 2'h1 : _r_superpage_repl_addr_T_10; // @[OneHot.scala:48:45]
wire [1:0] _r_superpage_repl_addr_T_12 = _r_superpage_repl_addr_T_6 ? 2'h0 : _r_superpage_repl_addr_T_11; // @[OneHot.scala:48:45]
wire [1:0] _r_superpage_repl_addr_T_13 = _r_superpage_repl_addr_T_4 ? _r_superpage_repl_addr_T_3 : _r_superpage_repl_addr_T_12; // @[Mux.scala:50:70]
wire r_sectored_repl_addr_left_subtree_older = state_vec_0[6]; // @[Replacement.scala:243:38, :305:17]
wire r_sectored_repl_addr_left_subtree_older_1 = r_sectored_repl_addr_left_subtree_state[2]; // @[package.scala:163:13]
wire r_sectored_repl_addr_left_subtree_state_1 = r_sectored_repl_addr_left_subtree_state[1]; // @[package.scala:163:13]
wire _r_sectored_repl_addr_T = r_sectored_repl_addr_left_subtree_state_1; // @[package.scala:163:13]
wire r_sectored_repl_addr_right_subtree_state_1 = r_sectored_repl_addr_left_subtree_state[0]; // @[package.scala:163:13]
wire _r_sectored_repl_addr_T_1 = r_sectored_repl_addr_right_subtree_state_1; // @[Replacement.scala:245:38, :262:12]
wire _r_sectored_repl_addr_T_2 = r_sectored_repl_addr_left_subtree_older_1 ? _r_sectored_repl_addr_T : _r_sectored_repl_addr_T_1; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_sectored_repl_addr_T_3 = {r_sectored_repl_addr_left_subtree_older_1, _r_sectored_repl_addr_T_2}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire r_sectored_repl_addr_left_subtree_older_2 = r_sectored_repl_addr_right_subtree_state[2]; // @[Replacement.scala:243:38, :245:38]
wire r_sectored_repl_addr_left_subtree_state_2 = r_sectored_repl_addr_right_subtree_state[1]; // @[package.scala:163:13]
wire _r_sectored_repl_addr_T_4 = r_sectored_repl_addr_left_subtree_state_2; // @[package.scala:163:13]
wire r_sectored_repl_addr_right_subtree_state_2 = r_sectored_repl_addr_right_subtree_state[0]; // @[Replacement.scala:245:38]
wire _r_sectored_repl_addr_T_5 = r_sectored_repl_addr_right_subtree_state_2; // @[Replacement.scala:245:38, :262:12]
wire _r_sectored_repl_addr_T_6 = r_sectored_repl_addr_left_subtree_older_2 ? _r_sectored_repl_addr_T_4 : _r_sectored_repl_addr_T_5; // @[Replacement.scala:243:38, :250:16, :262:12]
wire [1:0] _r_sectored_repl_addr_T_7 = {r_sectored_repl_addr_left_subtree_older_2, _r_sectored_repl_addr_T_6}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [1:0] _r_sectored_repl_addr_T_8 = r_sectored_repl_addr_left_subtree_older ? _r_sectored_repl_addr_T_3 : _r_sectored_repl_addr_T_7; // @[Replacement.scala:243:38, :249:12, :250:16]
wire [2:0] _r_sectored_repl_addr_T_9 = {r_sectored_repl_addr_left_subtree_older, _r_sectored_repl_addr_T_8}; // @[Replacement.scala:243:38, :249:12, :250:16]
wire _r_sectored_repl_addr_valids_T_1 = _r_sectored_repl_addr_valids_T | sectored_entries_0_0_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_2 = _r_sectored_repl_addr_valids_T_1 | sectored_entries_0_0_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_4 = _r_sectored_repl_addr_valids_T_3 | sectored_entries_0_1_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_5 = _r_sectored_repl_addr_valids_T_4 | sectored_entries_0_1_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_7 = _r_sectored_repl_addr_valids_T_6 | sectored_entries_0_2_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_8 = _r_sectored_repl_addr_valids_T_7 | sectored_entries_0_2_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_10 = _r_sectored_repl_addr_valids_T_9 | sectored_entries_0_3_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_11 = _r_sectored_repl_addr_valids_T_10 | sectored_entries_0_3_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_13 = _r_sectored_repl_addr_valids_T_12 | sectored_entries_0_4_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_14 = _r_sectored_repl_addr_valids_T_13 | sectored_entries_0_4_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_16 = _r_sectored_repl_addr_valids_T_15 | sectored_entries_0_5_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_17 = _r_sectored_repl_addr_valids_T_16 | sectored_entries_0_5_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_19 = _r_sectored_repl_addr_valids_T_18 | sectored_entries_0_6_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_20 = _r_sectored_repl_addr_valids_T_19 | sectored_entries_0_6_valid_3; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_22 = _r_sectored_repl_addr_valids_T_21 | sectored_entries_0_7_valid_2; // @[package.scala:81:59]
wire _r_sectored_repl_addr_valids_T_23 = _r_sectored_repl_addr_valids_T_22 | sectored_entries_0_7_valid_3; // @[package.scala:81:59]
wire [1:0] r_sectored_repl_addr_valids_lo_lo = {_r_sectored_repl_addr_valids_T_5, _r_sectored_repl_addr_valids_T_2}; // @[package.scala:45:27, :81:59]
wire [1:0] r_sectored_repl_addr_valids_lo_hi = {_r_sectored_repl_addr_valids_T_11, _r_sectored_repl_addr_valids_T_8}; // @[package.scala:45:27, :81:59]
wire [3:0] r_sectored_repl_addr_valids_lo = {r_sectored_repl_addr_valids_lo_hi, r_sectored_repl_addr_valids_lo_lo}; // @[package.scala:45:27]
wire [1:0] r_sectored_repl_addr_valids_hi_lo = {_r_sectored_repl_addr_valids_T_17, _r_sectored_repl_addr_valids_T_14}; // @[package.scala:45:27, :81:59]
wire [1:0] r_sectored_repl_addr_valids_hi_hi = {_r_sectored_repl_addr_valids_T_23, _r_sectored_repl_addr_valids_T_20}; // @[package.scala:45:27, :81:59]
wire [3:0] r_sectored_repl_addr_valids_hi = {r_sectored_repl_addr_valids_hi_hi, r_sectored_repl_addr_valids_hi_lo}; // @[package.scala:45:27]
wire [7:0] r_sectored_repl_addr_valids = {r_sectored_repl_addr_valids_hi, r_sectored_repl_addr_valids_lo}; // @[package.scala:45:27]
wire _r_sectored_repl_addr_T_10 = &r_sectored_repl_addr_valids; // @[package.scala:45:27]
wire [7:0] _r_sectored_repl_addr_T_11 = ~r_sectored_repl_addr_valids; // @[package.scala:45:27]
wire _r_sectored_repl_addr_T_12 = _r_sectored_repl_addr_T_11[0]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_13 = _r_sectored_repl_addr_T_11[1]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_14 = _r_sectored_repl_addr_T_11[2]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_15 = _r_sectored_repl_addr_T_11[3]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_16 = _r_sectored_repl_addr_T_11[4]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_17 = _r_sectored_repl_addr_T_11[5]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_18 = _r_sectored_repl_addr_T_11[6]; // @[OneHot.scala:48:45]
wire _r_sectored_repl_addr_T_19 = _r_sectored_repl_addr_T_11[7]; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_20 = {2'h3, ~_r_sectored_repl_addr_T_18}; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_21 = _r_sectored_repl_addr_T_17 ? 3'h5 : _r_sectored_repl_addr_T_20; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_22 = _r_sectored_repl_addr_T_16 ? 3'h4 : _r_sectored_repl_addr_T_21; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_23 = _r_sectored_repl_addr_T_15 ? 3'h3 : _r_sectored_repl_addr_T_22; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_24 = _r_sectored_repl_addr_T_14 ? 3'h2 : _r_sectored_repl_addr_T_23; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_25 = _r_sectored_repl_addr_T_13 ? 3'h1 : _r_sectored_repl_addr_T_24; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_26 = _r_sectored_repl_addr_T_12 ? 3'h0 : _r_sectored_repl_addr_T_25; // @[OneHot.scala:48:45]
wire [2:0] _r_sectored_repl_addr_T_27 = _r_sectored_repl_addr_T_10 ? _r_sectored_repl_addr_T_9 : _r_sectored_repl_addr_T_26; // @[Mux.scala:50:70]
wire _r_sectored_hit_valid_T = sector_hits_0 | sector_hits_1; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_1 = _r_sectored_hit_valid_T | sector_hits_2; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_2 = _r_sectored_hit_valid_T_1 | sector_hits_3; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_3 = _r_sectored_hit_valid_T_2 | sector_hits_4; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_4 = _r_sectored_hit_valid_T_3 | sector_hits_5; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_5 = _r_sectored_hit_valid_T_4 | sector_hits_6; // @[package.scala:81:59]
wire _r_sectored_hit_valid_T_6 = _r_sectored_hit_valid_T_5 | sector_hits_7; // @[package.scala:81:59]
wire [3:0] r_sectored_hit_bits_lo = {r_sectored_hit_bits_lo_hi, r_sectored_hit_bits_lo_lo}; // @[OneHot.scala:21:45]
wire [3:0] r_sectored_hit_bits_hi = {r_sectored_hit_bits_hi_hi, r_sectored_hit_bits_hi_lo}; // @[OneHot.scala:21:45]
wire [7:0] _r_sectored_hit_bits_T = {r_sectored_hit_bits_hi, r_sectored_hit_bits_lo}; // @[OneHot.scala:21:45]
wire [3:0] r_sectored_hit_bits_hi_1 = _r_sectored_hit_bits_T[7:4]; // @[OneHot.scala:21:45, :30:18]
wire [3:0] r_sectored_hit_bits_lo_1 = _r_sectored_hit_bits_T[3:0]; // @[OneHot.scala:21:45, :31:18]
wire _r_sectored_hit_bits_T_1 = |r_sectored_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _r_sectored_hit_bits_T_2 = r_sectored_hit_bits_hi_1 | r_sectored_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] r_sectored_hit_bits_hi_2 = _r_sectored_hit_bits_T_2[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] r_sectored_hit_bits_lo_2 = _r_sectored_hit_bits_T_2[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _r_sectored_hit_bits_T_3 = |r_sectored_hit_bits_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _r_sectored_hit_bits_T_4 = r_sectored_hit_bits_hi_2 | r_sectored_hit_bits_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _r_sectored_hit_bits_T_5 = _r_sectored_hit_bits_T_4[1]; // @[OneHot.scala:32:28]
wire [1:0] _r_sectored_hit_bits_T_6 = {_r_sectored_hit_bits_T_3, _r_sectored_hit_bits_T_5}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _r_sectored_hit_bits_T_7 = {_r_sectored_hit_bits_T_1, _r_sectored_hit_bits_T_6}; // @[OneHot.scala:32:{10,14}]
wire _r_superpage_hit_valid_T = superpage_hits_0 | superpage_hits_1; // @[package.scala:81:59]
wire _r_superpage_hit_valid_T_1 = _r_superpage_hit_valid_T | superpage_hits_2; // @[package.scala:81:59]
wire _r_superpage_hit_valid_T_2 = _r_superpage_hit_valid_T_1 | superpage_hits_3; // @[package.scala:81:59]
wire [3:0] _r_superpage_hit_bits_T = {r_superpage_hit_bits_hi, r_superpage_hit_bits_lo}; // @[OneHot.scala:21:45]
wire [1:0] r_superpage_hit_bits_hi_1 = _r_superpage_hit_bits_T[3:2]; // @[OneHot.scala:21:45, :30:18]
wire [1:0] r_superpage_hit_bits_lo_1 = _r_superpage_hit_bits_T[1:0]; // @[OneHot.scala:21:45, :31:18]
wire _r_superpage_hit_bits_T_1 = |r_superpage_hit_bits_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _r_superpage_hit_bits_T_2 = r_superpage_hit_bits_hi_1 | r_superpage_hit_bits_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _r_superpage_hit_bits_T_3 = _r_superpage_hit_bits_T_2[1]; // @[OneHot.scala:32:28]
wire [1:0] _r_superpage_hit_bits_T_4 = {_r_superpage_hit_bits_T_1, _r_superpage_hit_bits_T_3}; // @[OneHot.scala:32:{10,14}]
wire [1:0] _state_T = {1'h1, io_sfence_valid_0}; // @[TLB.scala:318:7, :704:45] |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_14 :
input clock : Clock
input reset : Reset
output io : { flip d : UInt<1>, q : UInt<1>}
node _output_T = asAsyncReset(reset)
node _output_T_1 = bits(io.d, 0, 0)
inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_14
connect output_chain.clock, clock
connect output_chain.reset, _output_T
connect output_chain.io.d, _output_T_1
wire output_0 : UInt<1>
connect output_0, output_chain.io.q
connect io.q, output_0 | module AsyncResetSynchronizerShiftReg_w1_d3_i0_14( // @[SynchronizerReg.scala:80:7]
input clock, // @[SynchronizerReg.scala:80:7]
input reset, // @[SynchronizerReg.scala:80:7]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7]
wire _output_T = reset; // @[SynchronizerReg.scala:86:21]
wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41]
wire output_0; // @[ShiftReg.scala:48:24]
wire io_q_0; // @[SynchronizerReg.scala:80:7]
assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7]
AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_14 output_chain ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (_output_T), // @[SynchronizerReg.scala:86:21]
.io_d (_output_T_1), // @[SynchronizerReg.scala:87:41]
.io_q (output_0)
); // @[ShiftReg.scala:45:23]
assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLSlaveBEToNoC :
input clock : Clock
input reset : Reset
output io : { tilelink : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flits : { b : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}, flip e : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}}
invalidate io.tilelink.e.bits.sink
invalidate io.tilelink.e.valid
invalidate io.tilelink.e.ready
invalidate io.tilelink.d.bits.corrupt
invalidate io.tilelink.d.bits.data
invalidate io.tilelink.d.bits.denied
invalidate io.tilelink.d.bits.sink
invalidate io.tilelink.d.bits.source
invalidate io.tilelink.d.bits.size
invalidate io.tilelink.d.bits.param
invalidate io.tilelink.d.bits.opcode
invalidate io.tilelink.d.valid
invalidate io.tilelink.d.ready
invalidate io.tilelink.c.bits.corrupt
invalidate io.tilelink.c.bits.data
invalidate io.tilelink.c.bits.address
invalidate io.tilelink.c.bits.source
invalidate io.tilelink.c.bits.size
invalidate io.tilelink.c.bits.param
invalidate io.tilelink.c.bits.opcode
invalidate io.tilelink.c.valid
invalidate io.tilelink.c.ready
invalidate io.tilelink.b.bits.corrupt
invalidate io.tilelink.b.bits.data
invalidate io.tilelink.b.bits.mask
invalidate io.tilelink.b.bits.address
invalidate io.tilelink.b.bits.source
invalidate io.tilelink.b.bits.size
invalidate io.tilelink.b.bits.param
invalidate io.tilelink.b.bits.opcode
invalidate io.tilelink.b.valid
invalidate io.tilelink.b.ready
invalidate io.tilelink.a.bits.corrupt
invalidate io.tilelink.a.bits.data
invalidate io.tilelink.a.bits.mask
invalidate io.tilelink.a.bits.address
invalidate io.tilelink.a.bits.source
invalidate io.tilelink.a.bits.size
invalidate io.tilelink.a.bits.param
invalidate io.tilelink.a.bits.opcode
invalidate io.tilelink.a.valid
invalidate io.tilelink.a.ready
inst b of TLBToNoC
connect b.clock, clock
connect b.reset, reset
inst e of TLEFromNoC
connect e.clock, clock
connect e.reset, reset
connect b.io.protocol, io.tilelink.b
connect io.tilelink.e.bits, e.io.protocol.bits
connect io.tilelink.e.valid, e.io.protocol.valid
connect e.io.protocol.ready, io.tilelink.e.ready
connect io.flits.b.bits, b.io.flit.bits
connect io.flits.b.valid, b.io.flit.valid
connect b.io.flit.ready, io.flits.b.ready
connect e.io.flit, io.flits.e | module TLSlaveBEToNoC( // @[Tilelink.scala:189:7]
input clock, // @[Tilelink.scala:189:7]
input reset, // @[Tilelink.scala:189:7]
input io_flits_b_ready, // @[Tilelink.scala:196:14]
output io_flits_b_valid, // @[Tilelink.scala:196:14]
output io_flits_b_bits_head, // @[Tilelink.scala:196:14]
output io_flits_b_bits_tail, // @[Tilelink.scala:196:14]
output [72:0] io_flits_b_bits_payload, // @[Tilelink.scala:196:14]
output [3:0] io_flits_b_bits_egress_id, // @[Tilelink.scala:196:14]
output io_flits_e_ready, // @[Tilelink.scala:196:14]
input io_flits_e_valid, // @[Tilelink.scala:196:14]
input io_flits_e_bits_head, // @[Tilelink.scala:196:14]
input io_flits_e_bits_tail // @[Tilelink.scala:196:14]
);
TLBToNoC b ( // @[Tilelink.scala:204:17]
.clock (clock),
.reset (reset),
.io_flit_ready (io_flits_b_ready),
.io_flit_valid (io_flits_b_valid),
.io_flit_bits_head (io_flits_b_bits_head),
.io_flit_bits_tail (io_flits_b_bits_tail),
.io_flit_bits_payload (io_flits_b_bits_payload),
.io_flit_bits_egress_id (io_flits_b_bits_egress_id)
); // @[Tilelink.scala:204:17]
TLEFromNoC e ( // @[Tilelink.scala:205:17]
.clock (clock),
.reset (reset),
.io_flit_ready (io_flits_e_ready),
.io_flit_valid (io_flits_e_valid),
.io_flit_bits_head (io_flits_e_bits_head),
.io_flit_bits_tail (io_flits_e_bits_tail)
); // @[Tilelink.scala:205:17]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module Router :
input clock : Clock
input reset : Reset
output auto : { debug_out : { va_stall : UInt[3], sa_stall : UInt[3]}, egress_nodes_out : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, flip ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<6>, flip vc_free : UInt<6>}, flip dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<6>, flip vc_free : UInt<6>}}
wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<6>, flip vc_free : UInt<6>}
invalidate destNodesIn.vc_free
invalidate destNodesIn.credit_return
invalidate destNodesIn.flit[0].bits.virt_channel_id
invalidate destNodesIn.flit[0].bits.flow.egress_node_id
invalidate destNodesIn.flit[0].bits.flow.egress_node
invalidate destNodesIn.flit[0].bits.flow.ingress_node_id
invalidate destNodesIn.flit[0].bits.flow.ingress_node
invalidate destNodesIn.flit[0].bits.flow.vnet_id
invalidate destNodesIn.flit[0].bits.payload
invalidate destNodesIn.flit[0].bits.tail
invalidate destNodesIn.flit[0].bits.head
invalidate destNodesIn.flit[0].valid
inst monitor of NoCMonitor
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.vc_free, destNodesIn.vc_free
connect monitor.io.in.credit_return, destNodesIn.credit_return
connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id
connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id
connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node
connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id
connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node
connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id
connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload
connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail
connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head
connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid
wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<6>, flip vc_free : UInt<6>}
invalidate sourceNodesOut.vc_free
invalidate sourceNodesOut.credit_return
invalidate sourceNodesOut.flit[0].bits.virt_channel_id
invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id
invalidate sourceNodesOut.flit[0].bits.flow.egress_node
invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id
invalidate sourceNodesOut.flit[0].bits.flow.ingress_node
invalidate sourceNodesOut.flit[0].bits.flow.vnet_id
invalidate sourceNodesOut.flit[0].bits.payload
invalidate sourceNodesOut.flit[0].bits.tail
invalidate sourceNodesOut.flit[0].bits.head
invalidate sourceNodesOut.flit[0].valid
wire ingressNodesIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesIn.flit.bits.egress_id
invalidate ingressNodesIn.flit.bits.payload
invalidate ingressNodesIn.flit.bits.tail
invalidate ingressNodesIn.flit.bits.head
invalidate ingressNodesIn.flit.valid
invalidate ingressNodesIn.flit.ready
wire ingressNodesIn_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesIn_1.flit.bits.egress_id
invalidate ingressNodesIn_1.flit.bits.payload
invalidate ingressNodesIn_1.flit.bits.tail
invalidate ingressNodesIn_1.flit.bits.head
invalidate ingressNodesIn_1.flit.valid
invalidate ingressNodesIn_1.flit.ready
wire egressNodesOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesOut.flit.bits.ingress_id
invalidate egressNodesOut.flit.bits.payload
invalidate egressNodesOut.flit.bits.tail
invalidate egressNodesOut.flit.bits.head
invalidate egressNodesOut.flit.valid
invalidate egressNodesOut.flit.ready
wire debugNodeOut : { va_stall : UInt[3], sa_stall : UInt[3]}
invalidate debugNodeOut.sa_stall[0]
invalidate debugNodeOut.sa_stall[1]
invalidate debugNodeOut.sa_stall[2]
invalidate debugNodeOut.va_stall[0]
invalidate debugNodeOut.va_stall[1]
invalidate debugNodeOut.va_stall[2]
connect destNodesIn, auto.dest_nodes_in
connect auto.source_nodes_out, sourceNodesOut
connect ingressNodesIn, auto.ingress_nodes_in_0
connect ingressNodesIn_1, auto.ingress_nodes_in_1
connect auto.egress_nodes_out, egressNodesOut
connect auto.debug_out, debugNodeOut
inst input_unit_0_from_12 of InputUnit
connect input_unit_0_from_12.clock, clock
connect input_unit_0_from_12.reset, reset
inst ingress_unit_1_from_2 of IngressUnit
connect ingress_unit_1_from_2.clock, clock
connect ingress_unit_1_from_2.reset, reset
inst ingress_unit_2_from_3 of IngressUnit_1
connect ingress_unit_2_from_3.clock, clock
connect ingress_unit_2_from_3.reset, reset
inst output_unit_0_to_1 of OutputUnit
connect output_unit_0_to_1.clock, clock
connect output_unit_0_to_1.reset, reset
inst egress_unit_1_to_1 of EgressUnit
connect egress_unit_1_to_1.clock, clock
connect egress_unit_1_to_1.reset, reset
inst switch of Switch
connect switch.clock, clock
connect switch.reset, reset
inst switch_allocator of SwitchAllocator
connect switch_allocator.clock, clock
connect switch_allocator.reset, reset
inst vc_allocator of RotatingSingleVCAllocator
connect vc_allocator.clock, clock
connect vc_allocator.reset, reset
inst route_computer of RouteComputer
connect route_computer.clock, clock
connect route_computer.reset, reset
node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid)
node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid)
node _fires_count_T_2 = and(vc_allocator.io.req.`2`.ready, vc_allocator.io.req.`2`.valid)
node _fires_count_T_3 = add(_fires_count_T_1, _fires_count_T_2)
node _fires_count_T_4 = bits(_fires_count_T_3, 1, 0)
node _fires_count_T_5 = add(_fires_count_T, _fires_count_T_4)
node _fires_count_T_6 = bits(_fires_count_T_5, 1, 0)
wire fires_count : UInt
connect fires_count, _fires_count_T_6
connect input_unit_0_from_12.io.in, destNodesIn
connect ingress_unit_1_from_2.io.in, ingressNodesIn.flit
connect ingress_unit_2_from_3.io.in, ingressNodesIn_1.flit
connect output_unit_0_to_1.io.out.vc_free, sourceNodesOut.vc_free
connect output_unit_0_to_1.io.out.credit_return, sourceNodesOut.credit_return
connect sourceNodesOut.flit, output_unit_0_to_1.io.out.flit
connect egressNodesOut.flit.bits, egress_unit_1_to_1.io.out.bits
connect egressNodesOut.flit.valid, egress_unit_1_to_1.io.out.valid
connect egress_unit_1_to_1.io.out.ready, egressNodesOut.flit.ready
connect route_computer.io.req.`0`, input_unit_0_from_12.io.router_req
connect route_computer.io.req.`1`, ingress_unit_1_from_2.io.router_req
connect route_computer.io.req.`2`, ingress_unit_2_from_3.io.router_req
connect input_unit_0_from_12.io.router_resp, route_computer.io.resp.`0`
connect ingress_unit_1_from_2.io.router_resp, route_computer.io.resp.`1`
connect ingress_unit_2_from_3.io.router_resp, route_computer.io.resp.`2`
connect vc_allocator.io.req.`0`, input_unit_0_from_12.io.vcalloc_req
connect vc_allocator.io.req.`1`, ingress_unit_1_from_2.io.vcalloc_req
connect vc_allocator.io.req.`2`, ingress_unit_2_from_3.io.vcalloc_req
connect input_unit_0_from_12.io.vcalloc_resp, vc_allocator.io.resp.`0`
connect ingress_unit_1_from_2.io.vcalloc_resp, vc_allocator.io.resp.`1`
connect ingress_unit_2_from_3.io.vcalloc_resp, vc_allocator.io.resp.`2`
connect output_unit_0_to_1.io.allocs, vc_allocator.io.out_allocs.`0`
connect egress_unit_1_to_1.io.allocs, vc_allocator.io.out_allocs.`1`
connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_1.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_1.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_1.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_1.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_1.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_1.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_1.io.channel_status[1].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_1.io.channel_status[1].flow.egress_node
connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_1.io.channel_status[1].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_1.io.channel_status[1].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_1.io.channel_status[1].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_1.io.channel_status[1].occupied
connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_1.io.channel_status[2].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_1.io.channel_status[2].flow.egress_node
connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_1.io.channel_status[2].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_1.io.channel_status[2].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_1.io.channel_status[2].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_1.io.channel_status[2].occupied
connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_1.io.channel_status[3].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_1.io.channel_status[3].flow.egress_node
connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_1.io.channel_status[3].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_1.io.channel_status[3].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_1.io.channel_status[3].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_1.io.channel_status[3].occupied
connect vc_allocator.io.channel_status.`0`[4].flow.egress_node_id, output_unit_0_to_1.io.channel_status[4].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[4].flow.egress_node, output_unit_0_to_1.io.channel_status[4].flow.egress_node
connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node_id, output_unit_0_to_1.io.channel_status[4].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node, output_unit_0_to_1.io.channel_status[4].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[4].flow.vnet_id, output_unit_0_to_1.io.channel_status[4].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[4].occupied, output_unit_0_to_1.io.channel_status[4].occupied
connect vc_allocator.io.channel_status.`0`[5].flow.egress_node_id, output_unit_0_to_1.io.channel_status[5].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[5].flow.egress_node, output_unit_0_to_1.io.channel_status[5].flow.egress_node
connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node_id, output_unit_0_to_1.io.channel_status[5].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node, output_unit_0_to_1.io.channel_status[5].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[5].flow.vnet_id, output_unit_0_to_1.io.channel_status[5].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[5].occupied, output_unit_0_to_1.io.channel_status[5].occupied
connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, egress_unit_1_to_1.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, egress_unit_1_to_1.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, egress_unit_1_to_1.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, egress_unit_1_to_1.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, egress_unit_1_to_1.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[0].occupied, egress_unit_1_to_1.io.channel_status[0].occupied
connect input_unit_0_from_12.io.out_credit_available.`0`[0], output_unit_0_to_1.io.credit_available[0]
connect input_unit_0_from_12.io.out_credit_available.`0`[1], output_unit_0_to_1.io.credit_available[1]
connect input_unit_0_from_12.io.out_credit_available.`0`[2], output_unit_0_to_1.io.credit_available[2]
connect input_unit_0_from_12.io.out_credit_available.`0`[3], output_unit_0_to_1.io.credit_available[3]
connect input_unit_0_from_12.io.out_credit_available.`0`[4], output_unit_0_to_1.io.credit_available[4]
connect input_unit_0_from_12.io.out_credit_available.`0`[5], output_unit_0_to_1.io.credit_available[5]
connect input_unit_0_from_12.io.out_credit_available.`1`[0], egress_unit_1_to_1.io.credit_available[0]
connect ingress_unit_1_from_2.io.out_credit_available.`0`[0], output_unit_0_to_1.io.credit_available[0]
connect ingress_unit_1_from_2.io.out_credit_available.`0`[1], output_unit_0_to_1.io.credit_available[1]
connect ingress_unit_1_from_2.io.out_credit_available.`0`[2], output_unit_0_to_1.io.credit_available[2]
connect ingress_unit_1_from_2.io.out_credit_available.`0`[3], output_unit_0_to_1.io.credit_available[3]
connect ingress_unit_1_from_2.io.out_credit_available.`0`[4], output_unit_0_to_1.io.credit_available[4]
connect ingress_unit_1_from_2.io.out_credit_available.`0`[5], output_unit_0_to_1.io.credit_available[5]
connect ingress_unit_1_from_2.io.out_credit_available.`1`[0], egress_unit_1_to_1.io.credit_available[0]
connect ingress_unit_2_from_3.io.out_credit_available.`0`[0], output_unit_0_to_1.io.credit_available[0]
connect ingress_unit_2_from_3.io.out_credit_available.`0`[1], output_unit_0_to_1.io.credit_available[1]
connect ingress_unit_2_from_3.io.out_credit_available.`0`[2], output_unit_0_to_1.io.credit_available[2]
connect ingress_unit_2_from_3.io.out_credit_available.`0`[3], output_unit_0_to_1.io.credit_available[3]
connect ingress_unit_2_from_3.io.out_credit_available.`0`[4], output_unit_0_to_1.io.credit_available[4]
connect ingress_unit_2_from_3.io.out_credit_available.`0`[5], output_unit_0_to_1.io.credit_available[5]
connect ingress_unit_2_from_3.io.out_credit_available.`1`[0], egress_unit_1_to_1.io.credit_available[0]
connect switch_allocator.io.req.`0`[0], input_unit_0_from_12.io.salloc_req[0]
connect switch_allocator.io.req.`1`[0], ingress_unit_1_from_2.io.salloc_req[0]
connect switch_allocator.io.req.`2`[0], ingress_unit_2_from_3.io.salloc_req[0]
connect output_unit_0_to_1.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail
connect output_unit_0_to_1.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc
connect output_unit_0_to_1.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail
connect output_unit_0_to_1.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc
connect output_unit_0_to_1.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail
connect output_unit_0_to_1.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc
connect output_unit_0_to_1.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail
connect output_unit_0_to_1.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc
connect output_unit_0_to_1.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`0`[4].tail
connect output_unit_0_to_1.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`0`[4].alloc
connect output_unit_0_to_1.io.credit_alloc[5].tail, switch_allocator.io.credit_alloc.`0`[5].tail
connect output_unit_0_to_1.io.credit_alloc[5].alloc, switch_allocator.io.credit_alloc.`0`[5].alloc
connect egress_unit_1_to_1.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail
connect egress_unit_1_to_1.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc
connect switch.io.in.`0`[0], input_unit_0_from_12.io.out[0]
connect switch.io.in.`1`[0], ingress_unit_1_from_2.io.out[0]
connect switch.io.in.`2`[0], ingress_unit_2_from_3.io.out[0]
connect output_unit_0_to_1.io.in, switch.io.out.`0`
connect egress_unit_1_to_1.io.in, switch.io.out.`1`
reg REG : { `1` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock
connect REG, switch_allocator.io.switch_sel
connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0]
connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0]
connect switch.io.sel.`0`[0].`2`[0], REG.`0`[0].`2`[0]
connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0]
connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0]
connect switch.io.sel.`1`[0].`2`[0], REG.`1`[0].`2`[0]
connect input_unit_0_from_12.io.block, UInt<1>(0h0)
connect ingress_unit_1_from_2.io.block, UInt<1>(0h0)
connect ingress_unit_2_from_3.io.block, UInt<1>(0h0)
connect debugNodeOut.va_stall[0], input_unit_0_from_12.io.debug.va_stall
connect debugNodeOut.va_stall[1], ingress_unit_1_from_2.io.debug.va_stall
connect debugNodeOut.va_stall[2], ingress_unit_2_from_3.io.debug.va_stall
connect debugNodeOut.sa_stall[0], input_unit_0_from_12.io.debug.sa_stall
connect debugNodeOut.sa_stall[1], ingress_unit_1_from_2.io.debug.sa_stall
connect debugNodeOut.sa_stall[2], ingress_unit_2_from_3.io.debug.sa_stall
regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0)
node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1))
node _debug_tsc_T_1 = tail(_debug_tsc_T, 1)
connect debug_tsc, _debug_tsc_T_1
regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0)
node _debug_sample_T = add(debug_sample, UInt<1>(0h1))
node _debug_sample_T_1 = tail(_debug_sample_T, 1)
connect debug_sample, _debug_sample_T_1
inst plusarg_reader of plusarg_reader_18
node _T = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_1 = tail(_T, 1)
node _T_2 = eq(debug_sample, _T_1)
when _T_2 :
connect debug_sample, UInt<1>(0h0)
regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid)
node _util_ctr_T_1 = tail(_util_ctr_T, 1)
connect util_ctr, _util_ctr_T_1
node _fired_T = or(fired, destNodesIn.flit[0].valid)
connect fired, _fired_T
node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_5 = tail(_T_4, 1)
node _T_6 = eq(debug_sample, _T_5)
node _T_7 = and(_T_3, _T_6)
node _T_8 = and(_T_7, fired)
when _T_8 :
node _T_9 = asUInt(reset)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
printf(clock, UInt<1>(0h1), "nocsample %d 12 0 %d\n", debug_tsc, util_ctr) : printf
connect fired, destNodesIn.flit[0].valid
node _T_11 = and(ingressNodesIn.flit.ready, ingressNodesIn.flit.valid)
regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_2 = add(util_ctr_1, _T_11)
node _util_ctr_T_3 = tail(_util_ctr_T_2, 1)
connect util_ctr_1, _util_ctr_T_3
node _fired_T_1 = or(fired_1, _T_11)
connect fired_1, _fired_T_1
node _T_12 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_13 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_14 = tail(_T_13, 1)
node _T_15 = eq(debug_sample, _T_14)
node _T_16 = and(_T_12, _T_15)
node _T_17 = and(_T_16, fired_1)
when _T_17 :
node _T_18 = asUInt(reset)
node _T_19 = eq(_T_18, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "nocsample %d i2 0 %d\n", debug_tsc, util_ctr_1) : printf_1
connect fired_1, _T_11
node _T_20 = and(ingressNodesIn_1.flit.ready, ingressNodesIn_1.flit.valid)
regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_4 = add(util_ctr_2, _T_20)
node _util_ctr_T_5 = tail(_util_ctr_T_4, 1)
connect util_ctr_2, _util_ctr_T_5
node _fired_T_2 = or(fired_2, _T_20)
connect fired_2, _fired_T_2
node _T_21 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_22 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_23 = tail(_T_22, 1)
node _T_24 = eq(debug_sample, _T_23)
node _T_25 = and(_T_21, _T_24)
node _T_26 = and(_T_25, fired_2)
when _T_26 :
node _T_27 = asUInt(reset)
node _T_28 = eq(_T_27, UInt<1>(0h0))
when _T_28 :
printf(clock, UInt<1>(0h1), "nocsample %d i3 0 %d\n", debug_tsc, util_ctr_2) : printf_2
connect fired_2, _T_20
node _T_29 = and(egressNodesOut.flit.ready, egressNodesOut.flit.valid)
regreset util_ctr_3 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_3 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_6 = add(util_ctr_3, _T_29)
node _util_ctr_T_7 = tail(_util_ctr_T_6, 1)
connect util_ctr_3, _util_ctr_T_7
node _fired_T_3 = or(fired_3, _T_29)
connect fired_3, _fired_T_3
node _T_30 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_31 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_32 = tail(_T_31, 1)
node _T_33 = eq(debug_sample, _T_32)
node _T_34 = and(_T_30, _T_33)
node _T_35 = and(_T_34, fired_3)
when _T_35 :
node _T_36 = asUInt(reset)
node _T_37 = eq(_T_36, UInt<1>(0h0))
when _T_37 :
printf(clock, UInt<1>(0h1), "nocsample %d 0 e1 %d\n", debug_tsc, util_ctr_3) : printf_3
connect fired_3, _T_29 | module Router( // @[Router.scala:89:25]
input clock, // @[Router.scala:89:25]
input reset, // @[Router.scala:89:25]
output [2:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_egress_nodes_out_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_ingress_nodes_in_1_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_0_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_0_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_ingress_nodes_in_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_ingress_nodes_in_0_flit_bits_egress_id, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25]
input [5:0] auto_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25]
output [5:0] auto_dest_nodes_in_vc_free // @[LazyModuleImp.scala:107:25]
);
wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire _route_computer_io_resp_1_vc_sel_0_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_1; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_2; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_3; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_4; // @[Router.scala:136:32]
wire _route_computer_io_resp_1_vc_sel_0_5; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_0; // @[Router.scala:136:32]
wire _route_computer_io_resp_0_vc_sel_0_1; // @[Router.scala:136:32]
wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_3; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_5; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_3; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_1_vc_sel_0_5; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_5_alloc; // @[Router.scala:133:30]
wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_5_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34]
wire _switch_io_out_1_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire _switch_io_out_0_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [3:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _egress_unit_1_to_1_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_1_to_1_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_1_to_1_io_out_valid; // @[Router.scala:125:13]
wire _output_unit_0_to_1_io_credit_available_0; // @[Router.scala:122:13]
wire _output_unit_0_to_1_io_credit_available_1; // @[Router.scala:122:13]
wire _output_unit_0_to_1_io_credit_available_3; // @[Router.scala:122:13]
wire _output_unit_0_to_1_io_credit_available_5; // @[Router.scala:122:13]
wire _output_unit_0_to_1_io_channel_status_0_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_1_io_channel_status_1_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_1_io_channel_status_3_occupied; // @[Router.scala:122:13]
wire _output_unit_0_to_1_io_channel_status_5_occupied; // @[Router.scala:122:13]
wire _ingress_unit_2_from_3_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_3_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_3_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_3_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_2_from_3_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_2_from_3_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_2_from_3_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_2_from_3_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_2_from_3_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_3_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_3_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_3_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_2_from_3_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_2_from_3_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_2_from_3_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_2_from_3_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_2_from_3_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_2_from_3_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_3_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_2_from_3_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [72:0] _ingress_unit_2_from_3_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_2_from_3_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_2_from_3_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_2_from_3_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_2_from_3_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_2_from_3_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_2_from_3_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_2_from_3_io_in_ready; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_1_from_2_io_router_req_bits_flow_egress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_1_from_2_io_router_req_bits_flow_egress_node_id; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [72:0] _ingress_unit_1_from_2_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_1_from_2_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_1_from_2_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_1_from_2_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [3:0] _ingress_unit_1_from_2_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_1_from_2_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_1_from_2_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_1_from_2_io_in_ready; // @[Router.scala:116:13]
wire [2:0] _input_unit_0_from_12_io_router_req_bits_src_virt_id; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_12_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_12_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_12_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_12_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_12_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13]
wire _input_unit_0_from_12_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_12_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_12_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13]
wire _input_unit_0_from_12_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_0_from_12_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_12_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_12_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13]
wire _input_unit_0_from_12_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13]
wire _input_unit_0_from_12_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13]
wire _input_unit_0_from_12_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13]
wire _input_unit_0_from_12_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13]
wire _input_unit_0_from_12_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13]
wire _input_unit_0_from_12_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_0_from_12_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_12_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_0_from_12_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [72:0] _input_unit_0_from_12_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_12_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_12_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_12_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [3:0] _input_unit_0_from_12_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_12_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_12_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13]
wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_12_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _ingress_unit_1_from_2_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_2_ready & _ingress_unit_2_from_3_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35]
reg REG_1_0_2_0; // @[Router.scala:178:14]
reg REG_1_0_1_0; // @[Router.scala:178:14]
reg REG_1_0_0_0; // @[Router.scala:178:14]
reg REG_0_0_2_0; // @[Router.scala:178:14]
reg REG_0_0_1_0; // @[Router.scala:178:14]
reg REG_0_0_0_0; // @[Router.scala:178:14]
reg [63:0] debug_tsc; // @[Router.scala:195:28]
reg [63:0] debug_sample; // @[Router.scala:197:31]
wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11]
reg [63:0] util_ctr; // @[Router.scala:203:29]
reg fired; // @[Router.scala:204:26]
wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11]
wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_1; // @[Router.scala:203:29]
reg fired_1; // @[Router.scala:204:26]
wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_2; // @[Router.scala:203:29]
reg fired_2; // @[Router.scala:204:26]
wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_3; // @[Router.scala:203:29]
reg fired_3; // @[Router.scala:204:26]
wire _GEN_4 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}] |
Generate the Verilog code corresponding to this FIRRTL code module Router_32 :
input clock : Clock
input reset : Reset
output auto : { debug_out : { va_stall : UInt[3], sa_stall : UInt[3]}, egress_nodes_out_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, egress_nodes_out_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, egress_nodes_out_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}, flip ingress_nodes_in_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, flip ingress_nodes_in_0 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}, source_nodes_out : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}, flip dest_nodes_in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}}
wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}
invalidate destNodesIn.vc_free
invalidate destNodesIn.credit_return
invalidate destNodesIn.flit[0].bits.virt_channel_id
invalidate destNodesIn.flit[0].bits.flow.egress_node_id
invalidate destNodesIn.flit[0].bits.flow.egress_node
invalidate destNodesIn.flit[0].bits.flow.ingress_node_id
invalidate destNodesIn.flit[0].bits.flow.ingress_node
invalidate destNodesIn.flit[0].bits.flow.vnet_id
invalidate destNodesIn.flit[0].bits.payload
invalidate destNodesIn.flit[0].bits.tail
invalidate destNodesIn.flit[0].bits.head
invalidate destNodesIn.flit[0].valid
inst monitor of NoCMonitor_75
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.vc_free, destNodesIn.vc_free
connect monitor.io.in.credit_return, destNodesIn.credit_return
connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id
connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id
connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node
connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id
connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node
connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id
connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload
connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail
connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head
connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid
wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}
invalidate sourceNodesOut.vc_free
invalidate sourceNodesOut.credit_return
invalidate sourceNodesOut.flit[0].bits.virt_channel_id
invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id
invalidate sourceNodesOut.flit[0].bits.flow.egress_node
invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id
invalidate sourceNodesOut.flit[0].bits.flow.ingress_node
invalidate sourceNodesOut.flit[0].bits.flow.vnet_id
invalidate sourceNodesOut.flit[0].bits.payload
invalidate sourceNodesOut.flit[0].bits.tail
invalidate sourceNodesOut.flit[0].bits.head
invalidate sourceNodesOut.flit[0].valid
wire ingressNodesIn : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesIn.flit.bits.egress_id
invalidate ingressNodesIn.flit.bits.payload
invalidate ingressNodesIn.flit.bits.tail
invalidate ingressNodesIn.flit.bits.head
invalidate ingressNodesIn.flit.valid
invalidate ingressNodesIn.flit.ready
wire ingressNodesIn_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}}
invalidate ingressNodesIn_1.flit.bits.egress_id
invalidate ingressNodesIn_1.flit.bits.payload
invalidate ingressNodesIn_1.flit.bits.tail
invalidate ingressNodesIn_1.flit.bits.head
invalidate ingressNodesIn_1.flit.valid
invalidate ingressNodesIn_1.flit.ready
wire egressNodesOut : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesOut.flit.bits.ingress_id
invalidate egressNodesOut.flit.bits.payload
invalidate egressNodesOut.flit.bits.tail
invalidate egressNodesOut.flit.bits.head
invalidate egressNodesOut.flit.valid
invalidate egressNodesOut.flit.ready
wire egressNodesOut_1 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesOut_1.flit.bits.ingress_id
invalidate egressNodesOut_1.flit.bits.payload
invalidate egressNodesOut_1.flit.bits.tail
invalidate egressNodesOut_1.flit.bits.head
invalidate egressNodesOut_1.flit.valid
invalidate egressNodesOut_1.flit.ready
wire egressNodesOut_2 : { flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}
invalidate egressNodesOut_2.flit.bits.ingress_id
invalidate egressNodesOut_2.flit.bits.payload
invalidate egressNodesOut_2.flit.bits.tail
invalidate egressNodesOut_2.flit.bits.head
invalidate egressNodesOut_2.flit.valid
invalidate egressNodesOut_2.flit.ready
wire debugNodeOut : { va_stall : UInt[3], sa_stall : UInt[3]}
invalidate debugNodeOut.sa_stall[0]
invalidate debugNodeOut.sa_stall[1]
invalidate debugNodeOut.sa_stall[2]
invalidate debugNodeOut.va_stall[0]
invalidate debugNodeOut.va_stall[1]
invalidate debugNodeOut.va_stall[2]
connect destNodesIn, auto.dest_nodes_in
connect auto.source_nodes_out, sourceNodesOut
connect ingressNodesIn, auto.ingress_nodes_in_0
connect ingressNodesIn_1, auto.ingress_nodes_in_1
connect auto.egress_nodes_out_0, egressNodesOut
connect auto.egress_nodes_out_1, egressNodesOut_1
connect auto.egress_nodes_out_2, egressNodesOut_2
connect auto.debug_out, debugNodeOut
inst input_unit_0_from_12 of InputUnit_75
connect input_unit_0_from_12.clock, clock
connect input_unit_0_from_12.reset, reset
inst ingress_unit_1_from_7 of IngressUnit_44
connect ingress_unit_1_from_7.clock, clock
connect ingress_unit_1_from_7.reset, reset
inst ingress_unit_2_from_8 of IngressUnit_45
connect ingress_unit_2_from_8.clock, clock
connect ingress_unit_2_from_8.reset, reset
inst output_unit_0_to_12 of OutputUnit_75
connect output_unit_0_to_12.clock, clock
connect output_unit_0_to_12.reset, reset
inst egress_unit_1_to_8 of EgressUnit_41
connect egress_unit_1_to_8.clock, clock
connect egress_unit_1_to_8.reset, reset
inst egress_unit_2_to_9 of EgressUnit_42
connect egress_unit_2_to_9.clock, clock
connect egress_unit_2_to_9.reset, reset
inst egress_unit_3_to_10 of EgressUnit_43
connect egress_unit_3_to_10.clock, clock
connect egress_unit_3_to_10.reset, reset
inst switch of Switch_32
connect switch.clock, clock
connect switch.reset, reset
inst switch_allocator of SwitchAllocator_32
connect switch_allocator.clock, clock
connect switch_allocator.reset, reset
inst vc_allocator of RotatingSingleVCAllocator_32
connect vc_allocator.clock, clock
connect vc_allocator.reset, reset
inst route_computer of RouteComputer_32
connect route_computer.clock, clock
connect route_computer.reset, reset
node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid)
node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid)
node _fires_count_T_2 = and(vc_allocator.io.req.`2`.ready, vc_allocator.io.req.`2`.valid)
node _fires_count_T_3 = add(_fires_count_T_1, _fires_count_T_2)
node _fires_count_T_4 = bits(_fires_count_T_3, 1, 0)
node _fires_count_T_5 = add(_fires_count_T, _fires_count_T_4)
node _fires_count_T_6 = bits(_fires_count_T_5, 1, 0)
wire fires_count : UInt
connect fires_count, _fires_count_T_6
connect input_unit_0_from_12.io.in, destNodesIn
connect ingress_unit_1_from_7.io.in, ingressNodesIn.flit
connect ingress_unit_2_from_8.io.in, ingressNodesIn_1.flit
connect output_unit_0_to_12.io.out.vc_free, sourceNodesOut.vc_free
connect output_unit_0_to_12.io.out.credit_return, sourceNodesOut.credit_return
connect sourceNodesOut.flit, output_unit_0_to_12.io.out.flit
connect egressNodesOut.flit.bits, egress_unit_1_to_8.io.out.bits
connect egressNodesOut.flit.valid, egress_unit_1_to_8.io.out.valid
connect egress_unit_1_to_8.io.out.ready, egressNodesOut.flit.ready
connect egressNodesOut_1.flit.bits, egress_unit_2_to_9.io.out.bits
connect egressNodesOut_1.flit.valid, egress_unit_2_to_9.io.out.valid
connect egress_unit_2_to_9.io.out.ready, egressNodesOut_1.flit.ready
connect egressNodesOut_2.flit.bits, egress_unit_3_to_10.io.out.bits
connect egressNodesOut_2.flit.valid, egress_unit_3_to_10.io.out.valid
connect egress_unit_3_to_10.io.out.ready, egressNodesOut_2.flit.ready
connect route_computer.io.req.`0`, input_unit_0_from_12.io.router_req
connect route_computer.io.req.`1`, ingress_unit_1_from_7.io.router_req
connect route_computer.io.req.`2`, ingress_unit_2_from_8.io.router_req
connect input_unit_0_from_12.io.router_resp, route_computer.io.resp.`0`
connect ingress_unit_1_from_7.io.router_resp, route_computer.io.resp.`1`
connect ingress_unit_2_from_8.io.router_resp, route_computer.io.resp.`2`
connect vc_allocator.io.req.`0`, input_unit_0_from_12.io.vcalloc_req
connect vc_allocator.io.req.`1`, ingress_unit_1_from_7.io.vcalloc_req
connect vc_allocator.io.req.`2`, ingress_unit_2_from_8.io.vcalloc_req
connect input_unit_0_from_12.io.vcalloc_resp, vc_allocator.io.resp.`0`
connect ingress_unit_1_from_7.io.vcalloc_resp, vc_allocator.io.resp.`1`
connect ingress_unit_2_from_8.io.vcalloc_resp, vc_allocator.io.resp.`2`
connect output_unit_0_to_12.io.allocs, vc_allocator.io.out_allocs.`0`
connect egress_unit_1_to_8.io.allocs, vc_allocator.io.out_allocs.`1`
connect egress_unit_2_to_9.io.allocs, vc_allocator.io.out_allocs.`2`
connect egress_unit_3_to_10.io.allocs, vc_allocator.io.out_allocs.`3`
connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_12.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_12.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_12.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_12.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_12.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_12.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_12.io.channel_status[1].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_12.io.channel_status[1].flow.egress_node
connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_12.io.channel_status[1].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_12.io.channel_status[1].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_12.io.channel_status[1].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_12.io.channel_status[1].occupied
connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_12.io.channel_status[2].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_12.io.channel_status[2].flow.egress_node
connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_12.io.channel_status[2].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_12.io.channel_status[2].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_12.io.channel_status[2].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_12.io.channel_status[2].occupied
connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_12.io.channel_status[3].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_12.io.channel_status[3].flow.egress_node
connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_12.io.channel_status[3].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_12.io.channel_status[3].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_12.io.channel_status[3].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_12.io.channel_status[3].occupied
connect vc_allocator.io.channel_status.`0`[4].flow.egress_node_id, output_unit_0_to_12.io.channel_status[4].flow.egress_node_id
connect vc_allocator.io.channel_status.`0`[4].flow.egress_node, output_unit_0_to_12.io.channel_status[4].flow.egress_node
connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node_id, output_unit_0_to_12.io.channel_status[4].flow.ingress_node_id
connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node, output_unit_0_to_12.io.channel_status[4].flow.ingress_node
connect vc_allocator.io.channel_status.`0`[4].flow.vnet_id, output_unit_0_to_12.io.channel_status[4].flow.vnet_id
connect vc_allocator.io.channel_status.`0`[4].occupied, output_unit_0_to_12.io.channel_status[4].occupied
connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, egress_unit_1_to_8.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, egress_unit_1_to_8.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, egress_unit_1_to_8.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, egress_unit_1_to_8.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, egress_unit_1_to_8.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`1`[0].occupied, egress_unit_1_to_8.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`2`[0].flow.egress_node_id, egress_unit_2_to_9.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`2`[0].flow.egress_node, egress_unit_2_to_9.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node_id, egress_unit_2_to_9.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node, egress_unit_2_to_9.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`2`[0].flow.vnet_id, egress_unit_2_to_9.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`2`[0].occupied, egress_unit_2_to_9.io.channel_status[0].occupied
connect vc_allocator.io.channel_status.`3`[0].flow.egress_node_id, egress_unit_3_to_10.io.channel_status[0].flow.egress_node_id
connect vc_allocator.io.channel_status.`3`[0].flow.egress_node, egress_unit_3_to_10.io.channel_status[0].flow.egress_node
connect vc_allocator.io.channel_status.`3`[0].flow.ingress_node_id, egress_unit_3_to_10.io.channel_status[0].flow.ingress_node_id
connect vc_allocator.io.channel_status.`3`[0].flow.ingress_node, egress_unit_3_to_10.io.channel_status[0].flow.ingress_node
connect vc_allocator.io.channel_status.`3`[0].flow.vnet_id, egress_unit_3_to_10.io.channel_status[0].flow.vnet_id
connect vc_allocator.io.channel_status.`3`[0].occupied, egress_unit_3_to_10.io.channel_status[0].occupied
connect input_unit_0_from_12.io.out_credit_available.`0`[0], output_unit_0_to_12.io.credit_available[0]
connect input_unit_0_from_12.io.out_credit_available.`0`[1], output_unit_0_to_12.io.credit_available[1]
connect input_unit_0_from_12.io.out_credit_available.`0`[2], output_unit_0_to_12.io.credit_available[2]
connect input_unit_0_from_12.io.out_credit_available.`0`[3], output_unit_0_to_12.io.credit_available[3]
connect input_unit_0_from_12.io.out_credit_available.`0`[4], output_unit_0_to_12.io.credit_available[4]
connect input_unit_0_from_12.io.out_credit_available.`1`[0], egress_unit_1_to_8.io.credit_available[0]
connect input_unit_0_from_12.io.out_credit_available.`2`[0], egress_unit_2_to_9.io.credit_available[0]
connect input_unit_0_from_12.io.out_credit_available.`3`[0], egress_unit_3_to_10.io.credit_available[0]
connect ingress_unit_1_from_7.io.out_credit_available.`0`[0], output_unit_0_to_12.io.credit_available[0]
connect ingress_unit_1_from_7.io.out_credit_available.`0`[1], output_unit_0_to_12.io.credit_available[1]
connect ingress_unit_1_from_7.io.out_credit_available.`0`[2], output_unit_0_to_12.io.credit_available[2]
connect ingress_unit_1_from_7.io.out_credit_available.`0`[3], output_unit_0_to_12.io.credit_available[3]
connect ingress_unit_1_from_7.io.out_credit_available.`0`[4], output_unit_0_to_12.io.credit_available[4]
connect ingress_unit_1_from_7.io.out_credit_available.`1`[0], egress_unit_1_to_8.io.credit_available[0]
connect ingress_unit_1_from_7.io.out_credit_available.`2`[0], egress_unit_2_to_9.io.credit_available[0]
connect ingress_unit_1_from_7.io.out_credit_available.`3`[0], egress_unit_3_to_10.io.credit_available[0]
connect ingress_unit_2_from_8.io.out_credit_available.`0`[0], output_unit_0_to_12.io.credit_available[0]
connect ingress_unit_2_from_8.io.out_credit_available.`0`[1], output_unit_0_to_12.io.credit_available[1]
connect ingress_unit_2_from_8.io.out_credit_available.`0`[2], output_unit_0_to_12.io.credit_available[2]
connect ingress_unit_2_from_8.io.out_credit_available.`0`[3], output_unit_0_to_12.io.credit_available[3]
connect ingress_unit_2_from_8.io.out_credit_available.`0`[4], output_unit_0_to_12.io.credit_available[4]
connect ingress_unit_2_from_8.io.out_credit_available.`1`[0], egress_unit_1_to_8.io.credit_available[0]
connect ingress_unit_2_from_8.io.out_credit_available.`2`[0], egress_unit_2_to_9.io.credit_available[0]
connect ingress_unit_2_from_8.io.out_credit_available.`3`[0], egress_unit_3_to_10.io.credit_available[0]
connect switch_allocator.io.req.`0`[0], input_unit_0_from_12.io.salloc_req[0]
connect switch_allocator.io.req.`1`[0], ingress_unit_1_from_7.io.salloc_req[0]
connect switch_allocator.io.req.`2`[0], ingress_unit_2_from_8.io.salloc_req[0]
connect output_unit_0_to_12.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail
connect output_unit_0_to_12.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc
connect output_unit_0_to_12.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail
connect output_unit_0_to_12.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc
connect output_unit_0_to_12.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail
connect output_unit_0_to_12.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc
connect output_unit_0_to_12.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail
connect output_unit_0_to_12.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc
connect output_unit_0_to_12.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`0`[4].tail
connect output_unit_0_to_12.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`0`[4].alloc
connect egress_unit_1_to_8.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail
connect egress_unit_1_to_8.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc
connect egress_unit_2_to_9.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`2`[0].tail
connect egress_unit_2_to_9.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`2`[0].alloc
connect egress_unit_3_to_10.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`3`[0].tail
connect egress_unit_3_to_10.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`3`[0].alloc
connect switch.io.in.`0`[0], input_unit_0_from_12.io.out[0]
connect switch.io.in.`1`[0], ingress_unit_1_from_7.io.out[0]
connect switch.io.in.`2`[0], ingress_unit_2_from_8.io.out[0]
connect output_unit_0_to_12.io.in, switch.io.out.`0`
connect egress_unit_1_to_8.io.in, switch.io.out.`1`
connect egress_unit_2_to_9.io.in, switch.io.out.`2`
connect egress_unit_3_to_10.io.in, switch.io.out.`3`
reg REG : { `3` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `2` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock
connect REG, switch_allocator.io.switch_sel
connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0]
connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0]
connect switch.io.sel.`0`[0].`2`[0], REG.`0`[0].`2`[0]
connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0]
connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0]
connect switch.io.sel.`1`[0].`2`[0], REG.`1`[0].`2`[0]
connect switch.io.sel.`2`[0].`0`[0], REG.`2`[0].`0`[0]
connect switch.io.sel.`2`[0].`1`[0], REG.`2`[0].`1`[0]
connect switch.io.sel.`2`[0].`2`[0], REG.`2`[0].`2`[0]
connect switch.io.sel.`3`[0].`0`[0], REG.`3`[0].`0`[0]
connect switch.io.sel.`3`[0].`1`[0], REG.`3`[0].`1`[0]
connect switch.io.sel.`3`[0].`2`[0], REG.`3`[0].`2`[0]
connect input_unit_0_from_12.io.block, UInt<1>(0h0)
connect ingress_unit_1_from_7.io.block, UInt<1>(0h0)
connect ingress_unit_2_from_8.io.block, UInt<1>(0h0)
connect debugNodeOut.va_stall[0], input_unit_0_from_12.io.debug.va_stall
connect debugNodeOut.va_stall[1], ingress_unit_1_from_7.io.debug.va_stall
connect debugNodeOut.va_stall[2], ingress_unit_2_from_8.io.debug.va_stall
connect debugNodeOut.sa_stall[0], input_unit_0_from_12.io.debug.sa_stall
connect debugNodeOut.sa_stall[1], ingress_unit_1_from_7.io.debug.sa_stall
connect debugNodeOut.sa_stall[2], ingress_unit_2_from_8.io.debug.sa_stall
regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0)
node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1))
node _debug_tsc_T_1 = tail(_debug_tsc_T, 1)
connect debug_tsc, _debug_tsc_T_1
regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0)
node _debug_sample_T = add(debug_sample, UInt<1>(0h1))
node _debug_sample_T_1 = tail(_debug_sample_T, 1)
connect debug_sample, _debug_sample_T_1
inst plusarg_reader of plusarg_reader_80
node _T = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_1 = tail(_T, 1)
node _T_2 = eq(debug_sample, _T_1)
when _T_2 :
connect debug_sample, UInt<1>(0h0)
regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid)
node _util_ctr_T_1 = tail(_util_ctr_T, 1)
connect util_ctr, _util_ctr_T_1
node _fired_T = or(fired, destNodesIn.flit[0].valid)
connect fired, _fired_T
node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_5 = tail(_T_4, 1)
node _T_6 = eq(debug_sample, _T_5)
node _T_7 = and(_T_3, _T_6)
node _T_8 = and(_T_7, fired)
when _T_8 :
node _T_9 = asUInt(reset)
node _T_10 = eq(_T_9, UInt<1>(0h0))
when _T_10 :
printf(clock, UInt<1>(0h1), "nocsample %d 12 3 %d\n", debug_tsc, util_ctr) : printf
connect fired, destNodesIn.flit[0].valid
node _T_11 = and(ingressNodesIn.flit.ready, ingressNodesIn.flit.valid)
regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_2 = add(util_ctr_1, _T_11)
node _util_ctr_T_3 = tail(_util_ctr_T_2, 1)
connect util_ctr_1, _util_ctr_T_3
node _fired_T_1 = or(fired_1, _T_11)
connect fired_1, _fired_T_1
node _T_12 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_13 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_14 = tail(_T_13, 1)
node _T_15 = eq(debug_sample, _T_14)
node _T_16 = and(_T_12, _T_15)
node _T_17 = and(_T_16, fired_1)
when _T_17 :
node _T_18 = asUInt(reset)
node _T_19 = eq(_T_18, UInt<1>(0h0))
when _T_19 :
printf(clock, UInt<1>(0h1), "nocsample %d i7 3 %d\n", debug_tsc, util_ctr_1) : printf_1
connect fired_1, _T_11
node _T_20 = and(ingressNodesIn_1.flit.ready, ingressNodesIn_1.flit.valid)
regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_4 = add(util_ctr_2, _T_20)
node _util_ctr_T_5 = tail(_util_ctr_T_4, 1)
connect util_ctr_2, _util_ctr_T_5
node _fired_T_2 = or(fired_2, _T_20)
connect fired_2, _fired_T_2
node _T_21 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_22 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_23 = tail(_T_22, 1)
node _T_24 = eq(debug_sample, _T_23)
node _T_25 = and(_T_21, _T_24)
node _T_26 = and(_T_25, fired_2)
when _T_26 :
node _T_27 = asUInt(reset)
node _T_28 = eq(_T_27, UInt<1>(0h0))
when _T_28 :
printf(clock, UInt<1>(0h1), "nocsample %d i8 3 %d\n", debug_tsc, util_ctr_2) : printf_2
connect fired_2, _T_20
node _T_29 = and(egressNodesOut.flit.ready, egressNodesOut.flit.valid)
regreset util_ctr_3 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_3 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_6 = add(util_ctr_3, _T_29)
node _util_ctr_T_7 = tail(_util_ctr_T_6, 1)
connect util_ctr_3, _util_ctr_T_7
node _fired_T_3 = or(fired_3, _T_29)
connect fired_3, _fired_T_3
node _T_30 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_31 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_32 = tail(_T_31, 1)
node _T_33 = eq(debug_sample, _T_32)
node _T_34 = and(_T_30, _T_33)
node _T_35 = and(_T_34, fired_3)
when _T_35 :
node _T_36 = asUInt(reset)
node _T_37 = eq(_T_36, UInt<1>(0h0))
when _T_37 :
printf(clock, UInt<1>(0h1), "nocsample %d 3 e8 %d\n", debug_tsc, util_ctr_3) : printf_3
connect fired_3, _T_29
node _T_38 = and(egressNodesOut_1.flit.ready, egressNodesOut_1.flit.valid)
regreset util_ctr_4 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_4 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_8 = add(util_ctr_4, _T_38)
node _util_ctr_T_9 = tail(_util_ctr_T_8, 1)
connect util_ctr_4, _util_ctr_T_9
node _fired_T_4 = or(fired_4, _T_38)
connect fired_4, _fired_T_4
node _T_39 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_40 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_41 = tail(_T_40, 1)
node _T_42 = eq(debug_sample, _T_41)
node _T_43 = and(_T_39, _T_42)
node _T_44 = and(_T_43, fired_4)
when _T_44 :
node _T_45 = asUInt(reset)
node _T_46 = eq(_T_45, UInt<1>(0h0))
when _T_46 :
printf(clock, UInt<1>(0h1), "nocsample %d 3 e9 %d\n", debug_tsc, util_ctr_4) : printf_4
connect fired_4, _T_38
node _T_47 = and(egressNodesOut_2.flit.ready, egressNodesOut_2.flit.valid)
regreset util_ctr_5 : UInt<64>, clock, reset, UInt<64>(0h0)
regreset fired_5 : UInt<1>, clock, reset, UInt<1>(0h0)
node _util_ctr_T_10 = add(util_ctr_5, _T_47)
node _util_ctr_T_11 = tail(_util_ctr_T_10, 1)
connect util_ctr_5, _util_ctr_T_11
node _fired_T_5 = or(fired_5, _T_47)
connect fired_5, _fired_T_5
node _T_48 = neq(plusarg_reader.out, UInt<1>(0h0))
node _T_49 = sub(plusarg_reader.out, UInt<1>(0h1))
node _T_50 = tail(_T_49, 1)
node _T_51 = eq(debug_sample, _T_50)
node _T_52 = and(_T_48, _T_51)
node _T_53 = and(_T_52, fired_5)
when _T_53 :
node _T_54 = asUInt(reset)
node _T_55 = eq(_T_54, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "nocsample %d 3 e10 %d\n", debug_tsc, util_ctr_5) : printf_5
connect fired_5, _T_47 | module Router_32( // @[Router.scala:89:25]
input clock, // @[Router.scala:89:25]
input reset, // @[Router.scala:89:25]
output [2:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_2_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_2_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_2_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_2_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_1_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input auto_egress_nodes_out_0_flit_ready, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_valid, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_egress_nodes_out_0_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_egress_nodes_out_0_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_ingress_nodes_in_1_flit_ready, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_1_flit_valid, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_1_flit_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_ingress_nodes_in_1_flit_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_ingress_nodes_in_1_flit_bits_payload, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_valid, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
output auto_source_nodes_out_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
output [72:0] auto_source_nodes_out_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_source_nodes_out_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_source_nodes_out_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_source_nodes_out_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_source_nodes_out_credit_return, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_source_nodes_out_vc_free, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_valid, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_bits_head, // @[LazyModuleImp.scala:107:25]
input auto_dest_nodes_in_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25]
input [72:0] auto_dest_nodes_in_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_dest_nodes_in_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_dest_nodes_in_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_dest_nodes_in_credit_return, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_dest_nodes_in_vc_free // @[LazyModuleImp.scala:107:25]
);
wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_1; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_2; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_3; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_2_vc_sel_0_4; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_3_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_2_0; // @[Router.scala:133:30]
wire _vc_allocator_io_resp_0_vc_sel_1_0; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_3_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_2_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_1_0_alloc; // @[Router.scala:133:30]
wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30]
wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_3_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_3_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_2_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_0_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_1_0_tail; // @[Router.scala:132:34]
wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_3_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34]
wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34]
wire _switch_io_out_3_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_3_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_3_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_3_0_bits_payload; // @[Router.scala:131:24]
wire _switch_io_out_2_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24]
wire _switch_io_out_1_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24]
wire _switch_io_out_0_0_valid; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24]
wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24]
wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24]
wire [4:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24]
wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24]
wire [2:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24]
wire _egress_unit_3_to_10_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_3_to_10_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_3_to_10_io_out_valid; // @[Router.scala:125:13]
wire _egress_unit_2_to_9_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_2_to_9_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_2_to_9_io_out_valid; // @[Router.scala:125:13]
wire _egress_unit_1_to_8_io_credit_available_0; // @[Router.scala:125:13]
wire _egress_unit_1_to_8_io_channel_status_0_occupied; // @[Router.scala:125:13]
wire _egress_unit_1_to_8_io_out_valid; // @[Router.scala:125:13]
wire _output_unit_0_to_12_io_credit_available_1; // @[Router.scala:122:13]
wire _output_unit_0_to_12_io_channel_status_1_occupied; // @[Router.scala:122:13]
wire _ingress_unit_2_from_8_io_vcalloc_req_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_8_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_8_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_8_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_8_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_8_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_2_from_8_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_2_from_8_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_2_from_8_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_2_from_8_io_salloc_req_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_8_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_8_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_8_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_8_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:116:13]
wire _ingress_unit_2_from_8_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:116:13]
wire _ingress_unit_2_from_8_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:116:13]
wire _ingress_unit_2_from_8_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:116:13]
wire _ingress_unit_2_from_8_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:116:13]
wire _ingress_unit_2_from_8_io_salloc_req_0_bits_tail; // @[Router.scala:116:13]
wire _ingress_unit_2_from_8_io_out_0_valid; // @[Router.scala:116:13]
wire _ingress_unit_2_from_8_io_out_0_bits_flit_head; // @[Router.scala:116:13]
wire _ingress_unit_2_from_8_io_out_0_bits_flit_tail; // @[Router.scala:116:13]
wire [72:0] _ingress_unit_2_from_8_io_out_0_bits_flit_payload; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_2_from_8_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:116:13]
wire [4:0] _ingress_unit_2_from_8_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_2_from_8_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:116:13]
wire [4:0] _ingress_unit_2_from_8_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:116:13]
wire [1:0] _ingress_unit_2_from_8_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:116:13]
wire [2:0] _ingress_unit_2_from_8_io_out_0_bits_out_virt_channel; // @[Router.scala:116:13]
wire _ingress_unit_2_from_8_io_in_ready; // @[Router.scala:116:13]
wire _input_unit_0_from_12_io_vcalloc_req_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_12_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_0_from_12_io_vcalloc_req_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_0_from_12_io_vcalloc_req_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_12_io_salloc_req_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_12_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13]
wire _input_unit_0_from_12_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13]
wire _input_unit_0_from_12_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13]
wire _input_unit_0_from_12_io_salloc_req_0_bits_tail; // @[Router.scala:112:13]
wire _input_unit_0_from_12_io_out_0_valid; // @[Router.scala:112:13]
wire _input_unit_0_from_12_io_out_0_bits_flit_head; // @[Router.scala:112:13]
wire _input_unit_0_from_12_io_out_0_bits_flit_tail; // @[Router.scala:112:13]
wire [72:0] _input_unit_0_from_12_io_out_0_bits_flit_payload; // @[Router.scala:112:13]
wire [2:0] _input_unit_0_from_12_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_0_from_12_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_12_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13]
wire [4:0] _input_unit_0_from_12_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13]
wire [1:0] _input_unit_0_from_12_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13]
wire [1:0] fires_count = {1'h0, _vc_allocator_io_req_2_ready & _ingress_unit_2_from_8_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_12_io_vcalloc_req_valid}; // @[Decoupled.scala:51:35]
reg REG_3_0_2_0; // @[Router.scala:178:14]
reg REG_3_0_0_0; // @[Router.scala:178:14]
reg REG_2_0_2_0; // @[Router.scala:178:14]
reg REG_2_0_0_0; // @[Router.scala:178:14]
reg REG_1_0_2_0; // @[Router.scala:178:14]
reg REG_1_0_0_0; // @[Router.scala:178:14]
reg REG_0_0_2_0; // @[Router.scala:178:14]
reg [63:0] debug_tsc; // @[Router.scala:195:28]
reg [63:0] debug_sample; // @[Router.scala:197:31]
wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11]
reg [63:0] util_ctr; // @[Router.scala:203:29]
reg fired; // @[Router.scala:204:26]
wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11]
wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_2; // @[Router.scala:203:29]
reg fired_2; // @[Router.scala:204:26]
wire _GEN_2 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_3; // @[Router.scala:203:29]
reg fired_3; // @[Router.scala:204:26]
wire _GEN_3 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_4; // @[Router.scala:203:29]
reg fired_4; // @[Router.scala:204:26]
wire _GEN_4 = _GEN_0 & fired_4; // @[Router.scala:204:26, :207:{33,71}]
reg [63:0] util_ctr_5; // @[Router.scala:203:29]
reg fired_5; // @[Router.scala:204:26]
wire _GEN_5 = _GEN_0 & fired_5; // @[Router.scala:204:26, :207:{33,71}] |
Generate the Verilog code corresponding to this FIRRTL code module PE_261 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_5
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<8>, clock
reg c2 : SInt<8>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h0), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node _c1_T = bits(io.in_d, 7, 0)
node _c1_T_1 = asSInt(_c1_T)
connect c1, _c1_T_1
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node _c2_T = bits(io.in_d, 7, 0)
node _c2_T_1 = asSInt(_c2_T)
connect c2, _c2_T_1
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h0), _T_4)
node _T_6 = or(UInt<1>(0h1), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_261( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid // @[PE.scala:35:14]
);
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7]
wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60]
wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33]
wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [7:0] c1; // @[PE.scala:70:15]
wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [7:0] c2; // @[PE.scala:71:15]
wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25]
wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7]
wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30]
wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28]
wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}]
wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38]
assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16]
wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8]
c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15]
if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8]
c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15]
if (io_in_valid_0) // @[PE.scala:31:7]
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
always @(posedge)
MacUnit_5 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_b_0), // @[PE.scala:31:7]
.io_out_d (io_out_b_0)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_342 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_342( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module INToRecFN_i64_e11_s53_2 :
output io : { flip signedIn : UInt<1>, flip in : UInt<64>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>}
node _intAsRawFloat_sign_T = bits(io.in, 63, 63)
node intAsRawFloat_sign = and(io.signedIn, _intAsRawFloat_sign_T)
node _intAsRawFloat_absIn_T = sub(UInt<1>(0h0), io.in)
node _intAsRawFloat_absIn_T_1 = tail(_intAsRawFloat_absIn_T, 1)
node intAsRawFloat_absIn = mux(intAsRawFloat_sign, _intAsRawFloat_absIn_T_1, io.in)
node _intAsRawFloat_extAbsIn_T = cat(UInt<64>(0h0), intAsRawFloat_absIn)
node intAsRawFloat_extAbsIn = bits(_intAsRawFloat_extAbsIn_T, 63, 0)
node _intAsRawFloat_adjustedNormDist_T = bits(intAsRawFloat_extAbsIn, 0, 0)
node _intAsRawFloat_adjustedNormDist_T_1 = bits(intAsRawFloat_extAbsIn, 1, 1)
node _intAsRawFloat_adjustedNormDist_T_2 = bits(intAsRawFloat_extAbsIn, 2, 2)
node _intAsRawFloat_adjustedNormDist_T_3 = bits(intAsRawFloat_extAbsIn, 3, 3)
node _intAsRawFloat_adjustedNormDist_T_4 = bits(intAsRawFloat_extAbsIn, 4, 4)
node _intAsRawFloat_adjustedNormDist_T_5 = bits(intAsRawFloat_extAbsIn, 5, 5)
node _intAsRawFloat_adjustedNormDist_T_6 = bits(intAsRawFloat_extAbsIn, 6, 6)
node _intAsRawFloat_adjustedNormDist_T_7 = bits(intAsRawFloat_extAbsIn, 7, 7)
node _intAsRawFloat_adjustedNormDist_T_8 = bits(intAsRawFloat_extAbsIn, 8, 8)
node _intAsRawFloat_adjustedNormDist_T_9 = bits(intAsRawFloat_extAbsIn, 9, 9)
node _intAsRawFloat_adjustedNormDist_T_10 = bits(intAsRawFloat_extAbsIn, 10, 10)
node _intAsRawFloat_adjustedNormDist_T_11 = bits(intAsRawFloat_extAbsIn, 11, 11)
node _intAsRawFloat_adjustedNormDist_T_12 = bits(intAsRawFloat_extAbsIn, 12, 12)
node _intAsRawFloat_adjustedNormDist_T_13 = bits(intAsRawFloat_extAbsIn, 13, 13)
node _intAsRawFloat_adjustedNormDist_T_14 = bits(intAsRawFloat_extAbsIn, 14, 14)
node _intAsRawFloat_adjustedNormDist_T_15 = bits(intAsRawFloat_extAbsIn, 15, 15)
node _intAsRawFloat_adjustedNormDist_T_16 = bits(intAsRawFloat_extAbsIn, 16, 16)
node _intAsRawFloat_adjustedNormDist_T_17 = bits(intAsRawFloat_extAbsIn, 17, 17)
node _intAsRawFloat_adjustedNormDist_T_18 = bits(intAsRawFloat_extAbsIn, 18, 18)
node _intAsRawFloat_adjustedNormDist_T_19 = bits(intAsRawFloat_extAbsIn, 19, 19)
node _intAsRawFloat_adjustedNormDist_T_20 = bits(intAsRawFloat_extAbsIn, 20, 20)
node _intAsRawFloat_adjustedNormDist_T_21 = bits(intAsRawFloat_extAbsIn, 21, 21)
node _intAsRawFloat_adjustedNormDist_T_22 = bits(intAsRawFloat_extAbsIn, 22, 22)
node _intAsRawFloat_adjustedNormDist_T_23 = bits(intAsRawFloat_extAbsIn, 23, 23)
node _intAsRawFloat_adjustedNormDist_T_24 = bits(intAsRawFloat_extAbsIn, 24, 24)
node _intAsRawFloat_adjustedNormDist_T_25 = bits(intAsRawFloat_extAbsIn, 25, 25)
node _intAsRawFloat_adjustedNormDist_T_26 = bits(intAsRawFloat_extAbsIn, 26, 26)
node _intAsRawFloat_adjustedNormDist_T_27 = bits(intAsRawFloat_extAbsIn, 27, 27)
node _intAsRawFloat_adjustedNormDist_T_28 = bits(intAsRawFloat_extAbsIn, 28, 28)
node _intAsRawFloat_adjustedNormDist_T_29 = bits(intAsRawFloat_extAbsIn, 29, 29)
node _intAsRawFloat_adjustedNormDist_T_30 = bits(intAsRawFloat_extAbsIn, 30, 30)
node _intAsRawFloat_adjustedNormDist_T_31 = bits(intAsRawFloat_extAbsIn, 31, 31)
node _intAsRawFloat_adjustedNormDist_T_32 = bits(intAsRawFloat_extAbsIn, 32, 32)
node _intAsRawFloat_adjustedNormDist_T_33 = bits(intAsRawFloat_extAbsIn, 33, 33)
node _intAsRawFloat_adjustedNormDist_T_34 = bits(intAsRawFloat_extAbsIn, 34, 34)
node _intAsRawFloat_adjustedNormDist_T_35 = bits(intAsRawFloat_extAbsIn, 35, 35)
node _intAsRawFloat_adjustedNormDist_T_36 = bits(intAsRawFloat_extAbsIn, 36, 36)
node _intAsRawFloat_adjustedNormDist_T_37 = bits(intAsRawFloat_extAbsIn, 37, 37)
node _intAsRawFloat_adjustedNormDist_T_38 = bits(intAsRawFloat_extAbsIn, 38, 38)
node _intAsRawFloat_adjustedNormDist_T_39 = bits(intAsRawFloat_extAbsIn, 39, 39)
node _intAsRawFloat_adjustedNormDist_T_40 = bits(intAsRawFloat_extAbsIn, 40, 40)
node _intAsRawFloat_adjustedNormDist_T_41 = bits(intAsRawFloat_extAbsIn, 41, 41)
node _intAsRawFloat_adjustedNormDist_T_42 = bits(intAsRawFloat_extAbsIn, 42, 42)
node _intAsRawFloat_adjustedNormDist_T_43 = bits(intAsRawFloat_extAbsIn, 43, 43)
node _intAsRawFloat_adjustedNormDist_T_44 = bits(intAsRawFloat_extAbsIn, 44, 44)
node _intAsRawFloat_adjustedNormDist_T_45 = bits(intAsRawFloat_extAbsIn, 45, 45)
node _intAsRawFloat_adjustedNormDist_T_46 = bits(intAsRawFloat_extAbsIn, 46, 46)
node _intAsRawFloat_adjustedNormDist_T_47 = bits(intAsRawFloat_extAbsIn, 47, 47)
node _intAsRawFloat_adjustedNormDist_T_48 = bits(intAsRawFloat_extAbsIn, 48, 48)
node _intAsRawFloat_adjustedNormDist_T_49 = bits(intAsRawFloat_extAbsIn, 49, 49)
node _intAsRawFloat_adjustedNormDist_T_50 = bits(intAsRawFloat_extAbsIn, 50, 50)
node _intAsRawFloat_adjustedNormDist_T_51 = bits(intAsRawFloat_extAbsIn, 51, 51)
node _intAsRawFloat_adjustedNormDist_T_52 = bits(intAsRawFloat_extAbsIn, 52, 52)
node _intAsRawFloat_adjustedNormDist_T_53 = bits(intAsRawFloat_extAbsIn, 53, 53)
node _intAsRawFloat_adjustedNormDist_T_54 = bits(intAsRawFloat_extAbsIn, 54, 54)
node _intAsRawFloat_adjustedNormDist_T_55 = bits(intAsRawFloat_extAbsIn, 55, 55)
node _intAsRawFloat_adjustedNormDist_T_56 = bits(intAsRawFloat_extAbsIn, 56, 56)
node _intAsRawFloat_adjustedNormDist_T_57 = bits(intAsRawFloat_extAbsIn, 57, 57)
node _intAsRawFloat_adjustedNormDist_T_58 = bits(intAsRawFloat_extAbsIn, 58, 58)
node _intAsRawFloat_adjustedNormDist_T_59 = bits(intAsRawFloat_extAbsIn, 59, 59)
node _intAsRawFloat_adjustedNormDist_T_60 = bits(intAsRawFloat_extAbsIn, 60, 60)
node _intAsRawFloat_adjustedNormDist_T_61 = bits(intAsRawFloat_extAbsIn, 61, 61)
node _intAsRawFloat_adjustedNormDist_T_62 = bits(intAsRawFloat_extAbsIn, 62, 62)
node _intAsRawFloat_adjustedNormDist_T_63 = bits(intAsRawFloat_extAbsIn, 63, 63)
node _intAsRawFloat_adjustedNormDist_T_64 = mux(_intAsRawFloat_adjustedNormDist_T_1, UInt<6>(0h3e), UInt<6>(0h3f))
node _intAsRawFloat_adjustedNormDist_T_65 = mux(_intAsRawFloat_adjustedNormDist_T_2, UInt<6>(0h3d), _intAsRawFloat_adjustedNormDist_T_64)
node _intAsRawFloat_adjustedNormDist_T_66 = mux(_intAsRawFloat_adjustedNormDist_T_3, UInt<6>(0h3c), _intAsRawFloat_adjustedNormDist_T_65)
node _intAsRawFloat_adjustedNormDist_T_67 = mux(_intAsRawFloat_adjustedNormDist_T_4, UInt<6>(0h3b), _intAsRawFloat_adjustedNormDist_T_66)
node _intAsRawFloat_adjustedNormDist_T_68 = mux(_intAsRawFloat_adjustedNormDist_T_5, UInt<6>(0h3a), _intAsRawFloat_adjustedNormDist_T_67)
node _intAsRawFloat_adjustedNormDist_T_69 = mux(_intAsRawFloat_adjustedNormDist_T_6, UInt<6>(0h39), _intAsRawFloat_adjustedNormDist_T_68)
node _intAsRawFloat_adjustedNormDist_T_70 = mux(_intAsRawFloat_adjustedNormDist_T_7, UInt<6>(0h38), _intAsRawFloat_adjustedNormDist_T_69)
node _intAsRawFloat_adjustedNormDist_T_71 = mux(_intAsRawFloat_adjustedNormDist_T_8, UInt<6>(0h37), _intAsRawFloat_adjustedNormDist_T_70)
node _intAsRawFloat_adjustedNormDist_T_72 = mux(_intAsRawFloat_adjustedNormDist_T_9, UInt<6>(0h36), _intAsRawFloat_adjustedNormDist_T_71)
node _intAsRawFloat_adjustedNormDist_T_73 = mux(_intAsRawFloat_adjustedNormDist_T_10, UInt<6>(0h35), _intAsRawFloat_adjustedNormDist_T_72)
node _intAsRawFloat_adjustedNormDist_T_74 = mux(_intAsRawFloat_adjustedNormDist_T_11, UInt<6>(0h34), _intAsRawFloat_adjustedNormDist_T_73)
node _intAsRawFloat_adjustedNormDist_T_75 = mux(_intAsRawFloat_adjustedNormDist_T_12, UInt<6>(0h33), _intAsRawFloat_adjustedNormDist_T_74)
node _intAsRawFloat_adjustedNormDist_T_76 = mux(_intAsRawFloat_adjustedNormDist_T_13, UInt<6>(0h32), _intAsRawFloat_adjustedNormDist_T_75)
node _intAsRawFloat_adjustedNormDist_T_77 = mux(_intAsRawFloat_adjustedNormDist_T_14, UInt<6>(0h31), _intAsRawFloat_adjustedNormDist_T_76)
node _intAsRawFloat_adjustedNormDist_T_78 = mux(_intAsRawFloat_adjustedNormDist_T_15, UInt<6>(0h30), _intAsRawFloat_adjustedNormDist_T_77)
node _intAsRawFloat_adjustedNormDist_T_79 = mux(_intAsRawFloat_adjustedNormDist_T_16, UInt<6>(0h2f), _intAsRawFloat_adjustedNormDist_T_78)
node _intAsRawFloat_adjustedNormDist_T_80 = mux(_intAsRawFloat_adjustedNormDist_T_17, UInt<6>(0h2e), _intAsRawFloat_adjustedNormDist_T_79)
node _intAsRawFloat_adjustedNormDist_T_81 = mux(_intAsRawFloat_adjustedNormDist_T_18, UInt<6>(0h2d), _intAsRawFloat_adjustedNormDist_T_80)
node _intAsRawFloat_adjustedNormDist_T_82 = mux(_intAsRawFloat_adjustedNormDist_T_19, UInt<6>(0h2c), _intAsRawFloat_adjustedNormDist_T_81)
node _intAsRawFloat_adjustedNormDist_T_83 = mux(_intAsRawFloat_adjustedNormDist_T_20, UInt<6>(0h2b), _intAsRawFloat_adjustedNormDist_T_82)
node _intAsRawFloat_adjustedNormDist_T_84 = mux(_intAsRawFloat_adjustedNormDist_T_21, UInt<6>(0h2a), _intAsRawFloat_adjustedNormDist_T_83)
node _intAsRawFloat_adjustedNormDist_T_85 = mux(_intAsRawFloat_adjustedNormDist_T_22, UInt<6>(0h29), _intAsRawFloat_adjustedNormDist_T_84)
node _intAsRawFloat_adjustedNormDist_T_86 = mux(_intAsRawFloat_adjustedNormDist_T_23, UInt<6>(0h28), _intAsRawFloat_adjustedNormDist_T_85)
node _intAsRawFloat_adjustedNormDist_T_87 = mux(_intAsRawFloat_adjustedNormDist_T_24, UInt<6>(0h27), _intAsRawFloat_adjustedNormDist_T_86)
node _intAsRawFloat_adjustedNormDist_T_88 = mux(_intAsRawFloat_adjustedNormDist_T_25, UInt<6>(0h26), _intAsRawFloat_adjustedNormDist_T_87)
node _intAsRawFloat_adjustedNormDist_T_89 = mux(_intAsRawFloat_adjustedNormDist_T_26, UInt<6>(0h25), _intAsRawFloat_adjustedNormDist_T_88)
node _intAsRawFloat_adjustedNormDist_T_90 = mux(_intAsRawFloat_adjustedNormDist_T_27, UInt<6>(0h24), _intAsRawFloat_adjustedNormDist_T_89)
node _intAsRawFloat_adjustedNormDist_T_91 = mux(_intAsRawFloat_adjustedNormDist_T_28, UInt<6>(0h23), _intAsRawFloat_adjustedNormDist_T_90)
node _intAsRawFloat_adjustedNormDist_T_92 = mux(_intAsRawFloat_adjustedNormDist_T_29, UInt<6>(0h22), _intAsRawFloat_adjustedNormDist_T_91)
node _intAsRawFloat_adjustedNormDist_T_93 = mux(_intAsRawFloat_adjustedNormDist_T_30, UInt<6>(0h21), _intAsRawFloat_adjustedNormDist_T_92)
node _intAsRawFloat_adjustedNormDist_T_94 = mux(_intAsRawFloat_adjustedNormDist_T_31, UInt<6>(0h20), _intAsRawFloat_adjustedNormDist_T_93)
node _intAsRawFloat_adjustedNormDist_T_95 = mux(_intAsRawFloat_adjustedNormDist_T_32, UInt<5>(0h1f), _intAsRawFloat_adjustedNormDist_T_94)
node _intAsRawFloat_adjustedNormDist_T_96 = mux(_intAsRawFloat_adjustedNormDist_T_33, UInt<5>(0h1e), _intAsRawFloat_adjustedNormDist_T_95)
node _intAsRawFloat_adjustedNormDist_T_97 = mux(_intAsRawFloat_adjustedNormDist_T_34, UInt<5>(0h1d), _intAsRawFloat_adjustedNormDist_T_96)
node _intAsRawFloat_adjustedNormDist_T_98 = mux(_intAsRawFloat_adjustedNormDist_T_35, UInt<5>(0h1c), _intAsRawFloat_adjustedNormDist_T_97)
node _intAsRawFloat_adjustedNormDist_T_99 = mux(_intAsRawFloat_adjustedNormDist_T_36, UInt<5>(0h1b), _intAsRawFloat_adjustedNormDist_T_98)
node _intAsRawFloat_adjustedNormDist_T_100 = mux(_intAsRawFloat_adjustedNormDist_T_37, UInt<5>(0h1a), _intAsRawFloat_adjustedNormDist_T_99)
node _intAsRawFloat_adjustedNormDist_T_101 = mux(_intAsRawFloat_adjustedNormDist_T_38, UInt<5>(0h19), _intAsRawFloat_adjustedNormDist_T_100)
node _intAsRawFloat_adjustedNormDist_T_102 = mux(_intAsRawFloat_adjustedNormDist_T_39, UInt<5>(0h18), _intAsRawFloat_adjustedNormDist_T_101)
node _intAsRawFloat_adjustedNormDist_T_103 = mux(_intAsRawFloat_adjustedNormDist_T_40, UInt<5>(0h17), _intAsRawFloat_adjustedNormDist_T_102)
node _intAsRawFloat_adjustedNormDist_T_104 = mux(_intAsRawFloat_adjustedNormDist_T_41, UInt<5>(0h16), _intAsRawFloat_adjustedNormDist_T_103)
node _intAsRawFloat_adjustedNormDist_T_105 = mux(_intAsRawFloat_adjustedNormDist_T_42, UInt<5>(0h15), _intAsRawFloat_adjustedNormDist_T_104)
node _intAsRawFloat_adjustedNormDist_T_106 = mux(_intAsRawFloat_adjustedNormDist_T_43, UInt<5>(0h14), _intAsRawFloat_adjustedNormDist_T_105)
node _intAsRawFloat_adjustedNormDist_T_107 = mux(_intAsRawFloat_adjustedNormDist_T_44, UInt<5>(0h13), _intAsRawFloat_adjustedNormDist_T_106)
node _intAsRawFloat_adjustedNormDist_T_108 = mux(_intAsRawFloat_adjustedNormDist_T_45, UInt<5>(0h12), _intAsRawFloat_adjustedNormDist_T_107)
node _intAsRawFloat_adjustedNormDist_T_109 = mux(_intAsRawFloat_adjustedNormDist_T_46, UInt<5>(0h11), _intAsRawFloat_adjustedNormDist_T_108)
node _intAsRawFloat_adjustedNormDist_T_110 = mux(_intAsRawFloat_adjustedNormDist_T_47, UInt<5>(0h10), _intAsRawFloat_adjustedNormDist_T_109)
node _intAsRawFloat_adjustedNormDist_T_111 = mux(_intAsRawFloat_adjustedNormDist_T_48, UInt<4>(0hf), _intAsRawFloat_adjustedNormDist_T_110)
node _intAsRawFloat_adjustedNormDist_T_112 = mux(_intAsRawFloat_adjustedNormDist_T_49, UInt<4>(0he), _intAsRawFloat_adjustedNormDist_T_111)
node _intAsRawFloat_adjustedNormDist_T_113 = mux(_intAsRawFloat_adjustedNormDist_T_50, UInt<4>(0hd), _intAsRawFloat_adjustedNormDist_T_112)
node _intAsRawFloat_adjustedNormDist_T_114 = mux(_intAsRawFloat_adjustedNormDist_T_51, UInt<4>(0hc), _intAsRawFloat_adjustedNormDist_T_113)
node _intAsRawFloat_adjustedNormDist_T_115 = mux(_intAsRawFloat_adjustedNormDist_T_52, UInt<4>(0hb), _intAsRawFloat_adjustedNormDist_T_114)
node _intAsRawFloat_adjustedNormDist_T_116 = mux(_intAsRawFloat_adjustedNormDist_T_53, UInt<4>(0ha), _intAsRawFloat_adjustedNormDist_T_115)
node _intAsRawFloat_adjustedNormDist_T_117 = mux(_intAsRawFloat_adjustedNormDist_T_54, UInt<4>(0h9), _intAsRawFloat_adjustedNormDist_T_116)
node _intAsRawFloat_adjustedNormDist_T_118 = mux(_intAsRawFloat_adjustedNormDist_T_55, UInt<4>(0h8), _intAsRawFloat_adjustedNormDist_T_117)
node _intAsRawFloat_adjustedNormDist_T_119 = mux(_intAsRawFloat_adjustedNormDist_T_56, UInt<3>(0h7), _intAsRawFloat_adjustedNormDist_T_118)
node _intAsRawFloat_adjustedNormDist_T_120 = mux(_intAsRawFloat_adjustedNormDist_T_57, UInt<3>(0h6), _intAsRawFloat_adjustedNormDist_T_119)
node _intAsRawFloat_adjustedNormDist_T_121 = mux(_intAsRawFloat_adjustedNormDist_T_58, UInt<3>(0h5), _intAsRawFloat_adjustedNormDist_T_120)
node _intAsRawFloat_adjustedNormDist_T_122 = mux(_intAsRawFloat_adjustedNormDist_T_59, UInt<3>(0h4), _intAsRawFloat_adjustedNormDist_T_121)
node _intAsRawFloat_adjustedNormDist_T_123 = mux(_intAsRawFloat_adjustedNormDist_T_60, UInt<2>(0h3), _intAsRawFloat_adjustedNormDist_T_122)
node _intAsRawFloat_adjustedNormDist_T_124 = mux(_intAsRawFloat_adjustedNormDist_T_61, UInt<2>(0h2), _intAsRawFloat_adjustedNormDist_T_123)
node _intAsRawFloat_adjustedNormDist_T_125 = mux(_intAsRawFloat_adjustedNormDist_T_62, UInt<1>(0h1), _intAsRawFloat_adjustedNormDist_T_124)
node intAsRawFloat_adjustedNormDist = mux(_intAsRawFloat_adjustedNormDist_T_63, UInt<1>(0h0), _intAsRawFloat_adjustedNormDist_T_125)
node _intAsRawFloat_sig_T = dshl(intAsRawFloat_extAbsIn, intAsRawFloat_adjustedNormDist)
node intAsRawFloat_sig = bits(_intAsRawFloat_sig_T, 63, 0)
wire intAsRawFloat : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<9>, sig : UInt<65>}
connect intAsRawFloat.isNaN, UInt<1>(0h0)
connect intAsRawFloat.isInf, UInt<1>(0h0)
node _intAsRawFloat_out_isZero_T = bits(intAsRawFloat_sig, 63, 63)
node _intAsRawFloat_out_isZero_T_1 = eq(_intAsRawFloat_out_isZero_T, UInt<1>(0h0))
connect intAsRawFloat.isZero, _intAsRawFloat_out_isZero_T_1
connect intAsRawFloat.sign, intAsRawFloat_sign
node _intAsRawFloat_out_sExp_T = bits(intAsRawFloat_adjustedNormDist, 5, 0)
node _intAsRawFloat_out_sExp_T_1 = not(_intAsRawFloat_out_sExp_T)
node _intAsRawFloat_out_sExp_T_2 = cat(UInt<2>(0h2), _intAsRawFloat_out_sExp_T_1)
node _intAsRawFloat_out_sExp_T_3 = cvt(_intAsRawFloat_out_sExp_T_2)
connect intAsRawFloat.sExp, _intAsRawFloat_out_sExp_T_3
connect intAsRawFloat.sig, intAsRawFloat_sig
inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie7_is64_oe11_os53_2
connect roundAnyRawFNToRecFN.io.invalidExc, UInt<1>(0h0)
connect roundAnyRawFNToRecFN.io.infiniteExc, UInt<1>(0h0)
connect roundAnyRawFNToRecFN.io.in.sig, intAsRawFloat.sig
connect roundAnyRawFNToRecFN.io.in.sExp, intAsRawFloat.sExp
connect roundAnyRawFNToRecFN.io.in.sign, intAsRawFloat.sign
connect roundAnyRawFNToRecFN.io.in.isZero, intAsRawFloat.isZero
connect roundAnyRawFNToRecFN.io.in.isInf, intAsRawFloat.isInf
connect roundAnyRawFNToRecFN.io.in.isNaN, intAsRawFloat.isNaN
connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode
connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess
connect io.out, roundAnyRawFNToRecFN.io.out
connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags | module INToRecFN_i64_e11_s53_2( // @[INToRecFN.scala:43:7]
input io_signedIn, // @[INToRecFN.scala:46:16]
input [63:0] io_in, // @[INToRecFN.scala:46:16]
input [2:0] io_roundingMode, // @[INToRecFN.scala:46:16]
output [64:0] io_out, // @[INToRecFN.scala:46:16]
output [4:0] io_exceptionFlags // @[INToRecFN.scala:46:16]
);
wire io_signedIn_0 = io_signedIn; // @[INToRecFN.scala:43:7]
wire [63:0] io_in_0 = io_in; // @[INToRecFN.scala:43:7]
wire [2:0] io_roundingMode_0 = io_roundingMode; // @[INToRecFN.scala:43:7]
wire intAsRawFloat_isNaN = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire intAsRawFloat_isInf = 1'h0; // @[rawFloatFromIN.scala:59:23]
wire io_detectTininess = 1'h1; // @[INToRecFN.scala:43:7]
wire [64:0] io_out_0; // @[INToRecFN.scala:43:7]
wire [4:0] io_exceptionFlags_0; // @[INToRecFN.scala:43:7]
wire _intAsRawFloat_sign_T = io_in_0[63]; // @[rawFloatFromIN.scala:51:34]
wire intAsRawFloat_sign = io_signedIn_0 & _intAsRawFloat_sign_T; // @[rawFloatFromIN.scala:51:{29,34}]
wire intAsRawFloat_sign_0 = intAsRawFloat_sign; // @[rawFloatFromIN.scala:51:29, :59:23]
wire [64:0] _intAsRawFloat_absIn_T = 65'h0 - {1'h0, io_in_0}; // @[rawFloatFromIN.scala:52:31]
wire [63:0] _intAsRawFloat_absIn_T_1 = _intAsRawFloat_absIn_T[63:0]; // @[rawFloatFromIN.scala:52:31]
wire [63:0] intAsRawFloat_absIn = intAsRawFloat_sign ? _intAsRawFloat_absIn_T_1 : io_in_0; // @[rawFloatFromIN.scala:51:29, :52:{24,31}]
wire [127:0] _intAsRawFloat_extAbsIn_T = {64'h0, intAsRawFloat_absIn}; // @[rawFloatFromIN.scala:52:24, :53:44]
wire [63:0] intAsRawFloat_extAbsIn = _intAsRawFloat_extAbsIn_T[63:0]; // @[rawFloatFromIN.scala:53:{44,53}]
wire _intAsRawFloat_adjustedNormDist_T = intAsRawFloat_extAbsIn[0]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_1 = intAsRawFloat_extAbsIn[1]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_2 = intAsRawFloat_extAbsIn[2]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_3 = intAsRawFloat_extAbsIn[3]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_4 = intAsRawFloat_extAbsIn[4]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_5 = intAsRawFloat_extAbsIn[5]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_6 = intAsRawFloat_extAbsIn[6]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_7 = intAsRawFloat_extAbsIn[7]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_8 = intAsRawFloat_extAbsIn[8]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_9 = intAsRawFloat_extAbsIn[9]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_10 = intAsRawFloat_extAbsIn[10]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_11 = intAsRawFloat_extAbsIn[11]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_12 = intAsRawFloat_extAbsIn[12]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_13 = intAsRawFloat_extAbsIn[13]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_14 = intAsRawFloat_extAbsIn[14]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_15 = intAsRawFloat_extAbsIn[15]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_16 = intAsRawFloat_extAbsIn[16]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_17 = intAsRawFloat_extAbsIn[17]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_18 = intAsRawFloat_extAbsIn[18]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_19 = intAsRawFloat_extAbsIn[19]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_20 = intAsRawFloat_extAbsIn[20]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_21 = intAsRawFloat_extAbsIn[21]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_22 = intAsRawFloat_extAbsIn[22]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_23 = intAsRawFloat_extAbsIn[23]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_24 = intAsRawFloat_extAbsIn[24]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_25 = intAsRawFloat_extAbsIn[25]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_26 = intAsRawFloat_extAbsIn[26]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_27 = intAsRawFloat_extAbsIn[27]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_28 = intAsRawFloat_extAbsIn[28]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_29 = intAsRawFloat_extAbsIn[29]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_30 = intAsRawFloat_extAbsIn[30]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_31 = intAsRawFloat_extAbsIn[31]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_32 = intAsRawFloat_extAbsIn[32]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_33 = intAsRawFloat_extAbsIn[33]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_34 = intAsRawFloat_extAbsIn[34]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_35 = intAsRawFloat_extAbsIn[35]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_36 = intAsRawFloat_extAbsIn[36]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_37 = intAsRawFloat_extAbsIn[37]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_38 = intAsRawFloat_extAbsIn[38]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_39 = intAsRawFloat_extAbsIn[39]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_40 = intAsRawFloat_extAbsIn[40]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_41 = intAsRawFloat_extAbsIn[41]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_42 = intAsRawFloat_extAbsIn[42]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_43 = intAsRawFloat_extAbsIn[43]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_44 = intAsRawFloat_extAbsIn[44]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_45 = intAsRawFloat_extAbsIn[45]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_46 = intAsRawFloat_extAbsIn[46]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_47 = intAsRawFloat_extAbsIn[47]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_48 = intAsRawFloat_extAbsIn[48]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_49 = intAsRawFloat_extAbsIn[49]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_50 = intAsRawFloat_extAbsIn[50]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_51 = intAsRawFloat_extAbsIn[51]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_52 = intAsRawFloat_extAbsIn[52]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_53 = intAsRawFloat_extAbsIn[53]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_54 = intAsRawFloat_extAbsIn[54]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_55 = intAsRawFloat_extAbsIn[55]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_56 = intAsRawFloat_extAbsIn[56]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_57 = intAsRawFloat_extAbsIn[57]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_58 = intAsRawFloat_extAbsIn[58]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_59 = intAsRawFloat_extAbsIn[59]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_60 = intAsRawFloat_extAbsIn[60]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_61 = intAsRawFloat_extAbsIn[61]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_62 = intAsRawFloat_extAbsIn[62]; // @[rawFloatFromIN.scala:53:53]
wire _intAsRawFloat_adjustedNormDist_T_63 = intAsRawFloat_extAbsIn[63]; // @[rawFloatFromIN.scala:53:53]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_64 = {5'h1F, ~_intAsRawFloat_adjustedNormDist_T_1}; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_65 = _intAsRawFloat_adjustedNormDist_T_2 ? 6'h3D : _intAsRawFloat_adjustedNormDist_T_64; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_66 = _intAsRawFloat_adjustedNormDist_T_3 ? 6'h3C : _intAsRawFloat_adjustedNormDist_T_65; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_67 = _intAsRawFloat_adjustedNormDist_T_4 ? 6'h3B : _intAsRawFloat_adjustedNormDist_T_66; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_68 = _intAsRawFloat_adjustedNormDist_T_5 ? 6'h3A : _intAsRawFloat_adjustedNormDist_T_67; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_69 = _intAsRawFloat_adjustedNormDist_T_6 ? 6'h39 : _intAsRawFloat_adjustedNormDist_T_68; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_70 = _intAsRawFloat_adjustedNormDist_T_7 ? 6'h38 : _intAsRawFloat_adjustedNormDist_T_69; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_71 = _intAsRawFloat_adjustedNormDist_T_8 ? 6'h37 : _intAsRawFloat_adjustedNormDist_T_70; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_72 = _intAsRawFloat_adjustedNormDist_T_9 ? 6'h36 : _intAsRawFloat_adjustedNormDist_T_71; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_73 = _intAsRawFloat_adjustedNormDist_T_10 ? 6'h35 : _intAsRawFloat_adjustedNormDist_T_72; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_74 = _intAsRawFloat_adjustedNormDist_T_11 ? 6'h34 : _intAsRawFloat_adjustedNormDist_T_73; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_75 = _intAsRawFloat_adjustedNormDist_T_12 ? 6'h33 : _intAsRawFloat_adjustedNormDist_T_74; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_76 = _intAsRawFloat_adjustedNormDist_T_13 ? 6'h32 : _intAsRawFloat_adjustedNormDist_T_75; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_77 = _intAsRawFloat_adjustedNormDist_T_14 ? 6'h31 : _intAsRawFloat_adjustedNormDist_T_76; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_78 = _intAsRawFloat_adjustedNormDist_T_15 ? 6'h30 : _intAsRawFloat_adjustedNormDist_T_77; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_79 = _intAsRawFloat_adjustedNormDist_T_16 ? 6'h2F : _intAsRawFloat_adjustedNormDist_T_78; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_80 = _intAsRawFloat_adjustedNormDist_T_17 ? 6'h2E : _intAsRawFloat_adjustedNormDist_T_79; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_81 = _intAsRawFloat_adjustedNormDist_T_18 ? 6'h2D : _intAsRawFloat_adjustedNormDist_T_80; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_82 = _intAsRawFloat_adjustedNormDist_T_19 ? 6'h2C : _intAsRawFloat_adjustedNormDist_T_81; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_83 = _intAsRawFloat_adjustedNormDist_T_20 ? 6'h2B : _intAsRawFloat_adjustedNormDist_T_82; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_84 = _intAsRawFloat_adjustedNormDist_T_21 ? 6'h2A : _intAsRawFloat_adjustedNormDist_T_83; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_85 = _intAsRawFloat_adjustedNormDist_T_22 ? 6'h29 : _intAsRawFloat_adjustedNormDist_T_84; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_86 = _intAsRawFloat_adjustedNormDist_T_23 ? 6'h28 : _intAsRawFloat_adjustedNormDist_T_85; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_87 = _intAsRawFloat_adjustedNormDist_T_24 ? 6'h27 : _intAsRawFloat_adjustedNormDist_T_86; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_88 = _intAsRawFloat_adjustedNormDist_T_25 ? 6'h26 : _intAsRawFloat_adjustedNormDist_T_87; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_89 = _intAsRawFloat_adjustedNormDist_T_26 ? 6'h25 : _intAsRawFloat_adjustedNormDist_T_88; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_90 = _intAsRawFloat_adjustedNormDist_T_27 ? 6'h24 : _intAsRawFloat_adjustedNormDist_T_89; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_91 = _intAsRawFloat_adjustedNormDist_T_28 ? 6'h23 : _intAsRawFloat_adjustedNormDist_T_90; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_92 = _intAsRawFloat_adjustedNormDist_T_29 ? 6'h22 : _intAsRawFloat_adjustedNormDist_T_91; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_93 = _intAsRawFloat_adjustedNormDist_T_30 ? 6'h21 : _intAsRawFloat_adjustedNormDist_T_92; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_94 = _intAsRawFloat_adjustedNormDist_T_31 ? 6'h20 : _intAsRawFloat_adjustedNormDist_T_93; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_95 = _intAsRawFloat_adjustedNormDist_T_32 ? 6'h1F : _intAsRawFloat_adjustedNormDist_T_94; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_96 = _intAsRawFloat_adjustedNormDist_T_33 ? 6'h1E : _intAsRawFloat_adjustedNormDist_T_95; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_97 = _intAsRawFloat_adjustedNormDist_T_34 ? 6'h1D : _intAsRawFloat_adjustedNormDist_T_96; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_98 = _intAsRawFloat_adjustedNormDist_T_35 ? 6'h1C : _intAsRawFloat_adjustedNormDist_T_97; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_99 = _intAsRawFloat_adjustedNormDist_T_36 ? 6'h1B : _intAsRawFloat_adjustedNormDist_T_98; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_100 = _intAsRawFloat_adjustedNormDist_T_37 ? 6'h1A : _intAsRawFloat_adjustedNormDist_T_99; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_101 = _intAsRawFloat_adjustedNormDist_T_38 ? 6'h19 : _intAsRawFloat_adjustedNormDist_T_100; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_102 = _intAsRawFloat_adjustedNormDist_T_39 ? 6'h18 : _intAsRawFloat_adjustedNormDist_T_101; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_103 = _intAsRawFloat_adjustedNormDist_T_40 ? 6'h17 : _intAsRawFloat_adjustedNormDist_T_102; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_104 = _intAsRawFloat_adjustedNormDist_T_41 ? 6'h16 : _intAsRawFloat_adjustedNormDist_T_103; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_105 = _intAsRawFloat_adjustedNormDist_T_42 ? 6'h15 : _intAsRawFloat_adjustedNormDist_T_104; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_106 = _intAsRawFloat_adjustedNormDist_T_43 ? 6'h14 : _intAsRawFloat_adjustedNormDist_T_105; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_107 = _intAsRawFloat_adjustedNormDist_T_44 ? 6'h13 : _intAsRawFloat_adjustedNormDist_T_106; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_108 = _intAsRawFloat_adjustedNormDist_T_45 ? 6'h12 : _intAsRawFloat_adjustedNormDist_T_107; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_109 = _intAsRawFloat_adjustedNormDist_T_46 ? 6'h11 : _intAsRawFloat_adjustedNormDist_T_108; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_110 = _intAsRawFloat_adjustedNormDist_T_47 ? 6'h10 : _intAsRawFloat_adjustedNormDist_T_109; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_111 = _intAsRawFloat_adjustedNormDist_T_48 ? 6'hF : _intAsRawFloat_adjustedNormDist_T_110; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_112 = _intAsRawFloat_adjustedNormDist_T_49 ? 6'hE : _intAsRawFloat_adjustedNormDist_T_111; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_113 = _intAsRawFloat_adjustedNormDist_T_50 ? 6'hD : _intAsRawFloat_adjustedNormDist_T_112; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_114 = _intAsRawFloat_adjustedNormDist_T_51 ? 6'hC : _intAsRawFloat_adjustedNormDist_T_113; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_115 = _intAsRawFloat_adjustedNormDist_T_52 ? 6'hB : _intAsRawFloat_adjustedNormDist_T_114; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_116 = _intAsRawFloat_adjustedNormDist_T_53 ? 6'hA : _intAsRawFloat_adjustedNormDist_T_115; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_117 = _intAsRawFloat_adjustedNormDist_T_54 ? 6'h9 : _intAsRawFloat_adjustedNormDist_T_116; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_118 = _intAsRawFloat_adjustedNormDist_T_55 ? 6'h8 : _intAsRawFloat_adjustedNormDist_T_117; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_119 = _intAsRawFloat_adjustedNormDist_T_56 ? 6'h7 : _intAsRawFloat_adjustedNormDist_T_118; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_120 = _intAsRawFloat_adjustedNormDist_T_57 ? 6'h6 : _intAsRawFloat_adjustedNormDist_T_119; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_121 = _intAsRawFloat_adjustedNormDist_T_58 ? 6'h5 : _intAsRawFloat_adjustedNormDist_T_120; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_122 = _intAsRawFloat_adjustedNormDist_T_59 ? 6'h4 : _intAsRawFloat_adjustedNormDist_T_121; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_123 = _intAsRawFloat_adjustedNormDist_T_60 ? 6'h3 : _intAsRawFloat_adjustedNormDist_T_122; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_124 = _intAsRawFloat_adjustedNormDist_T_61 ? 6'h2 : _intAsRawFloat_adjustedNormDist_T_123; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_adjustedNormDist_T_125 = _intAsRawFloat_adjustedNormDist_T_62 ? 6'h1 : _intAsRawFloat_adjustedNormDist_T_124; // @[Mux.scala:50:70]
wire [5:0] intAsRawFloat_adjustedNormDist = _intAsRawFloat_adjustedNormDist_T_63 ? 6'h0 : _intAsRawFloat_adjustedNormDist_T_125; // @[Mux.scala:50:70]
wire [5:0] _intAsRawFloat_out_sExp_T = intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70]
wire [126:0] _intAsRawFloat_sig_T = {63'h0, intAsRawFloat_extAbsIn} << intAsRawFloat_adjustedNormDist; // @[Mux.scala:50:70]
wire [63:0] intAsRawFloat_sig = _intAsRawFloat_sig_T[63:0]; // @[rawFloatFromIN.scala:56:{22,41}]
wire _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:62:23]
wire [8:0] _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:64:72]
wire intAsRawFloat_isZero; // @[rawFloatFromIN.scala:59:23]
wire [8:0] intAsRawFloat_sExp; // @[rawFloatFromIN.scala:59:23]
wire [64:0] intAsRawFloat_sig_0; // @[rawFloatFromIN.scala:59:23]
wire _intAsRawFloat_out_isZero_T = intAsRawFloat_sig[63]; // @[rawFloatFromIN.scala:56:41, :62:28]
assign _intAsRawFloat_out_isZero_T_1 = ~_intAsRawFloat_out_isZero_T; // @[rawFloatFromIN.scala:62:{23,28}]
assign intAsRawFloat_isZero = _intAsRawFloat_out_isZero_T_1; // @[rawFloatFromIN.scala:59:23, :62:23]
wire [5:0] _intAsRawFloat_out_sExp_T_1 = ~_intAsRawFloat_out_sExp_T; // @[rawFloatFromIN.scala:64:{36,53}]
wire [7:0] _intAsRawFloat_out_sExp_T_2 = {2'h2, _intAsRawFloat_out_sExp_T_1}; // @[rawFloatFromIN.scala:64:{33,36}]
assign _intAsRawFloat_out_sExp_T_3 = {1'h0, _intAsRawFloat_out_sExp_T_2}; // @[rawFloatFromIN.scala:64:{33,72}]
assign intAsRawFloat_sExp = _intAsRawFloat_out_sExp_T_3; // @[rawFloatFromIN.scala:59:23, :64:72]
assign intAsRawFloat_sig_0 = {1'h0, intAsRawFloat_sig}; // @[rawFloatFromIN.scala:56:41, :59:23, :65:20]
RoundAnyRawFNToRecFN_ie7_is64_oe11_os53_2 roundAnyRawFNToRecFN ( // @[INToRecFN.scala:60:15]
.io_in_isZero (intAsRawFloat_isZero), // @[rawFloatFromIN.scala:59:23]
.io_in_sign (intAsRawFloat_sign_0), // @[rawFloatFromIN.scala:59:23]
.io_in_sExp (intAsRawFloat_sExp), // @[rawFloatFromIN.scala:59:23]
.io_in_sig (intAsRawFloat_sig_0), // @[rawFloatFromIN.scala:59:23]
.io_roundingMode (io_roundingMode_0), // @[INToRecFN.scala:43:7]
.io_out (io_out_0),
.io_exceptionFlags (io_exceptionFlags_0)
); // @[INToRecFN.scala:60:15]
assign io_out = io_out_0; // @[INToRecFN.scala:43:7]
assign io_exceptionFlags = io_exceptionFlags_0; // @[INToRecFN.scala:43:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_53 :
input clock : Clock
input reset : Reset
output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}}
when io.in.a.valid :
node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7))
node _T_1 = asUInt(reset)
node _T_2 = eq(_T_1, UInt<1>(0h0))
when _T_2 :
node _T_3 = eq(_T, UInt<1>(0h0))
when _T_3 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf
assert(clock, _T, UInt<1>(0h1), "") : assert
node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE : UInt<1>[1]
connect _source_ok_WIRE[0], _source_ok_T
node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0)
node is_aligned_mask = not(_is_aligned_mask_T_1)
node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask)
node is_aligned = eq(_is_aligned_T, UInt<1>(0h0))
node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0))
node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0)
node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount)
node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0)
node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1))
node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2))
node mask_sub_size = bits(mask_sizeOH, 1, 1)
node mask_sub_bit = bits(io.in.a.bits.address, 1, 1)
node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0))
node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit)
node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2)
node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T)
node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit)
node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2)
node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1)
node mask_size = bits(mask_sizeOH, 0, 0)
node mask_bit = bits(io.in.a.bits.address, 0, 0)
node mask_nbit = eq(mask_bit, UInt<1>(0h0))
node mask_eq = and(mask_sub_0_2, mask_nbit)
node _mask_acc_T = and(mask_size, mask_eq)
node mask_acc = or(mask_sub_0_1, _mask_acc_T)
node mask_eq_1 = and(mask_sub_0_2, mask_bit)
node _mask_acc_T_1 = and(mask_size, mask_eq_1)
node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1)
node mask_eq_2 = and(mask_sub_1_2, mask_nbit)
node _mask_acc_T_2 = and(mask_size, mask_eq_2)
node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2)
node mask_eq_3 = and(mask_sub_1_2, mask_bit)
node _mask_acc_T_3 = and(mask_size, mask_eq_3)
node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3)
node mask_lo = cat(mask_acc_1, mask_acc)
node mask_hi = cat(mask_acc_3, mask_acc_2)
node mask = cat(mask_hi, mask_lo)
node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_5 = eq(_T_4, UInt<1>(0h0))
node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_7 = cvt(_T_6)
node _T_8 = and(_T_7, asSInt(UInt<1>(0h0)))
node _T_9 = asSInt(_T_8)
node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0)))
node _T_11 = or(_T_5, _T_10)
node _T_12 = asUInt(reset)
node _T_13 = eq(_T_12, UInt<1>(0h0))
when _T_13 :
node _T_14 = eq(_T_11, UInt<1>(0h0))
when _T_14 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1
assert(clock, _T_11, UInt<1>(0h1), "") : assert_1
node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6))
when _T_15 :
node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_17 = and(UInt<1>(0h0), _T_16)
node _T_18 = or(UInt<1>(0h0), _T_17)
node _T_19 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_20 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_21 = and(_T_19, _T_20)
node _T_22 = or(UInt<1>(0h0), _T_21)
node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_24 = cvt(_T_23)
node _T_25 = and(_T_24, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_26 = asSInt(_T_25)
node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0)))
node _T_28 = and(_T_22, _T_27)
node _T_29 = or(UInt<1>(0h0), _T_28)
node _T_30 = and(_T_18, _T_29)
node _T_31 = asUInt(reset)
node _T_32 = eq(_T_31, UInt<1>(0h0))
when _T_32 :
node _T_33 = eq(_T_30, UInt<1>(0h0))
when _T_33 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2
assert(clock, _T_30, UInt<1>(0h1), "") : assert_2
node _T_34 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_35 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_36 = and(_T_34, _T_35)
node _T_37 = or(UInt<1>(0h0), _T_36)
node _T_38 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_39 = cvt(_T_38)
node _T_40 = and(_T_39, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_41 = asSInt(_T_40)
node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0)))
node _T_43 = and(_T_37, _T_42)
node _T_44 = or(UInt<1>(0h0), _T_43)
node _T_45 = and(UInt<1>(0h0), _T_44)
node _T_46 = asUInt(reset)
node _T_47 = eq(_T_46, UInt<1>(0h0))
when _T_47 :
node _T_48 = eq(_T_45, UInt<1>(0h0))
when _T_48 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3
assert(clock, _T_45, UInt<1>(0h1), "") : assert_3
node _T_49 = asUInt(reset)
node _T_50 = eq(_T_49, UInt<1>(0h0))
when _T_50 :
node _T_51 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_51 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4
node _T_52 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_53 = asUInt(reset)
node _T_54 = eq(_T_53, UInt<1>(0h0))
when _T_54 :
node _T_55 = eq(_T_52, UInt<1>(0h0))
when _T_55 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5
assert(clock, _T_52, UInt<1>(0h1), "") : assert_5
node _T_56 = asUInt(reset)
node _T_57 = eq(_T_56, UInt<1>(0h0))
when _T_57 :
node _T_58 = eq(is_aligned, UInt<1>(0h0))
when _T_58 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6
node _T_59 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_60 = asUInt(reset)
node _T_61 = eq(_T_60, UInt<1>(0h0))
when _T_61 :
node _T_62 = eq(_T_59, UInt<1>(0h0))
when _T_62 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7
assert(clock, _T_59, UInt<1>(0h1), "") : assert_7
node _T_63 = not(io.in.a.bits.mask)
node _T_64 = eq(_T_63, UInt<1>(0h0))
node _T_65 = asUInt(reset)
node _T_66 = eq(_T_65, UInt<1>(0h0))
when _T_66 :
node _T_67 = eq(_T_64, UInt<1>(0h0))
when _T_67 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8
assert(clock, _T_64, UInt<1>(0h1), "") : assert_8
node _T_68 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_69 = asUInt(reset)
node _T_70 = eq(_T_69, UInt<1>(0h0))
when _T_70 :
node _T_71 = eq(_T_68, UInt<1>(0h0))
when _T_71 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9
assert(clock, _T_68, UInt<1>(0h1), "") : assert_9
node _T_72 = eq(io.in.a.bits.opcode, UInt<3>(0h7))
when _T_72 :
node _T_73 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_74 = and(UInt<1>(0h0), _T_73)
node _T_75 = or(UInt<1>(0h0), _T_74)
node _T_76 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_77 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_78 = and(_T_76, _T_77)
node _T_79 = or(UInt<1>(0h0), _T_78)
node _T_80 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_81 = cvt(_T_80)
node _T_82 = and(_T_81, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_83 = asSInt(_T_82)
node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0)))
node _T_85 = and(_T_79, _T_84)
node _T_86 = or(UInt<1>(0h0), _T_85)
node _T_87 = and(_T_75, _T_86)
node _T_88 = asUInt(reset)
node _T_89 = eq(_T_88, UInt<1>(0h0))
when _T_89 :
node _T_90 = eq(_T_87, UInt<1>(0h0))
when _T_90 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10
assert(clock, _T_87, UInt<1>(0h1), "") : assert_10
node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc))
node _T_93 = and(_T_91, _T_92)
node _T_94 = or(UInt<1>(0h0), _T_93)
node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_96 = cvt(_T_95)
node _T_97 = and(_T_96, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_98 = asSInt(_T_97)
node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0)))
node _T_100 = and(_T_94, _T_99)
node _T_101 = or(UInt<1>(0h0), _T_100)
node _T_102 = and(UInt<1>(0h0), _T_101)
node _T_103 = asUInt(reset)
node _T_104 = eq(_T_103, UInt<1>(0h0))
when _T_104 :
node _T_105 = eq(_T_102, UInt<1>(0h0))
when _T_105 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11
assert(clock, _T_102, UInt<1>(0h1), "") : assert_11
node _T_106 = asUInt(reset)
node _T_107 = eq(_T_106, UInt<1>(0h0))
when _T_107 :
node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_108 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12
node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2))
node _T_110 = asUInt(reset)
node _T_111 = eq(_T_110, UInt<1>(0h0))
when _T_111 :
node _T_112 = eq(_T_109, UInt<1>(0h0))
when _T_112 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13
assert(clock, _T_109, UInt<1>(0h1), "") : assert_13
node _T_113 = asUInt(reset)
node _T_114 = eq(_T_113, UInt<1>(0h0))
when _T_114 :
node _T_115 = eq(is_aligned, UInt<1>(0h0))
when _T_115 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14
node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2))
node _T_117 = asUInt(reset)
node _T_118 = eq(_T_117, UInt<1>(0h0))
when _T_118 :
node _T_119 = eq(_T_116, UInt<1>(0h0))
when _T_119 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15
assert(clock, _T_116, UInt<1>(0h1), "") : assert_15
node _T_120 = neq(io.in.a.bits.param, UInt<2>(0h0))
node _T_121 = asUInt(reset)
node _T_122 = eq(_T_121, UInt<1>(0h0))
when _T_122 :
node _T_123 = eq(_T_120, UInt<1>(0h0))
when _T_123 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16
assert(clock, _T_120, UInt<1>(0h1), "") : assert_16
node _T_124 = not(io.in.a.bits.mask)
node _T_125 = eq(_T_124, UInt<1>(0h0))
node _T_126 = asUInt(reset)
node _T_127 = eq(_T_126, UInt<1>(0h0))
when _T_127 :
node _T_128 = eq(_T_125, UInt<1>(0h0))
when _T_128 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17
assert(clock, _T_125, UInt<1>(0h1), "") : assert_17
node _T_129 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_130 = asUInt(reset)
node _T_131 = eq(_T_130, UInt<1>(0h0))
when _T_131 :
node _T_132 = eq(_T_129, UInt<1>(0h0))
when _T_132 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18
assert(clock, _T_129, UInt<1>(0h1), "") : assert_18
node _T_133 = eq(io.in.a.bits.opcode, UInt<3>(0h4))
when _T_133 :
node _T_134 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_135 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_136 = and(_T_134, _T_135)
node _T_137 = or(UInt<1>(0h0), _T_136)
node _T_138 = asUInt(reset)
node _T_139 = eq(_T_138, UInt<1>(0h0))
when _T_139 :
node _T_140 = eq(_T_137, UInt<1>(0h0))
when _T_140 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19
assert(clock, _T_137, UInt<1>(0h1), "") : assert_19
node _T_141 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_142 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_143 = and(_T_141, _T_142)
node _T_144 = or(UInt<1>(0h0), _T_143)
node _T_145 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_146 = cvt(_T_145)
node _T_147 = and(_T_146, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_148 = asSInt(_T_147)
node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0)))
node _T_150 = and(_T_144, _T_149)
node _T_151 = or(UInt<1>(0h0), _T_150)
node _T_152 = asUInt(reset)
node _T_153 = eq(_T_152, UInt<1>(0h0))
when _T_153 :
node _T_154 = eq(_T_151, UInt<1>(0h0))
when _T_154 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20
assert(clock, _T_151, UInt<1>(0h1), "") : assert_20
node _T_155 = asUInt(reset)
node _T_156 = eq(_T_155, UInt<1>(0h0))
when _T_156 :
node _T_157 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_157 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21
node _T_158 = asUInt(reset)
node _T_159 = eq(_T_158, UInt<1>(0h0))
when _T_159 :
node _T_160 = eq(is_aligned, UInt<1>(0h0))
when _T_160 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22
node _T_161 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_162 = asUInt(reset)
node _T_163 = eq(_T_162, UInt<1>(0h0))
when _T_163 :
node _T_164 = eq(_T_161, UInt<1>(0h0))
when _T_164 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23
assert(clock, _T_161, UInt<1>(0h1), "") : assert_23
node _T_165 = eq(io.in.a.bits.mask, mask)
node _T_166 = asUInt(reset)
node _T_167 = eq(_T_166, UInt<1>(0h0))
when _T_167 :
node _T_168 = eq(_T_165, UInt<1>(0h0))
when _T_168 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24
assert(clock, _T_165, UInt<1>(0h1), "") : assert_24
node _T_169 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_170 = asUInt(reset)
node _T_171 = eq(_T_170, UInt<1>(0h0))
when _T_171 :
node _T_172 = eq(_T_169, UInt<1>(0h0))
when _T_172 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25
assert(clock, _T_169, UInt<1>(0h1), "") : assert_25
node _T_173 = eq(io.in.a.bits.opcode, UInt<1>(0h0))
when _T_173 :
node _T_174 = eq(UInt<2>(0h2), io.in.a.bits.size)
node _T_175 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_176 = and(_T_174, _T_175)
node _T_177 = or(UInt<1>(0h0), _T_176)
node _T_178 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_179 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_180 = and(_T_178, _T_179)
node _T_181 = or(UInt<1>(0h0), _T_180)
node _T_182 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_183 = cvt(_T_182)
node _T_184 = and(_T_183, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_185 = asSInt(_T_184)
node _T_186 = eq(_T_185, asSInt(UInt<1>(0h0)))
node _T_187 = and(_T_181, _T_186)
node _T_188 = or(UInt<1>(0h0), _T_187)
node _T_189 = and(_T_177, _T_188)
node _T_190 = asUInt(reset)
node _T_191 = eq(_T_190, UInt<1>(0h0))
when _T_191 :
node _T_192 = eq(_T_189, UInt<1>(0h0))
when _T_192 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26
assert(clock, _T_189, UInt<1>(0h1), "") : assert_26
node _T_193 = asUInt(reset)
node _T_194 = eq(_T_193, UInt<1>(0h0))
when _T_194 :
node _T_195 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_195 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27
node _T_196 = asUInt(reset)
node _T_197 = eq(_T_196, UInt<1>(0h0))
when _T_197 :
node _T_198 = eq(is_aligned, UInt<1>(0h0))
when _T_198 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28
node _T_199 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_200 = asUInt(reset)
node _T_201 = eq(_T_200, UInt<1>(0h0))
when _T_201 :
node _T_202 = eq(_T_199, UInt<1>(0h0))
when _T_202 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29
assert(clock, _T_199, UInt<1>(0h1), "") : assert_29
node _T_203 = eq(io.in.a.bits.mask, mask)
node _T_204 = asUInt(reset)
node _T_205 = eq(_T_204, UInt<1>(0h0))
when _T_205 :
node _T_206 = eq(_T_203, UInt<1>(0h0))
when _T_206 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30
assert(clock, _T_203, UInt<1>(0h1), "") : assert_30
node _T_207 = eq(io.in.a.bits.opcode, UInt<1>(0h1))
when _T_207 :
node _T_208 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_209 = and(UInt<1>(0h0), _T_208)
node _T_210 = or(UInt<1>(0h0), _T_209)
node _T_211 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_212 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_213 = and(_T_211, _T_212)
node _T_214 = or(UInt<1>(0h0), _T_213)
node _T_215 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_216 = cvt(_T_215)
node _T_217 = and(_T_216, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_218 = asSInt(_T_217)
node _T_219 = eq(_T_218, asSInt(UInt<1>(0h0)))
node _T_220 = and(_T_214, _T_219)
node _T_221 = or(UInt<1>(0h0), _T_220)
node _T_222 = and(_T_210, _T_221)
node _T_223 = asUInt(reset)
node _T_224 = eq(_T_223, UInt<1>(0h0))
when _T_224 :
node _T_225 = eq(_T_222, UInt<1>(0h0))
when _T_225 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31
assert(clock, _T_222, UInt<1>(0h1), "") : assert_31
node _T_226 = asUInt(reset)
node _T_227 = eq(_T_226, UInt<1>(0h0))
when _T_227 :
node _T_228 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_228 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32
node _T_229 = asUInt(reset)
node _T_230 = eq(_T_229, UInt<1>(0h0))
when _T_230 :
node _T_231 = eq(is_aligned, UInt<1>(0h0))
when _T_231 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33
node _T_232 = eq(io.in.a.bits.param, UInt<1>(0h0))
node _T_233 = asUInt(reset)
node _T_234 = eq(_T_233, UInt<1>(0h0))
when _T_234 :
node _T_235 = eq(_T_232, UInt<1>(0h0))
when _T_235 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34
assert(clock, _T_232, UInt<1>(0h1), "") : assert_34
node _T_236 = not(mask)
node _T_237 = and(io.in.a.bits.mask, _T_236)
node _T_238 = eq(_T_237, UInt<1>(0h0))
node _T_239 = asUInt(reset)
node _T_240 = eq(_T_239, UInt<1>(0h0))
when _T_240 :
node _T_241 = eq(_T_238, UInt<1>(0h0))
when _T_241 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35
assert(clock, _T_238, UInt<1>(0h1), "") : assert_35
node _T_242 = eq(io.in.a.bits.opcode, UInt<2>(0h2))
when _T_242 :
node _T_243 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_244 = and(UInt<1>(0h0), _T_243)
node _T_245 = or(UInt<1>(0h0), _T_244)
node _T_246 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_247 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_248 = cvt(_T_247)
node _T_249 = and(_T_248, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_250 = asSInt(_T_249)
node _T_251 = eq(_T_250, asSInt(UInt<1>(0h0)))
node _T_252 = and(_T_246, _T_251)
node _T_253 = or(UInt<1>(0h0), _T_252)
node _T_254 = and(_T_245, _T_253)
node _T_255 = asUInt(reset)
node _T_256 = eq(_T_255, UInt<1>(0h0))
when _T_256 :
node _T_257 = eq(_T_254, UInt<1>(0h0))
when _T_257 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36
assert(clock, _T_254, UInt<1>(0h1), "") : assert_36
node _T_258 = asUInt(reset)
node _T_259 = eq(_T_258, UInt<1>(0h0))
when _T_259 :
node _T_260 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_260 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37
node _T_261 = asUInt(reset)
node _T_262 = eq(_T_261, UInt<1>(0h0))
when _T_262 :
node _T_263 = eq(is_aligned, UInt<1>(0h0))
when _T_263 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38
node _T_264 = leq(io.in.a.bits.param, UInt<3>(0h4))
node _T_265 = asUInt(reset)
node _T_266 = eq(_T_265, UInt<1>(0h0))
when _T_266 :
node _T_267 = eq(_T_264, UInt<1>(0h0))
when _T_267 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39
assert(clock, _T_264, UInt<1>(0h1), "") : assert_39
node _T_268 = eq(io.in.a.bits.mask, mask)
node _T_269 = asUInt(reset)
node _T_270 = eq(_T_269, UInt<1>(0h0))
when _T_270 :
node _T_271 = eq(_T_268, UInt<1>(0h0))
when _T_271 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40
assert(clock, _T_268, UInt<1>(0h1), "") : assert_40
node _T_272 = eq(io.in.a.bits.opcode, UInt<2>(0h3))
when _T_272 :
node _T_273 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_274 = and(UInt<1>(0h0), _T_273)
node _T_275 = or(UInt<1>(0h0), _T_274)
node _T_276 = or(UInt<1>(0h0), UInt<1>(0h0))
node _T_277 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_278 = cvt(_T_277)
node _T_279 = and(_T_278, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_280 = asSInt(_T_279)
node _T_281 = eq(_T_280, asSInt(UInt<1>(0h0)))
node _T_282 = and(_T_276, _T_281)
node _T_283 = or(UInt<1>(0h0), _T_282)
node _T_284 = and(_T_275, _T_283)
node _T_285 = asUInt(reset)
node _T_286 = eq(_T_285, UInt<1>(0h0))
when _T_286 :
node _T_287 = eq(_T_284, UInt<1>(0h0))
when _T_287 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41
assert(clock, _T_284, UInt<1>(0h1), "") : assert_41
node _T_288 = asUInt(reset)
node _T_289 = eq(_T_288, UInt<1>(0h0))
when _T_289 :
node _T_290 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_290 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42
node _T_291 = asUInt(reset)
node _T_292 = eq(_T_291, UInt<1>(0h0))
when _T_292 :
node _T_293 = eq(is_aligned, UInt<1>(0h0))
when _T_293 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43
node _T_294 = leq(io.in.a.bits.param, UInt<3>(0h3))
node _T_295 = asUInt(reset)
node _T_296 = eq(_T_295, UInt<1>(0h0))
when _T_296 :
node _T_297 = eq(_T_294, UInt<1>(0h0))
when _T_297 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44
assert(clock, _T_294, UInt<1>(0h1), "") : assert_44
node _T_298 = eq(io.in.a.bits.mask, mask)
node _T_299 = asUInt(reset)
node _T_300 = eq(_T_299, UInt<1>(0h0))
when _T_300 :
node _T_301 = eq(_T_298, UInt<1>(0h0))
when _T_301 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45
assert(clock, _T_298, UInt<1>(0h1), "") : assert_45
node _T_302 = eq(io.in.a.bits.opcode, UInt<3>(0h5))
when _T_302 :
node _T_303 = eq(io.in.a.bits.source, UInt<1>(0h0))
node _T_304 = and(UInt<1>(0h0), _T_303)
node _T_305 = or(UInt<1>(0h0), _T_304)
node _T_306 = leq(UInt<1>(0h0), io.in.a.bits.size)
node _T_307 = leq(io.in.a.bits.size, UInt<2>(0h2))
node _T_308 = and(_T_306, _T_307)
node _T_309 = or(UInt<1>(0h0), _T_308)
node _T_310 = xor(io.in.a.bits.address, UInt<1>(0h0))
node _T_311 = cvt(_T_310)
node _T_312 = and(_T_311, asSInt(UInt<129>(0h100000000000000000000000000000000)))
node _T_313 = asSInt(_T_312)
node _T_314 = eq(_T_313, asSInt(UInt<1>(0h0)))
node _T_315 = and(_T_309, _T_314)
node _T_316 = or(UInt<1>(0h0), _T_315)
node _T_317 = and(_T_305, _T_316)
node _T_318 = asUInt(reset)
node _T_319 = eq(_T_318, UInt<1>(0h0))
when _T_319 :
node _T_320 = eq(_T_317, UInt<1>(0h0))
when _T_320 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46
assert(clock, _T_317, UInt<1>(0h1), "") : assert_46
node _T_321 = asUInt(reset)
node _T_322 = eq(_T_321, UInt<1>(0h0))
when _T_322 :
node _T_323 = eq(_source_ok_WIRE[0], UInt<1>(0h0))
when _T_323 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47
assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47
node _T_324 = asUInt(reset)
node _T_325 = eq(_T_324, UInt<1>(0h0))
when _T_325 :
node _T_326 = eq(is_aligned, UInt<1>(0h0))
when _T_326 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48
assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48
node _T_327 = leq(io.in.a.bits.param, UInt<1>(0h1))
node _T_328 = asUInt(reset)
node _T_329 = eq(_T_328, UInt<1>(0h0))
when _T_329 :
node _T_330 = eq(_T_327, UInt<1>(0h0))
when _T_330 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49
assert(clock, _T_327, UInt<1>(0h1), "") : assert_49
node _T_331 = eq(io.in.a.bits.mask, mask)
node _T_332 = asUInt(reset)
node _T_333 = eq(_T_332, UInt<1>(0h0))
when _T_333 :
node _T_334 = eq(_T_331, UInt<1>(0h0))
when _T_334 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50
assert(clock, _T_331, UInt<1>(0h1), "") : assert_50
node _T_335 = eq(io.in.a.bits.corrupt, UInt<1>(0h0))
node _T_336 = asUInt(reset)
node _T_337 = eq(_T_336, UInt<1>(0h0))
when _T_337 :
node _T_338 = eq(_T_335, UInt<1>(0h0))
when _T_338 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51
assert(clock, _T_335, UInt<1>(0h1), "") : assert_51
when io.in.d.valid :
node _T_339 = leq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_340 = asUInt(reset)
node _T_341 = eq(_T_340, UInt<1>(0h0))
when _T_341 :
node _T_342 = eq(_T_339, UInt<1>(0h0))
when _T_342 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52
assert(clock, _T_339, UInt<1>(0h1), "") : assert_52
node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0))
wire _source_ok_WIRE_1 : UInt<1>[1]
connect _source_ok_WIRE_1[0], _source_ok_T_1
node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h1))
node _T_343 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
when _T_343 :
node _T_344 = asUInt(reset)
node _T_345 = eq(_T_344, UInt<1>(0h0))
when _T_345 :
node _T_346 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_346 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53
node _T_347 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_348 = asUInt(reset)
node _T_349 = eq(_T_348, UInt<1>(0h0))
when _T_349 :
node _T_350 = eq(_T_347, UInt<1>(0h0))
when _T_350 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54
assert(clock, _T_347, UInt<1>(0h1), "") : assert_54
node _T_351 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_352 = asUInt(reset)
node _T_353 = eq(_T_352, UInt<1>(0h0))
when _T_353 :
node _T_354 = eq(_T_351, UInt<1>(0h0))
when _T_354 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55
assert(clock, _T_351, UInt<1>(0h1), "") : assert_55
node _T_355 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_356 = asUInt(reset)
node _T_357 = eq(_T_356, UInt<1>(0h0))
when _T_357 :
node _T_358 = eq(_T_355, UInt<1>(0h0))
when _T_358 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56
assert(clock, _T_355, UInt<1>(0h1), "") : assert_56
node _T_359 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_360 = asUInt(reset)
node _T_361 = eq(_T_360, UInt<1>(0h0))
when _T_361 :
node _T_362 = eq(_T_359, UInt<1>(0h0))
when _T_362 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57
assert(clock, _T_359, UInt<1>(0h1), "") : assert_57
node _T_363 = eq(io.in.d.bits.opcode, UInt<3>(0h4))
when _T_363 :
node _T_364 = asUInt(reset)
node _T_365 = eq(_T_364, UInt<1>(0h0))
when _T_365 :
node _T_366 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_366 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58
node _T_367 = asUInt(reset)
node _T_368 = eq(_T_367, UInt<1>(0h0))
when _T_368 :
node _T_369 = eq(sink_ok, UInt<1>(0h0))
when _T_369 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59
node _T_370 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_371 = asUInt(reset)
node _T_372 = eq(_T_371, UInt<1>(0h0))
when _T_372 :
node _T_373 = eq(_T_370, UInt<1>(0h0))
when _T_373 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60
assert(clock, _T_370, UInt<1>(0h1), "") : assert_60
node _T_374 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_375 = asUInt(reset)
node _T_376 = eq(_T_375, UInt<1>(0h0))
when _T_376 :
node _T_377 = eq(_T_374, UInt<1>(0h0))
when _T_377 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61
assert(clock, _T_374, UInt<1>(0h1), "") : assert_61
node _T_378 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_379 = asUInt(reset)
node _T_380 = eq(_T_379, UInt<1>(0h0))
when _T_380 :
node _T_381 = eq(_T_378, UInt<1>(0h0))
when _T_381 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62
assert(clock, _T_378, UInt<1>(0h1), "") : assert_62
node _T_382 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_383 = asUInt(reset)
node _T_384 = eq(_T_383, UInt<1>(0h0))
when _T_384 :
node _T_385 = eq(_T_382, UInt<1>(0h0))
when _T_385 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63
assert(clock, _T_382, UInt<1>(0h1), "") : assert_63
node _T_386 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_387 = or(UInt<1>(0h1), _T_386)
node _T_388 = asUInt(reset)
node _T_389 = eq(_T_388, UInt<1>(0h0))
when _T_389 :
node _T_390 = eq(_T_387, UInt<1>(0h0))
when _T_390 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64
assert(clock, _T_387, UInt<1>(0h1), "") : assert_64
node _T_391 = eq(io.in.d.bits.opcode, UInt<3>(0h5))
when _T_391 :
node _T_392 = asUInt(reset)
node _T_393 = eq(_T_392, UInt<1>(0h0))
when _T_393 :
node _T_394 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_394 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65
node _T_395 = asUInt(reset)
node _T_396 = eq(_T_395, UInt<1>(0h0))
when _T_396 :
node _T_397 = eq(sink_ok, UInt<1>(0h0))
when _T_397 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66
assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66
node _T_398 = geq(io.in.d.bits.size, UInt<2>(0h2))
node _T_399 = asUInt(reset)
node _T_400 = eq(_T_399, UInt<1>(0h0))
when _T_400 :
node _T_401 = eq(_T_398, UInt<1>(0h0))
when _T_401 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67
assert(clock, _T_398, UInt<1>(0h1), "") : assert_67
node _T_402 = leq(io.in.d.bits.param, UInt<2>(0h2))
node _T_403 = asUInt(reset)
node _T_404 = eq(_T_403, UInt<1>(0h0))
when _T_404 :
node _T_405 = eq(_T_402, UInt<1>(0h0))
when _T_405 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68
assert(clock, _T_402, UInt<1>(0h1), "") : assert_68
node _T_406 = neq(io.in.d.bits.param, UInt<2>(0h2))
node _T_407 = asUInt(reset)
node _T_408 = eq(_T_407, UInt<1>(0h0))
when _T_408 :
node _T_409 = eq(_T_406, UInt<1>(0h0))
when _T_409 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69
assert(clock, _T_406, UInt<1>(0h1), "") : assert_69
node _T_410 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_411 = or(_T_410, io.in.d.bits.corrupt)
node _T_412 = asUInt(reset)
node _T_413 = eq(_T_412, UInt<1>(0h0))
when _T_413 :
node _T_414 = eq(_T_411, UInt<1>(0h0))
when _T_414 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70
assert(clock, _T_411, UInt<1>(0h1), "") : assert_70
node _T_415 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_416 = or(UInt<1>(0h1), _T_415)
node _T_417 = asUInt(reset)
node _T_418 = eq(_T_417, UInt<1>(0h0))
when _T_418 :
node _T_419 = eq(_T_416, UInt<1>(0h0))
when _T_419 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71
assert(clock, _T_416, UInt<1>(0h1), "") : assert_71
node _T_420 = eq(io.in.d.bits.opcode, UInt<1>(0h0))
when _T_420 :
node _T_421 = asUInt(reset)
node _T_422 = eq(_T_421, UInt<1>(0h0))
when _T_422 :
node _T_423 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_423 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72
node _T_424 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_425 = asUInt(reset)
node _T_426 = eq(_T_425, UInt<1>(0h0))
when _T_426 :
node _T_427 = eq(_T_424, UInt<1>(0h0))
when _T_427 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73
assert(clock, _T_424, UInt<1>(0h1), "") : assert_73
node _T_428 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_429 = asUInt(reset)
node _T_430 = eq(_T_429, UInt<1>(0h0))
when _T_430 :
node _T_431 = eq(_T_428, UInt<1>(0h0))
when _T_431 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74
assert(clock, _T_428, UInt<1>(0h1), "") : assert_74
node _T_432 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_433 = or(UInt<1>(0h1), _T_432)
node _T_434 = asUInt(reset)
node _T_435 = eq(_T_434, UInt<1>(0h0))
when _T_435 :
node _T_436 = eq(_T_433, UInt<1>(0h0))
when _T_436 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75
assert(clock, _T_433, UInt<1>(0h1), "") : assert_75
node _T_437 = eq(io.in.d.bits.opcode, UInt<1>(0h1))
when _T_437 :
node _T_438 = asUInt(reset)
node _T_439 = eq(_T_438, UInt<1>(0h0))
when _T_439 :
node _T_440 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_440 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76
node _T_441 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_442 = asUInt(reset)
node _T_443 = eq(_T_442, UInt<1>(0h0))
when _T_443 :
node _T_444 = eq(_T_441, UInt<1>(0h0))
when _T_444 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77
assert(clock, _T_441, UInt<1>(0h1), "") : assert_77
node _T_445 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_446 = or(_T_445, io.in.d.bits.corrupt)
node _T_447 = asUInt(reset)
node _T_448 = eq(_T_447, UInt<1>(0h0))
when _T_448 :
node _T_449 = eq(_T_446, UInt<1>(0h0))
when _T_449 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78
assert(clock, _T_446, UInt<1>(0h1), "") : assert_78
node _T_450 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_451 = or(UInt<1>(0h1), _T_450)
node _T_452 = asUInt(reset)
node _T_453 = eq(_T_452, UInt<1>(0h0))
when _T_453 :
node _T_454 = eq(_T_451, UInt<1>(0h0))
when _T_454 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79
assert(clock, _T_451, UInt<1>(0h1), "") : assert_79
node _T_455 = eq(io.in.d.bits.opcode, UInt<2>(0h2))
when _T_455 :
node _T_456 = asUInt(reset)
node _T_457 = eq(_T_456, UInt<1>(0h0))
when _T_457 :
node _T_458 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0))
when _T_458 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80
assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80
node _T_459 = eq(io.in.d.bits.param, UInt<1>(0h0))
node _T_460 = asUInt(reset)
node _T_461 = eq(_T_460, UInt<1>(0h0))
when _T_461 :
node _T_462 = eq(_T_459, UInt<1>(0h0))
when _T_462 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81
assert(clock, _T_459, UInt<1>(0h1), "") : assert_81
node _T_463 = eq(io.in.d.bits.corrupt, UInt<1>(0h0))
node _T_464 = asUInt(reset)
node _T_465 = eq(_T_464, UInt<1>(0h0))
when _T_465 :
node _T_466 = eq(_T_463, UInt<1>(0h0))
when _T_466 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82
assert(clock, _T_463, UInt<1>(0h1), "") : assert_82
node _T_467 = eq(io.in.d.bits.denied, UInt<1>(0h0))
node _T_468 = or(UInt<1>(0h1), _T_467)
node _T_469 = asUInt(reset)
node _T_470 = eq(_T_469, UInt<1>(0h0))
when _T_470 :
node _T_471 = eq(_T_468, UInt<1>(0h0))
when _T_471 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83
assert(clock, _T_468, UInt<1>(0h1), "") : assert_83
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<32>(0h0)
connect _WIRE.bits.mask, UInt<4>(0h0)
connect _WIRE.bits.address, UInt<128>(0h0)
connect _WIRE.bits.source, UInt<1>(0h0)
connect _WIRE.bits.size, UInt<2>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
node _T_472 = eq(_WIRE_1.valid, UInt<1>(0h0))
node _T_473 = asUInt(reset)
node _T_474 = eq(_T_473, UInt<1>(0h0))
when _T_474 :
node _T_475 = eq(_T_472, UInt<1>(0h0))
when _T_475 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84
assert(clock, _T_472, UInt<1>(0h1), "") : assert_84
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<32>(0h0)
connect _WIRE_2.bits.address, UInt<128>(0h0)
connect _WIRE_2.bits.source, UInt<1>(0h0)
connect _WIRE_2.bits.size, UInt<2>(0h0)
connect _WIRE_2.bits.param, UInt<3>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
node _T_476 = eq(_WIRE_3.valid, UInt<1>(0h0))
node _T_477 = asUInt(reset)
node _T_478 = eq(_T_477, UInt<1>(0h0))
when _T_478 :
node _T_479 = eq(_T_476, UInt<1>(0h0))
when _T_479 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85
assert(clock, _T_476, UInt<1>(0h1), "") : assert_85
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_4.bits.sink, UInt<1>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
node _T_480 = eq(_WIRE_5.valid, UInt<1>(0h0))
node _T_481 = asUInt(reset)
node _T_482 = eq(_T_481, UInt<1>(0h0))
when _T_482 :
node _T_483 = eq(_T_480, UInt<1>(0h0))
when _T_483 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86
assert(clock, _T_480, UInt<1>(0h1), "") : assert_86
node _a_first_T = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0)
node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1)
node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2)
node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0))
node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0))
regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1))
node a_first_counter1 = tail(_a_first_counter1_T, 1)
node a_first = eq(a_first_counter, UInt<1>(0h0))
node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1))
node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0))
node a_first_last = or(_a_first_last_T, _a_first_last_T_1)
node a_first_done = and(a_first_last, _a_first_T)
node _a_first_count_T = not(a_first_counter1)
node a_first_count = and(a_first_beats1, _a_first_count_T)
when _a_first_T :
node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1)
connect a_first_counter, _a_first_counter_T
reg opcode : UInt, clock
reg param : UInt, clock
reg size : UInt, clock
reg source : UInt, clock
reg address : UInt, clock
node _T_484 = eq(a_first, UInt<1>(0h0))
node _T_485 = and(io.in.a.valid, _T_484)
when _T_485 :
node _T_486 = eq(io.in.a.bits.opcode, opcode)
node _T_487 = asUInt(reset)
node _T_488 = eq(_T_487, UInt<1>(0h0))
when _T_488 :
node _T_489 = eq(_T_486, UInt<1>(0h0))
when _T_489 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87
assert(clock, _T_486, UInt<1>(0h1), "") : assert_87
node _T_490 = eq(io.in.a.bits.param, param)
node _T_491 = asUInt(reset)
node _T_492 = eq(_T_491, UInt<1>(0h0))
when _T_492 :
node _T_493 = eq(_T_490, UInt<1>(0h0))
when _T_493 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88
assert(clock, _T_490, UInt<1>(0h1), "") : assert_88
node _T_494 = eq(io.in.a.bits.size, size)
node _T_495 = asUInt(reset)
node _T_496 = eq(_T_495, UInt<1>(0h0))
when _T_496 :
node _T_497 = eq(_T_494, UInt<1>(0h0))
when _T_497 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89
assert(clock, _T_494, UInt<1>(0h1), "") : assert_89
node _T_498 = eq(io.in.a.bits.source, source)
node _T_499 = asUInt(reset)
node _T_500 = eq(_T_499, UInt<1>(0h0))
when _T_500 :
node _T_501 = eq(_T_498, UInt<1>(0h0))
when _T_501 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90
assert(clock, _T_498, UInt<1>(0h1), "") : assert_90
node _T_502 = eq(io.in.a.bits.address, address)
node _T_503 = asUInt(reset)
node _T_504 = eq(_T_503, UInt<1>(0h0))
when _T_504 :
node _T_505 = eq(_T_502, UInt<1>(0h0))
when _T_505 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91
assert(clock, _T_502, UInt<1>(0h1), "") : assert_91
node _T_506 = and(io.in.a.ready, io.in.a.valid)
node _T_507 = and(_T_506, a_first)
when _T_507 :
connect opcode, io.in.a.bits.opcode
connect param, io.in.a.bits.param
connect size, io.in.a.bits.size
connect source, io.in.a.bits.source
connect address, io.in.a.bits.address
node _d_first_T = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0)
node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1)
node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2)
node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0))
regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1))
node d_first_counter1 = tail(_d_first_counter1_T, 1)
node d_first = eq(d_first_counter, UInt<1>(0h0))
node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1))
node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0))
node d_first_last = or(_d_first_last_T, _d_first_last_T_1)
node d_first_done = and(d_first_last, _d_first_T)
node _d_first_count_T = not(d_first_counter1)
node d_first_count = and(d_first_beats1, _d_first_count_T)
when _d_first_T :
node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1)
connect d_first_counter, _d_first_counter_T
reg opcode_1 : UInt, clock
reg param_1 : UInt, clock
reg size_1 : UInt, clock
reg source_1 : UInt, clock
reg sink : UInt, clock
reg denied : UInt<1>, clock
node _T_508 = eq(d_first, UInt<1>(0h0))
node _T_509 = and(io.in.d.valid, _T_508)
when _T_509 :
node _T_510 = eq(io.in.d.bits.opcode, opcode_1)
node _T_511 = asUInt(reset)
node _T_512 = eq(_T_511, UInt<1>(0h0))
when _T_512 :
node _T_513 = eq(_T_510, UInt<1>(0h0))
when _T_513 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92
assert(clock, _T_510, UInt<1>(0h1), "") : assert_92
node _T_514 = eq(io.in.d.bits.param, param_1)
node _T_515 = asUInt(reset)
node _T_516 = eq(_T_515, UInt<1>(0h0))
when _T_516 :
node _T_517 = eq(_T_514, UInt<1>(0h0))
when _T_517 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93
assert(clock, _T_514, UInt<1>(0h1), "") : assert_93
node _T_518 = eq(io.in.d.bits.size, size_1)
node _T_519 = asUInt(reset)
node _T_520 = eq(_T_519, UInt<1>(0h0))
when _T_520 :
node _T_521 = eq(_T_518, UInt<1>(0h0))
when _T_521 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94
assert(clock, _T_518, UInt<1>(0h1), "") : assert_94
node _T_522 = eq(io.in.d.bits.source, source_1)
node _T_523 = asUInt(reset)
node _T_524 = eq(_T_523, UInt<1>(0h0))
when _T_524 :
node _T_525 = eq(_T_522, UInt<1>(0h0))
when _T_525 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95
assert(clock, _T_522, UInt<1>(0h1), "") : assert_95
node _T_526 = eq(io.in.d.bits.sink, sink)
node _T_527 = asUInt(reset)
node _T_528 = eq(_T_527, UInt<1>(0h0))
when _T_528 :
node _T_529 = eq(_T_526, UInt<1>(0h0))
when _T_529 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96
assert(clock, _T_526, UInt<1>(0h1), "") : assert_96
node _T_530 = eq(io.in.d.bits.denied, denied)
node _T_531 = asUInt(reset)
node _T_532 = eq(_T_531, UInt<1>(0h0))
when _T_532 :
node _T_533 = eq(_T_530, UInt<1>(0h0))
when _T_533 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97
assert(clock, _T_530, UInt<1>(0h1), "") : assert_97
node _T_534 = and(io.in.d.ready, io.in.d.valid)
node _T_535 = and(_T_534, d_first)
when _T_535 :
connect opcode_1, io.in.d.bits.opcode
connect param_1, io.in.d.bits.param
connect size_1, io.in.d.bits.size
connect source_1, io.in.d.bits.source
connect sink, io.in.d.bits.sink
connect denied, io.in.d.bits.denied
regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0)
node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid)
node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size)
node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0)
node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4)
node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2)
node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2)
node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0))
node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0))
regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1))
node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1)
node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0))
node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1))
node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0))
node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3)
node a_first_done_1 = and(a_first_last_1, _a_first_T_1)
node _a_first_count_T_1 = not(a_first_counter1_1)
node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1)
when _a_first_T_1 :
node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1)
connect a_first_counter_1, _a_first_counter_T_1
node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0)
node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4)
node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2)
node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0))
regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1))
node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1)
node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0))
node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1))
node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0))
node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3)
node d_first_done_1 = and(d_first_last_1, _d_first_T_1)
node _d_first_count_T_1 = not(d_first_counter1_1)
node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1)
when _d_first_T_1 :
node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1)
connect d_first_counter_1, _d_first_counter_T_1
wire a_set : UInt<1>
connect a_set, UInt<1>(0h0)
wire a_set_wo_ready : UInt<1>
connect a_set_wo_ready, UInt<1>(0h0)
wire a_opcodes_set : UInt<4>
connect a_opcodes_set, UInt<4>(0h0)
wire a_sizes_set : UInt<4>
connect a_sizes_set, UInt<4>(0h0)
wire a_opcode_lookup : UInt<3>
connect a_opcode_lookup, UInt<3>(0h0)
node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T)
node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2)
node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1))
node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1)
node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5)
node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1))
connect a_opcode_lookup, _a_opcode_lookup_T_7
wire a_size_lookup : UInt<4>
connect a_size_lookup, UInt<4>(0h0)
node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T)
node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2)
node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1))
node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1)
node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5)
node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1))
connect a_size_lookup, _a_size_lookup_T_7
wire responseMap : UInt<3>[8]
connect responseMap[0], UInt<1>(0h0)
connect responseMap[1], UInt<1>(0h0)
connect responseMap[2], UInt<1>(0h1)
connect responseMap[3], UInt<1>(0h1)
connect responseMap[4], UInt<1>(0h1)
connect responseMap[5], UInt<2>(0h2)
connect responseMap[6], UInt<3>(0h4)
connect responseMap[7], UInt<3>(0h4)
wire responseMapSecondOption : UInt<3>[8]
connect responseMapSecondOption[0], UInt<1>(0h0)
connect responseMapSecondOption[1], UInt<1>(0h0)
connect responseMapSecondOption[2], UInt<1>(0h1)
connect responseMapSecondOption[3], UInt<1>(0h1)
connect responseMapSecondOption[4], UInt<1>(0h1)
connect responseMapSecondOption[5], UInt<2>(0h2)
connect responseMapSecondOption[6], UInt<3>(0h5)
connect responseMapSecondOption[7], UInt<3>(0h4)
wire a_opcodes_set_interm : UInt<4>
connect a_opcodes_set_interm, UInt<4>(0h0)
wire a_sizes_set_interm : UInt<3>
connect a_sizes_set_interm, UInt<3>(0h0)
node _T_536 = and(io.in.a.valid, a_first_1)
node _T_537 = and(_T_536, UInt<1>(0h1))
when _T_537 :
node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set_wo_ready, _a_set_wo_ready_T
node _T_538 = and(io.in.a.ready, io.in.a.valid)
node _T_539 = and(_T_538, a_first_1)
node _T_540 = and(_T_539, UInt<1>(0h1))
when _T_540 :
node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source)
connect a_set, _a_set_T
node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1))
node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1))
connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1
node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1))
node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1))
connect a_sizes_set_interm, _a_sizes_set_interm_T_1
node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T)
connect a_opcodes_set, _a_opcodes_set_T_1
node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2))
node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T)
connect a_sizes_set, _a_sizes_set_T_1
node _T_541 = dshr(inflight, io.in.a.bits.source)
node _T_542 = bits(_T_541, 0, 0)
node _T_543 = eq(_T_542, UInt<1>(0h0))
node _T_544 = asUInt(reset)
node _T_545 = eq(_T_544, UInt<1>(0h0))
when _T_545 :
node _T_546 = eq(_T_543, UInt<1>(0h0))
when _T_546 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98
assert(clock, _T_543, UInt<1>(0h1), "") : assert_98
wire d_clr : UInt<1>
connect d_clr, UInt<1>(0h0)
wire d_clr_wo_ready : UInt<1>
connect d_clr_wo_ready, UInt<1>(0h0)
wire d_opcodes_clr : UInt<4>
connect d_opcodes_clr, UInt<4>(0h0)
wire d_sizes_clr : UInt<4>
connect d_sizes_clr, UInt<4>(0h0)
node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_547 = and(io.in.d.valid, d_first_1)
node _T_548 = and(_T_547, UInt<1>(0h1))
node _T_549 = eq(d_release_ack, UInt<1>(0h0))
node _T_550 = and(_T_548, _T_549)
when _T_550 :
node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready, _d_clr_wo_ready_T
node _T_551 = and(io.in.d.ready, io.in.d.valid)
node _T_552 = and(_T_551, d_first_1)
node _T_553 = and(_T_552, UInt<1>(0h1))
node _T_554 = eq(d_release_ack, UInt<1>(0h0))
node _T_555 = and(_T_553, _T_554)
when _T_555 :
node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr, _d_clr_T
node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T)
node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1))
node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1)
node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4)
connect d_opcodes_clr, _d_opcodes_clr_T_5
node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T)
node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1))
node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1)
node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4)
connect d_sizes_clr, _d_sizes_clr_T_5
node _T_556 = and(io.in.d.valid, d_first_1)
node _T_557 = and(_T_556, UInt<1>(0h1))
node _T_558 = eq(d_release_ack, UInt<1>(0h0))
node _T_559 = and(_T_557, _T_558)
when _T_559 :
node _same_cycle_resp_T = and(io.in.a.valid, a_first_1)
node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1))
node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source)
node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2)
node _T_560 = dshr(inflight, io.in.d.bits.source)
node _T_561 = bits(_T_560, 0, 0)
node _T_562 = or(_T_561, same_cycle_resp)
node _T_563 = asUInt(reset)
node _T_564 = eq(_T_563, UInt<1>(0h0))
when _T_564 :
node _T_565 = eq(_T_562, UInt<1>(0h0))
when _T_565 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99
assert(clock, _T_562, UInt<1>(0h1), "") : assert_99
when same_cycle_resp :
node _T_566 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode])
node _T_567 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode])
node _T_568 = or(_T_566, _T_567)
node _T_569 = asUInt(reset)
node _T_570 = eq(_T_569, UInt<1>(0h0))
when _T_570 :
node _T_571 = eq(_T_568, UInt<1>(0h0))
when _T_571 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100
assert(clock, _T_568, UInt<1>(0h1), "") : assert_100
node _T_572 = eq(io.in.a.bits.size, io.in.d.bits.size)
node _T_573 = asUInt(reset)
node _T_574 = eq(_T_573, UInt<1>(0h0))
when _T_574 :
node _T_575 = eq(_T_572, UInt<1>(0h0))
when _T_575 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101
assert(clock, _T_572, UInt<1>(0h1), "") : assert_101
else :
node _T_576 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup])
node _T_577 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup])
node _T_578 = or(_T_576, _T_577)
node _T_579 = asUInt(reset)
node _T_580 = eq(_T_579, UInt<1>(0h0))
when _T_580 :
node _T_581 = eq(_T_578, UInt<1>(0h0))
when _T_581 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102
assert(clock, _T_578, UInt<1>(0h1), "") : assert_102
node _T_582 = eq(io.in.d.bits.size, a_size_lookup)
node _T_583 = asUInt(reset)
node _T_584 = eq(_T_583, UInt<1>(0h0))
when _T_584 :
node _T_585 = eq(_T_582, UInt<1>(0h0))
when _T_585 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103
assert(clock, _T_582, UInt<1>(0h1), "") : assert_103
node _T_586 = and(io.in.d.valid, d_first_1)
node _T_587 = and(_T_586, a_first_1)
node _T_588 = and(_T_587, io.in.a.valid)
node _T_589 = eq(io.in.a.bits.source, io.in.d.bits.source)
node _T_590 = and(_T_588, _T_589)
node _T_591 = eq(d_release_ack, UInt<1>(0h0))
node _T_592 = and(_T_590, _T_591)
when _T_592 :
node _T_593 = eq(io.in.d.ready, UInt<1>(0h0))
node _T_594 = or(_T_593, io.in.a.ready)
node _T_595 = asUInt(reset)
node _T_596 = eq(_T_595, UInt<1>(0h0))
when _T_596 :
node _T_597 = eq(_T_594, UInt<1>(0h0))
when _T_597 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104
assert(clock, _T_594, UInt<1>(0h1), "") : assert_104
node _inflight_T = or(inflight, a_set)
node _inflight_T_1 = not(d_clr)
node _inflight_T_2 = and(_inflight_T, _inflight_T_1)
connect inflight, _inflight_T_2
node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set)
node _inflight_opcodes_T_1 = not(d_opcodes_clr)
node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1)
connect inflight_opcodes, _inflight_opcodes_T_2
node _inflight_sizes_T = or(inflight_sizes, a_sizes_set)
node _inflight_sizes_T_1 = not(d_sizes_clr)
node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1)
connect inflight_sizes, _inflight_sizes_T_2
regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader of plusarg_reader_107
node _T_598 = orr(inflight)
node _T_599 = eq(_T_598, UInt<1>(0h0))
node _T_600 = eq(plusarg_reader.out, UInt<1>(0h0))
node _T_601 = or(_T_599, _T_600)
node _T_602 = lt(watchdog, plusarg_reader.out)
node _T_603 = or(_T_601, _T_602)
node _T_604 = asUInt(reset)
node _T_605 = eq(_T_604, UInt<1>(0h0))
when _T_605 :
node _T_606 = eq(_T_603, UInt<1>(0h0))
when _T_606 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105
assert(clock, _T_603, UInt<1>(0h1), "") : assert_105
node _watchdog_T = add(watchdog, UInt<1>(0h1))
node _watchdog_T_1 = tail(_watchdog_T, 1)
connect watchdog, _watchdog_T_1
node _T_607 = and(io.in.a.ready, io.in.a.valid)
node _T_608 = and(io.in.d.ready, io.in.d.valid)
node _T_609 = or(_T_607, _T_608)
when _T_609 :
connect watchdog, UInt<1>(0h0)
regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0)
regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0)
wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE.bits.data, UInt<32>(0h0)
connect _c_first_WIRE.bits.address, UInt<128>(0h0)
connect _c_first_WIRE.bits.source, UInt<1>(0h0)
connect _c_first_WIRE.bits.size, UInt<2>(0h0)
connect _c_first_WIRE.bits.param, UInt<3>(0h0)
connect _c_first_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE.valid, UInt<1>(0h0)
connect _c_first_WIRE.ready, UInt<1>(0h0)
wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_1.bits, _c_first_WIRE.bits
connect _c_first_WIRE_1.valid, _c_first_WIRE.valid
connect _c_first_WIRE_1.ready, _c_first_WIRE.ready
wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_first_WIRE_2.bits.address, UInt<128>(0h0)
connect _c_first_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_first_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_first_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_first_WIRE_2.valid, UInt<1>(0h0)
connect _c_first_WIRE_2.ready, UInt<1>(0h0)
wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits
connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid
connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready
node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid)
node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size)
node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0)
node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1)
node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2)
node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0)
node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0))
regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0)
node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1))
node c_first_counter1 = tail(_c_first_counter1_T, 1)
node c_first = eq(c_first_counter, UInt<1>(0h0))
node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1))
node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0))
node c_first_last = or(_c_first_last_T, _c_first_last_T_1)
node c_first_done = and(c_first_last, _c_first_T)
node _c_first_count_T = not(c_first_counter1)
node c_first_count = and(c_first_beats1, _c_first_count_T)
when _c_first_T :
node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1)
connect c_first_counter, _c_first_counter_T
node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid)
node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size)
node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0)
node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7)
node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2)
node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0)
node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0))
regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1))
node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1)
node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0))
node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1))
node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0))
node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5)
node d_first_done_2 = and(d_first_last_2, _d_first_T_2)
node _d_first_count_T_2 = not(d_first_counter1_2)
node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2)
when _d_first_T_2 :
node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2)
connect d_first_counter_2, _d_first_counter_T_2
wire c_set : UInt<1>
connect c_set, UInt<1>(0h0)
wire c_set_wo_ready : UInt<1>
connect c_set_wo_ready, UInt<1>(0h0)
wire c_opcodes_set : UInt<4>
connect c_opcodes_set, UInt<4>(0h0)
wire c_sizes_set : UInt<4>
connect c_sizes_set, UInt<4>(0h0)
wire c_opcode_lookup : UInt<4>
connect c_opcode_lookup, UInt<4>(0h0)
wire c_size_lookup : UInt<4>
connect c_size_lookup, UInt<4>(0h0)
node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T)
node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2)
node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1))
node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1)
node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5)
node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1))
connect c_opcode_lookup, _c_opcode_lookup_T_7
node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T)
node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2)
node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1))
node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1)
node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5)
node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1))
connect c_size_lookup, _c_size_lookup_T_7
wire c_opcodes_set_interm : UInt<4>
connect c_opcodes_set_interm, UInt<4>(0h0)
wire c_sizes_set_interm : UInt<3>
connect c_sizes_set_interm, UInt<3>(0h0)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<32>(0h0)
connect _WIRE_6.bits.address, UInt<128>(0h0)
connect _WIRE_6.bits.source, UInt<1>(0h0)
connect _WIRE_6.bits.size, UInt<2>(0h0)
connect _WIRE_6.bits.param, UInt<3>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
node _T_610 = and(_WIRE_7.valid, c_first)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<32>(0h0)
connect _WIRE_8.bits.address, UInt<128>(0h0)
connect _WIRE_8.bits.source, UInt<1>(0h0)
connect _WIRE_8.bits.size, UInt<2>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
node _T_611 = bits(_WIRE_9.bits.opcode, 2, 2)
node _T_612 = bits(_WIRE_9.bits.opcode, 1, 1)
node _T_613 = and(_T_611, _T_612)
node _T_614 = and(_T_610, _T_613)
when _T_614 :
wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_wo_ready_WIRE.bits.address, UInt<128>(0h0)
connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0)
connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0)
wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits
connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid
connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready
node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source)
connect c_set_wo_ready, _c_set_wo_ready_T
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<32>(0h0)
connect _WIRE_10.bits.address, UInt<128>(0h0)
connect _WIRE_10.bits.source, UInt<1>(0h0)
connect _WIRE_10.bits.size, UInt<2>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
node _T_615 = and(_WIRE_11.ready, _WIRE_11.valid)
node _T_616 = and(_T_615, c_first)
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<32>(0h0)
connect _WIRE_12.bits.address, UInt<128>(0h0)
connect _WIRE_12.bits.source, UInt<1>(0h0)
connect _WIRE_12.bits.size, UInt<2>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
node _T_617 = bits(_WIRE_13.bits.opcode, 2, 2)
node _T_618 = bits(_WIRE_13.bits.opcode, 1, 1)
node _T_619 = and(_T_617, _T_618)
node _T_620 = and(_T_616, _T_619)
when _T_620 :
wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_set_WIRE.bits.address, UInt<128>(0h0)
connect _c_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_set_WIRE.valid, UInt<1>(0h0)
connect _c_set_WIRE.ready, UInt<1>(0h0)
wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_set_WIRE_1.bits, _c_set_WIRE.bits
connect _c_set_WIRE_1.valid, _c_set_WIRE.valid
connect _c_set_WIRE_1.ready, _c_set_WIRE.ready
node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source)
connect c_set, _c_set_T
wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.address, UInt<128>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits
connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid
connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready
node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1))
node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1))
connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1
wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_interm_WIRE.bits.address, UInt<128>(0h0)
connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits
connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid
connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready
node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1))
node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1))
connect c_sizes_set_interm, _c_sizes_set_interm_T_1
wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_opcodes_set_WIRE.bits.address, UInt<128>(0h0)
connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0)
connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0)
wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits
connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid
connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready
node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T)
connect c_opcodes_set, _c_opcodes_set_T_1
wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0)
connect _c_sizes_set_WIRE.bits.address, UInt<128>(0h0)
connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0)
connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0)
connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0)
connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_sizes_set_WIRE.valid, UInt<1>(0h0)
connect _c_sizes_set_WIRE.ready, UInt<1>(0h0)
wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits
connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid
connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready
node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2))
node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T)
connect c_sizes_set, _c_sizes_set_T_1
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<32>(0h0)
connect _WIRE_14.bits.address, UInt<128>(0h0)
connect _WIRE_14.bits.source, UInt<1>(0h0)
connect _WIRE_14.bits.size, UInt<2>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
node _T_621 = dshr(inflight_1, _WIRE_15.bits.source)
node _T_622 = bits(_T_621, 0, 0)
node _T_623 = eq(_T_622, UInt<1>(0h0))
node _T_624 = asUInt(reset)
node _T_625 = eq(_T_624, UInt<1>(0h0))
when _T_625 :
node _T_626 = eq(_T_623, UInt<1>(0h0))
when _T_626 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106
assert(clock, _T_623, UInt<1>(0h1), "") : assert_106
wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE.bits.address, UInt<128>(0h0)
connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits
connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid
connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready
node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4))
wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0)
connect _c_probe_ack_WIRE_2.bits.address, UInt<128>(0h0)
connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0)
connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0)
connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0)
wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits
connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid
connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready
node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5))
node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1)
wire d_clr_1 : UInt<1>
connect d_clr_1, UInt<1>(0h0)
wire d_clr_wo_ready_1 : UInt<1>
connect d_clr_wo_ready_1, UInt<1>(0h0)
wire d_opcodes_clr_1 : UInt<4>
connect d_opcodes_clr_1, UInt<4>(0h0)
wire d_sizes_clr_1 : UInt<4>
connect d_sizes_clr_1, UInt<4>(0h0)
node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6))
node _T_627 = and(io.in.d.valid, d_first_2)
node _T_628 = and(_T_627, UInt<1>(0h1))
node _T_629 = and(_T_628, d_release_ack_1)
when _T_629 :
node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1
node _T_630 = and(io.in.d.ready, io.in.d.valid)
node _T_631 = and(_T_630, d_first_2)
node _T_632 = and(_T_631, UInt<1>(0h1))
node _T_633 = and(_T_632, d_release_ack_1)
when _T_633 :
node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source)
connect d_clr_1, _d_clr_T_1
node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6)
node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1))
node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1)
node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10)
connect d_opcodes_clr_1, _d_opcodes_clr_T_11
node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2))
node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6)
node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1))
node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1)
node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2))
node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10)
connect d_sizes_clr_1, _d_sizes_clr_T_11
node _T_634 = and(io.in.d.valid, d_first_2)
node _T_635 = and(_T_634, UInt<1>(0h1))
node _T_636 = and(_T_635, d_release_ack_1)
when _T_636 :
wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE.bits.address, UInt<128>(0h0)
connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits
connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid
connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready
node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first)
wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_2.bits.address, UInt<128>(0h0)
connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits
connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid
connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready
node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2)
node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1)
node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5)
node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6)
wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0)
connect _same_cycle_resp_WIRE_4.bits.address, UInt<128>(0h0)
connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0)
connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0)
connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0)
connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0)
wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits
connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid
connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready
node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source)
node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8)
node _T_637 = dshr(inflight_1, io.in.d.bits.source)
node _T_638 = bits(_T_637, 0, 0)
node _T_639 = or(_T_638, same_cycle_resp_1)
node _T_640 = asUInt(reset)
node _T_641 = eq(_T_640, UInt<1>(0h0))
when _T_641 :
node _T_642 = eq(_T_639, UInt<1>(0h0))
when _T_642 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107
assert(clock, _T_639, UInt<1>(0h1), "") : assert_107
when same_cycle_resp_1 :
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_16.bits.corrupt, UInt<1>(0h0)
connect _WIRE_16.bits.data, UInt<32>(0h0)
connect _WIRE_16.bits.address, UInt<128>(0h0)
connect _WIRE_16.bits.source, UInt<1>(0h0)
connect _WIRE_16.bits.size, UInt<2>(0h0)
connect _WIRE_16.bits.param, UInt<3>(0h0)
connect _WIRE_16.bits.opcode, UInt<3>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
node _T_643 = eq(io.in.d.bits.size, _WIRE_17.bits.size)
node _T_644 = asUInt(reset)
node _T_645 = eq(_T_644, UInt<1>(0h0))
when _T_645 :
node _T_646 = eq(_T_643, UInt<1>(0h0))
when _T_646 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108
assert(clock, _T_643, UInt<1>(0h1), "") : assert_108
else :
node _T_647 = eq(io.in.d.bits.size, c_size_lookup)
node _T_648 = asUInt(reset)
node _T_649 = eq(_T_648, UInt<1>(0h0))
when _T_649 :
node _T_650 = eq(_T_647, UInt<1>(0h0))
when _T_650 :
printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109
assert(clock, _T_647, UInt<1>(0h1), "") : assert_109
node _T_651 = and(io.in.d.valid, d_first_2)
node _T_652 = and(_T_651, c_first)
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_18.bits.corrupt, UInt<1>(0h0)
connect _WIRE_18.bits.data, UInt<32>(0h0)
connect _WIRE_18.bits.address, UInt<128>(0h0)
connect _WIRE_18.bits.source, UInt<1>(0h0)
connect _WIRE_18.bits.size, UInt<2>(0h0)
connect _WIRE_18.bits.param, UInt<3>(0h0)
connect _WIRE_18.bits.opcode, UInt<3>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
node _T_653 = and(_T_652, _WIRE_19.valid)
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_20.bits.corrupt, UInt<1>(0h0)
connect _WIRE_20.bits.data, UInt<32>(0h0)
connect _WIRE_20.bits.address, UInt<128>(0h0)
connect _WIRE_20.bits.source, UInt<1>(0h0)
connect _WIRE_20.bits.size, UInt<2>(0h0)
connect _WIRE_20.bits.param, UInt<3>(0h0)
connect _WIRE_20.bits.opcode, UInt<3>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
node _T_654 = eq(_WIRE_21.bits.source, io.in.d.bits.source)
node _T_655 = and(_T_653, _T_654)
node _T_656 = and(_T_655, d_release_ack_1)
node _T_657 = eq(c_probe_ack, UInt<1>(0h0))
node _T_658 = and(_T_656, _T_657)
when _T_658 :
node _T_659 = eq(io.in.d.ready, UInt<1>(0h0))
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_22.bits.corrupt, UInt<1>(0h0)
connect _WIRE_22.bits.data, UInt<32>(0h0)
connect _WIRE_22.bits.address, UInt<128>(0h0)
connect _WIRE_22.bits.source, UInt<1>(0h0)
connect _WIRE_22.bits.size, UInt<2>(0h0)
connect _WIRE_22.bits.param, UInt<3>(0h0)
connect _WIRE_22.bits.opcode, UInt<3>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
node _T_660 = or(_T_659, _WIRE_23.ready)
node _T_661 = asUInt(reset)
node _T_662 = eq(_T_661, UInt<1>(0h0))
when _T_662 :
node _T_663 = eq(_T_660, UInt<1>(0h0))
when _T_663 :
printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110
assert(clock, _T_660, UInt<1>(0h1), "") : assert_110
node _inflight_T_3 = or(inflight_1, c_set)
node _inflight_T_4 = not(d_clr_1)
node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4)
connect inflight_1, _inflight_T_5
node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set)
node _inflight_opcodes_T_4 = not(d_opcodes_clr_1)
node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4)
connect inflight_opcodes_1, _inflight_opcodes_T_5
node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set)
node _inflight_sizes_T_4 = not(d_sizes_clr_1)
node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4)
connect inflight_sizes_1, _inflight_sizes_T_5
regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0)
inst plusarg_reader_1 of plusarg_reader_108
node _T_664 = orr(inflight_1)
node _T_665 = eq(_T_664, UInt<1>(0h0))
node _T_666 = eq(plusarg_reader_1.out, UInt<1>(0h0))
node _T_667 = or(_T_665, _T_666)
node _T_668 = lt(watchdog_1, plusarg_reader_1.out)
node _T_669 = or(_T_667, _T_668)
node _T_670 = asUInt(reset)
node _T_671 = eq(_T_670, UInt<1>(0h0))
when _T_671 :
node _T_672 = eq(_T_669, UInt<1>(0h0))
when _T_672 :
printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111
assert(clock, _T_669, UInt<1>(0h1), "") : assert_111
node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1))
node _watchdog_T_3 = tail(_watchdog_T_2, 1)
connect watchdog_1, _watchdog_T_3
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<32>(0h0)
connect _WIRE_24.bits.address, UInt<128>(0h0)
connect _WIRE_24.bits.source, UInt<1>(0h0)
connect _WIRE_24.bits.size, UInt<2>(0h0)
connect _WIRE_24.bits.param, UInt<3>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
node _T_673 = and(_WIRE_25.ready, _WIRE_25.valid)
node _T_674 = and(io.in.d.ready, io.in.d.valid)
node _T_675 = or(_T_673, _T_674)
when _T_675 :
connect watchdog_1, UInt<1>(0h0) | module TLMonitor_53( // @[Monitor.scala:36:7]
input clock, // @[Monitor.scala:36:7]
input reset, // @[Monitor.scala:36:7]
input io_in_a_ready, // @[Monitor.scala:20:14]
input io_in_a_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14]
input [127:0] io_in_a_bits_address, // @[Monitor.scala:20:14]
input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14]
input io_in_d_ready, // @[Monitor.scala:20:14]
input io_in_d_valid, // @[Monitor.scala:20:14]
input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14]
input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14]
input io_in_d_bits_denied, // @[Monitor.scala:20:14]
input io_in_d_bits_corrupt // @[Monitor.scala:20:14]
);
wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11]
wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11]
wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7]
wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7]
wire [127:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7]
wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7]
wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7]
wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7]
wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7]
wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7]
wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7]
wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7]
wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7]
wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7]
wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49]
wire mask_sub_size = 1'h0; // @[Misc.scala:209:26]
wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38]
wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38]
wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count = 1'h0; // @[Edges.scala:234:25]
wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25]
wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35]
wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59]
wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36]
wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14]
wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25]
wire c_first_done = 1'h0; // @[Edges.scala:233:22]
wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27]
wire c_first_count = 1'h0; // @[Edges.scala:234:25]
wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21]
wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59]
wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14]
wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25]
wire c_set = 1'h0; // @[Monitor.scala:738:34]
wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34]
wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47]
wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95]
wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71]
wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44]
wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36]
wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51]
wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40]
wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55]
wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61]
wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88]
wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31]
wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21]
wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_size = 1'h1; // @[Misc.scala:209:26]
wire mask_acc = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29]
wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29]
wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9]
wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31]
wire sink_ok = 1'h1; // @[Monitor.scala:309:31]
wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last = 1'h1; // @[Edges.scala:232:33]
wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33]
wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113]
wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28]
wire c_first = 1'h1; // @[Edges.scala:231:25]
wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43]
wire c_first_last = 1'h1; // @[Edges.scala:232:33]
wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43]
wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33]
wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113]
wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46]
wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10]
wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10]
wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46]
wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46]
wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76]
wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28]
wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7]
wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34]
wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7]
wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42]
wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40]
wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51]
wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7]
wire [3:0] mask = 4'hF; // @[Misc.scala:222:10]
wire [31:0] io_in_d_bits_data = 32'h0; // @[Monitor.scala:36:7]
wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_first_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_first_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_first_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_first_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_set_wo_ready_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_set_wo_ready_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_opcodes_set_interm_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_sizes_set_interm_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_sizes_set_interm_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_opcodes_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_opcodes_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_sizes_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_sizes_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_probe_ack_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_probe_ack_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _c_probe_ack_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _c_probe_ack_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _same_cycle_resp_WIRE_4_bits_address = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _same_cycle_resp_WIRE_5_bits_address = 128'h0; // @[Bundles.scala:265:61]
wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76]
wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76]
wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46]
wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74]
wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61]
wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76]
wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74]
wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76]
wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74]
wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69]
wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65]
wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79]
wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77]
wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101]
wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99]
wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34]
wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34]
wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69]
wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67]
wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40]
wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53]
wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79]
wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77]
wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101]
wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99]
wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57]
wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57]
wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57]
wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57]
wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51]
wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51]
wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12]
wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27]
wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81]
wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35]
wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52]
wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54]
wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42]
wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59]
wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61]
wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71]
wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42]
wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59]
wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42]
wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51]
wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42]
wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42]
wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71]
wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71]
wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123]
wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117]
wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48]
wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48]
wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123]
wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119]
wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48]
wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48]
wire [127:0] _is_aligned_T = {126'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7]
wire is_aligned = _is_aligned_T == 128'h0; // @[Edges.scala:21:{16,24}]
wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26]
wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27]
wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20]
wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27]
wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26]
wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20]
wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38]
wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38]
wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27]
wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38]
wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27]
wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38]
wire _T_607 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35]
wire _a_first_T; // @[Decoupled.scala:51:35]
assign _a_first_T = _T_607; // @[Decoupled.scala:51:35]
wire _a_first_T_1; // @[Decoupled.scala:51:35]
assign _a_first_T_1 = _T_607; // @[Decoupled.scala:51:35]
wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35]
wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7]
wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
reg a_first_counter; // @[Edges.scala:229:27]
wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28]
wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode; // @[Monitor.scala:387:22]
reg [127:0] address; // @[Monitor.scala:391:22]
wire _T_675 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35]
wire _d_first_T; // @[Decoupled.scala:51:35]
assign _d_first_T = _T_675; // @[Decoupled.scala:51:35]
wire _d_first_T_1; // @[Decoupled.scala:51:35]
assign _d_first_T_1 = _T_675; // @[Decoupled.scala:51:35]
wire _d_first_T_2; // @[Decoupled.scala:51:35]
assign _d_first_T_2 = _T_675; // @[Decoupled.scala:51:35]
wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35]
wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71]
assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71]
wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71]
assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71]
wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7]
reg d_first_counter; // @[Edges.scala:229:27]
wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28]
wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21]
reg [2:0] opcode_1; // @[Monitor.scala:538:22]
reg [1:0] param_1; // @[Monitor.scala:539:22]
reg [1:0] size_1; // @[Monitor.scala:540:22]
reg denied; // @[Monitor.scala:543:22]
reg [1:0] inflight; // @[Monitor.scala:614:27]
reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35]
wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44]
reg [3:0] inflight_sizes; // @[Monitor.scala:618:33]
wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40]
wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35]
wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}]
reg a_first_counter_1; // @[Edges.scala:229:27]
wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}]
reg d_first_counter_1; // @[Edges.scala:229:27]
wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28]
wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21]
wire a_set; // @[Monitor.scala:626:34]
wire a_set_wo_ready; // @[Monitor.scala:627:34]
wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33]
wire [3:0] a_sizes_set; // @[Monitor.scala:632:31]
wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35]
wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}]
wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}]
assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}]
wire [3:0] a_size_lookup; // @[Monitor.scala:639:33]
wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}]
wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}]
assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}]
wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40]
wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38]
wire _T_537 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26]
assign a_set_wo_ready = _T_537; // @[Monitor.scala:627:34, :651:26]
wire _same_cycle_resp_T; // @[Monitor.scala:684:44]
assign _same_cycle_resp_T = _T_537; // @[Monitor.scala:651:26, :684:44]
assign a_set = _T_607 & a_first_1; // @[Decoupled.scala:51:35]
wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53]
wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}]
assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}]
assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28]
wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54]
assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}]
wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52]
assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}]
wire d_clr; // @[Monitor.scala:664:34]
wire d_clr_wo_ready; // @[Monitor.scala:665:34]
wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33]
wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31]
wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46]
wire d_release_ack; // @[Monitor.scala:673:46]
assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46]
wire d_release_ack_1; // @[Monitor.scala:783:46]
assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46]
wire _T_586 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26]
assign d_clr_wo_ready = _T_586 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}]
assign d_clr = _T_675 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35]
wire [3:0] _GEN_1 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21]
assign d_opcodes_clr = _GEN_1; // @[Monitor.scala:668:33, :678:89, :680:21]
assign d_sizes_clr = _GEN_1; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21]
wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}]
wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}]
wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27]
wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38]
wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}]
wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43]
wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62]
wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}]
wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39]
wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56]
wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}]
reg [31:0] watchdog; // @[Monitor.scala:709:27]
wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26]
wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26]
reg [1:0] inflight_1; // @[Monitor.scala:726:35]
wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35]
reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35]
wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44]
wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43]
reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35]
wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42]
wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41]
wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35]
wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}]
wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}]
reg d_first_counter_2; // @[Edges.scala:229:27]
wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25]
wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28]
wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28]
wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25]
wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27]
wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21]
wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35]
wire [3:0] c_size_lookup; // @[Monitor.scala:748:35]
wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}]
wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}]
assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}]
wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}]
wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}]
assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}]
wire d_clr_1; // @[Monitor.scala:774:34]
wire d_clr_wo_ready_1; // @[Monitor.scala:775:34]
wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34]
wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34]
wire _T_651 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26]
assign d_clr_wo_ready_1 = _T_651 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}]
assign d_clr_1 = _T_675 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35]
wire [3:0] _GEN_2 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21]
assign d_opcodes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :788:88, :790:21]
assign d_sizes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21]
wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46]
wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}]
wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62]
wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}]
wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58]
wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}]
reg [31:0] watchdog_1; // @[Monitor.scala:818:27] |
Generate the Verilog code corresponding to this FIRRTL code module ALUExeUnit_2 :
input clock : Clock
input reset : Reset
output io : { fu_types : UInt<10>, flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, rs1_data : UInt<65>, rs2_data : UInt<65>, rs3_data : UInt<65>, pred_data : UInt<1>, kill : UInt<1>}}, ll_iresp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}, ll_fresp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}, bypass : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}[0], flip brupdate : { b1 : { resolve_mask : UInt<8>, mispredict_mask : UInt<8>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip lsu_io : { flip req : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, predicated : UInt<1>, data : UInt<64>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}, addr : UInt<40>, mxcpt : { valid : UInt<1>, bits : UInt<25>}, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}}}, iresp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}, fresp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, data : UInt<65>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<8>, br_tag : UInt<3>, ftq_idx : UInt<4>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<5>, ldq_idx : UInt<3>, stq_idx : UInt<3>, rxq_idx : UInt<2>, pdst : UInt<6>, prs1 : UInt<6>, prs2 : UInt<6>, prs3 : UInt<6>, ppred : UInt<4>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<6>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, flags : UInt<5>}}}}}, flip bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[0], flip mcontext : UInt<0>, flip scontext : UInt<0>, flip com_exception : UInt<1>}
connect io.req.ready, UInt<1>(0h0)
connect io.ll_iresp.valid, UInt<1>(0h0)
invalidate io.ll_iresp.bits.fflags.bits.flags
invalidate io.ll_iresp.bits.fflags.bits.uop.debug_tsrc
invalidate io.ll_iresp.bits.fflags.bits.uop.debug_fsrc
invalidate io.ll_iresp.bits.fflags.bits.uop.bp_xcpt_if
invalidate io.ll_iresp.bits.fflags.bits.uop.bp_debug_if
invalidate io.ll_iresp.bits.fflags.bits.uop.xcpt_ma_if
invalidate io.ll_iresp.bits.fflags.bits.uop.xcpt_ae_if
invalidate io.ll_iresp.bits.fflags.bits.uop.xcpt_pf_if
invalidate io.ll_iresp.bits.fflags.bits.uop.fp_single
invalidate io.ll_iresp.bits.fflags.bits.uop.fp_val
invalidate io.ll_iresp.bits.fflags.bits.uop.frs3_en
invalidate io.ll_iresp.bits.fflags.bits.uop.lrs2_rtype
invalidate io.ll_iresp.bits.fflags.bits.uop.lrs1_rtype
invalidate io.ll_iresp.bits.fflags.bits.uop.dst_rtype
invalidate io.ll_iresp.bits.fflags.bits.uop.ldst_val
invalidate io.ll_iresp.bits.fflags.bits.uop.lrs3
invalidate io.ll_iresp.bits.fflags.bits.uop.lrs2
invalidate io.ll_iresp.bits.fflags.bits.uop.lrs1
invalidate io.ll_iresp.bits.fflags.bits.uop.ldst
invalidate io.ll_iresp.bits.fflags.bits.uop.ldst_is_rs1
invalidate io.ll_iresp.bits.fflags.bits.uop.flush_on_commit
invalidate io.ll_iresp.bits.fflags.bits.uop.is_unique
invalidate io.ll_iresp.bits.fflags.bits.uop.is_sys_pc2epc
invalidate io.ll_iresp.bits.fflags.bits.uop.uses_stq
invalidate io.ll_iresp.bits.fflags.bits.uop.uses_ldq
invalidate io.ll_iresp.bits.fflags.bits.uop.is_amo
invalidate io.ll_iresp.bits.fflags.bits.uop.is_fencei
invalidate io.ll_iresp.bits.fflags.bits.uop.is_fence
invalidate io.ll_iresp.bits.fflags.bits.uop.mem_signed
invalidate io.ll_iresp.bits.fflags.bits.uop.mem_size
invalidate io.ll_iresp.bits.fflags.bits.uop.mem_cmd
invalidate io.ll_iresp.bits.fflags.bits.uop.bypassable
invalidate io.ll_iresp.bits.fflags.bits.uop.exc_cause
invalidate io.ll_iresp.bits.fflags.bits.uop.exception
invalidate io.ll_iresp.bits.fflags.bits.uop.stale_pdst
invalidate io.ll_iresp.bits.fflags.bits.uop.ppred_busy
invalidate io.ll_iresp.bits.fflags.bits.uop.prs3_busy
invalidate io.ll_iresp.bits.fflags.bits.uop.prs2_busy
invalidate io.ll_iresp.bits.fflags.bits.uop.prs1_busy
invalidate io.ll_iresp.bits.fflags.bits.uop.ppred
invalidate io.ll_iresp.bits.fflags.bits.uop.prs3
invalidate io.ll_iresp.bits.fflags.bits.uop.prs2
invalidate io.ll_iresp.bits.fflags.bits.uop.prs1
invalidate io.ll_iresp.bits.fflags.bits.uop.pdst
invalidate io.ll_iresp.bits.fflags.bits.uop.rxq_idx
invalidate io.ll_iresp.bits.fflags.bits.uop.stq_idx
invalidate io.ll_iresp.bits.fflags.bits.uop.ldq_idx
invalidate io.ll_iresp.bits.fflags.bits.uop.rob_idx
invalidate io.ll_iresp.bits.fflags.bits.uop.csr_addr
invalidate io.ll_iresp.bits.fflags.bits.uop.imm_packed
invalidate io.ll_iresp.bits.fflags.bits.uop.taken
invalidate io.ll_iresp.bits.fflags.bits.uop.pc_lob
invalidate io.ll_iresp.bits.fflags.bits.uop.edge_inst
invalidate io.ll_iresp.bits.fflags.bits.uop.ftq_idx
invalidate io.ll_iresp.bits.fflags.bits.uop.br_tag
invalidate io.ll_iresp.bits.fflags.bits.uop.br_mask
invalidate io.ll_iresp.bits.fflags.bits.uop.is_sfb
invalidate io.ll_iresp.bits.fflags.bits.uop.is_jal
invalidate io.ll_iresp.bits.fflags.bits.uop.is_jalr
invalidate io.ll_iresp.bits.fflags.bits.uop.is_br
invalidate io.ll_iresp.bits.fflags.bits.uop.iw_p2_poisoned
invalidate io.ll_iresp.bits.fflags.bits.uop.iw_p1_poisoned
invalidate io.ll_iresp.bits.fflags.bits.uop.iw_state
invalidate io.ll_iresp.bits.fflags.bits.uop.ctrl.is_std
invalidate io.ll_iresp.bits.fflags.bits.uop.ctrl.is_sta
invalidate io.ll_iresp.bits.fflags.bits.uop.ctrl.is_load
invalidate io.ll_iresp.bits.fflags.bits.uop.ctrl.csr_cmd
invalidate io.ll_iresp.bits.fflags.bits.uop.ctrl.fcn_dw
invalidate io.ll_iresp.bits.fflags.bits.uop.ctrl.op_fcn
invalidate io.ll_iresp.bits.fflags.bits.uop.ctrl.imm_sel
invalidate io.ll_iresp.bits.fflags.bits.uop.ctrl.op2_sel
invalidate io.ll_iresp.bits.fflags.bits.uop.ctrl.op1_sel
invalidate io.ll_iresp.bits.fflags.bits.uop.ctrl.br_type
invalidate io.ll_iresp.bits.fflags.bits.uop.fu_code
invalidate io.ll_iresp.bits.fflags.bits.uop.iq_type
invalidate io.ll_iresp.bits.fflags.bits.uop.debug_pc
invalidate io.ll_iresp.bits.fflags.bits.uop.is_rvc
invalidate io.ll_iresp.bits.fflags.bits.uop.debug_inst
invalidate io.ll_iresp.bits.fflags.bits.uop.inst
invalidate io.ll_iresp.bits.fflags.bits.uop.uopc
invalidate io.ll_iresp.bits.fflags.valid
invalidate io.ll_iresp.bits.predicated
invalidate io.ll_iresp.bits.data
invalidate io.ll_iresp.bits.uop.debug_tsrc
invalidate io.ll_iresp.bits.uop.debug_fsrc
invalidate io.ll_iresp.bits.uop.bp_xcpt_if
invalidate io.ll_iresp.bits.uop.bp_debug_if
invalidate io.ll_iresp.bits.uop.xcpt_ma_if
invalidate io.ll_iresp.bits.uop.xcpt_ae_if
invalidate io.ll_iresp.bits.uop.xcpt_pf_if
invalidate io.ll_iresp.bits.uop.fp_single
invalidate io.ll_iresp.bits.uop.fp_val
invalidate io.ll_iresp.bits.uop.frs3_en
invalidate io.ll_iresp.bits.uop.lrs2_rtype
invalidate io.ll_iresp.bits.uop.lrs1_rtype
invalidate io.ll_iresp.bits.uop.dst_rtype
invalidate io.ll_iresp.bits.uop.ldst_val
invalidate io.ll_iresp.bits.uop.lrs3
invalidate io.ll_iresp.bits.uop.lrs2
invalidate io.ll_iresp.bits.uop.lrs1
invalidate io.ll_iresp.bits.uop.ldst
invalidate io.ll_iresp.bits.uop.ldst_is_rs1
invalidate io.ll_iresp.bits.uop.flush_on_commit
invalidate io.ll_iresp.bits.uop.is_unique
invalidate io.ll_iresp.bits.uop.is_sys_pc2epc
invalidate io.ll_iresp.bits.uop.uses_stq
invalidate io.ll_iresp.bits.uop.uses_ldq
invalidate io.ll_iresp.bits.uop.is_amo
invalidate io.ll_iresp.bits.uop.is_fencei
invalidate io.ll_iresp.bits.uop.is_fence
invalidate io.ll_iresp.bits.uop.mem_signed
invalidate io.ll_iresp.bits.uop.mem_size
invalidate io.ll_iresp.bits.uop.mem_cmd
invalidate io.ll_iresp.bits.uop.bypassable
invalidate io.ll_iresp.bits.uop.exc_cause
invalidate io.ll_iresp.bits.uop.exception
invalidate io.ll_iresp.bits.uop.stale_pdst
invalidate io.ll_iresp.bits.uop.ppred_busy
invalidate io.ll_iresp.bits.uop.prs3_busy
invalidate io.ll_iresp.bits.uop.prs2_busy
invalidate io.ll_iresp.bits.uop.prs1_busy
invalidate io.ll_iresp.bits.uop.ppred
invalidate io.ll_iresp.bits.uop.prs3
invalidate io.ll_iresp.bits.uop.prs2
invalidate io.ll_iresp.bits.uop.prs1
invalidate io.ll_iresp.bits.uop.pdst
invalidate io.ll_iresp.bits.uop.rxq_idx
invalidate io.ll_iresp.bits.uop.stq_idx
invalidate io.ll_iresp.bits.uop.ldq_idx
invalidate io.ll_iresp.bits.uop.rob_idx
invalidate io.ll_iresp.bits.uop.csr_addr
invalidate io.ll_iresp.bits.uop.imm_packed
invalidate io.ll_iresp.bits.uop.taken
invalidate io.ll_iresp.bits.uop.pc_lob
invalidate io.ll_iresp.bits.uop.edge_inst
invalidate io.ll_iresp.bits.uop.ftq_idx
invalidate io.ll_iresp.bits.uop.br_tag
invalidate io.ll_iresp.bits.uop.br_mask
invalidate io.ll_iresp.bits.uop.is_sfb
invalidate io.ll_iresp.bits.uop.is_jal
invalidate io.ll_iresp.bits.uop.is_jalr
invalidate io.ll_iresp.bits.uop.is_br
invalidate io.ll_iresp.bits.uop.iw_p2_poisoned
invalidate io.ll_iresp.bits.uop.iw_p1_poisoned
invalidate io.ll_iresp.bits.uop.iw_state
invalidate io.ll_iresp.bits.uop.ctrl.is_std
invalidate io.ll_iresp.bits.uop.ctrl.is_sta
invalidate io.ll_iresp.bits.uop.ctrl.is_load
invalidate io.ll_iresp.bits.uop.ctrl.csr_cmd
invalidate io.ll_iresp.bits.uop.ctrl.fcn_dw
invalidate io.ll_iresp.bits.uop.ctrl.op_fcn
invalidate io.ll_iresp.bits.uop.ctrl.imm_sel
invalidate io.ll_iresp.bits.uop.ctrl.op2_sel
invalidate io.ll_iresp.bits.uop.ctrl.op1_sel
invalidate io.ll_iresp.bits.uop.ctrl.br_type
invalidate io.ll_iresp.bits.uop.fu_code
invalidate io.ll_iresp.bits.uop.iq_type
invalidate io.ll_iresp.bits.uop.debug_pc
invalidate io.ll_iresp.bits.uop.is_rvc
invalidate io.ll_iresp.bits.uop.debug_inst
invalidate io.ll_iresp.bits.uop.inst
invalidate io.ll_iresp.bits.uop.uopc
connect io.ll_iresp.bits.fflags.valid, UInt<1>(0h0)
connect io.ll_iresp.bits.predicated, UInt<1>(0h0)
connect io.ll_fresp.valid, UInt<1>(0h0)
invalidate io.ll_fresp.bits.fflags.bits.flags
invalidate io.ll_fresp.bits.fflags.bits.uop.debug_tsrc
invalidate io.ll_fresp.bits.fflags.bits.uop.debug_fsrc
invalidate io.ll_fresp.bits.fflags.bits.uop.bp_xcpt_if
invalidate io.ll_fresp.bits.fflags.bits.uop.bp_debug_if
invalidate io.ll_fresp.bits.fflags.bits.uop.xcpt_ma_if
invalidate io.ll_fresp.bits.fflags.bits.uop.xcpt_ae_if
invalidate io.ll_fresp.bits.fflags.bits.uop.xcpt_pf_if
invalidate io.ll_fresp.bits.fflags.bits.uop.fp_single
invalidate io.ll_fresp.bits.fflags.bits.uop.fp_val
invalidate io.ll_fresp.bits.fflags.bits.uop.frs3_en
invalidate io.ll_fresp.bits.fflags.bits.uop.lrs2_rtype
invalidate io.ll_fresp.bits.fflags.bits.uop.lrs1_rtype
invalidate io.ll_fresp.bits.fflags.bits.uop.dst_rtype
invalidate io.ll_fresp.bits.fflags.bits.uop.ldst_val
invalidate io.ll_fresp.bits.fflags.bits.uop.lrs3
invalidate io.ll_fresp.bits.fflags.bits.uop.lrs2
invalidate io.ll_fresp.bits.fflags.bits.uop.lrs1
invalidate io.ll_fresp.bits.fflags.bits.uop.ldst
invalidate io.ll_fresp.bits.fflags.bits.uop.ldst_is_rs1
invalidate io.ll_fresp.bits.fflags.bits.uop.flush_on_commit
invalidate io.ll_fresp.bits.fflags.bits.uop.is_unique
invalidate io.ll_fresp.bits.fflags.bits.uop.is_sys_pc2epc
invalidate io.ll_fresp.bits.fflags.bits.uop.uses_stq
invalidate io.ll_fresp.bits.fflags.bits.uop.uses_ldq
invalidate io.ll_fresp.bits.fflags.bits.uop.is_amo
invalidate io.ll_fresp.bits.fflags.bits.uop.is_fencei
invalidate io.ll_fresp.bits.fflags.bits.uop.is_fence
invalidate io.ll_fresp.bits.fflags.bits.uop.mem_signed
invalidate io.ll_fresp.bits.fflags.bits.uop.mem_size
invalidate io.ll_fresp.bits.fflags.bits.uop.mem_cmd
invalidate io.ll_fresp.bits.fflags.bits.uop.bypassable
invalidate io.ll_fresp.bits.fflags.bits.uop.exc_cause
invalidate io.ll_fresp.bits.fflags.bits.uop.exception
invalidate io.ll_fresp.bits.fflags.bits.uop.stale_pdst
invalidate io.ll_fresp.bits.fflags.bits.uop.ppred_busy
invalidate io.ll_fresp.bits.fflags.bits.uop.prs3_busy
invalidate io.ll_fresp.bits.fflags.bits.uop.prs2_busy
invalidate io.ll_fresp.bits.fflags.bits.uop.prs1_busy
invalidate io.ll_fresp.bits.fflags.bits.uop.ppred
invalidate io.ll_fresp.bits.fflags.bits.uop.prs3
invalidate io.ll_fresp.bits.fflags.bits.uop.prs2
invalidate io.ll_fresp.bits.fflags.bits.uop.prs1
invalidate io.ll_fresp.bits.fflags.bits.uop.pdst
invalidate io.ll_fresp.bits.fflags.bits.uop.rxq_idx
invalidate io.ll_fresp.bits.fflags.bits.uop.stq_idx
invalidate io.ll_fresp.bits.fflags.bits.uop.ldq_idx
invalidate io.ll_fresp.bits.fflags.bits.uop.rob_idx
invalidate io.ll_fresp.bits.fflags.bits.uop.csr_addr
invalidate io.ll_fresp.bits.fflags.bits.uop.imm_packed
invalidate io.ll_fresp.bits.fflags.bits.uop.taken
invalidate io.ll_fresp.bits.fflags.bits.uop.pc_lob
invalidate io.ll_fresp.bits.fflags.bits.uop.edge_inst
invalidate io.ll_fresp.bits.fflags.bits.uop.ftq_idx
invalidate io.ll_fresp.bits.fflags.bits.uop.br_tag
invalidate io.ll_fresp.bits.fflags.bits.uop.br_mask
invalidate io.ll_fresp.bits.fflags.bits.uop.is_sfb
invalidate io.ll_fresp.bits.fflags.bits.uop.is_jal
invalidate io.ll_fresp.bits.fflags.bits.uop.is_jalr
invalidate io.ll_fresp.bits.fflags.bits.uop.is_br
invalidate io.ll_fresp.bits.fflags.bits.uop.iw_p2_poisoned
invalidate io.ll_fresp.bits.fflags.bits.uop.iw_p1_poisoned
invalidate io.ll_fresp.bits.fflags.bits.uop.iw_state
invalidate io.ll_fresp.bits.fflags.bits.uop.ctrl.is_std
invalidate io.ll_fresp.bits.fflags.bits.uop.ctrl.is_sta
invalidate io.ll_fresp.bits.fflags.bits.uop.ctrl.is_load
invalidate io.ll_fresp.bits.fflags.bits.uop.ctrl.csr_cmd
invalidate io.ll_fresp.bits.fflags.bits.uop.ctrl.fcn_dw
invalidate io.ll_fresp.bits.fflags.bits.uop.ctrl.op_fcn
invalidate io.ll_fresp.bits.fflags.bits.uop.ctrl.imm_sel
invalidate io.ll_fresp.bits.fflags.bits.uop.ctrl.op2_sel
invalidate io.ll_fresp.bits.fflags.bits.uop.ctrl.op1_sel
invalidate io.ll_fresp.bits.fflags.bits.uop.ctrl.br_type
invalidate io.ll_fresp.bits.fflags.bits.uop.fu_code
invalidate io.ll_fresp.bits.fflags.bits.uop.iq_type
invalidate io.ll_fresp.bits.fflags.bits.uop.debug_pc
invalidate io.ll_fresp.bits.fflags.bits.uop.is_rvc
invalidate io.ll_fresp.bits.fflags.bits.uop.debug_inst
invalidate io.ll_fresp.bits.fflags.bits.uop.inst
invalidate io.ll_fresp.bits.fflags.bits.uop.uopc
invalidate io.ll_fresp.bits.fflags.valid
invalidate io.ll_fresp.bits.predicated
invalidate io.ll_fresp.bits.data
invalidate io.ll_fresp.bits.uop.debug_tsrc
invalidate io.ll_fresp.bits.uop.debug_fsrc
invalidate io.ll_fresp.bits.uop.bp_xcpt_if
invalidate io.ll_fresp.bits.uop.bp_debug_if
invalidate io.ll_fresp.bits.uop.xcpt_ma_if
invalidate io.ll_fresp.bits.uop.xcpt_ae_if
invalidate io.ll_fresp.bits.uop.xcpt_pf_if
invalidate io.ll_fresp.bits.uop.fp_single
invalidate io.ll_fresp.bits.uop.fp_val
invalidate io.ll_fresp.bits.uop.frs3_en
invalidate io.ll_fresp.bits.uop.lrs2_rtype
invalidate io.ll_fresp.bits.uop.lrs1_rtype
invalidate io.ll_fresp.bits.uop.dst_rtype
invalidate io.ll_fresp.bits.uop.ldst_val
invalidate io.ll_fresp.bits.uop.lrs3
invalidate io.ll_fresp.bits.uop.lrs2
invalidate io.ll_fresp.bits.uop.lrs1
invalidate io.ll_fresp.bits.uop.ldst
invalidate io.ll_fresp.bits.uop.ldst_is_rs1
invalidate io.ll_fresp.bits.uop.flush_on_commit
invalidate io.ll_fresp.bits.uop.is_unique
invalidate io.ll_fresp.bits.uop.is_sys_pc2epc
invalidate io.ll_fresp.bits.uop.uses_stq
invalidate io.ll_fresp.bits.uop.uses_ldq
invalidate io.ll_fresp.bits.uop.is_amo
invalidate io.ll_fresp.bits.uop.is_fencei
invalidate io.ll_fresp.bits.uop.is_fence
invalidate io.ll_fresp.bits.uop.mem_signed
invalidate io.ll_fresp.bits.uop.mem_size
invalidate io.ll_fresp.bits.uop.mem_cmd
invalidate io.ll_fresp.bits.uop.bypassable
invalidate io.ll_fresp.bits.uop.exc_cause
invalidate io.ll_fresp.bits.uop.exception
invalidate io.ll_fresp.bits.uop.stale_pdst
invalidate io.ll_fresp.bits.uop.ppred_busy
invalidate io.ll_fresp.bits.uop.prs3_busy
invalidate io.ll_fresp.bits.uop.prs2_busy
invalidate io.ll_fresp.bits.uop.prs1_busy
invalidate io.ll_fresp.bits.uop.ppred
invalidate io.ll_fresp.bits.uop.prs3
invalidate io.ll_fresp.bits.uop.prs2
invalidate io.ll_fresp.bits.uop.prs1
invalidate io.ll_fresp.bits.uop.pdst
invalidate io.ll_fresp.bits.uop.rxq_idx
invalidate io.ll_fresp.bits.uop.stq_idx
invalidate io.ll_fresp.bits.uop.ldq_idx
invalidate io.ll_fresp.bits.uop.rob_idx
invalidate io.ll_fresp.bits.uop.csr_addr
invalidate io.ll_fresp.bits.uop.imm_packed
invalidate io.ll_fresp.bits.uop.taken
invalidate io.ll_fresp.bits.uop.pc_lob
invalidate io.ll_fresp.bits.uop.edge_inst
invalidate io.ll_fresp.bits.uop.ftq_idx
invalidate io.ll_fresp.bits.uop.br_tag
invalidate io.ll_fresp.bits.uop.br_mask
invalidate io.ll_fresp.bits.uop.is_sfb
invalidate io.ll_fresp.bits.uop.is_jal
invalidate io.ll_fresp.bits.uop.is_jalr
invalidate io.ll_fresp.bits.uop.is_br
invalidate io.ll_fresp.bits.uop.iw_p2_poisoned
invalidate io.ll_fresp.bits.uop.iw_p1_poisoned
invalidate io.ll_fresp.bits.uop.iw_state
invalidate io.ll_fresp.bits.uop.ctrl.is_std
invalidate io.ll_fresp.bits.uop.ctrl.is_sta
invalidate io.ll_fresp.bits.uop.ctrl.is_load
invalidate io.ll_fresp.bits.uop.ctrl.csr_cmd
invalidate io.ll_fresp.bits.uop.ctrl.fcn_dw
invalidate io.ll_fresp.bits.uop.ctrl.op_fcn
invalidate io.ll_fresp.bits.uop.ctrl.imm_sel
invalidate io.ll_fresp.bits.uop.ctrl.op2_sel
invalidate io.ll_fresp.bits.uop.ctrl.op1_sel
invalidate io.ll_fresp.bits.uop.ctrl.br_type
invalidate io.ll_fresp.bits.uop.fu_code
invalidate io.ll_fresp.bits.uop.iq_type
invalidate io.ll_fresp.bits.uop.debug_pc
invalidate io.ll_fresp.bits.uop.is_rvc
invalidate io.ll_fresp.bits.uop.debug_inst
invalidate io.ll_fresp.bits.uop.inst
invalidate io.ll_fresp.bits.uop.uopc
connect io.ll_fresp.bits.fflags.valid, UInt<1>(0h0)
connect io.ll_fresp.bits.predicated, UInt<1>(0h0)
wire div_busy : UInt<1>
connect div_busy, UInt<1>(0h0)
wire ifpu_busy : UInt<1>
connect ifpu_busy, UInt<1>(0h0)
node _io_fu_types_T = mux(UInt<1>(0h0), UInt<10>(0h1), UInt<1>(0h0))
node _io_fu_types_T_1 = mux(UInt<1>(0h0), UInt<10>(0h8), UInt<1>(0h0))
node _io_fu_types_T_2 = or(_io_fu_types_T, _io_fu_types_T_1)
node _io_fu_types_T_3 = eq(div_busy, UInt<1>(0h0))
node _io_fu_types_T_4 = and(_io_fu_types_T_3, UInt<1>(0h0))
node _io_fu_types_T_5 = mux(_io_fu_types_T_4, UInt<10>(0h10), UInt<1>(0h0))
node _io_fu_types_T_6 = or(_io_fu_types_T_2, _io_fu_types_T_5)
node _io_fu_types_T_7 = mux(UInt<1>(0h0), UInt<10>(0h20), UInt<1>(0h0))
node _io_fu_types_T_8 = or(_io_fu_types_T_6, _io_fu_types_T_7)
node _io_fu_types_T_9 = mux(UInt<1>(0h0), UInt<10>(0h2), UInt<1>(0h0))
node _io_fu_types_T_10 = or(_io_fu_types_T_8, _io_fu_types_T_9)
node _io_fu_types_T_11 = eq(ifpu_busy, UInt<1>(0h0))
node _io_fu_types_T_12 = and(_io_fu_types_T_11, UInt<1>(0h0))
node _io_fu_types_T_13 = mux(_io_fu_types_T_12, UInt<10>(0h100), UInt<1>(0h0))
node _io_fu_types_T_14 = or(_io_fu_types_T_10, _io_fu_types_T_13)
node _io_fu_types_T_15 = mux(UInt<1>(0h1), UInt<10>(0h4), UInt<1>(0h0))
node _io_fu_types_T_16 = or(_io_fu_types_T_14, _io_fu_types_T_15)
connect io.fu_types, _io_fu_types_T_16
wire div_resp_val : UInt<1>
connect div_resp_val, UInt<1>(0h0)
inst maddrcalc of MemAddrCalcUnit_1
connect maddrcalc.clock, clock
connect maddrcalc.reset, reset
connect maddrcalc.io.req, io.req
node _maddrcalc_io_req_valid_T = and(io.req.bits.uop.fu_code, UInt<10>(0h4))
node _maddrcalc_io_req_valid_T_1 = neq(_maddrcalc_io_req_valid_T, UInt<1>(0h0))
node _maddrcalc_io_req_valid_T_2 = and(io.req.valid, _maddrcalc_io_req_valid_T_1)
connect maddrcalc.io.req.valid, _maddrcalc_io_req_valid_T_2
connect maddrcalc.io.brupdate, io.brupdate
connect maddrcalc.io.status.uie, io.status.uie
connect maddrcalc.io.status.sie, io.status.sie
connect maddrcalc.io.status.hie, io.status.hie
connect maddrcalc.io.status.mie, io.status.mie
connect maddrcalc.io.status.upie, io.status.upie
connect maddrcalc.io.status.spie, io.status.spie
connect maddrcalc.io.status.ube, io.status.ube
connect maddrcalc.io.status.mpie, io.status.mpie
connect maddrcalc.io.status.spp, io.status.spp
connect maddrcalc.io.status.vs, io.status.vs
connect maddrcalc.io.status.mpp, io.status.mpp
connect maddrcalc.io.status.fs, io.status.fs
connect maddrcalc.io.status.xs, io.status.xs
connect maddrcalc.io.status.mprv, io.status.mprv
connect maddrcalc.io.status.sum, io.status.sum
connect maddrcalc.io.status.mxr, io.status.mxr
connect maddrcalc.io.status.tvm, io.status.tvm
connect maddrcalc.io.status.tw, io.status.tw
connect maddrcalc.io.status.tsr, io.status.tsr
connect maddrcalc.io.status.zero1, io.status.zero1
connect maddrcalc.io.status.sd_rv32, io.status.sd_rv32
connect maddrcalc.io.status.uxl, io.status.uxl
connect maddrcalc.io.status.sxl, io.status.sxl
connect maddrcalc.io.status.sbe, io.status.sbe
connect maddrcalc.io.status.mbe, io.status.mbe
connect maddrcalc.io.status.gva, io.status.gva
connect maddrcalc.io.status.mpv, io.status.mpv
connect maddrcalc.io.status.zero2, io.status.zero2
connect maddrcalc.io.status.sd, io.status.sd
connect maddrcalc.io.status.v, io.status.v
connect maddrcalc.io.status.prv, io.status.prv
connect maddrcalc.io.status.dv, io.status.dv
connect maddrcalc.io.status.dprv, io.status.dprv
connect maddrcalc.io.status.isa, io.status.isa
connect maddrcalc.io.status.wfi, io.status.wfi
connect maddrcalc.io.status.cease, io.status.cease
connect maddrcalc.io.status.debug, io.status.debug
connect maddrcalc.io.mcontext, io.mcontext
connect maddrcalc.io.scontext, io.scontext
invalidate maddrcalc.io.resp.ready
connect io.lsu_io.req.bits, maddrcalc.io.resp.bits
connect io.lsu_io.req.valid, maddrcalc.io.resp.valid
connect io.ll_iresp, io.lsu_io.iresp
connect io.ll_fresp, io.lsu_io.fresp
node _T = leq(UInt<1>(0h0), UInt<1>(0h1))
node _T_1 = eq(div_resp_val, UInt<1>(0h0))
node _T_2 = and(_T, _T_1)
node _T_3 = leq(UInt<1>(0h0), UInt<2>(0h2))
node _T_4 = and(_T_3, div_resp_val)
node _T_5 = or(_T_2, _T_4)
node _T_6 = asUInt(reset)
node _T_7 = eq(_T_6, UInt<1>(0h0))
when _T_7 :
node _T_8 = eq(_T_5, UInt<1>(0h0))
when _T_8 :
printf(clock, UInt<1>(0h1), "Assertion failed: Multiple functional units are fighting over the write port.\n at execution-unit.scala:425 assert ((PopCount(iresp_fu_units.map(_.io.resp.valid)) <= 1.U && !div_resp_val) ||\n") : printf
assert(clock, _T_5, UInt<1>(0h1), "") : assert | module ALUExeUnit_2( // @[execution-unit.scala:204:7]
input clock, // @[execution-unit.scala:204:7]
input reset, // @[execution-unit.scala:204:7]
input io_req_valid, // @[execution-unit.scala:104:14]
input [6:0] io_req_bits_uop_uopc, // @[execution-unit.scala:104:14]
input [31:0] io_req_bits_uop_inst, // @[execution-unit.scala:104:14]
input [31:0] io_req_bits_uop_debug_inst, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_rvc, // @[execution-unit.scala:104:14]
input [39:0] io_req_bits_uop_debug_pc, // @[execution-unit.scala:104:14]
input [2:0] io_req_bits_uop_iq_type, // @[execution-unit.scala:104:14]
input [9:0] io_req_bits_uop_fu_code, // @[execution-unit.scala:104:14]
input [3:0] io_req_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
input [2:0] io_req_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
input [2:0] io_req_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
input [4:0] io_req_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
input [2:0] io_req_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_iw_state, // @[execution-unit.scala:104:14]
input io_req_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
input io_req_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_br, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_jalr, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_jal, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_sfb, // @[execution-unit.scala:104:14]
input [7:0] io_req_bits_uop_br_mask, // @[execution-unit.scala:104:14]
input [2:0] io_req_bits_uop_br_tag, // @[execution-unit.scala:104:14]
input [3:0] io_req_bits_uop_ftq_idx, // @[execution-unit.scala:104:14]
input io_req_bits_uop_edge_inst, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_pc_lob, // @[execution-unit.scala:104:14]
input io_req_bits_uop_taken, // @[execution-unit.scala:104:14]
input [19:0] io_req_bits_uop_imm_packed, // @[execution-unit.scala:104:14]
input [11:0] io_req_bits_uop_csr_addr, // @[execution-unit.scala:104:14]
input [4:0] io_req_bits_uop_rob_idx, // @[execution-unit.scala:104:14]
input [2:0] io_req_bits_uop_ldq_idx, // @[execution-unit.scala:104:14]
input [2:0] io_req_bits_uop_stq_idx, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_rxq_idx, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_pdst, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_prs1, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_prs2, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_prs3, // @[execution-unit.scala:104:14]
input [3:0] io_req_bits_uop_ppred, // @[execution-unit.scala:104:14]
input io_req_bits_uop_prs1_busy, // @[execution-unit.scala:104:14]
input io_req_bits_uop_prs2_busy, // @[execution-unit.scala:104:14]
input io_req_bits_uop_prs3_busy, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ppred_busy, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_stale_pdst, // @[execution-unit.scala:104:14]
input io_req_bits_uop_exception, // @[execution-unit.scala:104:14]
input [63:0] io_req_bits_uop_exc_cause, // @[execution-unit.scala:104:14]
input io_req_bits_uop_bypassable, // @[execution-unit.scala:104:14]
input [4:0] io_req_bits_uop_mem_cmd, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_mem_size, // @[execution-unit.scala:104:14]
input io_req_bits_uop_mem_signed, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_fence, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_fencei, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_amo, // @[execution-unit.scala:104:14]
input io_req_bits_uop_uses_ldq, // @[execution-unit.scala:104:14]
input io_req_bits_uop_uses_stq, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
input io_req_bits_uop_is_unique, // @[execution-unit.scala:104:14]
input io_req_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_ldst, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_lrs1, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_lrs2, // @[execution-unit.scala:104:14]
input [5:0] io_req_bits_uop_lrs3, // @[execution-unit.scala:104:14]
input io_req_bits_uop_ldst_val, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_dst_rtype, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
input io_req_bits_uop_frs3_en, // @[execution-unit.scala:104:14]
input io_req_bits_uop_fp_val, // @[execution-unit.scala:104:14]
input io_req_bits_uop_fp_single, // @[execution-unit.scala:104:14]
input io_req_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
input io_req_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
input io_req_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
input io_req_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14]
input io_req_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14]
input [1:0] io_req_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14]
input [64:0] io_req_bits_rs1_data, // @[execution-unit.scala:104:14]
input [64:0] io_req_bits_rs2_data, // @[execution-unit.scala:104:14]
input io_req_bits_kill, // @[execution-unit.scala:104:14]
output io_ll_iresp_valid, // @[execution-unit.scala:104:14]
output [6:0] io_ll_iresp_bits_uop_uopc, // @[execution-unit.scala:104:14]
output [31:0] io_ll_iresp_bits_uop_inst, // @[execution-unit.scala:104:14]
output [31:0] io_ll_iresp_bits_uop_debug_inst, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_is_rvc, // @[execution-unit.scala:104:14]
output [39:0] io_ll_iresp_bits_uop_debug_pc, // @[execution-unit.scala:104:14]
output [2:0] io_ll_iresp_bits_uop_iq_type, // @[execution-unit.scala:104:14]
output [9:0] io_ll_iresp_bits_uop_fu_code, // @[execution-unit.scala:104:14]
output [3:0] io_ll_iresp_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
output [1:0] io_ll_iresp_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
output [2:0] io_ll_iresp_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
output [2:0] io_ll_iresp_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
output [4:0] io_ll_iresp_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
output [2:0] io_ll_iresp_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
output [1:0] io_ll_iresp_bits_uop_iw_state, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_is_br, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_is_jalr, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_is_jal, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_is_sfb, // @[execution-unit.scala:104:14]
output [7:0] io_ll_iresp_bits_uop_br_mask, // @[execution-unit.scala:104:14]
output [2:0] io_ll_iresp_bits_uop_br_tag, // @[execution-unit.scala:104:14]
output [3:0] io_ll_iresp_bits_uop_ftq_idx, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_edge_inst, // @[execution-unit.scala:104:14]
output [5:0] io_ll_iresp_bits_uop_pc_lob, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_taken, // @[execution-unit.scala:104:14]
output [19:0] io_ll_iresp_bits_uop_imm_packed, // @[execution-unit.scala:104:14]
output [11:0] io_ll_iresp_bits_uop_csr_addr, // @[execution-unit.scala:104:14]
output [4:0] io_ll_iresp_bits_uop_rob_idx, // @[execution-unit.scala:104:14]
output [2:0] io_ll_iresp_bits_uop_ldq_idx, // @[execution-unit.scala:104:14]
output [2:0] io_ll_iresp_bits_uop_stq_idx, // @[execution-unit.scala:104:14]
output [1:0] io_ll_iresp_bits_uop_rxq_idx, // @[execution-unit.scala:104:14]
output [5:0] io_ll_iresp_bits_uop_pdst, // @[execution-unit.scala:104:14]
output [5:0] io_ll_iresp_bits_uop_prs1, // @[execution-unit.scala:104:14]
output [5:0] io_ll_iresp_bits_uop_prs2, // @[execution-unit.scala:104:14]
output [5:0] io_ll_iresp_bits_uop_prs3, // @[execution-unit.scala:104:14]
output [3:0] io_ll_iresp_bits_uop_ppred, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_prs1_busy, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_prs2_busy, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_prs3_busy, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_ppred_busy, // @[execution-unit.scala:104:14]
output [5:0] io_ll_iresp_bits_uop_stale_pdst, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_exception, // @[execution-unit.scala:104:14]
output [63:0] io_ll_iresp_bits_uop_exc_cause, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_bypassable, // @[execution-unit.scala:104:14]
output [4:0] io_ll_iresp_bits_uop_mem_cmd, // @[execution-unit.scala:104:14]
output [1:0] io_ll_iresp_bits_uop_mem_size, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_mem_signed, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_is_fence, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_is_fencei, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_is_amo, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_uses_ldq, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_uses_stq, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_is_unique, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
output [5:0] io_ll_iresp_bits_uop_ldst, // @[execution-unit.scala:104:14]
output [5:0] io_ll_iresp_bits_uop_lrs1, // @[execution-unit.scala:104:14]
output [5:0] io_ll_iresp_bits_uop_lrs2, // @[execution-unit.scala:104:14]
output [5:0] io_ll_iresp_bits_uop_lrs3, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_ldst_val, // @[execution-unit.scala:104:14]
output [1:0] io_ll_iresp_bits_uop_dst_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_ll_iresp_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_ll_iresp_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_frs3_en, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_fp_val, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_fp_single, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14]
output io_ll_iresp_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
output [1:0] io_ll_iresp_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14]
output [1:0] io_ll_iresp_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14]
output [64:0] io_ll_iresp_bits_data, // @[execution-unit.scala:104:14]
output io_ll_fresp_valid, // @[execution-unit.scala:104:14]
output [6:0] io_ll_fresp_bits_uop_uopc, // @[execution-unit.scala:104:14]
output [31:0] io_ll_fresp_bits_uop_inst, // @[execution-unit.scala:104:14]
output [31:0] io_ll_fresp_bits_uop_debug_inst, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_is_rvc, // @[execution-unit.scala:104:14]
output [39:0] io_ll_fresp_bits_uop_debug_pc, // @[execution-unit.scala:104:14]
output [2:0] io_ll_fresp_bits_uop_iq_type, // @[execution-unit.scala:104:14]
output [9:0] io_ll_fresp_bits_uop_fu_code, // @[execution-unit.scala:104:14]
output [3:0] io_ll_fresp_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
output [1:0] io_ll_fresp_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
output [2:0] io_ll_fresp_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
output [2:0] io_ll_fresp_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
output [4:0] io_ll_fresp_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
output [2:0] io_ll_fresp_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
output [1:0] io_ll_fresp_bits_uop_iw_state, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_is_br, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_is_jalr, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_is_jal, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_is_sfb, // @[execution-unit.scala:104:14]
output [7:0] io_ll_fresp_bits_uop_br_mask, // @[execution-unit.scala:104:14]
output [2:0] io_ll_fresp_bits_uop_br_tag, // @[execution-unit.scala:104:14]
output [3:0] io_ll_fresp_bits_uop_ftq_idx, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_edge_inst, // @[execution-unit.scala:104:14]
output [5:0] io_ll_fresp_bits_uop_pc_lob, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_taken, // @[execution-unit.scala:104:14]
output [19:0] io_ll_fresp_bits_uop_imm_packed, // @[execution-unit.scala:104:14]
output [11:0] io_ll_fresp_bits_uop_csr_addr, // @[execution-unit.scala:104:14]
output [4:0] io_ll_fresp_bits_uop_rob_idx, // @[execution-unit.scala:104:14]
output [2:0] io_ll_fresp_bits_uop_ldq_idx, // @[execution-unit.scala:104:14]
output [2:0] io_ll_fresp_bits_uop_stq_idx, // @[execution-unit.scala:104:14]
output [1:0] io_ll_fresp_bits_uop_rxq_idx, // @[execution-unit.scala:104:14]
output [5:0] io_ll_fresp_bits_uop_pdst, // @[execution-unit.scala:104:14]
output [5:0] io_ll_fresp_bits_uop_prs1, // @[execution-unit.scala:104:14]
output [5:0] io_ll_fresp_bits_uop_prs2, // @[execution-unit.scala:104:14]
output [5:0] io_ll_fresp_bits_uop_prs3, // @[execution-unit.scala:104:14]
output [3:0] io_ll_fresp_bits_uop_ppred, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_prs1_busy, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_prs2_busy, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_prs3_busy, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_ppred_busy, // @[execution-unit.scala:104:14]
output [5:0] io_ll_fresp_bits_uop_stale_pdst, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_exception, // @[execution-unit.scala:104:14]
output [63:0] io_ll_fresp_bits_uop_exc_cause, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_bypassable, // @[execution-unit.scala:104:14]
output [4:0] io_ll_fresp_bits_uop_mem_cmd, // @[execution-unit.scala:104:14]
output [1:0] io_ll_fresp_bits_uop_mem_size, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_mem_signed, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_is_fence, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_is_fencei, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_is_amo, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_uses_ldq, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_uses_stq, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_is_unique, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
output [5:0] io_ll_fresp_bits_uop_ldst, // @[execution-unit.scala:104:14]
output [5:0] io_ll_fresp_bits_uop_lrs1, // @[execution-unit.scala:104:14]
output [5:0] io_ll_fresp_bits_uop_lrs2, // @[execution-unit.scala:104:14]
output [5:0] io_ll_fresp_bits_uop_lrs3, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_ldst_val, // @[execution-unit.scala:104:14]
output [1:0] io_ll_fresp_bits_uop_dst_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_ll_fresp_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_ll_fresp_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_frs3_en, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_fp_val, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_fp_single, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14]
output io_ll_fresp_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
output [1:0] io_ll_fresp_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14]
output [1:0] io_ll_fresp_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14]
output [64:0] io_ll_fresp_bits_data, // @[execution-unit.scala:104:14]
input [7:0] io_brupdate_b1_resolve_mask, // @[execution-unit.scala:104:14]
input [7:0] io_brupdate_b1_mispredict_mask, // @[execution-unit.scala:104:14]
input [6:0] io_brupdate_b2_uop_uopc, // @[execution-unit.scala:104:14]
input [31:0] io_brupdate_b2_uop_inst, // @[execution-unit.scala:104:14]
input [31:0] io_brupdate_b2_uop_debug_inst, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_rvc, // @[execution-unit.scala:104:14]
input [39:0] io_brupdate_b2_uop_debug_pc, // @[execution-unit.scala:104:14]
input [2:0] io_brupdate_b2_uop_iq_type, // @[execution-unit.scala:104:14]
input [9:0] io_brupdate_b2_uop_fu_code, // @[execution-unit.scala:104:14]
input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_iw_state, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_br, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_jalr, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_jal, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_sfb, // @[execution-unit.scala:104:14]
input [7:0] io_brupdate_b2_uop_br_mask, // @[execution-unit.scala:104:14]
input [2:0] io_brupdate_b2_uop_br_tag, // @[execution-unit.scala:104:14]
input [3:0] io_brupdate_b2_uop_ftq_idx, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_edge_inst, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_pc_lob, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_taken, // @[execution-unit.scala:104:14]
input [19:0] io_brupdate_b2_uop_imm_packed, // @[execution-unit.scala:104:14]
input [11:0] io_brupdate_b2_uop_csr_addr, // @[execution-unit.scala:104:14]
input [4:0] io_brupdate_b2_uop_rob_idx, // @[execution-unit.scala:104:14]
input [2:0] io_brupdate_b2_uop_ldq_idx, // @[execution-unit.scala:104:14]
input [2:0] io_brupdate_b2_uop_stq_idx, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_rxq_idx, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_pdst, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_prs1, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_prs2, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_prs3, // @[execution-unit.scala:104:14]
input [3:0] io_brupdate_b2_uop_ppred, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_prs1_busy, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_prs2_busy, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_prs3_busy, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ppred_busy, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_stale_pdst, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_exception, // @[execution-unit.scala:104:14]
input [63:0] io_brupdate_b2_uop_exc_cause, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_bypassable, // @[execution-unit.scala:104:14]
input [4:0] io_brupdate_b2_uop_mem_cmd, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_mem_size, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_mem_signed, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_fence, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_fencei, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_amo, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_uses_ldq, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_uses_stq, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_is_unique, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_flush_on_commit, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_ldst, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_lrs1, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_lrs2, // @[execution-unit.scala:104:14]
input [5:0] io_brupdate_b2_uop_lrs3, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_ldst_val, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_dst_rtype, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_frs3_en, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_fp_val, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_fp_single, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_bp_debug_if, // @[execution-unit.scala:104:14]
input io_brupdate_b2_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[execution-unit.scala:104:14]
input io_brupdate_b2_valid, // @[execution-unit.scala:104:14]
input io_brupdate_b2_mispredict, // @[execution-unit.scala:104:14]
input io_brupdate_b2_taken, // @[execution-unit.scala:104:14]
input [2:0] io_brupdate_b2_cfi_type, // @[execution-unit.scala:104:14]
input [1:0] io_brupdate_b2_pc_sel, // @[execution-unit.scala:104:14]
input [39:0] io_brupdate_b2_jalr_target, // @[execution-unit.scala:104:14]
input [20:0] io_brupdate_b2_target_offset, // @[execution-unit.scala:104:14]
input io_status_debug, // @[execution-unit.scala:104:14]
input io_status_cease, // @[execution-unit.scala:104:14]
input io_status_wfi, // @[execution-unit.scala:104:14]
input [1:0] io_status_dprv, // @[execution-unit.scala:104:14]
input io_status_dv, // @[execution-unit.scala:104:14]
input [1:0] io_status_prv, // @[execution-unit.scala:104:14]
input io_status_v, // @[execution-unit.scala:104:14]
input io_status_sd, // @[execution-unit.scala:104:14]
input io_status_mpv, // @[execution-unit.scala:104:14]
input io_status_gva, // @[execution-unit.scala:104:14]
input io_status_tsr, // @[execution-unit.scala:104:14]
input io_status_tw, // @[execution-unit.scala:104:14]
input io_status_tvm, // @[execution-unit.scala:104:14]
input io_status_mxr, // @[execution-unit.scala:104:14]
input io_status_sum, // @[execution-unit.scala:104:14]
input io_status_mprv, // @[execution-unit.scala:104:14]
input [1:0] io_status_fs, // @[execution-unit.scala:104:14]
input [1:0] io_status_mpp, // @[execution-unit.scala:104:14]
input io_status_spp, // @[execution-unit.scala:104:14]
input io_status_mpie, // @[execution-unit.scala:104:14]
input io_status_spie, // @[execution-unit.scala:104:14]
input io_status_mie, // @[execution-unit.scala:104:14]
input io_status_sie, // @[execution-unit.scala:104:14]
output io_lsu_io_req_valid, // @[execution-unit.scala:104:14]
output [6:0] io_lsu_io_req_bits_uop_uopc, // @[execution-unit.scala:104:14]
output [31:0] io_lsu_io_req_bits_uop_inst, // @[execution-unit.scala:104:14]
output [31:0] io_lsu_io_req_bits_uop_debug_inst, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_is_rvc, // @[execution-unit.scala:104:14]
output [39:0] io_lsu_io_req_bits_uop_debug_pc, // @[execution-unit.scala:104:14]
output [2:0] io_lsu_io_req_bits_uop_iq_type, // @[execution-unit.scala:104:14]
output [9:0] io_lsu_io_req_bits_uop_fu_code, // @[execution-unit.scala:104:14]
output [3:0] io_lsu_io_req_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
output [1:0] io_lsu_io_req_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
output [2:0] io_lsu_io_req_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
output [2:0] io_lsu_io_req_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
output [4:0] io_lsu_io_req_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
output [2:0] io_lsu_io_req_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
output [1:0] io_lsu_io_req_bits_uop_iw_state, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_is_br, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_is_jalr, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_is_jal, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_is_sfb, // @[execution-unit.scala:104:14]
output [7:0] io_lsu_io_req_bits_uop_br_mask, // @[execution-unit.scala:104:14]
output [2:0] io_lsu_io_req_bits_uop_br_tag, // @[execution-unit.scala:104:14]
output [3:0] io_lsu_io_req_bits_uop_ftq_idx, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_edge_inst, // @[execution-unit.scala:104:14]
output [5:0] io_lsu_io_req_bits_uop_pc_lob, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_taken, // @[execution-unit.scala:104:14]
output [19:0] io_lsu_io_req_bits_uop_imm_packed, // @[execution-unit.scala:104:14]
output [11:0] io_lsu_io_req_bits_uop_csr_addr, // @[execution-unit.scala:104:14]
output [4:0] io_lsu_io_req_bits_uop_rob_idx, // @[execution-unit.scala:104:14]
output [2:0] io_lsu_io_req_bits_uop_ldq_idx, // @[execution-unit.scala:104:14]
output [2:0] io_lsu_io_req_bits_uop_stq_idx, // @[execution-unit.scala:104:14]
output [1:0] io_lsu_io_req_bits_uop_rxq_idx, // @[execution-unit.scala:104:14]
output [5:0] io_lsu_io_req_bits_uop_pdst, // @[execution-unit.scala:104:14]
output [5:0] io_lsu_io_req_bits_uop_prs1, // @[execution-unit.scala:104:14]
output [5:0] io_lsu_io_req_bits_uop_prs2, // @[execution-unit.scala:104:14]
output [5:0] io_lsu_io_req_bits_uop_prs3, // @[execution-unit.scala:104:14]
output [3:0] io_lsu_io_req_bits_uop_ppred, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_prs1_busy, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_prs2_busy, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_prs3_busy, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_ppred_busy, // @[execution-unit.scala:104:14]
output [5:0] io_lsu_io_req_bits_uop_stale_pdst, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_exception, // @[execution-unit.scala:104:14]
output [63:0] io_lsu_io_req_bits_uop_exc_cause, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_bypassable, // @[execution-unit.scala:104:14]
output [4:0] io_lsu_io_req_bits_uop_mem_cmd, // @[execution-unit.scala:104:14]
output [1:0] io_lsu_io_req_bits_uop_mem_size, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_mem_signed, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_is_fence, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_is_fencei, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_is_amo, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_uses_ldq, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_uses_stq, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_is_unique, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
output [5:0] io_lsu_io_req_bits_uop_ldst, // @[execution-unit.scala:104:14]
output [5:0] io_lsu_io_req_bits_uop_lrs1, // @[execution-unit.scala:104:14]
output [5:0] io_lsu_io_req_bits_uop_lrs2, // @[execution-unit.scala:104:14]
output [5:0] io_lsu_io_req_bits_uop_lrs3, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_ldst_val, // @[execution-unit.scala:104:14]
output [1:0] io_lsu_io_req_bits_uop_dst_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_lsu_io_req_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
output [1:0] io_lsu_io_req_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_frs3_en, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_fp_val, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_fp_single, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
output [1:0] io_lsu_io_req_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14]
output [1:0] io_lsu_io_req_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14]
output [63:0] io_lsu_io_req_bits_data, // @[execution-unit.scala:104:14]
output [39:0] io_lsu_io_req_bits_addr, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_mxcpt_valid, // @[execution-unit.scala:104:14]
output [24:0] io_lsu_io_req_bits_mxcpt_bits, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_sfence_valid, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_sfence_bits_rs1, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_sfence_bits_rs2, // @[execution-unit.scala:104:14]
output [38:0] io_lsu_io_req_bits_sfence_bits_addr, // @[execution-unit.scala:104:14]
output io_lsu_io_req_bits_sfence_bits_asid, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_valid, // @[execution-unit.scala:104:14]
input [6:0] io_lsu_io_iresp_bits_uop_uopc, // @[execution-unit.scala:104:14]
input [31:0] io_lsu_io_iresp_bits_uop_inst, // @[execution-unit.scala:104:14]
input [31:0] io_lsu_io_iresp_bits_uop_debug_inst, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_is_rvc, // @[execution-unit.scala:104:14]
input [39:0] io_lsu_io_iresp_bits_uop_debug_pc, // @[execution-unit.scala:104:14]
input [2:0] io_lsu_io_iresp_bits_uop_iq_type, // @[execution-unit.scala:104:14]
input [9:0] io_lsu_io_iresp_bits_uop_fu_code, // @[execution-unit.scala:104:14]
input [3:0] io_lsu_io_iresp_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
input [1:0] io_lsu_io_iresp_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
input [2:0] io_lsu_io_iresp_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
input [2:0] io_lsu_io_iresp_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
input [4:0] io_lsu_io_iresp_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
input [2:0] io_lsu_io_iresp_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
input [1:0] io_lsu_io_iresp_bits_uop_iw_state, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_is_br, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_is_jalr, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_is_jal, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_is_sfb, // @[execution-unit.scala:104:14]
input [7:0] io_lsu_io_iresp_bits_uop_br_mask, // @[execution-unit.scala:104:14]
input [2:0] io_lsu_io_iresp_bits_uop_br_tag, // @[execution-unit.scala:104:14]
input [3:0] io_lsu_io_iresp_bits_uop_ftq_idx, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_edge_inst, // @[execution-unit.scala:104:14]
input [5:0] io_lsu_io_iresp_bits_uop_pc_lob, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_taken, // @[execution-unit.scala:104:14]
input [19:0] io_lsu_io_iresp_bits_uop_imm_packed, // @[execution-unit.scala:104:14]
input [11:0] io_lsu_io_iresp_bits_uop_csr_addr, // @[execution-unit.scala:104:14]
input [4:0] io_lsu_io_iresp_bits_uop_rob_idx, // @[execution-unit.scala:104:14]
input [2:0] io_lsu_io_iresp_bits_uop_ldq_idx, // @[execution-unit.scala:104:14]
input [2:0] io_lsu_io_iresp_bits_uop_stq_idx, // @[execution-unit.scala:104:14]
input [1:0] io_lsu_io_iresp_bits_uop_rxq_idx, // @[execution-unit.scala:104:14]
input [5:0] io_lsu_io_iresp_bits_uop_pdst, // @[execution-unit.scala:104:14]
input [5:0] io_lsu_io_iresp_bits_uop_prs1, // @[execution-unit.scala:104:14]
input [5:0] io_lsu_io_iresp_bits_uop_prs2, // @[execution-unit.scala:104:14]
input [5:0] io_lsu_io_iresp_bits_uop_prs3, // @[execution-unit.scala:104:14]
input [3:0] io_lsu_io_iresp_bits_uop_ppred, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_prs1_busy, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_prs2_busy, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_prs3_busy, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_ppred_busy, // @[execution-unit.scala:104:14]
input [5:0] io_lsu_io_iresp_bits_uop_stale_pdst, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_exception, // @[execution-unit.scala:104:14]
input [63:0] io_lsu_io_iresp_bits_uop_exc_cause, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_bypassable, // @[execution-unit.scala:104:14]
input [4:0] io_lsu_io_iresp_bits_uop_mem_cmd, // @[execution-unit.scala:104:14]
input [1:0] io_lsu_io_iresp_bits_uop_mem_size, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_mem_signed, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_is_fence, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_is_fencei, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_is_amo, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_uses_ldq, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_uses_stq, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_is_unique, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
input [5:0] io_lsu_io_iresp_bits_uop_ldst, // @[execution-unit.scala:104:14]
input [5:0] io_lsu_io_iresp_bits_uop_lrs1, // @[execution-unit.scala:104:14]
input [5:0] io_lsu_io_iresp_bits_uop_lrs2, // @[execution-unit.scala:104:14]
input [5:0] io_lsu_io_iresp_bits_uop_lrs3, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_ldst_val, // @[execution-unit.scala:104:14]
input [1:0] io_lsu_io_iresp_bits_uop_dst_rtype, // @[execution-unit.scala:104:14]
input [1:0] io_lsu_io_iresp_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
input [1:0] io_lsu_io_iresp_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_frs3_en, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_fp_val, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_fp_single, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14]
input io_lsu_io_iresp_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
input [1:0] io_lsu_io_iresp_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14]
input [1:0] io_lsu_io_iresp_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14]
input [63:0] io_lsu_io_iresp_bits_data, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_valid, // @[execution-unit.scala:104:14]
input [6:0] io_lsu_io_fresp_bits_uop_uopc, // @[execution-unit.scala:104:14]
input [31:0] io_lsu_io_fresp_bits_uop_inst, // @[execution-unit.scala:104:14]
input [31:0] io_lsu_io_fresp_bits_uop_debug_inst, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_is_rvc, // @[execution-unit.scala:104:14]
input [39:0] io_lsu_io_fresp_bits_uop_debug_pc, // @[execution-unit.scala:104:14]
input [2:0] io_lsu_io_fresp_bits_uop_iq_type, // @[execution-unit.scala:104:14]
input [9:0] io_lsu_io_fresp_bits_uop_fu_code, // @[execution-unit.scala:104:14]
input [3:0] io_lsu_io_fresp_bits_uop_ctrl_br_type, // @[execution-unit.scala:104:14]
input [1:0] io_lsu_io_fresp_bits_uop_ctrl_op1_sel, // @[execution-unit.scala:104:14]
input [2:0] io_lsu_io_fresp_bits_uop_ctrl_op2_sel, // @[execution-unit.scala:104:14]
input [2:0] io_lsu_io_fresp_bits_uop_ctrl_imm_sel, // @[execution-unit.scala:104:14]
input [4:0] io_lsu_io_fresp_bits_uop_ctrl_op_fcn, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_ctrl_fcn_dw, // @[execution-unit.scala:104:14]
input [2:0] io_lsu_io_fresp_bits_uop_ctrl_csr_cmd, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_ctrl_is_load, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_ctrl_is_sta, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_ctrl_is_std, // @[execution-unit.scala:104:14]
input [1:0] io_lsu_io_fresp_bits_uop_iw_state, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_iw_p1_poisoned, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_iw_p2_poisoned, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_is_br, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_is_jalr, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_is_jal, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_is_sfb, // @[execution-unit.scala:104:14]
input [7:0] io_lsu_io_fresp_bits_uop_br_mask, // @[execution-unit.scala:104:14]
input [2:0] io_lsu_io_fresp_bits_uop_br_tag, // @[execution-unit.scala:104:14]
input [3:0] io_lsu_io_fresp_bits_uop_ftq_idx, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_edge_inst, // @[execution-unit.scala:104:14]
input [5:0] io_lsu_io_fresp_bits_uop_pc_lob, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_taken, // @[execution-unit.scala:104:14]
input [19:0] io_lsu_io_fresp_bits_uop_imm_packed, // @[execution-unit.scala:104:14]
input [11:0] io_lsu_io_fresp_bits_uop_csr_addr, // @[execution-unit.scala:104:14]
input [4:0] io_lsu_io_fresp_bits_uop_rob_idx, // @[execution-unit.scala:104:14]
input [2:0] io_lsu_io_fresp_bits_uop_ldq_idx, // @[execution-unit.scala:104:14]
input [2:0] io_lsu_io_fresp_bits_uop_stq_idx, // @[execution-unit.scala:104:14]
input [1:0] io_lsu_io_fresp_bits_uop_rxq_idx, // @[execution-unit.scala:104:14]
input [5:0] io_lsu_io_fresp_bits_uop_pdst, // @[execution-unit.scala:104:14]
input [5:0] io_lsu_io_fresp_bits_uop_prs1, // @[execution-unit.scala:104:14]
input [5:0] io_lsu_io_fresp_bits_uop_prs2, // @[execution-unit.scala:104:14]
input [5:0] io_lsu_io_fresp_bits_uop_prs3, // @[execution-unit.scala:104:14]
input [3:0] io_lsu_io_fresp_bits_uop_ppred, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_prs1_busy, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_prs2_busy, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_prs3_busy, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_ppred_busy, // @[execution-unit.scala:104:14]
input [5:0] io_lsu_io_fresp_bits_uop_stale_pdst, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_exception, // @[execution-unit.scala:104:14]
input [63:0] io_lsu_io_fresp_bits_uop_exc_cause, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_bypassable, // @[execution-unit.scala:104:14]
input [4:0] io_lsu_io_fresp_bits_uop_mem_cmd, // @[execution-unit.scala:104:14]
input [1:0] io_lsu_io_fresp_bits_uop_mem_size, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_mem_signed, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_is_fence, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_is_fencei, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_is_amo, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_uses_ldq, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_uses_stq, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_is_sys_pc2epc, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_is_unique, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_flush_on_commit, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_ldst_is_rs1, // @[execution-unit.scala:104:14]
input [5:0] io_lsu_io_fresp_bits_uop_ldst, // @[execution-unit.scala:104:14]
input [5:0] io_lsu_io_fresp_bits_uop_lrs1, // @[execution-unit.scala:104:14]
input [5:0] io_lsu_io_fresp_bits_uop_lrs2, // @[execution-unit.scala:104:14]
input [5:0] io_lsu_io_fresp_bits_uop_lrs3, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_ldst_val, // @[execution-unit.scala:104:14]
input [1:0] io_lsu_io_fresp_bits_uop_dst_rtype, // @[execution-unit.scala:104:14]
input [1:0] io_lsu_io_fresp_bits_uop_lrs1_rtype, // @[execution-unit.scala:104:14]
input [1:0] io_lsu_io_fresp_bits_uop_lrs2_rtype, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_frs3_en, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_fp_val, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_fp_single, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_xcpt_pf_if, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_xcpt_ae_if, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_xcpt_ma_if, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_bp_debug_if, // @[execution-unit.scala:104:14]
input io_lsu_io_fresp_bits_uop_bp_xcpt_if, // @[execution-unit.scala:104:14]
input [1:0] io_lsu_io_fresp_bits_uop_debug_fsrc, // @[execution-unit.scala:104:14]
input [1:0] io_lsu_io_fresp_bits_uop_debug_tsrc, // @[execution-unit.scala:104:14]
input [64:0] io_lsu_io_fresp_bits_data, // @[execution-unit.scala:104:14]
input io_com_exception // @[execution-unit.scala:104:14]
);
wire [64:0] _maddrcalc_io_resp_bits_data; // @[execution-unit.scala:388:27]
wire io_req_valid_0 = io_req_valid; // @[execution-unit.scala:204:7]
wire [6:0] io_req_bits_uop_uopc_0 = io_req_bits_uop_uopc; // @[execution-unit.scala:204:7]
wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[execution-unit.scala:204:7]
wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[execution-unit.scala:204:7]
wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[execution-unit.scala:204:7]
wire [2:0] io_req_bits_uop_iq_type_0 = io_req_bits_uop_iq_type; // @[execution-unit.scala:204:7]
wire [9:0] io_req_bits_uop_fu_code_0 = io_req_bits_uop_fu_code; // @[execution-unit.scala:204:7]
wire [3:0] io_req_bits_uop_ctrl_br_type_0 = io_req_bits_uop_ctrl_br_type; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_ctrl_op1_sel_0 = io_req_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:204:7]
wire [2:0] io_req_bits_uop_ctrl_op2_sel_0 = io_req_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:204:7]
wire [2:0] io_req_bits_uop_ctrl_imm_sel_0 = io_req_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:204:7]
wire [4:0] io_req_bits_uop_ctrl_op_fcn_0 = io_req_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_ctrl_fcn_dw_0 = io_req_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:204:7]
wire [2:0] io_req_bits_uop_ctrl_csr_cmd_0 = io_req_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_ctrl_is_load_0 = io_req_bits_uop_ctrl_is_load; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_ctrl_is_sta_0 = io_req_bits_uop_ctrl_is_sta; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_ctrl_is_std_0 = io_req_bits_uop_ctrl_is_std; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_iw_state_0 = io_req_bits_uop_iw_state; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_iw_p1_poisoned_0 = io_req_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_iw_p2_poisoned_0 = io_req_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_br_0 = io_req_bits_uop_is_br; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_jalr_0 = io_req_bits_uop_is_jalr; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_jal_0 = io_req_bits_uop_is_jal; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[execution-unit.scala:204:7]
wire [7:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[execution-unit.scala:204:7]
wire [2:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[execution-unit.scala:204:7]
wire [3:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[execution-unit.scala:204:7]
wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[execution-unit.scala:204:7]
wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[execution-unit.scala:204:7]
wire [11:0] io_req_bits_uop_csr_addr_0 = io_req_bits_uop_csr_addr; // @[execution-unit.scala:204:7]
wire [4:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[execution-unit.scala:204:7]
wire [2:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[execution-unit.scala:204:7]
wire [2:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[execution-unit.scala:204:7]
wire [5:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[execution-unit.scala:204:7]
wire [5:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[execution-unit.scala:204:7]
wire [5:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[execution-unit.scala:204:7]
wire [5:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[execution-unit.scala:204:7]
wire [3:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[execution-unit.scala:204:7]
wire [5:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[execution-unit.scala:204:7]
wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_bypassable_0 = io_req_bits_uop_bypassable; // @[execution-unit.scala:204:7]
wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[execution-unit.scala:204:7]
wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[execution-unit.scala:204:7]
wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[execution-unit.scala:204:7]
wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[execution-unit.scala:204:7]
wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_ldst_val_0 = io_req_bits_uop_ldst_val; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_fp_single_0 = io_req_bits_uop_fp_single; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[execution-unit.scala:204:7]
wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[execution-unit.scala:204:7]
wire [1:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[execution-unit.scala:204:7]
wire [64:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[execution-unit.scala:204:7]
wire [64:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[execution-unit.scala:204:7]
wire io_req_bits_kill_0 = io_req_bits_kill; // @[execution-unit.scala:204:7]
wire [7:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[execution-unit.scala:204:7]
wire [7:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[execution-unit.scala:204:7]
wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[execution-unit.scala:204:7]
wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[execution-unit.scala:204:7]
wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[execution-unit.scala:204:7]
wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[execution-unit.scala:204:7]
wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[execution-unit.scala:204:7]
wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[execution-unit.scala:204:7]
wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[execution-unit.scala:204:7]
wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[execution-unit.scala:204:7]
wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[execution-unit.scala:204:7]
wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[execution-unit.scala:204:7]
wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[execution-unit.scala:204:7]
wire [7:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[execution-unit.scala:204:7]
wire [2:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[execution-unit.scala:204:7]
wire [3:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[execution-unit.scala:204:7]
wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[execution-unit.scala:204:7]
wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[execution-unit.scala:204:7]
wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[execution-unit.scala:204:7]
wire [4:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[execution-unit.scala:204:7]
wire [2:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[execution-unit.scala:204:7]
wire [2:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[execution-unit.scala:204:7]
wire [5:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[execution-unit.scala:204:7]
wire [5:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[execution-unit.scala:204:7]
wire [5:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[execution-unit.scala:204:7]
wire [5:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[execution-unit.scala:204:7]
wire [3:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[execution-unit.scala:204:7]
wire [5:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[execution-unit.scala:204:7]
wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[execution-unit.scala:204:7]
wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[execution-unit.scala:204:7]
wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[execution-unit.scala:204:7]
wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[execution-unit.scala:204:7]
wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[execution-unit.scala:204:7]
wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[execution-unit.scala:204:7]
wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[execution-unit.scala:204:7]
wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[execution-unit.scala:204:7]
wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[execution-unit.scala:204:7]
wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[execution-unit.scala:204:7]
wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[execution-unit.scala:204:7]
wire io_status_debug_0 = io_status_debug; // @[execution-unit.scala:204:7]
wire io_status_cease_0 = io_status_cease; // @[execution-unit.scala:204:7]
wire io_status_wfi_0 = io_status_wfi; // @[execution-unit.scala:204:7]
wire [1:0] io_status_dprv_0 = io_status_dprv; // @[execution-unit.scala:204:7]
wire io_status_dv_0 = io_status_dv; // @[execution-unit.scala:204:7]
wire [1:0] io_status_prv_0 = io_status_prv; // @[execution-unit.scala:204:7]
wire io_status_v_0 = io_status_v; // @[execution-unit.scala:204:7]
wire io_status_sd_0 = io_status_sd; // @[execution-unit.scala:204:7]
wire io_status_mpv_0 = io_status_mpv; // @[execution-unit.scala:204:7]
wire io_status_gva_0 = io_status_gva; // @[execution-unit.scala:204:7]
wire io_status_tsr_0 = io_status_tsr; // @[execution-unit.scala:204:7]
wire io_status_tw_0 = io_status_tw; // @[execution-unit.scala:204:7]
wire io_status_tvm_0 = io_status_tvm; // @[execution-unit.scala:204:7]
wire io_status_mxr_0 = io_status_mxr; // @[execution-unit.scala:204:7]
wire io_status_sum_0 = io_status_sum; // @[execution-unit.scala:204:7]
wire io_status_mprv_0 = io_status_mprv; // @[execution-unit.scala:204:7]
wire [1:0] io_status_fs_0 = io_status_fs; // @[execution-unit.scala:204:7]
wire [1:0] io_status_mpp_0 = io_status_mpp; // @[execution-unit.scala:204:7]
wire io_status_spp_0 = io_status_spp; // @[execution-unit.scala:204:7]
wire io_status_mpie_0 = io_status_mpie; // @[execution-unit.scala:204:7]
wire io_status_spie_0 = io_status_spie; // @[execution-unit.scala:204:7]
wire io_status_mie_0 = io_status_mie; // @[execution-unit.scala:204:7]
wire io_status_sie_0 = io_status_sie; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_valid_0 = io_lsu_io_iresp_valid; // @[execution-unit.scala:204:7]
wire [6:0] io_lsu_io_iresp_bits_uop_uopc_0 = io_lsu_io_iresp_bits_uop_uopc; // @[execution-unit.scala:204:7]
wire [31:0] io_lsu_io_iresp_bits_uop_inst_0 = io_lsu_io_iresp_bits_uop_inst; // @[execution-unit.scala:204:7]
wire [31:0] io_lsu_io_iresp_bits_uop_debug_inst_0 = io_lsu_io_iresp_bits_uop_debug_inst; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_is_rvc_0 = io_lsu_io_iresp_bits_uop_is_rvc; // @[execution-unit.scala:204:7]
wire [39:0] io_lsu_io_iresp_bits_uop_debug_pc_0 = io_lsu_io_iresp_bits_uop_debug_pc; // @[execution-unit.scala:204:7]
wire [2:0] io_lsu_io_iresp_bits_uop_iq_type_0 = io_lsu_io_iresp_bits_uop_iq_type; // @[execution-unit.scala:204:7]
wire [9:0] io_lsu_io_iresp_bits_uop_fu_code_0 = io_lsu_io_iresp_bits_uop_fu_code; // @[execution-unit.scala:204:7]
wire [3:0] io_lsu_io_iresp_bits_uop_ctrl_br_type_0 = io_lsu_io_iresp_bits_uop_ctrl_br_type; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_iresp_bits_uop_ctrl_op1_sel_0 = io_lsu_io_iresp_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:204:7]
wire [2:0] io_lsu_io_iresp_bits_uop_ctrl_op2_sel_0 = io_lsu_io_iresp_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:204:7]
wire [2:0] io_lsu_io_iresp_bits_uop_ctrl_imm_sel_0 = io_lsu_io_iresp_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:204:7]
wire [4:0] io_lsu_io_iresp_bits_uop_ctrl_op_fcn_0 = io_lsu_io_iresp_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_ctrl_fcn_dw_0 = io_lsu_io_iresp_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:204:7]
wire [2:0] io_lsu_io_iresp_bits_uop_ctrl_csr_cmd_0 = io_lsu_io_iresp_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_ctrl_is_load_0 = io_lsu_io_iresp_bits_uop_ctrl_is_load; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_ctrl_is_sta_0 = io_lsu_io_iresp_bits_uop_ctrl_is_sta; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_ctrl_is_std_0 = io_lsu_io_iresp_bits_uop_ctrl_is_std; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_iresp_bits_uop_iw_state_0 = io_lsu_io_iresp_bits_uop_iw_state; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_iw_p1_poisoned_0 = io_lsu_io_iresp_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_iw_p2_poisoned_0 = io_lsu_io_iresp_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_is_br_0 = io_lsu_io_iresp_bits_uop_is_br; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_is_jalr_0 = io_lsu_io_iresp_bits_uop_is_jalr; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_is_jal_0 = io_lsu_io_iresp_bits_uop_is_jal; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_is_sfb_0 = io_lsu_io_iresp_bits_uop_is_sfb; // @[execution-unit.scala:204:7]
wire [7:0] io_lsu_io_iresp_bits_uop_br_mask_0 = io_lsu_io_iresp_bits_uop_br_mask; // @[execution-unit.scala:204:7]
wire [2:0] io_lsu_io_iresp_bits_uop_br_tag_0 = io_lsu_io_iresp_bits_uop_br_tag; // @[execution-unit.scala:204:7]
wire [3:0] io_lsu_io_iresp_bits_uop_ftq_idx_0 = io_lsu_io_iresp_bits_uop_ftq_idx; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_edge_inst_0 = io_lsu_io_iresp_bits_uop_edge_inst; // @[execution-unit.scala:204:7]
wire [5:0] io_lsu_io_iresp_bits_uop_pc_lob_0 = io_lsu_io_iresp_bits_uop_pc_lob; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_taken_0 = io_lsu_io_iresp_bits_uop_taken; // @[execution-unit.scala:204:7]
wire [19:0] io_lsu_io_iresp_bits_uop_imm_packed_0 = io_lsu_io_iresp_bits_uop_imm_packed; // @[execution-unit.scala:204:7]
wire [11:0] io_lsu_io_iresp_bits_uop_csr_addr_0 = io_lsu_io_iresp_bits_uop_csr_addr; // @[execution-unit.scala:204:7]
wire [4:0] io_lsu_io_iresp_bits_uop_rob_idx_0 = io_lsu_io_iresp_bits_uop_rob_idx; // @[execution-unit.scala:204:7]
wire [2:0] io_lsu_io_iresp_bits_uop_ldq_idx_0 = io_lsu_io_iresp_bits_uop_ldq_idx; // @[execution-unit.scala:204:7]
wire [2:0] io_lsu_io_iresp_bits_uop_stq_idx_0 = io_lsu_io_iresp_bits_uop_stq_idx; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_iresp_bits_uop_rxq_idx_0 = io_lsu_io_iresp_bits_uop_rxq_idx; // @[execution-unit.scala:204:7]
wire [5:0] io_lsu_io_iresp_bits_uop_pdst_0 = io_lsu_io_iresp_bits_uop_pdst; // @[execution-unit.scala:204:7]
wire [5:0] io_lsu_io_iresp_bits_uop_prs1_0 = io_lsu_io_iresp_bits_uop_prs1; // @[execution-unit.scala:204:7]
wire [5:0] io_lsu_io_iresp_bits_uop_prs2_0 = io_lsu_io_iresp_bits_uop_prs2; // @[execution-unit.scala:204:7]
wire [5:0] io_lsu_io_iresp_bits_uop_prs3_0 = io_lsu_io_iresp_bits_uop_prs3; // @[execution-unit.scala:204:7]
wire [3:0] io_lsu_io_iresp_bits_uop_ppred_0 = io_lsu_io_iresp_bits_uop_ppred; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_prs1_busy_0 = io_lsu_io_iresp_bits_uop_prs1_busy; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_prs2_busy_0 = io_lsu_io_iresp_bits_uop_prs2_busy; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_prs3_busy_0 = io_lsu_io_iresp_bits_uop_prs3_busy; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_ppred_busy_0 = io_lsu_io_iresp_bits_uop_ppred_busy; // @[execution-unit.scala:204:7]
wire [5:0] io_lsu_io_iresp_bits_uop_stale_pdst_0 = io_lsu_io_iresp_bits_uop_stale_pdst; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_exception_0 = io_lsu_io_iresp_bits_uop_exception; // @[execution-unit.scala:204:7]
wire [63:0] io_lsu_io_iresp_bits_uop_exc_cause_0 = io_lsu_io_iresp_bits_uop_exc_cause; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_bypassable_0 = io_lsu_io_iresp_bits_uop_bypassable; // @[execution-unit.scala:204:7]
wire [4:0] io_lsu_io_iresp_bits_uop_mem_cmd_0 = io_lsu_io_iresp_bits_uop_mem_cmd; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_iresp_bits_uop_mem_size_0 = io_lsu_io_iresp_bits_uop_mem_size; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_mem_signed_0 = io_lsu_io_iresp_bits_uop_mem_signed; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_is_fence_0 = io_lsu_io_iresp_bits_uop_is_fence; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_is_fencei_0 = io_lsu_io_iresp_bits_uop_is_fencei; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_is_amo_0 = io_lsu_io_iresp_bits_uop_is_amo; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_uses_ldq_0 = io_lsu_io_iresp_bits_uop_uses_ldq; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_uses_stq_0 = io_lsu_io_iresp_bits_uop_uses_stq; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_is_sys_pc2epc_0 = io_lsu_io_iresp_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_is_unique_0 = io_lsu_io_iresp_bits_uop_is_unique; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_flush_on_commit_0 = io_lsu_io_iresp_bits_uop_flush_on_commit; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_ldst_is_rs1_0 = io_lsu_io_iresp_bits_uop_ldst_is_rs1; // @[execution-unit.scala:204:7]
wire [5:0] io_lsu_io_iresp_bits_uop_ldst_0 = io_lsu_io_iresp_bits_uop_ldst; // @[execution-unit.scala:204:7]
wire [5:0] io_lsu_io_iresp_bits_uop_lrs1_0 = io_lsu_io_iresp_bits_uop_lrs1; // @[execution-unit.scala:204:7]
wire [5:0] io_lsu_io_iresp_bits_uop_lrs2_0 = io_lsu_io_iresp_bits_uop_lrs2; // @[execution-unit.scala:204:7]
wire [5:0] io_lsu_io_iresp_bits_uop_lrs3_0 = io_lsu_io_iresp_bits_uop_lrs3; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_ldst_val_0 = io_lsu_io_iresp_bits_uop_ldst_val; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_iresp_bits_uop_dst_rtype_0 = io_lsu_io_iresp_bits_uop_dst_rtype; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_iresp_bits_uop_lrs1_rtype_0 = io_lsu_io_iresp_bits_uop_lrs1_rtype; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_iresp_bits_uop_lrs2_rtype_0 = io_lsu_io_iresp_bits_uop_lrs2_rtype; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_frs3_en_0 = io_lsu_io_iresp_bits_uop_frs3_en; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_fp_val_0 = io_lsu_io_iresp_bits_uop_fp_val; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_fp_single_0 = io_lsu_io_iresp_bits_uop_fp_single; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_xcpt_pf_if_0 = io_lsu_io_iresp_bits_uop_xcpt_pf_if; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_xcpt_ae_if_0 = io_lsu_io_iresp_bits_uop_xcpt_ae_if; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_xcpt_ma_if_0 = io_lsu_io_iresp_bits_uop_xcpt_ma_if; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_bp_debug_if_0 = io_lsu_io_iresp_bits_uop_bp_debug_if; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_uop_bp_xcpt_if_0 = io_lsu_io_iresp_bits_uop_bp_xcpt_if; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_iresp_bits_uop_debug_fsrc_0 = io_lsu_io_iresp_bits_uop_debug_fsrc; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_iresp_bits_uop_debug_tsrc_0 = io_lsu_io_iresp_bits_uop_debug_tsrc; // @[execution-unit.scala:204:7]
wire [63:0] io_lsu_io_iresp_bits_data_0 = io_lsu_io_iresp_bits_data; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_valid_0 = io_lsu_io_fresp_valid; // @[execution-unit.scala:204:7]
wire [6:0] io_lsu_io_fresp_bits_uop_uopc_0 = io_lsu_io_fresp_bits_uop_uopc; // @[execution-unit.scala:204:7]
wire [31:0] io_lsu_io_fresp_bits_uop_inst_0 = io_lsu_io_fresp_bits_uop_inst; // @[execution-unit.scala:204:7]
wire [31:0] io_lsu_io_fresp_bits_uop_debug_inst_0 = io_lsu_io_fresp_bits_uop_debug_inst; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_is_rvc_0 = io_lsu_io_fresp_bits_uop_is_rvc; // @[execution-unit.scala:204:7]
wire [39:0] io_lsu_io_fresp_bits_uop_debug_pc_0 = io_lsu_io_fresp_bits_uop_debug_pc; // @[execution-unit.scala:204:7]
wire [2:0] io_lsu_io_fresp_bits_uop_iq_type_0 = io_lsu_io_fresp_bits_uop_iq_type; // @[execution-unit.scala:204:7]
wire [9:0] io_lsu_io_fresp_bits_uop_fu_code_0 = io_lsu_io_fresp_bits_uop_fu_code; // @[execution-unit.scala:204:7]
wire [3:0] io_lsu_io_fresp_bits_uop_ctrl_br_type_0 = io_lsu_io_fresp_bits_uop_ctrl_br_type; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_fresp_bits_uop_ctrl_op1_sel_0 = io_lsu_io_fresp_bits_uop_ctrl_op1_sel; // @[execution-unit.scala:204:7]
wire [2:0] io_lsu_io_fresp_bits_uop_ctrl_op2_sel_0 = io_lsu_io_fresp_bits_uop_ctrl_op2_sel; // @[execution-unit.scala:204:7]
wire [2:0] io_lsu_io_fresp_bits_uop_ctrl_imm_sel_0 = io_lsu_io_fresp_bits_uop_ctrl_imm_sel; // @[execution-unit.scala:204:7]
wire [4:0] io_lsu_io_fresp_bits_uop_ctrl_op_fcn_0 = io_lsu_io_fresp_bits_uop_ctrl_op_fcn; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_ctrl_fcn_dw_0 = io_lsu_io_fresp_bits_uop_ctrl_fcn_dw; // @[execution-unit.scala:204:7]
wire [2:0] io_lsu_io_fresp_bits_uop_ctrl_csr_cmd_0 = io_lsu_io_fresp_bits_uop_ctrl_csr_cmd; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_ctrl_is_load_0 = io_lsu_io_fresp_bits_uop_ctrl_is_load; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_ctrl_is_sta_0 = io_lsu_io_fresp_bits_uop_ctrl_is_sta; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_ctrl_is_std_0 = io_lsu_io_fresp_bits_uop_ctrl_is_std; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_fresp_bits_uop_iw_state_0 = io_lsu_io_fresp_bits_uop_iw_state; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_iw_p1_poisoned_0 = io_lsu_io_fresp_bits_uop_iw_p1_poisoned; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_iw_p2_poisoned_0 = io_lsu_io_fresp_bits_uop_iw_p2_poisoned; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_is_br_0 = io_lsu_io_fresp_bits_uop_is_br; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_is_jalr_0 = io_lsu_io_fresp_bits_uop_is_jalr; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_is_jal_0 = io_lsu_io_fresp_bits_uop_is_jal; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_is_sfb_0 = io_lsu_io_fresp_bits_uop_is_sfb; // @[execution-unit.scala:204:7]
wire [7:0] io_lsu_io_fresp_bits_uop_br_mask_0 = io_lsu_io_fresp_bits_uop_br_mask; // @[execution-unit.scala:204:7]
wire [2:0] io_lsu_io_fresp_bits_uop_br_tag_0 = io_lsu_io_fresp_bits_uop_br_tag; // @[execution-unit.scala:204:7]
wire [3:0] io_lsu_io_fresp_bits_uop_ftq_idx_0 = io_lsu_io_fresp_bits_uop_ftq_idx; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_edge_inst_0 = io_lsu_io_fresp_bits_uop_edge_inst; // @[execution-unit.scala:204:7]
wire [5:0] io_lsu_io_fresp_bits_uop_pc_lob_0 = io_lsu_io_fresp_bits_uop_pc_lob; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_taken_0 = io_lsu_io_fresp_bits_uop_taken; // @[execution-unit.scala:204:7]
wire [19:0] io_lsu_io_fresp_bits_uop_imm_packed_0 = io_lsu_io_fresp_bits_uop_imm_packed; // @[execution-unit.scala:204:7]
wire [11:0] io_lsu_io_fresp_bits_uop_csr_addr_0 = io_lsu_io_fresp_bits_uop_csr_addr; // @[execution-unit.scala:204:7]
wire [4:0] io_lsu_io_fresp_bits_uop_rob_idx_0 = io_lsu_io_fresp_bits_uop_rob_idx; // @[execution-unit.scala:204:7]
wire [2:0] io_lsu_io_fresp_bits_uop_ldq_idx_0 = io_lsu_io_fresp_bits_uop_ldq_idx; // @[execution-unit.scala:204:7]
wire [2:0] io_lsu_io_fresp_bits_uop_stq_idx_0 = io_lsu_io_fresp_bits_uop_stq_idx; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_fresp_bits_uop_rxq_idx_0 = io_lsu_io_fresp_bits_uop_rxq_idx; // @[execution-unit.scala:204:7]
wire [5:0] io_lsu_io_fresp_bits_uop_pdst_0 = io_lsu_io_fresp_bits_uop_pdst; // @[execution-unit.scala:204:7]
wire [5:0] io_lsu_io_fresp_bits_uop_prs1_0 = io_lsu_io_fresp_bits_uop_prs1; // @[execution-unit.scala:204:7]
wire [5:0] io_lsu_io_fresp_bits_uop_prs2_0 = io_lsu_io_fresp_bits_uop_prs2; // @[execution-unit.scala:204:7]
wire [5:0] io_lsu_io_fresp_bits_uop_prs3_0 = io_lsu_io_fresp_bits_uop_prs3; // @[execution-unit.scala:204:7]
wire [3:0] io_lsu_io_fresp_bits_uop_ppred_0 = io_lsu_io_fresp_bits_uop_ppred; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_prs1_busy_0 = io_lsu_io_fresp_bits_uop_prs1_busy; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_prs2_busy_0 = io_lsu_io_fresp_bits_uop_prs2_busy; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_prs3_busy_0 = io_lsu_io_fresp_bits_uop_prs3_busy; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_ppred_busy_0 = io_lsu_io_fresp_bits_uop_ppred_busy; // @[execution-unit.scala:204:7]
wire [5:0] io_lsu_io_fresp_bits_uop_stale_pdst_0 = io_lsu_io_fresp_bits_uop_stale_pdst; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_exception_0 = io_lsu_io_fresp_bits_uop_exception; // @[execution-unit.scala:204:7]
wire [63:0] io_lsu_io_fresp_bits_uop_exc_cause_0 = io_lsu_io_fresp_bits_uop_exc_cause; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_bypassable_0 = io_lsu_io_fresp_bits_uop_bypassable; // @[execution-unit.scala:204:7]
wire [4:0] io_lsu_io_fresp_bits_uop_mem_cmd_0 = io_lsu_io_fresp_bits_uop_mem_cmd; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_fresp_bits_uop_mem_size_0 = io_lsu_io_fresp_bits_uop_mem_size; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_mem_signed_0 = io_lsu_io_fresp_bits_uop_mem_signed; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_is_fence_0 = io_lsu_io_fresp_bits_uop_is_fence; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_is_fencei_0 = io_lsu_io_fresp_bits_uop_is_fencei; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_is_amo_0 = io_lsu_io_fresp_bits_uop_is_amo; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_uses_ldq_0 = io_lsu_io_fresp_bits_uop_uses_ldq; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_uses_stq_0 = io_lsu_io_fresp_bits_uop_uses_stq; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_is_sys_pc2epc_0 = io_lsu_io_fresp_bits_uop_is_sys_pc2epc; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_is_unique_0 = io_lsu_io_fresp_bits_uop_is_unique; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_flush_on_commit_0 = io_lsu_io_fresp_bits_uop_flush_on_commit; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_ldst_is_rs1_0 = io_lsu_io_fresp_bits_uop_ldst_is_rs1; // @[execution-unit.scala:204:7]
wire [5:0] io_lsu_io_fresp_bits_uop_ldst_0 = io_lsu_io_fresp_bits_uop_ldst; // @[execution-unit.scala:204:7]
wire [5:0] io_lsu_io_fresp_bits_uop_lrs1_0 = io_lsu_io_fresp_bits_uop_lrs1; // @[execution-unit.scala:204:7]
wire [5:0] io_lsu_io_fresp_bits_uop_lrs2_0 = io_lsu_io_fresp_bits_uop_lrs2; // @[execution-unit.scala:204:7]
wire [5:0] io_lsu_io_fresp_bits_uop_lrs3_0 = io_lsu_io_fresp_bits_uop_lrs3; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_ldst_val_0 = io_lsu_io_fresp_bits_uop_ldst_val; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_fresp_bits_uop_dst_rtype_0 = io_lsu_io_fresp_bits_uop_dst_rtype; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_fresp_bits_uop_lrs1_rtype_0 = io_lsu_io_fresp_bits_uop_lrs1_rtype; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_fresp_bits_uop_lrs2_rtype_0 = io_lsu_io_fresp_bits_uop_lrs2_rtype; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_frs3_en_0 = io_lsu_io_fresp_bits_uop_frs3_en; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_fp_val_0 = io_lsu_io_fresp_bits_uop_fp_val; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_fp_single_0 = io_lsu_io_fresp_bits_uop_fp_single; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_xcpt_pf_if_0 = io_lsu_io_fresp_bits_uop_xcpt_pf_if; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_xcpt_ae_if_0 = io_lsu_io_fresp_bits_uop_xcpt_ae_if; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_xcpt_ma_if_0 = io_lsu_io_fresp_bits_uop_xcpt_ma_if; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_bp_debug_if_0 = io_lsu_io_fresp_bits_uop_bp_debug_if; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_uop_bp_xcpt_if_0 = io_lsu_io_fresp_bits_uop_bp_xcpt_if; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_fresp_bits_uop_debug_fsrc_0 = io_lsu_io_fresp_bits_uop_debug_fsrc; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_fresp_bits_uop_debug_tsrc_0 = io_lsu_io_fresp_bits_uop_debug_tsrc; // @[execution-unit.scala:204:7]
wire [64:0] io_lsu_io_fresp_bits_data_0 = io_lsu_io_fresp_bits_data; // @[execution-unit.scala:204:7]
wire io_com_exception_0 = io_com_exception; // @[execution-unit.scala:204:7]
wire [1:0] io_status_sxl = 2'h2; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [1:0] io_status_uxl = 2'h2; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [63:0] io_ll_iresp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [63:0] io_ll_fresp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [63:0] io_lsu_io_req_bits_fflags_bits_uop_exc_cause = 64'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [63:0] io_lsu_io_iresp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [63:0] io_lsu_io_fresp_bits_fflags_bits_uop_exc_cause = 64'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [11:0] io_ll_iresp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [11:0] io_ll_fresp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [11:0] io_lsu_io_req_bits_fflags_bits_uop_csr_addr = 12'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [11:0] io_lsu_io_iresp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [11:0] io_lsu_io_fresp_bits_fflags_bits_uop_csr_addr = 12'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [19:0] io_ll_iresp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [19:0] io_ll_fresp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [19:0] io_lsu_io_req_bits_fflags_bits_uop_imm_packed = 20'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [19:0] io_lsu_io_iresp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [19:0] io_lsu_io_fresp_bits_fflags_bits_uop_imm_packed = 20'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_ll_iresp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_ll_iresp_bits_fflags_bits_uop_pdst = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_ll_iresp_bits_fflags_bits_uop_prs1 = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_ll_iresp_bits_fflags_bits_uop_prs2 = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_ll_iresp_bits_fflags_bits_uop_prs3 = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_ll_iresp_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_ll_iresp_bits_fflags_bits_uop_ldst = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_ll_iresp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_ll_iresp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_ll_iresp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_ll_fresp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_ll_fresp_bits_fflags_bits_uop_pdst = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_ll_fresp_bits_fflags_bits_uop_prs1 = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_ll_fresp_bits_fflags_bits_uop_prs2 = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_ll_fresp_bits_fflags_bits_uop_prs3 = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_ll_fresp_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_ll_fresp_bits_fflags_bits_uop_ldst = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_ll_fresp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_ll_fresp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_ll_fresp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_lsu_io_req_bits_fflags_bits_uop_pc_lob = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_lsu_io_req_bits_fflags_bits_uop_pdst = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_lsu_io_req_bits_fflags_bits_uop_prs1 = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_lsu_io_req_bits_fflags_bits_uop_prs2 = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_lsu_io_req_bits_fflags_bits_uop_prs3 = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_lsu_io_req_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_lsu_io_req_bits_fflags_bits_uop_ldst = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_lsu_io_req_bits_fflags_bits_uop_lrs1 = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_lsu_io_req_bits_fflags_bits_uop_lrs2 = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_lsu_io_req_bits_fflags_bits_uop_lrs3 = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_lsu_io_iresp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_lsu_io_iresp_bits_fflags_bits_uop_pdst = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_lsu_io_iresp_bits_fflags_bits_uop_prs1 = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_lsu_io_iresp_bits_fflags_bits_uop_prs2 = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_lsu_io_iresp_bits_fflags_bits_uop_prs3 = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_lsu_io_iresp_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_lsu_io_iresp_bits_fflags_bits_uop_ldst = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_lsu_io_iresp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_lsu_io_iresp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_lsu_io_iresp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_lsu_io_fresp_bits_fflags_bits_uop_pc_lob = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_lsu_io_fresp_bits_fflags_bits_uop_pdst = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_lsu_io_fresp_bits_fflags_bits_uop_prs1 = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_lsu_io_fresp_bits_fflags_bits_uop_prs2 = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_lsu_io_fresp_bits_fflags_bits_uop_prs3 = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_lsu_io_fresp_bits_fflags_bits_uop_stale_pdst = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_lsu_io_fresp_bits_fflags_bits_uop_ldst = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_lsu_io_fresp_bits_fflags_bits_uop_lrs1 = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_lsu_io_fresp_bits_fflags_bits_uop_lrs2 = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [5:0] io_lsu_io_fresp_bits_fflags_bits_uop_lrs3 = 6'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [4:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [4:0] io_ll_iresp_bits_fflags_bits_uop_rob_idx = 5'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [4:0] io_ll_iresp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [4:0] io_ll_iresp_bits_fflags_bits_flags = 5'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [4:0] io_ll_fresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [4:0] io_ll_fresp_bits_fflags_bits_uop_rob_idx = 5'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [4:0] io_ll_fresp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [4:0] io_ll_fresp_bits_fflags_bits_flags = 5'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [4:0] io_lsu_io_req_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [4:0] io_lsu_io_req_bits_fflags_bits_uop_rob_idx = 5'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [4:0] io_lsu_io_req_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [4:0] io_lsu_io_req_bits_fflags_bits_flags = 5'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [4:0] io_lsu_io_iresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [4:0] io_lsu_io_iresp_bits_fflags_bits_uop_rob_idx = 5'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [4:0] io_lsu_io_iresp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [4:0] io_lsu_io_iresp_bits_fflags_bits_flags = 5'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [4:0] io_lsu_io_fresp_bits_fflags_bits_uop_ctrl_op_fcn = 5'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [4:0] io_lsu_io_fresp_bits_fflags_bits_uop_rob_idx = 5'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [4:0] io_lsu_io_fresp_bits_fflags_bits_uop_mem_cmd = 5'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [4:0] io_lsu_io_fresp_bits_fflags_bits_flags = 5'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [3:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [3:0] io_ll_iresp_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [3:0] io_ll_iresp_bits_fflags_bits_uop_ppred = 4'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [3:0] io_ll_fresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [3:0] io_ll_fresp_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [3:0] io_ll_fresp_bits_fflags_bits_uop_ppred = 4'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [3:0] io_lsu_io_req_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [3:0] io_lsu_io_req_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [3:0] io_lsu_io_req_bits_fflags_bits_uop_ppred = 4'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [3:0] io_lsu_io_iresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [3:0] io_lsu_io_iresp_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [3:0] io_lsu_io_iresp_bits_fflags_bits_uop_ppred = 4'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [3:0] io_lsu_io_fresp_bits_fflags_bits_uop_ctrl_br_type = 4'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [3:0] io_lsu_io_fresp_bits_fflags_bits_uop_ftq_idx = 4'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [3:0] io_lsu_io_fresp_bits_fflags_bits_uop_ppred = 4'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [9:0] io_ll_iresp_bits_fflags_bits_uop_fu_code = 10'h0; // @[execution-unit.scala:204:7]
wire [9:0] io_ll_fresp_bits_fflags_bits_uop_fu_code = 10'h0; // @[execution-unit.scala:204:7]
wire [9:0] io_lsu_io_req_bits_fflags_bits_uop_fu_code = 10'h0; // @[execution-unit.scala:204:7]
wire [9:0] io_lsu_io_iresp_bits_fflags_bits_uop_fu_code = 10'h0; // @[execution-unit.scala:204:7]
wire [9:0] io_lsu_io_fresp_bits_fflags_bits_uop_fu_code = 10'h0; // @[execution-unit.scala:204:7]
wire [9:0] _io_fu_types_T = 10'h0; // @[execution-unit.scala:260:21]
wire [9:0] _io_fu_types_T_1 = 10'h0; // @[execution-unit.scala:261:21]
wire [9:0] _io_fu_types_T_2 = 10'h0; // @[execution-unit.scala:260:45]
wire [9:0] _io_fu_types_T_5 = 10'h0; // @[execution-unit.scala:262:21]
wire [9:0] _io_fu_types_T_6 = 10'h0; // @[execution-unit.scala:261:45]
wire [9:0] _io_fu_types_T_7 = 10'h0; // @[execution-unit.scala:263:21]
wire [9:0] _io_fu_types_T_8 = 10'h0; // @[execution-unit.scala:262:58]
wire [9:0] _io_fu_types_T_9 = 10'h0; // @[execution-unit.scala:264:21]
wire [9:0] _io_fu_types_T_10 = 10'h0; // @[execution-unit.scala:263:45]
wire [9:0] _io_fu_types_T_13 = 10'h0; // @[execution-unit.scala:265:21]
wire [9:0] _io_fu_types_T_14 = 10'h0; // @[execution-unit.scala:264:49]
wire [2:0] io_ll_iresp_bits_fflags_bits_uop_iq_type = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_ll_iresp_bits_fflags_bits_uop_br_tag = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_ll_iresp_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_ll_iresp_bits_fflags_bits_uop_stq_idx = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_ll_fresp_bits_fflags_bits_uop_iq_type = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_ll_fresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_ll_fresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_ll_fresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_ll_fresp_bits_fflags_bits_uop_br_tag = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_ll_fresp_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_ll_fresp_bits_fflags_bits_uop_stq_idx = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_lsu_io_req_bits_fflags_bits_uop_iq_type = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_lsu_io_req_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_lsu_io_req_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_lsu_io_req_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_lsu_io_req_bits_fflags_bits_uop_br_tag = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_lsu_io_req_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_lsu_io_req_bits_fflags_bits_uop_stq_idx = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_lsu_io_iresp_bits_fflags_bits_uop_iq_type = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_lsu_io_iresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_lsu_io_iresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_lsu_io_iresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_lsu_io_iresp_bits_fflags_bits_uop_br_tag = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_lsu_io_iresp_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_lsu_io_iresp_bits_fflags_bits_uop_stq_idx = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_lsu_io_fresp_bits_fflags_bits_uop_iq_type = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_lsu_io_fresp_bits_fflags_bits_uop_ctrl_op2_sel = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_lsu_io_fresp_bits_fflags_bits_uop_ctrl_imm_sel = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_lsu_io_fresp_bits_fflags_bits_uop_ctrl_csr_cmd = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_lsu_io_fresp_bits_fflags_bits_uop_br_tag = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_lsu_io_fresp_bits_fflags_bits_uop_ldq_idx = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [2:0] io_lsu_io_fresp_bits_fflags_bits_uop_stq_idx = 3'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [39:0] io_ll_iresp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [39:0] io_ll_fresp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [39:0] io_lsu_io_req_bits_fflags_bits_uop_debug_pc = 40'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [39:0] io_lsu_io_iresp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [39:0] io_lsu_io_fresp_bits_fflags_bits_uop_debug_pc = 40'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [31:0] io_ll_iresp_bits_fflags_bits_uop_inst = 32'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [31:0] io_ll_iresp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [31:0] io_ll_fresp_bits_fflags_bits_uop_inst = 32'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [31:0] io_ll_fresp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [31:0] io_lsu_io_req_bits_fflags_bits_uop_inst = 32'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [31:0] io_lsu_io_req_bits_fflags_bits_uop_debug_inst = 32'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [31:0] io_lsu_io_iresp_bits_fflags_bits_uop_inst = 32'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [31:0] io_lsu_io_iresp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [31:0] io_lsu_io_fresp_bits_fflags_bits_uop_inst = 32'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [31:0] io_lsu_io_fresp_bits_fflags_bits_uop_debug_inst = 32'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [6:0] io_ll_iresp_bits_fflags_bits_uop_uopc = 7'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [6:0] io_ll_fresp_bits_fflags_bits_uop_uopc = 7'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [6:0] io_lsu_io_req_bits_fflags_bits_uop_uopc = 7'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [6:0] io_lsu_io_iresp_bits_fflags_bits_uop_uopc = 7'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [6:0] io_lsu_io_fresp_bits_fflags_bits_uop_uopc = 7'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [64:0] io_req_bits_rs3_data = 65'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire io_req_ready = 1'h1; // @[execution-unit.scala:104:14, :204:7, :262:22, :265:22, :388:27, :425:83]
wire io_ll_iresp_ready = 1'h1; // @[execution-unit.scala:104:14, :204:7, :262:22, :265:22, :388:27, :425:83]
wire io_ll_fresp_ready = 1'h1; // @[execution-unit.scala:104:14, :204:7, :262:22, :265:22, :388:27, :425:83]
wire io_lsu_io_iresp_ready = 1'h1; // @[execution-unit.scala:104:14, :204:7, :262:22, :265:22, :388:27, :425:83]
wire io_lsu_io_fresp_ready = 1'h1; // @[execution-unit.scala:104:14, :204:7, :262:22, :265:22, :388:27, :425:83]
wire _io_fu_types_T_3 = 1'h1; // @[execution-unit.scala:104:14, :204:7, :262:22, :265:22, :388:27, :425:83]
wire _io_fu_types_T_11 = 1'h1; // @[execution-unit.scala:104:14, :204:7, :262:22, :265:22, :388:27, :425:83]
wire [9:0] io_fu_types = 10'h4; // @[execution-unit.scala:204:7]
wire [9:0] _io_fu_types_T_15 = 10'h4; // @[execution-unit.scala:266:21]
wire [9:0] _io_fu_types_T_16 = 10'h4; // @[execution-unit.scala:265:60]
wire [1:0] io_ll_iresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_iresp_bits_fflags_bits_uop_iw_state = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_iresp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_iresp_bits_fflags_bits_uop_mem_size = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_iresp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_iresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_iresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_iresp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_iresp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_fflags_bits_uop_iw_state = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_fflags_bits_uop_mem_size = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_status_xs = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_status_vs = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_req_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_req_bits_fflags_bits_uop_iw_state = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_req_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_req_bits_fflags_bits_uop_mem_size = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_req_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_req_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_req_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_req_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_req_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_iresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_iresp_bits_fflags_bits_uop_iw_state = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_iresp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_iresp_bits_fflags_bits_uop_mem_size = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_iresp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_iresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_iresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_iresp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_iresp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_fresp_bits_fflags_bits_uop_ctrl_op1_sel = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_fresp_bits_fflags_bits_uop_iw_state = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_fresp_bits_fflags_bits_uop_rxq_idx = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_fresp_bits_fflags_bits_uop_mem_size = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_fresp_bits_fflags_bits_uop_dst_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_fresp_bits_fflags_bits_uop_lrs1_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_fresp_bits_fflags_bits_uop_lrs2_rtype = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_fresp_bits_fflags_bits_uop_debug_fsrc = 2'h0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_fresp_bits_fflags_bits_uop_debug_tsrc = 2'h0; // @[execution-unit.scala:204:7]
wire [7:0] io_ll_iresp_bits_fflags_bits_uop_br_mask = 8'h0; // @[execution-unit.scala:204:7]
wire [7:0] io_ll_fresp_bits_fflags_bits_uop_br_mask = 8'h0; // @[execution-unit.scala:204:7]
wire [7:0] io_status_zero1 = 8'h0; // @[execution-unit.scala:204:7]
wire [7:0] io_lsu_io_req_bits_fflags_bits_uop_br_mask = 8'h0; // @[execution-unit.scala:204:7]
wire [7:0] io_lsu_io_iresp_bits_fflags_bits_uop_br_mask = 8'h0; // @[execution-unit.scala:204:7]
wire [7:0] io_lsu_io_fresp_bits_fflags_bits_uop_br_mask = 8'h0; // @[execution-unit.scala:204:7]
wire io_req_bits_pred_data = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_predicated = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_valid = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_is_br = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_is_jal = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_taken = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_exception = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_bypassable = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_is_fence = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_is_amo = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_is_unique = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_fp_val = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_fp_single = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_predicated = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_valid = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_is_br = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_is_jal = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_taken = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_exception = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_bypassable = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_is_fence = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_is_amo = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_is_unique = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_fp_val = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_fp_single = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_status_mbe = 1'h0; // @[execution-unit.scala:204:7]
wire io_status_sbe = 1'h0; // @[execution-unit.scala:204:7]
wire io_status_sd_rv32 = 1'h0; // @[execution-unit.scala:204:7]
wire io_status_ube = 1'h0; // @[execution-unit.scala:204:7]
wire io_status_upie = 1'h0; // @[execution-unit.scala:204:7]
wire io_status_hie = 1'h0; // @[execution-unit.scala:204:7]
wire io_status_uie = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_predicated = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_valid = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_is_rvc = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_is_br = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_is_jalr = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_is_jal = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_is_sfb = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_edge_inst = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_taken = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_exception = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_bypassable = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_mem_signed = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_is_fence = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_is_fencei = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_is_amo = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_uses_stq = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_is_unique = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_ldst_val = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_frs3_en = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_fp_val = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_fp_single = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_sfence_bits_hv = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_sfence_bits_hg = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_predicated = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_valid = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_is_br = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_is_jal = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_taken = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_exception = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_bypassable = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_is_fence = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_is_amo = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_is_unique = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_fp_val = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_fp_single = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_iresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_predicated = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_valid = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_is_rvc = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_ctrl_fcn_dw = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_ctrl_is_load = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_ctrl_is_sta = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_ctrl_is_std = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_iw_p1_poisoned = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_iw_p2_poisoned = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_is_br = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_is_jalr = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_is_jal = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_is_sfb = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_edge_inst = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_taken = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_prs1_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_prs2_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_prs3_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_ppred_busy = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_exception = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_bypassable = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_mem_signed = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_is_fence = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_is_fencei = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_is_amo = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_uses_ldq = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_uses_stq = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_is_sys_pc2epc = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_is_unique = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_flush_on_commit = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_ldst_is_rs1 = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_ldst_val = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_frs3_en = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_fp_val = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_fp_single = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_xcpt_pf_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_xcpt_ae_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_xcpt_ma_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_bp_debug_if = 1'h0; // @[execution-unit.scala:204:7]
wire io_lsu_io_fresp_bits_fflags_bits_uop_bp_xcpt_if = 1'h0; // @[execution-unit.scala:204:7]
wire div_busy = 1'h0; // @[execution-unit.scala:253:27]
wire ifpu_busy = 1'h0; // @[execution-unit.scala:254:27]
wire _io_fu_types_T_4 = 1'h0; // @[execution-unit.scala:262:32]
wire _io_fu_types_T_12 = 1'h0; // @[execution-unit.scala:265:33]
wire div_resp_val = 1'h0; // @[execution-unit.scala:364:30]
wire [22:0] io_status_zero2 = 23'h0; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire [31:0] io_status_isa = 32'h14112D; // @[execution-unit.scala:104:14, :204:7, :388:27]
wire io_ll_iresp_valid_0 = io_lsu_io_iresp_valid_0; // @[execution-unit.scala:204:7]
wire [6:0] io_ll_iresp_bits_uop_uopc_0 = io_lsu_io_iresp_bits_uop_uopc_0; // @[execution-unit.scala:204:7]
wire [31:0] io_ll_iresp_bits_uop_inst_0 = io_lsu_io_iresp_bits_uop_inst_0; // @[execution-unit.scala:204:7]
wire [31:0] io_ll_iresp_bits_uop_debug_inst_0 = io_lsu_io_iresp_bits_uop_debug_inst_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_is_rvc_0 = io_lsu_io_iresp_bits_uop_is_rvc_0; // @[execution-unit.scala:204:7]
wire [39:0] io_ll_iresp_bits_uop_debug_pc_0 = io_lsu_io_iresp_bits_uop_debug_pc_0; // @[execution-unit.scala:204:7]
wire [2:0] io_ll_iresp_bits_uop_iq_type_0 = io_lsu_io_iresp_bits_uop_iq_type_0; // @[execution-unit.scala:204:7]
wire [9:0] io_ll_iresp_bits_uop_fu_code_0 = io_lsu_io_iresp_bits_uop_fu_code_0; // @[execution-unit.scala:204:7]
wire [3:0] io_ll_iresp_bits_uop_ctrl_br_type_0 = io_lsu_io_iresp_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_iresp_bits_uop_ctrl_op1_sel_0 = io_lsu_io_iresp_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_ll_iresp_bits_uop_ctrl_op2_sel_0 = io_lsu_io_iresp_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_ll_iresp_bits_uop_ctrl_imm_sel_0 = io_lsu_io_iresp_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:204:7]
wire [4:0] io_ll_iresp_bits_uop_ctrl_op_fcn_0 = io_lsu_io_iresp_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_ctrl_fcn_dw_0 = io_lsu_io_iresp_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:204:7]
wire [2:0] io_ll_iresp_bits_uop_ctrl_csr_cmd_0 = io_lsu_io_iresp_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_ctrl_is_load_0 = io_lsu_io_iresp_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_ctrl_is_sta_0 = io_lsu_io_iresp_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_ctrl_is_std_0 = io_lsu_io_iresp_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_iresp_bits_uop_iw_state_0 = io_lsu_io_iresp_bits_uop_iw_state_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_iw_p1_poisoned_0 = io_lsu_io_iresp_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_iw_p2_poisoned_0 = io_lsu_io_iresp_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_is_br_0 = io_lsu_io_iresp_bits_uop_is_br_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_is_jalr_0 = io_lsu_io_iresp_bits_uop_is_jalr_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_is_jal_0 = io_lsu_io_iresp_bits_uop_is_jal_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_is_sfb_0 = io_lsu_io_iresp_bits_uop_is_sfb_0; // @[execution-unit.scala:204:7]
wire [7:0] io_ll_iresp_bits_uop_br_mask_0 = io_lsu_io_iresp_bits_uop_br_mask_0; // @[execution-unit.scala:204:7]
wire [2:0] io_ll_iresp_bits_uop_br_tag_0 = io_lsu_io_iresp_bits_uop_br_tag_0; // @[execution-unit.scala:204:7]
wire [3:0] io_ll_iresp_bits_uop_ftq_idx_0 = io_lsu_io_iresp_bits_uop_ftq_idx_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_edge_inst_0 = io_lsu_io_iresp_bits_uop_edge_inst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_iresp_bits_uop_pc_lob_0 = io_lsu_io_iresp_bits_uop_pc_lob_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_taken_0 = io_lsu_io_iresp_bits_uop_taken_0; // @[execution-unit.scala:204:7]
wire [19:0] io_ll_iresp_bits_uop_imm_packed_0 = io_lsu_io_iresp_bits_uop_imm_packed_0; // @[execution-unit.scala:204:7]
wire [11:0] io_ll_iresp_bits_uop_csr_addr_0 = io_lsu_io_iresp_bits_uop_csr_addr_0; // @[execution-unit.scala:204:7]
wire [4:0] io_ll_iresp_bits_uop_rob_idx_0 = io_lsu_io_iresp_bits_uop_rob_idx_0; // @[execution-unit.scala:204:7]
wire [2:0] io_ll_iresp_bits_uop_ldq_idx_0 = io_lsu_io_iresp_bits_uop_ldq_idx_0; // @[execution-unit.scala:204:7]
wire [2:0] io_ll_iresp_bits_uop_stq_idx_0 = io_lsu_io_iresp_bits_uop_stq_idx_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_iresp_bits_uop_rxq_idx_0 = io_lsu_io_iresp_bits_uop_rxq_idx_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_iresp_bits_uop_pdst_0 = io_lsu_io_iresp_bits_uop_pdst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_iresp_bits_uop_prs1_0 = io_lsu_io_iresp_bits_uop_prs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_iresp_bits_uop_prs2_0 = io_lsu_io_iresp_bits_uop_prs2_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_iresp_bits_uop_prs3_0 = io_lsu_io_iresp_bits_uop_prs3_0; // @[execution-unit.scala:204:7]
wire [3:0] io_ll_iresp_bits_uop_ppred_0 = io_lsu_io_iresp_bits_uop_ppred_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_prs1_busy_0 = io_lsu_io_iresp_bits_uop_prs1_busy_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_prs2_busy_0 = io_lsu_io_iresp_bits_uop_prs2_busy_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_prs3_busy_0 = io_lsu_io_iresp_bits_uop_prs3_busy_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_ppred_busy_0 = io_lsu_io_iresp_bits_uop_ppred_busy_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_iresp_bits_uop_stale_pdst_0 = io_lsu_io_iresp_bits_uop_stale_pdst_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_exception_0 = io_lsu_io_iresp_bits_uop_exception_0; // @[execution-unit.scala:204:7]
wire [63:0] io_ll_iresp_bits_uop_exc_cause_0 = io_lsu_io_iresp_bits_uop_exc_cause_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_bypassable_0 = io_lsu_io_iresp_bits_uop_bypassable_0; // @[execution-unit.scala:204:7]
wire [4:0] io_ll_iresp_bits_uop_mem_cmd_0 = io_lsu_io_iresp_bits_uop_mem_cmd_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_iresp_bits_uop_mem_size_0 = io_lsu_io_iresp_bits_uop_mem_size_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_mem_signed_0 = io_lsu_io_iresp_bits_uop_mem_signed_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_is_fence_0 = io_lsu_io_iresp_bits_uop_is_fence_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_is_fencei_0 = io_lsu_io_iresp_bits_uop_is_fencei_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_is_amo_0 = io_lsu_io_iresp_bits_uop_is_amo_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_uses_ldq_0 = io_lsu_io_iresp_bits_uop_uses_ldq_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_uses_stq_0 = io_lsu_io_iresp_bits_uop_uses_stq_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_is_sys_pc2epc_0 = io_lsu_io_iresp_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_is_unique_0 = io_lsu_io_iresp_bits_uop_is_unique_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_flush_on_commit_0 = io_lsu_io_iresp_bits_uop_flush_on_commit_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_ldst_is_rs1_0 = io_lsu_io_iresp_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_iresp_bits_uop_ldst_0 = io_lsu_io_iresp_bits_uop_ldst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_iresp_bits_uop_lrs1_0 = io_lsu_io_iresp_bits_uop_lrs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_iresp_bits_uop_lrs2_0 = io_lsu_io_iresp_bits_uop_lrs2_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_iresp_bits_uop_lrs3_0 = io_lsu_io_iresp_bits_uop_lrs3_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_ldst_val_0 = io_lsu_io_iresp_bits_uop_ldst_val_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_iresp_bits_uop_dst_rtype_0 = io_lsu_io_iresp_bits_uop_dst_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_iresp_bits_uop_lrs1_rtype_0 = io_lsu_io_iresp_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_iresp_bits_uop_lrs2_rtype_0 = io_lsu_io_iresp_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_frs3_en_0 = io_lsu_io_iresp_bits_uop_frs3_en_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_fp_val_0 = io_lsu_io_iresp_bits_uop_fp_val_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_fp_single_0 = io_lsu_io_iresp_bits_uop_fp_single_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_xcpt_pf_if_0 = io_lsu_io_iresp_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_xcpt_ae_if_0 = io_lsu_io_iresp_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_xcpt_ma_if_0 = io_lsu_io_iresp_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_bp_debug_if_0 = io_lsu_io_iresp_bits_uop_bp_debug_if_0; // @[execution-unit.scala:204:7]
wire io_ll_iresp_bits_uop_bp_xcpt_if_0 = io_lsu_io_iresp_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_iresp_bits_uop_debug_fsrc_0 = io_lsu_io_iresp_bits_uop_debug_fsrc_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_iresp_bits_uop_debug_tsrc_0 = io_lsu_io_iresp_bits_uop_debug_tsrc_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_valid_0 = io_lsu_io_fresp_valid_0; // @[execution-unit.scala:204:7]
wire [6:0] io_ll_fresp_bits_uop_uopc_0 = io_lsu_io_fresp_bits_uop_uopc_0; // @[execution-unit.scala:204:7]
wire [31:0] io_ll_fresp_bits_uop_inst_0 = io_lsu_io_fresp_bits_uop_inst_0; // @[execution-unit.scala:204:7]
wire [31:0] io_ll_fresp_bits_uop_debug_inst_0 = io_lsu_io_fresp_bits_uop_debug_inst_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_is_rvc_0 = io_lsu_io_fresp_bits_uop_is_rvc_0; // @[execution-unit.scala:204:7]
wire [39:0] io_ll_fresp_bits_uop_debug_pc_0 = io_lsu_io_fresp_bits_uop_debug_pc_0; // @[execution-unit.scala:204:7]
wire [2:0] io_ll_fresp_bits_uop_iq_type_0 = io_lsu_io_fresp_bits_uop_iq_type_0; // @[execution-unit.scala:204:7]
wire [9:0] io_ll_fresp_bits_uop_fu_code_0 = io_lsu_io_fresp_bits_uop_fu_code_0; // @[execution-unit.scala:204:7]
wire [3:0] io_ll_fresp_bits_uop_ctrl_br_type_0 = io_lsu_io_fresp_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_uop_ctrl_op1_sel_0 = io_lsu_io_fresp_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_ll_fresp_bits_uop_ctrl_op2_sel_0 = io_lsu_io_fresp_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_ll_fresp_bits_uop_ctrl_imm_sel_0 = io_lsu_io_fresp_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:204:7]
wire [4:0] io_ll_fresp_bits_uop_ctrl_op_fcn_0 = io_lsu_io_fresp_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_ctrl_fcn_dw_0 = io_lsu_io_fresp_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:204:7]
wire [2:0] io_ll_fresp_bits_uop_ctrl_csr_cmd_0 = io_lsu_io_fresp_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_ctrl_is_load_0 = io_lsu_io_fresp_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_ctrl_is_sta_0 = io_lsu_io_fresp_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_ctrl_is_std_0 = io_lsu_io_fresp_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_uop_iw_state_0 = io_lsu_io_fresp_bits_uop_iw_state_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_iw_p1_poisoned_0 = io_lsu_io_fresp_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_iw_p2_poisoned_0 = io_lsu_io_fresp_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_is_br_0 = io_lsu_io_fresp_bits_uop_is_br_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_is_jalr_0 = io_lsu_io_fresp_bits_uop_is_jalr_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_is_jal_0 = io_lsu_io_fresp_bits_uop_is_jal_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_is_sfb_0 = io_lsu_io_fresp_bits_uop_is_sfb_0; // @[execution-unit.scala:204:7]
wire [7:0] io_ll_fresp_bits_uop_br_mask_0 = io_lsu_io_fresp_bits_uop_br_mask_0; // @[execution-unit.scala:204:7]
wire [2:0] io_ll_fresp_bits_uop_br_tag_0 = io_lsu_io_fresp_bits_uop_br_tag_0; // @[execution-unit.scala:204:7]
wire [3:0] io_ll_fresp_bits_uop_ftq_idx_0 = io_lsu_io_fresp_bits_uop_ftq_idx_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_edge_inst_0 = io_lsu_io_fresp_bits_uop_edge_inst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_fresp_bits_uop_pc_lob_0 = io_lsu_io_fresp_bits_uop_pc_lob_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_taken_0 = io_lsu_io_fresp_bits_uop_taken_0; // @[execution-unit.scala:204:7]
wire [19:0] io_ll_fresp_bits_uop_imm_packed_0 = io_lsu_io_fresp_bits_uop_imm_packed_0; // @[execution-unit.scala:204:7]
wire [11:0] io_ll_fresp_bits_uop_csr_addr_0 = io_lsu_io_fresp_bits_uop_csr_addr_0; // @[execution-unit.scala:204:7]
wire [4:0] io_ll_fresp_bits_uop_rob_idx_0 = io_lsu_io_fresp_bits_uop_rob_idx_0; // @[execution-unit.scala:204:7]
wire [2:0] io_ll_fresp_bits_uop_ldq_idx_0 = io_lsu_io_fresp_bits_uop_ldq_idx_0; // @[execution-unit.scala:204:7]
wire [2:0] io_ll_fresp_bits_uop_stq_idx_0 = io_lsu_io_fresp_bits_uop_stq_idx_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_uop_rxq_idx_0 = io_lsu_io_fresp_bits_uop_rxq_idx_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_fresp_bits_uop_pdst_0 = io_lsu_io_fresp_bits_uop_pdst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_fresp_bits_uop_prs1_0 = io_lsu_io_fresp_bits_uop_prs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_fresp_bits_uop_prs2_0 = io_lsu_io_fresp_bits_uop_prs2_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_fresp_bits_uop_prs3_0 = io_lsu_io_fresp_bits_uop_prs3_0; // @[execution-unit.scala:204:7]
wire [3:0] io_ll_fresp_bits_uop_ppred_0 = io_lsu_io_fresp_bits_uop_ppred_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_prs1_busy_0 = io_lsu_io_fresp_bits_uop_prs1_busy_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_prs2_busy_0 = io_lsu_io_fresp_bits_uop_prs2_busy_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_prs3_busy_0 = io_lsu_io_fresp_bits_uop_prs3_busy_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_ppred_busy_0 = io_lsu_io_fresp_bits_uop_ppred_busy_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_fresp_bits_uop_stale_pdst_0 = io_lsu_io_fresp_bits_uop_stale_pdst_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_exception_0 = io_lsu_io_fresp_bits_uop_exception_0; // @[execution-unit.scala:204:7]
wire [63:0] io_ll_fresp_bits_uop_exc_cause_0 = io_lsu_io_fresp_bits_uop_exc_cause_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_bypassable_0 = io_lsu_io_fresp_bits_uop_bypassable_0; // @[execution-unit.scala:204:7]
wire [4:0] io_ll_fresp_bits_uop_mem_cmd_0 = io_lsu_io_fresp_bits_uop_mem_cmd_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_uop_mem_size_0 = io_lsu_io_fresp_bits_uop_mem_size_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_mem_signed_0 = io_lsu_io_fresp_bits_uop_mem_signed_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_is_fence_0 = io_lsu_io_fresp_bits_uop_is_fence_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_is_fencei_0 = io_lsu_io_fresp_bits_uop_is_fencei_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_is_amo_0 = io_lsu_io_fresp_bits_uop_is_amo_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_uses_ldq_0 = io_lsu_io_fresp_bits_uop_uses_ldq_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_uses_stq_0 = io_lsu_io_fresp_bits_uop_uses_stq_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_is_sys_pc2epc_0 = io_lsu_io_fresp_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_is_unique_0 = io_lsu_io_fresp_bits_uop_is_unique_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_flush_on_commit_0 = io_lsu_io_fresp_bits_uop_flush_on_commit_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_ldst_is_rs1_0 = io_lsu_io_fresp_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_fresp_bits_uop_ldst_0 = io_lsu_io_fresp_bits_uop_ldst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_fresp_bits_uop_lrs1_0 = io_lsu_io_fresp_bits_uop_lrs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_fresp_bits_uop_lrs2_0 = io_lsu_io_fresp_bits_uop_lrs2_0; // @[execution-unit.scala:204:7]
wire [5:0] io_ll_fresp_bits_uop_lrs3_0 = io_lsu_io_fresp_bits_uop_lrs3_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_ldst_val_0 = io_lsu_io_fresp_bits_uop_ldst_val_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_uop_dst_rtype_0 = io_lsu_io_fresp_bits_uop_dst_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_uop_lrs1_rtype_0 = io_lsu_io_fresp_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_uop_lrs2_rtype_0 = io_lsu_io_fresp_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_frs3_en_0 = io_lsu_io_fresp_bits_uop_frs3_en_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_fp_val_0 = io_lsu_io_fresp_bits_uop_fp_val_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_fp_single_0 = io_lsu_io_fresp_bits_uop_fp_single_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_xcpt_pf_if_0 = io_lsu_io_fresp_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_xcpt_ae_if_0 = io_lsu_io_fresp_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_xcpt_ma_if_0 = io_lsu_io_fresp_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_bp_debug_if_0 = io_lsu_io_fresp_bits_uop_bp_debug_if_0; // @[execution-unit.scala:204:7]
wire io_ll_fresp_bits_uop_bp_xcpt_if_0 = io_lsu_io_fresp_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_uop_debug_fsrc_0 = io_lsu_io_fresp_bits_uop_debug_fsrc_0; // @[execution-unit.scala:204:7]
wire [1:0] io_ll_fresp_bits_uop_debug_tsrc_0 = io_lsu_io_fresp_bits_uop_debug_tsrc_0; // @[execution-unit.scala:204:7]
wire [64:0] io_ll_fresp_bits_data_0 = io_lsu_io_fresp_bits_data_0; // @[execution-unit.scala:204:7]
wire [64:0] io_ll_iresp_bits_data_0; // @[execution-unit.scala:204:7]
wire [3:0] io_lsu_io_req_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_req_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_lsu_io_req_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:204:7]
wire [2:0] io_lsu_io_req_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:204:7]
wire [4:0] io_lsu_io_req_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:204:7]
wire [2:0] io_lsu_io_req_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:204:7]
wire [6:0] io_lsu_io_req_bits_uop_uopc_0; // @[execution-unit.scala:204:7]
wire [31:0] io_lsu_io_req_bits_uop_inst_0; // @[execution-unit.scala:204:7]
wire [31:0] io_lsu_io_req_bits_uop_debug_inst_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_is_rvc_0; // @[execution-unit.scala:204:7]
wire [39:0] io_lsu_io_req_bits_uop_debug_pc_0; // @[execution-unit.scala:204:7]
wire [2:0] io_lsu_io_req_bits_uop_iq_type_0; // @[execution-unit.scala:204:7]
wire [9:0] io_lsu_io_req_bits_uop_fu_code_0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_req_bits_uop_iw_state_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_is_br_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_is_jalr_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_is_jal_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_is_sfb_0; // @[execution-unit.scala:204:7]
wire [7:0] io_lsu_io_req_bits_uop_br_mask_0; // @[execution-unit.scala:204:7]
wire [2:0] io_lsu_io_req_bits_uop_br_tag_0; // @[execution-unit.scala:204:7]
wire [3:0] io_lsu_io_req_bits_uop_ftq_idx_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_edge_inst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_lsu_io_req_bits_uop_pc_lob_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_taken_0; // @[execution-unit.scala:204:7]
wire [19:0] io_lsu_io_req_bits_uop_imm_packed_0; // @[execution-unit.scala:204:7]
wire [11:0] io_lsu_io_req_bits_uop_csr_addr_0; // @[execution-unit.scala:204:7]
wire [4:0] io_lsu_io_req_bits_uop_rob_idx_0; // @[execution-unit.scala:204:7]
wire [2:0] io_lsu_io_req_bits_uop_ldq_idx_0; // @[execution-unit.scala:204:7]
wire [2:0] io_lsu_io_req_bits_uop_stq_idx_0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_req_bits_uop_rxq_idx_0; // @[execution-unit.scala:204:7]
wire [5:0] io_lsu_io_req_bits_uop_pdst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_lsu_io_req_bits_uop_prs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_lsu_io_req_bits_uop_prs2_0; // @[execution-unit.scala:204:7]
wire [5:0] io_lsu_io_req_bits_uop_prs3_0; // @[execution-unit.scala:204:7]
wire [3:0] io_lsu_io_req_bits_uop_ppred_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_prs1_busy_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_prs2_busy_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_prs3_busy_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_ppred_busy_0; // @[execution-unit.scala:204:7]
wire [5:0] io_lsu_io_req_bits_uop_stale_pdst_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_exception_0; // @[execution-unit.scala:204:7]
wire [63:0] io_lsu_io_req_bits_uop_exc_cause_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_bypassable_0; // @[execution-unit.scala:204:7]
wire [4:0] io_lsu_io_req_bits_uop_mem_cmd_0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_req_bits_uop_mem_size_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_mem_signed_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_is_fence_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_is_fencei_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_is_amo_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_uses_ldq_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_uses_stq_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_is_unique_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_flush_on_commit_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_lsu_io_req_bits_uop_ldst_0; // @[execution-unit.scala:204:7]
wire [5:0] io_lsu_io_req_bits_uop_lrs1_0; // @[execution-unit.scala:204:7]
wire [5:0] io_lsu_io_req_bits_uop_lrs2_0; // @[execution-unit.scala:204:7]
wire [5:0] io_lsu_io_req_bits_uop_lrs3_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_ldst_val_0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_req_bits_uop_dst_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_req_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_req_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_frs3_en_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_fp_val_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_fp_single_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_bp_debug_if_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_req_bits_uop_debug_fsrc_0; // @[execution-unit.scala:204:7]
wire [1:0] io_lsu_io_req_bits_uop_debug_tsrc_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_mxcpt_valid_0; // @[execution-unit.scala:204:7]
wire [24:0] io_lsu_io_req_bits_mxcpt_bits_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_sfence_bits_rs1_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_sfence_bits_rs2_0; // @[execution-unit.scala:204:7]
wire [38:0] io_lsu_io_req_bits_sfence_bits_addr_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_sfence_bits_asid_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_bits_sfence_valid_0; // @[execution-unit.scala:204:7]
wire [63:0] io_lsu_io_req_bits_data_0; // @[execution-unit.scala:204:7]
wire [39:0] io_lsu_io_req_bits_addr_0; // @[execution-unit.scala:204:7]
wire io_lsu_io_req_valid_0; // @[execution-unit.scala:204:7]
wire [9:0] _maddrcalc_io_req_valid_T = io_req_bits_uop_fu_code_0 & 10'h4; // @[execution-unit.scala:204:7]
wire _maddrcalc_io_req_valid_T_1 = |_maddrcalc_io_req_valid_T; // @[micro-op.scala:154:{40,47}]
wire _maddrcalc_io_req_valid_T_2 = io_req_valid_0 & _maddrcalc_io_req_valid_T_1; // @[execution-unit.scala:204:7, :390:45]
assign io_lsu_io_req_bits_data_0 = _maddrcalc_io_resp_bits_data[63:0]; // @[execution-unit.scala:204:7, :388:27, :399:19]
assign io_ll_iresp_bits_data_0 = {1'h0, io_lsu_io_iresp_bits_data_0}; // @[execution-unit.scala:204:7, :401:17]
MemAddrCalcUnit_1 maddrcalc ( // @[execution-unit.scala:388:27]
.clock (clock),
.reset (reset),
.io_req_valid (_maddrcalc_io_req_valid_T_2), // @[execution-unit.scala:390:45]
.io_req_bits_uop_uopc (io_req_bits_uop_uopc_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_inst (io_req_bits_uop_inst_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_debug_inst (io_req_bits_uop_debug_inst_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_is_rvc (io_req_bits_uop_is_rvc_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_debug_pc (io_req_bits_uop_debug_pc_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_iq_type (io_req_bits_uop_iq_type_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_fu_code (io_req_bits_uop_fu_code_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_ctrl_br_type (io_req_bits_uop_ctrl_br_type_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_ctrl_op1_sel (io_req_bits_uop_ctrl_op1_sel_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_ctrl_op2_sel (io_req_bits_uop_ctrl_op2_sel_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_ctrl_imm_sel (io_req_bits_uop_ctrl_imm_sel_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_ctrl_op_fcn (io_req_bits_uop_ctrl_op_fcn_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_ctrl_fcn_dw (io_req_bits_uop_ctrl_fcn_dw_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_ctrl_csr_cmd (io_req_bits_uop_ctrl_csr_cmd_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_ctrl_is_load (io_req_bits_uop_ctrl_is_load_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_ctrl_is_sta (io_req_bits_uop_ctrl_is_sta_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_ctrl_is_std (io_req_bits_uop_ctrl_is_std_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_iw_state (io_req_bits_uop_iw_state_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_iw_p1_poisoned (io_req_bits_uop_iw_p1_poisoned_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_iw_p2_poisoned (io_req_bits_uop_iw_p2_poisoned_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_is_br (io_req_bits_uop_is_br_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_is_jalr (io_req_bits_uop_is_jalr_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_is_jal (io_req_bits_uop_is_jal_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_is_sfb (io_req_bits_uop_is_sfb_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_br_mask (io_req_bits_uop_br_mask_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_br_tag (io_req_bits_uop_br_tag_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_ftq_idx (io_req_bits_uop_ftq_idx_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_edge_inst (io_req_bits_uop_edge_inst_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_pc_lob (io_req_bits_uop_pc_lob_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_taken (io_req_bits_uop_taken_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_imm_packed (io_req_bits_uop_imm_packed_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_csr_addr (io_req_bits_uop_csr_addr_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_rob_idx (io_req_bits_uop_rob_idx_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_ldq_idx (io_req_bits_uop_ldq_idx_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_stq_idx (io_req_bits_uop_stq_idx_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_rxq_idx (io_req_bits_uop_rxq_idx_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_pdst (io_req_bits_uop_pdst_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_prs1 (io_req_bits_uop_prs1_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_prs2 (io_req_bits_uop_prs2_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_prs3 (io_req_bits_uop_prs3_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_ppred (io_req_bits_uop_ppred_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_prs1_busy (io_req_bits_uop_prs1_busy_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_prs2_busy (io_req_bits_uop_prs2_busy_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_prs3_busy (io_req_bits_uop_prs3_busy_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_ppred_busy (io_req_bits_uop_ppred_busy_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_stale_pdst (io_req_bits_uop_stale_pdst_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_exception (io_req_bits_uop_exception_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_exc_cause (io_req_bits_uop_exc_cause_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_bypassable (io_req_bits_uop_bypassable_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_mem_cmd (io_req_bits_uop_mem_cmd_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_mem_size (io_req_bits_uop_mem_size_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_mem_signed (io_req_bits_uop_mem_signed_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_is_fence (io_req_bits_uop_is_fence_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_is_fencei (io_req_bits_uop_is_fencei_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_is_amo (io_req_bits_uop_is_amo_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_uses_ldq (io_req_bits_uop_uses_ldq_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_uses_stq (io_req_bits_uop_uses_stq_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_is_sys_pc2epc (io_req_bits_uop_is_sys_pc2epc_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_is_unique (io_req_bits_uop_is_unique_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_flush_on_commit (io_req_bits_uop_flush_on_commit_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_ldst_is_rs1 (io_req_bits_uop_ldst_is_rs1_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_ldst (io_req_bits_uop_ldst_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_lrs1 (io_req_bits_uop_lrs1_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_lrs2 (io_req_bits_uop_lrs2_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_lrs3 (io_req_bits_uop_lrs3_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_ldst_val (io_req_bits_uop_ldst_val_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_dst_rtype (io_req_bits_uop_dst_rtype_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_lrs1_rtype (io_req_bits_uop_lrs1_rtype_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_lrs2_rtype (io_req_bits_uop_lrs2_rtype_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_frs3_en (io_req_bits_uop_frs3_en_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_fp_val (io_req_bits_uop_fp_val_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_fp_single (io_req_bits_uop_fp_single_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_xcpt_pf_if (io_req_bits_uop_xcpt_pf_if_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_xcpt_ae_if (io_req_bits_uop_xcpt_ae_if_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_xcpt_ma_if (io_req_bits_uop_xcpt_ma_if_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_bp_debug_if (io_req_bits_uop_bp_debug_if_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_bp_xcpt_if (io_req_bits_uop_bp_xcpt_if_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_debug_fsrc (io_req_bits_uop_debug_fsrc_0), // @[execution-unit.scala:204:7]
.io_req_bits_uop_debug_tsrc (io_req_bits_uop_debug_tsrc_0), // @[execution-unit.scala:204:7]
.io_req_bits_rs1_data (io_req_bits_rs1_data_0), // @[execution-unit.scala:204:7]
.io_req_bits_rs2_data (io_req_bits_rs2_data_0), // @[execution-unit.scala:204:7]
.io_req_bits_kill (io_req_bits_kill_0), // @[execution-unit.scala:204:7]
.io_resp_valid (io_lsu_io_req_valid_0),
.io_resp_bits_uop_uopc (io_lsu_io_req_bits_uop_uopc_0),
.io_resp_bits_uop_inst (io_lsu_io_req_bits_uop_inst_0),
.io_resp_bits_uop_debug_inst (io_lsu_io_req_bits_uop_debug_inst_0),
.io_resp_bits_uop_is_rvc (io_lsu_io_req_bits_uop_is_rvc_0),
.io_resp_bits_uop_debug_pc (io_lsu_io_req_bits_uop_debug_pc_0),
.io_resp_bits_uop_iq_type (io_lsu_io_req_bits_uop_iq_type_0),
.io_resp_bits_uop_fu_code (io_lsu_io_req_bits_uop_fu_code_0),
.io_resp_bits_uop_ctrl_br_type (io_lsu_io_req_bits_uop_ctrl_br_type_0),
.io_resp_bits_uop_ctrl_op1_sel (io_lsu_io_req_bits_uop_ctrl_op1_sel_0),
.io_resp_bits_uop_ctrl_op2_sel (io_lsu_io_req_bits_uop_ctrl_op2_sel_0),
.io_resp_bits_uop_ctrl_imm_sel (io_lsu_io_req_bits_uop_ctrl_imm_sel_0),
.io_resp_bits_uop_ctrl_op_fcn (io_lsu_io_req_bits_uop_ctrl_op_fcn_0),
.io_resp_bits_uop_ctrl_fcn_dw (io_lsu_io_req_bits_uop_ctrl_fcn_dw_0),
.io_resp_bits_uop_ctrl_csr_cmd (io_lsu_io_req_bits_uop_ctrl_csr_cmd_0),
.io_resp_bits_uop_ctrl_is_load (io_lsu_io_req_bits_uop_ctrl_is_load_0),
.io_resp_bits_uop_ctrl_is_sta (io_lsu_io_req_bits_uop_ctrl_is_sta_0),
.io_resp_bits_uop_ctrl_is_std (io_lsu_io_req_bits_uop_ctrl_is_std_0),
.io_resp_bits_uop_iw_state (io_lsu_io_req_bits_uop_iw_state_0),
.io_resp_bits_uop_iw_p1_poisoned (io_lsu_io_req_bits_uop_iw_p1_poisoned_0),
.io_resp_bits_uop_iw_p2_poisoned (io_lsu_io_req_bits_uop_iw_p2_poisoned_0),
.io_resp_bits_uop_is_br (io_lsu_io_req_bits_uop_is_br_0),
.io_resp_bits_uop_is_jalr (io_lsu_io_req_bits_uop_is_jalr_0),
.io_resp_bits_uop_is_jal (io_lsu_io_req_bits_uop_is_jal_0),
.io_resp_bits_uop_is_sfb (io_lsu_io_req_bits_uop_is_sfb_0),
.io_resp_bits_uop_br_mask (io_lsu_io_req_bits_uop_br_mask_0),
.io_resp_bits_uop_br_tag (io_lsu_io_req_bits_uop_br_tag_0),
.io_resp_bits_uop_ftq_idx (io_lsu_io_req_bits_uop_ftq_idx_0),
.io_resp_bits_uop_edge_inst (io_lsu_io_req_bits_uop_edge_inst_0),
.io_resp_bits_uop_pc_lob (io_lsu_io_req_bits_uop_pc_lob_0),
.io_resp_bits_uop_taken (io_lsu_io_req_bits_uop_taken_0),
.io_resp_bits_uop_imm_packed (io_lsu_io_req_bits_uop_imm_packed_0),
.io_resp_bits_uop_csr_addr (io_lsu_io_req_bits_uop_csr_addr_0),
.io_resp_bits_uop_rob_idx (io_lsu_io_req_bits_uop_rob_idx_0),
.io_resp_bits_uop_ldq_idx (io_lsu_io_req_bits_uop_ldq_idx_0),
.io_resp_bits_uop_stq_idx (io_lsu_io_req_bits_uop_stq_idx_0),
.io_resp_bits_uop_rxq_idx (io_lsu_io_req_bits_uop_rxq_idx_0),
.io_resp_bits_uop_pdst (io_lsu_io_req_bits_uop_pdst_0),
.io_resp_bits_uop_prs1 (io_lsu_io_req_bits_uop_prs1_0),
.io_resp_bits_uop_prs2 (io_lsu_io_req_bits_uop_prs2_0),
.io_resp_bits_uop_prs3 (io_lsu_io_req_bits_uop_prs3_0),
.io_resp_bits_uop_ppred (io_lsu_io_req_bits_uop_ppred_0),
.io_resp_bits_uop_prs1_busy (io_lsu_io_req_bits_uop_prs1_busy_0),
.io_resp_bits_uop_prs2_busy (io_lsu_io_req_bits_uop_prs2_busy_0),
.io_resp_bits_uop_prs3_busy (io_lsu_io_req_bits_uop_prs3_busy_0),
.io_resp_bits_uop_ppred_busy (io_lsu_io_req_bits_uop_ppred_busy_0),
.io_resp_bits_uop_stale_pdst (io_lsu_io_req_bits_uop_stale_pdst_0),
.io_resp_bits_uop_exception (io_lsu_io_req_bits_uop_exception_0),
.io_resp_bits_uop_exc_cause (io_lsu_io_req_bits_uop_exc_cause_0),
.io_resp_bits_uop_bypassable (io_lsu_io_req_bits_uop_bypassable_0),
.io_resp_bits_uop_mem_cmd (io_lsu_io_req_bits_uop_mem_cmd_0),
.io_resp_bits_uop_mem_size (io_lsu_io_req_bits_uop_mem_size_0),
.io_resp_bits_uop_mem_signed (io_lsu_io_req_bits_uop_mem_signed_0),
.io_resp_bits_uop_is_fence (io_lsu_io_req_bits_uop_is_fence_0),
.io_resp_bits_uop_is_fencei (io_lsu_io_req_bits_uop_is_fencei_0),
.io_resp_bits_uop_is_amo (io_lsu_io_req_bits_uop_is_amo_0),
.io_resp_bits_uop_uses_ldq (io_lsu_io_req_bits_uop_uses_ldq_0),
.io_resp_bits_uop_uses_stq (io_lsu_io_req_bits_uop_uses_stq_0),
.io_resp_bits_uop_is_sys_pc2epc (io_lsu_io_req_bits_uop_is_sys_pc2epc_0),
.io_resp_bits_uop_is_unique (io_lsu_io_req_bits_uop_is_unique_0),
.io_resp_bits_uop_flush_on_commit (io_lsu_io_req_bits_uop_flush_on_commit_0),
.io_resp_bits_uop_ldst_is_rs1 (io_lsu_io_req_bits_uop_ldst_is_rs1_0),
.io_resp_bits_uop_ldst (io_lsu_io_req_bits_uop_ldst_0),
.io_resp_bits_uop_lrs1 (io_lsu_io_req_bits_uop_lrs1_0),
.io_resp_bits_uop_lrs2 (io_lsu_io_req_bits_uop_lrs2_0),
.io_resp_bits_uop_lrs3 (io_lsu_io_req_bits_uop_lrs3_0),
.io_resp_bits_uop_ldst_val (io_lsu_io_req_bits_uop_ldst_val_0),
.io_resp_bits_uop_dst_rtype (io_lsu_io_req_bits_uop_dst_rtype_0),
.io_resp_bits_uop_lrs1_rtype (io_lsu_io_req_bits_uop_lrs1_rtype_0),
.io_resp_bits_uop_lrs2_rtype (io_lsu_io_req_bits_uop_lrs2_rtype_0),
.io_resp_bits_uop_frs3_en (io_lsu_io_req_bits_uop_frs3_en_0),
.io_resp_bits_uop_fp_val (io_lsu_io_req_bits_uop_fp_val_0),
.io_resp_bits_uop_fp_single (io_lsu_io_req_bits_uop_fp_single_0),
.io_resp_bits_uop_xcpt_pf_if (io_lsu_io_req_bits_uop_xcpt_pf_if_0),
.io_resp_bits_uop_xcpt_ae_if (io_lsu_io_req_bits_uop_xcpt_ae_if_0),
.io_resp_bits_uop_xcpt_ma_if (io_lsu_io_req_bits_uop_xcpt_ma_if_0),
.io_resp_bits_uop_bp_debug_if (io_lsu_io_req_bits_uop_bp_debug_if_0),
.io_resp_bits_uop_bp_xcpt_if (io_lsu_io_req_bits_uop_bp_xcpt_if_0),
.io_resp_bits_uop_debug_fsrc (io_lsu_io_req_bits_uop_debug_fsrc_0),
.io_resp_bits_uop_debug_tsrc (io_lsu_io_req_bits_uop_debug_tsrc_0),
.io_resp_bits_data (_maddrcalc_io_resp_bits_data),
.io_resp_bits_addr (io_lsu_io_req_bits_addr_0),
.io_resp_bits_mxcpt_valid (io_lsu_io_req_bits_mxcpt_valid_0),
.io_resp_bits_mxcpt_bits (io_lsu_io_req_bits_mxcpt_bits_0),
.io_resp_bits_sfence_valid (io_lsu_io_req_bits_sfence_valid_0),
.io_resp_bits_sfence_bits_rs1 (io_lsu_io_req_bits_sfence_bits_rs1_0),
.io_resp_bits_sfence_bits_rs2 (io_lsu_io_req_bits_sfence_bits_rs2_0),
.io_resp_bits_sfence_bits_addr (io_lsu_io_req_bits_sfence_bits_addr_0),
.io_resp_bits_sfence_bits_asid (io_lsu_io_req_bits_sfence_bits_asid_0),
.io_brupdate_b1_resolve_mask (io_brupdate_b1_resolve_mask_0), // @[execution-unit.scala:204:7]
.io_brupdate_b1_mispredict_mask (io_brupdate_b1_mispredict_mask_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_uopc (io_brupdate_b2_uop_uopc_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_inst (io_brupdate_b2_uop_inst_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_debug_inst (io_brupdate_b2_uop_debug_inst_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_is_rvc (io_brupdate_b2_uop_is_rvc_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_debug_pc (io_brupdate_b2_uop_debug_pc_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_iq_type (io_brupdate_b2_uop_iq_type_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_fu_code (io_brupdate_b2_uop_fu_code_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_ctrl_br_type (io_brupdate_b2_uop_ctrl_br_type_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_ctrl_op1_sel (io_brupdate_b2_uop_ctrl_op1_sel_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_ctrl_op2_sel (io_brupdate_b2_uop_ctrl_op2_sel_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_ctrl_imm_sel (io_brupdate_b2_uop_ctrl_imm_sel_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_ctrl_op_fcn (io_brupdate_b2_uop_ctrl_op_fcn_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_ctrl_fcn_dw (io_brupdate_b2_uop_ctrl_fcn_dw_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_ctrl_csr_cmd (io_brupdate_b2_uop_ctrl_csr_cmd_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_ctrl_is_load (io_brupdate_b2_uop_ctrl_is_load_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_ctrl_is_sta (io_brupdate_b2_uop_ctrl_is_sta_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_ctrl_is_std (io_brupdate_b2_uop_ctrl_is_std_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_iw_state (io_brupdate_b2_uop_iw_state_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_iw_p1_poisoned (io_brupdate_b2_uop_iw_p1_poisoned_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_iw_p2_poisoned (io_brupdate_b2_uop_iw_p2_poisoned_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_is_br (io_brupdate_b2_uop_is_br_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_is_jalr (io_brupdate_b2_uop_is_jalr_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_is_jal (io_brupdate_b2_uop_is_jal_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_is_sfb (io_brupdate_b2_uop_is_sfb_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_br_mask (io_brupdate_b2_uop_br_mask_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_br_tag (io_brupdate_b2_uop_br_tag_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_ftq_idx (io_brupdate_b2_uop_ftq_idx_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_edge_inst (io_brupdate_b2_uop_edge_inst_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_pc_lob (io_brupdate_b2_uop_pc_lob_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_taken (io_brupdate_b2_uop_taken_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_imm_packed (io_brupdate_b2_uop_imm_packed_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_csr_addr (io_brupdate_b2_uop_csr_addr_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_rob_idx (io_brupdate_b2_uop_rob_idx_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_ldq_idx (io_brupdate_b2_uop_ldq_idx_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_stq_idx (io_brupdate_b2_uop_stq_idx_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_rxq_idx (io_brupdate_b2_uop_rxq_idx_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_pdst (io_brupdate_b2_uop_pdst_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_prs1 (io_brupdate_b2_uop_prs1_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_prs2 (io_brupdate_b2_uop_prs2_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_prs3 (io_brupdate_b2_uop_prs3_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_ppred (io_brupdate_b2_uop_ppred_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_prs1_busy (io_brupdate_b2_uop_prs1_busy_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_prs2_busy (io_brupdate_b2_uop_prs2_busy_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_prs3_busy (io_brupdate_b2_uop_prs3_busy_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_ppred_busy (io_brupdate_b2_uop_ppred_busy_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_stale_pdst (io_brupdate_b2_uop_stale_pdst_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_exception (io_brupdate_b2_uop_exception_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_exc_cause (io_brupdate_b2_uop_exc_cause_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_bypassable (io_brupdate_b2_uop_bypassable_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_mem_cmd (io_brupdate_b2_uop_mem_cmd_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_mem_size (io_brupdate_b2_uop_mem_size_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_mem_signed (io_brupdate_b2_uop_mem_signed_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_is_fence (io_brupdate_b2_uop_is_fence_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_is_fencei (io_brupdate_b2_uop_is_fencei_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_is_amo (io_brupdate_b2_uop_is_amo_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_uses_ldq (io_brupdate_b2_uop_uses_ldq_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_uses_stq (io_brupdate_b2_uop_uses_stq_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_is_sys_pc2epc (io_brupdate_b2_uop_is_sys_pc2epc_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_is_unique (io_brupdate_b2_uop_is_unique_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_flush_on_commit (io_brupdate_b2_uop_flush_on_commit_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_ldst_is_rs1 (io_brupdate_b2_uop_ldst_is_rs1_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_ldst (io_brupdate_b2_uop_ldst_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_lrs1 (io_brupdate_b2_uop_lrs1_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_lrs2 (io_brupdate_b2_uop_lrs2_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_lrs3 (io_brupdate_b2_uop_lrs3_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_ldst_val (io_brupdate_b2_uop_ldst_val_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_dst_rtype (io_brupdate_b2_uop_dst_rtype_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_lrs1_rtype (io_brupdate_b2_uop_lrs1_rtype_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_lrs2_rtype (io_brupdate_b2_uop_lrs2_rtype_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_frs3_en (io_brupdate_b2_uop_frs3_en_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_fp_val (io_brupdate_b2_uop_fp_val_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_fp_single (io_brupdate_b2_uop_fp_single_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_xcpt_pf_if (io_brupdate_b2_uop_xcpt_pf_if_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_xcpt_ae_if (io_brupdate_b2_uop_xcpt_ae_if_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_xcpt_ma_if (io_brupdate_b2_uop_xcpt_ma_if_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_bp_debug_if (io_brupdate_b2_uop_bp_debug_if_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_bp_xcpt_if (io_brupdate_b2_uop_bp_xcpt_if_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_debug_fsrc (io_brupdate_b2_uop_debug_fsrc_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_uop_debug_tsrc (io_brupdate_b2_uop_debug_tsrc_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_valid (io_brupdate_b2_valid_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_mispredict (io_brupdate_b2_mispredict_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_taken (io_brupdate_b2_taken_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_cfi_type (io_brupdate_b2_cfi_type_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_pc_sel (io_brupdate_b2_pc_sel_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_jalr_target (io_brupdate_b2_jalr_target_0), // @[execution-unit.scala:204:7]
.io_brupdate_b2_target_offset (io_brupdate_b2_target_offset_0), // @[execution-unit.scala:204:7]
.io_status_debug (io_status_debug_0), // @[execution-unit.scala:204:7]
.io_status_cease (io_status_cease_0), // @[execution-unit.scala:204:7]
.io_status_wfi (io_status_wfi_0), // @[execution-unit.scala:204:7]
.io_status_dprv (io_status_dprv_0), // @[execution-unit.scala:204:7]
.io_status_dv (io_status_dv_0), // @[execution-unit.scala:204:7]
.io_status_prv (io_status_prv_0), // @[execution-unit.scala:204:7]
.io_status_v (io_status_v_0), // @[execution-unit.scala:204:7]
.io_status_sd (io_status_sd_0), // @[execution-unit.scala:204:7]
.io_status_mpv (io_status_mpv_0), // @[execution-unit.scala:204:7]
.io_status_gva (io_status_gva_0), // @[execution-unit.scala:204:7]
.io_status_tsr (io_status_tsr_0), // @[execution-unit.scala:204:7]
.io_status_tw (io_status_tw_0), // @[execution-unit.scala:204:7]
.io_status_tvm (io_status_tvm_0), // @[execution-unit.scala:204:7]
.io_status_mxr (io_status_mxr_0), // @[execution-unit.scala:204:7]
.io_status_sum (io_status_sum_0), // @[execution-unit.scala:204:7]
.io_status_mprv (io_status_mprv_0), // @[execution-unit.scala:204:7]
.io_status_fs (io_status_fs_0), // @[execution-unit.scala:204:7]
.io_status_mpp (io_status_mpp_0), // @[execution-unit.scala:204:7]
.io_status_spp (io_status_spp_0), // @[execution-unit.scala:204:7]
.io_status_mpie (io_status_mpie_0), // @[execution-unit.scala:204:7]
.io_status_spie (io_status_spie_0), // @[execution-unit.scala:204:7]
.io_status_mie (io_status_mie_0), // @[execution-unit.scala:204:7]
.io_status_sie (io_status_sie_0) // @[execution-unit.scala:204:7]
); // @[execution-unit.scala:388:27]
assign io_ll_iresp_valid = io_ll_iresp_valid_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_uopc = io_ll_iresp_bits_uop_uopc_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_inst = io_ll_iresp_bits_uop_inst_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_debug_inst = io_ll_iresp_bits_uop_debug_inst_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_is_rvc = io_ll_iresp_bits_uop_is_rvc_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_debug_pc = io_ll_iresp_bits_uop_debug_pc_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_iq_type = io_ll_iresp_bits_uop_iq_type_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_fu_code = io_ll_iresp_bits_uop_fu_code_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_ctrl_br_type = io_ll_iresp_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_ctrl_op1_sel = io_ll_iresp_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_ctrl_op2_sel = io_ll_iresp_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_ctrl_imm_sel = io_ll_iresp_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_ctrl_op_fcn = io_ll_iresp_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_ctrl_fcn_dw = io_ll_iresp_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_ctrl_csr_cmd = io_ll_iresp_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_ctrl_is_load = io_ll_iresp_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_ctrl_is_sta = io_ll_iresp_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_ctrl_is_std = io_ll_iresp_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_iw_state = io_ll_iresp_bits_uop_iw_state_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_iw_p1_poisoned = io_ll_iresp_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_iw_p2_poisoned = io_ll_iresp_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_is_br = io_ll_iresp_bits_uop_is_br_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_is_jalr = io_ll_iresp_bits_uop_is_jalr_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_is_jal = io_ll_iresp_bits_uop_is_jal_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_is_sfb = io_ll_iresp_bits_uop_is_sfb_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_br_mask = io_ll_iresp_bits_uop_br_mask_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_br_tag = io_ll_iresp_bits_uop_br_tag_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_ftq_idx = io_ll_iresp_bits_uop_ftq_idx_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_edge_inst = io_ll_iresp_bits_uop_edge_inst_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_pc_lob = io_ll_iresp_bits_uop_pc_lob_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_taken = io_ll_iresp_bits_uop_taken_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_imm_packed = io_ll_iresp_bits_uop_imm_packed_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_csr_addr = io_ll_iresp_bits_uop_csr_addr_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_rob_idx = io_ll_iresp_bits_uop_rob_idx_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_ldq_idx = io_ll_iresp_bits_uop_ldq_idx_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_stq_idx = io_ll_iresp_bits_uop_stq_idx_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_rxq_idx = io_ll_iresp_bits_uop_rxq_idx_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_pdst = io_ll_iresp_bits_uop_pdst_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_prs1 = io_ll_iresp_bits_uop_prs1_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_prs2 = io_ll_iresp_bits_uop_prs2_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_prs3 = io_ll_iresp_bits_uop_prs3_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_ppred = io_ll_iresp_bits_uop_ppred_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_prs1_busy = io_ll_iresp_bits_uop_prs1_busy_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_prs2_busy = io_ll_iresp_bits_uop_prs2_busy_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_prs3_busy = io_ll_iresp_bits_uop_prs3_busy_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_ppred_busy = io_ll_iresp_bits_uop_ppred_busy_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_stale_pdst = io_ll_iresp_bits_uop_stale_pdst_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_exception = io_ll_iresp_bits_uop_exception_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_exc_cause = io_ll_iresp_bits_uop_exc_cause_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_bypassable = io_ll_iresp_bits_uop_bypassable_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_mem_cmd = io_ll_iresp_bits_uop_mem_cmd_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_mem_size = io_ll_iresp_bits_uop_mem_size_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_mem_signed = io_ll_iresp_bits_uop_mem_signed_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_is_fence = io_ll_iresp_bits_uop_is_fence_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_is_fencei = io_ll_iresp_bits_uop_is_fencei_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_is_amo = io_ll_iresp_bits_uop_is_amo_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_uses_ldq = io_ll_iresp_bits_uop_uses_ldq_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_uses_stq = io_ll_iresp_bits_uop_uses_stq_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_is_sys_pc2epc = io_ll_iresp_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_is_unique = io_ll_iresp_bits_uop_is_unique_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_flush_on_commit = io_ll_iresp_bits_uop_flush_on_commit_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_ldst_is_rs1 = io_ll_iresp_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_ldst = io_ll_iresp_bits_uop_ldst_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_lrs1 = io_ll_iresp_bits_uop_lrs1_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_lrs2 = io_ll_iresp_bits_uop_lrs2_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_lrs3 = io_ll_iresp_bits_uop_lrs3_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_ldst_val = io_ll_iresp_bits_uop_ldst_val_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_dst_rtype = io_ll_iresp_bits_uop_dst_rtype_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_lrs1_rtype = io_ll_iresp_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_lrs2_rtype = io_ll_iresp_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_frs3_en = io_ll_iresp_bits_uop_frs3_en_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_fp_val = io_ll_iresp_bits_uop_fp_val_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_fp_single = io_ll_iresp_bits_uop_fp_single_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_xcpt_pf_if = io_ll_iresp_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_xcpt_ae_if = io_ll_iresp_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_xcpt_ma_if = io_ll_iresp_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_bp_debug_if = io_ll_iresp_bits_uop_bp_debug_if_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_bp_xcpt_if = io_ll_iresp_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_debug_fsrc = io_ll_iresp_bits_uop_debug_fsrc_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_uop_debug_tsrc = io_ll_iresp_bits_uop_debug_tsrc_0; // @[execution-unit.scala:204:7]
assign io_ll_iresp_bits_data = io_ll_iresp_bits_data_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_valid = io_ll_fresp_valid_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_uopc = io_ll_fresp_bits_uop_uopc_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_inst = io_ll_fresp_bits_uop_inst_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_debug_inst = io_ll_fresp_bits_uop_debug_inst_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_is_rvc = io_ll_fresp_bits_uop_is_rvc_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_debug_pc = io_ll_fresp_bits_uop_debug_pc_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_iq_type = io_ll_fresp_bits_uop_iq_type_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_fu_code = io_ll_fresp_bits_uop_fu_code_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_ctrl_br_type = io_ll_fresp_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_ctrl_op1_sel = io_ll_fresp_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_ctrl_op2_sel = io_ll_fresp_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_ctrl_imm_sel = io_ll_fresp_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_ctrl_op_fcn = io_ll_fresp_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_ctrl_fcn_dw = io_ll_fresp_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_ctrl_csr_cmd = io_ll_fresp_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_ctrl_is_load = io_ll_fresp_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_ctrl_is_sta = io_ll_fresp_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_ctrl_is_std = io_ll_fresp_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_iw_state = io_ll_fresp_bits_uop_iw_state_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_iw_p1_poisoned = io_ll_fresp_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_iw_p2_poisoned = io_ll_fresp_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_is_br = io_ll_fresp_bits_uop_is_br_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_is_jalr = io_ll_fresp_bits_uop_is_jalr_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_is_jal = io_ll_fresp_bits_uop_is_jal_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_is_sfb = io_ll_fresp_bits_uop_is_sfb_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_br_mask = io_ll_fresp_bits_uop_br_mask_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_br_tag = io_ll_fresp_bits_uop_br_tag_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_ftq_idx = io_ll_fresp_bits_uop_ftq_idx_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_edge_inst = io_ll_fresp_bits_uop_edge_inst_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_pc_lob = io_ll_fresp_bits_uop_pc_lob_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_taken = io_ll_fresp_bits_uop_taken_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_imm_packed = io_ll_fresp_bits_uop_imm_packed_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_csr_addr = io_ll_fresp_bits_uop_csr_addr_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_rob_idx = io_ll_fresp_bits_uop_rob_idx_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_ldq_idx = io_ll_fresp_bits_uop_ldq_idx_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_stq_idx = io_ll_fresp_bits_uop_stq_idx_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_rxq_idx = io_ll_fresp_bits_uop_rxq_idx_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_pdst = io_ll_fresp_bits_uop_pdst_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_prs1 = io_ll_fresp_bits_uop_prs1_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_prs2 = io_ll_fresp_bits_uop_prs2_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_prs3 = io_ll_fresp_bits_uop_prs3_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_ppred = io_ll_fresp_bits_uop_ppred_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_prs1_busy = io_ll_fresp_bits_uop_prs1_busy_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_prs2_busy = io_ll_fresp_bits_uop_prs2_busy_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_prs3_busy = io_ll_fresp_bits_uop_prs3_busy_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_ppred_busy = io_ll_fresp_bits_uop_ppred_busy_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_stale_pdst = io_ll_fresp_bits_uop_stale_pdst_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_exception = io_ll_fresp_bits_uop_exception_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_exc_cause = io_ll_fresp_bits_uop_exc_cause_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_bypassable = io_ll_fresp_bits_uop_bypassable_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_mem_cmd = io_ll_fresp_bits_uop_mem_cmd_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_mem_size = io_ll_fresp_bits_uop_mem_size_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_mem_signed = io_ll_fresp_bits_uop_mem_signed_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_is_fence = io_ll_fresp_bits_uop_is_fence_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_is_fencei = io_ll_fresp_bits_uop_is_fencei_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_is_amo = io_ll_fresp_bits_uop_is_amo_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_uses_ldq = io_ll_fresp_bits_uop_uses_ldq_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_uses_stq = io_ll_fresp_bits_uop_uses_stq_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_is_sys_pc2epc = io_ll_fresp_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_is_unique = io_ll_fresp_bits_uop_is_unique_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_flush_on_commit = io_ll_fresp_bits_uop_flush_on_commit_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_ldst_is_rs1 = io_ll_fresp_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_ldst = io_ll_fresp_bits_uop_ldst_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_lrs1 = io_ll_fresp_bits_uop_lrs1_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_lrs2 = io_ll_fresp_bits_uop_lrs2_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_lrs3 = io_ll_fresp_bits_uop_lrs3_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_ldst_val = io_ll_fresp_bits_uop_ldst_val_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_dst_rtype = io_ll_fresp_bits_uop_dst_rtype_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_lrs1_rtype = io_ll_fresp_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_lrs2_rtype = io_ll_fresp_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_frs3_en = io_ll_fresp_bits_uop_frs3_en_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_fp_val = io_ll_fresp_bits_uop_fp_val_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_fp_single = io_ll_fresp_bits_uop_fp_single_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_xcpt_pf_if = io_ll_fresp_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_xcpt_ae_if = io_ll_fresp_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_xcpt_ma_if = io_ll_fresp_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_bp_debug_if = io_ll_fresp_bits_uop_bp_debug_if_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_bp_xcpt_if = io_ll_fresp_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_debug_fsrc = io_ll_fresp_bits_uop_debug_fsrc_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_uop_debug_tsrc = io_ll_fresp_bits_uop_debug_tsrc_0; // @[execution-unit.scala:204:7]
assign io_ll_fresp_bits_data = io_ll_fresp_bits_data_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_valid = io_lsu_io_req_valid_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_uopc = io_lsu_io_req_bits_uop_uopc_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_inst = io_lsu_io_req_bits_uop_inst_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_debug_inst = io_lsu_io_req_bits_uop_debug_inst_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_is_rvc = io_lsu_io_req_bits_uop_is_rvc_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_debug_pc = io_lsu_io_req_bits_uop_debug_pc_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_iq_type = io_lsu_io_req_bits_uop_iq_type_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_fu_code = io_lsu_io_req_bits_uop_fu_code_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_ctrl_br_type = io_lsu_io_req_bits_uop_ctrl_br_type_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_ctrl_op1_sel = io_lsu_io_req_bits_uop_ctrl_op1_sel_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_ctrl_op2_sel = io_lsu_io_req_bits_uop_ctrl_op2_sel_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_ctrl_imm_sel = io_lsu_io_req_bits_uop_ctrl_imm_sel_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_ctrl_op_fcn = io_lsu_io_req_bits_uop_ctrl_op_fcn_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_ctrl_fcn_dw = io_lsu_io_req_bits_uop_ctrl_fcn_dw_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_ctrl_csr_cmd = io_lsu_io_req_bits_uop_ctrl_csr_cmd_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_ctrl_is_load = io_lsu_io_req_bits_uop_ctrl_is_load_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_ctrl_is_sta = io_lsu_io_req_bits_uop_ctrl_is_sta_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_ctrl_is_std = io_lsu_io_req_bits_uop_ctrl_is_std_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_iw_state = io_lsu_io_req_bits_uop_iw_state_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_iw_p1_poisoned = io_lsu_io_req_bits_uop_iw_p1_poisoned_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_iw_p2_poisoned = io_lsu_io_req_bits_uop_iw_p2_poisoned_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_is_br = io_lsu_io_req_bits_uop_is_br_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_is_jalr = io_lsu_io_req_bits_uop_is_jalr_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_is_jal = io_lsu_io_req_bits_uop_is_jal_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_is_sfb = io_lsu_io_req_bits_uop_is_sfb_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_br_mask = io_lsu_io_req_bits_uop_br_mask_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_br_tag = io_lsu_io_req_bits_uop_br_tag_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_ftq_idx = io_lsu_io_req_bits_uop_ftq_idx_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_edge_inst = io_lsu_io_req_bits_uop_edge_inst_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_pc_lob = io_lsu_io_req_bits_uop_pc_lob_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_taken = io_lsu_io_req_bits_uop_taken_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_imm_packed = io_lsu_io_req_bits_uop_imm_packed_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_csr_addr = io_lsu_io_req_bits_uop_csr_addr_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_rob_idx = io_lsu_io_req_bits_uop_rob_idx_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_ldq_idx = io_lsu_io_req_bits_uop_ldq_idx_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_stq_idx = io_lsu_io_req_bits_uop_stq_idx_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_rxq_idx = io_lsu_io_req_bits_uop_rxq_idx_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_pdst = io_lsu_io_req_bits_uop_pdst_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_prs1 = io_lsu_io_req_bits_uop_prs1_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_prs2 = io_lsu_io_req_bits_uop_prs2_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_prs3 = io_lsu_io_req_bits_uop_prs3_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_ppred = io_lsu_io_req_bits_uop_ppred_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_prs1_busy = io_lsu_io_req_bits_uop_prs1_busy_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_prs2_busy = io_lsu_io_req_bits_uop_prs2_busy_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_prs3_busy = io_lsu_io_req_bits_uop_prs3_busy_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_ppred_busy = io_lsu_io_req_bits_uop_ppred_busy_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_stale_pdst = io_lsu_io_req_bits_uop_stale_pdst_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_exception = io_lsu_io_req_bits_uop_exception_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_exc_cause = io_lsu_io_req_bits_uop_exc_cause_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_bypassable = io_lsu_io_req_bits_uop_bypassable_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_mem_cmd = io_lsu_io_req_bits_uop_mem_cmd_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_mem_size = io_lsu_io_req_bits_uop_mem_size_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_mem_signed = io_lsu_io_req_bits_uop_mem_signed_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_is_fence = io_lsu_io_req_bits_uop_is_fence_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_is_fencei = io_lsu_io_req_bits_uop_is_fencei_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_is_amo = io_lsu_io_req_bits_uop_is_amo_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_uses_ldq = io_lsu_io_req_bits_uop_uses_ldq_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_uses_stq = io_lsu_io_req_bits_uop_uses_stq_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_is_sys_pc2epc = io_lsu_io_req_bits_uop_is_sys_pc2epc_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_is_unique = io_lsu_io_req_bits_uop_is_unique_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_flush_on_commit = io_lsu_io_req_bits_uop_flush_on_commit_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_ldst_is_rs1 = io_lsu_io_req_bits_uop_ldst_is_rs1_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_ldst = io_lsu_io_req_bits_uop_ldst_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_lrs1 = io_lsu_io_req_bits_uop_lrs1_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_lrs2 = io_lsu_io_req_bits_uop_lrs2_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_lrs3 = io_lsu_io_req_bits_uop_lrs3_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_ldst_val = io_lsu_io_req_bits_uop_ldst_val_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_dst_rtype = io_lsu_io_req_bits_uop_dst_rtype_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_lrs1_rtype = io_lsu_io_req_bits_uop_lrs1_rtype_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_lrs2_rtype = io_lsu_io_req_bits_uop_lrs2_rtype_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_frs3_en = io_lsu_io_req_bits_uop_frs3_en_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_fp_val = io_lsu_io_req_bits_uop_fp_val_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_fp_single = io_lsu_io_req_bits_uop_fp_single_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_xcpt_pf_if = io_lsu_io_req_bits_uop_xcpt_pf_if_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_xcpt_ae_if = io_lsu_io_req_bits_uop_xcpt_ae_if_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_xcpt_ma_if = io_lsu_io_req_bits_uop_xcpt_ma_if_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_bp_debug_if = io_lsu_io_req_bits_uop_bp_debug_if_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_bp_xcpt_if = io_lsu_io_req_bits_uop_bp_xcpt_if_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_debug_fsrc = io_lsu_io_req_bits_uop_debug_fsrc_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_uop_debug_tsrc = io_lsu_io_req_bits_uop_debug_tsrc_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_data = io_lsu_io_req_bits_data_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_addr = io_lsu_io_req_bits_addr_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_mxcpt_valid = io_lsu_io_req_bits_mxcpt_valid_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_mxcpt_bits = io_lsu_io_req_bits_mxcpt_bits_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_sfence_valid = io_lsu_io_req_bits_sfence_valid_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_sfence_bits_rs1 = io_lsu_io_req_bits_sfence_bits_rs1_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_sfence_bits_rs2 = io_lsu_io_req_bits_sfence_bits_rs2_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_sfence_bits_addr = io_lsu_io_req_bits_sfence_bits_addr_0; // @[execution-unit.scala:204:7]
assign io_lsu_io_req_bits_sfence_bits_asid = io_lsu_io_req_bits_sfence_bits_asid_0; // @[execution-unit.scala:204:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLXbar_i2_o1_a32d128s5k4z4u :
input clock : Clock
input reset : Reset
output auto : { flip anon_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}, flip anon_in_0 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}}
wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}
invalidate anonIn.d.bits.corrupt
invalidate anonIn.d.bits.data
invalidate anonIn.d.bits.denied
invalidate anonIn.d.bits.sink
invalidate anonIn.d.bits.source
invalidate anonIn.d.bits.size
invalidate anonIn.d.bits.param
invalidate anonIn.d.bits.opcode
invalidate anonIn.d.valid
invalidate anonIn.d.ready
invalidate anonIn.a.bits.corrupt
invalidate anonIn.a.bits.data
invalidate anonIn.a.bits.mask
invalidate anonIn.a.bits.address
invalidate anonIn.a.bits.source
invalidate anonIn.a.bits.size
invalidate anonIn.a.bits.param
invalidate anonIn.a.bits.opcode
invalidate anonIn.a.valid
invalidate anonIn.a.ready
wire anonIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}
invalidate anonIn_1.d.bits.corrupt
invalidate anonIn_1.d.bits.data
invalidate anonIn_1.d.bits.denied
invalidate anonIn_1.d.bits.sink
invalidate anonIn_1.d.bits.source
invalidate anonIn_1.d.bits.size
invalidate anonIn_1.d.bits.param
invalidate anonIn_1.d.bits.opcode
invalidate anonIn_1.d.valid
invalidate anonIn_1.d.ready
invalidate anonIn_1.a.bits.corrupt
invalidate anonIn_1.a.bits.data
invalidate anonIn_1.a.bits.mask
invalidate anonIn_1.a.bits.address
invalidate anonIn_1.a.bits.source
invalidate anonIn_1.a.bits.size
invalidate anonIn_1.a.bits.param
invalidate anonIn_1.a.bits.opcode
invalidate anonIn_1.a.valid
invalidate anonIn_1.a.ready
inst monitor of TLMonitor_43
connect monitor.clock, clock
connect monitor.reset, reset
connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt
connect monitor.io.in.d.bits.data, anonIn.d.bits.data
connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied
connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink
connect monitor.io.in.d.bits.source, anonIn.d.bits.source
connect monitor.io.in.d.bits.size, anonIn.d.bits.size
connect monitor.io.in.d.bits.param, anonIn.d.bits.param
connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode
connect monitor.io.in.d.valid, anonIn.d.valid
connect monitor.io.in.d.ready, anonIn.d.ready
connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt
connect monitor.io.in.a.bits.data, anonIn.a.bits.data
connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask
connect monitor.io.in.a.bits.address, anonIn.a.bits.address
connect monitor.io.in.a.bits.source, anonIn.a.bits.source
connect monitor.io.in.a.bits.size, anonIn.a.bits.size
connect monitor.io.in.a.bits.param, anonIn.a.bits.param
connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode
connect monitor.io.in.a.valid, anonIn.a.valid
connect monitor.io.in.a.ready, anonIn.a.ready
inst monitor_1 of TLMonitor_44
connect monitor_1.clock, clock
connect monitor_1.reset, reset
connect monitor_1.io.in.d.bits.corrupt, anonIn_1.d.bits.corrupt
connect monitor_1.io.in.d.bits.data, anonIn_1.d.bits.data
connect monitor_1.io.in.d.bits.denied, anonIn_1.d.bits.denied
connect monitor_1.io.in.d.bits.sink, anonIn_1.d.bits.sink
connect monitor_1.io.in.d.bits.source, anonIn_1.d.bits.source
connect monitor_1.io.in.d.bits.size, anonIn_1.d.bits.size
connect monitor_1.io.in.d.bits.param, anonIn_1.d.bits.param
connect monitor_1.io.in.d.bits.opcode, anonIn_1.d.bits.opcode
connect monitor_1.io.in.d.valid, anonIn_1.d.valid
connect monitor_1.io.in.d.ready, anonIn_1.d.ready
connect monitor_1.io.in.a.bits.corrupt, anonIn_1.a.bits.corrupt
connect monitor_1.io.in.a.bits.data, anonIn_1.a.bits.data
connect monitor_1.io.in.a.bits.mask, anonIn_1.a.bits.mask
connect monitor_1.io.in.a.bits.address, anonIn_1.a.bits.address
connect monitor_1.io.in.a.bits.source, anonIn_1.a.bits.source
connect monitor_1.io.in.a.bits.size, anonIn_1.a.bits.size
connect monitor_1.io.in.a.bits.param, anonIn_1.a.bits.param
connect monitor_1.io.in.a.bits.opcode, anonIn_1.a.bits.opcode
connect monitor_1.io.in.a.valid, anonIn_1.a.valid
connect monitor_1.io.in.a.ready, anonIn_1.a.ready
wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}
invalidate anonOut.d.bits.corrupt
invalidate anonOut.d.bits.data
invalidate anonOut.d.bits.denied
invalidate anonOut.d.bits.sink
invalidate anonOut.d.bits.source
invalidate anonOut.d.bits.size
invalidate anonOut.d.bits.param
invalidate anonOut.d.bits.opcode
invalidate anonOut.d.valid
invalidate anonOut.d.ready
invalidate anonOut.a.bits.corrupt
invalidate anonOut.a.bits.data
invalidate anonOut.a.bits.mask
invalidate anonOut.a.bits.address
invalidate anonOut.a.bits.source
invalidate anonOut.a.bits.size
invalidate anonOut.a.bits.param
invalidate anonOut.a.bits.opcode
invalidate anonOut.a.valid
invalidate anonOut.a.ready
connect auto.anon_out, anonOut
connect anonIn, auto.anon_in_0
connect anonIn_1, auto.anon_in_1
wire in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}[2]
connect in[0].a.bits.corrupt, anonIn.a.bits.corrupt
connect in[0].a.bits.data, anonIn.a.bits.data
connect in[0].a.bits.mask, anonIn.a.bits.mask
connect in[0].a.bits.address, anonIn.a.bits.address
connect in[0].a.bits.source, anonIn.a.bits.source
connect in[0].a.bits.size, anonIn.a.bits.size
connect in[0].a.bits.param, anonIn.a.bits.param
connect in[0].a.bits.opcode, anonIn.a.bits.opcode
connect in[0].a.valid, anonIn.a.valid
connect anonIn.a.ready, in[0].a.ready
node _in_0_a_bits_source_T = or(anonIn.a.bits.source, UInt<5>(0h10))
connect in[0].a.bits.source, _in_0_a_bits_source_T
wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE.bits.corrupt, UInt<1>(0h0)
connect _WIRE.bits.data, UInt<128>(0h0)
connect _WIRE.bits.mask, UInt<16>(0h0)
connect _WIRE.bits.address, UInt<32>(0h0)
connect _WIRE.bits.source, UInt<5>(0h0)
connect _WIRE.bits.size, UInt<4>(0h0)
connect _WIRE.bits.param, UInt<2>(0h0)
connect _WIRE.bits.opcode, UInt<3>(0h0)
connect _WIRE.valid, UInt<1>(0h0)
connect _WIRE.ready, UInt<1>(0h0)
wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_1.bits, _WIRE.bits
connect _WIRE_1.valid, _WIRE.valid
connect _WIRE_1.ready, _WIRE.ready
invalidate _WIRE_1.bits.corrupt
invalidate _WIRE_1.bits.data
invalidate _WIRE_1.bits.mask
invalidate _WIRE_1.bits.address
invalidate _WIRE_1.bits.source
invalidate _WIRE_1.bits.size
invalidate _WIRE_1.bits.param
invalidate _WIRE_1.bits.opcode
invalidate _WIRE_1.valid
invalidate _WIRE_1.ready
wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _WIRE_2.bits.data, UInt<128>(0h0)
connect _WIRE_2.bits.mask, UInt<16>(0h0)
connect _WIRE_2.bits.address, UInt<32>(0h0)
connect _WIRE_2.bits.source, UInt<4>(0h0)
connect _WIRE_2.bits.size, UInt<4>(0h0)
connect _WIRE_2.bits.param, UInt<2>(0h0)
connect _WIRE_2.bits.opcode, UInt<3>(0h0)
connect _WIRE_2.valid, UInt<1>(0h0)
connect _WIRE_2.ready, UInt<1>(0h0)
wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_3.bits, _WIRE_2.bits
connect _WIRE_3.valid, _WIRE_2.valid
connect _WIRE_3.ready, _WIRE_2.ready
invalidate _WIRE_3.bits.corrupt
invalidate _WIRE_3.bits.data
invalidate _WIRE_3.bits.mask
invalidate _WIRE_3.bits.address
invalidate _WIRE_3.bits.source
invalidate _WIRE_3.bits.size
invalidate _WIRE_3.bits.param
invalidate _WIRE_3.bits.opcode
invalidate _WIRE_3.valid
invalidate _WIRE_3.ready
wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_4.bits.corrupt, UInt<1>(0h0)
connect _WIRE_4.bits.data, UInt<128>(0h0)
connect _WIRE_4.bits.mask, UInt<16>(0h0)
connect _WIRE_4.bits.address, UInt<32>(0h0)
connect _WIRE_4.bits.source, UInt<5>(0h0)
connect _WIRE_4.bits.size, UInt<4>(0h0)
connect _WIRE_4.bits.param, UInt<2>(0h0)
connect _WIRE_4.bits.opcode, UInt<3>(0h0)
connect _WIRE_4.valid, UInt<1>(0h0)
connect _WIRE_4.ready, UInt<1>(0h0)
wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_5.bits, _WIRE_4.bits
connect _WIRE_5.valid, _WIRE_4.valid
connect _WIRE_5.ready, _WIRE_4.ready
connect _WIRE_5.ready, UInt<1>(0h1)
wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_6.bits.corrupt, UInt<1>(0h0)
connect _WIRE_6.bits.data, UInt<128>(0h0)
connect _WIRE_6.bits.mask, UInt<16>(0h0)
connect _WIRE_6.bits.address, UInt<32>(0h0)
connect _WIRE_6.bits.source, UInt<4>(0h0)
connect _WIRE_6.bits.size, UInt<4>(0h0)
connect _WIRE_6.bits.param, UInt<2>(0h0)
connect _WIRE_6.bits.opcode, UInt<3>(0h0)
connect _WIRE_6.valid, UInt<1>(0h0)
connect _WIRE_6.ready, UInt<1>(0h0)
wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_7.bits, _WIRE_6.bits
connect _WIRE_7.valid, _WIRE_6.valid
connect _WIRE_7.ready, _WIRE_6.ready
connect _WIRE_7.valid, UInt<1>(0h0)
wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_8.bits.corrupt, UInt<1>(0h0)
connect _WIRE_8.bits.data, UInt<128>(0h0)
connect _WIRE_8.bits.address, UInt<32>(0h0)
connect _WIRE_8.bits.source, UInt<5>(0h0)
connect _WIRE_8.bits.size, UInt<4>(0h0)
connect _WIRE_8.bits.param, UInt<3>(0h0)
connect _WIRE_8.bits.opcode, UInt<3>(0h0)
connect _WIRE_8.valid, UInt<1>(0h0)
connect _WIRE_8.ready, UInt<1>(0h0)
wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_9.bits, _WIRE_8.bits
connect _WIRE_9.valid, _WIRE_8.valid
connect _WIRE_9.ready, _WIRE_8.ready
invalidate _WIRE_9.bits.corrupt
invalidate _WIRE_9.bits.data
invalidate _WIRE_9.bits.address
invalidate _WIRE_9.bits.source
invalidate _WIRE_9.bits.size
invalidate _WIRE_9.bits.param
invalidate _WIRE_9.bits.opcode
invalidate _WIRE_9.valid
invalidate _WIRE_9.ready
wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_10.bits.corrupt, UInt<1>(0h0)
connect _WIRE_10.bits.data, UInt<128>(0h0)
connect _WIRE_10.bits.address, UInt<32>(0h0)
connect _WIRE_10.bits.source, UInt<4>(0h0)
connect _WIRE_10.bits.size, UInt<4>(0h0)
connect _WIRE_10.bits.param, UInt<3>(0h0)
connect _WIRE_10.bits.opcode, UInt<3>(0h0)
connect _WIRE_10.valid, UInt<1>(0h0)
connect _WIRE_10.ready, UInt<1>(0h0)
wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_11.bits, _WIRE_10.bits
connect _WIRE_11.valid, _WIRE_10.valid
connect _WIRE_11.ready, _WIRE_10.ready
invalidate _WIRE_11.bits.corrupt
invalidate _WIRE_11.bits.data
invalidate _WIRE_11.bits.address
invalidate _WIRE_11.bits.source
invalidate _WIRE_11.bits.size
invalidate _WIRE_11.bits.param
invalidate _WIRE_11.bits.opcode
invalidate _WIRE_11.valid
invalidate _WIRE_11.ready
wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_12.bits.corrupt, UInt<1>(0h0)
connect _WIRE_12.bits.data, UInt<128>(0h0)
connect _WIRE_12.bits.address, UInt<32>(0h0)
connect _WIRE_12.bits.source, UInt<5>(0h0)
connect _WIRE_12.bits.size, UInt<4>(0h0)
connect _WIRE_12.bits.param, UInt<3>(0h0)
connect _WIRE_12.bits.opcode, UInt<3>(0h0)
connect _WIRE_12.valid, UInt<1>(0h0)
connect _WIRE_12.ready, UInt<1>(0h0)
wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_13.bits, _WIRE_12.bits
connect _WIRE_13.valid, _WIRE_12.valid
connect _WIRE_13.ready, _WIRE_12.ready
connect _WIRE_13.valid, UInt<1>(0h0)
wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_14.bits.corrupt, UInt<1>(0h0)
connect _WIRE_14.bits.data, UInt<128>(0h0)
connect _WIRE_14.bits.address, UInt<32>(0h0)
connect _WIRE_14.bits.source, UInt<4>(0h0)
connect _WIRE_14.bits.size, UInt<4>(0h0)
connect _WIRE_14.bits.param, UInt<3>(0h0)
connect _WIRE_14.bits.opcode, UInt<3>(0h0)
connect _WIRE_14.valid, UInt<1>(0h0)
connect _WIRE_14.ready, UInt<1>(0h0)
wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_15.bits, _WIRE_14.bits
connect _WIRE_15.valid, _WIRE_14.valid
connect _WIRE_15.ready, _WIRE_14.ready
connect _WIRE_15.ready, UInt<1>(0h1)
connect anonIn.d.bits.corrupt, in[0].d.bits.corrupt
connect anonIn.d.bits.data, in[0].d.bits.data
connect anonIn.d.bits.denied, in[0].d.bits.denied
connect anonIn.d.bits.sink, in[0].d.bits.sink
connect anonIn.d.bits.source, in[0].d.bits.source
connect anonIn.d.bits.size, in[0].d.bits.size
connect anonIn.d.bits.param, in[0].d.bits.param
connect anonIn.d.bits.opcode, in[0].d.bits.opcode
connect anonIn.d.valid, in[0].d.valid
connect in[0].d.ready, anonIn.d.ready
node _anonIn_d_bits_source_T = bits(in[0].d.bits.source, 3, 0)
connect anonIn.d.bits.source, _anonIn_d_bits_source_T
wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_16.bits.sink, UInt<4>(0h0)
connect _WIRE_16.valid, UInt<1>(0h0)
connect _WIRE_16.ready, UInt<1>(0h0)
wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_17.bits, _WIRE_16.bits
connect _WIRE_17.valid, _WIRE_16.valid
connect _WIRE_17.ready, _WIRE_16.ready
invalidate _WIRE_17.bits.sink
invalidate _WIRE_17.valid
invalidate _WIRE_17.ready
wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_18.bits.sink, UInt<4>(0h0)
connect _WIRE_18.valid, UInt<1>(0h0)
connect _WIRE_18.ready, UInt<1>(0h0)
wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_19.bits, _WIRE_18.bits
connect _WIRE_19.valid, _WIRE_18.valid
connect _WIRE_19.ready, _WIRE_18.ready
invalidate _WIRE_19.bits.sink
invalidate _WIRE_19.valid
invalidate _WIRE_19.ready
wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_20.bits.sink, UInt<4>(0h0)
connect _WIRE_20.valid, UInt<1>(0h0)
connect _WIRE_20.ready, UInt<1>(0h0)
wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_21.bits, _WIRE_20.bits
connect _WIRE_21.valid, _WIRE_20.valid
connect _WIRE_21.ready, _WIRE_20.ready
connect _WIRE_21.valid, UInt<1>(0h0)
wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_22.bits.sink, UInt<4>(0h0)
connect _WIRE_22.valid, UInt<1>(0h0)
connect _WIRE_22.ready, UInt<1>(0h0)
wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_23.bits, _WIRE_22.bits
connect _WIRE_23.valid, _WIRE_22.valid
connect _WIRE_23.ready, _WIRE_22.ready
connect _WIRE_23.ready, UInt<1>(0h1)
connect in[1].a.bits.corrupt, anonIn_1.a.bits.corrupt
connect in[1].a.bits.data, anonIn_1.a.bits.data
connect in[1].a.bits.mask, anonIn_1.a.bits.mask
connect in[1].a.bits.address, anonIn_1.a.bits.address
connect in[1].a.bits.source, anonIn_1.a.bits.source
connect in[1].a.bits.size, anonIn_1.a.bits.size
connect in[1].a.bits.param, anonIn_1.a.bits.param
connect in[1].a.bits.opcode, anonIn_1.a.bits.opcode
connect in[1].a.valid, anonIn_1.a.valid
connect anonIn_1.a.ready, in[1].a.ready
node _in_1_a_bits_source_T = or(anonIn_1.a.bits.source, UInt<1>(0h0))
connect in[1].a.bits.source, _in_1_a_bits_source_T
wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_24.bits.corrupt, UInt<1>(0h0)
connect _WIRE_24.bits.data, UInt<128>(0h0)
connect _WIRE_24.bits.mask, UInt<16>(0h0)
connect _WIRE_24.bits.address, UInt<32>(0h0)
connect _WIRE_24.bits.source, UInt<5>(0h0)
connect _WIRE_24.bits.size, UInt<4>(0h0)
connect _WIRE_24.bits.param, UInt<2>(0h0)
connect _WIRE_24.bits.opcode, UInt<3>(0h0)
connect _WIRE_24.valid, UInt<1>(0h0)
connect _WIRE_24.ready, UInt<1>(0h0)
wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_25.bits, _WIRE_24.bits
connect _WIRE_25.valid, _WIRE_24.valid
connect _WIRE_25.ready, _WIRE_24.ready
invalidate _WIRE_25.bits.corrupt
invalidate _WIRE_25.bits.data
invalidate _WIRE_25.bits.mask
invalidate _WIRE_25.bits.address
invalidate _WIRE_25.bits.source
invalidate _WIRE_25.bits.size
invalidate _WIRE_25.bits.param
invalidate _WIRE_25.bits.opcode
invalidate _WIRE_25.valid
invalidate _WIRE_25.ready
wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_26.bits.corrupt, UInt<1>(0h0)
connect _WIRE_26.bits.data, UInt<128>(0h0)
connect _WIRE_26.bits.mask, UInt<16>(0h0)
connect _WIRE_26.bits.address, UInt<32>(0h0)
connect _WIRE_26.bits.source, UInt<4>(0h0)
connect _WIRE_26.bits.size, UInt<4>(0h0)
connect _WIRE_26.bits.param, UInt<2>(0h0)
connect _WIRE_26.bits.opcode, UInt<3>(0h0)
connect _WIRE_26.valid, UInt<1>(0h0)
connect _WIRE_26.ready, UInt<1>(0h0)
wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_27.bits, _WIRE_26.bits
connect _WIRE_27.valid, _WIRE_26.valid
connect _WIRE_27.ready, _WIRE_26.ready
invalidate _WIRE_27.bits.corrupt
invalidate _WIRE_27.bits.data
invalidate _WIRE_27.bits.mask
invalidate _WIRE_27.bits.address
invalidate _WIRE_27.bits.source
invalidate _WIRE_27.bits.size
invalidate _WIRE_27.bits.param
invalidate _WIRE_27.bits.opcode
invalidate _WIRE_27.valid
invalidate _WIRE_27.ready
wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_28.bits.corrupt, UInt<1>(0h0)
connect _WIRE_28.bits.data, UInt<128>(0h0)
connect _WIRE_28.bits.mask, UInt<16>(0h0)
connect _WIRE_28.bits.address, UInt<32>(0h0)
connect _WIRE_28.bits.source, UInt<5>(0h0)
connect _WIRE_28.bits.size, UInt<4>(0h0)
connect _WIRE_28.bits.param, UInt<2>(0h0)
connect _WIRE_28.bits.opcode, UInt<3>(0h0)
connect _WIRE_28.valid, UInt<1>(0h0)
connect _WIRE_28.ready, UInt<1>(0h0)
wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_29.bits, _WIRE_28.bits
connect _WIRE_29.valid, _WIRE_28.valid
connect _WIRE_29.ready, _WIRE_28.ready
connect _WIRE_29.ready, UInt<1>(0h1)
wire _WIRE_30 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_30.bits.corrupt, UInt<1>(0h0)
connect _WIRE_30.bits.data, UInt<128>(0h0)
connect _WIRE_30.bits.mask, UInt<16>(0h0)
connect _WIRE_30.bits.address, UInt<32>(0h0)
connect _WIRE_30.bits.source, UInt<4>(0h0)
connect _WIRE_30.bits.size, UInt<4>(0h0)
connect _WIRE_30.bits.param, UInt<2>(0h0)
connect _WIRE_30.bits.opcode, UInt<3>(0h0)
connect _WIRE_30.valid, UInt<1>(0h0)
connect _WIRE_30.ready, UInt<1>(0h0)
wire _WIRE_31 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_31.bits, _WIRE_30.bits
connect _WIRE_31.valid, _WIRE_30.valid
connect _WIRE_31.ready, _WIRE_30.ready
connect _WIRE_31.valid, UInt<1>(0h0)
wire _WIRE_32 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_32.bits.corrupt, UInt<1>(0h0)
connect _WIRE_32.bits.data, UInt<128>(0h0)
connect _WIRE_32.bits.address, UInt<32>(0h0)
connect _WIRE_32.bits.source, UInt<5>(0h0)
connect _WIRE_32.bits.size, UInt<4>(0h0)
connect _WIRE_32.bits.param, UInt<3>(0h0)
connect _WIRE_32.bits.opcode, UInt<3>(0h0)
connect _WIRE_32.valid, UInt<1>(0h0)
connect _WIRE_32.ready, UInt<1>(0h0)
wire _WIRE_33 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_33.bits, _WIRE_32.bits
connect _WIRE_33.valid, _WIRE_32.valid
connect _WIRE_33.ready, _WIRE_32.ready
invalidate _WIRE_33.bits.corrupt
invalidate _WIRE_33.bits.data
invalidate _WIRE_33.bits.address
invalidate _WIRE_33.bits.source
invalidate _WIRE_33.bits.size
invalidate _WIRE_33.bits.param
invalidate _WIRE_33.bits.opcode
invalidate _WIRE_33.valid
invalidate _WIRE_33.ready
wire _WIRE_34 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_34.bits.corrupt, UInt<1>(0h0)
connect _WIRE_34.bits.data, UInt<128>(0h0)
connect _WIRE_34.bits.address, UInt<32>(0h0)
connect _WIRE_34.bits.source, UInt<4>(0h0)
connect _WIRE_34.bits.size, UInt<4>(0h0)
connect _WIRE_34.bits.param, UInt<3>(0h0)
connect _WIRE_34.bits.opcode, UInt<3>(0h0)
connect _WIRE_34.valid, UInt<1>(0h0)
connect _WIRE_34.ready, UInt<1>(0h0)
wire _WIRE_35 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_35.bits, _WIRE_34.bits
connect _WIRE_35.valid, _WIRE_34.valid
connect _WIRE_35.ready, _WIRE_34.ready
invalidate _WIRE_35.bits.corrupt
invalidate _WIRE_35.bits.data
invalidate _WIRE_35.bits.address
invalidate _WIRE_35.bits.source
invalidate _WIRE_35.bits.size
invalidate _WIRE_35.bits.param
invalidate _WIRE_35.bits.opcode
invalidate _WIRE_35.valid
invalidate _WIRE_35.ready
wire _WIRE_36 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_36.bits.corrupt, UInt<1>(0h0)
connect _WIRE_36.bits.data, UInt<128>(0h0)
connect _WIRE_36.bits.address, UInt<32>(0h0)
connect _WIRE_36.bits.source, UInt<5>(0h0)
connect _WIRE_36.bits.size, UInt<4>(0h0)
connect _WIRE_36.bits.param, UInt<3>(0h0)
connect _WIRE_36.bits.opcode, UInt<3>(0h0)
connect _WIRE_36.valid, UInt<1>(0h0)
connect _WIRE_36.ready, UInt<1>(0h0)
wire _WIRE_37 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_37.bits, _WIRE_36.bits
connect _WIRE_37.valid, _WIRE_36.valid
connect _WIRE_37.ready, _WIRE_36.ready
connect _WIRE_37.valid, UInt<1>(0h0)
wire _WIRE_38 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_38.bits.corrupt, UInt<1>(0h0)
connect _WIRE_38.bits.data, UInt<128>(0h0)
connect _WIRE_38.bits.address, UInt<32>(0h0)
connect _WIRE_38.bits.source, UInt<4>(0h0)
connect _WIRE_38.bits.size, UInt<4>(0h0)
connect _WIRE_38.bits.param, UInt<3>(0h0)
connect _WIRE_38.bits.opcode, UInt<3>(0h0)
connect _WIRE_38.valid, UInt<1>(0h0)
connect _WIRE_38.ready, UInt<1>(0h0)
wire _WIRE_39 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_39.bits, _WIRE_38.bits
connect _WIRE_39.valid, _WIRE_38.valid
connect _WIRE_39.ready, _WIRE_38.ready
connect _WIRE_39.ready, UInt<1>(0h1)
connect anonIn_1.d.bits.corrupt, in[1].d.bits.corrupt
connect anonIn_1.d.bits.data, in[1].d.bits.data
connect anonIn_1.d.bits.denied, in[1].d.bits.denied
connect anonIn_1.d.bits.sink, in[1].d.bits.sink
connect anonIn_1.d.bits.source, in[1].d.bits.source
connect anonIn_1.d.bits.size, in[1].d.bits.size
connect anonIn_1.d.bits.param, in[1].d.bits.param
connect anonIn_1.d.bits.opcode, in[1].d.bits.opcode
connect anonIn_1.d.valid, in[1].d.valid
connect in[1].d.ready, anonIn_1.d.ready
node _anonIn_d_bits_source_T_1 = bits(in[1].d.bits.source, 3, 0)
connect anonIn_1.d.bits.source, _anonIn_d_bits_source_T_1
wire _WIRE_40 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_40.bits.sink, UInt<4>(0h0)
connect _WIRE_40.valid, UInt<1>(0h0)
connect _WIRE_40.ready, UInt<1>(0h0)
wire _WIRE_41 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_41.bits, _WIRE_40.bits
connect _WIRE_41.valid, _WIRE_40.valid
connect _WIRE_41.ready, _WIRE_40.ready
invalidate _WIRE_41.bits.sink
invalidate _WIRE_41.valid
invalidate _WIRE_41.ready
wire _WIRE_42 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_42.bits.sink, UInt<4>(0h0)
connect _WIRE_42.valid, UInt<1>(0h0)
connect _WIRE_42.ready, UInt<1>(0h0)
wire _WIRE_43 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_43.bits, _WIRE_42.bits
connect _WIRE_43.valid, _WIRE_42.valid
connect _WIRE_43.ready, _WIRE_42.ready
invalidate _WIRE_43.bits.sink
invalidate _WIRE_43.valid
invalidate _WIRE_43.ready
wire _WIRE_44 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_44.bits.sink, UInt<4>(0h0)
connect _WIRE_44.valid, UInt<1>(0h0)
connect _WIRE_44.ready, UInt<1>(0h0)
wire _WIRE_45 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_45.bits, _WIRE_44.bits
connect _WIRE_45.valid, _WIRE_44.valid
connect _WIRE_45.ready, _WIRE_44.ready
connect _WIRE_45.valid, UInt<1>(0h0)
wire _WIRE_46 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_46.bits.sink, UInt<4>(0h0)
connect _WIRE_46.valid, UInt<1>(0h0)
connect _WIRE_46.ready, UInt<1>(0h0)
wire _WIRE_47 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_47.bits, _WIRE_46.bits
connect _WIRE_47.valid, _WIRE_46.valid
connect _WIRE_47.ready, _WIRE_46.ready
connect _WIRE_47.ready, UInt<1>(0h1)
wire out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}[1]
connect anonOut.a.bits.corrupt, out[0].a.bits.corrupt
connect anonOut.a.bits.data, out[0].a.bits.data
connect anonOut.a.bits.mask, out[0].a.bits.mask
connect anonOut.a.bits.address, out[0].a.bits.address
connect anonOut.a.bits.source, out[0].a.bits.source
connect anonOut.a.bits.size, out[0].a.bits.size
connect anonOut.a.bits.param, out[0].a.bits.param
connect anonOut.a.bits.opcode, out[0].a.bits.opcode
connect anonOut.a.valid, out[0].a.valid
connect out[0].a.ready, anonOut.a.ready
wire _WIRE_48 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_48.bits.corrupt, UInt<1>(0h0)
connect _WIRE_48.bits.data, UInt<128>(0h0)
connect _WIRE_48.bits.mask, UInt<16>(0h0)
connect _WIRE_48.bits.address, UInt<32>(0h0)
connect _WIRE_48.bits.source, UInt<5>(0h0)
connect _WIRE_48.bits.size, UInt<4>(0h0)
connect _WIRE_48.bits.param, UInt<2>(0h0)
connect _WIRE_48.bits.opcode, UInt<3>(0h0)
connect _WIRE_48.valid, UInt<1>(0h0)
connect _WIRE_48.ready, UInt<1>(0h0)
wire _WIRE_49 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_49.bits, _WIRE_48.bits
connect _WIRE_49.valid, _WIRE_48.valid
connect _WIRE_49.ready, _WIRE_48.ready
invalidate _WIRE_49.bits.corrupt
invalidate _WIRE_49.bits.data
invalidate _WIRE_49.bits.mask
invalidate _WIRE_49.bits.address
invalidate _WIRE_49.bits.source
invalidate _WIRE_49.bits.size
invalidate _WIRE_49.bits.param
invalidate _WIRE_49.bits.opcode
invalidate _WIRE_49.valid
invalidate _WIRE_49.ready
wire _WIRE_50 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_50.bits.corrupt, UInt<1>(0h0)
connect _WIRE_50.bits.data, UInt<128>(0h0)
connect _WIRE_50.bits.mask, UInt<16>(0h0)
connect _WIRE_50.bits.address, UInt<32>(0h0)
connect _WIRE_50.bits.source, UInt<5>(0h0)
connect _WIRE_50.bits.size, UInt<4>(0h0)
connect _WIRE_50.bits.param, UInt<2>(0h0)
connect _WIRE_50.bits.opcode, UInt<3>(0h0)
connect _WIRE_50.valid, UInt<1>(0h0)
connect _WIRE_50.ready, UInt<1>(0h0)
wire _WIRE_51 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_51.bits, _WIRE_50.bits
connect _WIRE_51.valid, _WIRE_50.valid
connect _WIRE_51.ready, _WIRE_50.ready
invalidate _WIRE_51.bits.corrupt
invalidate _WIRE_51.bits.data
invalidate _WIRE_51.bits.mask
invalidate _WIRE_51.bits.address
invalidate _WIRE_51.bits.source
invalidate _WIRE_51.bits.size
invalidate _WIRE_51.bits.param
invalidate _WIRE_51.bits.opcode
invalidate _WIRE_51.valid
invalidate _WIRE_51.ready
wire _WIRE_52 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_52.bits.corrupt, UInt<1>(0h0)
connect _WIRE_52.bits.data, UInt<128>(0h0)
connect _WIRE_52.bits.mask, UInt<16>(0h0)
connect _WIRE_52.bits.address, UInt<32>(0h0)
connect _WIRE_52.bits.source, UInt<5>(0h0)
connect _WIRE_52.bits.size, UInt<4>(0h0)
connect _WIRE_52.bits.param, UInt<2>(0h0)
connect _WIRE_52.bits.opcode, UInt<3>(0h0)
connect _WIRE_52.valid, UInt<1>(0h0)
connect _WIRE_52.ready, UInt<1>(0h0)
wire _WIRE_53 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_53.bits, _WIRE_52.bits
connect _WIRE_53.valid, _WIRE_52.valid
connect _WIRE_53.ready, _WIRE_52.ready
connect _WIRE_53.valid, UInt<1>(0h0)
wire _WIRE_54 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_54.bits.corrupt, UInt<1>(0h0)
connect _WIRE_54.bits.data, UInt<128>(0h0)
connect _WIRE_54.bits.mask, UInt<16>(0h0)
connect _WIRE_54.bits.address, UInt<32>(0h0)
connect _WIRE_54.bits.source, UInt<5>(0h0)
connect _WIRE_54.bits.size, UInt<4>(0h0)
connect _WIRE_54.bits.param, UInt<2>(0h0)
connect _WIRE_54.bits.opcode, UInt<3>(0h0)
connect _WIRE_54.valid, UInt<1>(0h0)
connect _WIRE_54.ready, UInt<1>(0h0)
wire _WIRE_55 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_55.bits, _WIRE_54.bits
connect _WIRE_55.valid, _WIRE_54.valid
connect _WIRE_55.ready, _WIRE_54.ready
connect _WIRE_55.ready, UInt<1>(0h1)
wire _WIRE_56 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_56.bits.corrupt, UInt<1>(0h0)
connect _WIRE_56.bits.data, UInt<128>(0h0)
connect _WIRE_56.bits.address, UInt<32>(0h0)
connect _WIRE_56.bits.source, UInt<5>(0h0)
connect _WIRE_56.bits.size, UInt<4>(0h0)
connect _WIRE_56.bits.param, UInt<3>(0h0)
connect _WIRE_56.bits.opcode, UInt<3>(0h0)
connect _WIRE_56.valid, UInt<1>(0h0)
connect _WIRE_56.ready, UInt<1>(0h0)
wire _WIRE_57 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_57.bits, _WIRE_56.bits
connect _WIRE_57.valid, _WIRE_56.valid
connect _WIRE_57.ready, _WIRE_56.ready
invalidate _WIRE_57.bits.corrupt
invalidate _WIRE_57.bits.data
invalidate _WIRE_57.bits.address
invalidate _WIRE_57.bits.source
invalidate _WIRE_57.bits.size
invalidate _WIRE_57.bits.param
invalidate _WIRE_57.bits.opcode
invalidate _WIRE_57.valid
invalidate _WIRE_57.ready
wire _WIRE_58 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_58.bits.corrupt, UInt<1>(0h0)
connect _WIRE_58.bits.data, UInt<128>(0h0)
connect _WIRE_58.bits.address, UInt<32>(0h0)
connect _WIRE_58.bits.source, UInt<5>(0h0)
connect _WIRE_58.bits.size, UInt<4>(0h0)
connect _WIRE_58.bits.param, UInt<3>(0h0)
connect _WIRE_58.bits.opcode, UInt<3>(0h0)
connect _WIRE_58.valid, UInt<1>(0h0)
connect _WIRE_58.ready, UInt<1>(0h0)
wire _WIRE_59 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_59.bits, _WIRE_58.bits
connect _WIRE_59.valid, _WIRE_58.valid
connect _WIRE_59.ready, _WIRE_58.ready
invalidate _WIRE_59.bits.corrupt
invalidate _WIRE_59.bits.data
invalidate _WIRE_59.bits.address
invalidate _WIRE_59.bits.source
invalidate _WIRE_59.bits.size
invalidate _WIRE_59.bits.param
invalidate _WIRE_59.bits.opcode
invalidate _WIRE_59.valid
invalidate _WIRE_59.ready
wire _WIRE_60 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_60.bits.corrupt, UInt<1>(0h0)
connect _WIRE_60.bits.data, UInt<128>(0h0)
connect _WIRE_60.bits.address, UInt<32>(0h0)
connect _WIRE_60.bits.source, UInt<5>(0h0)
connect _WIRE_60.bits.size, UInt<4>(0h0)
connect _WIRE_60.bits.param, UInt<3>(0h0)
connect _WIRE_60.bits.opcode, UInt<3>(0h0)
connect _WIRE_60.valid, UInt<1>(0h0)
connect _WIRE_60.ready, UInt<1>(0h0)
wire _WIRE_61 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_61.bits, _WIRE_60.bits
connect _WIRE_61.valid, _WIRE_60.valid
connect _WIRE_61.ready, _WIRE_60.ready
connect _WIRE_61.ready, UInt<1>(0h1)
wire _WIRE_62 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_62.bits.corrupt, UInt<1>(0h0)
connect _WIRE_62.bits.data, UInt<128>(0h0)
connect _WIRE_62.bits.address, UInt<32>(0h0)
connect _WIRE_62.bits.source, UInt<5>(0h0)
connect _WIRE_62.bits.size, UInt<4>(0h0)
connect _WIRE_62.bits.param, UInt<3>(0h0)
connect _WIRE_62.bits.opcode, UInt<3>(0h0)
connect _WIRE_62.valid, UInt<1>(0h0)
connect _WIRE_62.ready, UInt<1>(0h0)
wire _WIRE_63 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_63.bits, _WIRE_62.bits
connect _WIRE_63.valid, _WIRE_62.valid
connect _WIRE_63.ready, _WIRE_62.ready
connect _WIRE_63.valid, UInt<1>(0h0)
connect out[0].d.bits.corrupt, anonOut.d.bits.corrupt
connect out[0].d.bits.data, anonOut.d.bits.data
connect out[0].d.bits.denied, anonOut.d.bits.denied
connect out[0].d.bits.sink, anonOut.d.bits.sink
connect out[0].d.bits.source, anonOut.d.bits.source
connect out[0].d.bits.size, anonOut.d.bits.size
connect out[0].d.bits.param, anonOut.d.bits.param
connect out[0].d.bits.opcode, anonOut.d.bits.opcode
connect out[0].d.valid, anonOut.d.valid
connect anonOut.d.ready, out[0].d.ready
node _out_0_d_bits_sink_T = or(anonOut.d.bits.sink, UInt<1>(0h0))
connect out[0].d.bits.sink, _out_0_d_bits_sink_T
wire _WIRE_64 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_64.bits.sink, UInt<4>(0h0)
connect _WIRE_64.valid, UInt<1>(0h0)
connect _WIRE_64.ready, UInt<1>(0h0)
wire _WIRE_65 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_65.bits, _WIRE_64.bits
connect _WIRE_65.valid, _WIRE_64.valid
connect _WIRE_65.ready, _WIRE_64.ready
invalidate _WIRE_65.bits.sink
invalidate _WIRE_65.valid
invalidate _WIRE_65.ready
wire _WIRE_66 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_66.bits.sink, UInt<4>(0h0)
connect _WIRE_66.valid, UInt<1>(0h0)
connect _WIRE_66.ready, UInt<1>(0h0)
wire _WIRE_67 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_67.bits, _WIRE_66.bits
connect _WIRE_67.valid, _WIRE_66.valid
connect _WIRE_67.ready, _WIRE_66.ready
invalidate _WIRE_67.bits.sink
invalidate _WIRE_67.valid
invalidate _WIRE_67.ready
wire _WIRE_68 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_68.bits.sink, UInt<4>(0h0)
connect _WIRE_68.valid, UInt<1>(0h0)
connect _WIRE_68.ready, UInt<1>(0h0)
wire _WIRE_69 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_69.bits, _WIRE_68.bits
connect _WIRE_69.valid, _WIRE_68.valid
connect _WIRE_69.ready, _WIRE_68.ready
connect _WIRE_69.ready, UInt<1>(0h1)
wire _WIRE_70 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_70.bits.sink, UInt<4>(0h0)
connect _WIRE_70.valid, UInt<1>(0h0)
connect _WIRE_70.ready, UInt<1>(0h0)
wire _WIRE_71 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_71.bits, _WIRE_70.bits
connect _WIRE_71.valid, _WIRE_70.valid
connect _WIRE_71.ready, _WIRE_70.ready
connect _WIRE_71.valid, UInt<1>(0h0)
wire _addressC_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _addressC_WIRE.bits.corrupt, UInt<1>(0h0)
connect _addressC_WIRE.bits.data, UInt<128>(0h0)
connect _addressC_WIRE.bits.address, UInt<32>(0h0)
connect _addressC_WIRE.bits.source, UInt<5>(0h0)
connect _addressC_WIRE.bits.size, UInt<4>(0h0)
connect _addressC_WIRE.bits.param, UInt<3>(0h0)
connect _addressC_WIRE.bits.opcode, UInt<3>(0h0)
connect _addressC_WIRE.valid, UInt<1>(0h0)
connect _addressC_WIRE.ready, UInt<1>(0h0)
wire _addressC_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _addressC_WIRE_1.bits, _addressC_WIRE.bits
connect _addressC_WIRE_1.valid, _addressC_WIRE.valid
connect _addressC_WIRE_1.ready, _addressC_WIRE.ready
wire _addressC_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _addressC_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _addressC_WIRE_2.bits.data, UInt<128>(0h0)
connect _addressC_WIRE_2.bits.address, UInt<32>(0h0)
connect _addressC_WIRE_2.bits.source, UInt<5>(0h0)
connect _addressC_WIRE_2.bits.size, UInt<4>(0h0)
connect _addressC_WIRE_2.bits.param, UInt<3>(0h0)
connect _addressC_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _addressC_WIRE_2.valid, UInt<1>(0h0)
connect _addressC_WIRE_2.ready, UInt<1>(0h0)
wire _addressC_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _addressC_WIRE_3.bits, _addressC_WIRE_2.bits
connect _addressC_WIRE_3.valid, _addressC_WIRE_2.valid
connect _addressC_WIRE_3.ready, _addressC_WIRE_2.ready
node _requestAIO_T = xor(in[0].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_1 = cvt(_requestAIO_T)
node _requestAIO_T_2 = and(_requestAIO_T_1, asSInt(UInt<1>(0h0)))
node _requestAIO_T_3 = asSInt(_requestAIO_T_2)
node _requestAIO_T_4 = eq(_requestAIO_T_3, asSInt(UInt<1>(0h0)))
node requestAIO_0_0 = or(UInt<1>(0h1), _requestAIO_T_4)
node _requestAIO_T_5 = xor(in[1].a.bits.address, UInt<1>(0h0))
node _requestAIO_T_6 = cvt(_requestAIO_T_5)
node _requestAIO_T_7 = and(_requestAIO_T_6, asSInt(UInt<1>(0h0)))
node _requestAIO_T_8 = asSInt(_requestAIO_T_7)
node _requestAIO_T_9 = eq(_requestAIO_T_8, asSInt(UInt<1>(0h0)))
node requestAIO_1_0 = or(UInt<1>(0h1), _requestAIO_T_9)
node _requestCIO_T = xor(_addressC_WIRE_1.bits.address, UInt<1>(0h0))
node _requestCIO_T_1 = cvt(_requestCIO_T)
node _requestCIO_T_2 = and(_requestCIO_T_1, asSInt(UInt<1>(0h0)))
node _requestCIO_T_3 = asSInt(_requestCIO_T_2)
node _requestCIO_T_4 = eq(_requestCIO_T_3, asSInt(UInt<1>(0h0)))
node requestCIO_0_0 = or(UInt<1>(0h1), _requestCIO_T_4)
node _requestCIO_T_5 = xor(_addressC_WIRE_3.bits.address, UInt<1>(0h0))
node _requestCIO_T_6 = cvt(_requestCIO_T_5)
node _requestCIO_T_7 = and(_requestCIO_T_6, asSInt(UInt<1>(0h0)))
node _requestCIO_T_8 = asSInt(_requestCIO_T_7)
node _requestCIO_T_9 = eq(_requestCIO_T_8, asSInt(UInt<1>(0h0)))
node requestCIO_1_0 = or(UInt<1>(0h1), _requestCIO_T_9)
wire _requestBOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _requestBOI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE.bits.data, UInt<128>(0h0)
connect _requestBOI_WIRE.bits.mask, UInt<16>(0h0)
connect _requestBOI_WIRE.bits.address, UInt<32>(0h0)
connect _requestBOI_WIRE.bits.source, UInt<5>(0h0)
connect _requestBOI_WIRE.bits.size, UInt<4>(0h0)
connect _requestBOI_WIRE.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE.valid, UInt<1>(0h0)
connect _requestBOI_WIRE.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_1.bits, _requestBOI_WIRE.bits
connect _requestBOI_WIRE_1.valid, _requestBOI_WIRE.valid
connect _requestBOI_WIRE_1.ready, _requestBOI_WIRE.ready
node _requestBOI_uncommonBits_T = or(_requestBOI_WIRE_1.bits.source, UInt<4>(0h0))
node requestBOI_uncommonBits = bits(_requestBOI_uncommonBits_T, 3, 0)
node _requestBOI_T = shr(_requestBOI_WIRE_1.bits.source, 4)
node _requestBOI_T_1 = eq(_requestBOI_T, UInt<1>(0h1))
node _requestBOI_T_2 = leq(UInt<1>(0h0), requestBOI_uncommonBits)
node _requestBOI_T_3 = and(_requestBOI_T_1, _requestBOI_T_2)
node _requestBOI_T_4 = leq(requestBOI_uncommonBits, UInt<4>(0hf))
node requestBOI_0_0 = and(_requestBOI_T_3, _requestBOI_T_4)
wire _requestBOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _requestBOI_WIRE_2.bits.data, UInt<128>(0h0)
connect _requestBOI_WIRE_2.bits.mask, UInt<16>(0h0)
connect _requestBOI_WIRE_2.bits.address, UInt<32>(0h0)
connect _requestBOI_WIRE_2.bits.source, UInt<5>(0h0)
connect _requestBOI_WIRE_2.bits.size, UInt<4>(0h0)
connect _requestBOI_WIRE_2.bits.param, UInt<2>(0h0)
connect _requestBOI_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _requestBOI_WIRE_2.valid, UInt<1>(0h0)
connect _requestBOI_WIRE_2.ready, UInt<1>(0h0)
wire _requestBOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _requestBOI_WIRE_3.bits, _requestBOI_WIRE_2.bits
connect _requestBOI_WIRE_3.valid, _requestBOI_WIRE_2.valid
connect _requestBOI_WIRE_3.ready, _requestBOI_WIRE_2.ready
node _requestBOI_uncommonBits_T_1 = or(_requestBOI_WIRE_3.bits.source, UInt<4>(0h0))
node requestBOI_uncommonBits_1 = bits(_requestBOI_uncommonBits_T_1, 3, 0)
node _requestBOI_T_5 = shr(_requestBOI_WIRE_3.bits.source, 4)
node _requestBOI_T_6 = eq(_requestBOI_T_5, UInt<1>(0h0))
node _requestBOI_T_7 = leq(UInt<1>(0h0), requestBOI_uncommonBits_1)
node _requestBOI_T_8 = and(_requestBOI_T_6, _requestBOI_T_7)
node _requestBOI_T_9 = leq(requestBOI_uncommonBits_1, UInt<4>(0hf))
node requestBOI_0_1 = and(_requestBOI_T_8, _requestBOI_T_9)
node _requestDOI_uncommonBits_T = or(out[0].d.bits.source, UInt<4>(0h0))
node requestDOI_uncommonBits = bits(_requestDOI_uncommonBits_T, 3, 0)
node _requestDOI_T = shr(out[0].d.bits.source, 4)
node _requestDOI_T_1 = eq(_requestDOI_T, UInt<1>(0h1))
node _requestDOI_T_2 = leq(UInt<1>(0h0), requestDOI_uncommonBits)
node _requestDOI_T_3 = and(_requestDOI_T_1, _requestDOI_T_2)
node _requestDOI_T_4 = leq(requestDOI_uncommonBits, UInt<4>(0hf))
node requestDOI_0_0 = and(_requestDOI_T_3, _requestDOI_T_4)
node _requestDOI_uncommonBits_T_1 = or(out[0].d.bits.source, UInt<4>(0h0))
node requestDOI_uncommonBits_1 = bits(_requestDOI_uncommonBits_T_1, 3, 0)
node _requestDOI_T_5 = shr(out[0].d.bits.source, 4)
node _requestDOI_T_6 = eq(_requestDOI_T_5, UInt<1>(0h0))
node _requestDOI_T_7 = leq(UInt<1>(0h0), requestDOI_uncommonBits_1)
node _requestDOI_T_8 = and(_requestDOI_T_6, _requestDOI_T_7)
node _requestDOI_T_9 = leq(requestDOI_uncommonBits_1, UInt<4>(0hf))
node requestDOI_0_1 = and(_requestDOI_T_8, _requestDOI_T_9)
wire _requestEIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _requestEIO_WIRE.bits.sink, UInt<4>(0h0)
connect _requestEIO_WIRE.valid, UInt<1>(0h0)
connect _requestEIO_WIRE.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _requestEIO_WIRE_1.bits, _requestEIO_WIRE.bits
connect _requestEIO_WIRE_1.valid, _requestEIO_WIRE.valid
connect _requestEIO_WIRE_1.ready, _requestEIO_WIRE.ready
node _requestEIO_uncommonBits_T = or(_requestEIO_WIRE_1.bits.sink, UInt<4>(0h0))
node requestEIO_uncommonBits = bits(_requestEIO_uncommonBits_T, 3, 0)
node _requestEIO_T = shr(_requestEIO_WIRE_1.bits.sink, 4)
node _requestEIO_T_1 = eq(_requestEIO_T, UInt<1>(0h0))
node _requestEIO_T_2 = leq(UInt<1>(0h0), requestEIO_uncommonBits)
node _requestEIO_T_3 = and(_requestEIO_T_1, _requestEIO_T_2)
node _requestEIO_T_4 = leq(requestEIO_uncommonBits, UInt<4>(0hf))
node requestEIO_0_0 = and(_requestEIO_T_3, _requestEIO_T_4)
wire _requestEIO_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _requestEIO_WIRE_2.bits.sink, UInt<4>(0h0)
connect _requestEIO_WIRE_2.valid, UInt<1>(0h0)
connect _requestEIO_WIRE_2.ready, UInt<1>(0h0)
wire _requestEIO_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _requestEIO_WIRE_3.bits, _requestEIO_WIRE_2.bits
connect _requestEIO_WIRE_3.valid, _requestEIO_WIRE_2.valid
connect _requestEIO_WIRE_3.ready, _requestEIO_WIRE_2.ready
node _requestEIO_uncommonBits_T_1 = or(_requestEIO_WIRE_3.bits.sink, UInt<4>(0h0))
node requestEIO_uncommonBits_1 = bits(_requestEIO_uncommonBits_T_1, 3, 0)
node _requestEIO_T_5 = shr(_requestEIO_WIRE_3.bits.sink, 4)
node _requestEIO_T_6 = eq(_requestEIO_T_5, UInt<1>(0h0))
node _requestEIO_T_7 = leq(UInt<1>(0h0), requestEIO_uncommonBits_1)
node _requestEIO_T_8 = and(_requestEIO_T_6, _requestEIO_T_7)
node _requestEIO_T_9 = leq(requestEIO_uncommonBits_1, UInt<4>(0hf))
node requestEIO_1_0 = and(_requestEIO_T_8, _requestEIO_T_9)
node _beatsAI_decode_T = dshl(UInt<12>(0hfff), in[0].a.bits.size)
node _beatsAI_decode_T_1 = bits(_beatsAI_decode_T, 11, 0)
node _beatsAI_decode_T_2 = not(_beatsAI_decode_T_1)
node beatsAI_decode = shr(_beatsAI_decode_T_2, 4)
node _beatsAI_opdata_T = bits(in[0].a.bits.opcode, 2, 2)
node beatsAI_opdata = eq(_beatsAI_opdata_T, UInt<1>(0h0))
node beatsAI_0 = mux(beatsAI_opdata, beatsAI_decode, UInt<1>(0h0))
node _beatsAI_decode_T_3 = dshl(UInt<12>(0hfff), in[1].a.bits.size)
node _beatsAI_decode_T_4 = bits(_beatsAI_decode_T_3, 11, 0)
node _beatsAI_decode_T_5 = not(_beatsAI_decode_T_4)
node beatsAI_decode_1 = shr(_beatsAI_decode_T_5, 4)
node _beatsAI_opdata_T_1 = bits(in[1].a.bits.opcode, 2, 2)
node beatsAI_opdata_1 = eq(_beatsAI_opdata_T_1, UInt<1>(0h0))
node beatsAI_1 = mux(beatsAI_opdata_1, beatsAI_decode_1, UInt<1>(0h0))
wire _beatsBO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _beatsBO_WIRE.bits.corrupt, UInt<1>(0h0)
connect _beatsBO_WIRE.bits.data, UInt<128>(0h0)
connect _beatsBO_WIRE.bits.mask, UInt<16>(0h0)
connect _beatsBO_WIRE.bits.address, UInt<32>(0h0)
connect _beatsBO_WIRE.bits.source, UInt<5>(0h0)
connect _beatsBO_WIRE.bits.size, UInt<4>(0h0)
connect _beatsBO_WIRE.bits.param, UInt<2>(0h0)
connect _beatsBO_WIRE.bits.opcode, UInt<3>(0h0)
connect _beatsBO_WIRE.valid, UInt<1>(0h0)
connect _beatsBO_WIRE.ready, UInt<1>(0h0)
wire _beatsBO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _beatsBO_WIRE_1.bits, _beatsBO_WIRE.bits
connect _beatsBO_WIRE_1.valid, _beatsBO_WIRE.valid
connect _beatsBO_WIRE_1.ready, _beatsBO_WIRE.ready
node _beatsBO_decode_T = dshl(UInt<12>(0hfff), _beatsBO_WIRE_1.bits.size)
node _beatsBO_decode_T_1 = bits(_beatsBO_decode_T, 11, 0)
node _beatsBO_decode_T_2 = not(_beatsBO_decode_T_1)
node beatsBO_decode = shr(_beatsBO_decode_T_2, 4)
node _beatsBO_opdata_T = bits(_beatsBO_WIRE_1.bits.opcode, 2, 2)
node beatsBO_opdata = eq(_beatsBO_opdata_T, UInt<1>(0h0))
node beatsBO_0 = mux(UInt<1>(0h0), beatsBO_decode, UInt<1>(0h0))
wire _beatsCI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _beatsCI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _beatsCI_WIRE.bits.data, UInt<128>(0h0)
connect _beatsCI_WIRE.bits.address, UInt<32>(0h0)
connect _beatsCI_WIRE.bits.source, UInt<5>(0h0)
connect _beatsCI_WIRE.bits.size, UInt<4>(0h0)
connect _beatsCI_WIRE.bits.param, UInt<3>(0h0)
connect _beatsCI_WIRE.bits.opcode, UInt<3>(0h0)
connect _beatsCI_WIRE.valid, UInt<1>(0h0)
connect _beatsCI_WIRE.ready, UInt<1>(0h0)
wire _beatsCI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_1.bits, _beatsCI_WIRE.bits
connect _beatsCI_WIRE_1.valid, _beatsCI_WIRE.valid
connect _beatsCI_WIRE_1.ready, _beatsCI_WIRE.ready
node _beatsCI_decode_T = dshl(UInt<12>(0hfff), _beatsCI_WIRE_1.bits.size)
node _beatsCI_decode_T_1 = bits(_beatsCI_decode_T, 11, 0)
node _beatsCI_decode_T_2 = not(_beatsCI_decode_T_1)
node beatsCI_decode = shr(_beatsCI_decode_T_2, 4)
node beatsCI_opdata = bits(_beatsCI_WIRE_1.bits.opcode, 0, 0)
node beatsCI_0 = mux(UInt<1>(0h0), beatsCI_decode, UInt<1>(0h0))
wire _beatsCI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _beatsCI_WIRE_2.bits.data, UInt<128>(0h0)
connect _beatsCI_WIRE_2.bits.address, UInt<32>(0h0)
connect _beatsCI_WIRE_2.bits.source, UInt<5>(0h0)
connect _beatsCI_WIRE_2.bits.size, UInt<4>(0h0)
connect _beatsCI_WIRE_2.bits.param, UInt<3>(0h0)
connect _beatsCI_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _beatsCI_WIRE_2.valid, UInt<1>(0h0)
connect _beatsCI_WIRE_2.ready, UInt<1>(0h0)
wire _beatsCI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _beatsCI_WIRE_3.bits, _beatsCI_WIRE_2.bits
connect _beatsCI_WIRE_3.valid, _beatsCI_WIRE_2.valid
connect _beatsCI_WIRE_3.ready, _beatsCI_WIRE_2.ready
node _beatsCI_decode_T_3 = dshl(UInt<12>(0hfff), _beatsCI_WIRE_3.bits.size)
node _beatsCI_decode_T_4 = bits(_beatsCI_decode_T_3, 11, 0)
node _beatsCI_decode_T_5 = not(_beatsCI_decode_T_4)
node beatsCI_decode_1 = shr(_beatsCI_decode_T_5, 4)
node beatsCI_opdata_1 = bits(_beatsCI_WIRE_3.bits.opcode, 0, 0)
node beatsCI_1 = mux(UInt<1>(0h0), beatsCI_decode_1, UInt<1>(0h0))
node _beatsDO_decode_T = dshl(UInt<12>(0hfff), out[0].d.bits.size)
node _beatsDO_decode_T_1 = bits(_beatsDO_decode_T, 11, 0)
node _beatsDO_decode_T_2 = not(_beatsDO_decode_T_1)
node beatsDO_decode = shr(_beatsDO_decode_T_2, 4)
node beatsDO_opdata = bits(out[0].d.bits.opcode, 0, 0)
node beatsDO_0 = mux(beatsDO_opdata, beatsDO_decode, UInt<1>(0h0))
wire _beatsEI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _beatsEI_WIRE.bits.sink, UInt<4>(0h0)
connect _beatsEI_WIRE.valid, UInt<1>(0h0)
connect _beatsEI_WIRE.ready, UInt<1>(0h0)
wire _beatsEI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _beatsEI_WIRE_1.bits, _beatsEI_WIRE.bits
connect _beatsEI_WIRE_1.valid, _beatsEI_WIRE.valid
connect _beatsEI_WIRE_1.ready, _beatsEI_WIRE.ready
wire _beatsEI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _beatsEI_WIRE_2.bits.sink, UInt<4>(0h0)
connect _beatsEI_WIRE_2.valid, UInt<1>(0h0)
connect _beatsEI_WIRE_2.ready, UInt<1>(0h0)
wire _beatsEI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _beatsEI_WIRE_3.bits, _beatsEI_WIRE_2.bits
connect _beatsEI_WIRE_3.valid, _beatsEI_WIRE_2.valid
connect _beatsEI_WIRE_3.ready, _beatsEI_WIRE_2.ready
wire portsAOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}[1]
connect portsAOI_filtered[0].bits, in[0].a.bits
node _portsAOI_filtered_0_valid_T = or(requestAIO_0_0, UInt<1>(0h1))
node _portsAOI_filtered_0_valid_T_1 = and(in[0].a.valid, _portsAOI_filtered_0_valid_T)
connect portsAOI_filtered[0].valid, _portsAOI_filtered_0_valid_T_1
connect in[0].a.ready, portsAOI_filtered[0].ready
wire portsAOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}[1]
connect portsAOI_filtered_1[0].bits, in[1].a.bits
node _portsAOI_filtered_0_valid_T_2 = or(requestAIO_1_0, UInt<1>(0h1))
node _portsAOI_filtered_0_valid_T_3 = and(in[1].a.valid, _portsAOI_filtered_0_valid_T_2)
connect portsAOI_filtered_1[0].valid, _portsAOI_filtered_0_valid_T_3
connect in[1].a.ready, portsAOI_filtered_1[0].ready
wire _portsBIO_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _portsBIO_WIRE.bits.corrupt, UInt<1>(0h0)
connect _portsBIO_WIRE.bits.data, UInt<128>(0h0)
connect _portsBIO_WIRE.bits.mask, UInt<16>(0h0)
connect _portsBIO_WIRE.bits.address, UInt<32>(0h0)
connect _portsBIO_WIRE.bits.source, UInt<5>(0h0)
connect _portsBIO_WIRE.bits.size, UInt<4>(0h0)
connect _portsBIO_WIRE.bits.param, UInt<2>(0h0)
connect _portsBIO_WIRE.bits.opcode, UInt<3>(0h0)
connect _portsBIO_WIRE.valid, UInt<1>(0h0)
connect _portsBIO_WIRE.ready, UInt<1>(0h0)
wire _portsBIO_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _portsBIO_WIRE_1.bits, _portsBIO_WIRE.bits
connect _portsBIO_WIRE_1.valid, _portsBIO_WIRE.valid
connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE.ready
wire portsBIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}[2]
connect portsBIO_filtered[0].bits, _portsBIO_WIRE_1.bits
node _portsBIO_filtered_0_valid_T = or(requestBOI_0_0, UInt<1>(0h0))
node _portsBIO_filtered_0_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_0_valid_T)
connect portsBIO_filtered[0].valid, _portsBIO_filtered_0_valid_T_1
connect portsBIO_filtered[1].bits, _portsBIO_WIRE_1.bits
node _portsBIO_filtered_1_valid_T = or(requestBOI_0_1, UInt<1>(0h0))
node _portsBIO_filtered_1_valid_T_1 = and(_portsBIO_WIRE_1.valid, _portsBIO_filtered_1_valid_T)
connect portsBIO_filtered[1].valid, _portsBIO_filtered_1_valid_T_1
node _portsBIO_T = mux(requestBOI_0_0, portsBIO_filtered[0].ready, UInt<1>(0h0))
node _portsBIO_T_1 = mux(requestBOI_0_1, portsBIO_filtered[1].ready, UInt<1>(0h0))
node _portsBIO_T_2 = or(_portsBIO_T, _portsBIO_T_1)
wire _portsBIO_WIRE_2 : UInt<1>
connect _portsBIO_WIRE_2, _portsBIO_T_2
connect _portsBIO_WIRE_1.ready, _portsBIO_WIRE_2
wire _portsCOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _portsCOI_WIRE.bits.corrupt, UInt<1>(0h0)
connect _portsCOI_WIRE.bits.data, UInt<128>(0h0)
connect _portsCOI_WIRE.bits.address, UInt<32>(0h0)
connect _portsCOI_WIRE.bits.source, UInt<5>(0h0)
connect _portsCOI_WIRE.bits.size, UInt<4>(0h0)
connect _portsCOI_WIRE.bits.param, UInt<3>(0h0)
connect _portsCOI_WIRE.bits.opcode, UInt<3>(0h0)
connect _portsCOI_WIRE.valid, UInt<1>(0h0)
connect _portsCOI_WIRE.ready, UInt<1>(0h0)
wire _portsCOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_1.bits, _portsCOI_WIRE.bits
connect _portsCOI_WIRE_1.valid, _portsCOI_WIRE.valid
connect _portsCOI_WIRE_1.ready, _portsCOI_WIRE.ready
wire portsCOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}[1]
connect portsCOI_filtered[0].bits, _portsCOI_WIRE_1.bits
node _portsCOI_filtered_0_valid_T = or(requestCIO_0_0, UInt<1>(0h1))
node _portsCOI_filtered_0_valid_T_1 = and(_portsCOI_WIRE_1.valid, _portsCOI_filtered_0_valid_T)
connect portsCOI_filtered[0].valid, _portsCOI_filtered_0_valid_T_1
connect _portsCOI_WIRE_1.ready, portsCOI_filtered[0].ready
wire _portsCOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_2.bits.corrupt, UInt<1>(0h0)
connect _portsCOI_WIRE_2.bits.data, UInt<128>(0h0)
connect _portsCOI_WIRE_2.bits.address, UInt<32>(0h0)
connect _portsCOI_WIRE_2.bits.source, UInt<5>(0h0)
connect _portsCOI_WIRE_2.bits.size, UInt<4>(0h0)
connect _portsCOI_WIRE_2.bits.param, UInt<3>(0h0)
connect _portsCOI_WIRE_2.bits.opcode, UInt<3>(0h0)
connect _portsCOI_WIRE_2.valid, UInt<1>(0h0)
connect _portsCOI_WIRE_2.ready, UInt<1>(0h0)
wire _portsCOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _portsCOI_WIRE_3.bits, _portsCOI_WIRE_2.bits
connect _portsCOI_WIRE_3.valid, _portsCOI_WIRE_2.valid
connect _portsCOI_WIRE_3.ready, _portsCOI_WIRE_2.ready
wire portsCOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}[1]
connect portsCOI_filtered_1[0].bits, _portsCOI_WIRE_3.bits
node _portsCOI_filtered_0_valid_T_2 = or(requestCIO_1_0, UInt<1>(0h1))
node _portsCOI_filtered_0_valid_T_3 = and(_portsCOI_WIRE_3.valid, _portsCOI_filtered_0_valid_T_2)
connect portsCOI_filtered_1[0].valid, _portsCOI_filtered_0_valid_T_3
connect _portsCOI_WIRE_3.ready, portsCOI_filtered_1[0].ready
wire portsDIO_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}[2]
connect portsDIO_filtered[0].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[0].bits.data, out[0].d.bits.data
connect portsDIO_filtered[0].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[0].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[0].bits.source, out[0].d.bits.source
connect portsDIO_filtered[0].bits.size, out[0].d.bits.size
connect portsDIO_filtered[0].bits.param, out[0].d.bits.param
connect portsDIO_filtered[0].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_0_valid_T = or(requestDOI_0_0, UInt<1>(0h0))
node _portsDIO_filtered_0_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_0_valid_T)
connect portsDIO_filtered[0].valid, _portsDIO_filtered_0_valid_T_1
connect portsDIO_filtered[1].bits.corrupt, out[0].d.bits.corrupt
connect portsDIO_filtered[1].bits.data, out[0].d.bits.data
connect portsDIO_filtered[1].bits.denied, out[0].d.bits.denied
connect portsDIO_filtered[1].bits.sink, out[0].d.bits.sink
connect portsDIO_filtered[1].bits.source, out[0].d.bits.source
connect portsDIO_filtered[1].bits.size, out[0].d.bits.size
connect portsDIO_filtered[1].bits.param, out[0].d.bits.param
connect portsDIO_filtered[1].bits.opcode, out[0].d.bits.opcode
node _portsDIO_filtered_1_valid_T = or(requestDOI_0_1, UInt<1>(0h0))
node _portsDIO_filtered_1_valid_T_1 = and(out[0].d.valid, _portsDIO_filtered_1_valid_T)
connect portsDIO_filtered[1].valid, _portsDIO_filtered_1_valid_T_1
node _portsDIO_out_0_d_ready_T = mux(requestDOI_0_0, portsDIO_filtered[0].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_1 = mux(requestDOI_0_1, portsDIO_filtered[1].ready, UInt<1>(0h0))
node _portsDIO_out_0_d_ready_T_2 = or(_portsDIO_out_0_d_ready_T, _portsDIO_out_0_d_ready_T_1)
wire _portsDIO_out_0_d_ready_WIRE : UInt<1>
connect _portsDIO_out_0_d_ready_WIRE, _portsDIO_out_0_d_ready_T_2
connect out[0].d.ready, _portsDIO_out_0_d_ready_WIRE
wire _portsEOI_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _portsEOI_WIRE.bits.sink, UInt<4>(0h0)
connect _portsEOI_WIRE.valid, UInt<1>(0h0)
connect _portsEOI_WIRE.ready, UInt<1>(0h0)
wire _portsEOI_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _portsEOI_WIRE_1.bits, _portsEOI_WIRE.bits
connect _portsEOI_WIRE_1.valid, _portsEOI_WIRE.valid
connect _portsEOI_WIRE_1.ready, _portsEOI_WIRE.ready
wire portsEOI_filtered : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}[1]
connect portsEOI_filtered[0].bits, _portsEOI_WIRE_1.bits
node _portsEOI_filtered_0_valid_T = or(requestEIO_0_0, UInt<1>(0h1))
node _portsEOI_filtered_0_valid_T_1 = and(_portsEOI_WIRE_1.valid, _portsEOI_filtered_0_valid_T)
connect portsEOI_filtered[0].valid, _portsEOI_filtered_0_valid_T_1
connect _portsEOI_WIRE_1.ready, portsEOI_filtered[0].ready
wire _portsEOI_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _portsEOI_WIRE_2.bits.sink, UInt<4>(0h0)
connect _portsEOI_WIRE_2.valid, UInt<1>(0h0)
connect _portsEOI_WIRE_2.ready, UInt<1>(0h0)
wire _portsEOI_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _portsEOI_WIRE_3.bits, _portsEOI_WIRE_2.bits
connect _portsEOI_WIRE_3.valid, _portsEOI_WIRE_2.valid
connect _portsEOI_WIRE_3.ready, _portsEOI_WIRE_2.ready
wire portsEOI_filtered_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}[1]
connect portsEOI_filtered_1[0].bits, _portsEOI_WIRE_3.bits
node _portsEOI_filtered_0_valid_T_2 = or(requestEIO_1_0, UInt<1>(0h1))
node _portsEOI_filtered_0_valid_T_3 = and(_portsEOI_WIRE_3.valid, _portsEOI_filtered_0_valid_T_2)
connect portsEOI_filtered_1[0].valid, _portsEOI_filtered_0_valid_T_3
connect _portsEOI_WIRE_3.ready, portsEOI_filtered_1[0].ready
regreset beatsLeft : UInt, clock, reset, UInt<1>(0h0)
node idle = eq(beatsLeft, UInt<1>(0h0))
node latch = and(idle, out[0].a.ready)
node _readys_T = cat(portsAOI_filtered_1[0].valid, portsAOI_filtered[0].valid)
node readys_valid = bits(_readys_T, 1, 0)
node _readys_T_1 = eq(readys_valid, _readys_T)
node _readys_T_2 = asUInt(reset)
node _readys_T_3 = eq(_readys_T_2, UInt<1>(0h0))
when _readys_T_3 :
node _readys_T_4 = eq(_readys_T_1, UInt<1>(0h0))
when _readys_T_4 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:22 assert (valid === valids)\n") : readys_printf
assert(clock, _readys_T_1, UInt<1>(0h1), "") : readys_assert
regreset readys_mask : UInt<2>, clock, reset, UInt<2>(0h3)
node _readys_filter_T = not(readys_mask)
node _readys_filter_T_1 = and(readys_valid, _readys_filter_T)
node readys_filter = cat(_readys_filter_T_1, readys_valid)
node _readys_unready_T = shr(readys_filter, 1)
node _readys_unready_T_1 = or(readys_filter, _readys_unready_T)
node _readys_unready_T_2 = bits(_readys_unready_T_1, 3, 0)
node _readys_unready_T_3 = shr(_readys_unready_T_2, 1)
node _readys_unready_T_4 = shl(readys_mask, 2)
node readys_unready = or(_readys_unready_T_3, _readys_unready_T_4)
node _readys_readys_T = shr(readys_unready, 2)
node _readys_readys_T_1 = bits(readys_unready, 1, 0)
node _readys_readys_T_2 = and(_readys_readys_T, _readys_readys_T_1)
node readys_readys = not(_readys_readys_T_2)
node _readys_T_5 = orr(readys_valid)
node _readys_T_6 = and(latch, _readys_T_5)
when _readys_T_6 :
node _readys_mask_T = and(readys_readys, readys_valid)
node _readys_mask_T_1 = shl(_readys_mask_T, 1)
node _readys_mask_T_2 = bits(_readys_mask_T_1, 1, 0)
node _readys_mask_T_3 = or(_readys_mask_T, _readys_mask_T_2)
node _readys_mask_T_4 = bits(_readys_mask_T_3, 1, 0)
connect readys_mask, _readys_mask_T_4
node _readys_T_7 = bits(readys_readys, 1, 0)
node _readys_T_8 = bits(_readys_T_7, 0, 0)
node _readys_T_9 = bits(_readys_T_7, 1, 1)
wire readys : UInt<1>[2]
connect readys[0], _readys_T_8
connect readys[1], _readys_T_9
node _winner_T = and(readys[0], portsAOI_filtered[0].valid)
node _winner_T_1 = and(readys[1], portsAOI_filtered_1[0].valid)
wire winner : UInt<1>[2]
connect winner[0], _winner_T
connect winner[1], _winner_T_1
node prefixOR_1 = or(UInt<1>(0h0), winner[0])
node _prefixOR_T = or(prefixOR_1, winner[1])
node _T = eq(UInt<1>(0h0), UInt<1>(0h0))
node _T_1 = eq(winner[0], UInt<1>(0h0))
node _T_2 = or(_T, _T_1)
node _T_3 = eq(prefixOR_1, UInt<1>(0h0))
node _T_4 = eq(winner[1], UInt<1>(0h0))
node _T_5 = or(_T_3, _T_4)
node _T_6 = and(_T_2, _T_5)
node _T_7 = asUInt(reset)
node _T_8 = eq(_T_7, UInt<1>(0h0))
when _T_8 :
node _T_9 = eq(_T_6, UInt<1>(0h0))
when _T_9 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:77 assert((prefixOR zip winner) map { case (p,w) => !p || !w } reduce {_ && _})\n") : printf
assert(clock, _T_6, UInt<1>(0h1), "") : assert
node _T_10 = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid)
node _T_11 = eq(_T_10, UInt<1>(0h0))
node _T_12 = or(winner[0], winner[1])
node _T_13 = or(_T_11, _T_12)
node _T_14 = asUInt(reset)
node _T_15 = eq(_T_14, UInt<1>(0h0))
when _T_15 :
node _T_16 = eq(_T_13, UInt<1>(0h0))
when _T_16 :
printf(clock, UInt<1>(0h1), "Assertion failed\n at Arbiter.scala:79 assert (!valids.reduce(_||_) || winner.reduce(_||_))\n") : printf_1
assert(clock, _T_13, UInt<1>(0h1), "") : assert_1
node maskedBeats_0 = mux(winner[0], beatsAI_0, UInt<1>(0h0))
node maskedBeats_1 = mux(winner[1], beatsAI_1, UInt<1>(0h0))
node initBeats = or(maskedBeats_0, maskedBeats_1)
node _beatsLeft_T = and(out[0].a.ready, out[0].a.valid)
node _beatsLeft_T_1 = sub(beatsLeft, _beatsLeft_T)
node _beatsLeft_T_2 = tail(_beatsLeft_T_1, 1)
node _beatsLeft_T_3 = mux(latch, initBeats, _beatsLeft_T_2)
connect beatsLeft, _beatsLeft_T_3
wire _state_WIRE : UInt<1>[2]
connect _state_WIRE[0], UInt<1>(0h0)
connect _state_WIRE[1], UInt<1>(0h0)
regreset state : UInt<1>[2], clock, reset, _state_WIRE
node muxState = mux(idle, winner, state)
connect state, muxState
node allowed = mux(idle, readys, state)
node _filtered_0_ready_T = and(out[0].a.ready, allowed[0])
connect portsAOI_filtered[0].ready, _filtered_0_ready_T
node _filtered_0_ready_T_1 = and(out[0].a.ready, allowed[1])
connect portsAOI_filtered_1[0].ready, _filtered_0_ready_T_1
node _out_0_a_valid_T = or(portsAOI_filtered[0].valid, portsAOI_filtered_1[0].valid)
node _out_0_a_valid_T_1 = mux(state[0], portsAOI_filtered[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_2 = mux(state[1], portsAOI_filtered_1[0].valid, UInt<1>(0h0))
node _out_0_a_valid_T_3 = or(_out_0_a_valid_T_1, _out_0_a_valid_T_2)
wire _out_0_a_valid_WIRE : UInt<1>
connect _out_0_a_valid_WIRE, _out_0_a_valid_T_3
node _out_0_a_valid_T_4 = mux(idle, _out_0_a_valid_T, _out_0_a_valid_WIRE)
connect out[0].a.valid, _out_0_a_valid_T_4
wire _out_0_a_bits_WIRE : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}
node _out_0_a_bits_T = mux(muxState[0], portsAOI_filtered[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_1 = mux(muxState[1], portsAOI_filtered_1[0].bits.corrupt, UInt<1>(0h0))
node _out_0_a_bits_T_2 = or(_out_0_a_bits_T, _out_0_a_bits_T_1)
wire _out_0_a_bits_WIRE_1 : UInt<1>
connect _out_0_a_bits_WIRE_1, _out_0_a_bits_T_2
connect _out_0_a_bits_WIRE.corrupt, _out_0_a_bits_WIRE_1
node _out_0_a_bits_T_3 = mux(muxState[0], portsAOI_filtered[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_4 = mux(muxState[1], portsAOI_filtered_1[0].bits.data, UInt<1>(0h0))
node _out_0_a_bits_T_5 = or(_out_0_a_bits_T_3, _out_0_a_bits_T_4)
wire _out_0_a_bits_WIRE_2 : UInt<128>
connect _out_0_a_bits_WIRE_2, _out_0_a_bits_T_5
connect _out_0_a_bits_WIRE.data, _out_0_a_bits_WIRE_2
node _out_0_a_bits_T_6 = mux(muxState[0], portsAOI_filtered[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_7 = mux(muxState[1], portsAOI_filtered_1[0].bits.mask, UInt<1>(0h0))
node _out_0_a_bits_T_8 = or(_out_0_a_bits_T_6, _out_0_a_bits_T_7)
wire _out_0_a_bits_WIRE_3 : UInt<16>
connect _out_0_a_bits_WIRE_3, _out_0_a_bits_T_8
connect _out_0_a_bits_WIRE.mask, _out_0_a_bits_WIRE_3
wire _out_0_a_bits_WIRE_4 : { }
connect _out_0_a_bits_WIRE.echo, _out_0_a_bits_WIRE_4
wire _out_0_a_bits_WIRE_5 : { }
connect _out_0_a_bits_WIRE.user, _out_0_a_bits_WIRE_5
node _out_0_a_bits_T_9 = mux(muxState[0], portsAOI_filtered[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_10 = mux(muxState[1], portsAOI_filtered_1[0].bits.address, UInt<1>(0h0))
node _out_0_a_bits_T_11 = or(_out_0_a_bits_T_9, _out_0_a_bits_T_10)
wire _out_0_a_bits_WIRE_6 : UInt<32>
connect _out_0_a_bits_WIRE_6, _out_0_a_bits_T_11
connect _out_0_a_bits_WIRE.address, _out_0_a_bits_WIRE_6
node _out_0_a_bits_T_12 = mux(muxState[0], portsAOI_filtered[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_13 = mux(muxState[1], portsAOI_filtered_1[0].bits.source, UInt<1>(0h0))
node _out_0_a_bits_T_14 = or(_out_0_a_bits_T_12, _out_0_a_bits_T_13)
wire _out_0_a_bits_WIRE_7 : UInt<5>
connect _out_0_a_bits_WIRE_7, _out_0_a_bits_T_14
connect _out_0_a_bits_WIRE.source, _out_0_a_bits_WIRE_7
node _out_0_a_bits_T_15 = mux(muxState[0], portsAOI_filtered[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_16 = mux(muxState[1], portsAOI_filtered_1[0].bits.size, UInt<1>(0h0))
node _out_0_a_bits_T_17 = or(_out_0_a_bits_T_15, _out_0_a_bits_T_16)
wire _out_0_a_bits_WIRE_8 : UInt<4>
connect _out_0_a_bits_WIRE_8, _out_0_a_bits_T_17
connect _out_0_a_bits_WIRE.size, _out_0_a_bits_WIRE_8
node _out_0_a_bits_T_18 = mux(muxState[0], portsAOI_filtered[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_19 = mux(muxState[1], portsAOI_filtered_1[0].bits.param, UInt<1>(0h0))
node _out_0_a_bits_T_20 = or(_out_0_a_bits_T_18, _out_0_a_bits_T_19)
wire _out_0_a_bits_WIRE_9 : UInt<3>
connect _out_0_a_bits_WIRE_9, _out_0_a_bits_T_20
connect _out_0_a_bits_WIRE.param, _out_0_a_bits_WIRE_9
node _out_0_a_bits_T_21 = mux(muxState[0], portsAOI_filtered[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_22 = mux(muxState[1], portsAOI_filtered_1[0].bits.opcode, UInt<1>(0h0))
node _out_0_a_bits_T_23 = or(_out_0_a_bits_T_21, _out_0_a_bits_T_22)
wire _out_0_a_bits_WIRE_10 : UInt<3>
connect _out_0_a_bits_WIRE_10, _out_0_a_bits_T_23
connect _out_0_a_bits_WIRE.opcode, _out_0_a_bits_WIRE_10
connect out[0].a.bits.corrupt, _out_0_a_bits_WIRE.corrupt
connect out[0].a.bits.data, _out_0_a_bits_WIRE.data
connect out[0].a.bits.mask, _out_0_a_bits_WIRE.mask
connect out[0].a.bits.address, _out_0_a_bits_WIRE.address
connect out[0].a.bits.source, _out_0_a_bits_WIRE.source
connect out[0].a.bits.size, _out_0_a_bits_WIRE.size
connect out[0].a.bits.param, _out_0_a_bits_WIRE.param
connect out[0].a.bits.opcode, _out_0_a_bits_WIRE.opcode
wire _WIRE_72 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_72.bits.corrupt, UInt<1>(0h0)
connect _WIRE_72.bits.data, UInt<128>(0h0)
connect _WIRE_72.bits.address, UInt<32>(0h0)
connect _WIRE_72.bits.source, UInt<5>(0h0)
connect _WIRE_72.bits.size, UInt<4>(0h0)
connect _WIRE_72.bits.param, UInt<3>(0h0)
connect _WIRE_72.bits.opcode, UInt<3>(0h0)
connect _WIRE_72.valid, UInt<1>(0h0)
connect _WIRE_72.ready, UInt<1>(0h0)
wire _WIRE_73 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_73.bits, _WIRE_72.bits
connect _WIRE_73.valid, _WIRE_72.valid
connect _WIRE_73.ready, _WIRE_72.ready
invalidate _WIRE_73.bits.corrupt
invalidate _WIRE_73.bits.data
invalidate _WIRE_73.bits.address
invalidate _WIRE_73.bits.source
invalidate _WIRE_73.bits.size
invalidate _WIRE_73.bits.param
invalidate _WIRE_73.bits.opcode
wire _WIRE_74 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_74.bits.sink, UInt<4>(0h0)
connect _WIRE_74.valid, UInt<1>(0h0)
connect _WIRE_74.ready, UInt<1>(0h0)
wire _WIRE_75 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}
connect _WIRE_75.bits, _WIRE_74.bits
connect _WIRE_75.valid, _WIRE_74.valid
connect _WIRE_75.ready, _WIRE_74.ready
invalidate _WIRE_75.bits.sink
connect portsCOI_filtered[0].ready, UInt<1>(0h0)
connect portsCOI_filtered_1[0].ready, UInt<1>(0h0)
connect portsEOI_filtered[0].ready, UInt<1>(0h0)
connect portsEOI_filtered_1[0].ready, UInt<1>(0h0)
wire _WIRE_76 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_76.bits.corrupt, UInt<1>(0h0)
connect _WIRE_76.bits.data, UInt<128>(0h0)
connect _WIRE_76.bits.mask, UInt<16>(0h0)
connect _WIRE_76.bits.address, UInt<32>(0h0)
connect _WIRE_76.bits.source, UInt<5>(0h0)
connect _WIRE_76.bits.size, UInt<4>(0h0)
connect _WIRE_76.bits.param, UInt<2>(0h0)
connect _WIRE_76.bits.opcode, UInt<3>(0h0)
connect _WIRE_76.valid, UInt<1>(0h0)
connect _WIRE_76.ready, UInt<1>(0h0)
wire _WIRE_77 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_77.bits, _WIRE_76.bits
connect _WIRE_77.valid, _WIRE_76.valid
connect _WIRE_77.ready, _WIRE_76.ready
invalidate _WIRE_77.bits.corrupt
invalidate _WIRE_77.bits.data
invalidate _WIRE_77.bits.mask
invalidate _WIRE_77.bits.address
invalidate _WIRE_77.bits.source
invalidate _WIRE_77.bits.size
invalidate _WIRE_77.bits.param
invalidate _WIRE_77.bits.opcode
connect in[0].d, portsDIO_filtered[0]
connect portsBIO_filtered[0].ready, UInt<1>(0h0)
wire _WIRE_78 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_78.bits.corrupt, UInt<1>(0h0)
connect _WIRE_78.bits.data, UInt<128>(0h0)
connect _WIRE_78.bits.mask, UInt<16>(0h0)
connect _WIRE_78.bits.address, UInt<32>(0h0)
connect _WIRE_78.bits.source, UInt<5>(0h0)
connect _WIRE_78.bits.size, UInt<4>(0h0)
connect _WIRE_78.bits.param, UInt<2>(0h0)
connect _WIRE_78.bits.opcode, UInt<3>(0h0)
connect _WIRE_78.valid, UInt<1>(0h0)
connect _WIRE_78.ready, UInt<1>(0h0)
wire _WIRE_79 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}
connect _WIRE_79.bits, _WIRE_78.bits
connect _WIRE_79.valid, _WIRE_78.valid
connect _WIRE_79.ready, _WIRE_78.ready
invalidate _WIRE_79.bits.corrupt
invalidate _WIRE_79.bits.data
invalidate _WIRE_79.bits.mask
invalidate _WIRE_79.bits.address
invalidate _WIRE_79.bits.source
invalidate _WIRE_79.bits.size
invalidate _WIRE_79.bits.param
invalidate _WIRE_79.bits.opcode
connect in[1].d, portsDIO_filtered[1]
connect portsBIO_filtered[1].ready, UInt<1>(0h0) | module TLXbar_i2_o1_a32d128s5k4z4u( // @[Xbar.scala:74:9]
input clock, // @[Xbar.scala:74:9]
input reset, // @[Xbar.scala:74:9]
output auto_anon_in_1_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [15:0] auto_anon_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_anon_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_1_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_1_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_1_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_anon_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_1_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_a_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_in_0_a_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_0_a_bits_size, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_in_0_a_bits_source, // @[LazyModuleImp.scala:107:25]
input [31:0] auto_anon_in_0_a_bits_address, // @[LazyModuleImp.scala:107:25]
input [15:0] auto_anon_in_0_a_bits_mask, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_anon_in_0_a_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_in_0_d_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_in_0_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [1:0] auto_anon_in_0_d_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_0_d_bits_size, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_0_d_bits_source, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_in_0_d_bits_sink, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_denied, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_anon_in_0_d_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_in_0_d_bits_corrupt, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25]
output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25]
output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25]
output [4:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25]
output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25]
output [15:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25]
output [127:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25]
output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25]
input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25]
input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25]
input [4:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25]
input [3:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25]
input [127:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25]
input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25]
);
wire [3:0] out_0_d_bits_sink; // @[Xbar.scala:216:19]
wire [4:0] in_1_a_bits_source; // @[Xbar.scala:159:18]
wire [4:0] in_0_a_bits_source; // @[Xbar.scala:159:18]
wire auto_anon_in_1_a_valid_0 = auto_anon_in_1_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_a_bits_opcode_0 = auto_anon_in_1_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_a_bits_param_0 = auto_anon_in_1_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_a_bits_size_0 = auto_anon_in_1_a_bits_size; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_a_bits_source_0 = auto_anon_in_1_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_1_a_bits_address_0 = auto_anon_in_1_a_bits_address; // @[Xbar.scala:74:9]
wire [15:0] auto_anon_in_1_a_bits_mask_0 = auto_anon_in_1_a_bits_mask; // @[Xbar.scala:74:9]
wire [127:0] auto_anon_in_1_a_bits_data_0 = auto_anon_in_1_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_1_a_bits_corrupt_0 = auto_anon_in_1_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_ready_0 = auto_anon_in_1_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_valid_0 = auto_anon_in_0_a_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_a_bits_opcode_0 = auto_anon_in_0_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_a_bits_param_0 = auto_anon_in_0_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_a_bits_size_0 = auto_anon_in_0_a_bits_size; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_a_bits_source_0 = auto_anon_in_0_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_in_0_a_bits_address_0 = auto_anon_in_0_a_bits_address; // @[Xbar.scala:74:9]
wire [15:0] auto_anon_in_0_a_bits_mask_0 = auto_anon_in_0_a_bits_mask; // @[Xbar.scala:74:9]
wire [127:0] auto_anon_in_0_a_bits_data_0 = auto_anon_in_0_a_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_bits_corrupt_0 = auto_anon_in_0_a_bits_corrupt; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_ready_0 = auto_anon_in_0_d_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[Xbar.scala:74:9]
wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[Xbar.scala:74:9]
wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[Xbar.scala:74:9]
wire [127:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[Xbar.scala:74:9]
wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[Xbar.scala:74:9]
wire _readys_T_2 = reset; // @[Arbiter.scala:22:12]
wire _addressC_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _addressC_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _addressC_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire _requestBOI_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_T = 1'h0; // @[Parameters.scala:54:10]
wire _requestBOI_T_1 = 1'h0; // @[Parameters.scala:54:32]
wire _requestBOI_T_3 = 1'h0; // @[Parameters.scala:54:67]
wire requestBOI_0_0 = 1'h0; // @[Parameters.scala:56:48]
wire _requestBOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _requestBOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _requestBOI_T_5 = 1'h0; // @[Parameters.scala:54:10]
wire _requestEIO_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_T = 1'h0; // @[Parameters.scala:54:10]
wire _requestEIO_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74]
wire _requestEIO_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61]
wire _requestEIO_T_5 = 1'h0; // @[Parameters.scala:54:10]
wire _beatsBO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _beatsBO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire _beatsBO_opdata_T = 1'h0; // @[Edges.scala:97:37]
wire _beatsCI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire beatsCI_opdata = 1'h0; // @[Edges.scala:102:36]
wire _beatsCI_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _beatsCI_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _beatsCI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire beatsCI_opdata_1 = 1'h0; // @[Edges.scala:102:36]
wire _beatsEI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74]
wire _beatsEI_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61]
wire _beatsEI_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61]
wire _portsBIO_WIRE_ready = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_valid = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74]
wire _portsBIO_WIRE_1_ready = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_1_valid = 1'h0; // @[Bundles.scala:264:61]
wire _portsBIO_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61]
wire portsBIO_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsBIO_filtered_1_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsBIO_filtered_0_valid_T = 1'h0; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_filtered_1_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsBIO_T = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_T_1 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_T_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsBIO_WIRE_2 = 1'h0; // @[Mux.scala:30:73]
wire _portsCOI_WIRE_ready = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_valid = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire portsCOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsCOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74]
wire _portsCOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61]
wire _portsCOI_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61]
wire portsCOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire portsCOI_filtered_1_0_bits_corrupt = 1'h0; // @[Xbar.scala:352:24]
wire _portsCOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_WIRE_ready = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_valid = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_1_ready = 1'h0; // @[Bundles.scala:267:61]
wire _portsEOI_WIRE_1_valid = 1'h0; // @[Bundles.scala:267:61]
wire portsEOI_filtered_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_1 = 1'h0; // @[Xbar.scala:355:40]
wire _portsEOI_WIRE_2_ready = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_2_valid = 1'h0; // @[Bundles.scala:267:74]
wire _portsEOI_WIRE_3_ready = 1'h0; // @[Bundles.scala:267:61]
wire _portsEOI_WIRE_3_valid = 1'h0; // @[Bundles.scala:267:61]
wire portsEOI_filtered_1_0_ready = 1'h0; // @[Xbar.scala:352:24]
wire portsEOI_filtered_1_0_valid = 1'h0; // @[Xbar.scala:352:24]
wire _portsEOI_filtered_0_valid_T_3 = 1'h0; // @[Xbar.scala:355:40]
wire _state_WIRE_0 = 1'h0; // @[Arbiter.scala:88:34]
wire _state_WIRE_1 = 1'h0; // @[Arbiter.scala:88:34]
wire _requestAIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire requestAIO_0_0 = 1'h1; // @[Xbar.scala:307:107]
wire _requestAIO_T_9 = 1'h1; // @[Parameters.scala:137:59]
wire requestAIO_1_0 = 1'h1; // @[Xbar.scala:307:107]
wire _requestCIO_T_4 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_0_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestCIO_T_9 = 1'h1; // @[Parameters.scala:137:59]
wire requestCIO_1_0 = 1'h1; // @[Xbar.scala:308:107]
wire _requestBOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _requestBOI_T_6 = 1'h1; // @[Parameters.scala:54:32]
wire _requestBOI_T_7 = 1'h1; // @[Parameters.scala:56:32]
wire _requestBOI_T_8 = 1'h1; // @[Parameters.scala:54:67]
wire _requestBOI_T_9 = 1'h1; // @[Parameters.scala:57:20]
wire requestBOI_0_1 = 1'h1; // @[Parameters.scala:56:48]
wire _requestDOI_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire _requestDOI_T_7 = 1'h1; // @[Parameters.scala:56:32]
wire _requestDOI_T_9 = 1'h1; // @[Parameters.scala:57:20]
wire _requestEIO_T_1 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_2 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_3 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_4 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_0_0 = 1'h1; // @[Parameters.scala:56:48]
wire _requestEIO_T_6 = 1'h1; // @[Parameters.scala:54:32]
wire _requestEIO_T_7 = 1'h1; // @[Parameters.scala:56:32]
wire _requestEIO_T_8 = 1'h1; // @[Parameters.scala:54:67]
wire _requestEIO_T_9 = 1'h1; // @[Parameters.scala:57:20]
wire requestEIO_1_0 = 1'h1; // @[Parameters.scala:56:48]
wire beatsBO_opdata = 1'h1; // @[Edges.scala:97:28]
wire _portsAOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsAOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire _portsBIO_filtered_1_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsCOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T = 1'h1; // @[Xbar.scala:355:54]
wire _portsEOI_filtered_0_valid_T_2 = 1'h1; // @[Xbar.scala:355:54]
wire [3:0] _addressC_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _addressC_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _addressC_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _addressC_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _requestBOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _requestBOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] requestBOI_uncommonBits = 4'h0; // @[Parameters.scala:52:56]
wire [3:0] _requestBOI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _requestBOI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] requestBOI_uncommonBits_1 = 4'h0; // @[Parameters.scala:52:56]
wire [3:0] _requestEIO_WIRE_bits_sink = 4'h0; // @[Bundles.scala:267:74]
wire [3:0] _requestEIO_WIRE_1_bits_sink = 4'h0; // @[Bundles.scala:267:61]
wire [3:0] _requestEIO_uncommonBits_T = 4'h0; // @[Parameters.scala:52:29]
wire [3:0] requestEIO_uncommonBits = 4'h0; // @[Parameters.scala:52:56]
wire [3:0] _requestEIO_WIRE_2_bits_sink = 4'h0; // @[Bundles.scala:267:74]
wire [3:0] _requestEIO_WIRE_3_bits_sink = 4'h0; // @[Bundles.scala:267:61]
wire [3:0] _requestEIO_uncommonBits_T_1 = 4'h0; // @[Parameters.scala:52:29]
wire [3:0] requestEIO_uncommonBits_1 = 4'h0; // @[Parameters.scala:52:56]
wire [3:0] _beatsBO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _beatsBO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] _beatsCI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _beatsCI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _beatsCI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _beatsCI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] _beatsEI_WIRE_bits_sink = 4'h0; // @[Bundles.scala:267:74]
wire [3:0] _beatsEI_WIRE_1_bits_sink = 4'h0; // @[Bundles.scala:267:61]
wire [3:0] _beatsEI_WIRE_2_bits_sink = 4'h0; // @[Bundles.scala:267:74]
wire [3:0] _beatsEI_WIRE_3_bits_sink = 4'h0; // @[Bundles.scala:267:61]
wire [3:0] _portsBIO_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74]
wire [3:0] _portsBIO_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:264:61]
wire [3:0] portsBIO_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] portsBIO_filtered_1_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] _portsCOI_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _portsCOI_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] portsCOI_filtered_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] _portsCOI_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74]
wire [3:0] _portsCOI_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61]
wire [3:0] portsCOI_filtered_1_0_bits_size = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] _portsEOI_WIRE_bits_sink = 4'h0; // @[Bundles.scala:267:74]
wire [3:0] _portsEOI_WIRE_1_bits_sink = 4'h0; // @[Bundles.scala:267:61]
wire [3:0] portsEOI_filtered_0_bits_sink = 4'h0; // @[Xbar.scala:352:24]
wire [3:0] _portsEOI_WIRE_2_bits_sink = 4'h0; // @[Bundles.scala:267:74]
wire [3:0] _portsEOI_WIRE_3_bits_sink = 4'h0; // @[Bundles.scala:267:61]
wire [3:0] portsEOI_filtered_1_0_bits_sink = 4'h0; // @[Xbar.scala:352:24]
wire [127:0] _addressC_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _addressC_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _addressC_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _addressC_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _requestBOI_WIRE_bits_data = 128'h0; // @[Bundles.scala:264:74]
wire [127:0] _requestBOI_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:264:61]
wire [127:0] _requestBOI_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:264:74]
wire [127:0] _requestBOI_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:264:61]
wire [127:0] _beatsBO_WIRE_bits_data = 128'h0; // @[Bundles.scala:264:74]
wire [127:0] _beatsBO_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:264:61]
wire [127:0] _beatsCI_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _beatsCI_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _beatsCI_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _beatsCI_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] _portsBIO_WIRE_bits_data = 128'h0; // @[Bundles.scala:264:74]
wire [127:0] _portsBIO_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:264:61]
wire [127:0] portsBIO_filtered_0_bits_data = 128'h0; // @[Xbar.scala:352:24]
wire [127:0] portsBIO_filtered_1_bits_data = 128'h0; // @[Xbar.scala:352:24]
wire [127:0] _portsCOI_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _portsCOI_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] portsCOI_filtered_0_bits_data = 128'h0; // @[Xbar.scala:352:24]
wire [127:0] _portsCOI_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74]
wire [127:0] _portsCOI_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61]
wire [127:0] portsCOI_filtered_1_0_bits_data = 128'h0; // @[Xbar.scala:352:24]
wire [31:0] _addressC_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _addressC_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _addressC_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _addressC_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _requestCIO_T = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestCIO_T_5 = 32'h0; // @[Parameters.scala:137:31]
wire [31:0] _requestBOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _requestBOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _requestBOI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _requestBOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _beatsBO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _beatsBO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] _beatsCI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _beatsCI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _beatsCI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _beatsCI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] _portsBIO_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74]
wire [31:0] _portsBIO_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:264:61]
wire [31:0] portsBIO_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] portsBIO_filtered_1_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] _portsCOI_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _portsCOI_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] portsCOI_filtered_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [31:0] _portsCOI_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74]
wire [31:0] _portsCOI_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61]
wire [31:0] portsCOI_filtered_1_0_bits_address = 32'h0; // @[Xbar.scala:352:24]
wire [4:0] _addressC_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _addressC_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _addressC_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _addressC_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _requestBOI_WIRE_bits_source = 5'h0; // @[Bundles.scala:264:74]
wire [4:0] _requestBOI_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:264:61]
wire [4:0] _requestBOI_uncommonBits_T = 5'h0; // @[Parameters.scala:52:29]
wire [4:0] _requestBOI_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:264:74]
wire [4:0] _requestBOI_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:264:61]
wire [4:0] _requestBOI_uncommonBits_T_1 = 5'h0; // @[Parameters.scala:52:29]
wire [4:0] _beatsBO_WIRE_bits_source = 5'h0; // @[Bundles.scala:264:74]
wire [4:0] _beatsBO_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:264:61]
wire [4:0] _beatsCI_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _beatsCI_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _beatsCI_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _beatsCI_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] _portsBIO_WIRE_bits_source = 5'h0; // @[Bundles.scala:264:74]
wire [4:0] _portsBIO_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:264:61]
wire [4:0] portsBIO_filtered_0_bits_source = 5'h0; // @[Xbar.scala:352:24]
wire [4:0] portsBIO_filtered_1_bits_source = 5'h0; // @[Xbar.scala:352:24]
wire [4:0] _portsCOI_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _portsCOI_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] portsCOI_filtered_0_bits_source = 5'h0; // @[Xbar.scala:352:24]
wire [4:0] _portsCOI_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74]
wire [4:0] _portsCOI_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61]
wire [4:0] portsCOI_filtered_1_0_bits_source = 5'h0; // @[Xbar.scala:352:24]
wire [2:0] _addressC_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _addressC_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _addressC_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _addressC_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _addressC_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _requestBOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _requestBOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _requestBOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _requestBOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _beatsBO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _beatsBO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] _beatsCI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _beatsCI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _beatsCI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _beatsCI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _beatsCI_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _portsBIO_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74]
wire [2:0] _portsBIO_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61]
wire [2:0] portsBIO_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsBIO_filtered_1_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _portsCOI_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _portsCOI_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] portsCOI_filtered_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] _portsCOI_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74]
wire [2:0] _portsCOI_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] _portsCOI_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61]
wire [2:0] portsCOI_filtered_1_0_bits_opcode = 3'h0; // @[Xbar.scala:352:24]
wire [2:0] portsCOI_filtered_1_0_bits_param = 3'h0; // @[Xbar.scala:352:24]
wire [15:0] _requestBOI_WIRE_bits_mask = 16'h0; // @[Bundles.scala:264:74]
wire [15:0] _requestBOI_WIRE_1_bits_mask = 16'h0; // @[Bundles.scala:264:61]
wire [15:0] _requestBOI_WIRE_2_bits_mask = 16'h0; // @[Bundles.scala:264:74]
wire [15:0] _requestBOI_WIRE_3_bits_mask = 16'h0; // @[Bundles.scala:264:61]
wire [15:0] _beatsBO_WIRE_bits_mask = 16'h0; // @[Bundles.scala:264:74]
wire [15:0] _beatsBO_WIRE_1_bits_mask = 16'h0; // @[Bundles.scala:264:61]
wire [15:0] _portsBIO_WIRE_bits_mask = 16'h0; // @[Bundles.scala:264:74]
wire [15:0] _portsBIO_WIRE_1_bits_mask = 16'h0; // @[Bundles.scala:264:61]
wire [15:0] portsBIO_filtered_0_bits_mask = 16'h0; // @[Xbar.scala:352:24]
wire [15:0] portsBIO_filtered_1_bits_mask = 16'h0; // @[Xbar.scala:352:24]
wire [1:0] _requestBOI_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _requestBOI_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _requestBOI_WIRE_2_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _requestBOI_WIRE_3_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _beatsBO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _beatsBO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] _portsBIO_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74]
wire [1:0] _portsBIO_WIRE_1_bits_param = 2'h0; // @[Bundles.scala:264:61]
wire [1:0] portsBIO_filtered_0_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [1:0] portsBIO_filtered_1_bits_param = 2'h0; // @[Xbar.scala:352:24]
wire [7:0] beatsBO_decode = 8'h0; // @[Edges.scala:220:59]
wire [7:0] beatsBO_0 = 8'h0; // @[Edges.scala:221:14]
wire [7:0] beatsCI_decode = 8'h0; // @[Edges.scala:220:59]
wire [7:0] beatsCI_0 = 8'h0; // @[Edges.scala:221:14]
wire [7:0] beatsCI_decode_1 = 8'h0; // @[Edges.scala:220:59]
wire [7:0] beatsCI_1 = 8'h0; // @[Edges.scala:221:14]
wire [11:0] _beatsBO_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_2 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsCI_decode_T_5 = 12'h0; // @[package.scala:243:46]
wire [11:0] _beatsBO_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_1 = 12'hFFF; // @[package.scala:243:76]
wire [11:0] _beatsCI_decode_T_4 = 12'hFFF; // @[package.scala:243:76]
wire [26:0] _beatsBO_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T = 27'hFFF; // @[package.scala:243:71]
wire [26:0] _beatsCI_decode_T_3 = 27'hFFF; // @[package.scala:243:71]
wire [32:0] _requestAIO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_7 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestAIO_T_8 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_1 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_2 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_3 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_6 = 33'h0; // @[Parameters.scala:137:41]
wire [32:0] _requestCIO_T_7 = 33'h0; // @[Parameters.scala:137:46]
wire [32:0] _requestCIO_T_8 = 33'h0; // @[Parameters.scala:137:46]
wire anonIn_1_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_1_a_valid = auto_anon_in_1_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_1_a_bits_opcode = auto_anon_in_1_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_1_a_bits_param = auto_anon_in_1_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_1_a_bits_size = auto_anon_in_1_a_bits_size_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_1_a_bits_source = auto_anon_in_1_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_1_a_bits_address = auto_anon_in_1_a_bits_address_0; // @[Xbar.scala:74:9]
wire [15:0] anonIn_1_a_bits_mask = auto_anon_in_1_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [127:0] anonIn_1_a_bits_data = auto_anon_in_1_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_1_a_bits_corrupt = auto_anon_in_1_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_1_d_ready = auto_anon_in_1_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_1_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_1_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_1_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_1_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_1_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_1_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_denied; // @[MixedNode.scala:551:17]
wire [127:0] anonIn_1_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_1_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonIn_a_ready; // @[MixedNode.scala:551:17]
wire anonIn_a_valid = auto_anon_in_0_a_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_opcode = auto_anon_in_0_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] anonIn_a_bits_param = auto_anon_in_0_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_a_bits_size = auto_anon_in_0_a_bits_size_0; // @[Xbar.scala:74:9]
wire [3:0] anonIn_a_bits_source = auto_anon_in_0_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] anonIn_a_bits_address = auto_anon_in_0_a_bits_address_0; // @[Xbar.scala:74:9]
wire [15:0] anonIn_a_bits_mask = auto_anon_in_0_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [127:0] anonIn_a_bits_data = auto_anon_in_0_a_bits_data_0; // @[Xbar.scala:74:9]
wire anonIn_a_bits_corrupt = auto_anon_in_0_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire anonIn_d_ready = auto_anon_in_0_d_ready_0; // @[Xbar.scala:74:9]
wire anonIn_d_valid; // @[MixedNode.scala:551:17]
wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17]
wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17]
wire [3:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17]
wire [127:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17]
wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17]
wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[Xbar.scala:74:9]
wire anonOut_a_valid; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17]
wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17]
wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17]
wire [4:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17]
wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17]
wire [15:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17]
wire [127:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17]
wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17]
wire anonOut_d_ready; // @[MixedNode.scala:542:17]
wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[Xbar.scala:74:9]
wire [3:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [127:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[Xbar.scala:74:9]
wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_1_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_1_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_d_bits_size_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_d_bits_source_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_1_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [127:0] auto_anon_in_1_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_1_d_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_a_ready_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_in_0_d_bits_opcode_0; // @[Xbar.scala:74:9]
wire [1:0] auto_anon_in_0_d_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_d_bits_size_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_d_bits_source_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_in_0_d_bits_sink_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_bits_denied_0; // @[Xbar.scala:74:9]
wire [127:0] auto_anon_in_0_d_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_in_0_d_valid_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_a_bits_opcode_0; // @[Xbar.scala:74:9]
wire [2:0] auto_anon_out_a_bits_param_0; // @[Xbar.scala:74:9]
wire [3:0] auto_anon_out_a_bits_size_0; // @[Xbar.scala:74:9]
wire [4:0] auto_anon_out_a_bits_source_0; // @[Xbar.scala:74:9]
wire [31:0] auto_anon_out_a_bits_address_0; // @[Xbar.scala:74:9]
wire [15:0] auto_anon_out_a_bits_mask_0; // @[Xbar.scala:74:9]
wire [127:0] auto_anon_out_a_bits_data_0; // @[Xbar.scala:74:9]
wire auto_anon_out_a_bits_corrupt_0; // @[Xbar.scala:74:9]
wire auto_anon_out_a_valid_0; // @[Xbar.scala:74:9]
wire auto_anon_out_d_ready_0; // @[Xbar.scala:74:9]
wire in_0_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_0_a_ready_0 = anonIn_a_ready; // @[Xbar.scala:74:9]
wire in_0_a_valid = anonIn_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_0_a_bits_opcode = anonIn_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_0_a_bits_param = anonIn_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_0_a_bits_size = anonIn_a_bits_size; // @[Xbar.scala:159:18]
wire [31:0] in_0_a_bits_address = anonIn_a_bits_address; // @[Xbar.scala:159:18]
wire [15:0] in_0_a_bits_mask = anonIn_a_bits_mask; // @[Xbar.scala:159:18]
wire [127:0] in_0_a_bits_data = anonIn_a_bits_data; // @[Xbar.scala:159:18]
wire in_0_a_bits_corrupt = anonIn_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_0_d_ready = anonIn_d_ready; // @[Xbar.scala:159:18]
wire in_0_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_valid_0 = anonIn_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_0_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_0_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_param_0 = anonIn_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_0_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_size_0 = anonIn_d_bits_size; // @[Xbar.scala:74:9]
wire [3:0] _anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign auto_anon_in_0_d_bits_source_0 = anonIn_d_bits_source; // @[Xbar.scala:74:9]
wire [3:0] in_0_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_sink_0 = anonIn_d_bits_sink; // @[Xbar.scala:74:9]
wire in_0_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_denied_0 = anonIn_d_bits_denied; // @[Xbar.scala:74:9]
wire [127:0] in_0_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_data_0 = anonIn_d_bits_data; // @[Xbar.scala:74:9]
wire in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_0_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[Xbar.scala:74:9]
wire in_1_a_ready; // @[Xbar.scala:159:18]
assign auto_anon_in_1_a_ready_0 = anonIn_1_a_ready; // @[Xbar.scala:74:9]
wire in_1_a_valid = anonIn_1_a_valid; // @[Xbar.scala:159:18]
wire [2:0] in_1_a_bits_opcode = anonIn_1_a_bits_opcode; // @[Xbar.scala:159:18]
wire [2:0] in_1_a_bits_param = anonIn_1_a_bits_param; // @[Xbar.scala:159:18]
wire [3:0] in_1_a_bits_size = anonIn_1_a_bits_size; // @[Xbar.scala:159:18]
wire [3:0] _in_1_a_bits_source_T = anonIn_1_a_bits_source; // @[Xbar.scala:166:55]
wire [31:0] in_1_a_bits_address = anonIn_1_a_bits_address; // @[Xbar.scala:159:18]
wire [15:0] in_1_a_bits_mask = anonIn_1_a_bits_mask; // @[Xbar.scala:159:18]
wire [127:0] in_1_a_bits_data = anonIn_1_a_bits_data; // @[Xbar.scala:159:18]
wire in_1_a_bits_corrupt = anonIn_1_a_bits_corrupt; // @[Xbar.scala:159:18]
wire in_1_d_ready = anonIn_1_d_ready; // @[Xbar.scala:159:18]
wire in_1_d_valid; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_valid_0 = anonIn_1_d_valid; // @[Xbar.scala:74:9]
wire [2:0] in_1_d_bits_opcode; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_opcode_0 = anonIn_1_d_bits_opcode; // @[Xbar.scala:74:9]
wire [1:0] in_1_d_bits_param; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_param_0 = anonIn_1_d_bits_param; // @[Xbar.scala:74:9]
wire [3:0] in_1_d_bits_size; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_size_0 = anonIn_1_d_bits_size; // @[Xbar.scala:74:9]
wire [3:0] _anonIn_d_bits_source_T_1; // @[Xbar.scala:156:69]
assign auto_anon_in_1_d_bits_source_0 = anonIn_1_d_bits_source; // @[Xbar.scala:74:9]
wire [3:0] in_1_d_bits_sink; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_sink_0 = anonIn_1_d_bits_sink; // @[Xbar.scala:74:9]
wire in_1_d_bits_denied; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_denied_0 = anonIn_1_d_bits_denied; // @[Xbar.scala:74:9]
wire [127:0] in_1_d_bits_data; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_data_0 = anonIn_1_d_bits_data; // @[Xbar.scala:74:9]
wire in_1_d_bits_corrupt; // @[Xbar.scala:159:18]
assign auto_anon_in_1_d_bits_corrupt_0 = anonIn_1_d_bits_corrupt; // @[Xbar.scala:74:9]
wire out_0_a_ready = anonOut_a_ready; // @[Xbar.scala:216:19]
wire out_0_a_valid; // @[Xbar.scala:216:19]
assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[Xbar.scala:74:9]
wire [2:0] out_0_a_bits_opcode; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[Xbar.scala:74:9]
wire [2:0] out_0_a_bits_param; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[Xbar.scala:74:9]
wire [3:0] out_0_a_bits_size; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[Xbar.scala:74:9]
wire [4:0] out_0_a_bits_source; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[Xbar.scala:74:9]
wire [31:0] out_0_a_bits_address; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[Xbar.scala:74:9]
wire [15:0] out_0_a_bits_mask; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[Xbar.scala:74:9]
wire [127:0] out_0_a_bits_data; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[Xbar.scala:74:9]
wire out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[Xbar.scala:74:9]
wire out_0_d_ready; // @[Xbar.scala:216:19]
assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[Xbar.scala:74:9]
wire out_0_d_valid = anonOut_d_valid; // @[Xbar.scala:216:19]
wire [2:0] out_0_d_bits_opcode = anonOut_d_bits_opcode; // @[Xbar.scala:216:19]
wire [1:0] out_0_d_bits_param = anonOut_d_bits_param; // @[Xbar.scala:216:19]
wire [3:0] out_0_d_bits_size = anonOut_d_bits_size; // @[Xbar.scala:216:19]
wire [4:0] out_0_d_bits_source = anonOut_d_bits_source; // @[Xbar.scala:216:19]
wire [3:0] _out_0_d_bits_sink_T = anonOut_d_bits_sink; // @[Xbar.scala:251:53]
wire out_0_d_bits_denied = anonOut_d_bits_denied; // @[Xbar.scala:216:19]
wire [127:0] out_0_d_bits_data = anonOut_d_bits_data; // @[Xbar.scala:216:19]
wire out_0_d_bits_corrupt = anonOut_d_bits_corrupt; // @[Xbar.scala:216:19]
wire portsAOI_filtered_0_ready; // @[Xbar.scala:352:24]
assign anonIn_a_ready = in_0_a_ready; // @[Xbar.scala:159:18]
wire _portsAOI_filtered_0_valid_T_1 = in_0_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] portsAOI_filtered_0_bits_opcode = in_0_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_0_bits_param = in_0_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [4:0] _in_0_a_bits_source_T; // @[Xbar.scala:166:55]
wire [3:0] portsAOI_filtered_0_bits_size = in_0_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [4:0] portsAOI_filtered_0_bits_source = in_0_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T = in_0_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_0_bits_address = in_0_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [15:0] portsAOI_filtered_0_bits_mask = in_0_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [127:0] portsAOI_filtered_0_bits_data = in_0_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_0_bits_corrupt = in_0_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_0_ready = in_0_d_ready; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_0_valid; // @[Xbar.scala:352:24]
assign anonIn_d_valid = in_0_d_valid; // @[Xbar.scala:159:18]
wire [2:0] portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:352:24]
assign anonIn_d_bits_opcode = in_0_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] portsDIO_filtered_0_bits_param; // @[Xbar.scala:352:24]
assign anonIn_d_bits_param = in_0_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] portsDIO_filtered_0_bits_size; // @[Xbar.scala:352:24]
assign anonIn_d_bits_size = in_0_d_bits_size; // @[Xbar.scala:159:18]
wire [4:0] portsDIO_filtered_0_bits_source; // @[Xbar.scala:352:24]
wire [3:0] portsDIO_filtered_0_bits_sink; // @[Xbar.scala:352:24]
assign anonIn_d_bits_sink = in_0_d_bits_sink; // @[Xbar.scala:159:18]
wire portsDIO_filtered_0_bits_denied; // @[Xbar.scala:352:24]
assign anonIn_d_bits_denied = in_0_d_bits_denied; // @[Xbar.scala:159:18]
wire [127:0] portsDIO_filtered_0_bits_data; // @[Xbar.scala:352:24]
assign anonIn_d_bits_data = in_0_d_bits_data; // @[Xbar.scala:159:18]
wire portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:352:24]
assign anonIn_d_bits_corrupt = in_0_d_bits_corrupt; // @[Xbar.scala:159:18]
wire portsAOI_filtered_1_0_ready; // @[Xbar.scala:352:24]
assign anonIn_1_a_ready = in_1_a_ready; // @[Xbar.scala:159:18]
wire _portsAOI_filtered_0_valid_T_3 = in_1_a_valid; // @[Xbar.scala:159:18, :355:40]
wire [2:0] portsAOI_filtered_1_0_bits_opcode = in_1_a_bits_opcode; // @[Xbar.scala:159:18, :352:24]
wire [2:0] portsAOI_filtered_1_0_bits_param = in_1_a_bits_param; // @[Xbar.scala:159:18, :352:24]
wire [3:0] portsAOI_filtered_1_0_bits_size = in_1_a_bits_size; // @[Xbar.scala:159:18, :352:24]
wire [4:0] portsAOI_filtered_1_0_bits_source = in_1_a_bits_source; // @[Xbar.scala:159:18, :352:24]
wire [31:0] _requestAIO_T_5 = in_1_a_bits_address; // @[Xbar.scala:159:18]
wire [31:0] portsAOI_filtered_1_0_bits_address = in_1_a_bits_address; // @[Xbar.scala:159:18, :352:24]
wire [15:0] portsAOI_filtered_1_0_bits_mask = in_1_a_bits_mask; // @[Xbar.scala:159:18, :352:24]
wire [127:0] portsAOI_filtered_1_0_bits_data = in_1_a_bits_data; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_1_0_bits_corrupt = in_1_a_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_1_ready = in_1_d_ready; // @[Xbar.scala:159:18, :352:24]
wire portsDIO_filtered_1_valid; // @[Xbar.scala:352:24]
assign anonIn_1_d_valid = in_1_d_valid; // @[Xbar.scala:159:18]
wire [2:0] portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_opcode = in_1_d_bits_opcode; // @[Xbar.scala:159:18]
wire [1:0] portsDIO_filtered_1_bits_param; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_param = in_1_d_bits_param; // @[Xbar.scala:159:18]
wire [3:0] portsDIO_filtered_1_bits_size; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_size = in_1_d_bits_size; // @[Xbar.scala:159:18]
wire [4:0] portsDIO_filtered_1_bits_source; // @[Xbar.scala:352:24]
wire [3:0] portsDIO_filtered_1_bits_sink; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_sink = in_1_d_bits_sink; // @[Xbar.scala:159:18]
wire portsDIO_filtered_1_bits_denied; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_denied = in_1_d_bits_denied; // @[Xbar.scala:159:18]
wire [127:0] portsDIO_filtered_1_bits_data; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_data = in_1_d_bits_data; // @[Xbar.scala:159:18]
wire portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:352:24]
assign anonIn_1_d_bits_corrupt = in_1_d_bits_corrupt; // @[Xbar.scala:159:18]
wire [4:0] in_0_d_bits_source; // @[Xbar.scala:159:18]
wire [4:0] in_1_d_bits_source; // @[Xbar.scala:159:18]
assign _in_0_a_bits_source_T = {1'h1, anonIn_a_bits_source}; // @[Xbar.scala:166:55]
assign in_0_a_bits_source = _in_0_a_bits_source_T; // @[Xbar.scala:159:18, :166:55]
assign _anonIn_d_bits_source_T = in_0_d_bits_source[3:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_d_bits_source = _anonIn_d_bits_source_T; // @[Xbar.scala:156:69]
assign in_1_a_bits_source = {1'h0, _in_1_a_bits_source_T}; // @[Xbar.scala:159:18, :166:{29,55}]
assign _anonIn_d_bits_source_T_1 = in_1_d_bits_source[3:0]; // @[Xbar.scala:156:69, :159:18]
assign anonIn_1_d_bits_source = _anonIn_d_bits_source_T_1; // @[Xbar.scala:156:69]
wire _out_0_a_valid_T_4; // @[Arbiter.scala:96:24]
assign anonOut_a_valid = out_0_a_valid; // @[Xbar.scala:216:19]
wire [2:0] _out_0_a_bits_WIRE_opcode; // @[Mux.scala:30:73]
assign anonOut_a_bits_opcode = out_0_a_bits_opcode; // @[Xbar.scala:216:19]
wire [2:0] _out_0_a_bits_WIRE_param; // @[Mux.scala:30:73]
assign anonOut_a_bits_param = out_0_a_bits_param; // @[Xbar.scala:216:19]
wire [3:0] _out_0_a_bits_WIRE_size; // @[Mux.scala:30:73]
assign anonOut_a_bits_size = out_0_a_bits_size; // @[Xbar.scala:216:19]
wire [4:0] _out_0_a_bits_WIRE_source; // @[Mux.scala:30:73]
assign anonOut_a_bits_source = out_0_a_bits_source; // @[Xbar.scala:216:19]
wire [31:0] _out_0_a_bits_WIRE_address; // @[Mux.scala:30:73]
assign anonOut_a_bits_address = out_0_a_bits_address; // @[Xbar.scala:216:19]
wire [15:0] _out_0_a_bits_WIRE_mask; // @[Mux.scala:30:73]
assign anonOut_a_bits_mask = out_0_a_bits_mask; // @[Xbar.scala:216:19]
wire [127:0] _out_0_a_bits_WIRE_data; // @[Mux.scala:30:73]
assign anonOut_a_bits_data = out_0_a_bits_data; // @[Xbar.scala:216:19]
wire _out_0_a_bits_WIRE_corrupt; // @[Mux.scala:30:73]
assign anonOut_a_bits_corrupt = out_0_a_bits_corrupt; // @[Xbar.scala:216:19]
wire _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73]
assign anonOut_d_ready = out_0_d_ready; // @[Xbar.scala:216:19]
assign portsDIO_filtered_0_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_opcode = out_0_d_bits_opcode; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_param = out_0_d_bits_param; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_size = out_0_d_bits_size; // @[Xbar.scala:216:19, :352:24]
wire [4:0] _requestDOI_uncommonBits_T = out_0_d_bits_source; // @[Xbar.scala:216:19]
wire [4:0] _requestDOI_uncommonBits_T_1 = out_0_d_bits_source; // @[Xbar.scala:216:19]
assign portsDIO_filtered_0_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_source = out_0_d_bits_source; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_sink = out_0_d_bits_sink; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_denied = out_0_d_bits_denied; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_data = out_0_d_bits_data; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_0_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign portsDIO_filtered_1_bits_corrupt = out_0_d_bits_corrupt; // @[Xbar.scala:216:19, :352:24]
assign out_0_d_bits_sink = _out_0_d_bits_sink_T; // @[Xbar.scala:216:19, :251:53]
wire [32:0] _requestAIO_T_1 = {1'h0, _requestAIO_T}; // @[Parameters.scala:137:{31,41}]
wire [32:0] _requestAIO_T_6 = {1'h0, _requestAIO_T_5}; // @[Parameters.scala:137:{31,41}]
wire [3:0] requestDOI_uncommonBits = _requestDOI_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T = out_0_d_bits_source[4]; // @[Xbar.scala:216:19]
wire _requestDOI_T_5 = out_0_d_bits_source[4]; // @[Xbar.scala:216:19]
wire _requestDOI_T_1 = _requestDOI_T; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_3 = _requestDOI_T_1; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_0 = _requestDOI_T_3; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_0_valid_T = requestDOI_0_0; // @[Xbar.scala:355:54]
wire [3:0] requestDOI_uncommonBits_1 = _requestDOI_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}]
wire _requestDOI_T_6 = ~_requestDOI_T_5; // @[Parameters.scala:54:{10,32}]
wire _requestDOI_T_8 = _requestDOI_T_6; // @[Parameters.scala:54:{32,67}]
wire requestDOI_0_1 = _requestDOI_T_8; // @[Parameters.scala:54:67, :56:48]
wire _portsDIO_filtered_1_valid_T = requestDOI_0_1; // @[Xbar.scala:355:54]
wire [26:0] _beatsAI_decode_T = 27'hFFF << in_0_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_1 = _beatsAI_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_2 = ~_beatsAI_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] beatsAI_decode = _beatsAI_decode_T_2[11:4]; // @[package.scala:243:46]
wire _beatsAI_opdata_T = in_0_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata = ~_beatsAI_opdata_T; // @[Edges.scala:92:{28,37}]
wire [7:0] beatsAI_0 = beatsAI_opdata ? beatsAI_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsAI_decode_T_3 = 27'hFFF << in_1_a_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsAI_decode_T_4 = _beatsAI_decode_T_3[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsAI_decode_T_5 = ~_beatsAI_decode_T_4; // @[package.scala:243:{46,76}]
wire [7:0] beatsAI_decode_1 = _beatsAI_decode_T_5[11:4]; // @[package.scala:243:46]
wire _beatsAI_opdata_T_1 = in_1_a_bits_opcode[2]; // @[Xbar.scala:159:18]
wire beatsAI_opdata_1 = ~_beatsAI_opdata_T_1; // @[Edges.scala:92:{28,37}]
wire [7:0] beatsAI_1 = beatsAI_opdata_1 ? beatsAI_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14]
wire [26:0] _beatsDO_decode_T = 27'hFFF << out_0_d_bits_size; // @[package.scala:243:71]
wire [11:0] _beatsDO_decode_T_1 = _beatsDO_decode_T[11:0]; // @[package.scala:243:{71,76}]
wire [11:0] _beatsDO_decode_T_2 = ~_beatsDO_decode_T_1; // @[package.scala:243:{46,76}]
wire [7:0] beatsDO_decode = _beatsDO_decode_T_2[11:4]; // @[package.scala:243:46]
wire beatsDO_opdata = out_0_d_bits_opcode[0]; // @[Xbar.scala:216:19]
wire [7:0] beatsDO_0 = beatsDO_opdata ? beatsDO_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14]
wire _filtered_0_ready_T; // @[Arbiter.scala:94:31]
assign in_0_a_ready = portsAOI_filtered_0_ready; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
assign portsAOI_filtered_0_valid = _portsAOI_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _filtered_0_ready_T_1; // @[Arbiter.scala:94:31]
assign in_1_a_ready = portsAOI_filtered_1_0_ready; // @[Xbar.scala:159:18, :352:24]
wire portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
assign portsAOI_filtered_1_0_valid = _portsAOI_filtered_0_valid_T_3; // @[Xbar.scala:352:24, :355:40]
wire _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:355:40]
assign in_0_d_valid = portsDIO_filtered_0_valid; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_opcode = portsDIO_filtered_0_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_param = portsDIO_filtered_0_bits_param; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_size = portsDIO_filtered_0_bits_size; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_source = portsDIO_filtered_0_bits_source; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_sink = portsDIO_filtered_0_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_denied = portsDIO_filtered_0_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_data = portsDIO_filtered_0_bits_data; // @[Xbar.scala:159:18, :352:24]
assign in_0_d_bits_corrupt = portsDIO_filtered_0_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
wire _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:355:40]
assign in_1_d_valid = portsDIO_filtered_1_valid; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_opcode = portsDIO_filtered_1_bits_opcode; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_param = portsDIO_filtered_1_bits_param; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_size = portsDIO_filtered_1_bits_size; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_source = portsDIO_filtered_1_bits_source; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_sink = portsDIO_filtered_1_bits_sink; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_denied = portsDIO_filtered_1_bits_denied; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_data = portsDIO_filtered_1_bits_data; // @[Xbar.scala:159:18, :352:24]
assign in_1_d_bits_corrupt = portsDIO_filtered_1_bits_corrupt; // @[Xbar.scala:159:18, :352:24]
assign _portsDIO_filtered_0_valid_T_1 = out_0_d_valid & _portsDIO_filtered_0_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_0_valid = _portsDIO_filtered_0_valid_T_1; // @[Xbar.scala:352:24, :355:40]
assign _portsDIO_filtered_1_valid_T_1 = out_0_d_valid & _portsDIO_filtered_1_valid_T; // @[Xbar.scala:216:19, :355:{40,54}]
assign portsDIO_filtered_1_valid = _portsDIO_filtered_1_valid_T_1; // @[Xbar.scala:352:24, :355:40]
wire _portsDIO_out_0_d_ready_T = requestDOI_0_0 & portsDIO_filtered_0_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_1 = requestDOI_0_1 & portsDIO_filtered_1_ready; // @[Mux.scala:30:73]
wire _portsDIO_out_0_d_ready_T_2 = _portsDIO_out_0_d_ready_T | _portsDIO_out_0_d_ready_T_1; // @[Mux.scala:30:73]
assign _portsDIO_out_0_d_ready_WIRE = _portsDIO_out_0_d_ready_T_2; // @[Mux.scala:30:73]
assign out_0_d_ready = _portsDIO_out_0_d_ready_WIRE; // @[Mux.scala:30:73]
reg [7:0] beatsLeft; // @[Arbiter.scala:60:30]
wire idle = beatsLeft == 8'h0; // @[Arbiter.scala:60:30, :61:28]
wire latch = idle & out_0_a_ready; // @[Xbar.scala:216:19]
wire [1:0] _readys_T = {portsAOI_filtered_1_0_valid, portsAOI_filtered_0_valid}; // @[Xbar.scala:352:24]
wire [1:0] readys_valid = _readys_T; // @[Arbiter.scala:21:23, :68:51]
wire _readys_T_1 = readys_valid == _readys_T; // @[Arbiter.scala:21:23, :22:19, :68:51]
wire _readys_T_3 = ~_readys_T_2; // @[Arbiter.scala:22:12]
wire _readys_T_4 = ~_readys_T_1; // @[Arbiter.scala:22:{12,19}]
reg [1:0] readys_mask; // @[Arbiter.scala:23:23]
wire [1:0] _readys_filter_T = ~readys_mask; // @[Arbiter.scala:23:23, :24:30]
wire [1:0] _readys_filter_T_1 = readys_valid & _readys_filter_T; // @[Arbiter.scala:21:23, :24:{28,30}]
wire [3:0] readys_filter = {_readys_filter_T_1, readys_valid}; // @[Arbiter.scala:21:23, :24:{21,28}]
wire [2:0] _readys_unready_T = readys_filter[3:1]; // @[package.scala:262:48]
wire [3:0] _readys_unready_T_1 = {readys_filter[3], readys_filter[2:0] | _readys_unready_T}; // @[package.scala:262:{43,48}]
wire [3:0] _readys_unready_T_2 = _readys_unready_T_1; // @[package.scala:262:43, :263:17]
wire [2:0] _readys_unready_T_3 = _readys_unready_T_2[3:1]; // @[package.scala:263:17]
wire [3:0] _readys_unready_T_4 = {readys_mask, 2'h0}; // @[Arbiter.scala:23:23, :25:66]
wire [3:0] readys_unready = {1'h0, _readys_unready_T_3} | _readys_unready_T_4; // @[Arbiter.scala:25:{52,58,66}]
wire [1:0] _readys_readys_T = readys_unready[3:2]; // @[Arbiter.scala:25:58, :26:29]
wire [1:0] _readys_readys_T_1 = readys_unready[1:0]; // @[Arbiter.scala:25:58, :26:48]
wire [1:0] _readys_readys_T_2 = _readys_readys_T & _readys_readys_T_1; // @[Arbiter.scala:26:{29,39,48}]
wire [1:0] readys_readys = ~_readys_readys_T_2; // @[Arbiter.scala:26:{18,39}]
wire [1:0] _readys_T_7 = readys_readys; // @[Arbiter.scala:26:18, :30:11]
wire _readys_T_5 = |readys_valid; // @[Arbiter.scala:21:23, :27:27]
wire _readys_T_6 = latch & _readys_T_5; // @[Arbiter.scala:27:{18,27}, :62:24]
wire [1:0] _readys_mask_T = readys_readys & readys_valid; // @[Arbiter.scala:21:23, :26:18, :28:29]
wire [2:0] _readys_mask_T_1 = {_readys_mask_T, 1'h0}; // @[package.scala:253:48]
wire [1:0] _readys_mask_T_2 = _readys_mask_T_1[1:0]; // @[package.scala:253:{48,53}]
wire [1:0] _readys_mask_T_3 = _readys_mask_T | _readys_mask_T_2; // @[package.scala:253:{43,53}]
wire [1:0] _readys_mask_T_4 = _readys_mask_T_3; // @[package.scala:253:43, :254:17]
wire _readys_T_8 = _readys_T_7[0]; // @[Arbiter.scala:30:11, :68:76]
wire readys_0 = _readys_T_8; // @[Arbiter.scala:68:{27,76}]
wire _readys_T_9 = _readys_T_7[1]; // @[Arbiter.scala:30:11, :68:76]
wire readys_1 = _readys_T_9; // @[Arbiter.scala:68:{27,76}]
wire _winner_T = readys_0 & portsAOI_filtered_0_valid; // @[Xbar.scala:352:24]
wire winner_0 = _winner_T; // @[Arbiter.scala:71:{27,69}]
wire _winner_T_1 = readys_1 & portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24]
wire winner_1 = _winner_T_1; // @[Arbiter.scala:71:{27,69}]
wire prefixOR_1 = winner_0; // @[Arbiter.scala:71:27, :76:48]
wire _prefixOR_T = prefixOR_1 | winner_1; // @[Arbiter.scala:71:27, :76:48]
wire _out_0_a_valid_T = portsAOI_filtered_0_valid | portsAOI_filtered_1_0_valid; // @[Xbar.scala:352:24] |
Generate the Verilog code corresponding to this FIRRTL code module PE_495 :
input clock : Clock
input reset : Reset
output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>}
inst mac_unit of MacUnit_239
connect mac_unit.clock, clock
connect mac_unit.reset, reset
reg c1 : SInt<32>, clock
reg c2 : SInt<32>, clock
connect io.out_a, io.in_a
connect io.out_control.dataflow, io.in_control.dataflow
connect io.out_control.propagate, io.in_control.propagate
connect io.out_control.shift, io.in_control.shift
connect io.out_id, io.in_id
connect io.out_last, io.in_last
connect io.out_valid, io.in_valid
connect mac_unit.io.in_a, io.in_a
reg last_s : UInt<1>, clock
when io.in_valid :
connect last_s, io.in_control.propagate
node flip = neq(last_s, io.in_control.propagate)
node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0))
connect io.bad_dataflow, UInt<1>(0h0)
node _T = eq(io.in_control.dataflow, UInt<1>(0h0))
node _T_1 = and(UInt<1>(0h1), _T)
node _T_2 = or(UInt<1>(0h0), _T_1)
when _T_2 :
node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_3 :
node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1)
node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2)
node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0)
node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4)
node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_1 = asUInt(c1)
node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1)
node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3)
node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1))
node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1)
node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6)
node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7)
node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0))
node _io_out_c_ones_digit_T = dshr(c1, shift_offset)
node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0)
node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit)
node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T)
node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0)
node _io_out_c_T = dshr(c1, shift_offset)
node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1)
node _io_out_c_T_3 = tail(_io_out_c_T_2, 1)
node _io_out_c_T_4 = asSInt(_io_out_c_T_3)
node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4)
node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7)
node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0)
node _io_out_c_T_10 = asSInt(_io_out_c_T_9)
connect io.out_c, _io_out_c_T_10
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE : SInt<8>
node _mac_unit_io_in_b_T = asUInt(io.in_b)
node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T)
connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE
connect mac_unit.io.in_c, c2
connect c2, mac_unit.io.out_d
node c1_sign = bits(io.in_d, 19, 19)
node c1_lo_lo_hi = cat(c1_sign, c1_sign)
node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign)
node c1_lo_hi_hi = cat(c1_sign, c1_sign)
node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign)
node c1_lo = cat(c1_lo_hi, c1_lo_lo)
node c1_hi_lo_hi = cat(c1_sign, c1_sign)
node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign)
node c1_hi_hi_hi = cat(c1_sign, c1_sign)
node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign)
node c1_hi = cat(c1_hi_hi, c1_hi_lo)
node _c1_T = cat(c1_hi, c1_lo)
node c1_lo_1 = asUInt(io.in_d)
node _c1_T_1 = cat(_c1_T, c1_lo_1)
wire _c1_WIRE : SInt<32>
node _c1_T_2 = asSInt(_c1_T_1)
connect _c1_WIRE, _c1_T_2
connect c1, _c1_WIRE
else :
node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0))
node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1)
node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7)
node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0)
node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9)
node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_10 = asUInt(c2)
node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1))
node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1)
node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12)
node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1))
node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1)
node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15)
node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16)
node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0))
node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset)
node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0)
node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1)
node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2)
node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0)
node _io_out_c_T_11 = dshr(c2, shift_offset)
node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0)))
node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12)
node _io_out_c_T_14 = tail(_io_out_c_T_13, 1)
node _io_out_c_T_15 = asSInt(_io_out_c_T_14)
node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff)))
node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000)))
node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15)
node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18)
node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0)
node _io_out_c_T_21 = asSInt(_io_out_c_T_20)
connect io.out_c, _io_out_c_T_21
connect io.out_b, io.in_b
wire _mac_unit_io_in_b_WIRE_1 : SInt<8>
node _mac_unit_io_in_b_T_2 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2)
connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1
connect mac_unit.io.in_c, c1
connect c1, mac_unit.io.out_d
node c2_sign = bits(io.in_d, 19, 19)
node c2_lo_lo_hi = cat(c2_sign, c2_sign)
node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign)
node c2_lo_hi_hi = cat(c2_sign, c2_sign)
node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign)
node c2_lo = cat(c2_lo_hi, c2_lo_lo)
node c2_hi_lo_hi = cat(c2_sign, c2_sign)
node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign)
node c2_hi_hi_hi = cat(c2_sign, c2_sign)
node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign)
node c2_hi = cat(c2_hi_hi, c2_hi_lo)
node _c2_T = cat(c2_hi, c2_lo)
node c2_lo_1 = asUInt(io.in_d)
node _c2_T_1 = cat(_c2_T, c2_lo_1)
wire _c2_WIRE : SInt<32>
node _c2_T_2 = asSInt(_c2_T_1)
connect _c2_WIRE, _c2_T_2
connect c2, _c2_WIRE
else :
node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1))
node _T_5 = and(UInt<1>(0h1), _T_4)
node _T_6 = or(UInt<1>(0h0), _T_5)
when _T_6 :
node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1))
when _T_7 :
connect io.out_c, c1
wire _mac_unit_io_in_b_WIRE_2 : SInt<8>
node _mac_unit_io_in_b_T_4 = asUInt(c2)
node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4)
connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c1, io.in_d
else :
connect io.out_c, c2
wire _mac_unit_io_in_b_WIRE_3 : SInt<8>
node _mac_unit_io_in_b_T_6 = asUInt(c1)
node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6)
connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3
connect mac_unit.io.in_c, io.in_b
connect io.out_b, mac_unit.io.out_d
connect c2, io.in_d
else :
connect io.bad_dataflow, UInt<1>(0h1)
invalidate io.out_c
invalidate io.out_b
wire _mac_unit_io_in_b_WIRE_4 : SInt<8>
node _mac_unit_io_in_b_T_8 = asUInt(io.in_b)
node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8)
connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9
connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4
connect mac_unit.io.in_c, c2
node _T_8 = eq(io.in_valid, UInt<1>(0h0))
when _T_8 :
connect c1, c1
connect c2, c2
invalidate mac_unit.io.in_b
invalidate mac_unit.io.in_c | module PE_495( // @[PE.scala:31:7]
input clock, // @[PE.scala:31:7]
input reset, // @[PE.scala:31:7]
input [7:0] io_in_a, // @[PE.scala:35:14]
input [19:0] io_in_b, // @[PE.scala:35:14]
input [19:0] io_in_d, // @[PE.scala:35:14]
output [7:0] io_out_a, // @[PE.scala:35:14]
output [19:0] io_out_b, // @[PE.scala:35:14]
output [19:0] io_out_c, // @[PE.scala:35:14]
input io_in_control_dataflow, // @[PE.scala:35:14]
input io_in_control_propagate, // @[PE.scala:35:14]
input [4:0] io_in_control_shift, // @[PE.scala:35:14]
output io_out_control_dataflow, // @[PE.scala:35:14]
output io_out_control_propagate, // @[PE.scala:35:14]
output [4:0] io_out_control_shift, // @[PE.scala:35:14]
input [2:0] io_in_id, // @[PE.scala:35:14]
output [2:0] io_out_id, // @[PE.scala:35:14]
input io_in_last, // @[PE.scala:35:14]
output io_out_last, // @[PE.scala:35:14]
input io_in_valid, // @[PE.scala:35:14]
output io_out_valid, // @[PE.scala:35:14]
output io_bad_dataflow // @[PE.scala:35:14]
);
wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24]
wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7]
wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7]
wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7]
wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7]
wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7]
wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7]
wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7]
wire io_in_last_0 = io_in_last; // @[PE.scala:31:7]
wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7]
wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7]
wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7]
wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37]
wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37]
wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35]
wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7]
wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7]
wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7]
wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7]
wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7]
wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7]
wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7]
wire [19:0] io_out_b_0; // @[PE.scala:31:7]
wire [19:0] io_out_c_0; // @[PE.scala:31:7]
reg [31:0] c1; // @[PE.scala:70:15]
wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15]
wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38]
reg [31:0] c2; // @[PE.scala:71:15]
wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15]
wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38]
reg last_s; // @[PE.scala:89:25]
wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21]
wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25]
wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25]
wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32]
wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32]
assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32]
wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25]
wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53]
assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53]
wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66]
assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66]
wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15]
wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}]
wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25]
wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27]
wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27]
assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27]
wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25]
wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15]
wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15]
assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37]
wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37]
wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7]
wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18]
wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61]
wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53]
wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15]
wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50]
wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}]
wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66]
wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}]
wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}]
wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81]
wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}]
wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}]
wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}]
wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15]
wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30]
assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30]
wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15]
assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15]
wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30]
wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38]
wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}]
wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}]
wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33]
wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}]
wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28]
wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28]
wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33]
wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60]
wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16]
wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16]
wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}]
wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37]
wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37]
wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18]
wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18]
assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18]
wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18]
wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18]
wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18]
wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18]
wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}]
wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}]
wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61]
wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38]
wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38]
wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38]
wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38]
assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16]
assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101]
wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35]
wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35]
wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10]
wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10]
always @(posedge clock) begin // @[PE.scala:31:7]
if (io_in_valid_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0) begin // @[PE.scala:31:7]
if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10]
c1 <= _GEN_7; // @[PE.scala:70:15, :124:10]
if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30]
end
else // @[PE.scala:71:15, :118:101, :119:30]
c2 <= _GEN_7; // @[PE.scala:71:15, :124:10]
end
else begin // @[PE.scala:31:7]
c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10]
c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10]
end
last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25]
end
always @(posedge)
MacUnit_239 mac_unit ( // @[PE.scala:64:24]
.clock (clock),
.reset (reset),
.io_in_a (io_in_a_0), // @[PE.scala:31:7]
.io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}]
.io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24]
.io_out_d (_mac_unit_io_out_d)
); // @[PE.scala:64:24]
assign io_out_a = io_out_a_0; // @[PE.scala:31:7]
assign io_out_b = io_out_b_0; // @[PE.scala:31:7]
assign io_out_c = io_out_c_0; // @[PE.scala:31:7]
assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7]
assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7]
assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7]
assign io_out_id = io_out_id_0; // @[PE.scala:31:7]
assign io_out_last = io_out_last_0; // @[PE.scala:31:7]
assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7]
assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module TLCToNoC :
input clock : Clock
input reset : Reset
output io : { flip protocol : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flit : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<65>, egress_id : UInt}}}
inst q of Queue1_TLBundleC_a32d64s6k5z4c
connect q.clock, clock
connect q.reset, reset
wire has_body : UInt<1>
node _head_T = and(q.io.deq.ready, q.io.deq.valid)
node _head_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size)
node _head_beats1_decode_T_1 = bits(_head_beats1_decode_T, 11, 0)
node _head_beats1_decode_T_2 = not(_head_beats1_decode_T_1)
node head_beats1_decode = shr(_head_beats1_decode_T_2, 3)
node head_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0)
node head_beats1 = mux(UInt<1>(0h0), head_beats1_decode, UInt<1>(0h0))
regreset head_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _head_counter1_T = sub(head_counter, UInt<1>(0h1))
node head_counter1 = tail(_head_counter1_T, 1)
node head = eq(head_counter, UInt<1>(0h0))
node _head_last_T = eq(head_counter, UInt<1>(0h1))
node _head_last_T_1 = eq(head_beats1, UInt<1>(0h0))
node head_last = or(_head_last_T, _head_last_T_1)
node head_done = and(head_last, _head_T)
node _head_count_T = not(head_counter1)
node head_count = and(head_beats1, _head_count_T)
when _head_T :
node _head_counter_T = mux(head, head_beats1, head_counter1)
connect head_counter, _head_counter_T
node _tail_T = and(q.io.deq.ready, q.io.deq.valid)
node _tail_beats1_decode_T = dshl(UInt<12>(0hfff), q.io.deq.bits.size)
node _tail_beats1_decode_T_1 = bits(_tail_beats1_decode_T, 11, 0)
node _tail_beats1_decode_T_2 = not(_tail_beats1_decode_T_1)
node tail_beats1_decode = shr(_tail_beats1_decode_T_2, 3)
node tail_beats1_opdata = bits(q.io.deq.bits.opcode, 0, 0)
node tail_beats1 = mux(UInt<1>(0h0), tail_beats1_decode, UInt<1>(0h0))
regreset tail_counter : UInt<9>, clock, reset, UInt<9>(0h0)
node _tail_counter1_T = sub(tail_counter, UInt<1>(0h1))
node tail_counter1 = tail(_tail_counter1_T, 1)
node tail_first = eq(tail_counter, UInt<1>(0h0))
node _tail_last_T = eq(tail_counter, UInt<1>(0h1))
node _tail_last_T_1 = eq(tail_beats1, UInt<1>(0h0))
node tail = or(_tail_last_T, _tail_last_T_1)
node tail_done = and(tail, _tail_T)
node _tail_count_T = not(tail_counter1)
node tail_count = and(tail_beats1, _tail_count_T)
when _tail_T :
node _tail_counter_T = mux(tail_first, tail_beats1, tail_counter1)
connect tail_counter, _tail_counter_T
node body = cat(q.io.deq.bits.data, q.io.deq.bits.corrupt)
node const_lo = cat(q.io.deq.bits.source, q.io.deq.bits.address)
node const_hi_hi = cat(q.io.deq.bits.opcode, q.io.deq.bits.param)
node const_hi = cat(const_hi_hi, q.io.deq.bits.size)
node const = cat(const_hi, const_lo)
regreset is_body : UInt<1>, clock, reset, UInt<1>(0h0)
connect io.flit.valid, q.io.deq.valid
node _q_io_deq_ready_T = eq(has_body, UInt<1>(0h0))
node _q_io_deq_ready_T_1 = or(is_body, _q_io_deq_ready_T)
node _q_io_deq_ready_T_2 = and(io.flit.ready, _q_io_deq_ready_T_1)
connect q.io.deq.ready, _q_io_deq_ready_T_2
node _io_flit_bits_head_T = eq(is_body, UInt<1>(0h0))
node _io_flit_bits_head_T_1 = and(head, _io_flit_bits_head_T)
connect io.flit.bits.head, _io_flit_bits_head_T_1
node _io_flit_bits_tail_T = eq(has_body, UInt<1>(0h0))
node _io_flit_bits_tail_T_1 = or(is_body, _io_flit_bits_tail_T)
node _io_flit_bits_tail_T_2 = and(tail, _io_flit_bits_tail_T_1)
connect io.flit.bits.tail, _io_flit_bits_tail_T_2
node _io_flit_bits_egress_id_requestOH_T = xor(q.io.deq.bits.address, UInt<1>(0h0))
node _io_flit_bits_egress_id_requestOH_T_1 = cvt(_io_flit_bits_egress_id_requestOH_T)
node _io_flit_bits_egress_id_requestOH_T_2 = and(_io_flit_bits_egress_id_requestOH_T_1, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_3 = asSInt(_io_flit_bits_egress_id_requestOH_T_2)
node _io_flit_bits_egress_id_requestOH_T_4 = eq(_io_flit_bits_egress_id_requestOH_T_3, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_5 = or(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_4)
node io_flit_bits_egress_id_requestOH_0 = and(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_5)
node _io_flit_bits_egress_id_requestOH_T_6 = xor(q.io.deq.bits.address, UInt<1>(0h0))
node _io_flit_bits_egress_id_requestOH_T_7 = cvt(_io_flit_bits_egress_id_requestOH_T_6)
node _io_flit_bits_egress_id_requestOH_T_8 = and(_io_flit_bits_egress_id_requestOH_T_7, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_9 = asSInt(_io_flit_bits_egress_id_requestOH_T_8)
node _io_flit_bits_egress_id_requestOH_T_10 = eq(_io_flit_bits_egress_id_requestOH_T_9, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_11 = or(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_10)
node io_flit_bits_egress_id_requestOH_1 = and(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_11)
node _io_flit_bits_egress_id_requestOH_T_12 = xor(q.io.deq.bits.address, UInt<1>(0h0))
node _io_flit_bits_egress_id_requestOH_T_13 = cvt(_io_flit_bits_egress_id_requestOH_T_12)
node _io_flit_bits_egress_id_requestOH_T_14 = and(_io_flit_bits_egress_id_requestOH_T_13, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_15 = asSInt(_io_flit_bits_egress_id_requestOH_T_14)
node _io_flit_bits_egress_id_requestOH_T_16 = eq(_io_flit_bits_egress_id_requestOH_T_15, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_17 = or(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_16)
node io_flit_bits_egress_id_requestOH_2 = and(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_17)
node _io_flit_bits_egress_id_requestOH_T_18 = xor(q.io.deq.bits.address, UInt<1>(0h0))
node _io_flit_bits_egress_id_requestOH_T_19 = cvt(_io_flit_bits_egress_id_requestOH_T_18)
node _io_flit_bits_egress_id_requestOH_T_20 = and(_io_flit_bits_egress_id_requestOH_T_19, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_21 = asSInt(_io_flit_bits_egress_id_requestOH_T_20)
node _io_flit_bits_egress_id_requestOH_T_22 = eq(_io_flit_bits_egress_id_requestOH_T_21, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_23 = or(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_22)
node io_flit_bits_egress_id_requestOH_3 = and(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_23)
node _io_flit_bits_egress_id_requestOH_T_24 = xor(q.io.deq.bits.address, UInt<1>(0h0))
node _io_flit_bits_egress_id_requestOH_T_25 = cvt(_io_flit_bits_egress_id_requestOH_T_24)
node _io_flit_bits_egress_id_requestOH_T_26 = and(_io_flit_bits_egress_id_requestOH_T_25, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_27 = asSInt(_io_flit_bits_egress_id_requestOH_T_26)
node _io_flit_bits_egress_id_requestOH_T_28 = eq(_io_flit_bits_egress_id_requestOH_T_27, asSInt(UInt<1>(0h0)))
node _io_flit_bits_egress_id_requestOH_T_29 = or(UInt<1>(0h1), _io_flit_bits_egress_id_requestOH_T_28)
node io_flit_bits_egress_id_requestOH_4 = and(UInt<1>(0h0), _io_flit_bits_egress_id_requestOH_T_29)
node _io_flit_bits_egress_id_T = mux(io_flit_bits_egress_id_requestOH_0, UInt<4>(0hb), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_1 = mux(io_flit_bits_egress_id_requestOH_1, UInt<4>(0he), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_2 = mux(io_flit_bits_egress_id_requestOH_2, UInt<5>(0h11), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_3 = mux(io_flit_bits_egress_id_requestOH_3, UInt<5>(0h14), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_4 = mux(io_flit_bits_egress_id_requestOH_4, UInt<5>(0h17), UInt<1>(0h0))
node _io_flit_bits_egress_id_T_5 = or(_io_flit_bits_egress_id_T, _io_flit_bits_egress_id_T_1)
node _io_flit_bits_egress_id_T_6 = or(_io_flit_bits_egress_id_T_5, _io_flit_bits_egress_id_T_2)
node _io_flit_bits_egress_id_T_7 = or(_io_flit_bits_egress_id_T_6, _io_flit_bits_egress_id_T_3)
node _io_flit_bits_egress_id_T_8 = or(_io_flit_bits_egress_id_T_7, _io_flit_bits_egress_id_T_4)
wire _io_flit_bits_egress_id_WIRE : UInt<5>
connect _io_flit_bits_egress_id_WIRE, _io_flit_bits_egress_id_T_8
connect io.flit.bits.egress_id, _io_flit_bits_egress_id_WIRE
node _io_flit_bits_payload_T = mux(is_body, body, const)
connect io.flit.bits.payload, _io_flit_bits_payload_T
node _T = and(io.flit.ready, io.flit.valid)
node _T_1 = and(_T, io.flit.bits.head)
when _T_1 :
connect is_body, UInt<1>(0h1)
node _T_2 = and(io.flit.ready, io.flit.valid)
node _T_3 = and(_T_2, io.flit.bits.tail)
when _T_3 :
connect is_body, UInt<1>(0h0)
node has_body_opdata = bits(q.io.deq.bits.opcode, 0, 0)
connect has_body, UInt<1>(0h0)
connect q.io.enq, io.protocol
node _q_io_enq_bits_source_T = or(io.protocol.bits.source, UInt<1>(0h0))
connect q.io.enq.bits.source, _q_io_enq_bits_source_T | module TLCToNoC( // @[TilelinkAdapters.scala:151:7]
input clock, // @[TilelinkAdapters.scala:151:7]
input reset, // @[TilelinkAdapters.scala:151:7]
output io_flit_valid // @[TilelinkAdapters.scala:19:14]
);
Queue1_TLBundleC_a32d64s6k5z4c q ( // @[TilelinkAdapters.scala:26:17]
.clock (clock),
.reset (reset),
.io_enq_ready (/* unused */),
.io_enq_valid (1'h0), // @[Decoupled.scala:51:35]
.io_enq_bits_opcode (3'h0), // @[TilelinkAdapters.scala:19:14, :26:17]
.io_enq_bits_param (3'h0), // @[TilelinkAdapters.scala:19:14, :26:17]
.io_enq_bits_size (4'h0), // @[TilelinkAdapters.scala:19:14, :26:17]
.io_enq_bits_source (6'h0), // @[TilelinkAdapters.scala:19:14, :26:17]
.io_enq_bits_address (32'h0), // @[TilelinkAdapters.scala:19:14, :26:17]
.io_enq_bits_data (64'h0), // @[TilelinkAdapters.scala:19:14, :26:17]
.io_enq_bits_corrupt (1'h0), // @[Decoupled.scala:51:35]
.io_deq_ready (1'h0), // @[Decoupled.scala:51:35]
.io_deq_valid (io_flit_valid),
.io_deq_bits_opcode (/* unused */),
.io_deq_bits_param (/* unused */),
.io_deq_bits_size (/* unused */),
.io_deq_bits_source (/* unused */),
.io_deq_bits_address (/* unused */),
.io_deq_bits_data (/* unused */),
.io_deq_bits_corrupt (/* unused */)
); // @[TilelinkAdapters.scala:26:17]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_364 :
input clock : Clock
input reset : AsyncReset
output io : { flip d : UInt<1>, q : UInt<1>}
regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0)
regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0)
node _sync_2_T = bits(io.d, 0, 0)
connect sync_2, _sync_2_T
connect sync_0, sync_1
connect sync_1, sync_2
connect io.q, sync_0 | module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_364( // @[SynchronizerReg.scala:68:19]
input clock, // @[SynchronizerReg.scala:68:19]
input reset, // @[SynchronizerReg.scala:68:19]
input io_d, // @[ShiftReg.scala:36:14]
output io_q // @[ShiftReg.scala:36:14]
);
wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19]
wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19]
wire io_q_0; // @[SynchronizerReg.scala:68:19]
reg sync_0; // @[SynchronizerReg.scala:51:87]
assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19]
reg sync_1; // @[SynchronizerReg.scala:51:87]
reg sync_2; // @[SynchronizerReg.scala:51:87]
always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19]
if (reset) begin // @[SynchronizerReg.scala:68:19]
sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87]
sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87]
end
else begin // @[SynchronizerReg.scala:68:19]
sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87]
sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87]
sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22]
end
always @(posedge, posedge) |
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_294 :
input clock : Clock
input reset : Reset
output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}}
connect io.y, io.x | module OptimizationBarrier_TLBEntryData_294( // @[package.scala:267:30]
input clock, // @[package.scala:267:30]
input reset, // @[package.scala:267:30]
input [19:0] io_x_ppn, // @[package.scala:268:18]
input io_x_u, // @[package.scala:268:18]
input io_x_g, // @[package.scala:268:18]
input io_x_ae_ptw, // @[package.scala:268:18]
input io_x_ae_final, // @[package.scala:268:18]
input io_x_ae_stage2, // @[package.scala:268:18]
input io_x_pf, // @[package.scala:268:18]
input io_x_gf, // @[package.scala:268:18]
input io_x_sw, // @[package.scala:268:18]
input io_x_sx, // @[package.scala:268:18]
input io_x_sr, // @[package.scala:268:18]
input io_x_hw, // @[package.scala:268:18]
input io_x_hx, // @[package.scala:268:18]
input io_x_hr, // @[package.scala:268:18]
input io_x_pw, // @[package.scala:268:18]
input io_x_px, // @[package.scala:268:18]
input io_x_pr, // @[package.scala:268:18]
input io_x_ppp, // @[package.scala:268:18]
input io_x_pal, // @[package.scala:268:18]
input io_x_paa, // @[package.scala:268:18]
input io_x_eff, // @[package.scala:268:18]
input io_x_c, // @[package.scala:268:18]
input io_x_fragmented_superpage, // @[package.scala:268:18]
output [19:0] io_y_ppn // @[package.scala:268:18]
);
wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30]
wire io_x_u_0 = io_x_u; // @[package.scala:267:30]
wire io_x_g_0 = io_x_g; // @[package.scala:267:30]
wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30]
wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30]
wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30]
wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30]
wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30]
wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30]
wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30]
wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30]
wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30]
wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30]
wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30]
wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30]
wire io_x_px_0 = io_x_px; // @[package.scala:267:30]
wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30]
wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30]
wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30]
wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30]
wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30]
wire io_x_c_0 = io_x_c; // @[package.scala:267:30]
wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30]
wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30]
wire io_y_u = io_x_u_0; // @[package.scala:267:30]
wire io_y_g = io_x_g_0; // @[package.scala:267:30]
wire io_y_ae_ptw = io_x_ae_ptw_0; // @[package.scala:267:30]
wire io_y_ae_final = io_x_ae_final_0; // @[package.scala:267:30]
wire io_y_ae_stage2 = io_x_ae_stage2_0; // @[package.scala:267:30]
wire io_y_pf = io_x_pf_0; // @[package.scala:267:30]
wire io_y_gf = io_x_gf_0; // @[package.scala:267:30]
wire io_y_sw = io_x_sw_0; // @[package.scala:267:30]
wire io_y_sx = io_x_sx_0; // @[package.scala:267:30]
wire io_y_sr = io_x_sr_0; // @[package.scala:267:30]
wire io_y_hw = io_x_hw_0; // @[package.scala:267:30]
wire io_y_hx = io_x_hx_0; // @[package.scala:267:30]
wire io_y_hr = io_x_hr_0; // @[package.scala:267:30]
wire io_y_pw = io_x_pw_0; // @[package.scala:267:30]
wire io_y_px = io_x_px_0; // @[package.scala:267:30]
wire io_y_pr = io_x_pr_0; // @[package.scala:267:30]
wire io_y_ppp = io_x_ppp_0; // @[package.scala:267:30]
wire io_y_pal = io_x_pal_0; // @[package.scala:267:30]
wire io_y_paa = io_x_paa_0; // @[package.scala:267:30]
wire io_y_eff = io_x_eff_0; // @[package.scala:267:30]
wire io_y_c = io_x_c_0; // @[package.scala:267:30]
wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30]
assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_14 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_23
connect io_out_source_extend.clock, clock
connect io_out_source_extend.reset, reset
connect io_out_source_extend.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_extend.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_14( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_23 io_out_source_extend ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module SinkA :
input clock : Clock
input reset : Reset
output io : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}}, flip a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, flip pb_pop : { flip ready : UInt<1>, valid : UInt<1>, bits : { index : UInt<6>, last : UInt<1>}}, pb_beat : { data : UInt<32>, mask : UInt<4>, corrupt : UInt<1>}}
inst putbuffer of ListBuffer_PutBufferAEntry_q40_e40
connect putbuffer.clock, clock
connect putbuffer.reset, reset
regreset lists : UInt<40>, clock, reset, UInt<40>(0h0)
wire lists_set : UInt<40>
connect lists_set, UInt<40>(0h0)
wire lists_clr : UInt<40>
connect lists_clr, UInt<40>(0h0)
node _lists_T = or(lists, lists_set)
node _lists_T_1 = not(lists_clr)
node _lists_T_2 = and(_lists_T, _lists_T_1)
connect lists, _lists_T_2
node _free_T = andr(lists)
node free = eq(_free_T, UInt<1>(0h0))
node _freeOH_T = not(lists)
node _freeOH_T_1 = shl(_freeOH_T, 1)
node _freeOH_T_2 = bits(_freeOH_T_1, 39, 0)
node _freeOH_T_3 = or(_freeOH_T, _freeOH_T_2)
node _freeOH_T_4 = shl(_freeOH_T_3, 2)
node _freeOH_T_5 = bits(_freeOH_T_4, 39, 0)
node _freeOH_T_6 = or(_freeOH_T_3, _freeOH_T_5)
node _freeOH_T_7 = shl(_freeOH_T_6, 4)
node _freeOH_T_8 = bits(_freeOH_T_7, 39, 0)
node _freeOH_T_9 = or(_freeOH_T_6, _freeOH_T_8)
node _freeOH_T_10 = shl(_freeOH_T_9, 8)
node _freeOH_T_11 = bits(_freeOH_T_10, 39, 0)
node _freeOH_T_12 = or(_freeOH_T_9, _freeOH_T_11)
node _freeOH_T_13 = shl(_freeOH_T_12, 16)
node _freeOH_T_14 = bits(_freeOH_T_13, 39, 0)
node _freeOH_T_15 = or(_freeOH_T_12, _freeOH_T_14)
node _freeOH_T_16 = shl(_freeOH_T_15, 32)
node _freeOH_T_17 = bits(_freeOH_T_16, 39, 0)
node _freeOH_T_18 = or(_freeOH_T_15, _freeOH_T_17)
node _freeOH_T_19 = bits(_freeOH_T_18, 39, 0)
node _freeOH_T_20 = shl(_freeOH_T_19, 1)
node _freeOH_T_21 = not(_freeOH_T_20)
node _freeOH_T_22 = not(lists)
node freeOH = and(_freeOH_T_21, _freeOH_T_22)
node freeIdx_hi = bits(freeOH, 40, 32)
node freeIdx_lo = bits(freeOH, 31, 0)
node _freeIdx_T = orr(freeIdx_hi)
node _freeIdx_T_1 = or(freeIdx_hi, freeIdx_lo)
node freeIdx_hi_1 = bits(_freeIdx_T_1, 31, 16)
node freeIdx_lo_1 = bits(_freeIdx_T_1, 15, 0)
node _freeIdx_T_2 = orr(freeIdx_hi_1)
node _freeIdx_T_3 = or(freeIdx_hi_1, freeIdx_lo_1)
node freeIdx_hi_2 = bits(_freeIdx_T_3, 15, 8)
node freeIdx_lo_2 = bits(_freeIdx_T_3, 7, 0)
node _freeIdx_T_4 = orr(freeIdx_hi_2)
node _freeIdx_T_5 = or(freeIdx_hi_2, freeIdx_lo_2)
node freeIdx_hi_3 = bits(_freeIdx_T_5, 7, 4)
node freeIdx_lo_3 = bits(_freeIdx_T_5, 3, 0)
node _freeIdx_T_6 = orr(freeIdx_hi_3)
node _freeIdx_T_7 = or(freeIdx_hi_3, freeIdx_lo_3)
node freeIdx_hi_4 = bits(_freeIdx_T_7, 3, 2)
node freeIdx_lo_4 = bits(_freeIdx_T_7, 1, 0)
node _freeIdx_T_8 = orr(freeIdx_hi_4)
node _freeIdx_T_9 = or(freeIdx_hi_4, freeIdx_lo_4)
node _freeIdx_T_10 = bits(_freeIdx_T_9, 1, 1)
node _freeIdx_T_11 = cat(_freeIdx_T_8, _freeIdx_T_10)
node _freeIdx_T_12 = cat(_freeIdx_T_6, _freeIdx_T_11)
node _freeIdx_T_13 = cat(_freeIdx_T_4, _freeIdx_T_12)
node _freeIdx_T_14 = cat(_freeIdx_T_2, _freeIdx_T_13)
node freeIdx = cat(_freeIdx_T, _freeIdx_T_14)
node _first_T = and(io.a.ready, io.a.valid)
node _first_beats1_decode_T = dshl(UInt<6>(0h3f), io.a.bits.size)
node _first_beats1_decode_T_1 = bits(_first_beats1_decode_T, 5, 0)
node _first_beats1_decode_T_2 = not(_first_beats1_decode_T_1)
node first_beats1_decode = shr(_first_beats1_decode_T_2, 2)
node _first_beats1_opdata_T = bits(io.a.bits.opcode, 2, 2)
node first_beats1_opdata = eq(_first_beats1_opdata_T, UInt<1>(0h0))
node first_beats1 = mux(first_beats1_opdata, first_beats1_decode, UInt<1>(0h0))
regreset first_counter : UInt<4>, clock, reset, UInt<4>(0h0)
node _first_counter1_T = sub(first_counter, UInt<1>(0h1))
node first_counter1 = tail(_first_counter1_T, 1)
node first = eq(first_counter, UInt<1>(0h0))
node _first_last_T = eq(first_counter, UInt<1>(0h1))
node _first_last_T_1 = eq(first_beats1, UInt<1>(0h0))
node first_last = or(_first_last_T, _first_last_T_1)
node first_done = and(first_last, _first_T)
node _first_count_T = not(first_counter1)
node first_count = and(first_beats1, _first_count_T)
when _first_T :
node _first_counter_T = mux(first, first_beats1, first_counter1)
connect first_counter, _first_counter_T
node _hasData_opdata_T = bits(io.a.bits.opcode, 2, 2)
node hasData = eq(_hasData_opdata_T, UInt<1>(0h0))
node _req_block_T = eq(io.req.ready, UInt<1>(0h0))
node req_block = and(first, _req_block_T)
node _buf_block_T = eq(putbuffer.io.push.ready, UInt<1>(0h0))
node buf_block = and(hasData, _buf_block_T)
node _set_block_T = and(hasData, first)
node _set_block_T_1 = eq(free, UInt<1>(0h0))
node set_block = and(_set_block_T, _set_block_T_1)
node _T = and(io.a.valid, req_block)
node _T_1 = and(io.a.valid, buf_block)
node _T_2 = and(io.a.valid, set_block)
node _io_a_ready_T = eq(req_block, UInt<1>(0h0))
node _io_a_ready_T_1 = eq(buf_block, UInt<1>(0h0))
node _io_a_ready_T_2 = and(_io_a_ready_T, _io_a_ready_T_1)
node _io_a_ready_T_3 = eq(set_block, UInt<1>(0h0))
node _io_a_ready_T_4 = and(_io_a_ready_T_2, _io_a_ready_T_3)
connect io.a.ready, _io_a_ready_T_4
node _io_req_valid_T = and(io.a.valid, first)
node _io_req_valid_T_1 = eq(buf_block, UInt<1>(0h0))
node _io_req_valid_T_2 = and(_io_req_valid_T, _io_req_valid_T_1)
node _io_req_valid_T_3 = eq(set_block, UInt<1>(0h0))
node _io_req_valid_T_4 = and(_io_req_valid_T_2, _io_req_valid_T_3)
connect io.req.valid, _io_req_valid_T_4
node _putbuffer_io_push_valid_T = and(io.a.valid, hasData)
node _putbuffer_io_push_valid_T_1 = eq(req_block, UInt<1>(0h0))
node _putbuffer_io_push_valid_T_2 = and(_putbuffer_io_push_valid_T, _putbuffer_io_push_valid_T_1)
node _putbuffer_io_push_valid_T_3 = eq(set_block, UInt<1>(0h0))
node _putbuffer_io_push_valid_T_4 = and(_putbuffer_io_push_valid_T_2, _putbuffer_io_push_valid_T_3)
connect putbuffer.io.push.valid, _putbuffer_io_push_valid_T_4
node _T_3 = and(io.a.valid, first)
node _T_4 = and(_T_3, hasData)
node _T_5 = eq(req_block, UInt<1>(0h0))
node _T_6 = and(_T_4, _T_5)
node _T_7 = eq(buf_block, UInt<1>(0h0))
node _T_8 = and(_T_6, _T_7)
when _T_8 :
connect lists_set, freeOH
node _offset_T = bits(io.a.bits.address, 0, 0)
node _offset_T_1 = bits(io.a.bits.address, 1, 1)
node _offset_T_2 = bits(io.a.bits.address, 2, 2)
node _offset_T_3 = bits(io.a.bits.address, 3, 3)
node _offset_T_4 = bits(io.a.bits.address, 4, 4)
node _offset_T_5 = bits(io.a.bits.address, 5, 5)
node _offset_T_6 = bits(io.a.bits.address, 6, 6)
node _offset_T_7 = bits(io.a.bits.address, 7, 7)
node _offset_T_8 = bits(io.a.bits.address, 8, 8)
node _offset_T_9 = bits(io.a.bits.address, 9, 9)
node _offset_T_10 = bits(io.a.bits.address, 10, 10)
node _offset_T_11 = bits(io.a.bits.address, 11, 11)
node _offset_T_12 = bits(io.a.bits.address, 12, 12)
node _offset_T_13 = bits(io.a.bits.address, 13, 13)
node _offset_T_14 = bits(io.a.bits.address, 14, 14)
node _offset_T_15 = bits(io.a.bits.address, 15, 15)
node _offset_T_16 = bits(io.a.bits.address, 16, 16)
node _offset_T_17 = bits(io.a.bits.address, 17, 17)
node _offset_T_18 = bits(io.a.bits.address, 18, 18)
node _offset_T_19 = bits(io.a.bits.address, 19, 19)
node _offset_T_20 = bits(io.a.bits.address, 20, 20)
node _offset_T_21 = bits(io.a.bits.address, 21, 21)
node _offset_T_22 = bits(io.a.bits.address, 22, 22)
node _offset_T_23 = bits(io.a.bits.address, 23, 23)
node _offset_T_24 = bits(io.a.bits.address, 24, 24)
node _offset_T_25 = bits(io.a.bits.address, 25, 25)
node _offset_T_26 = bits(io.a.bits.address, 26, 26)
node _offset_T_27 = bits(io.a.bits.address, 27, 27)
node _offset_T_28 = bits(io.a.bits.address, 31, 31)
node offset_lo_lo_lo_hi = cat(_offset_T_2, _offset_T_1)
node offset_lo_lo_lo = cat(offset_lo_lo_lo_hi, _offset_T)
node offset_lo_lo_hi_lo = cat(_offset_T_4, _offset_T_3)
node offset_lo_lo_hi_hi = cat(_offset_T_6, _offset_T_5)
node offset_lo_lo_hi = cat(offset_lo_lo_hi_hi, offset_lo_lo_hi_lo)
node offset_lo_lo = cat(offset_lo_lo_hi, offset_lo_lo_lo)
node offset_lo_hi_lo_hi = cat(_offset_T_9, _offset_T_8)
node offset_lo_hi_lo = cat(offset_lo_hi_lo_hi, _offset_T_7)
node offset_lo_hi_hi_lo = cat(_offset_T_11, _offset_T_10)
node offset_lo_hi_hi_hi = cat(_offset_T_13, _offset_T_12)
node offset_lo_hi_hi = cat(offset_lo_hi_hi_hi, offset_lo_hi_hi_lo)
node offset_lo_hi = cat(offset_lo_hi_hi, offset_lo_hi_lo)
node offset_lo = cat(offset_lo_hi, offset_lo_lo)
node offset_hi_lo_lo_hi = cat(_offset_T_16, _offset_T_15)
node offset_hi_lo_lo = cat(offset_hi_lo_lo_hi, _offset_T_14)
node offset_hi_lo_hi_lo = cat(_offset_T_18, _offset_T_17)
node offset_hi_lo_hi_hi = cat(_offset_T_20, _offset_T_19)
node offset_hi_lo_hi = cat(offset_hi_lo_hi_hi, offset_hi_lo_hi_lo)
node offset_hi_lo = cat(offset_hi_lo_hi, offset_hi_lo_lo)
node offset_hi_hi_lo_lo = cat(_offset_T_22, _offset_T_21)
node offset_hi_hi_lo_hi = cat(_offset_T_24, _offset_T_23)
node offset_hi_hi_lo = cat(offset_hi_hi_lo_hi, offset_hi_hi_lo_lo)
node offset_hi_hi_hi_lo = cat(_offset_T_26, _offset_T_25)
node offset_hi_hi_hi_hi = cat(_offset_T_28, _offset_T_27)
node offset_hi_hi_hi = cat(offset_hi_hi_hi_hi, offset_hi_hi_hi_lo)
node offset_hi_hi = cat(offset_hi_hi_hi, offset_hi_hi_lo)
node offset_hi = cat(offset_hi_hi, offset_hi_lo)
node offset = cat(offset_hi, offset_lo)
node set = shr(offset, 6)
node tag = shr(set, 10)
node tag_1 = bits(tag, 12, 0)
node set_1 = bits(set, 9, 0)
node offset_1 = bits(offset, 5, 0)
reg put_r : UInt<6>, clock
when first :
connect put_r, freeIdx
node put = mux(first, freeIdx, put_r)
wire _WIRE : UInt<1>[3]
connect _WIRE[0], UInt<1>(0h1)
connect _WIRE[1], UInt<1>(0h0)
connect _WIRE[2], UInt<1>(0h0)
connect io.req.bits.prio, _WIRE
connect io.req.bits.control, UInt<1>(0h0)
connect io.req.bits.opcode, io.a.bits.opcode
connect io.req.bits.param, io.a.bits.param
connect io.req.bits.size, io.a.bits.size
connect io.req.bits.source, io.a.bits.source
connect io.req.bits.offset, offset_1
connect io.req.bits.set, set_1
connect io.req.bits.tag, tag_1
connect io.req.bits.put, put
connect putbuffer.io.push.bits.index, put
connect putbuffer.io.push.bits.data.data, io.a.bits.data
connect putbuffer.io.push.bits.data.mask, io.a.bits.mask
connect putbuffer.io.push.bits.data.corrupt, io.a.bits.corrupt
connect putbuffer.io.pop.bits, io.pb_pop.bits.index
node _putbuffer_io_pop_valid_T = and(io.pb_pop.ready, io.pb_pop.valid)
connect putbuffer.io.pop.valid, _putbuffer_io_pop_valid_T
node _io_pb_pop_ready_T = dshr(putbuffer.io.valid, io.pb_pop.bits.index)
node _io_pb_pop_ready_T_1 = bits(_io_pb_pop_ready_T, 0, 0)
connect io.pb_pop.ready, _io_pb_pop_ready_T_1
connect io.pb_beat, putbuffer.io.data
node _T_9 = and(io.pb_pop.ready, io.pb_pop.valid)
node _T_10 = and(_T_9, io.pb_pop.bits.last)
when _T_10 :
node lists_clr_shiftAmount = bits(io.pb_pop.bits.index, 5, 0)
node _lists_clr_T = dshl(UInt<1>(0h1), lists_clr_shiftAmount)
node _lists_clr_T_1 = bits(_lists_clr_T, 39, 0)
connect lists_clr, _lists_clr_T_1 | module SinkA( // @[SinkA.scala:38:7]
input clock, // @[SinkA.scala:38:7]
input reset, // @[SinkA.scala:38:7]
input io_req_ready, // @[SinkA.scala:40:14]
output io_req_valid, // @[SinkA.scala:40:14]
output [2:0] io_req_bits_opcode, // @[SinkA.scala:40:14]
output [2:0] io_req_bits_param, // @[SinkA.scala:40:14]
output [2:0] io_req_bits_size, // @[SinkA.scala:40:14]
output [5:0] io_req_bits_source, // @[SinkA.scala:40:14]
output [12:0] io_req_bits_tag, // @[SinkA.scala:40:14]
output [5:0] io_req_bits_offset, // @[SinkA.scala:40:14]
output [5:0] io_req_bits_put, // @[SinkA.scala:40:14]
output [9:0] io_req_bits_set, // @[SinkA.scala:40:14]
output io_a_ready, // @[SinkA.scala:40:14]
input io_a_valid, // @[SinkA.scala:40:14]
input [2:0] io_a_bits_opcode, // @[SinkA.scala:40:14]
input [2:0] io_a_bits_param, // @[SinkA.scala:40:14]
input [2:0] io_a_bits_size, // @[SinkA.scala:40:14]
input [5:0] io_a_bits_source, // @[SinkA.scala:40:14]
input [31:0] io_a_bits_address, // @[SinkA.scala:40:14]
input [3:0] io_a_bits_mask, // @[SinkA.scala:40:14]
input [31:0] io_a_bits_data, // @[SinkA.scala:40:14]
input io_a_bits_corrupt, // @[SinkA.scala:40:14]
output io_pb_pop_ready, // @[SinkA.scala:40:14]
input io_pb_pop_valid, // @[SinkA.scala:40:14]
input [5:0] io_pb_pop_bits_index, // @[SinkA.scala:40:14]
input io_pb_pop_bits_last, // @[SinkA.scala:40:14]
output [31:0] io_pb_beat_data, // @[SinkA.scala:40:14]
output [3:0] io_pb_beat_mask, // @[SinkA.scala:40:14]
output io_pb_beat_corrupt // @[SinkA.scala:40:14]
);
wire _putbuffer_io_push_ready; // @[SinkA.scala:51:25]
wire [39:0] _putbuffer_io_valid; // @[SinkA.scala:51:25]
wire io_req_ready_0 = io_req_ready; // @[SinkA.scala:38:7]
wire io_a_valid_0 = io_a_valid; // @[SinkA.scala:38:7]
wire [2:0] io_a_bits_opcode_0 = io_a_bits_opcode; // @[SinkA.scala:38:7]
wire [2:0] io_a_bits_param_0 = io_a_bits_param; // @[SinkA.scala:38:7]
wire [2:0] io_a_bits_size_0 = io_a_bits_size; // @[SinkA.scala:38:7]
wire [5:0] io_a_bits_source_0 = io_a_bits_source; // @[SinkA.scala:38:7]
wire [31:0] io_a_bits_address_0 = io_a_bits_address; // @[SinkA.scala:38:7]
wire [3:0] io_a_bits_mask_0 = io_a_bits_mask; // @[SinkA.scala:38:7]
wire [31:0] io_a_bits_data_0 = io_a_bits_data; // @[SinkA.scala:38:7]
wire io_a_bits_corrupt_0 = io_a_bits_corrupt; // @[SinkA.scala:38:7]
wire io_pb_pop_valid_0 = io_pb_pop_valid; // @[SinkA.scala:38:7]
wire [5:0] io_pb_pop_bits_index_0 = io_pb_pop_bits_index; // @[SinkA.scala:38:7]
wire io_pb_pop_bits_last_0 = io_pb_pop_bits_last; // @[SinkA.scala:38:7]
wire io_req_bits_prio_1 = 1'h0; // @[SinkA.scala:38:7]
wire io_req_bits_prio_2 = 1'h0; // @[SinkA.scala:38:7]
wire io_req_bits_control = 1'h0; // @[SinkA.scala:38:7]
wire io_req_bits_prio_0 = 1'h1; // @[SinkA.scala:38:7]
wire _io_req_valid_T_4; // @[SinkA.scala:79:50]
wire [12:0] tag_1; // @[Parameters.scala:217:9]
wire [5:0] offset_1; // @[Parameters.scala:217:50]
wire [5:0] put; // @[SinkA.scala:84:16]
wire [9:0] set_1; // @[Parameters.scala:217:28]
wire _io_a_ready_T_4; // @[SinkA.scala:78:39]
wire [2:0] io_req_bits_opcode_0 = io_a_bits_opcode_0; // @[SinkA.scala:38:7]
wire [2:0] io_req_bits_param_0 = io_a_bits_param_0; // @[SinkA.scala:38:7]
wire [2:0] io_req_bits_size_0 = io_a_bits_size_0; // @[SinkA.scala:38:7]
wire [5:0] io_req_bits_source_0 = io_a_bits_source_0; // @[SinkA.scala:38:7]
wire _io_pb_pop_ready_T_1; // @[SinkA.scala:105:40]
wire [5:0] lists_clr_shiftAmount = io_pb_pop_bits_index_0; // @[OneHot.scala:64:49]
wire [12:0] io_req_bits_tag_0; // @[SinkA.scala:38:7]
wire [5:0] io_req_bits_offset_0; // @[SinkA.scala:38:7]
wire [5:0] io_req_bits_put_0; // @[SinkA.scala:38:7]
wire [9:0] io_req_bits_set_0; // @[SinkA.scala:38:7]
wire io_req_valid_0; // @[SinkA.scala:38:7]
wire io_a_ready_0; // @[SinkA.scala:38:7]
wire io_pb_pop_ready_0; // @[SinkA.scala:38:7]
wire [31:0] io_pb_beat_data_0; // @[SinkA.scala:38:7]
wire [3:0] io_pb_beat_mask_0; // @[SinkA.scala:38:7]
wire io_pb_beat_corrupt_0; // @[SinkA.scala:38:7]
reg [39:0] lists; // @[SinkA.scala:52:22]
wire [39:0] lists_set; // @[SinkA.scala:54:27]
wire [39:0] lists_clr; // @[SinkA.scala:55:27]
wire [39:0] _lists_T = lists | lists_set; // @[SinkA.scala:52:22, :54:27, :56:19]
wire [39:0] _lists_T_1 = ~lists_clr; // @[SinkA.scala:55:27, :56:34]
wire [39:0] _lists_T_2 = _lists_T & _lists_T_1; // @[SinkA.scala:56:{19,32,34}]
wire _free_T = &lists; // @[SinkA.scala:52:22, :58:21]
wire free = ~_free_T; // @[SinkA.scala:58:{14,21}]
wire [39:0] _freeOH_T = ~lists; // @[SinkA.scala:52:22, :59:25]
wire [40:0] _freeOH_T_1 = {_freeOH_T, 1'h0}; // @[package.scala:253:48]
wire [39:0] _freeOH_T_2 = _freeOH_T_1[39:0]; // @[package.scala:253:{48,53}]
wire [39:0] _freeOH_T_3 = _freeOH_T | _freeOH_T_2; // @[package.scala:253:{43,53}]
wire [41:0] _freeOH_T_4 = {_freeOH_T_3, 2'h0}; // @[package.scala:253:{43,48}]
wire [39:0] _freeOH_T_5 = _freeOH_T_4[39:0]; // @[package.scala:253:{48,53}]
wire [39:0] _freeOH_T_6 = _freeOH_T_3 | _freeOH_T_5; // @[package.scala:253:{43,53}]
wire [43:0] _freeOH_T_7 = {_freeOH_T_6, 4'h0}; // @[package.scala:253:{43,48}]
wire [39:0] _freeOH_T_8 = _freeOH_T_7[39:0]; // @[package.scala:253:{48,53}]
wire [39:0] _freeOH_T_9 = _freeOH_T_6 | _freeOH_T_8; // @[package.scala:253:{43,53}]
wire [47:0] _freeOH_T_10 = {_freeOH_T_9, 8'h0}; // @[package.scala:253:{43,48}]
wire [39:0] _freeOH_T_11 = _freeOH_T_10[39:0]; // @[package.scala:253:{48,53}]
wire [39:0] _freeOH_T_12 = _freeOH_T_9 | _freeOH_T_11; // @[package.scala:253:{43,53}]
wire [55:0] _freeOH_T_13 = {_freeOH_T_12, 16'h0}; // @[package.scala:253:{43,48}]
wire [39:0] _freeOH_T_14 = _freeOH_T_13[39:0]; // @[package.scala:253:{48,53}]
wire [39:0] _freeOH_T_15 = _freeOH_T_12 | _freeOH_T_14; // @[package.scala:253:{43,53}]
wire [71:0] _freeOH_T_16 = {_freeOH_T_15, 32'h0}; // @[package.scala:253:{43,48}]
wire [39:0] _freeOH_T_17 = _freeOH_T_16[39:0]; // @[package.scala:253:{48,53}]
wire [39:0] _freeOH_T_18 = _freeOH_T_15 | _freeOH_T_17; // @[package.scala:253:{43,53}]
wire [39:0] _freeOH_T_19 = _freeOH_T_18; // @[package.scala:253:43, :254:17]
wire [40:0] _freeOH_T_20 = {_freeOH_T_19, 1'h0}; // @[package.scala:254:17]
wire [40:0] _freeOH_T_21 = ~_freeOH_T_20; // @[SinkA.scala:59:{16,33}]
wire [39:0] _freeOH_T_22 = ~lists; // @[SinkA.scala:52:22, :59:{25,41}]
wire [40:0] freeOH = {1'h0, _freeOH_T_21[39:0] & _freeOH_T_22}; // @[SinkA.scala:59:{16,39,41}]
wire [8:0] freeIdx_hi = freeOH[40:32]; // @[OneHot.scala:30:18]
wire [31:0] freeIdx_lo = freeOH[31:0]; // @[OneHot.scala:31:18]
wire _freeIdx_T = |freeIdx_hi; // @[OneHot.scala:30:18, :32:14]
wire [31:0] _freeIdx_T_1 = {23'h0, freeIdx_hi} | freeIdx_lo; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [15:0] freeIdx_hi_1 = _freeIdx_T_1[31:16]; // @[OneHot.scala:30:18, :32:28]
wire [15:0] freeIdx_lo_1 = _freeIdx_T_1[15:0]; // @[OneHot.scala:31:18, :32:28]
wire _freeIdx_T_2 = |freeIdx_hi_1; // @[OneHot.scala:30:18, :32:14]
wire [15:0] _freeIdx_T_3 = freeIdx_hi_1 | freeIdx_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [7:0] freeIdx_hi_2 = _freeIdx_T_3[15:8]; // @[OneHot.scala:30:18, :32:28]
wire [7:0] freeIdx_lo_2 = _freeIdx_T_3[7:0]; // @[OneHot.scala:31:18, :32:28]
wire _freeIdx_T_4 = |freeIdx_hi_2; // @[OneHot.scala:30:18, :32:14]
wire [7:0] _freeIdx_T_5 = freeIdx_hi_2 | freeIdx_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [3:0] freeIdx_hi_3 = _freeIdx_T_5[7:4]; // @[OneHot.scala:30:18, :32:28]
wire [3:0] freeIdx_lo_3 = _freeIdx_T_5[3:0]; // @[OneHot.scala:31:18, :32:28]
wire _freeIdx_T_6 = |freeIdx_hi_3; // @[OneHot.scala:30:18, :32:14]
wire [3:0] _freeIdx_T_7 = freeIdx_hi_3 | freeIdx_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28]
wire [1:0] freeIdx_hi_4 = _freeIdx_T_7[3:2]; // @[OneHot.scala:30:18, :32:28]
wire [1:0] freeIdx_lo_4 = _freeIdx_T_7[1:0]; // @[OneHot.scala:31:18, :32:28]
wire _freeIdx_T_8 = |freeIdx_hi_4; // @[OneHot.scala:30:18, :32:14]
wire [1:0] _freeIdx_T_9 = freeIdx_hi_4 | freeIdx_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28]
wire _freeIdx_T_10 = _freeIdx_T_9[1]; // @[OneHot.scala:32:28]
wire [1:0] _freeIdx_T_11 = {_freeIdx_T_8, _freeIdx_T_10}; // @[OneHot.scala:32:{10,14}]
wire [2:0] _freeIdx_T_12 = {_freeIdx_T_6, _freeIdx_T_11}; // @[OneHot.scala:32:{10,14}]
wire [3:0] _freeIdx_T_13 = {_freeIdx_T_4, _freeIdx_T_12}; // @[OneHot.scala:32:{10,14}]
wire [4:0] _freeIdx_T_14 = {_freeIdx_T_2, _freeIdx_T_13}; // @[OneHot.scala:32:{10,14}]
wire [5:0] freeIdx = {_freeIdx_T, _freeIdx_T_14}; // @[OneHot.scala:32:{10,14}]
wire _first_T = io_a_ready_0 & io_a_valid_0; // @[Decoupled.scala:51:35]
wire [12:0] _first_beats1_decode_T = 13'h3F << io_a_bits_size_0; // @[package.scala:243:71]
wire [5:0] _first_beats1_decode_T_1 = _first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}]
wire [5:0] _first_beats1_decode_T_2 = ~_first_beats1_decode_T_1; // @[package.scala:243:{46,76}]
wire [3:0] first_beats1_decode = _first_beats1_decode_T_2[5:2]; // @[package.scala:243:46]
wire _first_beats1_opdata_T = io_a_bits_opcode_0[2]; // @[Edges.scala:92:37]
wire _hasData_opdata_T = io_a_bits_opcode_0[2]; // @[Edges.scala:92:37]
wire first_beats1_opdata = ~_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}]
wire [3:0] first_beats1 = first_beats1_opdata ? first_beats1_decode : 4'h0; // @[Edges.scala:92:28, :220:59, :221:14]
reg [3:0] first_counter; // @[Edges.scala:229:27]
wire [4:0] _first_counter1_T = {1'h0, first_counter} - 5'h1; // @[Edges.scala:229:27, :230:28]
wire [3:0] first_counter1 = _first_counter1_T[3:0]; // @[Edges.scala:230:28]
wire first = first_counter == 4'h0; // @[Edges.scala:229:27, :231:25]
wire _first_last_T = first_counter == 4'h1; // @[Edges.scala:229:27, :232:25]
wire _first_last_T_1 = first_beats1 == 4'h0; // @[Edges.scala:221:14, :232:43]
wire first_last = _first_last_T | _first_last_T_1; // @[Edges.scala:232:{25,33,43}]
wire first_done = first_last & _first_T; // @[Decoupled.scala:51:35]
wire [3:0] _first_count_T = ~first_counter1; // @[Edges.scala:230:28, :234:27]
wire [3:0] first_count = first_beats1 & _first_count_T; // @[Edges.scala:221:14, :234:{25,27}]
wire [3:0] _first_counter_T = first ? first_beats1 : first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21]
wire hasData = ~_hasData_opdata_T; // @[Edges.scala:92:{28,37}]
wire _req_block_T = ~io_req_ready_0; // @[SinkA.scala:38:7, :70:28]
wire req_block = first & _req_block_T; // @[Edges.scala:231:25]
wire _buf_block_T = ~_putbuffer_io_push_ready; // @[SinkA.scala:51:25, :71:30]
wire buf_block = hasData & _buf_block_T; // @[Edges.scala:92:28]
wire _set_block_T = hasData & first; // @[Edges.scala:92:28, :231:25]
wire _set_block_T_1 = ~free; // @[SinkA.scala:58:14, :72:39]
wire set_block = _set_block_T & _set_block_T_1; // @[SinkA.scala:72:{27,36,39}]
wire _io_a_ready_T = ~req_block; // @[SinkA.scala:70:25, :78:14]
wire _io_a_ready_T_1 = ~buf_block; // @[SinkA.scala:71:27, :78:28]
wire _io_a_ready_T_2 = _io_a_ready_T & _io_a_ready_T_1; // @[SinkA.scala:78:{14,25,28}]
wire _io_a_ready_T_3 = ~set_block; // @[SinkA.scala:72:36, :78:42]
assign _io_a_ready_T_4 = _io_a_ready_T_2 & _io_a_ready_T_3; // @[SinkA.scala:78:{25,39,42}]
assign io_a_ready_0 = _io_a_ready_T_4; // @[SinkA.scala:38:7, :78:39]
wire _io_req_valid_T = io_a_valid_0 & first; // @[Edges.scala:231:25]
wire _io_req_valid_T_1 = ~buf_block; // @[SinkA.scala:71:27, :78:28, :79:39]
wire _io_req_valid_T_2 = _io_req_valid_T & _io_req_valid_T_1; // @[SinkA.scala:79:{27,36,39}]
wire _io_req_valid_T_3 = ~set_block; // @[SinkA.scala:72:36, :78:42, :79:53]
assign _io_req_valid_T_4 = _io_req_valid_T_2 & _io_req_valid_T_3; // @[SinkA.scala:79:{36,50,53}]
assign io_req_valid_0 = _io_req_valid_T_4; // @[SinkA.scala:38:7, :79:50]
wire _putbuffer_io_push_valid_T = io_a_valid_0 & hasData; // @[Edges.scala:92:28]
wire _putbuffer_io_push_valid_T_1 = ~req_block; // @[SinkA.scala:70:25, :78:14, :80:52]
wire _putbuffer_io_push_valid_T_2 = _putbuffer_io_push_valid_T & _putbuffer_io_push_valid_T_1; // @[SinkA.scala:80:{38,49,52}]
wire _putbuffer_io_push_valid_T_3 = ~set_block; // @[SinkA.scala:72:36, :78:42, :80:66]
wire _putbuffer_io_push_valid_T_4 = _putbuffer_io_push_valid_T_2 & _putbuffer_io_push_valid_T_3; // @[SinkA.scala:80:{49,63,66}]
assign lists_set = _io_req_valid_T & hasData & ~req_block & ~buf_block ? freeOH[39:0] : 40'h0; // @[Edges.scala:92:28]
wire _offset_T = io_a_bits_address_0[0]; // @[SinkA.scala:38:7]
wire _offset_T_1 = io_a_bits_address_0[1]; // @[SinkA.scala:38:7]
wire _offset_T_2 = io_a_bits_address_0[2]; // @[SinkA.scala:38:7]
wire _offset_T_3 = io_a_bits_address_0[3]; // @[SinkA.scala:38:7]
wire _offset_T_4 = io_a_bits_address_0[4]; // @[SinkA.scala:38:7]
wire _offset_T_5 = io_a_bits_address_0[5]; // @[SinkA.scala:38:7]
wire _offset_T_6 = io_a_bits_address_0[6]; // @[SinkA.scala:38:7]
wire _offset_T_7 = io_a_bits_address_0[7]; // @[SinkA.scala:38:7]
wire _offset_T_8 = io_a_bits_address_0[8]; // @[SinkA.scala:38:7]
wire _offset_T_9 = io_a_bits_address_0[9]; // @[SinkA.scala:38:7]
wire _offset_T_10 = io_a_bits_address_0[10]; // @[SinkA.scala:38:7]
wire _offset_T_11 = io_a_bits_address_0[11]; // @[SinkA.scala:38:7]
wire _offset_T_12 = io_a_bits_address_0[12]; // @[SinkA.scala:38:7]
wire _offset_T_13 = io_a_bits_address_0[13]; // @[SinkA.scala:38:7]
wire _offset_T_14 = io_a_bits_address_0[14]; // @[SinkA.scala:38:7]
wire _offset_T_15 = io_a_bits_address_0[15]; // @[SinkA.scala:38:7]
wire _offset_T_16 = io_a_bits_address_0[16]; // @[SinkA.scala:38:7]
wire _offset_T_17 = io_a_bits_address_0[17]; // @[SinkA.scala:38:7]
wire _offset_T_18 = io_a_bits_address_0[18]; // @[SinkA.scala:38:7]
wire _offset_T_19 = io_a_bits_address_0[19]; // @[SinkA.scala:38:7]
wire _offset_T_20 = io_a_bits_address_0[20]; // @[SinkA.scala:38:7]
wire _offset_T_21 = io_a_bits_address_0[21]; // @[SinkA.scala:38:7]
wire _offset_T_22 = io_a_bits_address_0[22]; // @[SinkA.scala:38:7]
wire _offset_T_23 = io_a_bits_address_0[23]; // @[SinkA.scala:38:7]
wire _offset_T_24 = io_a_bits_address_0[24]; // @[SinkA.scala:38:7]
wire _offset_T_25 = io_a_bits_address_0[25]; // @[SinkA.scala:38:7]
wire _offset_T_26 = io_a_bits_address_0[26]; // @[SinkA.scala:38:7]
wire _offset_T_27 = io_a_bits_address_0[27]; // @[SinkA.scala:38:7]
wire _offset_T_28 = io_a_bits_address_0[31]; // @[SinkA.scala:38:7]
wire [1:0] offset_lo_lo_lo_hi = {_offset_T_2, _offset_T_1}; // @[Parameters.scala:214:{21,47}]
wire [2:0] offset_lo_lo_lo = {offset_lo_lo_lo_hi, _offset_T}; // @[Parameters.scala:214:{21,47}]
wire [1:0] offset_lo_lo_hi_lo = {_offset_T_4, _offset_T_3}; // @[Parameters.scala:214:{21,47}]
wire [1:0] offset_lo_lo_hi_hi = {_offset_T_6, _offset_T_5}; // @[Parameters.scala:214:{21,47}]
wire [3:0] offset_lo_lo_hi = {offset_lo_lo_hi_hi, offset_lo_lo_hi_lo}; // @[Parameters.scala:214:21]
wire [6:0] offset_lo_lo = {offset_lo_lo_hi, offset_lo_lo_lo}; // @[Parameters.scala:214:21]
wire [1:0] offset_lo_hi_lo_hi = {_offset_T_9, _offset_T_8}; // @[Parameters.scala:214:{21,47}]
wire [2:0] offset_lo_hi_lo = {offset_lo_hi_lo_hi, _offset_T_7}; // @[Parameters.scala:214:{21,47}]
wire [1:0] offset_lo_hi_hi_lo = {_offset_T_11, _offset_T_10}; // @[Parameters.scala:214:{21,47}]
wire [1:0] offset_lo_hi_hi_hi = {_offset_T_13, _offset_T_12}; // @[Parameters.scala:214:{21,47}]
wire [3:0] offset_lo_hi_hi = {offset_lo_hi_hi_hi, offset_lo_hi_hi_lo}; // @[Parameters.scala:214:21]
wire [6:0] offset_lo_hi = {offset_lo_hi_hi, offset_lo_hi_lo}; // @[Parameters.scala:214:21]
wire [13:0] offset_lo = {offset_lo_hi, offset_lo_lo}; // @[Parameters.scala:214:21]
wire [1:0] offset_hi_lo_lo_hi = {_offset_T_16, _offset_T_15}; // @[Parameters.scala:214:{21,47}]
wire [2:0] offset_hi_lo_lo = {offset_hi_lo_lo_hi, _offset_T_14}; // @[Parameters.scala:214:{21,47}]
wire [1:0] offset_hi_lo_hi_lo = {_offset_T_18, _offset_T_17}; // @[Parameters.scala:214:{21,47}]
wire [1:0] offset_hi_lo_hi_hi = {_offset_T_20, _offset_T_19}; // @[Parameters.scala:214:{21,47}]
wire [3:0] offset_hi_lo_hi = {offset_hi_lo_hi_hi, offset_hi_lo_hi_lo}; // @[Parameters.scala:214:21]
wire [6:0] offset_hi_lo = {offset_hi_lo_hi, offset_hi_lo_lo}; // @[Parameters.scala:214:21]
wire [1:0] offset_hi_hi_lo_lo = {_offset_T_22, _offset_T_21}; // @[Parameters.scala:214:{21,47}]
wire [1:0] offset_hi_hi_lo_hi = {_offset_T_24, _offset_T_23}; // @[Parameters.scala:214:{21,47}]
wire [3:0] offset_hi_hi_lo = {offset_hi_hi_lo_hi, offset_hi_hi_lo_lo}; // @[Parameters.scala:214:21]
wire [1:0] offset_hi_hi_hi_lo = {_offset_T_26, _offset_T_25}; // @[Parameters.scala:214:{21,47}]
wire [1:0] offset_hi_hi_hi_hi = {_offset_T_28, _offset_T_27}; // @[Parameters.scala:214:{21,47}]
wire [3:0] offset_hi_hi_hi = {offset_hi_hi_hi_hi, offset_hi_hi_hi_lo}; // @[Parameters.scala:214:21]
wire [7:0] offset_hi_hi = {offset_hi_hi_hi, offset_hi_hi_lo}; // @[Parameters.scala:214:21]
wire [14:0] offset_hi = {offset_hi_hi, offset_hi_lo}; // @[Parameters.scala:214:21]
wire [28:0] offset = {offset_hi, offset_lo}; // @[Parameters.scala:214:21]
wire [22:0] set = offset[28:6]; // @[Parameters.scala:214:21, :215:22]
wire [12:0] tag = set[22:10]; // @[Parameters.scala:215:22, :216:19]
assign tag_1 = tag; // @[Parameters.scala:216:19, :217:9]
assign io_req_bits_tag_0 = tag_1; // @[SinkA.scala:38:7]
assign set_1 = set[9:0]; // @[Parameters.scala:215:22, :217:28]
assign io_req_bits_set_0 = set_1; // @[SinkA.scala:38:7]
assign offset_1 = offset[5:0]; // @[Parameters.scala:214:21, :217:50]
assign io_req_bits_offset_0 = offset_1; // @[SinkA.scala:38:7]
reg [5:0] put_r; // @[SinkA.scala:84:42]
assign put = first ? freeIdx : put_r; // @[OneHot.scala:32:10]
assign io_req_bits_put_0 = put; // @[SinkA.scala:38:7, :84:16]
wire _putbuffer_io_pop_valid_T = io_pb_pop_ready_0 & io_pb_pop_valid_0; // @[Decoupled.scala:51:35]
wire [39:0] _io_pb_pop_ready_T = _putbuffer_io_valid >> io_pb_pop_bits_index_0; // @[SinkA.scala:38:7, :51:25, :105:40]
assign _io_pb_pop_ready_T_1 = _io_pb_pop_ready_T[0]; // @[SinkA.scala:105:40]
assign io_pb_pop_ready_0 = _io_pb_pop_ready_T_1; // @[SinkA.scala:38:7, :105:40]
wire [63:0] _lists_clr_T = 64'h1 << lists_clr_shiftAmount; // @[OneHot.scala:64:49, :65:12]
wire [39:0] _lists_clr_T_1 = _lists_clr_T[39:0]; // @[OneHot.scala:65:{12,27}]
assign lists_clr = _putbuffer_io_pop_valid_T & io_pb_pop_bits_last_0 ? _lists_clr_T_1 : 40'h0; // @[OneHot.scala:65:27]
always @(posedge clock) begin // @[SinkA.scala:38:7]
if (reset) begin // @[SinkA.scala:38:7]
lists <= 40'h0; // @[SinkA.scala:52:22]
first_counter <= 4'h0; // @[Edges.scala:229:27]
end
else begin // @[SinkA.scala:38:7]
lists <= _lists_T_2; // @[SinkA.scala:52:22, :56:32]
if (_first_T) // @[Decoupled.scala:51:35]
first_counter <= _first_counter_T; // @[Edges.scala:229:27, :236:21]
end
if (first) // @[Edges.scala:231:25]
put_r <= freeIdx; // @[OneHot.scala:32:10]
always @(posedge)
ListBuffer_PutBufferAEntry_q40_e40 putbuffer ( // @[SinkA.scala:51:25]
.clock (clock),
.reset (reset),
.io_push_ready (_putbuffer_io_push_ready),
.io_push_valid (_putbuffer_io_push_valid_T_4), // @[SinkA.scala:80:63]
.io_push_bits_index (put), // @[SinkA.scala:84:16]
.io_push_bits_data_data (io_a_bits_data_0), // @[SinkA.scala:38:7]
.io_push_bits_data_mask (io_a_bits_mask_0), // @[SinkA.scala:38:7]
.io_push_bits_data_corrupt (io_a_bits_corrupt_0), // @[SinkA.scala:38:7]
.io_valid (_putbuffer_io_valid),
.io_pop_valid (_putbuffer_io_pop_valid_T), // @[Decoupled.scala:51:35]
.io_pop_bits (io_pb_pop_bits_index_0), // @[SinkA.scala:38:7]
.io_data_data (io_pb_beat_data_0),
.io_data_mask (io_pb_beat_mask_0),
.io_data_corrupt (io_pb_beat_corrupt_0)
); // @[SinkA.scala:51:25]
assign io_req_valid = io_req_valid_0; // @[SinkA.scala:38:7]
assign io_req_bits_opcode = io_req_bits_opcode_0; // @[SinkA.scala:38:7]
assign io_req_bits_param = io_req_bits_param_0; // @[SinkA.scala:38:7]
assign io_req_bits_size = io_req_bits_size_0; // @[SinkA.scala:38:7]
assign io_req_bits_source = io_req_bits_source_0; // @[SinkA.scala:38:7]
assign io_req_bits_tag = io_req_bits_tag_0; // @[SinkA.scala:38:7]
assign io_req_bits_offset = io_req_bits_offset_0; // @[SinkA.scala:38:7]
assign io_req_bits_put = io_req_bits_put_0; // @[SinkA.scala:38:7]
assign io_req_bits_set = io_req_bits_set_0; // @[SinkA.scala:38:7]
assign io_a_ready = io_a_ready_0; // @[SinkA.scala:38:7]
assign io_pb_pop_ready = io_pb_pop_ready_0; // @[SinkA.scala:38:7]
assign io_pb_beat_data = io_pb_beat_data_0; // @[SinkA.scala:38:7]
assign io_pb_beat_mask = io_pb_beat_mask_0; // @[SinkA.scala:38:7]
assign io_pb_beat_corrupt = io_pb_beat_corrupt_0; // @[SinkA.scala:38:7]
endmodule |
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_7 :
output io : { flip in : UInt<1>, out : UInt<1>}
input clock : Clock
input reset : AsyncReset
inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_9
connect io_out_source_valid.clock, clock
connect io_out_source_valid.reset, reset
connect io_out_source_valid.io.d, io.in
wire _io_out_WIRE : UInt<1>
connect _io_out_WIRE, io_out_source_valid.io.q
connect io.out, _io_out_WIRE | module AsyncValidSync_7( // @[AsyncQueue.scala:58:7]
input io_in, // @[AsyncQueue.scala:59:14]
output io_out, // @[AsyncQueue.scala:59:14]
input clock, // @[AsyncQueue.scala:63:17]
input reset // @[AsyncQueue.scala:64:17]
);
wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7]
wire _io_out_WIRE; // @[ShiftReg.scala:48:24]
wire io_out_0; // @[AsyncQueue.scala:58:7]
assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24]
AsyncResetSynchronizerShiftReg_w1_d3_i0_9 io_out_source_valid ( // @[ShiftReg.scala:45:23]
.clock (clock),
.reset (reset),
.io_d (io_in_0), // @[AsyncQueue.scala:58:7]
.io_q (_io_out_WIRE)
); // @[ShiftReg.scala:45:23]
assign io_out = io_out_0; // @[AsyncQueue.scala:58:7]
endmodule |
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